1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifndef GET_CC_REGISTER_LISTS
10
11static bool CC_XCore(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, CCState &State);
14static bool RetCC_XCore(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, CCState &State);
17
18
19static bool CC_XCore(unsigned ValNo, MVT ValVT,
20 MVT LocVT, CCValAssign::LocInfo LocInfo,
21 ISD::ArgFlagsTy ArgFlags, CCState &State) {
22
23 if (LocVT == MVT::i8 ||
24 LocVT == MVT::i16) {
25 LocVT = MVT::i32;
26 if (ArgFlags.isSExt())
27 LocInfo = CCValAssign::SExt;
28 else if (ArgFlags.isZExt())
29 LocInfo = CCValAssign::ZExt;
30 else
31 LocInfo = CCValAssign::AExt;
32 }
33
34 if (ArgFlags.isNest()) {
35 if (MCRegister Reg = State.AllocateReg(Reg: XCore::R11)) {
36 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
37 return false;
38 }
39 }
40
41 if (LocVT == MVT::i32) {
42 static const MCPhysReg RegList1[] = {
43 XCore::R0, XCore::R1, XCore::R2, XCore::R3
44 };
45 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
46 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
47 return false;
48 }
49 }
50
51 if (LocVT == MVT::i32) {
52 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
53 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
54 return false;
55 }
56
57 return true; // CC didn't match.
58}
59
60
61static bool RetCC_XCore(unsigned ValNo, MVT ValVT,
62 MVT LocVT, CCValAssign::LocInfo LocInfo,
63 ISD::ArgFlagsTy ArgFlags, CCState &State) {
64
65 if (LocVT == MVT::i32) {
66 static const MCPhysReg RegList1[] = {
67 XCore::R0, XCore::R1, XCore::R2, XCore::R3
68 };
69 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
70 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
71 return false;
72 }
73 }
74
75 if (LocVT == MVT::i32) {
76 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
77 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
78 return false;
79 }
80
81 return true; // CC didn't match.
82}
83
84#else
85
86const MCRegister CC_XCore_ArgRegs[] = { XCore::R0, XCore::R1, XCore::R11, XCore::R2, XCore::R3 };
87const MCRegister RetCC_XCore_ArgRegs[] = { XCore::R0, XCore::R1, XCore::R2, XCore::R3 };
88
89#endif // CC_REGISTER_LIST
90