1//===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the XCoreTargetLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "XCoreISelLowering.h"
14#include "XCore.h"
15#include "XCoreMachineFunctionInfo.h"
16#include "XCoreSubtarget.h"
17#include "XCoreTargetMachine.h"
18#include "XCoreTargetObjectFile.h"
19#include "llvm/CodeGen/CallingConvLower.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineJumpTableInfo.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/ValueTypes.h"
26#include "llvm/IR/CallingConv.h"
27#include "llvm/IR/Constants.h"
28#include "llvm/IR/DerivedTypes.h"
29#include "llvm/IR/Function.h"
30#include "llvm/IR/GlobalVariable.h"
31#include "llvm/IR/Intrinsics.h"
32#include "llvm/IR/IntrinsicsXCore.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/KnownBits.h"
36#include "llvm/Support/raw_ostream.h"
37#include <algorithm>
38
39using namespace llvm;
40
41#define DEBUG_TYPE "xcore-lower"
42
43XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
44 const XCoreSubtarget &Subtarget)
45 : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
46
47 // Set up the register classes.
48 addRegisterClass(VT: MVT::i32, RC: &XCore::GRRegsRegClass);
49
50 // Compute derived properties from the register classes
51 computeRegisterProperties(TRI: Subtarget.getRegisterInfo());
52
53 setStackPointerRegisterToSaveRestore(XCore::SP);
54
55 setSchedulingPreference(Sched::Source);
56
57 // Use i32 for setcc operations results (slt, sgt, ...).
58 setBooleanContents(ZeroOrOneBooleanContent);
59 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
60
61 // XCore does not have the NodeTypes below.
62 setOperationAction(Op: ISD::BR_CC, VT: MVT::i32, Action: Expand);
63 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i32, Action: Expand);
64
65 // 64bit
66 setOperationAction(Op: ISD::ADD, VT: MVT::i64, Action: Custom);
67 setOperationAction(Op: ISD::SUB, VT: MVT::i64, Action: Custom);
68 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i32, Action: Custom);
69 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i32, Action: Custom);
70 setOperationAction(Op: ISD::MULHS, VT: MVT::i32, Action: Expand);
71 setOperationAction(Op: ISD::MULHU, VT: MVT::i32, Action: Expand);
72 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i32, Action: Expand);
73 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i32, Action: Expand);
74 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i32, Action: Expand);
75
76 // Bit Manipulation
77 setOperationAction(Op: ISD::CTPOP, VT: MVT::i32, Action: Expand);
78 setOperationAction(Op: ISD::ROTL , VT: MVT::i32, Action: Expand);
79 setOperationAction(Op: ISD::ROTR , VT: MVT::i32, Action: Expand);
80 setOperationAction(Op: ISD::BITREVERSE , VT: MVT::i32, Action: Legal);
81
82 setOperationAction(Op: ISD::TRAP, VT: MVT::Other, Action: Legal);
83
84 // Jump tables.
85 setOperationAction(Op: ISD::BR_JT, VT: MVT::Other, Action: Custom);
86
87 setOperationAction(Op: ISD::GlobalAddress, VT: MVT::i32, Action: Custom);
88 setOperationAction(Op: ISD::BlockAddress, VT: MVT::i32 , Action: Custom);
89
90 // Conversion of i64 -> double produces constantpool nodes
91 setOperationAction(Op: ISD::ConstantPool, VT: MVT::i32, Action: Custom);
92
93 // Loads
94 for (MVT VT : MVT::integer_valuetypes()) {
95 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
96 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
97 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
98
99 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::i8, Action: Expand);
100 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: VT, MemVT: MVT::i16, Action: Expand);
101 }
102
103 // Custom expand misaligned loads / stores.
104 setOperationAction(Op: ISD::LOAD, VT: MVT::i32, Action: Custom);
105 setOperationAction(Op: ISD::STORE, VT: MVT::i32, Action: Custom);
106
107 // Varargs
108 setOperationAction(Op: ISD::VAEND, VT: MVT::Other, Action: Expand);
109 setOperationAction(Op: ISD::VACOPY, VT: MVT::Other, Action: Expand);
110 setOperationAction(Op: ISD::VAARG, VT: MVT::Other, Action: Custom);
111 setOperationAction(Op: ISD::VASTART, VT: MVT::Other, Action: Custom);
112
113 // Dynamic stack
114 setOperationAction(Op: ISD::STACKSAVE, VT: MVT::Other, Action: Expand);
115 setOperationAction(Op: ISD::STACKRESTORE, VT: MVT::Other, Action: Expand);
116 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i32, Action: Expand);
117
118 // Exception handling
119 setOperationAction(Op: ISD::EH_RETURN, VT: MVT::Other, Action: Custom);
120 setOperationAction(Op: ISD::FRAME_TO_ARGS_OFFSET, VT: MVT::i32, Action: Custom);
121
122 setOperationAction(Op: ISD::ATOMIC_FENCE, VT: MVT::Other, Action: Custom);
123
124 // TRAMPOLINE is custom lowered.
125 setOperationAction(Op: ISD::INIT_TRAMPOLINE, VT: MVT::Other, Action: Custom);
126 setOperationAction(Op: ISD::ADJUST_TRAMPOLINE, VT: MVT::Other, Action: Custom);
127
128 // We want to custom lower some of our intrinsics.
129 setOperationAction(Op: ISD::INTRINSIC_WO_CHAIN, VT: MVT::Other, Action: Custom);
130
131 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 4;
132 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize
133 = MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 2;
134
135 // We have target-specific dag combine patterns for the following nodes:
136 setTargetDAGCombine(
137 {ISD::STORE, ISD::ADD, ISD::INTRINSIC_VOID, ISD::INTRINSIC_W_CHAIN});
138
139 setMinFunctionAlignment(Align(2));
140 setPrefFunctionAlignment(Align(4));
141
142 // This target doesn't implement native atomics.
143 setMaxAtomicSizeInBitsSupported(0);
144}
145
146bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
147 if (Val.getOpcode() != ISD::LOAD)
148 return false;
149
150 EVT VT1 = Val.getValueType();
151 if (!VT1.isSimple() || !VT1.isInteger() ||
152 !VT2.isSimple() || !VT2.isInteger())
153 return false;
154
155 switch (VT1.getSimpleVT().SimpleTy) {
156 default: break;
157 case MVT::i8:
158 return true;
159 }
160
161 return false;
162}
163
164SDValue XCoreTargetLowering::
165LowerOperation(SDValue Op, SelectionDAG &DAG) const {
166 switch (Op.getOpcode())
167 {
168 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
169 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
170 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
171 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
172 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
173 case ISD::LOAD: return LowerLOAD(Op, DAG);
174 case ISD::STORE: return LowerSTORE(Op, DAG);
175 case ISD::VAARG: return LowerVAARG(Op, DAG);
176 case ISD::VASTART: return LowerVASTART(Op, DAG);
177 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG);
178 case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG);
179 // FIXME: Remove these when LegalizeDAGTypes lands.
180 case ISD::ADD:
181 case ISD::SUB: return ExpandADDSUB(Op: Op.getNode(), DAG);
182 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
183 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
184 case ISD::FRAME_TO_ARGS_OFFSET: return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
185 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
186 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
187 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
188 case ISD::ATOMIC_FENCE:
189 return LowerATOMIC_FENCE(Op, DAG);
190 default:
191 llvm_unreachable("unimplemented operand");
192 }
193}
194
195/// ReplaceNodeResults - Replace the results of node with an illegal result
196/// type with new values built out of custom code.
197void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
198 SmallVectorImpl<SDValue>&Results,
199 SelectionDAG &DAG) const {
200 switch (N->getOpcode()) {
201 default:
202 llvm_unreachable("Don't know how to custom expand this!");
203 case ISD::ADD:
204 case ISD::SUB:
205 Results.push_back(Elt: ExpandADDSUB(Op: N, DAG));
206 return;
207 }
208}
209
210//===----------------------------------------------------------------------===//
211// Misc Lower Operation implementation
212//===----------------------------------------------------------------------===//
213
214SDValue XCoreTargetLowering::getGlobalAddressWrapper(SDValue GA,
215 const GlobalValue *GV,
216 SelectionDAG &DAG) const {
217 // FIXME there is no actual debug info here
218 SDLoc dl(GA);
219
220 if (GV->getValueType()->isFunctionTy())
221 return DAG.getNode(Opcode: XCoreISD::PCRelativeWrapper, DL: dl, VT: MVT::i32, Operand: GA);
222
223 const auto *GVar = dyn_cast<GlobalVariable>(Val: GV);
224 if ((GV->hasSection() && GV->getSection().starts_with(Prefix: ".cp.")) ||
225 (GVar && GVar->isConstant() && GV->hasLocalLinkage()))
226 return DAG.getNode(Opcode: XCoreISD::CPRelativeWrapper, DL: dl, VT: MVT::i32, Operand: GA);
227
228 return DAG.getNode(Opcode: XCoreISD::DPRelativeWrapper, DL: dl, VT: MVT::i32, Operand: GA);
229}
230
231static bool IsSmallObject(const GlobalValue *GV, const XCoreTargetLowering &XTL) {
232 if (XTL.getTargetMachine().getCodeModel() == CodeModel::Small)
233 return true;
234
235 Type *ObjType = GV->getValueType();
236 if (!ObjType->isSized())
237 return false;
238
239 auto &DL = GV->getDataLayout();
240 unsigned ObjSize = DL.getTypeAllocSize(Ty: ObjType);
241 return ObjSize < CodeModelLargeSize && ObjSize != 0;
242}
243
244SDValue XCoreTargetLowering::
245LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
246{
247 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Val&: Op);
248 const GlobalValue *GV = GN->getGlobal();
249 SDLoc DL(GN);
250 int64_t Offset = GN->getOffset();
251 if (IsSmallObject(GV, XTL: *this)) {
252 // We can only fold positive offsets that are a multiple of the word size.
253 int64_t FoldedOffset = std::max(a: Offset & ~3, b: (int64_t)0);
254 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, VT: MVT::i32, offset: FoldedOffset);
255 GA = getGlobalAddressWrapper(GA, GV, DAG);
256 // Handle the rest of the offset.
257 if (Offset != FoldedOffset) {
258 SDValue Remaining =
259 DAG.getSignedConstant(Val: Offset - FoldedOffset, DL, VT: MVT::i32);
260 GA = DAG.getNode(Opcode: ISD::ADD, DL, VT: MVT::i32, N1: GA, N2: Remaining);
261 }
262 return GA;
263 } else {
264 // Ideally we would not fold in offset with an index <= 11.
265 Type *Ty = Type::getInt32Ty(C&: *DAG.getContext());
266 Constant *Idx = ConstantInt::get(Ty, V: Offset);
267 Constant *GAI = ConstantExpr::getGetElementPtr(
268 Ty: Type::getInt8Ty(C&: *DAG.getContext()), C: const_cast<GlobalValue *>(GV), Idx);
269 SDValue CP = DAG.getConstantPool(C: GAI, VT: MVT::i32);
270 return DAG.getLoad(VT: getPointerTy(DL: DAG.getDataLayout()), dl: DL,
271 Chain: DAG.getEntryNode(), Ptr: CP, PtrInfo: MachinePointerInfo());
272 }
273}
274
275SDValue XCoreTargetLowering::
276LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
277{
278 SDLoc DL(Op);
279 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
280 const BlockAddress *BA = cast<BlockAddressSDNode>(Val&: Op)->getBlockAddress();
281 SDValue Result = DAG.getTargetBlockAddress(BA, VT: PtrVT);
282
283 return DAG.getNode(Opcode: XCoreISD::PCRelativeWrapper, DL, VT: PtrVT, Operand: Result);
284}
285
286SDValue XCoreTargetLowering::
287LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
288{
289 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Val&: Op);
290 // FIXME there isn't really debug info here
291 SDLoc dl(CP);
292 EVT PtrVT = Op.getValueType();
293 SDValue Res;
294 if (CP->isMachineConstantPoolEntry()) {
295 Res = DAG.getTargetConstantPool(C: CP->getMachineCPVal(), VT: PtrVT,
296 Align: CP->getAlign(), Offset: CP->getOffset());
297 } else {
298 Res = DAG.getTargetConstantPool(C: CP->getConstVal(), VT: PtrVT, Align: CP->getAlign(),
299 Offset: CP->getOffset());
300 }
301 return DAG.getNode(Opcode: XCoreISD::CPRelativeWrapper, DL: dl, VT: MVT::i32, Operand: Res);
302}
303
304unsigned XCoreTargetLowering::getJumpTableEncoding() const {
305 return MachineJumpTableInfo::EK_Inline;
306}
307
308SDValue XCoreTargetLowering::
309LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
310{
311 SDValue Chain = Op.getOperand(i: 0);
312 SDValue Table = Op.getOperand(i: 1);
313 SDValue Index = Op.getOperand(i: 2);
314 SDLoc dl(Op);
315 JumpTableSDNode *JT = cast<JumpTableSDNode>(Val&: Table);
316 unsigned JTI = JT->getIndex();
317 MachineFunction &MF = DAG.getMachineFunction();
318 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
319 SDValue TargetJT = DAG.getTargetJumpTable(JTI: JT->getIndex(), VT: MVT::i32);
320
321 unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size();
322 if (NumEntries <= 32) {
323 return DAG.getNode(Opcode: XCoreISD::BR_JT, DL: dl, VT: MVT::Other, N1: Chain, N2: TargetJT, N3: Index);
324 }
325 assert((NumEntries >> 31) == 0);
326 SDValue ScaledIndex = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: MVT::i32, N1: Index,
327 N2: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i32));
328 return DAG.getNode(Opcode: XCoreISD::BR_JT32, DL: dl, VT: MVT::Other, N1: Chain, N2: TargetJT,
329 N3: ScaledIndex);
330}
331
332SDValue XCoreTargetLowering::lowerLoadWordFromAlignedBasePlusOffset(
333 const SDLoc &DL, SDValue Chain, SDValue Base, int64_t Offset,
334 SelectionDAG &DAG) const {
335 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
336 if ((Offset & 0x3) == 0) {
337 return DAG.getLoad(VT: PtrVT, dl: DL, Chain, Ptr: Base, PtrInfo: MachinePointerInfo());
338 }
339 // Lower to pair of consecutive word aligned loads plus some bit shifting.
340 int32_t HighOffset = alignTo(Value: Offset, Align: 4);
341 int32_t LowOffset = HighOffset - 4;
342 SDValue LowAddr, HighAddr;
343 if (GlobalAddressSDNode *GASD =
344 dyn_cast<GlobalAddressSDNode>(Val: Base.getNode())) {
345 LowAddr = DAG.getGlobalAddress(GV: GASD->getGlobal(), DL, VT: Base.getValueType(),
346 offset: LowOffset);
347 HighAddr = DAG.getGlobalAddress(GV: GASD->getGlobal(), DL, VT: Base.getValueType(),
348 offset: HighOffset);
349 } else {
350 LowAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT: MVT::i32, N1: Base,
351 N2: DAG.getConstant(Val: LowOffset, DL, VT: MVT::i32));
352 HighAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT: MVT::i32, N1: Base,
353 N2: DAG.getConstant(Val: HighOffset, DL, VT: MVT::i32));
354 }
355 SDValue LowShift = DAG.getConstant(Val: (Offset - LowOffset) * 8, DL, VT: MVT::i32);
356 SDValue HighShift = DAG.getConstant(Val: (HighOffset - Offset) * 8, DL, VT: MVT::i32);
357
358 SDValue Low = DAG.getLoad(VT: PtrVT, dl: DL, Chain, Ptr: LowAddr, PtrInfo: MachinePointerInfo());
359 SDValue High = DAG.getLoad(VT: PtrVT, dl: DL, Chain, Ptr: HighAddr, PtrInfo: MachinePointerInfo());
360 SDValue LowShifted = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i32, N1: Low, N2: LowShift);
361 SDValue HighShifted = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32, N1: High, N2: HighShift);
362 SDValue Result = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i32, N1: LowShifted, N2: HighShifted);
363 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, N1: Low.getValue(R: 1),
364 N2: High.getValue(R: 1));
365 SDValue Ops[] = { Result, Chain };
366 return DAG.getMergeValues(Ops, dl: DL);
367}
368
369static bool isWordAligned(SDValue Value, SelectionDAG &DAG)
370{
371 KnownBits Known = DAG.computeKnownBits(Op: Value);
372 return Known.countMinTrailingZeros() >= 2;
373}
374
375SDValue XCoreTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
376 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
377 LLVMContext &Context = *DAG.getContext();
378 LoadSDNode *LD = cast<LoadSDNode>(Val&: Op);
379 assert(LD->getExtensionType() == ISD::NON_EXTLOAD &&
380 "Unexpected extension type");
381 assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");
382
383 if (allowsMemoryAccessForAlignment(Context, DL: DAG.getDataLayout(),
384 VT: LD->getMemoryVT(), MMO: *LD->getMemOperand()))
385 return SDValue();
386
387 SDValue Chain = LD->getChain();
388 SDValue BasePtr = LD->getBasePtr();
389 SDLoc DL(Op);
390
391 if (!LD->isVolatile()) {
392 const GlobalValue *GV;
393 int64_t Offset = 0;
394 if (DAG.isBaseWithConstantOffset(Op: BasePtr) &&
395 isWordAligned(Value: BasePtr->getOperand(Num: 0), DAG)) {
396 SDValue NewBasePtr = BasePtr->getOperand(Num: 0);
397 Offset = cast<ConstantSDNode>(Val: BasePtr->getOperand(Num: 1))->getSExtValue();
398 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, Base: NewBasePtr,
399 Offset, DAG);
400 }
401 if (TLI.isGAPlusOffset(N: BasePtr.getNode(), GA&: GV, Offset) &&
402 GV->getPointerAlignment(DL: DAG.getDataLayout()) >= 4) {
403 SDValue NewBasePtr = DAG.getGlobalAddress(GV, DL,
404 VT: BasePtr->getValueType(ResNo: 0));
405 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, Base: NewBasePtr,
406 Offset, DAG);
407 }
408 }
409
410 if (LD->getAlign() == Align(2)) {
411 SDValue Low = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl: DL, VT: MVT::i32, Chain, Ptr: BasePtr,
412 PtrInfo: LD->getPointerInfo(), MemVT: MVT::i16, Alignment: Align(2),
413 MMOFlags: LD->getMemOperand()->getFlags());
414 SDValue HighAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT: MVT::i32, N1: BasePtr,
415 N2: DAG.getConstant(Val: 2, DL, VT: MVT::i32));
416 SDValue High =
417 DAG.getExtLoad(ExtType: ISD::EXTLOAD, dl: DL, VT: MVT::i32, Chain, Ptr: HighAddr,
418 PtrInfo: LD->getPointerInfo().getWithOffset(O: 2), MemVT: MVT::i16,
419 Alignment: Align(2), MMOFlags: LD->getMemOperand()->getFlags());
420 SDValue HighShifted = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32, N1: High,
421 N2: DAG.getConstant(Val: 16, DL, VT: MVT::i32));
422 SDValue Result = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i32, N1: Low, N2: HighShifted);
423 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, N1: Low.getValue(R: 1),
424 N2: High.getValue(R: 1));
425 SDValue Ops[] = { Result, Chain };
426 return DAG.getMergeValues(Ops, dl: DL);
427 }
428
429 // Lower to a call to __misaligned_load(BasePtr).
430 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(C&: Context);
431 TargetLowering::ArgListTy Args;
432 TargetLowering::ArgListEntry Entry;
433
434 Entry.Ty = IntPtrTy;
435 Entry.Node = BasePtr;
436 Args.push_back(x: Entry);
437
438 TargetLowering::CallLoweringInfo CLI(DAG);
439 CLI.setDebugLoc(DL).setChain(Chain).setLibCallee(
440 CC: CallingConv::C, ResultType: IntPtrTy,
441 Target: DAG.getExternalSymbol(Sym: "__misaligned_load",
442 VT: getPointerTy(DL: DAG.getDataLayout())),
443 ArgsList: std::move(Args));
444
445 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
446 SDValue Ops[] = { CallResult.first, CallResult.second };
447 return DAG.getMergeValues(Ops, dl: DL);
448}
449
450SDValue XCoreTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
451 LLVMContext &Context = *DAG.getContext();
452 StoreSDNode *ST = cast<StoreSDNode>(Val&: Op);
453 assert(!ST->isTruncatingStore() && "Unexpected store type");
454 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");
455
456 if (allowsMemoryAccessForAlignment(Context, DL: DAG.getDataLayout(),
457 VT: ST->getMemoryVT(), MMO: *ST->getMemOperand()))
458 return SDValue();
459
460 SDValue Chain = ST->getChain();
461 SDValue BasePtr = ST->getBasePtr();
462 SDValue Value = ST->getValue();
463 SDLoc dl(Op);
464
465 if (ST->getAlign() == Align(2)) {
466 SDValue Low = Value;
467 SDValue High = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: MVT::i32, N1: Value,
468 N2: DAG.getConstant(Val: 16, DL: dl, VT: MVT::i32));
469 SDValue StoreLow =
470 DAG.getTruncStore(Chain, dl, Val: Low, Ptr: BasePtr, PtrInfo: ST->getPointerInfo(),
471 SVT: MVT::i16, Alignment: Align(2), MMOFlags: ST->getMemOperand()->getFlags());
472 SDValue HighAddr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: BasePtr,
473 N2: DAG.getConstant(Val: 2, DL: dl, VT: MVT::i32));
474 SDValue StoreHigh = DAG.getTruncStore(
475 Chain, dl, Val: High, Ptr: HighAddr, PtrInfo: ST->getPointerInfo().getWithOffset(O: 2),
476 SVT: MVT::i16, Alignment: Align(2), MMOFlags: ST->getMemOperand()->getFlags());
477 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: StoreLow, N2: StoreHigh);
478 }
479
480 // Lower to a call to __misaligned_store(BasePtr, Value).
481 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(C&: Context);
482 TargetLowering::ArgListTy Args;
483 TargetLowering::ArgListEntry Entry;
484
485 Entry.Ty = IntPtrTy;
486 Entry.Node = BasePtr;
487 Args.push_back(x: Entry);
488
489 Entry.Node = Value;
490 Args.push_back(x: Entry);
491
492 TargetLowering::CallLoweringInfo CLI(DAG);
493 CLI.setDebugLoc(dl).setChain(Chain).setCallee(
494 CC: CallingConv::C, ResultType: Type::getVoidTy(C&: Context),
495 Target: DAG.getExternalSymbol(Sym: "__misaligned_store",
496 VT: getPointerTy(DL: DAG.getDataLayout())),
497 ArgsList: std::move(Args));
498
499 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
500 return CallResult.second;
501}
502
503SDValue XCoreTargetLowering::
504LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
505{
506 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
507 "Unexpected operand to lower!");
508 SDLoc dl(Op);
509 SDValue LHS = Op.getOperand(i: 0);
510 SDValue RHS = Op.getOperand(i: 1);
511 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32);
512 SDValue Hi = DAG.getNode(Opcode: XCoreISD::MACCS, DL: dl,
513 VTList: DAG.getVTList(VT1: MVT::i32, VT2: MVT::i32), N1: Zero, N2: Zero,
514 N3: LHS, N4: RHS);
515 SDValue Lo(Hi.getNode(), 1);
516 SDValue Ops[] = { Lo, Hi };
517 return DAG.getMergeValues(Ops, dl);
518}
519
520SDValue XCoreTargetLowering::
521LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
522{
523 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
524 "Unexpected operand to lower!");
525 SDLoc dl(Op);
526 SDValue LHS = Op.getOperand(i: 0);
527 SDValue RHS = Op.getOperand(i: 1);
528 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32);
529 SDValue Hi = DAG.getNode(Opcode: XCoreISD::LMUL, DL: dl,
530 VTList: DAG.getVTList(VT1: MVT::i32, VT2: MVT::i32), N1: LHS, N2: RHS,
531 N3: Zero, N4: Zero);
532 SDValue Lo(Hi.getNode(), 1);
533 SDValue Ops[] = { Lo, Hi };
534 return DAG.getMergeValues(Ops, dl);
535}
536
537/// isADDADDMUL - Return whether Op is in a form that is equivalent to
538/// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then
539/// each intermediate result in the calculation must also have a single use.
540/// If the Op is in the correct form the constituent parts are written to Mul0,
541/// Mul1, Addend0 and Addend1.
542static bool
543isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0,
544 SDValue &Addend1, bool requireIntermediatesHaveOneUse)
545{
546 if (Op.getOpcode() != ISD::ADD)
547 return false;
548 SDValue N0 = Op.getOperand(i: 0);
549 SDValue N1 = Op.getOperand(i: 1);
550 SDValue AddOp;
551 SDValue OtherOp;
552 if (N0.getOpcode() == ISD::ADD) {
553 AddOp = N0;
554 OtherOp = N1;
555 } else if (N1.getOpcode() == ISD::ADD) {
556 AddOp = N1;
557 OtherOp = N0;
558 } else {
559 return false;
560 }
561 if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse())
562 return false;
563 if (OtherOp.getOpcode() == ISD::MUL) {
564 // add(add(a,b),mul(x,y))
565 if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse())
566 return false;
567 Mul0 = OtherOp.getOperand(i: 0);
568 Mul1 = OtherOp.getOperand(i: 1);
569 Addend0 = AddOp.getOperand(i: 0);
570 Addend1 = AddOp.getOperand(i: 1);
571 return true;
572 }
573 if (AddOp.getOperand(i: 0).getOpcode() == ISD::MUL) {
574 // add(add(mul(x,y),a),b)
575 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(i: 0).hasOneUse())
576 return false;
577 Mul0 = AddOp.getOperand(i: 0).getOperand(i: 0);
578 Mul1 = AddOp.getOperand(i: 0).getOperand(i: 1);
579 Addend0 = AddOp.getOperand(i: 1);
580 Addend1 = OtherOp;
581 return true;
582 }
583 if (AddOp.getOperand(i: 1).getOpcode() == ISD::MUL) {
584 // add(add(a,mul(x,y)),b)
585 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(i: 1).hasOneUse())
586 return false;
587 Mul0 = AddOp.getOperand(i: 1).getOperand(i: 0);
588 Mul1 = AddOp.getOperand(i: 1).getOperand(i: 1);
589 Addend0 = AddOp.getOperand(i: 0);
590 Addend1 = OtherOp;
591 return true;
592 }
593 return false;
594}
595
596SDValue XCoreTargetLowering::
597TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
598{
599 SDValue Mul;
600 SDValue Other;
601 if (N->getOperand(Num: 0).getOpcode() == ISD::MUL) {
602 Mul = N->getOperand(Num: 0);
603 Other = N->getOperand(Num: 1);
604 } else if (N->getOperand(Num: 1).getOpcode() == ISD::MUL) {
605 Mul = N->getOperand(Num: 1);
606 Other = N->getOperand(Num: 0);
607 } else {
608 return SDValue();
609 }
610 SDLoc dl(N);
611 SDValue LL, RL, AddendL, AddendH;
612 LL = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
613 N1: Mul.getOperand(i: 0), N2: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
614 RL = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
615 N1: Mul.getOperand(i: 1), N2: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
616 AddendL = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
617 N1: Other, N2: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
618 AddendH = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
619 N1: Other, N2: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i32));
620 APInt HighMask = APInt::getHighBitsSet(numBits: 64, hiBitsSet: 32);
621 unsigned LHSSB = DAG.ComputeNumSignBits(Op: Mul.getOperand(i: 0));
622 unsigned RHSSB = DAG.ComputeNumSignBits(Op: Mul.getOperand(i: 1));
623 if (DAG.MaskedValueIsZero(Op: Mul.getOperand(i: 0), Mask: HighMask) &&
624 DAG.MaskedValueIsZero(Op: Mul.getOperand(i: 1), Mask: HighMask)) {
625 // The inputs are both zero-extended.
626 SDValue Hi = DAG.getNode(Opcode: XCoreISD::MACCU, DL: dl,
627 VTList: DAG.getVTList(VT1: MVT::i32, VT2: MVT::i32), N1: AddendH,
628 N2: AddendL, N3: LL, N4: RL);
629 SDValue Lo(Hi.getNode(), 1);
630 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: Lo, N2: Hi);
631 }
632 if (LHSSB > 32 && RHSSB > 32) {
633 // The inputs are both sign-extended.
634 SDValue Hi = DAG.getNode(Opcode: XCoreISD::MACCS, DL: dl,
635 VTList: DAG.getVTList(VT1: MVT::i32, VT2: MVT::i32), N1: AddendH,
636 N2: AddendL, N3: LL, N4: RL);
637 SDValue Lo(Hi.getNode(), 1);
638 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: Lo, N2: Hi);
639 }
640 SDValue LH, RH;
641 LH = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
642 N1: Mul.getOperand(i: 0), N2: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i32));
643 RH = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
644 N1: Mul.getOperand(i: 1), N2: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i32));
645 SDValue Hi = DAG.getNode(Opcode: XCoreISD::MACCU, DL: dl,
646 VTList: DAG.getVTList(VT1: MVT::i32, VT2: MVT::i32), N1: AddendH,
647 N2: AddendL, N3: LL, N4: RL);
648 SDValue Lo(Hi.getNode(), 1);
649 RH = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT: MVT::i32, N1: LL, N2: RH);
650 LH = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT: MVT::i32, N1: LH, N2: RL);
651 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: Hi, N2: RH);
652 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: Hi, N2: LH);
653 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: Lo, N2: Hi);
654}
655
656SDValue XCoreTargetLowering::
657ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
658{
659 assert(N->getValueType(0) == MVT::i64 &&
660 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
661 "Unknown operand to lower!");
662
663 if (N->getOpcode() == ISD::ADD)
664 if (SDValue Result = TryExpandADDWithMul(N, DAG))
665 return Result;
666
667 SDLoc dl(N);
668
669 // Extract components
670 SDValue LHSL = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
671 N1: N->getOperand(Num: 0),
672 N2: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
673 SDValue LHSH = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
674 N1: N->getOperand(Num: 0),
675 N2: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i32));
676 SDValue RHSL = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
677 N1: N->getOperand(Num: 1),
678 N2: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
679 SDValue RHSH = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
680 N1: N->getOperand(Num: 1),
681 N2: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i32));
682
683 // Expand
684 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
685 XCoreISD::LSUB;
686 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32);
687 SDValue Lo = DAG.getNode(Opcode, DL: dl, VTList: DAG.getVTList(VT1: MVT::i32, VT2: MVT::i32),
688 N1: LHSL, N2: RHSL, N3: Zero);
689 SDValue Carry(Lo.getNode(), 1);
690
691 SDValue Hi = DAG.getNode(Opcode, DL: dl, VTList: DAG.getVTList(VT1: MVT::i32, VT2: MVT::i32),
692 N1: LHSH, N2: RHSH, N3: Carry);
693 SDValue Ignored(Hi.getNode(), 1);
694 // Merge the pieces
695 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: Lo, N2: Hi);
696}
697
698SDValue XCoreTargetLowering::
699LowerVAARG(SDValue Op, SelectionDAG &DAG) const
700{
701 // Whist llvm does not support aggregate varargs we can ignore
702 // the possibility of the ValueType being an implicit byVal vararg.
703 SDNode *Node = Op.getNode();
704 EVT VT = Node->getValueType(ResNo: 0); // not an aggregate
705 SDValue InChain = Node->getOperand(Num: 0);
706 SDValue VAListPtr = Node->getOperand(Num: 1);
707 EVT PtrVT = VAListPtr.getValueType();
708 const Value *SV = cast<SrcValueSDNode>(Val: Node->getOperand(Num: 2))->getValue();
709 SDLoc dl(Node);
710 SDValue VAList =
711 DAG.getLoad(VT: PtrVT, dl, Chain: InChain, Ptr: VAListPtr, PtrInfo: MachinePointerInfo(SV));
712 // Increment the pointer, VAList, to the next vararg
713 SDValue nextPtr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: PtrVT, N1: VAList,
714 N2: DAG.getIntPtrConstant(Val: VT.getSizeInBits() / 8,
715 DL: dl));
716 // Store the incremented VAList to the legalized pointer
717 InChain = DAG.getStore(Chain: VAList.getValue(R: 1), dl, Val: nextPtr, Ptr: VAListPtr,
718 PtrInfo: MachinePointerInfo(SV));
719 // Load the actual argument out of the pointer VAList
720 return DAG.getLoad(VT, dl, Chain: InChain, Ptr: VAList, PtrInfo: MachinePointerInfo());
721}
722
723SDValue XCoreTargetLowering::
724LowerVASTART(SDValue Op, SelectionDAG &DAG) const
725{
726 SDLoc dl(Op);
727 // vastart stores the address of the VarArgsFrameIndex slot into the
728 // memory location argument
729 MachineFunction &MF = DAG.getMachineFunction();
730 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
731 SDValue Addr = DAG.getFrameIndex(FI: XFI->getVarArgsFrameIndex(), VT: MVT::i32);
732 return DAG.getStore(Chain: Op.getOperand(i: 0), dl, Val: Addr, Ptr: Op.getOperand(i: 1),
733 PtrInfo: MachinePointerInfo());
734}
735
736SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op,
737 SelectionDAG &DAG) const {
738 // This nodes represent llvm.frameaddress on the DAG.
739 // It takes one operand, the index of the frame address to return.
740 // An index of zero corresponds to the current function's frame address.
741 // An index of one to the parent's frame address, and so on.
742 // Depths > 0 not supported yet!
743 if (Op.getConstantOperandVal(i: 0) > 0)
744 return SDValue();
745
746 MachineFunction &MF = DAG.getMachineFunction();
747 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
748 return DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl: SDLoc(Op),
749 Reg: RegInfo->getFrameRegister(MF), VT: MVT::i32);
750}
751
752SDValue XCoreTargetLowering::
753LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
754 // This nodes represent llvm.returnaddress on the DAG.
755 // It takes one operand, the index of the return address to return.
756 // An index of zero corresponds to the current function's return address.
757 // An index of one to the parent's return address, and so on.
758 // Depths > 0 not supported yet!
759 if (Op.getConstantOperandVal(i: 0) > 0)
760 return SDValue();
761
762 MachineFunction &MF = DAG.getMachineFunction();
763 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
764 int FI = XFI->createLRSpillSlot(MF);
765 SDValue FIN = DAG.getFrameIndex(FI, VT: MVT::i32);
766 return DAG.getLoad(VT: getPointerTy(DL: DAG.getDataLayout()), dl: SDLoc(Op),
767 Chain: DAG.getEntryNode(), Ptr: FIN,
768 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI));
769}
770
771SDValue XCoreTargetLowering::
772LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const {
773 // This node represents offset from frame pointer to first on-stack argument.
774 // This is needed for correct stack adjustment during unwind.
775 // However, we don't know the offset until after the frame has be finalised.
776 // This is done during the XCoreFTAOElim pass.
777 return DAG.getNode(Opcode: XCoreISD::FRAME_TO_ARGS_OFFSET, DL: SDLoc(Op), VT: MVT::i32);
778}
779
780SDValue XCoreTargetLowering::
781LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
782 // OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER)
783 // This node represents 'eh_return' gcc dwarf builtin, which is used to
784 // return from exception. The general meaning is: adjust stack by OFFSET and
785 // pass execution to HANDLER.
786 MachineFunction &MF = DAG.getMachineFunction();
787 SDValue Chain = Op.getOperand(i: 0);
788 SDValue Offset = Op.getOperand(i: 1);
789 SDValue Handler = Op.getOperand(i: 2);
790 SDLoc dl(Op);
791
792 // Absolute SP = (FP + FrameToArgs) + Offset
793 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
794 SDValue Stack = DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl,
795 Reg: RegInfo->getFrameRegister(MF), VT: MVT::i32);
796 SDValue FrameToArgs = DAG.getNode(Opcode: XCoreISD::FRAME_TO_ARGS_OFFSET, DL: dl,
797 VT: MVT::i32);
798 Stack = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: Stack, N2: FrameToArgs);
799 Stack = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: Stack, N2: Offset);
800
801 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
802 // which leaves 2 caller saved registers, R2 & R3 for us to use.
803 unsigned StackReg = XCore::R2;
804 unsigned HandlerReg = XCore::R3;
805
806 SDValue OutChains[] = {
807 DAG.getCopyToReg(Chain, dl, Reg: StackReg, N: Stack),
808 DAG.getCopyToReg(Chain, dl, Reg: HandlerReg, N: Handler)
809 };
810
811 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
812
813 return DAG.getNode(Opcode: XCoreISD::EH_RETURN, DL: dl, VT: MVT::Other, N1: Chain,
814 N2: DAG.getRegister(Reg: StackReg, VT: MVT::i32),
815 N3: DAG.getRegister(Reg: HandlerReg, VT: MVT::i32));
816
817}
818
819SDValue XCoreTargetLowering::
820LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
821 return Op.getOperand(i: 0);
822}
823
824SDValue XCoreTargetLowering::
825LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
826 SDValue Chain = Op.getOperand(i: 0);
827 SDValue Trmp = Op.getOperand(i: 1); // trampoline
828 SDValue FPtr = Op.getOperand(i: 2); // nested function
829 SDValue Nest = Op.getOperand(i: 3); // 'nest' parameter value
830
831 const Value *TrmpAddr = cast<SrcValueSDNode>(Val: Op.getOperand(i: 4))->getValue();
832
833 // .align 4
834 // LDAPF_u10 r11, nest
835 // LDW_2rus r11, r11[0]
836 // STWSP_ru6 r11, sp[0]
837 // LDAPF_u10 r11, fptr
838 // LDW_2rus r11, r11[0]
839 // BAU_1r r11
840 // nest:
841 // .word nest
842 // fptr:
843 // .word fptr
844 SDValue OutChains[5];
845
846 SDValue Addr = Trmp;
847
848 SDLoc dl(Op);
849 OutChains[0] =
850 DAG.getStore(Chain, dl, Val: DAG.getConstant(Val: 0x0a3cd805, DL: dl, VT: MVT::i32), Ptr: Addr,
851 PtrInfo: MachinePointerInfo(TrmpAddr));
852
853 Addr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: Trmp,
854 N2: DAG.getConstant(Val: 4, DL: dl, VT: MVT::i32));
855 OutChains[1] =
856 DAG.getStore(Chain, dl, Val: DAG.getConstant(Val: 0xd80456c0, DL: dl, VT: MVT::i32), Ptr: Addr,
857 PtrInfo: MachinePointerInfo(TrmpAddr, 4));
858
859 Addr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: Trmp,
860 N2: DAG.getConstant(Val: 8, DL: dl, VT: MVT::i32));
861 OutChains[2] =
862 DAG.getStore(Chain, dl, Val: DAG.getConstant(Val: 0x27fb0a3c, DL: dl, VT: MVT::i32), Ptr: Addr,
863 PtrInfo: MachinePointerInfo(TrmpAddr, 8));
864
865 Addr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: Trmp,
866 N2: DAG.getConstant(Val: 12, DL: dl, VT: MVT::i32));
867 OutChains[3] =
868 DAG.getStore(Chain, dl, Val: Nest, Ptr: Addr, PtrInfo: MachinePointerInfo(TrmpAddr, 12));
869
870 Addr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: Trmp,
871 N2: DAG.getConstant(Val: 16, DL: dl, VT: MVT::i32));
872 OutChains[4] =
873 DAG.getStore(Chain, dl, Val: FPtr, Ptr: Addr, PtrInfo: MachinePointerInfo(TrmpAddr, 16));
874
875 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
876}
877
878SDValue XCoreTargetLowering::
879LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
880 SDLoc DL(Op);
881 unsigned IntNo = Op.getConstantOperandVal(i: 0);
882 switch (IntNo) {
883 case Intrinsic::xcore_crc8:
884 EVT VT = Op.getValueType();
885 SDValue Data =
886 DAG.getNode(Opcode: XCoreISD::CRC8, DL, VTList: DAG.getVTList(VT1: VT, VT2: VT),
887 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2) , N3: Op.getOperand(i: 3));
888 SDValue Crc(Data.getNode(), 1);
889 SDValue Results[] = { Crc, Data };
890 return DAG.getMergeValues(Ops: Results, dl: DL);
891 }
892 return SDValue();
893}
894
895SDValue XCoreTargetLowering::
896LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const {
897 SDLoc DL(Op);
898 return DAG.getNode(Opcode: ISD::MEMBARRIER, DL, VT: MVT::Other, Operand: Op.getOperand(i: 0));
899}
900
901//===----------------------------------------------------------------------===//
902// Calling Convention Implementation
903//===----------------------------------------------------------------------===//
904
905#include "XCoreGenCallingConv.inc"
906
907//===----------------------------------------------------------------------===//
908// Call Calling Convention Implementation
909//===----------------------------------------------------------------------===//
910
911/// XCore call implementation
912SDValue
913XCoreTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
914 SmallVectorImpl<SDValue> &InVals) const {
915 SelectionDAG &DAG = CLI.DAG;
916 SDLoc &dl = CLI.DL;
917 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
918 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
919 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
920 SDValue Chain = CLI.Chain;
921 SDValue Callee = CLI.Callee;
922 bool &isTailCall = CLI.IsTailCall;
923 CallingConv::ID CallConv = CLI.CallConv;
924 bool isVarArg = CLI.IsVarArg;
925
926 // XCore target does not yet support tail call optimization.
927 isTailCall = false;
928
929 // For now, only CallingConv::C implemented
930 switch (CallConv)
931 {
932 default:
933 report_fatal_error(reason: "Unsupported calling convention");
934 case CallingConv::Fast:
935 case CallingConv::C:
936 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
937 Outs, OutVals, Ins, dl, DAG, InVals);
938 }
939}
940
941/// LowerCallResult - Lower the result values of a call into the
942/// appropriate copies out of appropriate physical registers / memory locations.
943static SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
944 const SmallVectorImpl<CCValAssign> &RVLocs,
945 const SDLoc &dl, SelectionDAG &DAG,
946 SmallVectorImpl<SDValue> &InVals) {
947 SmallVector<std::pair<int, unsigned>, 4> ResultMemLocs;
948 // Copy results out of physical registers.
949 for (const CCValAssign &VA : RVLocs) {
950 if (VA.isRegLoc()) {
951 Chain = DAG.getCopyFromReg(Chain, dl, Reg: VA.getLocReg(), VT: VA.getValVT(),
952 Glue: InGlue).getValue(R: 1);
953 InGlue = Chain.getValue(R: 2);
954 InVals.push_back(Elt: Chain.getValue(R: 0));
955 } else {
956 assert(VA.isMemLoc());
957 ResultMemLocs.push_back(Elt: std::make_pair(x: VA.getLocMemOffset(),
958 y: InVals.size()));
959 // Reserve space for this result.
960 InVals.push_back(Elt: SDValue());
961 }
962 }
963
964 // Copy results out of memory.
965 SmallVector<SDValue, 4> MemOpChains;
966 for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) {
967 int offset = ResultMemLocs[i].first;
968 unsigned index = ResultMemLocs[i].second;
969 SDVTList VTs = DAG.getVTList(VT1: MVT::i32, VT2: MVT::Other);
970 SDValue Ops[] = { Chain, DAG.getConstant(Val: offset / 4, DL: dl, VT: MVT::i32) };
971 SDValue load = DAG.getNode(Opcode: XCoreISD::LDWSP, DL: dl, VTList: VTs, Ops);
972 InVals[index] = load;
973 MemOpChains.push_back(Elt: load.getValue(R: 1));
974 }
975
976 // Transform all loads nodes into one single node because
977 // all load nodes are independent of each other.
978 if (!MemOpChains.empty())
979 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains);
980
981 return Chain;
982}
983
984/// LowerCCCCallTo - functions arguments are copied from virtual
985/// regs to (physical regs)/(stack frame), CALLSEQ_START and
986/// CALLSEQ_END are emitted.
987/// TODO: isTailCall, sret.
988SDValue XCoreTargetLowering::LowerCCCCallTo(
989 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
990 bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
991 const SmallVectorImpl<SDValue> &OutVals,
992 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
993 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
994
995 // Analyze operands of the call, assigning locations to each operand.
996 SmallVector<CCValAssign, 16> ArgLocs;
997 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
998 *DAG.getContext());
999
1000 // The ABI dictates there should be one stack slot available to the callee
1001 // on function entry (for saving lr).
1002 CCInfo.AllocateStack(Size: 4, Alignment: Align(4));
1003
1004 CCInfo.AnalyzeCallOperands(Outs, Fn: CC_XCore);
1005
1006 SmallVector<CCValAssign, 16> RVLocs;
1007 // Analyze return values to determine the number of bytes of stack required.
1008 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1009 *DAG.getContext());
1010 RetCCInfo.AllocateStack(Size: CCInfo.getStackSize(), Alignment: Align(4));
1011 RetCCInfo.AnalyzeCallResult(Ins, Fn: RetCC_XCore);
1012
1013 // Get a count of how many bytes are to be pushed on the stack.
1014 unsigned NumBytes = RetCCInfo.getStackSize();
1015
1016 Chain = DAG.getCALLSEQ_START(Chain, InSize: NumBytes, OutSize: 0, DL: dl);
1017
1018 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
1019 SmallVector<SDValue, 12> MemOpChains;
1020
1021 // Walk the register/memloc assignments, inserting copies/loads.
1022 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1023 CCValAssign &VA = ArgLocs[i];
1024 SDValue Arg = OutVals[i];
1025
1026 // Promote the value if needed.
1027 switch (VA.getLocInfo()) {
1028 default: llvm_unreachable("Unknown loc info!");
1029 case CCValAssign::Full: break;
1030 case CCValAssign::SExt:
1031 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
1032 break;
1033 case CCValAssign::ZExt:
1034 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
1035 break;
1036 case CCValAssign::AExt:
1037 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
1038 break;
1039 }
1040
1041 // Arguments that can be passed on register must be kept at
1042 // RegsToPass vector
1043 if (VA.isRegLoc()) {
1044 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1045 } else {
1046 assert(VA.isMemLoc());
1047
1048 int Offset = VA.getLocMemOffset();
1049
1050 MemOpChains.push_back(Elt: DAG.getNode(Opcode: XCoreISD::STWSP, DL: dl, VT: MVT::Other,
1051 N1: Chain, N2: Arg,
1052 N3: DAG.getConstant(Val: Offset/4, DL: dl,
1053 VT: MVT::i32)));
1054 }
1055 }
1056
1057 // Transform all store nodes into one single node because
1058 // all store nodes are independent of each other.
1059 if (!MemOpChains.empty())
1060 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains);
1061
1062 // Build a sequence of copy-to-reg nodes chained together with token
1063 // chain and flag operands which copy the outgoing args into registers.
1064 // The InGlue in necessary since all emitted instructions must be
1065 // stuck together.
1066 SDValue InGlue;
1067 for (const auto &[Reg, N] : RegsToPass) {
1068 Chain = DAG.getCopyToReg(Chain, dl, Reg, N, Glue: InGlue);
1069 InGlue = Chain.getValue(R: 1);
1070 }
1071
1072 // If the callee is a GlobalAddress node (quite common, every direct call is)
1073 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1074 // Likewise ExternalSymbol -> TargetExternalSymbol.
1075 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
1076 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL: dl, VT: MVT::i32);
1077 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee))
1078 Callee = DAG.getTargetExternalSymbol(Sym: E->getSymbol(), VT: MVT::i32);
1079
1080 // XCoreBranchLink = #chain, #target_address, #opt_in_flags...
1081 // = Chain, Callee, Reg#1, Reg#2, ...
1082 //
1083 // Returns a chain & a flag for retval copy to use.
1084 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1085 SmallVector<SDValue, 8> Ops;
1086 Ops.push_back(Elt: Chain);
1087 Ops.push_back(Elt: Callee);
1088
1089 // Add argument registers to the end of the list so that they are
1090 // known live into the call.
1091 for (const auto &[Reg, N] : RegsToPass)
1092 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
1093
1094 if (InGlue.getNode())
1095 Ops.push_back(Elt: InGlue);
1096
1097 Chain = DAG.getNode(Opcode: XCoreISD::BL, DL: dl, VTList: NodeTys, Ops);
1098 InGlue = Chain.getValue(R: 1);
1099
1100 // Create the CALLSEQ_END node.
1101 Chain = DAG.getCALLSEQ_END(Chain, Size1: NumBytes, Size2: 0, Glue: InGlue, DL: dl);
1102 InGlue = Chain.getValue(R: 1);
1103
1104 // Handle result values, copying them out of physregs into vregs that we
1105 // return.
1106 return LowerCallResult(Chain, InGlue, RVLocs, dl, DAG, InVals);
1107}
1108
1109//===----------------------------------------------------------------------===//
1110// Formal Arguments Calling Convention Implementation
1111//===----------------------------------------------------------------------===//
1112
1113namespace {
1114 struct ArgDataPair { SDValue SDV; ISD::ArgFlagsTy Flags; };
1115}
1116
1117/// XCore formal arguments implementation
1118SDValue XCoreTargetLowering::LowerFormalArguments(
1119 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1120 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1121 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1122 switch (CallConv)
1123 {
1124 default:
1125 report_fatal_error(reason: "Unsupported calling convention");
1126 case CallingConv::C:
1127 case CallingConv::Fast:
1128 return LowerCCCArguments(Chain, CallConv, isVarArg,
1129 Ins, dl, DAG, InVals);
1130 }
1131}
1132
1133/// LowerCCCArguments - transform physical registers into
1134/// virtual registers and generate load operations for
1135/// arguments places on the stack.
1136/// TODO: sret
1137SDValue XCoreTargetLowering::LowerCCCArguments(
1138 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1139 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1140 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1141 MachineFunction &MF = DAG.getMachineFunction();
1142 MachineFrameInfo &MFI = MF.getFrameInfo();
1143 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1144 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1145
1146 // Assign locations to all of the incoming arguments.
1147 SmallVector<CCValAssign, 16> ArgLocs;
1148 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1149 *DAG.getContext());
1150
1151 CCInfo.AnalyzeFormalArguments(Ins, Fn: CC_XCore);
1152
1153 unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize();
1154
1155 unsigned LRSaveSize = StackSlotSize;
1156
1157 if (!isVarArg)
1158 XFI->setReturnStackOffset(CCInfo.getStackSize() + LRSaveSize);
1159
1160 // All getCopyFromReg ops must precede any getMemcpys to prevent the
1161 // scheduler clobbering a register before it has been copied.
1162 // The stages are:
1163 // 1. CopyFromReg (and load) arg & vararg registers.
1164 // 2. Chain CopyFromReg nodes into a TokenFactor.
1165 // 3. Memcpy 'byVal' args & push final InVals.
1166 // 4. Chain mem ops nodes into a TokenFactor.
1167 SmallVector<SDValue, 4> CFRegNode;
1168 SmallVector<ArgDataPair, 4> ArgData;
1169 SmallVector<SDValue, 4> MemOps;
1170
1171 // 1a. CopyFromReg (and load) arg registers.
1172 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1173
1174 CCValAssign &VA = ArgLocs[i];
1175 SDValue ArgIn;
1176
1177 if (VA.isRegLoc()) {
1178 // Arguments passed in registers
1179 EVT RegVT = VA.getLocVT();
1180 switch (RegVT.getSimpleVT().SimpleTy) {
1181 default:
1182 {
1183#ifndef NDEBUG
1184 errs() << "LowerFormalArguments Unhandled argument type: "
1185 << RegVT << "\n";
1186#endif
1187 llvm_unreachable(nullptr);
1188 }
1189 case MVT::i32:
1190 Register VReg = RegInfo.createVirtualRegister(RegClass: &XCore::GRRegsRegClass);
1191 RegInfo.addLiveIn(Reg: VA.getLocReg(), vreg: VReg);
1192 ArgIn = DAG.getCopyFromReg(Chain, dl, Reg: VReg, VT: RegVT);
1193 CFRegNode.push_back(Elt: ArgIn.getValue(R: ArgIn->getNumValues() - 1));
1194 }
1195 } else {
1196 // Only arguments passed on the stack should make it here.
1197 assert(VA.isMemLoc());
1198 // Load the argument to a virtual register
1199 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
1200 if (ObjSize > StackSlotSize) {
1201 errs() << "LowerFormalArguments Unhandled argument type: "
1202 << VA.getLocVT() << "\n";
1203 }
1204 // Create the frame index object for this incoming parameter...
1205 int FI = MFI.CreateFixedObject(Size: ObjSize,
1206 SPOffset: LRSaveSize + VA.getLocMemOffset(),
1207 IsImmutable: true);
1208
1209 // Create the SelectionDAG nodes corresponding to a load
1210 //from this parameter
1211 SDValue FIN = DAG.getFrameIndex(FI, VT: MVT::i32);
1212 ArgIn = DAG.getLoad(VT: VA.getLocVT(), dl, Chain, Ptr: FIN,
1213 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI));
1214 }
1215 const ArgDataPair ADP = { .SDV: ArgIn, .Flags: Ins[i].Flags };
1216 ArgData.push_back(Elt: ADP);
1217 }
1218
1219 // 1b. CopyFromReg vararg registers.
1220 if (isVarArg) {
1221 // Argument registers
1222 static const MCPhysReg ArgRegs[] = {
1223 XCore::R0, XCore::R1, XCore::R2, XCore::R3
1224 };
1225 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1226 unsigned FirstVAReg = CCInfo.getFirstUnallocated(Regs: ArgRegs);
1227 if (FirstVAReg < std::size(ArgRegs)) {
1228 int offset = 0;
1229 // Save remaining registers, storing higher register numbers at a higher
1230 // address
1231 for (int i = std::size(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
1232 // Create a stack slot
1233 int FI = MFI.CreateFixedObject(Size: 4, SPOffset: offset, IsImmutable: true);
1234 if (i == (int)FirstVAReg) {
1235 XFI->setVarArgsFrameIndex(FI);
1236 }
1237 offset -= StackSlotSize;
1238 SDValue FIN = DAG.getFrameIndex(FI, VT: MVT::i32);
1239 // Move argument from phys reg -> virt reg
1240 Register VReg = RegInfo.createVirtualRegister(RegClass: &XCore::GRRegsRegClass);
1241 RegInfo.addLiveIn(Reg: ArgRegs[i], vreg: VReg);
1242 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg: VReg, VT: MVT::i32);
1243 CFRegNode.push_back(Elt: Val.getValue(R: Val->getNumValues() - 1));
1244 // Move argument from virt reg -> stack
1245 SDValue Store =
1246 DAG.getStore(Chain: Val.getValue(R: 1), dl, Val, Ptr: FIN, PtrInfo: MachinePointerInfo());
1247 MemOps.push_back(Elt: Store);
1248 }
1249 } else {
1250 // This will point to the next argument passed via stack.
1251 XFI->setVarArgsFrameIndex(
1252 MFI.CreateFixedObject(Size: 4, SPOffset: LRSaveSize + CCInfo.getStackSize(), IsImmutable: true));
1253 }
1254 }
1255
1256 // 2. chain CopyFromReg nodes into a TokenFactor.
1257 if (!CFRegNode.empty())
1258 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: CFRegNode);
1259
1260 // 3. Memcpy 'byVal' args & push final InVals.
1261 // Aggregates passed "byVal" need to be copied by the callee.
1262 // The callee will use a pointer to this copy, rather than the original
1263 // pointer.
1264 for (const ArgDataPair &ArgDI : ArgData) {
1265 if (ArgDI.Flags.isByVal() && ArgDI.Flags.getByValSize()) {
1266 unsigned Size = ArgDI.Flags.getByValSize();
1267 Align Alignment =
1268 std::max(a: Align(StackSlotSize), b: ArgDI.Flags.getNonZeroByValAlign());
1269 // Create a new object on the stack and copy the pointee into it.
1270 int FI = MFI.CreateStackObject(Size, Alignment, isSpillSlot: false);
1271 SDValue FIN = DAG.getFrameIndex(FI, VT: MVT::i32);
1272 InVals.push_back(Elt: FIN);
1273 MemOps.push_back(Elt: DAG.getMemcpy(
1274 Chain, dl, Dst: FIN, Src: ArgDI.SDV, Size: DAG.getConstant(Val: Size, DL: dl, VT: MVT::i32),
1275 Alignment, isVol: false, AlwaysInline: false, /*CI=*/nullptr, OverrideTailCall: std::nullopt,
1276 DstPtrInfo: MachinePointerInfo(), SrcPtrInfo: MachinePointerInfo()));
1277 } else {
1278 InVals.push_back(Elt: ArgDI.SDV);
1279 }
1280 }
1281
1282 // 4, chain mem ops nodes into a TokenFactor.
1283 if (!MemOps.empty()) {
1284 MemOps.push_back(Elt: Chain);
1285 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOps);
1286 }
1287
1288 return Chain;
1289}
1290
1291//===----------------------------------------------------------------------===//
1292// Return Value Calling Convention Implementation
1293//===----------------------------------------------------------------------===//
1294
1295bool XCoreTargetLowering::
1296CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1297 bool isVarArg,
1298 const SmallVectorImpl<ISD::OutputArg> &Outs,
1299 LLVMContext &Context, const Type *RetTy) const {
1300 SmallVector<CCValAssign, 16> RVLocs;
1301 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1302 if (!CCInfo.CheckReturn(Outs, Fn: RetCC_XCore))
1303 return false;
1304 if (CCInfo.getStackSize() != 0 && isVarArg)
1305 return false;
1306 return true;
1307}
1308
1309SDValue
1310XCoreTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1311 bool isVarArg,
1312 const SmallVectorImpl<ISD::OutputArg> &Outs,
1313 const SmallVectorImpl<SDValue> &OutVals,
1314 const SDLoc &dl, SelectionDAG &DAG) const {
1315
1316 XCoreFunctionInfo *XFI =
1317 DAG.getMachineFunction().getInfo<XCoreFunctionInfo>();
1318 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1319
1320 // CCValAssign - represent the assignment of
1321 // the return value to a location
1322 SmallVector<CCValAssign, 16> RVLocs;
1323
1324 // CCState - Info about the registers and stack slot.
1325 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1326 *DAG.getContext());
1327
1328 // Analyze return values.
1329 if (!isVarArg)
1330 CCInfo.AllocateStack(Size: XFI->getReturnStackOffset(), Alignment: Align(4));
1331
1332 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_XCore);
1333
1334 SDValue Glue;
1335 SmallVector<SDValue, 4> RetOps(1, Chain);
1336
1337 // Return on XCore is always a "retsp 0"
1338 RetOps.push_back(Elt: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
1339
1340 SmallVector<SDValue, 4> MemOpChains;
1341 // Handle return values that must be copied to memory.
1342 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1343 CCValAssign &VA = RVLocs[i];
1344 if (VA.isRegLoc())
1345 continue;
1346 assert(VA.isMemLoc());
1347 if (isVarArg) {
1348 report_fatal_error(reason: "Can't return value from vararg function in memory");
1349 }
1350
1351 int Offset = VA.getLocMemOffset();
1352 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
1353 // Create the frame index object for the memory location.
1354 int FI = MFI.CreateFixedObject(Size: ObjSize, SPOffset: Offset, IsImmutable: false);
1355
1356 // Create a SelectionDAG node corresponding to a store
1357 // to this memory location.
1358 SDValue FIN = DAG.getFrameIndex(FI, VT: MVT::i32);
1359 MemOpChains.push_back(Elt: DAG.getStore(
1360 Chain, dl, Val: OutVals[i], Ptr: FIN,
1361 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI)));
1362 }
1363
1364 // Transform all store nodes into one single node because
1365 // all stores are independent of each other.
1366 if (!MemOpChains.empty())
1367 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains);
1368
1369 // Now handle return values copied to registers.
1370 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1371 CCValAssign &VA = RVLocs[i];
1372 if (!VA.isRegLoc())
1373 continue;
1374 // Copy the result values into the output registers.
1375 Chain = DAG.getCopyToReg(Chain, dl, Reg: VA.getLocReg(), N: OutVals[i], Glue);
1376
1377 // guarantee that all emitted copies are
1378 // stuck together, avoiding something bad
1379 Glue = Chain.getValue(R: 1);
1380 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
1381 }
1382
1383 RetOps[0] = Chain; // Update chain.
1384
1385 // Add the glue if we have it.
1386 if (Glue.getNode())
1387 RetOps.push_back(Elt: Glue);
1388
1389 return DAG.getNode(Opcode: XCoreISD::RETSP, DL: dl, VT: MVT::Other, Ops: RetOps);
1390}
1391
1392//===----------------------------------------------------------------------===//
1393// Other Lowering Code
1394//===----------------------------------------------------------------------===//
1395
1396MachineBasicBlock *
1397XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1398 MachineBasicBlock *BB) const {
1399 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1400 DebugLoc dl = MI.getDebugLoc();
1401 assert((MI.getOpcode() == XCore::SELECT_CC) &&
1402 "Unexpected instr type to insert");
1403
1404 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1405 // control-flow pattern. The incoming instruction knows the destination vreg
1406 // to set, the condition code register to branch on, the true/false values to
1407 // select between, and a branch opcode to use.
1408 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1409 MachineFunction::iterator It = ++BB->getIterator();
1410
1411 // thisMBB:
1412 // ...
1413 // TrueVal = ...
1414 // cmpTY ccX, r1, r2
1415 // bCC copy1MBB
1416 // fallthrough --> copy0MBB
1417 MachineBasicBlock *thisMBB = BB;
1418 MachineFunction *F = BB->getParent();
1419 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
1420 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
1421 F->insert(MBBI: It, MBB: copy0MBB);
1422 F->insert(MBBI: It, MBB: sinkMBB);
1423
1424 // Transfer the remainder of BB and its successor edges to sinkMBB.
1425 sinkMBB->splice(Where: sinkMBB->begin(), Other: BB,
1426 From: std::next(x: MachineBasicBlock::iterator(MI)), To: BB->end());
1427 sinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
1428
1429 // Next, add the true and fallthrough blocks as its successors.
1430 BB->addSuccessor(Succ: copy0MBB);
1431 BB->addSuccessor(Succ: sinkMBB);
1432
1433 BuildMI(BB, MIMD: dl, MCID: TII.get(Opcode: XCore::BRFT_lru6))
1434 .addReg(RegNo: MI.getOperand(i: 1).getReg())
1435 .addMBB(MBB: sinkMBB);
1436
1437 // copy0MBB:
1438 // %FalseValue = ...
1439 // # fallthrough to sinkMBB
1440 BB = copy0MBB;
1441
1442 // Update machine-CFG edges
1443 BB->addSuccessor(Succ: sinkMBB);
1444
1445 // sinkMBB:
1446 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1447 // ...
1448 BB = sinkMBB;
1449 BuildMI(BB&: *BB, I: BB->begin(), MIMD: dl, MCID: TII.get(Opcode: XCore::PHI), DestReg: MI.getOperand(i: 0).getReg())
1450 .addReg(RegNo: MI.getOperand(i: 3).getReg())
1451 .addMBB(MBB: copy0MBB)
1452 .addReg(RegNo: MI.getOperand(i: 2).getReg())
1453 .addMBB(MBB: thisMBB);
1454
1455 MI.eraseFromParent(); // The pseudo instruction is gone now.
1456 return BB;
1457}
1458
1459//===----------------------------------------------------------------------===//
1460// Target Optimization Hooks
1461//===----------------------------------------------------------------------===//
1462
1463SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
1464 DAGCombinerInfo &DCI) const {
1465 SelectionDAG &DAG = DCI.DAG;
1466 SDLoc dl(N);
1467 switch (N->getOpcode()) {
1468 default: break;
1469 case ISD::INTRINSIC_VOID:
1470 switch (N->getConstantOperandVal(Num: 1)) {
1471 case Intrinsic::xcore_outt:
1472 case Intrinsic::xcore_outct:
1473 case Intrinsic::xcore_chkct: {
1474 SDValue OutVal = N->getOperand(Num: 3);
1475 // These instructions ignore the high bits.
1476 if (OutVal.hasOneUse()) {
1477 unsigned BitWidth = OutVal.getValueSizeInBits();
1478 APInt DemandedMask = APInt::getLowBitsSet(numBits: BitWidth, loBitsSet: 8);
1479 KnownBits Known;
1480 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1481 !DCI.isBeforeLegalizeOps());
1482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1483 if (TLI.ShrinkDemandedConstant(Op: OutVal, DemandedBits: DemandedMask, TLO) ||
1484 TLI.SimplifyDemandedBits(Op: OutVal, DemandedBits: DemandedMask, Known, TLO))
1485 DCI.CommitTargetLoweringOpt(TLO);
1486 }
1487 break;
1488 }
1489 case Intrinsic::xcore_setpt: {
1490 SDValue Time = N->getOperand(Num: 3);
1491 // This instruction ignores the high bits.
1492 if (Time.hasOneUse()) {
1493 unsigned BitWidth = Time.getValueSizeInBits();
1494 APInt DemandedMask = APInt::getLowBitsSet(numBits: BitWidth, loBitsSet: 16);
1495 KnownBits Known;
1496 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1497 !DCI.isBeforeLegalizeOps());
1498 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1499 if (TLI.ShrinkDemandedConstant(Op: Time, DemandedBits: DemandedMask, TLO) ||
1500 TLI.SimplifyDemandedBits(Op: Time, DemandedBits: DemandedMask, Known, TLO))
1501 DCI.CommitTargetLoweringOpt(TLO);
1502 }
1503 break;
1504 }
1505 }
1506 break;
1507 case XCoreISD::LADD: {
1508 SDValue N0 = N->getOperand(Num: 0);
1509 SDValue N1 = N->getOperand(Num: 1);
1510 SDValue N2 = N->getOperand(Num: 2);
1511 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(Val&: N0);
1512 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Val&: N1);
1513 EVT VT = N0.getValueType();
1514
1515 // canonicalize constant to RHS
1516 if (N0C && !N1C)
1517 return DAG.getNode(Opcode: XCoreISD::LADD, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), N1, N2: N0, N3: N2);
1518
1519 // fold (ladd 0, 0, x) -> 0, x & 1
1520 if (N0C && N0C->isZero() && N1C && N1C->isZero()) {
1521 SDValue Carry = DAG.getConstant(Val: 0, DL: dl, VT);
1522 SDValue Result = DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: N2,
1523 N2: DAG.getConstant(Val: 1, DL: dl, VT));
1524 SDValue Ops[] = { Result, Carry };
1525 return DAG.getMergeValues(Ops, dl);
1526 }
1527
1528 // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the
1529 // low bit set
1530 if (N1C && N1C->isZero() && N->hasNUsesOfValue(NUses: 0, Value: 1)) {
1531 APInt Mask = APInt::getHighBitsSet(numBits: VT.getSizeInBits(),
1532 hiBitsSet: VT.getSizeInBits() - 1);
1533 KnownBits Known = DAG.computeKnownBits(Op: N2);
1534 if ((Known.Zero & Mask) == Mask) {
1535 SDValue Carry = DAG.getConstant(Val: 0, DL: dl, VT);
1536 SDValue Result = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: N0, N2);
1537 SDValue Ops[] = { Result, Carry };
1538 return DAG.getMergeValues(Ops, dl);
1539 }
1540 }
1541 }
1542 break;
1543 case XCoreISD::LSUB: {
1544 SDValue N0 = N->getOperand(Num: 0);
1545 SDValue N1 = N->getOperand(Num: 1);
1546 SDValue N2 = N->getOperand(Num: 2);
1547 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(Val&: N0);
1548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Val&: N1);
1549 EVT VT = N0.getValueType();
1550
1551 // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set
1552 if (N0C && N0C->isZero() && N1C && N1C->isZero()) {
1553 APInt Mask = APInt::getHighBitsSet(numBits: VT.getSizeInBits(),
1554 hiBitsSet: VT.getSizeInBits() - 1);
1555 KnownBits Known = DAG.computeKnownBits(Op: N2);
1556 if ((Known.Zero & Mask) == Mask) {
1557 SDValue Borrow = N2;
1558 SDValue Result = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT,
1559 N1: DAG.getConstant(Val: 0, DL: dl, VT), N2);
1560 SDValue Ops[] = { Result, Borrow };
1561 return DAG.getMergeValues(Ops, dl);
1562 }
1563 }
1564
1565 // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the
1566 // low bit set
1567 if (N1C && N1C->isZero() && N->hasNUsesOfValue(NUses: 0, Value: 1)) {
1568 APInt Mask = APInt::getHighBitsSet(numBits: VT.getSizeInBits(),
1569 hiBitsSet: VT.getSizeInBits() - 1);
1570 KnownBits Known = DAG.computeKnownBits(Op: N2);
1571 if ((Known.Zero & Mask) == Mask) {
1572 SDValue Borrow = DAG.getConstant(Val: 0, DL: dl, VT);
1573 SDValue Result = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: N0, N2);
1574 SDValue Ops[] = { Result, Borrow };
1575 return DAG.getMergeValues(Ops, dl);
1576 }
1577 }
1578 }
1579 break;
1580 case XCoreISD::LMUL: {
1581 SDValue N0 = N->getOperand(Num: 0);
1582 SDValue N1 = N->getOperand(Num: 1);
1583 SDValue N2 = N->getOperand(Num: 2);
1584 SDValue N3 = N->getOperand(Num: 3);
1585 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(Val&: N0);
1586 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Val&: N1);
1587 EVT VT = N0.getValueType();
1588 // Canonicalize multiplicative constant to RHS. If both multiplicative
1589 // operands are constant canonicalize smallest to RHS.
1590 if ((N0C && !N1C) ||
1591 (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue()))
1592 return DAG.getNode(Opcode: XCoreISD::LMUL, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT),
1593 N1, N2: N0, N3: N2, N4: N3);
1594
1595 // lmul(x, 0, a, b)
1596 if (N1C && N1C->isZero()) {
1597 // If the high result is unused fold to add(a, b)
1598 if (N->hasNUsesOfValue(NUses: 0, Value: 0)) {
1599 SDValue Lo = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: N2, N2: N3);
1600 SDValue Ops[] = { Lo, Lo };
1601 return DAG.getMergeValues(Ops, dl);
1602 }
1603 // Otherwise fold to ladd(a, b, 0)
1604 SDValue Result =
1605 DAG.getNode(Opcode: XCoreISD::LADD, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), N1: N2, N2: N3, N3: N1);
1606 SDValue Carry(Result.getNode(), 1);
1607 SDValue Ops[] = { Carry, Result };
1608 return DAG.getMergeValues(Ops, dl);
1609 }
1610 }
1611 break;
1612 case ISD::ADD: {
1613 // Fold 32 bit expressions such as add(add(mul(x,y),a),b) ->
1614 // lmul(x, y, a, b). The high result of lmul will be ignored.
1615 // This is only profitable if the intermediate results are unused
1616 // elsewhere.
1617 SDValue Mul0, Mul1, Addend0, Addend1;
1618 if (N->getValueType(ResNo: 0) == MVT::i32 &&
1619 isADDADDMUL(Op: SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, requireIntermediatesHaveOneUse: true)) {
1620 SDValue Ignored = DAG.getNode(Opcode: XCoreISD::LMUL, DL: dl,
1621 VTList: DAG.getVTList(VT1: MVT::i32, VT2: MVT::i32), N1: Mul0,
1622 N2: Mul1, N3: Addend0, N4: Addend1);
1623 SDValue Result(Ignored.getNode(), 1);
1624 return Result;
1625 }
1626 APInt HighMask = APInt::getHighBitsSet(numBits: 64, hiBitsSet: 32);
1627 // Fold 64 bit expression such as add(add(mul(x,y),a),b) ->
1628 // lmul(x, y, a, b) if all operands are zero-extended. We do this
1629 // before type legalization as it is messy to match the operands after
1630 // that.
1631 if (N->getValueType(ResNo: 0) == MVT::i64 &&
1632 isADDADDMUL(Op: SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, requireIntermediatesHaveOneUse: false) &&
1633 DAG.MaskedValueIsZero(Op: Mul0, Mask: HighMask) &&
1634 DAG.MaskedValueIsZero(Op: Mul1, Mask: HighMask) &&
1635 DAG.MaskedValueIsZero(Op: Addend0, Mask: HighMask) &&
1636 DAG.MaskedValueIsZero(Op: Addend1, Mask: HighMask)) {
1637 SDValue Mul0L = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
1638 N1: Mul0, N2: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
1639 SDValue Mul1L = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
1640 N1: Mul1, N2: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
1641 SDValue Addend0L = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
1642 N1: Addend0, N2: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
1643 SDValue Addend1L = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i32,
1644 N1: Addend1, N2: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
1645 SDValue Hi = DAG.getNode(Opcode: XCoreISD::LMUL, DL: dl,
1646 VTList: DAG.getVTList(VT1: MVT::i32, VT2: MVT::i32), N1: Mul0L, N2: Mul1L,
1647 N3: Addend0L, N4: Addend1L);
1648 SDValue Lo(Hi.getNode(), 1);
1649 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: Lo, N2: Hi);
1650 }
1651 }
1652 break;
1653 case ISD::STORE: {
1654 // Replace unaligned store of unaligned load with memmove.
1655 StoreSDNode *ST = cast<StoreSDNode>(Val: N);
1656 if (!DCI.isBeforeLegalize() ||
1657 allowsMemoryAccessForAlignment(Context&: *DAG.getContext(), DL: DAG.getDataLayout(),
1658 VT: ST->getMemoryVT(),
1659 MMO: *ST->getMemOperand()) ||
1660 ST->isVolatile() || ST->isIndexed()) {
1661 break;
1662 }
1663 SDValue Chain = ST->getChain();
1664
1665 unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits();
1666 assert((StoreBits % 8) == 0 &&
1667 "Store size in bits must be a multiple of 8");
1668 Align Alignment = ST->getAlign();
1669
1670 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val: ST->getValue())) {
1671 if (LD->hasNUsesOfValue(NUses: 1, Value: 0) && ST->getMemoryVT() == LD->getMemoryVT() &&
1672 LD->getAlign() == Alignment &&
1673 !LD->isVolatile() && !LD->isIndexed() &&
1674 Chain.reachesChainWithoutSideEffects(Dest: SDValue(LD, 1))) {
1675 bool isTail = isInTailCallPosition(DAG, Node: ST, Chain);
1676 return DAG.getMemmove(Chain, dl, Dst: ST->getBasePtr(), Src: LD->getBasePtr(),
1677 Size: DAG.getConstant(Val: StoreBits / 8, DL: dl, VT: MVT::i32),
1678 Alignment, isVol: false, CI: nullptr, OverrideTailCall: isTail,
1679 DstPtrInfo: ST->getPointerInfo(), SrcPtrInfo: LD->getPointerInfo());
1680 }
1681 }
1682 break;
1683 }
1684 }
1685 return SDValue();
1686}
1687
1688void XCoreTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1689 KnownBits &Known,
1690 const APInt &DemandedElts,
1691 const SelectionDAG &DAG,
1692 unsigned Depth) const {
1693 Known.resetAll();
1694 switch (Op.getOpcode()) {
1695 default: break;
1696 case XCoreISD::LADD:
1697 case XCoreISD::LSUB:
1698 if (Op.getResNo() == 1) {
1699 // Top bits of carry / borrow are clear.
1700 Known.Zero = APInt::getHighBitsSet(numBits: Known.getBitWidth(),
1701 hiBitsSet: Known.getBitWidth() - 1);
1702 }
1703 break;
1704 case ISD::INTRINSIC_W_CHAIN:
1705 {
1706 unsigned IntNo = Op.getConstantOperandVal(i: 1);
1707 switch (IntNo) {
1708 case Intrinsic::xcore_getts:
1709 // High bits are known to be zero.
1710 Known.Zero =
1711 APInt::getHighBitsSet(numBits: Known.getBitWidth(), hiBitsSet: Known.getBitWidth() - 16);
1712 break;
1713 case Intrinsic::xcore_int:
1714 case Intrinsic::xcore_inct:
1715 // High bits are known to be zero.
1716 Known.Zero =
1717 APInt::getHighBitsSet(numBits: Known.getBitWidth(), hiBitsSet: Known.getBitWidth() - 8);
1718 break;
1719 case Intrinsic::xcore_testct:
1720 // Result is either 0 or 1.
1721 Known.Zero =
1722 APInt::getHighBitsSet(numBits: Known.getBitWidth(), hiBitsSet: Known.getBitWidth() - 1);
1723 break;
1724 case Intrinsic::xcore_testwct:
1725 // Result is in the range 0 - 4.
1726 Known.Zero =
1727 APInt::getHighBitsSet(numBits: Known.getBitWidth(), hiBitsSet: Known.getBitWidth() - 3);
1728 break;
1729 }
1730 }
1731 break;
1732 }
1733}
1734
1735//===----------------------------------------------------------------------===//
1736// Addressing mode description hooks
1737//===----------------------------------------------------------------------===//
1738
1739static inline bool isImmUs(int64_t val)
1740{
1741 return (val >= 0 && val <= 11);
1742}
1743
1744static inline bool isImmUs2(int64_t val)
1745{
1746 return (val%2 == 0 && isImmUs(val: val/2));
1747}
1748
1749static inline bool isImmUs4(int64_t val)
1750{
1751 return (val%4 == 0 && isImmUs(val: val/4));
1752}
1753
1754/// isLegalAddressingMode - Return true if the addressing mode represented
1755/// by AM is legal for this target, for a load/store of the specified type.
1756bool XCoreTargetLowering::isLegalAddressingMode(const DataLayout &DL,
1757 const AddrMode &AM, Type *Ty,
1758 unsigned AS,
1759 Instruction *I) const {
1760 if (Ty->getTypeID() == Type::VoidTyID)
1761 return AM.Scale == 0 && isImmUs(val: AM.BaseOffs) && isImmUs4(val: AM.BaseOffs);
1762
1763 unsigned Size = DL.getTypeAllocSize(Ty);
1764 if (AM.BaseGV) {
1765 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
1766 AM.BaseOffs%4 == 0;
1767 }
1768
1769 switch (Size) {
1770 case 1:
1771 // reg + imm
1772 if (AM.Scale == 0) {
1773 return isImmUs(val: AM.BaseOffs);
1774 }
1775 // reg + reg
1776 return AM.Scale == 1 && AM.BaseOffs == 0;
1777 case 2:
1778 case 3:
1779 // reg + imm
1780 if (AM.Scale == 0) {
1781 return isImmUs2(val: AM.BaseOffs);
1782 }
1783 // reg + reg<<1
1784 return AM.Scale == 2 && AM.BaseOffs == 0;
1785 default:
1786 // reg + imm
1787 if (AM.Scale == 0) {
1788 return isImmUs4(val: AM.BaseOffs);
1789 }
1790 // reg + reg<<2
1791 return AM.Scale == 4 && AM.BaseOffs == 0;
1792 }
1793}
1794
1795//===----------------------------------------------------------------------===//
1796// XCore Inline Assembly Support
1797//===----------------------------------------------------------------------===//
1798
1799std::pair<unsigned, const TargetRegisterClass *>
1800XCoreTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1801 StringRef Constraint,
1802 MVT VT) const {
1803 if (Constraint.size() == 1) {
1804 switch (Constraint[0]) {
1805 default : break;
1806 case 'r':
1807 return std::make_pair(x: 0U, y: &XCore::GRRegsRegClass);
1808 }
1809 }
1810 // Use the default implementation in TargetLowering to convert the register
1811 // constraint into a member of a register class.
1812 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
1813}
1814