1//===- PPC.cpp ------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ABIInfoImpl.h"
10#include "TargetInfo.h"
11#include "clang/Basic/DiagnosticFrontend.h"
12
13using namespace clang;
14using namespace clang::CodeGen;
15
16static RValue complexTempStructure(CodeGenFunction &CGF, Address VAListAddr,
17 QualType Ty, CharUnits SlotSize,
18 CharUnits EltSize, const ComplexType *CTy) {
19 Address Addr =
20 emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy: CGF.Int8Ty, DirectSize: SlotSize * 2,
21 DirectAlign: SlotSize, SlotSize, /*AllowHigher*/ AllowHigherAlign: true);
22
23 Address RealAddr = Addr;
24 Address ImagAddr = RealAddr;
25 if (CGF.CGM.getDataLayout().isBigEndian()) {
26 RealAddr =
27 CGF.Builder.CreateConstInBoundsByteGEP(Addr: RealAddr, Offset: SlotSize - EltSize);
28 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(Addr: ImagAddr,
29 Offset: 2 * SlotSize - EltSize);
30 } else {
31 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(Addr: RealAddr, Offset: SlotSize);
32 }
33
34 llvm::Type *EltTy = CGF.ConvertTypeForMem(T: CTy->getElementType());
35 RealAddr = RealAddr.withElementType(ElemTy: EltTy);
36 ImagAddr = ImagAddr.withElementType(ElemTy: EltTy);
37 llvm::Value *Real = CGF.Builder.CreateLoad(Addr: RealAddr, Name: ".vareal");
38 llvm::Value *Imag = CGF.Builder.CreateLoad(Addr: ImagAddr, Name: ".vaimag");
39
40 return RValue::getComplex(V1: Real, V2: Imag);
41}
42
43static bool PPC_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
44 llvm::Value *Address, bool Is64Bit,
45 bool IsAIX) {
46 // This is calculated from the LLVM and GCC tables and verified
47 // against gcc output. AFAIK all PPC ABIs use the same encoding.
48
49 CodeGen::CGBuilderTy &Builder = CGF.Builder;
50
51 llvm::IntegerType *i8 = CGF.Int8Ty;
52 llvm::Value *Four8 = llvm::ConstantInt::get(Ty: i8, V: 4);
53 llvm::Value *Eight8 = llvm::ConstantInt::get(Ty: i8, V: 8);
54 llvm::Value *Sixteen8 = llvm::ConstantInt::get(Ty: i8, V: 16);
55
56 // 0-31: r0-31, the 4-byte or 8-byte general-purpose registers
57 AssignToArrayRange(Builder, Array: Address, Value: Is64Bit ? Eight8 : Four8, FirstIndex: 0, LastIndex: 31);
58
59 // 32-63: fp0-31, the 8-byte floating-point registers
60 AssignToArrayRange(Builder, Array: Address, Value: Eight8, FirstIndex: 32, LastIndex: 63);
61
62 // 64-67 are various 4-byte or 8-byte special-purpose registers:
63 // 64: mq
64 // 65: lr
65 // 66: ctr
66 // 67: ap
67 AssignToArrayRange(Builder, Array: Address, Value: Is64Bit ? Eight8 : Four8, FirstIndex: 64, LastIndex: 67);
68
69 // 68-76 are various 4-byte special-purpose registers:
70 // 68-75 cr0-7
71 // 76: xer
72 AssignToArrayRange(Builder, Array: Address, Value: Four8, FirstIndex: 68, LastIndex: 76);
73
74 // 77-108: v0-31, the 16-byte vector registers
75 AssignToArrayRange(Builder, Array: Address, Value: Sixteen8, FirstIndex: 77, LastIndex: 108);
76
77 // 109: vrsave
78 // 110: vscr
79 AssignToArrayRange(Builder, Array: Address, Value: Is64Bit ? Eight8 : Four8, FirstIndex: 109, LastIndex: 110);
80
81 // AIX does not utilize the rest of the registers.
82 if (IsAIX)
83 return false;
84
85 // 111: spe_acc
86 // 112: spefscr
87 // 113: sfp
88 AssignToArrayRange(Builder, Array: Address, Value: Is64Bit ? Eight8 : Four8, FirstIndex: 111, LastIndex: 113);
89
90 if (!Is64Bit)
91 return false;
92
93 // TODO: Need to verify if these registers are used on 64 bit AIX with Power8
94 // or above CPU.
95 // 64-bit only registers:
96 // 114: tfhar
97 // 115: tfiar
98 // 116: texasr
99 AssignToArrayRange(Builder, Array: Address, Value: Eight8, FirstIndex: 114, LastIndex: 116);
100
101 return false;
102}
103
104// AIX
105namespace {
106/// AIXABIInfo - The AIX XCOFF ABI information.
107class AIXABIInfo : public ABIInfo {
108 const bool Is64Bit;
109 const unsigned PtrByteSize;
110 CharUnits getParamTypeAlignment(QualType Ty) const;
111
112public:
113 AIXABIInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)
114 : ABIInfo(CGT), Is64Bit(Is64Bit), PtrByteSize(Is64Bit ? 8 : 4) {}
115
116 bool isPromotableTypeForABI(QualType Ty) const;
117
118 ABIArgInfo classifyReturnType(QualType RetTy) const;
119 ABIArgInfo classifyArgumentType(QualType Ty) const;
120
121 void computeInfo(CGFunctionInfo &FI) const override {
122 if (!getCXXABI().classifyReturnType(FI))
123 FI.getReturnInfo() = classifyReturnType(RetTy: FI.getReturnType());
124
125 for (auto &I : FI.arguments())
126 I.info = classifyArgumentType(Ty: I.type);
127 }
128
129 RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
130 AggValueSlot Slot) const override;
131};
132
133class AIXTargetCodeGenInfo : public TargetCodeGenInfo {
134 const bool Is64Bit;
135
136public:
137 AIXTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)
138 : TargetCodeGenInfo(std::make_unique<AIXABIInfo>(args&: CGT, args&: Is64Bit)),
139 Is64Bit(Is64Bit) {}
140 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
141 return 1; // r1 is the dedicated stack pointer
142 }
143
144 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
145 llvm::Value *Address) const override;
146
147 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
148 CodeGen::CodeGenModule &M) const override;
149};
150} // namespace
151
152// Return true if the ABI requires Ty to be passed sign- or zero-
153// extended to 32/64 bits.
154bool AIXABIInfo::isPromotableTypeForABI(QualType Ty) const {
155 // Treat an enum type as its underlying type.
156 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
157 Ty = EnumTy->getDecl()->getIntegerType();
158
159 // Promotable integer types are required to be promoted by the ABI.
160 if (getContext().isPromotableIntegerType(T: Ty))
161 return true;
162
163 if (!Is64Bit)
164 return false;
165
166 // For 64 bit mode, in addition to the usual promotable integer types, we also
167 // need to extend all 32-bit types, since the ABI requires promotion to 64
168 // bits.
169 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
170 switch (BT->getKind()) {
171 case BuiltinType::Int:
172 case BuiltinType::UInt:
173 return true;
174 default:
175 break;
176 }
177
178 return false;
179}
180
181ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy) const {
182 if (RetTy->isAnyComplexType())
183 return ABIArgInfo::getDirect();
184
185 if (RetTy->isVectorType())
186 return ABIArgInfo::getDirect();
187
188 if (RetTy->isVoidType())
189 return ABIArgInfo::getIgnore();
190
191 if (isAggregateTypeForABI(T: RetTy))
192 return getNaturalAlignIndirect(Ty: RetTy, AddrSpace: getDataLayout().getAllocaAddrSpace());
193
194 return (isPromotableTypeForABI(Ty: RetTy) ? ABIArgInfo::getExtend(Ty: RetTy)
195 : ABIArgInfo::getDirect());
196}
197
198ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
199 Ty = useFirstFieldIfTransparentUnion(Ty);
200
201 if (Ty->isAnyComplexType())
202 return ABIArgInfo::getDirect();
203
204 if (Ty->isVectorType())
205 return ABIArgInfo::getDirect();
206
207 if (isAggregateTypeForABI(T: Ty)) {
208 // Records with non-trivial destructors/copy-constructors should not be
209 // passed by value.
210 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(T: Ty, CXXABI&: getCXXABI()))
211 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
212 ByVal: RAA == CGCXXABI::RAA_DirectInMemory);
213
214 CharUnits CCAlign = getParamTypeAlignment(Ty);
215 CharUnits TyAlign = getContext().getTypeAlignInChars(T: Ty);
216
217 return ABIArgInfo::getIndirect(
218 Alignment: CCAlign, /*AddrSpace=*/getDataLayout().getAllocaAddrSpace(),
219 /*ByVal=*/true,
220 /*Realign=*/TyAlign > CCAlign);
221 }
222
223 return (isPromotableTypeForABI(Ty)
224 ? ABIArgInfo::getExtend(Ty, T: CGT.ConvertType(T: Ty))
225 : ABIArgInfo::getDirect());
226}
227
228CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
229 // Complex types are passed just like their elements.
230 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
231 Ty = CTy->getElementType();
232
233 if (Ty->isVectorType())
234 return CharUnits::fromQuantity(Quantity: 16);
235
236 // If the structure contains a vector type, the alignment is 16.
237 if (isRecordWithSIMDVectorType(Context&: getContext(), Ty))
238 return CharUnits::fromQuantity(Quantity: 16);
239
240 return CharUnits::fromQuantity(Quantity: PtrByteSize);
241}
242
243RValue AIXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
244 QualType Ty, AggValueSlot Slot) const {
245
246 auto TypeInfo = getContext().getTypeInfoInChars(T: Ty);
247 TypeInfo.Align = getParamTypeAlignment(Ty);
248
249 CharUnits SlotSize = CharUnits::fromQuantity(Quantity: PtrByteSize);
250
251 // If we have a complex type and the base type is smaller than the register
252 // size, the ABI calls for the real and imaginary parts to be right-adjusted
253 // in separate words in 32bit mode or doublewords in 64bit mode. However,
254 // Clang expects us to produce a pointer to a structure with the two parts
255 // packed tightly. So generate loads of the real and imaginary parts relative
256 // to the va_list pointer, and store them to a temporary structure. We do the
257 // same as the PPC64ABI here.
258 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
259 CharUnits EltSize = TypeInfo.Width / 2;
260 if (EltSize < SlotSize)
261 return complexTempStructure(CGF, VAListAddr, Ty, SlotSize, EltSize, CTy);
262 }
263
264 return emitVoidPtrVAArg(CGF, VAListAddr, ValueTy: Ty, /*Indirect*/ IsIndirect: false, ValueInfo: TypeInfo,
265 SlotSizeAndAlign: SlotSize, /*AllowHigher*/ AllowHigherAlign: true, Slot);
266}
267
268bool AIXTargetCodeGenInfo::initDwarfEHRegSizeTable(
269 CodeGen::CodeGenFunction &CGF, llvm::Value *Address) const {
270 return PPC_initDwarfEHRegSizeTable(CGF, Address, Is64Bit, /*IsAIX*/ true);
271}
272
273void AIXTargetCodeGenInfo::setTargetAttributes(
274 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
275 if (!isa<llvm::GlobalVariable>(Val: GV))
276 return;
277
278 auto *GVar = cast<llvm::GlobalVariable>(Val: GV);
279 auto GVId = GV->getName();
280
281 // Is this a global variable specified by the user as toc-data?
282 bool UserSpecifiedTOC =
283 llvm::binary_search(Range: M.getCodeGenOpts().TocDataVarsUserSpecified, Value&: GVId);
284 // Assumes the same variable cannot be in both TocVarsUserSpecified and
285 // NoTocVars.
286 if (UserSpecifiedTOC ||
287 ((M.getCodeGenOpts().AllTocData) &&
288 !llvm::binary_search(Range: M.getCodeGenOpts().NoTocDataVars, Value&: GVId))) {
289 const unsigned long PointerSize =
290 GV->getParent()->getDataLayout().getPointerSizeInBits() / 8;
291 auto *VarD = dyn_cast<VarDecl>(Val: D);
292 assert(VarD && "Invalid declaration of global variable.");
293
294 ASTContext &Context = D->getASTContext();
295 unsigned Alignment = Context.toBits(CharSize: Context.getDeclAlign(D)) / 8;
296 const auto *Ty = VarD->getType().getTypePtr();
297 const RecordDecl *RDecl =
298 Ty->isRecordType() ? Ty->getAs<RecordType>()->getDecl() : nullptr;
299
300 bool EmitDiagnostic = UserSpecifiedTOC && GV->hasExternalLinkage();
301 auto reportUnsupportedWarning = [&](bool ShouldEmitWarning, StringRef Msg) {
302 if (ShouldEmitWarning)
303 M.getDiags().Report(Loc: D->getLocation(), DiagID: diag::warn_toc_unsupported_type)
304 << GVId << Msg;
305 };
306 if (!Ty || Ty->isIncompleteType())
307 reportUnsupportedWarning(EmitDiagnostic, "of incomplete type");
308 else if (RDecl && RDecl->hasFlexibleArrayMember())
309 reportUnsupportedWarning(EmitDiagnostic,
310 "it contains a flexible array member");
311 else if (VarD->getTLSKind() != VarDecl::TLS_None)
312 reportUnsupportedWarning(EmitDiagnostic, "of thread local storage");
313 else if (PointerSize < Context.getTypeInfo(T: VarD->getType()).Width / 8)
314 reportUnsupportedWarning(EmitDiagnostic,
315 "variable is larger than a pointer");
316 else if (PointerSize < Alignment)
317 reportUnsupportedWarning(EmitDiagnostic,
318 "variable is aligned wider than a pointer");
319 else if (D->hasAttr<SectionAttr>())
320 reportUnsupportedWarning(EmitDiagnostic,
321 "variable has a section attribute");
322 else if (GV->hasExternalLinkage() ||
323 (M.getCodeGenOpts().AllTocData && !GV->hasLocalLinkage()))
324 GVar->addAttribute(Kind: "toc-data");
325 }
326}
327
328// PowerPC-32
329namespace {
330/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
331class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
332 bool IsSoftFloatABI;
333 bool IsRetSmallStructInRegABI;
334
335 CharUnits getParamTypeAlignment(QualType Ty) const;
336
337public:
338 PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI,
339 bool RetSmallStructInRegABI)
340 : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI),
341 IsRetSmallStructInRegABI(RetSmallStructInRegABI) {}
342
343 ABIArgInfo classifyReturnType(QualType RetTy) const;
344
345 void computeInfo(CGFunctionInfo &FI) const override {
346 if (!getCXXABI().classifyReturnType(FI))
347 FI.getReturnInfo() = classifyReturnType(RetTy: FI.getReturnType());
348 for (auto &I : FI.arguments())
349 I.info = classifyArgumentType(RetTy: I.type);
350 }
351
352 RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
353 AggValueSlot Slot) const override;
354};
355
356class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
357public:
358 PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI,
359 bool RetSmallStructInRegABI)
360 : TargetCodeGenInfo(std::make_unique<PPC32_SVR4_ABIInfo>(
361 args&: CGT, args&: SoftFloatABI, args&: RetSmallStructInRegABI)) {}
362
363 static bool isStructReturnInRegABI(const llvm::Triple &Triple,
364 const CodeGenOptions &Opts);
365
366 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
367 // This is recovered from gcc output.
368 return 1; // r1 is the dedicated stack pointer
369 }
370
371 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
372 llvm::Value *Address) const override;
373};
374}
375
376CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
377 // Complex types are passed just like their elements.
378 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
379 Ty = CTy->getElementType();
380
381 if (Ty->isVectorType())
382 return CharUnits::fromQuantity(Quantity: getContext().getTypeSize(T: Ty) == 128 ? 16
383 : 4);
384
385 // For single-element float/vector structs, we consider the whole type
386 // to have the same alignment requirements as its single element.
387 const Type *AlignTy = nullptr;
388 if (const Type *EltType = isSingleElementStruct(T: Ty, Context&: getContext())) {
389 const BuiltinType *BT = EltType->getAs<BuiltinType>();
390 if ((EltType->isVectorType() && getContext().getTypeSize(T: EltType) == 128) ||
391 (BT && BT->isFloatingPoint()))
392 AlignTy = EltType;
393 }
394
395 if (AlignTy)
396 return CharUnits::fromQuantity(Quantity: AlignTy->isVectorType() ? 16 : 4);
397 return CharUnits::fromQuantity(Quantity: 4);
398}
399
400ABIArgInfo PPC32_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
401 uint64_t Size;
402
403 // -msvr4-struct-return puts small aggregates in GPR3 and GPR4.
404 if (isAggregateTypeForABI(T: RetTy) && IsRetSmallStructInRegABI &&
405 (Size = getContext().getTypeSize(T: RetTy)) <= 64) {
406 // System V ABI (1995), page 3-22, specified:
407 // > A structure or union whose size is less than or equal to 8 bytes
408 // > shall be returned in r3 and r4, as if it were first stored in the
409 // > 8-byte aligned memory area and then the low addressed word were
410 // > loaded into r3 and the high-addressed word into r4. Bits beyond
411 // > the last member of the structure or union are not defined.
412 //
413 // GCC for big-endian PPC32 inserts the pad before the first member,
414 // not "beyond the last member" of the struct. To stay compatible
415 // with GCC, we coerce the struct to an integer of the same size.
416 // LLVM will extend it and return i32 in r3, or i64 in r3:r4.
417 if (Size == 0)
418 return ABIArgInfo::getIgnore();
419 else {
420 llvm::Type *CoerceTy = llvm::Type::getIntNTy(C&: getVMContext(), N: Size);
421 return ABIArgInfo::getDirect(T: CoerceTy);
422 }
423 }
424
425 return DefaultABIInfo::classifyReturnType(RetTy);
426}
427
428// TODO: this implementation is now likely redundant with
429// DefaultABIInfo::EmitVAArg.
430RValue PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
431 QualType Ty, AggValueSlot Slot) const {
432 if (getTarget().getTriple().isOSDarwin()) {
433 auto TI = getContext().getTypeInfoInChars(T: Ty);
434 TI.Align = getParamTypeAlignment(Ty);
435
436 CharUnits SlotSize = CharUnits::fromQuantity(Quantity: 4);
437 return emitVoidPtrVAArg(CGF, VAListAddr: VAList, ValueTy: Ty,
438 IsIndirect: classifyArgumentType(RetTy: Ty).isIndirect(), ValueInfo: TI, SlotSizeAndAlign: SlotSize,
439 /*AllowHigherAlign=*/true, Slot);
440 }
441
442 const unsigned OverflowLimit = 8;
443 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
444 // TODO: Implement this. For now ignore.
445 (void)CTy;
446 return RValue::getAggregate(addr: Address::invalid()); // FIXME?
447 }
448
449 // struct __va_list_tag {
450 // unsigned char gpr;
451 // unsigned char fpr;
452 // unsigned short reserved;
453 // void *overflow_arg_area;
454 // void *reg_save_area;
455 // };
456
457 bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(T: Ty) == 64;
458 bool isInt = !Ty->isFloatingType();
459 bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(T: Ty) == 64;
460
461 // All aggregates are passed indirectly? That doesn't seem consistent
462 // with the argument-lowering code.
463 bool isIndirect = isAggregateTypeForABI(T: Ty);
464
465 CGBuilderTy &Builder = CGF.Builder;
466
467 // The calling convention either uses 1-2 GPRs or 1 FPR.
468 Address NumRegsAddr = Address::invalid();
469 if (isInt || IsSoftFloatABI) {
470 NumRegsAddr = Builder.CreateStructGEP(Addr: VAList, Index: 0, Name: "gpr");
471 } else {
472 NumRegsAddr = Builder.CreateStructGEP(Addr: VAList, Index: 1, Name: "fpr");
473 }
474
475 llvm::Value *NumRegs = Builder.CreateLoad(Addr: NumRegsAddr, Name: "numUsedRegs");
476
477 // "Align" the register count when TY is i64.
478 if (isI64 || (isF64 && IsSoftFloatABI)) {
479 NumRegs = Builder.CreateAdd(LHS: NumRegs, RHS: Builder.getInt8(C: 1));
480 NumRegs = Builder.CreateAnd(LHS: NumRegs, RHS: Builder.getInt8(C: (uint8_t) ~1U));
481 }
482
483 llvm::Value *CC =
484 Builder.CreateICmpULT(LHS: NumRegs, RHS: Builder.getInt8(C: OverflowLimit), Name: "cond");
485
486 llvm::BasicBlock *UsingRegs = CGF.createBasicBlock(name: "using_regs");
487 llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock(name: "using_overflow");
488 llvm::BasicBlock *Cont = CGF.createBasicBlock(name: "cont");
489
490 Builder.CreateCondBr(Cond: CC, True: UsingRegs, False: UsingOverflow);
491
492 llvm::Type *DirectTy = CGF.ConvertType(T: Ty), *ElementTy = DirectTy;
493 if (isIndirect)
494 DirectTy = CGF.UnqualPtrTy;
495
496 // Case 1: consume registers.
497 Address RegAddr = Address::invalid();
498 {
499 CGF.EmitBlock(BB: UsingRegs);
500
501 Address RegSaveAreaPtr = Builder.CreateStructGEP(Addr: VAList, Index: 4);
502 RegAddr = Address(Builder.CreateLoad(Addr: RegSaveAreaPtr), CGF.Int8Ty,
503 CharUnits::fromQuantity(Quantity: 8));
504 assert(RegAddr.getElementType() == CGF.Int8Ty);
505
506 // Floating-point registers start after the general-purpose registers.
507 if (!(isInt || IsSoftFloatABI)) {
508 RegAddr = Builder.CreateConstInBoundsByteGEP(Addr: RegAddr,
509 Offset: CharUnits::fromQuantity(Quantity: 32));
510 }
511
512 // Get the address of the saved value by scaling the number of
513 // registers we've used by the number of
514 CharUnits RegSize = CharUnits::fromQuantity(Quantity: (isInt || IsSoftFloatABI) ? 4 : 8);
515 llvm::Value *RegOffset =
516 Builder.CreateMul(LHS: NumRegs, RHS: Builder.getInt8(C: RegSize.getQuantity()));
517 RegAddr = Address(Builder.CreateInBoundsGEP(
518 Ty: CGF.Int8Ty, Ptr: RegAddr.emitRawPointer(CGF), IdxList: RegOffset),
519 DirectTy,
520 RegAddr.getAlignment().alignmentOfArrayElement(elementSize: RegSize));
521
522 // Increase the used-register count.
523 NumRegs =
524 Builder.CreateAdd(LHS: NumRegs,
525 RHS: Builder.getInt8(C: (isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
526 Builder.CreateStore(Val: NumRegs, Addr: NumRegsAddr);
527
528 CGF.EmitBranch(Block: Cont);
529 }
530
531 // Case 2: consume space in the overflow area.
532 Address MemAddr = Address::invalid();
533 {
534 CGF.EmitBlock(BB: UsingOverflow);
535
536 Builder.CreateStore(Val: Builder.getInt8(C: OverflowLimit), Addr: NumRegsAddr);
537
538 // Everything in the overflow area is rounded up to a size of at least 4.
539 CharUnits OverflowAreaAlign = CharUnits::fromQuantity(Quantity: 4);
540
541 CharUnits Size;
542 if (!isIndirect) {
543 auto TypeInfo = CGF.getContext().getTypeInfoInChars(T: Ty);
544 Size = TypeInfo.Width.alignTo(Align: OverflowAreaAlign);
545 } else {
546 Size = CGF.getPointerSize();
547 }
548
549 Address OverflowAreaAddr = Builder.CreateStructGEP(Addr: VAList, Index: 3);
550 Address OverflowArea =
551 Address(Builder.CreateLoad(Addr: OverflowAreaAddr, Name: "argp.cur"), CGF.Int8Ty,
552 OverflowAreaAlign);
553 // Round up address of argument to alignment
554 CharUnits Align = CGF.getContext().getTypeAlignInChars(T: Ty);
555 if (Align > OverflowAreaAlign) {
556 llvm::Value *Ptr = OverflowArea.emitRawPointer(CGF);
557 OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
558 OverflowArea.getElementType(), Align);
559 }
560
561 MemAddr = OverflowArea.withElementType(ElemTy: DirectTy);
562
563 // Increase the overflow area.
564 OverflowArea = Builder.CreateConstInBoundsByteGEP(Addr: OverflowArea, Offset: Size);
565 Builder.CreateStore(Val: OverflowArea.emitRawPointer(CGF), Addr: OverflowAreaAddr);
566 CGF.EmitBranch(Block: Cont);
567 }
568
569 CGF.EmitBlock(BB: Cont);
570
571 // Merge the cases with a phi.
572 Address Result = emitMergePHI(CGF, Addr1: RegAddr, Block1: UsingRegs, Addr2: MemAddr, Block2: UsingOverflow,
573 Name: "vaarg.addr");
574
575 // Load the pointer if the argument was passed indirectly.
576 if (isIndirect) {
577 Result = Address(Builder.CreateLoad(Addr: Result, Name: "aggr"), ElementTy,
578 getContext().getTypeAlignInChars(T: Ty));
579 }
580
581 return CGF.EmitLoadOfAnyValue(V: CGF.MakeAddrLValue(Addr: Result, T: Ty), Slot);
582}
583
584bool PPC32TargetCodeGenInfo::isStructReturnInRegABI(
585 const llvm::Triple &Triple, const CodeGenOptions &Opts) {
586 assert(Triple.isPPC32());
587
588 switch (Opts.getStructReturnConvention()) {
589 case CodeGenOptions::SRCK_Default:
590 break;
591 case CodeGenOptions::SRCK_OnStack: // -maix-struct-return
592 return false;
593 case CodeGenOptions::SRCK_InRegs: // -msvr4-struct-return
594 return true;
595 }
596
597 if (Triple.isOSBinFormatELF() && !Triple.isOSLinux())
598 return true;
599
600 return false;
601}
602
603bool
604PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
605 llvm::Value *Address) const {
606 return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ false,
607 /*IsAIX*/ false);
608}
609
610// PowerPC-64
611
612namespace {
613
614/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
615class PPC64_SVR4_ABIInfo : public ABIInfo {
616 static const unsigned GPRBits = 64;
617 PPC64_SVR4_ABIKind Kind;
618 bool IsSoftFloatABI;
619
620public:
621 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, PPC64_SVR4_ABIKind Kind,
622 bool SoftFloatABI)
623 : ABIInfo(CGT), Kind(Kind), IsSoftFloatABI(SoftFloatABI) {}
624
625 bool isPromotableTypeForABI(QualType Ty) const;
626 CharUnits getParamTypeAlignment(QualType Ty) const;
627
628 ABIArgInfo classifyReturnType(QualType RetTy) const;
629 ABIArgInfo classifyArgumentType(QualType Ty) const;
630
631 bool isHomogeneousAggregateBaseType(QualType Ty) const override;
632 bool isHomogeneousAggregateSmallEnough(const Type *Ty,
633 uint64_t Members) const override;
634
635 // TODO: We can add more logic to computeInfo to improve performance.
636 // Example: For aggregate arguments that fit in a register, we could
637 // use getDirectInReg (as is done below for structs containing a single
638 // floating-point value) to avoid pushing them to memory on function
639 // entry. This would require changing the logic in PPCISelLowering
640 // when lowering the parameters in the caller and args in the callee.
641 void computeInfo(CGFunctionInfo &FI) const override {
642 if (!getCXXABI().classifyReturnType(FI))
643 FI.getReturnInfo() = classifyReturnType(RetTy: FI.getReturnType());
644 for (auto &I : FI.arguments()) {
645 // We rely on the default argument classification for the most part.
646 // One exception: An aggregate containing a single floating-point
647 // or vector item must be passed in a register if one is available.
648 const Type *T = isSingleElementStruct(T: I.type, Context&: getContext());
649 if (T) {
650 const BuiltinType *BT = T->getAs<BuiltinType>();
651 if ((T->isVectorType() && getContext().getTypeSize(T) == 128) ||
652 (BT && BT->isFloatingPoint())) {
653 QualType QT(T, 0);
654 I.info = ABIArgInfo::getDirectInReg(T: CGT.ConvertType(T: QT));
655 continue;
656 }
657 }
658 I.info = classifyArgumentType(Ty: I.type);
659 }
660 }
661
662 RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
663 AggValueSlot Slot) const override;
664};
665
666class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
667
668public:
669 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT, PPC64_SVR4_ABIKind Kind,
670 bool SoftFloatABI)
671 : TargetCodeGenInfo(
672 std::make_unique<PPC64_SVR4_ABIInfo>(args&: CGT, args&: Kind, args&: SoftFloatABI)) {
673 SwiftInfo =
674 std::make_unique<SwiftABIInfo>(args&: CGT, /*SwiftErrorInRegister=*/args: false);
675 }
676
677 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
678 // This is recovered from gcc output.
679 return 1; // r1 is the dedicated stack pointer
680 }
681
682 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
683 llvm::Value *Address) const override;
684 void emitTargetMetadata(CodeGen::CodeGenModule &CGM,
685 const llvm::MapVector<GlobalDecl, StringRef>
686 &MangledDeclNames) const override;
687};
688
689class PPC64TargetCodeGenInfo : public TargetCodeGenInfo {
690public:
691 PPC64TargetCodeGenInfo(CodeGenTypes &CGT)
692 : TargetCodeGenInfo(std::make_unique<DefaultABIInfo>(args&: CGT)) {}
693
694 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
695 // This is recovered from gcc output.
696 return 1; // r1 is the dedicated stack pointer
697 }
698
699 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
700 llvm::Value *Address) const override;
701};
702}
703
704// Return true if the ABI requires Ty to be passed sign- or zero-
705// extended to 64 bits.
706bool
707PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
708 // Treat an enum type as its underlying type.
709 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
710 Ty = EnumTy->getDecl()->getIntegerType();
711
712 // Promotable integer types are required to be promoted by the ABI.
713 if (isPromotableIntegerTypeForABI(Ty))
714 return true;
715
716 // In addition to the usual promotable integer types, we also need to
717 // extend all 32-bit types, since the ABI requires promotion to 64 bits.
718 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
719 switch (BT->getKind()) {
720 case BuiltinType::Int:
721 case BuiltinType::UInt:
722 return true;
723 default:
724 break;
725 }
726
727 if (const auto *EIT = Ty->getAs<BitIntType>())
728 if (EIT->getNumBits() < 64)
729 return true;
730
731 return false;
732}
733
734/// isAlignedParamType - Determine whether a type requires 16-byte or
735/// higher alignment in the parameter area. Always returns at least 8.
736CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
737 // Complex types are passed just like their elements.
738 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
739 Ty = CTy->getElementType();
740
741 auto FloatUsesVector = [this](QualType Ty){
742 return Ty->isRealFloatingType() && &getContext().getFloatTypeSemantics(
743 T: Ty) == &llvm::APFloat::IEEEquad();
744 };
745
746 // Only vector types of size 16 bytes need alignment (larger types are
747 // passed via reference, smaller types are not aligned).
748 if (Ty->isVectorType()) {
749 return CharUnits::fromQuantity(Quantity: getContext().getTypeSize(T: Ty) == 128 ? 16 : 8);
750 } else if (FloatUsesVector(Ty)) {
751 // According to ABI document section 'Optional Save Areas': If extended
752 // precision floating-point values in IEEE BINARY 128 QUADRUPLE PRECISION
753 // format are supported, map them to a single quadword, quadword aligned.
754 return CharUnits::fromQuantity(Quantity: 16);
755 }
756
757 // For single-element float/vector structs, we consider the whole type
758 // to have the same alignment requirements as its single element.
759 const Type *AlignAsType = nullptr;
760 const Type *EltType = isSingleElementStruct(T: Ty, Context&: getContext());
761 if (EltType) {
762 const BuiltinType *BT = EltType->getAs<BuiltinType>();
763 if ((EltType->isVectorType() && getContext().getTypeSize(T: EltType) == 128) ||
764 (BT && BT->isFloatingPoint()))
765 AlignAsType = EltType;
766 }
767
768 // Likewise for ELFv2 homogeneous aggregates.
769 const Type *Base = nullptr;
770 uint64_t Members = 0;
771 if (!AlignAsType && Kind == PPC64_SVR4_ABIKind::ELFv2 &&
772 isAggregateTypeForABI(T: Ty) && isHomogeneousAggregate(Ty, Base, Members))
773 AlignAsType = Base;
774
775 // With special case aggregates, only vector base types need alignment.
776 if (AlignAsType) {
777 bool UsesVector = AlignAsType->isVectorType() ||
778 FloatUsesVector(QualType(AlignAsType, 0));
779 return CharUnits::fromQuantity(Quantity: UsesVector ? 16 : 8);
780 }
781
782 // Otherwise, we only need alignment for any aggregate type that
783 // has an alignment requirement of >= 16 bytes.
784 if (isAggregateTypeForABI(T: Ty) && getContext().getTypeAlign(T: Ty) >= 128) {
785 return CharUnits::fromQuantity(Quantity: 16);
786 }
787
788 return CharUnits::fromQuantity(Quantity: 8);
789}
790
791bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
792 // Homogeneous aggregates for ELFv2 must have base types of float,
793 // double, long double, or 128-bit vectors.
794 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
795 if (BT->getKind() == BuiltinType::Float ||
796 BT->getKind() == BuiltinType::Double ||
797 BT->getKind() == BuiltinType::LongDouble ||
798 BT->getKind() == BuiltinType::Ibm128 ||
799 (getContext().getTargetInfo().hasFloat128Type() &&
800 (BT->getKind() == BuiltinType::Float128))) {
801 if (IsSoftFloatABI)
802 return false;
803 return true;
804 }
805 }
806 if (const VectorType *VT = Ty->getAs<VectorType>()) {
807 if (getContext().getTypeSize(T: VT) == 128)
808 return true;
809 }
810 return false;
811}
812
813bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
814 const Type *Base, uint64_t Members) const {
815 // Vector and fp128 types require one register, other floating point types
816 // require one or two registers depending on their size.
817 uint32_t NumRegs =
818 ((getContext().getTargetInfo().hasFloat128Type() &&
819 Base->isFloat128Type()) ||
820 Base->isVectorType()) ? 1
821 : (getContext().getTypeSize(T: Base) + 63) / 64;
822
823 // Homogeneous Aggregates may occupy at most 8 registers.
824 return Members * NumRegs <= 8;
825}
826
827ABIArgInfo
828PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
829 Ty = useFirstFieldIfTransparentUnion(Ty);
830
831 if (Ty->isAnyComplexType())
832 return ABIArgInfo::getDirect();
833
834 // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
835 // or via reference (larger than 16 bytes).
836 if (Ty->isVectorType()) {
837 uint64_t Size = getContext().getTypeSize(T: Ty);
838 if (Size > 128)
839 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
840 /*ByVal=*/false);
841 else if (Size < 128) {
842 llvm::Type *CoerceTy = llvm::IntegerType::get(C&: getVMContext(), NumBits: Size);
843 return ABIArgInfo::getDirect(T: CoerceTy);
844 }
845 }
846
847 if (const auto *EIT = Ty->getAs<BitIntType>())
848 if (EIT->getNumBits() > 128)
849 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
850 /*ByVal=*/true);
851
852 if (isAggregateTypeForABI(T: Ty)) {
853 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(T: Ty, CXXABI&: getCXXABI()))
854 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
855 ByVal: RAA == CGCXXABI::RAA_DirectInMemory);
856
857 uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
858 uint64_t TyAlign = getContext().getTypeAlignInChars(T: Ty).getQuantity();
859
860 // ELFv2 homogeneous aggregates are passed as array types.
861 const Type *Base = nullptr;
862 uint64_t Members = 0;
863 if (Kind == PPC64_SVR4_ABIKind::ELFv2 &&
864 isHomogeneousAggregate(Ty, Base, Members)) {
865 llvm::Type *BaseTy = CGT.ConvertType(T: QualType(Base, 0));
866 llvm::Type *CoerceTy = llvm::ArrayType::get(ElementType: BaseTy, NumElements: Members);
867 return ABIArgInfo::getDirect(T: CoerceTy);
868 }
869
870 // If an aggregate may end up fully in registers, we do not
871 // use the ByVal method, but pass the aggregate as array.
872 // This is usually beneficial since we avoid forcing the
873 // back-end to store the argument to memory.
874 uint64_t Bits = getContext().getTypeSize(T: Ty);
875 if (Bits > 0 && Bits <= 8 * GPRBits) {
876 llvm::Type *CoerceTy;
877
878 // Types up to 8 bytes are passed as integer type (which will be
879 // properly aligned in the argument save area doubleword).
880 if (Bits <= GPRBits)
881 CoerceTy =
882 llvm::IntegerType::get(C&: getVMContext(), NumBits: llvm::alignTo(Value: Bits, Align: 8));
883 // Larger types are passed as arrays, with the base type selected
884 // according to the required alignment in the save area.
885 else {
886 uint64_t RegBits = ABIAlign * 8;
887 uint64_t NumRegs = llvm::alignTo(Value: Bits, Align: RegBits) / RegBits;
888 llvm::Type *RegTy = llvm::IntegerType::get(C&: getVMContext(), NumBits: RegBits);
889 CoerceTy = llvm::ArrayType::get(ElementType: RegTy, NumElements: NumRegs);
890 }
891
892 return ABIArgInfo::getDirect(T: CoerceTy);
893 }
894
895 // All other aggregates are passed ByVal.
896 return ABIArgInfo::getIndirect(
897 Alignment: CharUnits::fromQuantity(Quantity: ABIAlign),
898 /*AddrSpace=*/getDataLayout().getAllocaAddrSpace(),
899 /*ByVal=*/true, /*Realign=*/TyAlign > ABIAlign);
900 }
901
902 return (isPromotableTypeForABI(Ty)
903 ? ABIArgInfo::getExtend(Ty, T: CGT.ConvertType(T: Ty))
904 : ABIArgInfo::getDirect());
905}
906
907ABIArgInfo
908PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
909 if (RetTy->isVoidType())
910 return ABIArgInfo::getIgnore();
911
912 if (RetTy->isAnyComplexType())
913 return ABIArgInfo::getDirect();
914
915 // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
916 // or via reference (larger than 16 bytes).
917 if (RetTy->isVectorType()) {
918 uint64_t Size = getContext().getTypeSize(T: RetTy);
919 if (Size > 128)
920 return getNaturalAlignIndirect(Ty: RetTy,
921 AddrSpace: getDataLayout().getAllocaAddrSpace());
922 else if (Size < 128) {
923 llvm::Type *CoerceTy = llvm::IntegerType::get(C&: getVMContext(), NumBits: Size);
924 return ABIArgInfo::getDirect(T: CoerceTy);
925 }
926 }
927
928 if (const auto *EIT = RetTy->getAs<BitIntType>())
929 if (EIT->getNumBits() > 128)
930 return getNaturalAlignIndirect(
931 Ty: RetTy, AddrSpace: getDataLayout().getAllocaAddrSpace(), /*ByVal=*/false);
932
933 if (isAggregateTypeForABI(T: RetTy)) {
934 // ELFv2 homogeneous aggregates are returned as array types.
935 const Type *Base = nullptr;
936 uint64_t Members = 0;
937 if (Kind == PPC64_SVR4_ABIKind::ELFv2 &&
938 isHomogeneousAggregate(Ty: RetTy, Base, Members)) {
939 llvm::Type *BaseTy = CGT.ConvertType(T: QualType(Base, 0));
940 llvm::Type *CoerceTy = llvm::ArrayType::get(ElementType: BaseTy, NumElements: Members);
941 return ABIArgInfo::getDirect(T: CoerceTy);
942 }
943
944 // ELFv2 small aggregates are returned in up to two registers.
945 uint64_t Bits = getContext().getTypeSize(T: RetTy);
946 if (Kind == PPC64_SVR4_ABIKind::ELFv2 && Bits <= 2 * GPRBits) {
947 if (Bits == 0)
948 return ABIArgInfo::getIgnore();
949
950 llvm::Type *CoerceTy;
951 if (Bits > GPRBits) {
952 CoerceTy = llvm::IntegerType::get(C&: getVMContext(), NumBits: GPRBits);
953 CoerceTy = llvm::StructType::get(elt1: CoerceTy, elts: CoerceTy);
954 } else
955 CoerceTy =
956 llvm::IntegerType::get(C&: getVMContext(), NumBits: llvm::alignTo(Value: Bits, Align: 8));
957 return ABIArgInfo::getDirect(T: CoerceTy);
958 }
959
960 // All other aggregates are returned indirectly.
961 return getNaturalAlignIndirect(Ty: RetTy, AddrSpace: getDataLayout().getAllocaAddrSpace());
962 }
963
964 return (isPromotableTypeForABI(Ty: RetTy) ? ABIArgInfo::getExtend(Ty: RetTy)
965 : ABIArgInfo::getDirect());
966}
967
968// Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
969RValue PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
970 QualType Ty, AggValueSlot Slot) const {
971 auto TypeInfo = getContext().getTypeInfoInChars(T: Ty);
972 TypeInfo.Align = getParamTypeAlignment(Ty);
973
974 CharUnits SlotSize = CharUnits::fromQuantity(Quantity: 8);
975
976 // If we have a complex type and the base type is smaller than 8 bytes,
977 // the ABI calls for the real and imaginary parts to be right-adjusted
978 // in separate doublewords. However, Clang expects us to produce a
979 // pointer to a structure with the two parts packed tightly. So generate
980 // loads of the real and imaginary parts relative to the va_list pointer,
981 // and store them to a temporary structure.
982 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
983 CharUnits EltSize = TypeInfo.Width / 2;
984 if (EltSize < SlotSize)
985 return complexTempStructure(CGF, VAListAddr, Ty, SlotSize, EltSize, CTy);
986 }
987
988 // Otherwise, just use the general rule.
989 //
990 // The PPC64 ABI passes some arguments in integer registers, even to variadic
991 // functions. To allow va_list to use the simple "void*" representation,
992 // variadic calls allocate space in the argument area for the integer argument
993 // registers, and variadic functions spill their integer argument registers to
994 // this area in their prologues. When aggregates smaller than a register are
995 // passed this way, they are passed in the least significant bits of the
996 // register, which means that after spilling on big-endian targets they will
997 // be right-aligned in their argument slot. This is uncommon; for a variety of
998 // reasons, other big-endian targets don't end up right-aligning aggregate
999 // types this way, and so right-alignment only applies to fundamental types.
1000 // So on PPC64, we must force the use of right-alignment even for aggregates.
1001 return emitVoidPtrVAArg(CGF, VAListAddr, ValueTy: Ty, /*Indirect*/ IsIndirect: false, ValueInfo: TypeInfo,
1002 SlotSizeAndAlign: SlotSize, /*AllowHigher*/ AllowHigherAlign: true, Slot,
1003 /*ForceRightAdjust*/ true);
1004}
1005
1006bool
1007PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
1008 CodeGen::CodeGenFunction &CGF,
1009 llvm::Value *Address) const {
1010 return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ true,
1011 /*IsAIX*/ false);
1012}
1013
1014void PPC64_SVR4_TargetCodeGenInfo::emitTargetMetadata(
1015 CodeGen::CodeGenModule &CGM,
1016 const llvm::MapVector<GlobalDecl, StringRef> &MangledDeclNames) const {
1017 if (CGM.getTypes().isLongDoubleReferenced()) {
1018 llvm::LLVMContext &Ctx = CGM.getLLVMContext();
1019 const auto *flt = &CGM.getTarget().getLongDoubleFormat();
1020 if (flt == &llvm::APFloat::PPCDoubleDouble())
1021 CGM.getModule().addModuleFlag(Behavior: llvm::Module::Error, Key: "float-abi",
1022 Val: llvm::MDString::get(Context&: Ctx, Str: "doubledouble"));
1023 else if (flt == &llvm::APFloat::IEEEquad())
1024 CGM.getModule().addModuleFlag(Behavior: llvm::Module::Error, Key: "float-abi",
1025 Val: llvm::MDString::get(Context&: Ctx, Str: "ieeequad"));
1026 else if (flt == &llvm::APFloat::IEEEdouble())
1027 CGM.getModule().addModuleFlag(Behavior: llvm::Module::Error, Key: "float-abi",
1028 Val: llvm::MDString::get(Context&: Ctx, Str: "ieeedouble"));
1029 }
1030}
1031
1032bool
1033PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1034 llvm::Value *Address) const {
1035 return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ true,
1036 /*IsAIX*/ false);
1037}
1038
1039std::unique_ptr<TargetCodeGenInfo>
1040CodeGen::createAIXTargetCodeGenInfo(CodeGenModule &CGM, bool Is64Bit) {
1041 return std::make_unique<AIXTargetCodeGenInfo>(args&: CGM.getTypes(), args&: Is64Bit);
1042}
1043
1044std::unique_ptr<TargetCodeGenInfo>
1045CodeGen::createPPC32TargetCodeGenInfo(CodeGenModule &CGM, bool SoftFloatABI) {
1046 bool RetSmallStructInRegABI = PPC32TargetCodeGenInfo::isStructReturnInRegABI(
1047 Triple: CGM.getTriple(), Opts: CGM.getCodeGenOpts());
1048 return std::make_unique<PPC32TargetCodeGenInfo>(args&: CGM.getTypes(), args&: SoftFloatABI,
1049 args&: RetSmallStructInRegABI);
1050}
1051
1052std::unique_ptr<TargetCodeGenInfo>
1053CodeGen::createPPC64TargetCodeGenInfo(CodeGenModule &CGM) {
1054 return std::make_unique<PPC64TargetCodeGenInfo>(args&: CGM.getTypes());
1055}
1056
1057std::unique_ptr<TargetCodeGenInfo> CodeGen::createPPC64_SVR4_TargetCodeGenInfo(
1058 CodeGenModule &CGM, PPC64_SVR4_ABIKind Kind, bool SoftFloatABI) {
1059 return std::make_unique<PPC64_SVR4_TargetCodeGenInfo>(args&: CGM.getTypes(), args&: Kind,
1060 args&: SoftFloatABI);
1061}
1062