1//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements an allocation order for virtual registers.
10//
11// The preferred allocation order for a virtual register depends on allocation
12// hints and target hooks. The AllocationOrder class encapsulates all of that.
13//
14//===----------------------------------------------------------------------===//
15
16#include "AllocationOrder.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/CodeGen/RegisterClassInfo.h"
20#include "llvm/CodeGen/VirtRegMap.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23
24using namespace llvm;
25
26#define DEBUG_TYPE "regalloc"
27
28// Compare VirtRegMap::getRegAllocPref().
29AllocationOrder AllocationOrder::create(Register VirtReg, const VirtRegMap &VRM,
30 const RegisterClassInfo &RegClassInfo,
31 const LiveRegMatrix *Matrix) {
32 const MachineFunction &MF = VRM.getMachineFunction();
33 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
34 auto Order = RegClassInfo.getOrder(RC: MF.getRegInfo().getRegClass(Reg: VirtReg));
35 SmallVector<MCPhysReg, 16> Hints;
36 bool HardHints =
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, VRM: &VRM, Matrix);
38
39 LLVM_DEBUG({
40 if (!Hints.empty()) {
41 dbgs() << "hints:";
42 for (MCPhysReg Hint : Hints)
43 dbgs() << ' ' << printReg(Hint, TRI);
44 dbgs() << '\n';
45 }
46 });
47 assert(all_of(Hints,
48 [&](MCPhysReg Hint) { return is_contained(Order, Hint); }) &&
49 "Target hint is outside allocation order.");
50 return AllocationOrder(std::move(Hints), Order, HardHints);
51}
52