1//===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Collect the sequence of machine instructions for a basic block.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineBasicBlock.h"
14#include "llvm/ADT/STLExtras.h"
15#include "llvm/ADT/StringExtras.h"
16#include "llvm/CodeGen/LiveIntervals.h"
17#include "llvm/CodeGen/LivePhysRegs.h"
18#include "llvm/CodeGen/LiveVariables.h"
19#include "llvm/CodeGen/MachineDomTreeUpdater.h"
20#include "llvm/CodeGen/MachineDominators.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineJumpTableInfo.h"
24#include "llvm/CodeGen/MachineLoopInfo.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/SlotIndexes.h"
27#include "llvm/CodeGen/TargetInstrInfo.h"
28#include "llvm/CodeGen/TargetLowering.h"
29#include "llvm/CodeGen/TargetRegisterInfo.h"
30#include "llvm/CodeGen/TargetSubtargetInfo.h"
31#include "llvm/Config/llvm-config.h"
32#include "llvm/IR/BasicBlock.h"
33#include "llvm/IR/ModuleSlotTracker.h"
34#include "llvm/MC/MCAsmInfo.h"
35#include "llvm/MC/MCContext.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/raw_ostream.h"
38#include "llvm/Target/TargetMachine.h"
39#include <algorithm>
40#include <cmath>
41using namespace llvm;
42
43#define DEBUG_TYPE "codegen"
44
45static cl::opt<bool> PrintSlotIndexes(
46 "print-slotindexes",
47 cl::desc("When printing machine IR, annotate instructions and blocks with "
48 "SlotIndexes when available"),
49 cl::init(Val: true), cl::Hidden);
50
51MachineBasicBlock::MachineBasicBlock(MachineFunction &MF, const BasicBlock *B)
52 : BB(B), Number(-1), xParent(&MF) {
53 Insts.Parent = this;
54 if (B)
55 IrrLoopHeaderWeight = B->getIrrLoopHeaderWeight();
56}
57
58MachineBasicBlock::~MachineBasicBlock() = default;
59
60/// Return the MCSymbol for this basic block.
61MCSymbol *MachineBasicBlock::getSymbol() const {
62 if (!CachedMCSymbol) {
63 const MachineFunction *MF = getParent();
64 MCContext &Ctx = MF->getContext();
65
66 // We emit a non-temporary symbol -- with a descriptive name -- if it begins
67 // a section (with basic block sections). Otherwise we fall back to use temp
68 // label.
69 if (MF->hasBBSections() && isBeginSection()) {
70 SmallString<5> Suffix;
71 if (SectionID == MBBSectionID::ColdSectionID) {
72 Suffix += ".cold";
73 } else if (SectionID == MBBSectionID::ExceptionSectionID) {
74 Suffix += ".eh";
75 } else {
76 // For symbols that represent basic block sections, we add ".__part." to
77 // allow tools like symbolizers to know that this represents a part of
78 // the original function.
79 Suffix = (Suffix + Twine(".__part.") + Twine(SectionID.Number)).str();
80 }
81 CachedMCSymbol = Ctx.getOrCreateSymbol(Name: MF->getName() + Suffix);
82 } else {
83 // If the block occurs as label in inline assembly, parsing the assembly
84 // needs an actual label name => set AlwaysEmit in these cases.
85 CachedMCSymbol = Ctx.createBlockSymbol(
86 Name: "BB" + Twine(MF->getFunctionNumber()) + "_" + Twine(getNumber()),
87 /*AlwaysEmit=*/hasLabelMustBeEmitted());
88 }
89 }
90 return CachedMCSymbol;
91}
92
93MCSymbol *MachineBasicBlock::getEHContSymbol() const {
94 if (!CachedEHContMCSymbol) {
95 const MachineFunction *MF = getParent();
96 SmallString<128> SymbolName;
97 raw_svector_ostream(SymbolName)
98 << "$ehgcr_" << MF->getFunctionNumber() << '_' << getNumber();
99 CachedEHContMCSymbol = MF->getContext().getOrCreateSymbol(Name: SymbolName);
100 }
101 return CachedEHContMCSymbol;
102}
103
104MCSymbol *MachineBasicBlock::getEndSymbol() const {
105 if (!CachedEndMCSymbol) {
106 const MachineFunction *MF = getParent();
107 MCContext &Ctx = MF->getContext();
108 CachedEndMCSymbol = Ctx.createBlockSymbol(
109 Name: "BB_END" + Twine(MF->getFunctionNumber()) + "_" + Twine(getNumber()),
110 /*AlwaysEmit=*/false);
111 }
112 return CachedEndMCSymbol;
113}
114
115raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
116 MBB.print(OS);
117 return OS;
118}
119
120Printable llvm::printMBBReference(const MachineBasicBlock &MBB) {
121 return Printable([&MBB](raw_ostream &OS) { return MBB.printAsOperand(OS); });
122}
123
124/// When an MBB is added to an MF, we need to update the parent pointer of the
125/// MBB, the MBB numbering, and any instructions in the MBB to be on the right
126/// operand list for registers.
127///
128/// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
129/// gets the next available unique MBB number. If it is removed from a
130/// MachineFunction, it goes back to being #-1.
131void ilist_callback_traits<MachineBasicBlock>::addNodeToList(
132 MachineBasicBlock *N) {
133 MachineFunction &MF = *N->getParent();
134 N->Number = MF.addToMBBNumbering(MBB: N);
135
136 // Make sure the instructions have their operands in the reginfo lists.
137 MachineRegisterInfo &RegInfo = MF.getRegInfo();
138 for (MachineInstr &MI : N->instrs())
139 MI.addRegOperandsToUseLists(RegInfo);
140}
141
142void ilist_callback_traits<MachineBasicBlock>::removeNodeFromList(
143 MachineBasicBlock *N) {
144 N->getParent()->removeFromMBBNumbering(N: N->Number);
145 N->Number = -1;
146}
147
148/// When we add an instruction to a basic block list, we update its parent
149/// pointer and add its operands from reg use/def lists if appropriate.
150void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
151 assert(!N->getParent() && "machine instruction already in a basic block");
152 N->setParent(Parent);
153
154 // Add the instruction's register operands to their corresponding
155 // use/def lists.
156 MachineFunction *MF = Parent->getParent();
157 N->addRegOperandsToUseLists(MF->getRegInfo());
158 MF->handleInsertion(MI&: *N);
159}
160
161/// When we remove an instruction from a basic block list, we update its parent
162/// pointer and remove its operands from reg use/def lists if appropriate.
163void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
164 assert(N->getParent() && "machine instruction not in a basic block");
165
166 // Remove from the use/def lists.
167 if (MachineFunction *MF = N->getMF()) {
168 MF->handleRemoval(MI&: *N);
169 N->removeRegOperandsFromUseLists(MF->getRegInfo());
170 }
171
172 N->setParent(nullptr);
173}
174
175/// When moving a range of instructions from one MBB list to another, we need to
176/// update the parent pointers and the use/def lists.
177void ilist_traits<MachineInstr>::transferNodesFromList(ilist_traits &FromList,
178 instr_iterator First,
179 instr_iterator Last) {
180 assert(Parent->getParent() == FromList.Parent->getParent() &&
181 "cannot transfer MachineInstrs between MachineFunctions");
182
183 // If it's within the same BB, there's nothing to do.
184 if (this == &FromList)
185 return;
186
187 assert(Parent != FromList.Parent && "Two lists have the same parent?");
188
189 // If splicing between two blocks within the same function, just update the
190 // parent pointers.
191 for (; First != Last; ++First)
192 First->setParent(Parent);
193}
194
195void ilist_traits<MachineInstr>::deleteNode(MachineInstr *MI) {
196 assert(!MI->getParent() && "MI is still in a block!");
197 Parent->getParent()->deleteMachineInstr(MI);
198}
199
200MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
201 instr_iterator I = instr_begin(), E = instr_end();
202 while (I != E && I->isPHI())
203 ++I;
204 assert((I == E || !I->isInsideBundle()) &&
205 "First non-phi MI cannot be inside a bundle!");
206 return I;
207}
208
209MachineBasicBlock::iterator
210MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) {
211 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
212
213 iterator E = end();
214 while (I != E && (I->isPHI() || I->isPosition() ||
215 TII->isBasicBlockPrologue(MI: *I)))
216 ++I;
217 // FIXME: This needs to change if we wish to bundle labels
218 // inside the bundle.
219 assert((I == E || !I->isInsideBundle()) &&
220 "First non-phi / non-label instruction is inside a bundle!");
221 return I;
222}
223
224MachineBasicBlock::iterator
225MachineBasicBlock::SkipPHIsLabelsAndDebug(MachineBasicBlock::iterator I,
226 Register Reg, bool SkipPseudoOp) {
227 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
228
229 iterator E = end();
230 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugInstr() ||
231 (SkipPseudoOp && I->isPseudoProbe()) ||
232 TII->isBasicBlockPrologue(MI: *I, Reg)))
233 ++I;
234 // FIXME: This needs to change if we wish to bundle labels / dbg_values
235 // inside the bundle.
236 assert((I == E || !I->isInsideBundle()) &&
237 "First non-phi / non-label / non-debug "
238 "instruction is inside a bundle!");
239 return I;
240}
241
242MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
243 iterator B = begin(), E = end(), I = E;
244 while (I != B && ((--I)->isTerminator() || I->isDebugInstr()))
245 ; /*noop */
246 while (I != E && !I->isTerminator())
247 ++I;
248 return I;
249}
250
251MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
252 instr_iterator B = instr_begin(), E = instr_end(), I = E;
253 while (I != B && ((--I)->isTerminator() || I->isDebugInstr()))
254 ; /*noop */
255 while (I != E && !I->isTerminator())
256 ++I;
257 return I;
258}
259
260MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminatorForward() {
261 return find_if(Range: instrs(), P: [](auto &II) { return II.isTerminator(); });
262}
263
264MachineBasicBlock::iterator
265MachineBasicBlock::getFirstNonDebugInstr(bool SkipPseudoOp) {
266 // Skip over begin-of-block dbg_value instructions.
267 return skipDebugInstructionsForward(It: begin(), End: end(), SkipPseudoOp);
268}
269
270MachineBasicBlock::iterator
271MachineBasicBlock::getLastNonDebugInstr(bool SkipPseudoOp) {
272 // Skip over end-of-block dbg_value instructions.
273 instr_iterator B = instr_begin(), I = instr_end();
274 while (I != B) {
275 --I;
276 // Return instruction that starts a bundle.
277 if (I->isDebugInstr() || I->isInsideBundle())
278 continue;
279 if (SkipPseudoOp && I->isPseudoProbe())
280 continue;
281 return I;
282 }
283 // The block is all debug values.
284 return end();
285}
286
287bool MachineBasicBlock::hasEHPadSuccessor() const {
288 for (const MachineBasicBlock *Succ : successors())
289 if (Succ->isEHPad())
290 return true;
291 return false;
292}
293
294bool MachineBasicBlock::isEntryBlock() const {
295 return getParent()->begin() == getIterator();
296}
297
298#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
299LLVM_DUMP_METHOD void MachineBasicBlock::dump() const {
300 print(dbgs());
301}
302#endif
303
304bool MachineBasicBlock::mayHaveInlineAsmBr() const {
305 for (const MachineBasicBlock *Succ : successors()) {
306 if (Succ->isInlineAsmBrIndirectTarget())
307 return true;
308 }
309 return false;
310}
311
312bool MachineBasicBlock::isLegalToHoistInto() const {
313 if (isReturnBlock() || hasEHPadSuccessor() || mayHaveInlineAsmBr())
314 return false;
315 return true;
316}
317
318bool MachineBasicBlock::hasName() const {
319 if (const BasicBlock *LBB = getBasicBlock())
320 return LBB->hasName();
321 return false;
322}
323
324StringRef MachineBasicBlock::getName() const {
325 if (const BasicBlock *LBB = getBasicBlock())
326 return LBB->getName();
327 else
328 return StringRef("", 0);
329}
330
331/// Return a hopefully unique identifier for this block.
332std::string MachineBasicBlock::getFullName() const {
333 std::string Name;
334 if (getParent())
335 Name = (getParent()->getName() + ":").str();
336 if (getBasicBlock())
337 Name += getBasicBlock()->getName();
338 else
339 Name += ("BB" + Twine(getNumber())).str();
340 return Name;
341}
342
343void MachineBasicBlock::print(raw_ostream &OS, const SlotIndexes *Indexes,
344 bool IsStandalone) const {
345 const MachineFunction *MF = getParent();
346 if (!MF) {
347 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
348 << " is null\n";
349 return;
350 }
351 const Function &F = MF->getFunction();
352 const Module *M = F.getParent();
353 ModuleSlotTracker MST(M);
354 MST.incorporateFunction(F);
355 print(OS, MST, Indexes, IsStandalone);
356}
357
358void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
359 const SlotIndexes *Indexes,
360 bool IsStandalone) const {
361 const MachineFunction *MF = getParent();
362 if (!MF) {
363 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
364 << " is null\n";
365 return;
366 }
367
368 if (Indexes && PrintSlotIndexes)
369 OS << Indexes->getMBBStartIdx(mbb: this) << '\t';
370
371 printName(os&: OS, printNameFlags: PrintNameIr | PrintNameAttributes, moduleSlotTracker: &MST);
372 OS << ":\n";
373
374 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
375 const MachineRegisterInfo &MRI = MF->getRegInfo();
376 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
377 bool HasLineAttributes = false;
378
379 // Print the preds of this block according to the CFG.
380 if (!pred_empty() && IsStandalone) {
381 if (Indexes) OS << '\t';
382 // Don't indent(2), align with previous line attributes.
383 OS << "; predecessors: ";
384 ListSeparator LS;
385 for (auto *Pred : predecessors())
386 OS << LS << printMBBReference(MBB: *Pred);
387 OS << '\n';
388 HasLineAttributes = true;
389 }
390
391 if (!succ_empty()) {
392 if (Indexes) OS << '\t';
393 // Print the successors
394 OS.indent(NumSpaces: 2) << "successors: ";
395 ListSeparator LS;
396 for (auto I = succ_begin(), E = succ_end(); I != E; ++I) {
397 OS << LS << printMBBReference(MBB: **I);
398 if (!Probs.empty())
399 OS << '('
400 << format(Fmt: "0x%08" PRIx32, Vals: getSuccProbability(Succ: I).getNumerator())
401 << ')';
402 }
403 if (!Probs.empty() && IsStandalone) {
404 // Print human readable probabilities as comments.
405 OS << "; ";
406 ListSeparator LS;
407 for (auto I = succ_begin(), E = succ_end(); I != E; ++I) {
408 const BranchProbability &BP = getSuccProbability(Succ: I);
409 OS << LS << printMBBReference(MBB: **I) << '('
410 << format(Fmt: "%.2f%%",
411 Vals: rint(x: ((double)BP.getNumerator() / BP.getDenominator()) *
412 100.0 * 100.0) /
413 100.0)
414 << ')';
415 }
416 }
417
418 OS << '\n';
419 HasLineAttributes = true;
420 }
421
422 if (!livein_empty() && MRI.tracksLiveness()) {
423 if (Indexes) OS << '\t';
424 OS.indent(NumSpaces: 2) << "liveins: ";
425
426 ListSeparator LS;
427 for (const auto &LI : liveins()) {
428 OS << LS << printReg(Reg: LI.PhysReg, TRI);
429 if (!LI.LaneMask.all())
430 OS << ":0x" << PrintLaneMask(LaneMask: LI.LaneMask);
431 }
432 HasLineAttributes = true;
433 }
434
435 if (HasLineAttributes)
436 OS << '\n';
437
438 bool IsInBundle = false;
439 for (const MachineInstr &MI : instrs()) {
440 if (Indexes && PrintSlotIndexes) {
441 if (Indexes->hasIndex(instr: MI))
442 OS << Indexes->getInstructionIndex(MI);
443 OS << '\t';
444 }
445
446 if (IsInBundle && !MI.isInsideBundle()) {
447 OS.indent(NumSpaces: 2) << "}\n";
448 IsInBundle = false;
449 }
450
451 OS.indent(NumSpaces: IsInBundle ? 4 : 2);
452 MI.print(OS, MST, IsStandalone, /*SkipOpers=*/false, /*SkipDebugLoc=*/false,
453 /*AddNewLine=*/false, TII: &TII);
454
455 if (!IsInBundle && MI.getFlag(Flag: MachineInstr::BundledSucc)) {
456 OS << " {";
457 IsInBundle = true;
458 }
459 OS << '\n';
460 }
461
462 if (IsInBundle)
463 OS.indent(NumSpaces: 2) << "}\n";
464
465 if (IrrLoopHeaderWeight && IsStandalone) {
466 if (Indexes) OS << '\t';
467 OS.indent(NumSpaces: 2) << "; Irreducible loop header weight: " << *IrrLoopHeaderWeight
468 << '\n';
469 }
470}
471
472/// Print the basic block's name as:
473///
474/// bb.{number}[.{ir-name}] [(attributes...)]
475///
476/// The {ir-name} is only printed when the \ref PrintNameIr flag is passed
477/// (which is the default). If the IR block has no name, it is identified
478/// numerically using the attribute syntax as "(%ir-block.{ir-slot})".
479///
480/// When the \ref PrintNameAttributes flag is passed, additional attributes
481/// of the block are printed when set.
482///
483/// \param printNameFlags Combination of \ref PrintNameFlag flags indicating
484/// the parts to print.
485/// \param moduleSlotTracker Optional ModuleSlotTracker. This method will
486/// incorporate its own tracker when necessary to
487/// determine the block's IR name.
488void MachineBasicBlock::printName(raw_ostream &os, unsigned printNameFlags,
489 ModuleSlotTracker *moduleSlotTracker) const {
490 os << "bb." << getNumber();
491 bool hasAttributes = false;
492
493 auto PrintBBRef = [&](const BasicBlock *bb) {
494 os << "%ir-block.";
495 if (bb->hasName()) {
496 os << bb->getName();
497 } else {
498 int slot = -1;
499
500 if (moduleSlotTracker) {
501 slot = moduleSlotTracker->getLocalSlot(V: bb);
502 } else if (bb->getParent()) {
503 ModuleSlotTracker tmpTracker(bb->getModule(), false);
504 tmpTracker.incorporateFunction(F: *bb->getParent());
505 slot = tmpTracker.getLocalSlot(V: bb);
506 }
507
508 if (slot == -1)
509 os << "<ir-block badref>";
510 else
511 os << slot;
512 }
513 };
514
515 if (printNameFlags & PrintNameIr) {
516 if (const auto *bb = getBasicBlock()) {
517 if (bb->hasName()) {
518 os << '.' << bb->getName();
519 } else {
520 hasAttributes = true;
521 os << " (";
522 PrintBBRef(bb);
523 }
524 }
525 }
526
527 if (printNameFlags & PrintNameAttributes) {
528 if (isMachineBlockAddressTaken()) {
529 os << (hasAttributes ? ", " : " (");
530 os << "machine-block-address-taken";
531 hasAttributes = true;
532 }
533 if (isIRBlockAddressTaken()) {
534 os << (hasAttributes ? ", " : " (");
535 os << "ir-block-address-taken ";
536 PrintBBRef(getAddressTakenIRBlock());
537 hasAttributes = true;
538 }
539 if (isEHPad()) {
540 os << (hasAttributes ? ", " : " (");
541 os << "landing-pad";
542 hasAttributes = true;
543 }
544 if (isInlineAsmBrIndirectTarget()) {
545 os << (hasAttributes ? ", " : " (");
546 os << "inlineasm-br-indirect-target";
547 hasAttributes = true;
548 }
549 if (isEHFuncletEntry()) {
550 os << (hasAttributes ? ", " : " (");
551 os << "ehfunclet-entry";
552 hasAttributes = true;
553 }
554 if (getAlignment() != Align(1)) {
555 os << (hasAttributes ? ", " : " (");
556 os << "align " << getAlignment().value();
557 hasAttributes = true;
558 }
559 if (getSectionID() != MBBSectionID(0)) {
560 os << (hasAttributes ? ", " : " (");
561 os << "bbsections ";
562 switch (getSectionID().Type) {
563 case MBBSectionID::SectionType::Exception:
564 os << "Exception";
565 break;
566 case MBBSectionID::SectionType::Cold:
567 os << "Cold";
568 break;
569 default:
570 os << getSectionID().Number;
571 }
572 hasAttributes = true;
573 }
574 if (getBBID().has_value()) {
575 os << (hasAttributes ? ", " : " (");
576 os << "bb_id " << getBBID()->BaseID;
577 if (getBBID()->CloneID != 0)
578 os << " " << getBBID()->CloneID;
579 hasAttributes = true;
580 }
581 if (CallFrameSize != 0) {
582 os << (hasAttributes ? ", " : " (");
583 os << "call-frame-size " << CallFrameSize;
584 hasAttributes = true;
585 }
586 }
587
588 if (hasAttributes)
589 os << ')';
590}
591
592void MachineBasicBlock::printAsOperand(raw_ostream &OS,
593 bool /*PrintType*/) const {
594 OS << '%';
595 printName(os&: OS, printNameFlags: 0);
596}
597
598void MachineBasicBlock::removeLiveIn(MCRegister Reg, LaneBitmask LaneMask) {
599 LiveInVector::iterator I = find_if(
600 Range&: LiveIns, P: [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
601 if (I == LiveIns.end())
602 return;
603
604 I->LaneMask &= ~LaneMask;
605 if (I->LaneMask.none())
606 LiveIns.erase(position: I);
607}
608
609MachineBasicBlock::livein_iterator
610MachineBasicBlock::removeLiveIn(MachineBasicBlock::livein_iterator I) {
611 // Get non-const version of iterator.
612 LiveInVector::iterator LI = LiveIns.begin() + (I - LiveIns.begin());
613 return LiveIns.erase(position: LI);
614}
615
616bool MachineBasicBlock::isLiveIn(MCRegister Reg, LaneBitmask LaneMask) const {
617 livein_iterator I = find_if(
618 Range: LiveIns, P: [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
619 return I != livein_end() && (I->LaneMask & LaneMask).any();
620}
621
622void MachineBasicBlock::sortUniqueLiveIns() {
623 llvm::sort(C&: LiveIns,
624 Comp: [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) {
625 return LI0.PhysReg < LI1.PhysReg;
626 });
627 // Liveins are sorted by physreg now we can merge their lanemasks.
628 LiveInVector::const_iterator I = LiveIns.begin();
629 LiveInVector::const_iterator J;
630 LiveInVector::iterator Out = LiveIns.begin();
631 for (; I != LiveIns.end(); ++Out, I = J) {
632 MCRegister PhysReg = I->PhysReg;
633 LaneBitmask LaneMask = I->LaneMask;
634 for (J = std::next(x: I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
635 LaneMask |= J->LaneMask;
636 Out->PhysReg = PhysReg;
637 Out->LaneMask = LaneMask;
638 }
639 LiveIns.erase(first: Out, last: LiveIns.end());
640}
641
642Register
643MachineBasicBlock::addLiveIn(MCRegister PhysReg, const TargetRegisterClass *RC) {
644 assert(getParent() && "MBB must be inserted in function");
645 assert(PhysReg.isPhysical() && "Expected physreg");
646 assert(RC && "Register class is required");
647 assert((isEHPad() || this == &getParent()->front()) &&
648 "Only the entry block and landing pads can have physreg live ins");
649
650 bool LiveIn = isLiveIn(Reg: PhysReg);
651 iterator I = SkipPHIsAndLabels(I: begin()), E = end();
652 MachineRegisterInfo &MRI = getParent()->getRegInfo();
653 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
654
655 // Look for an existing copy.
656 if (LiveIn)
657 for (;I != E && I->isCopy(); ++I)
658 if (I->getOperand(i: 1).getReg() == PhysReg) {
659 Register VirtReg = I->getOperand(i: 0).getReg();
660 if (!MRI.constrainRegClass(Reg: VirtReg, RC))
661 llvm_unreachable("Incompatible live-in register class.");
662 return VirtReg;
663 }
664
665 // No luck, create a virtual register.
666 Register VirtReg = MRI.createVirtualRegister(RegClass: RC);
667 BuildMI(BB&: *this, I, MIMD: DebugLoc(), MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: VirtReg)
668 .addReg(RegNo: PhysReg, flags: RegState::Kill);
669 if (!LiveIn)
670 addLiveIn(PhysReg);
671 return VirtReg;
672}
673
674void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
675 getParent()->splice(InsertPt: NewAfter->getIterator(), MBBI: getIterator());
676}
677
678void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) {
679 getParent()->splice(InsertPt: ++NewBefore->getIterator(), MBBI: getIterator());
680}
681
682static int findJumpTableIndex(const MachineBasicBlock &MBB) {
683 MachineBasicBlock::const_iterator TerminatorI = MBB.getFirstTerminator();
684 if (TerminatorI == MBB.end())
685 return -1;
686 const MachineInstr &Terminator = *TerminatorI;
687 const TargetInstrInfo *TII = MBB.getParent()->getSubtarget().getInstrInfo();
688 return TII->getJumpTableIndex(MI: Terminator);
689}
690
691void MachineBasicBlock::updateTerminator(
692 MachineBasicBlock *PreviousLayoutSuccessor) {
693 LLVM_DEBUG(dbgs() << "Updating terminators on " << printMBBReference(*this)
694 << "\n");
695
696 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
697 // A block with no successors has no concerns with fall-through edges.
698 if (this->succ_empty())
699 return;
700
701 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
702 SmallVector<MachineOperand, 4> Cond;
703 DebugLoc DL = findBranchDebugLoc();
704 bool B = TII->analyzeBranch(MBB&: *this, TBB, FBB, Cond);
705 (void) B;
706 assert(!B && "UpdateTerminators requires analyzable predecessors!");
707 if (Cond.empty()) {
708 if (TBB) {
709 // The block has an unconditional branch. If its successor is now its
710 // layout successor, delete the branch.
711 if (isLayoutSuccessor(MBB: TBB))
712 TII->removeBranch(MBB&: *this);
713 } else {
714 // The block has an unconditional fallthrough, or the end of the block is
715 // unreachable.
716
717 // Unfortunately, whether the end of the block is unreachable is not
718 // immediately obvious; we must fall back to checking the successor list,
719 // and assuming that if the passed in block is in the succesor list and
720 // not an EHPad, it must be the intended target.
721 if (!PreviousLayoutSuccessor || !isSuccessor(MBB: PreviousLayoutSuccessor) ||
722 PreviousLayoutSuccessor->isEHPad())
723 return;
724
725 // If the unconditional successor block is not the current layout
726 // successor, insert a branch to jump to it.
727 if (!isLayoutSuccessor(MBB: PreviousLayoutSuccessor))
728 TII->insertBranch(MBB&: *this, TBB: PreviousLayoutSuccessor, FBB: nullptr, Cond, DL);
729 }
730 return;
731 }
732
733 if (FBB) {
734 // The block has a non-fallthrough conditional branch. If one of its
735 // successors is its layout successor, rewrite it to a fallthrough
736 // conditional branch.
737 if (isLayoutSuccessor(MBB: TBB)) {
738 if (TII->reverseBranchCondition(Cond))
739 return;
740 TII->removeBranch(MBB&: *this);
741 TII->insertBranch(MBB&: *this, TBB: FBB, FBB: nullptr, Cond, DL);
742 } else if (isLayoutSuccessor(MBB: FBB)) {
743 TII->removeBranch(MBB&: *this);
744 TII->insertBranch(MBB&: *this, TBB, FBB: nullptr, Cond, DL);
745 }
746 return;
747 }
748
749 // We now know we're going to fallthrough to PreviousLayoutSuccessor.
750 assert(PreviousLayoutSuccessor);
751 assert(!PreviousLayoutSuccessor->isEHPad());
752 assert(isSuccessor(PreviousLayoutSuccessor));
753
754 if (PreviousLayoutSuccessor == TBB) {
755 // We had a fallthrough to the same basic block as the conditional jump
756 // targets. Remove the conditional jump, leaving an unconditional
757 // fallthrough or an unconditional jump.
758 TII->removeBranch(MBB&: *this);
759 if (!isLayoutSuccessor(MBB: TBB)) {
760 Cond.clear();
761 TII->insertBranch(MBB&: *this, TBB, FBB: nullptr, Cond, DL);
762 }
763 return;
764 }
765
766 // The block has a fallthrough conditional branch.
767 if (isLayoutSuccessor(MBB: TBB)) {
768 if (TII->reverseBranchCondition(Cond)) {
769 // We can't reverse the condition, add an unconditional branch.
770 Cond.clear();
771 TII->insertBranch(MBB&: *this, TBB: PreviousLayoutSuccessor, FBB: nullptr, Cond, DL);
772 return;
773 }
774 TII->removeBranch(MBB&: *this);
775 TII->insertBranch(MBB&: *this, TBB: PreviousLayoutSuccessor, FBB: nullptr, Cond, DL);
776 } else if (!isLayoutSuccessor(MBB: PreviousLayoutSuccessor)) {
777 TII->removeBranch(MBB&: *this);
778 TII->insertBranch(MBB&: *this, TBB, FBB: PreviousLayoutSuccessor, Cond, DL);
779 }
780}
781
782void MachineBasicBlock::validateSuccProbs() const {
783#ifndef NDEBUG
784 int64_t Sum = 0;
785 for (auto Prob : Probs)
786 Sum += Prob.getNumerator();
787 // Due to precision issue, we assume that the sum of probabilities is one if
788 // the difference between the sum of their numerators and the denominator is
789 // no greater than the number of successors.
790 assert((uint64_t)std::abs(Sum - BranchProbability::getDenominator()) <=
791 Probs.size() &&
792 "The sum of successors's probabilities exceeds one.");
793#endif // NDEBUG
794}
795
796void MachineBasicBlock::addSuccessor(MachineBasicBlock *Succ,
797 BranchProbability Prob) {
798 // Probability list is either empty (if successor list isn't empty, this means
799 // disabled optimization) or has the same size as successor list.
800 if (!(Probs.empty() && !Successors.empty()))
801 Probs.push_back(x: Prob);
802 Successors.push_back(Elt: Succ);
803 Succ->addPredecessor(Pred: this);
804}
805
806void MachineBasicBlock::addSuccessorWithoutProb(MachineBasicBlock *Succ) {
807 // We need to make sure probability list is either empty or has the same size
808 // of successor list. When this function is called, we can safely delete all
809 // probability in the list.
810 Probs.clear();
811 Successors.push_back(Elt: Succ);
812 Succ->addPredecessor(Pred: this);
813}
814
815void MachineBasicBlock::splitSuccessor(MachineBasicBlock *Old,
816 MachineBasicBlock *New,
817 bool NormalizeSuccProbs) {
818 succ_iterator OldI = llvm::find(Range: successors(), Val: Old);
819 assert(OldI != succ_end() && "Old is not a successor of this block!");
820 assert(!llvm::is_contained(successors(), New) &&
821 "New is already a successor of this block!");
822
823 // Add a new successor with equal probability as the original one. Note
824 // that we directly copy the probability using the iterator rather than
825 // getting a potentially synthetic probability computed when unknown. This
826 // preserves the probabilities as-is and then we can renormalize them and
827 // query them effectively afterward.
828 addSuccessor(Succ: New, Prob: Probs.empty() ? BranchProbability::getUnknown()
829 : *getProbabilityIterator(I: OldI));
830 if (NormalizeSuccProbs)
831 normalizeSuccProbs();
832}
833
834void MachineBasicBlock::removeSuccessor(MachineBasicBlock *Succ,
835 bool NormalizeSuccProbs) {
836 succ_iterator I = find(Range&: Successors, Val: Succ);
837 removeSuccessor(I, NormalizeSuccProbs);
838}
839
840MachineBasicBlock::succ_iterator
841MachineBasicBlock::removeSuccessor(succ_iterator I, bool NormalizeSuccProbs) {
842 assert(I != Successors.end() && "Not a current successor!");
843
844 // If probability list is empty it means we don't use it (disabled
845 // optimization).
846 if (!Probs.empty()) {
847 probability_iterator WI = getProbabilityIterator(I);
848 Probs.erase(position: WI);
849 if (NormalizeSuccProbs)
850 normalizeSuccProbs();
851 }
852
853 (*I)->removePredecessor(Pred: this);
854 return Successors.erase(CI: I);
855}
856
857void MachineBasicBlock::replaceSuccessor(MachineBasicBlock *Old,
858 MachineBasicBlock *New) {
859 if (Old == New)
860 return;
861
862 succ_iterator E = succ_end();
863 succ_iterator NewI = E;
864 succ_iterator OldI = E;
865 for (succ_iterator I = succ_begin(); I != E; ++I) {
866 if (*I == Old) {
867 OldI = I;
868 if (NewI != E)
869 break;
870 }
871 if (*I == New) {
872 NewI = I;
873 if (OldI != E)
874 break;
875 }
876 }
877 assert(OldI != E && "Old is not a successor of this block");
878
879 // If New isn't already a successor, let it take Old's place.
880 if (NewI == E) {
881 Old->removePredecessor(Pred: this);
882 New->addPredecessor(Pred: this);
883 *OldI = New;
884 return;
885 }
886
887 // New is already a successor.
888 // Update its probability instead of adding a duplicate edge.
889 if (!Probs.empty()) {
890 auto ProbIter = getProbabilityIterator(I: NewI);
891 if (!ProbIter->isUnknown())
892 *ProbIter += *getProbabilityIterator(I: OldI);
893 }
894 removeSuccessor(I: OldI);
895}
896
897void MachineBasicBlock::copySuccessor(const MachineBasicBlock *Orig,
898 succ_iterator I) {
899 if (!Orig->Probs.empty())
900 addSuccessor(Succ: *I, Prob: Orig->getSuccProbability(Succ: I));
901 else
902 addSuccessorWithoutProb(Succ: *I);
903}
904
905void MachineBasicBlock::addPredecessor(MachineBasicBlock *Pred) {
906 Predecessors.push_back(Elt: Pred);
907}
908
909void MachineBasicBlock::removePredecessor(MachineBasicBlock *Pred) {
910 pred_iterator I = find(Range&: Predecessors, Val: Pred);
911 assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
912 Predecessors.erase(CI: I);
913}
914
915void MachineBasicBlock::transferSuccessors(MachineBasicBlock *FromMBB) {
916 if (this == FromMBB)
917 return;
918
919 while (!FromMBB->succ_empty()) {
920 MachineBasicBlock *Succ = *FromMBB->succ_begin();
921
922 // If probability list is empty it means we don't use it (disabled
923 // optimization).
924 if (!FromMBB->Probs.empty()) {
925 auto Prob = *FromMBB->Probs.begin();
926 addSuccessor(Succ, Prob);
927 } else
928 addSuccessorWithoutProb(Succ);
929
930 FromMBB->removeSuccessor(Succ);
931 }
932}
933
934void
935MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB) {
936 if (this == FromMBB)
937 return;
938
939 while (!FromMBB->succ_empty()) {
940 MachineBasicBlock *Succ = *FromMBB->succ_begin();
941 if (!FromMBB->Probs.empty()) {
942 auto Prob = *FromMBB->Probs.begin();
943 addSuccessor(Succ, Prob);
944 } else
945 addSuccessorWithoutProb(Succ);
946 FromMBB->removeSuccessor(Succ);
947
948 // Fix up any PHI nodes in the successor.
949 Succ->replacePhiUsesWith(Old: FromMBB, New: this);
950 }
951 normalizeSuccProbs();
952}
953
954bool MachineBasicBlock::isPredecessor(const MachineBasicBlock *MBB) const {
955 return is_contained(Range: predecessors(), Element: MBB);
956}
957
958bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
959 return is_contained(Range: successors(), Element: MBB);
960}
961
962bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const {
963 MachineFunction::const_iterator I(this);
964 return std::next(x: I) == MachineFunction::const_iterator(MBB);
965}
966
967const MachineBasicBlock *MachineBasicBlock::getSingleSuccessor() const {
968 return Successors.size() == 1 ? Successors[0] : nullptr;
969}
970
971const MachineBasicBlock *MachineBasicBlock::getSinglePredecessor() const {
972 return Predecessors.size() == 1 ? Predecessors[0] : nullptr;
973}
974
975MachineBasicBlock *MachineBasicBlock::getFallThrough(bool JumpToFallThrough) {
976 MachineFunction::iterator Fallthrough = getIterator();
977 ++Fallthrough;
978 // If FallthroughBlock is off the end of the function, it can't fall through.
979 if (Fallthrough == getParent()->end())
980 return nullptr;
981
982 // If FallthroughBlock isn't a successor, no fallthrough is possible.
983 if (!isSuccessor(MBB: &*Fallthrough))
984 return nullptr;
985
986 // Analyze the branches, if any, at the end of the block.
987 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
988 SmallVector<MachineOperand, 4> Cond;
989 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
990 if (TII->analyzeBranch(MBB&: *this, TBB, FBB, Cond)) {
991 // If we couldn't analyze the branch, examine the last instruction.
992 // If the block doesn't end in a known control barrier, assume fallthrough
993 // is possible. The isPredicated check is needed because this code can be
994 // called during IfConversion, where an instruction which is normally a
995 // Barrier is predicated and thus no longer an actual control barrier.
996 return (empty() || !back().isBarrier() || TII->isPredicated(MI: back()))
997 ? &*Fallthrough
998 : nullptr;
999 }
1000
1001 // If there is no branch, control always falls through.
1002 if (!TBB) return &*Fallthrough;
1003
1004 // If there is some explicit branch to the fallthrough block, it can obviously
1005 // reach, even though the branch should get folded to fall through implicitly.
1006 if (JumpToFallThrough && (MachineFunction::iterator(TBB) == Fallthrough ||
1007 MachineFunction::iterator(FBB) == Fallthrough))
1008 return &*Fallthrough;
1009
1010 // If it's an unconditional branch to some block not the fall through, it
1011 // doesn't fall through.
1012 if (Cond.empty()) return nullptr;
1013
1014 // Otherwise, if it is conditional and has no explicit false block, it falls
1015 // through.
1016 return (FBB == nullptr) ? &*Fallthrough : nullptr;
1017}
1018
1019bool MachineBasicBlock::canFallThrough() {
1020 return getFallThrough() != nullptr;
1021}
1022
1023MachineBasicBlock *MachineBasicBlock::splitAt(MachineInstr &MI,
1024 bool UpdateLiveIns,
1025 LiveIntervals *LIS) {
1026 MachineBasicBlock::iterator SplitPoint(&MI);
1027 ++SplitPoint;
1028
1029 if (SplitPoint == end()) {
1030 // Don't bother with a new block.
1031 return this;
1032 }
1033
1034 MachineFunction *MF = getParent();
1035
1036 LivePhysRegs LiveRegs;
1037 if (UpdateLiveIns) {
1038 // Make sure we add any physregs we define in the block as liveins to the
1039 // new block.
1040 MachineBasicBlock::iterator Prev(&MI);
1041 LiveRegs.init(TRI: *MF->getSubtarget().getRegisterInfo());
1042 LiveRegs.addLiveOuts(MBB: *this);
1043 for (auto I = rbegin(), E = Prev.getReverse(); I != E; ++I)
1044 LiveRegs.stepBackward(MI: *I);
1045 }
1046
1047 MachineBasicBlock *SplitBB = MF->CreateMachineBasicBlock(BB: getBasicBlock());
1048
1049 MF->insert(MBBI: ++MachineFunction::iterator(this), MBB: SplitBB);
1050 SplitBB->splice(Where: SplitBB->begin(), Other: this, From: SplitPoint, To: end());
1051
1052 SplitBB->transferSuccessorsAndUpdatePHIs(FromMBB: this);
1053 addSuccessor(Succ: SplitBB);
1054
1055 if (UpdateLiveIns)
1056 addLiveIns(MBB&: *SplitBB, LiveRegs);
1057
1058 if (LIS)
1059 LIS->insertMBBInMaps(MBB: SplitBB);
1060
1061 return SplitBB;
1062}
1063
1064// Returns `true` if there are possibly other users of the jump table at
1065// `JumpTableIndex` except for the ones in `IgnoreMBB`.
1066static bool jumpTableHasOtherUses(const MachineFunction &MF,
1067 const MachineBasicBlock &IgnoreMBB,
1068 int JumpTableIndex) {
1069 assert(JumpTableIndex >= 0 && "need valid index");
1070 const MachineJumpTableInfo &MJTI = *MF.getJumpTableInfo();
1071 const MachineJumpTableEntry &MJTE = MJTI.getJumpTables()[JumpTableIndex];
1072 // Take any basic block from the table; every user of the jump table must
1073 // show up in the predecessor list.
1074 const MachineBasicBlock *MBB = nullptr;
1075 for (MachineBasicBlock *B : MJTE.MBBs) {
1076 if (B != nullptr) {
1077 MBB = B;
1078 break;
1079 }
1080 }
1081 if (MBB == nullptr)
1082 return true; // can't rule out other users if there isn't any block.
1083 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1084 SmallVector<MachineOperand, 4> Cond;
1085 for (MachineBasicBlock *Pred : MBB->predecessors()) {
1086 if (Pred == &IgnoreMBB)
1087 continue;
1088 MachineBasicBlock *DummyT = nullptr;
1089 MachineBasicBlock *DummyF = nullptr;
1090 Cond.clear();
1091 if (!TII.analyzeBranch(MBB&: *Pred, TBB&: DummyT, FBB&: DummyF, Cond,
1092 /*AllowModify=*/false)) {
1093 // analyzable direct jump
1094 continue;
1095 }
1096 int PredJTI = findJumpTableIndex(MBB: *Pred);
1097 if (PredJTI >= 0) {
1098 if (PredJTI == JumpTableIndex)
1099 return true;
1100 continue;
1101 }
1102 // Be conservative for unanalyzable jumps.
1103 return true;
1104 }
1105 return false;
1106}
1107
1108class SlotIndexUpdateDelegate : public MachineFunction::Delegate {
1109private:
1110 MachineFunction &MF;
1111 SlotIndexes *Indexes;
1112 SmallSetVector<MachineInstr *, 2> Insertions;
1113
1114public:
1115 SlotIndexUpdateDelegate(MachineFunction &MF, SlotIndexes *Indexes)
1116 : MF(MF), Indexes(Indexes) {
1117 MF.setDelegate(this);
1118 }
1119
1120 ~SlotIndexUpdateDelegate() {
1121 MF.resetDelegate(delegate: this);
1122 for (auto MI : Insertions)
1123 Indexes->insertMachineInstrInMaps(MI&: *MI);
1124 }
1125
1126 void MF_HandleInsertion(MachineInstr &MI) override {
1127 // This is called before MI is inserted into block so defer index update.
1128 if (Indexes)
1129 Insertions.insert(X: &MI);
1130 }
1131
1132 void MF_HandleRemoval(MachineInstr &MI) override {
1133 if (Indexes && !Insertions.remove(X: &MI))
1134 Indexes->removeMachineInstrFromMaps(MI);
1135 }
1136};
1137
1138MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
1139 MachineBasicBlock *Succ, Pass *P, MachineFunctionAnalysisManager *MFAM,
1140 std::vector<SparseBitVector<>> *LiveInSets, MachineDomTreeUpdater *MDTU) {
1141#define GET_RESULT(RESULT, GETTER, INFIX) \
1142 [MF, P, MFAM]() { \
1143 if (P) { \
1144 auto *Wrapper = P->getAnalysisIfAvailable<RESULT##INFIX##WrapperPass>(); \
1145 return Wrapper ? &Wrapper->GETTER() : nullptr; \
1146 } \
1147 return MFAM->getCachedResult<RESULT##Analysis>(*MF); \
1148 }()
1149
1150 assert((P || MFAM) && "Need a way to get analysis results!");
1151 MachineFunction *MF = getParent();
1152 LiveIntervals *LIS = GET_RESULT(LiveIntervals, getLIS, );
1153 SlotIndexes *Indexes = GET_RESULT(SlotIndexes, getSI, );
1154 LiveVariables *LV = GET_RESULT(LiveVariables, getLV, );
1155 MachineLoopInfo *MLI = GET_RESULT(MachineLoop, getLI, Info);
1156 return SplitCriticalEdge(Succ, Analyses: {.LIS: LIS, .SI: Indexes, .LV: LV, .MLI: MLI}, LiveInSets, MDTU);
1157#undef GET_RESULT
1158}
1159
1160MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
1161 MachineBasicBlock *Succ, const SplitCriticalEdgeAnalyses &Analyses,
1162 std::vector<SparseBitVector<>> *LiveInSets, MachineDomTreeUpdater *MDTU) {
1163 if (!canSplitCriticalEdge(Succ))
1164 return nullptr;
1165
1166 MachineFunction *MF = getParent();
1167 MachineBasicBlock *PrevFallthrough = getNextNode();
1168
1169 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
1170 NMBB->setCallFrameSize(Succ->getCallFrameSize());
1171
1172 // Is there an indirect jump with jump table?
1173 bool ChangedIndirectJump = false;
1174 int JTI = findJumpTableIndex(MBB: *this);
1175 if (JTI >= 0) {
1176 MachineJumpTableInfo &MJTI = *MF->getJumpTableInfo();
1177 MJTI.ReplaceMBBInJumpTable(Idx: JTI, Old: Succ, New: NMBB);
1178 ChangedIndirectJump = true;
1179 }
1180
1181 MF->insert(MBBI: std::next(x: MachineFunction::iterator(this)), MBB: NMBB);
1182 LLVM_DEBUG(dbgs() << "Splitting critical edge: " << printMBBReference(*this)
1183 << " -- " << printMBBReference(*NMBB) << " -- "
1184 << printMBBReference(*Succ) << '\n');
1185 auto *LIS = Analyses.LIS;
1186 if (LIS)
1187 LIS->insertMBBInMaps(MBB: NMBB);
1188 else if (Analyses.SI)
1189 Analyses.SI->insertMBBInMaps(mbb: NMBB);
1190
1191 // On some targets like Mips, branches may kill virtual registers. Make sure
1192 // that LiveVariables is properly updated after updateTerminator replaces the
1193 // terminators.
1194 auto *LV = Analyses.LV;
1195 // Collect a list of virtual registers killed by the terminators.
1196 SmallVector<Register, 4> KilledRegs;
1197 if (LV)
1198 for (MachineInstr &MI :
1199 llvm::make_range(x: getFirstInstrTerminator(), y: instr_end())) {
1200 for (MachineOperand &MO : MI.all_uses()) {
1201 if (MO.getReg() == 0 || !MO.isKill() || MO.isUndef())
1202 continue;
1203 Register Reg = MO.getReg();
1204 if (Reg.isPhysical() || LV->getVarInfo(Reg).removeKill(MI)) {
1205 KilledRegs.push_back(Elt: Reg);
1206 LLVM_DEBUG(dbgs() << "Removing terminator kill: " << MI);
1207 MO.setIsKill(false);
1208 }
1209 }
1210 }
1211
1212 SmallVector<Register, 4> UsedRegs;
1213 if (LIS) {
1214 for (MachineInstr &MI :
1215 llvm::make_range(x: getFirstInstrTerminator(), y: instr_end())) {
1216 for (const MachineOperand &MO : MI.operands()) {
1217 if (!MO.isReg() || MO.getReg() == 0)
1218 continue;
1219
1220 Register Reg = MO.getReg();
1221 if (!is_contained(Range&: UsedRegs, Element: Reg))
1222 UsedRegs.push_back(Elt: Reg);
1223 }
1224 }
1225 }
1226
1227 ReplaceUsesOfBlockWith(Old: Succ, New: NMBB);
1228
1229 // Since we replaced all uses of Succ with NMBB, that should also be treated
1230 // as the fallthrough successor
1231 if (Succ == PrevFallthrough)
1232 PrevFallthrough = NMBB;
1233 auto *Indexes = Analyses.SI;
1234 if (!ChangedIndirectJump) {
1235 SlotIndexUpdateDelegate SlotUpdater(*MF, Indexes);
1236 updateTerminator(PreviousLayoutSuccessor: PrevFallthrough);
1237 }
1238
1239 // Insert unconditional "jump Succ" instruction in NMBB if necessary.
1240 NMBB->addSuccessor(Succ);
1241 if (!NMBB->isLayoutSuccessor(MBB: Succ)) {
1242 SlotIndexUpdateDelegate SlotUpdater(*MF, Indexes);
1243 SmallVector<MachineOperand, 4> Cond;
1244 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
1245
1246 // In original 'this' BB, there must be a branch instruction targeting at
1247 // Succ. We can not find it out since currently getBranchDestBlock was not
1248 // implemented for all targets. However, if the merged DL has column or line
1249 // number, the scope and non-zero column and line number is same with that
1250 // branch instruction so we can safely use it.
1251 DebugLoc DL, MergedDL = findBranchDebugLoc();
1252 if (MergedDL && (MergedDL.getLine() || MergedDL.getCol()))
1253 DL = MergedDL;
1254 TII->insertBranch(MBB&: *NMBB, TBB: Succ, FBB: nullptr, Cond, DL);
1255 }
1256
1257 // Fix PHI nodes in Succ so they refer to NMBB instead of this.
1258 Succ->replacePhiUsesWith(Old: this, New: NMBB);
1259
1260 // Inherit live-ins from the successor
1261 for (const auto &LI : Succ->liveins())
1262 NMBB->addLiveIn(RegMaskPair: LI);
1263
1264 // Update LiveVariables.
1265 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1266 if (LV) {
1267 // Restore kills of virtual registers that were killed by the terminators.
1268 while (!KilledRegs.empty()) {
1269 Register Reg = KilledRegs.pop_back_val();
1270 for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
1271 if (!(--I)->addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, /* AddIfNotFound= */ false))
1272 continue;
1273 if (Reg.isVirtual())
1274 LV->getVarInfo(Reg).Kills.push_back(x: &*I);
1275 LLVM_DEBUG(dbgs() << "Restored terminator kill: " << *I);
1276 break;
1277 }
1278 }
1279 // Update relevant live-through information.
1280 if (LiveInSets != nullptr)
1281 LV->addNewBlock(BB: NMBB, DomBB: this, SuccBB: Succ, LiveInSets&: *LiveInSets);
1282 else
1283 LV->addNewBlock(BB: NMBB, DomBB: this, SuccBB: Succ);
1284 }
1285
1286 if (LIS) {
1287 // After splitting the edge and updating SlotIndexes, live intervals may be
1288 // in one of two situations, depending on whether this block was the last in
1289 // the function. If the original block was the last in the function, all
1290 // live intervals will end prior to the beginning of the new split block. If
1291 // the original block was not at the end of the function, all live intervals
1292 // will extend to the end of the new split block.
1293
1294 bool isLastMBB =
1295 std::next(x: MachineFunction::iterator(NMBB)) == getParent()->end();
1296
1297 SlotIndex StartIndex = Indexes->getMBBEndIdx(mbb: this);
1298 SlotIndex PrevIndex = StartIndex.getPrevSlot();
1299 SlotIndex EndIndex = Indexes->getMBBEndIdx(mbb: NMBB);
1300
1301 // Find the registers used from NMBB in PHIs in Succ.
1302 SmallSet<Register, 8> PHISrcRegs;
1303 for (MachineBasicBlock::instr_iterator
1304 I = Succ->instr_begin(), E = Succ->instr_end();
1305 I != E && I->isPHI(); ++I) {
1306 for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
1307 if (I->getOperand(i: ni+1).getMBB() == NMBB) {
1308 MachineOperand &MO = I->getOperand(i: ni);
1309 Register Reg = MO.getReg();
1310 PHISrcRegs.insert(V: Reg);
1311 if (MO.isUndef())
1312 continue;
1313
1314 LiveInterval &LI = LIS->getInterval(Reg);
1315 VNInfo *VNI = LI.getVNInfoAt(Idx: PrevIndex);
1316 assert(VNI &&
1317 "PHI sources should be live out of their predecessors.");
1318 LI.addSegment(S: LiveInterval::Segment(StartIndex, EndIndex, VNI));
1319 for (auto &SR : LI.subranges())
1320 SR.addSegment(S: LiveInterval::Segment(StartIndex, EndIndex, VNI));
1321 }
1322 }
1323 }
1324
1325 MachineRegisterInfo *MRI = &getParent()->getRegInfo();
1326 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1327 Register Reg = Register::index2VirtReg(Index: i);
1328 if (PHISrcRegs.count(V: Reg) || !LIS->hasInterval(Reg))
1329 continue;
1330
1331 LiveInterval &LI = LIS->getInterval(Reg);
1332 if (!LI.liveAt(index: PrevIndex))
1333 continue;
1334
1335 bool isLiveOut = LI.liveAt(index: LIS->getMBBStartIdx(mbb: Succ));
1336 if (isLiveOut && isLastMBB) {
1337 VNInfo *VNI = LI.getVNInfoAt(Idx: PrevIndex);
1338 assert(VNI && "LiveInterval should have VNInfo where it is live.");
1339 LI.addSegment(S: LiveInterval::Segment(StartIndex, EndIndex, VNI));
1340 // Update subranges with live values
1341 for (auto &SR : LI.subranges()) {
1342 VNInfo *VNI = SR.getVNInfoAt(Idx: PrevIndex);
1343 if (VNI)
1344 SR.addSegment(S: LiveInterval::Segment(StartIndex, EndIndex, VNI));
1345 }
1346 } else if (!isLiveOut && !isLastMBB) {
1347 LI.removeSegment(Start: StartIndex, End: EndIndex);
1348 for (auto &SR : LI.subranges())
1349 SR.removeSegment(Start: StartIndex, End: EndIndex);
1350 }
1351 }
1352
1353 // Update all intervals for registers whose uses may have been modified by
1354 // updateTerminator().
1355 LIS->repairIntervalsInRange(MBB: this, Begin: getFirstTerminator(), End: end(), OrigRegs: UsedRegs);
1356 }
1357
1358 if (MDTU)
1359 MDTU->splitCriticalEdge(FromBB: this, ToBB: Succ, NewBB: NMBB);
1360
1361 if (MachineLoopInfo *MLI = Analyses.MLI)
1362 if (MachineLoop *TIL = MLI->getLoopFor(BB: this)) {
1363 // If one or the other blocks were not in a loop, the new block is not
1364 // either, and thus LI doesn't need to be updated.
1365 if (MachineLoop *DestLoop = MLI->getLoopFor(BB: Succ)) {
1366 if (TIL == DestLoop) {
1367 // Both in the same loop, the NMBB joins loop.
1368 DestLoop->addBasicBlockToLoop(NewBB: NMBB, LI&: *MLI);
1369 } else if (TIL->contains(L: DestLoop)) {
1370 // Edge from an outer loop to an inner loop. Add to the outer loop.
1371 TIL->addBasicBlockToLoop(NewBB: NMBB, LI&: *MLI);
1372 } else if (DestLoop->contains(L: TIL)) {
1373 // Edge from an inner loop to an outer loop. Add to the outer loop.
1374 DestLoop->addBasicBlockToLoop(NewBB: NMBB, LI&: *MLI);
1375 } else {
1376 // Edge from two loops with no containment relation. Because these
1377 // are natural loops, we know that the destination block must be the
1378 // header of its loop (adding a branch into a loop elsewhere would
1379 // create an irreducible loop).
1380 assert(DestLoop->getHeader() == Succ &&
1381 "Should not create irreducible loops!");
1382 if (MachineLoop *P = DestLoop->getParentLoop())
1383 P->addBasicBlockToLoop(NewBB: NMBB, LI&: *MLI);
1384 }
1385 }
1386 }
1387
1388 return NMBB;
1389}
1390
1391bool MachineBasicBlock::canSplitCriticalEdge(
1392 const MachineBasicBlock *Succ) const {
1393 // Splitting the critical edge to a landing pad block is non-trivial. Don't do
1394 // it in this generic function.
1395 if (Succ->isEHPad())
1396 return false;
1397
1398 // Splitting the critical edge to a callbr's indirect block isn't advised.
1399 // Don't do it in this generic function.
1400 if (Succ->isInlineAsmBrIndirectTarget())
1401 return false;
1402
1403 const MachineFunction *MF = getParent();
1404 // Performance might be harmed on HW that implements branching using exec mask
1405 // where both sides of the branches are always executed.
1406 if (MF->getTarget().requiresStructuredCFG())
1407 return false;
1408
1409 // Do we have an Indirect jump with a jumptable that we can rewrite?
1410 int JTI = findJumpTableIndex(MBB: *this);
1411 if (JTI >= 0 && !jumpTableHasOtherUses(MF: *MF, IgnoreMBB: *this, JumpTableIndex: JTI))
1412 return true;
1413
1414 // We may need to update this's terminator, but we can't do that if
1415 // analyzeBranch fails.
1416 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1417 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
1418 SmallVector<MachineOperand, 4> Cond;
1419 // AnalyzeBanch should modify this, since we did not allow modification.
1420 if (TII->analyzeBranch(MBB&: *const_cast<MachineBasicBlock *>(this), TBB, FBB, Cond,
1421 /*AllowModify*/ false))
1422 return false;
1423
1424 // Avoid bugpoint weirdness: A block may end with a conditional branch but
1425 // jumps to the same MBB is either case. We have duplicate CFG edges in that
1426 // case that we can't handle. Since this never happens in properly optimized
1427 // code, just skip those edges.
1428 if (TBB && TBB == FBB) {
1429 LLVM_DEBUG(dbgs() << "Won't split critical edge after degenerate "
1430 << printMBBReference(*this) << '\n');
1431 return false;
1432 }
1433 return true;
1434}
1435
1436/// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
1437/// neighboring instructions so the bundle won't be broken by removing MI.
1438static void unbundleSingleMI(MachineInstr *MI) {
1439 // Removing the first instruction in a bundle.
1440 if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
1441 MI->unbundleFromSucc();
1442 // Removing the last instruction in a bundle.
1443 if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
1444 MI->unbundleFromPred();
1445 // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
1446 // are already fine.
1447}
1448
1449MachineBasicBlock::instr_iterator
1450MachineBasicBlock::erase(MachineBasicBlock::instr_iterator I) {
1451 unbundleSingleMI(MI: &*I);
1452 return Insts.erase(where: I);
1453}
1454
1455MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) {
1456 unbundleSingleMI(MI);
1457 MI->clearFlag(Flag: MachineInstr::BundledPred);
1458 MI->clearFlag(Flag: MachineInstr::BundledSucc);
1459 return Insts.remove(IT: MI);
1460}
1461
1462MachineBasicBlock::instr_iterator
1463MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) {
1464 assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
1465 "Cannot insert instruction with bundle flags");
1466 // Set the bundle flags when inserting inside a bundle.
1467 if (I != instr_end() && I->isBundledWithPred()) {
1468 MI->setFlag(MachineInstr::BundledPred);
1469 MI->setFlag(MachineInstr::BundledSucc);
1470 }
1471 return Insts.insert(where: I, New: MI);
1472}
1473
1474/// This method unlinks 'this' from the containing function, and returns it, but
1475/// does not delete it.
1476MachineBasicBlock *MachineBasicBlock::removeFromParent() {
1477 assert(getParent() && "Not embedded in a function!");
1478 getParent()->remove(MBBI: this);
1479 return this;
1480}
1481
1482/// This method unlinks 'this' from the containing function, and deletes it.
1483void MachineBasicBlock::eraseFromParent() {
1484 assert(getParent() && "Not embedded in a function!");
1485 getParent()->erase(MBBI: this);
1486}
1487
1488/// Given a machine basic block that branched to 'Old', change the code and CFG
1489/// so that it branches to 'New' instead.
1490void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
1491 MachineBasicBlock *New) {
1492 assert(Old != New && "Cannot replace self with self!");
1493
1494 MachineBasicBlock::instr_iterator I = instr_end();
1495 while (I != instr_begin()) {
1496 --I;
1497 if (!I->isTerminator()) break;
1498
1499 // Scan the operands of this machine instruction, replacing any uses of Old
1500 // with New.
1501 for (MachineOperand &MO : I->operands())
1502 if (MO.isMBB() && MO.getMBB() == Old)
1503 MO.setMBB(New);
1504 }
1505
1506 // Update the successor information.
1507 replaceSuccessor(Old, New);
1508}
1509
1510void MachineBasicBlock::replacePhiUsesWith(MachineBasicBlock *Old,
1511 MachineBasicBlock *New) {
1512 for (MachineInstr &MI : phis())
1513 for (unsigned i = 2, e = MI.getNumOperands() + 1; i != e; i += 2) {
1514 MachineOperand &MO = MI.getOperand(i);
1515 if (MO.getMBB() == Old)
1516 MO.setMBB(New);
1517 }
1518}
1519
1520/// Find the next valid DebugLoc starting at MBBI, skipping any debug
1521/// instructions. Return UnknownLoc if there is none.
1522DebugLoc
1523MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
1524 // Skip debug declarations, we don't want a DebugLoc from them.
1525 MBBI = skipDebugInstructionsForward(It: MBBI, End: instr_end());
1526 if (MBBI != instr_end())
1527 return MBBI->getDebugLoc();
1528 return {};
1529}
1530
1531DebugLoc MachineBasicBlock::rfindDebugLoc(reverse_instr_iterator MBBI) {
1532 if (MBBI == instr_rend())
1533 return findDebugLoc(MBBI: instr_begin());
1534 // Skip debug declarations, we don't want a DebugLoc from them.
1535 MBBI = skipDebugInstructionsBackward(It: MBBI, Begin: instr_rbegin());
1536 if (!MBBI->isDebugInstr())
1537 return MBBI->getDebugLoc();
1538 return {};
1539}
1540
1541/// Find the previous valid DebugLoc preceding MBBI, skipping any debug
1542/// instructions. Return UnknownLoc if there is none.
1543DebugLoc MachineBasicBlock::findPrevDebugLoc(instr_iterator MBBI) {
1544 if (MBBI == instr_begin())
1545 return {};
1546 // Skip debug instructions, we don't want a DebugLoc from them.
1547 MBBI = prev_nodbg(It: MBBI, Begin: instr_begin());
1548 if (!MBBI->isDebugInstr())
1549 return MBBI->getDebugLoc();
1550 return {};
1551}
1552
1553DebugLoc MachineBasicBlock::rfindPrevDebugLoc(reverse_instr_iterator MBBI) {
1554 if (MBBI == instr_rend())
1555 return {};
1556 // Skip debug declarations, we don't want a DebugLoc from them.
1557 MBBI = next_nodbg(It: MBBI, End: instr_rend());
1558 if (MBBI != instr_rend())
1559 return MBBI->getDebugLoc();
1560 return {};
1561}
1562
1563/// Find and return the merged DebugLoc of the branch instructions of the block.
1564/// Return UnknownLoc if there is none.
1565DebugLoc
1566MachineBasicBlock::findBranchDebugLoc() {
1567 DebugLoc DL;
1568 auto TI = getFirstTerminator();
1569 while (TI != end() && !TI->isBranch())
1570 ++TI;
1571
1572 if (TI != end()) {
1573 DL = TI->getDebugLoc();
1574 for (++TI ; TI != end() ; ++TI)
1575 if (TI->isBranch())
1576 DL = DebugLoc::getMergedLocation(LocA: DL, LocB: TI->getDebugLoc());
1577 }
1578 return DL;
1579}
1580
1581/// Return probability of the edge from this block to MBB.
1582BranchProbability
1583MachineBasicBlock::getSuccProbability(const_succ_iterator Succ) const {
1584 if (Probs.empty())
1585 return BranchProbability(1, succ_size());
1586
1587 const auto &Prob = *getProbabilityIterator(I: Succ);
1588 if (!Prob.isUnknown())
1589 return Prob;
1590 // For unknown probabilities, collect the sum of all known ones, and evenly
1591 // ditribute the complemental of the sum to each unknown probability.
1592 unsigned KnownProbNum = 0;
1593 auto Sum = BranchProbability::getZero();
1594 for (const auto &P : Probs) {
1595 if (!P.isUnknown()) {
1596 Sum += P;
1597 KnownProbNum++;
1598 }
1599 }
1600 return Sum.getCompl() / (Probs.size() - KnownProbNum);
1601}
1602
1603bool MachineBasicBlock::canPredictBranchProbabilities() const {
1604 if (succ_size() <= 1)
1605 return true;
1606 if (!hasSuccessorProbabilities())
1607 return true;
1608
1609 SmallVector<BranchProbability, 8> Normalized(Probs.begin(), Probs.end());
1610 BranchProbability::normalizeProbabilities(R&: Normalized);
1611
1612 // Normalize assuming unknown probabilities. This will assign equal
1613 // probabilities to all successors.
1614 SmallVector<BranchProbability, 8> Equal(Normalized.size());
1615 BranchProbability::normalizeProbabilities(R&: Equal);
1616
1617 return llvm::equal(LRange&: Normalized, RRange&: Equal);
1618}
1619
1620/// Set successor probability of a given iterator.
1621void MachineBasicBlock::setSuccProbability(succ_iterator I,
1622 BranchProbability Prob) {
1623 assert(!Prob.isUnknown());
1624 if (Probs.empty())
1625 return;
1626 *getProbabilityIterator(I) = Prob;
1627}
1628
1629/// Return probability iterator corresonding to the I successor iterator
1630MachineBasicBlock::const_probability_iterator
1631MachineBasicBlock::getProbabilityIterator(
1632 MachineBasicBlock::const_succ_iterator I) const {
1633 assert(Probs.size() == Successors.size() && "Async probability list!");
1634 const size_t index = std::distance(first: Successors.begin(), last: I);
1635 assert(index < Probs.size() && "Not a current successor!");
1636 return Probs.begin() + index;
1637}
1638
1639/// Return probability iterator corresonding to the I successor iterator.
1640MachineBasicBlock::probability_iterator
1641MachineBasicBlock::getProbabilityIterator(MachineBasicBlock::succ_iterator I) {
1642 assert(Probs.size() == Successors.size() && "Async probability list!");
1643 const size_t index = std::distance(first: Successors.begin(), last: I);
1644 assert(index < Probs.size() && "Not a current successor!");
1645 return Probs.begin() + index;
1646}
1647
1648/// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1649/// as of just before "MI".
1650///
1651/// Search is localised to a neighborhood of
1652/// Neighborhood instructions before (searching for defs or kills) and N
1653/// instructions after (searching just for defs) MI.
1654MachineBasicBlock::LivenessQueryResult
1655MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
1656 MCRegister Reg, const_iterator Before,
1657 unsigned Neighborhood) const {
1658 unsigned N = Neighborhood;
1659
1660 // Try searching forwards from Before, looking for reads or defs.
1661 const_iterator I(Before);
1662 for (; I != end() && N > 0; ++I) {
1663 if (I->isDebugOrPseudoInstr())
1664 continue;
1665
1666 --N;
1667
1668 PhysRegInfo Info = AnalyzePhysRegInBundle(MI: *I, Reg, TRI);
1669
1670 // Register is live when we read it here.
1671 if (Info.Read)
1672 return LQR_Live;
1673 // Register is dead if we can fully overwrite or clobber it here.
1674 if (Info.FullyDefined || Info.Clobbered)
1675 return LQR_Dead;
1676 }
1677
1678 // If we reached the end, it is safe to clobber Reg at the end of a block of
1679 // no successor has it live in.
1680 if (I == end()) {
1681 for (MachineBasicBlock *S : successors()) {
1682 for (const MachineBasicBlock::RegisterMaskPair &LI : S->liveins()) {
1683 if (TRI->regsOverlap(RegA: LI.PhysReg, RegB: Reg))
1684 return LQR_Live;
1685 }
1686 }
1687
1688 return LQR_Dead;
1689 }
1690
1691
1692 N = Neighborhood;
1693
1694 // Start by searching backwards from Before, looking for kills, reads or defs.
1695 I = const_iterator(Before);
1696 // If this is the first insn in the block, don't search backwards.
1697 if (I != begin()) {
1698 do {
1699 --I;
1700
1701 if (I->isDebugOrPseudoInstr())
1702 continue;
1703
1704 --N;
1705
1706 PhysRegInfo Info = AnalyzePhysRegInBundle(MI: *I, Reg, TRI);
1707
1708 // Defs happen after uses so they take precedence if both are present.
1709
1710 // Register is dead after a dead def of the full register.
1711 if (Info.DeadDef)
1712 return LQR_Dead;
1713 // Register is (at least partially) live after a def.
1714 if (Info.Defined) {
1715 if (!Info.PartialDeadDef)
1716 return LQR_Live;
1717 // As soon as we saw a partial definition (dead or not),
1718 // we cannot tell if the value is partial live without
1719 // tracking the lanemasks. We are not going to do this,
1720 // so fall back on the remaining of the analysis.
1721 break;
1722 }
1723 // Register is dead after a full kill or clobber and no def.
1724 if (Info.Killed || Info.Clobbered)
1725 return LQR_Dead;
1726 // Register must be live if we read it.
1727 if (Info.Read)
1728 return LQR_Live;
1729
1730 } while (I != begin() && N > 0);
1731 }
1732
1733 // If all the instructions before this in the block are debug instructions,
1734 // skip over them.
1735 while (I != begin() && std::prev(x: I)->isDebugOrPseudoInstr())
1736 --I;
1737
1738 // Did we get to the start of the block?
1739 if (I == begin()) {
1740 // If so, the register's state is definitely defined by the live-in state.
1741 for (const MachineBasicBlock::RegisterMaskPair &LI : liveins())
1742 if (TRI->regsOverlap(RegA: LI.PhysReg, RegB: Reg))
1743 return LQR_Live;
1744
1745 return LQR_Dead;
1746 }
1747
1748 // At this point we have no idea of the liveness of the register.
1749 return LQR_Unknown;
1750}
1751
1752const uint32_t *
1753MachineBasicBlock::getBeginClobberMask(const TargetRegisterInfo *TRI) const {
1754 // EH funclet entry does not preserve any registers.
1755 return isEHFuncletEntry() ? TRI->getNoPreservedMask() : nullptr;
1756}
1757
1758const uint32_t *
1759MachineBasicBlock::getEndClobberMask(const TargetRegisterInfo *TRI) const {
1760 // If we see a return block with successors, this must be a funclet return,
1761 // which does not preserve any registers. If there are no successors, we don't
1762 // care what kind of return it is, putting a mask after it is a no-op.
1763 return isReturnBlock() && !succ_empty() ? TRI->getNoPreservedMask() : nullptr;
1764}
1765
1766void MachineBasicBlock::clearLiveIns() {
1767 LiveIns.clear();
1768}
1769
1770void MachineBasicBlock::clearLiveIns(
1771 std::vector<RegisterMaskPair> &OldLiveIns) {
1772 assert(OldLiveIns.empty() && "Vector must be empty");
1773 std::swap(x&: LiveIns, y&: OldLiveIns);
1774}
1775
1776MachineBasicBlock::livein_iterator MachineBasicBlock::livein_begin() const {
1777 assert(getParent()->getProperties().hasTracksLiveness() &&
1778 "Liveness information is accurate");
1779 return LiveIns.begin();
1780}
1781
1782MachineBasicBlock::liveout_iterator MachineBasicBlock::liveout_begin() const {
1783 const MachineFunction &MF = *getParent();
1784 assert(MF.getProperties().hasTracksLiveness() &&
1785 "Liveness information is accurate");
1786
1787 const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
1788 MCRegister ExceptionPointer, ExceptionSelector;
1789 if (MF.getFunction().hasPersonalityFn()) {
1790 auto PersonalityFn = MF.getFunction().getPersonalityFn();
1791 ExceptionPointer = TLI.getExceptionPointerRegister(PersonalityFn);
1792 ExceptionSelector = TLI.getExceptionSelectorRegister(PersonalityFn);
1793 }
1794
1795 return liveout_iterator(*this, ExceptionPointer, ExceptionSelector, false);
1796}
1797
1798bool MachineBasicBlock::sizeWithoutDebugLargerThan(unsigned Limit) const {
1799 unsigned Cntr = 0;
1800 auto R = instructionsWithoutDebug(It: begin(), End: end());
1801 for (auto I = R.begin(), E = R.end(); I != E; ++I) {
1802 if (++Cntr > Limit)
1803 return true;
1804 }
1805 return false;
1806}
1807
1808const MBBSectionID MBBSectionID::ColdSectionID(MBBSectionID::SectionType::Cold);
1809const MBBSectionID
1810 MBBSectionID::ExceptionSectionID(MBBSectionID::SectionType::Exception);
1811