1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements integer type expansion and promotion for LegalizeTypes.
10// Promotion is the act of changing a computation in an illegal type into a
11// computation in a larger type. For example, implementing i8 arithmetic in an
12// i32 register (often needed on powerpc).
13// Expansion is the act of changing a computation in an illegal type into a
14// computation in two identical registers of a smaller type. For example,
15// implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16// targets).
17//
18//===----------------------------------------------------------------------===//
19
20#include "LegalizeTypes.h"
21#include "llvm/Analysis/TargetLibraryInfo.h"
22#include "llvm/CodeGen/StackMaps.h"
23#include "llvm/CodeGen/TargetLowering.h"
24#include "llvm/IR/DerivedTypes.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/KnownBits.h"
27#include "llvm/Support/raw_ostream.h"
28#include <algorithm>
29using namespace llvm;
30
31#define DEBUG_TYPE "legalize-types"
32
33//===----------------------------------------------------------------------===//
34// Integer Result Promotion
35//===----------------------------------------------------------------------===//
36
37/// PromoteIntegerResult - This method is called when a result of a node is
38/// found to be in need of promotion to a larger type. At this point, the node
39/// may also have invalid operands or may have other results that need
40/// expansion, we just know that (at least) one result needs promotion.
41void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
42 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG));
43 SDValue Res = SDValue();
44
45 // See if the target wants to custom expand this node.
46 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true)) {
47 LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n");
48 return;
49 }
50
51 switch (N->getOpcode()) {
52 default:
53#ifndef NDEBUG
54 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
55 N->dump(&DAG); dbgs() << "\n";
56#endif
57 report_fatal_error(reason: "Do not know how to promote this operator!");
58 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
59 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
60 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
61 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
62 case ISD::VP_BITREVERSE:
63 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
64 case ISD::VP_BSWAP:
65 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
66 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
67 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
68 case ISD::VP_CTLZ_ZERO_UNDEF:
69 case ISD::VP_CTLZ:
70 case ISD::CTLZ_ZERO_UNDEF:
71 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
72 case ISD::PARITY:
73 case ISD::VP_CTPOP:
74 case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break;
75 case ISD::VP_CTTZ_ZERO_UNDEF:
76 case ISD::VP_CTTZ:
77 case ISD::CTTZ_ZERO_UNDEF:
78 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
79 case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
80 case ISD::VP_CTTZ_ELTS:
81 Res = PromoteIntRes_VP_CttzElements(N);
82 break;
83 case ISD::EXTRACT_VECTOR_ELT:
84 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
85 case ISD::LOAD: Res = PromoteIntRes_LOAD(N: cast<LoadSDNode>(Val: N)); break;
86 case ISD::VP_LOAD:
87 Res = PromoteIntRes_VP_LOAD(N: cast<VPLoadSDNode>(Val: N));
88 break;
89 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(N: cast<MaskedLoadSDNode>(Val: N));
90 break;
91 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(N: cast<MaskedGatherSDNode>(Val: N));
92 break;
93 case ISD::VECTOR_COMPRESS:
94 Res = PromoteIntRes_VECTOR_COMPRESS(N);
95 break;
96 case ISD::SELECT:
97 case ISD::VSELECT:
98 case ISD::VP_SELECT:
99 case ISD::VP_MERGE:
100 Res = PromoteIntRes_Select(N);
101 break;
102 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
103 case ISD::STRICT_FSETCC:
104 case ISD::STRICT_FSETCCS:
105 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
106 case ISD::SMIN:
107 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
108 case ISD::UMIN:
109 case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break;
110
111 case ISD::SHL:
112 case ISD::VP_SHL: Res = PromoteIntRes_SHL(N); break;
113 case ISD::SIGN_EXTEND_INREG:
114 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
115 case ISD::SRA:
116 case ISD::VP_SRA: Res = PromoteIntRes_SRA(N); break;
117 case ISD::SRL:
118 case ISD::VP_SRL: Res = PromoteIntRes_SRL(N); break;
119 case ISD::VP_TRUNCATE:
120 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
121 case ISD::POISON:
122 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
123 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
124 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
125
126 case ISD::EXTRACT_SUBVECTOR:
127 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
128 case ISD::INSERT_SUBVECTOR:
129 Res = PromoteIntRes_INSERT_SUBVECTOR(N); break;
130 case ISD::VECTOR_REVERSE:
131 Res = PromoteIntRes_VECTOR_REVERSE(N); break;
132 case ISD::VECTOR_SHUFFLE:
133 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
134 case ISD::VECTOR_SPLICE:
135 Res = PromoteIntRes_VECTOR_SPLICE(N); break;
136 case ISD::VECTOR_INTERLEAVE:
137 case ISD::VECTOR_DEINTERLEAVE:
138 Res = PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(N);
139 return;
140 case ISD::INSERT_VECTOR_ELT:
141 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
142 case ISD::BUILD_VECTOR:
143 Res = PromoteIntRes_BUILD_VECTOR(N);
144 break;
145 case ISD::SPLAT_VECTOR:
146 case ISD::SCALAR_TO_VECTOR:
147 case ISD::EXPERIMENTAL_VP_SPLAT:
148 Res = PromoteIntRes_ScalarOp(N);
149 break;
150 case ISD::STEP_VECTOR: Res = PromoteIntRes_STEP_VECTOR(N); break;
151 case ISD::CONCAT_VECTORS:
152 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
153
154 case ISD::ANY_EXTEND_VECTOR_INREG:
155 case ISD::SIGN_EXTEND_VECTOR_INREG:
156 case ISD::ZERO_EXTEND_VECTOR_INREG:
157 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
158
159 case ISD::VECTOR_FIND_LAST_ACTIVE:
160 Res = PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(N);
161 break;
162
163 case ISD::GET_ACTIVE_LANE_MASK:
164 Res = PromoteIntRes_GET_ACTIVE_LANE_MASK(N);
165 break;
166
167 case ISD::PARTIAL_REDUCE_UMLA:
168 case ISD::PARTIAL_REDUCE_SMLA:
169 case ISD::PARTIAL_REDUCE_SUMLA:
170 Res = PromoteIntRes_PARTIAL_REDUCE_MLA(N);
171 break;
172
173 case ISD::SIGN_EXTEND:
174 case ISD::VP_SIGN_EXTEND:
175 case ISD::ZERO_EXTEND:
176 case ISD::VP_ZERO_EXTEND:
177 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
178
179 case ISD::VP_FP_TO_SINT:
180 case ISD::VP_FP_TO_UINT:
181 case ISD::STRICT_FP_TO_SINT:
182 case ISD::STRICT_FP_TO_UINT:
183 case ISD::FP_TO_SINT:
184 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
185
186 case ISD::FP_TO_SINT_SAT:
187 case ISD::FP_TO_UINT_SAT:
188 Res = PromoteIntRes_FP_TO_XINT_SAT(N); break;
189
190 case ISD::FP_TO_BF16:
191 case ISD::FP_TO_FP16:
192 Res = PromoteIntRes_FP_TO_FP16_BF16(N);
193 break;
194 case ISD::STRICT_FP_TO_BF16:
195 case ISD::STRICT_FP_TO_FP16:
196 Res = PromoteIntRes_STRICT_FP_TO_FP16_BF16(N);
197 break;
198 case ISD::GET_ROUNDING: Res = PromoteIntRes_GET_ROUNDING(N); break;
199
200 case ISD::AND:
201 case ISD::OR:
202 case ISD::XOR:
203 case ISD::ADD:
204 case ISD::SUB:
205 case ISD::MUL:
206 case ISD::VP_AND:
207 case ISD::VP_OR:
208 case ISD::VP_XOR:
209 case ISD::VP_ADD:
210 case ISD::VP_SUB:
211 case ISD::VP_MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
212
213 case ISD::ABDS:
214 case ISD::AVGCEILS:
215 case ISD::AVGFLOORS:
216 case ISD::VP_SMIN:
217 case ISD::VP_SMAX:
218 case ISD::SDIV:
219 case ISD::SREM:
220 case ISD::VP_SDIV:
221 case ISD::VP_SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
222
223 case ISD::ABDU:
224 case ISD::AVGCEILU:
225 case ISD::AVGFLOORU:
226 case ISD::VP_UMIN:
227 case ISD::VP_UMAX:
228 case ISD::UDIV:
229 case ISD::UREM:
230 case ISD::VP_UDIV:
231 case ISD::VP_UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
232
233 case ISD::SADDO:
234 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
235 case ISD::UADDO:
236 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
237 case ISD::SMULO:
238 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
239
240 case ISD::ADDE:
241 case ISD::SUBE:
242 case ISD::UADDO_CARRY:
243 case ISD::USUBO_CARRY: Res = PromoteIntRes_UADDSUBO_CARRY(N, ResNo); break;
244
245 case ISD::SADDO_CARRY:
246 case ISD::SSUBO_CARRY: Res = PromoteIntRes_SADDSUBO_CARRY(N, ResNo); break;
247
248 case ISD::SADDSAT:
249 case ISD::UADDSAT:
250 case ISD::SSUBSAT:
251 case ISD::USUBSAT:
252 case ISD::SSHLSAT:
253 case ISD::USHLSAT:
254 Res = PromoteIntRes_ADDSUBSHLSAT<EmptyMatchContext>(N);
255 break;
256 case ISD::VP_SADDSAT:
257 case ISD::VP_UADDSAT:
258 case ISD::VP_SSUBSAT:
259 case ISD::VP_USUBSAT:
260 Res = PromoteIntRes_ADDSUBSHLSAT<VPMatchContext>(N);
261 break;
262
263 case ISD::SCMP:
264 case ISD::UCMP:
265 Res = PromoteIntRes_CMP(N);
266 break;
267
268 case ISD::SMULFIX:
269 case ISD::SMULFIXSAT:
270 case ISD::UMULFIX:
271 case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
272
273 case ISD::SDIVFIX:
274 case ISD::SDIVFIXSAT:
275 case ISD::UDIVFIX:
276 case ISD::UDIVFIXSAT: Res = PromoteIntRes_DIVFIX(N); break;
277
278 case ISD::ABS: Res = PromoteIntRes_ABS(N); break;
279
280 case ISD::ATOMIC_LOAD:
281 Res = PromoteIntRes_Atomic0(N: cast<AtomicSDNode>(Val: N)); break;
282
283 case ISD::ATOMIC_LOAD_ADD:
284 case ISD::ATOMIC_LOAD_SUB:
285 case ISD::ATOMIC_LOAD_AND:
286 case ISD::ATOMIC_LOAD_CLR:
287 case ISD::ATOMIC_LOAD_OR:
288 case ISD::ATOMIC_LOAD_XOR:
289 case ISD::ATOMIC_LOAD_NAND:
290 case ISD::ATOMIC_LOAD_MIN:
291 case ISD::ATOMIC_LOAD_MAX:
292 case ISD::ATOMIC_LOAD_UMIN:
293 case ISD::ATOMIC_LOAD_UMAX:
294 case ISD::ATOMIC_SWAP:
295 Res = PromoteIntRes_Atomic1(N: cast<AtomicSDNode>(Val: N)); break;
296
297 case ISD::ATOMIC_CMP_SWAP:
298 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
299 Res = PromoteIntRes_AtomicCmpSwap(N: cast<AtomicSDNode>(Val: N), ResNo);
300 break;
301
302 case ISD::VECREDUCE_ADD:
303 case ISD::VECREDUCE_MUL:
304 case ISD::VECREDUCE_AND:
305 case ISD::VECREDUCE_OR:
306 case ISD::VECREDUCE_XOR:
307 case ISD::VECREDUCE_SMAX:
308 case ISD::VECREDUCE_SMIN:
309 case ISD::VECREDUCE_UMAX:
310 case ISD::VECREDUCE_UMIN:
311 Res = PromoteIntRes_VECREDUCE(N);
312 break;
313
314 case ISD::VP_REDUCE_ADD:
315 case ISD::VP_REDUCE_MUL:
316 case ISD::VP_REDUCE_AND:
317 case ISD::VP_REDUCE_OR:
318 case ISD::VP_REDUCE_XOR:
319 case ISD::VP_REDUCE_SMAX:
320 case ISD::VP_REDUCE_SMIN:
321 case ISD::VP_REDUCE_UMAX:
322 case ISD::VP_REDUCE_UMIN:
323 Res = PromoteIntRes_VP_REDUCE(N);
324 break;
325
326 case ISD::FREEZE:
327 Res = PromoteIntRes_FREEZE(N);
328 break;
329
330 case ISD::ROTL:
331 case ISD::ROTR:
332 Res = PromoteIntRes_Rotate(N);
333 break;
334
335 case ISD::FSHL:
336 case ISD::FSHR:
337 Res = PromoteIntRes_FunnelShift(N);
338 break;
339
340 case ISD::VP_FSHL:
341 case ISD::VP_FSHR:
342 Res = PromoteIntRes_VPFunnelShift(N);
343 break;
344
345 case ISD::IS_FPCLASS:
346 Res = PromoteIntRes_IS_FPCLASS(N);
347 break;
348 case ISD::FFREXP:
349 Res = PromoteIntRes_FFREXP(N);
350 break;
351
352 case ISD::LRINT:
353 case ISD::LLRINT:
354 Res = PromoteIntRes_XRINT(N);
355 break;
356
357 case ISD::PATCHPOINT:
358 Res = PromoteIntRes_PATCHPOINT(N);
359 break;
360 }
361
362 // If the result is null then the sub-method took care of registering it.
363 if (Res.getNode())
364 SetPromotedInteger(Op: SDValue(N, ResNo), Result: Res);
365}
366
367SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
368 unsigned ResNo) {
369 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
370 return GetPromotedInteger(Op);
371}
372
373SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
374 // Sign-extend the new bits, and continue the assertion.
375 SDValue Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
376 return DAG.getNode(Opcode: ISD::AssertSext, DL: SDLoc(N),
377 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
378}
379
380SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
381 // Zero the new bits, and continue the assertion.
382 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
383 return DAG.getNode(Opcode: ISD::AssertZext, DL: SDLoc(N),
384 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
385}
386
387SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
388 EVT ResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
389 ISD::LoadExtType ExtType = N->getExtensionType();
390 if (ExtType == ISD::NON_EXTLOAD) {
391 switch (TLI.getExtendForAtomicOps()) {
392 case ISD::SIGN_EXTEND:
393 ExtType = ISD::SEXTLOAD;
394 break;
395 case ISD::ZERO_EXTEND:
396 ExtType = ISD::ZEXTLOAD;
397 break;
398 case ISD::ANY_EXTEND:
399 ExtType = ISD::EXTLOAD;
400 break;
401 default:
402 llvm_unreachable("Invalid atomic op extension");
403 }
404 }
405
406 SDValue Res =
407 DAG.getAtomicLoad(ExtType, dl: SDLoc(N), MemVT: N->getMemoryVT(), VT: ResVT,
408 Chain: N->getChain(), Ptr: N->getBasePtr(), MMO: N->getMemOperand());
409
410 // Legalize the chain result - switch anything that used the old chain to
411 // use the new one.
412 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
413 return Res;
414}
415
416SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
417 SDValue Op2 = GetPromotedInteger(Op: N->getOperand(Num: 2));
418 SDValue Res = DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N),
419 MemVT: N->getMemoryVT(),
420 Chain: N->getChain(), Ptr: N->getBasePtr(),
421 Val: Op2, MMO: N->getMemOperand());
422 // Legalize the chain result - switch anything that used the old chain to
423 // use the new one.
424 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
425 return Res;
426}
427
428SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
429 unsigned ResNo) {
430 if (ResNo == 1) {
431 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
432 EVT SVT = getSetCCResultType(VT: N->getOperand(Num: 2).getValueType());
433 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
434
435 // Only use the result of getSetCCResultType if it is legal,
436 // otherwise just use the promoted result type (NVT).
437 if (!TLI.isTypeLegal(VT: SVT))
438 SVT = NVT;
439
440 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: SVT, VT3: MVT::Other);
441 SDValue Res = DAG.getAtomicCmpSwap(
442 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs,
443 Chain: N->getChain(), Ptr: N->getBasePtr(), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
444 MMO: N->getMemOperand());
445 ReplaceValueWith(From: SDValue(N, 0), To: Res.getValue(R: 0));
446 ReplaceValueWith(From: SDValue(N, 2), To: Res.getValue(R: 2));
447 return DAG.getSExtOrTrunc(Op: Res.getValue(R: 1), DL: SDLoc(N), VT: NVT);
448 }
449
450 // Op2 is used for the comparison and thus must be extended according to the
451 // target's atomic operations. Op3 is merely stored and so can be left alone.
452 SDValue Op2 = N->getOperand(Num: 2);
453 SDValue Op3 = GetPromotedInteger(Op: N->getOperand(Num: 3));
454 switch (TLI.getExtendForAtomicCmpSwapArg()) {
455 case ISD::SIGN_EXTEND:
456 Op2 = SExtPromotedInteger(Op: Op2);
457 break;
458 case ISD::ZERO_EXTEND:
459 Op2 = ZExtPromotedInteger(Op: Op2);
460 break;
461 case ISD::ANY_EXTEND:
462 Op2 = GetPromotedInteger(Op: Op2);
463 break;
464 default:
465 llvm_unreachable("Invalid atomic op extension");
466 }
467
468 SDVTList VTs =
469 DAG.getVTList(VT1: Op2.getValueType(), VT2: N->getValueType(ResNo: 1), VT3: MVT::Other);
470 SDValue Res = DAG.getAtomicCmpSwap(
471 Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(), VTs, Chain: N->getChain(),
472 Ptr: N->getBasePtr(), Cmp: Op2, Swp: Op3, MMO: N->getMemOperand());
473 // Update the use to N with the newly created Res.
474 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
475 ReplaceValueWith(From: SDValue(N, i), To: Res.getValue(R: i));
476 return Res;
477}
478
479SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
480 SDValue InOp = N->getOperand(Num: 0);
481 EVT InVT = InOp.getValueType();
482 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
483 EVT OutVT = N->getValueType(ResNo: 0);
484 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
485 SDLoc dl(N);
486
487 switch (getTypeAction(VT: InVT)) {
488 case TargetLowering::TypeLegal:
489 break;
490 case TargetLowering::TypePromoteInteger:
491 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector() && !NInVT.isVector())
492 // The input promotes to the same size. Convert the promoted value.
493 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetPromotedInteger(Op: InOp));
494 break;
495 case TargetLowering::TypeSoftenFloat:
496 // Promote the integer operand by hand.
497 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftenedFloat(Op: InOp));
498 case TargetLowering::TypeSoftPromoteHalf:
499 // Promote the integer operand by hand.
500 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: GetSoftPromotedHalf(Op: InOp));
501 case TargetLowering::TypePromoteFloat: {
502 // Convert the promoted float by hand.
503 if (!NOutVT.isVector())
504 return DAG.getNode(Opcode: ISD::FP_TO_FP16, DL: dl, VT: NOutVT, Operand: GetPromotedFloat(Op: InOp));
505 break;
506 }
507 case TargetLowering::TypeExpandInteger:
508 case TargetLowering::TypeExpandFloat:
509 break;
510 case TargetLowering::TypeScalarizeVector:
511 // Convert the element to an integer and promote it by hand.
512 if (!NOutVT.isVector())
513 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
514 Operand: BitConvertToInteger(Op: GetScalarizedVector(Op: InOp)));
515 break;
516 case TargetLowering::TypeScalarizeScalableVector:
517 report_fatal_error(reason: "Scalarization of scalable vectors is not supported.");
518 case TargetLowering::TypeSplitVector: {
519 if (!NOutVT.isVector()) {
520 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
521 // pieces of the input into integers and reassemble in the final type.
522 SDValue Lo, Hi;
523 GetSplitVector(Op: N->getOperand(Num: 0), Lo, Hi);
524 Lo = BitConvertToInteger(Op: Lo);
525 Hi = BitConvertToInteger(Op: Hi);
526
527 if (DAG.getDataLayout().isBigEndian())
528 std::swap(a&: Lo, b&: Hi);
529
530 InOp = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
531 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
532 BitWidth: NOutVT.getSizeInBits()),
533 Operand: JoinIntegers(Lo, Hi));
534 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: InOp);
535 }
536 break;
537 }
538 case TargetLowering::TypeWidenVector:
539 // The input is widened to the same size. Convert to the widened value.
540 // Make sure that the outgoing value is not a vector, because this would
541 // make us bitcast between two vectors which are legalized in different ways.
542 if (NOutVT.bitsEq(VT: NInVT) && !NOutVT.isVector()) {
543 SDValue Res =
544 DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: GetWidenedVector(Op: InOp));
545
546 // For big endian targets we need to shift the casted value or the
547 // interesting bits will end up at the wrong place.
548 if (DAG.getDataLayout().isBigEndian()) {
549 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
550 assert(ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!");
551 Res = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NOutVT, N1: Res,
552 N2: DAG.getShiftAmountConstant(Val: ShiftAmt, VT: NOutVT, DL: dl));
553 }
554 return Res;
555 }
556 // If the output type is also a vector and widening it to the same size
557 // as the widened input type would be a legal type, we can widen the bitcast
558 // and handle the promotion after.
559 if (NOutVT.isVector()) {
560 TypeSize WidenInSize = NInVT.getSizeInBits();
561 TypeSize OutSize = OutVT.getSizeInBits();
562 if (WidenInSize.hasKnownScalarFactor(RHS: OutSize)) {
563 unsigned Scale = WidenInSize.getKnownScalarFactor(RHS: OutSize);
564 EVT WideOutVT =
565 EVT::getVectorVT(Context&: *DAG.getContext(), VT: OutVT.getVectorElementType(),
566 EC: OutVT.getVectorElementCount() * Scale);
567 if (isTypeLegal(VT: WideOutVT)) {
568 InOp = DAG.getBitcast(VT: WideOutVT, V: GetWidenedVector(Op: InOp));
569 InOp = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: InOp,
570 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
571 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: InOp);
572 }
573 }
574 }
575 }
576
577 // TODO: Handle big endian
578 if (!NOutVT.isVector() && InOp.getValueType().isVector() &&
579 DAG.getDataLayout().isLittleEndian()) {
580 // Pad the vector operand with undef and cast to a wider integer.
581 EVT EltVT = InOp.getValueType().getVectorElementType();
582 TypeSize EltSize = EltVT.getSizeInBits();
583 TypeSize OutSize = NOutVT.getSizeInBits();
584
585 if (OutSize.hasKnownScalarFactor(RHS: EltSize)) {
586 unsigned NumEltsWithPadding = OutSize.getKnownScalarFactor(RHS: EltSize);
587 EVT WideVecVT =
588 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
589
590 if (isTypeLegal(VT: WideVecVT)) {
591 SDValue Inserted = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: WideVecVT,
592 N1: DAG.getUNDEF(VT: WideVecVT), N2: InOp,
593 N3: DAG.getVectorIdxConstant(Val: 0, DL: dl));
594
595 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NOutVT, Operand: Inserted);
596 }
597 }
598 }
599
600 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT,
601 Operand: CreateStackStoreLoad(Op: InOp, DestVT: OutVT));
602}
603
604SDValue DAGTypeLegalizer::PromoteIntRes_FREEZE(SDNode *N) {
605 SDValue V = GetPromotedInteger(Op: N->getOperand(Num: 0));
606 return DAG.getNode(Opcode: ISD::FREEZE, DL: SDLoc(N),
607 VT: V.getValueType(), Operand: V);
608}
609
610SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
611 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
612 EVT OVT = N->getValueType(ResNo: 0);
613 EVT NVT = Op.getValueType();
614 SDLoc dl(N);
615
616 // If the larger BSWAP isn't supported by the target, try to expand now.
617 // If we expand later we'll end up with more operations since we lost the
618 // original type. We only do this for scalars since we have a shuffle
619 // based lowering for vectors in LegalizeVectorOps.
620 if (!OVT.isVector() &&
621 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BSWAP, VT: NVT)) {
622 if (SDValue Res = TLI.expandBSWAP(N, DAG))
623 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
624 }
625
626 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
627 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
628 if (N->getOpcode() == ISD::BSWAP)
629 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: NVT, Operand: Op),
630 N2: ShAmt);
631 SDValue Mask = N->getOperand(Num: 1);
632 SDValue EVL = N->getOperand(Num: 2);
633 return DAG.getNode(Opcode: ISD::VP_SRL, DL: dl, VT: NVT,
634 N1: DAG.getNode(Opcode: ISD::VP_BSWAP, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL), N2: ShAmt,
635 N3: Mask, N4: EVL);
636}
637
638SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
639 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
640 EVT OVT = N->getValueType(ResNo: 0);
641 EVT NVT = Op.getValueType();
642 SDLoc dl(N);
643
644 // If the larger BITREVERSE isn't supported by the target, try to expand now.
645 // If we expand later we'll end up with more operations since we lost the
646 // original type. We only do this for scalars since we have a shuffle
647 // based lowering for vectors in LegalizeVectorOps.
648 if (!OVT.isVector() && OVT.isSimple() &&
649 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::BITREVERSE, VT: NVT)) {
650 if (SDValue Res = TLI.expandBITREVERSE(N, DAG))
651 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Res);
652 }
653
654 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
655 SDValue ShAmt = DAG.getShiftAmountConstant(Val: DiffBits, VT: NVT, DL: dl);
656 if (N->getOpcode() == ISD::BITREVERSE)
657 return DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT,
658 N1: DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: NVT, Operand: Op), N2: ShAmt);
659 SDValue Mask = N->getOperand(Num: 1);
660 SDValue EVL = N->getOperand(Num: 2);
661 return DAG.getNode(Opcode: ISD::VP_SRL, DL: dl, VT: NVT,
662 N1: DAG.getNode(Opcode: ISD::VP_BITREVERSE, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL),
663 N2: ShAmt, N3: Mask, N4: EVL);
664}
665
666SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
667 // The pair element type may be legal, or may not promote to the same type as
668 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
669 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N),
670 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
671 VT: N->getValueType(ResNo: 0)), Operand: JoinIntegers(Lo: N->getOperand(Num: 0),
672 Hi: N->getOperand(Num: 1)));
673}
674
675SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
676 EVT VT = N->getValueType(ResNo: 0);
677 // FIXME there is no actual debug info here
678 SDLoc dl(N);
679 // Zero extend things like i1, sign extend everything else. It shouldn't
680 // matter in theory which one we pick, but this tends to give better code?
681 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
682 SDValue Result = DAG.getNode(Opcode: Opc, DL: dl,
683 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT),
684 Operand: SDValue(N, 0));
685 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
686 return Result;
687}
688
689SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
690 EVT OVT = N->getValueType(ResNo: 0);
691 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
692 SDLoc dl(N);
693
694 // If the larger CTLZ isn't supported by the target, try to expand now.
695 // If we expand later we'll end up with more operations since we lost the
696 // original type.
697 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
698 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ, VT: NVT) &&
699 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTLZ_ZERO_UNDEF, VT: NVT)) {
700 if (SDValue Result = TLI.expandCTLZ(N, DAG)) {
701 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
702 return Result;
703 }
704 }
705
706 unsigned CtlzOpcode = N->getOpcode();
707 if (CtlzOpcode == ISD::CTLZ || CtlzOpcode == ISD::VP_CTLZ) {
708 // Subtract off the extra leading bits in the bigger type.
709 SDValue ExtractLeadingBits = DAG.getConstant(
710 Val: NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), DL: dl, VT: NVT);
711
712 if (!N->isVPOpcode()) {
713 // Zero extend to the promoted type and do the count there.
714 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
715 return DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT,
716 N1: DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Op),
717 N2: ExtractLeadingBits);
718 }
719 SDValue Mask = N->getOperand(Num: 1);
720 SDValue EVL = N->getOperand(Num: 2);
721 // Zero extend to the promoted type and do the count there.
722 SDValue Op = VPZExtPromotedInteger(Op: N->getOperand(Num: 0), Mask, EVL);
723 return DAG.getNode(Opcode: ISD::VP_SUB, DL: dl, VT: NVT,
724 N1: DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL),
725 N2: ExtractLeadingBits, N3: Mask, N4: EVL);
726 }
727 if (CtlzOpcode == ISD::CTLZ_ZERO_UNDEF ||
728 CtlzOpcode == ISD::VP_CTLZ_ZERO_UNDEF) {
729 // Any Extend the argument
730 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
731 // Op = Op << (sizeinbits(NVT) - sizeinbits(Old VT))
732 unsigned SHLAmount = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
733 auto ShiftConst =
734 DAG.getShiftAmountConstant(Val: SHLAmount, VT: Op.getValueType(), DL: dl);
735 if (!N->isVPOpcode()) {
736 Op = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Op, N2: ShiftConst);
737 return DAG.getNode(Opcode: CtlzOpcode, DL: dl, VT: NVT, Operand: Op);
738 }
739
740 SDValue Mask = N->getOperand(Num: 1);
741 SDValue EVL = N->getOperand(Num: 2);
742 Op = DAG.getNode(Opcode: ISD::VP_SHL, DL: dl, VT: NVT, N1: Op, N2: ShiftConst, N3: Mask, N4: EVL);
743 return DAG.getNode(Opcode: CtlzOpcode, DL: dl, VT: NVT, N1: Op, N2: Mask, N3: EVL);
744 }
745 llvm_unreachable("Invalid CTLZ Opcode");
746}
747
748SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
749 EVT OVT = N->getValueType(ResNo: 0);
750 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
751
752 // If the larger CTPOP isn't supported by the target, try to expand now.
753 // If we expand later we'll end up with more operations since we lost the
754 // original type.
755 // TODO: Expand ISD::PARITY. Need to move ExpandPARITY from LegalizeDAG to
756 // TargetLowering.
757 if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
758 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTPOP, VT: NVT)) {
759 if (SDValue Result = TLI.expandCTPOP(N, DAG)) {
760 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Result);
761 return Result;
762 }
763 }
764
765 // Zero extend to the promoted type and do the count or parity there.
766 if (!N->isVPOpcode()) {
767 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
768 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: Op.getValueType(), Operand: Op);
769 }
770
771 SDValue Mask = N->getOperand(Num: 1);
772 SDValue EVL = N->getOperand(Num: 2);
773 SDValue Op = VPZExtPromotedInteger(Op: N->getOperand(Num: 0), Mask, EVL);
774 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: Op.getValueType(), N1: Op, N2: Mask,
775 N3: EVL);
776}
777
778SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
779 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
780 EVT OVT = N->getValueType(ResNo: 0);
781 EVT NVT = Op.getValueType();
782 SDLoc dl(N);
783
784 // If the larger CTTZ isn't supported by the target, try to expand now.
785 // If we expand later we'll end up with more operations since we lost the
786 // original type. Don't expand if we can use CTPOP or CTLZ expansion on the
787 // larger type.
788 if (!OVT.isVector() && TLI.isTypeLegal(VT: NVT) &&
789 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ, VT: NVT) &&
790 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::CTTZ_ZERO_UNDEF, VT: NVT) &&
791 !TLI.isOperationLegal(Op: ISD::CTPOP, VT: NVT) &&
792 !TLI.isOperationLegal(Op: ISD::CTLZ, VT: NVT)) {
793 if (SDValue Result = TLI.expandCTTZ(N, DAG)) {
794 Result = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Result);
795 return Result;
796 }
797 }
798
799 unsigned NewOpc = N->getOpcode();
800 if (NewOpc == ISD::CTTZ || NewOpc == ISD::VP_CTTZ) {
801 // The count is the same in the promoted type except if the original
802 // value was zero. This can be handled by setting the bit just off
803 // the top of the original type.
804 auto TopBit = APInt::getOneBitSet(numBits: NVT.getScalarSizeInBits(),
805 BitNo: OVT.getScalarSizeInBits());
806 if (NewOpc == ISD::CTTZ) {
807 Op = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Op, N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT));
808 NewOpc = ISD::CTTZ_ZERO_UNDEF;
809 } else {
810 Op =
811 DAG.getNode(Opcode: ISD::VP_OR, DL: dl, VT: NVT, N1: Op, N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT),
812 N3: N->getOperand(Num: 1), N4: N->getOperand(Num: 2));
813 NewOpc = ISD::VP_CTTZ_ZERO_UNDEF;
814 }
815 }
816 if (!N->isVPOpcode())
817 return DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: Op);
818 return DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, N1: Op, N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
819}
820
821SDValue DAGTypeLegalizer::PromoteIntRes_VP_CttzElements(SDNode *N) {
822 SDLoc DL(N);
823 EVT NewVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
824 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NewVT, Ops: N->ops());
825}
826
827SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
828 SDLoc dl(N);
829 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
830
831 SDValue Op0 = N->getOperand(Num: 0);
832 SDValue Op1 = N->getOperand(Num: 1);
833
834 // If the input also needs to be promoted, do that first so we can get a
835 // get a good idea for the output type.
836 if (TLI.getTypeAction(Context&: *DAG.getContext(), VT: Op0.getValueType())
837 == TargetLowering::TypePromoteInteger) {
838 SDValue In = GetPromotedInteger(Op: Op0);
839
840 // If the new type is larger than NVT, use it. We probably won't need to
841 // promote it again.
842 EVT SVT = In.getValueType().getScalarType();
843 if (SVT.bitsGE(VT: NVT)) {
844 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SVT, N1: In, N2: Op1);
845 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NVT);
846 }
847 }
848
849 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: NVT, N1: Op0, N2: Op1);
850}
851
852SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
853 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
854 unsigned NewOpc =
855 TLI.getPreferredFPToIntOpcode(Op: N->getOpcode(), FromVT: N->getValueType(ResNo: 0), ToVT: NVT);
856 SDLoc dl(N);
857
858 SDValue Res;
859 if (N->isStrictFPOpcode()) {
860 Res = DAG.getNode(Opcode: NewOpc, DL: dl, ResultTys: {NVT, MVT::Other},
861 Ops: {N->getOperand(Num: 0), N->getOperand(Num: 1)});
862 // Legalize the chain result - switch anything that used the old chain to
863 // use the new one.
864 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
865 } else if (NewOpc == ISD::VP_FP_TO_SINT || NewOpc == ISD::VP_FP_TO_UINT) {
866 Res = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Ops: {N->getOperand(Num: 0), N->getOperand(Num: 1),
867 N->getOperand(Num: 2)});
868 } else {
869 Res = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
870 }
871
872 // Assert that the converted value fits in the original type. If it doesn't
873 // (eg: because the value being converted is too big), then the result of the
874 // original operation was undefined anyway, so the assert is still correct.
875 //
876 // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
877 // before legalization: fp-to-uint16, 65534. -> 0xfffe
878 // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
879 return DAG.getNode(Opcode: (N->getOpcode() == ISD::FP_TO_UINT ||
880 N->getOpcode() == ISD::STRICT_FP_TO_UINT ||
881 N->getOpcode() == ISD::VP_FP_TO_UINT)
882 ? ISD::AssertZext
883 : ISD::AssertSext,
884 DL: dl, VT: NVT, N1: Res,
885 N2: DAG.getValueType(N->getValueType(ResNo: 0).getScalarType()));
886}
887
888SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT_SAT(SDNode *N) {
889 // Promote the result type, while keeping the original width in Op1.
890 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
891 SDLoc dl(N);
892 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
893 N2: N->getOperand(Num: 1));
894}
895
896SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16_BF16(SDNode *N) {
897 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
898 SDLoc dl(N);
899
900 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
901}
902
903SDValue DAGTypeLegalizer::PromoteIntRes_STRICT_FP_TO_FP16_BF16(SDNode *N) {
904 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
905 SDLoc dl(N);
906
907 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
908 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
909 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
910 return Res;
911}
912
913SDValue DAGTypeLegalizer::PromoteIntRes_XRINT(SDNode *N) {
914 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
915 SDLoc dl(N);
916 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
917}
918
919SDValue DAGTypeLegalizer::PromoteIntRes_GET_ROUNDING(SDNode *N) {
920 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
921 SDLoc dl(N);
922
923 SDValue Res =
924 DAG.getNode(Opcode: N->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
925
926 // Legalize the chain result - switch anything that used the old chain to
927 // use the new one.
928 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
929 return Res;
930}
931
932SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
933 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
934 SDLoc dl(N);
935
936 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
937 == TargetLowering::TypePromoteInteger) {
938 SDValue Res = GetPromotedInteger(Op: N->getOperand(Num: 0));
939 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
940
941 // If the result and operand types are the same after promotion, simplify
942 // to an in-register extension. Unless this is a VP_*_EXTEND.
943 if (NVT == Res.getValueType() && N->getNumOperands() == 1) {
944 // The high bits are not guaranteed to be anything. Insert an extend.
945 if (N->getOpcode() == ISD::SIGN_EXTEND)
946 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
947 N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
948 if (N->getOpcode() == ISD::ZERO_EXTEND)
949 return DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: N->getOperand(Num: 0).getValueType());
950 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
951 return Res;
952 }
953 }
954
955 // Otherwise, just extend the original operand all the way to the larger type.
956 if (N->getNumOperands() != 1) {
957 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
958 assert(N->isVPOpcode() && "Expected VP opcode");
959 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: N->getOperand(Num: 0),
960 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
961 }
962 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
963}
964
965SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
966 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
967 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
968 ISD::LoadExtType ExtType =
969 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
970 SDLoc dl(N);
971 SDValue Res = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
972 MemVT: N->getMemoryVT(), MMO: N->getMemOperand());
973
974 // Legalize the chain result - switch anything that used the old chain to
975 // use the new one.
976 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
977 return Res;
978}
979
980SDValue DAGTypeLegalizer::PromoteIntRes_VP_LOAD(VPLoadSDNode *N) {
981 assert(!N->isIndexed() && "Indexed vp_load during type legalization!");
982 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
983 ISD::LoadExtType ExtType = (N->getExtensionType() == ISD::NON_EXTLOAD)
984 ? ISD::EXTLOAD
985 : N->getExtensionType();
986 SDLoc dl(N);
987 SDValue Res =
988 DAG.getExtLoadVP(ExtType, dl, VT: NVT, Chain: N->getChain(), Ptr: N->getBasePtr(),
989 Mask: N->getMask(), EVL: N->getVectorLength(), MemVT: N->getMemoryVT(),
990 MMO: N->getMemOperand(), IsExpanding: N->isExpandingLoad());
991 // Legalize the chain result - switch anything that used the old chain to
992 // use the new one.
993 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
994 return Res;
995}
996
997SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
998 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
999 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
1000
1001 ISD::LoadExtType ExtType = N->getExtensionType();
1002 if (ExtType == ISD::NON_EXTLOAD)
1003 ExtType = ISD::EXTLOAD;
1004
1005 SDLoc dl(N);
1006 SDValue Res = DAG.getMaskedLoad(VT: NVT, dl, Chain: N->getChain(), Base: N->getBasePtr(),
1007 Offset: N->getOffset(), Mask: N->getMask(), Src0: ExtPassThru,
1008 MemVT: N->getMemoryVT(), MMO: N->getMemOperand(),
1009 AM: N->getAddressingMode(), ExtType,
1010 IsExpanding: N->isExpandingLoad());
1011 // Legalize the chain result - switch anything that used the old chain to
1012 // use the new one.
1013 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1014 return Res;
1015}
1016
1017SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
1018 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1019 SDValue ExtPassThru = GetPromotedInteger(Op: N->getPassThru());
1020 assert(NVT == ExtPassThru.getValueType() &&
1021 "Gather result type and the passThru argument type should be the same");
1022
1023 ISD::LoadExtType ExtType = N->getExtensionType();
1024 if (ExtType == ISD::NON_EXTLOAD)
1025 ExtType = ISD::EXTLOAD;
1026
1027 SDLoc dl(N);
1028 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
1029 N->getIndex(), N->getScale() };
1030 SDValue Res = DAG.getMaskedGather(VTs: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
1031 MemVT: N->getMemoryVT(), dl, Ops,
1032 MMO: N->getMemOperand(), IndexType: N->getIndexType(),
1033 ExtTy: ExtType);
1034 // Legalize the chain result - switch anything that used the old chain to
1035 // use the new one.
1036 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1037 return Res;
1038}
1039
1040SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_COMPRESS(SDNode *N) {
1041 SDValue Vec = GetPromotedInteger(Op: N->getOperand(Num: 0));
1042 SDValue Passthru = GetPromotedInteger(Op: N->getOperand(Num: 2));
1043 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT: Vec.getValueType(), N1: Vec,
1044 N2: N->getOperand(Num: 1), N3: Passthru);
1045}
1046
1047/// Promote the overflow flag of an overflowing arithmetic node.
1048SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
1049 // Change the return type of the boolean result while obeying
1050 // getSetCCResultType.
1051 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1052 EVT VT = N->getValueType(ResNo: 0);
1053 EVT SVT = getSetCCResultType(VT);
1054 SDValue Ops[3] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
1055 unsigned NumOps = N->getNumOperands();
1056 assert(NumOps <= 3 && "Too many operands");
1057 if (NumOps == 3)
1058 Ops[2] = PromoteTargetBoolean(Bool: N->getOperand(Num: 2), ValVT: VT);
1059
1060 SDLoc dl(N);
1061 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: SVT),
1062 Ops: ArrayRef(Ops, NumOps));
1063
1064 // Modified the sum result - switch anything that used the old sum to use
1065 // the new one.
1066 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1067
1068 // Convert to the expected type.
1069 return DAG.getBoolExtOrTrunc(Op: Res.getValue(R: 1), SL: dl, VT: NVT, OpVT: VT);
1070}
1071
1072template <class MatchContextClass>
1073SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
1074 // If the promoted type is legal, we can convert this to:
1075 // 1. ANY_EXTEND iN to iM
1076 // 2. SHL by M-N
1077 // 3. [US][ADD|SUB|SHL]SAT
1078 // 4. L/ASHR by M-N
1079 // Else it is more efficient to convert this to a min and a max
1080 // operation in the higher precision arithmetic.
1081 SDLoc dl(N);
1082 SDValue Op1 = N->getOperand(Num: 0);
1083 SDValue Op2 = N->getOperand(Num: 1);
1084 MatchContextClass matcher(DAG, TLI, N);
1085
1086 unsigned Opcode = matcher.getRootBaseOpcode();
1087 unsigned OldBits = Op1.getScalarValueSizeInBits();
1088
1089 // USUBSAT can always be promoted as long as we have zero/sign-extended the
1090 // args.
1091 if (Opcode == ISD::USUBSAT) {
1092 SExtOrZExtPromotedOperands(LHS&: Op1, RHS&: Op2);
1093 return matcher.getNode(ISD::USUBSAT, dl, Op1.getValueType(), Op1, Op2);
1094 }
1095
1096 if (Opcode == ISD::UADDSAT) {
1097 EVT OVT = Op1.getValueType();
1098 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
1099 // We can promote if we use sign-extend. Do this if the target prefers.
1100 if (TLI.isSExtCheaperThanZExt(FromTy: OVT, ToTy: NVT)) {
1101 Op1 = SExtPromotedInteger(Op: Op1);
1102 Op2 = SExtPromotedInteger(Op: Op2);
1103 return matcher.getNode(ISD::UADDSAT, dl, NVT, Op1, Op2);
1104 }
1105
1106 Op1 = ZExtPromotedInteger(Op: Op1);
1107 Op2 = ZExtPromotedInteger(Op: Op2);
1108 unsigned NewBits = NVT.getScalarSizeInBits();
1109 APInt MaxVal = APInt::getLowBitsSet(numBits: NewBits, loBitsSet: OldBits);
1110 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: NVT);
1111 SDValue Add = matcher.getNode(ISD::ADD, dl, NVT, Op1, Op2);
1112 return matcher.getNode(ISD::UMIN, dl, NVT, Add, SatMax);
1113 }
1114
1115 bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
1116
1117 // FIXME: We need vp-aware PromotedInteger functions.
1118 if (IsShift) {
1119 Op1 = GetPromotedInteger(Op: Op1);
1120 Op2 = ZExtPromotedInteger(Op: Op2);
1121 } else {
1122 Op1 = SExtPromotedInteger(Op: Op1);
1123 Op2 = SExtPromotedInteger(Op: Op2);
1124 }
1125 EVT PromotedType = Op1.getValueType();
1126 unsigned NewBits = PromotedType.getScalarSizeInBits();
1127
1128 // Shift cannot use a min/max expansion, we can't detect overflow if all of
1129 // the bits have been shifted out.
1130 if (IsShift || matcher.isOperationLegal(Opcode, PromotedType)) {
1131 unsigned ShiftOp;
1132 switch (Opcode) {
1133 case ISD::SADDSAT:
1134 case ISD::SSUBSAT:
1135 case ISD::SSHLSAT:
1136 ShiftOp = ISD::SRA;
1137 break;
1138 case ISD::USHLSAT:
1139 ShiftOp = ISD::SRL;
1140 break;
1141 default:
1142 llvm_unreachable("Expected opcode to be signed or unsigned saturation "
1143 "addition, subtraction or left shift");
1144 }
1145
1146 unsigned SHLAmount = NewBits - OldBits;
1147 SDValue ShiftAmount =
1148 DAG.getShiftAmountConstant(Val: SHLAmount, VT: PromotedType, DL: dl);
1149 Op1 = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1, N2: ShiftAmount);
1150 if (!IsShift)
1151 Op2 = matcher.getNode(ISD::SHL, dl, PromotedType, Op2, ShiftAmount);
1152
1153 SDValue Result = matcher.getNode(Opcode, dl, PromotedType, Op1, Op2);
1154 return matcher.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
1155 }
1156
1157 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
1158 APInt MinVal = APInt::getSignedMinValue(numBits: OldBits).sext(width: NewBits);
1159 APInt MaxVal = APInt::getSignedMaxValue(numBits: OldBits).sext(width: NewBits);
1160 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT: PromotedType);
1161 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT: PromotedType);
1162 SDValue Result = matcher.getNode(AddOp, dl, PromotedType, Op1, Op2);
1163 Result = matcher.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
1164 Result = matcher.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
1165 return Result;
1166}
1167
1168SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
1169 // Can just promote the operands then continue with operation.
1170 SDLoc dl(N);
1171 SDValue Op1Promoted, Op2Promoted;
1172 bool Signed =
1173 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
1174 bool Saturating =
1175 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
1176 if (Signed) {
1177 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1178 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1179 } else {
1180 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1181 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1182 }
1183 EVT OldType = N->getOperand(Num: 0).getValueType();
1184 EVT PromotedType = Op1Promoted.getValueType();
1185 unsigned DiffSize =
1186 PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
1187
1188 if (Saturating) {
1189 // Promoting the operand and result values changes the saturation width,
1190 // which is extends the values that we clamp to on saturation. This could be
1191 // resolved by shifting one of the operands the same amount, which would
1192 // also shift the result we compare against, then shifting back.
1193 Op1Promoted =
1194 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1195 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1196 SDValue Result = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1197 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1198 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
1199 return DAG.getNode(Opcode: ShiftOp, DL: dl, VT: PromotedType, N1: Result,
1200 N2: DAG.getShiftAmountConstant(Val: DiffSize, VT: PromotedType, DL: dl));
1201 }
1202 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted, N2: Op2Promoted,
1203 N3: N->getOperand(Num: 2));
1204}
1205
1206static SDValue SaturateWidenedDIVFIX(SDValue V, SDLoc &dl,
1207 unsigned SatW, bool Signed,
1208 const TargetLowering &TLI,
1209 SelectionDAG &DAG) {
1210 EVT VT = V.getValueType();
1211 unsigned VTW = VT.getScalarSizeInBits();
1212
1213 if (!Signed) {
1214 // Saturate to the unsigned maximum by getting the minimum of V and the
1215 // maximum.
1216 return DAG.getNode(Opcode: ISD::UMIN, DL: dl, VT, N1: V,
1217 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW),
1218 DL: dl, VT));
1219 }
1220
1221 // Saturate to the signed maximum (the low SatW - 1 bits) by taking the
1222 // signed minimum of it and V.
1223 V = DAG.getNode(Opcode: ISD::SMIN, DL: dl, VT, N1: V,
1224 N2: DAG.getConstant(Val: APInt::getLowBitsSet(numBits: VTW, loBitsSet: SatW - 1),
1225 DL: dl, VT));
1226 // Saturate to the signed minimum (the high SatW + 1 bits) by taking the
1227 // signed maximum of it and V.
1228 V = DAG.getNode(Opcode: ISD::SMAX, DL: dl, VT, N1: V,
1229 N2: DAG.getConstant(Val: APInt::getHighBitsSet(numBits: VTW, hiBitsSet: VTW - SatW + 1),
1230 DL: dl, VT));
1231 return V;
1232}
1233
1234static SDValue earlyExpandDIVFIX(SDNode *N, SDValue LHS, SDValue RHS,
1235 unsigned Scale, const TargetLowering &TLI,
1236 SelectionDAG &DAG, unsigned SatW = 0) {
1237 EVT VT = LHS.getValueType();
1238 unsigned VTSize = VT.getScalarSizeInBits();
1239 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1240 N->getOpcode() == ISD::SDIVFIXSAT;
1241 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1242 N->getOpcode() == ISD::UDIVFIXSAT;
1243
1244 SDLoc dl(N);
1245 // Widen the types by a factor of two. This is guaranteed to expand, since it
1246 // will always have enough high bits in the LHS to shift into.
1247 EVT WideVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: VTSize * 2);
1248 if (VT.isVector())
1249 WideVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: WideVT,
1250 EC: VT.getVectorElementCount());
1251 LHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: LHS, DL: dl, VT: WideVT);
1252 RHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: RHS, DL: dl, VT: WideVT);
1253 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS, RHS, Scale,
1254 DAG);
1255 assert(Res && "Expanding DIVFIX with wide type failed?");
1256 if (Saturating) {
1257 // If the caller has told us to saturate at something less, use that width
1258 // instead of the type before doubling. However, it cannot be more than
1259 // what we just widened!
1260 assert(SatW <= VTSize &&
1261 "Tried to saturate to more than the original type?");
1262 Res = SaturateWidenedDIVFIX(V: Res, dl, SatW: SatW == 0 ? VTSize : SatW, Signed,
1263 TLI, DAG);
1264 }
1265 return DAG.getZExtOrTrunc(Op: Res, DL: dl, VT);
1266}
1267
1268SDValue DAGTypeLegalizer::PromoteIntRes_DIVFIX(SDNode *N) {
1269 SDLoc dl(N);
1270 SDValue Op1Promoted, Op2Promoted;
1271 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1272 N->getOpcode() == ISD::SDIVFIXSAT;
1273 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1274 N->getOpcode() == ISD::UDIVFIXSAT;
1275 if (Signed) {
1276 Op1Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1277 Op2Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1278 } else {
1279 Op1Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1280 Op2Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1281 }
1282 EVT PromotedType = Op1Promoted.getValueType();
1283 unsigned Scale = N->getConstantOperandVal(Num: 2);
1284
1285 // If the type is already legal and the operation is legal in that type, we
1286 // should not early expand.
1287 if (TLI.isTypeLegal(VT: PromotedType)) {
1288 TargetLowering::LegalizeAction Action =
1289 TLI.getFixedPointOperationAction(Op: N->getOpcode(), VT: PromotedType, Scale);
1290 if (Action == TargetLowering::Legal || Action == TargetLowering::Custom) {
1291 unsigned Diff = PromotedType.getScalarSizeInBits() -
1292 N->getValueType(ResNo: 0).getScalarSizeInBits();
1293 if (Saturating)
1294 Op1Promoted =
1295 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: PromotedType, N1: Op1Promoted,
1296 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1297 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: PromotedType, N1: Op1Promoted,
1298 N2: Op2Promoted, N3: N->getOperand(Num: 2));
1299 if (Saturating)
1300 Res = DAG.getNode(Opcode: Signed ? ISD::SRA : ISD::SRL, DL: dl, VT: PromotedType, N1: Res,
1301 N2: DAG.getShiftAmountConstant(Val: Diff, VT: PromotedType, DL: dl));
1302 return Res;
1303 }
1304 }
1305
1306 // See if we can perform the division in this type without expanding.
1307 if (SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: Op1Promoted,
1308 RHS: Op2Promoted, Scale, DAG)) {
1309 if (Saturating)
1310 Res = SaturateWidenedDIVFIX(V: Res, dl,
1311 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits(),
1312 Signed, TLI, DAG);
1313 return Res;
1314 }
1315 // If we cannot, expand it to twice the type width. If we are saturating, give
1316 // it the original width as a saturating width so we don't need to emit
1317 // two saturations.
1318 return earlyExpandDIVFIX(N, LHS: Op1Promoted, RHS: Op2Promoted, Scale, TLI, DAG,
1319 SatW: N->getValueType(ResNo: 0).getScalarSizeInBits());
1320}
1321
1322SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
1323 if (ResNo == 1)
1324 return PromoteIntRes_Overflow(N);
1325
1326 // The operation overflowed iff the result in the larger type is not the
1327 // sign extension of its truncation to the original type.
1328 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1329 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1330 EVT OVT = N->getOperand(Num: 0).getValueType();
1331 EVT NVT = LHS.getValueType();
1332 SDLoc dl(N);
1333
1334 // Do the arithmetic in the larger type.
1335 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
1336 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1337
1338 // Calculate the overflow flag: sign extend the arithmetic result from
1339 // the original type.
1340 SDValue Ofl = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: NVT, N1: Res,
1341 N2: DAG.getValueType(OVT));
1342 // Overflowed if and only if this is not equal to Res.
1343 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1344
1345 // Use the calculated overflow everywhere.
1346 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1347
1348 return Res;
1349}
1350
1351SDValue DAGTypeLegalizer::PromoteIntRes_CMP(SDNode *N) {
1352 EVT PromotedResultTy =
1353 TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1354 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: PromotedResultTy,
1355 N1: N->getOperand(Num: 0), N2: N->getOperand(Num: 1));
1356}
1357
1358SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
1359 SDValue Mask = N->getOperand(Num: 0);
1360
1361 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1362 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1363
1364 unsigned Opcode = N->getOpcode();
1365 if (Opcode == ISD::VP_SELECT || Opcode == ISD::VP_MERGE)
1366 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS,
1367 N4: N->getOperand(Num: 3));
1368 return DAG.getNode(Opcode, DL: SDLoc(N), VT: LHS.getValueType(), N1: Mask, N2: LHS, N3: RHS);
1369}
1370
1371SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
1372 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 2));
1373 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 3));
1374 return DAG.getNode(Opcode: ISD::SELECT_CC, DL: SDLoc(N),
1375 VT: LHS.getValueType(), N1: N->getOperand(Num: 0),
1376 N2: N->getOperand(Num: 1), N3: LHS, N4: RHS, N5: N->getOperand(Num: 4));
1377}
1378
1379SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
1380 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
1381 EVT InVT = N->getOperand(Num: OpNo).getValueType();
1382 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1383
1384 EVT SVT = getSetCCResultType(VT: InVT);
1385
1386 // If we got back a type that needs to be promoted, this likely means the
1387 // the input type also needs to be promoted. So get the promoted type for
1388 // the input and try the query again.
1389 if (getTypeAction(VT: SVT) == TargetLowering::TypePromoteInteger) {
1390 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
1391 InVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
1392 SVT = getSetCCResultType(VT: InVT);
1393 } else {
1394 // Input type isn't promoted, just use the default promoted type.
1395 SVT = NVT;
1396 }
1397 }
1398
1399 SDLoc dl(N);
1400 assert(SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() &&
1401 "Vector compare must return a vector result!");
1402
1403 // Get the SETCC result using the canonical SETCC type.
1404 SDValue SetCC;
1405 if (N->isStrictFPOpcode()) {
1406 SDVTList VTs = DAG.getVTList(VTs: {SVT, MVT::Other});
1407 SDValue Opers[] = {N->getOperand(Num: 0), N->getOperand(Num: 1),
1408 N->getOperand(Num: 2), N->getOperand(Num: 3)};
1409 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: VTs, Ops: Opers, Flags: N->getFlags());
1410 // Legalize the chain result - switch anything that used the old chain to
1411 // use the new one.
1412 ReplaceValueWith(From: SDValue(N, 1), To: SetCC.getValue(R: 1));
1413 } else
1414 SetCC = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: SVT, N1: N->getOperand(Num: 0),
1415 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), Flags: N->getFlags());
1416
1417 // Convert to the expected type.
1418 return DAG.getSExtOrTrunc(Op: SetCC, DL: dl, VT: NVT);
1419}
1420
1421SDValue DAGTypeLegalizer::PromoteIntRes_IS_FPCLASS(SDNode *N) {
1422 SDLoc DL(N);
1423 SDValue Arg = N->getOperand(Num: 0);
1424 SDValue Test = N->getOperand(Num: 1);
1425 EVT NResVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1426 return DAG.getNode(Opcode: ISD::IS_FPCLASS, DL, VT: NResVT, N1: Arg, N2: Test);
1427}
1428
1429SDValue DAGTypeLegalizer::PromoteIntRes_FFREXP(SDNode *N) {
1430 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 1));
1431 EVT VT = N->getValueType(ResNo: 0);
1432
1433 SDLoc dl(N);
1434 SDValue Res =
1435 DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: NVT), N: N->getOperand(Num: 0));
1436
1437 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1438 return Res.getValue(R: 1);
1439}
1440
1441SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
1442 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1443 SDValue RHS = N->getOperand(Num: 1);
1444 if (N->getOpcode() != ISD::VP_SHL) {
1445 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1446 RHS = ZExtPromotedInteger(Op: RHS);
1447
1448 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1449 }
1450
1451 SDValue Mask = N->getOperand(Num: 2);
1452 SDValue EVL = N->getOperand(Num: 3);
1453 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1454 RHS = VPZExtPromotedInteger(Op: RHS, Mask, EVL);
1455 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1456 N3: Mask, N4: EVL);
1457}
1458
1459SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
1460 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
1461 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: SDLoc(N),
1462 VT: Op.getValueType(), N1: Op, N2: N->getOperand(Num: 1));
1463}
1464
1465SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
1466 // The input may have strange things in the top bits of the registers, but
1467 // these operations don't care. They may have weird bits going out, but
1468 // that too is okay if they are integer operations.
1469 SDValue LHS = GetPromotedInteger(Op: N->getOperand(Num: 0));
1470 SDValue RHS = GetPromotedInteger(Op: N->getOperand(Num: 1));
1471 if (N->getNumOperands() == 2)
1472 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1473 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1474 assert(N->isVPOpcode() && "Expected VP opcode");
1475 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1476 N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
1477}
1478
1479SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
1480 if (N->getNumOperands() == 2) {
1481 // Sign extend the input.
1482 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1483 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1484 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1485 }
1486 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1487 assert(N->isVPOpcode() && "Expected VP opcode");
1488 SDValue Mask = N->getOperand(Num: 2);
1489 SDValue EVL = N->getOperand(Num: 3);
1490 // Sign extend the input.
1491 SDValue LHS = VPSExtPromotedInteger(Op: N->getOperand(Num: 0), Mask, EVL);
1492 SDValue RHS = VPSExtPromotedInteger(Op: N->getOperand(Num: 1), Mask, EVL);
1493 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1494 N3: Mask, N4: EVL);
1495}
1496
1497SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
1498 if (N->getNumOperands() == 2) {
1499 // Zero extend the input.
1500 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1501 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1502 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1503 }
1504 assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1505 assert(N->isVPOpcode() && "Expected VP opcode");
1506 // Zero extend the input.
1507 SDValue Mask = N->getOperand(Num: 2);
1508 SDValue EVL = N->getOperand(Num: 3);
1509 SDValue LHS = VPZExtPromotedInteger(Op: N->getOperand(Num: 0), Mask, EVL);
1510 SDValue RHS = VPZExtPromotedInteger(Op: N->getOperand(Num: 1), Mask, EVL);
1511 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1512 N3: Mask, N4: EVL);
1513}
1514
1515SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
1516 SDValue LHS = N->getOperand(Num: 0);
1517 SDValue RHS = N->getOperand(Num: 1);
1518
1519 // It doesn't matter if we sign extend or zero extend in the inputs. So do
1520 // whatever is best for the target and the promoted operands.
1521 SExtOrZExtPromotedOperands(LHS, RHS);
1522
1523 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N),
1524 VT: LHS.getValueType(), N1: LHS, N2: RHS);
1525}
1526
1527SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
1528 SDValue RHS = N->getOperand(Num: 1);
1529 if (N->getOpcode() != ISD::VP_SRA) {
1530 // The input value must be properly sign extended.
1531 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1532 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1533 RHS = ZExtPromotedInteger(Op: RHS);
1534 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1535 }
1536
1537 SDValue Mask = N->getOperand(Num: 2);
1538 SDValue EVL = N->getOperand(Num: 3);
1539 // The input value must be properly sign extended.
1540 SDValue LHS = VPSExtPromotedInteger(Op: N->getOperand(Num: 0), Mask, EVL);
1541 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1542 RHS = VPZExtPromotedInteger(Op: RHS, Mask, EVL);
1543 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1544 N3: Mask, N4: EVL);
1545}
1546
1547SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
1548 SDValue RHS = N->getOperand(Num: 1);
1549 if (N->getOpcode() != ISD::VP_SRL) {
1550 // The input value must be properly zero extended.
1551 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1552 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1553 RHS = ZExtPromotedInteger(Op: RHS);
1554 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS);
1555 }
1556
1557 SDValue Mask = N->getOperand(Num: 2);
1558 SDValue EVL = N->getOperand(Num: 3);
1559 // The input value must be properly zero extended.
1560 SDValue LHS = VPZExtPromotedInteger(Op: N->getOperand(Num: 0), Mask, EVL);
1561 if (getTypeAction(VT: RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1562 RHS = VPZExtPromotedInteger(Op: RHS, Mask, EVL);
1563 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: LHS.getValueType(), N1: LHS, N2: RHS,
1564 N3: Mask, N4: EVL);
1565}
1566
1567SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
1568 // Lower the rotate to shifts and ORs which can be promoted.
1569 SDValue Res = TLI.expandROT(N, AllowVectorOps: true /*AllowVectorOps*/, DAG);
1570 ReplaceValueWith(From: SDValue(N, 0), To: Res);
1571 return SDValue();
1572}
1573
1574SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
1575 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 0));
1576 SDValue Lo = GetPromotedInteger(Op: N->getOperand(Num: 1));
1577 SDValue Amt = N->getOperand(Num: 2);
1578 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1579 Amt = ZExtPromotedInteger(Op: Amt);
1580 EVT AmtVT = Amt.getValueType();
1581
1582 SDLoc DL(N);
1583 EVT OldVT = N->getOperand(Num: 0).getValueType();
1584 EVT VT = Lo.getValueType();
1585 unsigned Opcode = N->getOpcode();
1586 bool IsFSHR = Opcode == ISD::FSHR;
1587 unsigned OldBits = OldVT.getScalarSizeInBits();
1588 unsigned NewBits = VT.getScalarSizeInBits();
1589
1590 // Amount has to be interpreted modulo the old bit width.
1591 Amt = DAG.getNode(Opcode: ISD::UREM, DL, VT: AmtVT, N1: Amt,
1592 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT));
1593
1594 // If the promoted type is twice the size (or more), then we use the
1595 // traditional funnel 'double' shift codegen. This isn't necessary if the
1596 // shift amount is constant.
1597 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1598 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1599 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1600 !TLI.isOperationLegalOrCustom(Op: Opcode, VT)) {
1601 SDValue HiShift = DAG.getConstant(Val: OldBits, DL, VT);
1602 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi, N2: HiShift);
1603 Lo = DAG.getZeroExtendInReg(Op: Lo, DL, VT: OldVT);
1604 SDValue Res = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: Hi, N2: Lo);
1605 Res = DAG.getNode(Opcode: IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, N1: Res, N2: Amt);
1606 if (!IsFSHR)
1607 Res = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Res, N2: HiShift);
1608 return Res;
1609 }
1610
1611 // Shift Lo up to occupy the upper bits of the promoted type.
1612 SDValue ShiftOffset = DAG.getConstant(Val: NewBits - OldBits, DL, VT: AmtVT);
1613 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Lo, N2: ShiftOffset);
1614
1615 // Increase Amount to shift the result into the lower bits of the promoted
1616 // type.
1617 if (IsFSHR)
1618 Amt = DAG.getNode(Opcode: ISD::ADD, DL, VT: AmtVT, N1: Amt, N2: ShiftOffset);
1619
1620 return DAG.getNode(Opcode, DL, VT, N1: Hi, N2: Lo, N3: Amt);
1621}
1622
1623// A vp version of PromoteIntRes_FunnelShift.
1624SDValue DAGTypeLegalizer::PromoteIntRes_VPFunnelShift(SDNode *N) {
1625 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 0));
1626 SDValue Lo = GetPromotedInteger(Op: N->getOperand(Num: 1));
1627 SDValue Amt = N->getOperand(Num: 2);
1628 SDValue Mask = N->getOperand(Num: 3);
1629 SDValue EVL = N->getOperand(Num: 4);
1630 if (getTypeAction(VT: Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1631 Amt = VPZExtPromotedInteger(Op: Amt, Mask, EVL);
1632 EVT AmtVT = Amt.getValueType();
1633
1634 SDLoc DL(N);
1635 EVT OldVT = N->getOperand(Num: 0).getValueType();
1636 EVT VT = Lo.getValueType();
1637 unsigned Opcode = N->getOpcode();
1638 bool IsFSHR = Opcode == ISD::VP_FSHR;
1639 unsigned OldBits = OldVT.getScalarSizeInBits();
1640 unsigned NewBits = VT.getScalarSizeInBits();
1641
1642 // Amount has to be interpreted modulo the old bit width.
1643 Amt = DAG.getNode(Opcode: ISD::VP_UREM, DL, VT: AmtVT, N1: Amt,
1644 N2: DAG.getConstant(Val: OldBits, DL, VT: AmtVT), N3: Mask, N4: EVL);
1645
1646 // If the promoted type is twice the size (or more), then we use the
1647 // traditional funnel 'double' shift codegen. This isn't necessary if the
1648 // shift amount is constant.
1649 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1650 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1651 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Val: Amt) &&
1652 !TLI.isOperationLegalOrCustom(Op: Opcode, VT)) {
1653 SDValue HiShift = DAG.getConstant(Val: OldBits, DL, VT);
1654 Hi = DAG.getNode(Opcode: ISD::VP_SHL, DL, VT, N1: Hi, N2: HiShift, N3: Mask, N4: EVL);
1655 Lo = DAG.getVPZeroExtendInReg(Op: Lo, Mask, EVL, DL, VT: OldVT);
1656 SDValue Res = DAG.getNode(Opcode: ISD::VP_OR, DL, VT, N1: Hi, N2: Lo, N3: Mask, N4: EVL);
1657 Res = DAG.getNode(Opcode: IsFSHR ? ISD::VP_SRL : ISD::VP_SHL, DL, VT, N1: Res, N2: Amt,
1658 N3: Mask, N4: EVL);
1659 if (!IsFSHR)
1660 Res = DAG.getNode(Opcode: ISD::VP_SRL, DL, VT, N1: Res, N2: HiShift, N3: Mask, N4: EVL);
1661 return Res;
1662 }
1663
1664 // Shift Lo up to occupy the upper bits of the promoted type.
1665 SDValue ShiftOffset = DAG.getConstant(Val: NewBits - OldBits, DL, VT: AmtVT);
1666 Lo = DAG.getNode(Opcode: ISD::VP_SHL, DL, VT, N1: Lo, N2: ShiftOffset, N3: Mask, N4: EVL);
1667
1668 // Increase Amount to shift the result into the lower bits of the promoted
1669 // type.
1670 if (IsFSHR)
1671 Amt = DAG.getNode(Opcode: ISD::VP_ADD, DL, VT: AmtVT, N1: Amt, N2: ShiftOffset, N3: Mask, N4: EVL);
1672
1673 return DAG.getNode(Opcode, DL, VT, N1: Hi, N2: Lo, N3: Amt, N4: Mask, N5: EVL);
1674}
1675
1676SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
1677 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1678 SDValue Res;
1679 SDValue InOp = N->getOperand(Num: 0);
1680 SDLoc dl(N);
1681
1682 switch (getTypeAction(VT: InOp.getValueType())) {
1683 default: llvm_unreachable("Unknown type action!");
1684 case TargetLowering::TypeLegal:
1685 case TargetLowering::TypeExpandInteger:
1686 Res = InOp;
1687 break;
1688 case TargetLowering::TypePromoteInteger:
1689 Res = GetPromotedInteger(Op: InOp);
1690 break;
1691 case TargetLowering::TypeSplitVector: {
1692 EVT InVT = InOp.getValueType();
1693 assert(InVT.isVector() && "Cannot split scalar types");
1694 ElementCount NumElts = InVT.getVectorElementCount();
1695 assert(NumElts == NVT.getVectorElementCount() &&
1696 "Dst and Src must have the same number of elements");
1697 assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&
1698 "Promoted vector type must be a power of two");
1699
1700 SDValue EOp1, EOp2;
1701 GetSplitVector(Op: InOp, Lo&: EOp1, Hi&: EOp2);
1702
1703 EVT HalfNVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getScalarType(),
1704 EC: NumElts.divideCoefficientBy(RHS: 2));
1705 if (N->getOpcode() == ISD::TRUNCATE) {
1706 EOp1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp1);
1707 EOp2 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: HalfNVT, Operand: EOp2);
1708 } else {
1709 assert(N->getOpcode() == ISD::VP_TRUNCATE &&
1710 "Expected VP_TRUNCATE opcode");
1711 SDValue MaskLo, MaskHi, EVLLo, EVLHi;
1712 std::tie(args&: MaskLo, args&: MaskHi) = SplitMask(Mask: N->getOperand(Num: 1));
1713 std::tie(args&: EVLLo, args&: EVLHi) =
1714 DAG.SplitEVL(N: N->getOperand(Num: 2), VecVT: N->getValueType(ResNo: 0), DL: dl);
1715 EOp1 = DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: HalfNVT, N1: EOp1, N2: MaskLo, N3: EVLLo);
1716 EOp2 = DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: HalfNVT, N1: EOp2, N2: MaskHi, N3: EVLHi);
1717 }
1718 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL: dl, VT: NVT, N1: EOp1, N2: EOp2);
1719 }
1720 // TODO: VP_TRUNCATE need to handle when TypeWidenVector access to some
1721 // targets.
1722 case TargetLowering::TypeWidenVector: {
1723 SDValue WideInOp = GetWidenedVector(Op: InOp);
1724
1725 // Truncate widened InOp.
1726 unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
1727 EVT TruncVT = EVT::getVectorVT(Context&: *DAG.getContext(),
1728 VT: N->getValueType(ResNo: 0).getScalarType(), NumElements: NumElem);
1729 SDValue WideTrunc = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: TruncVT, Operand: WideInOp);
1730
1731 // Zero extend so that the elements are of same type as those of NVT
1732 EVT ExtVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: NVT.getVectorElementType(),
1733 NumElements: NumElem);
1734 SDValue WideExt = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: ExtVT, Operand: WideTrunc);
1735
1736 // Extract the low NVT subvector.
1737 SDValue ZeroIdx = DAG.getVectorIdxConstant(Val: 0, DL: dl);
1738 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NVT, N1: WideExt, N2: ZeroIdx);
1739 }
1740 }
1741
1742 // Truncate to NVT instead of VT
1743 if (N->getOpcode() == ISD::VP_TRUNCATE)
1744 return DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: dl, VT: NVT, N1: Res, N2: N->getOperand(Num: 1),
1745 N3: N->getOperand(Num: 2));
1746 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Res);
1747}
1748
1749SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
1750 if (ResNo == 1)
1751 return PromoteIntRes_Overflow(N);
1752
1753 // The operation overflowed iff the result in the larger type is not the
1754 // zero extension of its truncation to the original type.
1755 SDValue LHS = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
1756 SDValue RHS = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
1757 EVT OVT = N->getOperand(Num: 0).getValueType();
1758 EVT NVT = LHS.getValueType();
1759 SDLoc dl(N);
1760
1761 // Do the arithmetic in the larger type.
1762 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1763 SDValue Res = DAG.getNode(Opcode, DL: dl, VT: NVT, N1: LHS, N2: RHS);
1764
1765 // Calculate the overflow flag: zero extend the arithmetic result from
1766 // the original type.
1767 SDValue Ofl = DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: OVT);
1768 // Overflowed if and only if this is not equal to Res.
1769 Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Ofl, RHS: Res, Cond: ISD::SETNE);
1770
1771 // Use the calculated overflow everywhere.
1772 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
1773
1774 return Res;
1775}
1776
1777// Handle promotion for the ADDE/SUBE/UADDO_CARRY/USUBO_CARRY nodes. Notice that
1778// the third operand of ADDE/SUBE nodes is carry flag, which differs from
1779// the UADDO_CARRY/USUBO_CARRY nodes in that the third operand is carry Boolean.
1780SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO_CARRY(SDNode *N,
1781 unsigned ResNo) {
1782 if (ResNo == 1)
1783 return PromoteIntRes_Overflow(N);
1784
1785 // We need to sign-extend the operands so the carry value computed by the
1786 // wide operation will be equivalent to the carry value computed by the
1787 // narrow operation.
1788 // An UADDO_CARRY can generate carry only if any of the operands has its
1789 // most significant bit set. Sign extension propagates the most significant
1790 // bit into the higher bits which means the extra bit that the narrow
1791 // addition would need (i.e. the carry) will be propagated through the higher
1792 // bits of the wide addition.
1793 // A USUBO_CARRY can generate borrow only if LHS < RHS and this property will
1794 // be preserved by sign extension.
1795 SDValue LHS = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1796 SDValue RHS = SExtPromotedInteger(Op: N->getOperand(Num: 1));
1797
1798 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(ResNo: 1)};
1799
1800 // Do the arithmetic in the wide type.
1801 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VTList: DAG.getVTList(VTs: ValueVTs),
1802 N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
1803
1804 // Update the users of the original carry/borrow value.
1805 ReplaceValueWith(From: SDValue(N, 1), To: Res.getValue(R: 1));
1806
1807 return SDValue(Res.getNode(), 0);
1808}
1809
1810SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO_CARRY(SDNode *N,
1811 unsigned ResNo) {
1812 assert(ResNo == 1 && "Don't know how to promote other results yet.");
1813 return PromoteIntRes_Overflow(N);
1814}
1815
1816SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
1817 EVT OVT = N->getValueType(ResNo: 0);
1818 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OVT);
1819
1820 // If a larger ABS or SMAX isn't supported by the target, try to expand now.
1821 // If we expand later we'll end up sign extending more than just the sra input
1822 // in sra+xor+sub expansion.
1823 if (!OVT.isVector() &&
1824 !TLI.isOperationLegalOrCustomOrPromote(Op: ISD::ABS, VT: NVT) &&
1825 !TLI.isOperationLegal(Op: ISD::SMAX, VT: NVT)) {
1826 if (SDValue Res = TLI.expandABS(N, DAG))
1827 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand: Res);
1828 }
1829
1830 SDValue Op0 = SExtPromotedInteger(Op: N->getOperand(Num: 0));
1831 return DAG.getNode(Opcode: ISD::ABS, DL: SDLoc(N), VT: Op0.getValueType(), Operand: Op0);
1832}
1833
1834SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
1835 // Promote the overflow bit trivially.
1836 if (ResNo == 1)
1837 return PromoteIntRes_Overflow(N);
1838
1839 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
1840 SDLoc DL(N);
1841 EVT SmallVT = LHS.getValueType();
1842
1843 // To determine if the result overflowed in a larger type, we extend the
1844 // input to the larger type, do the multiply (checking if it overflows),
1845 // then also check the high bits of the result to see if overflow happened
1846 // there.
1847 if (N->getOpcode() == ISD::SMULO) {
1848 LHS = SExtPromotedInteger(Op: LHS);
1849 RHS = SExtPromotedInteger(Op: RHS);
1850 } else {
1851 LHS = ZExtPromotedInteger(Op: LHS);
1852 RHS = ZExtPromotedInteger(Op: RHS);
1853 }
1854 SDVTList VTs = DAG.getVTList(VT1: LHS.getValueType(), VT2: N->getValueType(ResNo: 1));
1855 SDValue Mul = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N1: LHS, N2: RHS);
1856
1857 // Overflow occurred if it occurred in the larger type, or if the high part
1858 // of the result does not zero/sign-extend the low part. Check this second
1859 // possibility first.
1860 SDValue Overflow;
1861 if (N->getOpcode() == ISD::UMULO) {
1862 // Unsigned overflow occurred if the high part is non-zero.
1863 unsigned Shift = SmallVT.getScalarSizeInBits();
1864 SDValue Hi =
1865 DAG.getNode(Opcode: ISD::SRL, DL, VT: Mul.getValueType(), N1: Mul,
1866 N2: DAG.getShiftAmountConstant(Val: Shift, VT: Mul.getValueType(), DL));
1867 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: Hi,
1868 RHS: DAG.getConstant(Val: 0, DL, VT: Hi.getValueType()),
1869 Cond: ISD::SETNE);
1870 } else {
1871 // Signed overflow occurred if the high part does not sign extend the low.
1872 SDValue SExt = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT: Mul.getValueType(),
1873 N1: Mul, N2: DAG.getValueType(SmallVT));
1874 Overflow = DAG.getSetCC(DL, VT: N->getValueType(ResNo: 1), LHS: SExt, RHS: Mul, Cond: ISD::SETNE);
1875 }
1876
1877 // The only other way for overflow to occur is if the multiplication in the
1878 // larger type itself overflowed.
1879 Overflow = DAG.getNode(Opcode: ISD::OR, DL, VT: N->getValueType(ResNo: 1), N1: Overflow,
1880 N2: SDValue(Mul.getNode(), 1));
1881
1882 // Use the calculated overflow everywhere.
1883 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
1884 return Mul;
1885}
1886
1887SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
1888 return DAG.getUNDEF(VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(),
1889 VT: N->getValueType(ResNo: 0)));
1890}
1891
1892SDValue DAGTypeLegalizer::PromoteIntRes_VSCALE(SDNode *N) {
1893 EVT VT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1894
1895 const APInt &MulImm = N->getConstantOperandAPInt(Num: 0);
1896 return DAG.getVScale(DL: SDLoc(N), VT, MulImm: MulImm.sext(width: VT.getSizeInBits()));
1897}
1898
1899SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
1900 SDValue Chain = N->getOperand(Num: 0); // Get the chain.
1901 SDValue Ptr = N->getOperand(Num: 1); // Get the pointer.
1902 EVT VT = N->getValueType(ResNo: 0);
1903 SDLoc dl(N);
1904
1905 MVT RegVT = TLI.getRegisterType(Context&: *DAG.getContext(), VT);
1906 unsigned NumRegs = TLI.getNumRegisters(Context&: *DAG.getContext(), VT);
1907 // The argument is passed as NumRegs registers of type RegVT.
1908
1909 SmallVector<SDValue, 8> Parts(NumRegs);
1910 for (unsigned i = 0; i < NumRegs; ++i) {
1911 Parts[i] = DAG.getVAArg(VT: RegVT, dl, Chain, Ptr, SV: N->getOperand(Num: 2),
1912 Align: N->getConstantOperandVal(Num: 3));
1913 Chain = Parts[i].getValue(R: 1);
1914 }
1915
1916 // Handle endianness of the load.
1917 if (DAG.getDataLayout().isBigEndian())
1918 std::reverse(first: Parts.begin(), last: Parts.end());
1919
1920 // Assemble the parts in the promoted type.
1921 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
1922 SDValue Res = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[0]);
1923 for (unsigned i = 1; i < NumRegs; ++i) {
1924 SDValue Part = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Parts[i]);
1925 // Shift it to the right position and "or" it in.
1926 Part = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Part,
1927 N2: DAG.getConstant(Val: i * RegVT.getSizeInBits(), DL: dl,
1928 VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
1929 Res = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Res, N2: Part);
1930 }
1931
1932 // Modified the chain result - switch anything that used the old chain to
1933 // use the new one.
1934 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
1935
1936 return Res;
1937}
1938
1939//===----------------------------------------------------------------------===//
1940// Integer Operand Promotion
1941//===----------------------------------------------------------------------===//
1942
1943/// PromoteIntegerOperand - This method is called when the specified operand of
1944/// the specified node is found to need promotion. At this point, all of the
1945/// result types of the node are known to be legal, but other operands of the
1946/// node may need promotion or expansion as well as the specified one.
1947bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
1948 LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG));
1949 SDValue Res = SDValue();
1950 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false)) {
1951 LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
1952 return false;
1953 }
1954
1955 switch (N->getOpcode()) {
1956 default:
1957 #ifndef NDEBUG
1958 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
1959 N->dump(&DAG); dbgs() << "\n";
1960 #endif
1961 report_fatal_error(reason: "Do not know how to promote this operator's operand!");
1962
1963 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
1964 case ISD::ATOMIC_STORE:
1965 Res = PromoteIntOp_ATOMIC_STORE(N: cast<AtomicSDNode>(Val: N));
1966 break;
1967 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
1968 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
1969 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
1970 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
1971 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
1972 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
1973 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
1974 case ISD::FAKE_USE:
1975 Res = PromoteIntOp_FAKE_USE(N);
1976 break;
1977 case ISD::INSERT_VECTOR_ELT:
1978 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);
1979 break;
1980 case ISD::SPLAT_VECTOR:
1981 case ISD::SCALAR_TO_VECTOR:
1982 case ISD::EXPERIMENTAL_VP_SPLAT:
1983 Res = PromoteIntOp_ScalarOp(N);
1984 break;
1985 case ISD::VSELECT:
1986 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
1987 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
1988 case ISD::VP_SETCC:
1989 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
1990 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
1991 case ISD::VP_SIGN_EXTEND: Res = PromoteIntOp_VP_SIGN_EXTEND(N); break;
1992 case ISD::VP_SINT_TO_FP:
1993 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
1994 case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
1995 case ISD::STORE: Res = PromoteIntOp_STORE(N: cast<StoreSDNode>(Val: N),
1996 OpNo); break;
1997 case ISD::VP_STORE:
1998 Res = PromoteIntOp_VP_STORE(N: cast<VPStoreSDNode>(Val: N), OpNo);
1999 break;
2000 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(N: cast<MaskedStoreSDNode>(Val: N),
2001 OpNo); break;
2002 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(N: cast<MaskedLoadSDNode>(Val: N),
2003 OpNo); break;
2004 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(N: cast<MaskedGatherSDNode>(Val: N),
2005 OpNo); break;
2006 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(N: cast<MaskedScatterSDNode>(Val: N),
2007 OpNo); break;
2008 case ISD::VECTOR_COMPRESS:
2009 Res = PromoteIntOp_VECTOR_COMPRESS(N, OpNo);
2010 break;
2011 case ISD::VP_TRUNCATE:
2012 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
2013 case ISD::BF16_TO_FP:
2014 case ISD::FP16_TO_FP:
2015 case ISD::VP_UINT_TO_FP:
2016 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
2017 case ISD::STRICT_FP16_TO_FP:
2018 case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
2019 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
2020 case ISD::VP_ZERO_EXTEND: Res = PromoteIntOp_VP_ZERO_EXTEND(N); break;
2021 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
2022 case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break;
2023
2024 case ISD::SHL:
2025 case ISD::SRA:
2026 case ISD::SRL:
2027 case ISD::ROTL:
2028 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
2029
2030 case ISD::SCMP:
2031 case ISD::UCMP: Res = PromoteIntOp_CMP(N); break;
2032
2033 case ISD::FSHL:
2034 case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break;
2035
2036 case ISD::FRAMEADDR:
2037 case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
2038
2039 case ISD::SMULFIX:
2040 case ISD::SMULFIXSAT:
2041 case ISD::UMULFIX:
2042 case ISD::UMULFIXSAT:
2043 case ISD::SDIVFIX:
2044 case ISD::SDIVFIXSAT:
2045 case ISD::UDIVFIX:
2046 case ISD::UDIVFIXSAT: Res = PromoteIntOp_FIX(N); break;
2047 case ISD::FPOWI:
2048 case ISD::STRICT_FPOWI:
2049 case ISD::FLDEXP:
2050 case ISD::STRICT_FLDEXP: Res = PromoteIntOp_ExpOp(N); break;
2051 case ISD::VECREDUCE_ADD:
2052 case ISD::VECREDUCE_MUL:
2053 case ISD::VECREDUCE_AND:
2054 case ISD::VECREDUCE_OR:
2055 case ISD::VECREDUCE_XOR:
2056 case ISD::VECREDUCE_SMAX:
2057 case ISD::VECREDUCE_SMIN:
2058 case ISD::VECREDUCE_UMAX:
2059 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
2060 case ISD::VP_REDUCE_ADD:
2061 case ISD::VP_REDUCE_MUL:
2062 case ISD::VP_REDUCE_AND:
2063 case ISD::VP_REDUCE_OR:
2064 case ISD::VP_REDUCE_XOR:
2065 case ISD::VP_REDUCE_SMAX:
2066 case ISD::VP_REDUCE_SMIN:
2067 case ISD::VP_REDUCE_UMAX:
2068 case ISD::VP_REDUCE_UMIN:
2069 Res = PromoteIntOp_VP_REDUCE(N, OpNo);
2070 break;
2071
2072 case ISD::SET_ROUNDING: Res = PromoteIntOp_SET_ROUNDING(N); break;
2073 case ISD::STACKMAP:
2074 Res = PromoteIntOp_STACKMAP(N, OpNo);
2075 break;
2076 case ISD::PATCHPOINT:
2077 Res = PromoteIntOp_PATCHPOINT(N, OpNo);
2078 break;
2079 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
2080 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
2081 Res = PromoteIntOp_VP_STRIDED(N, OpNo);
2082 break;
2083 case ISD::EXPERIMENTAL_VP_SPLICE:
2084 Res = PromoteIntOp_VP_SPLICE(N, OpNo);
2085 break;
2086 case ISD::EXPERIMENTAL_VECTOR_HISTOGRAM:
2087 Res = PromoteIntOp_VECTOR_HISTOGRAM(N, OpNo);
2088 break;
2089 case ISD::VECTOR_FIND_LAST_ACTIVE:
2090 Res = PromoteIntOp_VECTOR_FIND_LAST_ACTIVE(N, OpNo);
2091 break;
2092 case ISD::GET_ACTIVE_LANE_MASK:
2093 Res = PromoteIntOp_GET_ACTIVE_LANE_MASK(N);
2094 break;
2095 case ISD::PARTIAL_REDUCE_UMLA:
2096 case ISD::PARTIAL_REDUCE_SMLA:
2097 case ISD::PARTIAL_REDUCE_SUMLA:
2098 Res = PromoteIntOp_PARTIAL_REDUCE_MLA(N);
2099 break;
2100 }
2101
2102 // If the result is null, the sub-method took care of registering results etc.
2103 if (!Res.getNode()) return false;
2104
2105 // If the result is N, the sub-method updated N in place. Tell the legalizer
2106 // core about this.
2107 if (Res.getNode() == N)
2108 return true;
2109
2110 const bool IsStrictFp = N->isStrictFPOpcode();
2111 assert(Res.getValueType() == N->getValueType(0) &&
2112 N->getNumValues() == (IsStrictFp ? 2 : 1) &&
2113 "Invalid operand expansion");
2114 LLVM_DEBUG(dbgs() << "Replacing: "; N->dump(&DAG); dbgs() << " with: ";
2115 Res.dump());
2116
2117 ReplaceValueWith(From: SDValue(N, 0), To: Res);
2118 if (IsStrictFp)
2119 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res.getNode(), 1));
2120
2121 return false;
2122}
2123
2124// These operands can be either sign extended or zero extended as long as we
2125// treat them the same. If an extension is free, choose that. Otherwise, follow
2126// target preference.
2127void DAGTypeLegalizer::SExtOrZExtPromotedOperands(SDValue &LHS, SDValue &RHS) {
2128 SDValue OpL = GetPromotedInteger(Op: LHS);
2129 SDValue OpR = GetPromotedInteger(Op: RHS);
2130
2131 if (TLI.isSExtCheaperThanZExt(FromTy: LHS.getValueType(), ToTy: OpL.getValueType())) {
2132 // The target would prefer to promote the comparison operand with sign
2133 // extension. Honor that unless the promoted values are already zero
2134 // extended.
2135 unsigned OpLEffectiveBits =
2136 DAG.computeKnownBits(Op: OpL).countMaxActiveBits();
2137 unsigned OpREffectiveBits =
2138 DAG.computeKnownBits(Op: OpR).countMaxActiveBits();
2139 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2140 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2141 LHS = OpL;
2142 RHS = OpR;
2143 return;
2144 }
2145
2146 // The promoted values aren't zero extended, use a sext_inreg.
2147 LHS = SExtPromotedInteger(Op: LHS);
2148 RHS = SExtPromotedInteger(Op: RHS);
2149 return;
2150 }
2151
2152 // Prefer to promote the comparison operand with zero extension.
2153
2154 // If the width of OpL/OpR excluding the duplicated sign bits is no greater
2155 // than the width of LHS/RHS, we can avoid/ inserting a zext_inreg operation
2156 // that we might not be able to remove.
2157 unsigned OpLEffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpL);
2158 unsigned OpREffectiveBits = DAG.ComputeMaxSignificantBits(Op: OpR);
2159 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
2160 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
2161 LHS = OpL;
2162 RHS = OpR;
2163 return;
2164 }
2165
2166 // Otherwise, use zext_inreg.
2167 LHS = ZExtPromotedInteger(Op: LHS);
2168 RHS = ZExtPromotedInteger(Op: RHS);
2169}
2170
2171/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
2172/// shared among BR_CC, SELECT_CC, and SETCC handlers.
2173void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
2174 ISD::CondCode CCCode) {
2175 // We have to insert explicit sign or zero extends. Note that we could
2176 // insert sign extends for ALL conditions. For those operations where either
2177 // zero or sign extension would be valid, we ask the target which extension
2178 // it would prefer.
2179
2180 // Signed comparisons always require sign extension.
2181 if (ISD::isSignedIntSetCC(Code: CCCode)) {
2182 LHS = SExtPromotedInteger(Op: LHS);
2183 RHS = SExtPromotedInteger(Op: RHS);
2184 return;
2185 }
2186
2187 assert((ISD::isUnsignedIntSetCC(CCCode) || ISD::isIntEqualitySetCC(CCCode)) &&
2188 "Unknown integer comparison!");
2189
2190 SExtOrZExtPromotedOperands(LHS, RHS);
2191}
2192
2193SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
2194 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2195 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2196}
2197
2198SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
2199 SDValue Op1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
2200 return DAG.getAtomic(Opcode: N->getOpcode(), dl: SDLoc(N), MemVT: N->getMemoryVT(),
2201 Chain: N->getChain(), Ptr: Op1, Val: N->getBasePtr(), MMO: N->getMemOperand());
2202}
2203
2204SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
2205 EVT OutVT = N->getValueType(ResNo: 0);
2206 SDValue InOp = N->getOperand(Num: 0);
2207 EVT InVT = InOp.getValueType();
2208 EVT NInVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT);
2209 SDLoc dl(N);
2210
2211 switch (getTypeAction(VT: InVT)) {
2212 case TargetLowering::TypePromoteInteger: {
2213 // TODO: Handle big endian
2214 if (OutVT.isVector() && DAG.getDataLayout().isLittleEndian()) {
2215 EVT EltVT = OutVT.getVectorElementType();
2216 TypeSize EltSize = EltVT.getSizeInBits();
2217 TypeSize NInSize = NInVT.getSizeInBits();
2218
2219 if (NInSize.hasKnownScalarFactor(RHS: EltSize)) {
2220 unsigned NumEltsWithPadding = NInSize.getKnownScalarFactor(RHS: EltSize);
2221 EVT WideVecVT =
2222 EVT::getVectorVT(Context&: *DAG.getContext(), VT: EltVT, NumElements: NumEltsWithPadding);
2223
2224 if (isTypeLegal(VT: WideVecVT)) {
2225 SDValue Promoted = GetPromotedInteger(Op: InOp);
2226 SDValue Cast = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: WideVecVT, Operand: Promoted);
2227 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Cast,
2228 N2: DAG.getVectorIdxConstant(Val: 0, DL: dl));
2229 }
2230 }
2231 }
2232
2233 break;
2234 }
2235 default:
2236 break;
2237 }
2238
2239 // This should only occur in unusual situations like bitcasting to an
2240 // x86_fp80, so just turn it into a store+load
2241 return CreateStackStoreLoad(Op: InOp, DestVT: OutVT);
2242}
2243
2244SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
2245 assert(OpNo == 2 && "Don't know how to promote this operand!");
2246
2247 SDValue LHS = N->getOperand(Num: 2);
2248 SDValue RHS = N->getOperand(Num: 3);
2249 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get());
2250
2251 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
2252 // legal types.
2253 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2254 Op2: N->getOperand(Num: 1), Op3: LHS, Op4: RHS, Op5: N->getOperand(Num: 4)),
2255 0);
2256}
2257
2258SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
2259 assert(OpNo == 1 && "only know how to promote condition");
2260
2261 // Promote all the way up to the canonical SetCC type.
2262 SDValue Cond = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: MVT::Other);
2263
2264 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
2265 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Cond,
2266 Op3: N->getOperand(Num: 2)), 0);
2267}
2268
2269SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
2270 // Since the result type is legal, the operands must promote to it.
2271 EVT OVT = N->getOperand(Num: 0).getValueType();
2272 SDValue Lo = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2273 SDValue Hi = GetPromotedInteger(Op: N->getOperand(Num: 1));
2274 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
2275 SDLoc dl(N);
2276
2277 Hi = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: N->getValueType(ResNo: 0), N1: Hi,
2278 N2: DAG.getConstant(Val: OVT.getSizeInBits(), DL: dl,
2279 VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
2280 return DAG.getNode(Opcode: ISD::OR, DL: dl, VT: N->getValueType(ResNo: 0), N1: Lo, N2: Hi);
2281}
2282
2283SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
2284 // The vector type is legal but the element type is not. This implies
2285 // that the vector is a power-of-two in length and that the element
2286 // type does not have a strange size (eg: it is not i1).
2287 EVT VecVT = N->getValueType(ResNo: 0);
2288 unsigned NumElts = VecVT.getVectorNumElements();
2289 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
2290 "Legal vector of one illegal element?");
2291
2292 // Promote the inserted value. The type does not need to match the
2293 // vector element type. Check that any extra bits introduced will be
2294 // truncated away.
2295 assert(N->getOperand(0).getValueSizeInBits() >=
2296 N->getValueType(0).getScalarSizeInBits() &&
2297 "Type of inserted value narrower than vector element type!");
2298
2299 SmallVector<SDValue, 16> NewOps;
2300 for (unsigned i = 0; i < NumElts; ++i)
2301 NewOps.push_back(Elt: GetPromotedInteger(Op: N->getOperand(Num: i)));
2302
2303 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2304}
2305
2306SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
2307 unsigned OpNo) {
2308 if (OpNo == 1) {
2309 // Promote the inserted value. This is valid because the type does not
2310 // have to match the vector element type.
2311
2312 // Check that any extra bits introduced will be truncated away.
2313 assert(N->getOperand(1).getValueSizeInBits() >=
2314 N->getValueType(0).getScalarSizeInBits() &&
2315 "Type of inserted value narrower than vector element type!");
2316 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2317 Op2: GetPromotedInteger(Op: N->getOperand(Num: 1)),
2318 Op3: N->getOperand(Num: 2)),
2319 0);
2320 }
2321
2322 assert(OpNo == 2 && "Different operand and result vector types?");
2323
2324 // Promote the index.
2325 SDValue Idx = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 2), DL: SDLoc(N),
2326 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
2327 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2328 Op2: N->getOperand(Num: 1), Op3: Idx), 0);
2329}
2330
2331SDValue DAGTypeLegalizer::PromoteIntOp_ScalarOp(SDNode *N) {
2332 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2333 if (N->getOpcode() == ISD::EXPERIMENTAL_VP_SPLAT)
2334 return SDValue(
2335 DAG.UpdateNodeOperands(N, Op1: Op, Op2: N->getOperand(Num: 1), Op3: N->getOperand(Num: 2)), 0);
2336
2337 // Integer SPLAT_VECTOR/SCALAR_TO_VECTOR operands are implicitly truncated,
2338 // so just promote the operand in place.
2339 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2340}
2341
2342SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
2343 assert(OpNo == 0 && "Only know how to promote the condition!");
2344 SDValue Cond = N->getOperand(Num: 0);
2345 EVT OpTy = N->getOperand(Num: 1).getValueType();
2346
2347 if (N->getOpcode() == ISD::VSELECT)
2348 if (SDValue Res = WidenVSELECTMask(N))
2349 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: N->getValueType(ResNo: 0),
2350 N1: Res, N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
2351
2352 // Promote all the way up to the canonical SetCC type.
2353 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
2354 Cond = PromoteTargetBoolean(Bool: Cond, ValVT: OpVT);
2355
2356 return SDValue(DAG.UpdateNodeOperands(N, Op1: Cond, Op2: N->getOperand(Num: 1),
2357 Op3: N->getOperand(Num: 2)), 0);
2358}
2359
2360SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
2361 assert(OpNo == 0 && "Don't know how to promote this operand!");
2362
2363 SDValue LHS = N->getOperand(Num: 0);
2364 SDValue RHS = N->getOperand(Num: 1);
2365 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get());
2366
2367 // The CC (#4) and the possible return values (#2 and #3) have legal types.
2368 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2),
2369 Op4: N->getOperand(Num: 3), Op5: N->getOperand(Num: 4)), 0);
2370}
2371
2372SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
2373 assert(OpNo == 0 && "Don't know how to promote this operand!");
2374
2375 SDValue LHS = N->getOperand(Num: 0);
2376 SDValue RHS = N->getOperand(Num: 1);
2377 PromoteSetCCOperands(LHS, RHS, CCCode: cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get());
2378
2379 // The CC (#2) is always legal.
2380 if (N->getOpcode() == ISD::SETCC)
2381 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2)), 0);
2382
2383 assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
2384
2385 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS, Op3: N->getOperand(Num: 2),
2386 Op4: N->getOperand(Num: 3), Op5: N->getOperand(Num: 4)),
2387 0);
2388}
2389
2390SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
2391 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2392 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2393}
2394
2395SDValue DAGTypeLegalizer::PromoteIntOp_CMP(SDNode *N) {
2396 SDValue LHS = N->getOperand(Num: 0);
2397 SDValue RHS = N->getOperand(Num: 1);
2398
2399 if (N->getOpcode() == ISD::SCMP) {
2400 LHS = SExtPromotedInteger(Op: LHS);
2401 RHS = SExtPromotedInteger(Op: RHS);
2402 } else {
2403 SExtOrZExtPromotedOperands(LHS, RHS);
2404 }
2405
2406 return SDValue(DAG.UpdateNodeOperands(N, Op1: LHS, Op2: RHS), 0);
2407}
2408
2409SDValue DAGTypeLegalizer::PromoteIntOp_FunnelShift(SDNode *N) {
2410 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1),
2411 Op3: ZExtPromotedInteger(Op: N->getOperand(Num: 2))), 0);
2412}
2413
2414SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
2415 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2416 SDLoc dl(N);
2417 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Op);
2418 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Op.getValueType(),
2419 N1: Op, N2: DAG.getValueType(N->getOperand(Num: 0).getValueType()));
2420}
2421
2422SDValue DAGTypeLegalizer::PromoteIntOp_VP_SIGN_EXTEND(SDNode *N) {
2423 SDLoc dl(N);
2424 EVT VT = N->getValueType(ResNo: 0);
2425 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2426 // FIXME: There is no VP_ANY_EXTEND yet.
2427 Op = DAG.getNode(Opcode: ISD::VP_ZERO_EXTEND, DL: dl, VT, N1: Op, N2: N->getOperand(Num: 1),
2428 N3: N->getOperand(Num: 2));
2429 unsigned Diff =
2430 VT.getScalarSizeInBits() - N->getOperand(Num: 0).getScalarValueSizeInBits();
2431 SDValue ShAmt = DAG.getShiftAmountConstant(Val: Diff, VT, DL: dl);
2432 // FIXME: There is no VP_SIGN_EXTEND_INREG so use a pair of shifts.
2433 SDValue Shl = DAG.getNode(Opcode: ISD::VP_SHL, DL: dl, VT, N1: Op, N2: ShAmt, N3: N->getOperand(Num: 1),
2434 N4: N->getOperand(Num: 2));
2435 return DAG.getNode(Opcode: ISD::VP_SRA, DL: dl, VT, N1: Shl, N2: ShAmt, N3: N->getOperand(Num: 1),
2436 N4: N->getOperand(Num: 2));
2437}
2438
2439SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
2440 if (N->getOpcode() == ISD::VP_SINT_TO_FP)
2441 return SDValue(DAG.UpdateNodeOperands(N,
2442 Op1: SExtPromotedInteger(Op: N->getOperand(Num: 0)),
2443 Op2: N->getOperand(Num: 1), Op3: N->getOperand(Num: 2)),
2444 0);
2445 return SDValue(DAG.UpdateNodeOperands(N,
2446 Op: SExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2447}
2448
2449SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N) {
2450 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2451 Op2: SExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2452}
2453
2454SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
2455 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2456 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
2457 SDLoc dl(N);
2458
2459 SDValue Val = GetPromotedInteger(Op: N->getValue()); // Get promoted value.
2460
2461 // Truncate the value and store the result.
2462 return DAG.getTruncStore(Chain: Ch, dl, Val, Ptr,
2463 SVT: N->getMemoryVT(), MMO: N->getMemOperand());
2464}
2465
2466SDValue DAGTypeLegalizer::PromoteIntOp_VP_STORE(VPStoreSDNode *N,
2467 unsigned OpNo) {
2468
2469 assert(OpNo == 1 && "Unexpected operand for promotion");
2470 assert(!N->isIndexed() && "expecting unindexed vp_store!");
2471
2472 SDValue DataOp = GetPromotedInteger(Op: N->getValue());
2473 return DAG.getTruncStoreVP(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Ptr: N->getBasePtr(),
2474 Mask: N->getMask(), EVL: N->getVectorLength(),
2475 SVT: N->getMemoryVT(), MMO: N->getMemOperand(),
2476 IsCompressing: N->isCompressingStore());
2477}
2478
2479SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
2480 unsigned OpNo) {
2481 SDValue DataOp = N->getValue();
2482 SDValue Mask = N->getMask();
2483
2484 if (OpNo == 4) {
2485 // The Mask. Update in place.
2486 EVT DataVT = DataOp.getValueType();
2487 Mask = PromoteTargetBoolean(Bool: Mask, ValVT: DataVT);
2488 SmallVector<SDValue, 4> NewOps(N->ops());
2489 NewOps[4] = Mask;
2490 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2491 }
2492
2493 assert(OpNo == 1 && "Unexpected operand for promotion");
2494 DataOp = GetPromotedInteger(Op: DataOp);
2495
2496 return DAG.getMaskedStore(Chain: N->getChain(), dl: SDLoc(N), Val: DataOp, Base: N->getBasePtr(),
2497 Offset: N->getOffset(), Mask, MemVT: N->getMemoryVT(),
2498 MMO: N->getMemOperand(), AM: N->getAddressingMode(),
2499 /*IsTruncating*/ true, IsCompressing: N->isCompressingStore());
2500}
2501
2502SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
2503 unsigned OpNo) {
2504 assert(OpNo == 3 && "Only know how to promote the mask!");
2505 EVT DataVT = N->getValueType(ResNo: 0);
2506 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2507 SmallVector<SDValue, 4> NewOps(N->ops());
2508 NewOps[OpNo] = Mask;
2509 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2510 if (Res == N)
2511 return SDValue(Res, 0);
2512
2513 // Update triggered CSE, do our own replacement since caller can't.
2514 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2515 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2516 return SDValue();
2517}
2518
2519SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
2520 unsigned OpNo) {
2521 SmallVector<SDValue, 5> NewOps(N->ops());
2522
2523 if (OpNo == 2) {
2524 // The Mask
2525 EVT DataVT = N->getValueType(ResNo: 0);
2526 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2527 } else if (OpNo == 4) {
2528 // The Index
2529 if (N->isIndexSigned())
2530 // Need to sign extend the index since the bits will likely be used.
2531 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2532 else
2533 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2534 } else
2535 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2536
2537 SDNode *Res = DAG.UpdateNodeOperands(N, Ops: NewOps);
2538 if (Res == N)
2539 return SDValue(Res, 0);
2540
2541 // Update triggered CSE, do our own replacement since caller can't.
2542 ReplaceValueWith(From: SDValue(N, 0), To: SDValue(Res, 0));
2543 ReplaceValueWith(From: SDValue(N, 1), To: SDValue(Res, 1));
2544 return SDValue();
2545}
2546
2547SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
2548 unsigned OpNo) {
2549 bool TruncateStore = N->isTruncatingStore();
2550 SmallVector<SDValue, 5> NewOps(N->ops());
2551
2552 if (OpNo == 2) {
2553 // The Mask
2554 EVT DataVT = N->getValue().getValueType();
2555 NewOps[OpNo] = PromoteTargetBoolean(Bool: N->getOperand(Num: OpNo), ValVT: DataVT);
2556 } else if (OpNo == 4) {
2557 // The Index
2558 if (N->isIndexSigned())
2559 // Need to sign extend the index since the bits will likely be used.
2560 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2561 else
2562 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2563 } else {
2564 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2565 TruncateStore = true;
2566 }
2567
2568 return DAG.getMaskedScatter(VTs: DAG.getVTList(VT: MVT::Other), MemVT: N->getMemoryVT(),
2569 dl: SDLoc(N), Ops: NewOps, MMO: N->getMemOperand(),
2570 IndexType: N->getIndexType(), IsTruncating: TruncateStore);
2571}
2572
2573SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_COMPRESS(SDNode *N,
2574 unsigned OpNo) {
2575 assert(OpNo == 1 && "Can only promote VECTOR_COMPRESS mask.");
2576 SDValue Vec = N->getOperand(Num: 0);
2577 EVT VT = Vec.getValueType();
2578 SDValue Passthru = N->getOperand(Num: 2);
2579 SDValue Mask = PromoteTargetBoolean(Bool: N->getOperand(Num: 1), ValVT: VT);
2580 return DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: SDLoc(N), VT, N1: Vec, N2: Mask, N3: Passthru);
2581}
2582
2583SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
2584 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2585 if (N->getOpcode() == ISD::VP_TRUNCATE)
2586 return DAG.getNode(Opcode: ISD::VP_TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: Op,
2587 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2));
2588 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
2589}
2590
2591SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
2592 if (N->getOpcode() == ISD::VP_UINT_TO_FP)
2593 return SDValue(DAG.UpdateNodeOperands(N,
2594 Op1: ZExtPromotedInteger(Op: N->getOperand(Num: 0)),
2595 Op2: N->getOperand(Num: 1), Op3: N->getOperand(Num: 2)),
2596 0);
2597 return SDValue(DAG.UpdateNodeOperands(N,
2598 Op: ZExtPromotedInteger(Op: N->getOperand(Num: 0))), 0);
2599}
2600
2601SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N) {
2602 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2603 Op2: ZExtPromotedInteger(Op: N->getOperand(Num: 1))), 0);
2604}
2605
2606SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
2607 SDLoc dl(N);
2608 SDValue Src = N->getOperand(Num: 0);
2609 SDValue Op = GetPromotedInteger(Op: Src);
2610 EVT VT = N->getValueType(ResNo: 0);
2611
2612 // If this zext has the nneg flag and the target prefers sext, see if the
2613 // promoted input is already sign extended.
2614 // TODO: Should we have some way to set nneg on ISD::AND instead?
2615 if (N->getFlags().hasNonNeg() && Op.getValueType() == VT &&
2616 TLI.isSExtCheaperThanZExt(FromTy: Src.getValueType(), ToTy: VT)) {
2617 unsigned OpEffectiveBits = DAG.ComputeMaxSignificantBits(Op);
2618 if (OpEffectiveBits <= Src.getScalarValueSizeInBits())
2619 return Op;
2620 }
2621
2622 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT, Operand: Op);
2623 return DAG.getZeroExtendInReg(Op, DL: dl, VT: Src.getValueType());
2624}
2625
2626SDValue DAGTypeLegalizer::PromoteIntOp_VP_ZERO_EXTEND(SDNode *N) {
2627 SDLoc dl(N);
2628 EVT VT = N->getValueType(ResNo: 0);
2629 SDValue Op = GetPromotedInteger(Op: N->getOperand(Num: 0));
2630 // FIXME: There is no VP_ANY_EXTEND yet.
2631 Op = DAG.getNode(Opcode: ISD::VP_ZERO_EXTEND, DL: dl, VT, N1: Op, N2: N->getOperand(Num: 1),
2632 N3: N->getOperand(Num: 2));
2633 return DAG.getVPZeroExtendInReg(Op, Mask: N->getOperand(Num: 1), EVL: N->getOperand(Num: 2), DL: dl,
2634 VT: N->getOperand(Num: 0).getValueType());
2635}
2636
2637SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
2638 SDValue Op2 = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
2639 return SDValue(
2640 DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1), Op3: Op2), 0);
2641}
2642
2643SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
2644 // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
2645 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2646 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2647}
2648
2649SDValue DAGTypeLegalizer::PromoteIntOp_ExpOp(SDNode *N) {
2650 bool IsStrict = N->isStrictFPOpcode();
2651 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
2652
2653 bool IsPowI =
2654 N->getOpcode() == ISD::FPOWI || N->getOpcode() == ISD::STRICT_FPOWI;
2655 unsigned OpOffset = IsStrict ? 1 : 0;
2656
2657 // The integer operand is the last operand in FPOWI (or FLDEXP) (so the result
2658 // and floating point operand is already type legalized).
2659 RTLIB::Libcall LC = IsPowI ? RTLIB::getPOWI(RetVT: N->getValueType(ResNo: 0))
2660 : RTLIB::getLDEXP(RetVT: N->getValueType(ResNo: 0));
2661
2662 if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(Call: LC)) {
2663 // Scalarize vector FPOWI instead of promoting the type. This allows the
2664 // scalar FPOWIs to be visited and converted to libcalls before promoting
2665 // the type.
2666 // FIXME: This should be done in LegalizeVectorOps/LegalizeDAG, but call
2667 // lowering needs the unpromoted EVT.
2668 if (IsPowI && N->getValueType(ResNo: 0).isVector())
2669 return DAG.UnrollVectorOp(N);
2670 SmallVector<SDValue, 3> NewOps(N->ops());
2671 NewOps[1 + OpOffset] = SExtPromotedInteger(Op: N->getOperand(Num: 1 + OpOffset));
2672 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2673 }
2674
2675 // We can't just promote the exponent type in FPOWI, since we want to lower
2676 // the node to a libcall and we if we promote to a type larger than
2677 // sizeof(int) the libcall might not be according to the targets ABI. Instead
2678 // we rewrite to a libcall here directly, letting makeLibCall handle promotion
2679 // if the target accepts it according to shouldSignExtendTypeInLibCall.
2680
2681 // The exponent should fit in a sizeof(int) type for the libcall to be valid.
2682 assert(DAG.getLibInfo().getIntSize() ==
2683 N->getOperand(1 + OpOffset).getValueType().getSizeInBits() &&
2684 "POWI exponent should match with sizeof(int) when doing the libcall.");
2685 TargetLowering::MakeLibCallOptions CallOptions;
2686 CallOptions.setIsSigned(true);
2687 SDValue Ops[2] = {N->getOperand(Num: 0 + OpOffset), N->getOperand(Num: 1 + OpOffset)};
2688 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
2689 DAG, LC, RetVT: N->getValueType(ResNo: 0), Ops, CallOptions, dl: SDLoc(N), Chain);
2690 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
2691 if (IsStrict)
2692 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
2693 return SDValue();
2694}
2695
2696static unsigned getExtendForIntVecReduction(SDNode *N) {
2697 switch (N->getOpcode()) {
2698 default:
2699 llvm_unreachable("Expected integer vector reduction");
2700 case ISD::VECREDUCE_ADD:
2701 case ISD::VECREDUCE_MUL:
2702 case ISD::VECREDUCE_AND:
2703 case ISD::VECREDUCE_OR:
2704 case ISD::VECREDUCE_XOR:
2705 case ISD::VP_REDUCE_ADD:
2706 case ISD::VP_REDUCE_MUL:
2707 case ISD::VP_REDUCE_AND:
2708 case ISD::VP_REDUCE_OR:
2709 case ISD::VP_REDUCE_XOR:
2710 return ISD::ANY_EXTEND;
2711 case ISD::VECREDUCE_SMAX:
2712 case ISD::VECREDUCE_SMIN:
2713 case ISD::VP_REDUCE_SMAX:
2714 case ISD::VP_REDUCE_SMIN:
2715 return ISD::SIGN_EXTEND;
2716 case ISD::VECREDUCE_UMAX:
2717 case ISD::VECREDUCE_UMIN:
2718 case ISD::VP_REDUCE_UMAX:
2719 case ISD::VP_REDUCE_UMIN:
2720 return ISD::ZERO_EXTEND;
2721 }
2722}
2723
2724SDValue DAGTypeLegalizer::PromoteIntOpVectorReduction(SDNode *N, SDValue V) {
2725 switch (getExtendForIntVecReduction(N)) {
2726 default:
2727 llvm_unreachable("Impossible extension kind for integer reduction");
2728 case ISD::ANY_EXTEND:
2729 return GetPromotedInteger(Op: V);
2730 case ISD::SIGN_EXTEND:
2731 return SExtPromotedInteger(Op: V);
2732 case ISD::ZERO_EXTEND:
2733 return ZExtPromotedInteger(Op: V);
2734 }
2735}
2736
2737SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
2738 SDLoc dl(N);
2739 SDValue Op = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
2740
2741 EVT OrigEltVT = N->getOperand(Num: 0).getValueType().getVectorElementType();
2742 EVT InVT = Op.getValueType();
2743 EVT EltVT = InVT.getVectorElementType();
2744 EVT ResVT = N->getValueType(ResNo: 0);
2745 unsigned Opcode = N->getOpcode();
2746
2747 // An i1 vecreduce_xor is equivalent to vecreduce_add, use that instead if
2748 // vecreduce_xor is not legal
2749 if (Opcode == ISD::VECREDUCE_XOR && OrigEltVT == MVT::i1 &&
2750 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_XOR, VT: InVT) &&
2751 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_ADD, VT: InVT))
2752 Opcode = ISD::VECREDUCE_ADD;
2753
2754 // An i1 vecreduce_or is equivalent to vecreduce_umax, use that instead if
2755 // vecreduce_or is not legal
2756 else if (Opcode == ISD::VECREDUCE_OR && OrigEltVT == MVT::i1 &&
2757 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_OR, VT: InVT) &&
2758 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMAX, VT: InVT)) {
2759 Opcode = ISD::VECREDUCE_UMAX;
2760 // Can't use promoteTargetBoolean here because we still need
2761 // to either sign_ext or zero_ext in the undefined case.
2762 switch (TLI.getBooleanContents(Type: InVT)) {
2763 case TargetLoweringBase::UndefinedBooleanContent:
2764 case TargetLoweringBase::ZeroOrOneBooleanContent:
2765 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2766 break;
2767 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2768 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
2769 break;
2770 }
2771 }
2772
2773 // An i1 vecreduce_and is equivalent to vecreduce_umin, use that instead if
2774 // vecreduce_and is not legal
2775 else if (Opcode == ISD::VECREDUCE_AND && OrigEltVT == MVT::i1 &&
2776 !TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_AND, VT: InVT) &&
2777 TLI.isOperationLegalOrCustom(Op: ISD::VECREDUCE_UMIN, VT: InVT)) {
2778 Opcode = ISD::VECREDUCE_UMIN;
2779 // Can't use promoteTargetBoolean here because we still need
2780 // to either sign_ext or zero_ext in the undefined case.
2781 switch (TLI.getBooleanContents(Type: InVT)) {
2782 case TargetLoweringBase::UndefinedBooleanContent:
2783 case TargetLoweringBase::ZeroOrOneBooleanContent:
2784 Op = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2785 break;
2786 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2787 Op = SExtPromotedInteger(Op: N->getOperand(Num: 0));
2788 break;
2789 }
2790 }
2791
2792 if (ResVT.bitsGE(VT: EltVT))
2793 return DAG.getNode(Opcode, DL: SDLoc(N), VT: ResVT, Operand: Op);
2794
2795 // Result size must be >= element size. If this is not the case after
2796 // promotion, also promote the result type and then truncate.
2797 SDValue Reduce = DAG.getNode(Opcode, DL: dl, VT: EltVT, Operand: Op);
2798 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: ResVT, Operand: Reduce);
2799}
2800
2801SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
2802 SDLoc DL(N);
2803 SDValue Op = N->getOperand(Num: OpNo);
2804 SmallVector<SDValue, 4> NewOps(N->ops());
2805
2806 if (OpNo == 2) { // Mask
2807 // Update in place.
2808 NewOps[2] = PromoteTargetBoolean(Bool: Op, ValVT: N->getOperand(Num: 1).getValueType());
2809 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2810 }
2811
2812 assert(OpNo == 1 && "Unexpected operand for promotion");
2813
2814 Op = PromoteIntOpVectorReduction(N, V: Op);
2815
2816 NewOps[OpNo] = Op;
2817
2818 EVT VT = N->getValueType(ResNo: 0);
2819 EVT EltVT = Op.getValueType().getScalarType();
2820
2821 if (VT.bitsGE(VT: EltVT))
2822 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT, Ops: NewOps);
2823
2824 // Result size must be >= element/start-value size. If this is not the case
2825 // after promotion, also promote both the start value and result type and
2826 // then truncate.
2827 NewOps[0] =
2828 DAG.getNode(Opcode: getExtendForIntVecReduction(N), DL, VT: EltVT, Operand: N->getOperand(Num: 0));
2829 SDValue Reduce = DAG.getNode(Opcode: N->getOpcode(), DL, VT: EltVT, Ops: NewOps);
2830 return DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT, Operand: Reduce);
2831}
2832
2833SDValue DAGTypeLegalizer::PromoteIntOp_SET_ROUNDING(SDNode *N) {
2834 SDValue Op = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
2835 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Op), 0);
2836}
2837
2838SDValue DAGTypeLegalizer::PromoteIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
2839 assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
2840 SmallVector<SDValue> NewOps(N->ops());
2841 SDValue Operand = N->getOperand(Num: OpNo);
2842 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: Operand.getValueType());
2843 NewOps[OpNo] = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand);
2844 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2845}
2846
2847SDValue DAGTypeLegalizer::PromoteIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
2848 assert(OpNo >= 7);
2849 SmallVector<SDValue> NewOps(N->ops());
2850 SDValue Operand = N->getOperand(Num: OpNo);
2851 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: Operand.getValueType());
2852 NewOps[OpNo] = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: NVT, Operand);
2853 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2854}
2855
2856SDValue DAGTypeLegalizer::PromoteIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
2857 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
2858 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
2859
2860 SmallVector<SDValue, 8> NewOps(N->ops());
2861 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2862
2863 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2864}
2865
2866SDValue DAGTypeLegalizer::PromoteIntOp_VP_SPLICE(SDNode *N, unsigned OpNo) {
2867 SmallVector<SDValue, 6> NewOps(N->ops());
2868
2869 if (OpNo == 2) { // Offset operand
2870 NewOps[OpNo] = SExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2871 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2872 }
2873
2874 assert((OpNo == 4 || OpNo == 5) && "Unexpected operand for promotion");
2875
2876 NewOps[OpNo] = ZExtPromotedInteger(Op: N->getOperand(Num: OpNo));
2877 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2878}
2879
2880SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_HISTOGRAM(SDNode *N,
2881 unsigned OpNo) {
2882 assert(OpNo == 1 && "Unexpected operand for promotion");
2883 SmallVector<SDValue, 7> NewOps(N->ops());
2884 NewOps[1] = GetPromotedInteger(Op: N->getOperand(Num: 1));
2885 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2886}
2887
2888SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_FIND_LAST_ACTIVE(SDNode *N,
2889 unsigned OpNo) {
2890 SmallVector<SDValue, 1> NewOps(N->ops());
2891 NewOps[OpNo] = GetPromotedInteger(Op: N->getOperand(Num: OpNo));
2892 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2893}
2894
2895SDValue DAGTypeLegalizer::PromoteIntOp_GET_ACTIVE_LANE_MASK(SDNode *N) {
2896 SmallVector<SDValue, 1> NewOps(N->ops());
2897 NewOps[0] = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
2898 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
2899 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2900}
2901
2902SDValue DAGTypeLegalizer::PromoteIntOp_PARTIAL_REDUCE_MLA(SDNode *N) {
2903 SmallVector<SDValue, 1> NewOps(N->ops());
2904 switch (N->getOpcode()) {
2905 case ISD::PARTIAL_REDUCE_SMLA:
2906 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
2907 NewOps[2] = SExtPromotedInteger(Op: N->getOperand(Num: 2));
2908 break;
2909 case ISD::PARTIAL_REDUCE_UMLA:
2910 NewOps[1] = ZExtPromotedInteger(Op: N->getOperand(Num: 1));
2911 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
2912 break;
2913 case ISD::PARTIAL_REDUCE_SUMLA:
2914 NewOps[1] = SExtPromotedInteger(Op: N->getOperand(Num: 1));
2915 NewOps[2] = ZExtPromotedInteger(Op: N->getOperand(Num: 2));
2916 break;
2917 default:
2918 llvm_unreachable("unexpected opcode");
2919 }
2920 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
2921}
2922
2923//===----------------------------------------------------------------------===//
2924// Integer Result Expansion
2925//===----------------------------------------------------------------------===//
2926
2927/// ExpandIntegerResult - This method is called when the specified result of the
2928/// specified node is found to need expansion. At this point, the node may also
2929/// have invalid operands or may have other results that need promotion, we just
2930/// know that (at least) one result needs expansion.
2931void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
2932 LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG));
2933 SDValue Lo, Hi;
2934 Lo = Hi = SDValue();
2935
2936 // See if the target wants to custom expand this node.
2937 if (CustomLowerNode(N, VT: N->getValueType(ResNo), LegalizeResult: true))
2938 return;
2939
2940 switch (N->getOpcode()) {
2941 default:
2942#ifndef NDEBUG
2943 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
2944 N->dump(&DAG); dbgs() << "\n";
2945#endif
2946 report_fatal_error(reason: "Do not know how to expand the result of this "
2947 "operator!");
2948
2949 case ISD::ARITH_FENCE: SplitRes_ARITH_FENCE(N, Lo, Hi); break;
2950 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
2951 case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break;
2952 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
2953 case ISD::POISON:
2954 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
2955 case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break;
2956 case ISD::SETCC: ExpandIntRes_SETCC(N, Lo, Hi); break;
2957
2958 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
2959 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
2960 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
2961 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
2962 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
2963
2964 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
2965 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
2966 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
2967 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
2968 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
2969 case ISD::PARITY: ExpandIntRes_PARITY(N, Lo, Hi); break;
2970 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
2971 case ISD::ABS: ExpandIntRes_ABS(N, Lo, Hi); break;
2972 case ISD::ABDS:
2973 case ISD::ABDU: ExpandIntRes_ABD(N, Lo, Hi); break;
2974 case ISD::CTLZ_ZERO_UNDEF:
2975 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
2976 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
2977 case ISD::CTTZ_ZERO_UNDEF:
2978 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
2979 case ISD::GET_ROUNDING:ExpandIntRes_GET_ROUNDING(N, Lo, Hi); break;
2980 case ISD::STRICT_FP_TO_SINT:
2981 case ISD::FP_TO_SINT:
2982 case ISD::STRICT_FP_TO_UINT:
2983 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_XINT(N, Lo, Hi); break;
2984 case ISD::FP_TO_SINT_SAT:
2985 case ISD::FP_TO_UINT_SAT: ExpandIntRes_FP_TO_XINT_SAT(N, Lo, Hi); break;
2986 case ISD::STRICT_LROUND:
2987 case ISD::STRICT_LRINT:
2988 case ISD::LROUND:
2989 case ISD::LRINT:
2990 case ISD::STRICT_LLROUND:
2991 case ISD::STRICT_LLRINT:
2992 case ISD::LLROUND:
2993 case ISD::LLRINT: ExpandIntRes_XROUND_XRINT(N, Lo, Hi); break;
2994 case ISD::LOAD: ExpandIntRes_LOAD(N: cast<LoadSDNode>(Val: N), Lo, Hi); break;
2995 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
2996 case ISD::READCYCLECOUNTER:
2997 case ISD::READSTEADYCOUNTER: ExpandIntRes_READCOUNTER(N, Lo, Hi); break;
2998 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
2999 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
3000 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
3001 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
3002 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
3003 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
3004 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
3005 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
3006 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
3007
3008 case ISD::ATOMIC_LOAD_ADD:
3009 case ISD::ATOMIC_LOAD_SUB:
3010 case ISD::ATOMIC_LOAD_AND:
3011 case ISD::ATOMIC_LOAD_CLR:
3012 case ISD::ATOMIC_LOAD_OR:
3013 case ISD::ATOMIC_LOAD_XOR:
3014 case ISD::ATOMIC_LOAD_NAND:
3015 case ISD::ATOMIC_LOAD_MIN:
3016 case ISD::ATOMIC_LOAD_MAX:
3017 case ISD::ATOMIC_LOAD_UMIN:
3018 case ISD::ATOMIC_LOAD_UMAX:
3019 case ISD::ATOMIC_SWAP:
3020 case ISD::ATOMIC_CMP_SWAP: {
3021 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node: N);
3022 SplitInteger(Op: Tmp.first, Lo, Hi);
3023 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
3024 break;
3025 }
3026 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3027 AtomicSDNode *AN = cast<AtomicSDNode>(Val: N);
3028 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: MVT::Other);
3029 SDValue Tmp = DAG.getAtomicCmpSwap(
3030 Opcode: ISD::ATOMIC_CMP_SWAP, dl: SDLoc(N), MemVT: AN->getMemoryVT(), VTs,
3031 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 1), Cmp: N->getOperand(Num: 2), Swp: N->getOperand(Num: 3),
3032 MMO: AN->getMemOperand());
3033
3034 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
3035 // success simply by comparing the loaded value against the ingoing
3036 // comparison.
3037 SDValue Success = DAG.getSetCC(DL: SDLoc(N), VT: N->getValueType(ResNo: 1), LHS: Tmp,
3038 RHS: N->getOperand(Num: 2), Cond: ISD::SETEQ);
3039
3040 SplitInteger(Op: Tmp, Lo, Hi);
3041 ReplaceValueWith(From: SDValue(N, 1), To: Success);
3042 ReplaceValueWith(From: SDValue(N, 2), To: Tmp.getValue(R: 1));
3043 break;
3044 }
3045
3046 case ISD::AND:
3047 case ISD::OR:
3048 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
3049
3050 case ISD::UMAX:
3051 case ISD::SMAX:
3052 case ISD::UMIN:
3053 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
3054
3055 case ISD::SCMP:
3056 case ISD::UCMP: ExpandIntRes_CMP(N, Lo, Hi); break;
3057
3058 case ISD::ADD:
3059 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
3060
3061 case ISD::ADDC:
3062 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
3063
3064 case ISD::ADDE:
3065 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
3066
3067 case ISD::UADDO_CARRY:
3068 case ISD::USUBO_CARRY: ExpandIntRes_UADDSUBO_CARRY(N, Lo, Hi); break;
3069
3070 case ISD::SADDO_CARRY:
3071 case ISD::SSUBO_CARRY: ExpandIntRes_SADDSUBO_CARRY(N, Lo, Hi); break;
3072
3073 case ISD::SHL:
3074 case ISD::SRA:
3075 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
3076
3077 case ISD::SADDO:
3078 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
3079 case ISD::UADDO:
3080 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
3081 case ISD::UMULO:
3082 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
3083
3084 case ISD::SADDSAT:
3085 case ISD::UADDSAT:
3086 case ISD::SSUBSAT:
3087 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
3088
3089 case ISD::SSHLSAT:
3090 case ISD::USHLSAT: ExpandIntRes_SHLSAT(N, Lo, Hi); break;
3091
3092 case ISD::AVGCEILS:
3093 case ISD::AVGCEILU:
3094 case ISD::AVGFLOORS:
3095 case ISD::AVGFLOORU: ExpandIntRes_AVG(N, Lo, Hi); break;
3096
3097 case ISD::SMULFIX:
3098 case ISD::SMULFIXSAT:
3099 case ISD::UMULFIX:
3100 case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
3101
3102 case ISD::SDIVFIX:
3103 case ISD::SDIVFIXSAT:
3104 case ISD::UDIVFIX:
3105 case ISD::UDIVFIXSAT: ExpandIntRes_DIVFIX(N, Lo, Hi); break;
3106
3107 case ISD::VECREDUCE_ADD:
3108 case ISD::VECREDUCE_MUL:
3109 case ISD::VECREDUCE_AND:
3110 case ISD::VECREDUCE_OR:
3111 case ISD::VECREDUCE_XOR:
3112 case ISD::VECREDUCE_SMAX:
3113 case ISD::VECREDUCE_SMIN:
3114 case ISD::VECREDUCE_UMAX:
3115 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
3116
3117 case ISD::ROTL:
3118 case ISD::ROTR:
3119 ExpandIntRes_Rotate(N, Lo, Hi);
3120 break;
3121
3122 case ISD::FSHL:
3123 case ISD::FSHR:
3124 ExpandIntRes_FunnelShift(N, Lo, Hi);
3125 break;
3126
3127 case ISD::VSCALE:
3128 ExpandIntRes_VSCALE(N, Lo, Hi);
3129 break;
3130 }
3131
3132 // If Lo/Hi is null, the sub-method took care of registering results etc.
3133 if (Lo.getNode())
3134 SetExpandedInteger(Op: SDValue(N, ResNo), Lo, Hi);
3135}
3136
3137/// Lower an atomic node to the appropriate builtin call.
3138std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
3139 unsigned Opc = Node->getOpcode();
3140 MVT VT = cast<AtomicSDNode>(Val: Node)->getMemoryVT().getSimpleVT();
3141 AtomicOrdering order = cast<AtomicSDNode>(Val: Node)->getMergedOrdering();
3142 // Lower to outline atomic libcall if outline atomics enabled,
3143 // or to sync libcall otherwise
3144 RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, Order: order, VT);
3145 EVT RetVT = Node->getValueType(ResNo: 0);
3146 TargetLowering::MakeLibCallOptions CallOptions;
3147 SmallVector<SDValue, 4> Ops;
3148 if (TLI.getLibcallName(Call: LC)) {
3149 Ops.append(in_start: Node->op_begin() + 2, in_end: Node->op_end());
3150 Ops.push_back(Elt: Node->getOperand(Num: 1));
3151 } else {
3152 LC = RTLIB::getSYNC(Opc, VT);
3153 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3154 "Unexpected atomic op or value type!");
3155 Ops.append(in_start: Node->op_begin() + 1, in_end: Node->op_end());
3156 }
3157 return TLI.makeLibCall(DAG, LC, RetVT, Ops, CallOptions, dl: SDLoc(Node),
3158 Chain: Node->getOperand(Num: 0));
3159}
3160
3161/// N is a shift by a value that needs to be expanded,
3162/// and the shift amount is a constant 'Amt'. Expand the operation.
3163void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
3164 SDValue &Lo, SDValue &Hi) {
3165 SDLoc DL(N);
3166 // Expand the incoming operand to be shifted, so that we have its parts
3167 SDValue InL, InH;
3168 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3169
3170 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
3171 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
3172 if (!Amt) {
3173 Lo = InL;
3174 Hi = InH;
3175 return;
3176 }
3177
3178 EVT NVT = InL.getValueType();
3179 unsigned VTBits = N->getValueType(ResNo: 0).getSizeInBits();
3180 unsigned NVTBits = NVT.getSizeInBits();
3181
3182 if (N->getOpcode() == ISD::SHL) {
3183 if (Amt.uge(RHS: VTBits)) {
3184 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3185 } else if (Amt.ugt(RHS: NVTBits)) {
3186 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3187 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3188 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3189 } else if (Amt == NVTBits) {
3190 Lo = DAG.getConstant(Val: 0, DL, VT: NVT);
3191 Hi = InL;
3192 } else {
3193 Lo = DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InL,
3194 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3195 Hi = DAG.getNode(
3196 Opcode: ISD::OR, DL, VT: NVT,
3197 N1: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3198 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3199 N2: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3200 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3201 }
3202 return;
3203 }
3204
3205 if (N->getOpcode() == ISD::SRL) {
3206 if (Amt.uge(RHS: VTBits)) {
3207 Lo = Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3208 } else if (Amt.ugt(RHS: NVTBits)) {
3209 Lo = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3210 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3211 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3212 } else if (Amt == NVTBits) {
3213 Lo = InH;
3214 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
3215 } else {
3216 Lo = DAG.getNode(
3217 Opcode: ISD::OR, DL, VT: NVT,
3218 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3219 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3220 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3221 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3222 Hi = DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InH,
3223 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3224 }
3225 return;
3226 }
3227
3228 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
3229 if (Amt.uge(RHS: VTBits)) {
3230 Hi = Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3231 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3232 } else if (Amt.ugt(RHS: NVTBits)) {
3233 Lo = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3234 N2: DAG.getShiftAmountConstant(Val: Amt - NVTBits, VT: NVT, DL));
3235 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3236 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3237 } else if (Amt == NVTBits) {
3238 Lo = InH;
3239 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3240 N2: DAG.getShiftAmountConstant(Val: NVTBits - 1, VT: NVT, DL));
3241 } else {
3242 Lo = DAG.getNode(
3243 Opcode: ISD::OR, DL, VT: NVT,
3244 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: NVT, N1: InL,
3245 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL)),
3246 N2: DAG.getNode(Opcode: ISD::SHL, DL, VT: NVT, N1: InH,
3247 N2: DAG.getShiftAmountConstant(Val: -Amt + NVTBits, VT: NVT, DL)));
3248 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: InH,
3249 N2: DAG.getShiftAmountConstant(Val: Amt, VT: NVT, DL));
3250 }
3251}
3252
3253/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
3254/// this shift based on knowledge of the high bit of the shift amount. If we
3255/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
3256/// shift amount.
3257bool DAGTypeLegalizer::
3258ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3259 unsigned Opc = N->getOpcode();
3260 SDValue In = N->getOperand(Num: 0);
3261 SDValue Amt = N->getOperand(Num: 1);
3262 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3263 EVT ShTy = Amt.getValueType();
3264 unsigned ShBits = ShTy.getScalarSizeInBits();
3265 unsigned NVTBits = NVT.getScalarSizeInBits();
3266 assert(isPowerOf2_32(NVTBits) &&
3267 "Expanded integer type size not a power of two!");
3268 SDLoc dl(N);
3269
3270 APInt HighBitMask = APInt::getHighBitsSet(numBits: ShBits, hiBitsSet: ShBits - Log2_32(Value: NVTBits));
3271 KnownBits Known = DAG.computeKnownBits(Op: Amt);
3272
3273 // If we don't know anything about the high bits, exit.
3274 if (((Known.Zero | Known.One) & HighBitMask) == 0)
3275 return false;
3276
3277 // Get the incoming operand to be shifted.
3278 SDValue InL, InH;
3279 GetExpandedInteger(Op: In, Lo&: InL, Hi&: InH);
3280
3281 // If we know that any of the high bits of the shift amount are one, then we
3282 // can do this as a couple of simple shifts.
3283 if (Known.One.intersects(RHS: HighBitMask)) {
3284 // Mask out the high bit, which we know is set.
3285 Amt = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShTy, N1: Amt,
3286 N2: DAG.getConstant(Val: ~HighBitMask, DL: dl, VT: ShTy));
3287
3288 switch (Opc) {
3289 default: llvm_unreachable("Unknown shift");
3290 case ISD::SHL:
3291 Lo = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Low part is zero.
3292 Hi = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt); // High part from Lo part.
3293 return true;
3294 case ISD::SRL:
3295 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3296 Lo = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3297 return true;
3298 case ISD::SRA:
3299 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign extend high part.
3300 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3301 Lo = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt); // Lo part from Hi part.
3302 return true;
3303 }
3304 }
3305
3306 // If we know that all of the high bits of the shift amount are zero, then we
3307 // can do this as a couple of simple shifts.
3308 if (HighBitMask.isSubsetOf(RHS: Known.Zero)) {
3309 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
3310 // shift if x is zero. We can use XOR here because x is known to be smaller
3311 // than 32.
3312 SDValue Amt2 = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: ShTy, N1: Amt,
3313 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3314
3315 unsigned Op1, Op2;
3316 switch (Opc) {
3317 default: llvm_unreachable("Unknown shift");
3318 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
3319 case ISD::SRL:
3320 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
3321 }
3322
3323 // When shifting right the arithmetic for Lo and Hi is swapped.
3324 if (Opc != ISD::SHL)
3325 std::swap(a&: InL, b&: InH);
3326
3327 // Use a little trick to get the bits that move from Lo to Hi. First
3328 // shift by one bit.
3329 SDValue Sh1 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: InL, N2: DAG.getConstant(Val: 1, DL: dl, VT: ShTy));
3330 // Then compute the remaining shift with amount-1.
3331 SDValue Sh2 = DAG.getNode(Opcode: Op2, DL: dl, VT: NVT, N1: Sh1, N2: Amt2);
3332
3333 Lo = DAG.getNode(Opcode: Opc, DL: dl, VT: NVT, N1: InL, N2: Amt);
3334 Hi = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: DAG.getNode(Opcode: Op1, DL: dl, VT: NVT, N1: InH, N2: Amt),N2: Sh2);
3335
3336 if (Opc != ISD::SHL)
3337 std::swap(a&: Hi, b&: Lo);
3338 return true;
3339 }
3340
3341 return false;
3342}
3343
3344/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
3345/// of any size.
3346bool DAGTypeLegalizer::
3347ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
3348 SDValue Amt = N->getOperand(Num: 1);
3349 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3350 EVT ShTy = Amt.getValueType();
3351 unsigned NVTBits = NVT.getSizeInBits();
3352 assert(isPowerOf2_32(NVTBits) &&
3353 "Expanded integer type size not a power of two!");
3354 SDLoc dl(N);
3355
3356 // Get the incoming operand to be shifted.
3357 SDValue InL, InH;
3358 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
3359
3360 SDValue NVBitsNode = DAG.getConstant(Val: NVTBits, DL: dl, VT: ShTy);
3361 SDValue AmtExcess = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: Amt, N2: NVBitsNode);
3362 SDValue AmtLack = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ShTy, N1: NVBitsNode, N2: Amt);
3363 SDValue isShort = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3364 LHS: Amt, RHS: NVBitsNode, Cond: ISD::SETULT);
3365 SDValue isZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: ShTy),
3366 LHS: Amt, RHS: DAG.getConstant(Val: 0, DL: dl, VT: ShTy),
3367 Cond: ISD::SETEQ);
3368
3369 SDValue LoS, HiS, LoL, HiL;
3370 switch (N->getOpcode()) {
3371 default: llvm_unreachable("Unknown shift");
3372 case ISD::SHL:
3373 // Short: ShAmt < NVTBits
3374 LoS = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: Amt);
3375 HiS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3376 N1: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: Amt),
3377 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: AmtLack));
3378
3379 // Long: ShAmt >= NVTBits
3380 LoL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Lo part is zero.
3381 HiL = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InL, N2: AmtExcess); // Hi from Lo part.
3382
3383 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL);
3384 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InH,
3385 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL));
3386 return true;
3387 case ISD::SRL:
3388 // Short: ShAmt < NVTBits
3389 HiS = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: Amt);
3390 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3391 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3392 // FIXME: If Amt is zero, the following shift generates an undefined result
3393 // on some architectures.
3394 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3395
3396 // Long: ShAmt >= NVTBits
3397 HiL = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // Hi part is zero.
3398 LoL = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3399
3400 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3401 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3402 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3403 return true;
3404 case ISD::SRA:
3405 // Short: ShAmt < NVTBits
3406 HiS = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: Amt);
3407 LoS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT,
3408 N1: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: InL, N2: Amt),
3409 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: InH, N2: AmtLack));
3410
3411 // Long: ShAmt >= NVTBits
3412 HiL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, // Sign of Hi part.
3413 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl, VT: ShTy));
3414 LoL = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: InH, N2: AmtExcess); // Lo from Hi part.
3415
3416 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: isZero, LHS: InL,
3417 RHS: DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: LoS, RHS: LoL));
3418 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: isShort, LHS: HiS, RHS: HiL);
3419 return true;
3420 }
3421}
3422
3423static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
3424
3425 switch (Op) {
3426 default: llvm_unreachable("invalid min/max opcode");
3427 case ISD::SMAX:
3428 return std::make_pair(x: ISD::SETGT, y: ISD::UMAX);
3429 case ISD::UMAX:
3430 return std::make_pair(x: ISD::SETUGT, y: ISD::UMAX);
3431 case ISD::SMIN:
3432 return std::make_pair(x: ISD::SETLT, y: ISD::UMIN);
3433 case ISD::UMIN:
3434 return std::make_pair(x: ISD::SETULT, y: ISD::UMIN);
3435 }
3436}
3437
3438void DAGTypeLegalizer::ExpandIntRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
3439 SDLoc DL(N);
3440
3441 SDValue LHS = N->getOperand(Num: 0);
3442 SDValue RHS = N->getOperand(Num: 1);
3443 EVT NewVT = getSetCCResultType(VT: LHS.getValueType());
3444
3445 // Taking the same approach as ScalarizeVecRes_SETCC
3446 SDValue Res = DAG.getNode(Opcode: ISD::SETCC, DL, VT: NewVT, N1: LHS, N2: RHS, N3: N->getOperand(Num: 2));
3447
3448 Res = DAG.getBoolExtOrTrunc(Op: Res, SL: DL, VT: N->getValueType(ResNo: 0), OpVT: NewVT);
3449 SplitInteger(Op: Res, Lo, Hi);
3450}
3451
3452void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
3453 SDValue &Lo, SDValue &Hi) {
3454 SDLoc DL(N);
3455
3456 SDValue LHS = N->getOperand(Num: 0);
3457 SDValue RHS = N->getOperand(Num: 1);
3458
3459 // If the upper halves are all sign bits, then we can perform the MINMAX on
3460 // the lower half and sign-extend the result to the upper half.
3461 unsigned NumBits = N->getValueType(ResNo: 0).getScalarSizeInBits();
3462 unsigned NumHalfBits = NumBits / 2;
3463 if (DAG.ComputeNumSignBits(Op: LHS) > NumHalfBits &&
3464 DAG.ComputeNumSignBits(Op: RHS) > NumHalfBits) {
3465 SDValue LHSL, LHSH, RHSL, RHSH;
3466 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3467 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3468 EVT NVT = LHSL.getValueType();
3469
3470 Lo = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: LHSL, N2: RHSL);
3471 Hi = DAG.getNode(Opcode: ISD::SRA, DL, VT: NVT, N1: Lo,
3472 N2: DAG.getShiftAmountConstant(Val: NumHalfBits - 1, VT: NVT, DL));
3473 return;
3474 }
3475
3476 // The Lo of smin(X, -1) is LHSL if X is negative. Otherwise it's -1.
3477 // The Lo of smax(X, 0) is 0 if X is negative. Otherwise it's LHSL.
3478 if ((N->getOpcode() == ISD::SMAX && isNullConstant(V: RHS)) ||
3479 (N->getOpcode() == ISD::SMIN && isAllOnesConstant(V: RHS))) {
3480 SDValue LHSL, LHSH, RHSL, RHSH;
3481 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3482 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3483 EVT NVT = LHSL.getValueType();
3484 EVT CCT = getSetCCResultType(VT: NVT);
3485
3486 SDValue HiNeg =
3487 DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: DAG.getConstant(Val: 0, DL, VT: NVT), Cond: ISD::SETLT);
3488 if (N->getOpcode() == ISD::SMIN) {
3489 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: LHSL, RHS: DAG.getAllOnesConstant(DL, VT: NVT));
3490 } else {
3491 Lo = DAG.getSelect(DL, VT: NVT, Cond: HiNeg, LHS: DAG.getConstant(Val: 0, DL, VT: NVT), RHS: LHSL);
3492 }
3493 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3494 return;
3495 }
3496
3497 const APInt *RHSVal = nullptr;
3498 if (auto *RHSConst = dyn_cast<ConstantSDNode>(Val&: RHS))
3499 RHSVal = &RHSConst->getAPIntValue();
3500
3501 // The high half of MIN/MAX is always just the the MIN/MAX of the
3502 // high halves of the operands. Expand this way if it appears profitable.
3503 if (RHSVal && (N->getOpcode() == ISD::UMIN || N->getOpcode() == ISD::UMAX) &&
3504 (RHSVal->countLeadingOnes() >= NumHalfBits ||
3505 RHSVal->countLeadingZeros() >= NumHalfBits)) {
3506 SDValue LHSL, LHSH, RHSL, RHSH;
3507 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3508 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3509 EVT NVT = LHSL.getValueType();
3510 EVT CCT = getSetCCResultType(VT: NVT);
3511
3512 ISD::NodeType LoOpc;
3513 ISD::CondCode CondC;
3514 std::tie(args&: CondC, args&: LoOpc) = getExpandedMinMaxOps(Op: N->getOpcode());
3515
3516 Hi = DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, Ops: {LHSH, RHSH});
3517 // We need to know whether to select Lo part that corresponds to 'winning'
3518 // Hi part or if Hi parts are equal.
3519 SDValue IsHiLeft = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: CondC);
3520 SDValue IsHiEq = DAG.getSetCC(DL, VT: CCT, LHS: LHSH, RHS: RHSH, Cond: ISD::SETEQ);
3521
3522 // Lo part corresponding to the 'winning' Hi part
3523 SDValue LoCmp = DAG.getSelect(DL, VT: NVT, Cond: IsHiLeft, LHS: LHSL, RHS: RHSL);
3524
3525 // Recursed Lo part if Hi parts are equal, this uses unsigned version
3526 SDValue LoMinMax = DAG.getNode(Opcode: LoOpc, DL, VT: NVT, Ops: {LHSL, RHSL});
3527
3528 Lo = DAG.getSelect(DL, VT: NVT, Cond: IsHiEq, LHS: LoMinMax, RHS: LoCmp);
3529 return;
3530 }
3531
3532 // Expand to "a < b ? a : b" etc. Prefer ge/le if that simplifies
3533 // the compare.
3534 ISD::CondCode Pred;
3535 switch (N->getOpcode()) {
3536 default: llvm_unreachable("How did we get here?");
3537 case ISD::SMAX:
3538 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3539 Pred = ISD::SETGE;
3540 else
3541 Pred = ISD::SETGT;
3542 break;
3543 case ISD::SMIN:
3544 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3545 Pred = ISD::SETLE;
3546 else
3547 Pred = ISD::SETLT;
3548 break;
3549 case ISD::UMAX:
3550 if (RHSVal && RHSVal->countTrailingZeros() >= NumHalfBits)
3551 Pred = ISD::SETUGE;
3552 else
3553 Pred = ISD::SETUGT;
3554 break;
3555 case ISD::UMIN:
3556 if (RHSVal && RHSVal->countTrailingOnes() >= NumHalfBits)
3557 Pred = ISD::SETULE;
3558 else
3559 Pred = ISD::SETULT;
3560 break;
3561 }
3562 EVT VT = N->getValueType(ResNo: 0);
3563 EVT CCT = getSetCCResultType(VT);
3564 SDValue Cond = DAG.getSetCC(DL, VT: CCT, LHS, RHS, Cond: Pred);
3565 SDValue Result = DAG.getSelect(DL, VT, Cond, LHS, RHS);
3566 SplitInteger(Op: Result, Lo, Hi);
3567}
3568
3569void DAGTypeLegalizer::ExpandIntRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
3570 SDValue ExpandedCMP = TLI.expandCMP(Node: N, DAG);
3571 SplitInteger(Op: ExpandedCMP, Lo, Hi);
3572}
3573
3574void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
3575 SDValue &Lo, SDValue &Hi) {
3576 SDLoc dl(N);
3577 // Expand the subcomponents.
3578 SDValue LHSL, LHSH, RHSL, RHSH;
3579 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3580 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3581
3582 EVT NVT = LHSL.getValueType();
3583 SDValue LoOps[2] = { LHSL, RHSL };
3584 SDValue HiOps[3] = { LHSH, RHSH };
3585
3586 bool HasOpCarry = TLI.isOperationLegalOrCustom(
3587 Op: N->getOpcode() == ISD::ADD ? ISD::UADDO_CARRY : ISD::USUBO_CARRY,
3588 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3589 if (HasOpCarry) {
3590 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
3591 if (N->getOpcode() == ISD::ADD) {
3592 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3593 HiOps[2] = Lo.getValue(R: 1);
3594 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3595 ? DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3596 : DAG.getNode(Opcode: ISD::UADDO_CARRY, DL: dl, VTList, Ops: HiOps);
3597 } else {
3598 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3599 HiOps[2] = Lo.getValue(R: 1);
3600 Hi = DAG.computeKnownBits(Op: HiOps[2]).isZero()
3601 ? DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2))
3602 : DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, Ops: HiOps);
3603 }
3604 return;
3605 }
3606
3607 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
3608 // them. TODO: Teach operation legalization how to expand unsupported
3609 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
3610 // a carry of type MVT::Glue, but there doesn't seem to be any way to
3611 // generate a value of this type in the expanded code sequence.
3612 bool hasCarry =
3613 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3614 ISD::ADDC : ISD::SUBC,
3615 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3616
3617 if (hasCarry) {
3618 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: MVT::Glue);
3619 if (N->getOpcode() == ISD::ADD) {
3620 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
3621 HiOps[2] = Lo.getValue(R: 1);
3622 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
3623 } else {
3624 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
3625 HiOps[2] = Lo.getValue(R: 1);
3626 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
3627 }
3628 return;
3629 }
3630
3631 bool hasOVF =
3632 TLI.isOperationLegalOrCustom(Op: N->getOpcode() == ISD::ADD ?
3633 ISD::UADDO : ISD::USUBO,
3634 VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
3635 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(Type: NVT);
3636
3637 if (hasOVF) {
3638 EVT OvfVT = getSetCCResultType(VT: NVT);
3639 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: OvfVT);
3640 int RevOpc;
3641 if (N->getOpcode() == ISD::ADD) {
3642 RevOpc = ISD::SUB;
3643 Lo = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList, Ops: LoOps);
3644 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3645 } else {
3646 RevOpc = ISD::ADD;
3647 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, Ops: LoOps);
3648 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3649 }
3650 SDValue OVF = Lo.getValue(R: 1);
3651
3652 switch (BoolType) {
3653 case TargetLoweringBase::UndefinedBooleanContent:
3654 OVF = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: OvfVT, N1: DAG.getConstant(Val: 1, DL: dl, VT: OvfVT), N2: OVF);
3655 [[fallthrough]];
3656 case TargetLoweringBase::ZeroOrOneBooleanContent:
3657 OVF = DAG.getZExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3658 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, N1: Hi, N2: OVF);
3659 break;
3660 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
3661 OVF = DAG.getSExtOrTrunc(Op: OVF, DL: dl, VT: NVT);
3662 Hi = DAG.getNode(Opcode: RevOpc, DL: dl, VT: NVT, N1: Hi, N2: OVF);
3663 }
3664 return;
3665 }
3666
3667 if (N->getOpcode() == ISD::ADD) {
3668 Lo = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: LoOps);
3669 SDValue Cmp;
3670 // Special case: X+1 has a carry out if X+1==0. This may reduce the live
3671 // range of X. We assume comparing with 0 is cheap.
3672 if (isOneConstant(V: LoOps[1]))
3673 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
3674 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
3675 else if (isAllOnesConstant(V: LoOps[1])) {
3676 if (isAllOnesConstant(V: HiOps[1]))
3677 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
3678 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETEQ);
3679 else
3680 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: LoOps[0],
3681 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
3682 } else
3683 Cmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo, RHS: LoOps[0],
3684 Cond: ISD::SETULT);
3685
3686 SDValue Carry;
3687 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
3688 Carry = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
3689 else
3690 Carry = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
3691 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
3692
3693 if (isAllOnesConstant(V: LoOps[1]) && isAllOnesConstant(V: HiOps[1])) {
3694 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: HiOps[0], N2: Carry);
3695 } else {
3696 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3697 Hi = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: Hi, N2: Carry);
3698 }
3699 } else {
3700 Lo = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: LoOps);
3701 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, Ops: ArrayRef(HiOps, 2));
3702 SDValue Cmp =
3703 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LoOps[0].getValueType()),
3704 LHS: LoOps[0], RHS: LoOps[1], Cond: ISD::SETULT);
3705
3706 SDValue Borrow;
3707 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
3708 Borrow = DAG.getZExtOrTrunc(Op: Cmp, DL: dl, VT: NVT);
3709 else
3710 Borrow = DAG.getSelect(DL: dl, VT: NVT, Cond: Cmp, LHS: DAG.getConstant(Val: 1, DL: dl, VT: NVT),
3711 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT));
3712
3713 Hi = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: Hi, N2: Borrow);
3714 }
3715}
3716
3717void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
3718 SDValue &Lo, SDValue &Hi) {
3719 // Expand the subcomponents.
3720 SDValue LHSL, LHSH, RHSL, RHSH;
3721 SDLoc dl(N);
3722 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3723 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3724 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
3725 SDValue LoOps[2] = { LHSL, RHSL };
3726 SDValue HiOps[3] = { LHSH, RHSH };
3727
3728 if (N->getOpcode() == ISD::ADDC) {
3729 Lo = DAG.getNode(Opcode: ISD::ADDC, DL: dl, VTList, Ops: LoOps);
3730 HiOps[2] = Lo.getValue(R: 1);
3731 Hi = DAG.getNode(Opcode: ISD::ADDE, DL: dl, VTList, Ops: HiOps);
3732 } else {
3733 Lo = DAG.getNode(Opcode: ISD::SUBC, DL: dl, VTList, Ops: LoOps);
3734 HiOps[2] = Lo.getValue(R: 1);
3735 Hi = DAG.getNode(Opcode: ISD::SUBE, DL: dl, VTList, Ops: HiOps);
3736 }
3737
3738 // Legalized the flag result - switch anything that used the old flag to
3739 // use the new one.
3740 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3741}
3742
3743void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
3744 SDValue &Lo, SDValue &Hi) {
3745 // Expand the subcomponents.
3746 SDValue LHSL, LHSH, RHSL, RHSH;
3747 SDLoc dl(N);
3748 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3749 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3750 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: MVT::Glue);
3751 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
3752 SDValue HiOps[3] = { LHSH, RHSH };
3753
3754 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
3755 HiOps[2] = Lo.getValue(R: 1);
3756 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
3757
3758 // Legalized the flag result - switch anything that used the old flag to
3759 // use the new one.
3760 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3761}
3762
3763void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
3764 SDValue &Lo, SDValue &Hi) {
3765 SDValue LHS = N->getOperand(Num: 0);
3766 SDValue RHS = N->getOperand(Num: 1);
3767 SDLoc dl(N);
3768
3769 SDValue Ovf;
3770
3771 unsigned CarryOp, NoCarryOp;
3772 ISD::CondCode Cond;
3773 switch(N->getOpcode()) {
3774 case ISD::UADDO:
3775 CarryOp = ISD::UADDO_CARRY;
3776 NoCarryOp = ISD::ADD;
3777 Cond = ISD::SETULT;
3778 break;
3779 case ISD::USUBO:
3780 CarryOp = ISD::USUBO_CARRY;
3781 NoCarryOp = ISD::SUB;
3782 Cond = ISD::SETUGT;
3783 break;
3784 default:
3785 llvm_unreachable("Node has unexpected Opcode");
3786 }
3787
3788 bool HasCarryOp = TLI.isOperationLegalOrCustom(
3789 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
3790
3791 if (HasCarryOp) {
3792 // Expand the subcomponents.
3793 SDValue LHSL, LHSH, RHSL, RHSH;
3794 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
3795 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
3796 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
3797 SDValue LoOps[2] = { LHSL, RHSL };
3798 SDValue HiOps[3] = { LHSH, RHSH };
3799
3800 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
3801 HiOps[2] = Lo.getValue(R: 1);
3802 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: HiOps);
3803
3804 Ovf = Hi.getValue(R: 1);
3805 } else {
3806 // Expand the result by simply replacing it with the equivalent
3807 // non-overflow-checking operation.
3808 SDValue Sum = DAG.getNode(Opcode: NoCarryOp, DL: dl, VT: LHS.getValueType(), N1: LHS, N2: RHS);
3809 SplitInteger(Op: Sum, Lo, Hi);
3810
3811 if (N->getOpcode() == ISD::UADDO && isOneConstant(V: RHS)) {
3812 // Special case: uaddo X, 1 overflowed if X+1 == 0. We can detect this
3813 // with (Lo | Hi) == 0.
3814 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: Lo.getValueType(), N1: Lo, N2: Hi);
3815 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Or,
3816 RHS: DAG.getConstant(Val: 0, DL: dl, VT: Lo.getValueType()), Cond: ISD::SETEQ);
3817 } else if (N->getOpcode() == ISD::UADDO && isAllOnesConstant(V: RHS)) {
3818 // Special case: uaddo X, -1 overflows if X == 0.
3819 Ovf =
3820 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS,
3821 RHS: DAG.getConstant(Val: 0, DL: dl, VT: LHS.getValueType()), Cond: ISD::SETNE);
3822 } else {
3823 // Calculate the overflow: addition overflows iff a + b < a, and
3824 // subtraction overflows iff a - b > a.
3825 Ovf = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Sum, RHS: LHS, Cond);
3826 }
3827 }
3828
3829 // Legalized the flag result - switch anything that used the old flag to
3830 // use the new one.
3831 ReplaceValueWith(From: SDValue(N, 1), To: Ovf);
3832}
3833
3834void DAGTypeLegalizer::ExpandIntRes_UADDSUBO_CARRY(SDNode *N, SDValue &Lo,
3835 SDValue &Hi) {
3836 // Expand the subcomponents.
3837 SDValue LHSL, LHSH, RHSL, RHSH;
3838 SDLoc dl(N);
3839 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3840 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3841 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
3842 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(Num: 2) };
3843 SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
3844
3845 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: LoOps);
3846 HiOps[2] = Lo.getValue(R: 1);
3847 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: HiOps);
3848
3849 // Legalized the flag result - switch anything that used the old flag to
3850 // use the new one.
3851 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3852}
3853
3854void DAGTypeLegalizer::ExpandIntRes_SADDSUBO_CARRY(SDNode *N,
3855 SDValue &Lo, SDValue &Hi) {
3856 // Expand the subcomponents.
3857 SDValue LHSL, LHSH, RHSL, RHSH;
3858 SDLoc dl(N);
3859 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
3860 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RHSL, Hi&: RHSH);
3861 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: N->getValueType(ResNo: 1));
3862
3863 // We need to use an unsigned carry op for the lo part.
3864 unsigned CarryOp =
3865 N->getOpcode() == ISD::SADDO_CARRY ? ISD::UADDO_CARRY : ISD::USUBO_CARRY;
3866 Lo = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSL, RHSL, N->getOperand(Num: 2) });
3867 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
3868
3869 // Legalized the flag result - switch anything that used the old flag to
3870 // use the new one.
3871 ReplaceValueWith(From: SDValue(N, 1), To: Hi.getValue(R: 1));
3872}
3873
3874void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
3875 SDValue &Lo, SDValue &Hi) {
3876 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3877 SDLoc dl(N);
3878 SDValue Op = N->getOperand(Num: 0);
3879 if (Op.getValueType().bitsLE(VT: NVT)) {
3880 // The low part is any extension of the input (which degenerates to a copy).
3881 Lo = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Op);
3882 Hi = DAG.getUNDEF(VT: NVT); // The high part is undefined.
3883 } else {
3884 // For example, extension of an i48 to an i64. The operand type necessarily
3885 // promotes to the result type, so will end up being expanded too.
3886 assert(getTypeAction(Op.getValueType()) ==
3887 TargetLowering::TypePromoteInteger &&
3888 "Only know how to promote this result!");
3889 SDValue Res = GetPromotedInteger(Op);
3890 assert(Res.getValueType() == N->getValueType(0) &&
3891 "Operand over promoted?");
3892 // Split the promoted operand. This will simplify when it is expanded.
3893 SplitInteger(Op: Res, Lo, Hi);
3894 }
3895}
3896
3897void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
3898 SDValue &Lo, SDValue &Hi) {
3899 SDLoc dl(N);
3900 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
3901 EVT NVT = Lo.getValueType();
3902 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
3903 unsigned NVTBits = NVT.getSizeInBits();
3904 unsigned EVTBits = EVT.getSizeInBits();
3905
3906 if (NVTBits < EVTBits) {
3907 Hi = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Hi,
3908 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
3909 BitWidth: EVTBits - NVTBits)));
3910 } else {
3911 Lo = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
3912 // The high part replicates the sign bit of Lo, make it explicit.
3913 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
3914 N2: DAG.getConstant(Val: NVTBits - 1, DL: dl,
3915 VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
3916 }
3917}
3918
3919void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
3920 SDValue &Lo, SDValue &Hi) {
3921 SDLoc dl(N);
3922 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
3923 EVT NVT = Lo.getValueType();
3924 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
3925 unsigned NVTBits = NVT.getSizeInBits();
3926 unsigned EVTBits = EVT.getSizeInBits();
3927
3928 if (NVTBits < EVTBits) {
3929 Hi = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Hi,
3930 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
3931 BitWidth: EVTBits - NVTBits)));
3932 } else {
3933 Lo = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: NVT, N1: Lo, N2: DAG.getValueType(EVT));
3934 // The high part must be zero, make it explicit.
3935 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
3936 }
3937}
3938
3939void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
3940 SDValue &Lo, SDValue &Hi) {
3941 SDLoc dl(N);
3942 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
3943 Lo = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Lo.getValueType(), Operand: Lo);
3944 Hi = DAG.getNode(Opcode: ISD::BITREVERSE, DL: dl, VT: Hi.getValueType(), Operand: Hi);
3945}
3946
3947void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
3948 SDValue &Lo, SDValue &Hi) {
3949 SDLoc dl(N);
3950 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: Hi, Hi&: Lo); // Note swapped operands.
3951 Lo = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Lo.getValueType(), Operand: Lo);
3952 Hi = DAG.getNode(Opcode: ISD::BSWAP, DL: dl, VT: Hi.getValueType(), Operand: Hi);
3953}
3954
3955void DAGTypeLegalizer::ExpandIntRes_PARITY(SDNode *N, SDValue &Lo,
3956 SDValue &Hi) {
3957 SDLoc dl(N);
3958 // parity(HiLo) -> parity(Lo^Hi)
3959 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
3960 EVT NVT = Lo.getValueType();
3961 Lo =
3962 DAG.getNode(Opcode: ISD::PARITY, DL: dl, VT: NVT, Operand: DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Hi));
3963 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
3964}
3965
3966void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
3967 SDValue &Lo, SDValue &Hi) {
3968 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
3969 unsigned NBitWidth = NVT.getSizeInBits();
3970 auto Constant = cast<ConstantSDNode>(Val: N);
3971 const APInt &Cst = Constant->getAPIntValue();
3972 bool IsTarget = Constant->isTargetOpcode();
3973 bool IsOpaque = Constant->isOpaque();
3974 SDLoc dl(N);
3975 Lo = DAG.getConstant(Val: Cst.trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget, isOpaque: IsOpaque);
3976 Hi = DAG.getConstant(Val: Cst.lshr(shiftAmt: NBitWidth).trunc(width: NBitWidth), DL: dl, VT: NVT, isTarget: IsTarget,
3977 isOpaque: IsOpaque);
3978}
3979
3980void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
3981 SDLoc dl(N);
3982
3983 SDValue N0 = N->getOperand(Num: 0);
3984 GetExpandedInteger(Op: N0, Lo, Hi);
3985 EVT NVT = Lo.getValueType();
3986
3987 // If the upper half is all sign bits, then we can perform the ABS on the
3988 // lower half and zero-extend.
3989 if (DAG.ComputeNumSignBits(Op: N0) > NVT.getScalarSizeInBits()) {
3990 Lo = DAG.getNode(Opcode: ISD::ABS, DL: dl, VT: NVT, Operand: Lo);
3991 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
3992 return;
3993 }
3994
3995 // If we have USUBO_CARRY, use the expanded form of the sra+xor+sub sequence
3996 // we use in LegalizeDAG. The SUB part of the expansion is based on
3997 // ExpandIntRes_ADDSUB which also uses USUBO_CARRY/USUBO after checking that
3998 // USUBO_CARRY is LegalOrCustom. Each of the pieces here can be further
3999 // expanded if needed. Shift expansion has a special case for filling with
4000 // sign bits so that we will only end up with one SRA.
4001 bool HasSubCarry = TLI.isOperationLegalOrCustom(
4002 Op: ISD::USUBO_CARRY, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: NVT));
4003 if (HasSubCarry) {
4004 SDValue Sign = DAG.getNode(
4005 Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Hi,
4006 N2: DAG.getShiftAmountConstant(Val: NVT.getSizeInBits() - 1, VT: NVT, DL: dl));
4007 SDVTList VTList = DAG.getVTList(VT1: NVT, VT2: getSetCCResultType(VT: NVT));
4008 Lo = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Lo, N2: Sign);
4009 Hi = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: NVT, N1: Hi, N2: Sign);
4010 Lo = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: Lo, N2: Sign);
4011 Hi = DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: Hi, N2: Sign, N3: Lo.getValue(R: 1));
4012 return;
4013 }
4014
4015 // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
4016 EVT VT = N->getValueType(ResNo: 0);
4017 SDValue Neg = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT,
4018 N1: DAG.getConstant(Val: 0, DL: dl, VT), N2: N0);
4019 SDValue NegLo, NegHi;
4020 SplitInteger(Op: Neg, Lo&: NegLo, Hi&: NegHi);
4021
4022 SDValue HiIsNeg = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4023 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETLT);
4024 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegLo, RHS: Lo);
4025 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: HiIsNeg, LHS: NegHi, RHS: Hi);
4026}
4027
4028void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
4029 SDValue &Lo, SDValue &Hi) {
4030 SDLoc dl(N);
4031 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
4032 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4033 EVT NVT = Lo.getValueType();
4034
4035 SDValue HiNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Hi,
4036 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4037
4038 SDValue LoLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Lo);
4039 SDValue HiLZ = DAG.getNode(Opcode: ISD::CTLZ_ZERO_UNDEF, DL: dl, VT: NVT, Operand: Hi);
4040
4041 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: HiNotZero, LHS: HiLZ,
4042 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: LoLZ,
4043 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4044 VT: NVT)));
4045 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4046}
4047
4048void DAGTypeLegalizer::ExpandIntRes_ABD(SDNode *N, SDValue &Lo, SDValue &Hi) {
4049 SDValue Result = TLI.expandABD(N, DAG);
4050 SplitInteger(Op: Result, Lo, Hi);
4051}
4052
4053void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, SDValue &Lo, SDValue &Hi) {
4054 SDValue Op = N->getOperand(Num: 0);
4055 EVT VT = N->getValueType(ResNo: 0);
4056 SDLoc DL(N);
4057
4058 if (TLI.getOperationAction(Op: ISD::CTPOP, VT) == TargetLoweringBase::LibCall) {
4059 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4060 if (VT == MVT::i32)
4061 LC = RTLIB::CTPOP_I32;
4062 else if (VT == MVT::i64)
4063 LC = RTLIB::CTPOP_I64;
4064 else if (VT == MVT::i128)
4065 LC = RTLIB::CTPOP_I128;
4066 assert(LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC) &&
4067 "LibCall explicitly requested, but not available");
4068 TargetLowering::MakeLibCallOptions CallOptions;
4069 EVT IntVT =
4070 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
4071 SDValue Res = TLI.makeLibCall(DAG, LC, RetVT: IntVT, Ops: Op, CallOptions, dl: DL).first;
4072 SplitInteger(Op: DAG.getSExtOrTrunc(Op: Res, DL, VT), Lo, Hi);
4073 return;
4074 }
4075
4076 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
4077 GetExpandedInteger(Op, Lo, Hi);
4078 EVT NVT = Lo.getValueType();
4079 Lo = DAG.getNode(Opcode: ISD::ADD, DL, VT: NVT, N1: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Lo),
4080 N2: DAG.getNode(Opcode: ISD::CTPOP, DL, VT: NVT, Operand: Hi));
4081 Hi = DAG.getConstant(Val: 0, DL, VT: NVT);
4082}
4083
4084void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
4085 SDValue &Lo, SDValue &Hi) {
4086 SDLoc dl(N);
4087 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
4088 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
4089 EVT NVT = Lo.getValueType();
4090
4091 SDValue LoNotZero = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: NVT), LHS: Lo,
4092 RHS: DAG.getConstant(Val: 0, DL: dl, VT: NVT), Cond: ISD::SETNE);
4093
4094 SDValue LoLZ = DAG.getNode(Opcode: ISD::CTTZ_ZERO_UNDEF, DL: dl, VT: NVT, Operand: Lo);
4095 SDValue HiLZ = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Hi);
4096
4097 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: LoNotZero, LHS: LoLZ,
4098 RHS: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: NVT, N1: HiLZ,
4099 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
4100 VT: NVT)));
4101 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4102}
4103
4104void DAGTypeLegalizer::ExpandIntRes_GET_ROUNDING(SDNode *N, SDValue &Lo,
4105 SDValue &Hi) {
4106 SDLoc dl(N);
4107 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4108 unsigned NBitWidth = NVT.getSizeInBits();
4109
4110 Lo = DAG.getNode(Opcode: ISD::GET_ROUNDING, DL: dl, ResultTys: {NVT, MVT::Other}, Ops: N->getOperand(Num: 0));
4111 SDValue Chain = Lo.getValue(R: 1);
4112 // The high part is the sign of Lo, as -1 is a valid value for GET_ROUNDING
4113 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4114 N2: DAG.getShiftAmountConstant(Val: NBitWidth - 1, VT: NVT, DL: dl));
4115
4116 // Legalize the chain result - switch anything that used the old chain to
4117 // use the new one.
4118 ReplaceValueWith(From: SDValue(N, 1), To: Chain);
4119}
4120
4121// Helper for producing an FP_EXTEND/STRICT_FP_EXTEND of Op.
4122static SDValue fpExtendHelper(SDValue Op, SDValue &Chain, bool IsStrict, EVT VT,
4123 SDLoc DL, SelectionDAG &DAG) {
4124 if (IsStrict) {
4125 Op = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL, ResultTys: {VT, MVT::Other}, Ops: {Chain, Op});
4126 Chain = Op.getValue(R: 1);
4127 return Op;
4128 }
4129 return DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT, Operand: Op);
4130}
4131
4132void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT(SDNode *N, SDValue &Lo,
4133 SDValue &Hi) {
4134 SDLoc dl(N);
4135 EVT VT = N->getValueType(ResNo: 0);
4136
4137 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
4138 N->getOpcode() == ISD::STRICT_FP_TO_SINT;
4139 bool IsStrict = N->isStrictFPOpcode();
4140 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4141 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4142 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypePromoteFloat)
4143 Op = GetPromotedFloat(Op);
4144
4145 // If the input is bf16 or needs to be soft promoted, extend to f32.
4146 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf ||
4147 Op.getValueType() == MVT::bf16) {
4148 Op = fpExtendHelper(Op, Chain, IsStrict, VT: MVT::f32, DL: dl, DAG);
4149 }
4150
4151 // NOTE: We need a variable that lives across makeLibCall so
4152 // CallOptions.setTypeListBeforeSoften can save a reference to it.
4153 EVT OpVT = Op.getValueType();
4154
4155 RTLIB::Libcall LC =
4156 IsSigned ? RTLIB::getFPTOSINT(OpVT, RetVT: VT) : RTLIB::getFPTOUINT(OpVT, RetVT: VT);
4157 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-xint conversion!");
4158 TargetLowering::MakeLibCallOptions CallOptions;
4159 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypeSoftenFloat)
4160 CallOptions.setTypeListBeforeSoften(OpsVT: OpVT, RetVT: VT);
4161 else
4162 CallOptions.setIsSigned(true); // FIXME: Is this needed?
4163 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT: VT, Ops: Op,
4164 CallOptions, dl, Chain);
4165 SplitInteger(Op: Tmp.first, Lo, Hi);
4166
4167 if (IsStrict)
4168 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4169}
4170
4171void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo,
4172 SDValue &Hi) {
4173 SDValue Res = TLI.expandFP_TO_INT_SAT(N, DAG);
4174 SplitInteger(Op: Res, Lo, Hi);
4175}
4176
4177void DAGTypeLegalizer::ExpandIntRes_XROUND_XRINT(SDNode *N, SDValue &Lo,
4178 SDValue &Hi) {
4179 SDLoc dl(N);
4180 bool IsStrict = N->isStrictFPOpcode();
4181 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
4182 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
4183
4184 assert(getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat &&
4185 "Input type needs to be promoted!");
4186
4187 EVT VT = Op.getValueType();
4188
4189 if (VT == MVT::f16) {
4190 // Extend to f32.
4191 VT = MVT::f32;
4192 Op = fpExtendHelper(Op, Chain, IsStrict, VT, DL: dl, DAG);
4193 }
4194
4195 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4196 if (N->getOpcode() == ISD::LROUND ||
4197 N->getOpcode() == ISD::STRICT_LROUND) {
4198 if (VT == MVT::f32)
4199 LC = RTLIB::LROUND_F32;
4200 else if (VT == MVT::f64)
4201 LC = RTLIB::LROUND_F64;
4202 else if (VT == MVT::f80)
4203 LC = RTLIB::LROUND_F80;
4204 else if (VT == MVT::f128)
4205 LC = RTLIB::LROUND_F128;
4206 else if (VT == MVT::ppcf128)
4207 LC = RTLIB::LROUND_PPCF128;
4208 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lround input type!");
4209 } else if (N->getOpcode() == ISD::LRINT ||
4210 N->getOpcode() == ISD::STRICT_LRINT) {
4211 if (VT == MVT::f32)
4212 LC = RTLIB::LRINT_F32;
4213 else if (VT == MVT::f64)
4214 LC = RTLIB::LRINT_F64;
4215 else if (VT == MVT::f80)
4216 LC = RTLIB::LRINT_F80;
4217 else if (VT == MVT::f128)
4218 LC = RTLIB::LRINT_F128;
4219 else if (VT == MVT::ppcf128)
4220 LC = RTLIB::LRINT_PPCF128;
4221 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected lrint input type!");
4222 } else if (N->getOpcode() == ISD::LLROUND ||
4223 N->getOpcode() == ISD::STRICT_LLROUND) {
4224 if (VT == MVT::f32)
4225 LC = RTLIB::LLROUND_F32;
4226 else if (VT == MVT::f64)
4227 LC = RTLIB::LLROUND_F64;
4228 else if (VT == MVT::f80)
4229 LC = RTLIB::LLROUND_F80;
4230 else if (VT == MVT::f128)
4231 LC = RTLIB::LLROUND_F128;
4232 else if (VT == MVT::ppcf128)
4233 LC = RTLIB::LLROUND_PPCF128;
4234 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!");
4235 } else if (N->getOpcode() == ISD::LLRINT ||
4236 N->getOpcode() == ISD::STRICT_LLRINT) {
4237 if (VT == MVT::f32)
4238 LC = RTLIB::LLRINT_F32;
4239 else if (VT == MVT::f64)
4240 LC = RTLIB::LLRINT_F64;
4241 else if (VT == MVT::f80)
4242 LC = RTLIB::LLRINT_F80;
4243 else if (VT == MVT::f128)
4244 LC = RTLIB::LLRINT_F128;
4245 else if (VT == MVT::ppcf128)
4246 LC = RTLIB::LLRINT_PPCF128;
4247 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!");
4248 } else
4249 llvm_unreachable("Unexpected opcode!");
4250
4251 EVT RetVT = N->getValueType(ResNo: 0);
4252
4253 TargetLowering::MakeLibCallOptions CallOptions;
4254 CallOptions.setIsSigned(true);
4255 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
4256 Ops: Op, CallOptions, dl,
4257 Chain);
4258 SplitInteger(Op: Tmp.first, Lo, Hi);
4259
4260 if (N->isStrictFPOpcode())
4261 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
4262}
4263
4264void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
4265 SDValue &Lo, SDValue &Hi) {
4266 assert(!N->isAtomic() && "Should have been a ATOMIC_LOAD?");
4267
4268 if (ISD::isNormalLoad(N)) {
4269 ExpandRes_NormalLoad(N, Lo, Hi);
4270 return;
4271 }
4272
4273 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
4274
4275 EVT VT = N->getValueType(ResNo: 0);
4276 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4277 SDValue Ch = N->getChain();
4278 SDValue Ptr = N->getBasePtr();
4279 ISD::LoadExtType ExtType = N->getExtensionType();
4280 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
4281 AAMDNodes AAInfo = N->getAAInfo();
4282 SDLoc dl(N);
4283
4284 assert(NVT.isByteSized() && "Expanded type not byte sized!");
4285
4286 if (N->getMemoryVT().bitsLE(VT: NVT)) {
4287 EVT MemVT = N->getMemoryVT();
4288
4289 Lo = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), MemVT,
4290 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4291
4292 // Remember the chain.
4293 Ch = Lo.getValue(R: 1);
4294
4295 if (ExtType == ISD::SEXTLOAD) {
4296 // The high part is obtained by SRA'ing all but one of the bits of the
4297 // lo part.
4298 unsigned LoSize = Lo.getValueSizeInBits();
4299 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
4300 N2: DAG.getConstant(Val: LoSize - 1, DL: dl,
4301 VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
4302 } else if (ExtType == ISD::ZEXTLOAD) {
4303 // The high part is just a zero.
4304 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4305 } else {
4306 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
4307 // The high part is undefined.
4308 Hi = DAG.getUNDEF(VT: NVT);
4309 }
4310 } else if (DAG.getDataLayout().isLittleEndian()) {
4311 // Little-endian - low bits are at low addresses.
4312 Lo = DAG.getLoad(VT: NVT, dl, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
4313 MMOFlags, AAInfo);
4314
4315 unsigned ExcessBits =
4316 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
4317 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
4318
4319 // Increment the pointer to the other half.
4320 unsigned IncrementSize = NVT.getSizeInBits()/8;
4321 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4322 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr,
4323 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize), MemVT: NEVT,
4324 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4325
4326 // Build a factor node to remember that this load is independent of the
4327 // other one.
4328 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4329 N2: Hi.getValue(R: 1));
4330 } else {
4331 // Big-endian - high bits are at low addresses. Favor aligned loads at
4332 // the cost of some bit-fiddling.
4333 EVT MemVT = N->getMemoryVT();
4334 unsigned EBytes = MemVT.getStoreSize();
4335 unsigned IncrementSize = NVT.getSizeInBits()/8;
4336 unsigned ExcessBits = (EBytes - IncrementSize)*8;
4337
4338 // Load both the high bits and maybe some of the low bits.
4339 Hi = DAG.getExtLoad(ExtType, dl, VT: NVT, Chain: Ch, Ptr, PtrInfo: N->getPointerInfo(),
4340 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(),
4341 BitWidth: MemVT.getSizeInBits() - ExcessBits),
4342 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4343
4344 // Increment the pointer to the other half.
4345 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
4346 // Load the rest of the low bits.
4347 Lo = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl, VT: NVT, Chain: Ch, Ptr,
4348 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
4349 MemVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
4350 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
4351
4352 // Build a factor node to remember that this load is independent of the
4353 // other one.
4354 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
4355 N2: Hi.getValue(R: 1));
4356
4357 if (ExcessBits < NVT.getSizeInBits()) {
4358 // Transfer low bits from the bottom of Hi to the top of Lo.
4359 Lo = DAG.getNode(
4360 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Lo,
4361 N2: DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
4362 N2: DAG.getConstant(Val: ExcessBits, DL: dl,
4363 VT: TLI.getPointerTy(DL: DAG.getDataLayout()))));
4364 // Move high bits to the right position in Hi.
4365 Hi = DAG.getNode(Opcode: ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, DL: dl, VT: NVT,
4366 N1: Hi,
4367 N2: DAG.getConstant(Val: NVT.getSizeInBits() - ExcessBits, DL: dl,
4368 VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
4369 }
4370 }
4371
4372 // Legalize the chain result - switch anything that used the old chain to
4373 // use the new one.
4374 ReplaceValueWith(From: SDValue(N, 1), To: Ch);
4375}
4376
4377void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
4378 SDValue &Lo, SDValue &Hi) {
4379 SDLoc dl(N);
4380 SDValue LL, LH, RL, RH;
4381 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4382 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4383 Lo = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LL, N2: RL);
4384 Hi = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: LL.getValueType(), N1: LH, N2: RH);
4385}
4386
4387void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
4388 SDValue &Lo, SDValue &Hi) {
4389 EVT VT = N->getValueType(ResNo: 0);
4390 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4391 SDLoc dl(N);
4392
4393 SDValue LL, LH, RL, RH;
4394 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LL, Hi&: LH);
4395 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: RL, Hi&: RH);
4396
4397 if (TLI.expandMUL(N, Lo, Hi, HiLoVT: NVT, DAG,
4398 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4399 LL, LH, RL, RH))
4400 return;
4401
4402 // If nothing else, we can make a libcall.
4403 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4404 if (VT == MVT::i16)
4405 LC = RTLIB::MUL_I16;
4406 else if (VT == MVT::i32)
4407 LC = RTLIB::MUL_I32;
4408 else if (VT == MVT::i64)
4409 LC = RTLIB::MUL_I64;
4410 else if (VT == MVT::i128)
4411 LC = RTLIB::MUL_I128;
4412
4413 if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(Call: LC)) {
4414 // Perform a wide multiplication where the wide type is the original VT and
4415 // the 4 parts are the split arguments.
4416 TLI.forceExpandMultiply(DAG, dl, /*Signed=*/false, Lo, Hi, LHS: LL, RHS: RL, HiLHS: LH, HiRHS: RH);
4417 return;
4418 }
4419
4420 // Note that we don't need to do a wide MUL here since we don't care about the
4421 // upper half of the result if it exceeds VT.
4422 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
4423 TargetLowering::MakeLibCallOptions CallOptions;
4424 CallOptions.setIsSigned(true);
4425 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first,
4426 Lo, Hi);
4427}
4428
4429void DAGTypeLegalizer::ExpandIntRes_READCOUNTER(SDNode *N, SDValue &Lo,
4430 SDValue &Hi) {
4431 SDLoc DL(N);
4432 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
4433 SDVTList VTs = DAG.getVTList(VT1: NVT, VT2: NVT, VT3: MVT::Other);
4434 SDValue R = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: VTs, N: N->getOperand(Num: 0));
4435 Lo = R.getValue(R: 0);
4436 Hi = R.getValue(R: 1);
4437 ReplaceValueWith(From: SDValue(N, 1), To: R.getValue(R: 2));
4438}
4439
4440void DAGTypeLegalizer::ExpandIntRes_AVG(SDNode *N, SDValue &Lo, SDValue &Hi) {
4441 SDValue Result = TLI.expandAVG(N, DAG);
4442 SplitInteger(Op: Result, Lo, Hi);
4443}
4444
4445void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
4446 SDValue &Hi) {
4447 SDValue Result = TLI.expandAddSubSat(Node: N, DAG);
4448 SplitInteger(Op: Result, Lo, Hi);
4449}
4450
4451void DAGTypeLegalizer::ExpandIntRes_SHLSAT(SDNode *N, SDValue &Lo,
4452 SDValue &Hi) {
4453 SDValue Result = TLI.expandShlSat(Node: N, DAG);
4454 SplitInteger(Op: Result, Lo, Hi);
4455}
4456
4457/// This performs an expansion of the integer result for a fixed point
4458/// multiplication. The default expansion performs rounding down towards
4459/// negative infinity, though targets that do care about rounding should specify
4460/// a target hook for rounding and provide their own expansion or lowering of
4461/// fixed point multiplication to be consistent with rounding.
4462void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
4463 SDValue &Hi) {
4464 SDLoc dl(N);
4465 EVT VT = N->getValueType(ResNo: 0);
4466 unsigned VTSize = VT.getScalarSizeInBits();
4467 SDValue LHS = N->getOperand(Num: 0);
4468 SDValue RHS = N->getOperand(Num: 1);
4469 uint64_t Scale = N->getConstantOperandVal(Num: 2);
4470 bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
4471 N->getOpcode() == ISD::UMULFIXSAT);
4472 bool Signed = (N->getOpcode() == ISD::SMULFIX ||
4473 N->getOpcode() == ISD::SMULFIXSAT);
4474
4475 // Handle special case when scale is equal to zero.
4476 if (!Scale) {
4477 SDValue Result;
4478 if (!Saturating) {
4479 Result = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: LHS, N2: RHS);
4480 } else {
4481 EVT BoolVT = getSetCCResultType(VT);
4482 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
4483 Result = DAG.getNode(Opcode: MulOp, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: BoolVT), N1: LHS, N2: RHS);
4484 SDValue Product = Result.getValue(R: 0);
4485 SDValue Overflow = Result.getValue(R: 1);
4486 if (Signed) {
4487 APInt MinVal = APInt::getSignedMinValue(numBits: VTSize);
4488 APInt MaxVal = APInt::getSignedMaxValue(numBits: VTSize);
4489 SDValue SatMin = DAG.getConstant(Val: MinVal, DL: dl, VT);
4490 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4491 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
4492 // Xor the inputs, if resulting sign bit is 0 the product will be
4493 // positive, else negative.
4494 SDValue Xor = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
4495 SDValue ProdNeg = DAG.getSetCC(DL: dl, VT: BoolVT, LHS: Xor, RHS: Zero, Cond: ISD::SETLT);
4496 Result = DAG.getSelect(DL: dl, VT, Cond: ProdNeg, LHS: SatMin, RHS: SatMax);
4497 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: Result, RHS: Product);
4498 } else {
4499 // For unsigned multiplication, we only need to check the max since we
4500 // can't really overflow towards zero.
4501 APInt MaxVal = APInt::getMaxValue(numBits: VTSize);
4502 SDValue SatMax = DAG.getConstant(Val: MaxVal, DL: dl, VT);
4503 Result = DAG.getSelect(DL: dl, VT, Cond: Overflow, LHS: SatMax, RHS: Product);
4504 }
4505 }
4506 SplitInteger(Op: Result, Lo, Hi);
4507 return;
4508 }
4509
4510 // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
4511 // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
4512 assert(Scale <= VTSize && "Scale can't be larger than the value type size.");
4513
4514 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4515 SDValue LL, LH, RL, RH;
4516 GetExpandedInteger(Op: LHS, Lo&: LL, Hi&: LH);
4517 GetExpandedInteger(Op: RHS, Lo&: RL, Hi&: RH);
4518 SmallVector<SDValue, 4> Result;
4519
4520 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
4521 if (!TLI.expandMUL_LOHI(Opcode: LoHiOp, VT, dl, LHS, RHS, Result, HiLoVT: NVT, DAG,
4522 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
4523 LL, LH, RL, RH)) {
4524 Result.clear();
4525 Result.resize(N: 4);
4526
4527 SDValue LoTmp, HiTmp;
4528 TLI.forceExpandWideMUL(DAG, dl, Signed, LHS, RHS, Lo&: LoTmp, Hi&: HiTmp);
4529 SplitInteger(Op: LoTmp, Lo&: Result[0], Hi&: Result[1]);
4530 SplitInteger(Op: HiTmp, Lo&: Result[2], Hi&: Result[3]);
4531 }
4532 assert(Result.size() == 4 && "Unexpected number of partlets in the result");
4533
4534 unsigned NVTSize = NVT.getScalarSizeInBits();
4535 assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "
4536 "the size of the current value type");
4537
4538 // After getting the multiplication result in 4 parts, we need to perform a
4539 // shift right by the amount of the scale to get the result in that scale.
4540 //
4541 // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
4542 // 128 bits that are cut into 4 32-bit parts:
4543 //
4544 // HH HL LH LL
4545 // |---32---|---32---|---32---|---32---|
4546 // 128 96 64 32 0
4547 //
4548 // |------VTSize-----|
4549 //
4550 // |NVTSize-|
4551 //
4552 // The resulting Lo and Hi would normally be in LL and LH after the shift. But
4553 // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
4554 // amount and get Lo and Hi using two funnel shifts. Or for the special case
4555 // when Scale is a multiple of NVTSize we can just pick the result without
4556 // shifting.
4557 uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
4558 if (Scale % NVTSize) {
4559 SDValue ShiftAmount = DAG.getShiftAmountConstant(Val: Scale % NVTSize, VT: NVT, DL: dl);
4560 Lo = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 1], N2: Result[Part0],
4561 N3: ShiftAmount);
4562 Hi = DAG.getNode(Opcode: ISD::FSHR, DL: dl, VT: NVT, N1: Result[Part0 + 2], N2: Result[Part0 + 1],
4563 N3: ShiftAmount);
4564 } else {
4565 Lo = Result[Part0];
4566 Hi = Result[Part0 + 1];
4567 }
4568
4569 // Unless saturation is requested we are done. The result is in <Hi,Lo>.
4570 if (!Saturating)
4571 return;
4572
4573 // Can not overflow when there is no integer part.
4574 if (Scale == VTSize)
4575 return;
4576
4577 // To handle saturation we must check for overflow in the multiplication.
4578 //
4579 // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
4580 // aren't all zeroes.
4581 //
4582 // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
4583 // aren't all ones or all zeroes.
4584 //
4585 // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
4586 // highest bit of HH determines saturation direction in the event of signed
4587 // saturation.
4588
4589 SDValue ResultHL = Result[2];
4590 SDValue ResultHH = Result[3];
4591
4592 SDValue SatMax, SatMin;
4593 SDValue NVTZero = DAG.getConstant(Val: 0, DL: dl, VT: NVT);
4594 SDValue NVTNeg1 = DAG.getAllOnesConstant(DL: dl, VT: NVT);
4595 EVT BoolNVT = getSetCCResultType(VT: NVT);
4596
4597 if (!Signed) {
4598 if (Scale < NVTSize) {
4599 // Overflow happened if ((HH | (HL >> Scale)) != 0).
4600 SDValue HLAdjusted =
4601 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHL,
4602 N2: DAG.getShiftAmountConstant(Val: Scale, VT: NVT, DL: dl));
4603 SDValue Tmp = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: HLAdjusted, N2: ResultHH);
4604 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: Tmp, RHS: NVTZero, Cond: ISD::SETNE);
4605 } else if (Scale == NVTSize) {
4606 // Overflow happened if (HH != 0).
4607 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETNE);
4608 } else if (Scale < VTSize) {
4609 // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
4610 SDValue HLAdjusted =
4611 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: ResultHL,
4612 N2: DAG.getShiftAmountConstant(Val: Scale - NVTSize, VT: NVT, DL: dl));
4613 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: HLAdjusted, RHS: NVTZero, Cond: ISD::SETNE);
4614 } else
4615 llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"
4616 "(and saturation can't happen with Scale==VTSize).");
4617
4618 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Hi);
4619 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: NVTNeg1, RHS: Lo);
4620 return;
4621 }
4622
4623 if (Scale < NVTSize) {
4624 // The number of overflow bits we can check are VTSize - Scale + 1 (we
4625 // include the sign bit). If these top bits are > 0, then we overflowed past
4626 // the max value. If these top bits are < -1, then we overflowed past the
4627 // min value. Otherwise, we did not overflow.
4628 unsigned OverflowBits = VTSize - Scale + 1;
4629 assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&
4630 "Extent of overflow bits must start within HL");
4631 SDValue HLHiMask = DAG.getConstant(
4632 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits - NVTSize), DL: dl, VT: NVT);
4633 SDValue HLLoMask = DAG.getConstant(
4634 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: VTSize - OverflowBits), DL: dl, VT: NVT);
4635 // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
4636 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4637 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4638 SDValue HLUGT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLLoMask, Cond: ISD::SETUGT);
4639 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4640 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLUGT));
4641 // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
4642 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4643 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4644 SDValue HLULT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: HLHiMask, Cond: ISD::SETULT);
4645 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4646 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLULT));
4647 } else if (Scale == NVTSize) {
4648 // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
4649 SDValue HHGT0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETGT);
4650 SDValue HHEQ0 = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTZero, Cond: ISD::SETEQ);
4651 SDValue HLNeg = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETLT);
4652 SatMax = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHGT0,
4653 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ0, N2: HLNeg));
4654 // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
4655 SDValue HHLT = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETLT);
4656 SDValue HHEQ = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: NVTNeg1, Cond: ISD::SETEQ);
4657 SDValue HLPos = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHL, RHS: NVTZero, Cond: ISD::SETGE);
4658 SatMin = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BoolNVT, N1: HHLT,
4659 N2: DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BoolNVT, N1: HHEQ, N2: HLPos));
4660 } else if (Scale < VTSize) {
4661 // This is similar to the case when we saturate if Scale < NVTSize, but we
4662 // only need to check HH.
4663 unsigned OverflowBits = VTSize - Scale + 1;
4664 SDValue HHHiMask = DAG.getConstant(
4665 Val: APInt::getHighBitsSet(numBits: NVTSize, hiBitsSet: OverflowBits), DL: dl, VT: NVT);
4666 SDValue HHLoMask = DAG.getConstant(
4667 Val: APInt::getLowBitsSet(numBits: NVTSize, loBitsSet: NVTSize - OverflowBits), DL: dl, VT: NVT);
4668 SatMax = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHLoMask, Cond: ISD::SETGT);
4669 SatMin = DAG.getSetCC(DL: dl, VT: BoolNVT, LHS: ResultHH, RHS: HHHiMask, Cond: ISD::SETLT);
4670 } else
4671 llvm_unreachable("Illegal scale for signed fixed point mul.");
4672
4673 // Saturate to signed maximum.
4674 APInt MaxHi = APInt::getSignedMaxValue(numBits: NVTSize);
4675 APInt MaxLo = APInt::getAllOnes(numBits: NVTSize);
4676 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxHi, DL: dl, VT: NVT), RHS: Hi);
4677 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMax, LHS: DAG.getConstant(Val: MaxLo, DL: dl, VT: NVT), RHS: Lo);
4678 // Saturate to signed minimum.
4679 APInt MinHi = APInt::getSignedMinValue(numBits: NVTSize);
4680 Hi = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: DAG.getConstant(Val: MinHi, DL: dl, VT: NVT), RHS: Hi);
4681 Lo = DAG.getSelect(DL: dl, VT: NVT, Cond: SatMin, LHS: NVTZero, RHS: Lo);
4682}
4683
4684void DAGTypeLegalizer::ExpandIntRes_DIVFIX(SDNode *N, SDValue &Lo,
4685 SDValue &Hi) {
4686 SDLoc dl(N);
4687 // Try expanding in the existing type first.
4688 SDValue Res = TLI.expandFixedPointDiv(Opcode: N->getOpcode(), dl, LHS: N->getOperand(Num: 0),
4689 RHS: N->getOperand(Num: 1),
4690 Scale: N->getConstantOperandVal(Num: 2), DAG);
4691
4692 if (!Res)
4693 Res = earlyExpandDIVFIX(N, LHS: N->getOperand(Num: 0), RHS: N->getOperand(Num: 1),
4694 Scale: N->getConstantOperandVal(Num: 2), TLI, DAG);
4695 SplitInteger(Op: Res, Lo, Hi);
4696}
4697
4698void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
4699 SDValue &Lo, SDValue &Hi) {
4700 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) &&
4701 "Node has unexpected Opcode");
4702 SDValue LHS = Node->getOperand(Num: 0);
4703 SDValue RHS = Node->getOperand(Num: 1);
4704 SDLoc dl(Node);
4705
4706 SDValue Ovf;
4707
4708 bool IsAdd = Node->getOpcode() == ISD::SADDO;
4709 unsigned CarryOp = IsAdd ? ISD::SADDO_CARRY : ISD::SSUBO_CARRY;
4710
4711 bool HasCarryOp = TLI.isOperationLegalOrCustom(
4712 Op: CarryOp, VT: TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: LHS.getValueType()));
4713
4714 if (HasCarryOp) {
4715 // Expand the subcomponents.
4716 SDValue LHSL, LHSH, RHSL, RHSH;
4717 GetExpandedInteger(Op: LHS, Lo&: LHSL, Hi&: LHSH);
4718 GetExpandedInteger(Op: RHS, Lo&: RHSL, Hi&: RHSH);
4719 SDVTList VTList = DAG.getVTList(VT1: LHSL.getValueType(), VT2: Node->getValueType(ResNo: 1));
4720
4721 Lo = DAG.getNode(Opcode: IsAdd ? ISD::UADDO : ISD::USUBO, DL: dl, VTList, Ops: {LHSL, RHSL});
4722 Hi = DAG.getNode(Opcode: CarryOp, DL: dl, VTList, Ops: { LHSH, RHSH, Lo.getValue(R: 1) });
4723
4724 Ovf = Hi.getValue(R: 1);
4725 } else {
4726 // Expand the result by simply replacing it with the equivalent
4727 // non-overflow-checking operation.
4728 SDValue Sum = DAG.getNode(Opcode: Node->getOpcode() == ISD::SADDO ?
4729 ISD::ADD : ISD::SUB, DL: dl, VT: LHS.getValueType(),
4730 N1: LHS, N2: RHS);
4731 SplitInteger(Op: Sum, Lo, Hi);
4732
4733 // Compute the overflow.
4734 //
4735 // LHSSign -> LHS < 0
4736 // RHSSign -> RHS < 0
4737 // SumSign -> Sum < 0
4738 //
4739 // Add:
4740 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4741 // Sub:
4742 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4743 //
4744 // To get better codegen we can rewrite this by doing bitwise math on
4745 // the integers and extract the final sign bit at the end. So the
4746 // above becomes:
4747 //
4748 // Add:
4749 // Overflow -> (~(LHS ^ RHS) & (LHS ^ Sum)) < 0
4750 // Sub:
4751 // Overflow -> ((LHS ^ RHS) & (LHS ^ Sum)) < 0
4752 //
4753 // NOTE: This is different than the expansion we do in expandSADDSUBO
4754 // because it is more costly to determine the RHS is > 0 for SSUBO with the
4755 // integers split.
4756 EVT VT = LHS.getValueType();
4757 SDValue SignsMatch = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: RHS);
4758 if (IsAdd)
4759 SignsMatch = DAG.getNOT(DL: dl, Val: SignsMatch, VT);
4760
4761 SDValue SumSignNE = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: LHS, N2: Sum);
4762 Ovf = DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: SignsMatch, N2: SumSignNE);
4763 EVT OType = Node->getValueType(ResNo: 1);
4764 Ovf = DAG.getSetCC(DL: dl, VT: OType, LHS: Ovf, RHS: DAG.getConstant(Val: 0, DL: dl, VT), Cond: ISD::SETLT);
4765 }
4766
4767 // Use the calculated overflow everywhere.
4768 ReplaceValueWith(From: SDValue(Node, 1), To: Ovf);
4769}
4770
4771void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
4772 SDValue &Lo, SDValue &Hi) {
4773 EVT VT = N->getValueType(ResNo: 0);
4774 SDLoc dl(N);
4775 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
4776
4777 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
4778 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
4779 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
4780 return;
4781 }
4782
4783 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4784 if (VT == MVT::i16)
4785 LC = RTLIB::SDIV_I16;
4786 else if (VT == MVT::i32)
4787 LC = RTLIB::SDIV_I32;
4788 else if (VT == MVT::i64)
4789 LC = RTLIB::SDIV_I64;
4790 else if (VT == MVT::i128)
4791 LC = RTLIB::SDIV_I128;
4792 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
4793
4794 TargetLowering::MakeLibCallOptions CallOptions;
4795 CallOptions.setIsSigned(true);
4796 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
4797}
4798
4799void DAGTypeLegalizer::ExpandIntRes_ShiftThroughStack(SDNode *N, SDValue &Lo,
4800 SDValue &Hi) {
4801 SDLoc dl(N);
4802 SDValue Shiftee = N->getOperand(Num: 0);
4803 EVT VT = Shiftee.getValueType();
4804 SDValue ShAmt = N->getOperand(Num: 1);
4805 EVT ShAmtVT = ShAmt.getValueType();
4806
4807 EVT LoadVT = VT;
4808 do {
4809 LoadVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: LoadVT);
4810 } while (!TLI.isTypeLegal(VT: LoadVT));
4811
4812 const unsigned ShiftUnitInBits = LoadVT.getStoreSizeInBits();
4813 assert(ShiftUnitInBits <= VT.getScalarSizeInBits());
4814 assert(isPowerOf2_32(ShiftUnitInBits) &&
4815 "Shifting unit is not a a power of two!");
4816
4817 const bool IsOneStepShift =
4818 DAG.computeKnownBits(Op: ShAmt).countMinTrailingZeros() >=
4819 Log2_32(Value: ShiftUnitInBits);
4820
4821 // If we can't do it as one step, we'll have two uses of shift amount,
4822 // and thus must freeze it.
4823 if (!IsOneStepShift)
4824 ShAmt = DAG.getFreeze(V: ShAmt);
4825
4826 unsigned VTBitWidth = VT.getScalarSizeInBits();
4827 assert(VTBitWidth % 8 == 0 && "Shifting a not byte multiple value?");
4828 unsigned VTByteWidth = VTBitWidth / 8;
4829 assert(isPowerOf2_32(VTByteWidth) &&
4830 "Shiftee type size is not a power of two!");
4831 unsigned StackSlotByteWidth = 2 * VTByteWidth;
4832 unsigned StackSlotBitWidth = 8 * StackSlotByteWidth;
4833 EVT StackSlotVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: StackSlotBitWidth);
4834
4835 // Get a temporary stack slot 2x the width of our VT.
4836 // FIXME: reuse stack slots?
4837 Align StackAlign = DAG.getReducedAlign(VT: StackSlotVT, /*UseABI=*/false);
4838 SDValue StackPtr =
4839 DAG.CreateStackTemporary(Bytes: StackSlotVT.getStoreSize(), Alignment: StackAlign);
4840 EVT PtrTy = StackPtr.getValueType();
4841 SDValue Ch = DAG.getEntryNode();
4842
4843 MachinePointerInfo StackPtrInfo = MachinePointerInfo::getFixedStack(
4844 MF&: DAG.getMachineFunction(),
4845 FI: cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex());
4846
4847 // Extend the value, that is being shifted, to the entire stack slot's width.
4848 SDValue Init;
4849 if (N->getOpcode() != ISD::SHL) {
4850 unsigned WideningOpc =
4851 N->getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4852 Init = DAG.getNode(Opcode: WideningOpc, DL: dl, VT: StackSlotVT, Operand: Shiftee);
4853 } else {
4854 // For left-shifts, pad the Shiftee's LSB with zeros to twice it's width.
4855 SDValue AllZeros = DAG.getConstant(Val: 0, DL: dl, VT);
4856 Init = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: StackSlotVT, N1: AllZeros, N2: Shiftee);
4857 }
4858 // And spill it into the stack slot.
4859 Ch = DAG.getStore(Chain: Ch, dl, Val: Init, Ptr: StackPtr, PtrInfo: StackPtrInfo, Alignment: StackAlign);
4860
4861 // Now, compute the full-byte offset into stack slot from where we can load.
4862 // We have shift amount, which is in bits. Offset should point to an aligned
4863 // address.
4864 SDNodeFlags Flags;
4865 Flags.setExact(IsOneStepShift);
4866 SDValue SrlTmp = DAG.getNode(
4867 Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: ShAmt,
4868 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT), Flags);
4869 SDValue BitOffset =
4870 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: ShAmtVT, N1: SrlTmp,
4871 N2: DAG.getConstant(Val: Log2_32(Value: ShiftUnitInBits), DL: dl, VT: ShAmtVT));
4872
4873 SDValue ByteOffset =
4874 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: ShAmtVT, N1: BitOffset,
4875 N2: DAG.getConstant(Val: 3, DL: dl, VT: ShAmtVT), Flags: SDNodeFlags::Exact);
4876 // And clamp it, because OOB load is an immediate UB,
4877 // while shift overflow would have *just* been poison.
4878 ByteOffset = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ByteOffset,
4879 N2: DAG.getConstant(Val: VTByteWidth - 1, DL: dl, VT: ShAmtVT));
4880 // We have exactly two strategies on indexing into stack slot here:
4881 // 1. upwards starting from the beginning of the slot
4882 // 2. downwards starting from the middle of the slot
4883 // On little-endian machine, we pick 1. for right shifts and 2. for left-shift
4884 // and vice versa on big-endian machine.
4885 bool WillIndexUpwards = N->getOpcode() != ISD::SHL;
4886 if (DAG.getDataLayout().isBigEndian())
4887 WillIndexUpwards = !WillIndexUpwards;
4888
4889 SDValue AdjStackPtr;
4890 if (WillIndexUpwards) {
4891 AdjStackPtr = StackPtr;
4892 } else {
4893 AdjStackPtr = DAG.getMemBasePlusOffset(
4894 Base: StackPtr, Offset: DAG.getConstant(Val: VTByteWidth, DL: dl, VT: PtrTy), DL: dl);
4895 ByteOffset = DAG.getNegative(Val: ByteOffset, DL: dl, VT: ShAmtVT);
4896 }
4897
4898 // Get the pointer somewhere into the stack slot from which we need to load.
4899 ByteOffset = DAG.getSExtOrTrunc(Op: ByteOffset, DL: dl, VT: PtrTy);
4900 AdjStackPtr = DAG.getMemBasePlusOffset(Base: AdjStackPtr, Offset: ByteOffset, DL: dl);
4901
4902 // And load it! While the load is not legal, legalizing it is obvious.
4903 SDValue Res =
4904 DAG.getLoad(VT, dl, Chain: Ch, Ptr: AdjStackPtr,
4905 PtrInfo: MachinePointerInfo::getUnknownStack(MF&: DAG.getMachineFunction()),
4906 Alignment: commonAlignment(A: StackAlign, Offset: LoadVT.getStoreSize()));
4907
4908 // If we may still have a remaining bits to shift by, do so now.
4909 if (!IsOneStepShift) {
4910 SDValue ShAmtRem =
4911 DAG.getNode(Opcode: ISD::AND, DL: dl, VT: ShAmtVT, N1: ShAmt,
4912 N2: DAG.getConstant(Val: ShiftUnitInBits - 1, DL: dl, VT: ShAmtVT));
4913 Res = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT, N1: Res, N2: ShAmtRem);
4914 }
4915
4916 // Finally, split the computed value.
4917 SplitInteger(Op: Res, Lo, Hi);
4918}
4919
4920void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
4921 SDValue &Lo, SDValue &Hi) {
4922 EVT VT = N->getValueType(ResNo: 0);
4923 unsigned Opc = N->getOpcode();
4924 SDLoc dl(N);
4925
4926 // If we can emit an efficient shift operation, do so now. Check to see if
4927 // the RHS is a constant.
4928 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1)))
4929 return ExpandShiftByConstant(N, Amt: CN->getAPIntValue(), Lo, Hi);
4930
4931 // If we can determine that the high bit of the shift is zero or one, even if
4932 // the low bits are variable, emit this shift in an optimized form.
4933 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
4934 return;
4935
4936 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
4937 unsigned PartsOpc;
4938 if (Opc == ISD::SHL) {
4939 PartsOpc = ISD::SHL_PARTS;
4940 } else if (Opc == ISD::SRL) {
4941 PartsOpc = ISD::SRL_PARTS;
4942 } else {
4943 assert(Opc == ISD::SRA && "Unknown shift!");
4944 PartsOpc = ISD::SRA_PARTS;
4945 }
4946
4947 // Next check to see if the target supports this SHL_PARTS operation or if it
4948 // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
4949 // size, but create a libcall instead.
4950 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
4951 TargetLowering::LegalizeAction Action = TLI.getOperationAction(Op: PartsOpc, VT: NVT);
4952 const bool LegalOrCustom =
4953 (Action == TargetLowering::Legal && TLI.isTypeLegal(VT: NVT)) ||
4954 Action == TargetLowering::Custom;
4955
4956 unsigned ExpansionFactor = 1;
4957 // That VT->NVT expansion is one step. But will we re-expand NVT?
4958 for (EVT TmpVT = NVT;;) {
4959 EVT NewTMPVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: TmpVT);
4960 if (NewTMPVT == TmpVT)
4961 break;
4962 TmpVT = NewTMPVT;
4963 ++ExpansionFactor;
4964 }
4965
4966 TargetLowering::ShiftLegalizationStrategy S =
4967 TLI.preferredShiftLegalizationStrategy(DAG, N, ExpansionFactor);
4968
4969 if (S == TargetLowering::ShiftLegalizationStrategy::ExpandThroughStack)
4970 return ExpandIntRes_ShiftThroughStack(N, Lo, Hi);
4971
4972 if (LegalOrCustom &&
4973 S != TargetLowering::ShiftLegalizationStrategy::LowerToLibcall) {
4974 // Expand the subcomponents.
4975 SDValue LHSL, LHSH;
4976 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: LHSL, Hi&: LHSH);
4977 EVT VT = LHSL.getValueType();
4978
4979 // If the shift amount operand is coming from a vector legalization it may
4980 // have an illegal type. Fix that first by casting the operand, otherwise
4981 // the new SHL_PARTS operation would need further legalization.
4982 SDValue ShiftOp = N->getOperand(Num: 1);
4983 EVT ShiftTy = TLI.getShiftAmountTy(LHSTy: VT, DL: DAG.getDataLayout());
4984 if (ShiftOp.getValueType() != ShiftTy)
4985 ShiftOp = DAG.getZExtOrTrunc(Op: ShiftOp, DL: dl, VT: ShiftTy);
4986
4987 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
4988 Lo = DAG.getNode(Opcode: PartsOpc, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
4989 Hi = Lo.getValue(R: 1);
4990 return;
4991 }
4992
4993 // Otherwise, emit a libcall.
4994 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4995 bool isSigned;
4996 if (Opc == ISD::SHL) {
4997 isSigned = false; /*sign irrelevant*/
4998 if (VT == MVT::i16)
4999 LC = RTLIB::SHL_I16;
5000 else if (VT == MVT::i32)
5001 LC = RTLIB::SHL_I32;
5002 else if (VT == MVT::i64)
5003 LC = RTLIB::SHL_I64;
5004 else if (VT == MVT::i128)
5005 LC = RTLIB::SHL_I128;
5006 } else if (Opc == ISD::SRL) {
5007 isSigned = false;
5008 if (VT == MVT::i16)
5009 LC = RTLIB::SRL_I16;
5010 else if (VT == MVT::i32)
5011 LC = RTLIB::SRL_I32;
5012 else if (VT == MVT::i64)
5013 LC = RTLIB::SRL_I64;
5014 else if (VT == MVT::i128)
5015 LC = RTLIB::SRL_I128;
5016 } else {
5017 assert(Opc == ISD::SRA && "Unknown shift!");
5018 isSigned = true;
5019 if (VT == MVT::i16)
5020 LC = RTLIB::SRA_I16;
5021 else if (VT == MVT::i32)
5022 LC = RTLIB::SRA_I32;
5023 else if (VT == MVT::i64)
5024 LC = RTLIB::SRA_I64;
5025 else if (VT == MVT::i128)
5026 LC = RTLIB::SRA_I128;
5027 }
5028
5029 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(Call: LC)) {
5030 EVT ShAmtTy =
5031 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: DAG.getLibInfo().getIntSize());
5032 SDValue ShAmt = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl, VT: ShAmtTy);
5033 SDValue Ops[2] = {N->getOperand(Num: 0), ShAmt};
5034 TargetLowering::MakeLibCallOptions CallOptions;
5035 CallOptions.setIsSigned(isSigned);
5036 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5037 return;
5038 }
5039
5040 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
5041 llvm_unreachable("Unsupported shift!");
5042}
5043
5044void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
5045 SDValue &Lo, SDValue &Hi) {
5046 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5047 SDLoc dl(N);
5048 SDValue Op = N->getOperand(Num: 0);
5049 if (Op.getValueType().bitsLE(VT: NVT)) {
5050 // The low part is sign extension of the input (degenerates to a copy).
5051 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5052 // The high part is obtained by SRA'ing all but one of the bits of low part.
5053 unsigned LoSize = NVT.getSizeInBits();
5054 Hi = DAG.getNode(
5055 Opcode: ISD::SRA, DL: dl, VT: NVT, N1: Lo,
5056 N2: DAG.getConstant(Val: LoSize - 1, DL: dl, VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
5057 } else {
5058 // For example, extension of an i48 to an i64. The operand type necessarily
5059 // promotes to the result type, so will end up being expanded too.
5060 assert(getTypeAction(Op.getValueType()) ==
5061 TargetLowering::TypePromoteInteger &&
5062 "Only know how to promote this result!");
5063 SDValue Res = GetPromotedInteger(Op);
5064 assert(Res.getValueType() == N->getValueType(0) &&
5065 "Operand over promoted?");
5066 // Split the promoted operand. This will simplify when it is expanded.
5067 SplitInteger(Op: Res, Lo, Hi);
5068 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5069 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5070 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5071 BitWidth: ExcessBits)));
5072 }
5073}
5074
5075void DAGTypeLegalizer::
5076ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
5077 SDLoc dl(N);
5078 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5079 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
5080
5081 if (EVT.bitsLE(VT: Lo.getValueType())) {
5082 // sext_inreg the low part if needed.
5083 Lo = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Lo.getValueType(), N1: Lo,
5084 N2: N->getOperand(Num: 1));
5085
5086 // The high part gets the sign extension from the lo-part. This handles
5087 // things like sextinreg V:i64 from i8.
5088 Hi = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: Hi.getValueType(), N1: Lo,
5089 N2: DAG.getConstant(Val: Hi.getValueSizeInBits() - 1, DL: dl,
5090 VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
5091 } else {
5092 // For example, extension of an i48 to an i64. Leave the low part alone,
5093 // sext_inreg the high part.
5094 unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
5095 Hi = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: Hi.getValueType(), N1: Hi,
5096 N2: DAG.getValueType(EVT::getIntegerVT(Context&: *DAG.getContext(),
5097 BitWidth: ExcessBits)));
5098 }
5099}
5100
5101void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
5102 SDValue &Lo, SDValue &Hi) {
5103 EVT VT = N->getValueType(ResNo: 0);
5104 SDLoc dl(N);
5105 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5106
5107 if (TLI.getOperationAction(Op: ISD::SDIVREM, VT) == TargetLowering::Custom) {
5108 SDValue Res = DAG.getNode(Opcode: ISD::SDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5109 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5110 return;
5111 }
5112
5113 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5114 if (VT == MVT::i16)
5115 LC = RTLIB::SREM_I16;
5116 else if (VT == MVT::i32)
5117 LC = RTLIB::SREM_I32;
5118 else if (VT == MVT::i64)
5119 LC = RTLIB::SREM_I64;
5120 else if (VT == MVT::i128)
5121 LC = RTLIB::SREM_I128;
5122 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
5123
5124 TargetLowering::MakeLibCallOptions CallOptions;
5125 CallOptions.setIsSigned(true);
5126 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5127}
5128
5129void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
5130 SDValue &Lo, SDValue &Hi) {
5131 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5132 SDLoc dl(N);
5133 Lo = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5134 Hi = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: N->getOperand(Num: 0).getValueType(),
5135 N1: N->getOperand(Num: 0),
5136 N2: DAG.getConstant(Val: NVT.getSizeInBits(), DL: dl,
5137 VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
5138 Hi = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: NVT, Operand: Hi);
5139}
5140
5141void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
5142 SDValue &Lo, SDValue &Hi) {
5143 EVT VT = N->getValueType(ResNo: 0);
5144 SDLoc dl(N);
5145
5146 if (N->getOpcode() == ISD::UMULO) {
5147 // This section expands the operation into the following sequence of
5148 // instructions. `iNh` here refers to a type which has half the bit width of
5149 // the type the original operation operated on.
5150 //
5151 // %0 = %LHS.HI != 0 && %RHS.HI != 0
5152 // %1 = { iNh, i1 } @umul.with.overflow.iNh(iNh %LHS.HI, iNh %RHS.LO)
5153 // %2 = { iNh, i1 } @umul.with.overflow.iNh(iNh %RHS.HI, iNh %LHS.LO)
5154 // %3 = mul nuw iN (%LHS.LOW as iN), (%RHS.LOW as iN)
5155 // %4 = add iNh %1.0, %2.0 as iN
5156 // %5 = { iNh, i1 } @uadd.with.overflow.iNh(iNh %4, iNh %3.HIGH)
5157 //
5158 // %lo = %3.LO
5159 // %hi = %5.0
5160 // %ovf = %0 || %1.1 || %2.1 || %5.1
5161 SDValue LHS = N->getOperand(Num: 0), RHS = N->getOperand(Num: 1);
5162 SDValue LHSHigh, LHSLow, RHSHigh, RHSLow;
5163 GetExpandedInteger(Op: LHS, Lo&: LHSLow, Hi&: LHSHigh);
5164 GetExpandedInteger(Op: RHS, Lo&: RHSLow, Hi&: RHSHigh);
5165 EVT HalfVT = LHSLow.getValueType();
5166 EVT BitVT = N->getValueType(ResNo: 1);
5167 SDVTList VTHalfWithO = DAG.getVTList(VT1: HalfVT, VT2: BitVT);
5168
5169 SDValue HalfZero = DAG.getConstant(Val: 0, DL: dl, VT: HalfVT);
5170 SDValue Overflow = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: BitVT,
5171 N1: DAG.getSetCC(DL: dl, VT: BitVT, LHS: LHSHigh, RHS: HalfZero, Cond: ISD::SETNE),
5172 N2: DAG.getSetCC(DL: dl, VT: BitVT, LHS: RHSHigh, RHS: HalfZero, Cond: ISD::SETNE));
5173
5174 SDValue One = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: LHSHigh, N2: RHSLow);
5175 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: One.getValue(R: 1));
5176
5177 SDValue Two = DAG.getNode(Opcode: ISD::UMULO, DL: dl, VTList: VTHalfWithO, N1: RHSHigh, N2: LHSLow);
5178 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Two.getValue(R: 1));
5179
5180 SDValue HighSum = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: HalfVT, N1: One, N2: Two);
5181
5182 // Cannot use `UMUL_LOHI` directly, because some 32-bit targets (ARM) do not
5183 // know how to expand `i64,i64 = umul_lohi a, b` and abort (why isn’t this
5184 // operation recursively legalized?).
5185 //
5186 // Many backends understand this pattern and will convert into LOHI
5187 // themselves, if applicable.
5188 SDValue Three = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT,
5189 N1: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: LHSLow),
5190 N2: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: RHSLow));
5191 SplitInteger(Op: Three, Lo, Hi);
5192
5193 Hi = DAG.getNode(Opcode: ISD::UADDO, DL: dl, VTList: VTHalfWithO, N1: Hi, N2: HighSum);
5194 Overflow = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: BitVT, N1: Overflow, N2: Hi.getValue(R: 1));
5195 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5196 return;
5197 }
5198
5199 Type *RetTy = VT.getTypeForEVT(Context&: *DAG.getContext());
5200 EVT PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
5201 Type *PtrTy = PtrVT.getTypeForEVT(Context&: *DAG.getContext());
5202
5203 // Replace this with a libcall that will check overflow.
5204 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5205 if (VT == MVT::i32)
5206 LC = RTLIB::MULO_I32;
5207 else if (VT == MVT::i64)
5208 LC = RTLIB::MULO_I64;
5209 else if (VT == MVT::i128)
5210 LC = RTLIB::MULO_I128;
5211
5212 // If we don't have the libcall or if the function we are compiling is the
5213 // implementation of the expected libcall (avoid inf-loop), expand inline.
5214 if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(Call: LC) ||
5215 TLI.getLibcallName(Call: LC) == DAG.getMachineFunction().getName()) {
5216 // FIXME: This is not an optimal expansion, but better than crashing.
5217 SDValue MulLo, MulHi;
5218 TLI.forceExpandWideMUL(DAG, dl, /*Signed=*/true, LHS: N->getOperand(Num: 0),
5219 RHS: N->getOperand(Num: 1), Lo&: MulLo, Hi&: MulHi);
5220 SDValue SRA =
5221 DAG.getNode(Opcode: ISD::SRA, DL: dl, VT, N1: MulLo,
5222 N2: DAG.getConstant(Val: VT.getScalarSizeInBits() - 1, DL: dl, VT));
5223 SDValue Overflow =
5224 DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: MulHi, RHS: SRA, Cond: ISD::SETNE);
5225 SplitInteger(Op: MulLo, Lo, Hi);
5226 ReplaceValueWith(From: SDValue(N, 1), To: Overflow);
5227 return;
5228 }
5229
5230 SDValue Temp = DAG.CreateStackTemporary(VT: PtrVT);
5231 // Temporary for the overflow value, default it to zero.
5232 SDValue Chain =
5233 DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT), Ptr: Temp,
5234 PtrInfo: MachinePointerInfo());
5235
5236 TargetLowering::ArgListTy Args;
5237 TargetLowering::ArgListEntry Entry;
5238 for (const SDValue &Op : N->op_values()) {
5239 EVT ArgVT = Op.getValueType();
5240 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
5241 Entry.Node = Op;
5242 Entry.Ty = ArgTy;
5243 Entry.IsSExt = true;
5244 Entry.IsZExt = false;
5245 Args.push_back(x: Entry);
5246 }
5247
5248 // Also pass the address of the overflow check.
5249 Entry.Node = Temp;
5250 Entry.Ty = PointerType::getUnqual(C&: PtrTy->getContext());
5251 Entry.IsSExt = true;
5252 Entry.IsZExt = false;
5253 Args.push_back(x: Entry);
5254
5255 SDValue Func = DAG.getExternalSymbol(Sym: TLI.getLibcallName(Call: LC), VT: PtrVT);
5256
5257 TargetLowering::CallLoweringInfo CLI(DAG);
5258 CLI.setDebugLoc(dl)
5259 .setChain(Chain)
5260 .setLibCallee(CC: TLI.getLibcallCallingConv(Call: LC), ResultType: RetTy, Target: Func, ArgsList: std::move(Args))
5261 .setSExtResult();
5262
5263 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
5264
5265 SplitInteger(Op: CallInfo.first, Lo, Hi);
5266 SDValue Temp2 =
5267 DAG.getLoad(VT: PtrVT, dl, Chain: CallInfo.second, Ptr: Temp, PtrInfo: MachinePointerInfo());
5268 SDValue Ofl = DAG.getSetCC(DL: dl, VT: N->getValueType(ResNo: 1), LHS: Temp2,
5269 RHS: DAG.getConstant(Val: 0, DL: dl, VT: PtrVT),
5270 Cond: ISD::SETNE);
5271 // Use the overflow from the libcall everywhere.
5272 ReplaceValueWith(From: SDValue(N, 1), To: Ofl);
5273}
5274
5275void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
5276 SDValue &Lo, SDValue &Hi) {
5277 EVT VT = N->getValueType(ResNo: 0);
5278 SDLoc dl(N);
5279 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5280
5281 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5282 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5283 SplitInteger(Op: Res.getValue(R: 0), Lo, Hi);
5284 return;
5285 }
5286
5287 // Try to expand UDIV by constant.
5288 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5289 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5290 // Only if the new type is legal.
5291 if (isTypeLegal(VT: NVT)) {
5292 SDValue InL, InH;
5293 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5294 SmallVector<SDValue> Result;
5295 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5296 Lo = Result[0];
5297 Hi = Result[1];
5298 return;
5299 }
5300 }
5301 }
5302
5303 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5304 if (VT == MVT::i16)
5305 LC = RTLIB::UDIV_I16;
5306 else if (VT == MVT::i32)
5307 LC = RTLIB::UDIV_I32;
5308 else if (VT == MVT::i64)
5309 LC = RTLIB::UDIV_I64;
5310 else if (VT == MVT::i128)
5311 LC = RTLIB::UDIV_I128;
5312 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
5313
5314 TargetLowering::MakeLibCallOptions CallOptions;
5315 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5316}
5317
5318void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
5319 SDValue &Lo, SDValue &Hi) {
5320 EVT VT = N->getValueType(ResNo: 0);
5321 SDLoc dl(N);
5322 SDValue Ops[2] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
5323
5324 if (TLI.getOperationAction(Op: ISD::UDIVREM, VT) == TargetLowering::Custom) {
5325 SDValue Res = DAG.getNode(Opcode: ISD::UDIVREM, DL: dl, VTList: DAG.getVTList(VT1: VT, VT2: VT), Ops);
5326 SplitInteger(Op: Res.getValue(R: 1), Lo, Hi);
5327 return;
5328 }
5329
5330 // Try to expand UREM by constant.
5331 if (isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
5332 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5333 // Only if the new type is legal.
5334 if (isTypeLegal(VT: NVT)) {
5335 SDValue InL, InH;
5336 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5337 SmallVector<SDValue> Result;
5338 if (TLI.expandDIVREMByConstant(N, Result, HiLoVT: NVT, DAG, LL: InL, LH: InH)) {
5339 Lo = Result[0];
5340 Hi = Result[1];
5341 return;
5342 }
5343 }
5344 }
5345
5346 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5347 if (VT == MVT::i16)
5348 LC = RTLIB::UREM_I16;
5349 else if (VT == MVT::i32)
5350 LC = RTLIB::UREM_I32;
5351 else if (VT == MVT::i64)
5352 LC = RTLIB::UREM_I64;
5353 else if (VT == MVT::i128)
5354 LC = RTLIB::UREM_I128;
5355 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
5356
5357 TargetLowering::MakeLibCallOptions CallOptions;
5358 SplitInteger(Op: TLI.makeLibCall(DAG, LC, RetVT: VT, Ops, CallOptions, dl).first, Lo, Hi);
5359}
5360
5361void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
5362 SDValue &Lo, SDValue &Hi) {
5363 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
5364 SDLoc dl(N);
5365 SDValue Op = N->getOperand(Num: 0);
5366 if (Op.getValueType().bitsLE(VT: NVT)) {
5367 // The low part is zero extension of the input (degenerates to a copy).
5368 Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
5369 Hi = DAG.getConstant(Val: 0, DL: dl, VT: NVT); // The high part is just a zero.
5370 } else {
5371 // For example, extension of an i48 to an i64. The operand type necessarily
5372 // promotes to the result type, so will end up being expanded too.
5373 assert(getTypeAction(Op.getValueType()) ==
5374 TargetLowering::TypePromoteInteger &&
5375 "Only know how to promote this result!");
5376 SDValue Res = GetPromotedInteger(Op);
5377 assert(Res.getValueType() == N->getValueType(0) &&
5378 "Operand over promoted?");
5379 // Split the promoted operand. This will simplify when it is expanded.
5380 SplitInteger(Op: Res, Lo, Hi);
5381 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
5382 Hi = DAG.getZeroExtendInReg(Op: Hi, DL: dl,
5383 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
5384 BitWidth: ExcessBits));
5385 }
5386}
5387
5388void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
5389 SDValue &Lo, SDValue &Hi) {
5390 SDLoc dl(N);
5391 EVT VT = cast<AtomicSDNode>(Val: N)->getMemoryVT();
5392 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::i1, VT3: MVT::Other);
5393 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
5394 SDValue Swap = DAG.getAtomicCmpSwap(
5395 Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
5396 MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(), VTs, Chain: N->getOperand(Num: 0),
5397 Ptr: N->getOperand(Num: 1), Cmp: Zero, Swp: Zero, MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
5398
5399 ReplaceValueWith(From: SDValue(N, 0), To: Swap.getValue(R: 0));
5400 ReplaceValueWith(From: SDValue(N, 1), To: Swap.getValue(R: 2));
5401}
5402
5403void DAGTypeLegalizer::ExpandIntRes_VECREDUCE(SDNode *N,
5404 SDValue &Lo, SDValue &Hi) {
5405 // TODO For VECREDUCE_(AND|OR|XOR) we could split the vector and calculate
5406 // both halves independently.
5407 SDValue Res = TLI.expandVecReduce(Node: N, DAG);
5408 SplitInteger(Op: Res, Lo, Hi);
5409}
5410
5411void DAGTypeLegalizer::ExpandIntRes_Rotate(SDNode *N,
5412 SDValue &Lo, SDValue &Hi) {
5413 // Delegate to funnel-shift expansion.
5414 SDLoc DL(N);
5415 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR;
5416 SDValue Res = DAG.getNode(Opcode, DL, VT: N->getValueType(ResNo: 0), N1: N->getOperand(Num: 0),
5417 N2: N->getOperand(Num: 0), N3: N->getOperand(Num: 1));
5418 SplitInteger(Op: Res, Lo, Hi);
5419}
5420
5421void DAGTypeLegalizer::ExpandIntRes_FunnelShift(SDNode *N, SDValue &Lo,
5422 SDValue &Hi) {
5423 // Values numbered from least significant to most significant.
5424 SDValue In1, In2, In3, In4;
5425 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: In3, Hi&: In4);
5426 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo&: In1, Hi&: In2);
5427 EVT HalfVT = In1.getValueType();
5428
5429 SDLoc DL(N);
5430 unsigned Opc = N->getOpcode();
5431 SDValue ShAmt = N->getOperand(Num: 2);
5432 EVT ShAmtVT = ShAmt.getValueType();
5433 EVT ShAmtCCVT = getSetCCResultType(VT: ShAmtVT);
5434
5435 // If the shift amount is at least half the bitwidth, swap the inputs.
5436 unsigned HalfVTBits = HalfVT.getScalarSizeInBits();
5437 SDValue AndNode = DAG.getNode(Opcode: ISD::AND, DL, VT: ShAmtVT, N1: ShAmt,
5438 N2: DAG.getConstant(Val: HalfVTBits, DL, VT: ShAmtVT));
5439 SDValue Cond =
5440 DAG.getSetCC(DL, VT: ShAmtCCVT, LHS: AndNode, RHS: DAG.getConstant(Val: 0, DL, VT: ShAmtVT),
5441 Cond: Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ);
5442
5443 // Expand to a pair of funnel shifts.
5444 EVT NewShAmtVT = TLI.getShiftAmountTy(LHSTy: HalfVT, DL: DAG.getDataLayout());
5445 SDValue NewShAmt = DAG.getAnyExtOrTrunc(Op: ShAmt, DL, VT: NewShAmtVT);
5446
5447 SDValue Select1 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In1, N3: In2);
5448 SDValue Select2 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In2, N3: In3);
5449 SDValue Select3 = DAG.getNode(Opcode: ISD::SELECT, DL, VT: HalfVT, N1: Cond, N2: In3, N3: In4);
5450 Lo = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select2, N2: Select1, N3: NewShAmt);
5451 Hi = DAG.getNode(Opcode: Opc, DL, VT: HalfVT, N1: Select3, N2: Select2, N3: NewShAmt);
5452}
5453
5454void DAGTypeLegalizer::ExpandIntRes_VSCALE(SDNode *N, SDValue &Lo,
5455 SDValue &Hi) {
5456 EVT VT = N->getValueType(ResNo: 0);
5457 EVT HalfVT =
5458 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: N->getValueSizeInBits(ResNo: 0) / 2);
5459 SDLoc dl(N);
5460
5461 // We assume VSCALE(1) fits into a legal integer.
5462 APInt One(HalfVT.getSizeInBits(), 1);
5463 SDValue VScaleBase = DAG.getVScale(DL: dl, VT: HalfVT, MulImm: One);
5464 VScaleBase = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: VScaleBase);
5465 SDValue Res = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: VScaleBase, N2: N->getOperand(Num: 0));
5466 SplitInteger(Op: Res, Lo, Hi);
5467}
5468
5469//===----------------------------------------------------------------------===//
5470// Integer Operand Expansion
5471//===----------------------------------------------------------------------===//
5472
5473/// ExpandIntegerOperand - This method is called when the specified operand of
5474/// the specified node is found to need expansion. At this point, all of the
5475/// result types of the node are known to be legal, but other operands of the
5476/// node may need promotion or expansion as well as the specified one.
5477bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
5478 LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG));
5479 SDValue Res = SDValue();
5480
5481 if (CustomLowerNode(N, VT: N->getOperand(Num: OpNo).getValueType(), LegalizeResult: false))
5482 return false;
5483
5484 switch (N->getOpcode()) {
5485 default:
5486 #ifndef NDEBUG
5487 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
5488 N->dump(&DAG); dbgs() << "\n";
5489 #endif
5490 report_fatal_error(reason: "Do not know how to expand this operator's operand!");
5491
5492 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
5493 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
5494 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
5495 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
5496 case ISD::FAKE_USE:
5497 Res = ExpandOp_FAKE_USE(N);
5498 break;
5499 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
5500 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
5501 case ISD::EXPERIMENTAL_VP_SPLAT:
5502 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break;
5503 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
5504 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
5505 case ISD::SETCCCARRY: Res = ExpandIntOp_SETCCCARRY(N); break;
5506 case ISD::STRICT_SINT_TO_FP:
5507 case ISD::SINT_TO_FP:
5508 case ISD::STRICT_UINT_TO_FP:
5509 case ISD::UINT_TO_FP: Res = ExpandIntOp_XINT_TO_FP(N); break;
5510 case ISD::STORE: Res = ExpandIntOp_STORE(N: cast<StoreSDNode>(Val: N), OpNo); break;
5511 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
5512
5513 case ISD::SHL:
5514 case ISD::SRA:
5515 case ISD::SRL:
5516 case ISD::ROTL:
5517 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
5518 case ISD::RETURNADDR:
5519 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
5520
5521 case ISD::SCMP:
5522 case ISD::UCMP: Res = ExpandIntOp_CMP(N); break;
5523
5524 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
5525 case ISD::STACKMAP:
5526 Res = ExpandIntOp_STACKMAP(N, OpNo);
5527 break;
5528 case ISD::PATCHPOINT:
5529 Res = ExpandIntOp_PATCHPOINT(N, OpNo);
5530 break;
5531 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
5532 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
5533 Res = ExpandIntOp_VP_STRIDED(N, OpNo);
5534 break;
5535 }
5536
5537 // If the result is null, the sub-method took care of registering results etc.
5538 if (!Res.getNode()) return false;
5539
5540 // If the result is N, the sub-method updated N in place. Tell the legalizer
5541 // core about this.
5542 if (Res.getNode() == N)
5543 return true;
5544
5545 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
5546 "Invalid operand expansion");
5547
5548 ReplaceValueWith(From: SDValue(N, 0), To: Res);
5549 return false;
5550}
5551
5552/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
5553/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
5554void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
5555 SDValue &NewRHS,
5556 ISD::CondCode &CCCode,
5557 const SDLoc &dl) {
5558 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5559 GetExpandedInteger(Op: NewLHS, Lo&: LHSLo, Hi&: LHSHi);
5560 GetExpandedInteger(Op: NewRHS, Lo&: RHSLo, Hi&: RHSHi);
5561
5562 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
5563 if (RHSLo == RHSHi && isAllOnesConstant(V: RHSLo)) {
5564 // Equality comparison to -1.
5565 NewLHS = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: LHSHi);
5566 NewRHS = RHSLo;
5567 return;
5568 }
5569
5570 NewLHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSLo, N2: RHSLo);
5571 NewRHS = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: LHSLo.getValueType(), N1: LHSHi, N2: RHSHi);
5572 NewLHS = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NewLHS.getValueType(), N1: NewLHS, N2: NewRHS);
5573 NewRHS = DAG.getConstant(Val: 0, DL: dl, VT: NewLHS.getValueType());
5574 return;
5575 }
5576
5577 // If this is a comparison of the sign bit, just look at the top part.
5578 // X > -1, x < 0
5579 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Val&: NewRHS))
5580 if ((CCCode == ISD::SETLT && CST->isZero()) || // X < 0
5581 (CCCode == ISD::SETGT && CST->isAllOnes())) { // X > -1
5582 NewLHS = LHSHi;
5583 NewRHS = RHSHi;
5584 return;
5585 }
5586
5587 // FIXME: This generated code sucks.
5588 ISD::CondCode LowCC;
5589 switch (CCCode) {
5590 default: llvm_unreachable("Unknown integer setcc!");
5591 case ISD::SETLT:
5592 case ISD::SETULT: LowCC = ISD::SETULT; break;
5593 case ISD::SETGT:
5594 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5595 case ISD::SETLE:
5596 case ISD::SETULE: LowCC = ISD::SETULE; break;
5597 case ISD::SETGE:
5598 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5599 }
5600
5601 // LoCmp = lo(op1) < lo(op2) // Always unsigned comparison
5602 // HiCmp = hi(op1) < hi(op2) // Signedness depends on operands
5603 // dest = hi(op1) == hi(op2) ? LoCmp : HiCmp;
5604
5605 // NOTE: on targets without efficient SELECT of bools, we can always use
5606 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5607 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
5608 nullptr);
5609 SDValue LoCmp, HiCmp;
5610 if (TLI.isTypeLegal(VT: LHSLo.getValueType()) &&
5611 TLI.isTypeLegal(VT: RHSLo.getValueType()))
5612 LoCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSLo.getValueType()), N0: LHSLo,
5613 N1: RHSLo, Cond: LowCC, foldBooleans: false, DCI&: DagCombineInfo, dl);
5614 if (!LoCmp.getNode())
5615 LoCmp = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: LHSLo.getValueType()), LHS: LHSLo,
5616 RHS: RHSLo, Cond: LowCC);
5617 if (TLI.isTypeLegal(VT: LHSHi.getValueType()) &&
5618 TLI.isTypeLegal(VT: RHSHi.getValueType()))
5619 HiCmp = TLI.SimplifySetCC(VT: getSetCCResultType(VT: LHSHi.getValueType()), N0: LHSHi,
5620 N1: RHSHi, Cond: CCCode, foldBooleans: false, DCI&: DagCombineInfo, dl);
5621 if (!HiCmp.getNode())
5622 HiCmp =
5623 DAG.getNode(Opcode: ISD::SETCC, DL: dl, VT: getSetCCResultType(VT: LHSHi.getValueType()),
5624 N1: LHSHi, N2: RHSHi, N3: DAG.getCondCode(Cond: CCCode));
5625
5626 ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(Val: LoCmp.getNode());
5627 ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(Val: HiCmp.getNode());
5628
5629 bool EqAllowed = ISD::isTrueWhenEqual(Cond: CCCode);
5630
5631 // FIXME: Is the HiCmpC->isOne() here correct for
5632 // ZeroOrNegativeOneBooleanContent.
5633 if ((EqAllowed && (HiCmpC && HiCmpC->isZero())) ||
5634 (!EqAllowed &&
5635 ((HiCmpC && HiCmpC->isOne()) || (LoCmpC && LoCmpC->isZero())))) {
5636 // For LE / GE, if high part is known false, ignore the low part.
5637 // For LT / GT: if low part is known false, return the high part.
5638 // if high part is known true, ignore the low part.
5639 NewLHS = HiCmp;
5640 NewRHS = SDValue();
5641 return;
5642 }
5643
5644 if (LHSHi == RHSHi) {
5645 // Comparing the low bits is enough.
5646 NewLHS = LoCmp;
5647 NewRHS = SDValue();
5648 return;
5649 }
5650
5651 // Lower with SETCCCARRY if the target supports it.
5652 EVT HiVT = LHSHi.getValueType();
5653 EVT ExpandVT = TLI.getTypeToExpandTo(Context&: *DAG.getContext(), VT: HiVT);
5654 bool HasSETCCCARRY = TLI.isOperationLegalOrCustom(Op: ISD::SETCCCARRY, VT: ExpandVT);
5655
5656 // FIXME: Make all targets support this, then remove the other lowering.
5657 if (HasSETCCCARRY) {
5658 // SETCCCARRY can detect < and >= directly. For > and <=, flip
5659 // operands and condition code.
5660 bool FlipOperands = false;
5661 switch (CCCode) {
5662 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
5663 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
5664 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
5665 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
5666 default: break;
5667 }
5668 if (FlipOperands) {
5669 std::swap(a&: LHSLo, b&: RHSLo);
5670 std::swap(a&: LHSHi, b&: RHSHi);
5671 }
5672 // Perform a wide subtraction, feeding the carry from the low part into
5673 // SETCCCARRY. The SETCCCARRY operation is essentially looking at the high
5674 // part of the result of LHS - RHS. It is negative iff LHS < RHS. It is
5675 // zero or positive iff LHS >= RHS.
5676 EVT LoVT = LHSLo.getValueType();
5677 SDVTList VTList = DAG.getVTList(VT1: LoVT, VT2: getSetCCResultType(VT: LoVT));
5678 SDValue LowCmp = DAG.getNode(Opcode: ISD::USUBO, DL: dl, VTList, N1: LHSLo, N2: RHSLo);
5679 SDValue Res = DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: getSetCCResultType(VT: HiVT),
5680 N1: LHSHi, N2: RHSHi, N3: LowCmp.getValue(R: 1),
5681 N4: DAG.getCondCode(Cond: CCCode));
5682 NewLHS = Res;
5683 NewRHS = SDValue();
5684 return;
5685 }
5686
5687 NewLHS = TLI.SimplifySetCC(VT: getSetCCResultType(VT: HiVT), N0: LHSHi, N1: RHSHi, Cond: ISD::SETEQ,
5688 foldBooleans: false, DCI&: DagCombineInfo, dl);
5689 if (!NewLHS.getNode())
5690 NewLHS =
5691 DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: HiVT), LHS: LHSHi, RHS: RHSHi, Cond: ISD::SETEQ);
5692 NewLHS = DAG.getSelect(DL: dl, VT: LoCmp.getValueType(), Cond: NewLHS, LHS: LoCmp, RHS: HiCmp);
5693 NewRHS = SDValue();
5694}
5695
5696SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
5697 SDValue NewLHS = N->getOperand(Num: 2), NewRHS = N->getOperand(Num: 3);
5698 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 1))->get();
5699 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5700
5701 // If ExpandSetCCOperands returned a scalar, we need to compare the result
5702 // against zero to select between true and false values.
5703 if (!NewRHS.getNode()) {
5704 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
5705 CCCode = ISD::SETNE;
5706 }
5707
5708 // Update N to have the operands specified.
5709 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
5710 Op2: DAG.getCondCode(Cond: CCCode), Op3: NewLHS, Op4: NewRHS,
5711 Op5: N->getOperand(Num: 4)), 0);
5712}
5713
5714SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
5715 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
5716 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get();
5717 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5718
5719 // If ExpandSetCCOperands returned a scalar, we need to compare the result
5720 // against zero to select between true and false values.
5721 if (!NewRHS.getNode()) {
5722 NewRHS = DAG.getConstant(Val: 0, DL: SDLoc(N), VT: NewLHS.getValueType());
5723 CCCode = ISD::SETNE;
5724 }
5725
5726 // Update N to have the operands specified.
5727 return SDValue(DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS,
5728 Op3: N->getOperand(Num: 2), Op4: N->getOperand(Num: 3),
5729 Op5: DAG.getCondCode(Cond: CCCode)), 0);
5730}
5731
5732SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
5733 SDValue NewLHS = N->getOperand(Num: 0), NewRHS = N->getOperand(Num: 1);
5734 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get();
5735 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, dl: SDLoc(N));
5736
5737 // If ExpandSetCCOperands returned a scalar, use it.
5738 if (!NewRHS.getNode()) {
5739 assert(NewLHS.getValueType() == N->getValueType(0) &&
5740 "Unexpected setcc expansion!");
5741 return NewLHS;
5742 }
5743
5744 // Otherwise, update N to have the operands specified.
5745 return SDValue(
5746 DAG.UpdateNodeOperands(N, Op1: NewLHS, Op2: NewRHS, Op3: DAG.getCondCode(Cond: CCCode)), 0);
5747}
5748
5749SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
5750 SDValue LHS = N->getOperand(Num: 0);
5751 SDValue RHS = N->getOperand(Num: 1);
5752 SDValue Carry = N->getOperand(Num: 2);
5753 SDValue Cond = N->getOperand(Num: 3);
5754 SDLoc dl = SDLoc(N);
5755
5756 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5757 GetExpandedInteger(Op: LHS, Lo&: LHSLo, Hi&: LHSHi);
5758 GetExpandedInteger(Op: RHS, Lo&: RHSLo, Hi&: RHSHi);
5759
5760 // Expand to a USUBO_CARRY for the low part and a SETCCCARRY for the high.
5761 SDVTList VTList = DAG.getVTList(VT1: LHSLo.getValueType(), VT2: Carry.getValueType());
5762 SDValue LowCmp =
5763 DAG.getNode(Opcode: ISD::USUBO_CARRY, DL: dl, VTList, N1: LHSLo, N2: RHSLo, N3: Carry);
5764 return DAG.getNode(Opcode: ISD::SETCCCARRY, DL: dl, VT: N->getValueType(ResNo: 0), N1: LHSHi, N2: RHSHi,
5765 N3: LowCmp.getValue(R: 1), N4: Cond);
5766}
5767
5768SDValue DAGTypeLegalizer::ExpandIntOp_SPLAT_VECTOR(SDNode *N) {
5769 // Split the operand and replace with SPLAT_VECTOR_PARTS.
5770 SDValue Lo, Hi;
5771 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5772 return DAG.getNode(Opcode: ISD::SPLAT_VECTOR_PARTS, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: Lo,
5773 N2: Hi);
5774}
5775
5776SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
5777 // The value being shifted is legal, but the shift amount is too big.
5778 // It follows that either the result of the shift is undefined, or the
5779 // upper half of the shift amount is zero. Just use the lower half.
5780 SDValue Lo, Hi;
5781 GetExpandedInteger(Op: N->getOperand(Num: 1), Lo, Hi);
5782 return SDValue(DAG.UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: Lo), 0);
5783}
5784
5785SDValue DAGTypeLegalizer::ExpandIntOp_CMP(SDNode *N) {
5786 return TLI.expandCMP(Node: N, DAG);
5787}
5788
5789SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
5790 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
5791 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
5792 // constant to valid type.
5793 SDValue Lo, Hi;
5794 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo, Hi);
5795 return SDValue(DAG.UpdateNodeOperands(N, Op: Lo), 0);
5796}
5797
5798SDValue DAGTypeLegalizer::ExpandIntOp_XINT_TO_FP(SDNode *N) {
5799 bool IsStrict = N->isStrictFPOpcode();
5800 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP ||
5801 N->getOpcode() == ISD::STRICT_SINT_TO_FP;
5802 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : SDValue();
5803 SDValue Op = N->getOperand(Num: IsStrict ? 1 : 0);
5804 EVT DstVT = N->getValueType(ResNo: 0);
5805 RTLIB::Libcall LC = IsSigned ? RTLIB::getSINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT)
5806 : RTLIB::getUINTTOFP(OpVT: Op.getValueType(), RetVT: DstVT);
5807 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
5808 "Don't know how to expand this XINT_TO_FP!");
5809 TargetLowering::MakeLibCallOptions CallOptions;
5810 CallOptions.setIsSigned(true);
5811 std::pair<SDValue, SDValue> Tmp =
5812 TLI.makeLibCall(DAG, LC, RetVT: DstVT, Ops: Op, CallOptions, dl: SDLoc(N), Chain);
5813
5814 if (!IsStrict)
5815 return Tmp.first;
5816
5817 ReplaceValueWith(From: SDValue(N, 1), To: Tmp.second);
5818 ReplaceValueWith(From: SDValue(N, 0), To: Tmp.first);
5819 return SDValue();
5820}
5821
5822SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
5823 assert(!N->isAtomic() && "Should have been a ATOMIC_STORE?");
5824
5825 if (ISD::isNormalStore(N))
5826 return ExpandOp_NormalStore(N, OpNo);
5827
5828 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
5829 assert(OpNo == 1 && "Can only expand the stored value so far");
5830
5831 EVT VT = N->getOperand(Num: 1).getValueType();
5832 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
5833 SDValue Ch = N->getChain();
5834 SDValue Ptr = N->getBasePtr();
5835 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
5836 AAMDNodes AAInfo = N->getAAInfo();
5837 SDLoc dl(N);
5838 SDValue Lo, Hi;
5839
5840 assert(NVT.isByteSized() && "Expanded type not byte sized!");
5841
5842 if (N->getMemoryVT().bitsLE(VT: NVT)) {
5843 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
5844 return DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(),
5845 SVT: N->getMemoryVT(), Alignment: N->getBaseAlign(), MMOFlags,
5846 AAInfo);
5847 }
5848
5849 if (DAG.getDataLayout().isLittleEndian()) {
5850 // Little-endian - low bits are at low addresses.
5851 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
5852
5853 Lo = DAG.getStore(Chain: Ch, dl, Val: Lo, Ptr, PtrInfo: N->getPointerInfo(), Alignment: N->getBaseAlign(),
5854 MMOFlags, AAInfo);
5855
5856 unsigned ExcessBits =
5857 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
5858 EVT NEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits);
5859
5860 // Increment the pointer to the other half.
5861 unsigned IncrementSize = NVT.getSizeInBits()/8;
5862 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
5863 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr,
5864 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
5865 SVT: NEVT, Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
5866 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
5867 }
5868
5869 // Big-endian - high bits are at low addresses. Favor aligned stores at
5870 // the cost of some bit-fiddling.
5871 GetExpandedInteger(Op: N->getValue(), Lo, Hi);
5872
5873 EVT ExtVT = N->getMemoryVT();
5874 unsigned EBytes = ExtVT.getStoreSize();
5875 unsigned IncrementSize = NVT.getSizeInBits()/8;
5876 unsigned ExcessBits = (EBytes - IncrementSize)*8;
5877 EVT HiVT = EVT::getIntegerVT(Context&: *DAG.getContext(),
5878 BitWidth: ExtVT.getSizeInBits() - ExcessBits);
5879
5880 if (ExcessBits < NVT.getSizeInBits()) {
5881 // Transfer high bits from the top of Lo to the bottom of Hi.
5882 Hi = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: Hi,
5883 N2: DAG.getConstant(Val: NVT.getSizeInBits() - ExcessBits, DL: dl,
5884 VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
5885 Hi = DAG.getNode(
5886 Opcode: ISD::OR, DL: dl, VT: NVT, N1: Hi,
5887 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: NVT, N1: Lo,
5888 N2: DAG.getConstant(Val: ExcessBits, DL: dl,
5889 VT: TLI.getPointerTy(DL: DAG.getDataLayout()))));
5890 }
5891
5892 // Store both the high bits and maybe some of the low bits.
5893 Hi = DAG.getTruncStore(Chain: Ch, dl, Val: Hi, Ptr, PtrInfo: N->getPointerInfo(), SVT: HiVT,
5894 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
5895
5896 // Increment the pointer to the other half.
5897 Ptr = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize));
5898 // Store the lowest ExcessBits bits in the second half.
5899 Lo = DAG.getTruncStore(Chain: Ch, dl, Val: Lo, Ptr,
5900 PtrInfo: N->getPointerInfo().getWithOffset(O: IncrementSize),
5901 SVT: EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExcessBits),
5902 Alignment: N->getBaseAlign(), MMOFlags, AAInfo);
5903 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
5904}
5905
5906SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
5907 SDValue InL, InH;
5908 GetExpandedInteger(Op: N->getOperand(Num: 0), Lo&: InL, Hi&: InH);
5909 // Just truncate the low part of the source.
5910 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: InL);
5911}
5912
5913SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
5914 SDLoc dl(N);
5915 SDValue Swap =
5916 DAG.getAtomic(Opcode: ISD::ATOMIC_SWAP, dl, MemVT: cast<AtomicSDNode>(Val: N)->getMemoryVT(),
5917 Chain: N->getOperand(Num: 0), Ptr: N->getOperand(Num: 2), Val: N->getOperand(Num: 1),
5918 MMO: cast<AtomicSDNode>(Val: N)->getMemOperand());
5919 return Swap.getValue(R: 1);
5920}
5921
5922SDValue DAGTypeLegalizer::ExpandIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
5923 assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
5924 (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
5925
5926 SDValue Hi; // The upper half is dropped out.
5927 SmallVector<SDValue, 8> NewOps(N->ops());
5928 GetExpandedInteger(Op: NewOps[OpNo], Lo&: NewOps[OpNo], Hi);
5929
5930 return SDValue(DAG.UpdateNodeOperands(N, Ops: NewOps), 0);
5931}
5932
5933SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SPLICE(SDNode *N) {
5934 SDLoc dl(N);
5935
5936 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
5937 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
5938 EVT OutVT = V0.getValueType();
5939
5940 return DAG.getNode(Opcode: ISD::VECTOR_SPLICE, DL: dl, VT: OutVT, N1: V0, N2: V1, N3: N->getOperand(Num: 2));
5941}
5942
5943SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE(SDNode *N) {
5944 SDLoc DL(N);
5945 unsigned Factor = N->getNumOperands();
5946
5947 SmallVector<SDValue, 8> Ops(Factor);
5948 for (unsigned i = 0; i != Factor; i++)
5949 Ops[i] = GetPromotedInteger(Op: N->getOperand(Num: i));
5950
5951 SmallVector<EVT, 8> ResVTs(Factor, Ops[0].getValueType());
5952 SDValue Res = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: DAG.getVTList(VTs: ResVTs), Ops);
5953
5954 for (unsigned i = 0; i != Factor; i++)
5955 SetPromotedInteger(Op: SDValue(N, i), Result: Res.getValue(R: i));
5956
5957 return SDValue();
5958}
5959
5960SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
5961
5962 EVT OutVT = N->getValueType(ResNo: 0);
5963 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
5964 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
5965 EVT NOutVTElem = NOutVT.getVectorElementType();
5966
5967 SDLoc dl(N);
5968 SDValue BaseIdx = N->getOperand(Num: 1);
5969
5970 // TODO: We may be able to use this for types other than scalable
5971 // vectors and fix those tests that expect BUILD_VECTOR to be used
5972 if (OutVT.isScalableVector()) {
5973 SDValue InOp0 = N->getOperand(Num: 0);
5974 EVT InVT = InOp0.getValueType();
5975
5976 // Try and extract from a smaller type so that it eventually falls
5977 // into the promotion code below.
5978 if (getTypeAction(VT: InVT) == TargetLowering::TypeSplitVector ||
5979 getTypeAction(VT: InVT) == TargetLowering::TypeLegal) {
5980 EVT NInVT = InVT.getHalfNumVectorElementsVT(Context&: *DAG.getContext());
5981 unsigned NElts = NInVT.getVectorMinNumElements();
5982 uint64_t IdxVal = BaseIdx->getAsZExtVal();
5983
5984 SDValue Step1 = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: NInVT, N1: InOp0,
5985 N2: DAG.getConstant(Val: alignDown(Value: IdxVal, Align: NElts), DL: dl,
5986 VT: BaseIdx.getValueType()));
5987 SDValue Step2 = DAG.getNode(
5988 Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: Step1,
5989 N2: DAG.getConstant(Val: IdxVal % NElts, DL: dl, VT: BaseIdx.getValueType()));
5990 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Step2);
5991 }
5992
5993 // Try and extract from a widened type.
5994 if (getTypeAction(VT: InVT) == TargetLowering::TypeWidenVector) {
5995 SDValue Ops[] = {GetWidenedVector(Op: InOp0), BaseIdx};
5996 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: OutVT, Ops);
5997 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
5998 }
5999
6000 // Promote operands and see if this is handled by target lowering,
6001 // Otherwise, use the BUILD_VECTOR approach below
6002 if (getTypeAction(VT: InVT) == TargetLowering::TypePromoteInteger) {
6003 // Collect the (promoted) operands
6004 SDValue Ops[] = { GetPromotedInteger(Op: InOp0), BaseIdx };
6005
6006 EVT PromEltVT = Ops[0].getValueType().getVectorElementType();
6007 assert(PromEltVT.bitsLE(NOutVTElem) &&
6008 "Promoted operand has an element type greater than result");
6009
6010 EVT ExtVT = NOutVT.changeVectorElementType(EltVT: PromEltVT);
6011 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: SDLoc(N), VT: ExtVT, Ops);
6012 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutVT, Operand: Ext);
6013 }
6014 }
6015
6016 if (OutVT.isScalableVector())
6017 report_fatal_error(reason: "Unable to promote scalable types using BUILD_VECTOR");
6018
6019 SDValue InOp0 = N->getOperand(Num: 0);
6020 if (getTypeAction(VT: InOp0.getValueType()) == TargetLowering::TypePromoteInteger)
6021 InOp0 = GetPromotedInteger(Op: InOp0);
6022
6023 EVT InVT = InOp0.getValueType();
6024 EVT InSVT = InVT.getVectorElementType();
6025
6026 unsigned OutNumElems = OutVT.getVectorNumElements();
6027 SmallVector<SDValue, 8> Ops;
6028 Ops.reserve(N: OutNumElems);
6029 for (unsigned i = 0; i != OutNumElems; ++i) {
6030 // Extract the element from the original vector.
6031 SDValue Index = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: BaseIdx.getValueType(), N1: BaseIdx,
6032 N2: DAG.getConstant(Val: i, DL: dl, VT: BaseIdx.getValueType()));
6033 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: InSVT,
6034 N1: N->getOperand(Num: 0), N2: Index);
6035 SDValue Op = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: NOutVTElem);
6036 // Insert the converted element to the new vector.
6037 Ops.push_back(Elt: Op);
6038 }
6039
6040 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6041}
6042
6043SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_SUBVECTOR(SDNode *N) {
6044 EVT OutVT = N->getValueType(ResNo: 0);
6045 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6046 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6047
6048 SDLoc dl(N);
6049 SDValue Vec = N->getOperand(Num: 0);
6050 SDValue SubVec = N->getOperand(Num: 1);
6051 SDValue Idx = N->getOperand(Num: 2);
6052
6053 EVT SubVecVT = SubVec.getValueType();
6054 EVT NSubVT =
6055 EVT::getVectorVT(Context&: *DAG.getContext(), VT: NOutVT.getVectorElementType(),
6056 EC: SubVecVT.getVectorElementCount());
6057
6058 Vec = GetPromotedInteger(Op: Vec);
6059 SubVec = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NSubVT, Operand: SubVec);
6060
6061 return DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: NOutVT, N1: Vec, N2: SubVec, N3: Idx);
6062}
6063
6064SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REVERSE(SDNode *N) {
6065 SDLoc dl(N);
6066
6067 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6068 EVT OutVT = V0.getValueType();
6069
6070 return DAG.getNode(Opcode: ISD::VECTOR_REVERSE, DL: dl, VT: OutVT, Operand: V0);
6071}
6072
6073SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
6074 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(Val: N);
6075 EVT VT = N->getValueType(ResNo: 0);
6076 SDLoc dl(N);
6077
6078 ArrayRef<int> NewMask = SV->getMask().slice(N: 0, M: VT.getVectorNumElements());
6079
6080 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6081 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6082 EVT OutVT = V0.getValueType();
6083
6084 return DAG.getVectorShuffle(VT: OutVT, dl, N1: V0, N2: V1, Mask: NewMask);
6085}
6086
6087SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
6088 EVT OutVT = N->getValueType(ResNo: 0);
6089 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6090 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6091 unsigned NumElems = N->getNumOperands();
6092 EVT NOutVTElem = NOutVT.getVectorElementType();
6093 TargetLoweringBase::BooleanContent NOutBoolType = TLI.getBooleanContents(Type: NOutVT);
6094 unsigned NOutExtOpc = TargetLowering::getExtendForContent(Content: NOutBoolType);
6095 SDLoc dl(N);
6096
6097 SmallVector<SDValue, 8> Ops;
6098 Ops.reserve(N: NumElems);
6099 for (unsigned i = 0; i != NumElems; ++i) {
6100 SDValue Op = N->getOperand(Num: i);
6101 EVT OpVT = Op.getValueType();
6102 // BUILD_VECTOR integer operand types are allowed to be larger than the
6103 // result's element type. This may still be true after the promotion. For
6104 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
6105 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
6106 if (OpVT.bitsLT(VT: NOutVTElem)) {
6107 unsigned ExtOpc = ISD::ANY_EXTEND;
6108 // Attempt to extend constant bool vectors to match target's BooleanContent.
6109 // While not necessary, this improves chances of the constant correctly
6110 // folding with compare results (e.g. for NOT patterns).
6111 if (OpVT == MVT::i1 && Op.getOpcode() == ISD::Constant)
6112 ExtOpc = NOutExtOpc;
6113 Op = DAG.getNode(Opcode: ExtOpc, DL: dl, VT: NOutVTElem, Operand: Op);
6114 }
6115 Ops.push_back(Elt: Op);
6116 }
6117
6118 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6119}
6120
6121SDValue DAGTypeLegalizer::PromoteIntRes_ScalarOp(SDNode *N) {
6122
6123 SDLoc dl(N);
6124
6125 assert(!N->getOperand(0).getValueType().isVector() &&
6126 "Input must be a scalar");
6127
6128 EVT OutVT = N->getValueType(ResNo: 0);
6129 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6130 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6131 EVT NOutElemVT = NOutVT.getVectorElementType();
6132
6133 SDValue Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NOutElemVT, Operand: N->getOperand(Num: 0));
6134 if (N->isVPOpcode())
6135 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NOutVT, N1: Op, N2: N->getOperand(Num: 1),
6136 N3: N->getOperand(Num: 2));
6137
6138 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NOutVT, Operand: Op);
6139}
6140
6141SDValue DAGTypeLegalizer::PromoteIntRes_STEP_VECTOR(SDNode *N) {
6142 SDLoc dl(N);
6143 EVT OutVT = N->getValueType(ResNo: 0);
6144 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6145 assert(NOutVT.isScalableVector() &&
6146 "Type must be promoted to a scalable vector type");
6147 const APInt &StepVal = N->getConstantOperandAPInt(Num: 0);
6148 return DAG.getStepVector(DL: dl, ResVT: NOutVT,
6149 StepVal: StepVal.sext(width: NOutVT.getScalarSizeInBits()));
6150}
6151
6152SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
6153 SDLoc dl(N);
6154
6155 EVT OutVT = N->getValueType(ResNo: 0);
6156 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6157 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6158
6159 unsigned NumOperands = N->getNumOperands();
6160 unsigned NumOutElem = NOutVT.getVectorMinNumElements();
6161 EVT OutElemTy = NOutVT.getVectorElementType();
6162 if (OutVT.isScalableVector()) {
6163 // Find the largest promoted element type for each of the operands.
6164 SDUse *MaxSizedValue = std::max_element(
6165 first: N->op_begin(), last: N->op_end(), comp: [](const SDValue &A, const SDValue &B) {
6166 EVT AVT = A.getValueType().getVectorElementType();
6167 EVT BVT = B.getValueType().getVectorElementType();
6168 return AVT.getScalarSizeInBits() < BVT.getScalarSizeInBits();
6169 });
6170 EVT MaxElementVT = MaxSizedValue->getValueType().getVectorElementType();
6171
6172 // Then promote all vectors to the largest element type.
6173 SmallVector<SDValue, 8> Ops;
6174 for (unsigned I = 0; I < NumOperands; ++I) {
6175 SDValue Op = N->getOperand(Num: I);
6176 EVT OpVT = Op.getValueType();
6177 if (getTypeAction(VT: OpVT) == TargetLowering::TypePromoteInteger)
6178 Op = GetPromotedInteger(Op);
6179 else
6180 assert(getTypeAction(OpVT) == TargetLowering::TypeLegal &&
6181 "Unhandled legalization type");
6182
6183 if (OpVT.getVectorElementType().getScalarSizeInBits() <
6184 MaxElementVT.getScalarSizeInBits())
6185 Op = DAG.getAnyExtOrTrunc(Op, DL: dl,
6186 VT: OpVT.changeVectorElementType(EltVT: MaxElementVT));
6187 Ops.push_back(Elt: Op);
6188 }
6189
6190 // Do the CONCAT on the promoted type and finally truncate to (the promoted)
6191 // NOutVT.
6192 return DAG.getAnyExtOrTrunc(
6193 Op: DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL: dl,
6194 VT: OutVT.changeVectorElementType(EltVT: MaxElementVT), Ops),
6195 DL: dl, VT: NOutVT);
6196 }
6197
6198 unsigned NumElem = N->getOperand(Num: 0).getValueType().getVectorNumElements();
6199 assert(NumElem * NumOperands == NumOutElem &&
6200 "Unexpected number of elements");
6201
6202 // Take the elements from the first vector.
6203 SmallVector<SDValue, 8> Ops(NumOutElem);
6204 for (unsigned i = 0; i < NumOperands; ++i) {
6205 SDValue Op = N->getOperand(Num: i);
6206 if (getTypeAction(VT: Op.getValueType()) == TargetLowering::TypePromoteInteger)
6207 Op = GetPromotedInteger(Op);
6208 EVT SclrTy = Op.getValueType().getVectorElementType();
6209 assert(NumElem == Op.getValueType().getVectorNumElements() &&
6210 "Unexpected number of elements");
6211
6212 for (unsigned j = 0; j < NumElem; ++j) {
6213 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Op,
6214 N2: DAG.getVectorIdxConstant(Val: j, DL: dl));
6215 Ops[i * NumElem + j] = DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: OutElemTy);
6216 }
6217 }
6218
6219 return DAG.getBuildVector(VT: NOutVT, DL: dl, Ops);
6220}
6221
6222SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
6223 EVT VT = N->getValueType(ResNo: 0);
6224 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6225 assert(NVT.isVector() && "This type must be promoted to a vector type");
6226
6227 SDLoc dl(N);
6228
6229 // For operands whose TypeAction is to promote, extend the promoted node
6230 // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
6231 // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
6232 // type..
6233 if (getTypeAction(VT: N->getOperand(Num: 0).getValueType())
6234 == TargetLowering::TypePromoteInteger) {
6235 SDValue Promoted;
6236
6237 switch(N->getOpcode()) {
6238 case ISD::SIGN_EXTEND_VECTOR_INREG:
6239 Promoted = SExtPromotedInteger(Op: N->getOperand(Num: 0));
6240 break;
6241 case ISD::ZERO_EXTEND_VECTOR_INREG:
6242 Promoted = ZExtPromotedInteger(Op: N->getOperand(Num: 0));
6243 break;
6244 case ISD::ANY_EXTEND_VECTOR_INREG:
6245 Promoted = GetPromotedInteger(Op: N->getOperand(Num: 0));
6246 break;
6247 default:
6248 llvm_unreachable("Node has unexpected Opcode");
6249 }
6250 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: Promoted);
6251 }
6252
6253 // Directly extend to the appropriate transform-to type.
6254 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Operand: N->getOperand(Num: 0));
6255}
6256
6257SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(SDNode *N) {
6258 EVT VT = N->getValueType(ResNo: 0);
6259 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6260 return DAG.getNode(Opcode: ISD::VECTOR_FIND_LAST_ACTIVE, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6261}
6262
6263SDValue DAGTypeLegalizer::PromoteIntRes_GET_ACTIVE_LANE_MASK(SDNode *N) {
6264 EVT VT = N->getValueType(ResNo: 0);
6265 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6266 return DAG.getNode(Opcode: ISD::GET_ACTIVE_LANE_MASK, DL: SDLoc(N), VT: NVT, Ops: N->ops());
6267}
6268
6269SDValue DAGTypeLegalizer::PromoteIntRes_PARTIAL_REDUCE_MLA(SDNode *N) {
6270 SDLoc DL(N);
6271 EVT VT = N->getValueType(ResNo: 0);
6272 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT);
6273 SDValue ExtAcc = GetPromotedInteger(Op: N->getOperand(Num: 0));
6274 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: NVT, N1: ExtAcc, N2: N->getOperand(Num: 1),
6275 N3: N->getOperand(Num: 2));
6276}
6277
6278SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
6279 EVT OutVT = N->getValueType(ResNo: 0);
6280 EVT NOutVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: OutVT);
6281 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
6282
6283 EVT NOutVTElem = NOutVT.getVectorElementType();
6284
6285 SDLoc dl(N);
6286 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6287
6288 SDValue ConvElem = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6289 VT: NOutVTElem, Operand: N->getOperand(Num: 1));
6290 return DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: NOutVT,
6291 N1: V0, N2: ConvElem, N3: N->getOperand(Num: 2));
6292}
6293
6294SDValue DAGTypeLegalizer::PromoteIntRes_VECREDUCE(SDNode *N) {
6295 // The VECREDUCE result size may be larger than the element size, so
6296 // we can simply change the result type.
6297 SDLoc dl(N);
6298 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6299 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: NVT, Ops: N->ops());
6300}
6301
6302SDValue DAGTypeLegalizer::PromoteIntRes_VP_REDUCE(SDNode *N) {
6303 // The VP_REDUCE result size may be larger than the element size, so we can
6304 // simply change the result type. However the start value and result must be
6305 // the same.
6306 SDLoc DL(N);
6307 SDValue Start = PromoteIntOpVectorReduction(N, V: N->getOperand(Num: 0));
6308 return DAG.getNode(Opcode: N->getOpcode(), DL, VT: Start.getValueType(), N1: Start,
6309 N2: N->getOperand(Num: 1), N3: N->getOperand(Num: 2), N4: N->getOperand(Num: 3));
6310}
6311
6312SDValue DAGTypeLegalizer::PromoteIntRes_PATCHPOINT(SDNode *N) {
6313 EVT NVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: N->getValueType(ResNo: 0));
6314 SDLoc dl(N);
6315
6316 assert(N->getNumValues() == 3 && "Expected 3 values for PATCHPOINT");
6317 SDVTList VTList = DAG.getVTList(VTs: {NVT, MVT::Other, MVT::Glue});
6318
6319 SmallVector<SDValue> Ops(N->ops());
6320 SDValue Res = DAG.getNode(Opcode: ISD::PATCHPOINT, DL: dl, VTList, Ops);
6321
6322 // Replace chain and glue uses with the new patchpoint.
6323 SDValue From[] = {SDValue(N, 1), SDValue(N, 2)};
6324 SDValue To[] = {Res.getValue(R: 1), Res.getValue(R: 2)};
6325 DAG.ReplaceAllUsesOfValuesWith(From, To, Num: 2);
6326
6327 return Res.getValue(R: 0);
6328}
6329
6330SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
6331 SDLoc dl(N);
6332 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6333 SDValue V1 = DAG.getZExtOrTrunc(Op: N->getOperand(Num: 1), DL: dl,
6334 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
6335 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl,
6336 VT: V0->getValueType(ResNo: 0).getScalarType(), N1: V0, N2: V1);
6337
6338 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
6339 // element types. If this is the case then we need to expand the outgoing
6340 // value and not truncate it.
6341 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6342}
6343
6344SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_SUBVECTOR(SDNode *N) {
6345 SDLoc dl(N);
6346 // The result type is equal to the first input operand's type, so the
6347 // type that needs promoting must be the second source vector.
6348 SDValue V0 = N->getOperand(Num: 0);
6349 SDValue V1 = GetPromotedInteger(Op: N->getOperand(Num: 1));
6350 SDValue Idx = N->getOperand(Num: 2);
6351 EVT PromVT = EVT::getVectorVT(Context&: *DAG.getContext(),
6352 VT: V1.getValueType().getVectorElementType(),
6353 EC: V0.getValueType().getVectorElementCount());
6354 V0 = DAG.getAnyExtOrTrunc(Op: V0, DL: dl, VT: PromVT);
6355 SDValue Ext = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: PromVT, N1: V0, N2: V1, N3: Idx);
6356 return DAG.getAnyExtOrTrunc(Op: Ext, DL: dl, VT: N->getValueType(ResNo: 0));
6357}
6358
6359// FIXME: We wouldn't need this if clang could promote short integers
6360// that are arguments to FAKE_USE.
6361SDValue DAGTypeLegalizer::PromoteIntOp_FAKE_USE(SDNode *N) {
6362 SDLoc dl(N);
6363 SDValue V0 = N->getOperand(Num: 0);
6364 SDValue V1 = N->getOperand(Num: 1);
6365 EVT InVT1 = V1.getValueType();
6366 SDValue VPromoted =
6367 DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl,
6368 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: InVT1), Operand: V1);
6369 return DAG.getNode(Opcode: N->getOpcode(), DL: dl, VT: N->getValueType(ResNo: 0), N1: V0, N2: VPromoted);
6370}
6371
6372SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
6373 SDLoc dl(N);
6374 SDValue V0 = GetPromotedInteger(Op: N->getOperand(Num: 0));
6375 MVT InVT = V0.getValueType().getSimpleVT();
6376 MVT OutVT = MVT::getVectorVT(VT: InVT.getVectorElementType(),
6377 NumElements: N->getValueType(ResNo: 0).getVectorNumElements());
6378 SDValue Ext = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: OutVT, N1: V0, N2: N->getOperand(Num: 1));
6379 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: N->getValueType(ResNo: 0), Operand: Ext);
6380}
6381
6382SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
6383 SDLoc dl(N);
6384
6385 EVT ResVT = N->getValueType(ResNo: 0);
6386 unsigned NumElems = N->getNumOperands();
6387
6388 if (ResVT.isScalableVector()) {
6389 SDValue ResVec = DAG.getUNDEF(VT: ResVT);
6390
6391 for (unsigned OpIdx = 0; OpIdx < NumElems; ++OpIdx) {
6392 SDValue Op = N->getOperand(Num: OpIdx);
6393 unsigned OpNumElts = Op.getValueType().getVectorMinNumElements();
6394 ResVec = DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: dl, VT: ResVT, N1: ResVec, N2: Op,
6395 N3: DAG.getIntPtrConstant(Val: OpIdx * OpNumElts, DL: dl));
6396 }
6397
6398 return ResVec;
6399 }
6400
6401 EVT RetSclrTy = N->getValueType(ResNo: 0).getVectorElementType();
6402
6403 SmallVector<SDValue, 8> NewOps;
6404 NewOps.reserve(N: NumElems);
6405
6406 // For each incoming vector
6407 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
6408 SDValue Incoming = GetPromotedInteger(Op: N->getOperand(Num: VecIdx));
6409 EVT SclrTy = Incoming->getValueType(ResNo: 0).getVectorElementType();
6410 unsigned NumElem = Incoming->getValueType(ResNo: 0).getVectorNumElements();
6411
6412 for (unsigned i=0; i<NumElem; ++i) {
6413 // Extract element from incoming vector
6414 SDValue Ex = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: SclrTy, N1: Incoming,
6415 N2: DAG.getVectorIdxConstant(Val: i, DL: dl));
6416 SDValue Tr = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: RetSclrTy, Operand: Ex);
6417 NewOps.push_back(Elt: Tr);
6418 }
6419 }
6420
6421 return DAG.getBuildVector(VT: N->getValueType(ResNo: 0), DL: dl, Ops: NewOps);
6422}
6423
6424SDValue DAGTypeLegalizer::ExpandIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
6425 assert(OpNo > 1);
6426 SDValue Op = N->getOperand(Num: OpNo);
6427
6428 // FIXME: Non-constant operands are not yet handled:
6429 // - https://github.com/llvm/llvm-project/issues/26431
6430 // - https://github.com/llvm/llvm-project/issues/55957
6431 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6432 if (!CN)
6433 return SDValue();
6434
6435 // Copy operands before the one being expanded.
6436 SmallVector<SDValue> NewOps;
6437 for (unsigned I = 0; I < OpNo; I++)
6438 NewOps.push_back(Elt: N->getOperand(Num: I));
6439
6440 EVT Ty = Op.getValueType();
6441 SDLoc DL = SDLoc(N);
6442 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6443 NewOps.push_back(
6444 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6445 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6446 } else {
6447 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6448 return SDValue();
6449 }
6450
6451 // Copy remaining operands.
6452 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6453 NewOps.push_back(Elt: N->getOperand(Num: I));
6454
6455 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6456
6457 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6458 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6459
6460 return SDValue(); // Signal that we have replaced the node already.
6461}
6462
6463SDValue DAGTypeLegalizer::ExpandIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
6464 assert(OpNo >= 7);
6465 SDValue Op = N->getOperand(Num: OpNo);
6466
6467 // FIXME: Non-constant operands are not yet handled:
6468 // - https://github.com/llvm/llvm-project/issues/26431
6469 // - https://github.com/llvm/llvm-project/issues/55957
6470 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val&: Op);
6471 if (!CN)
6472 return SDValue();
6473
6474 // Copy operands before the one being expanded.
6475 SmallVector<SDValue> NewOps;
6476 for (unsigned I = 0; I < OpNo; I++)
6477 NewOps.push_back(Elt: N->getOperand(Num: I));
6478
6479 EVT Ty = Op.getValueType();
6480 SDLoc DL = SDLoc(N);
6481 if (CN->getConstantIntValue()->getValue().getActiveBits() < 64) {
6482 NewOps.push_back(
6483 Elt: DAG.getTargetConstant(Val: StackMaps::ConstantOp, DL, VT: MVT::i64));
6484 NewOps.push_back(Elt: DAG.getTargetConstant(Val: CN->getZExtValue(), DL, VT: Ty));
6485 } else {
6486 // FIXME: https://github.com/llvm/llvm-project/issues/55609
6487 return SDValue();
6488 }
6489
6490 // Copy remaining operands.
6491 for (unsigned I = OpNo + 1; I < N->getNumOperands(); I++)
6492 NewOps.push_back(Elt: N->getOperand(Num: I));
6493
6494 SDValue NewNode = DAG.getNode(Opcode: N->getOpcode(), DL, VTList: N->getVTList(), Ops: NewOps);
6495
6496 for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
6497 ReplaceValueWith(From: SDValue(N, ResNum), To: NewNode.getValue(R: ResNum));
6498
6499 return SDValue(); // Signal that we have replaced the node already.
6500}
6501