1//===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines interfaces to access the target independent code
10// generation passes provided by the LLVM backend.
11//
12//===---------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/TargetPassConfig.h"
15#include "llvm/ADT/DenseMap.h"
16#include "llvm/ADT/SmallVector.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/Analysis/BasicAliasAnalysis.h"
19#include "llvm/Analysis/CallGraphSCCPass.h"
20#include "llvm/Analysis/ScopedNoAliasAA.h"
21#include "llvm/Analysis/TargetTransformInfo.h"
22#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
23#include "llvm/CodeGen/BasicBlockSectionsProfileReader.h"
24#include "llvm/CodeGen/CSEConfigBase.h"
25#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachinePassRegistry.h"
28#include "llvm/CodeGen/Passes.h"
29#include "llvm/CodeGen/RegAllocRegistry.h"
30#include "llvm/IR/IRPrintingPasses.h"
31#include "llvm/IR/LegacyPassManager.h"
32#include "llvm/IR/PassInstrumentation.h"
33#include "llvm/IR/Verifier.h"
34#include "llvm/InitializePasses.h"
35#include "llvm/MC/MCAsmInfo.h"
36#include "llvm/MC/MCTargetOptions.h"
37#include "llvm/Pass.h"
38#include "llvm/Support/CodeGen.h"
39#include "llvm/Support/CommandLine.h"
40#include "llvm/Support/Compiler.h"
41#include "llvm/Support/Debug.h"
42#include "llvm/Support/Discriminator.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/SaveAndRestore.h"
45#include "llvm/Support/Threading.h"
46#include "llvm/Support/VirtualFileSystem.h"
47#include "llvm/Support/WithColor.h"
48#include "llvm/Target/CGPassBuilderOption.h"
49#include "llvm/Target/TargetMachine.h"
50#include "llvm/Transforms/ObjCARC.h"
51#include "llvm/Transforms/Scalar.h"
52#include "llvm/Transforms/Utils.h"
53#include <cassert>
54#include <optional>
55#include <string>
56
57using namespace llvm;
58
59static cl::opt<bool>
60 EnableIPRA("enable-ipra", cl::init(Val: false), cl::Hidden,
61 cl::desc("Enable interprocedural register allocation "
62 "to reduce load/store at procedure calls."));
63static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
64 cl::desc("Disable Post Regalloc Scheduler"));
65static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
66 cl::desc("Disable branch folding"));
67static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
68 cl::desc("Disable tail duplication"));
69static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
70 cl::desc("Disable pre-register allocation tail duplication"));
71static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
72 cl::Hidden, cl::desc("Disable probability-driven block placement"));
73static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
74 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
75static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
76 cl::desc("Disable Stack Slot Coloring"));
77static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
78 cl::desc("Disable Machine Dead Code Elimination"));
79static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
80 cl::desc("Disable Early If-conversion"));
81static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
82 cl::desc("Disable Machine LICM"));
83static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
84 cl::desc("Disable Machine Common Subexpression Elimination"));
85static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
86 "optimize-regalloc", cl::Hidden,
87 cl::desc("Enable optimized register allocation compilation path."));
88static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
89 cl::Hidden,
90 cl::desc("Disable Machine LICM"));
91static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
92 cl::desc("Disable Machine Sinking"));
93static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
94 cl::Hidden,
95 cl::desc("Disable PostRA Machine Sinking"));
96static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
97 cl::desc("Disable Loop Strength Reduction Pass"));
98static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
99 cl::Hidden, cl::desc("Disable ConstantHoisting"));
100static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
101 cl::desc("Disable Codegen Prepare"));
102static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
103 cl::desc("Disable Copy Propagation pass"));
104static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
105 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
106static cl::opt<bool> DisableAtExitBasedGlobalDtorLowering(
107 "disable-atexit-based-global-dtor-lowering", cl::Hidden,
108 cl::desc("For MachO, disable atexit()-based global destructor lowering"));
109static cl::opt<bool> EnableImplicitNullChecks(
110 "enable-implicit-null-checks",
111 cl::desc("Fold null checks into faulting memory operations"),
112 cl::init(Val: false), cl::Hidden);
113static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
114 cl::desc("Disable MergeICmps Pass"),
115 cl::init(Val: false), cl::Hidden);
116static cl::opt<bool>
117 PrintISelInput("print-isel-input", cl::Hidden,
118 cl::desc("Print LLVM IR input to isel pass"));
119static cl::opt<cl::boolOrDefault>
120 VerifyMachineCode("verify-machineinstrs", cl::Hidden,
121 cl::desc("Verify generated machine code"));
122static cl::opt<cl::boolOrDefault>
123 DebugifyAndStripAll("debugify-and-strip-all-safe", cl::Hidden,
124 cl::desc("Debugify MIR before and Strip debug after "
125 "each pass except those known to be unsafe "
126 "when debug info is present"));
127static cl::opt<cl::boolOrDefault> DebugifyCheckAndStripAll(
128 "debugify-check-and-strip-all-safe", cl::Hidden,
129 cl::desc(
130 "Debugify MIR before, by checking and stripping the debug info after, "
131 "each pass except those known to be unsafe when debug info is "
132 "present"));
133// Enable or disable the MachineOutliner.
134static cl::opt<RunOutliner> EnableMachineOutliner(
135 "enable-machine-outliner", cl::desc("Enable the machine outliner"),
136 cl::Hidden, cl::ValueOptional, cl::init(Val: RunOutliner::TargetDefault),
137 cl::values(clEnumValN(RunOutliner::AlwaysOutline, "always",
138 "Run on all functions guaranteed to be beneficial"),
139 clEnumValN(RunOutliner::NeverOutline, "never",
140 "Disable all outlining"),
141 // Sentinel value for unspecified option.
142 clEnumValN(RunOutliner::AlwaysOutline, "", "")));
143static cl::opt<bool> EnableGlobalMergeFunc(
144 "enable-global-merge-func", cl::Hidden,
145 cl::desc("Enable global merge functions that are based on hash function"));
146// Disable the pass to fix unwind information. Whether the pass is included in
147// the pipeline is controlled via the target options, this option serves as
148// manual override.
149static cl::opt<bool> DisableCFIFixup("disable-cfi-fixup", cl::Hidden,
150 cl::desc("Disable the CFI fixup pass"));
151// Enable or disable FastISel. Both options are needed, because
152// FastISel is enabled by default with -fast, and we wish to be
153// able to enable or disable fast-isel independently from -O0.
154static cl::opt<cl::boolOrDefault>
155EnableFastISelOption("fast-isel", cl::Hidden,
156 cl::desc("Enable the \"fast\" instruction selector"));
157
158static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
159 "global-isel", cl::Hidden,
160 cl::desc("Enable the \"global\" instruction selector"));
161
162// FIXME: remove this after switching to NPM or GlobalISel, whichever gets there
163// first...
164static cl::opt<bool>
165 PrintAfterISel("print-after-isel", cl::init(Val: false), cl::Hidden,
166 cl::desc("Print machine instrs after ISel"));
167
168static cl::opt<GlobalISelAbortMode> EnableGlobalISelAbort(
169 "global-isel-abort", cl::Hidden,
170 cl::desc("Enable abort calls when \"global\" instruction selection "
171 "fails to lower/select an instruction"),
172 cl::values(
173 clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
174 clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
175 clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2",
176 "Disable the abort but emit a diagnostic on failure")));
177
178// Disable MIRProfileLoader before RegAlloc. This is for for debugging and
179// tuning purpose.
180static cl::opt<bool> DisableRAFSProfileLoader(
181 "disable-ra-fsprofile-loader", cl::init(Val: false), cl::Hidden,
182 cl::desc("Disable MIRProfileLoader before RegAlloc"));
183// Disable MIRProfileLoader before BloackPlacement. This is for for debugging
184// and tuning purpose.
185static cl::opt<bool> DisableLayoutFSProfileLoader(
186 "disable-layout-fsprofile-loader", cl::init(Val: false), cl::Hidden,
187 cl::desc("Disable MIRProfileLoader before BlockPlacement"));
188// Specify FSProfile file name.
189static cl::opt<std::string>
190 FSProfileFile("fs-profile-file", cl::init(Val: ""), cl::value_desc("filename"),
191 cl::desc("Flow Sensitive profile file name."), cl::Hidden);
192// Specify Remapping file for FSProfile.
193static cl::opt<std::string> FSRemappingFile(
194 "fs-remapping-file", cl::init(Val: ""), cl::value_desc("filename"),
195 cl::desc("Flow Sensitive profile remapping file name."), cl::Hidden);
196
197// Temporary option to allow experimenting with MachineScheduler as a post-RA
198// scheduler. Targets can "properly" enable this with
199// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
200// Targets can return true in targetSchedulesPostRAScheduling() and
201// insert a PostRA scheduling pass wherever it wants.
202static cl::opt<bool> MISchedPostRA(
203 "misched-postra", cl::Hidden,
204 cl::desc(
205 "Run MachineScheduler post regalloc (independent of preRA sched)"));
206
207// Experimental option to run live interval analysis early.
208static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
209 cl::desc("Run live interval analysis earlier in the pipeline"));
210
211static cl::opt<bool> DisableReplaceWithVecLib(
212 "disable-replace-with-vec-lib", cl::Hidden,
213 cl::desc("Disable replace with vector math call pass"));
214
215/// Option names for limiting the codegen pipeline.
216/// Those are used in error reporting and we didn't want
217/// to duplicate their names all over the place.
218static const char StartAfterOptName[] = "start-after";
219static const char StartBeforeOptName[] = "start-before";
220static const char StopAfterOptName[] = "stop-after";
221static const char StopBeforeOptName[] = "stop-before";
222
223static cl::opt<std::string>
224 StartAfterOpt(StringRef(StartAfterOptName),
225 cl::desc("Resume compilation after a specific pass"),
226 cl::value_desc("pass-name"), cl::init(Val: ""), cl::Hidden);
227
228static cl::opt<std::string>
229 StartBeforeOpt(StringRef(StartBeforeOptName),
230 cl::desc("Resume compilation before a specific pass"),
231 cl::value_desc("pass-name"), cl::init(Val: ""), cl::Hidden);
232
233static cl::opt<std::string>
234 StopAfterOpt(StringRef(StopAfterOptName),
235 cl::desc("Stop compilation after a specific pass"),
236 cl::value_desc("pass-name"), cl::init(Val: ""), cl::Hidden);
237
238static cl::opt<std::string>
239 StopBeforeOpt(StringRef(StopBeforeOptName),
240 cl::desc("Stop compilation before a specific pass"),
241 cl::value_desc("pass-name"), cl::init(Val: ""), cl::Hidden);
242
243/// Enable the machine function splitter pass.
244static cl::opt<bool> EnableMachineFunctionSplitter(
245 "enable-split-machine-functions", cl::Hidden,
246 cl::desc("Split out cold blocks from machine functions based on profile "
247 "information."));
248
249/// Disable the expand reductions pass for testing.
250static cl::opt<bool> DisableExpandReductions(
251 "disable-expand-reductions", cl::init(Val: false), cl::Hidden,
252 cl::desc("Disable the expand reduction intrinsics pass from running"));
253
254/// Disable the select optimization pass.
255static cl::opt<bool> DisableSelectOptimize(
256 "disable-select-optimize", cl::init(Val: true), cl::Hidden,
257 cl::desc("Disable the select-optimization pass from running"));
258
259/// Enable garbage-collecting empty basic blocks.
260static cl::opt<bool>
261 GCEmptyBlocks("gc-empty-basic-blocks", cl::init(Val: false), cl::Hidden,
262 cl::desc("Enable garbage-collecting empty basic blocks"));
263
264static cl::opt<bool>
265 SplitStaticData("split-static-data", cl::Hidden, cl::init(Val: false),
266 cl::desc("Split static data sections into hot and cold "
267 "sections using profile information"));
268
269/// Allow standard passes to be disabled by command line options. This supports
270/// simple binary flags that either suppress the pass or do nothing.
271/// i.e. -disable-mypass=false has no effect.
272/// These should be converted to boolOrDefault in order to use applyOverride.
273static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
274 bool Override) {
275 if (Override)
276 return IdentifyingPassPtr();
277 return PassID;
278}
279
280/// Allow standard passes to be disabled by the command line, regardless of who
281/// is adding the pass.
282///
283/// StandardID is the pass identified in the standard pass pipeline and provided
284/// to addPass(). It may be a target-specific ID in the case that the target
285/// directly adds its own pass, but in that case we harmlessly fall through.
286///
287/// TargetID is the pass that the target has configured to override StandardID.
288///
289/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
290/// pass to run. This allows multiple options to control a single pass depending
291/// on where in the pipeline that pass is added.
292static IdentifyingPassPtr overridePass(AnalysisID StandardID,
293 IdentifyingPassPtr TargetID) {
294 if (StandardID == &PostRASchedulerID)
295 return applyDisable(PassID: TargetID, Override: DisablePostRASched);
296
297 if (StandardID == &BranchFolderPassID)
298 return applyDisable(PassID: TargetID, Override: DisableBranchFold);
299
300 if (StandardID == &TailDuplicateLegacyID)
301 return applyDisable(PassID: TargetID, Override: DisableTailDuplicate);
302
303 if (StandardID == &EarlyTailDuplicateLegacyID)
304 return applyDisable(PassID: TargetID, Override: DisableEarlyTailDup);
305
306 if (StandardID == &MachineBlockPlacementID)
307 return applyDisable(PassID: TargetID, Override: DisableBlockPlacement);
308
309 if (StandardID == &StackSlotColoringID)
310 return applyDisable(PassID: TargetID, Override: DisableSSC);
311
312 if (StandardID == &DeadMachineInstructionElimID)
313 return applyDisable(PassID: TargetID, Override: DisableMachineDCE);
314
315 if (StandardID == &EarlyIfConverterLegacyID)
316 return applyDisable(PassID: TargetID, Override: DisableEarlyIfConversion);
317
318 if (StandardID == &EarlyMachineLICMID)
319 return applyDisable(PassID: TargetID, Override: DisableMachineLICM);
320
321 if (StandardID == &MachineCSELegacyID)
322 return applyDisable(PassID: TargetID, Override: DisableMachineCSE);
323
324 if (StandardID == &MachineLICMID)
325 return applyDisable(PassID: TargetID, Override: DisablePostRAMachineLICM);
326
327 if (StandardID == &MachineSinkingLegacyID)
328 return applyDisable(PassID: TargetID, Override: DisableMachineSink);
329
330 if (StandardID == &PostRAMachineSinkingID)
331 return applyDisable(PassID: TargetID, Override: DisablePostRAMachineSink);
332
333 if (StandardID == &MachineCopyPropagationID)
334 return applyDisable(PassID: TargetID, Override: DisableCopyProp);
335
336 return TargetID;
337}
338
339// Find the FSProfile file name. The internal option takes the precedence
340// before getting from TargetMachine.
341static std::string getFSProfileFile(const TargetMachine *TM) {
342 if (!FSProfileFile.empty())
343 return FSProfileFile.getValue();
344 const std::optional<PGOOptions> &PGOOpt = TM->getPGOOption();
345 if (PGOOpt == std::nullopt || PGOOpt->Action != PGOOptions::SampleUse)
346 return std::string();
347 return PGOOpt->ProfileFile;
348}
349
350// Find the Profile remapping file name. The internal option takes the
351// precedence before getting from TargetMachine.
352static std::string getFSRemappingFile(const TargetMachine *TM) {
353 if (!FSRemappingFile.empty())
354 return FSRemappingFile.getValue();
355 const std::optional<PGOOptions> &PGOOpt = TM->getPGOOption();
356 if (PGOOpt == std::nullopt || PGOOpt->Action != PGOOptions::SampleUse)
357 return std::string();
358 return PGOOpt->ProfileRemappingFile;
359}
360
361//===---------------------------------------------------------------------===//
362/// TargetPassConfig
363//===---------------------------------------------------------------------===//
364
365INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
366 "Target Pass Configuration", false, false)
367char TargetPassConfig::ID = 0;
368
369namespace {
370
371struct InsertedPass {
372 AnalysisID TargetPassID;
373 IdentifyingPassPtr InsertedPassID;
374
375 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
376 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID) {}
377
378 Pass *getInsertedPass() const {
379 assert(InsertedPassID.isValid() && "Illegal Pass ID!");
380 if (InsertedPassID.isInstance())
381 return InsertedPassID.getInstance();
382 Pass *NP = Pass::createPass(ID: InsertedPassID.getID());
383 assert(NP && "Pass ID not registered");
384 return NP;
385 }
386};
387
388} // end anonymous namespace
389
390namespace llvm {
391
392extern cl::opt<bool> EnableFSDiscriminator;
393
394class PassConfigImpl {
395public:
396 // List of passes explicitly substituted by this target. Normally this is
397 // empty, but it is a convenient way to suppress or replace specific passes
398 // that are part of a standard pass pipeline without overridding the entire
399 // pipeline. This mechanism allows target options to inherit a standard pass's
400 // user interface. For example, a target may disable a standard pass by
401 // default by substituting a pass ID of zero, and the user may still enable
402 // that standard pass with an explicit command line option.
403 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
404
405 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
406 /// is inserted after each instance of the first one.
407 SmallVector<InsertedPass, 4> InsertedPasses;
408};
409
410} // end namespace llvm
411
412// Out of line virtual method.
413TargetPassConfig::~TargetPassConfig() {
414 delete Impl;
415}
416
417static const PassInfo *getPassInfo(StringRef PassName) {
418 if (PassName.empty())
419 return nullptr;
420
421 const PassRegistry &PR = *PassRegistry::getPassRegistry();
422 const PassInfo *PI = PR.getPassInfo(Arg: PassName);
423 if (!PI)
424 reportFatalUsageError(reason: Twine('\"') + Twine(PassName) +
425 Twine("\" pass is not registered."));
426 return PI;
427}
428
429static AnalysisID getPassIDFromName(StringRef PassName) {
430 const PassInfo *PI = getPassInfo(PassName);
431 return PI ? PI->getTypeInfo() : nullptr;
432}
433
434static std::pair<StringRef, unsigned>
435getPassNameAndInstanceNum(StringRef PassName) {
436 StringRef Name, InstanceNumStr;
437 std::tie(args&: Name, args&: InstanceNumStr) = PassName.split(Separator: ',');
438
439 unsigned InstanceNum = 0;
440 if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(Radix: 10, Result&: InstanceNum))
441 reportFatalUsageError(reason: "invalid pass instance specifier " + PassName);
442
443 return std::make_pair(x&: Name, y&: InstanceNum);
444}
445
446void TargetPassConfig::setStartStopPasses() {
447 StringRef StartBeforeName;
448 std::tie(args&: StartBeforeName, args&: StartBeforeInstanceNum) =
449 getPassNameAndInstanceNum(PassName: StartBeforeOpt);
450
451 StringRef StartAfterName;
452 std::tie(args&: StartAfterName, args&: StartAfterInstanceNum) =
453 getPassNameAndInstanceNum(PassName: StartAfterOpt);
454
455 StringRef StopBeforeName;
456 std::tie(args&: StopBeforeName, args&: StopBeforeInstanceNum)
457 = getPassNameAndInstanceNum(PassName: StopBeforeOpt);
458
459 StringRef StopAfterName;
460 std::tie(args&: StopAfterName, args&: StopAfterInstanceNum)
461 = getPassNameAndInstanceNum(PassName: StopAfterOpt);
462
463 StartBefore = getPassIDFromName(PassName: StartBeforeName);
464 StartAfter = getPassIDFromName(PassName: StartAfterName);
465 StopBefore = getPassIDFromName(PassName: StopBeforeName);
466 StopAfter = getPassIDFromName(PassName: StopAfterName);
467 if (StartBefore && StartAfter)
468 reportFatalUsageError(reason: Twine(StartBeforeOptName) + Twine(" and ") +
469 Twine(StartAfterOptName) + Twine(" specified!"));
470 if (StopBefore && StopAfter)
471 reportFatalUsageError(reason: Twine(StopBeforeOptName) + Twine(" and ") +
472 Twine(StopAfterOptName) + Twine(" specified!"));
473 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
474}
475
476CGPassBuilderOption llvm::getCGPassBuilderOption() {
477 CGPassBuilderOption Opt;
478
479#define SET_OPTION(Option) \
480 if (Option.getNumOccurrences()) \
481 Opt.Option = Option;
482
483 SET_OPTION(EnableFastISelOption)
484 SET_OPTION(EnableGlobalISelAbort)
485 SET_OPTION(EnableGlobalISelOption)
486 SET_OPTION(EnableIPRA)
487 SET_OPTION(OptimizeRegAlloc)
488 SET_OPTION(VerifyMachineCode)
489 SET_OPTION(DisableAtExitBasedGlobalDtorLowering)
490 SET_OPTION(DisableExpandReductions)
491 SET_OPTION(PrintAfterISel)
492 SET_OPTION(FSProfileFile)
493 SET_OPTION(GCEmptyBlocks)
494
495#define SET_BOOLEAN_OPTION(Option) Opt.Option = Option;
496
497 SET_BOOLEAN_OPTION(EarlyLiveIntervals)
498 SET_BOOLEAN_OPTION(EnableBlockPlacementStats)
499 SET_BOOLEAN_OPTION(EnableGlobalMergeFunc)
500 SET_BOOLEAN_OPTION(EnableImplicitNullChecks)
501 SET_BOOLEAN_OPTION(EnableMachineOutliner)
502 SET_BOOLEAN_OPTION(MISchedPostRA)
503 SET_BOOLEAN_OPTION(DisableMergeICmps)
504 SET_BOOLEAN_OPTION(DisableLSR)
505 SET_BOOLEAN_OPTION(DisableConstantHoisting)
506 SET_BOOLEAN_OPTION(DisableCGP)
507 SET_BOOLEAN_OPTION(DisablePartialLibcallInlining)
508 SET_BOOLEAN_OPTION(DisableSelectOptimize)
509 SET_BOOLEAN_OPTION(PrintISelInput)
510 SET_BOOLEAN_OPTION(DebugifyAndStripAll)
511 SET_BOOLEAN_OPTION(DebugifyCheckAndStripAll)
512 SET_BOOLEAN_OPTION(DisableRAFSProfileLoader)
513 SET_BOOLEAN_OPTION(DisableCFIFixup)
514 SET_BOOLEAN_OPTION(EnableMachineFunctionSplitter)
515
516 return Opt;
517}
518
519void llvm::registerCodeGenCallback(PassInstrumentationCallbacks &PIC,
520 TargetMachine &TM) {
521
522 // Register a callback for disabling passes.
523 PIC.registerShouldRunOptionalPassCallback(C: [](StringRef P, Any) {
524
525#define DISABLE_PASS(Option, Name) \
526 if (Option && P.contains(#Name)) \
527 return false;
528 DISABLE_PASS(DisableBlockPlacement, MachineBlockPlacementPass)
529 DISABLE_PASS(DisableBranchFold, BranchFolderPass)
530 DISABLE_PASS(DisableCopyProp, MachineCopyPropagationPass)
531 DISABLE_PASS(DisableEarlyIfConversion, EarlyIfConverterLegacyPass)
532 DISABLE_PASS(DisableEarlyTailDup, EarlyTailDuplicatePass)
533 DISABLE_PASS(DisableMachineCSE, MachineCSELegacyPass)
534 DISABLE_PASS(DisableMachineDCE, DeadMachineInstructionElimPass)
535 DISABLE_PASS(DisableMachineLICM, EarlyMachineLICMPass)
536 DISABLE_PASS(DisableMachineSink, MachineSinkingPass)
537 DISABLE_PASS(DisablePostRAMachineLICM, MachineLICMPass)
538 DISABLE_PASS(DisablePostRAMachineSink, PostRAMachineSinkingPass)
539 DISABLE_PASS(DisablePostRASched, PostRASchedulerPass)
540 DISABLE_PASS(DisableSSC, StackSlotColoringPass)
541 DISABLE_PASS(DisableTailDuplicate, TailDuplicatePass)
542
543 return true;
544 });
545}
546
547Expected<TargetPassConfig::StartStopInfo>
548TargetPassConfig::getStartStopInfo(PassInstrumentationCallbacks &PIC) {
549 auto [StartBefore, StartBeforeInstanceNum] =
550 getPassNameAndInstanceNum(PassName: StartBeforeOpt);
551 auto [StartAfter, StartAfterInstanceNum] =
552 getPassNameAndInstanceNum(PassName: StartAfterOpt);
553 auto [StopBefore, StopBeforeInstanceNum] =
554 getPassNameAndInstanceNum(PassName: StopBeforeOpt);
555 auto [StopAfter, StopAfterInstanceNum] =
556 getPassNameAndInstanceNum(PassName: StopAfterOpt);
557
558 if (!StartBefore.empty() && !StartAfter.empty())
559 return make_error<StringError>(
560 Args: Twine(StartBeforeOptName) + " and " + StartAfterOptName + " specified!",
561 Args: std::make_error_code(e: std::errc::invalid_argument));
562 if (!StopBefore.empty() && !StopAfter.empty())
563 return make_error<StringError>(
564 Args: Twine(StopBeforeOptName) + " and " + StopAfterOptName + " specified!",
565 Args: std::make_error_code(e: std::errc::invalid_argument));
566
567 StartStopInfo Result;
568 Result.StartPass = StartBefore.empty() ? StartAfter : StartBefore;
569 Result.StopPass = StopBefore.empty() ? StopAfter : StopBefore;
570 Result.StartInstanceNum =
571 StartBefore.empty() ? StartAfterInstanceNum : StartBeforeInstanceNum;
572 Result.StopInstanceNum =
573 StopBefore.empty() ? StopAfterInstanceNum : StopBeforeInstanceNum;
574 Result.StartAfter = !StartAfter.empty();
575 Result.StopAfter = !StopAfter.empty();
576 Result.StartInstanceNum += Result.StartInstanceNum == 0;
577 Result.StopInstanceNum += Result.StopInstanceNum == 0;
578 return Result;
579}
580
581// Out of line constructor provides default values for pass options and
582// registers all common codegen passes.
583TargetPassConfig::TargetPassConfig(TargetMachine &TM, PassManagerBase &PM)
584 : ImmutablePass(ID), PM(&PM), TM(&TM) {
585 Impl = new PassConfigImpl();
586
587 PassRegistry &PR = *PassRegistry::getPassRegistry();
588 // Register all target independent codegen passes to activate their PassIDs,
589 // including this pass itself.
590 initializeCodeGen(PR);
591
592 // Also register alias analysis passes required by codegen passes.
593 initializeBasicAAWrapperPassPass(PR);
594 initializeAAResultsWrapperPassPass(PR);
595
596 if (EnableIPRA.getNumOccurrences()) {
597 TM.Options.EnableIPRA = EnableIPRA;
598 } else {
599 // If not explicitly specified, use target default.
600 TM.Options.EnableIPRA |= TM.useIPRA();
601 }
602
603 if (TM.Options.EnableIPRA)
604 setRequiresCodeGenSCCOrder();
605
606 if (EnableGlobalISelAbort.getNumOccurrences())
607 TM.Options.GlobalISelAbort = EnableGlobalISelAbort;
608
609 setStartStopPasses();
610}
611
612CodeGenOptLevel TargetPassConfig::getOptLevel() const {
613 return TM->getOptLevel();
614}
615
616/// Insert InsertedPassID pass after TargetPassID.
617void TargetPassConfig::insertPass(AnalysisID TargetPassID,
618 IdentifyingPassPtr InsertedPassID) {
619 assert(((!InsertedPassID.isInstance() &&
620 TargetPassID != InsertedPassID.getID()) ||
621 (InsertedPassID.isInstance() &&
622 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
623 "Insert a pass after itself!");
624 Impl->InsertedPasses.emplace_back(Args&: TargetPassID, Args&: InsertedPassID);
625}
626
627/// createPassConfig - Create a pass configuration object to be used by
628/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
629///
630/// Targets may override this to extend TargetPassConfig.
631TargetPassConfig *
632CodeGenTargetMachineImpl::createPassConfig(PassManagerBase &PM) {
633 return new TargetPassConfig(*this, PM);
634}
635
636TargetPassConfig::TargetPassConfig()
637 : ImmutablePass(ID) {
638 reportFatalUsageError(reason: "trying to construct TargetPassConfig without a target "
639 "machine. Scheduling a CodeGen pass without a target "
640 "triple set?");
641}
642
643bool TargetPassConfig::willCompleteCodeGenPipeline() {
644 return StopBeforeOpt.empty() && StopAfterOpt.empty();
645}
646
647bool TargetPassConfig::hasLimitedCodeGenPipeline() {
648 return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
649 !willCompleteCodeGenPipeline();
650}
651
652std::string TargetPassConfig::getLimitedCodeGenPipelineReason() {
653 if (!hasLimitedCodeGenPipeline())
654 return std::string();
655 std::string Res;
656 static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
657 &StopAfterOpt, &StopBeforeOpt};
658 static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
659 StopAfterOptName, StopBeforeOptName};
660 bool IsFirst = true;
661 for (int Idx = 0; Idx < 4; ++Idx)
662 if (!PassNames[Idx]->empty()) {
663 if (!IsFirst)
664 Res += " and ";
665 IsFirst = false;
666 Res += OptNames[Idx];
667 }
668 return Res;
669}
670
671// Helper to verify the analysis is really immutable.
672void TargetPassConfig::setOpt(bool &Opt, bool Val) {
673 assert(!Initialized && "PassConfig is immutable");
674 Opt = Val;
675}
676
677void TargetPassConfig::substitutePass(AnalysisID StandardID,
678 IdentifyingPassPtr TargetID) {
679 Impl->TargetPasses[StandardID] = TargetID;
680}
681
682IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
683 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
684 I = Impl->TargetPasses.find(Val: ID);
685 if (I == Impl->TargetPasses.end())
686 return ID;
687 return I->second;
688}
689
690bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
691 IdentifyingPassPtr TargetID = getPassSubstitution(ID);
692 IdentifyingPassPtr FinalPtr = overridePass(StandardID: ID, TargetID);
693 return !FinalPtr.isValid() || FinalPtr.isInstance() ||
694 FinalPtr.getID() != ID;
695}
696
697/// Add a pass to the PassManager if that pass is supposed to be run. If the
698/// Started/Stopped flags indicate either that the compilation should start at
699/// a later pass or that it should stop after an earlier pass, then do not add
700/// the pass. Finally, compare the current pass against the StartAfter
701/// and StopAfter options and change the Started/Stopped flags accordingly.
702void TargetPassConfig::addPass(Pass *P) {
703 assert(!Initialized && "PassConfig is immutable");
704
705 // Cache the Pass ID here in case the pass manager finds this pass is
706 // redundant with ones already scheduled / available, and deletes it.
707 // Fundamentally, once we add the pass to the manager, we no longer own it
708 // and shouldn't reference it.
709 AnalysisID PassID = P->getPassID();
710
711 if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
712 Started = true;
713 if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
714 Stopped = true;
715 if (Started && !Stopped) {
716 if (AddingMachinePasses) {
717 // Construct banner message before PM->add() as that may delete the pass.
718 std::string Banner =
719 std::string("After ") + std::string(P->getPassName());
720 addMachinePrePasses();
721 PM->add(P);
722 addMachinePostPasses(Banner);
723 } else {
724 PM->add(P);
725 }
726
727 // Add the passes after the pass P if there is any.
728 for (const auto &IP : Impl->InsertedPasses)
729 if (IP.TargetPassID == PassID)
730 addPass(P: IP.getInsertedPass());
731 } else {
732 delete P;
733 }
734
735 if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
736 Stopped = true;
737
738 if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
739 Started = true;
740 if (Stopped && !Started)
741 reportFatalUsageError(reason: "Cannot stop compilation after pass that is not run");
742}
743
744/// Add a CodeGen pass at this point in the pipeline after checking for target
745/// and command line overrides.
746///
747/// addPass cannot return a pointer to the pass instance because is internal the
748/// PassManager and the instance we create here may already be freed.
749AnalysisID TargetPassConfig::addPass(AnalysisID PassID) {
750 IdentifyingPassPtr TargetID = getPassSubstitution(ID: PassID);
751 IdentifyingPassPtr FinalPtr = overridePass(StandardID: PassID, TargetID);
752 if (!FinalPtr.isValid())
753 return nullptr;
754
755 Pass *P;
756 if (FinalPtr.isInstance())
757 P = FinalPtr.getInstance();
758 else {
759 P = Pass::createPass(ID: FinalPtr.getID());
760 if (!P)
761 llvm_unreachable("Pass ID not registered");
762 }
763 AnalysisID FinalID = P->getPassID();
764 addPass(P); // Ends the lifetime of P.
765
766 return FinalID;
767}
768
769void TargetPassConfig::printAndVerify(const std::string &Banner) {
770 addPrintPass(Banner);
771 addVerifyPass(Banner);
772}
773
774void TargetPassConfig::addPrintPass(const std::string &Banner) {
775 if (PrintAfterISel)
776 PM->add(P: createMachineFunctionPrinterPass(OS&: dbgs(), Banner));
777}
778
779void TargetPassConfig::addVerifyPass(const std::string &Banner) {
780 bool Verify = VerifyMachineCode == cl::BOU_TRUE;
781#ifdef EXPENSIVE_CHECKS
782 if (VerifyMachineCode == cl::BOU_UNSET)
783 Verify = TM->isMachineVerifierClean();
784#endif
785 if (Verify)
786 PM->add(P: createMachineVerifierPass(Banner));
787}
788
789void TargetPassConfig::addDebugifyPass() {
790 PM->add(P: createDebugifyMachineModulePass());
791}
792
793void TargetPassConfig::addStripDebugPass() {
794 PM->add(P: createStripDebugMachineModulePass(/*OnlyDebugified=*/true));
795}
796
797void TargetPassConfig::addCheckDebugPass() {
798 PM->add(P: createCheckDebugMachineModulePass());
799}
800
801void TargetPassConfig::addMachinePrePasses(bool AllowDebugify) {
802 if (AllowDebugify && DebugifyIsSafe &&
803 (DebugifyAndStripAll == cl::BOU_TRUE ||
804 DebugifyCheckAndStripAll == cl::BOU_TRUE))
805 addDebugifyPass();
806}
807
808void TargetPassConfig::addMachinePostPasses(const std::string &Banner) {
809 if (DebugifyIsSafe) {
810 if (DebugifyCheckAndStripAll == cl::BOU_TRUE) {
811 addCheckDebugPass();
812 addStripDebugPass();
813 } else if (DebugifyAndStripAll == cl::BOU_TRUE)
814 addStripDebugPass();
815 }
816 addVerifyPass(Banner);
817}
818
819/// Add common target configurable passes that perform LLVM IR to IR transforms
820/// following machine independent optimization.
821void TargetPassConfig::addIRPasses() {
822 // Before running any passes, run the verifier to determine if the input
823 // coming from the front-end and/or optimizer is valid.
824 if (!DisableVerify)
825 addPass(P: createVerifierPass());
826
827 if (getOptLevel() != CodeGenOptLevel::None) {
828 // Basic AliasAnalysis support.
829 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
830 // BasicAliasAnalysis wins if they disagree. This is intended to help
831 // support "obvious" type-punning idioms.
832 addPass(P: createTypeBasedAAWrapperPass());
833 addPass(P: createScopedNoAliasAAWrapperPass());
834 addPass(P: createBasicAAWrapperPass());
835
836 // Run loop strength reduction before anything else.
837 if (!DisableLSR) {
838 addPass(P: createCanonicalizeFreezeInLoopsPass());
839 addPass(P: createLoopStrengthReducePass());
840 if (EnableLoopTermFold)
841 addPass(P: createLoopTermFoldPass());
842 }
843
844 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
845 // loads and compares. ExpandMemCmpPass then tries to expand those calls
846 // into optimally-sized loads and compares. The transforms are enabled by a
847 // target lowering hook.
848 if (!DisableMergeICmps)
849 addPass(P: createMergeICmpsLegacyPass());
850 addPass(P: createExpandMemCmpLegacyPass());
851 }
852
853 // Run GC lowering passes for builtin collectors
854 // TODO: add a pass insertion point here
855 addPass(PassID: &GCLoweringID);
856 addPass(PassID: &ShadowStackGCLoweringID);
857
858 // For MachO, lower @llvm.global_dtors into @llvm.global_ctors with
859 // __cxa_atexit() calls to avoid emitting the deprecated __mod_term_func.
860 if (TM->getTargetTriple().isOSBinFormatMachO() &&
861 !DisableAtExitBasedGlobalDtorLowering)
862 addPass(P: createLowerGlobalDtorsLegacyPass());
863
864 // Make sure that no unreachable blocks are instruction selected.
865 addPass(P: createUnreachableBlockEliminationPass());
866
867 // Prepare expensive constants for SelectionDAG.
868 if (getOptLevel() != CodeGenOptLevel::None && !DisableConstantHoisting)
869 addPass(P: createConstantHoistingPass());
870
871 if (getOptLevel() != CodeGenOptLevel::None && !DisableReplaceWithVecLib)
872 addPass(P: createReplaceWithVeclibLegacyPass());
873
874 if (getOptLevel() != CodeGenOptLevel::None && !DisablePartialLibcallInlining)
875 addPass(P: createPartiallyInlineLibCallsPass());
876
877 // Instrument function entry after all inlining.
878 addPass(P: createPostInlineEntryExitInstrumenterPass());
879
880 // Add scalarization of target's unsupported masked memory intrinsics pass.
881 // the unsupported intrinsic will be replaced with a chain of basic blocks,
882 // that stores/loads element one-by-one if the appropriate mask bit is set.
883 addPass(P: createScalarizeMaskedMemIntrinLegacyPass());
884
885 // Expand reduction intrinsics into shuffle sequences if the target wants to.
886 // Allow disabling it for testing purposes.
887 if (!DisableExpandReductions)
888 addPass(P: createExpandReductionsPass());
889
890 // Convert conditional moves to conditional jumps when profitable.
891 if (getOptLevel() != CodeGenOptLevel::None && !DisableSelectOptimize)
892 addPass(P: createSelectOptimizePass());
893
894 if (EnableGlobalMergeFunc)
895 addPass(P: createGlobalMergeFuncPass());
896
897 if (TM->getTargetTriple().isOSWindows())
898 addPass(P: createWindowsSecureHotPatchingPass());
899}
900
901/// Turn exception handling constructs into something the code generators can
902/// handle.
903void TargetPassConfig::addPassesToHandleExceptions() {
904 const MCAsmInfo *MCAI = TM->getMCAsmInfo();
905 assert(MCAI && "No MCAsmInfo");
906 switch (MCAI->getExceptionHandlingType()) {
907 case ExceptionHandling::SjLj:
908 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
909 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
910 // catch info can get misplaced when a selector ends up more than one block
911 // removed from the parent invoke(s). This could happen when a landing
912 // pad is shared by multiple invokes and is also a target of a normal
913 // edge from elsewhere.
914 addPass(P: createSjLjEHPreparePass(TM));
915 [[fallthrough]];
916 case ExceptionHandling::DwarfCFI:
917 case ExceptionHandling::ARM:
918 case ExceptionHandling::AIX:
919 case ExceptionHandling::ZOS:
920 addPass(P: createDwarfEHPass(OptLevel: getOptLevel()));
921 break;
922 case ExceptionHandling::WinEH:
923 // We support using both GCC-style and MSVC-style exceptions on Windows, so
924 // add both preparation passes. Each pass will only actually run if it
925 // recognizes the personality function.
926 addPass(P: createWinEHPass());
927 addPass(P: createDwarfEHPass(OptLevel: getOptLevel()));
928 break;
929 case ExceptionHandling::Wasm:
930 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
931 // on catchpads and cleanuppads because it does not outline them into
932 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
933 // should remove PHIs there.
934 addPass(P: createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/true));
935 addPass(P: createWasmEHPass());
936 break;
937 case ExceptionHandling::None:
938 addPass(P: createLowerInvokePass());
939
940 // The lower invoke pass may create unreachable code. Remove it.
941 addPass(P: createUnreachableBlockEliminationPass());
942 break;
943 }
944}
945
946/// Add pass to prepare the LLVM IR for code generation. This should be done
947/// before exception handling preparation passes.
948void TargetPassConfig::addCodeGenPrepare() {
949 if (getOptLevel() != CodeGenOptLevel::None && !DisableCGP)
950 addPass(P: createCodeGenPrepareLegacyPass());
951}
952
953/// Add common passes that perform LLVM IR to IR transforms in preparation for
954/// instruction selection.
955void TargetPassConfig::addISelPrepare() {
956 addPreISel();
957
958 // Force codegen to run according to the callgraph.
959 if (requiresCodeGenSCCOrder())
960 addPass(P: new DummyCGSCCPass);
961
962 if (getOptLevel() != CodeGenOptLevel::None)
963 addPass(P: createObjCARCContractPass());
964
965 addPass(P: createCallBrPass());
966
967 // Add both the safe stack and the stack protection passes: each of them will
968 // only protect functions that have corresponding attributes.
969 addPass(P: createSafeStackPass());
970 addPass(P: createStackProtectorPass());
971
972 if (PrintISelInput)
973 addPass(P: createPrintFunctionPass(
974 OS&: dbgs(), Banner: "\n\n*** Final LLVM Code input to ISel ***\n"));
975
976 // All passes which modify the LLVM IR are now complete; run the verifier
977 // to ensure that the IR is valid.
978 if (!DisableVerify)
979 addPass(P: createVerifierPass());
980}
981
982bool TargetPassConfig::addCoreISelPasses() {
983 // Enable FastISel with -fast-isel, but allow that to be overridden.
984 TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
985
986 // Determine an instruction selector.
987 enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
988 SelectorType Selector;
989
990 if (EnableFastISelOption == cl::BOU_TRUE)
991 Selector = SelectorType::FastISel;
992 else if (EnableGlobalISelOption == cl::BOU_TRUE ||
993 (TM->Options.EnableGlobalISel &&
994 EnableGlobalISelOption != cl::BOU_FALSE))
995 Selector = SelectorType::GlobalISel;
996 else if (TM->getOptLevel() == CodeGenOptLevel::None &&
997 TM->getO0WantsFastISel())
998 Selector = SelectorType::FastISel;
999 else
1000 Selector = SelectorType::SelectionDAG;
1001
1002 // Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
1003 if (Selector == SelectorType::FastISel) {
1004 TM->setFastISel(true);
1005 TM->setGlobalISel(false);
1006 } else if (Selector == SelectorType::GlobalISel) {
1007 TM->setFastISel(false);
1008 TM->setGlobalISel(true);
1009 }
1010
1011 // FIXME: Injecting into the DAGISel pipeline seems to cause issues with
1012 // analyses needing to be re-run. This can result in being unable to
1013 // schedule passes (particularly with 'Function Alias Analysis
1014 // Results'). It's not entirely clear why but AFAICT this seems to be
1015 // due to one FunctionPassManager not being able to use analyses from a
1016 // previous one. As we're injecting a ModulePass we break the usual
1017 // pass manager into two. GlobalISel with the fallback path disabled
1018 // and -run-pass seem to be unaffected. The majority of GlobalISel
1019 // testing uses -run-pass so this probably isn't too bad.
1020 SaveAndRestore SavedDebugifyIsSafe(DebugifyIsSafe);
1021 if (Selector != SelectorType::GlobalISel || !isGlobalISelAbortEnabled())
1022 DebugifyIsSafe = false;
1023
1024 // Add instruction selector passes for global isel if enabled.
1025 if (Selector == SelectorType::GlobalISel) {
1026 SaveAndRestore SavedAddingMachinePasses(AddingMachinePasses, true);
1027 if (addIRTranslator())
1028 return true;
1029
1030 addPreLegalizeMachineIR();
1031
1032 if (addLegalizeMachineIR())
1033 return true;
1034
1035 // Before running the register bank selector, ask the target if it
1036 // wants to run some passes.
1037 addPreRegBankSelect();
1038
1039 if (addRegBankSelect())
1040 return true;
1041
1042 addPreGlobalInstructionSelect();
1043
1044 if (addGlobalInstructionSelect())
1045 return true;
1046 }
1047
1048 // Pass to reset the MachineFunction if the ISel failed. Outside of the above
1049 // if so that the verifier is not added to it.
1050 if (Selector == SelectorType::GlobalISel)
1051 addPass(P: createResetMachineFunctionPass(
1052 EmitFallbackDiag: reportDiagnosticWhenGlobalISelFallback(), AbortOnFailedISel: isGlobalISelAbortEnabled()));
1053
1054 // Run the SDAG InstSelector, providing a fallback path when we do not want to
1055 // abort on not-yet-supported input.
1056 if (Selector != SelectorType::GlobalISel || !isGlobalISelAbortEnabled())
1057 if (addInstSelector())
1058 return true;
1059
1060 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
1061 // FinalizeISel.
1062 addPass(PassID: &FinalizeISelID);
1063
1064 // Print the instruction selected machine code...
1065 printAndVerify(Banner: "After Instruction Selection");
1066
1067 return false;
1068}
1069
1070bool TargetPassConfig::addISelPasses() {
1071 if (TM->useEmulatedTLS())
1072 addPass(P: createLowerEmuTLSPass());
1073
1074 PM->add(P: createTargetTransformInfoWrapperPass(TIRA: TM->getTargetIRAnalysis()));
1075 addPass(P: createPreISelIntrinsicLoweringPass());
1076 addPass(P: createExpandLargeDivRemPass());
1077 addPass(P: createExpandFpPass());
1078 addIRPasses();
1079 addCodeGenPrepare();
1080 addPassesToHandleExceptions();
1081 addISelPrepare();
1082
1083 return addCoreISelPasses();
1084}
1085
1086/// -regalloc=... command line option.
1087static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
1088static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
1089 RegisterPassParser<RegisterRegAlloc>>
1090 RegAlloc("regalloc", cl::Hidden, cl::init(Val: &useDefaultRegisterAllocator),
1091 cl::desc("Register allocator to use"));
1092
1093/// Add the complete set of target-independent postISel code generator passes.
1094///
1095/// This can be read as the standard order of major LLVM CodeGen stages. Stages
1096/// with nontrivial configuration or multiple passes are broken out below in
1097/// add%Stage routines.
1098///
1099/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
1100/// addPre/Post methods with empty header implementations allow injecting
1101/// target-specific fixups just before or after major stages. Additionally,
1102/// targets have the flexibility to change pass order within a stage by
1103/// overriding default implementation of add%Stage routines below. Each
1104/// technique has maintainability tradeoffs because alternate pass orders are
1105/// not well supported. addPre/Post works better if the target pass is easily
1106/// tied to a common pass. But if it has subtle dependencies on multiple passes,
1107/// the target should override the stage instead.
1108///
1109/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
1110/// before/after any target-independent pass. But it's currently overkill.
1111void TargetPassConfig::addMachinePasses() {
1112 AddingMachinePasses = true;
1113
1114 // Add passes that optimize machine instructions in SSA form.
1115 if (getOptLevel() != CodeGenOptLevel::None) {
1116 addMachineSSAOptimization();
1117 } else {
1118 // If the target requests it, assign local variables to stack slots relative
1119 // to one another and simplify frame index references where possible.
1120 addPass(PassID: &LocalStackSlotAllocationID);
1121 }
1122
1123 if (TM->Options.EnableIPRA)
1124 addPass(P: createRegUsageInfoPropPass());
1125
1126 // Run pre-ra passes.
1127 addPreRegAlloc();
1128
1129 // Debugifying the register allocator passes seems to provoke some
1130 // non-determinism that affects CodeGen and there doesn't seem to be a point
1131 // where it becomes safe again so stop debugifying here.
1132 DebugifyIsSafe = false;
1133
1134 // Add a FSDiscriminator pass right before RA, so that we could get
1135 // more precise SampleFDO profile for RA.
1136 if (EnableFSDiscriminator) {
1137 addPass(P: createMIRAddFSDiscriminatorsPass(
1138 P: sampleprof::FSDiscriminatorPass::Pass1));
1139 const std::string ProfileFile = getFSProfileFile(TM);
1140 if (!ProfileFile.empty() && !DisableRAFSProfileLoader)
1141 addPass(P: createMIRProfileLoaderPass(File: ProfileFile, RemappingFile: getFSRemappingFile(TM),
1142 P: sampleprof::FSDiscriminatorPass::Pass1,
1143 FS: nullptr));
1144 }
1145
1146 // Run register allocation and passes that are tightly coupled with it,
1147 // including phi elimination and scheduling.
1148 if (getOptimizeRegAlloc())
1149 addOptimizedRegAlloc();
1150 else
1151 addFastRegAlloc();
1152
1153 // Run post-ra passes.
1154 addPostRegAlloc();
1155
1156 addPass(PassID: &RemoveRedundantDebugValuesID);
1157
1158 addPass(PassID: &FixupStatepointCallerSavedID);
1159
1160 // Insert prolog/epilog code. Eliminate abstract frame index references...
1161 if (getOptLevel() != CodeGenOptLevel::None) {
1162 addPass(PassID: &PostRAMachineSinkingID);
1163 addPass(PassID: &ShrinkWrapID);
1164 }
1165
1166 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
1167 // do so if it hasn't been disabled, substituted, or overridden.
1168 if (!isPassSubstitutedOrOverridden(ID: &PrologEpilogCodeInserterID))
1169 addPass(P: createPrologEpilogInserterPass());
1170
1171 /// Add passes that optimize machine instructions after register allocation.
1172 if (getOptLevel() != CodeGenOptLevel::None)
1173 addMachineLateOptimization();
1174
1175 // Expand pseudo instructions before second scheduling pass.
1176 addPass(PassID: &ExpandPostRAPseudosID);
1177
1178 // Run pre-sched2 passes.
1179 addPreSched2();
1180
1181 if (EnableImplicitNullChecks)
1182 addPass(PassID: &ImplicitNullChecksID);
1183
1184 // Second pass scheduler.
1185 // Let Target optionally insert this pass by itself at some other
1186 // point.
1187 if (getOptLevel() != CodeGenOptLevel::None &&
1188 !TM->targetSchedulesPostRAScheduling()) {
1189 if (MISchedPostRA)
1190 addPass(PassID: &PostMachineSchedulerID);
1191 else
1192 addPass(PassID: &PostRASchedulerID);
1193 }
1194
1195 // GC
1196 addGCPasses();
1197
1198 // Basic block placement.
1199 if (getOptLevel() != CodeGenOptLevel::None)
1200 addBlockPlacement();
1201
1202 // Insert before XRay Instrumentation.
1203 addPass(PassID: &FEntryInserterID);
1204
1205 addPass(PassID: &XRayInstrumentationID);
1206 addPass(PassID: &PatchableFunctionID);
1207
1208 addPreEmitPass();
1209
1210 if (TM->Options.EnableIPRA)
1211 // Collect register usage information and produce a register mask of
1212 // clobbered registers, to be used to optimize call sites.
1213 addPass(P: createRegUsageInfoCollector());
1214
1215 // FIXME: Some backends are incompatible with running the verifier after
1216 // addPreEmitPass. Maybe only pass "false" here for those targets?
1217 addPass(PassID: &FuncletLayoutID);
1218
1219 addPass(PassID: &RemoveLoadsIntoFakeUsesID);
1220 addPass(PassID: &StackMapLivenessID);
1221 addPass(PassID: &LiveDebugValuesID);
1222 addPass(PassID: &MachineSanitizerBinaryMetadataID);
1223
1224 if (TM->Options.EnableMachineOutliner &&
1225 getOptLevel() != CodeGenOptLevel::None &&
1226 EnableMachineOutliner != RunOutliner::NeverOutline) {
1227 bool RunOnAllFunctions =
1228 (EnableMachineOutliner == RunOutliner::AlwaysOutline);
1229 bool AddOutliner =
1230 RunOnAllFunctions || TM->Options.SupportsDefaultOutlining;
1231 if (AddOutliner)
1232 addPass(P: createMachineOutlinerPass(RunOnAllFunctions));
1233 }
1234
1235 if (GCEmptyBlocks)
1236 addPass(P: llvm::createGCEmptyBasicBlocksPass());
1237
1238 if (EnableFSDiscriminator)
1239 addPass(P: createMIRAddFSDiscriminatorsPass(
1240 P: sampleprof::FSDiscriminatorPass::PassLast));
1241
1242 if (TM->Options.EnableMachineFunctionSplitter ||
1243 EnableMachineFunctionSplitter || SplitStaticData ||
1244 TM->Options.EnableStaticDataPartitioning) {
1245 const std::string ProfileFile = getFSProfileFile(TM);
1246 if (!ProfileFile.empty()) {
1247 if (EnableFSDiscriminator) {
1248 addPass(P: createMIRProfileLoaderPass(
1249 File: ProfileFile, RemappingFile: getFSRemappingFile(TM),
1250 P: sampleprof::FSDiscriminatorPass::PassLast, FS: nullptr));
1251 } else {
1252 // Sample profile is given, but FSDiscriminator is not
1253 // enabled, this may result in performance regression.
1254 WithColor::warning()
1255 << "Using AutoFDO without FSDiscriminator for MFS may regress "
1256 "performance.\n";
1257 }
1258 }
1259 }
1260
1261 // Machine function splitter uses the basic block sections feature.
1262 // When used along with `-basic-block-sections=`, the basic-block-sections
1263 // feature takes precedence. This means functions eligible for
1264 // basic-block-sections optimizations (`=all`, or `=list=` with function
1265 // included in the list profile) will get that optimization instead.
1266 if (TM->Options.EnableMachineFunctionSplitter ||
1267 EnableMachineFunctionSplitter)
1268 addPass(P: createMachineFunctionSplitterPass());
1269
1270 if (SplitStaticData || TM->Options.EnableStaticDataPartitioning) {
1271 // The static data splitter pass is a machine function pass. and
1272 // static data annotator pass is a module-wide pass. See the file comment
1273 // in StaticDataAnnotator.cpp for the motivation.
1274 addPass(P: createStaticDataSplitterPass());
1275 addPass(P: createStaticDataAnnotatorPass());
1276 }
1277 // We run the BasicBlockSections pass if either we need BB sections or BB
1278 // address map (or both).
1279 if (TM->getBBSectionsType() != llvm::BasicBlockSection::None ||
1280 TM->Options.BBAddrMap) {
1281 if (TM->getBBSectionsType() == llvm::BasicBlockSection::List) {
1282 addPass(P: llvm::createBasicBlockSectionsProfileReaderWrapperPass(
1283 Buf: TM->getBBSectionsFuncListBuf()));
1284 addPass(P: llvm::createBasicBlockPathCloningPass());
1285 }
1286 addPass(P: llvm::createBasicBlockSectionsPass());
1287 }
1288
1289 addPostBBSections();
1290
1291 if (!DisableCFIFixup && TM->Options.EnableCFIFixup)
1292 addPass(P: createCFIFixup());
1293
1294 PM->add(P: createStackFrameLayoutAnalysisPass());
1295
1296 // Add passes that directly emit MI after all other MI passes.
1297 addPreEmitPass2();
1298
1299 AddingMachinePasses = false;
1300}
1301
1302/// Add passes that optimize machine instructions in SSA form.
1303void TargetPassConfig::addMachineSSAOptimization() {
1304 // Pre-ra tail duplication.
1305 addPass(PassID: &EarlyTailDuplicateLegacyID);
1306
1307 // Optimize PHIs before DCE: removing dead PHI cycles may make more
1308 // instructions dead.
1309 addPass(PassID: &OptimizePHIsLegacyID);
1310
1311 // This pass merges large allocas. StackSlotColoring is a different pass
1312 // which merges spill slots.
1313 addPass(PassID: &StackColoringLegacyID);
1314
1315 // If the target requests it, assign local variables to stack slots relative
1316 // to one another and simplify frame index references where possible.
1317 addPass(PassID: &LocalStackSlotAllocationID);
1318
1319 // With optimization, dead code should already be eliminated. However
1320 // there is one known exception: lowered code for arguments that are only
1321 // used by tail calls, where the tail calls reuse the incoming stack
1322 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1323 addPass(PassID: &DeadMachineInstructionElimID);
1324
1325 // Allow targets to insert passes that improve instruction level parallelism,
1326 // like if-conversion. Such passes will typically need dominator trees and
1327 // loop info, just like LICM and CSE below.
1328 addILPOpts();
1329
1330 addPass(PassID: &EarlyMachineLICMID);
1331 addPass(PassID: &MachineCSELegacyID);
1332
1333 addPass(PassID: &MachineSinkingLegacyID);
1334
1335 addPass(PassID: &PeepholeOptimizerLegacyID);
1336 // Clean-up the dead code that may have been generated by peephole
1337 // rewriting.
1338 addPass(PassID: &DeadMachineInstructionElimID);
1339}
1340
1341//===---------------------------------------------------------------------===//
1342/// Register Allocation Pass Configuration
1343//===---------------------------------------------------------------------===//
1344
1345bool TargetPassConfig::getOptimizeRegAlloc() const {
1346 switch (OptimizeRegAlloc) {
1347 case cl::BOU_UNSET:
1348 return getOptLevel() != CodeGenOptLevel::None;
1349 case cl::BOU_TRUE: return true;
1350 case cl::BOU_FALSE: return false;
1351 }
1352 llvm_unreachable("Invalid optimize-regalloc state");
1353}
1354
1355/// A dummy default pass factory indicates whether the register allocator is
1356/// overridden on the command line.
1357static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
1358
1359static RegisterRegAlloc
1360defaultRegAlloc("default",
1361 "pick register allocator based on -O option",
1362 useDefaultRegisterAllocator);
1363
1364static void initializeDefaultRegisterAllocatorOnce() {
1365 if (!RegisterRegAlloc::getDefault())
1366 RegisterRegAlloc::setDefault(RegAlloc);
1367}
1368
1369/// Instantiate the default register allocator pass for this target for either
1370/// the optimized or unoptimized allocation path. This will be added to the pass
1371/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1372/// in the optimized case.
1373///
1374/// A target that uses the standard regalloc pass order for fast or optimized
1375/// allocation may still override this for per-target regalloc
1376/// selection. But -regalloc=... always takes precedence.
1377FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
1378 if (Optimized)
1379 return createGreedyRegisterAllocator();
1380 else
1381 return createFastRegisterAllocator();
1382}
1383
1384/// Find and instantiate the register allocation pass requested by this target
1385/// at the current optimization level. Different register allocators are
1386/// defined as separate passes because they may require different analysis.
1387///
1388/// This helper ensures that the regalloc= option is always available,
1389/// even for targets that override the default allocator.
1390///
1391/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1392/// this can be folded into addPass.
1393FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
1394 // Initialize the global default.
1395 llvm::call_once(flag&: InitializeDefaultRegisterAllocatorFlag,
1396 F&: initializeDefaultRegisterAllocatorOnce);
1397
1398 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1399 if (Ctor != useDefaultRegisterAllocator)
1400 return Ctor();
1401
1402 // With no -regalloc= override, ask the target for a regalloc pass.
1403 return createTargetRegisterAllocator(Optimized);
1404}
1405
1406bool TargetPassConfig::isCustomizedRegAlloc() {
1407 return RegAlloc !=
1408 (RegisterRegAlloc::FunctionPassCtor)&useDefaultRegisterAllocator;
1409}
1410
1411bool TargetPassConfig::addRegAssignAndRewriteFast() {
1412 if (RegAlloc != (RegisterRegAlloc::FunctionPassCtor)&useDefaultRegisterAllocator &&
1413 RegAlloc != (RegisterRegAlloc::FunctionPassCtor)&createFastRegisterAllocator)
1414 reportFatalUsageError(
1415 reason: "Must use fast (default) register allocator for unoptimized regalloc.");
1416
1417 addPass(P: createRegAllocPass(Optimized: false));
1418
1419 // Allow targets to change the register assignments after
1420 // fast register allocation.
1421 addPostFastRegAllocRewrite();
1422 return true;
1423}
1424
1425bool TargetPassConfig::addRegAssignAndRewriteOptimized() {
1426 // Add the selected register allocation pass.
1427 addPass(P: createRegAllocPass(Optimized: true));
1428
1429 // Allow targets to change the register assignments before rewriting.
1430 addPreRewrite();
1431
1432 // Finally rewrite virtual registers.
1433 addPass(PassID: &VirtRegRewriterID);
1434
1435 // Regalloc scoring for ML-driven eviction - noop except when learning a new
1436 // eviction policy.
1437 addPass(P: createRegAllocScoringPass());
1438 return true;
1439}
1440
1441/// Return true if the default global register allocator is in use and
1442/// has not be overriden on the command line with '-regalloc=...'
1443bool TargetPassConfig::usingDefaultRegAlloc() const {
1444 return RegAlloc.getNumOccurrences() == 0;
1445}
1446
1447/// Add the minimum set of target-independent passes that are required for
1448/// register allocation. No coalescing or scheduling.
1449void TargetPassConfig::addFastRegAlloc() {
1450 addPass(PassID: &PHIEliminationID);
1451 addPass(PassID: &TwoAddressInstructionPassID);
1452
1453 addRegAssignAndRewriteFast();
1454}
1455
1456/// Add standard target-independent passes that are tightly coupled with
1457/// optimized register allocation, including coalescing, machine instruction
1458/// scheduling, and register allocation itself.
1459void TargetPassConfig::addOptimizedRegAlloc() {
1460 addPass(PassID: &DetectDeadLanesID);
1461
1462 addPass(PassID: &InitUndefID);
1463
1464 addPass(PassID: &ProcessImplicitDefsID);
1465
1466 // LiveVariables currently requires pure SSA form.
1467 //
1468 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1469 // LiveVariables can be removed completely, and LiveIntervals can be directly
1470 // computed. (We still either need to regenerate kill flags after regalloc, or
1471 // preferably fix the scavenger to not depend on them).
1472 // FIXME: UnreachableMachineBlockElim is a dependant pass of LiveVariables.
1473 // When LiveVariables is removed this has to be removed/moved either.
1474 // Explicit addition of UnreachableMachineBlockElim allows stopping before or
1475 // after it with -stop-before/-stop-after.
1476 addPass(PassID: &UnreachableMachineBlockElimID);
1477 addPass(PassID: &LiveVariablesID);
1478
1479 // Edge splitting is smarter with machine loop info.
1480 addPass(PassID: &MachineLoopInfoID);
1481 addPass(PassID: &PHIEliminationID);
1482
1483 // Eventually, we want to run LiveIntervals before PHI elimination.
1484 if (EarlyLiveIntervals)
1485 addPass(PassID: &LiveIntervalsID);
1486
1487 addPass(PassID: &TwoAddressInstructionPassID);
1488 addPass(PassID: &RegisterCoalescerID);
1489
1490 // The machine scheduler may accidentally create disconnected components
1491 // when moving subregister definitions around, avoid this by splitting them to
1492 // separate vregs before. Splitting can also improve reg. allocation quality.
1493 addPass(PassID: &RenameIndependentSubregsID);
1494
1495 // PreRA instruction scheduling.
1496 addPass(PassID: &MachineSchedulerID);
1497
1498 if (addRegAssignAndRewriteOptimized()) {
1499 // Perform stack slot coloring and post-ra machine LICM.
1500 addPass(PassID: &StackSlotColoringID);
1501
1502 // Allow targets to expand pseudo instructions depending on the choice of
1503 // registers before MachineCopyPropagation.
1504 addPostRewrite();
1505
1506 // Copy propagate to forward register uses and try to eliminate COPYs that
1507 // were not coalesced.
1508 addPass(PassID: &MachineCopyPropagationID);
1509
1510 // Run post-ra machine LICM to hoist reloads / remats.
1511 //
1512 // FIXME: can this move into MachineLateOptimization?
1513 addPass(PassID: &MachineLICMID);
1514 }
1515}
1516
1517//===---------------------------------------------------------------------===//
1518/// Post RegAlloc Pass Configuration
1519//===---------------------------------------------------------------------===//
1520
1521/// Add passes that optimize machine instructions after register allocation.
1522void TargetPassConfig::addMachineLateOptimization() {
1523 // Cleanup of redundant immediate/address loads.
1524 addPass(PassID: &MachineLateInstrsCleanupID);
1525
1526 // Branch folding must be run after regalloc and prolog/epilog insertion.
1527 addPass(PassID: &BranchFolderPassID);
1528
1529 // Tail duplication.
1530 // Note that duplicating tail just increases code size and degrades
1531 // performance for targets that require Structured Control Flow.
1532 // In addition it can also make CFG irreducible. Thus we disable it.
1533 if (!TM->requiresStructuredCFG())
1534 addPass(PassID: &TailDuplicateLegacyID);
1535
1536 // Copy propagation.
1537 addPass(PassID: &MachineCopyPropagationID);
1538}
1539
1540/// Add standard GC passes.
1541bool TargetPassConfig::addGCPasses() {
1542 addPass(PassID: &GCMachineCodeAnalysisID);
1543 return true;
1544}
1545
1546/// Add standard basic block placement passes.
1547void TargetPassConfig::addBlockPlacement() {
1548 if (EnableFSDiscriminator) {
1549 addPass(P: createMIRAddFSDiscriminatorsPass(
1550 P: sampleprof::FSDiscriminatorPass::Pass2));
1551 const std::string ProfileFile = getFSProfileFile(TM);
1552 if (!ProfileFile.empty() && !DisableLayoutFSProfileLoader)
1553 addPass(P: createMIRProfileLoaderPass(File: ProfileFile, RemappingFile: getFSRemappingFile(TM),
1554 P: sampleprof::FSDiscriminatorPass::Pass2,
1555 FS: nullptr));
1556 }
1557 if (addPass(PassID: &MachineBlockPlacementID)) {
1558 // Run a separate pass to collect block placement statistics.
1559 if (EnableBlockPlacementStats)
1560 addPass(PassID: &MachineBlockPlacementStatsID);
1561 }
1562}
1563
1564//===---------------------------------------------------------------------===//
1565/// GlobalISel Configuration
1566//===---------------------------------------------------------------------===//
1567bool TargetPassConfig::isGlobalISelAbortEnabled() const {
1568 return TM->Options.GlobalISelAbort == GlobalISelAbortMode::Enable;
1569}
1570
1571bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
1572 return TM->Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag;
1573}
1574
1575bool TargetPassConfig::isGISelCSEEnabled() const {
1576 return true;
1577}
1578
1579std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const {
1580 return std::make_unique<CSEConfigBase>();
1581}
1582