1//==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AArch64 implementation of the MRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
15
16#define GET_REGINFO_HEADER
17#include "AArch64GenRegisterInfo.inc"
18
19namespace llvm {
20
21class MachineFunction;
22class RegScavenger;
23class TargetRegisterClass;
24class Triple;
25
26class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
27 const Triple &TT;
28
29public:
30 AArch64RegisterInfo(const Triple &TT, unsigned HwMode);
31
32 // FIXME: This should be tablegen'd like getDwarfRegNum is
33 int getSEHRegNum(unsigned i) const {
34 return getEncodingValue(Reg: i);
35 }
36
37 bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
38 bool isUserReservedReg(const MachineFunction &MF, MCRegister Reg) const;
39 bool isStrictlyReservedReg(const MachineFunction &MF, MCRegister Reg) const;
40 bool isAnyArgRegReserved(const MachineFunction &MF) const;
41 void emitReservedArgRegCallError(const MachineFunction &MF) const;
42
43 void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const;
44 void UpdateCustomCallPreservedMask(MachineFunction &MF,
45 const uint32_t **Mask) const;
46
47 /// Code Generation virtual methods...
48 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
49 const MCPhysReg *getDarwinCalleeSavedRegs(const MachineFunction *MF) const;
50 const MCPhysReg *
51 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
52 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
53 CallingConv::ID) const override;
54 const uint32_t *getDarwinCallPreservedMask(const MachineFunction &MF,
55 CallingConv::ID) const;
56
57 unsigned getCSRFirstUseCost() const override {
58 // The cost will be compared against BlockFrequency where entry has the
59 // value of 1 << 14. A value of 5 will choose to spill or split really
60 // cold path instead of using a callee-saved register.
61 return 5;
62 }
63
64 const TargetRegisterClass *
65 getSubClassWithSubReg(const TargetRegisterClass *RC,
66 unsigned Idx) const override;
67
68 // Calls involved in thread-local variable lookup save more registers than
69 // normal calls, so they need a different mask to represent this.
70 const uint32_t *getTLSCallPreservedMask() const;
71
72 const uint32_t *getSMStartStopCallPreservedMask() const;
73 const uint32_t *SMEABISupportRoutinesCallPreservedMaskFromX0() const;
74
75 // Funclets on ARM64 Windows don't preserve any registers.
76 const uint32_t *getNoPreservedMask() const override;
77
78 // Unwinders may not preserve all Neon and SVE registers.
79 const uint32_t *
80 getCustomEHPadPreservedMask(const MachineFunction &MF) const override;
81
82 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
83 /// case that 'returned' is on an i64 first argument if the calling convention
84 /// is one that can (partially) model this attribute with a preserved mask
85 /// (i.e. it is a calling convention that uses the same register for the first
86 /// i64 argument and an i64 return value)
87 ///
88 /// Should return NULL in the case that the calling convention does not have
89 /// this property
90 const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
91 CallingConv::ID) const;
92
93 /// Stack probing calls preserve different CSRs to the normal CC.
94 const uint32_t *getWindowsStackProbePreservedMask() const;
95
96 BitVector getStrictlyReservedRegs(const MachineFunction &MF) const;
97 BitVector getUserReservedRegs(const MachineFunction &MF) const;
98 BitVector getReservedRegs(const MachineFunction &MF) const override;
99 std::optional<std::string>
100 explainReservedReg(const MachineFunction &MF,
101 MCRegister PhysReg) const override;
102 bool isAsmClobberable(const MachineFunction &MF,
103 MCRegister PhysReg) const override;
104 const TargetRegisterClass *
105 getPointerRegClass(const MachineFunction &MF,
106 unsigned Kind = 0) const override;
107 const TargetRegisterClass *
108 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
109
110 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
111 bool useFPForScavengingIndex(const MachineFunction &MF) const override;
112 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
113
114 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
115 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
116 int64_t Offset) const override;
117 Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx,
118 int64_t Offset) const override;
119 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
120 int64_t Offset) const override;
121 bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
122 unsigned FIOperandNum,
123 RegScavenger *RS = nullptr) const override;
124 bool cannotEliminateFrame(const MachineFunction &MF) const;
125
126 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
127 bool hasBasePointer(const MachineFunction &MF) const;
128 unsigned getBaseRegister() const;
129
130 bool isArgumentRegister(const MachineFunction &MF,
131 MCRegister Reg) const override;
132
133 // Debug information queries.
134 Register getFrameRegister(const MachineFunction &MF) const override;
135
136 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
137 MachineFunction &MF) const override;
138
139 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
140 SmallVectorImpl<MCPhysReg> &Hints,
141 const MachineFunction &MF, const VirtRegMap *VRM,
142 const LiveRegMatrix *Matrix) const override;
143
144 unsigned getLocalAddressRegister(const MachineFunction &MF) const;
145 bool regNeedsCFI(MCRegister Reg, MCRegister &RegToUseForCFI) const;
146
147 /// SrcRC and DstRC will be morphed into NewRC if this returns true
148 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
149 unsigned SubReg, const TargetRegisterClass *DstRC,
150 unsigned DstSubReg, const TargetRegisterClass *NewRC,
151 LiveIntervals &LIS) const override;
152
153 void getOffsetOpcodes(const StackOffset &Offset,
154 SmallVectorImpl<uint64_t> &Ops) const override;
155
156 bool shouldAnalyzePhysregInMachineLoopInfo(MCRegister R) const override;
157};
158
159} // end namespace llvm
160
161#endif
162