1//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone helper functions and enum definitions for
10// the AArch64 target useful for the compiler back-end and the MC libraries.
11// As such, it deliberately does not include references to LLVM core
12// code gen types, passes, etc..
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
17#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18
19// FIXME: Is it easiest to fix this layering violation by moving the .inc
20// #includes from AArch64MCTargetDesc.h to here?
21#include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
22#include "llvm/ADT/BitmaskEnum.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/StringSwitch.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/TargetParser/SubtargetFeature.h"
27
28namespace llvm {
29
30inline static MCRegister getWRegFromXReg(MCRegister Reg) {
31 switch (Reg.id()) {
32 case AArch64::X0: return AArch64::W0;
33 case AArch64::X1: return AArch64::W1;
34 case AArch64::X2: return AArch64::W2;
35 case AArch64::X3: return AArch64::W3;
36 case AArch64::X4: return AArch64::W4;
37 case AArch64::X5: return AArch64::W5;
38 case AArch64::X6: return AArch64::W6;
39 case AArch64::X7: return AArch64::W7;
40 case AArch64::X8: return AArch64::W8;
41 case AArch64::X9: return AArch64::W9;
42 case AArch64::X10: return AArch64::W10;
43 case AArch64::X11: return AArch64::W11;
44 case AArch64::X12: return AArch64::W12;
45 case AArch64::X13: return AArch64::W13;
46 case AArch64::X14: return AArch64::W14;
47 case AArch64::X15: return AArch64::W15;
48 case AArch64::X16: return AArch64::W16;
49 case AArch64::X17: return AArch64::W17;
50 case AArch64::X18: return AArch64::W18;
51 case AArch64::X19: return AArch64::W19;
52 case AArch64::X20: return AArch64::W20;
53 case AArch64::X21: return AArch64::W21;
54 case AArch64::X22: return AArch64::W22;
55 case AArch64::X23: return AArch64::W23;
56 case AArch64::X24: return AArch64::W24;
57 case AArch64::X25: return AArch64::W25;
58 case AArch64::X26: return AArch64::W26;
59 case AArch64::X27: return AArch64::W27;
60 case AArch64::X28: return AArch64::W28;
61 case AArch64::FP: return AArch64::W29;
62 case AArch64::LR: return AArch64::W30;
63 case AArch64::SP: return AArch64::WSP;
64 case AArch64::XZR: return AArch64::WZR;
65 }
66 // For anything else, return it unchanged.
67 return Reg;
68}
69
70inline static MCRegister getXRegFromWReg(MCRegister Reg) {
71 switch (Reg.id()) {
72 case AArch64::W0: return AArch64::X0;
73 case AArch64::W1: return AArch64::X1;
74 case AArch64::W2: return AArch64::X2;
75 case AArch64::W3: return AArch64::X3;
76 case AArch64::W4: return AArch64::X4;
77 case AArch64::W5: return AArch64::X5;
78 case AArch64::W6: return AArch64::X6;
79 case AArch64::W7: return AArch64::X7;
80 case AArch64::W8: return AArch64::X8;
81 case AArch64::W9: return AArch64::X9;
82 case AArch64::W10: return AArch64::X10;
83 case AArch64::W11: return AArch64::X11;
84 case AArch64::W12: return AArch64::X12;
85 case AArch64::W13: return AArch64::X13;
86 case AArch64::W14: return AArch64::X14;
87 case AArch64::W15: return AArch64::X15;
88 case AArch64::W16: return AArch64::X16;
89 case AArch64::W17: return AArch64::X17;
90 case AArch64::W18: return AArch64::X18;
91 case AArch64::W19: return AArch64::X19;
92 case AArch64::W20: return AArch64::X20;
93 case AArch64::W21: return AArch64::X21;
94 case AArch64::W22: return AArch64::X22;
95 case AArch64::W23: return AArch64::X23;
96 case AArch64::W24: return AArch64::X24;
97 case AArch64::W25: return AArch64::X25;
98 case AArch64::W26: return AArch64::X26;
99 case AArch64::W27: return AArch64::X27;
100 case AArch64::W28: return AArch64::X28;
101 case AArch64::W29: return AArch64::FP;
102 case AArch64::W30: return AArch64::LR;
103 case AArch64::WSP: return AArch64::SP;
104 case AArch64::WZR: return AArch64::XZR;
105 }
106 // For anything else, return it unchanged.
107 return Reg;
108}
109
110inline static MCRegister getXRegFromXRegTuple(MCRegister RegTuple) {
111 switch (RegTuple.id()) {
112 case AArch64::X0_X1_X2_X3_X4_X5_X6_X7: return AArch64::X0;
113 case AArch64::X2_X3_X4_X5_X6_X7_X8_X9: return AArch64::X2;
114 case AArch64::X4_X5_X6_X7_X8_X9_X10_X11: return AArch64::X4;
115 case AArch64::X6_X7_X8_X9_X10_X11_X12_X13: return AArch64::X6;
116 case AArch64::X8_X9_X10_X11_X12_X13_X14_X15: return AArch64::X8;
117 case AArch64::X10_X11_X12_X13_X14_X15_X16_X17: return AArch64::X10;
118 case AArch64::X12_X13_X14_X15_X16_X17_X18_X19: return AArch64::X12;
119 case AArch64::X14_X15_X16_X17_X18_X19_X20_X21: return AArch64::X14;
120 case AArch64::X16_X17_X18_X19_X20_X21_X22_X23: return AArch64::X16;
121 case AArch64::X18_X19_X20_X21_X22_X23_X24_X25: return AArch64::X18;
122 case AArch64::X20_X21_X22_X23_X24_X25_X26_X27: return AArch64::X20;
123 case AArch64::X22_X23_X24_X25_X26_X27_X28_FP: return AArch64::X22;
124 }
125 // For anything else, return it unchanged.
126 return RegTuple;
127}
128
129static inline MCRegister getBRegFromDReg(MCRegister Reg) {
130 switch (Reg.id()) {
131 case AArch64::D0: return AArch64::B0;
132 case AArch64::D1: return AArch64::B1;
133 case AArch64::D2: return AArch64::B2;
134 case AArch64::D3: return AArch64::B3;
135 case AArch64::D4: return AArch64::B4;
136 case AArch64::D5: return AArch64::B5;
137 case AArch64::D6: return AArch64::B6;
138 case AArch64::D7: return AArch64::B7;
139 case AArch64::D8: return AArch64::B8;
140 case AArch64::D9: return AArch64::B9;
141 case AArch64::D10: return AArch64::B10;
142 case AArch64::D11: return AArch64::B11;
143 case AArch64::D12: return AArch64::B12;
144 case AArch64::D13: return AArch64::B13;
145 case AArch64::D14: return AArch64::B14;
146 case AArch64::D15: return AArch64::B15;
147 case AArch64::D16: return AArch64::B16;
148 case AArch64::D17: return AArch64::B17;
149 case AArch64::D18: return AArch64::B18;
150 case AArch64::D19: return AArch64::B19;
151 case AArch64::D20: return AArch64::B20;
152 case AArch64::D21: return AArch64::B21;
153 case AArch64::D22: return AArch64::B22;
154 case AArch64::D23: return AArch64::B23;
155 case AArch64::D24: return AArch64::B24;
156 case AArch64::D25: return AArch64::B25;
157 case AArch64::D26: return AArch64::B26;
158 case AArch64::D27: return AArch64::B27;
159 case AArch64::D28: return AArch64::B28;
160 case AArch64::D29: return AArch64::B29;
161 case AArch64::D30: return AArch64::B30;
162 case AArch64::D31: return AArch64::B31;
163 }
164 // For anything else, return it unchanged.
165 return Reg;
166}
167
168static inline MCRegister getDRegFromBReg(MCRegister Reg) {
169 switch (Reg.id()) {
170 case AArch64::B0: return AArch64::D0;
171 case AArch64::B1: return AArch64::D1;
172 case AArch64::B2: return AArch64::D2;
173 case AArch64::B3: return AArch64::D3;
174 case AArch64::B4: return AArch64::D4;
175 case AArch64::B5: return AArch64::D5;
176 case AArch64::B6: return AArch64::D6;
177 case AArch64::B7: return AArch64::D7;
178 case AArch64::B8: return AArch64::D8;
179 case AArch64::B9: return AArch64::D9;
180 case AArch64::B10: return AArch64::D10;
181 case AArch64::B11: return AArch64::D11;
182 case AArch64::B12: return AArch64::D12;
183 case AArch64::B13: return AArch64::D13;
184 case AArch64::B14: return AArch64::D14;
185 case AArch64::B15: return AArch64::D15;
186 case AArch64::B16: return AArch64::D16;
187 case AArch64::B17: return AArch64::D17;
188 case AArch64::B18: return AArch64::D18;
189 case AArch64::B19: return AArch64::D19;
190 case AArch64::B20: return AArch64::D20;
191 case AArch64::B21: return AArch64::D21;
192 case AArch64::B22: return AArch64::D22;
193 case AArch64::B23: return AArch64::D23;
194 case AArch64::B24: return AArch64::D24;
195 case AArch64::B25: return AArch64::D25;
196 case AArch64::B26: return AArch64::D26;
197 case AArch64::B27: return AArch64::D27;
198 case AArch64::B28: return AArch64::D28;
199 case AArch64::B29: return AArch64::D29;
200 case AArch64::B30: return AArch64::D30;
201 case AArch64::B31: return AArch64::D31;
202 }
203 // For anything else, return it unchanged.
204 return Reg;
205}
206
207static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) {
208 switch (Opcode) {
209 case AArch64::LDADDAB: case AArch64::LDADDAH:
210 case AArch64::LDADDAW: case AArch64::LDADDAX:
211 case AArch64::LDADDALB: case AArch64::LDADDALH:
212 case AArch64::LDADDALW: case AArch64::LDADDALX:
213 case AArch64::LDCLRAB: case AArch64::LDCLRAH:
214 case AArch64::LDCLRAW: case AArch64::LDCLRAX:
215 case AArch64::LDCLRALB: case AArch64::LDCLRALH:
216 case AArch64::LDCLRALW: case AArch64::LDCLRALX:
217 case AArch64::LDEORAB: case AArch64::LDEORAH:
218 case AArch64::LDEORAW: case AArch64::LDEORAX:
219 case AArch64::LDEORALB: case AArch64::LDEORALH:
220 case AArch64::LDEORALW: case AArch64::LDEORALX:
221 case AArch64::LDSETAB: case AArch64::LDSETAH:
222 case AArch64::LDSETAW: case AArch64::LDSETAX:
223 case AArch64::LDSETALB: case AArch64::LDSETALH:
224 case AArch64::LDSETALW: case AArch64::LDSETALX:
225 case AArch64::LDSMAXAB: case AArch64::LDSMAXAH:
226 case AArch64::LDSMAXAW: case AArch64::LDSMAXAX:
227 case AArch64::LDSMAXALB: case AArch64::LDSMAXALH:
228 case AArch64::LDSMAXALW: case AArch64::LDSMAXALX:
229 case AArch64::LDSMINAB: case AArch64::LDSMINAH:
230 case AArch64::LDSMINAW: case AArch64::LDSMINAX:
231 case AArch64::LDSMINALB: case AArch64::LDSMINALH:
232 case AArch64::LDSMINALW: case AArch64::LDSMINALX:
233 case AArch64::LDUMAXAB: case AArch64::LDUMAXAH:
234 case AArch64::LDUMAXAW: case AArch64::LDUMAXAX:
235 case AArch64::LDUMAXALB: case AArch64::LDUMAXALH:
236 case AArch64::LDUMAXALW: case AArch64::LDUMAXALX:
237 case AArch64::LDUMINAB: case AArch64::LDUMINAH:
238 case AArch64::LDUMINAW: case AArch64::LDUMINAX:
239 case AArch64::LDUMINALB: case AArch64::LDUMINALH:
240 case AArch64::LDUMINALW: case AArch64::LDUMINALX:
241 case AArch64::SWPAB: case AArch64::SWPAH:
242 case AArch64::SWPAW: case AArch64::SWPAX:
243 case AArch64::SWPALB: case AArch64::SWPALH:
244 case AArch64::SWPALW: case AArch64::SWPALX:
245 return true;
246 }
247 return false;
248}
249
250namespace AArch64CC {
251
252// The CondCodes constants map directly to the 4-bit encoding of the condition
253// field for predicated instructions.
254enum CondCode { // Meaning (integer) Meaning (floating-point)
255 EQ = 0x0, // Equal Equal
256 NE = 0x1, // Not equal Not equal, or unordered
257 HS = 0x2, // Unsigned higher or same >, ==, or unordered
258 LO = 0x3, // Unsigned lower Less than
259 MI = 0x4, // Minus, negative Less than
260 PL = 0x5, // Plus, positive or zero >, ==, or unordered
261 VS = 0x6, // Overflow Unordered
262 VC = 0x7, // No overflow Not unordered
263 HI = 0x8, // Unsigned higher Greater than, or unordered
264 LS = 0x9, // Unsigned lower or same Less than or equal
265 GE = 0xa, // Greater than or equal Greater than or equal
266 LT = 0xb, // Less than Less than, or unordered
267 GT = 0xc, // Greater than Greater than
268 LE = 0xd, // Less than or equal <, ==, or unordered
269 AL = 0xe, // Always (unconditional) Always (unconditional)
270 NV = 0xf, // Always (unconditional) Always (unconditional)
271 // Note the NV exists purely to disassemble 0b1111. Execution is "always".
272 Invalid,
273
274 // Common aliases used for SVE.
275 ANY_ACTIVE = NE, // (!Z)
276 FIRST_ACTIVE = MI, // ( N)
277 LAST_ACTIVE = LO, // (!C)
278 NONE_ACTIVE = EQ // ( Z)
279};
280
281inline static const char *getCondCodeName(CondCode Code) {
282 switch (Code) {
283 default: llvm_unreachable("Unknown condition code");
284 case EQ: return "eq";
285 case NE: return "ne";
286 case HS: return "hs";
287 case LO: return "lo";
288 case MI: return "mi";
289 case PL: return "pl";
290 case VS: return "vs";
291 case VC: return "vc";
292 case HI: return "hi";
293 case LS: return "ls";
294 case GE: return "ge";
295 case LT: return "lt";
296 case GT: return "gt";
297 case LE: return "le";
298 case AL: return "al";
299 case NV: return "nv";
300 }
301}
302
303inline static CondCode getInvertedCondCode(CondCode Code) {
304 // To reverse a condition it's necessary to only invert the low bit:
305
306 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
307}
308
309/// getSwappedCondition - assume the flags are set by MI(a,b), return
310/// the condition code if we modify the instructions such that flags are
311/// set by MI(b,a).
312inline static CondCode getSwappedCondition(CondCode CC) {
313 switch (CC) {
314 default:
315 return AL;
316 case EQ:
317 return EQ;
318 case NE:
319 return NE;
320 case HS:
321 return LS;
322 case LO:
323 return HI;
324 case HI:
325 return LO;
326 case LS:
327 return HS;
328 case GE:
329 return LE;
330 case LT:
331 return GT;
332 case GT:
333 return LT;
334 case LE:
335 return GE;
336 }
337}
338
339/// Given a condition code, return NZCV flags that would satisfy that condition.
340/// The flag bits are in the format expected by the ccmp instructions.
341/// Note that many different flag settings can satisfy a given condition code,
342/// this function just returns one of them.
343inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
344 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
345 enum { N = 8, Z = 4, C = 2, V = 1 };
346 switch (Code) {
347 default: llvm_unreachable("Unknown condition code");
348 case EQ: return Z; // Z == 1
349 case NE: return 0; // Z == 0
350 case HS: return C; // C == 1
351 case LO: return 0; // C == 0
352 case MI: return N; // N == 1
353 case PL: return 0; // N == 0
354 case VS: return V; // V == 1
355 case VC: return 0; // V == 0
356 case HI: return C; // C == 1 && Z == 0
357 case LS: return 0; // C == 0 || Z == 1
358 case GE: return 0; // N == V
359 case LT: return N; // N != V
360 case GT: return 0; // Z == 0 && N == V
361 case LE: return Z; // Z == 1 || N != V
362 }
363}
364
365/// True, if a given condition code can be used in a fused compare-and-branch
366/// instructions, false otherwise.
367inline static bool isValidCBCond(AArch64CC::CondCode Code) {
368 switch (Code) {
369 default:
370 return false;
371 case AArch64CC::EQ:
372 case AArch64CC::NE:
373 case AArch64CC::HS:
374 case AArch64CC::LO:
375 case AArch64CC::HI:
376 case AArch64CC::LS:
377 case AArch64CC::GE:
378 case AArch64CC::LT:
379 case AArch64CC::GT:
380 case AArch64CC::LE:
381 return true;
382 }
383}
384
385} // end namespace AArch64CC
386
387struct SysAlias {
388 const char *Name;
389 uint16_t Encoding;
390 FeatureBitset FeaturesRequired;
391
392 constexpr SysAlias(const char *N, uint16_t E) : Name(N), Encoding(E) {}
393 constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
394 : Name(N), Encoding(E), FeaturesRequired(F) {}
395
396 bool haveFeatures(FeatureBitset ActiveFeatures) const {
397 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
398 (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
399 }
400
401 FeatureBitset getRequiredFeatures() const { return FeaturesRequired; }
402};
403
404struct SysAliasReg : SysAlias {
405 bool NeedsReg;
406 constexpr SysAliasReg(const char *N, uint16_t E, bool R)
407 : SysAlias(N, E), NeedsReg(R) {}
408 constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
409 : SysAlias(N, E, F), NeedsReg(R) {}
410};
411
412struct SysAliasImm : SysAlias {
413 uint16_t ImmValue;
414 constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
415 : SysAlias(N, E), ImmValue(I) {}
416 constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
417 : SysAlias(N, E, F), ImmValue(I) {}
418};
419
420namespace AArch64SVCR {
421 struct SVCR : SysAlias{
422 using SysAlias::SysAlias;
423 };
424#define GET_SVCRValues_DECL
425#define GET_SVCRsList_DECL
426#include "AArch64GenSystemOperands.inc"
427}
428
429namespace AArch64AT{
430 struct AT : SysAlias {
431 using SysAlias::SysAlias;
432 };
433#define GET_ATValues_DECL
434#define GET_ATsList_DECL
435#include "AArch64GenSystemOperands.inc"
436}
437
438namespace AArch64DB {
439 struct DB : SysAlias {
440 using SysAlias::SysAlias;
441 };
442#define GET_DBValues_DECL
443#define GET_DBsList_DECL
444#include "AArch64GenSystemOperands.inc"
445}
446
447namespace AArch64DBnXS {
448 struct DBnXS : SysAliasImm {
449 using SysAliasImm::SysAliasImm;
450 };
451#define GET_DBnXSValues_DECL
452#define GET_DBnXSsList_DECL
453#include "AArch64GenSystemOperands.inc"
454}
455
456namespace AArch64DC {
457 struct DC : SysAlias {
458 using SysAlias::SysAlias;
459 };
460#define GET_DCValues_DECL
461#define GET_DCsList_DECL
462#include "AArch64GenSystemOperands.inc"
463}
464
465namespace AArch64IC {
466 struct IC : SysAliasReg {
467 using SysAliasReg::SysAliasReg;
468 };
469#define GET_ICValues_DECL
470#define GET_ICsList_DECL
471#include "AArch64GenSystemOperands.inc"
472}
473
474namespace AArch64ISB {
475 struct ISB : SysAlias {
476 using SysAlias::SysAlias;
477 };
478#define GET_ISBValues_DECL
479#define GET_ISBsList_DECL
480#include "AArch64GenSystemOperands.inc"
481}
482
483namespace AArch64TSB {
484 struct TSB : SysAlias {
485 using SysAlias::SysAlias;
486 };
487#define GET_TSBValues_DECL
488#define GET_TSBsList_DECL
489#include "AArch64GenSystemOperands.inc"
490}
491
492namespace AArch64PRFM {
493 struct PRFM : SysAlias {
494 using SysAlias::SysAlias;
495 };
496#define GET_PRFMValues_DECL
497#define GET_PRFMsList_DECL
498#include "AArch64GenSystemOperands.inc"
499}
500
501namespace AArch64SVEPRFM {
502 struct SVEPRFM : SysAlias {
503 using SysAlias::SysAlias;
504 };
505#define GET_SVEPRFMValues_DECL
506#define GET_SVEPRFMsList_DECL
507#include "AArch64GenSystemOperands.inc"
508}
509
510namespace AArch64RPRFM {
511struct RPRFM : SysAlias {
512 using SysAlias::SysAlias;
513};
514#define GET_RPRFMValues_DECL
515#define GET_RPRFMsList_DECL
516#include "AArch64GenSystemOperands.inc"
517} // namespace AArch64RPRFM
518
519namespace AArch64SVEPredPattern {
520 struct SVEPREDPAT {
521 const char *Name;
522 uint16_t Encoding;
523 };
524#define GET_SVEPREDPATValues_DECL
525#define GET_SVEPREDPATsList_DECL
526#include "AArch64GenSystemOperands.inc"
527}
528
529namespace AArch64SVEVecLenSpecifier {
530 struct SVEVECLENSPECIFIER {
531 const char *Name;
532 uint16_t Encoding;
533 };
534#define GET_SVEVECLENSPECIFIERValues_DECL
535#define GET_SVEVECLENSPECIFIERsList_DECL
536#include "AArch64GenSystemOperands.inc"
537} // namespace AArch64SVEVecLenSpecifier
538
539/// Return the number of active elements for VL1 to VL256 predicate pattern,
540/// zero for all other patterns.
541inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern) {
542 switch (Pattern) {
543 default:
544 return 0;
545 case AArch64SVEPredPattern::vl1:
546 case AArch64SVEPredPattern::vl2:
547 case AArch64SVEPredPattern::vl3:
548 case AArch64SVEPredPattern::vl4:
549 case AArch64SVEPredPattern::vl5:
550 case AArch64SVEPredPattern::vl6:
551 case AArch64SVEPredPattern::vl7:
552 case AArch64SVEPredPattern::vl8:
553 return Pattern;
554 case AArch64SVEPredPattern::vl16:
555 return 16;
556 case AArch64SVEPredPattern::vl32:
557 return 32;
558 case AArch64SVEPredPattern::vl64:
559 return 64;
560 case AArch64SVEPredPattern::vl128:
561 return 128;
562 case AArch64SVEPredPattern::vl256:
563 return 256;
564 }
565}
566
567/// Return specific VL predicate pattern based on the number of elements.
568inline std::optional<unsigned>
569getSVEPredPatternFromNumElements(unsigned MinNumElts) {
570 switch (MinNumElts) {
571 default:
572 return std::nullopt;
573 case 1:
574 case 2:
575 case 3:
576 case 4:
577 case 5:
578 case 6:
579 case 7:
580 case 8:
581 return MinNumElts;
582 case 16:
583 return AArch64SVEPredPattern::vl16;
584 case 32:
585 return AArch64SVEPredPattern::vl32;
586 case 64:
587 return AArch64SVEPredPattern::vl64;
588 case 128:
589 return AArch64SVEPredPattern::vl128;
590 case 256:
591 return AArch64SVEPredPattern::vl256;
592 }
593}
594
595/// An enum to describe what types of loops we should attempt to tail-fold:
596/// Disabled: None
597/// Reductions: Loops containing reductions
598/// Recurrences: Loops with first-order recurrences, i.e. that would
599/// require a SVE splice instruction
600/// Reverse: Reverse loops
601/// Simple: Loops that are not reversed and don't contain reductions
602/// or first-order recurrences.
603/// All: All
604enum class TailFoldingOpts : uint8_t {
605 Disabled = 0x00,
606 Simple = 0x01,
607 Reductions = 0x02,
608 Recurrences = 0x04,
609 Reverse = 0x08,
610 All = Reductions | Recurrences | Simple | Reverse
611};
612
613LLVM_DECLARE_ENUM_AS_BITMASK(TailFoldingOpts,
614 /* LargestValue */ (long)TailFoldingOpts::Reverse);
615
616namespace AArch64ExactFPImm {
617struct ExactFPImm {
618 int Enum;
619 const char *Repr;
620};
621#define GET_ExactFPImmValues_DECL
622#define GET_ExactFPImmsList_DECL
623#include "AArch64GenSystemOperands.inc"
624}
625
626namespace AArch64PState {
627 struct PStateImm0_15 : SysAlias{
628 using SysAlias::SysAlias;
629 };
630#define GET_PStateImm0_15Values_DECL
631#define GET_PStateImm0_15sList_DECL
632#include "AArch64GenSystemOperands.inc"
633
634 struct PStateImm0_1 : SysAlias{
635 using SysAlias::SysAlias;
636 };
637#define GET_PStateImm0_1Values_DECL
638#define GET_PStateImm0_1sList_DECL
639#include "AArch64GenSystemOperands.inc"
640}
641
642namespace AArch64PSBHint {
643 struct PSB : SysAlias {
644 using SysAlias::SysAlias;
645 };
646#define GET_PSBValues_DECL
647#define GET_PSBsList_DECL
648#include "AArch64GenSystemOperands.inc"
649}
650
651namespace AArch64PHint {
652struct PHint {
653 const char *Name;
654 unsigned Encoding;
655 FeatureBitset FeaturesRequired;
656
657 bool haveFeatures(FeatureBitset ActiveFeatures) const {
658 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
659 (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
660 }
661};
662
663#define GET_PHintValues_DECL
664#define GET_PHintsList_DECL
665#include "AArch64GenSystemOperands.inc"
666
667const PHint *lookupPHintByName(StringRef);
668const PHint *lookupPHintByEncoding(uint16_t);
669} // namespace AArch64PHint
670
671namespace AArch64BTIHint {
672 struct BTI : SysAlias {
673 using SysAlias::SysAlias;
674 };
675#define GET_BTIValues_DECL
676#define GET_BTIsList_DECL
677#include "AArch64GenSystemOperands.inc"
678}
679
680namespace AArch64SME {
681enum ToggleCondition : unsigned {
682 Always,
683 IfCallerIsStreaming,
684 IfCallerIsNonStreaming
685};
686}
687
688namespace AArch64SE {
689 enum ShiftExtSpecifiers {
690 Invalid = -1,
691 LSL,
692 MSL,
693 LSR,
694 ASR,
695 ROR,
696
697 UXTB,
698 UXTH,
699 UXTW,
700 UXTX,
701
702 SXTB,
703 SXTH,
704 SXTW,
705 SXTX
706 };
707}
708
709namespace AArch64Layout {
710 enum VectorLayout {
711 Invalid = -1,
712 VL_8B,
713 VL_4H,
714 VL_2S,
715 VL_1D,
716
717 VL_16B,
718 VL_8H,
719 VL_4S,
720 VL_2D,
721
722 // Bare layout for the 128-bit vector
723 // (only show ".b", ".h", ".s", ".d" without vector number)
724 VL_B,
725 VL_H,
726 VL_S,
727 VL_D
728 };
729}
730
731inline static const char *
732AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
733 switch (Layout) {
734 case AArch64Layout::VL_8B: return ".8b";
735 case AArch64Layout::VL_4H: return ".4h";
736 case AArch64Layout::VL_2S: return ".2s";
737 case AArch64Layout::VL_1D: return ".1d";
738 case AArch64Layout::VL_16B: return ".16b";
739 case AArch64Layout::VL_8H: return ".8h";
740 case AArch64Layout::VL_4S: return ".4s";
741 case AArch64Layout::VL_2D: return ".2d";
742 case AArch64Layout::VL_B: return ".b";
743 case AArch64Layout::VL_H: return ".h";
744 case AArch64Layout::VL_S: return ".s";
745 case AArch64Layout::VL_D: return ".d";
746 default: llvm_unreachable("Unknown Vector Layout");
747 }
748}
749
750inline static AArch64Layout::VectorLayout
751AArch64StringToVectorLayout(StringRef LayoutStr) {
752 return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
753 .Case(S: ".8b", Value: AArch64Layout::VL_8B)
754 .Case(S: ".4h", Value: AArch64Layout::VL_4H)
755 .Case(S: ".2s", Value: AArch64Layout::VL_2S)
756 .Case(S: ".1d", Value: AArch64Layout::VL_1D)
757 .Case(S: ".16b", Value: AArch64Layout::VL_16B)
758 .Case(S: ".8h", Value: AArch64Layout::VL_8H)
759 .Case(S: ".4s", Value: AArch64Layout::VL_4S)
760 .Case(S: ".2d", Value: AArch64Layout::VL_2D)
761 .Case(S: ".b", Value: AArch64Layout::VL_B)
762 .Case(S: ".h", Value: AArch64Layout::VL_H)
763 .Case(S: ".s", Value: AArch64Layout::VL_S)
764 .Case(S: ".d", Value: AArch64Layout::VL_D)
765 .Default(Value: AArch64Layout::Invalid);
766}
767
768namespace AArch64SysReg {
769 struct SysReg {
770 const char Name[32];
771 unsigned Encoding;
772 bool Readable;
773 bool Writeable;
774 FeatureBitset FeaturesRequired;
775
776 bool haveFeatures(FeatureBitset ActiveFeatures) const {
777 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
778 (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
779 }
780 };
781
782#define GET_SysRegsList_DECL
783#define GET_SysRegValues_DECL
784#include "AArch64GenSystemOperands.inc"
785
786 uint32_t parseGenericRegister(StringRef Name);
787 std::string genericRegisterString(uint32_t Bits);
788}
789
790namespace AArch64TLBI {
791 struct TLBI : SysAliasReg {
792 using SysAliasReg::SysAliasReg;
793 };
794 #define GET_TLBITable_DECL
795 #include "AArch64GenSystemOperands.inc"
796}
797
798namespace AArch64II {
799/// Target Operand Flag enum.
800enum TOF {
801 //===------------------------------------------------------------------===//
802 // AArch64 Specific MachineOperand flags.
803
804 MO_NO_FLAG,
805
806 MO_FRAGMENT = 0x7,
807
808 /// MO_PAGE - A symbol operand with this flag represents the pc-relative
809 /// offset of the 4K page containing the symbol. This is used with the
810 /// ADRP instruction.
811 MO_PAGE = 1,
812
813 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
814 /// that symbol within a 4K page. This offset is added to the page address
815 /// to produce the complete address.
816 MO_PAGEOFF = 2,
817
818 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
819 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
820 MO_G3 = 3,
821
822 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
823 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
824 MO_G2 = 4,
825
826 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
827 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
828 MO_G1 = 5,
829
830 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
831 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
832 MO_G0 = 6,
833
834 /// MO_HI12 - This flag indicates that a symbol operand represents the bits
835 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
836 /// by-12-bits instruction.
837 MO_HI12 = 7,
838
839 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
840 /// reference is actually to the ".refptr.FOO" symbol. This is used for
841 /// stub symbols on windows.
842 MO_COFFSTUB = 0x8,
843
844 /// MO_GOT - This flag indicates that a symbol operand represents the
845 /// address of the GOT entry for the symbol, rather than the address of
846 /// the symbol itself.
847 MO_GOT = 0x10,
848
849 /// MO_NC - Indicates whether the linker is expected to check the symbol
850 /// reference for overflow. For example in an ADRP/ADD pair of relocations
851 /// the ADRP usually does check, but not the ADD.
852 MO_NC = 0x20,
853
854 /// MO_TLS - Indicates that the operand being accessed is some kind of
855 /// thread-local symbol. On Darwin, only one type of thread-local access
856 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
857 /// referee will affect interpretation.
858 MO_TLS = 0x40,
859
860 /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
861 /// to the symbol is for an import stub. This is used for DLL import
862 /// storage class indication on Windows.
863 MO_DLLIMPORT = 0x80,
864
865 /// MO_S - Indicates that the bits of the symbol operand represented by
866 /// MO_G0 etc are signed.
867 MO_S = 0x100,
868
869 /// MO_PREL - Indicates that the bits of the symbol operand represented by
870 /// MO_G0 etc are PC relative.
871 MO_PREL = 0x200,
872
873 /// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag
874 /// in bits 56-63.
875 /// On a FrameIndex operand, indicates that the underlying memory is tagged
876 /// with an unknown tag value (MTE); this needs to be lowered either to an
877 /// SP-relative load or store instruction (which do not check tags), or to
878 /// an LDG instruction to obtain the tag value.
879 MO_TAGGED = 0x400,
880
881 /// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version
882 /// of a symbol, not the original. For dllimport symbols, this means it
883 /// uses "__imp_aux". For other symbols, this means it uses the mangled
884 /// ("#" prefix for C) name.
885 MO_ARM64EC_CALLMANGLE = 0x800,
886};
887} // end namespace AArch64II
888
889//===----------------------------------------------------------------------===//
890// v8.3a Pointer Authentication
891//
892
893namespace AArch64PACKey {
894enum ID : uint8_t {
895 IA = 0,
896 IB = 1,
897 DA = 2,
898 DB = 3,
899 LAST = DB
900};
901} // namespace AArch64PACKey
902
903/// Return 2-letter identifier string for numeric key ID.
904inline static StringRef AArch64PACKeyIDToString(AArch64PACKey::ID KeyID) {
905 switch (KeyID) {
906 case AArch64PACKey::IA:
907 return StringRef("ia");
908 case AArch64PACKey::IB:
909 return StringRef("ib");
910 case AArch64PACKey::DA:
911 return StringRef("da");
912 case AArch64PACKey::DB:
913 return StringRef("db");
914 }
915 llvm_unreachable("Unhandled AArch64PACKey::ID enum");
916}
917
918/// Return numeric key ID for 2-letter identifier string.
919inline static std::optional<AArch64PACKey::ID>
920AArch64StringToPACKeyID(StringRef Name) {
921 if (Name == "ia")
922 return AArch64PACKey::IA;
923 if (Name == "ib")
924 return AArch64PACKey::IB;
925 if (Name == "da")
926 return AArch64PACKey::DA;
927 if (Name == "db")
928 return AArch64PACKey::DB;
929 return std::nullopt;
930}
931
932namespace AArch64 {
933// The number of bits in a SVE register is architecturally defined
934// to be a multiple of this value. If <M x t> has this number of bits,
935// a <n x M x t> vector can be stored in a SVE register without any
936// redundant bits. If <M x t> has this number of bits divided by P,
937// a <n x M x t> vector is stored in a SVE register by placing index i
938// in index i*P of a <n x (M*P) x t> vector. The other elements of the
939// <n x (M*P) x t> vector (such as index 1) are undefined.
940static constexpr unsigned SVEBitsPerBlock = 128;
941static constexpr unsigned SVEMaxBitsPerVector = 2048;
942} // end namespace AArch64
943} // end namespace llvm
944
945#endif
946