1 | //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | /// \file |
10 | /// Contains the definition of a TargetInstrInfo class that is common |
11 | /// to all AMD GPUs. |
12 | // |
13 | //===----------------------------------------------------------------------===// |
14 | |
15 | #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H |
16 | #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H |
17 | |
18 | #include "Utils/AMDGPUBaseInfo.h" |
19 | |
20 | namespace llvm { |
21 | |
22 | class GCNSubtarget; |
23 | class MachineMemOperand; |
24 | class MachineInstr; |
25 | |
26 | namespace AMDGPU { |
27 | |
28 | bool isUniformMMO(const MachineMemOperand *MMO); |
29 | |
30 | /// Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix. |
31 | /// |
32 | /// These opcodes have an Intrinsic::ID operand similar to a GIntrinsic. But |
33 | /// they are not actual instances of GIntrinsics, so we cannot use |
34 | /// GIntrinsic::getIntrinsicID() on them. |
35 | Intrinsic::ID getIntrinsicID(const MachineInstr &I); |
36 | |
37 | struct RsrcIntrinsic { |
38 | unsigned Intr; |
39 | uint8_t RsrcArg; |
40 | bool IsImage; |
41 | }; |
42 | const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr); |
43 | |
44 | struct D16ImageDimIntrinsic { |
45 | unsigned Intr; |
46 | unsigned D16HelperIntr; |
47 | }; |
48 | const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr); |
49 | |
50 | struct ImageDimIntrinsicInfo { |
51 | unsigned Intr; |
52 | unsigned BaseOpcode; |
53 | MIMGDim Dim; |
54 | |
55 | uint8_t NumOffsetArgs; |
56 | uint8_t NumBiasArgs; |
57 | uint8_t NumZCompareArgs; |
58 | uint8_t NumGradients; |
59 | uint8_t NumDmask; |
60 | uint8_t NumData; |
61 | uint8_t NumVAddrs; |
62 | uint8_t NumArgs; |
63 | |
64 | uint8_t DMaskIndex; |
65 | uint8_t VAddrStart; |
66 | uint8_t OffsetIndex; |
67 | uint8_t BiasIndex; |
68 | uint8_t ZCompareIndex; |
69 | uint8_t GradientStart; |
70 | uint8_t CoordStart; |
71 | uint8_t LodIndex; |
72 | uint8_t MipIndex; |
73 | uint8_t VAddrEnd; |
74 | uint8_t RsrcIndex; |
75 | uint8_t SampIndex; |
76 | uint8_t UnormIndex; |
77 | uint8_t TexFailCtrlIndex; |
78 | uint8_t CachePolicyIndex; |
79 | |
80 | uint8_t BiasTyArg; |
81 | uint8_t GradientTyArg; |
82 | uint8_t CoordTyArg; |
83 | }; |
84 | const ImageDimIntrinsicInfo *getImageDimIntrinsicInfo(unsigned Intr); |
85 | |
86 | const ImageDimIntrinsicInfo * |
87 | getImageDimIntrinsicByBaseOpcode(unsigned BaseOpcode, unsigned Dim); |
88 | |
89 | } // end AMDGPU namespace |
90 | } // End llvm namespace |
91 | |
92 | #endif |
93 | |