1//===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// R600 DAG Lowering interface definition
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
15#define LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
16
17#include "AMDGPUISelLowering.h"
18#include "llvm/CodeGen/MachineFunction.h"
19
20namespace llvm {
21
22class R600Subtarget;
23
24class R600TargetLowering final : public AMDGPUTargetLowering {
25
26 const R600Subtarget *Subtarget;
27public:
28 R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI);
29
30 const R600Subtarget *getSubtarget() const;
31
32 MachineBasicBlock *
33 EmitInstrWithCustomInserter(MachineInstr &MI,
34 MachineBasicBlock *BB) const override;
35 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
36 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
37 void ReplaceNodeResults(SDNode * N,
38 SmallVectorImpl<SDValue> &Results,
39 SelectionDAG &DAG) const override;
40 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
41 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
42 bool isVarArg,
43 const SmallVectorImpl<ISD::InputArg> &Ins,
44 const SDLoc &DL, SelectionDAG &DAG,
45 SmallVectorImpl<SDValue> &InVals) const override;
46 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
47 EVT VT) const override;
48
49 bool canMergeStoresTo(unsigned AS, EVT MemVT,
50 const MachineFunction &MF) const override;
51
52 bool allowsMisalignedMemoryAccesses(
53 EVT VT, unsigned AS, Align Alignment,
54 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
55 unsigned *IsFast = nullptr) const override;
56
57 bool canCombineTruncStore(EVT ValVT, EVT MemVT,
58 bool LegalOperations) const override {
59 // R600 has "custom" lowering for truncating stores despite not supporting
60 // those instructions. If we allow that custom lowering in the DAG combiner
61 // then all truncates are merged into truncating stores, giving worse code
62 // generation. This hook prevents the DAG combiner performing that combine.
63 return isTruncStoreLegal(ValVT, MemVT);
64 }
65
66private:
67 unsigned Gen;
68 /// Each OpenCL kernel has nine implicit parameters that are stored in the
69 /// first nine dwords of a Vertex Buffer. These implicit parameters are
70 /// lowered to load instructions which retrieve the values from the Vertex
71 /// Buffer.
72 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
73 unsigned DwordOffset) const;
74
75 void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
76 MachineRegisterInfo & MRI, unsigned dword_offset) const;
77 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[],
78 SelectionDAG &DAG, const SDLoc &DL) const;
79 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
80
81 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
85 SelectionDAG &DAG) const override;
86 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
87
88 SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
89 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
90 SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
91 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
92
93 SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
95 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
96 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
97 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
98 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
99 SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
100 unsigned mainop, unsigned ovf) const;
101
102 SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
103 SelectionDAG &DAG) const;
104 void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
105 unsigned &Channel, unsigned &PtrIncr) const;
106 bool isZero(SDValue Op) const;
107 bool isHWTrueValue(SDValue Op) const;
108 bool isHWFalseValue(SDValue Op) const;
109
110 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
111 SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
112 SelectionDAG &DAG) const;
113 SDValue constBufferLoad(LoadSDNode *LoadNode, int Block,
114 SelectionDAG &DAG) const;
115
116 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
117
118 TargetLowering::AtomicExpansionKind
119 shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const override;
120};
121
122} // End namespace llvm;
123
124#endif
125