1//===-- SILowerI1Copies.h --------------------------------------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition of the PhiLoweringHelper class that implements lane
11/// mask merging algorithm for divergent i1 phis.
12//
13//===----------------------------------------------------------------------===//
14
15#include "GCNSubtarget.h"
16#include "llvm/CodeGen/MachineBasicBlock.h"
17#include "llvm/CodeGen/MachinePostDominators.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/CodeGen/MachineSSAUpdater.h"
20
21namespace llvm {
22
23/// Incoming for lane maks phi as machine instruction, incoming register \p Reg
24/// and incoming block \p Block are taken from machine instruction.
25/// \p UpdatedReg (if valid) is \p Reg lane mask merged with another lane mask.
26struct Incoming {
27 Register Reg;
28 MachineBasicBlock *Block;
29 Register UpdatedReg;
30
31 Incoming(Register Reg, MachineBasicBlock *Block, Register UpdatedReg)
32 : Reg(Reg), Block(Block), UpdatedReg(UpdatedReg) {}
33};
34
35Register createLaneMaskReg(MachineRegisterInfo *MRI,
36 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs);
37
38class PhiLoweringHelper {
39public:
40 PhiLoweringHelper(MachineFunction *MF, MachineDominatorTree *DT,
41 MachinePostDominatorTree *PDT);
42 virtual ~PhiLoweringHelper() = default;
43
44protected:
45 bool IsWave32 = false;
46 MachineFunction *MF = nullptr;
47 MachineDominatorTree *DT = nullptr;
48 MachinePostDominatorTree *PDT = nullptr;
49 MachineRegisterInfo *MRI = nullptr;
50 const GCNSubtarget *ST = nullptr;
51 const SIInstrInfo *TII = nullptr;
52 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs;
53
54#ifndef NDEBUG
55 DenseSet<Register> PhiRegisters;
56#endif
57
58 Register ExecReg;
59 unsigned MovOp;
60 unsigned AndOp;
61 unsigned OrOp;
62 unsigned XorOp;
63 unsigned AndN2Op;
64 unsigned OrN2Op;
65
66public:
67 bool lowerPhis();
68 bool isConstantLaneMask(Register Reg, bool &Val) const;
69 MachineBasicBlock::iterator
70 getSaluInsertionAtEnd(MachineBasicBlock &MBB) const;
71
72 void initializeLaneMaskRegisterAttributes(Register LaneMask) {
73 LaneMaskRegAttrs = MRI->getVRegAttrs(Reg: LaneMask);
74 }
75
76 void
77 initializeLaneMaskRegisterAttributes(MachineRegisterInfo::VRegAttrs Attrs) {
78 LaneMaskRegAttrs = Attrs;
79 }
80
81 bool isLaneMaskReg(Register Reg) const {
82 return TII->getRegisterInfo().isSGPRReg(MRI: *MRI, Reg) &&
83 TII->getRegisterInfo().getRegSizeInBits(Reg, MRI: *MRI) ==
84 ST->getWavefrontSize();
85 }
86
87 // Helpers from lowerPhis that are different between sdag and global-isel.
88
89 virtual void markAsLaneMask(Register DstReg) const = 0;
90 virtual void getCandidatesForLowering(
91 SmallVectorImpl<MachineInstr *> &Vreg1Phis) const = 0;
92 virtual void
93 collectIncomingValuesFromPhi(const MachineInstr *MI,
94 SmallVectorImpl<Incoming> &Incomings) const = 0;
95 virtual void replaceDstReg(Register NewReg, Register OldReg,
96 MachineBasicBlock *MBB) = 0;
97 virtual void buildMergeLaneMasks(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator I,
99 const DebugLoc &DL, Register DstReg,
100 Register PrevReg, Register CurReg) = 0;
101 virtual void constrainAsLaneMask(Incoming &In) = 0;
102};
103
104} // end namespace llvm
105