1//=- LoongArchInstrInfo.h - LoongArch Instruction Information ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
14#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
15
16#include "LoongArchRegisterInfo.h"
17#include "llvm/CodeGen/TargetInstrInfo.h"
18
19#define GET_INSTRINFO_HEADER
20#include "LoongArchGenInstrInfo.inc"
21
22namespace llvm {
23
24class LoongArchSubtarget;
25
26class LoongArchInstrInfo : public LoongArchGenInstrInfo {
27public:
28 explicit LoongArchInstrInfo(LoongArchSubtarget &STI);
29
30 MCInst getNop() const override;
31
32 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
33 const DebugLoc &DL, Register DstReg, Register SrcReg,
34 bool KillSrc, bool RenamableDest = false,
35 bool RenamableSrc = false) const override;
36
37 void storeRegToStackSlot(
38 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
39 bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
40 const TargetRegisterInfo *TRI, Register VReg,
41 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
42 void loadRegFromStackSlot(
43 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg,
44 int FrameIndex, const TargetRegisterClass *RC,
45 const TargetRegisterInfo *TRI, Register VReg,
46 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
47
48 // Materializes the given integer Val into DstReg.
49 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
50 const DebugLoc &DL, Register DstReg, uint64_t Val,
51 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
52
53 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
54
55 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
56
57 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
58
59 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
60 MachineBasicBlock *&FBB,
61 SmallVectorImpl<MachineOperand> &Cond,
62 bool AllowModify) const override;
63
64 bool isBranchOffsetInRange(unsigned BranchOpc,
65 int64_t BrOffset) const override;
66
67 bool isSchedulingBoundary(const MachineInstr &MI,
68 const MachineBasicBlock *MBB,
69 const MachineFunction &MF) const override;
70
71 unsigned removeBranch(MachineBasicBlock &MBB,
72 int *BytesRemoved = nullptr) const override;
73
74 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
75 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
76 const DebugLoc &dl,
77 int *BytesAdded = nullptr) const override;
78
79 void insertIndirectBranch(MachineBasicBlock &MBB,
80 MachineBasicBlock &NewDestBB,
81 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
82 int64_t BrOffset, RegScavenger *RS) const override;
83
84 bool
85 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
86
87 std::pair<unsigned, unsigned>
88 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
89
90 ArrayRef<std::pair<unsigned, const char *>>
91 getSerializableDirectMachineOperandTargetFlags() const override;
92
93 ArrayRef<std::pair<unsigned, const char *>>
94 getSerializableBitmaskMachineOperandTargetFlags() const override;
95
96protected:
97 const LoongArchSubtarget &STI;
98};
99
100namespace LoongArch {
101
102// Returns true if this is the sext.w pattern, addi.w rd, rs, 0.
103bool isSEXT_W(const MachineInstr &MI);
104
105// Mask assignments for floating-point.
106static constexpr unsigned FClassMaskSignalingNaN = 0x001;
107static constexpr unsigned FClassMaskQuietNaN = 0x002;
108static constexpr unsigned FClassMaskNegativeInfinity = 0x004;
109static constexpr unsigned FClassMaskNegativeNormal = 0x008;
110static constexpr unsigned FClassMaskNegativeSubnormal = 0x010;
111static constexpr unsigned FClassMaskNegativeZero = 0x020;
112static constexpr unsigned FClassMaskPositiveInfinity = 0x040;
113static constexpr unsigned FClassMaskPositiveNormal = 0x080;
114static constexpr unsigned FClassMaskPositiveSubnormal = 0x100;
115static constexpr unsigned FClassMaskPositiveZero = 0x200;
116} // namespace LoongArch
117
118} // end namespace llvm
119#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
120