1//===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Subclass of MipsTargetLowering specialized for mips32/64.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
15
16#include "MipsISelLowering.h"
17#include "llvm/CodeGen/SelectionDAGNodes.h"
18#include "llvm/CodeGenTypes/MachineValueType.h"
19
20namespace llvm {
21
22class MachineBasicBlock;
23class MachineInstr;
24class MipsSubtarget;
25class MipsTargetMachine;
26class SelectionDAG;
27class TargetRegisterClass;
28
29 class MipsSETargetLowering : public MipsTargetLowering {
30 public:
31 explicit MipsSETargetLowering(const MipsTargetMachine &TM,
32 const MipsSubtarget &STI);
33
34 /// Enable MSA support for the given integer type and Register
35 /// class.
36 void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
37
38 /// Enable MSA support for the given floating-point type and
39 /// Register class.
40 void addMSAFloatType(MVT::SimpleValueType Ty,
41 const TargetRegisterClass *RC);
42
43 bool allowsMisalignedMemoryAccesses(
44 EVT VT, unsigned AS = 0, Align Alignment = Align(1),
45 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
46 unsigned *Fast = nullptr) const override;
47
48 TargetLoweringBase::LegalizeTypeAction
49 getPreferredVectorAction(MVT VT) const override;
50
51 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
52
53 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
54
55 MachineBasicBlock *
56 EmitInstrWithCustomInserter(MachineInstr &MI,
57 MachineBasicBlock *MBB) const override;
58
59 bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override {
60 return false;
61 }
62
63 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
64
65 private:
66 bool isEligibleForTailCallOptimization(
67 const CCState &CCInfo, unsigned NextStackOffset,
68 const MipsFunctionInfo &FI) const override;
69
70 void
71 getOpndList(SmallVectorImpl<SDValue> &Ops,
72 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
73 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
74 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
75 SDValue Chain) const override;
76
77 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
78 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
79 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
80
81 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
82 SelectionDAG &DAG) const;
83
84 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
85 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
86 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
87 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
88 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
89 /// Lower VECTOR_SHUFFLE into one of a number of instructions
90 /// depending on the indices in the shuffle.
91 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
92 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
93
94 MachineBasicBlock *emitBPOSGE32(MachineInstr &MI,
95 MachineBasicBlock *BB) const;
96 MachineBasicBlock *emitMSACBranchPseudo(MachineInstr &MI,
97 MachineBasicBlock *BB,
98 unsigned BranchOp) const;
99 /// Emit the COPY_FW pseudo instruction
100 MachineBasicBlock *emitCOPY_FW(MachineInstr &MI,
101 MachineBasicBlock *BB) const;
102 /// Emit the COPY_FD pseudo instruction
103 MachineBasicBlock *emitCOPY_FD(MachineInstr &MI,
104 MachineBasicBlock *BB) const;
105 /// Emit the INSERT_FW pseudo instruction
106 MachineBasicBlock *emitINSERT_FW(MachineInstr &MI,
107 MachineBasicBlock *BB) const;
108 /// Emit the INSERT_FD pseudo instruction
109 MachineBasicBlock *emitINSERT_FD(MachineInstr &MI,
110 MachineBasicBlock *BB) const;
111 /// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
112 MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr &MI,
113 MachineBasicBlock *BB,
114 unsigned EltSizeInBytes,
115 bool IsFP) const;
116 /// Emit the FILL_FW pseudo instruction
117 MachineBasicBlock *emitFILL_FW(MachineInstr &MI,
118 MachineBasicBlock *BB) const;
119 /// Emit the FILL_FD pseudo instruction
120 MachineBasicBlock *emitFILL_FD(MachineInstr &MI,
121 MachineBasicBlock *BB) const;
122 /// Emit the FEXP2_W_1 pseudo instructions.
123 MachineBasicBlock *emitFEXP2_W_1(MachineInstr &MI,
124 MachineBasicBlock *BB) const;
125 /// Emit the FEXP2_D_1 pseudo instructions.
126 MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI,
127 MachineBasicBlock *BB) const;
128 /// Emit the FILL_FW pseudo instruction
129 MachineBasicBlock *emitLD_F16_PSEUDO(MachineInstr &MI,
130 MachineBasicBlock *BB) const;
131 /// Emit the FILL_FD pseudo instruction
132 MachineBasicBlock *emitST_F16_PSEUDO(MachineInstr &MI,
133 MachineBasicBlock *BB) const;
134 /// Emit the FEXP2_W_1 pseudo instructions.
135 MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI,
136 MachineBasicBlock *BB,
137 bool IsFGR64) const;
138 /// Emit the FEXP2_D_1 pseudo instructions.
139 MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI,
140 MachineBasicBlock *BBi,
141 bool IsFGR64) const;
142 };
143
144} // end namespace llvm
145
146#endif // LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
147