1//===-- PPCFrameLowering.h - Define frame lowering for PowerPC --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#ifndef LLVM_LIB_TARGET_POWERPC_PPCFRAMELOWERING_H
13#define LLVM_LIB_TARGET_POWERPC_PPCFRAMELOWERING_H
14
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/CodeGen/TargetFrameLowering.h"
17#include "llvm/Target/TargetMachine.h"
18
19namespace llvm {
20class PPCSubtarget;
21
22class PPCFrameLowering: public TargetFrameLowering {
23 const PPCSubtarget &Subtarget;
24 const uint64_t ReturnSaveOffset;
25 const uint64_t TOCSaveOffset;
26 const uint64_t FramePointerSaveOffset;
27 const unsigned LinkageSize;
28 const uint64_t BasePointerSaveOffset;
29 const uint64_t CRSaveOffset;
30
31 // Map each group of one or two GPRs to corresponding VSR for spilling.
32 // TODO: Use local table in methods to avoid this mutable member.
33 mutable DenseMap<unsigned, std::pair<Register, Register>> VSRContainingGPRs;
34
35 /**
36 * Find register[s] that can be used in function prologue and epilogue
37 *
38 * Find register[s] that can be use as scratch register[s] in function
39 * prologue and epilogue to save various registers (Link Register, Base
40 * Pointer, etc.). Prefer R0/R12, if available. Otherwise choose whatever
41 * register[s] are available.
42 *
43 * This method will return true if it is able to find enough unique scratch
44 * registers (1 or 2 depending on the requirement). If it is unable to find
45 * enough available registers in the block, it will return false and set
46 * any passed output parameter that corresponds to a required unique register
47 * to PPC::NoRegister.
48 *
49 * \param[in] MBB The machine basic block to find an available register for
50 * \param[in] UseAtEnd Specify whether the scratch register will be used at
51 * the end of the basic block (i.e., will the scratch
52 * register kill a register defined in the basic block)
53 * \param[in] TwoUniqueRegsRequired Specify whether this basic block will
54 * require two unique scratch registers.
55 * \param[out] SR1 The scratch register to use
56 * \param[out] SR2 The second scratch register. If this pointer is not null
57 * the function will attempt to set it to an available
58 * register regardless of whether there is a hard requirement
59 * for two unique scratch registers.
60 * \return true if the required number of registers was found.
61 * false if the required number of scratch register weren't available.
62 * If either output parameter refers to a required scratch register
63 * that isn't available, it will be set to an invalid value.
64 */
65 bool findScratchRegister(MachineBasicBlock *MBB,
66 bool UseAtEnd,
67 bool TwoUniqueRegsRequired = false,
68 Register *SR1 = nullptr,
69 Register *SR2 = nullptr) const;
70 bool twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const;
71
72 /**
73 * Create branch instruction for PPC::TCRETURN* (tail call return)
74 *
75 * \param[in] MBB that is terminated by PPC::TCRETURN*
76 */
77 void createTailCallBranchInstr(MachineBasicBlock &MBB) const;
78
79 /**
80 * Check if the conditions are correct to allow for the stack update
81 * to be moved past the CSR save/restore code.
82 */
83 bool stackUpdateCanBeMoved(MachineFunction &MF) const;
84
85public:
86 PPCFrameLowering(const PPCSubtarget &STI);
87
88 /**
89 * Determine the frame layout and update the machine function.
90 */
91 uint64_t determineFrameLayoutAndUpdate(MachineFunction &MF,
92 bool UseEstimate = false) const;
93
94 /**
95 * Determine the frame layout but do not update the machine function.
96 * The MachineFunction object can be const in this case as it is not
97 * modified.
98 */
99 uint64_t determineFrameLayout(const MachineFunction &MF,
100 bool UseEstimate = false,
101 unsigned *NewMaxCallFrameSize = nullptr) const;
102
103 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
104 /// the function.
105 void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
106 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
107 void inlineStackProbe(MachineFunction &MF,
108 MachineBasicBlock &PrologMBB) const override;
109
110 bool needsFP(const MachineFunction &MF) const;
111 void replaceFPWithRealFP(MachineFunction &MF) const;
112
113 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
114 RegScavenger *RS = nullptr) const override;
115 void processFunctionBeforeFrameFinalized(MachineFunction &MF,
116 RegScavenger *RS = nullptr) const override;
117 void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
118
119 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
120 MachineBasicBlock::iterator MI,
121 ArrayRef<CalleeSavedInfo> CSI,
122 const TargetRegisterInfo *TRI) const override;
123 /// This function will assign callee saved gprs to volatile vector registers
124 /// for prologue spills when applicable. It returns false if there are any
125 /// registers which were not spilled to volatile vector registers.
126 bool
127 assignCalleeSavedSpillSlots(MachineFunction &MF,
128 const TargetRegisterInfo *TRI,
129 std::vector<CalleeSavedInfo> &CSI) const override;
130
131 MachineBasicBlock::iterator
132 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
133 MachineBasicBlock::iterator I) const override;
134
135 bool
136 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
137 MachineBasicBlock::iterator MI,
138 MutableArrayRef<CalleeSavedInfo> CSI,
139 const TargetRegisterInfo *TRI) const override;
140
141 /// targetHandlesStackFrameRounding - Returns true if the target is
142 /// responsible for rounding up the stack frame (probably at emitPrologue
143 /// time).
144 bool targetHandlesStackFrameRounding() const override { return true; }
145
146 /// getReturnSaveOffset - Return the previous frame offset to save the
147 /// return address.
148 uint64_t getReturnSaveOffset() const { return ReturnSaveOffset; }
149
150 /// getTOCSaveOffset - Return the previous frame offset to save the
151 /// TOC register -- 64-bit SVR4 ABI only.
152 uint64_t getTOCSaveOffset() const;
153
154 /// getFramePointerSaveOffset - Return the previous frame offset to save the
155 /// frame pointer.
156 uint64_t getFramePointerSaveOffset() const;
157
158 /// getBasePointerSaveOffset - Return the previous frame offset to save the
159 /// base pointer.
160 uint64_t getBasePointerSaveOffset() const;
161
162 /// getLinkageSize - Return the size of the PowerPC ABI linkage area.
163 ///
164 unsigned getLinkageSize() const { return LinkageSize; }
165
166 const SpillSlot *
167 getCalleeSavedSpillSlots(unsigned &NumEntries) const override;
168
169 bool enableShrinkWrapping(const MachineFunction &MF) const override;
170
171 /// Methods used by shrink wrapping to determine if MBB can be used for the
172 /// function prologue/epilogue.
173 bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
174 bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override;
175 void updateCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const;
176
177 uint64_t getStackThreshold() const override;
178
179protected:
180 bool hasFPImpl(const MachineFunction &MF) const override;
181};
182} // End llvm namespace
183
184#endif
185