1//===-- PPCTOCRegDeps.cpp - Add Extra TOC Register Dependencies -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// When resolving an address using the ELF ABI TOC pointer, two relocations are
10// generally required: one for the high part and one for the low part. Only
11// the high part generally explicitly depends on r2 (the TOC pointer). And, so,
12// we might produce code like this:
13//
14// .Ltmp526:
15// addis 3, 2, .LC12@toc@ha
16// .Ltmp1628:
17// std 2, 40(1)
18// ld 5, 0(27)
19// ld 2, 8(27)
20// ld 11, 16(27)
21// ld 3, .LC12@toc@l(3)
22// rldicl 4, 4, 0, 32
23// mtctr 5
24// bctrl
25// ld 2, 40(1)
26//
27// And there is nothing wrong with this code, as such, but there is a linker bug
28// in binutils (https://sourceware.org/bugzilla/show_bug.cgi?id=18414) that will
29// misoptimize this code sequence to this:
30// nop
31// std r2,40(r1)
32// ld r5,0(r27)
33// ld r2,8(r27)
34// ld r11,16(r27)
35// ld r3,-32472(r2)
36// clrldi r4,r4,32
37// mtctr r5
38// bctrl
39// ld r2,40(r1)
40// because the linker does not know (and does not check) that the value in r2
41// changed in between the instruction using the .LC12@toc@ha (TOC-relative)
42// relocation and the instruction using the .LC12@toc@l(3) relocation.
43// Because it finds these instructions using the relocations (and not by
44// scanning the instructions), it has been asserted that there is no good way
45// to detect the change of r2 in between. As a result, this bug may never be
46// fixed (i.e. it may become part of the definition of the ABI). GCC was
47// updated to add extra dependencies on r2 to instructions using the @toc@l
48// relocations to avoid this problem, and we'll do the same here.
49//
50// This is done as a separate pass because:
51// 1. These extra r2 dependencies are not really properties of the
52// instructions, but rather due to a linker bug, and maybe one day we'll be
53// able to get rid of them when targeting linkers without this bug (and,
54// thus, keeping the logic centralized here will make that
55// straightforward).
56// 2. There are ISel-level peephole optimizations that propagate the @toc@l
57// relocations to some user instructions, and so the exta dependencies do
58// not apply only to a fixed set of instructions (without undesirable
59// definition replication).
60//
61//===----------------------------------------------------------------------===//
62
63#include "PPC.h"
64#include "PPCInstrInfo.h"
65#include "PPCTargetMachine.h"
66#include "llvm/ADT/STLExtras.h"
67#include "llvm/ADT/Statistic.h"
68#include "llvm/CodeGen/MachineFrameInfo.h"
69#include "llvm/CodeGen/MachineFunctionPass.h"
70#include "llvm/CodeGen/MachineInstr.h"
71#include "llvm/Support/ErrorHandling.h"
72
73using namespace llvm;
74
75#define DEBUG_TYPE "ppc-toc-reg-deps"
76
77namespace {
78 // PPCTOCRegDeps pass - For simple functions without epilogue code, move
79 // returns up, and create conditional returns, to avoid unnecessary
80 // branch-to-blr sequences.
81 struct PPCTOCRegDeps : public MachineFunctionPass {
82 static char ID;
83 PPCTOCRegDeps() : MachineFunctionPass(ID) {}
84
85 protected:
86 bool hasTOCLoReloc(const MachineInstr &MI) {
87 if (MI.getOpcode() == PPC::LDtocL || MI.getOpcode() == PPC::ADDItocL8 ||
88 MI.getOpcode() == PPC::LWZtocL)
89 return true;
90
91 for (const MachineOperand &MO : MI.operands()) {
92 if (MO.getTargetFlags() == PPCII::MO_TOC_LO)
93 return true;
94 }
95
96 return false;
97 }
98
99 bool processBlock(MachineBasicBlock &MBB) {
100 bool Changed = false;
101
102 const bool isPPC64 =
103 MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
104 const unsigned TOCReg = isPPC64 ? PPC::X2 : PPC::R2;
105
106 for (auto &MI : MBB) {
107 if (!hasTOCLoReloc(MI))
108 continue;
109
110 MI.addOperand(Op: MachineOperand::CreateReg(Reg: TOCReg,
111 isDef: false /*IsDef*/,
112 isImp: true /*IsImp*/));
113 Changed = true;
114 }
115
116 return Changed;
117 }
118
119public:
120 bool runOnMachineFunction(MachineFunction &MF) override {
121 bool Changed = false;
122
123 for (MachineBasicBlock &B : llvm::make_early_inc_range(Range&: MF))
124 if (processBlock(MBB&: B))
125 Changed = true;
126
127 return Changed;
128 }
129
130 void getAnalysisUsage(AnalysisUsage &AU) const override {
131 MachineFunctionPass::getAnalysisUsage(AU);
132 }
133 };
134}
135
136INITIALIZE_PASS(PPCTOCRegDeps, DEBUG_TYPE,
137 "PowerPC TOC Register Dependencies", false, false)
138
139char PPCTOCRegDeps::ID = 0;
140FunctionPass*
141llvm::createPPCTOCRegDepsPass() { return new PPCTOCRegDeps(); }
142
143