| 1 | //===-- PPCTargetTransformInfo.h - PPC specific TTI -------------*- C++ -*-===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | /// \file |
| 9 | /// This file a TargetTransformInfoImplBase conforming object specific to the |
| 10 | /// PPC target machine. It uses the target's detailed information to |
| 11 | /// provide more precise answers to certain TTI queries, while letting the |
| 12 | /// target independent and default TTI implementations handle the rest. |
| 13 | /// |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
| 16 | #ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H |
| 17 | #define LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H |
| 18 | |
| 19 | #include "PPCTargetMachine.h" |
| 20 | #include "llvm/Analysis/TargetTransformInfo.h" |
| 21 | #include "llvm/CodeGen/BasicTTIImpl.h" |
| 22 | #include "llvm/CodeGen/TargetLowering.h" |
| 23 | #include <optional> |
| 24 | |
| 25 | namespace llvm { |
| 26 | |
| 27 | class PPCTTIImpl final : public BasicTTIImplBase<PPCTTIImpl> { |
| 28 | typedef BasicTTIImplBase<PPCTTIImpl> BaseT; |
| 29 | typedef TargetTransformInfo TTI; |
| 30 | friend BaseT; |
| 31 | |
| 32 | const PPCSubtarget *ST; |
| 33 | const PPCTargetLowering *TLI; |
| 34 | |
| 35 | const PPCSubtarget *getST() const { return ST; } |
| 36 | const PPCTargetLowering *getTLI() const { return TLI; } |
| 37 | |
| 38 | public: |
| 39 | explicit PPCTTIImpl(const PPCTargetMachine *TM, const Function &F) |
| 40 | : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)), |
| 41 | TLI(ST->getTargetLowering()) {} |
| 42 | |
| 43 | std::optional<Instruction *> |
| 44 | instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override; |
| 45 | |
| 46 | /// \name Scalar TTI Implementations |
| 47 | /// @{ |
| 48 | |
| 49 | using BaseT::getIntImmCost; |
| 50 | InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, |
| 51 | TTI::TargetCostKind CostKind) const override; |
| 52 | |
| 53 | InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, |
| 54 | const APInt &Imm, Type *Ty, |
| 55 | TTI::TargetCostKind CostKind, |
| 56 | Instruction *Inst = nullptr) const override; |
| 57 | InstructionCost |
| 58 | getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, |
| 59 | Type *Ty, TTI::TargetCostKind CostKind) const override; |
| 60 | |
| 61 | InstructionCost |
| 62 | getInstructionCost(const User *U, ArrayRef<const Value *> Operands, |
| 63 | TTI::TargetCostKind CostKind) const override; |
| 64 | |
| 65 | TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override; |
| 66 | bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, |
| 67 | AssumptionCache &AC, TargetLibraryInfo *LibInfo, |
| 68 | HardwareLoopInfo &HWLoopInfo) const override; |
| 69 | bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, |
| 70 | DominatorTree *DT, AssumptionCache *AC, |
| 71 | TargetLibraryInfo *LibInfo) const override; |
| 72 | bool getTgtMemIntrinsic(IntrinsicInst *Inst, |
| 73 | MemIntrinsicInfo &Info) const override; |
| 74 | void (Loop *L, ScalarEvolution &SE, |
| 75 | TTI::UnrollingPreferences &UP, |
| 76 | OptimizationRemarkEmitter *ORE) const override; |
| 77 | void getPeelingPreferences(Loop *L, ScalarEvolution &SE, |
| 78 | TTI::PeelingPreferences &PP) const override; |
| 79 | bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, |
| 80 | const TargetTransformInfo::LSRCost &C2) const override; |
| 81 | bool isNumRegsMajorCostOfLSR() const override; |
| 82 | bool shouldBuildRelLookupTables() const override; |
| 83 | /// @} |
| 84 | |
| 85 | /// \name Vector TTI Implementations |
| 86 | /// @{ |
| 87 | bool useColdCCForColdCall(Function &F) const override; |
| 88 | bool enableAggressiveInterleaving(bool LoopHasReductions) const override; |
| 89 | TTI::MemCmpExpansionOptions |
| 90 | enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override; |
| 91 | bool enableInterleavedAccessVectorization() const override; |
| 92 | |
| 93 | enum PPCRegisterClass { |
| 94 | GPRRC, FPRRC, VRRC, VSXRC |
| 95 | }; |
| 96 | unsigned getNumberOfRegisters(unsigned ClassID) const override; |
| 97 | unsigned getRegisterClassForType(bool Vector, |
| 98 | Type *Ty = nullptr) const override; |
| 99 | const char *getRegisterClassName(unsigned ClassID) const override; |
| 100 | TypeSize |
| 101 | getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override; |
| 102 | unsigned getCacheLineSize() const override; |
| 103 | unsigned getPrefetchDistance() const override; |
| 104 | unsigned getMaxInterleaveFactor(ElementCount VF) const override; |
| 105 | InstructionCost vectorCostAdjustmentFactor(unsigned Opcode, Type *Ty1, |
| 106 | Type *Ty2) const; |
| 107 | InstructionCost getArithmeticInstrCost( |
| 108 | unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, |
| 109 | TTI::OperandValueInfo Op1Info = {.Kind: TTI::OK_AnyValue, .Properties: TTI::OP_None}, |
| 110 | TTI::OperandValueInfo Op2Info = {.Kind: TTI::OK_AnyValue, .Properties: TTI::OP_None}, |
| 111 | ArrayRef<const Value *> Args = {}, |
| 112 | const Instruction *CxtI = nullptr) const override; |
| 113 | InstructionCost |
| 114 | getShuffleCost(TTI::ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy, |
| 115 | ArrayRef<int> Mask, TTI::TargetCostKind CostKind, int Index, |
| 116 | VectorType *SubTp, ArrayRef<const Value *> Args = {}, |
| 117 | const Instruction *CxtI = nullptr) const override; |
| 118 | InstructionCost |
| 119 | getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, |
| 120 | TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, |
| 121 | const Instruction *I = nullptr) const override; |
| 122 | InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, |
| 123 | const Instruction *I = nullptr) const override; |
| 124 | InstructionCost getCmpSelInstrCost( |
| 125 | unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, |
| 126 | TTI::TargetCostKind CostKind, |
| 127 | TTI::OperandValueInfo Op1Info = {.Kind: TTI::OK_AnyValue, .Properties: TTI::OP_None}, |
| 128 | TTI::OperandValueInfo Op2Info = {.Kind: TTI::OK_AnyValue, .Properties: TTI::OP_None}, |
| 129 | const Instruction *I = nullptr) const override; |
| 130 | using BaseT::getVectorInstrCost; |
| 131 | InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, |
| 132 | TTI::TargetCostKind CostKind, |
| 133 | unsigned Index, const Value *Op0, |
| 134 | const Value *Op1) const override; |
| 135 | InstructionCost getMemoryOpCost( |
| 136 | unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, |
| 137 | TTI::TargetCostKind CostKind, |
| 138 | TTI::OperandValueInfo OpInfo = {.Kind: TTI::OK_AnyValue, .Properties: TTI::OP_None}, |
| 139 | const Instruction *I = nullptr) const override; |
| 140 | InstructionCost getInterleavedMemoryOpCost( |
| 141 | unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, |
| 142 | Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, |
| 143 | bool UseMaskForCond = false, bool UseMaskForGaps = false) const override; |
| 144 | InstructionCost |
| 145 | getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, |
| 146 | TTI::TargetCostKind CostKind) const override; |
| 147 | bool areInlineCompatible(const Function *Caller, |
| 148 | const Function *Callee) const override; |
| 149 | bool areTypesABICompatible(const Function *Caller, const Function *Callee, |
| 150 | const ArrayRef<Type *> &Types) const override; |
| 151 | bool supportsTailCallFor(const CallBase *CB) const override; |
| 152 | |
| 153 | private: |
| 154 | // The following constant is used for estimating costs on power9. |
| 155 | static const InstructionCost::CostType P9PipelineFlushEstimate = 80; |
| 156 | |
| 157 | /// @} |
| 158 | }; |
| 159 | |
| 160 | } // end namespace llvm |
| 161 | |
| 162 | #endif |
| 163 | |