1//===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "SystemZMCTargetDesc.h"
10#include "SystemZGNUInstPrinter.h"
11#include "SystemZHLASMAsmStreamer.h"
12#include "SystemZHLASMInstPrinter.h"
13#include "SystemZMCAsmInfo.h"
14#include "SystemZTargetStreamer.h"
15#include "TargetInfo/SystemZTargetInfo.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDwarf.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstrAnalysis.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCStreamer.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Support/CommandLine.h"
26#include "llvm/Support/Compiler.h"
27
28using namespace llvm;
29
30#define GET_INSTRINFO_MC_DESC
31#define ENABLE_INSTR_PREDICATE_VERIFIER
32#include "SystemZGenInstrInfo.inc"
33
34#define GET_SUBTARGETINFO_MC_DESC
35#include "SystemZGenSubtargetInfo.inc"
36
37#define GET_REGINFO_MC_DESC
38#include "SystemZGenRegisterInfo.inc"
39
40// Temporary option to assist with the migration to a new HLASMAsmStreamer on
41// z/OS
42static cl::opt<bool> GNUAsOnzOSCL("emit-gnuas-syntax-on-zos",
43 cl::desc("Emit GNU Assembly Syntax on z/OS."),
44 cl::init(Val: true));
45
46const unsigned SystemZMC::GR32Regs[16] = {
47 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
48 SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
49 SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L,
50 SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L};
51
52const unsigned SystemZMC::GRH32Regs[16] = {
53 SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H,
54 SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H,
55 SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H,
56 SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H};
57
58const unsigned SystemZMC::GR64Regs[16] = {
59 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D,
60 SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D,
61 SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D,
62 SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D};
63
64const unsigned SystemZMC::GR128Regs[16] = {
65 SystemZ::R0Q, 0, SystemZ::R2Q, 0, SystemZ::R4Q, 0, SystemZ::R6Q, 0,
66 SystemZ::R8Q, 0, SystemZ::R10Q, 0, SystemZ::R12Q, 0, SystemZ::R14Q, 0};
67
68const unsigned SystemZMC::FP16Regs[16] = {
69 SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H,
70 SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H,
71 SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H,
72 SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H};
73
74const unsigned SystemZMC::FP32Regs[16] = {
75 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
76 SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
77 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
78 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S};
79
80const unsigned SystemZMC::FP64Regs[16] = {
81 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
82 SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
83 SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
84 SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D};
85
86const unsigned SystemZMC::FP128Regs[16] = {
87 SystemZ::F0Q, SystemZ::F1Q, 0, 0, SystemZ::F4Q, SystemZ::F5Q, 0, 0,
88 SystemZ::F8Q, SystemZ::F9Q, 0, 0, SystemZ::F12Q, SystemZ::F13Q, 0, 0};
89
90const unsigned SystemZMC::VR16Regs[32] = {
91 SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H,
92 SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F8H, SystemZ::F9H,
93 SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H,
94 SystemZ::F15H, SystemZ::F16H, SystemZ::F17H, SystemZ::F18H, SystemZ::F19H,
95 SystemZ::F20H, SystemZ::F21H, SystemZ::F22H, SystemZ::F23H, SystemZ::F24H,
96 SystemZ::F25H, SystemZ::F26H, SystemZ::F27H, SystemZ::F28H, SystemZ::F29H,
97 SystemZ::F30H, SystemZ::F31H};
98
99const unsigned SystemZMC::VR32Regs[32] = {
100 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S,
101 SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S,
102 SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S,
103 SystemZ::F15S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S,
104 SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S,
105 SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S,
106 SystemZ::F30S, SystemZ::F31S};
107
108const unsigned SystemZMC::VR64Regs[32] = {
109 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D,
110 SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D,
111 SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D,
112 SystemZ::F15D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D,
113 SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D,
114 SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D,
115 SystemZ::F30D, SystemZ::F31D};
116
117const unsigned SystemZMC::VR128Regs[32] = {
118 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4,
119 SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9,
120 SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14,
121 SystemZ::V15, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19,
122 SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24,
123 SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29,
124 SystemZ::V30, SystemZ::V31};
125
126const unsigned SystemZMC::AR32Regs[16] = {
127 SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3,
128 SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7,
129 SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11,
130 SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15};
131
132const unsigned SystemZMC::CR64Regs[16] = {
133 SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3,
134 SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7,
135 SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11,
136 SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15};
137
138unsigned SystemZMC::getFirstReg(unsigned Reg) {
139 static unsigned Map[SystemZ::NUM_TARGET_REGS];
140 static bool Initialized = false;
141 if (!Initialized) {
142 for (unsigned I = 0; I < 16; ++I) {
143 Map[GR32Regs[I]] = I;
144 Map[GRH32Regs[I]] = I;
145 Map[GR64Regs[I]] = I;
146 Map[GR128Regs[I]] = I;
147 Map[FP128Regs[I]] = I;
148 Map[AR32Regs[I]] = I;
149 }
150 for (unsigned I = 0; I < 32; ++I) {
151 Map[VR16Regs[I]] = I;
152 Map[VR32Regs[I]] = I;
153 Map[VR64Regs[I]] = I;
154 Map[VR128Regs[I]] = I;
155 }
156 }
157 assert(Reg < SystemZ::NUM_TARGET_REGS);
158 return Map[Reg];
159}
160
161static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
162 const Triple &TT,
163 const MCTargetOptions &Options) {
164 if (TT.isOSzOS())
165 return new SystemZMCAsmInfoGOFF(TT);
166
167 MCAsmInfo *MAI = new SystemZMCAsmInfoELF(TT);
168 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
169 L: nullptr, Register: MRI.getDwarfRegNum(RegNum: SystemZ::R15D, isEH: true),
170 Offset: SystemZMC::ELFCFAOffsetFromInitialSP);
171 MAI->addInitialFrameState(Inst);
172 return MAI;
173}
174
175static MCInstrInfo *createSystemZMCInstrInfo() {
176 MCInstrInfo *X = new MCInstrInfo();
177 InitSystemZMCInstrInfo(II: X);
178 return X;
179}
180
181static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) {
182 MCRegisterInfo *X = new MCRegisterInfo();
183 InitSystemZMCRegisterInfo(RI: X, RA: SystemZ::R14D);
184 return X;
185}
186
187static MCSubtargetInfo *
188createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
189 return createSystemZMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
190}
191
192static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
193 unsigned SyntaxVariant,
194 const MCAsmInfo &MAI,
195 const MCInstrInfo &MII,
196 const MCRegisterInfo &MRI) {
197 if (SyntaxVariant == AD_HLASM)
198 return new SystemZHLASMInstPrinter(MAI, MII, MRI);
199
200 return new SystemZGNUInstPrinter(MAI, MII, MRI);
201}
202
203static MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
204 formatted_raw_ostream &OS,
205 MCInstPrinter *InstPrint) {
206 if (S.getContext().getTargetTriple().isOSzOS() && !GNUAsOnzOSCL)
207 return new SystemZTargetHLASMStreamer(S, OS);
208 else
209 return new SystemZTargetGNUStreamer(S, OS);
210}
211
212static MCStreamer *createSystemZAsmStreamer(
213 MCContext &Ctx, std::unique_ptr<formatted_raw_ostream> OS,
214 std::unique_ptr<MCInstPrinter> IP, std::unique_ptr<MCCodeEmitter> CE,
215 std::unique_ptr<MCAsmBackend> TAB) {
216
217 auto TT = Ctx.getTargetTriple();
218 if (TT.isOSzOS() && !GNUAsOnzOSCL)
219 return new SystemZHLASMAsmStreamer(Ctx, std::move(OS), std::move(IP),
220 std::move(CE), std::move(TAB));
221
222 return llvm::createAsmStreamer(Ctx, OS: std::move(OS), InstPrint: std::move(IP),
223 CE: std::move(CE), TAB: std::move(TAB));
224}
225
226static MCTargetStreamer *
227createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
228 if (S.getContext().getTargetTriple().isOSzOS())
229 return new SystemZTargetGOFFStreamer(S);
230 else
231 return new SystemZTargetELFStreamer(S);
232}
233
234static MCTargetStreamer *
235createNullTargetStreamer(MCStreamer &S) {
236 return new SystemZTargetStreamer(S);
237}
238
239static MCInstrAnalysis *createSystemZMCInstrAnalysis(const MCInstrInfo *Info) {
240 return new MCInstrAnalysis(Info);
241}
242
243extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
244LLVMInitializeSystemZTargetMC() {
245 // Register the MCAsmInfo.
246 TargetRegistry::RegisterMCAsmInfo(T&: getTheSystemZTarget(),
247 Fn: createSystemZMCAsmInfo);
248
249 // Register the MCCodeEmitter.
250 TargetRegistry::RegisterMCCodeEmitter(T&: getTheSystemZTarget(),
251 Fn: createSystemZMCCodeEmitter);
252
253 // Register the MCInstrInfo.
254 TargetRegistry::RegisterMCInstrInfo(T&: getTheSystemZTarget(),
255 Fn: createSystemZMCInstrInfo);
256
257 // Register the MCRegisterInfo.
258 TargetRegistry::RegisterMCRegInfo(T&: getTheSystemZTarget(),
259 Fn: createSystemZMCRegisterInfo);
260
261 // Register the MCSubtargetInfo.
262 TargetRegistry::RegisterMCSubtargetInfo(T&: getTheSystemZTarget(),
263 Fn: createSystemZMCSubtargetInfo);
264
265 // Register the MCAsmBackend.
266 TargetRegistry::RegisterMCAsmBackend(T&: getTheSystemZTarget(),
267 Fn: createSystemZMCAsmBackend);
268
269 // Register the MCInstPrinter.
270 TargetRegistry::RegisterMCInstPrinter(T&: getTheSystemZTarget(),
271 Fn: createSystemZMCInstPrinter);
272
273 // Register the asm streamer.
274 TargetRegistry::RegisterAsmStreamer(T&: getTheSystemZTarget(),
275 Fn: createSystemZAsmStreamer);
276
277 // Register the asm target streamer.
278 TargetRegistry::RegisterAsmTargetStreamer(T&: getTheSystemZTarget(),
279 Fn: createAsmTargetStreamer);
280
281 // Register the obj streamer
282 TargetRegistry::RegisterObjectTargetStreamer(T&: getTheSystemZTarget(),
283 Fn: createObjectTargetStreamer);
284
285 // Register the null streamer
286 TargetRegistry::RegisterNullTargetStreamer(T&: getTheSystemZTarget(),
287 Fn: createNullTargetStreamer);
288
289 // Register the MCInstrAnalysis.
290 TargetRegistry::RegisterMCInstrAnalysis(T&: getTheSystemZTarget(),
291 Fn: createSystemZMCInstrAnalysis);
292}
293