1//===-- VEMCTargetDesc.cpp - VE Target Descriptions -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides VE specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "VEMCTargetDesc.h"
14#include "TargetInfo/VETargetInfo.h"
15#include "VEInstPrinter.h"
16#include "VEMCAsmInfo.h"
17#include "VETargetStreamer.h"
18#include "llvm/MC/MCInstrInfo.h"
19#include "llvm/MC/MCRegisterInfo.h"
20#include "llvm/MC/MCSubtargetInfo.h"
21#include "llvm/MC/TargetRegistry.h"
22#include "llvm/Support/Compiler.h"
23#include "llvm/Support/ErrorHandling.h"
24
25using namespace llvm;
26
27#define GET_INSTRINFO_MC_DESC
28#define ENABLE_INSTR_PREDICATE_VERIFIER
29#include "VEGenInstrInfo.inc"
30
31#define GET_SUBTARGETINFO_MC_DESC
32#include "VEGenSubtargetInfo.inc"
33
34#define GET_REGINFO_MC_DESC
35#include "VEGenRegisterInfo.inc"
36
37static MCAsmInfo *createVEMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT,
38 const MCTargetOptions &Options) {
39 MCAsmInfo *MAI = new VEELFMCAsmInfo(TT);
40 unsigned Reg = MRI.getDwarfRegNum(RegNum: VE::SX11, isEH: true);
41 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(L: nullptr, Register: Reg, Offset: 0);
42 MAI->addInitialFrameState(Inst);
43 return MAI;
44}
45
46static MCInstrInfo *createVEMCInstrInfo() {
47 MCInstrInfo *X = new MCInstrInfo();
48 InitVEMCInstrInfo(II: X);
49 return X;
50}
51
52static MCRegisterInfo *createVEMCRegisterInfo(const Triple &TT) {
53 MCRegisterInfo *X = new MCRegisterInfo();
54 InitVEMCRegisterInfo(RI: X, RA: VE::SX10);
55 return X;
56}
57
58static MCSubtargetInfo *createVEMCSubtargetInfo(const Triple &TT, StringRef CPU,
59 StringRef FS) {
60 if (CPU.empty())
61 CPU = "generic";
62 return createVEMCSubtargetInfoImpl(TT, CPU, /*TuneCPU=*/CPU, FS);
63}
64
65static MCTargetStreamer *
66createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
67 return new VETargetELFStreamer(S);
68}
69
70static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S,
71 formatted_raw_ostream &OS,
72 MCInstPrinter *InstPrint) {
73 return new VETargetAsmStreamer(S, OS);
74}
75
76static MCTargetStreamer *createNullTargetStreamer(MCStreamer &S) {
77 return new VETargetStreamer(S);
78}
79
80static MCInstPrinter *createVEMCInstPrinter(const Triple &T,
81 unsigned SyntaxVariant,
82 const MCAsmInfo &MAI,
83 const MCInstrInfo &MII,
84 const MCRegisterInfo &MRI) {
85 return new VEInstPrinter(MAI, MII, MRI);
86}
87
88extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVETargetMC() {
89 // Register the MC asm info.
90 RegisterMCAsmInfoFn X(getTheVETarget(), createVEMCAsmInfo);
91
92 for (Target *T : {&getTheVETarget()}) {
93 // Register the MC instruction info.
94 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createVEMCInstrInfo);
95
96 // Register the MC register info.
97 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createVEMCRegisterInfo);
98
99 // Register the MC subtarget info.
100 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createVEMCSubtargetInfo);
101
102 // Register the MC Code Emitter.
103 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createVEMCCodeEmitter);
104
105 // Register the asm backend.
106 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createVEAsmBackend);
107
108 // Register the object target streamer.
109 TargetRegistry::RegisterObjectTargetStreamer(T&: *T,
110 Fn: createObjectTargetStreamer);
111
112 // Register the asm streamer.
113 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createTargetAsmStreamer);
114
115 // Register the null streamer.
116 TargetRegistry::RegisterNullTargetStreamer(T&: *T, Fn: createNullTargetStreamer);
117
118 // Register the MCInstPrinter
119 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createVEMCInstPrinter);
120 }
121}
122