1//===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
14#define LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
15
16#include "llvm/CodeGen/TargetRegisterInfo.h"
17
18#define GET_REGINFO_HEADER
19#include "X86GenRegisterInfo.inc"
20
21namespace llvm {
22 class Triple;
23
24class X86RegisterInfo final : public X86GenRegisterInfo {
25private:
26 /// Is64Bit - Is the target 64-bits.
27 ///
28 bool Is64Bit;
29
30 /// IsWin64 - Is the target on of win64 flavours
31 ///
32 bool IsWin64;
33
34 /// IsUEFI64 - Is UEFI 64 bit target.
35 ///
36 bool IsUEFI64;
37
38 /// SlotSize - Stack slot size in bytes.
39 ///
40 unsigned SlotSize;
41
42 /// StackPtr - X86 physical register used as stack ptr.
43 ///
44 unsigned StackPtr;
45
46 /// FramePtr - X86 physical register used as frame ptr.
47 ///
48 unsigned FramePtr;
49
50 /// BasePtr - X86 physical register used as a base ptr in complex stack
51 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
52 /// variable size stack objects.
53 unsigned BasePtr;
54
55public:
56 explicit X86RegisterInfo(const Triple &TT);
57
58 /// Return the number of registers for the function.
59 unsigned getNumSupportedRegs(const MachineFunction &MF) const override;
60
61 /// getMatchingSuperRegClass - Return a subclass of the specified register
62 /// class A so that each register in it has a sub-register of the
63 /// specified sub-register index which is in the specified register class B.
64 const TargetRegisterClass *
65 getMatchingSuperRegClass(const TargetRegisterClass *A,
66 const TargetRegisterClass *B,
67 unsigned Idx) const override;
68
69 const TargetRegisterClass *
70 getSubClassWithSubReg(const TargetRegisterClass *RC,
71 unsigned Idx) const override;
72
73 const TargetRegisterClass *
74 getLargestLegalSuperClass(const TargetRegisterClass *RC,
75 const MachineFunction &MF) const override;
76
77 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
78 /// values.
79 const TargetRegisterClass *
80 getPointerRegClass(const MachineFunction &MF,
81 unsigned Kind = 0) const override;
82
83 /// getCrossCopyRegClass - Returns a legal register class to copy a register
84 /// in the specified class to or from. Returns NULL if it is possible to copy
85 /// between a two registers of the specified class.
86 const TargetRegisterClass *
87 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
88
89 /// getGPRsForTailCall - Returns a register class with registers that can be
90 /// used in forming tail calls.
91 const TargetRegisterClass *
92 getGPRsForTailCall(const MachineFunction &MF) const;
93
94 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
95 MachineFunction &MF) const override;
96
97 /// getCalleeSavedRegs - Return a null-terminated list of all of the
98 /// callee-save registers on this target.
99 const MCPhysReg *
100 getCalleeSavedRegs(const MachineFunction* MF) const override;
101 /// getIPRACSRegs - This API can be removed when rbp is safe to optimized out
102 /// when IPRA is on.
103 const MCPhysReg *getIPRACSRegs(const MachineFunction *MF) const override;
104 const MCPhysReg *
105 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
106 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
107 CallingConv::ID) const override;
108 const uint32_t *getNoPreservedMask() const override;
109
110 // Calls involved in thread-local variable lookup save more registers than
111 // normal calls, so they need a different mask to represent this.
112 const uint32_t *getDarwinTLSCallPreservedMask() const;
113
114 /// getReservedRegs - Returns a bitset indexed by physical register number
115 /// indicating if a register is a special register that has particular uses and
116 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
117 /// register scavenger to determine what registers are free.
118 BitVector getReservedRegs(const MachineFunction &MF) const override;
119
120 /// isArgumentReg - Returns true if Reg can be used as an argument to a
121 /// function.
122 bool isArgumentRegister(const MachineFunction &MF,
123 MCRegister Reg) const override;
124
125 /// Return true if it is tile register class.
126 bool isTileRegisterClass(const TargetRegisterClass *RC) const;
127
128 /// Returns true if PhysReg is a fixed register.
129 bool isFixedRegister(const MachineFunction &MF,
130 MCRegister PhysReg) const override;
131
132 void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
133
134 bool hasBasePointer(const MachineFunction &MF) const;
135
136 bool canRealignStack(const MachineFunction &MF) const override;
137
138 bool shouldRealignStack(const MachineFunction &MF) const override;
139
140 void eliminateFrameIndex(MachineBasicBlock::iterator II,
141 unsigned FIOperandNum, Register BaseReg,
142 int FIOffset) const;
143
144 bool eliminateFrameIndex(MachineBasicBlock::iterator MI,
145 int SPAdj, unsigned FIOperandNum,
146 RegScavenger *RS = nullptr) const override;
147
148 /// Process frame indices in forwards block order because
149 /// X86InstrInfo::getSPAdjust relies on it when searching for the
150 /// ADJCALLSTACKUP pseudo following a call.
151 /// TODO: Fix this and return true like all other targets.
152 bool eliminateFrameIndicesBackwards() const override { return false; }
153
154 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
155 /// when it reaches the "return" instruction. We can then pop a stack object
156 /// to this register without worry about clobbering it.
157 unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
158 MachineBasicBlock::iterator &MBBI) const;
159
160 // Debug information queries.
161 Register getFrameRegister(const MachineFunction &MF) const override;
162 Register getPtrSizedFrameRegister(const MachineFunction &MF) const;
163 Register getPtrSizedStackRegister(const MachineFunction &MF) const;
164 Register getStackRegister() const { return StackPtr; }
165 Register getBaseRegister() const { return BasePtr; }
166 /// Returns physical register used as frame pointer.
167 /// This will always returns the frame pointer register, contrary to
168 /// getFrameRegister() which returns the "base pointer" in situations
169 /// involving a stack, frame and base pointer.
170 Register getFramePtr() const { return FramePtr; }
171 // FIXME: Move to FrameInfok
172 unsigned getSlotSize() const { return SlotSize; }
173
174 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
175 SmallVectorImpl<MCPhysReg> &Hints,
176 const MachineFunction &MF, const VirtRegMap *VRM,
177 const LiveRegMatrix *Matrix) const override;
178
179 const TargetRegisterClass *
180 constrainRegClassToNonRex2(const TargetRegisterClass *RC) const;
181
182 bool isNonRex2RegClass(const TargetRegisterClass *RC) const;
183};
184
185} // End llvm namespace
186
187#endif
188