1//===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines wrappers for the Target class and related global
10// functionality. This makes it easier to access the data and provides a single
11// place that needs to check it for validity. All of these classes abort
12// on error conditions.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_UTILS_TABLEGEN_COMMON_CODEGENTARGET_H
17#define LLVM_UTILS_TABLEGEN_COMMON_CODEGENTARGET_H
18
19#include "Basic/CodeGenIntrinsics.h"
20#include "Basic/SDNodeProperties.h"
21#include "CodeGenHwModes.h"
22#include "CodeGenInstruction.h"
23#include "InfoByHwMode.h"
24#include "llvm/ADT/ArrayRef.h"
25#include "llvm/ADT/DenseMap.h"
26#include "llvm/ADT/SmallVector.h"
27#include "llvm/ADT/StringRef.h"
28#include "llvm/CodeGenTypes/MachineValueType.h"
29#include <cassert>
30#include <memory>
31#include <optional>
32#include <string>
33#include <vector>
34
35namespace llvm {
36
37class RecordKeeper;
38class Record;
39class CodeGenRegBank;
40class CodeGenRegister;
41class CodeGenRegisterClass;
42class CodeGenSchedModels;
43class CodeGenSubRegIndex;
44
45/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
46/// record corresponds to.
47MVT::SimpleValueType getValueType(const Record *Rec);
48
49StringRef getEnumName(MVT::SimpleValueType T);
50
51/// getQualifiedName - Return the name of the specified record, with a
52/// namespace qualifier if the record contains one.
53std::string getQualifiedName(const Record *R);
54
55/// CodeGenTarget - This class corresponds to the Target class in the .td files.
56///
57class CodeGenTarget {
58 const RecordKeeper &Records;
59 const Record *TargetRec;
60
61 mutable DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>>
62 InstructionMap;
63 mutable std::unique_ptr<CodeGenRegBank> RegBank;
64 mutable ArrayRef<const Record *> RegAltNameIndices;
65 mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
66 CodeGenHwModes CGH;
67 ArrayRef<const Record *> MacroFusions;
68 mutable bool HasVariableLengthEncodings = false;
69
70 void ReadInstructions() const;
71 void ReadLegalValueTypes() const;
72
73 mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
74
75 mutable StringRef InstNamespace;
76 mutable std::vector<const CodeGenInstruction *> InstrsByEnum;
77 mutable CodeGenIntrinsicMap Intrinsics;
78
79 mutable unsigned NumPseudoInstructions = 0;
80
81public:
82 CodeGenTarget(const RecordKeeper &Records);
83 ~CodeGenTarget();
84
85 const Record *getTargetRecord() const { return TargetRec; }
86 StringRef getName() const;
87
88 /// getInstNamespace - Return the target-specific instruction namespace.
89 ///
90 StringRef getInstNamespace() const;
91
92 /// getRegNamespace - Return the target-specific register namespace.
93 StringRef getRegNamespace() const;
94
95 /// getInstructionSet - Return the InstructionSet object.
96 ///
97 const Record *getInstructionSet() const;
98
99 /// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for
100 /// this target.
101 ///
102 bool getAllowRegisterRenaming() const;
103
104 /// getAsmParser - Return the AssemblyParser definition for this target.
105 ///
106 const Record *getAsmParser() const;
107
108 /// getAsmParserVariant - Return the AssemblyParserVariant definition for
109 /// this target.
110 ///
111 const Record *getAsmParserVariant(unsigned i) const;
112
113 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition
114 /// available for this target.
115 ///
116 unsigned getAsmParserVariantCount() const;
117
118 /// getAsmWriter - Return the AssemblyWriter definition for this target.
119 ///
120 const Record *getAsmWriter() const;
121
122 /// getRegBank - Return the register bank description.
123 CodeGenRegBank &getRegBank() const;
124
125 /// getRegisterByName - If there is a register with the specific AsmName,
126 /// return it.
127 const CodeGenRegister *getRegisterByName(StringRef Name) const;
128
129 ArrayRef<const Record *> getRegAltNameIndices() const {
130 if (RegAltNameIndices.empty())
131 RegAltNameIndices = Records.getAllDerivedDefinitions(ClassName: "RegAltNameIndex");
132 return RegAltNameIndices;
133 }
134
135 const CodeGenRegisterClass &getRegisterClass(const Record *R) const;
136
137 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
138 /// specified physical register.
139 std::vector<ValueTypeByHwMode> getRegisterVTs(const Record *R) const;
140
141 ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
142 if (LegalValueTypes.empty())
143 ReadLegalValueTypes();
144 return LegalValueTypes;
145 }
146
147 CodeGenSchedModels &getSchedModels() const;
148
149 const CodeGenHwModes &getHwModes() const { return CGH; }
150
151 bool hasMacroFusion() const { return !MacroFusions.empty(); }
152
153 ArrayRef<const Record *> getMacroFusions() const { return MacroFusions; }
154
155private:
156 DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>> &
157 getInstructionMap() const {
158 if (InstructionMap.empty())
159 ReadInstructions();
160 return InstructionMap;
161 }
162
163public:
164 CodeGenInstruction &getInstruction(const Record *InstRec) const {
165 auto I = getInstructionMap().find(Val: InstRec);
166 assert(I != InstructionMap.end() && "Not an instruction");
167 return *I->second;
168 }
169
170 /// Returns the number of predefined instructions.
171 static unsigned getNumFixedInstructions();
172
173 /// Return all of the instructions defined by the target, ordered by their
174 /// enum value.
175 /// The following order of instructions is also guaranteed:
176 /// - fixed / generic instructions as declared in TargetOpcodes.def, in order;
177 /// - pseudo instructions in lexicographical order sorted by name;
178 /// - other instructions in lexicographical order sorted by name.
179 ArrayRef<const CodeGenInstruction *> getInstructionsByEnumValue() const {
180 if (InstrsByEnum.empty())
181 ComputeInstrsByEnum();
182 return InstrsByEnum;
183 }
184
185 // Functions that return various slices of `getInstructionsByEnumValue`.
186 ArrayRef<const CodeGenInstruction *>
187 getGenericInstructionsByEnumValue() const {
188 return getInstructionsByEnumValue().take_front(N: getNumFixedInstructions());
189 }
190
191 ArrayRef<const CodeGenInstruction *>
192 getTargetInstructionsByEnumValue() const {
193 return getInstructionsByEnumValue().drop_front(N: getNumFixedInstructions());
194 }
195
196 ArrayRef<const CodeGenInstruction *>
197 getTargetPseudoInstructionsByEnumValue() const {
198 return getTargetInstructionsByEnumValue().take_front(N: NumPseudoInstructions);
199 }
200
201 ArrayRef<const CodeGenInstruction *>
202 getTargetNonPseudoInstructionsByEnumValue() const {
203 return getTargetInstructionsByEnumValue().drop_front(N: NumPseudoInstructions);
204 }
205
206 /// Return the integer enum value corresponding to this instruction record.
207 unsigned getInstrIntValue(const Record *R) const {
208 if (InstrsByEnum.empty())
209 ComputeInstrsByEnum();
210 return getInstruction(InstRec: R).EnumVal;
211 }
212
213 /// Return whether instructions have variable length encodings on this target.
214 bool hasVariableLengthEncodings() const { return HasVariableLengthEncodings; }
215
216 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
217 ///
218 bool isLittleEndianEncoding() const;
219
220 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
221 /// encodings, reverse the bit order of all instructions.
222 void reverseBitsForLittleEndianEncoding();
223
224 /// guessInstructionProperties - should we just guess unset instruction
225 /// properties?
226 bool guessInstructionProperties() const;
227
228 const CodeGenIntrinsic &getIntrinsic(const Record *Def) const {
229 return Intrinsics[Def];
230 }
231
232private:
233 void ComputeInstrsByEnum() const;
234};
235
236/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
237/// tablegen class in TargetSelectionDAG.td
238class ComplexPattern {
239 const Record *Ty;
240 unsigned NumOperands;
241 std::string SelectFunc;
242 std::vector<const Record *> RootNodes;
243 unsigned Properties; // Node properties
244 unsigned Complexity;
245 bool WantsRoot;
246 bool WantsParent;
247
248public:
249 ComplexPattern(const Record *R);
250
251 const Record *getValueType() const { return Ty; }
252 unsigned getNumOperands() const { return NumOperands; }
253 const std::string &getSelectFunc() const { return SelectFunc; }
254 ArrayRef<const Record *> getRootNodes() const { return RootNodes; }
255 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
256 unsigned getComplexity() const { return Complexity; }
257 bool wantsRoot() const { return WantsRoot; }
258 bool wantsParent() const { return WantsParent; }
259};
260
261} // namespace llvm
262
263#endif // LLVM_UTILS_TABLEGEN_COMMON_CODEGENTARGET_H
264