1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifndef GET_CC_REGISTER_LISTS
10
11static bool CC_Mips(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, CCState &State);
14static bool CC_Mips16RetHelper(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, CCState &State);
17static bool CC_MipsN(unsigned ValNo, MVT ValVT,
18 MVT LocVT, CCValAssign::LocInfo LocInfo,
19 ISD::ArgFlagsTy ArgFlags, CCState &State);
20static bool CC_MipsN_FastCC(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, CCState &State);
23static bool CC_MipsN_SoftFloat(unsigned ValNo, MVT ValVT,
24 MVT LocVT, CCValAssign::LocInfo LocInfo,
25 ISD::ArgFlagsTy ArgFlags, CCState &State);
26static bool CC_MipsN_VarArg(unsigned ValNo, MVT ValVT,
27 MVT LocVT, CCValAssign::LocInfo LocInfo,
28 ISD::ArgFlagsTy ArgFlags, CCState &State);
29static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
30 MVT LocVT, CCValAssign::LocInfo LocInfo,
31 ISD::ArgFlagsTy ArgFlags, CCState &State);
32static bool CC_MipsO32_FP(unsigned ValNo, MVT ValVT,
33 MVT LocVT, CCValAssign::LocInfo LocInfo,
34 ISD::ArgFlagsTy ArgFlags, CCState &State);
35static bool CC_MipsO32_FastCC(unsigned ValNo, MVT ValVT,
36 MVT LocVT, CCValAssign::LocInfo LocInfo,
37 ISD::ArgFlagsTy ArgFlags, CCState &State);
38static bool CC_Mips_ByVal(unsigned ValNo, MVT ValVT,
39 MVT LocVT, CCValAssign::LocInfo LocInfo,
40 ISD::ArgFlagsTy ArgFlags, CCState &State);
41static bool CC_Mips_FastCC(unsigned ValNo, MVT ValVT,
42 MVT LocVT, CCValAssign::LocInfo LocInfo,
43 ISD::ArgFlagsTy ArgFlags, CCState &State);
44static bool CC_Mips_FixedArg(unsigned ValNo, MVT ValVT,
45 MVT LocVT, CCValAssign::LocInfo LocInfo,
46 ISD::ArgFlagsTy ArgFlags, CCState &State);
47static bool CC_Mips_VarArg(unsigned ValNo, MVT ValVT,
48 MVT LocVT, CCValAssign::LocInfo LocInfo,
49 ISD::ArgFlagsTy ArgFlags, CCState &State);
50static bool RetCC_F128(unsigned ValNo, MVT ValVT,
51 MVT LocVT, CCValAssign::LocInfo LocInfo,
52 ISD::ArgFlagsTy ArgFlags, CCState &State);
53static bool RetCC_F128HardFloat(unsigned ValNo, MVT ValVT,
54 MVT LocVT, CCValAssign::LocInfo LocInfo,
55 ISD::ArgFlagsTy ArgFlags, CCState &State);
56static bool RetCC_F128SoftFloat(unsigned ValNo, MVT ValVT,
57 MVT LocVT, CCValAssign::LocInfo LocInfo,
58 ISD::ArgFlagsTy ArgFlags, CCState &State);
59static bool RetCC_Mips(unsigned ValNo, MVT ValVT,
60 MVT LocVT, CCValAssign::LocInfo LocInfo,
61 ISD::ArgFlagsTy ArgFlags, CCState &State);
62static bool RetCC_MipsN(unsigned ValNo, MVT ValVT,
63 MVT LocVT, CCValAssign::LocInfo LocInfo,
64 ISD::ArgFlagsTy ArgFlags, CCState &State);
65static bool RetCC_MipsO32(unsigned ValNo, MVT ValVT,
66 MVT LocVT, CCValAssign::LocInfo LocInfo,
67 ISD::ArgFlagsTy ArgFlags, CCState &State);
68
69
70static bool CC_Mips(unsigned ValNo, MVT ValVT,
71 MVT LocVT, CCValAssign::LocInfo LocInfo,
72 ISD::ArgFlagsTy ArgFlags, CCState &State) {
73
74 if (State.isVarArg()) {
75 if (!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)) {
76 if (!CC_Mips_VarArg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
77 return false;
78 }
79 }
80
81 if (!CC_Mips_FixedArg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
82 return false;
83
84 return true; // CC didn't match.
85}
86
87
88static bool CC_Mips16RetHelper(unsigned ValNo, MVT ValVT,
89 MVT LocVT, CCValAssign::LocInfo LocInfo,
90 ISD::ArgFlagsTy ArgFlags, CCState &State) {
91
92 if (ArgFlags.isByVal()) {
93 if (!CC_Mips_ByVal(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
94 return false;
95 }
96
97 if (LocVT == MVT::i32) {
98 static const MCPhysReg RegList1[] = {
99 Mips::V0, Mips::V1, Mips::A0, Mips::A1
100 };
101 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
102 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
103 return false;
104 }
105 }
106
107 return true; // CC didn't match.
108}
109
110
111static bool CC_MipsN(unsigned ValNo, MVT ValVT,
112 MVT LocVT, CCValAssign::LocInfo LocInfo,
113 ISD::ArgFlagsTy ArgFlags, CCState &State) {
114
115 if (LocVT == MVT::i8 ||
116 LocVT == MVT::i16 ||
117 LocVT == MVT::i32 ||
118 LocVT == MVT::i64) {
119 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
120 if (ArgFlags.isInReg()) {
121 LocVT = MVT::i64;
122 if (ArgFlags.isSExt())
123 LocInfo = CCValAssign::SExtUpper;
124 else if (ArgFlags.isZExt())
125 LocInfo = CCValAssign::ZExtUpper;
126 else
127 LocInfo = CCValAssign::AExtUpper;
128 }
129 }
130 }
131
132 if (LocVT == MVT::i8 ||
133 LocVT == MVT::i16 ||
134 LocVT == MVT::i32) {
135 if (!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)) {
136 LocVT = MVT::i64;
137 if (ArgFlags.isSExt())
138 LocInfo = CCValAssign::SExt;
139 else if (ArgFlags.isZExt())
140 LocInfo = CCValAssign::ZExt;
141 else
142 LocInfo = CCValAssign::AExt;
143 }
144 }
145
146 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
147 if (LocVT == MVT::i32) {
148 if (!CC_MipsN_SoftFloat(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
149 return false;
150 }
151 }
152
153 if (LocVT == MVT::i64) {
154 static const MCPhysReg RegList1[] = {
155 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
156 };
157 static const MCPhysReg RegList2[] = {
158 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
159 };
160 if (unsigned Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
161 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
162 return false;
163 }
164 }
165
166 if (LocVT == MVT::f32) {
167 static const MCPhysReg RegList3[] = {
168 Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19
169 };
170 static const MCPhysReg RegList4[] = {
171 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
172 };
173 if (unsigned Reg = State.AllocateReg(Regs: RegList3, ShadowRegs: RegList4)) {
174 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
175 return false;
176 }
177 }
178
179 if (LocVT == MVT::f64) {
180 static const MCPhysReg RegList5[] = {
181 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
182 };
183 static const MCPhysReg RegList6[] = {
184 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
185 };
186 if (unsigned Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
187 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
188 return false;
189 }
190 }
191
192 if (LocVT == MVT::f32) {
193 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(8));
194 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
195 return false;
196 }
197
198 if (LocVT == MVT::i64 ||
199 LocVT == MVT::f64) {
200 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
201 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
202 return false;
203 }
204
205 return true; // CC didn't match.
206}
207
208
209static bool CC_MipsN_FastCC(unsigned ValNo, MVT ValVT,
210 MVT LocVT, CCValAssign::LocInfo LocInfo,
211 ISD::ArgFlagsTy ArgFlags, CCState &State) {
212
213 if (LocVT == MVT::i64) {
214 static const MCPhysReg RegList1[] = {
215 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::T8_64, Mips::V1_64
216 };
217 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
218 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
219 return false;
220 }
221 }
222
223 if (LocVT == MVT::f64) {
224 static const MCPhysReg RegList2[] = {
225 Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
226 };
227 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
228 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
229 return false;
230 }
231 }
232
233 if (LocVT == MVT::i64 ||
234 LocVT == MVT::f64) {
235 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(8));
236 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
237 return false;
238 }
239
240 return true; // CC didn't match.
241}
242
243
244static bool CC_MipsN_SoftFloat(unsigned ValNo, MVT ValVT,
245 MVT LocVT, CCValAssign::LocInfo LocInfo,
246 ISD::ArgFlagsTy ArgFlags, CCState &State) {
247
248 static const MCPhysReg RegList1[] = {
249 Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3
250 };
251 static const MCPhysReg RegList2[] = {
252 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
253 };
254 if (unsigned Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
255 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
256 return false;
257 }
258
259 int64_t Offset3 = State.AllocateStack(Size: 4, Alignment: Align(8));
260 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
261 return false;
262
263 return true; // CC didn't match.
264}
265
266
267static bool CC_MipsN_VarArg(unsigned ValNo, MVT ValVT,
268 MVT LocVT, CCValAssign::LocInfo LocInfo,
269 ISD::ArgFlagsTy ArgFlags, CCState &State) {
270
271 if (LocVT == MVT::i8 ||
272 LocVT == MVT::i16 ||
273 LocVT == MVT::i32 ||
274 LocVT == MVT::i64) {
275 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
276 if (ArgFlags.isInReg()) {
277 LocVT = MVT::i64;
278 if (ArgFlags.isSExt())
279 LocInfo = CCValAssign::SExtUpper;
280 else if (ArgFlags.isZExt())
281 LocInfo = CCValAssign::ZExtUpper;
282 else
283 LocInfo = CCValAssign::AExtUpper;
284 }
285 }
286 }
287
288 if (LocVT == MVT::i8 ||
289 LocVT == MVT::i16 ||
290 LocVT == MVT::i32) {
291 LocVT = MVT::i64;
292 if (ArgFlags.isSExt())
293 LocInfo = CCValAssign::SExt;
294 else if (ArgFlags.isZExt())
295 LocInfo = CCValAssign::ZExt;
296 else
297 LocInfo = CCValAssign::AExt;
298 }
299
300 if (LocVT == MVT::f32) {
301 static const MCPhysReg RegList1[] = {
302 Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3
303 };
304 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
305 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
306 return false;
307 }
308 }
309
310 if (LocVT == MVT::i64 ||
311 LocVT == MVT::f64) {
312 static const MCPhysReg RegList2[] = {
313 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
314 };
315 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
316 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
317 return false;
318 }
319 }
320
321 if (LocVT == MVT::f32) {
322 int64_t Offset3 = State.AllocateStack(Size: 4, Alignment: Align(8));
323 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
324 return false;
325 }
326
327 if (LocVT == MVT::i64 ||
328 LocVT == MVT::f64) {
329 int64_t Offset4 = State.AllocateStack(Size: 8, Alignment: Align(8));
330 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
331 return false;
332 }
333
334 return true; // CC didn't match.
335}
336
337
338static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
339 MVT LocVT, CCValAssign::LocInfo LocInfo,
340 ISD::ArgFlagsTy ArgFlags, CCState &State) {
341
342 if (LocVT == MVT::i1 ||
343 LocVT == MVT::i8 ||
344 LocVT == MVT::i16) {
345 LocVT = MVT::i32;
346 if (ArgFlags.isSExt())
347 LocInfo = CCValAssign::SExt;
348 else if (ArgFlags.isZExt())
349 LocInfo = CCValAssign::ZExt;
350 else
351 LocInfo = CCValAssign::AExt;
352 }
353
354 if (LocVT == MVT::i32 ||
355 LocVT == MVT::f32) {
356 int64_t Offset1 = State.AllocateStack(Size: 4, Alignment: Align(4));
357 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
358 return false;
359 }
360
361 if (LocVT == MVT::f64) {
362 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(8));
363 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
364 return false;
365 }
366
367 return true; // CC didn't match.
368}
369
370
371static bool CC_MipsO32_FP(unsigned ValNo, MVT ValVT,
372 MVT LocVT, CCValAssign::LocInfo LocInfo,
373 ISD::ArgFlagsTy ArgFlags, CCState &State) {
374
375 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
376 if (!CC_MipsO32_FP32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
377 return false;
378 }
379
380 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
381 if (!CC_MipsO32_FP64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
382 return false;
383 }
384
385 return true; // CC didn't match.
386}
387
388
389static bool CC_MipsO32_FastCC(unsigned ValNo, MVT ValVT,
390 MVT LocVT, CCValAssign::LocInfo LocInfo,
391 ISD::ArgFlagsTy ArgFlags, CCState &State) {
392
393 if (LocVT == MVT::f64) {
394 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
395 static const MCPhysReg RegList1[] = {
396 Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9
397 };
398 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
399 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
400 return false;
401 }
402 }
403 }
404
405 if (LocVT == MVT::f64) {
406 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
407 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useOddSPReg()) {
408 static const MCPhysReg RegList2[] = {
409 Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
410 };
411 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
412 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
413 return false;
414 }
415 }
416 }
417 }
418
419 if (LocVT == MVT::f64) {
420 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
421 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).noOddSPReg()) {
422 static const MCPhysReg RegList3[] = {
423 Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64
424 };
425 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
426 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
427 return false;
428 }
429 }
430 }
431 }
432
433 if (LocVT == MVT::f64) {
434 int64_t Offset4 = State.AllocateStack(Size: 8, Alignment: Align(8));
435 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
436 return false;
437 }
438
439 return true; // CC didn't match.
440}
441
442
443static bool CC_Mips_ByVal(unsigned ValNo, MVT ValVT,
444 MVT LocVT, CCValAssign::LocInfo LocInfo,
445 ISD::ArgFlagsTy ArgFlags, CCState &State) {
446
447 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) {
448 if (ArgFlags.isByVal()) {
449 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
450 return false;
451 }
452 }
453
454 if (ArgFlags.isByVal()) {
455 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
456 return false;
457 }
458
459 return true; // CC didn't match.
460}
461
462
463static bool CC_Mips_FastCC(unsigned ValNo, MVT ValVT,
464 MVT LocVT, CCValAssign::LocInfo LocInfo,
465 ISD::ArgFlagsTy ArgFlags, CCState &State) {
466
467 if (ArgFlags.isByVal()) {
468 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
469 return false;
470 }
471
472 if (LocVT == MVT::i8 ||
473 LocVT == MVT::i16) {
474 LocVT = MVT::i32;
475 if (ArgFlags.isSExt())
476 LocInfo = CCValAssign::SExt;
477 else if (ArgFlags.isZExt())
478 LocInfo = CCValAssign::ZExt;
479 else
480 LocInfo = CCValAssign::AExt;
481 }
482
483 if (LocVT == MVT::i32) {
484 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isTargetNaCl()) {
485 static const MCPhysReg RegList1[] = {
486 Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::T8, Mips::V1
487 };
488 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
489 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
490 return false;
491 }
492 }
493 }
494
495 if (LocVT == MVT::i32) {
496 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isTargetNaCl()) {
497 static const MCPhysReg RegList2[] = {
498 Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::V1
499 };
500 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
501 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
502 return false;
503 }
504 }
505 }
506
507 if (LocVT == MVT::f32) {
508 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useOddSPReg()) {
509 static const MCPhysReg RegList3[] = {
510 Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19
511 };
512 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
513 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
514 return false;
515 }
516 }
517 }
518
519 if (LocVT == MVT::f32) {
520 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).noOddSPReg()) {
521 static const MCPhysReg RegList4[] = {
522 Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18
523 };
524 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
525 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
526 return false;
527 }
528 }
529 }
530
531 if (LocVT == MVT::i32 ||
532 LocVT == MVT::f32) {
533 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(4));
534 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
535 return false;
536 }
537
538 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) {
539 if (!CC_MipsO32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
540 return false;
541 }
542
543 if (!CC_MipsN_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
544 return false;
545
546 return true; // CC didn't match.
547}
548
549
550static bool CC_Mips_FixedArg(unsigned ValNo, MVT ValVT,
551 MVT LocVT, CCValAssign::LocInfo LocInfo,
552 ISD::ArgFlagsTy ArgFlags, CCState &State) {
553
554 if (State.getCallingConv() != CallingConv::Fast) {
555 if (static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == MipsCCState::Mips16RetHelperConv) {
556 if (!CC_Mips16RetHelper(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
557 return false;
558 }
559 }
560
561 if (ArgFlags.isByVal()) {
562 if (!CC_Mips_ByVal(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
563 return false;
564 }
565
566 if (LocVT == MVT::i64) {
567 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
568 if (static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)) {
569 LocVT = MVT::f64;
570 LocInfo = CCValAssign::BCvt;
571 }
572 }
573 }
574
575 if (State.getCallingConv() == CallingConv::Fast) {
576 if (!CC_Mips_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
577 return false;
578 }
579
580 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) {
581 if (!CC_MipsO32_FP(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
582 return false;
583 }
584
585 if (!CC_MipsN(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
586 return false;
587
588 return true; // CC didn't match.
589}
590
591
592static bool CC_Mips_VarArg(unsigned ValNo, MVT ValVT,
593 MVT LocVT, CCValAssign::LocInfo LocInfo,
594 ISD::ArgFlagsTy ArgFlags, CCState &State) {
595
596 if (ArgFlags.isByVal()) {
597 if (!CC_Mips_ByVal(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
598 return false;
599 }
600
601 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) {
602 if (!CC_MipsO32_FP(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
603 return false;
604 }
605
606 if (!CC_MipsN_VarArg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
607 return false;
608
609 return true; // CC didn't match.
610}
611
612
613static bool RetCC_F128(unsigned ValNo, MVT ValVT,
614 MVT LocVT, CCValAssign::LocInfo LocInfo,
615 ISD::ArgFlagsTy ArgFlags, CCState &State) {
616
617 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
618 if (LocVT == MVT::i64) {
619 if (!RetCC_F128SoftFloat(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
620 return false;
621 }
622 }
623
624 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
625 if (LocVT == MVT::i64) {
626 if (!RetCC_F128HardFloat(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
627 return false;
628 }
629 }
630
631 return true; // CC didn't match.
632}
633
634
635static bool RetCC_F128HardFloat(unsigned ValNo, MVT ValVT,
636 MVT LocVT, CCValAssign::LocInfo LocInfo,
637 ISD::ArgFlagsTy ArgFlags, CCState &State) {
638
639 LocVT = MVT::f64;
640 LocInfo = CCValAssign::BCvt;
641
642 if (ArgFlags.isInReg()) {
643 static const MCPhysReg RegList1[] = {
644 Mips::D0_64, Mips::D1_64
645 };
646 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
647 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
648 return false;
649 }
650 }
651
652 static const MCPhysReg RegList2[] = {
653 Mips::D0_64, Mips::D2_64
654 };
655 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
656 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
657 return false;
658 }
659
660 return true; // CC didn't match.
661}
662
663
664static bool RetCC_F128SoftFloat(unsigned ValNo, MVT ValVT,
665 MVT LocVT, CCValAssign::LocInfo LocInfo,
666 ISD::ArgFlagsTy ArgFlags, CCState &State) {
667
668 static const MCPhysReg RegList1[] = {
669 Mips::V0_64, Mips::A0_64
670 };
671 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
672 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
673 return false;
674 }
675
676 return true; // CC didn't match.
677}
678
679
680static bool RetCC_Mips(unsigned ValNo, MVT ValVT,
681 MVT LocVT, CCValAssign::LocInfo LocInfo,
682 ISD::ArgFlagsTy ArgFlags, CCState &State) {
683
684 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_N32()) {
685 if (!RetCC_MipsN(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
686 return false;
687 }
688
689 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_N64()) {
690 if (!RetCC_MipsN(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
691 return false;
692 }
693
694 if (!RetCC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
695 return false;
696
697 return true; // CC didn't match.
698}
699
700
701static bool RetCC_MipsN(unsigned ValNo, MVT ValVT,
702 MVT LocVT, CCValAssign::LocInfo LocInfo,
703 ISD::ArgFlagsTy ArgFlags, CCState &State) {
704
705 if (LocVT == MVT::i64) {
706 if (static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)) {
707 if (!RetCC_F128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
708 return false;
709 }
710 }
711
712 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
713 if (LocVT == MVT::i8 ||
714 LocVT == MVT::i16 ||
715 LocVT == MVT::i32 ||
716 LocVT == MVT::i64) {
717 if (ArgFlags.isInReg()) {
718 LocVT = MVT::i64;
719 if (ArgFlags.isSExt())
720 LocInfo = CCValAssign::SExt;
721 else if (ArgFlags.isZExt())
722 LocInfo = CCValAssign::ZExt;
723 else
724 LocInfo = CCValAssign::AExt;
725 }
726 }
727 }
728
729 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
730 if (LocVT == MVT::i8 ||
731 LocVT == MVT::i16 ||
732 LocVT == MVT::i32 ||
733 LocVT == MVT::i64) {
734 if (ArgFlags.isInReg()) {
735 LocVT = MVT::i64;
736 if (ArgFlags.isSExt())
737 LocInfo = CCValAssign::SExtUpper;
738 else if (ArgFlags.isZExt())
739 LocInfo = CCValAssign::ZExtUpper;
740 else
741 LocInfo = CCValAssign::AExtUpper;
742 }
743 }
744 }
745
746 if (LocVT == MVT::i64) {
747 static const MCPhysReg RegList1[] = {
748 Mips::V0_64, Mips::V1_64
749 };
750 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
751 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
752 return false;
753 }
754 }
755
756 if (LocVT == MVT::f32) {
757 static const MCPhysReg RegList2[] = {
758 Mips::F0, Mips::F2
759 };
760 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
761 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
762 return false;
763 }
764 }
765
766 if (LocVT == MVT::f64) {
767 static const MCPhysReg RegList3[] = {
768 Mips::D0_64, Mips::D2_64
769 };
770 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
771 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
772 return false;
773 }
774 }
775
776 return true; // CC didn't match.
777}
778
779
780static bool RetCC_MipsO32(unsigned ValNo, MVT ValVT,
781 MVT LocVT, CCValAssign::LocInfo LocInfo,
782 ISD::ArgFlagsTy ArgFlags, CCState &State) {
783
784 if (LocVT == MVT::i1 ||
785 LocVT == MVT::i8 ||
786 LocVT == MVT::i16) {
787 LocVT = MVT::i32;
788 if (ArgFlags.isSExt())
789 LocInfo = CCValAssign::SExt;
790 else if (ArgFlags.isZExt())
791 LocInfo = CCValAssign::ZExt;
792 else
793 LocInfo = CCValAssign::AExt;
794 }
795
796 if (!static_cast<MipsCCState *>(&State)->WasOriginalRetVectorFloat(ValNo)) {
797 if (LocVT == MVT::i32) {
798 static const MCPhysReg RegList1[] = {
799 Mips::V0, Mips::V1, Mips::A0, Mips::A1
800 };
801 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
802 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
803 return false;
804 }
805 }
806 }
807
808 if (LocVT == MVT::f32) {
809 static const MCPhysReg RegList2[] = {
810 Mips::F0, Mips::F2
811 };
812 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
813 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
814 return false;
815 }
816 }
817
818 if (LocVT == MVT::f64) {
819 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
820 static const MCPhysReg RegList3[] = {
821 Mips::D0_64, Mips::D2_64
822 };
823 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
824 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
825 return false;
826 }
827 }
828 }
829
830 if (LocVT == MVT::f64) {
831 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
832 static const MCPhysReg RegList4[] = {
833 Mips::D0, Mips::D1
834 };
835 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
836 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
837 return false;
838 }
839 }
840 }
841
842 return true; // CC didn't match.
843}
844
845#else
846
847const MCRegister CC_Mips_ArgRegs[] = { 0 };
848const MCRegister CC_Mips16RetHelper_ArgRegs[] = { Mips::A0, Mips::A1, Mips::V0, Mips::V1 };
849const MCRegister CC_MipsN_ArgRegs[] = { 0 };
850const MCRegister CC_MipsN_FastCC_ArgRegs[] = { Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::D0_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::T8_64, Mips::V1_64 };
851const MCRegister CC_MipsN_SoftFloat_ArgRegs[] = { 0 };
852const MCRegister CC_MipsN_VarArg_ArgRegs[] = { Mips::A0, Mips::A0_64, Mips::A1, Mips::A1_64, Mips::A2, Mips::A2_64, Mips::A3, Mips::A3_64, Mips::T0, Mips::T0_64, Mips::T1, Mips::T1_64, Mips::T2, Mips::T2_64, Mips::T3, Mips::T3_64 };
853const MCRegister CC_MipsO32_ArgRegs[] = { 0 };
854const MCRegister CC_MipsO32_FP_ArgRegs[] = { 0 };
855const MCRegister CC_MipsO32_FastCC_ArgRegs[] = { Mips::D0, Mips::D0_64, Mips::D1, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D1_64, Mips::D2, Mips::D2_64, Mips::D3, Mips::D3_64, Mips::D4, Mips::D4_64, Mips::D5, Mips::D5_64, Mips::D6, Mips::D6_64, Mips::D7, Mips::D7_64, Mips::D8, Mips::D8_64, Mips::D9, Mips::D9_64 };
856const MCRegister CC_Mips_ByVal_ArgRegs[] = { 0 };
857const MCRegister CC_Mips_FastCC_ArgRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::F0, Mips::F1, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::T8, Mips::V1 };
858const MCRegister CC_Mips_FixedArg_ArgRegs[] = { 0 };
859const MCRegister CC_Mips_VarArg_ArgRegs[] = { 0 };
860const MCRegister RetCC_F128_ArgRegs[] = { 0 };
861const MCRegister RetCC_F128HardFloat_ArgRegs[] = { Mips::D0_64, Mips::D1_64, Mips::D2_64 };
862const MCRegister RetCC_F128SoftFloat_ArgRegs[] = { Mips::A0_64, Mips::V0_64 };
863const MCRegister RetCC_Mips_ArgRegs[] = { 0 };
864const MCRegister RetCC_MipsN_ArgRegs[] = { Mips::D0_64, Mips::D2_64, Mips::F0, Mips::F2, Mips::V0_64, Mips::V1_64 };
865const MCRegister RetCC_MipsO32_ArgRegs[] = { Mips::A0, Mips::A1, Mips::D0, Mips::D0_64, Mips::D1, Mips::D2_64, Mips::F0, Mips::F2, Mips::V0, Mips::V1 };
866
867#endif // CC_REGISTER_LIST
868