1//===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file defines the MIPS-specific support for the FastISel class.
11/// Some of the target-specific code is generated by tablegen in the file
12/// MipsGenFastISel.inc, which is #included here.
13///
14//===----------------------------------------------------------------------===//
15
16#include "MCTargetDesc/MipsABIInfo.h"
17#include "MCTargetDesc/MipsBaseInfo.h"
18#include "MipsCCState.h"
19#include "MipsISelLowering.h"
20#include "MipsInstrInfo.h"
21#include "MipsMachineFunction.h"
22#include "MipsSubtarget.h"
23#include "MipsTargetMachine.h"
24#include "llvm/ADT/APInt.h"
25#include "llvm/ADT/ArrayRef.h"
26#include "llvm/ADT/DenseMap.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/Analysis/TargetLibraryInfo.h"
29#include "llvm/CodeGen/CallingConvLower.h"
30#include "llvm/CodeGen/FastISel.h"
31#include "llvm/CodeGen/FunctionLoweringInfo.h"
32#include "llvm/CodeGen/ISDOpcodes.h"
33#include "llvm/CodeGen/MachineBasicBlock.h"
34#include "llvm/CodeGen/MachineFrameInfo.h"
35#include "llvm/CodeGen/MachineInstrBuilder.h"
36#include "llvm/CodeGen/MachineMemOperand.h"
37#include "llvm/CodeGen/MachineRegisterInfo.h"
38#include "llvm/CodeGen/TargetInstrInfo.h"
39#include "llvm/CodeGen/TargetLowering.h"
40#include "llvm/CodeGen/ValueTypes.h"
41#include "llvm/CodeGenTypes/MachineValueType.h"
42#include "llvm/IR/Attributes.h"
43#include "llvm/IR/CallingConv.h"
44#include "llvm/IR/Constant.h"
45#include "llvm/IR/Constants.h"
46#include "llvm/IR/DataLayout.h"
47#include "llvm/IR/Function.h"
48#include "llvm/IR/GetElementPtrTypeIterator.h"
49#include "llvm/IR/GlobalValue.h"
50#include "llvm/IR/GlobalVariable.h"
51#include "llvm/IR/InstrTypes.h"
52#include "llvm/IR/Instruction.h"
53#include "llvm/IR/Instructions.h"
54#include "llvm/IR/IntrinsicInst.h"
55#include "llvm/IR/Operator.h"
56#include "llvm/IR/Type.h"
57#include "llvm/IR/User.h"
58#include "llvm/IR/Value.h"
59#include "llvm/MC/MCContext.h"
60#include "llvm/MC/MCInstrDesc.h"
61#include "llvm/MC/MCRegisterInfo.h"
62#include "llvm/MC/MCSymbol.h"
63#include "llvm/Support/Casting.h"
64#include "llvm/Support/Compiler.h"
65#include "llvm/Support/Debug.h"
66#include "llvm/Support/ErrorHandling.h"
67#include "llvm/Support/MathExtras.h"
68#include "llvm/Support/raw_ostream.h"
69#include <algorithm>
70#include <array>
71#include <cassert>
72#include <cstdint>
73
74#define DEBUG_TYPE "mips-fastisel"
75
76using namespace llvm;
77
78extern cl::opt<bool> EmitJalrReloc;
79
80namespace {
81
82class MipsFastISel final : public FastISel {
83
84 // All possible address modes.
85 class Address {
86 public:
87 using BaseKind = enum { RegBase, FrameIndexBase };
88
89 private:
90 BaseKind Kind = RegBase;
91 union {
92 unsigned Reg;
93 int FI;
94 } Base;
95
96 int64_t Offset = 0;
97
98 const GlobalValue *GV = nullptr;
99
100 public:
101 // Innocuous defaults for our address.
102 Address() { Base.Reg = 0; }
103
104 void setKind(BaseKind K) { Kind = K; }
105 BaseKind getKind() const { return Kind; }
106 bool isRegBase() const { return Kind == RegBase; }
107 bool isFIBase() const { return Kind == FrameIndexBase; }
108
109 void setReg(unsigned Reg) {
110 assert(isRegBase() && "Invalid base register access!");
111 Base.Reg = Reg;
112 }
113
114 unsigned getReg() const {
115 assert(isRegBase() && "Invalid base register access!");
116 return Base.Reg;
117 }
118
119 void setFI(unsigned FI) {
120 assert(isFIBase() && "Invalid base frame index access!");
121 Base.FI = FI;
122 }
123
124 unsigned getFI() const {
125 assert(isFIBase() && "Invalid base frame index access!");
126 return Base.FI;
127 }
128
129 void setOffset(int64_t Offset_) { Offset = Offset_; }
130 int64_t getOffset() const { return Offset; }
131 void setGlobalValue(const GlobalValue *G) { GV = G; }
132 const GlobalValue *getGlobalValue() { return GV; }
133 };
134
135 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
136 /// make the right decision when generating code for different targets.
137 const TargetMachine &TM;
138 const MipsSubtarget *Subtarget;
139 const TargetInstrInfo &TII;
140 const TargetLowering &TLI;
141 MipsFunctionInfo *MFI;
142
143 // Convenience variables to avoid some queries.
144 LLVMContext *Context;
145
146 bool fastLowerArguments() override;
147 bool fastLowerCall(CallLoweringInfo &CLI) override;
148 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
149
150 bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
151 // floating point but not reject doing fast-isel in other
152 // situations
153
154private:
155 // Selection routines.
156 bool selectLogicalOp(const Instruction *I);
157 bool selectLoad(const Instruction *I);
158 bool selectStore(const Instruction *I);
159 bool selectBranch(const Instruction *I);
160 bool selectSelect(const Instruction *I);
161 bool selectCmp(const Instruction *I);
162 bool selectFPExt(const Instruction *I);
163 bool selectFPTrunc(const Instruction *I);
164 bool selectFPToInt(const Instruction *I, bool IsSigned);
165 bool selectRet(const Instruction *I);
166 bool selectTrunc(const Instruction *I);
167 bool selectIntExt(const Instruction *I);
168 bool selectShift(const Instruction *I);
169 bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
170
171 // Utility helper routines.
172 bool isTypeLegal(Type *Ty, MVT &VT);
173 bool isTypeSupported(Type *Ty, MVT &VT);
174 bool isLoadTypeLegal(Type *Ty, MVT &VT);
175 bool computeAddress(const Value *Obj, Address &Addr);
176 bool computeCallAddress(const Value *V, Address &Addr);
177 void simplifyAddress(Address &Addr);
178
179 // Emit helper routines.
180 bool emitCmp(unsigned DestReg, const CmpInst *CI);
181 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr);
182 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr);
183 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
184 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
185
186 bool IsZExt);
187 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
188
189 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
190 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
191 unsigned DestReg);
192 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
193 unsigned DestReg);
194
195 unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
196
197 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
198 const Value *RHS);
199
200 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
201 unsigned materializeGV(const GlobalValue *GV, MVT VT);
202 unsigned materializeInt(const Constant *C, MVT VT);
203 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
204 unsigned materializeExternalCallSym(MCSymbol *Syn);
205
206 MachineInstrBuilder emitInst(unsigned Opc) {
207 return BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc));
208 }
209
210 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
211 return BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc),
212 DestReg: DstReg);
213 }
214
215 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
216 unsigned MemReg, int64_t MemOffset) {
217 return emitInst(Opc).addReg(RegNo: SrcReg).addReg(RegNo: MemReg).addImm(Val: MemOffset);
218 }
219
220 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
221 unsigned MemReg, int64_t MemOffset) {
222 return emitInst(Opc, DstReg).addReg(RegNo: MemReg).addImm(Val: MemOffset);
223 }
224
225 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
226 const TargetRegisterClass *RC,
227 unsigned Op0, unsigned Op1);
228
229 // for some reason, this default is not generated by tablegen
230 // so we explicitly generate it here.
231 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
232 unsigned Op0, uint64_t imm1, uint64_t imm2,
233 unsigned Op3) {
234 return 0;
235 }
236
237 // Call handling routines.
238private:
239 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
240 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
241 unsigned &NumBytes);
242 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
243
244 const MipsABIInfo &getABI() const {
245 return static_cast<const MipsTargetMachine &>(TM).getABI();
246 }
247
248public:
249 // Backend specific FastISel code.
250 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
251 const TargetLibraryInfo *libInfo)
252 : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
253 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
254 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
255 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
256 Context = &funcInfo.Fn->getContext();
257 UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
258 }
259
260 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
261 unsigned fastMaterializeConstant(const Constant *C) override;
262 bool fastSelectInstruction(const Instruction *I) override;
263
264#include "MipsGenFastISel.inc"
265};
266
267} // end anonymous namespace
268
269static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
270 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
271 CCState &State) LLVM_ATTRIBUTE_UNUSED;
272
273static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
274 CCValAssign::LocInfo LocInfo,
275 ISD::ArgFlagsTy ArgFlags, CCState &State) {
276 llvm_unreachable("should not be called");
277}
278
279static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
280 CCValAssign::LocInfo LocInfo,
281 ISD::ArgFlagsTy ArgFlags, CCState &State) {
282 llvm_unreachable("should not be called");
283}
284
285#include "MipsGenCallingConv.inc"
286
287CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
288 return CC_MipsO32;
289}
290
291unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
292 const Value *LHS, const Value *RHS) {
293 // Canonicalize immediates to the RHS first.
294 if (isa<ConstantInt>(Val: LHS) && !isa<ConstantInt>(Val: RHS))
295 std::swap(a&: LHS, b&: RHS);
296
297 unsigned Opc;
298 switch (ISDOpc) {
299 case ISD::AND:
300 Opc = Mips::AND;
301 break;
302 case ISD::OR:
303 Opc = Mips::OR;
304 break;
305 case ISD::XOR:
306 Opc = Mips::XOR;
307 break;
308 default:
309 llvm_unreachable("unexpected opcode");
310 }
311
312 Register LHSReg = getRegForValue(V: LHS);
313 if (!LHSReg)
314 return 0;
315
316 unsigned RHSReg;
317 if (const auto *C = dyn_cast<ConstantInt>(Val: RHS))
318 RHSReg = materializeInt(C, VT: MVT::i32);
319 else
320 RHSReg = getRegForValue(V: RHS);
321 if (!RHSReg)
322 return 0;
323
324 Register ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
325 if (!ResultReg)
326 return 0;
327
328 emitInst(Opc, DstReg: ResultReg).addReg(RegNo: LHSReg).addReg(RegNo: RHSReg);
329 return ResultReg;
330}
331
332unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
333 assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
334 "Alloca should always return a pointer.");
335
336 DenseMap<const AllocaInst *, int>::iterator SI =
337 FuncInfo.StaticAllocaMap.find(Val: AI);
338
339 if (SI != FuncInfo.StaticAllocaMap.end()) {
340 Register ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
341 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Mips::LEA_ADDiu),
342 DestReg: ResultReg)
343 .addFrameIndex(Idx: SI->second)
344 .addImm(Val: 0);
345 return ResultReg;
346 }
347
348 return 0;
349}
350
351unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
352 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
353 return 0;
354 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
355 const ConstantInt *CI = cast<ConstantInt>(Val: C);
356 return materialize32BitInt(Imm: CI->getZExtValue(), RC);
357}
358
359unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
360 const TargetRegisterClass *RC) {
361 Register ResultReg = createResultReg(RC);
362
363 if (isInt<16>(x: Imm)) {
364 unsigned Opc = Mips::ADDiu;
365 emitInst(Opc, DstReg: ResultReg).addReg(RegNo: Mips::ZERO).addImm(Val: Imm);
366 return ResultReg;
367 } else if (isUInt<16>(x: Imm)) {
368 emitInst(Opc: Mips::ORi, DstReg: ResultReg).addReg(RegNo: Mips::ZERO).addImm(Val: Imm);
369 return ResultReg;
370 }
371 unsigned Lo = Imm & 0xFFFF;
372 unsigned Hi = (Imm >> 16) & 0xFFFF;
373 if (Lo) {
374 // Both Lo and Hi have nonzero bits.
375 Register TmpReg = createResultReg(RC);
376 emitInst(Opc: Mips::LUi, DstReg: TmpReg).addImm(Val: Hi);
377 emitInst(Opc: Mips::ORi, DstReg: ResultReg).addReg(RegNo: TmpReg).addImm(Val: Lo);
378 } else {
379 emitInst(Opc: Mips::LUi, DstReg: ResultReg).addImm(Val: Hi);
380 }
381 return ResultReg;
382}
383
384unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
385 if (UnsupportedFPMode)
386 return 0;
387 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
388 if (VT == MVT::f32) {
389 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
390 Register DestReg = createResultReg(RC);
391 unsigned TempReg = materialize32BitInt(Imm, RC: &Mips::GPR32RegClass);
392 emitInst(Opc: Mips::MTC1, DstReg: DestReg).addReg(RegNo: TempReg);
393 return DestReg;
394 } else if (VT == MVT::f64) {
395 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
396 Register DestReg = createResultReg(RC);
397 unsigned TempReg1 = materialize32BitInt(Imm: Imm >> 32, RC: &Mips::GPR32RegClass);
398 unsigned TempReg2 =
399 materialize32BitInt(Imm: Imm & 0xFFFFFFFF, RC: &Mips::GPR32RegClass);
400 emitInst(Opc: Mips::BuildPairF64, DstReg: DestReg).addReg(RegNo: TempReg2).addReg(RegNo: TempReg1);
401 return DestReg;
402 }
403 return 0;
404}
405
406unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
407 // For now 32-bit only.
408 if (VT != MVT::i32)
409 return 0;
410 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
411 Register DestReg = createResultReg(RC);
412 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(Val: GV);
413 bool IsThreadLocal = GVar && GVar->isThreadLocal();
414 // TLS not supported at this time.
415 if (IsThreadLocal)
416 return 0;
417 emitInst(Opc: Mips::LW, DstReg: DestReg)
418 .addReg(RegNo: MFI->getGlobalBaseReg(MF&: *MF))
419 .addGlobalAddress(GV, Offset: 0, TargetFlags: MipsII::MO_GOT);
420 if ((GV->hasInternalLinkage() ||
421 (GV->hasLocalLinkage() && !isa<Function>(Val: GV)))) {
422 Register TempReg = createResultReg(RC);
423 emitInst(Opc: Mips::ADDiu, DstReg: TempReg)
424 .addReg(RegNo: DestReg)
425 .addGlobalAddress(GV, Offset: 0, TargetFlags: MipsII::MO_ABS_LO);
426 DestReg = TempReg;
427 }
428 return DestReg;
429}
430
431unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
432 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
433 Register DestReg = createResultReg(RC);
434 emitInst(Opc: Mips::LW, DstReg: DestReg)
435 .addReg(RegNo: MFI->getGlobalBaseReg(MF&: *MF))
436 .addSym(Sym, TargetFlags: MipsII::MO_GOT);
437 return DestReg;
438}
439
440// Materialize a constant into a register, and return the register
441// number (or zero if we failed to handle it).
442unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
443 EVT CEVT = TLI.getValueType(DL, Ty: C->getType(), AllowUnknown: true);
444
445 // Only handle simple types.
446 if (!CEVT.isSimple())
447 return 0;
448 MVT VT = CEVT.getSimpleVT();
449
450 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Val: C))
451 return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
452 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(Val: C))
453 return materializeGV(GV, VT);
454 else if (isa<ConstantInt>(Val: C))
455 return materializeInt(C, VT);
456
457 return 0;
458}
459
460bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
461 const User *U = nullptr;
462 unsigned Opcode = Instruction::UserOp1;
463 if (const Instruction *I = dyn_cast<Instruction>(Val: Obj)) {
464 // Don't walk into other basic blocks unless the object is an alloca from
465 // another block, otherwise it may not have a virtual register assigned.
466 if (FuncInfo.StaticAllocaMap.count(Val: static_cast<const AllocaInst *>(Obj)) ||
467 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
468 Opcode = I->getOpcode();
469 U = I;
470 }
471 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Val: Obj)) {
472 Opcode = C->getOpcode();
473 U = C;
474 }
475 switch (Opcode) {
476 default:
477 break;
478 case Instruction::BitCast:
479 // Look through bitcasts.
480 return computeAddress(Obj: U->getOperand(i: 0), Addr);
481 case Instruction::GetElementPtr: {
482 Address SavedAddr = Addr;
483 int64_t TmpOffset = Addr.getOffset();
484 // Iterate through the GEP folding the constants into offsets where
485 // we can.
486 gep_type_iterator GTI = gep_type_begin(GEP: U);
487 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
488 ++i, ++GTI) {
489 const Value *Op = *i;
490 if (StructType *STy = GTI.getStructTypeOrNull()) {
491 const StructLayout *SL = DL.getStructLayout(Ty: STy);
492 unsigned Idx = cast<ConstantInt>(Val: Op)->getZExtValue();
493 TmpOffset += SL->getElementOffset(Idx);
494 } else {
495 uint64_t S = GTI.getSequentialElementStride(DL);
496 while (true) {
497 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: Op)) {
498 // Constant-offset addressing.
499 TmpOffset += CI->getSExtValue() * S;
500 break;
501 }
502 if (canFoldAddIntoGEP(GEP: U, Add: Op)) {
503 // A compatible add with a constant operand. Fold the constant.
504 ConstantInt *CI =
505 cast<ConstantInt>(Val: cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 1));
506 TmpOffset += CI->getSExtValue() * S;
507 // Iterate on the other operand.
508 Op = cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 0);
509 continue;
510 }
511 // Unsupported
512 goto unsupported_gep;
513 }
514 }
515 }
516 // Try to grab the base operand now.
517 Addr.setOffset(TmpOffset);
518 if (computeAddress(Obj: U->getOperand(i: 0), Addr))
519 return true;
520 // We failed, restore everything and try the other options.
521 Addr = SavedAddr;
522 unsupported_gep:
523 break;
524 }
525 case Instruction::Alloca: {
526 const AllocaInst *AI = cast<AllocaInst>(Val: Obj);
527 DenseMap<const AllocaInst *, int>::iterator SI =
528 FuncInfo.StaticAllocaMap.find(Val: AI);
529 if (SI != FuncInfo.StaticAllocaMap.end()) {
530 Addr.setKind(Address::FrameIndexBase);
531 Addr.setFI(SI->second);
532 return true;
533 }
534 break;
535 }
536 }
537 Addr.setReg(getRegForValue(V: Obj));
538 return Addr.getReg() != 0;
539}
540
541bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
542 const User *U = nullptr;
543 unsigned Opcode = Instruction::UserOp1;
544
545 if (const auto *I = dyn_cast<Instruction>(Val: V)) {
546 // Check if the value is defined in the same basic block. This information
547 // is crucial to know whether or not folding an operand is valid.
548 if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
549 Opcode = I->getOpcode();
550 U = I;
551 }
552 } else if (const auto *C = dyn_cast<ConstantExpr>(Val: V)) {
553 Opcode = C->getOpcode();
554 U = C;
555 }
556
557 switch (Opcode) {
558 default:
559 break;
560 case Instruction::BitCast:
561 // Look past bitcasts if its operand is in the same BB.
562 return computeCallAddress(V: U->getOperand(i: 0), Addr);
563 break;
564 case Instruction::IntToPtr:
565 // Look past no-op inttoptrs if its operand is in the same BB.
566 if (TLI.getValueType(DL, Ty: U->getOperand(i: 0)->getType()) ==
567 TLI.getPointerTy(DL))
568 return computeCallAddress(V: U->getOperand(i: 0), Addr);
569 break;
570 case Instruction::PtrToInt:
571 // Look past no-op ptrtoints if its operand is in the same BB.
572 if (TLI.getValueType(DL, Ty: U->getType()) == TLI.getPointerTy(DL))
573 return computeCallAddress(V: U->getOperand(i: 0), Addr);
574 break;
575 }
576
577 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Val: V)) {
578 Addr.setGlobalValue(GV);
579 return true;
580 }
581
582 // If all else fails, try to materialize the value in a register.
583 if (!Addr.getGlobalValue()) {
584 Addr.setReg(getRegForValue(V));
585 return Addr.getReg() != 0;
586 }
587
588 return false;
589}
590
591bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
592 EVT evt = TLI.getValueType(DL, Ty, AllowUnknown: true);
593 // Only handle simple types.
594 if (evt == MVT::Other || !evt.isSimple())
595 return false;
596 VT = evt.getSimpleVT();
597
598 // Handle all legal types, i.e. a register that will directly hold this
599 // value.
600 return TLI.isTypeLegal(VT);
601}
602
603bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
604 if (Ty->isVectorTy())
605 return false;
606
607 if (isTypeLegal(Ty, VT))
608 return true;
609
610 // If this is a type than can be sign or zero-extended to a basic operation
611 // go ahead and accept it now.
612 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
613 return true;
614
615 return false;
616}
617
618bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
619 if (isTypeLegal(Ty, VT))
620 return true;
621 // We will extend this in a later patch:
622 // If this is a type than can be sign or zero-extended to a basic operation
623 // go ahead and accept it now.
624 if (VT == MVT::i8 || VT == MVT::i16)
625 return true;
626 return false;
627}
628
629// Because of how EmitCmp is called with fast-isel, you can
630// end up with redundant "andi" instructions after the sequences emitted below.
631// We should try and solve this issue in the future.
632//
633bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
634 const Value *Left = CI->getOperand(i_nocapture: 0), *Right = CI->getOperand(i_nocapture: 1);
635 bool IsUnsigned = CI->isUnsigned();
636 unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
637 if (LeftReg == 0)
638 return false;
639 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
640 if (RightReg == 0)
641 return false;
642 CmpInst::Predicate P = CI->getPredicate();
643
644 switch (P) {
645 default:
646 return false;
647 case CmpInst::ICMP_EQ: {
648 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
649 emitInst(Opc: Mips::XOR, DstReg: TempReg).addReg(RegNo: LeftReg).addReg(RegNo: RightReg);
650 emitInst(Opc: Mips::SLTiu, DstReg: ResultReg).addReg(RegNo: TempReg).addImm(Val: 1);
651 break;
652 }
653 case CmpInst::ICMP_NE: {
654 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
655 emitInst(Opc: Mips::XOR, DstReg: TempReg).addReg(RegNo: LeftReg).addReg(RegNo: RightReg);
656 emitInst(Opc: Mips::SLTu, DstReg: ResultReg).addReg(RegNo: Mips::ZERO).addReg(RegNo: TempReg);
657 break;
658 }
659 case CmpInst::ICMP_UGT:
660 emitInst(Opc: Mips::SLTu, DstReg: ResultReg).addReg(RegNo: RightReg).addReg(RegNo: LeftReg);
661 break;
662 case CmpInst::ICMP_ULT:
663 emitInst(Opc: Mips::SLTu, DstReg: ResultReg).addReg(RegNo: LeftReg).addReg(RegNo: RightReg);
664 break;
665 case CmpInst::ICMP_UGE: {
666 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
667 emitInst(Opc: Mips::SLTu, DstReg: TempReg).addReg(RegNo: LeftReg).addReg(RegNo: RightReg);
668 emitInst(Opc: Mips::XORi, DstReg: ResultReg).addReg(RegNo: TempReg).addImm(Val: 1);
669 break;
670 }
671 case CmpInst::ICMP_ULE: {
672 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
673 emitInst(Opc: Mips::SLTu, DstReg: TempReg).addReg(RegNo: RightReg).addReg(RegNo: LeftReg);
674 emitInst(Opc: Mips::XORi, DstReg: ResultReg).addReg(RegNo: TempReg).addImm(Val: 1);
675 break;
676 }
677 case CmpInst::ICMP_SGT:
678 emitInst(Opc: Mips::SLT, DstReg: ResultReg).addReg(RegNo: RightReg).addReg(RegNo: LeftReg);
679 break;
680 case CmpInst::ICMP_SLT:
681 emitInst(Opc: Mips::SLT, DstReg: ResultReg).addReg(RegNo: LeftReg).addReg(RegNo: RightReg);
682 break;
683 case CmpInst::ICMP_SGE: {
684 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
685 emitInst(Opc: Mips::SLT, DstReg: TempReg).addReg(RegNo: LeftReg).addReg(RegNo: RightReg);
686 emitInst(Opc: Mips::XORi, DstReg: ResultReg).addReg(RegNo: TempReg).addImm(Val: 1);
687 break;
688 }
689 case CmpInst::ICMP_SLE: {
690 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
691 emitInst(Opc: Mips::SLT, DstReg: TempReg).addReg(RegNo: RightReg).addReg(RegNo: LeftReg);
692 emitInst(Opc: Mips::XORi, DstReg: ResultReg).addReg(RegNo: TempReg).addImm(Val: 1);
693 break;
694 }
695 case CmpInst::FCMP_OEQ:
696 case CmpInst::FCMP_UNE:
697 case CmpInst::FCMP_OLT:
698 case CmpInst::FCMP_OLE:
699 case CmpInst::FCMP_OGT:
700 case CmpInst::FCMP_OGE: {
701 if (UnsupportedFPMode)
702 return false;
703 bool IsFloat = Left->getType()->isFloatTy();
704 bool IsDouble = Left->getType()->isDoubleTy();
705 if (!IsFloat && !IsDouble)
706 return false;
707 unsigned Opc, CondMovOpc;
708 switch (P) {
709 case CmpInst::FCMP_OEQ:
710 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
711 CondMovOpc = Mips::MOVT_I;
712 break;
713 case CmpInst::FCMP_UNE:
714 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
715 CondMovOpc = Mips::MOVF_I;
716 break;
717 case CmpInst::FCMP_OLT:
718 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
719 CondMovOpc = Mips::MOVT_I;
720 break;
721 case CmpInst::FCMP_OLE:
722 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
723 CondMovOpc = Mips::MOVT_I;
724 break;
725 case CmpInst::FCMP_OGT:
726 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
727 CondMovOpc = Mips::MOVF_I;
728 break;
729 case CmpInst::FCMP_OGE:
730 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
731 CondMovOpc = Mips::MOVF_I;
732 break;
733 default:
734 llvm_unreachable("Only switching of a subset of CCs.");
735 }
736 Register RegWithZero = createResultReg(RC: &Mips::GPR32RegClass);
737 Register RegWithOne = createResultReg(RC: &Mips::GPR32RegClass);
738 emitInst(Opc: Mips::ADDiu, DstReg: RegWithZero).addReg(RegNo: Mips::ZERO).addImm(Val: 0);
739 emitInst(Opc: Mips::ADDiu, DstReg: RegWithOne).addReg(RegNo: Mips::ZERO).addImm(Val: 1);
740 emitInst(Opc).addReg(RegNo: Mips::FCC0, flags: RegState::Define).addReg(RegNo: LeftReg)
741 .addReg(RegNo: RightReg);
742 emitInst(Opc: CondMovOpc, DstReg: ResultReg)
743 .addReg(RegNo: RegWithOne)
744 .addReg(RegNo: Mips::FCC0)
745 .addReg(RegNo: RegWithZero);
746 break;
747 }
748 }
749 return true;
750}
751
752bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr) {
753 //
754 // more cases will be handled here in following patches.
755 //
756 unsigned Opc;
757 switch (VT.SimpleTy) {
758 case MVT::i32:
759 ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
760 Opc = Mips::LW;
761 break;
762 case MVT::i16:
763 ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
764 Opc = Mips::LHu;
765 break;
766 case MVT::i8:
767 ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
768 Opc = Mips::LBu;
769 break;
770 case MVT::f32:
771 if (UnsupportedFPMode)
772 return false;
773 ResultReg = createResultReg(RC: &Mips::FGR32RegClass);
774 Opc = Mips::LWC1;
775 break;
776 case MVT::f64:
777 if (UnsupportedFPMode)
778 return false;
779 ResultReg = createResultReg(RC: &Mips::AFGR64RegClass);
780 Opc = Mips::LDC1;
781 break;
782 default:
783 return false;
784 }
785 if (Addr.isRegBase()) {
786 simplifyAddress(Addr);
787 emitInstLoad(Opc, DstReg: ResultReg, MemReg: Addr.getReg(), MemOffset: Addr.getOffset());
788 return true;
789 }
790 if (Addr.isFIBase()) {
791 unsigned FI = Addr.getFI();
792 int64_t Offset = Addr.getOffset();
793 MachineFrameInfo &MFI = MF->getFrameInfo();
794 MachineMemOperand *MMO = MF->getMachineMemOperand(
795 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI), F: MachineMemOperand::MOLoad,
796 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: Align(4));
797 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
798 .addFrameIndex(Idx: FI)
799 .addImm(Val: Offset)
800 .addMemOperand(MMO);
801 return true;
802 }
803 return false;
804}
805
806bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr) {
807 //
808 // more cases will be handled here in following patches.
809 //
810 unsigned Opc;
811 switch (VT.SimpleTy) {
812 case MVT::i8:
813 Opc = Mips::SB;
814 break;
815 case MVT::i16:
816 Opc = Mips::SH;
817 break;
818 case MVT::i32:
819 Opc = Mips::SW;
820 break;
821 case MVT::f32:
822 if (UnsupportedFPMode)
823 return false;
824 Opc = Mips::SWC1;
825 break;
826 case MVT::f64:
827 if (UnsupportedFPMode)
828 return false;
829 Opc = Mips::SDC1;
830 break;
831 default:
832 return false;
833 }
834 if (Addr.isRegBase()) {
835 simplifyAddress(Addr);
836 emitInstStore(Opc, SrcReg, MemReg: Addr.getReg(), MemOffset: Addr.getOffset());
837 return true;
838 }
839 if (Addr.isFIBase()) {
840 unsigned FI = Addr.getFI();
841 int64_t Offset = Addr.getOffset();
842 MachineFrameInfo &MFI = MF->getFrameInfo();
843 MachineMemOperand *MMO = MF->getMachineMemOperand(
844 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI), F: MachineMemOperand::MOStore,
845 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: Align(4));
846 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc))
847 .addReg(RegNo: SrcReg)
848 .addFrameIndex(Idx: FI)
849 .addImm(Val: Offset)
850 .addMemOperand(MMO);
851 return true;
852 }
853 return false;
854}
855
856bool MipsFastISel::selectLogicalOp(const Instruction *I) {
857 MVT VT;
858 if (!isTypeSupported(Ty: I->getType(), VT))
859 return false;
860
861 unsigned ResultReg;
862 switch (I->getOpcode()) {
863 default:
864 llvm_unreachable("Unexpected instruction.");
865 case Instruction::And:
866 ResultReg = emitLogicalOp(ISDOpc: ISD::AND, RetVT: VT, LHS: I->getOperand(i: 0), RHS: I->getOperand(i: 1));
867 break;
868 case Instruction::Or:
869 ResultReg = emitLogicalOp(ISDOpc: ISD::OR, RetVT: VT, LHS: I->getOperand(i: 0), RHS: I->getOperand(i: 1));
870 break;
871 case Instruction::Xor:
872 ResultReg = emitLogicalOp(ISDOpc: ISD::XOR, RetVT: VT, LHS: I->getOperand(i: 0), RHS: I->getOperand(i: 1));
873 break;
874 }
875
876 if (!ResultReg)
877 return false;
878
879 updateValueMap(I, Reg: ResultReg);
880 return true;
881}
882
883bool MipsFastISel::selectLoad(const Instruction *I) {
884 // Atomic loads need special handling.
885 if (cast<LoadInst>(Val: I)->isAtomic())
886 return false;
887
888 // Verify we have a legal type before going any further.
889 MVT VT;
890 if (!isLoadTypeLegal(Ty: I->getType(), VT))
891 return false;
892
893 // See if we can handle this address.
894 Address Addr;
895 if (!computeAddress(Obj: I->getOperand(i: 0), Addr))
896 return false;
897
898 unsigned ResultReg;
899 if (!emitLoad(VT, ResultReg, Addr))
900 return false;
901 updateValueMap(I, Reg: ResultReg);
902 return true;
903}
904
905bool MipsFastISel::selectStore(const Instruction *I) {
906 Value *Op0 = I->getOperand(i: 0);
907 unsigned SrcReg = 0;
908
909 // Atomic stores need special handling.
910 if (cast<StoreInst>(Val: I)->isAtomic())
911 return false;
912
913 // Verify we have a legal type before going any further.
914 MVT VT;
915 if (!isLoadTypeLegal(Ty: I->getOperand(i: 0)->getType(), VT))
916 return false;
917
918 // Get the value to be stored into a register.
919 SrcReg = getRegForValue(V: Op0);
920 if (SrcReg == 0)
921 return false;
922
923 // See if we can handle this address.
924 Address Addr;
925 if (!computeAddress(Obj: I->getOperand(i: 1), Addr))
926 return false;
927
928 if (!emitStore(VT, SrcReg, Addr))
929 return false;
930 return true;
931}
932
933// This can cause a redundant sltiu to be generated.
934// FIXME: try and eliminate this in a future patch.
935bool MipsFastISel::selectBranch(const Instruction *I) {
936 const BranchInst *BI = cast<BranchInst>(Val: I);
937 MachineBasicBlock *BrBB = FuncInfo.MBB;
938 //
939 // TBB is the basic block for the case where the comparison is true.
940 // FBB is the basic block for the case where the comparison is false.
941 // if (cond) goto TBB
942 // goto FBB
943 // TBB:
944 //
945 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(i: 0)];
946 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(i: 1)];
947
948 // Fold the common case of a conditional branch with a comparison
949 // in the same block.
950 unsigned ZExtCondReg = 0;
951 if (const CmpInst *CI = dyn_cast<CmpInst>(Val: BI->getCondition())) {
952 if (CI->hasOneUse() && CI->getParent() == I->getParent()) {
953 ZExtCondReg = createResultReg(RC: &Mips::GPR32RegClass);
954 if (!emitCmp(ResultReg: ZExtCondReg, CI))
955 return false;
956 }
957 }
958
959 // For the general case, we need to mask with 1.
960 if (ZExtCondReg == 0) {
961 Register CondReg = getRegForValue(V: BI->getCondition());
962 if (CondReg == 0)
963 return false;
964
965 ZExtCondReg = emitIntExt(SrcVT: MVT::i1, SrcReg: CondReg, DestVT: MVT::i32, isZExt: true);
966 if (ZExtCondReg == 0)
967 return false;
968 }
969
970 BuildMI(BB&: *BrBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Mips::BGTZ))
971 .addReg(RegNo: ZExtCondReg)
972 .addMBB(MBB: TBB);
973 finishCondBranch(BranchBB: BI->getParent(), TrueMBB: TBB, FalseMBB: FBB);
974 return true;
975}
976
977bool MipsFastISel::selectCmp(const Instruction *I) {
978 const CmpInst *CI = cast<CmpInst>(Val: I);
979 Register ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
980 if (!emitCmp(ResultReg, CI))
981 return false;
982 updateValueMap(I, Reg: ResultReg);
983 return true;
984}
985
986// Attempt to fast-select a floating-point extend instruction.
987bool MipsFastISel::selectFPExt(const Instruction *I) {
988 if (UnsupportedFPMode)
989 return false;
990 Value *Src = I->getOperand(i: 0);
991 EVT SrcVT = TLI.getValueType(DL, Ty: Src->getType(), AllowUnknown: true);
992 EVT DestVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
993
994 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
995 return false;
996
997 Register SrcReg =
998 getRegForValue(V: Src); // this must be a 32bit floating point register class
999 // maybe we should handle this differently
1000 if (!SrcReg)
1001 return false;
1002
1003 Register DestReg = createResultReg(RC: &Mips::AFGR64RegClass);
1004 emitInst(Opc: Mips::CVT_D32_S, DstReg: DestReg).addReg(RegNo: SrcReg);
1005 updateValueMap(I, Reg: DestReg);
1006 return true;
1007}
1008
1009bool MipsFastISel::selectSelect(const Instruction *I) {
1010 assert(isa<SelectInst>(I) && "Expected a select instruction.");
1011
1012 LLVM_DEBUG(dbgs() << "selectSelect\n");
1013
1014 MVT VT;
1015 if (!isTypeSupported(Ty: I->getType(), VT) || UnsupportedFPMode) {
1016 LLVM_DEBUG(
1017 dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
1018 return false;
1019 }
1020
1021 unsigned CondMovOpc;
1022 const TargetRegisterClass *RC;
1023
1024 if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
1025 CondMovOpc = Mips::MOVN_I_I;
1026 RC = &Mips::GPR32RegClass;
1027 } else if (VT == MVT::f32) {
1028 CondMovOpc = Mips::MOVN_I_S;
1029 RC = &Mips::FGR32RegClass;
1030 } else if (VT == MVT::f64) {
1031 CondMovOpc = Mips::MOVN_I_D32;
1032 RC = &Mips::AFGR64RegClass;
1033 } else
1034 return false;
1035
1036 const SelectInst *SI = cast<SelectInst>(Val: I);
1037 const Value *Cond = SI->getCondition();
1038 Register Src1Reg = getRegForValue(V: SI->getTrueValue());
1039 Register Src2Reg = getRegForValue(V: SI->getFalseValue());
1040 Register CondReg = getRegForValue(V: Cond);
1041
1042 if (!Src1Reg || !Src2Reg || !CondReg)
1043 return false;
1044
1045 Register ZExtCondReg = createResultReg(RC: &Mips::GPR32RegClass);
1046 if (!ZExtCondReg)
1047 return false;
1048
1049 if (!emitIntExt(SrcVT: MVT::i1, SrcReg: CondReg, DestVT: MVT::i32, DestReg: ZExtCondReg, IsZExt: true))
1050 return false;
1051
1052 Register ResultReg = createResultReg(RC);
1053 Register TempReg = createResultReg(RC);
1054
1055 if (!ResultReg || !TempReg)
1056 return false;
1057
1058 emitInst(Opc: TargetOpcode::COPY, DstReg: TempReg).addReg(RegNo: Src2Reg);
1059 emitInst(Opc: CondMovOpc, DstReg: ResultReg)
1060 .addReg(RegNo: Src1Reg).addReg(RegNo: ZExtCondReg).addReg(RegNo: TempReg);
1061 updateValueMap(I, Reg: ResultReg);
1062 return true;
1063}
1064
1065// Attempt to fast-select a floating-point truncate instruction.
1066bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1067 if (UnsupportedFPMode)
1068 return false;
1069 Value *Src = I->getOperand(i: 0);
1070 EVT SrcVT = TLI.getValueType(DL, Ty: Src->getType(), AllowUnknown: true);
1071 EVT DestVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
1072
1073 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1074 return false;
1075
1076 Register SrcReg = getRegForValue(V: Src);
1077 if (!SrcReg)
1078 return false;
1079
1080 Register DestReg = createResultReg(RC: &Mips::FGR32RegClass);
1081 if (!DestReg)
1082 return false;
1083
1084 emitInst(Opc: Mips::CVT_S_D32, DstReg: DestReg).addReg(RegNo: SrcReg);
1085 updateValueMap(I, Reg: DestReg);
1086 return true;
1087}
1088
1089// Attempt to fast-select a floating-point-to-integer conversion.
1090bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1091 if (UnsupportedFPMode)
1092 return false;
1093 MVT DstVT, SrcVT;
1094 if (!IsSigned)
1095 return false; // We don't handle this case yet. There is no native
1096 // instruction for this but it can be synthesized.
1097 Type *DstTy = I->getType();
1098 if (!isTypeLegal(Ty: DstTy, VT&: DstVT))
1099 return false;
1100
1101 if (DstVT != MVT::i32)
1102 return false;
1103
1104 Value *Src = I->getOperand(i: 0);
1105 Type *SrcTy = Src->getType();
1106 if (!isTypeLegal(Ty: SrcTy, VT&: SrcVT))
1107 return false;
1108
1109 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1110 return false;
1111
1112 Register SrcReg = getRegForValue(V: Src);
1113 if (SrcReg == 0)
1114 return false;
1115
1116 // Determine the opcode for the conversion, which takes place
1117 // entirely within FPRs.
1118 Register DestReg = createResultReg(RC: &Mips::GPR32RegClass);
1119 Register TempReg = createResultReg(RC: &Mips::FGR32RegClass);
1120 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1121
1122 // Generate the convert.
1123 emitInst(Opc, DstReg: TempReg).addReg(RegNo: SrcReg);
1124 emitInst(Opc: Mips::MFC1, DstReg: DestReg).addReg(RegNo: TempReg);
1125
1126 updateValueMap(I, Reg: DestReg);
1127 return true;
1128}
1129
1130bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1131 SmallVectorImpl<MVT> &OutVTs,
1132 unsigned &NumBytes) {
1133 CallingConv::ID CC = CLI.CallConv;
1134 SmallVector<CCValAssign, 16> ArgLocs;
1135 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1136 CCInfo.AnalyzeCallOperands(ArgVTs&: OutVTs, Flags&: CLI.OutFlags, Fn: CCAssignFnForCall(CC));
1137 // Get a count of how many bytes are to be pushed on the stack.
1138 NumBytes = CCInfo.getStackSize();
1139 // This is the minimum argument area used for A0-A3.
1140 if (NumBytes < 16)
1141 NumBytes = 16;
1142
1143 emitInst(Opc: Mips::ADJCALLSTACKDOWN).addImm(Val: 16).addImm(Val: 0);
1144 // Process the args.
1145 MVT firstMVT;
1146 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1147 CCValAssign &VA = ArgLocs[i];
1148 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1149 MVT ArgVT = OutVTs[VA.getValNo()];
1150
1151 if (i == 0) {
1152 firstMVT = ArgVT;
1153 if (ArgVT == MVT::f32) {
1154 VA.convertToReg(RegNo: Mips::F12);
1155 } else if (ArgVT == MVT::f64) {
1156 if (Subtarget->isFP64bit())
1157 VA.convertToReg(RegNo: Mips::D6_64);
1158 else
1159 VA.convertToReg(RegNo: Mips::D6);
1160 }
1161 } else if (i == 1) {
1162 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1163 if (ArgVT == MVT::f32) {
1164 VA.convertToReg(RegNo: Mips::F14);
1165 } else if (ArgVT == MVT::f64) {
1166 if (Subtarget->isFP64bit())
1167 VA.convertToReg(RegNo: Mips::D7_64);
1168 else
1169 VA.convertToReg(RegNo: Mips::D7);
1170 }
1171 }
1172 }
1173 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1174 (ArgVT == MVT::i8)) &&
1175 VA.isMemLoc()) {
1176 switch (VA.getLocMemOffset()) {
1177 case 0:
1178 VA.convertToReg(RegNo: Mips::A0);
1179 break;
1180 case 4:
1181 VA.convertToReg(RegNo: Mips::A1);
1182 break;
1183 case 8:
1184 VA.convertToReg(RegNo: Mips::A2);
1185 break;
1186 case 12:
1187 VA.convertToReg(RegNo: Mips::A3);
1188 break;
1189 default:
1190 break;
1191 }
1192 }
1193 Register ArgReg = getRegForValue(V: ArgVal);
1194 if (!ArgReg)
1195 return false;
1196
1197 // Handle arg promotion: SExt, ZExt, AExt.
1198 switch (VA.getLocInfo()) {
1199 case CCValAssign::Full:
1200 break;
1201 case CCValAssign::AExt:
1202 case CCValAssign::SExt: {
1203 MVT DestVT = VA.getLocVT();
1204 MVT SrcVT = ArgVT;
1205 ArgReg = emitIntExt(SrcVT, SrcReg: ArgReg, DestVT, /*isZExt=*/false);
1206 if (!ArgReg)
1207 return false;
1208 break;
1209 }
1210 case CCValAssign::ZExt: {
1211 MVT DestVT = VA.getLocVT();
1212 MVT SrcVT = ArgVT;
1213 ArgReg = emitIntExt(SrcVT, SrcReg: ArgReg, DestVT, /*isZExt=*/true);
1214 if (!ArgReg)
1215 return false;
1216 break;
1217 }
1218 default:
1219 llvm_unreachable("Unknown arg promotion!");
1220 }
1221
1222 // Now copy/store arg to correct locations.
1223 if (VA.isRegLoc() && !VA.needsCustom()) {
1224 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1225 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: VA.getLocReg()).addReg(RegNo: ArgReg);
1226 CLI.OutRegs.push_back(Elt: VA.getLocReg());
1227 } else if (VA.needsCustom()) {
1228 llvm_unreachable("Mips does not use custom args.");
1229 return false;
1230 } else {
1231 //
1232 // FIXME: This path will currently return false. It was copied
1233 // from the AArch64 port and should be essentially fine for Mips too.
1234 // The work to finish up this path will be done in a follow-on patch.
1235 //
1236 assert(VA.isMemLoc() && "Assuming store on stack.");
1237 // Don't emit stores for undef values.
1238 if (isa<UndefValue>(Val: ArgVal))
1239 continue;
1240
1241 // Need to store on the stack.
1242 // FIXME: This alignment is incorrect but this path is disabled
1243 // for now (will return false). We need to determine the right alignment
1244 // based on the normal alignment for the underlying machine type.
1245 //
1246 unsigned ArgSize = alignTo(Size: ArgVT.getSizeInBits(), Align: 4);
1247
1248 unsigned BEAlign = 0;
1249 if (ArgSize < 8 && !Subtarget->isLittle())
1250 BEAlign = 8 - ArgSize;
1251
1252 Address Addr;
1253 Addr.setKind(Address::RegBase);
1254 Addr.setReg(Mips::SP);
1255 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1256
1257 Align Alignment = DL.getABITypeAlign(Ty: ArgVal->getType());
1258 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1259 PtrInfo: MachinePointerInfo::getStack(MF&: *FuncInfo.MF, Offset: Addr.getOffset()),
1260 F: MachineMemOperand::MOStore, Size: ArgVT.getStoreSize(), BaseAlignment: Alignment);
1261 (void)(MMO);
1262 // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1263 return false; // can't store on the stack yet.
1264 }
1265 }
1266
1267 return true;
1268}
1269
1270bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1271 unsigned NumBytes) {
1272 CallingConv::ID CC = CLI.CallConv;
1273 emitInst(Opc: Mips::ADJCALLSTACKUP).addImm(Val: 16).addImm(Val: 0);
1274 if (RetVT != MVT::isVoid) {
1275 SmallVector<CCValAssign, 16> RVLocs;
1276 MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1277
1278 CCInfo.AnalyzeCallResult(Ins: CLI.Ins, Fn: RetCC_Mips, RetTy: CLI.RetTy,
1279 Func: CLI.Symbol ? CLI.Symbol->getName().data()
1280 : nullptr);
1281
1282 // Only handle a single return value.
1283 if (RVLocs.size() != 1)
1284 return false;
1285 // Copy all of the result registers out of their specified physreg.
1286 MVT CopyVT = RVLocs[0].getValVT();
1287 // Special handling for extended integers.
1288 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1289 CopyVT = MVT::i32;
1290
1291 Register ResultReg = createResultReg(RC: TLI.getRegClassFor(VT: CopyVT));
1292 if (!ResultReg)
1293 return false;
1294 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1295 MCID: TII.get(Opcode: TargetOpcode::COPY),
1296 DestReg: ResultReg).addReg(RegNo: RVLocs[0].getLocReg());
1297 CLI.InRegs.push_back(Elt: RVLocs[0].getLocReg());
1298
1299 CLI.ResultReg = ResultReg;
1300 CLI.NumResultRegs = 1;
1301 }
1302 return true;
1303}
1304
1305bool MipsFastISel::fastLowerArguments() {
1306 LLVM_DEBUG(dbgs() << "fastLowerArguments\n");
1307
1308 if (!FuncInfo.CanLowerReturn) {
1309 LLVM_DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1310 return false;
1311 }
1312
1313 const Function *F = FuncInfo.Fn;
1314 if (F->isVarArg()) {
1315 LLVM_DEBUG(dbgs() << ".. gave up (varargs)\n");
1316 return false;
1317 }
1318
1319 CallingConv::ID CC = F->getCallingConv();
1320 if (CC != CallingConv::C) {
1321 LLVM_DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1322 return false;
1323 }
1324
1325 std::array<MCPhysReg, 4> GPR32ArgRegs = {._M_elems: {Mips::A0, Mips::A1, Mips::A2,
1326 Mips::A3}};
1327 std::array<MCPhysReg, 2> FGR32ArgRegs = {._M_elems: {Mips::F12, Mips::F14}};
1328 std::array<MCPhysReg, 2> AFGR64ArgRegs = {._M_elems: {Mips::D6, Mips::D7}};
1329 auto NextGPR32 = GPR32ArgRegs.begin();
1330 auto NextFGR32 = FGR32ArgRegs.begin();
1331 auto NextAFGR64 = AFGR64ArgRegs.begin();
1332
1333 struct AllocatedReg {
1334 const TargetRegisterClass *RC;
1335 unsigned Reg;
1336 AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1337 : RC(RC), Reg(Reg) {}
1338 };
1339
1340 // Only handle simple cases. i.e. All arguments are directly mapped to
1341 // registers of the appropriate type.
1342 SmallVector<AllocatedReg, 4> Allocation;
1343 for (const auto &FormalArg : F->args()) {
1344 if (FormalArg.hasAttribute(Kind: Attribute::InReg) ||
1345 FormalArg.hasAttribute(Kind: Attribute::StructRet) ||
1346 FormalArg.hasAttribute(Kind: Attribute::ByVal)) {
1347 LLVM_DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1348 return false;
1349 }
1350
1351 Type *ArgTy = FormalArg.getType();
1352 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1353 LLVM_DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1354 return false;
1355 }
1356
1357 EVT ArgVT = TLI.getValueType(DL, Ty: ArgTy);
1358 LLVM_DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
1359 << ArgVT << "\n");
1360 if (!ArgVT.isSimple()) {
1361 LLVM_DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1362 return false;
1363 }
1364
1365 switch (ArgVT.getSimpleVT().SimpleTy) {
1366 case MVT::i1:
1367 case MVT::i8:
1368 case MVT::i16:
1369 if (!FormalArg.hasAttribute(Kind: Attribute::SExt) &&
1370 !FormalArg.hasAttribute(Kind: Attribute::ZExt)) {
1371 // It must be any extend, this shouldn't happen for clang-generated IR
1372 // so just fall back on SelectionDAG.
1373 LLVM_DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1374 return false;
1375 }
1376
1377 if (NextGPR32 == GPR32ArgRegs.end()) {
1378 LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1379 return false;
1380 }
1381
1382 LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1383 Allocation.emplace_back(Args: &Mips::GPR32RegClass, Args&: *NextGPR32++);
1384
1385 // Allocating any GPR32 prohibits further use of floating point arguments.
1386 NextFGR32 = FGR32ArgRegs.end();
1387 NextAFGR64 = AFGR64ArgRegs.end();
1388 break;
1389
1390 case MVT::i32:
1391 if (FormalArg.hasAttribute(Kind: Attribute::ZExt)) {
1392 // The O32 ABI does not permit a zero-extended i32.
1393 LLVM_DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1394 return false;
1395 }
1396
1397 if (NextGPR32 == GPR32ArgRegs.end()) {
1398 LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1399 return false;
1400 }
1401
1402 LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1403 Allocation.emplace_back(Args: &Mips::GPR32RegClass, Args&: *NextGPR32++);
1404
1405 // Allocating any GPR32 prohibits further use of floating point arguments.
1406 NextFGR32 = FGR32ArgRegs.end();
1407 NextAFGR64 = AFGR64ArgRegs.end();
1408 break;
1409
1410 case MVT::f32:
1411 if (UnsupportedFPMode) {
1412 LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1413 return false;
1414 }
1415 if (NextFGR32 == FGR32ArgRegs.end()) {
1416 LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1417 return false;
1418 }
1419 LLVM_DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1420 Allocation.emplace_back(Args: &Mips::FGR32RegClass, Args&: *NextFGR32++);
1421 // Allocating an FGR32 also allocates the super-register AFGR64, and
1422 // ABI rules require us to skip the corresponding GPR32.
1423 if (NextGPR32 != GPR32ArgRegs.end())
1424 NextGPR32++;
1425 if (NextAFGR64 != AFGR64ArgRegs.end())
1426 NextAFGR64++;
1427 break;
1428
1429 case MVT::f64:
1430 if (UnsupportedFPMode) {
1431 LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1432 return false;
1433 }
1434 if (NextAFGR64 == AFGR64ArgRegs.end()) {
1435 LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1436 return false;
1437 }
1438 LLVM_DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1439 Allocation.emplace_back(Args: &Mips::AFGR64RegClass, Args&: *NextAFGR64++);
1440 // Allocating an FGR32 also allocates the super-register AFGR64, and
1441 // ABI rules require us to skip the corresponding GPR32 pair.
1442 if (NextGPR32 != GPR32ArgRegs.end())
1443 NextGPR32++;
1444 if (NextGPR32 != GPR32ArgRegs.end())
1445 NextGPR32++;
1446 if (NextFGR32 != FGR32ArgRegs.end())
1447 NextFGR32++;
1448 break;
1449
1450 default:
1451 LLVM_DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1452 return false;
1453 }
1454 }
1455
1456 for (const auto &FormalArg : F->args()) {
1457 unsigned ArgNo = FormalArg.getArgNo();
1458 unsigned SrcReg = Allocation[ArgNo].Reg;
1459 Register DstReg = FuncInfo.MF->addLiveIn(PReg: SrcReg, RC: Allocation[ArgNo].RC);
1460 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1461 // Without this, EmitLiveInCopies may eliminate the livein if its only
1462 // use is a bitcast (which isn't turned into an instruction).
1463 Register ResultReg = createResultReg(RC: Allocation[ArgNo].RC);
1464 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1465 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg)
1466 .addReg(RegNo: DstReg, flags: getKillRegState(B: true));
1467 updateValueMap(I: &FormalArg, Reg: ResultReg);
1468 }
1469
1470 // Calculate the size of the incoming arguments area.
1471 // We currently reject all the cases where this would be non-zero.
1472 unsigned IncomingArgSizeInBytes = 0;
1473
1474 // Account for the reserved argument area on ABI's that have one (O32).
1475 // It seems strange to do this on the caller side but it's necessary in
1476 // SelectionDAG's implementation.
1477 IncomingArgSizeInBytes = std::min(a: getABI().GetCalleeAllocdArgSizeInBytes(CC),
1478 b: IncomingArgSizeInBytes);
1479
1480 MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(Size: IncomingArgSizeInBytes,
1481 HasByval: false);
1482
1483 return true;
1484}
1485
1486bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1487 CallingConv::ID CC = CLI.CallConv;
1488 bool IsTailCall = CLI.IsTailCall;
1489 bool IsVarArg = CLI.IsVarArg;
1490 const Value *Callee = CLI.Callee;
1491 MCSymbol *Symbol = CLI.Symbol;
1492
1493 // Do not handle FastCC.
1494 if (CC == CallingConv::Fast)
1495 return false;
1496
1497 // Allow SelectionDAG isel to handle tail calls.
1498 if (IsTailCall)
1499 return false;
1500
1501 // Let SDISel handle vararg functions.
1502 if (IsVarArg)
1503 return false;
1504
1505 // FIXME: Only handle *simple* calls for now.
1506 MVT RetVT;
1507 if (CLI.RetTy->isVoidTy())
1508 RetVT = MVT::isVoid;
1509 else if (!isTypeSupported(Ty: CLI.RetTy, VT&: RetVT))
1510 return false;
1511
1512 for (auto Flag : CLI.OutFlags)
1513 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1514 return false;
1515
1516 // Set up the argument vectors.
1517 SmallVector<MVT, 16> OutVTs;
1518 OutVTs.reserve(N: CLI.OutVals.size());
1519
1520 for (auto *Val : CLI.OutVals) {
1521 MVT VT;
1522 if (!isTypeLegal(Ty: Val->getType(), VT) &&
1523 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1524 return false;
1525
1526 // We don't handle vector parameters yet.
1527 if (VT.isVector() || VT.getSizeInBits() > 64)
1528 return false;
1529
1530 OutVTs.push_back(Elt: VT);
1531 }
1532
1533 Address Addr;
1534 if (!computeCallAddress(V: Callee, Addr))
1535 return false;
1536
1537 // Handle the arguments now that we've gotten them.
1538 unsigned NumBytes;
1539 if (!processCallArgs(CLI, OutVTs, NumBytes))
1540 return false;
1541
1542 if (!Addr.getGlobalValue())
1543 return false;
1544
1545 // Issue the call.
1546 unsigned DestAddress;
1547 if (Symbol)
1548 DestAddress = materializeExternalCallSym(Sym: Symbol);
1549 else
1550 DestAddress = materializeGV(GV: Addr.getGlobalValue(), VT: MVT::i32);
1551 emitInst(Opc: TargetOpcode::COPY, DstReg: Mips::T9).addReg(RegNo: DestAddress);
1552 MachineInstrBuilder MIB =
1553 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Mips::JALR),
1554 DestReg: Mips::RA).addReg(RegNo: Mips::T9);
1555
1556 // Add implicit physical register uses to the call.
1557 for (auto Reg : CLI.OutRegs)
1558 MIB.addReg(RegNo: Reg, flags: RegState::Implicit);
1559
1560 // Add a register mask with the call-preserved registers.
1561 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1562 MIB.addRegMask(Mask: TRI.getCallPreservedMask(MF: *FuncInfo.MF, CC));
1563
1564 CLI.Call = MIB;
1565
1566 if (EmitJalrReloc && !Subtarget->inMips16Mode()) {
1567 // Attach callee address to the instruction, let asm printer emit
1568 // .reloc R_MIPS_JALR.
1569 if (Symbol)
1570 MIB.addSym(Sym: Symbol, TargetFlags: MipsII::MO_JALR);
1571 else
1572 MIB.addSym(Sym: FuncInfo.MF->getContext().getOrCreateSymbol(
1573 Name: Addr.getGlobalValue()->getName()), TargetFlags: MipsII::MO_JALR);
1574 }
1575
1576 // Finish off the call including any return values.
1577 return finishCall(CLI, RetVT, NumBytes);
1578}
1579
1580bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1581 switch (II->getIntrinsicID()) {
1582 default:
1583 return false;
1584 case Intrinsic::bswap: {
1585 Type *RetTy = II->getCalledFunction()->getReturnType();
1586
1587 MVT VT;
1588 if (!isTypeSupported(Ty: RetTy, VT))
1589 return false;
1590
1591 Register SrcReg = getRegForValue(V: II->getOperand(i_nocapture: 0));
1592 if (SrcReg == 0)
1593 return false;
1594 Register DestReg = createResultReg(RC: &Mips::GPR32RegClass);
1595 if (DestReg == 0)
1596 return false;
1597 if (VT == MVT::i16) {
1598 if (Subtarget->hasMips32r2()) {
1599 emitInst(Opc: Mips::WSBH, DstReg: DestReg).addReg(RegNo: SrcReg);
1600 updateValueMap(I: II, Reg: DestReg);
1601 return true;
1602 } else {
1603 unsigned TempReg[3];
1604 for (unsigned &R : TempReg) {
1605 R = createResultReg(RC: &Mips::GPR32RegClass);
1606 if (R == 0)
1607 return false;
1608 }
1609 emitInst(Opc: Mips::SLL, DstReg: TempReg[0]).addReg(RegNo: SrcReg).addImm(Val: 8);
1610 emitInst(Opc: Mips::SRL, DstReg: TempReg[1]).addReg(RegNo: SrcReg).addImm(Val: 8);
1611 emitInst(Opc: Mips::ANDi, DstReg: TempReg[2]).addReg(RegNo: TempReg[1]).addImm(Val: 0xFF);
1612 emitInst(Opc: Mips::OR, DstReg: DestReg).addReg(RegNo: TempReg[0]).addReg(RegNo: TempReg[2]);
1613 updateValueMap(I: II, Reg: DestReg);
1614 return true;
1615 }
1616 } else if (VT == MVT::i32) {
1617 if (Subtarget->hasMips32r2()) {
1618 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
1619 emitInst(Opc: Mips::WSBH, DstReg: TempReg).addReg(RegNo: SrcReg);
1620 emitInst(Opc: Mips::ROTR, DstReg: DestReg).addReg(RegNo: TempReg).addImm(Val: 16);
1621 updateValueMap(I: II, Reg: DestReg);
1622 return true;
1623 } else {
1624 unsigned TempReg[8];
1625 for (unsigned &R : TempReg) {
1626 R = createResultReg(RC: &Mips::GPR32RegClass);
1627 if (R == 0)
1628 return false;
1629 }
1630
1631 emitInst(Opc: Mips::SRL, DstReg: TempReg[0]).addReg(RegNo: SrcReg).addImm(Val: 8);
1632 emitInst(Opc: Mips::SRL, DstReg: TempReg[1]).addReg(RegNo: SrcReg).addImm(Val: 24);
1633 emitInst(Opc: Mips::ANDi, DstReg: TempReg[2]).addReg(RegNo: TempReg[0]).addImm(Val: 0xFF00);
1634 emitInst(Opc: Mips::OR, DstReg: TempReg[3]).addReg(RegNo: TempReg[1]).addReg(RegNo: TempReg[2]);
1635
1636 emitInst(Opc: Mips::ANDi, DstReg: TempReg[4]).addReg(RegNo: SrcReg).addImm(Val: 0xFF00);
1637 emitInst(Opc: Mips::SLL, DstReg: TempReg[5]).addReg(RegNo: TempReg[4]).addImm(Val: 8);
1638
1639 emitInst(Opc: Mips::SLL, DstReg: TempReg[6]).addReg(RegNo: SrcReg).addImm(Val: 24);
1640 emitInst(Opc: Mips::OR, DstReg: TempReg[7]).addReg(RegNo: TempReg[3]).addReg(RegNo: TempReg[5]);
1641 emitInst(Opc: Mips::OR, DstReg: DestReg).addReg(RegNo: TempReg[6]).addReg(RegNo: TempReg[7]);
1642 updateValueMap(I: II, Reg: DestReg);
1643 return true;
1644 }
1645 }
1646 return false;
1647 }
1648 case Intrinsic::memcpy:
1649 case Intrinsic::memmove: {
1650 const auto *MTI = cast<MemTransferInst>(Val: II);
1651 // Don't handle volatile.
1652 if (MTI->isVolatile())
1653 return false;
1654 if (!MTI->getLength()->getType()->isIntegerTy(Bitwidth: 32))
1655 return false;
1656 const char *IntrMemName = isa<MemCpyInst>(Val: II) ? "memcpy" : "memmove";
1657 return lowerCallTo(CI: II, SymName: IntrMemName, NumArgs: II->arg_size() - 1);
1658 }
1659 case Intrinsic::memset: {
1660 const MemSetInst *MSI = cast<MemSetInst>(Val: II);
1661 // Don't handle volatile.
1662 if (MSI->isVolatile())
1663 return false;
1664 if (!MSI->getLength()->getType()->isIntegerTy(Bitwidth: 32))
1665 return false;
1666 return lowerCallTo(CI: II, SymName: "memset", NumArgs: II->arg_size() - 1);
1667 }
1668 }
1669 return false;
1670}
1671
1672bool MipsFastISel::selectRet(const Instruction *I) {
1673 const Function &F = *I->getParent()->getParent();
1674 const ReturnInst *Ret = cast<ReturnInst>(Val: I);
1675
1676 LLVM_DEBUG(dbgs() << "selectRet\n");
1677
1678 if (!FuncInfo.CanLowerReturn)
1679 return false;
1680
1681 // Build a list of return value registers.
1682 SmallVector<unsigned, 4> RetRegs;
1683
1684 if (Ret->getNumOperands() > 0) {
1685 CallingConv::ID CC = F.getCallingConv();
1686
1687 // Do not handle FastCC.
1688 if (CC == CallingConv::Fast)
1689 return false;
1690
1691 SmallVector<ISD::OutputArg, 4> Outs;
1692 GetReturnInfo(CC, ReturnType: F.getReturnType(), attr: F.getAttributes(), Outs, TLI, DL);
1693
1694 // Analyze operands of the call, assigning locations to each operand.
1695 SmallVector<CCValAssign, 16> ValLocs;
1696 MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1697 I->getContext());
1698 CCAssignFn *RetCC = RetCC_Mips;
1699 CCInfo.AnalyzeReturn(Outs, Fn: RetCC);
1700
1701 // Only handle a single return value for now.
1702 if (ValLocs.size() != 1)
1703 return false;
1704
1705 CCValAssign &VA = ValLocs[0];
1706 const Value *RV = Ret->getOperand(i_nocapture: 0);
1707
1708 // Don't bother handling odd stuff for now.
1709 if ((VA.getLocInfo() != CCValAssign::Full) &&
1710 (VA.getLocInfo() != CCValAssign::BCvt))
1711 return false;
1712
1713 // Only handle register returns for now.
1714 if (!VA.isRegLoc())
1715 return false;
1716
1717 Register Reg = getRegForValue(V: RV);
1718 if (Reg == 0)
1719 return false;
1720
1721 unsigned SrcReg = Reg + VA.getValNo();
1722 Register DestReg = VA.getLocReg();
1723 // Avoid a cross-class copy. This is very unlikely.
1724 if (!MRI.getRegClass(Reg: SrcReg)->contains(Reg: DestReg))
1725 return false;
1726
1727 EVT RVEVT = TLI.getValueType(DL, Ty: RV->getType());
1728 if (!RVEVT.isSimple())
1729 return false;
1730
1731 if (RVEVT.isVector())
1732 return false;
1733
1734 MVT RVVT = RVEVT.getSimpleVT();
1735 if (RVVT == MVT::f128)
1736 return false;
1737
1738 // Do not handle FGR64 returns for now.
1739 if (RVVT == MVT::f64 && UnsupportedFPMode) {
1740 LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1741 return false;
1742 }
1743
1744 MVT DestVT = VA.getValVT();
1745 // Special handling for extended integers.
1746 if (RVVT != DestVT) {
1747 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1748 return false;
1749
1750 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1751 bool IsZExt = Outs[0].Flags.isZExt();
1752 SrcReg = emitIntExt(SrcVT: RVVT, SrcReg, DestVT, isZExt: IsZExt);
1753 if (SrcReg == 0)
1754 return false;
1755 }
1756 }
1757
1758 // Make the copy.
1759 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1760 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg).addReg(RegNo: SrcReg);
1761
1762 // Add register to return instruction.
1763 RetRegs.push_back(Elt: VA.getLocReg());
1764 }
1765 MachineInstrBuilder MIB = emitInst(Opc: Mips::RetRA);
1766 for (unsigned Reg : RetRegs)
1767 MIB.addReg(RegNo: Reg, flags: RegState::Implicit);
1768 return true;
1769}
1770
1771bool MipsFastISel::selectTrunc(const Instruction *I) {
1772 // The high bits for a type smaller than the register size are assumed to be
1773 // undefined.
1774 Value *Op = I->getOperand(i: 0);
1775
1776 EVT SrcVT, DestVT;
1777 SrcVT = TLI.getValueType(DL, Ty: Op->getType(), AllowUnknown: true);
1778 DestVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
1779
1780 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1781 return false;
1782 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1783 return false;
1784
1785 Register SrcReg = getRegForValue(V: Op);
1786 if (!SrcReg)
1787 return false;
1788
1789 // Because the high bits are undefined, a truncate doesn't generate
1790 // any code.
1791 updateValueMap(I, Reg: SrcReg);
1792 return true;
1793}
1794
1795bool MipsFastISel::selectIntExt(const Instruction *I) {
1796 Type *DestTy = I->getType();
1797 Value *Src = I->getOperand(i: 0);
1798 Type *SrcTy = Src->getType();
1799
1800 bool isZExt = isa<ZExtInst>(Val: I);
1801 Register SrcReg = getRegForValue(V: Src);
1802 if (!SrcReg)
1803 return false;
1804
1805 EVT SrcEVT, DestEVT;
1806 SrcEVT = TLI.getValueType(DL, Ty: SrcTy, AllowUnknown: true);
1807 DestEVT = TLI.getValueType(DL, Ty: DestTy, AllowUnknown: true);
1808 if (!SrcEVT.isSimple())
1809 return false;
1810 if (!DestEVT.isSimple())
1811 return false;
1812
1813 MVT SrcVT = SrcEVT.getSimpleVT();
1814 MVT DestVT = DestEVT.getSimpleVT();
1815 Register ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
1816
1817 if (!emitIntExt(SrcVT, SrcReg, DestVT, DestReg: ResultReg, IsZExt: isZExt))
1818 return false;
1819 updateValueMap(I, Reg: ResultReg);
1820 return true;
1821}
1822
1823bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1824 unsigned DestReg) {
1825 unsigned ShiftAmt;
1826 switch (SrcVT.SimpleTy) {
1827 default:
1828 return false;
1829 case MVT::i8:
1830 ShiftAmt = 24;
1831 break;
1832 case MVT::i16:
1833 ShiftAmt = 16;
1834 break;
1835 }
1836 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
1837 emitInst(Opc: Mips::SLL, DstReg: TempReg).addReg(RegNo: SrcReg).addImm(Val: ShiftAmt);
1838 emitInst(Opc: Mips::SRA, DstReg: DestReg).addReg(RegNo: TempReg).addImm(Val: ShiftAmt);
1839 return true;
1840}
1841
1842bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1843 unsigned DestReg) {
1844 switch (SrcVT.SimpleTy) {
1845 default:
1846 return false;
1847 case MVT::i8:
1848 emitInst(Opc: Mips::SEB, DstReg: DestReg).addReg(RegNo: SrcReg);
1849 break;
1850 case MVT::i16:
1851 emitInst(Opc: Mips::SEH, DstReg: DestReg).addReg(RegNo: SrcReg);
1852 break;
1853 }
1854 return true;
1855}
1856
1857bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1858 unsigned DestReg) {
1859 if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1860 return false;
1861 if (Subtarget->hasMips32r2())
1862 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1863 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1864}
1865
1866bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1867 unsigned DestReg) {
1868 int64_t Imm;
1869
1870 switch (SrcVT.SimpleTy) {
1871 default:
1872 return false;
1873 case MVT::i1:
1874 Imm = 1;
1875 break;
1876 case MVT::i8:
1877 Imm = 0xff;
1878 break;
1879 case MVT::i16:
1880 Imm = 0xffff;
1881 break;
1882 }
1883
1884 emitInst(Opc: Mips::ANDi, DstReg: DestReg).addReg(RegNo: SrcReg).addImm(Val: Imm);
1885 return true;
1886}
1887
1888bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1889 unsigned DestReg, bool IsZExt) {
1890 // FastISel does not have plumbing to deal with extensions where the SrcVT or
1891 // DestVT are odd things, so test to make sure that they are both types we can
1892 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1893 // bail out to SelectionDAG.
1894 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1895 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1896 return false;
1897 if (IsZExt)
1898 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1899 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1900}
1901
1902unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1903 bool isZExt) {
1904 unsigned DestReg = createResultReg(RC: &Mips::GPR32RegClass);
1905 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, IsZExt: isZExt);
1906 return Success ? DestReg : 0;
1907}
1908
1909bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1910 EVT DestEVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
1911 if (!DestEVT.isSimple())
1912 return false;
1913
1914 MVT DestVT = DestEVT.getSimpleVT();
1915 if (DestVT != MVT::i32)
1916 return false;
1917
1918 unsigned DivOpc;
1919 switch (ISDOpcode) {
1920 default:
1921 return false;
1922 case ISD::SDIV:
1923 case ISD::SREM:
1924 DivOpc = Mips::SDIV;
1925 break;
1926 case ISD::UDIV:
1927 case ISD::UREM:
1928 DivOpc = Mips::UDIV;
1929 break;
1930 }
1931
1932 Register Src0Reg = getRegForValue(V: I->getOperand(i: 0));
1933 Register Src1Reg = getRegForValue(V: I->getOperand(i: 1));
1934 if (!Src0Reg || !Src1Reg)
1935 return false;
1936
1937 emitInst(Opc: DivOpc).addReg(RegNo: Src0Reg).addReg(RegNo: Src1Reg);
1938 emitInst(Opc: Mips::TEQ).addReg(RegNo: Src1Reg).addReg(RegNo: Mips::ZERO).addImm(Val: 7);
1939
1940 Register ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
1941 if (!ResultReg)
1942 return false;
1943
1944 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1945 ? Mips::MFHI
1946 : Mips::MFLO;
1947 emitInst(Opc: MFOpc, DstReg: ResultReg);
1948
1949 updateValueMap(I, Reg: ResultReg);
1950 return true;
1951}
1952
1953bool MipsFastISel::selectShift(const Instruction *I) {
1954 MVT RetVT;
1955
1956 if (!isTypeSupported(Ty: I->getType(), VT&: RetVT))
1957 return false;
1958
1959 Register ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
1960 if (!ResultReg)
1961 return false;
1962
1963 unsigned Opcode = I->getOpcode();
1964 const Value *Op0 = I->getOperand(i: 0);
1965 Register Op0Reg = getRegForValue(V: Op0);
1966 if (!Op0Reg)
1967 return false;
1968
1969 // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1970 if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1971 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
1972 if (!TempReg)
1973 return false;
1974
1975 MVT Op0MVT = TLI.getValueType(DL, Ty: Op0->getType(), AllowUnknown: true).getSimpleVT();
1976 bool IsZExt = Opcode == Instruction::LShr;
1977 if (!emitIntExt(SrcVT: Op0MVT, SrcReg: Op0Reg, DestVT: MVT::i32, DestReg: TempReg, IsZExt))
1978 return false;
1979
1980 Op0Reg = TempReg;
1981 }
1982
1983 if (const auto *C = dyn_cast<ConstantInt>(Val: I->getOperand(i: 1))) {
1984 uint64_t ShiftVal = C->getZExtValue();
1985
1986 switch (Opcode) {
1987 default:
1988 llvm_unreachable("Unexpected instruction.");
1989 case Instruction::Shl:
1990 Opcode = Mips::SLL;
1991 break;
1992 case Instruction::AShr:
1993 Opcode = Mips::SRA;
1994 break;
1995 case Instruction::LShr:
1996 Opcode = Mips::SRL;
1997 break;
1998 }
1999
2000 emitInst(Opc: Opcode, DstReg: ResultReg).addReg(RegNo: Op0Reg).addImm(Val: ShiftVal);
2001 updateValueMap(I, Reg: ResultReg);
2002 return true;
2003 }
2004
2005 Register Op1Reg = getRegForValue(V: I->getOperand(i: 1));
2006 if (!Op1Reg)
2007 return false;
2008
2009 switch (Opcode) {
2010 default:
2011 llvm_unreachable("Unexpected instruction.");
2012 case Instruction::Shl:
2013 Opcode = Mips::SLLV;
2014 break;
2015 case Instruction::AShr:
2016 Opcode = Mips::SRAV;
2017 break;
2018 case Instruction::LShr:
2019 Opcode = Mips::SRLV;
2020 break;
2021 }
2022
2023 emitInst(Opc: Opcode, DstReg: ResultReg).addReg(RegNo: Op0Reg).addReg(RegNo: Op1Reg);
2024 updateValueMap(I, Reg: ResultReg);
2025 return true;
2026}
2027
2028bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
2029 switch (I->getOpcode()) {
2030 default:
2031 break;
2032 case Instruction::Load:
2033 return selectLoad(I);
2034 case Instruction::Store:
2035 return selectStore(I);
2036 case Instruction::SDiv:
2037 if (!selectBinaryOp(I, ISDOpcode: ISD::SDIV))
2038 return selectDivRem(I, ISDOpcode: ISD::SDIV);
2039 return true;
2040 case Instruction::UDiv:
2041 if (!selectBinaryOp(I, ISDOpcode: ISD::UDIV))
2042 return selectDivRem(I, ISDOpcode: ISD::UDIV);
2043 return true;
2044 case Instruction::SRem:
2045 if (!selectBinaryOp(I, ISDOpcode: ISD::SREM))
2046 return selectDivRem(I, ISDOpcode: ISD::SREM);
2047 return true;
2048 case Instruction::URem:
2049 if (!selectBinaryOp(I, ISDOpcode: ISD::UREM))
2050 return selectDivRem(I, ISDOpcode: ISD::UREM);
2051 return true;
2052 case Instruction::Shl:
2053 case Instruction::LShr:
2054 case Instruction::AShr:
2055 return selectShift(I);
2056 case Instruction::And:
2057 case Instruction::Or:
2058 case Instruction::Xor:
2059 return selectLogicalOp(I);
2060 case Instruction::Br:
2061 return selectBranch(I);
2062 case Instruction::Ret:
2063 return selectRet(I);
2064 case Instruction::Trunc:
2065 return selectTrunc(I);
2066 case Instruction::ZExt:
2067 case Instruction::SExt:
2068 return selectIntExt(I);
2069 case Instruction::FPTrunc:
2070 return selectFPTrunc(I);
2071 case Instruction::FPExt:
2072 return selectFPExt(I);
2073 case Instruction::FPToSI:
2074 return selectFPToInt(I, /*isSigned*/ IsSigned: true);
2075 case Instruction::FPToUI:
2076 return selectFPToInt(I, /*isSigned*/ IsSigned: false);
2077 case Instruction::ICmp:
2078 case Instruction::FCmp:
2079 return selectCmp(I);
2080 case Instruction::Select:
2081 return selectSelect(I);
2082 }
2083 return false;
2084}
2085
2086unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2087 bool IsUnsigned) {
2088 Register VReg = getRegForValue(V);
2089 if (VReg == 0)
2090 return 0;
2091 MVT VMVT = TLI.getValueType(DL, Ty: V->getType(), AllowUnknown: true).getSimpleVT();
2092
2093 if (VMVT == MVT::i1)
2094 return 0;
2095
2096 if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2097 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
2098 if (!emitIntExt(SrcVT: VMVT, SrcReg: VReg, DestVT: MVT::i32, DestReg: TempReg, IsZExt: IsUnsigned))
2099 return 0;
2100 VReg = TempReg;
2101 }
2102 return VReg;
2103}
2104
2105void MipsFastISel::simplifyAddress(Address &Addr) {
2106 if (!isInt<16>(x: Addr.getOffset())) {
2107 unsigned TempReg =
2108 materialize32BitInt(Imm: Addr.getOffset(), RC: &Mips::GPR32RegClass);
2109 Register DestReg = createResultReg(RC: &Mips::GPR32RegClass);
2110 emitInst(Opc: Mips::ADDu, DstReg: DestReg).addReg(RegNo: TempReg).addReg(RegNo: Addr.getReg());
2111 Addr.setReg(DestReg);
2112 Addr.setOffset(0);
2113 }
2114}
2115
2116unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2117 const TargetRegisterClass *RC,
2118 unsigned Op0, unsigned Op1) {
2119 // We treat the MUL instruction in a special way because it clobbers
2120 // the HI0 & LO0 registers. The TableGen definition of this instruction can
2121 // mark these registers only as implicitly defined. As a result, the
2122 // register allocator runs out of registers when this instruction is
2123 // followed by another instruction that defines the same registers too.
2124 // We can fix this by explicitly marking those registers as dead.
2125 if (MachineInstOpcode == Mips::MUL) {
2126 Register ResultReg = createResultReg(RC);
2127 const MCInstrDesc &II = TII.get(Opcode: MachineInstOpcode);
2128 Op0 = constrainOperandRegClass(II, Op: Op0, OpNum: II.getNumDefs());
2129 Op1 = constrainOperandRegClass(II, Op: Op1, OpNum: II.getNumDefs() + 1);
2130 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II, DestReg: ResultReg)
2131 .addReg(RegNo: Op0)
2132 .addReg(RegNo: Op1)
2133 .addReg(RegNo: Mips::HI0, flags: RegState::ImplicitDefine | RegState::Dead)
2134 .addReg(RegNo: Mips::LO0, flags: RegState::ImplicitDefine | RegState::Dead);
2135 return ResultReg;
2136 }
2137
2138 return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op1);
2139}
2140
2141namespace llvm {
2142
2143FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
2144 const TargetLibraryInfo *libInfo) {
2145 return new MipsFastISel(funcInfo, libInfo);
2146}
2147
2148} // end namespace llvm
2149