1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_immZExt5(int64_t Imm) {
12return Imm == (Imm & 0x1f);
13}
14static bool Predicate_immZExt6(int64_t Imm) {
15return Imm == (Imm & 0x3f);
16}
17static bool Predicate_immSExt6(int64_t Imm) {
18return isInt<6>(x: Imm);
19}
20static bool Predicate_immZExt4Ptr(int64_t Imm) {
21return isUInt<4>(x: Imm);
22}
23static bool Predicate_immZExt3Ptr(int64_t Imm) {
24return isUInt<3>(x: Imm);
25}
26static bool Predicate_immZExt2Ptr(int64_t Imm) {
27return isUInt<2>(x: Imm);
28}
29static bool Predicate_immZExt1Ptr(int64_t Imm) {
30return isUInt<1>(x: Imm);
31}
32static bool Predicate_immZExt4(int64_t Imm) {
33return isUInt<4>(x: Imm);
34}
35static bool Predicate_immSExtAddiur2(int64_t Imm) {
36return Imm == 1 || Imm == -1 ||
37 ((Imm % 4 == 0) &&
38 Imm < 28 && Imm > 0);
39}
40static bool Predicate_immSExtAddius5(int64_t Imm) {
41return Imm >= -8 && Imm <= 7;
42}
43static bool Predicate_immZExtAndi16(int64_t Imm) {
44return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
45 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
46 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
47}
48static bool Predicate_immZExt2Shift(int64_t Imm) {
49return Imm >= 1 && Imm <= 8;
50}
51
52
53// FastEmit functions for ISD::BITCAST.
54
55unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0) {
56 if (RetVT.SimpleTy != MVT::f32)
57 return 0;
58 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
59 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MMR6, RC: &Mips::FGR32RegClass, Op0);
60 }
61 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
62 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MM, RC: &Mips::FGR32RegClass, Op0);
63 }
64 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
65 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1, RC: &Mips::FGR32RegClass, Op0);
66 }
67 return 0;
68}
69
70unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0) {
71 if (RetVT.SimpleTy != MVT::f64)
72 return 0;
73 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
74 return fastEmitInst_r(MachineInstOpcode: Mips::DMTC1, RC: &Mips::FGR64RegClass, Op0);
75 }
76 return 0;
77}
78
79unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0) {
80 if (RetVT.SimpleTy != MVT::i32)
81 return 0;
82 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
83 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MMR6, RC: &Mips::GPR32RegClass, Op0);
84 }
85 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
86 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MM, RC: &Mips::GPR32RegClass, Op0);
87 }
88 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
89 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1, RC: &Mips::GPR32RegClass, Op0);
90 }
91 return 0;
92}
93
94unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0) {
95 if (RetVT.SimpleTy != MVT::i64)
96 return 0;
97 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
98 return fastEmitInst_r(MachineInstOpcode: Mips::DMFC1, RC: &Mips::GPR64RegClass, Op0);
99 }
100 return 0;
101}
102
103unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0) {
104 switch (VT.SimpleTy) {
105 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
106 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
107 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
108 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
109 default: return 0;
110 }
111}
112
113// FastEmit functions for ISD::BRIND.
114
115unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0) {
116 if (RetVT.SimpleTy != MVT::isVoid)
117 return 0;
118 if ((Subtarget->inMips16Mode())) {
119 return fastEmitInst_r(MachineInstOpcode: Mips::JrcRx16, RC: &Mips::CPU16RegsRegClass, Op0);
120 }
121 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
122 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch_MMR6, RC: &Mips::GPR32RegClass, Op0);
123 }
124 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
125 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch_MM, RC: &Mips::GPR32RegClass, Op0);
126 }
127 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
128 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndrectHazardBranchR6, RC: &Mips::GPR32RegClass, Op0);
129 }
130 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
131 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranchR6, RC: &Mips::GPR32RegClass, Op0);
132 }
133 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
134 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectHazardBranch, RC: &Mips::GPR32RegClass, Op0);
135 }
136 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
137 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch, RC: &Mips::GPR32RegClass, Op0);
138 }
139 return 0;
140}
141
142unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0) {
143 if (RetVT.SimpleTy != MVT::isVoid)
144 return 0;
145 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
146 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndrectHazardBranch64R6, RC: &Mips::GPR64RegClass, Op0);
147 }
148 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
149 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch64R6, RC: &Mips::GPR64RegClass, Op0);
150 }
151 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
152 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectHazardBranch64, RC: &Mips::GPR64RegClass, Op0);
153 }
154 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
155 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch64, RC: &Mips::GPR64RegClass, Op0);
156 }
157 return 0;
158}
159
160unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0) {
161 switch (VT.SimpleTy) {
162 case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0);
163 case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0);
164 default: return 0;
165 }
166}
167
168// FastEmit functions for ISD::CTLZ.
169
170unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0) {
171 if (RetVT.SimpleTy != MVT::i32)
172 return 0;
173 if ((Subtarget->inMicroMipsMode())) {
174 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_MM, RC: &Mips::GPR32RegClass, Op0);
175 }
176 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
177 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_R6, RC: &Mips::GPR32RegClass, Op0);
178 }
179 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
180 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ, RC: &Mips::GPR32RegClass, Op0);
181 }
182 return 0;
183}
184
185unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0) {
186 if (RetVT.SimpleTy != MVT::i64)
187 return 0;
188 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
189 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ_R6, RC: &Mips::GPR64RegClass, Op0);
190 }
191 if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
192 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ, RC: &Mips::GPR64RegClass, Op0);
193 }
194 return 0;
195}
196
197unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
198 if (RetVT.SimpleTy != MVT::v16i8)
199 return 0;
200 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
201 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_B, RC: &Mips::MSA128BRegClass, Op0);
202 }
203 return 0;
204}
205
206unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
207 if (RetVT.SimpleTy != MVT::v8i16)
208 return 0;
209 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
210 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_H, RC: &Mips::MSA128HRegClass, Op0);
211 }
212 return 0;
213}
214
215unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
216 if (RetVT.SimpleTy != MVT::v4i32)
217 return 0;
218 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
219 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_W, RC: &Mips::MSA128WRegClass, Op0);
220 }
221 return 0;
222}
223
224unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
225 if (RetVT.SimpleTy != MVT::v2i64)
226 return 0;
227 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
228 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_D, RC: &Mips::MSA128DRegClass, Op0);
229 }
230 return 0;
231}
232
233unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0) {
234 switch (VT.SimpleTy) {
235 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
236 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
237 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0);
238 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0);
239 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0);
240 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0);
241 default: return 0;
242 }
243}
244
245// FastEmit functions for ISD::CTPOP.
246
247unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0) {
248 if (RetVT.SimpleTy != MVT::i32)
249 return 0;
250 if ((Subtarget->hasCnMips())) {
251 return fastEmitInst_r(MachineInstOpcode: Mips::POP, RC: &Mips::GPR32RegClass, Op0);
252 }
253 return 0;
254}
255
256unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0) {
257 if (RetVT.SimpleTy != MVT::i64)
258 return 0;
259 if ((Subtarget->hasCnMips())) {
260 return fastEmitInst_r(MachineInstOpcode: Mips::DPOP, RC: &Mips::GPR64RegClass, Op0);
261 }
262 return 0;
263}
264
265unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
266 if (RetVT.SimpleTy != MVT::v16i8)
267 return 0;
268 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
269 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_B, RC: &Mips::MSA128BRegClass, Op0);
270 }
271 return 0;
272}
273
274unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
275 if (RetVT.SimpleTy != MVT::v8i16)
276 return 0;
277 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
278 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_H, RC: &Mips::MSA128HRegClass, Op0);
279 }
280 return 0;
281}
282
283unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
284 if (RetVT.SimpleTy != MVT::v4i32)
285 return 0;
286 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
287 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_W, RC: &Mips::MSA128WRegClass, Op0);
288 }
289 return 0;
290}
291
292unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
293 if (RetVT.SimpleTy != MVT::v2i64)
294 return 0;
295 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
296 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_D, RC: &Mips::MSA128DRegClass, Op0);
297 }
298 return 0;
299}
300
301unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0) {
302 switch (VT.SimpleTy) {
303 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
304 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
305 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
306 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0);
307 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0);
308 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0);
309 default: return 0;
310 }
311}
312
313// FastEmit functions for ISD::FABS.
314
315unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0) {
316 if (RetVT.SimpleTy != MVT::f32)
317 return 0;
318 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) {
319 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_S_MM, RC: &Mips::FGR32RegClass, Op0);
320 }
321 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) {
322 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_S, RC: &Mips::FGR32RegClass, Op0);
323 }
324 return 0;
325}
326
327unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0) {
328 if (RetVT.SimpleTy != MVT::f64)
329 return 0;
330 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
331 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64_MM, RC: &Mips::FGR64RegClass, Op0);
332 }
333 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
334 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
335 }
336 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) {
337 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64, RC: &Mips::FGR64RegClass, Op0);
338 }
339 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) {
340 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32, RC: &Mips::AFGR64RegClass, Op0);
341 }
342 return 0;
343}
344
345unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
346 if (RetVT.SimpleTy != MVT::v4f32)
347 return 0;
348 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
349 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_W, RC: &Mips::MSA128WRegClass, Op0);
350 }
351 return 0;
352}
353
354unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
355 if (RetVT.SimpleTy != MVT::v2f64)
356 return 0;
357 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
358 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D, RC: &Mips::MSA128DRegClass, Op0);
359 }
360 return 0;
361}
362
363unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0) {
364 switch (VT.SimpleTy) {
365 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
366 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
367 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
368 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
369 default: return 0;
370 }
371}
372
373// FastEmit functions for ISD::FEXP2.
374
375unsigned fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
376 if (RetVT.SimpleTy != MVT::v4f32)
377 return 0;
378 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
379 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_W_1_PSEUDO, RC: &Mips::MSA128WRegClass, Op0);
380 }
381 return 0;
382}
383
384unsigned fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
385 if (RetVT.SimpleTy != MVT::v2f64)
386 return 0;
387 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
388 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_D_1_PSEUDO, RC: &Mips::MSA128DRegClass, Op0);
389 }
390 return 0;
391}
392
393unsigned fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, unsigned Op0) {
394 switch (VT.SimpleTy) {
395 case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0);
396 case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0);
397 default: return 0;
398 }
399}
400
401// FastEmit functions for ISD::FLOG2.
402
403unsigned fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
404 if (RetVT.SimpleTy != MVT::v4f32)
405 return 0;
406 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
407 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_W, RC: &Mips::MSA128WRegClass, Op0);
408 }
409 return 0;
410}
411
412unsigned fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
413 if (RetVT.SimpleTy != MVT::v2f64)
414 return 0;
415 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
416 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_D, RC: &Mips::MSA128DRegClass, Op0);
417 }
418 return 0;
419}
420
421unsigned fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, unsigned Op0) {
422 switch (VT.SimpleTy) {
423 case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0);
424 case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0);
425 default: return 0;
426 }
427}
428
429// FastEmit functions for ISD::FNEG.
430
431unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0) {
432 if (RetVT.SimpleTy != MVT::f32)
433 return 0;
434 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
435 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
436 }
437 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
438 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MM, RC: &Mips::FGR32RegClass, Op0);
439 }
440 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
441 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S, RC: &Mips::FGR32RegClass, Op0);
442 }
443 return 0;
444}
445
446unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0) {
447 if (RetVT.SimpleTy != MVT::f64)
448 return 0;
449 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
450 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64_MM, RC: &Mips::FGR64RegClass, Op0);
451 }
452 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
453 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
454 }
455 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
456 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64, RC: &Mips::FGR64RegClass, Op0);
457 }
458 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
459 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32, RC: &Mips::AFGR64RegClass, Op0);
460 }
461 return 0;
462}
463
464unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0) {
465 switch (VT.SimpleTy) {
466 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
467 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
468 default: return 0;
469 }
470}
471
472// FastEmit functions for ISD::FP_EXTEND.
473
474unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0) {
475 if ((Subtarget->hasMSA())) {
476 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_EXTEND_W_PSEUDO, RC: &Mips::FGR32RegClass, Op0);
477 }
478 return 0;
479}
480
481unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0) {
482 if ((Subtarget->hasMSA())) {
483 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_EXTEND_D_PSEUDO, RC: &Mips::FGR64RegClass, Op0);
484 }
485 return 0;
486}
487
488unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0) {
489switch (RetVT.SimpleTy) {
490 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0);
491 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0);
492 default: return 0;
493}
494}
495
496unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) {
497 if (RetVT.SimpleTy != MVT::f64)
498 return 0;
499 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
500 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S_MM, RC: &Mips::AFGR64RegClass, Op0);
501 }
502 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
503 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S_MM, RC: &Mips::FGR64RegClass, Op0);
504 }
505 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
506 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
507 }
508 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
509 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
510 }
511 return 0;
512}
513
514unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
515 switch (VT.SimpleTy) {
516 case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0);
517 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
518 default: return 0;
519 }
520}
521
522// FastEmit functions for ISD::FP_ROUND.
523
524unsigned fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0) {
525 if (RetVT.SimpleTy != MVT::f16)
526 return 0;
527 if ((Subtarget->hasMSA())) {
528 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_ROUND_W_PSEUDO, RC: &Mips::MSA128F16RegClass, Op0);
529 }
530 return 0;
531}
532
533unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0) {
534 if ((Subtarget->hasMSA())) {
535 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_ROUND_D_PSEUDO, RC: &Mips::MSA128F16RegClass, Op0);
536 }
537 return 0;
538}
539
540unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0) {
541 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
542 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32_MM, RC: &Mips::FGR32RegClass, Op0);
543 }
544 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
545 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64_MM, RC: &Mips::FGR32RegClass, Op0);
546 }
547 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
548 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
549 }
550 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
551 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
552 }
553 return 0;
554}
555
556unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) {
557switch (RetVT.SimpleTy) {
558 case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0);
559 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0);
560 default: return 0;
561}
562}
563
564unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) {
565 switch (VT.SimpleTy) {
566 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0);
567 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
568 default: return 0;
569 }
570}
571
572// FastEmit functions for ISD::FP_TO_SINT.
573
574unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
575 if (RetVT.SimpleTy != MVT::v4i32)
576 return 0;
577 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
578 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_W, RC: &Mips::MSA128WRegClass, Op0);
579 }
580 return 0;
581}
582
583unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
584 if (RetVT.SimpleTy != MVT::v2i64)
585 return 0;
586 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
587 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_D, RC: &Mips::MSA128DRegClass, Op0);
588 }
589 return 0;
590}
591
592unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) {
593 switch (VT.SimpleTy) {
594 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
595 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
596 default: return 0;
597 }
598}
599
600// FastEmit functions for ISD::FP_TO_UINT.
601
602unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
603 if (RetVT.SimpleTy != MVT::v4i32)
604 return 0;
605 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
606 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_W, RC: &Mips::MSA128WRegClass, Op0);
607 }
608 return 0;
609}
610
611unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
612 if (RetVT.SimpleTy != MVT::v2i64)
613 return 0;
614 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
615 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_D, RC: &Mips::MSA128DRegClass, Op0);
616 }
617 return 0;
618}
619
620unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) {
621 switch (VT.SimpleTy) {
622 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
623 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
624 default: return 0;
625 }
626}
627
628// FastEmit functions for ISD::FRINT.
629
630unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
631 if (RetVT.SimpleTy != MVT::v4f32)
632 return 0;
633 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
634 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_W, RC: &Mips::MSA128WRegClass, Op0);
635 }
636 return 0;
637}
638
639unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
640 if (RetVT.SimpleTy != MVT::v2f64)
641 return 0;
642 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
643 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_D, RC: &Mips::MSA128DRegClass, Op0);
644 }
645 return 0;
646}
647
648unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0) {
649 switch (VT.SimpleTy) {
650 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
651 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
652 default: return 0;
653 }
654}
655
656// FastEmit functions for ISD::FSQRT.
657
658unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) {
659 if (RetVT.SimpleTy != MVT::f32)
660 return 0;
661 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
662 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S_MM, RC: &Mips::FGR32RegClass, Op0);
663 }
664 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
665 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
666 }
667 return 0;
668}
669
670unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) {
671 if (RetVT.SimpleTy != MVT::f64)
672 return 0;
673 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
674 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64_MM, RC: &Mips::FGR64RegClass, Op0);
675 }
676 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
677 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
678 }
679 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
680 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
681 }
682 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
683 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
684 }
685 return 0;
686}
687
688unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
689 if (RetVT.SimpleTy != MVT::v4f32)
690 return 0;
691 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
692 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_W, RC: &Mips::MSA128WRegClass, Op0);
693 }
694 return 0;
695}
696
697unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
698 if (RetVT.SimpleTy != MVT::v2f64)
699 return 0;
700 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
701 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D, RC: &Mips::MSA128DRegClass, Op0);
702 }
703 return 0;
704}
705
706unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) {
707 switch (VT.SimpleTy) {
708 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
709 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
710 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
711 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
712 default: return 0;
713 }
714}
715
716// FastEmit functions for ISD::SIGN_EXTEND.
717
718unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) {
719 if (RetVT.SimpleTy != MVT::i64)
720 return 0;
721 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
722 return fastEmitInst_r(MachineInstOpcode: Mips::SLL64_32, RC: &Mips::GPR64RegClass, Op0);
723 }
724 return 0;
725}
726
727unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
728 switch (VT.SimpleTy) {
729 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
730 default: return 0;
731 }
732}
733
734// FastEmit functions for ISD::SINT_TO_FP.
735
736unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) {
737 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
738}
739
740unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) {
741 if ((Subtarget->isFP64bit())) {
742 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
743 }
744 if ((!Subtarget->isFP64bit())) {
745 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
746 }
747 return 0;
748}
749
750unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) {
751switch (RetVT.SimpleTy) {
752 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
753 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
754 default: return 0;
755}
756}
757
758unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0) {
759 if (RetVT.SimpleTy != MVT::f64)
760 return 0;
761 if ((Subtarget->isFP64bit())) {
762 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
763 }
764 return 0;
765}
766
767unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
768 if (RetVT.SimpleTy != MVT::v4f32)
769 return 0;
770 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
771 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_W, RC: &Mips::MSA128WRegClass, Op0);
772 }
773 return 0;
774}
775
776unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
777 if (RetVT.SimpleTy != MVT::v2f64)
778 return 0;
779 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
780 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_D, RC: &Mips::MSA128DRegClass, Op0);
781 }
782 return 0;
783}
784
785unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) {
786 switch (VT.SimpleTy) {
787 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
788 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
789 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
790 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
791 default: return 0;
792 }
793}
794
795// FastEmit functions for ISD::UINT_TO_FP.
796
797unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
798 if (RetVT.SimpleTy != MVT::v4f32)
799 return 0;
800 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
801 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_W, RC: &Mips::MSA128WRegClass, Op0);
802 }
803 return 0;
804}
805
806unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
807 if (RetVT.SimpleTy != MVT::v2f64)
808 return 0;
809 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
810 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_D, RC: &Mips::MSA128DRegClass, Op0);
811 }
812 return 0;
813}
814
815unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) {
816 switch (VT.SimpleTy) {
817 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
818 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
819 default: return 0;
820 }
821}
822
823// FastEmit functions for MipsISD::JmpLink.
824
825unsigned fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, unsigned Op0) {
826 if (RetVT.SimpleTy != MVT::isVoid)
827 return 0;
828 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
829 return fastEmitInst_r(MachineInstOpcode: Mips::JALR16_MM, RC: &Mips::GPR32RegClass, Op0);
830 }
831 if ((Subtarget->inMips16Mode())) {
832 return fastEmitInst_r(MachineInstOpcode: Mips::JumpLinkReg16, RC: &Mips::CPU16RegsRegClass, Op0);
833 }
834 if ((!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
835 return fastEmitInst_r(MachineInstOpcode: Mips::JALRHBPseudo, RC: &Mips::GPR32RegClass, Op0);
836 }
837 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())) {
838 return fastEmitInst_r(MachineInstOpcode: Mips::JALRPseudo, RC: &Mips::GPR32RegClass, Op0);
839 }
840 return 0;
841}
842
843unsigned fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, unsigned Op0) {
844 if (RetVT.SimpleTy != MVT::isVoid)
845 return 0;
846 if ((Subtarget->isABI_N64()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
847 return fastEmitInst_r(MachineInstOpcode: Mips::JALRHB64Pseudo, RC: &Mips::GPR64RegClass, Op0);
848 }
849 if ((Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMips16Mode())) {
850 return fastEmitInst_r(MachineInstOpcode: Mips::JALR64Pseudo, RC: &Mips::GPR64RegClass, Op0);
851 }
852 return 0;
853}
854
855unsigned fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, unsigned Op0) {
856 switch (VT.SimpleTy) {
857 case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0);
858 case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0);
859 default: return 0;
860 }
861}
862
863// FastEmit functions for MipsISD::MFHI.
864
865unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(unsigned Op0) {
866 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
867 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
868 }
869 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
870 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI_MM, RC: &Mips::GPR32RegClass, Op0);
871 }
872 if ((Subtarget->hasDSP())) {
873 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP, RC: &Mips::GPR32RegClass, Op0);
874 }
875 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
876 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI, RC: &Mips::GPR32RegClass, Op0);
877 }
878 return 0;
879}
880
881unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(unsigned Op0) {
882 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
883 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI64, RC: &Mips::GPR64RegClass, Op0);
884 }
885 return 0;
886}
887
888unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, unsigned Op0) {
889switch (RetVT.SimpleTy) {
890 case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0);
891 case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0);
892 default: return 0;
893}
894}
895
896unsigned fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, unsigned Op0) {
897 switch (VT.SimpleTy) {
898 case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0);
899 default: return 0;
900 }
901}
902
903// FastEmit functions for MipsISD::MFLO.
904
905unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(unsigned Op0) {
906 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
907 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
908 }
909 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
910 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO_MM, RC: &Mips::GPR32RegClass, Op0);
911 }
912 if ((Subtarget->hasDSP())) {
913 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP, RC: &Mips::GPR32RegClass, Op0);
914 }
915 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
916 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO, RC: &Mips::GPR32RegClass, Op0);
917 }
918 return 0;
919}
920
921unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(unsigned Op0) {
922 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
923 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO64, RC: &Mips::GPR64RegClass, Op0);
924 }
925 return 0;
926}
927
928unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, unsigned Op0) {
929switch (RetVT.SimpleTy) {
930 case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0);
931 case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0);
932 default: return 0;
933}
934}
935
936unsigned fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, unsigned Op0) {
937 switch (VT.SimpleTy) {
938 case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0);
939 default: return 0;
940 }
941}
942
943// FastEmit functions for MipsISD::MTC1_D64.
944
945unsigned fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, unsigned Op0) {
946 if (RetVT.SimpleTy != MVT::f64)
947 return 0;
948 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
949 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64_MM, RC: &Mips::FGR64RegClass, Op0);
950 }
951 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
952 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64, RC: &Mips::FGR64RegClass, Op0);
953 }
954 return 0;
955}
956
957unsigned fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, unsigned Op0) {
958 switch (VT.SimpleTy) {
959 case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0);
960 default: return 0;
961 }
962}
963
964// FastEmit functions for MipsISD::TailCall.
965
966unsigned fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, unsigned Op0) {
967 if (RetVT.SimpleTy != MVT::isVoid)
968 return 0;
969 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
970 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG_MMR6, RC: &Mips::GPR32RegClass, Op0);
971 }
972 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
973 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG_MM, RC: &Mips::GPR32RegClass, Op0);
974 }
975 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
976 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLHBR6REG, RC: &Mips::GPR32RegClass, Op0);
977 }
978 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
979 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLR6REG, RC: &Mips::GPR32RegClass, Op0);
980 }
981 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
982 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREGHB, RC: &Mips::GPR32RegClass, Op0);
983 }
984 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
985 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG, RC: &Mips::GPR32RegClass, Op0);
986 }
987 return 0;
988}
989
990unsigned fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, unsigned Op0) {
991 if (RetVT.SimpleTy != MVT::isVoid)
992 return 0;
993 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
994 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLHB64R6REG, RC: &Mips::GPR64RegClass, Op0);
995 }
996 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
997 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALL64R6REG, RC: &Mips::GPR64RegClass, Op0);
998 }
999 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
1000 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREGHB64, RC: &Mips::GPR64RegClass, Op0);
1001 }
1002 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1003 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG64, RC: &Mips::GPR64RegClass, Op0);
1004 }
1005 return 0;
1006}
1007
1008unsigned fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, unsigned Op0) {
1009 switch (VT.SimpleTy) {
1010 case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0);
1011 case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0);
1012 default: return 0;
1013 }
1014}
1015
1016// FastEmit functions for MipsISD::TruncIntFP.
1017
1018unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(unsigned Op0) {
1019 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1020 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
1021 }
1022 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1023 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MM, RC: &Mips::FGR32RegClass, Op0);
1024 }
1025 if ((Subtarget->hasStandardEncoding())) {
1026 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S, RC: &Mips::FGR32RegClass, Op0);
1027 }
1028 return 0;
1029}
1030
1031unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(unsigned Op0) {
1032 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1033 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_S, RC: &Mips::FGR64RegClass, Op0);
1034 }
1035 return 0;
1036}
1037
1038unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, unsigned Op0) {
1039switch (RetVT.SimpleTy) {
1040 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0);
1041 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0);
1042 default: return 0;
1043}
1044}
1045
1046unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(unsigned Op0) {
1047 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1048 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D_MMR6, RC: &Mips::FGR32RegClass, Op0);
1049 }
1050 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
1051 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_W_D64_MM, RC: &Mips::FGR32RegClass, Op0);
1052 }
1053 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
1054 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_MM, RC: &Mips::FGR32RegClass, Op0);
1055 }
1056 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1057 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D64, RC: &Mips::FGR32RegClass, Op0);
1058 }
1059 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1060 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D32, RC: &Mips::FGR32RegClass, Op0);
1061 }
1062 return 0;
1063}
1064
1065unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(unsigned Op0) {
1066 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1067 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_D64, RC: &Mips::FGR64RegClass, Op0);
1068 }
1069 return 0;
1070}
1071
1072unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, unsigned Op0) {
1073switch (RetVT.SimpleTy) {
1074 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0);
1075 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0);
1076 default: return 0;
1077}
1078}
1079
1080unsigned fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, unsigned Op0) {
1081 switch (VT.SimpleTy) {
1082 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0);
1083 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0);
1084 default: return 0;
1085 }
1086}
1087
1088// FastEmit functions for MipsISD::VALL_NONZERO.
1089
1090unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
1091 if (RetVT.SimpleTy != MVT::i32)
1092 return 0;
1093 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1094}
1095
1096unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
1097 if (RetVT.SimpleTy != MVT::i32)
1098 return 0;
1099 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1100}
1101
1102unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1103 if (RetVT.SimpleTy != MVT::i32)
1104 return 0;
1105 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1106}
1107
1108unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
1109 if (RetVT.SimpleTy != MVT::i32)
1110 return 0;
1111 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1112}
1113
1114unsigned fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0) {
1115 switch (VT.SimpleTy) {
1116 case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0);
1117 case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0);
1118 case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0);
1119 case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0);
1120 default: return 0;
1121 }
1122}
1123
1124// FastEmit functions for MipsISD::VALL_ZERO.
1125
1126unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
1127 if (RetVT.SimpleTy != MVT::i32)
1128 return 0;
1129 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1130}
1131
1132unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
1133 if (RetVT.SimpleTy != MVT::i32)
1134 return 0;
1135 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1136}
1137
1138unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1139 if (RetVT.SimpleTy != MVT::i32)
1140 return 0;
1141 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1142}
1143
1144unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
1145 if (RetVT.SimpleTy != MVT::i32)
1146 return 0;
1147 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1148}
1149
1150unsigned fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, unsigned Op0) {
1151 switch (VT.SimpleTy) {
1152 case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0);
1153 case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0);
1154 case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0);
1155 case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0);
1156 default: return 0;
1157 }
1158}
1159
1160// FastEmit functions for MipsISD::VANY_NONZERO.
1161
1162unsigned fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
1163 if (RetVT.SimpleTy != MVT::i32)
1164 return 0;
1165 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1166}
1167
1168unsigned fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0) {
1169 switch (VT.SimpleTy) {
1170 case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0);
1171 default: return 0;
1172 }
1173}
1174
1175// FastEmit functions for MipsISD::VANY_ZERO.
1176
1177unsigned fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
1178 if (RetVT.SimpleTy != MVT::i32)
1179 return 0;
1180 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1181}
1182
1183unsigned fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, unsigned Op0) {
1184 switch (VT.SimpleTy) {
1185 case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0);
1186 default: return 0;
1187 }
1188}
1189
1190// Top-level FastEmit function.
1191
1192unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0) override {
1193 switch (Opcode) {
1194 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1195 case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0);
1196 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1197 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1198 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1199 case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0);
1200 case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0);
1201 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1202 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1203 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1204 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1205 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1206 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1207 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1208 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1209 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1210 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1211 case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0);
1212 case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0);
1213 case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0);
1214 case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0);
1215 case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0);
1216 case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0);
1217 case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0);
1218 case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0);
1219 case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0);
1220 case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0);
1221 default: return 0;
1222 }
1223}
1224
1225// FastEmit functions for ISD::ADD.
1226
1227unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1228 if (RetVT.SimpleTy != MVT::i32)
1229 return 0;
1230 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1231 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
1232 }
1233 if ((Subtarget->inMips16Mode())) {
1234 return fastEmitInst_rr(MachineInstOpcode: Mips::AdduRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1235 }
1236 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1237 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1238 }
1239 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1240 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1241 }
1242 return 0;
1243}
1244
1245unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1246 if (RetVT.SimpleTy != MVT::i64)
1247 return 0;
1248 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1249 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1250 }
1251 return 0;
1252}
1253
1254unsigned fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1255 if (RetVT.SimpleTy != MVT::v4i8)
1256 return 0;
1257 if ((Subtarget->hasDSP())) {
1258 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
1259 }
1260 return 0;
1261}
1262
1263unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1264 if (RetVT.SimpleTy != MVT::v16i8)
1265 return 0;
1266 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1267 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1268 }
1269 return 0;
1270}
1271
1272unsigned fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1273 if (RetVT.SimpleTy != MVT::v2i16)
1274 return 0;
1275 if ((Subtarget->hasDSP())) {
1276 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1277 }
1278 return 0;
1279}
1280
1281unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1282 if (RetVT.SimpleTy != MVT::v8i16)
1283 return 0;
1284 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1285 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1286 }
1287 return 0;
1288}
1289
1290unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1291 if (RetVT.SimpleTy != MVT::v4i32)
1292 return 0;
1293 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1294 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1295 }
1296 return 0;
1297}
1298
1299unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1300 if (RetVT.SimpleTy != MVT::v2i64)
1301 return 0;
1302 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1303 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1304 }
1305 return 0;
1306}
1307
1308unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1309 switch (VT.SimpleTy) {
1310 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1311 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1312 case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op1);
1313 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1314 case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op1);
1315 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1316 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1317 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1318 default: return 0;
1319 }
1320}
1321
1322// FastEmit functions for ISD::ADDC.
1323
1324unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1325 if (RetVT.SimpleTy != MVT::i32)
1326 return 0;
1327 if ((Subtarget->hasDSP())) {
1328 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDSC, RC: &Mips::GPR32RegClass, Op0, Op1);
1329 }
1330 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
1331 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1332 }
1333 return 0;
1334}
1335
1336unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1337 if (RetVT.SimpleTy != MVT::i64)
1338 return 0;
1339 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
1340 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1341 }
1342 return 0;
1343}
1344
1345unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1346 switch (VT.SimpleTy) {
1347 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op1);
1348 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op1);
1349 default: return 0;
1350 }
1351}
1352
1353// FastEmit functions for ISD::ADDE.
1354
1355unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1356 if (RetVT.SimpleTy != MVT::i32)
1357 return 0;
1358 if ((Subtarget->hasDSP())) {
1359 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDWC, RC: &Mips::GPR32RegClass, Op0, Op1);
1360 }
1361 return 0;
1362}
1363
1364unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1365 switch (VT.SimpleTy) {
1366 case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op1);
1367 default: return 0;
1368 }
1369}
1370
1371// FastEmit functions for ISD::AND.
1372
1373unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1374 if (RetVT.SimpleTy != MVT::i32)
1375 return 0;
1376 if ((Subtarget->inMips16Mode())) {
1377 return fastEmitInst_rr(MachineInstOpcode: Mips::AndRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1378 }
1379 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1380 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1381 }
1382 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1383 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1384 }
1385 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1386 return fastEmitInst_rr(MachineInstOpcode: Mips::AND, RC: &Mips::GPR32RegClass, Op0, Op1);
1387 }
1388 return 0;
1389}
1390
1391unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1392 if (RetVT.SimpleTy != MVT::i64)
1393 return 0;
1394 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1395 return fastEmitInst_rr(MachineInstOpcode: Mips::AND64, RC: &Mips::GPR64RegClass, Op0, Op1);
1396 }
1397 return 0;
1398}
1399
1400unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1401 if (RetVT.SimpleTy != MVT::v16i8)
1402 return 0;
1403 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1404 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
1405 }
1406 return 0;
1407}
1408
1409unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1410 if (RetVT.SimpleTy != MVT::v8i16)
1411 return 0;
1412 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1413 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
1414 }
1415 return 0;
1416}
1417
1418unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1419 if (RetVT.SimpleTy != MVT::v4i32)
1420 return 0;
1421 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1422 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
1423 }
1424 return 0;
1425}
1426
1427unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1428 if (RetVT.SimpleTy != MVT::v2i64)
1429 return 0;
1430 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1431 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
1432 }
1433 return 0;
1434}
1435
1436unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1437 switch (VT.SimpleTy) {
1438 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1439 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1440 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1441 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1442 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1443 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1444 default: return 0;
1445 }
1446}
1447
1448// FastEmit functions for ISD::FADD.
1449
1450unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1451 if (RetVT.SimpleTy != MVT::f32)
1452 return 0;
1453 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1454 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1455 }
1456 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1457 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1458 }
1459 return 0;
1460}
1461
1462unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1463 if (RetVT.SimpleTy != MVT::f64)
1464 return 0;
1465 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1466 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1467 }
1468 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1469 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1470 }
1471 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1472 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1473 }
1474 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1475 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1476 }
1477 return 0;
1478}
1479
1480unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1481 if (RetVT.SimpleTy != MVT::v4f32)
1482 return 0;
1483 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1484 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1485 }
1486 return 0;
1487}
1488
1489unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1490 if (RetVT.SimpleTy != MVT::v2f64)
1491 return 0;
1492 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1493 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1494 }
1495 return 0;
1496}
1497
1498unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1499 switch (VT.SimpleTy) {
1500 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1501 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1502 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1503 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1504 default: return 0;
1505 }
1506}
1507
1508// FastEmit functions for ISD::FDIV.
1509
1510unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1511 if (RetVT.SimpleTy != MVT::f32)
1512 return 0;
1513 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1514 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1515 }
1516 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1517 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1518 }
1519 return 0;
1520}
1521
1522unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1523 if (RetVT.SimpleTy != MVT::f64)
1524 return 0;
1525 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1526 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1527 }
1528 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1529 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1530 }
1531 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1532 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1533 }
1534 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1535 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1536 }
1537 return 0;
1538}
1539
1540unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1541 if (RetVT.SimpleTy != MVT::v4f32)
1542 return 0;
1543 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1544 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1545 }
1546 return 0;
1547}
1548
1549unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1550 if (RetVT.SimpleTy != MVT::v2f64)
1551 return 0;
1552 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1553 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1554 }
1555 return 0;
1556}
1557
1558unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1559 switch (VT.SimpleTy) {
1560 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1561 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1562 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1563 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1564 default: return 0;
1565 }
1566}
1567
1568// FastEmit functions for ISD::FMAXNUM_IEEE.
1569
1570unsigned fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1571 if (RetVT.SimpleTy != MVT::f32)
1572 return 0;
1573 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1574 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1575 }
1576 return 0;
1577}
1578
1579unsigned fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1580 if (RetVT.SimpleTy != MVT::f64)
1581 return 0;
1582 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1583 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1584 }
1585 return 0;
1586}
1587
1588unsigned fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1589 switch (VT.SimpleTy) {
1590 case MVT::f32: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1591 case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1592 default: return 0;
1593 }
1594}
1595
1596// FastEmit functions for ISD::FMINNUM_IEEE.
1597
1598unsigned fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1599 if (RetVT.SimpleTy != MVT::f32)
1600 return 0;
1601 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1602 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1603 }
1604 return 0;
1605}
1606
1607unsigned fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1608 if (RetVT.SimpleTy != MVT::f64)
1609 return 0;
1610 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1611 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1612 }
1613 return 0;
1614}
1615
1616unsigned fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1617 switch (VT.SimpleTy) {
1618 case MVT::f32: return fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1619 case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1620 default: return 0;
1621 }
1622}
1623
1624// FastEmit functions for ISD::FMUL.
1625
1626unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1627 if (RetVT.SimpleTy != MVT::f32)
1628 return 0;
1629 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1630 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1631 }
1632 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1633 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1634 }
1635 return 0;
1636}
1637
1638unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1639 if (RetVT.SimpleTy != MVT::f64)
1640 return 0;
1641 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1642 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1643 }
1644 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1645 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1646 }
1647 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1648 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1649 }
1650 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1651 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1652 }
1653 return 0;
1654}
1655
1656unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1657 if (RetVT.SimpleTy != MVT::v4f32)
1658 return 0;
1659 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1660 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1661 }
1662 return 0;
1663}
1664
1665unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1666 if (RetVT.SimpleTy != MVT::v2f64)
1667 return 0;
1668 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1669 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1670 }
1671 return 0;
1672}
1673
1674unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1675 switch (VT.SimpleTy) {
1676 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1677 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1678 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1679 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1680 default: return 0;
1681 }
1682}
1683
1684// FastEmit functions for ISD::FSUB.
1685
1686unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1687 if (RetVT.SimpleTy != MVT::f32)
1688 return 0;
1689 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1690 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1691 }
1692 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1693 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1694 }
1695 return 0;
1696}
1697
1698unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1699 if (RetVT.SimpleTy != MVT::f64)
1700 return 0;
1701 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1702 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1703 }
1704 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1705 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1706 }
1707 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1708 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1709 }
1710 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1711 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1712 }
1713 return 0;
1714}
1715
1716unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1717 if (RetVT.SimpleTy != MVT::v4f32)
1718 return 0;
1719 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1720 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1721 }
1722 return 0;
1723}
1724
1725unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1726 if (RetVT.SimpleTy != MVT::v2f64)
1727 return 0;
1728 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1729 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1730 }
1731 return 0;
1732}
1733
1734unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1735 switch (VT.SimpleTy) {
1736 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
1737 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
1738 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
1739 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
1740 default: return 0;
1741 }
1742}
1743
1744// FastEmit functions for ISD::MUL.
1745
1746unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1747 if (RetVT.SimpleTy != MVT::i32)
1748 return 0;
1749 if ((Subtarget->inMips16Mode())) {
1750 return fastEmitInst_rr(MachineInstOpcode: Mips::MultRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1751 }
1752 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1753 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1754 }
1755 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1756 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1757 }
1758 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1759 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_R6, RC: &Mips::GPR32RegClass, Op0, Op1);
1760 }
1761 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1762 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL, RC: &Mips::GPR32RegClass, Op0, Op1);
1763 }
1764 return 0;
1765}
1766
1767unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1768 if (RetVT.SimpleTy != MVT::i64)
1769 return 0;
1770 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1771 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL_R6, RC: &Mips::GPR64RegClass, Op0, Op1);
1772 }
1773 if ((Subtarget->hasCnMips())) {
1774 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL, RC: &Mips::GPR64RegClass, Op0, Op1);
1775 }
1776 return 0;
1777}
1778
1779unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1780 if (RetVT.SimpleTy != MVT::v16i8)
1781 return 0;
1782 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1783 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1784 }
1785 return 0;
1786}
1787
1788unsigned fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1789 if (RetVT.SimpleTy != MVT::v2i16)
1790 return 0;
1791 if ((Subtarget->hasDSPR2())) {
1792 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1793 }
1794 return 0;
1795}
1796
1797unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1798 if (RetVT.SimpleTy != MVT::v8i16)
1799 return 0;
1800 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1801 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1802 }
1803 return 0;
1804}
1805
1806unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1807 if (RetVT.SimpleTy != MVT::v4i32)
1808 return 0;
1809 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1810 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1811 }
1812 return 0;
1813}
1814
1815unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1816 if (RetVT.SimpleTy != MVT::v2i64)
1817 return 0;
1818 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1819 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1820 }
1821 return 0;
1822}
1823
1824unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1825 switch (VT.SimpleTy) {
1826 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
1827 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
1828 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op1);
1829 case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op1);
1830 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
1831 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
1832 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
1833 default: return 0;
1834 }
1835}
1836
1837// FastEmit functions for ISD::MULHS.
1838
1839unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1840 if (RetVT.SimpleTy != MVT::i32)
1841 return 0;
1842 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1843 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1844 }
1845 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1846 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH, RC: &Mips::GPR32RegClass, Op0, Op1);
1847 }
1848 return 0;
1849}
1850
1851unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1852 if (RetVT.SimpleTy != MVT::i64)
1853 return 0;
1854 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1855 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUH, RC: &Mips::GPR64RegClass, Op0, Op1);
1856 }
1857 return 0;
1858}
1859
1860unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1861 switch (VT.SimpleTy) {
1862 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1);
1863 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1);
1864 default: return 0;
1865 }
1866}
1867
1868// FastEmit functions for ISD::MULHU.
1869
1870unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1871 if (RetVT.SimpleTy != MVT::i32)
1872 return 0;
1873 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1874 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1875 }
1876 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1877 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU, RC: &Mips::GPR32RegClass, Op0, Op1);
1878 }
1879 return 0;
1880}
1881
1882unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1883 if (RetVT.SimpleTy != MVT::i64)
1884 return 0;
1885 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1886 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUHU, RC: &Mips::GPR64RegClass, Op0, Op1);
1887 }
1888 return 0;
1889}
1890
1891unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1892 switch (VT.SimpleTy) {
1893 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1);
1894 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1);
1895 default: return 0;
1896 }
1897}
1898
1899// FastEmit functions for ISD::OR.
1900
1901unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1902 if (RetVT.SimpleTy != MVT::i32)
1903 return 0;
1904 if ((Subtarget->inMips16Mode())) {
1905 return fastEmitInst_rr(MachineInstOpcode: Mips::OrRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1906 }
1907 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1908 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1909 }
1910 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1911 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1912 }
1913 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1914 return fastEmitInst_rr(MachineInstOpcode: Mips::OR, RC: &Mips::GPR32RegClass, Op0, Op1);
1915 }
1916 return 0;
1917}
1918
1919unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1920 if (RetVT.SimpleTy != MVT::i64)
1921 return 0;
1922 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1923 return fastEmitInst_rr(MachineInstOpcode: Mips::OR64, RC: &Mips::GPR64RegClass, Op0, Op1);
1924 }
1925 return 0;
1926}
1927
1928unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1929 if (RetVT.SimpleTy != MVT::v16i8)
1930 return 0;
1931 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1932 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
1933 }
1934 return 0;
1935}
1936
1937unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1938 if (RetVT.SimpleTy != MVT::v8i16)
1939 return 0;
1940 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1941 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
1942 }
1943 return 0;
1944}
1945
1946unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1947 if (RetVT.SimpleTy != MVT::v4i32)
1948 return 0;
1949 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1950 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
1951 }
1952 return 0;
1953}
1954
1955unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1956 if (RetVT.SimpleTy != MVT::v2i64)
1957 return 0;
1958 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1959 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
1960 }
1961 return 0;
1962}
1963
1964unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1965 switch (VT.SimpleTy) {
1966 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
1967 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
1968 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
1969 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
1970 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
1971 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
1972 default: return 0;
1973 }
1974}
1975
1976// FastEmit functions for ISD::ROTR.
1977
1978unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1979 if (RetVT.SimpleTy != MVT::i32)
1980 return 0;
1981 if ((Subtarget->inMicroMipsMode())) {
1982 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1983 }
1984 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1985 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV, RC: &Mips::GPR32RegClass, Op0, Op1);
1986 }
1987 return 0;
1988}
1989
1990unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1991 switch (VT.SimpleTy) {
1992 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
1993 default: return 0;
1994 }
1995}
1996
1997// FastEmit functions for ISD::SDIV.
1998
1999unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2000 if (RetVT.SimpleTy != MVT::i32)
2001 return 0;
2002 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2003 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2004 }
2005 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2006 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV, RC: &Mips::GPR32RegClass, Op0, Op1);
2007 }
2008 return 0;
2009}
2010
2011unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2012 if (RetVT.SimpleTy != MVT::i64)
2013 return 0;
2014 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2015 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIV, RC: &Mips::GPR64RegClass, Op0, Op1);
2016 }
2017 return 0;
2018}
2019
2020unsigned fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2021 if (RetVT.SimpleTy != MVT::v16i8)
2022 return 0;
2023 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2024 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2025 }
2026 return 0;
2027}
2028
2029unsigned fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2030 if (RetVT.SimpleTy != MVT::v8i16)
2031 return 0;
2032 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2033 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2034 }
2035 return 0;
2036}
2037
2038unsigned fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2039 if (RetVT.SimpleTy != MVT::v4i32)
2040 return 0;
2041 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2042 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2043 }
2044 return 0;
2045}
2046
2047unsigned fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2048 if (RetVT.SimpleTy != MVT::v2i64)
2049 return 0;
2050 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2051 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2052 }
2053 return 0;
2054}
2055
2056unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2057 switch (VT.SimpleTy) {
2058 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
2059 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
2060 case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2061 case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2062 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2063 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2064 default: return 0;
2065 }
2066}
2067
2068// FastEmit functions for ISD::SHL.
2069
2070unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2071 if (RetVT.SimpleTy != MVT::i32)
2072 return 0;
2073 if ((Subtarget->inMicroMipsMode())) {
2074 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2075 }
2076 if ((Subtarget->inMips16Mode())) {
2077 return fastEmitInst_rr(MachineInstOpcode: Mips::SllvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2078 }
2079 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2080 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2081 }
2082 return 0;
2083}
2084
2085unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2086 if (RetVT.SimpleTy != MVT::v16i8)
2087 return 0;
2088 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2089 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2090 }
2091 return 0;
2092}
2093
2094unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2095 if (RetVT.SimpleTy != MVT::v8i16)
2096 return 0;
2097 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2098 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2099 }
2100 return 0;
2101}
2102
2103unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2104 if (RetVT.SimpleTy != MVT::v4i32)
2105 return 0;
2106 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2107 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2108 }
2109 return 0;
2110}
2111
2112unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2113 if (RetVT.SimpleTy != MVT::v2i64)
2114 return 0;
2115 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2116 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2117 }
2118 return 0;
2119}
2120
2121unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2122 switch (VT.SimpleTy) {
2123 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
2124 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
2125 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
2126 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
2127 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
2128 default: return 0;
2129 }
2130}
2131
2132// FastEmit functions for ISD::SMAX.
2133
2134unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2135 if (RetVT.SimpleTy != MVT::v16i8)
2136 return 0;
2137 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2138 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2139 }
2140 return 0;
2141}
2142
2143unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2144 if (RetVT.SimpleTy != MVT::v8i16)
2145 return 0;
2146 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2147 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2148 }
2149 return 0;
2150}
2151
2152unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2153 if (RetVT.SimpleTy != MVT::v4i32)
2154 return 0;
2155 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2156 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2157 }
2158 return 0;
2159}
2160
2161unsigned fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2162 if (RetVT.SimpleTy != MVT::v2i64)
2163 return 0;
2164 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2165 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2166 }
2167 return 0;
2168}
2169
2170unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2171 switch (VT.SimpleTy) {
2172 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2173 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2174 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2175 case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2176 default: return 0;
2177 }
2178}
2179
2180// FastEmit functions for ISD::SMIN.
2181
2182unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2183 if (RetVT.SimpleTy != MVT::v16i8)
2184 return 0;
2185 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2186 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2187 }
2188 return 0;
2189}
2190
2191unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2192 if (RetVT.SimpleTy != MVT::v8i16)
2193 return 0;
2194 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2195 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2196 }
2197 return 0;
2198}
2199
2200unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2201 if (RetVT.SimpleTy != MVT::v4i32)
2202 return 0;
2203 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2204 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2205 }
2206 return 0;
2207}
2208
2209unsigned fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2210 if (RetVT.SimpleTy != MVT::v2i64)
2211 return 0;
2212 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2213 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2214 }
2215 return 0;
2216}
2217
2218unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2219 switch (VT.SimpleTy) {
2220 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2221 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2222 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2223 case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
2224 default: return 0;
2225 }
2226}
2227
2228// FastEmit functions for ISD::SRA.
2229
2230unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2231 if (RetVT.SimpleTy != MVT::i32)
2232 return 0;
2233 if ((Subtarget->inMicroMipsMode())) {
2234 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2235 }
2236 if ((Subtarget->inMips16Mode())) {
2237 return fastEmitInst_rr(MachineInstOpcode: Mips::SravRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2238 }
2239 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2240 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV, RC: &Mips::GPR32RegClass, Op0, Op1);
2241 }
2242 return 0;
2243}
2244
2245unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2246 if (RetVT.SimpleTy != MVT::v16i8)
2247 return 0;
2248 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2249 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2250 }
2251 return 0;
2252}
2253
2254unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2255 if (RetVT.SimpleTy != MVT::v8i16)
2256 return 0;
2257 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2258 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2259 }
2260 return 0;
2261}
2262
2263unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2264 if (RetVT.SimpleTy != MVT::v4i32)
2265 return 0;
2266 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2267 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2268 }
2269 return 0;
2270}
2271
2272unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2273 if (RetVT.SimpleTy != MVT::v2i64)
2274 return 0;
2275 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2276 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2277 }
2278 return 0;
2279}
2280
2281unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2282 switch (VT.SimpleTy) {
2283 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2284 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
2285 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
2286 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
2287 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
2288 default: return 0;
2289 }
2290}
2291
2292// FastEmit functions for ISD::SREM.
2293
2294unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2295 if (RetVT.SimpleTy != MVT::i32)
2296 return 0;
2297 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2298 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2299 }
2300 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2301 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD, RC: &Mips::GPR32RegClass, Op0, Op1);
2302 }
2303 return 0;
2304}
2305
2306unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2307 if (RetVT.SimpleTy != MVT::i64)
2308 return 0;
2309 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2310 return fastEmitInst_rr(MachineInstOpcode: Mips::DMOD, RC: &Mips::GPR64RegClass, Op0, Op1);
2311 }
2312 return 0;
2313}
2314
2315unsigned fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2316 if (RetVT.SimpleTy != MVT::v16i8)
2317 return 0;
2318 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2319 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2320 }
2321 return 0;
2322}
2323
2324unsigned fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2325 if (RetVT.SimpleTy != MVT::v8i16)
2326 return 0;
2327 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2328 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2329 }
2330 return 0;
2331}
2332
2333unsigned fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2334 if (RetVT.SimpleTy != MVT::v4i32)
2335 return 0;
2336 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2337 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2338 }
2339 return 0;
2340}
2341
2342unsigned fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2343 if (RetVT.SimpleTy != MVT::v2i64)
2344 return 0;
2345 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2346 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2347 }
2348 return 0;
2349}
2350
2351unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2352 switch (VT.SimpleTy) {
2353 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2354 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2355 case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op1);
2356 case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op1);
2357 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1);
2358 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1);
2359 default: return 0;
2360 }
2361}
2362
2363// FastEmit functions for ISD::SRL.
2364
2365unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2366 if (RetVT.SimpleTy != MVT::i32)
2367 return 0;
2368 if ((Subtarget->inMicroMipsMode())) {
2369 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2370 }
2371 if ((Subtarget->inMips16Mode())) {
2372 return fastEmitInst_rr(MachineInstOpcode: Mips::SrlvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2373 }
2374 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2375 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2376 }
2377 return 0;
2378}
2379
2380unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2381 if (RetVT.SimpleTy != MVT::v16i8)
2382 return 0;
2383 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2384 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2385 }
2386 return 0;
2387}
2388
2389unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2390 if (RetVT.SimpleTy != MVT::v8i16)
2391 return 0;
2392 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2393 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2394 }
2395 return 0;
2396}
2397
2398unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2399 if (RetVT.SimpleTy != MVT::v4i32)
2400 return 0;
2401 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2402 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2403 }
2404 return 0;
2405}
2406
2407unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2408 if (RetVT.SimpleTy != MVT::v2i64)
2409 return 0;
2410 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2411 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2412 }
2413 return 0;
2414}
2415
2416unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2417 switch (VT.SimpleTy) {
2418 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2419 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
2420 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
2421 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
2422 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
2423 default: return 0;
2424 }
2425}
2426
2427// FastEmit functions for ISD::SUB.
2428
2429unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2430 if (RetVT.SimpleTy != MVT::i32)
2431 return 0;
2432 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2433 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
2434 }
2435 if ((Subtarget->inMips16Mode())) {
2436 return fastEmitInst_rr(MachineInstOpcode: Mips::SubuRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2437 }
2438 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2439 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2440 }
2441 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2442 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2443 }
2444 return 0;
2445}
2446
2447unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2448 if (RetVT.SimpleTy != MVT::i64)
2449 return 0;
2450 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2451 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2452 }
2453 return 0;
2454}
2455
2456unsigned fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2457 if (RetVT.SimpleTy != MVT::v4i8)
2458 return 0;
2459 if ((Subtarget->hasDSP())) {
2460 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
2461 }
2462 return 0;
2463}
2464
2465unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2466 if (RetVT.SimpleTy != MVT::v16i8)
2467 return 0;
2468 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2469 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2470 }
2471 return 0;
2472}
2473
2474unsigned fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2475 if (RetVT.SimpleTy != MVT::v2i16)
2476 return 0;
2477 if ((Subtarget->hasDSP())) {
2478 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
2479 }
2480 return 0;
2481}
2482
2483unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2484 if (RetVT.SimpleTy != MVT::v8i16)
2485 return 0;
2486 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2487 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2488 }
2489 return 0;
2490}
2491
2492unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2493 if (RetVT.SimpleTy != MVT::v4i32)
2494 return 0;
2495 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2496 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2497 }
2498 return 0;
2499}
2500
2501unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2502 if (RetVT.SimpleTy != MVT::v2i64)
2503 return 0;
2504 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2505 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2506 }
2507 return 0;
2508}
2509
2510unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2511 switch (VT.SimpleTy) {
2512 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2513 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2514 case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op1);
2515 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2516 case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op1);
2517 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2518 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2519 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2520 default: return 0;
2521 }
2522}
2523
2524// FastEmit functions for ISD::SUBC.
2525
2526unsigned fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2527 if (RetVT.SimpleTy != MVT::i32)
2528 return 0;
2529 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2530 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2531 }
2532 if ((Subtarget->inMicroMipsMode())) {
2533 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2534 }
2535 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2536 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2537 }
2538 return 0;
2539}
2540
2541unsigned fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2542 if (RetVT.SimpleTy != MVT::i64)
2543 return 0;
2544 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())) {
2545 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2546 }
2547 return 0;
2548}
2549
2550unsigned fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2551 switch (VT.SimpleTy) {
2552 case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op1);
2553 case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op1);
2554 default: return 0;
2555 }
2556}
2557
2558// FastEmit functions for ISD::UDIV.
2559
2560unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2561 if (RetVT.SimpleTy != MVT::i32)
2562 return 0;
2563 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2564 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2565 }
2566 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2567 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU, RC: &Mips::GPR32RegClass, Op0, Op1);
2568 }
2569 return 0;
2570}
2571
2572unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2573 if (RetVT.SimpleTy != MVT::i64)
2574 return 0;
2575 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2576 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIVU, RC: &Mips::GPR64RegClass, Op0, Op1);
2577 }
2578 return 0;
2579}
2580
2581unsigned fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2582 if (RetVT.SimpleTy != MVT::v16i8)
2583 return 0;
2584 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2585 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2586 }
2587 return 0;
2588}
2589
2590unsigned fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2591 if (RetVT.SimpleTy != MVT::v8i16)
2592 return 0;
2593 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2594 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2595 }
2596 return 0;
2597}
2598
2599unsigned fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2600 if (RetVT.SimpleTy != MVT::v4i32)
2601 return 0;
2602 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2603 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2604 }
2605 return 0;
2606}
2607
2608unsigned fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2609 if (RetVT.SimpleTy != MVT::v2i64)
2610 return 0;
2611 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2612 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2613 }
2614 return 0;
2615}
2616
2617unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2618 switch (VT.SimpleTy) {
2619 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2620 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2621 case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2622 case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2623 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2624 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2625 default: return 0;
2626 }
2627}
2628
2629// FastEmit functions for ISD::UMAX.
2630
2631unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2632 if (RetVT.SimpleTy != MVT::v16i8)
2633 return 0;
2634 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2635 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2636 }
2637 return 0;
2638}
2639
2640unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2641 if (RetVT.SimpleTy != MVT::v8i16)
2642 return 0;
2643 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2644 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2645 }
2646 return 0;
2647}
2648
2649unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2650 if (RetVT.SimpleTy != MVT::v4i32)
2651 return 0;
2652 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2653 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2654 }
2655 return 0;
2656}
2657
2658unsigned fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2659 if (RetVT.SimpleTy != MVT::v2i64)
2660 return 0;
2661 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2662 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2663 }
2664 return 0;
2665}
2666
2667unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2668 switch (VT.SimpleTy) {
2669 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2670 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2671 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2672 case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2673 default: return 0;
2674 }
2675}
2676
2677// FastEmit functions for ISD::UMIN.
2678
2679unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2680 if (RetVT.SimpleTy != MVT::v16i8)
2681 return 0;
2682 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2683 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2684 }
2685 return 0;
2686}
2687
2688unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2689 if (RetVT.SimpleTy != MVT::v8i16)
2690 return 0;
2691 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2692 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2693 }
2694 return 0;
2695}
2696
2697unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2698 if (RetVT.SimpleTy != MVT::v4i32)
2699 return 0;
2700 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2701 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2702 }
2703 return 0;
2704}
2705
2706unsigned fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2707 if (RetVT.SimpleTy != MVT::v2i64)
2708 return 0;
2709 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2710 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2711 }
2712 return 0;
2713}
2714
2715unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2716 switch (VT.SimpleTy) {
2717 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2718 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2719 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2720 case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
2721 default: return 0;
2722 }
2723}
2724
2725// FastEmit functions for ISD::UREM.
2726
2727unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2728 if (RetVT.SimpleTy != MVT::i32)
2729 return 0;
2730 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2731 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2732 }
2733 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2734 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU, RC: &Mips::GPR32RegClass, Op0, Op1);
2735 }
2736 return 0;
2737}
2738
2739unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2740 if (RetVT.SimpleTy != MVT::i64)
2741 return 0;
2742 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2743 return fastEmitInst_rr(MachineInstOpcode: Mips::DMODU, RC: &Mips::GPR64RegClass, Op0, Op1);
2744 }
2745 return 0;
2746}
2747
2748unsigned fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2749 if (RetVT.SimpleTy != MVT::v16i8)
2750 return 0;
2751 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2752 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2753 }
2754 return 0;
2755}
2756
2757unsigned fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2758 if (RetVT.SimpleTy != MVT::v8i16)
2759 return 0;
2760 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2761 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2762 }
2763 return 0;
2764}
2765
2766unsigned fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2767 if (RetVT.SimpleTy != MVT::v4i32)
2768 return 0;
2769 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2770 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2771 }
2772 return 0;
2773}
2774
2775unsigned fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2776 if (RetVT.SimpleTy != MVT::v2i64)
2777 return 0;
2778 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2779 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2780 }
2781 return 0;
2782}
2783
2784unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2785 switch (VT.SimpleTy) {
2786 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
2787 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
2788 case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op1);
2789 case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op1);
2790 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1);
2791 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1);
2792 default: return 0;
2793 }
2794}
2795
2796// FastEmit functions for ISD::XOR.
2797
2798unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2799 if (RetVT.SimpleTy != MVT::i32)
2800 return 0;
2801 if ((Subtarget->inMips16Mode())) {
2802 return fastEmitInst_rr(MachineInstOpcode: Mips::XorRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2803 }
2804 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2805 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2806 }
2807 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2808 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2809 }
2810 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2811 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR, RC: &Mips::GPR32RegClass, Op0, Op1);
2812 }
2813 return 0;
2814}
2815
2816unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2817 if (RetVT.SimpleTy != MVT::i64)
2818 return 0;
2819 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
2820 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR64, RC: &Mips::GPR64RegClass, Op0, Op1);
2821 }
2822 return 0;
2823}
2824
2825unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2826 if (RetVT.SimpleTy != MVT::v16i8)
2827 return 0;
2828 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2829 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
2830 }
2831 return 0;
2832}
2833
2834unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2835 if (RetVT.SimpleTy != MVT::v8i16)
2836 return 0;
2837 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2838 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
2839 }
2840 return 0;
2841}
2842
2843unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2844 if (RetVT.SimpleTy != MVT::v4i32)
2845 return 0;
2846 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2847 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
2848 }
2849 return 0;
2850}
2851
2852unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2853 if (RetVT.SimpleTy != MVT::v2i64)
2854 return 0;
2855 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2856 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
2857 }
2858 return 0;
2859}
2860
2861unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2862 switch (VT.SimpleTy) {
2863 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
2864 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
2865 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
2866 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
2867 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
2868 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
2869 default: return 0;
2870 }
2871}
2872
2873// FastEmit functions for MipsISD::BuildPairF64.
2874
2875unsigned fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2876 if (RetVT.SimpleTy != MVT::f64)
2877 return 0;
2878 if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
2879 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64_64, RC: &Mips::FGR64RegClass, Op0, Op1);
2880 }
2881 if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
2882 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64, RC: &Mips::AFGR64RegClass, Op0, Op1);
2883 }
2884 return 0;
2885}
2886
2887unsigned fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2888 switch (VT.SimpleTy) {
2889 case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op1);
2890 default: return 0;
2891 }
2892}
2893
2894// FastEmit functions for MipsISD::DivRem.
2895
2896unsigned fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2897 if (RetVT.SimpleTy != MVT::Untyped)
2898 return 0;
2899 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2900 return fastEmitInst_rr(MachineInstOpcode: Mips::SDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
2901 }
2902 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2903 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoSDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
2904 }
2905 return 0;
2906}
2907
2908unsigned fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2909 if (RetVT.SimpleTy != MVT::Untyped)
2910 return 0;
2911 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2912 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDSDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
2913 }
2914 return 0;
2915}
2916
2917unsigned fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2918 switch (VT.SimpleTy) {
2919 case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op1);
2920 case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op1);
2921 default: return 0;
2922 }
2923}
2924
2925// FastEmit functions for MipsISD::DivRem16.
2926
2927unsigned fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2928 if (RetVT.SimpleTy != MVT::isVoid)
2929 return 0;
2930 if ((Subtarget->inMips16Mode())) {
2931 return fastEmitInst_rr(MachineInstOpcode: Mips::DivRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2932 }
2933 return 0;
2934}
2935
2936unsigned fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2937 switch (VT.SimpleTy) {
2938 case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op1);
2939 default: return 0;
2940 }
2941}
2942
2943// FastEmit functions for MipsISD::DivRemU.
2944
2945unsigned fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2946 if (RetVT.SimpleTy != MVT::Untyped)
2947 return 0;
2948 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2949 return fastEmitInst_rr(MachineInstOpcode: Mips::UDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
2950 }
2951 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2952 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoUDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
2953 }
2954 return 0;
2955}
2956
2957unsigned fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2958 if (RetVT.SimpleTy != MVT::Untyped)
2959 return 0;
2960 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2961 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDUDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
2962 }
2963 return 0;
2964}
2965
2966unsigned fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2967 switch (VT.SimpleTy) {
2968 case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op1);
2969 case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op1);
2970 default: return 0;
2971 }
2972}
2973
2974// FastEmit functions for MipsISD::DivRemU16.
2975
2976unsigned fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2977 if (RetVT.SimpleTy != MVT::isVoid)
2978 return 0;
2979 if ((Subtarget->inMips16Mode())) {
2980 return fastEmitInst_rr(MachineInstOpcode: Mips::DivuRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2981 }
2982 return 0;
2983}
2984
2985unsigned fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2986 switch (VT.SimpleTy) {
2987 case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op1);
2988 default: return 0;
2989 }
2990}
2991
2992// FastEmit functions for MipsISD::EH_RETURN.
2993
2994unsigned fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2995 if (RetVT.SimpleTy != MVT::isVoid)
2996 return 0;
2997 return fastEmitInst_rr(MachineInstOpcode: Mips::MIPSeh_return32, RC: &Mips::GPR32RegClass, Op0, Op1);
2998}
2999
3000unsigned fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3001 if (RetVT.SimpleTy != MVT::isVoid)
3002 return 0;
3003 return fastEmitInst_rr(MachineInstOpcode: Mips::MIPSeh_return64, RC: &Mips::GPR64RegClass, Op0, Op1);
3004}
3005
3006unsigned fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3007 switch (VT.SimpleTy) {
3008 case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op1);
3009 case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op1);
3010 default: return 0;
3011 }
3012}
3013
3014// FastEmit functions for MipsISD::ILVEV.
3015
3016unsigned fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3017 if (RetVT.SimpleTy != MVT::v16i8)
3018 return 0;
3019 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3020 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3021 }
3022 return 0;
3023}
3024
3025unsigned fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3026 if (RetVT.SimpleTy != MVT::v8i16)
3027 return 0;
3028 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3029 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3030 }
3031 return 0;
3032}
3033
3034unsigned fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3035 if (RetVT.SimpleTy != MVT::v4i32)
3036 return 0;
3037 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3038 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3039 }
3040 return 0;
3041}
3042
3043unsigned fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3044 if (RetVT.SimpleTy != MVT::v2i64)
3045 return 0;
3046 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3047 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3048 }
3049 return 0;
3050}
3051
3052unsigned fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3053 switch (VT.SimpleTy) {
3054 case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3055 case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3056 case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3057 case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3058 default: return 0;
3059 }
3060}
3061
3062// FastEmit functions for MipsISD::ILVL.
3063
3064unsigned fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3065 if (RetVT.SimpleTy != MVT::v16i8)
3066 return 0;
3067 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3068 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3069 }
3070 return 0;
3071}
3072
3073unsigned fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3074 if (RetVT.SimpleTy != MVT::v8i16)
3075 return 0;
3076 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3077 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3078 }
3079 return 0;
3080}
3081
3082unsigned fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3083 if (RetVT.SimpleTy != MVT::v4i32)
3084 return 0;
3085 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3086 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3087 }
3088 return 0;
3089}
3090
3091unsigned fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3092 if (RetVT.SimpleTy != MVT::v2i64)
3093 return 0;
3094 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3095 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3096 }
3097 return 0;
3098}
3099
3100unsigned fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3101 switch (VT.SimpleTy) {
3102 case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op1);
3103 case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op1);
3104 case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op1);
3105 case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op1);
3106 default: return 0;
3107 }
3108}
3109
3110// FastEmit functions for MipsISD::ILVOD.
3111
3112unsigned fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3113 if (RetVT.SimpleTy != MVT::v16i8)
3114 return 0;
3115 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3116 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3117 }
3118 return 0;
3119}
3120
3121unsigned fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3122 if (RetVT.SimpleTy != MVT::v8i16)
3123 return 0;
3124 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3125 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3126 }
3127 return 0;
3128}
3129
3130unsigned fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3131 if (RetVT.SimpleTy != MVT::v4i32)
3132 return 0;
3133 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3134 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3135 }
3136 return 0;
3137}
3138
3139unsigned fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3140 if (RetVT.SimpleTy != MVT::v2i64)
3141 return 0;
3142 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3143 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3144 }
3145 return 0;
3146}
3147
3148unsigned fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3149 switch (VT.SimpleTy) {
3150 case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3151 case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3152 case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3153 case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3154 default: return 0;
3155 }
3156}
3157
3158// FastEmit functions for MipsISD::ILVR.
3159
3160unsigned fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3161 if (RetVT.SimpleTy != MVT::v16i8)
3162 return 0;
3163 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3164 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3165 }
3166 return 0;
3167}
3168
3169unsigned fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3170 if (RetVT.SimpleTy != MVT::v8i16)
3171 return 0;
3172 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3173 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3174 }
3175 return 0;
3176}
3177
3178unsigned fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3179 if (RetVT.SimpleTy != MVT::v4i32)
3180 return 0;
3181 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3182 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3183 }
3184 return 0;
3185}
3186
3187unsigned fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3188 if (RetVT.SimpleTy != MVT::v2i64)
3189 return 0;
3190 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3191 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3192 }
3193 return 0;
3194}
3195
3196unsigned fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3197 switch (VT.SimpleTy) {
3198 case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op1);
3199 case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op1);
3200 case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op1);
3201 case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op1);
3202 default: return 0;
3203 }
3204}
3205
3206// FastEmit functions for MipsISD::MTLOHI.
3207
3208unsigned fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3209 if (RetVT.SimpleTy != MVT::Untyped)
3210 return 0;
3211 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3212 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3213 }
3214 if ((Subtarget->hasDSP()) && (!Subtarget->inMips16Mode())) {
3215 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3216 }
3217 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3218 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI, RC: &Mips::ACC64RegClass, Op0, Op1);
3219 }
3220 return 0;
3221}
3222
3223unsigned fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3224 if (RetVT.SimpleTy != MVT::Untyped)
3225 return 0;
3226 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3227 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI64, RC: &Mips::ACC128RegClass, Op0, Op1);
3228 }
3229 return 0;
3230}
3231
3232unsigned fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3233 switch (VT.SimpleTy) {
3234 case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op1);
3235 case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op1);
3236 default: return 0;
3237 }
3238}
3239
3240// FastEmit functions for MipsISD::Mult.
3241
3242unsigned fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3243 if (RetVT.SimpleTy != MVT::Untyped)
3244 return 0;
3245 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3246 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3247 }
3248 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3249 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3250 }
3251 if ((Subtarget->hasDSP())) {
3252 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3253 }
3254 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3255 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT, RC: &Mips::ACC64RegClass, Op0, Op1);
3256 }
3257 return 0;
3258}
3259
3260unsigned fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3261 if (RetVT.SimpleTy != MVT::Untyped)
3262 return 0;
3263 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3264 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULT, RC: &Mips::ACC128RegClass, Op0, Op1);
3265 }
3266 return 0;
3267}
3268
3269unsigned fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3270 switch (VT.SimpleTy) {
3271 case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op1);
3272 case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op1);
3273 default: return 0;
3274 }
3275}
3276
3277// FastEmit functions for MipsISD::Multu.
3278
3279unsigned fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3280 if (RetVT.SimpleTy != MVT::Untyped)
3281 return 0;
3282 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3283 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3284 }
3285 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3286 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3287 }
3288 if ((Subtarget->hasDSP())) {
3289 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3290 }
3291 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3292 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu, RC: &Mips::ACC64RegClass, Op0, Op1);
3293 }
3294 return 0;
3295}
3296
3297unsigned fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3298 if (RetVT.SimpleTy != MVT::Untyped)
3299 return 0;
3300 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3301 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULTu, RC: &Mips::ACC128RegClass, Op0, Op1);
3302 }
3303 return 0;
3304}
3305
3306unsigned fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3307 switch (VT.SimpleTy) {
3308 case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op1);
3309 case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op1);
3310 default: return 0;
3311 }
3312}
3313
3314// FastEmit functions for MipsISD::PCKEV.
3315
3316unsigned fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3317 if (RetVT.SimpleTy != MVT::v16i8)
3318 return 0;
3319 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3320 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3321 }
3322 return 0;
3323}
3324
3325unsigned fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3326 if (RetVT.SimpleTy != MVT::v8i16)
3327 return 0;
3328 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3329 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3330 }
3331 return 0;
3332}
3333
3334unsigned fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3335 if (RetVT.SimpleTy != MVT::v4i32)
3336 return 0;
3337 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3338 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3339 }
3340 return 0;
3341}
3342
3343unsigned fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3344 if (RetVT.SimpleTy != MVT::v2i64)
3345 return 0;
3346 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3347 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3348 }
3349 return 0;
3350}
3351
3352unsigned fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3353 switch (VT.SimpleTy) {
3354 case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3355 case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3356 case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3357 case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3358 default: return 0;
3359 }
3360}
3361
3362// FastEmit functions for MipsISD::PCKOD.
3363
3364unsigned fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3365 if (RetVT.SimpleTy != MVT::v16i8)
3366 return 0;
3367 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3368 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3369 }
3370 return 0;
3371}
3372
3373unsigned fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3374 if (RetVT.SimpleTy != MVT::v8i16)
3375 return 0;
3376 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3377 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3378 }
3379 return 0;
3380}
3381
3382unsigned fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3383 if (RetVT.SimpleTy != MVT::v4i32)
3384 return 0;
3385 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3386 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3387 }
3388 return 0;
3389}
3390
3391unsigned fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3392 if (RetVT.SimpleTy != MVT::v2i64)
3393 return 0;
3394 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3395 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3396 }
3397 return 0;
3398}
3399
3400unsigned fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3401 switch (VT.SimpleTy) {
3402 case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3403 case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3404 case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3405 case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3406 default: return 0;
3407 }
3408}
3409
3410// FastEmit functions for MipsISD::VNOR.
3411
3412unsigned fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3413 if (RetVT.SimpleTy != MVT::v16i8)
3414 return 0;
3415 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3416 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
3417 }
3418 return 0;
3419}
3420
3421unsigned fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3422 if (RetVT.SimpleTy != MVT::v8i16)
3423 return 0;
3424 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3425 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
3426 }
3427 return 0;
3428}
3429
3430unsigned fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3431 if (RetVT.SimpleTy != MVT::v4i32)
3432 return 0;
3433 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3434 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
3435 }
3436 return 0;
3437}
3438
3439unsigned fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3440 if (RetVT.SimpleTy != MVT::v2i64)
3441 return 0;
3442 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3443 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
3444 }
3445 return 0;
3446}
3447
3448unsigned fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3449 switch (VT.SimpleTy) {
3450 case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op1);
3451 case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op1);
3452 case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op1);
3453 case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op1);
3454 default: return 0;
3455 }
3456}
3457
3458// Top-level FastEmit function.
3459
3460unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, unsigned Op1) override {
3461 switch (Opcode) {
3462 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
3463 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op1);
3464 case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op1);
3465 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
3466 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
3467 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
3468 case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3469 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3470 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
3471 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
3472 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
3473 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1);
3474 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1);
3475 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
3476 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
3477 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
3478 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
3479 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
3480 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
3481 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
3482 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
3483 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
3484 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
3485 case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op1);
3486 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
3487 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
3488 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
3489 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
3490 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
3491 case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op1);
3492 case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op1);
3493 case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op1);
3494 case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op1);
3495 case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op1);
3496 case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op1);
3497 case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op1);
3498 case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op1);
3499 case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op1);
3500 case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op1);
3501 case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op1);
3502 case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op1);
3503 case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op1);
3504 case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op1);
3505 case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op1);
3506 case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op1);
3507 default: return 0;
3508 }
3509}
3510
3511// FastEmit functions for MipsISD::ExtractElementF64.
3512
3513unsigned fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
3514 if (RetVT.SimpleTy != MVT::i32)
3515 return 0;
3516 if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3517 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64_64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3518 }
3519 if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3520 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3521 }
3522 return 0;
3523}
3524
3525unsigned fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3526 switch (VT.SimpleTy) {
3527 case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, imm1);
3528 default: return 0;
3529 }
3530}
3531
3532// FastEmit functions for MipsISD::SHLL_DSP.
3533
3534unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
3535 if (RetVT.SimpleTy != MVT::v4i8)
3536 return 0;
3537 if ((Subtarget->hasDSP())) {
3538 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3539 }
3540 return 0;
3541}
3542
3543unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
3544 if (RetVT.SimpleTy != MVT::v2i16)
3545 return 0;
3546 if ((Subtarget->hasDSP())) {
3547 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3548 }
3549 return 0;
3550}
3551
3552unsigned fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3553 switch (VT.SimpleTy) {
3554 case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3555 case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3556 default: return 0;
3557 }
3558}
3559
3560// FastEmit functions for MipsISD::SHRA_DSP.
3561
3562unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
3563 if (RetVT.SimpleTy != MVT::v4i8)
3564 return 0;
3565 if ((Subtarget->hasDSPR2())) {
3566 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3567 }
3568 return 0;
3569}
3570
3571unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
3572 if (RetVT.SimpleTy != MVT::v2i16)
3573 return 0;
3574 if ((Subtarget->hasDSP())) {
3575 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3576 }
3577 return 0;
3578}
3579
3580unsigned fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3581 switch (VT.SimpleTy) {
3582 case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3583 case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3584 default: return 0;
3585 }
3586}
3587
3588// FastEmit functions for MipsISD::SHRL_DSP.
3589
3590unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
3591 if (RetVT.SimpleTy != MVT::v4i8)
3592 return 0;
3593 if ((Subtarget->hasDSP())) {
3594 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3595 }
3596 return 0;
3597}
3598
3599unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
3600 if (RetVT.SimpleTy != MVT::v2i16)
3601 return 0;
3602 if ((Subtarget->hasDSPR2())) {
3603 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3604 }
3605 return 0;
3606}
3607
3608unsigned fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3609 switch (VT.SimpleTy) {
3610 case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3611 case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3612 default: return 0;
3613 }
3614}
3615
3616// Top-level FastEmit function.
3617
3618unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) override {
3619 if (VT == MVT::i32 && Predicate_immZExt5(Imm: imm1))
3620 if (unsigned Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, imm1))
3621 return Reg;
3622
3623 if (VT == MVT::i32 && Predicate_immZExt6(Imm: imm1))
3624 if (unsigned Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, imm1))
3625 return Reg;
3626
3627 if (VT == MVT::iPTR && Predicate_immZExt2Ptr(Imm: imm1))
3628 if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, imm1))
3629 return Reg;
3630
3631 if (VT == MVT::iPTR && Predicate_immZExt1Ptr(Imm: imm1))
3632 if (unsigned Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, imm1))
3633 return Reg;
3634
3635 if (VT == MVT::i32 && Predicate_immZExt4(Imm: imm1))
3636 if (unsigned Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, imm1))
3637 return Reg;
3638
3639 if (VT == MVT::i32 && Predicate_immSExtAddiur2(Imm: imm1))
3640 if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, imm1))
3641 return Reg;
3642
3643 if (VT == MVT::i32 && Predicate_immSExtAddius5(Imm: imm1))
3644 if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, imm1))
3645 return Reg;
3646
3647 if (VT == MVT::i32 && Predicate_immZExtAndi16(Imm: imm1))
3648 if (unsigned Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, imm1))
3649 return Reg;
3650
3651 if (VT == MVT::i32 && Predicate_immZExt2Shift(Imm: imm1))
3652 if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, imm1))
3653 return Reg;
3654
3655 switch (Opcode) {
3656 case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, imm1);
3657 case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, imm1);
3658 case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, imm1);
3659 case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, imm1);
3660 default: return 0;
3661 }
3662}
3663
3664// FastEmit functions for ISD::ROTR.
3665
3666unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, uint64_t imm1) {
3667 if (RetVT.SimpleTy != MVT::i32)
3668 return 0;
3669 if ((Subtarget->inMicroMipsMode())) {
3670 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3671 }
3672 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3673 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3674 }
3675 return 0;
3676}
3677
3678unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3679 switch (VT.SimpleTy) {
3680 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3681 default: return 0;
3682 }
3683}
3684
3685// FastEmit functions for ISD::SHL.
3686
3687unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, uint64_t imm1) {
3688 if (RetVT.SimpleTy != MVT::i32)
3689 return 0;
3690 if ((Subtarget->inMicroMipsMode())) {
3691 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3692 }
3693 if ((Subtarget->inMips16Mode())) {
3694 return fastEmitInst_ri(MachineInstOpcode: Mips::SllX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3695 }
3696 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3697 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3698 }
3699 return 0;
3700}
3701
3702unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3703 switch (VT.SimpleTy) {
3704 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3705 default: return 0;
3706 }
3707}
3708
3709// FastEmit functions for ISD::SRA.
3710
3711unsigned fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, uint64_t imm1) {
3712 if (RetVT.SimpleTy != MVT::i32)
3713 return 0;
3714 if ((Subtarget->inMicroMipsMode())) {
3715 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3716 }
3717 if ((Subtarget->inMips16Mode())) {
3718 return fastEmitInst_ri(MachineInstOpcode: Mips::SraX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3719 }
3720 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3721 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3722 }
3723 return 0;
3724}
3725
3726unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3727 switch (VT.SimpleTy) {
3728 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3729 default: return 0;
3730 }
3731}
3732
3733// FastEmit functions for ISD::SRL.
3734
3735unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, uint64_t imm1) {
3736 if (RetVT.SimpleTy != MVT::i32)
3737 return 0;
3738 if ((Subtarget->inMicroMipsMode())) {
3739 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3740 }
3741 if ((Subtarget->inMips16Mode())) {
3742 return fastEmitInst_ri(MachineInstOpcode: Mips::SrlX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3743 }
3744 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3745 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3746 }
3747 return 0;
3748}
3749
3750unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3751 switch (VT.SimpleTy) {
3752 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3753 default: return 0;
3754 }
3755}
3756
3757// Top-level FastEmit function.
3758
3759unsigned fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
3760 switch (Opcode) {
3761 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3762 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3763 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3764 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3765 default: return 0;
3766 }
3767}
3768
3769// FastEmit functions for ISD::ROTR.
3770
3771unsigned fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, uint64_t imm1) {
3772 if (RetVT.SimpleTy != MVT::i64)
3773 return 0;
3774 if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3775 return fastEmitInst_ri(MachineInstOpcode: Mips::DROTR, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3776 }
3777 return 0;
3778}
3779
3780unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3781 switch (VT.SimpleTy) {
3782 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3783 default: return 0;
3784 }
3785}
3786
3787// FastEmit functions for ISD::SHL.
3788
3789unsigned fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, uint64_t imm1) {
3790 if (RetVT.SimpleTy != MVT::i64)
3791 return 0;
3792 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3793 return fastEmitInst_ri(MachineInstOpcode: Mips::DSLL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3794 }
3795 return 0;
3796}
3797
3798unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3799 switch (VT.SimpleTy) {
3800 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3801 default: return 0;
3802 }
3803}
3804
3805// FastEmit functions for ISD::SRA.
3806
3807unsigned fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, uint64_t imm1) {
3808 if (RetVT.SimpleTy != MVT::i64)
3809 return 0;
3810 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3811 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRA, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3812 }
3813 return 0;
3814}
3815
3816unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3817 switch (VT.SimpleTy) {
3818 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3819 default: return 0;
3820 }
3821}
3822
3823// FastEmit functions for ISD::SRL.
3824
3825unsigned fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, uint64_t imm1) {
3826 if (RetVT.SimpleTy != MVT::i64)
3827 return 0;
3828 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3829 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3830 }
3831 return 0;
3832}
3833
3834unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3835 switch (VT.SimpleTy) {
3836 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3837 default: return 0;
3838 }
3839}
3840
3841// Top-level FastEmit function.
3842
3843unsigned fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
3844 switch (Opcode) {
3845 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3846 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3847 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3848 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3849 default: return 0;
3850 }
3851}
3852
3853// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3854
3855unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, unsigned Op0, uint64_t imm1) {
3856 if (RetVT.SimpleTy != MVT::f32)
3857 return 0;
3858 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3859 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FW_PSEUDO, RC: &Mips::FGR32RegClass, Op0, Imm: imm1);
3860 }
3861 return 0;
3862}
3863
3864unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3865 switch (VT.SimpleTy) {
3866 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, imm1);
3867 default: return 0;
3868 }
3869}
3870
3871// Top-level FastEmit function.
3872
3873unsigned fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
3874 switch (Opcode) {
3875 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, imm1);
3876 default: return 0;
3877 }
3878}
3879
3880// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3881
3882unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, unsigned Op0, uint64_t imm1) {
3883 if (RetVT.SimpleTy != MVT::f64)
3884 return 0;
3885 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3886 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FD_PSEUDO, RC: &Mips::FGR64RegClass, Op0, Imm: imm1);
3887 }
3888 return 0;
3889}
3890
3891unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3892 switch (VT.SimpleTy) {
3893 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, imm1);
3894 default: return 0;
3895 }
3896}
3897
3898// Top-level FastEmit function.
3899
3900unsigned fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
3901 switch (Opcode) {
3902 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, imm1);
3903 default: return 0;
3904 }
3905}
3906
3907// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3908
3909unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, unsigned Op0, uint64_t imm1) {
3910 if (RetVT.SimpleTy != MVT::i32)
3911 return 0;
3912 if ((Subtarget->hasMSA())) {
3913 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_S_W, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3914 }
3915 return 0;
3916}
3917
3918unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3919 switch (VT.SimpleTy) {
3920 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, imm1);
3921 default: return 0;
3922 }
3923}
3924
3925// Top-level FastEmit function.
3926
3927unsigned fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
3928 switch (Opcode) {
3929 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, imm1);
3930 default: return 0;
3931 }
3932}
3933
3934// FastEmit functions for ISD::ADD.
3935
3936unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, unsigned Op0, uint64_t imm1) {
3937 if (RetVT.SimpleTy != MVT::i32)
3938 return 0;
3939 if ((Subtarget->inMicroMipsMode())) {
3940 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUR2_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
3941 }
3942 return 0;
3943}
3944
3945unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3946 switch (VT.SimpleTy) {
3947 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, imm1);
3948 default: return 0;
3949 }
3950}
3951
3952// Top-level FastEmit function.
3953
3954unsigned fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
3955 switch (Opcode) {
3956 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, imm1);
3957 default: return 0;
3958 }
3959}
3960
3961// FastEmit functions for ISD::ADD.
3962
3963unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, unsigned Op0, uint64_t imm1) {
3964 if (RetVT.SimpleTy != MVT::i32)
3965 return 0;
3966 if ((Subtarget->inMicroMipsMode())) {
3967 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUS5_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3968 }
3969 return 0;
3970}
3971
3972unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
3973 switch (VT.SimpleTy) {
3974 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, imm1);
3975 default: return 0;
3976 }
3977}
3978
3979// Top-level FastEmit function.
3980
3981unsigned fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
3982 switch (Opcode) {
3983 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, imm1);
3984 default: return 0;
3985 }
3986}
3987
3988// FastEmit functions for ISD::AND.
3989
3990unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, unsigned Op0, uint64_t imm1) {
3991 if (RetVT.SimpleTy != MVT::i32)
3992 return 0;
3993 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
3994 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
3995 }
3996 if ((Subtarget->inMicroMipsMode())) {
3997 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
3998 }
3999 return 0;
4000}
4001
4002unsigned fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
4003 switch (VT.SimpleTy) {
4004 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, imm1);
4005 default: return 0;
4006 }
4007}
4008
4009// Top-level FastEmit function.
4010
4011unsigned fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
4012 switch (Opcode) {
4013 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, imm1);
4014 default: return 0;
4015 }
4016}
4017
4018// FastEmit functions for ISD::SHL.
4019
4020unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, uint64_t imm1) {
4021 if (RetVT.SimpleTy != MVT::i32)
4022 return 0;
4023 if ((Subtarget->inMicroMipsMode())) {
4024 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4025 }
4026 return 0;
4027}
4028
4029unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
4030 switch (VT.SimpleTy) {
4031 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4032 default: return 0;
4033 }
4034}
4035
4036// FastEmit functions for ISD::SRL.
4037
4038unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, uint64_t imm1) {
4039 if (RetVT.SimpleTy != MVT::i32)
4040 return 0;
4041 if ((Subtarget->inMicroMipsMode())) {
4042 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4043 }
4044 return 0;
4045}
4046
4047unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
4048 switch (VT.SimpleTy) {
4049 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4050 default: return 0;
4051 }
4052}
4053
4054// Top-level FastEmit function.
4055
4056unsigned fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
4057 switch (Opcode) {
4058 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4059 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4060 default: return 0;
4061 }
4062}
4063
4064// FastEmit functions for ISD::Constant.
4065
4066unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
4067 if (RetVT.SimpleTy != MVT::i32)
4068 return 0;
4069 if ((Subtarget->inMips16Mode())) {
4070 return fastEmitInst_i(MachineInstOpcode: Mips::LwConstant32, RC: &Mips::CPU16RegsRegClass, Imm: imm0);
4071 }
4072 return 0;
4073}
4074
4075unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
4076 switch (VT.SimpleTy) {
4077 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
4078 default: return 0;
4079 }
4080}
4081
4082// Top-level FastEmit function.
4083
4084unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
4085 switch (Opcode) {
4086 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
4087 default: return 0;
4088 }
4089}
4090
4091