1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the PPC target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_imm32SExt16(int64_t Imm) {
12
13 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
14 // sign extended field. Used by instructions like 'addi'.
15 return (int32_t)Imm == (short)Imm;
16
17}
18static bool Predicate_imm64SExt16(int64_t Imm) {
19
20 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
21 // sign extended field. Used by instructions like 'addi'.
22 return (int64_t)Imm == (short)Imm;
23
24}
25static bool Predicate_immSExt5NonZero(int64_t Imm) {
26 return Imm && isInt<5>(x: Imm);
27}
28static bool Predicate_i32immNonAllOneNonZero(int64_t Imm) {
29 return Imm && (Imm != -1);
30}
31
32
33// FastEmit functions for ISD::READCYCLECOUNTER.
34
35unsigned fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) {
36 if (RetVT.SimpleTy != MVT::i64)
37 return 0;
38 return fastEmitInst_(MachineInstOpcode: PPC::MFTB8, RC: &PPC::G8RCRegClass);
39}
40
41unsigned fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) {
42 switch (VT.SimpleTy) {
43 case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT);
44 default: return 0;
45 }
46}
47
48// FastEmit functions for PPCISD::GET_TPOINTER.
49
50unsigned fastEmit_PPCISD_GET_TPOINTER_MVT_i32_(MVT RetVT) {
51 if (RetVT.SimpleTy != MVT::i32)
52 return 0;
53 return fastEmitInst_(MachineInstOpcode: PPC::GETtlsTpointer32AIX, RC: &PPC::GPRCRegClass);
54}
55
56unsigned fastEmit_PPCISD_GET_TPOINTER_(MVT VT, MVT RetVT) {
57 switch (VT.SimpleTy) {
58 case MVT::i32: return fastEmit_PPCISD_GET_TPOINTER_MVT_i32_(RetVT);
59 default: return 0;
60 }
61}
62
63// FastEmit functions for PPCISD::MFFS.
64
65unsigned fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) {
66 if (RetVT.SimpleTy != MVT::f64)
67 return 0;
68 if ((Subtarget->hasFPU())) {
69 return fastEmitInst_(MachineInstOpcode: PPC::MFFS, RC: &PPC::F8RCRegClass);
70 }
71 return 0;
72}
73
74unsigned fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) {
75 switch (VT.SimpleTy) {
76 case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT);
77 default: return 0;
78 }
79}
80
81// FastEmit functions for PPCISD::PPC32_GOT.
82
83unsigned fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) {
84 if (RetVT.SimpleTy != MVT::i32)
85 return 0;
86 return fastEmitInst_(MachineInstOpcode: PPC::PPC32GOT, RC: &PPC::GPRCRegClass);
87}
88
89unsigned fastEmit_PPCISD_PPC32_GOT_(MVT VT, MVT RetVT) {
90 switch (VT.SimpleTy) {
91 case MVT::i32: return fastEmit_PPCISD_PPC32_GOT_MVT_i32_(RetVT);
92 default: return 0;
93 }
94}
95
96// Top-level FastEmit function.
97
98unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override {
99 switch (Opcode) {
100 case ISD::READCYCLECOUNTER: return fastEmit_ISD_READCYCLECOUNTER_(VT, RetVT);
101 case PPCISD::GET_TPOINTER: return fastEmit_PPCISD_GET_TPOINTER_(VT, RetVT);
102 case PPCISD::MFFS: return fastEmit_PPCISD_MFFS_(VT, RetVT);
103 case PPCISD::PPC32_GOT: return fastEmit_PPCISD_PPC32_GOT_(VT, RetVT);
104 default: return 0;
105 }
106}
107
108// FastEmit functions for ISD::ANY_EXTEND.
109
110unsigned fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(unsigned Op0) {
111 if ((Subtarget->isISA3_1())) {
112 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC, RC: &PPC::GPRCRegClass, Op0);
113 }
114 return 0;
115}
116
117unsigned fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(unsigned Op0) {
118 if ((Subtarget->isISA3_1())) {
119 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC8, RC: &PPC::G8RCRegClass, Op0);
120 }
121 return 0;
122}
123
124unsigned fastEmit_ISD_ANY_EXTEND_MVT_i1_r(MVT RetVT, unsigned Op0) {
125switch (RetVT.SimpleTy) {
126 case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(Op0);
127 case MVT::i64: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(Op0);
128 default: return 0;
129}
130}
131
132unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
133 switch (VT.SimpleTy) {
134 case MVT::i1: return fastEmit_ISD_ANY_EXTEND_MVT_i1_r(RetVT, Op0);
135 default: return 0;
136 }
137}
138
139// FastEmit functions for ISD::BITCAST.
140
141unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0) {
142 if (RetVT.SimpleTy != MVT::f64)
143 return 0;
144 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
145 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRD, RC: &PPC::VSFRCRegClass, Op0);
146 }
147 return 0;
148}
149
150unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0) {
151 if (RetVT.SimpleTy != MVT::i64)
152 return 0;
153 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
154 return fastEmitInst_r(MachineInstOpcode: PPC::MFVSRD, RC: &PPC::G8RCRegClass, Op0);
155 }
156 return 0;
157}
158
159unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0) {
160 switch (VT.SimpleTy) {
161 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
162 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
163 default: return 0;
164 }
165}
166
167// FastEmit functions for ISD::BSWAP.
168
169unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0) {
170 if (RetVT.SimpleTy != MVT::i32)
171 return 0;
172 if ((Subtarget->isISA3_1())) {
173 return fastEmitInst_r(MachineInstOpcode: PPC::BRW, RC: &PPC::GPRCRegClass, Op0);
174 }
175 return 0;
176}
177
178unsigned fastEmit_ISD_BSWAP_MVT_i64_r(MVT RetVT, unsigned Op0) {
179 if (RetVT.SimpleTy != MVT::i64)
180 return 0;
181 if ((Subtarget->isISA3_1())) {
182 return fastEmitInst_r(MachineInstOpcode: PPC::BRD, RC: &PPC::G8RCRegClass, Op0);
183 }
184 return 0;
185}
186
187unsigned fastEmit_ISD_BSWAP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
188 if (RetVT.SimpleTy != MVT::v4i32)
189 return 0;
190 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
191 return fastEmitInst_r(MachineInstOpcode: PPC::XXBRW, RC: &PPC::VSRCRegClass, Op0);
192 }
193 return 0;
194}
195
196unsigned fastEmit_ISD_BSWAP_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
197 if (RetVT.SimpleTy != MVT::v2i64)
198 return 0;
199 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
200 return fastEmitInst_r(MachineInstOpcode: PPC::XXBRD, RC: &PPC::VSRCRegClass, Op0);
201 }
202 return 0;
203}
204
205unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0) {
206 switch (VT.SimpleTy) {
207 case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0);
208 case MVT::i64: return fastEmit_ISD_BSWAP_MVT_i64_r(RetVT, Op0);
209 case MVT::v4i32: return fastEmit_ISD_BSWAP_MVT_v4i32_r(RetVT, Op0);
210 case MVT::v2i64: return fastEmit_ISD_BSWAP_MVT_v2i64_r(RetVT, Op0);
211 default: return 0;
212 }
213}
214
215// FastEmit functions for ISD::CTLZ.
216
217unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0) {
218 if (RetVT.SimpleTy != MVT::i32)
219 return 0;
220 return fastEmitInst_r(MachineInstOpcode: PPC::CNTLZW, RC: &PPC::GPRCRegClass, Op0);
221}
222
223unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0) {
224 if (RetVT.SimpleTy != MVT::i64)
225 return 0;
226 return fastEmitInst_r(MachineInstOpcode: PPC::CNTLZD, RC: &PPC::G8RCRegClass, Op0);
227}
228
229unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
230 if (RetVT.SimpleTy != MVT::v16i8)
231 return 0;
232 if ((Subtarget->hasP8Altivec())) {
233 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZB, RC: &PPC::VRRCRegClass, Op0);
234 }
235 return 0;
236}
237
238unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
239 if (RetVT.SimpleTy != MVT::v8i16)
240 return 0;
241 if ((Subtarget->hasP8Altivec())) {
242 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZH, RC: &PPC::VRRCRegClass, Op0);
243 }
244 return 0;
245}
246
247unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
248 if (RetVT.SimpleTy != MVT::v4i32)
249 return 0;
250 if ((Subtarget->hasP8Altivec())) {
251 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZW, RC: &PPC::VRRCRegClass, Op0);
252 }
253 return 0;
254}
255
256unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
257 if (RetVT.SimpleTy != MVT::v2i64)
258 return 0;
259 if ((Subtarget->hasP8Altivec())) {
260 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZD, RC: &PPC::VRRCRegClass, Op0);
261 }
262 return 0;
263}
264
265unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0) {
266 switch (VT.SimpleTy) {
267 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
268 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
269 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0);
270 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0);
271 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0);
272 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0);
273 default: return 0;
274 }
275}
276
277// FastEmit functions for ISD::CTPOP.
278
279unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0) {
280 if (RetVT.SimpleTy != MVT::i32)
281 return 0;
282 return fastEmitInst_r(MachineInstOpcode: PPC::POPCNTW, RC: &PPC::GPRCRegClass, Op0);
283}
284
285unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0) {
286 if (RetVT.SimpleTy != MVT::i64)
287 return 0;
288 return fastEmitInst_r(MachineInstOpcode: PPC::POPCNTD, RC: &PPC::G8RCRegClass, Op0);
289}
290
291unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
292 if (RetVT.SimpleTy != MVT::v16i8)
293 return 0;
294 if ((Subtarget->hasP8Altivec())) {
295 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTB, RC: &PPC::VRRCRegClass, Op0);
296 }
297 return 0;
298}
299
300unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
301 if (RetVT.SimpleTy != MVT::v8i16)
302 return 0;
303 if ((Subtarget->hasP8Altivec())) {
304 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTH, RC: &PPC::VRRCRegClass, Op0);
305 }
306 return 0;
307}
308
309unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
310 if (RetVT.SimpleTy != MVT::v4i32)
311 return 0;
312 if ((Subtarget->hasP8Altivec())) {
313 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTW, RC: &PPC::VRRCRegClass, Op0);
314 }
315 return 0;
316}
317
318unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
319 if (RetVT.SimpleTy != MVT::v2i64)
320 return 0;
321 if ((Subtarget->hasP8Altivec())) {
322 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTD, RC: &PPC::VRRCRegClass, Op0);
323 }
324 return 0;
325}
326
327unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0) {
328 switch (VT.SimpleTy) {
329 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
330 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
331 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
332 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0);
333 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0);
334 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0);
335 default: return 0;
336 }
337}
338
339// FastEmit functions for ISD::CTTZ.
340
341unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0) {
342 if (RetVT.SimpleTy != MVT::i32)
343 return 0;
344 if ((Subtarget->isISA3_0())) {
345 return fastEmitInst_r(MachineInstOpcode: PPC::CNTTZW, RC: &PPC::GPRCRegClass, Op0);
346 }
347 return 0;
348}
349
350unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0) {
351 if (RetVT.SimpleTy != MVT::i64)
352 return 0;
353 if ((Subtarget->isISA3_0())) {
354 return fastEmitInst_r(MachineInstOpcode: PPC::CNTTZD, RC: &PPC::G8RCRegClass, Op0);
355 }
356 return 0;
357}
358
359unsigned fastEmit_ISD_CTTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
360 if (RetVT.SimpleTy != MVT::v16i8)
361 return 0;
362 if ((Subtarget->hasP9Altivec())) {
363 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZB, RC: &PPC::VRRCRegClass, Op0);
364 }
365 return 0;
366}
367
368unsigned fastEmit_ISD_CTTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
369 if (RetVT.SimpleTy != MVT::v8i16)
370 return 0;
371 if ((Subtarget->hasP9Altivec())) {
372 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZH, RC: &PPC::VRRCRegClass, Op0);
373 }
374 return 0;
375}
376
377unsigned fastEmit_ISD_CTTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
378 if (RetVT.SimpleTy != MVT::v4i32)
379 return 0;
380 if ((Subtarget->hasP9Altivec())) {
381 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZW, RC: &PPC::VRRCRegClass, Op0);
382 }
383 return 0;
384}
385
386unsigned fastEmit_ISD_CTTZ_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
387 if (RetVT.SimpleTy != MVT::v2i64)
388 return 0;
389 if ((Subtarget->hasP9Altivec())) {
390 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZD, RC: &PPC::VRRCRegClass, Op0);
391 }
392 return 0;
393}
394
395unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0) {
396 switch (VT.SimpleTy) {
397 case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0);
398 case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0);
399 case MVT::v16i8: return fastEmit_ISD_CTTZ_MVT_v16i8_r(RetVT, Op0);
400 case MVT::v8i16: return fastEmit_ISD_CTTZ_MVT_v8i16_r(RetVT, Op0);
401 case MVT::v4i32: return fastEmit_ISD_CTTZ_MVT_v4i32_r(RetVT, Op0);
402 case MVT::v2i64: return fastEmit_ISD_CTTZ_MVT_v2i64_r(RetVT, Op0);
403 default: return 0;
404 }
405}
406
407// FastEmit functions for ISD::FABS.
408
409unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0) {
410 if (RetVT.SimpleTy != MVT::f32)
411 return 0;
412 if ((Subtarget->hasSPE())) {
413 return fastEmitInst_r(MachineInstOpcode: PPC::EFSABS, RC: &PPC::GPRCRegClass, Op0);
414 }
415 if ((Subtarget->hasFPU())) {
416 return fastEmitInst_r(MachineInstOpcode: PPC::FABSS, RC: &PPC::F4RCRegClass, Op0);
417 }
418 return 0;
419}
420
421unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0) {
422 if (RetVT.SimpleTy != MVT::f64)
423 return 0;
424 if ((Subtarget->hasVSX())) {
425 return fastEmitInst_r(MachineInstOpcode: PPC::XSABSDP, RC: &PPC::VSFRCRegClass, Op0);
426 }
427 if ((Subtarget->hasSPE())) {
428 return fastEmitInst_r(MachineInstOpcode: PPC::EFDABS, RC: &PPC::SPERCRegClass, Op0);
429 }
430 if ((Subtarget->hasFPU())) {
431 return fastEmitInst_r(MachineInstOpcode: PPC::FABSD, RC: &PPC::F8RCRegClass, Op0);
432 }
433 return 0;
434}
435
436unsigned fastEmit_ISD_FABS_MVT_f128_r(MVT RetVT, unsigned Op0) {
437 if (RetVT.SimpleTy != MVT::f128)
438 return 0;
439 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
440 return fastEmitInst_r(MachineInstOpcode: PPC::XSABSQP, RC: &PPC::VRRCRegClass, Op0);
441 }
442 return 0;
443}
444
445unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
446 if (RetVT.SimpleTy != MVT::v4f32)
447 return 0;
448 if ((Subtarget->hasVSX())) {
449 return fastEmitInst_r(MachineInstOpcode: PPC::XVABSSP, RC: &PPC::VSRCRegClass, Op0);
450 }
451 return 0;
452}
453
454unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
455 if (RetVT.SimpleTy != MVT::v2f64)
456 return 0;
457 if ((Subtarget->hasVSX())) {
458 return fastEmitInst_r(MachineInstOpcode: PPC::XVABSDP, RC: &PPC::VSRCRegClass, Op0);
459 }
460 return 0;
461}
462
463unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0) {
464 switch (VT.SimpleTy) {
465 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
466 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
467 case MVT::f128: return fastEmit_ISD_FABS_MVT_f128_r(RetVT, Op0);
468 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
469 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
470 default: return 0;
471 }
472}
473
474// FastEmit functions for ISD::FCEIL.
475
476unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0) {
477 if (RetVT.SimpleTy != MVT::f32)
478 return 0;
479 if ((Subtarget->hasFPU())) {
480 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPS, RC: &PPC::F4RCRegClass, Op0);
481 }
482 return 0;
483}
484
485unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0) {
486 if (RetVT.SimpleTy != MVT::f64)
487 return 0;
488 if ((Subtarget->hasVSX())) {
489 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIP, RC: &PPC::VSFRCRegClass, Op0);
490 }
491 if ((Subtarget->hasFPU())) {
492 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPD, RC: &PPC::F8RCRegClass, Op0);
493 }
494 return 0;
495}
496
497unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
498 if (RetVT.SimpleTy != MVT::v4f32)
499 return 0;
500 if ((Subtarget->hasVSX())) {
501 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIP, RC: &PPC::VSRCRegClass, Op0);
502 }
503 if ((Subtarget->hasAltivec())) {
504 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIP, RC: &PPC::VRRCRegClass, Op0);
505 }
506 return 0;
507}
508
509unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
510 if (RetVT.SimpleTy != MVT::v2f64)
511 return 0;
512 if ((Subtarget->hasVSX())) {
513 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIP, RC: &PPC::VSRCRegClass, Op0);
514 }
515 return 0;
516}
517
518unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0) {
519 switch (VT.SimpleTy) {
520 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0);
521 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0);
522 case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0);
523 case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0);
524 default: return 0;
525 }
526}
527
528// FastEmit functions for ISD::FFLOOR.
529
530unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0) {
531 if (RetVT.SimpleTy != MVT::f32)
532 return 0;
533 if ((Subtarget->hasFPU())) {
534 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMS, RC: &PPC::F4RCRegClass, Op0);
535 }
536 return 0;
537}
538
539unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0) {
540 if (RetVT.SimpleTy != MVT::f64)
541 return 0;
542 if ((Subtarget->hasVSX())) {
543 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIM, RC: &PPC::VSFRCRegClass, Op0);
544 }
545 if ((Subtarget->hasFPU())) {
546 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMD, RC: &PPC::F8RCRegClass, Op0);
547 }
548 return 0;
549}
550
551unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
552 if (RetVT.SimpleTy != MVT::v4f32)
553 return 0;
554 if ((Subtarget->hasVSX())) {
555 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIM, RC: &PPC::VSRCRegClass, Op0);
556 }
557 if ((Subtarget->hasAltivec())) {
558 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIM, RC: &PPC::VRRCRegClass, Op0);
559 }
560 return 0;
561}
562
563unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
564 if (RetVT.SimpleTy != MVT::v2f64)
565 return 0;
566 if ((Subtarget->hasVSX())) {
567 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIM, RC: &PPC::VSRCRegClass, Op0);
568 }
569 return 0;
570}
571
572unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0) {
573 switch (VT.SimpleTy) {
574 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0);
575 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0);
576 case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0);
577 case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0);
578 default: return 0;
579 }
580}
581
582// FastEmit functions for ISD::FNEARBYINT.
583
584unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
585 if (RetVT.SimpleTy != MVT::f64)
586 return 0;
587 if ((Subtarget->hasVSX())) {
588 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIC, RC: &PPC::VSFRCRegClass, Op0);
589 }
590 return 0;
591}
592
593unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
594 if (RetVT.SimpleTy != MVT::v4f32)
595 return 0;
596 if ((Subtarget->hasVSX())) {
597 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIC, RC: &PPC::VSRCRegClass, Op0);
598 }
599 if ((Subtarget->hasAltivec())) {
600 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIN, RC: &PPC::VRRCRegClass, Op0);
601 }
602 return 0;
603}
604
605unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
606 if (RetVT.SimpleTy != MVT::v2f64)
607 return 0;
608 if ((Subtarget->hasVSX())) {
609 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIC, RC: &PPC::VSRCRegClass, Op0);
610 }
611 return 0;
612}
613
614unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0) {
615 switch (VT.SimpleTy) {
616 case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0);
617 case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0);
618 case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0);
619 default: return 0;
620 }
621}
622
623// FastEmit functions for ISD::FNEG.
624
625unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0) {
626 if (RetVT.SimpleTy != MVT::f32)
627 return 0;
628 if ((Subtarget->hasSPE())) {
629 return fastEmitInst_r(MachineInstOpcode: PPC::EFSNEG, RC: &PPC::GPRCRegClass, Op0);
630 }
631 if ((Subtarget->hasFPU())) {
632 return fastEmitInst_r(MachineInstOpcode: PPC::FNEGS, RC: &PPC::F4RCRegClass, Op0);
633 }
634 return 0;
635}
636
637unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0) {
638 if (RetVT.SimpleTy != MVT::f64)
639 return 0;
640 if ((Subtarget->hasVSX())) {
641 return fastEmitInst_r(MachineInstOpcode: PPC::XSNEGDP, RC: &PPC::VSFRCRegClass, Op0);
642 }
643 if ((Subtarget->hasSPE())) {
644 return fastEmitInst_r(MachineInstOpcode: PPC::EFDNEG, RC: &PPC::SPERCRegClass, Op0);
645 }
646 if ((Subtarget->hasFPU())) {
647 return fastEmitInst_r(MachineInstOpcode: PPC::FNEGD, RC: &PPC::F8RCRegClass, Op0);
648 }
649 return 0;
650}
651
652unsigned fastEmit_ISD_FNEG_MVT_f128_r(MVT RetVT, unsigned Op0) {
653 if (RetVT.SimpleTy != MVT::f128)
654 return 0;
655 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
656 return fastEmitInst_r(MachineInstOpcode: PPC::XSNEGQP, RC: &PPC::VRRCRegClass, Op0);
657 }
658 return 0;
659}
660
661unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
662 if (RetVT.SimpleTy != MVT::v4f32)
663 return 0;
664 if ((Subtarget->hasVSX())) {
665 return fastEmitInst_r(MachineInstOpcode: PPC::XVNEGSP, RC: &PPC::VSRCRegClass, Op0);
666 }
667 return 0;
668}
669
670unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
671 if (RetVT.SimpleTy != MVT::v2f64)
672 return 0;
673 if ((Subtarget->hasVSX())) {
674 return fastEmitInst_r(MachineInstOpcode: PPC::XVNEGDP, RC: &PPC::VSRCRegClass, Op0);
675 }
676 return 0;
677}
678
679unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0) {
680 switch (VT.SimpleTy) {
681 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
682 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
683 case MVT::f128: return fastEmit_ISD_FNEG_MVT_f128_r(RetVT, Op0);
684 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0);
685 case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0);
686 default: return 0;
687 }
688}
689
690// FastEmit functions for ISD::FP_EXTEND.
691
692unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) {
693 if (RetVT.SimpleTy != MVT::f64)
694 return 0;
695 if ((Subtarget->hasSPE())) {
696 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFS, RC: &PPC::SPERCRegClass, Op0);
697 }
698 return 0;
699}
700
701unsigned fastEmit_ISD_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0) {
702 if (RetVT.SimpleTy != MVT::f128)
703 return 0;
704 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
705 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPQP, RC: &PPC::VRRCRegClass, Op0);
706 }
707 return 0;
708}
709
710unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
711 switch (VT.SimpleTy) {
712 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
713 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f64_r(RetVT, Op0);
714 default: return 0;
715 }
716}
717
718// FastEmit functions for ISD::FP_ROUND.
719
720unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) {
721 if (RetVT.SimpleTy != MVT::f32)
722 return 0;
723 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
724 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSP, RC: &PPC::VSSRCRegClass, Op0);
725 }
726 if ((Subtarget->hasSPE())) {
727 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFD, RC: &PPC::GPRCRegClass, Op0);
728 }
729 if ((Subtarget->hasFPU())) {
730 return fastEmitInst_r(MachineInstOpcode: PPC::FRSP, RC: &PPC::F4RCRegClass, Op0);
731 }
732 return 0;
733}
734
735unsigned fastEmit_ISD_FP_ROUND_MVT_f128_r(MVT RetVT, unsigned Op0) {
736 if (RetVT.SimpleTy != MVT::f64)
737 return 0;
738 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
739 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPDP, RC: &PPC::VFRCRegClass, Op0);
740 }
741 return 0;
742}
743
744unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) {
745 switch (VT.SimpleTy) {
746 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
747 case MVT::f128: return fastEmit_ISD_FP_ROUND_MVT_f128_r(RetVT, Op0);
748 default: return 0;
749 }
750}
751
752// FastEmit functions for ISD::FP_TO_SINT.
753
754unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) {
755 if (RetVT.SimpleTy != MVT::i32)
756 return 0;
757 if ((Subtarget->hasSPE())) {
758 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTSIZ, RC: &PPC::GPRCRegClass, Op0);
759 }
760 return 0;
761}
762
763unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
764 if (RetVT.SimpleTy != MVT::i32)
765 return 0;
766 if ((Subtarget->hasSPE())) {
767 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTSIZ, RC: &PPC::GPRCRegClass, Op0);
768 }
769 return 0;
770}
771
772unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
773 if (RetVT.SimpleTy != MVT::v4i32)
774 return 0;
775 if ((Subtarget->hasVSX())) {
776 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPSXWS, RC: &PPC::VSRCRegClass, Op0);
777 }
778 if ((Subtarget->hasAltivec())) {
779 return fastEmitInst_r(MachineInstOpcode: PPC::VCTSXS_0, RC: &PPC::VRRCRegClass, Op0);
780 }
781 return 0;
782}
783
784unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
785 if (RetVT.SimpleTy != MVT::v2i64)
786 return 0;
787 if ((Subtarget->hasVSX())) {
788 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPSXDS, RC: &PPC::VSRCRegClass, Op0);
789 }
790 return 0;
791}
792
793unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) {
794 switch (VT.SimpleTy) {
795 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
796 case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
797 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
798 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
799 default: return 0;
800 }
801}
802
803// FastEmit functions for ISD::FP_TO_UINT.
804
805unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) {
806 if (RetVT.SimpleTy != MVT::i32)
807 return 0;
808 if ((Subtarget->hasSPE())) {
809 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTUIZ, RC: &PPC::GPRCRegClass, Op0);
810 }
811 return 0;
812}
813
814unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
815 if (RetVT.SimpleTy != MVT::i32)
816 return 0;
817 if ((Subtarget->hasSPE())) {
818 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTUIZ, RC: &PPC::GPRCRegClass, Op0);
819 }
820 return 0;
821}
822
823unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
824 if (RetVT.SimpleTy != MVT::v4i32)
825 return 0;
826 if ((Subtarget->hasVSX())) {
827 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPUXWS, RC: &PPC::VSRCRegClass, Op0);
828 }
829 if ((Subtarget->hasAltivec())) {
830 return fastEmitInst_r(MachineInstOpcode: PPC::VCTUXS_0, RC: &PPC::VRRCRegClass, Op0);
831 }
832 return 0;
833}
834
835unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
836 if (RetVT.SimpleTy != MVT::v2i64)
837 return 0;
838 if ((Subtarget->hasVSX())) {
839 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPUXDS, RC: &PPC::VSRCRegClass, Op0);
840 }
841 return 0;
842}
843
844unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) {
845 switch (VT.SimpleTy) {
846 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
847 case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
848 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
849 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
850 default: return 0;
851 }
852}
853
854// FastEmit functions for ISD::FRINT.
855
856unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
857 if (RetVT.SimpleTy != MVT::f64)
858 return 0;
859 if ((Subtarget->hasVSX())) {
860 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIC, RC: &PPC::VSFRCRegClass, Op0);
861 }
862 return 0;
863}
864
865unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
866 if (RetVT.SimpleTy != MVT::v4f32)
867 return 0;
868 if ((Subtarget->hasVSX())) {
869 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIC, RC: &PPC::VSRCRegClass, Op0);
870 }
871 return 0;
872}
873
874unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
875 if (RetVT.SimpleTy != MVT::v2f64)
876 return 0;
877 if ((Subtarget->hasVSX())) {
878 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIC, RC: &PPC::VSRCRegClass, Op0);
879 }
880 return 0;
881}
882
883unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0) {
884 switch (VT.SimpleTy) {
885 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0);
886 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
887 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
888 default: return 0;
889 }
890}
891
892// FastEmit functions for ISD::FROUND.
893
894unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0) {
895 if (RetVT.SimpleTy != MVT::f32)
896 return 0;
897 if ((Subtarget->hasFPU())) {
898 return fastEmitInst_r(MachineInstOpcode: PPC::FRINS, RC: &PPC::F4RCRegClass, Op0);
899 }
900 return 0;
901}
902
903unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0) {
904 if (RetVT.SimpleTy != MVT::f64)
905 return 0;
906 if ((Subtarget->hasVSX())) {
907 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPI, RC: &PPC::VSFRCRegClass, Op0);
908 }
909 if ((Subtarget->hasFPU())) {
910 return fastEmitInst_r(MachineInstOpcode: PPC::FRIND, RC: &PPC::F8RCRegClass, Op0);
911 }
912 return 0;
913}
914
915unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
916 if (RetVT.SimpleTy != MVT::v4f32)
917 return 0;
918 if ((Subtarget->hasVSX())) {
919 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPI, RC: &PPC::VSRCRegClass, Op0);
920 }
921 return 0;
922}
923
924unsigned fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
925 if (RetVT.SimpleTy != MVT::v2f64)
926 return 0;
927 if ((Subtarget->hasVSX())) {
928 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPI, RC: &PPC::VSRCRegClass, Op0);
929 }
930 return 0;
931}
932
933unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0) {
934 switch (VT.SimpleTy) {
935 case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0);
936 case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0);
937 case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0);
938 case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0);
939 default: return 0;
940 }
941}
942
943// FastEmit functions for ISD::FSQRT.
944
945unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) {
946 if (RetVT.SimpleTy != MVT::f32)
947 return 0;
948 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
949 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTSP, RC: &PPC::VSSRCRegClass, Op0);
950 }
951 if ((Subtarget->hasFPU())) {
952 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRTS, RC: &PPC::F4RCRegClass, Op0);
953 }
954 return 0;
955}
956
957unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) {
958 if (RetVT.SimpleTy != MVT::f64)
959 return 0;
960 if ((Subtarget->hasVSX())) {
961 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTDP, RC: &PPC::VSFRCRegClass, Op0);
962 }
963 if ((Subtarget->hasFPU())) {
964 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRT, RC: &PPC::F8RCRegClass, Op0);
965 }
966 return 0;
967}
968
969unsigned fastEmit_ISD_FSQRT_MVT_f128_r(MVT RetVT, unsigned Op0) {
970 if (RetVT.SimpleTy != MVT::f128)
971 return 0;
972 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
973 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTQP, RC: &PPC::VRRCRegClass, Op0);
974 }
975 return 0;
976}
977
978unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
979 if (RetVT.SimpleTy != MVT::v4f32)
980 return 0;
981 if ((Subtarget->hasVSX())) {
982 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTSP, RC: &PPC::VSRCRegClass, Op0);
983 }
984 return 0;
985}
986
987unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
988 if (RetVT.SimpleTy != MVT::v2f64)
989 return 0;
990 if ((Subtarget->hasVSX())) {
991 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTDP, RC: &PPC::VSRCRegClass, Op0);
992 }
993 return 0;
994}
995
996unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) {
997 switch (VT.SimpleTy) {
998 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
999 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
1000 case MVT::f128: return fastEmit_ISD_FSQRT_MVT_f128_r(RetVT, Op0);
1001 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
1002 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
1003 default: return 0;
1004 }
1005}
1006
1007// FastEmit functions for ISD::FTRUNC.
1008
1009unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0) {
1010 if (RetVT.SimpleTy != MVT::f32)
1011 return 0;
1012 if ((Subtarget->hasFPU())) {
1013 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZS, RC: &PPC::F4RCRegClass, Op0);
1014 }
1015 return 0;
1016}
1017
1018unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0) {
1019 if (RetVT.SimpleTy != MVT::f64)
1020 return 0;
1021 if ((Subtarget->hasVSX())) {
1022 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIZ, RC: &PPC::VSFRCRegClass, Op0);
1023 }
1024 if ((Subtarget->hasFPU())) {
1025 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZD, RC: &PPC::F8RCRegClass, Op0);
1026 }
1027 return 0;
1028}
1029
1030unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
1031 if (RetVT.SimpleTy != MVT::v4f32)
1032 return 0;
1033 if ((Subtarget->hasVSX())) {
1034 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIZ, RC: &PPC::VSRCRegClass, Op0);
1035 }
1036 if ((Subtarget->hasAltivec())) {
1037 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIZ, RC: &PPC::VRRCRegClass, Op0);
1038 }
1039 return 0;
1040}
1041
1042unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1043 if (RetVT.SimpleTy != MVT::v2f64)
1044 return 0;
1045 if ((Subtarget->hasVSX())) {
1046 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIZ, RC: &PPC::VSRCRegClass, Op0);
1047 }
1048 return 0;
1049}
1050
1051unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0) {
1052 switch (VT.SimpleTy) {
1053 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0);
1054 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0);
1055 case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0);
1056 case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0);
1057 default: return 0;
1058 }
1059}
1060
1061// FastEmit functions for ISD::SCALAR_TO_VECTOR.
1062
1063unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0) {
1064 if (RetVT.SimpleTy != MVT::v4i32)
1065 return 0;
1066 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1067 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRWS, RC: &PPC::VSRCRegClass, Op0);
1068 }
1069 return 0;
1070}
1071
1072unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0) {
1073 if (RetVT.SimpleTy != MVT::v4f32)
1074 return 0;
1075 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) {
1076 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSPN, RC: &PPC::VSRCRegClass, Op0);
1077 }
1078 return 0;
1079}
1080
1081unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0) {
1082 switch (VT.SimpleTy) {
1083 case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0);
1084 case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0);
1085 default: return 0;
1086 }
1087}
1088
1089// FastEmit functions for ISD::SIGN_EXTEND.
1090
1091unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(unsigned Op0) {
1092 if ((Subtarget->isISA3_1())) {
1093 return fastEmitInst_r(MachineInstOpcode: PPC::SETNBC, RC: &PPC::GPRCRegClass, Op0);
1094 }
1095 return 0;
1096}
1097
1098unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(unsigned Op0) {
1099 if ((Subtarget->isISA3_1())) {
1100 return fastEmitInst_r(MachineInstOpcode: PPC::SETNBC8, RC: &PPC::G8RCRegClass, Op0);
1101 }
1102 return 0;
1103}
1104
1105unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(MVT RetVT, unsigned Op0) {
1106switch (RetVT.SimpleTy) {
1107 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(Op0);
1108 case MVT::i64: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(Op0);
1109 default: return 0;
1110}
1111}
1112
1113unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) {
1114 if (RetVT.SimpleTy != MVT::i64)
1115 return 0;
1116 return fastEmitInst_r(MachineInstOpcode: PPC::EXTSW_32_64, RC: &PPC::G8RCRegClass, Op0);
1117}
1118
1119unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
1120 switch (VT.SimpleTy) {
1121 case MVT::i1: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(RetVT, Op0);
1122 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
1123 default: return 0;
1124 }
1125}
1126
1127// FastEmit functions for ISD::SINT_TO_FP.
1128
1129unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) {
1130 if ((Subtarget->hasSPE())) {
1131 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFSI, RC: &PPC::GPRCRegClass, Op0);
1132 }
1133 return 0;
1134}
1135
1136unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) {
1137 if ((Subtarget->hasSPE())) {
1138 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFSI, RC: &PPC::SPERCRegClass, Op0);
1139 }
1140 return 0;
1141}
1142
1143unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) {
1144switch (RetVT.SimpleTy) {
1145 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1146 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1147 default: return 0;
1148}
1149}
1150
1151unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1152 if (RetVT.SimpleTy != MVT::v4f32)
1153 return 0;
1154 if ((Subtarget->hasVSX())) {
1155 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXWSP, RC: &PPC::VSRCRegClass, Op0);
1156 }
1157 if ((Subtarget->hasAltivec())) {
1158 return fastEmitInst_r(MachineInstOpcode: PPC::VCFSX_0, RC: &PPC::VRRCRegClass, Op0);
1159 }
1160 return 0;
1161}
1162
1163unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
1164 if (RetVT.SimpleTy != MVT::v2f64)
1165 return 0;
1166 if ((Subtarget->hasVSX())) {
1167 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXDDP, RC: &PPC::VSRCRegClass, Op0);
1168 }
1169 return 0;
1170}
1171
1172unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) {
1173 switch (VT.SimpleTy) {
1174 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
1175 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1176 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1177 default: return 0;
1178 }
1179}
1180
1181// FastEmit functions for ISD::STRICT_FCEIL.
1182
1183unsigned fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0) {
1184 if (RetVT.SimpleTy != MVT::f32)
1185 return 0;
1186 if ((Subtarget->hasFPU())) {
1187 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPS, RC: &PPC::F4RCRegClass, Op0);
1188 }
1189 return 0;
1190}
1191
1192unsigned fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0) {
1193 if (RetVT.SimpleTy != MVT::f64)
1194 return 0;
1195 if ((Subtarget->hasVSX())) {
1196 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIP, RC: &PPC::VSFRCRegClass, Op0);
1197 }
1198 if ((Subtarget->hasFPU())) {
1199 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPD, RC: &PPC::F8RCRegClass, Op0);
1200 }
1201 return 0;
1202}
1203
1204unsigned fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
1205 if (RetVT.SimpleTy != MVT::v4f32)
1206 return 0;
1207 if ((Subtarget->hasVSX())) {
1208 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIP, RC: &PPC::VSRCRegClass, Op0);
1209 }
1210 return 0;
1211}
1212
1213unsigned fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1214 if (RetVT.SimpleTy != MVT::v2f64)
1215 return 0;
1216 if ((Subtarget->hasVSX())) {
1217 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIP, RC: &PPC::VSRCRegClass, Op0);
1218 }
1219 return 0;
1220}
1221
1222unsigned fastEmit_ISD_STRICT_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0) {
1223 switch (VT.SimpleTy) {
1224 case MVT::f32: return fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(RetVT, Op0);
1225 case MVT::f64: return fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(RetVT, Op0);
1226 case MVT::v4f32: return fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(RetVT, Op0);
1227 case MVT::v2f64: return fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(RetVT, Op0);
1228 default: return 0;
1229 }
1230}
1231
1232// FastEmit functions for ISD::STRICT_FFLOOR.
1233
1234unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0) {
1235 if (RetVT.SimpleTy != MVT::f32)
1236 return 0;
1237 if ((Subtarget->hasFPU())) {
1238 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMS, RC: &PPC::F4RCRegClass, Op0);
1239 }
1240 return 0;
1241}
1242
1243unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0) {
1244 if (RetVT.SimpleTy != MVT::f64)
1245 return 0;
1246 if ((Subtarget->hasVSX())) {
1247 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIM, RC: &PPC::VSFRCRegClass, Op0);
1248 }
1249 if ((Subtarget->hasFPU())) {
1250 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMD, RC: &PPC::F8RCRegClass, Op0);
1251 }
1252 return 0;
1253}
1254
1255unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
1256 if (RetVT.SimpleTy != MVT::v4f32)
1257 return 0;
1258 if ((Subtarget->hasVSX())) {
1259 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIM, RC: &PPC::VSRCRegClass, Op0);
1260 }
1261 return 0;
1262}
1263
1264unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1265 if (RetVT.SimpleTy != MVT::v2f64)
1266 return 0;
1267 if ((Subtarget->hasVSX())) {
1268 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIM, RC: &PPC::VSRCRegClass, Op0);
1269 }
1270 return 0;
1271}
1272
1273unsigned fastEmit_ISD_STRICT_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0) {
1274 switch (VT.SimpleTy) {
1275 case MVT::f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(RetVT, Op0);
1276 case MVT::f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(RetVT, Op0);
1277 case MVT::v4f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(RetVT, Op0);
1278 case MVT::v2f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(RetVT, Op0);
1279 default: return 0;
1280 }
1281}
1282
1283// FastEmit functions for ISD::STRICT_FP_EXTEND.
1284
1285unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) {
1286 if (RetVT.SimpleTy != MVT::f64)
1287 return 0;
1288 if ((Subtarget->hasSPE())) {
1289 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFS, RC: &PPC::SPERCRegClass, Op0);
1290 }
1291 return 0;
1292}
1293
1294unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0) {
1295 if (RetVT.SimpleTy != MVT::f128)
1296 return 0;
1297 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1298 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPQP, RC: &PPC::VRRCRegClass, Op0);
1299 }
1300 return 0;
1301}
1302
1303unsigned fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
1304 switch (VT.SimpleTy) {
1305 case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0);
1306 case MVT::f64: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(RetVT, Op0);
1307 default: return 0;
1308 }
1309}
1310
1311// FastEmit functions for ISD::STRICT_FP_ROUND.
1312
1313unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) {
1314 if (RetVT.SimpleTy != MVT::f32)
1315 return 0;
1316 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1317 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSP, RC: &PPC::VSSRCRegClass, Op0);
1318 }
1319 if ((Subtarget->hasSPE())) {
1320 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFD, RC: &PPC::GPRCRegClass, Op0);
1321 }
1322 if ((Subtarget->hasFPU())) {
1323 return fastEmitInst_r(MachineInstOpcode: PPC::FRSP, RC: &PPC::F4RCRegClass, Op0);
1324 }
1325 return 0;
1326}
1327
1328unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(MVT RetVT, unsigned Op0) {
1329 if (RetVT.SimpleTy != MVT::f64)
1330 return 0;
1331 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1332 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPDP, RC: &PPC::VFRCRegClass, Op0);
1333 }
1334 return 0;
1335}
1336
1337unsigned fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) {
1338 switch (VT.SimpleTy) {
1339 case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0);
1340 case MVT::f128: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(RetVT, Op0);
1341 default: return 0;
1342 }
1343}
1344
1345// FastEmit functions for ISD::STRICT_FP_TO_SINT.
1346
1347unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) {
1348 if (RetVT.SimpleTy != MVT::i32)
1349 return 0;
1350 if ((Subtarget->hasSPE())) {
1351 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTSIZ, RC: &PPC::GPRCRegClass, Op0);
1352 }
1353 return 0;
1354}
1355
1356unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
1357 if (RetVT.SimpleTy != MVT::i32)
1358 return 0;
1359 if ((Subtarget->hasSPE())) {
1360 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTSIZ, RC: &PPC::GPRCRegClass, Op0);
1361 }
1362 return 0;
1363}
1364
1365unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
1366 if (RetVT.SimpleTy != MVT::v4i32)
1367 return 0;
1368 if ((Subtarget->hasVSX())) {
1369 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPSXWS, RC: &PPC::VSRCRegClass, Op0);
1370 }
1371 return 0;
1372}
1373
1374unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1375 if (RetVT.SimpleTy != MVT::v2i64)
1376 return 0;
1377 if ((Subtarget->hasVSX())) {
1378 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPSXDS, RC: &PPC::VSRCRegClass, Op0);
1379 }
1380 return 0;
1381}
1382
1383unsigned fastEmit_ISD_STRICT_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) {
1384 switch (VT.SimpleTy) {
1385 case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
1386 case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
1387 case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
1388 case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
1389 default: return 0;
1390 }
1391}
1392
1393// FastEmit functions for ISD::STRICT_FP_TO_UINT.
1394
1395unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) {
1396 if (RetVT.SimpleTy != MVT::i32)
1397 return 0;
1398 if ((Subtarget->hasSPE())) {
1399 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTUIZ, RC: &PPC::GPRCRegClass, Op0);
1400 }
1401 return 0;
1402}
1403
1404unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
1405 if (RetVT.SimpleTy != MVT::i32)
1406 return 0;
1407 if ((Subtarget->hasSPE())) {
1408 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTUIZ, RC: &PPC::GPRCRegClass, Op0);
1409 }
1410 return 0;
1411}
1412
1413unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
1414 if (RetVT.SimpleTy != MVT::v4i32)
1415 return 0;
1416 if ((Subtarget->hasVSX())) {
1417 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPUXWS, RC: &PPC::VSRCRegClass, Op0);
1418 }
1419 return 0;
1420}
1421
1422unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1423 if (RetVT.SimpleTy != MVT::v2i64)
1424 return 0;
1425 if ((Subtarget->hasVSX())) {
1426 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPUXDS, RC: &PPC::VSRCRegClass, Op0);
1427 }
1428 return 0;
1429}
1430
1431unsigned fastEmit_ISD_STRICT_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) {
1432 switch (VT.SimpleTy) {
1433 case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
1434 case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
1435 case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
1436 case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
1437 default: return 0;
1438 }
1439}
1440
1441// FastEmit functions for ISD::STRICT_FRINT.
1442
1443unsigned fastEmit_ISD_STRICT_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
1444 if (RetVT.SimpleTy != MVT::f64)
1445 return 0;
1446 if ((Subtarget->hasVSX())) {
1447 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIC, RC: &PPC::VSFRCRegClass, Op0);
1448 }
1449 return 0;
1450}
1451
1452unsigned fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
1453 if (RetVT.SimpleTy != MVT::v4f32)
1454 return 0;
1455 if ((Subtarget->hasVSX())) {
1456 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIC, RC: &PPC::VSRCRegClass, Op0);
1457 }
1458 return 0;
1459}
1460
1461unsigned fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1462 if (RetVT.SimpleTy != MVT::v2f64)
1463 return 0;
1464 if ((Subtarget->hasVSX())) {
1465 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIC, RC: &PPC::VSRCRegClass, Op0);
1466 }
1467 return 0;
1468}
1469
1470unsigned fastEmit_ISD_STRICT_FRINT_r(MVT VT, MVT RetVT, unsigned Op0) {
1471 switch (VT.SimpleTy) {
1472 case MVT::f64: return fastEmit_ISD_STRICT_FRINT_MVT_f64_r(RetVT, Op0);
1473 case MVT::v4f32: return fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(RetVT, Op0);
1474 case MVT::v2f64: return fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(RetVT, Op0);
1475 default: return 0;
1476 }
1477}
1478
1479// FastEmit functions for ISD::STRICT_FROUND.
1480
1481unsigned fastEmit_ISD_STRICT_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0) {
1482 if (RetVT.SimpleTy != MVT::f32)
1483 return 0;
1484 if ((Subtarget->hasFPU())) {
1485 return fastEmitInst_r(MachineInstOpcode: PPC::FRINS, RC: &PPC::F4RCRegClass, Op0);
1486 }
1487 return 0;
1488}
1489
1490unsigned fastEmit_ISD_STRICT_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0) {
1491 if (RetVT.SimpleTy != MVT::f64)
1492 return 0;
1493 if ((Subtarget->hasVSX())) {
1494 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPI, RC: &PPC::VSFRCRegClass, Op0);
1495 }
1496 if ((Subtarget->hasFPU())) {
1497 return fastEmitInst_r(MachineInstOpcode: PPC::FRIND, RC: &PPC::F8RCRegClass, Op0);
1498 }
1499 return 0;
1500}
1501
1502unsigned fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
1503 if (RetVT.SimpleTy != MVT::v4f32)
1504 return 0;
1505 if ((Subtarget->hasVSX())) {
1506 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPI, RC: &PPC::VSRCRegClass, Op0);
1507 }
1508 return 0;
1509}
1510
1511unsigned fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1512 if (RetVT.SimpleTy != MVT::v2f64)
1513 return 0;
1514 if ((Subtarget->hasVSX())) {
1515 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPI, RC: &PPC::VSRCRegClass, Op0);
1516 }
1517 return 0;
1518}
1519
1520unsigned fastEmit_ISD_STRICT_FROUND_r(MVT VT, MVT RetVT, unsigned Op0) {
1521 switch (VT.SimpleTy) {
1522 case MVT::f32: return fastEmit_ISD_STRICT_FROUND_MVT_f32_r(RetVT, Op0);
1523 case MVT::f64: return fastEmit_ISD_STRICT_FROUND_MVT_f64_r(RetVT, Op0);
1524 case MVT::v4f32: return fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(RetVT, Op0);
1525 case MVT::v2f64: return fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(RetVT, Op0);
1526 default: return 0;
1527 }
1528}
1529
1530// FastEmit functions for ISD::STRICT_FSQRT.
1531
1532unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) {
1533 if (RetVT.SimpleTy != MVT::f32)
1534 return 0;
1535 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1536 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTSP, RC: &PPC::VSSRCRegClass, Op0);
1537 }
1538 if ((Subtarget->hasFPU())) {
1539 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRTS, RC: &PPC::F4RCRegClass, Op0);
1540 }
1541 return 0;
1542}
1543
1544unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) {
1545 if (RetVT.SimpleTy != MVT::f64)
1546 return 0;
1547 if ((Subtarget->hasVSX())) {
1548 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTDP, RC: &PPC::VSFRCRegClass, Op0);
1549 }
1550 if ((Subtarget->hasFPU())) {
1551 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRT, RC: &PPC::F8RCRegClass, Op0);
1552 }
1553 return 0;
1554}
1555
1556unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(MVT RetVT, unsigned Op0) {
1557 if (RetVT.SimpleTy != MVT::f128)
1558 return 0;
1559 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1560 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTQP, RC: &PPC::VRRCRegClass, Op0);
1561 }
1562 return 0;
1563}
1564
1565unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
1566 if (RetVT.SimpleTy != MVT::v4f32)
1567 return 0;
1568 if ((Subtarget->hasVSX())) {
1569 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTSP, RC: &PPC::VSRCRegClass, Op0);
1570 }
1571 return 0;
1572}
1573
1574unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1575 if (RetVT.SimpleTy != MVT::v2f64)
1576 return 0;
1577 if ((Subtarget->hasVSX())) {
1578 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTDP, RC: &PPC::VSRCRegClass, Op0);
1579 }
1580 return 0;
1581}
1582
1583unsigned fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) {
1584 switch (VT.SimpleTy) {
1585 case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0);
1586 case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0);
1587 case MVT::f128: return fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(RetVT, Op0);
1588 case MVT::v4f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(RetVT, Op0);
1589 case MVT::v2f64: return fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(RetVT, Op0);
1590 default: return 0;
1591 }
1592}
1593
1594// FastEmit functions for ISD::STRICT_FTRUNC.
1595
1596unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0) {
1597 if (RetVT.SimpleTy != MVT::f32)
1598 return 0;
1599 if ((Subtarget->hasFPU())) {
1600 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZS, RC: &PPC::F4RCRegClass, Op0);
1601 }
1602 return 0;
1603}
1604
1605unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0) {
1606 if (RetVT.SimpleTy != MVT::f64)
1607 return 0;
1608 if ((Subtarget->hasVSX())) {
1609 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIZ, RC: &PPC::VSFRCRegClass, Op0);
1610 }
1611 if ((Subtarget->hasFPU())) {
1612 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZD, RC: &PPC::F8RCRegClass, Op0);
1613 }
1614 return 0;
1615}
1616
1617unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
1618 if (RetVT.SimpleTy != MVT::v4f32)
1619 return 0;
1620 if ((Subtarget->hasVSX())) {
1621 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIZ, RC: &PPC::VSRCRegClass, Op0);
1622 }
1623 return 0;
1624}
1625
1626unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1627 if (RetVT.SimpleTy != MVT::v2f64)
1628 return 0;
1629 if ((Subtarget->hasVSX())) {
1630 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIZ, RC: &PPC::VSRCRegClass, Op0);
1631 }
1632 return 0;
1633}
1634
1635unsigned fastEmit_ISD_STRICT_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0) {
1636 switch (VT.SimpleTy) {
1637 case MVT::f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(RetVT, Op0);
1638 case MVT::f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(RetVT, Op0);
1639 case MVT::v4f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(RetVT, Op0);
1640 case MVT::v2f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(RetVT, Op0);
1641 default: return 0;
1642 }
1643}
1644
1645// FastEmit functions for ISD::STRICT_SINT_TO_FP.
1646
1647unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) {
1648 if ((Subtarget->hasSPE())) {
1649 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFSI, RC: &PPC::GPRCRegClass, Op0);
1650 }
1651 return 0;
1652}
1653
1654unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) {
1655 if ((Subtarget->hasSPE())) {
1656 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFSI, RC: &PPC::SPERCRegClass, Op0);
1657 }
1658 return 0;
1659}
1660
1661unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) {
1662switch (RetVT.SimpleTy) {
1663 case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1664 case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1665 default: return 0;
1666}
1667}
1668
1669unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1670 if (RetVT.SimpleTy != MVT::v4f32)
1671 return 0;
1672 if ((Subtarget->hasVSX())) {
1673 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXWSP, RC: &PPC::VSRCRegClass, Op0);
1674 }
1675 return 0;
1676}
1677
1678unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
1679 if (RetVT.SimpleTy != MVT::v2f64)
1680 return 0;
1681 if ((Subtarget->hasVSX())) {
1682 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXDDP, RC: &PPC::VSRCRegClass, Op0);
1683 }
1684 return 0;
1685}
1686
1687unsigned fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) {
1688 switch (VT.SimpleTy) {
1689 case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
1690 case MVT::v4i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1691 case MVT::v2i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1692 default: return 0;
1693 }
1694}
1695
1696// FastEmit functions for ISD::STRICT_UINT_TO_FP.
1697
1698unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) {
1699 if ((Subtarget->hasSPE())) {
1700 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFUI, RC: &PPC::GPRCRegClass, Op0);
1701 }
1702 return 0;
1703}
1704
1705unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) {
1706 if ((Subtarget->hasSPE())) {
1707 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFUI, RC: &PPC::SPERCRegClass, Op0);
1708 }
1709 return 0;
1710}
1711
1712unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) {
1713switch (RetVT.SimpleTy) {
1714 case MVT::f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1715 case MVT::f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1716 default: return 0;
1717}
1718}
1719
1720unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1721 if (RetVT.SimpleTy != MVT::v4f32)
1722 return 0;
1723 if ((Subtarget->hasVSX())) {
1724 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXWSP, RC: &PPC::VSRCRegClass, Op0);
1725 }
1726 return 0;
1727}
1728
1729unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
1730 if (RetVT.SimpleTy != MVT::v2f64)
1731 return 0;
1732 if ((Subtarget->hasVSX())) {
1733 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXDDP, RC: &PPC::VSRCRegClass, Op0);
1734 }
1735 return 0;
1736}
1737
1738unsigned fastEmit_ISD_STRICT_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) {
1739 switch (VT.SimpleTy) {
1740 case MVT::i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1741 case MVT::v4i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1742 case MVT::v2i64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1743 default: return 0;
1744 }
1745}
1746
1747// FastEmit functions for ISD::TRUNCATE.
1748
1749unsigned fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, unsigned Op0) {
1750 if (RetVT.SimpleTy != MVT::i1)
1751 return 0;
1752 return fastEmitInst_r(MachineInstOpcode: PPC::ANDI_rec_1_GT_BIT, RC: &PPC::CRBITRCRegClass, Op0);
1753}
1754
1755unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0) {
1756 if (RetVT.SimpleTy != MVT::i1)
1757 return 0;
1758 return fastEmitInst_r(MachineInstOpcode: PPC::ANDI_rec_1_GT_BIT8, RC: &PPC::CRBITRCRegClass, Op0);
1759}
1760
1761unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0) {
1762 switch (VT.SimpleTy) {
1763 case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0);
1764 case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0);
1765 default: return 0;
1766 }
1767}
1768
1769// FastEmit functions for ISD::UINT_TO_FP.
1770
1771unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) {
1772 if ((Subtarget->hasSPE())) {
1773 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFUI, RC: &PPC::GPRCRegClass, Op0);
1774 }
1775 return 0;
1776}
1777
1778unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) {
1779 if ((Subtarget->hasSPE())) {
1780 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFUI, RC: &PPC::SPERCRegClass, Op0);
1781 }
1782 return 0;
1783}
1784
1785unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) {
1786switch (RetVT.SimpleTy) {
1787 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1788 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1789 default: return 0;
1790}
1791}
1792
1793unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1794 if (RetVT.SimpleTy != MVT::v4f32)
1795 return 0;
1796 if ((Subtarget->hasVSX())) {
1797 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXWSP, RC: &PPC::VSRCRegClass, Op0);
1798 }
1799 if ((Subtarget->hasAltivec())) {
1800 return fastEmitInst_r(MachineInstOpcode: PPC::VCFUX_0, RC: &PPC::VRRCRegClass, Op0);
1801 }
1802 return 0;
1803}
1804
1805unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
1806 if (RetVT.SimpleTy != MVT::v2f64)
1807 return 0;
1808 if ((Subtarget->hasVSX())) {
1809 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXDDP, RC: &PPC::VSRCRegClass, Op0);
1810 }
1811 return 0;
1812}
1813
1814unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) {
1815 switch (VT.SimpleTy) {
1816 case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1817 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1818 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1819 default: return 0;
1820 }
1821}
1822
1823// FastEmit functions for ISD::ZERO_EXTEND.
1824
1825unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(unsigned Op0) {
1826 if ((Subtarget->isISA3_1())) {
1827 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC, RC: &PPC::GPRCRegClass, Op0);
1828 }
1829 return 0;
1830}
1831
1832unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(unsigned Op0) {
1833 if ((Subtarget->isISA3_1())) {
1834 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC8, RC: &PPC::G8RCRegClass, Op0);
1835 }
1836 return 0;
1837}
1838
1839unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(MVT RetVT, unsigned Op0) {
1840switch (RetVT.SimpleTy) {
1841 case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(Op0);
1842 case MVT::i64: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(Op0);
1843 default: return 0;
1844}
1845}
1846
1847unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
1848 switch (VT.SimpleTy) {
1849 case MVT::i1: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(RetVT, Op0);
1850 default: return 0;
1851 }
1852}
1853
1854// FastEmit functions for PPCISD::FCFID.
1855
1856unsigned fastEmit_PPCISD_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0) {
1857 if (RetVT.SimpleTy != MVT::f64)
1858 return 0;
1859 if ((Subtarget->hasVSX())) {
1860 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDDP, RC: &PPC::VSFRCRegClass, Op0);
1861 }
1862 return fastEmitInst_r(MachineInstOpcode: PPC::FCFID, RC: &PPC::F8RCRegClass, Op0);
1863}
1864
1865unsigned fastEmit_PPCISD_FCFID_r(MVT VT, MVT RetVT, unsigned Op0) {
1866 switch (VT.SimpleTy) {
1867 case MVT::f64: return fastEmit_PPCISD_FCFID_MVT_f64_r(RetVT, Op0);
1868 default: return 0;
1869 }
1870}
1871
1872// FastEmit functions for PPCISD::FCFIDS.
1873
1874unsigned fastEmit_PPCISD_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0) {
1875 if (RetVT.SimpleTy != MVT::f32)
1876 return 0;
1877 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1878 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDSP, RC: &PPC::VSSRCRegClass, Op0);
1879 }
1880 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDS, RC: &PPC::F4RCRegClass, Op0);
1881}
1882
1883unsigned fastEmit_PPCISD_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0) {
1884 switch (VT.SimpleTy) {
1885 case MVT::f64: return fastEmit_PPCISD_FCFIDS_MVT_f64_r(RetVT, Op0);
1886 default: return 0;
1887 }
1888}
1889
1890// FastEmit functions for PPCISD::FCFIDU.
1891
1892unsigned fastEmit_PPCISD_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0) {
1893 if (RetVT.SimpleTy != MVT::f64)
1894 return 0;
1895 if ((Subtarget->hasVSX())) {
1896 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDDP, RC: &PPC::VSFRCRegClass, Op0);
1897 }
1898 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDU, RC: &PPC::F8RCRegClass, Op0);
1899}
1900
1901unsigned fastEmit_PPCISD_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0) {
1902 switch (VT.SimpleTy) {
1903 case MVT::f64: return fastEmit_PPCISD_FCFIDU_MVT_f64_r(RetVT, Op0);
1904 default: return 0;
1905 }
1906}
1907
1908// FastEmit functions for PPCISD::FCFIDUS.
1909
1910unsigned fastEmit_PPCISD_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0) {
1911 if (RetVT.SimpleTy != MVT::f32)
1912 return 0;
1913 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1914 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDSP, RC: &PPC::VSSRCRegClass, Op0);
1915 }
1916 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDUS, RC: &PPC::F4RCRegClass, Op0);
1917}
1918
1919unsigned fastEmit_PPCISD_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0) {
1920 switch (VT.SimpleTy) {
1921 case MVT::f64: return fastEmit_PPCISD_FCFIDUS_MVT_f64_r(RetVT, Op0);
1922 default: return 0;
1923 }
1924}
1925
1926// FastEmit functions for PPCISD::FCTIDUZ.
1927
1928unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0) {
1929 if (RetVT.SimpleTy != MVT::f32)
1930 return 0;
1931 if ((Subtarget->hasVSX())) {
1932 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDSs, RC: &PPC::VSSRCRegClass, Op0);
1933 }
1934 return 0;
1935}
1936
1937unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0) {
1938 if (RetVT.SimpleTy != MVT::f64)
1939 return 0;
1940 if ((Subtarget->hasVSX())) {
1941 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDS, RC: &PPC::VSFRCRegClass, Op0);
1942 }
1943 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDUZ, RC: &PPC::F8RCRegClass, Op0);
1944}
1945
1946unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f128_r(MVT RetVT, unsigned Op0) {
1947 if (RetVT.SimpleTy != MVT::f128)
1948 return 0;
1949 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1950 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUDZ, RC: &PPC::VRRCRegClass, Op0);
1951 }
1952 return 0;
1953}
1954
1955unsigned fastEmit_PPCISD_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0) {
1956 switch (VT.SimpleTy) {
1957 case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0);
1958 case MVT::f64: return fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(RetVT, Op0);
1959 case MVT::f128: return fastEmit_PPCISD_FCTIDUZ_MVT_f128_r(RetVT, Op0);
1960 default: return 0;
1961 }
1962}
1963
1964// FastEmit functions for PPCISD::FCTIDZ.
1965
1966unsigned fastEmit_PPCISD_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0) {
1967 if (RetVT.SimpleTy != MVT::f32)
1968 return 0;
1969 if ((Subtarget->hasVSX())) {
1970 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDSs, RC: &PPC::VSSRCRegClass, Op0);
1971 }
1972 return 0;
1973}
1974
1975unsigned fastEmit_PPCISD_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0) {
1976 if (RetVT.SimpleTy != MVT::f64)
1977 return 0;
1978 if ((Subtarget->hasVSX())) {
1979 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDS, RC: &PPC::VSFRCRegClass, Op0);
1980 }
1981 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDZ, RC: &PPC::F8RCRegClass, Op0);
1982}
1983
1984unsigned fastEmit_PPCISD_FCTIDZ_MVT_f128_r(MVT RetVT, unsigned Op0) {
1985 if (RetVT.SimpleTy != MVT::f128)
1986 return 0;
1987 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1988 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSDZ, RC: &PPC::VRRCRegClass, Op0);
1989 }
1990 return 0;
1991}
1992
1993unsigned fastEmit_PPCISD_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0) {
1994 switch (VT.SimpleTy) {
1995 case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0);
1996 case MVT::f64: return fastEmit_PPCISD_FCTIDZ_MVT_f64_r(RetVT, Op0);
1997 case MVT::f128: return fastEmit_PPCISD_FCTIDZ_MVT_f128_r(RetVT, Op0);
1998 default: return 0;
1999 }
2000}
2001
2002// FastEmit functions for PPCISD::FCTIWUZ.
2003
2004unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0) {
2005 if (RetVT.SimpleTy != MVT::f32)
2006 return 0;
2007 if ((Subtarget->hasVSX())) {
2008 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWSs, RC: &PPC::VSSRCRegClass, Op0);
2009 }
2010 return 0;
2011}
2012
2013unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0) {
2014 if (RetVT.SimpleTy != MVT::f64)
2015 return 0;
2016 if ((Subtarget->hasVSX())) {
2017 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWS, RC: &PPC::VSFRCRegClass, Op0);
2018 }
2019 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWUZ, RC: &PPC::F8RCRegClass, Op0);
2020}
2021
2022unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f128_r(MVT RetVT, unsigned Op0) {
2023 if (RetVT.SimpleTy != MVT::f128)
2024 return 0;
2025 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2026 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUWZ, RC: &PPC::VRRCRegClass, Op0);
2027 }
2028 return 0;
2029}
2030
2031unsigned fastEmit_PPCISD_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0) {
2032 switch (VT.SimpleTy) {
2033 case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0);
2034 case MVT::f64: return fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(RetVT, Op0);
2035 case MVT::f128: return fastEmit_PPCISD_FCTIWUZ_MVT_f128_r(RetVT, Op0);
2036 default: return 0;
2037 }
2038}
2039
2040// FastEmit functions for PPCISD::FCTIWZ.
2041
2042unsigned fastEmit_PPCISD_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0) {
2043 if (RetVT.SimpleTy != MVT::f32)
2044 return 0;
2045 if ((Subtarget->hasVSX())) {
2046 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWSs, RC: &PPC::VSSRCRegClass, Op0);
2047 }
2048 return 0;
2049}
2050
2051unsigned fastEmit_PPCISD_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0) {
2052 if (RetVT.SimpleTy != MVT::f64)
2053 return 0;
2054 if ((Subtarget->hasVSX())) {
2055 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWS, RC: &PPC::VSFRCRegClass, Op0);
2056 }
2057 if ((Subtarget->hasFPU())) {
2058 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWZ, RC: &PPC::F8RCRegClass, Op0);
2059 }
2060 return 0;
2061}
2062
2063unsigned fastEmit_PPCISD_FCTIWZ_MVT_f128_r(MVT RetVT, unsigned Op0) {
2064 if (RetVT.SimpleTy != MVT::f128)
2065 return 0;
2066 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2067 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSWZ, RC: &PPC::VRRCRegClass, Op0);
2068 }
2069 return 0;
2070}
2071
2072unsigned fastEmit_PPCISD_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0) {
2073 switch (VT.SimpleTy) {
2074 case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0);
2075 case MVT::f64: return fastEmit_PPCISD_FCTIWZ_MVT_f64_r(RetVT, Op0);
2076 case MVT::f128: return fastEmit_PPCISD_FCTIWZ_MVT_f128_r(RetVT, Op0);
2077 default: return 0;
2078 }
2079}
2080
2081// FastEmit functions for PPCISD::FRE.
2082
2083unsigned fastEmit_PPCISD_FRE_MVT_f32_r(MVT RetVT, unsigned Op0) {
2084 if (RetVT.SimpleTy != MVT::f32)
2085 return 0;
2086 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2087 return fastEmitInst_r(MachineInstOpcode: PPC::XSRESP, RC: &PPC::VSSRCRegClass, Op0);
2088 }
2089 if ((Subtarget->hasFPU())) {
2090 return fastEmitInst_r(MachineInstOpcode: PPC::FRES, RC: &PPC::F4RCRegClass, Op0);
2091 }
2092 return 0;
2093}
2094
2095unsigned fastEmit_PPCISD_FRE_MVT_f64_r(MVT RetVT, unsigned Op0) {
2096 if (RetVT.SimpleTy != MVT::f64)
2097 return 0;
2098 if ((Subtarget->hasVSX())) {
2099 return fastEmitInst_r(MachineInstOpcode: PPC::XSREDP, RC: &PPC::VSFRCRegClass, Op0);
2100 }
2101 if ((Subtarget->hasFPU())) {
2102 return fastEmitInst_r(MachineInstOpcode: PPC::FRE, RC: &PPC::F8RCRegClass, Op0);
2103 }
2104 return 0;
2105}
2106
2107unsigned fastEmit_PPCISD_FRE_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
2108 if (RetVT.SimpleTy != MVT::v4f32)
2109 return 0;
2110 if ((Subtarget->hasVSX())) {
2111 return fastEmitInst_r(MachineInstOpcode: PPC::XVRESP, RC: &PPC::VSRCRegClass, Op0);
2112 }
2113 if ((Subtarget->hasAltivec())) {
2114 return fastEmitInst_r(MachineInstOpcode: PPC::VREFP, RC: &PPC::VRRCRegClass, Op0);
2115 }
2116 return 0;
2117}
2118
2119unsigned fastEmit_PPCISD_FRE_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
2120 if (RetVT.SimpleTy != MVT::v2f64)
2121 return 0;
2122 if ((Subtarget->hasVSX())) {
2123 return fastEmitInst_r(MachineInstOpcode: PPC::XVREDP, RC: &PPC::VSRCRegClass, Op0);
2124 }
2125 return 0;
2126}
2127
2128unsigned fastEmit_PPCISD_FRE_r(MVT VT, MVT RetVT, unsigned Op0) {
2129 switch (VT.SimpleTy) {
2130 case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0);
2131 case MVT::f64: return fastEmit_PPCISD_FRE_MVT_f64_r(RetVT, Op0);
2132 case MVT::v4f32: return fastEmit_PPCISD_FRE_MVT_v4f32_r(RetVT, Op0);
2133 case MVT::v2f64: return fastEmit_PPCISD_FRE_MVT_v2f64_r(RetVT, Op0);
2134 default: return 0;
2135 }
2136}
2137
2138// FastEmit functions for PPCISD::FRSQRTE.
2139
2140unsigned fastEmit_PPCISD_FRSQRTE_MVT_f32_r(MVT RetVT, unsigned Op0) {
2141 if (RetVT.SimpleTy != MVT::f32)
2142 return 0;
2143 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2144 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSQRTESP, RC: &PPC::VSSRCRegClass, Op0);
2145 }
2146 if ((Subtarget->hasFPU())) {
2147 return fastEmitInst_r(MachineInstOpcode: PPC::FRSQRTES, RC: &PPC::F4RCRegClass, Op0);
2148 }
2149 return 0;
2150}
2151
2152unsigned fastEmit_PPCISD_FRSQRTE_MVT_f64_r(MVT RetVT, unsigned Op0) {
2153 if (RetVT.SimpleTy != MVT::f64)
2154 return 0;
2155 if ((Subtarget->hasVSX())) {
2156 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSQRTEDP, RC: &PPC::VSFRCRegClass, Op0);
2157 }
2158 if ((Subtarget->hasFPU())) {
2159 return fastEmitInst_r(MachineInstOpcode: PPC::FRSQRTE, RC: &PPC::F8RCRegClass, Op0);
2160 }
2161 return 0;
2162}
2163
2164unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
2165 if (RetVT.SimpleTy != MVT::v4f32)
2166 return 0;
2167 if ((Subtarget->hasVSX())) {
2168 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSQRTESP, RC: &PPC::VSRCRegClass, Op0);
2169 }
2170 if ((Subtarget->hasAltivec())) {
2171 return fastEmitInst_r(MachineInstOpcode: PPC::VRSQRTEFP, RC: &PPC::VRRCRegClass, Op0);
2172 }
2173 return 0;
2174}
2175
2176unsigned fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
2177 if (RetVT.SimpleTy != MVT::v2f64)
2178 return 0;
2179 if ((Subtarget->hasVSX())) {
2180 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSQRTEDP, RC: &PPC::VSRCRegClass, Op0);
2181 }
2182 return 0;
2183}
2184
2185unsigned fastEmit_PPCISD_FRSQRTE_r(MVT VT, MVT RetVT, unsigned Op0) {
2186 switch (VT.SimpleTy) {
2187 case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0);
2188 case MVT::f64: return fastEmit_PPCISD_FRSQRTE_MVT_f64_r(RetVT, Op0);
2189 case MVT::v4f32: return fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0);
2190 case MVT::v2f64: return fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0);
2191 default: return 0;
2192 }
2193}
2194
2195// FastEmit functions for PPCISD::FSQRT.
2196
2197unsigned fastEmit_PPCISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) {
2198 if (RetVT.SimpleTy != MVT::f64)
2199 return 0;
2200 if ((Subtarget->hasVSX())) {
2201 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTDP, RC: &PPC::VSFRCRegClass, Op0);
2202 }
2203 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRT, RC: &PPC::F8RCRegClass, Op0);
2204}
2205
2206unsigned fastEmit_PPCISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
2207 if (RetVT.SimpleTy != MVT::v4f32)
2208 return 0;
2209 if ((Subtarget->hasVSX())) {
2210 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTSP, RC: &PPC::VSRCRegClass, Op0);
2211 }
2212 return 0;
2213}
2214
2215unsigned fastEmit_PPCISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
2216 if (RetVT.SimpleTy != MVT::v2f64)
2217 return 0;
2218 if ((Subtarget->hasVSX())) {
2219 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTDP, RC: &PPC::VSRCRegClass, Op0);
2220 }
2221 return 0;
2222}
2223
2224unsigned fastEmit_PPCISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) {
2225 switch (VT.SimpleTy) {
2226 case MVT::f64: return fastEmit_PPCISD_FSQRT_MVT_f64_r(RetVT, Op0);
2227 case MVT::v4f32: return fastEmit_PPCISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
2228 case MVT::v2f64: return fastEmit_PPCISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
2229 default: return 0;
2230 }
2231}
2232
2233// FastEmit functions for PPCISD::FTSQRT.
2234
2235unsigned fastEmit_PPCISD_FTSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) {
2236 if (RetVT.SimpleTy != MVT::i32)
2237 return 0;
2238 if ((Subtarget->hasVSX())) {
2239 return fastEmitInst_r(MachineInstOpcode: PPC::XSTSQRTDP, RC: &PPC::CRRCRegClass, Op0);
2240 }
2241 if ((Subtarget->hasFPU())) {
2242 return fastEmitInst_r(MachineInstOpcode: PPC::FTSQRT, RC: &PPC::CRRCRegClass, Op0);
2243 }
2244 return 0;
2245}
2246
2247unsigned fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
2248 if (RetVT.SimpleTy != MVT::i32)
2249 return 0;
2250 if ((Subtarget->hasVSX())) {
2251 return fastEmitInst_r(MachineInstOpcode: PPC::XVTSQRTSP, RC: &PPC::CRRCRegClass, Op0);
2252 }
2253 return 0;
2254}
2255
2256unsigned fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
2257 if (RetVT.SimpleTy != MVT::i32)
2258 return 0;
2259 if ((Subtarget->hasVSX())) {
2260 return fastEmitInst_r(MachineInstOpcode: PPC::XVTSQRTDP, RC: &PPC::CRRCRegClass, Op0);
2261 }
2262 return 0;
2263}
2264
2265unsigned fastEmit_PPCISD_FTSQRT_r(MVT VT, MVT RetVT, unsigned Op0) {
2266 switch (VT.SimpleTy) {
2267 case MVT::f64: return fastEmit_PPCISD_FTSQRT_MVT_f64_r(RetVT, Op0);
2268 case MVT::v4f32: return fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(RetVT, Op0);
2269 case MVT::v2f64: return fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(RetVT, Op0);
2270 default: return 0;
2271 }
2272}
2273
2274// FastEmit functions for PPCISD::GET_TLS_MOD_AIX.
2275
2276unsigned fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i32_r(MVT RetVT, unsigned Op0) {
2277 if (RetVT.SimpleTy != MVT::i32)
2278 return 0;
2279 return fastEmitInst_r(MachineInstOpcode: PPC::GETtlsMOD32AIX, RC: &PPC::GPRCRegClass, Op0);
2280}
2281
2282unsigned fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i64_r(MVT RetVT, unsigned Op0) {
2283 if (RetVT.SimpleTy != MVT::i64)
2284 return 0;
2285 return fastEmitInst_r(MachineInstOpcode: PPC::GETtlsMOD64AIX, RC: &PPC::G8RCRegClass, Op0);
2286}
2287
2288unsigned fastEmit_PPCISD_GET_TLS_MOD_AIX_r(MVT VT, MVT RetVT, unsigned Op0) {
2289 switch (VT.SimpleTy) {
2290 case MVT::i32: return fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i32_r(RetVT, Op0);
2291 case MVT::i64: return fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i64_r(RetVT, Op0);
2292 default: return 0;
2293 }
2294}
2295
2296// FastEmit functions for PPCISD::MFVSR.
2297
2298unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(unsigned Op0) {
2299 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2300 return fastEmitInst_r(MachineInstOpcode: PPC::MFVSRWZ, RC: &PPC::GPRCRegClass, Op0);
2301 }
2302 return 0;
2303}
2304
2305unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(unsigned Op0) {
2306 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2307 return fastEmitInst_r(MachineInstOpcode: PPC::MFVSRD, RC: &PPC::G8RCRegClass, Op0);
2308 }
2309 return 0;
2310}
2311
2312unsigned fastEmit_PPCISD_MFVSR_MVT_f64_r(MVT RetVT, unsigned Op0) {
2313switch (RetVT.SimpleTy) {
2314 case MVT::i32: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Op0);
2315 case MVT::i64: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Op0);
2316 default: return 0;
2317}
2318}
2319
2320unsigned fastEmit_PPCISD_MFVSR_r(MVT VT, MVT RetVT, unsigned Op0) {
2321 switch (VT.SimpleTy) {
2322 case MVT::f64: return fastEmit_PPCISD_MFVSR_MVT_f64_r(RetVT, Op0);
2323 default: return 0;
2324 }
2325}
2326
2327// FastEmit functions for PPCISD::MTCTR.
2328
2329unsigned fastEmit_PPCISD_MTCTR_MVT_i32_r(MVT RetVT, unsigned Op0) {
2330 if (RetVT.SimpleTy != MVT::isVoid)
2331 return 0;
2332 return fastEmitInst_r(MachineInstOpcode: PPC::MTCTR, RC: &PPC::GPRCRegClass, Op0);
2333}
2334
2335unsigned fastEmit_PPCISD_MTCTR_MVT_i64_r(MVT RetVT, unsigned Op0) {
2336 if (RetVT.SimpleTy != MVT::isVoid)
2337 return 0;
2338 return fastEmitInst_r(MachineInstOpcode: PPC::MTCTR8, RC: &PPC::G8RCRegClass, Op0);
2339}
2340
2341unsigned fastEmit_PPCISD_MTCTR_r(MVT VT, MVT RetVT, unsigned Op0) {
2342 switch (VT.SimpleTy) {
2343 case MVT::i32: return fastEmit_PPCISD_MTCTR_MVT_i32_r(RetVT, Op0);
2344 case MVT::i64: return fastEmit_PPCISD_MTCTR_MVT_i64_r(RetVT, Op0);
2345 default: return 0;
2346 }
2347}
2348
2349// FastEmit functions for PPCISD::MTVSRA.
2350
2351unsigned fastEmit_PPCISD_MTVSRA_MVT_i32_r(MVT RetVT, unsigned Op0) {
2352 if (RetVT.SimpleTy != MVT::f64)
2353 return 0;
2354 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2355 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRWA, RC: &PPC::VSFRCRegClass, Op0);
2356 }
2357 return 0;
2358}
2359
2360unsigned fastEmit_PPCISD_MTVSRA_MVT_i64_r(MVT RetVT, unsigned Op0) {
2361 if (RetVT.SimpleTy != MVT::f64)
2362 return 0;
2363 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2364 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRD, RC: &PPC::VSFRCRegClass, Op0);
2365 }
2366 return 0;
2367}
2368
2369unsigned fastEmit_PPCISD_MTVSRA_r(MVT VT, MVT RetVT, unsigned Op0) {
2370 switch (VT.SimpleTy) {
2371 case MVT::i32: return fastEmit_PPCISD_MTVSRA_MVT_i32_r(RetVT, Op0);
2372 case MVT::i64: return fastEmit_PPCISD_MTVSRA_MVT_i64_r(RetVT, Op0);
2373 default: return 0;
2374 }
2375}
2376
2377// FastEmit functions for PPCISD::MTVSRZ.
2378
2379unsigned fastEmit_PPCISD_MTVSRZ_MVT_i32_r(MVT RetVT, unsigned Op0) {
2380 if (RetVT.SimpleTy != MVT::f64)
2381 return 0;
2382 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2383 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRWZ, RC: &PPC::VSFRCRegClass, Op0);
2384 }
2385 return 0;
2386}
2387
2388unsigned fastEmit_PPCISD_MTVSRZ_r(MVT VT, MVT RetVT, unsigned Op0) {
2389 switch (VT.SimpleTy) {
2390 case MVT::i32: return fastEmit_PPCISD_MTVSRZ_MVT_i32_r(RetVT, Op0);
2391 default: return 0;
2392 }
2393}
2394
2395// FastEmit functions for PPCISD::SCALAR_TO_VECTOR_PERMUTED.
2396
2397unsigned fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(MVT RetVT, unsigned Op0) {
2398 if (RetVT.SimpleTy != MVT::v4f32)
2399 return 0;
2400 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (Subtarget->isLittleEndian())) {
2401 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSPN, RC: &PPC::VSRCRegClass, Op0);
2402 }
2403 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) {
2404 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSPN, RC: &PPC::VSRCRegClass, Op0);
2405 }
2406 return 0;
2407}
2408
2409unsigned fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_r(MVT VT, MVT RetVT, unsigned Op0) {
2410 switch (VT.SimpleTy) {
2411 case MVT::f32: return fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(RetVT, Op0);
2412 default: return 0;
2413 }
2414}
2415
2416// FastEmit functions for PPCISD::STRICT_FCFID.
2417
2418unsigned fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0) {
2419 if (RetVT.SimpleTy != MVT::f64)
2420 return 0;
2421 if ((Subtarget->hasVSX())) {
2422 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDDP, RC: &PPC::VSFRCRegClass, Op0);
2423 }
2424 return fastEmitInst_r(MachineInstOpcode: PPC::FCFID, RC: &PPC::F8RCRegClass, Op0);
2425}
2426
2427unsigned fastEmit_PPCISD_STRICT_FCFID_r(MVT VT, MVT RetVT, unsigned Op0) {
2428 switch (VT.SimpleTy) {
2429 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(RetVT, Op0);
2430 default: return 0;
2431 }
2432}
2433
2434// FastEmit functions for PPCISD::STRICT_FCFIDS.
2435
2436unsigned fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0) {
2437 if (RetVT.SimpleTy != MVT::f32)
2438 return 0;
2439 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2440 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDSP, RC: &PPC::VSSRCRegClass, Op0);
2441 }
2442 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDS, RC: &PPC::F4RCRegClass, Op0);
2443}
2444
2445unsigned fastEmit_PPCISD_STRICT_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0) {
2446 switch (VT.SimpleTy) {
2447 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(RetVT, Op0);
2448 default: return 0;
2449 }
2450}
2451
2452// FastEmit functions for PPCISD::STRICT_FCFIDU.
2453
2454unsigned fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0) {
2455 if (RetVT.SimpleTy != MVT::f64)
2456 return 0;
2457 if ((Subtarget->hasVSX())) {
2458 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDDP, RC: &PPC::VSFRCRegClass, Op0);
2459 }
2460 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDU, RC: &PPC::F8RCRegClass, Op0);
2461}
2462
2463unsigned fastEmit_PPCISD_STRICT_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0) {
2464 switch (VT.SimpleTy) {
2465 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(RetVT, Op0);
2466 default: return 0;
2467 }
2468}
2469
2470// FastEmit functions for PPCISD::STRICT_FCFIDUS.
2471
2472unsigned fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0) {
2473 if (RetVT.SimpleTy != MVT::f32)
2474 return 0;
2475 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2476 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDSP, RC: &PPC::VSSRCRegClass, Op0);
2477 }
2478 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDUS, RC: &PPC::F4RCRegClass, Op0);
2479}
2480
2481unsigned fastEmit_PPCISD_STRICT_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0) {
2482 switch (VT.SimpleTy) {
2483 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(RetVT, Op0);
2484 default: return 0;
2485 }
2486}
2487
2488// FastEmit functions for PPCISD::STRICT_FCTIDUZ.
2489
2490unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0) {
2491 if (RetVT.SimpleTy != MVT::f32)
2492 return 0;
2493 if ((Subtarget->hasVSX())) {
2494 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDSs, RC: &PPC::VSSRCRegClass, Op0);
2495 }
2496 return 0;
2497}
2498
2499unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0) {
2500 if (RetVT.SimpleTy != MVT::f64)
2501 return 0;
2502 if ((Subtarget->hasVSX())) {
2503 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDS, RC: &PPC::VSFRCRegClass, Op0);
2504 }
2505 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDUZ, RC: &PPC::F8RCRegClass, Op0);
2506}
2507
2508unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f128_r(MVT RetVT, unsigned Op0) {
2509 if (RetVT.SimpleTy != MVT::f128)
2510 return 0;
2511 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2512 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUDZ, RC: &PPC::VRRCRegClass, Op0);
2513 }
2514 return 0;
2515}
2516
2517unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0) {
2518 switch (VT.SimpleTy) {
2519 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(RetVT, Op0);
2520 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(RetVT, Op0);
2521 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f128_r(RetVT, Op0);
2522 default: return 0;
2523 }
2524}
2525
2526// FastEmit functions for PPCISD::STRICT_FCTIDZ.
2527
2528unsigned fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0) {
2529 if (RetVT.SimpleTy != MVT::f32)
2530 return 0;
2531 if ((Subtarget->hasVSX())) {
2532 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDSs, RC: &PPC::VSSRCRegClass, Op0);
2533 }
2534 return 0;
2535}
2536
2537unsigned fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0) {
2538 if (RetVT.SimpleTy != MVT::f64)
2539 return 0;
2540 if ((Subtarget->hasVSX())) {
2541 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDS, RC: &PPC::VSFRCRegClass, Op0);
2542 }
2543 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDZ, RC: &PPC::F8RCRegClass, Op0);
2544}
2545
2546unsigned fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f128_r(MVT RetVT, unsigned Op0) {
2547 if (RetVT.SimpleTy != MVT::f128)
2548 return 0;
2549 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2550 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSDZ, RC: &PPC::VRRCRegClass, Op0);
2551 }
2552 return 0;
2553}
2554
2555unsigned fastEmit_PPCISD_STRICT_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0) {
2556 switch (VT.SimpleTy) {
2557 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(RetVT, Op0);
2558 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(RetVT, Op0);
2559 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f128_r(RetVT, Op0);
2560 default: return 0;
2561 }
2562}
2563
2564// FastEmit functions for PPCISD::STRICT_FCTIWUZ.
2565
2566unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0) {
2567 if (RetVT.SimpleTy != MVT::f32)
2568 return 0;
2569 if ((Subtarget->hasVSX())) {
2570 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWSs, RC: &PPC::VSSRCRegClass, Op0);
2571 }
2572 return 0;
2573}
2574
2575unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0) {
2576 if (RetVT.SimpleTy != MVT::f64)
2577 return 0;
2578 if ((Subtarget->hasVSX())) {
2579 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWS, RC: &PPC::VSFRCRegClass, Op0);
2580 }
2581 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWUZ, RC: &PPC::F8RCRegClass, Op0);
2582}
2583
2584unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f128_r(MVT RetVT, unsigned Op0) {
2585 if (RetVT.SimpleTy != MVT::f128)
2586 return 0;
2587 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2588 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUWZ, RC: &PPC::VRRCRegClass, Op0);
2589 }
2590 return 0;
2591}
2592
2593unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0) {
2594 switch (VT.SimpleTy) {
2595 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(RetVT, Op0);
2596 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(RetVT, Op0);
2597 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f128_r(RetVT, Op0);
2598 default: return 0;
2599 }
2600}
2601
2602// FastEmit functions for PPCISD::STRICT_FCTIWZ.
2603
2604unsigned fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0) {
2605 if (RetVT.SimpleTy != MVT::f32)
2606 return 0;
2607 if ((Subtarget->hasVSX())) {
2608 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWSs, RC: &PPC::VSSRCRegClass, Op0);
2609 }
2610 return 0;
2611}
2612
2613unsigned fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0) {
2614 if (RetVT.SimpleTy != MVT::f64)
2615 return 0;
2616 if ((Subtarget->hasVSX())) {
2617 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWS, RC: &PPC::VSFRCRegClass, Op0);
2618 }
2619 if ((Subtarget->hasFPU())) {
2620 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWZ, RC: &PPC::F8RCRegClass, Op0);
2621 }
2622 return 0;
2623}
2624
2625unsigned fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f128_r(MVT RetVT, unsigned Op0) {
2626 if (RetVT.SimpleTy != MVT::f128)
2627 return 0;
2628 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2629 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSWZ, RC: &PPC::VRRCRegClass, Op0);
2630 }
2631 return 0;
2632}
2633
2634unsigned fastEmit_PPCISD_STRICT_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0) {
2635 switch (VT.SimpleTy) {
2636 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(RetVT, Op0);
2637 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(RetVT, Op0);
2638 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f128_r(RetVT, Op0);
2639 default: return 0;
2640 }
2641}
2642
2643// FastEmit functions for PPCISD::TLSLD_AIX.
2644
2645unsigned fastEmit_PPCISD_TLSLD_AIX_MVT_i32_r(MVT RetVT, unsigned Op0) {
2646 if (RetVT.SimpleTy != MVT::i32)
2647 return 0;
2648 return fastEmitInst_r(MachineInstOpcode: PPC::TLSLDAIX, RC: &PPC::GPRCRegClass, Op0);
2649}
2650
2651unsigned fastEmit_PPCISD_TLSLD_AIX_MVT_i64_r(MVT RetVT, unsigned Op0) {
2652 if (RetVT.SimpleTy != MVT::i64)
2653 return 0;
2654 return fastEmitInst_r(MachineInstOpcode: PPC::TLSLDAIX8, RC: &PPC::G8RCRegClass, Op0);
2655}
2656
2657unsigned fastEmit_PPCISD_TLSLD_AIX_r(MVT VT, MVT RetVT, unsigned Op0) {
2658 switch (VT.SimpleTy) {
2659 case MVT::i32: return fastEmit_PPCISD_TLSLD_AIX_MVT_i32_r(RetVT, Op0);
2660 case MVT::i64: return fastEmit_PPCISD_TLSLD_AIX_MVT_i64_r(RetVT, Op0);
2661 default: return 0;
2662 }
2663}
2664
2665// FastEmit functions for PPCISD::XXMFACC.
2666
2667unsigned fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(MVT RetVT, unsigned Op0) {
2668 if (RetVT.SimpleTy != MVT::v512i1)
2669 return 0;
2670 if ((!Subtarget->isISAFuture()) && (Subtarget->hasMMA())) {
2671 return fastEmitInst_r(MachineInstOpcode: PPC::XXMFACC, RC: &PPC::ACCRCRegClass, Op0);
2672 }
2673 return 0;
2674}
2675
2676unsigned fastEmit_PPCISD_XXMFACC_r(MVT VT, MVT RetVT, unsigned Op0) {
2677 switch (VT.SimpleTy) {
2678 case MVT::v512i1: return fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(RetVT, Op0);
2679 default: return 0;
2680 }
2681}
2682
2683// FastEmit functions for PPCISD::XXSPLTI_SP_TO_DP.
2684
2685unsigned fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(MVT RetVT, unsigned Op0) {
2686 if (RetVT.SimpleTy != MVT::v2f64)
2687 return 0;
2688 if ((Subtarget->hasPrefixInstrs())) {
2689 return fastEmitInst_r(MachineInstOpcode: PPC::XXSPLTIDP, RC: &PPC::VSRCRegClass, Op0);
2690 }
2691 return 0;
2692}
2693
2694unsigned fastEmit_PPCISD_XXSPLTI_SP_TO_DP_r(MVT VT, MVT RetVT, unsigned Op0) {
2695 switch (VT.SimpleTy) {
2696 case MVT::i32: return fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(RetVT, Op0);
2697 default: return 0;
2698 }
2699}
2700
2701// Top-level FastEmit function.
2702
2703unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0) override {
2704 switch (Opcode) {
2705 case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0);
2706 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
2707 case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0);
2708 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
2709 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
2710 case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0);
2711 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
2712 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0);
2713 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0);
2714 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0);
2715 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
2716 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
2717 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
2718 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
2719 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
2720 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
2721 case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0);
2722 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
2723 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0);
2724 case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0);
2725 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
2726 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
2727 case ISD::STRICT_FCEIL: return fastEmit_ISD_STRICT_FCEIL_r(VT, RetVT, Op0);
2728 case ISD::STRICT_FFLOOR: return fastEmit_ISD_STRICT_FFLOOR_r(VT, RetVT, Op0);
2729 case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0);
2730 case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0);
2731 case ISD::STRICT_FP_TO_SINT: return fastEmit_ISD_STRICT_FP_TO_SINT_r(VT, RetVT, Op0);
2732 case ISD::STRICT_FP_TO_UINT: return fastEmit_ISD_STRICT_FP_TO_UINT_r(VT, RetVT, Op0);
2733 case ISD::STRICT_FRINT: return fastEmit_ISD_STRICT_FRINT_r(VT, RetVT, Op0);
2734 case ISD::STRICT_FROUND: return fastEmit_ISD_STRICT_FROUND_r(VT, RetVT, Op0);
2735 case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0);
2736 case ISD::STRICT_FTRUNC: return fastEmit_ISD_STRICT_FTRUNC_r(VT, RetVT, Op0);
2737 case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0);
2738 case ISD::STRICT_UINT_TO_FP: return fastEmit_ISD_STRICT_UINT_TO_FP_r(VT, RetVT, Op0);
2739 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0);
2740 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
2741 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0);
2742 case PPCISD::FCFID: return fastEmit_PPCISD_FCFID_r(VT, RetVT, Op0);
2743 case PPCISD::FCFIDS: return fastEmit_PPCISD_FCFIDS_r(VT, RetVT, Op0);
2744 case PPCISD::FCFIDU: return fastEmit_PPCISD_FCFIDU_r(VT, RetVT, Op0);
2745 case PPCISD::FCFIDUS: return fastEmit_PPCISD_FCFIDUS_r(VT, RetVT, Op0);
2746 case PPCISD::FCTIDUZ: return fastEmit_PPCISD_FCTIDUZ_r(VT, RetVT, Op0);
2747 case PPCISD::FCTIDZ: return fastEmit_PPCISD_FCTIDZ_r(VT, RetVT, Op0);
2748 case PPCISD::FCTIWUZ: return fastEmit_PPCISD_FCTIWUZ_r(VT, RetVT, Op0);
2749 case PPCISD::FCTIWZ: return fastEmit_PPCISD_FCTIWZ_r(VT, RetVT, Op0);
2750 case PPCISD::FRE: return fastEmit_PPCISD_FRE_r(VT, RetVT, Op0);
2751 case PPCISD::FRSQRTE: return fastEmit_PPCISD_FRSQRTE_r(VT, RetVT, Op0);
2752 case PPCISD::FSQRT: return fastEmit_PPCISD_FSQRT_r(VT, RetVT, Op0);
2753 case PPCISD::FTSQRT: return fastEmit_PPCISD_FTSQRT_r(VT, RetVT, Op0);
2754 case PPCISD::GET_TLS_MOD_AIX: return fastEmit_PPCISD_GET_TLS_MOD_AIX_r(VT, RetVT, Op0);
2755 case PPCISD::MFVSR: return fastEmit_PPCISD_MFVSR_r(VT, RetVT, Op0);
2756 case PPCISD::MTCTR: return fastEmit_PPCISD_MTCTR_r(VT, RetVT, Op0);
2757 case PPCISD::MTVSRA: return fastEmit_PPCISD_MTVSRA_r(VT, RetVT, Op0);
2758 case PPCISD::MTVSRZ: return fastEmit_PPCISD_MTVSRZ_r(VT, RetVT, Op0);
2759 case PPCISD::SCALAR_TO_VECTOR_PERMUTED: return fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_r(VT, RetVT, Op0);
2760 case PPCISD::STRICT_FCFID: return fastEmit_PPCISD_STRICT_FCFID_r(VT, RetVT, Op0);
2761 case PPCISD::STRICT_FCFIDS: return fastEmit_PPCISD_STRICT_FCFIDS_r(VT, RetVT, Op0);
2762 case PPCISD::STRICT_FCFIDU: return fastEmit_PPCISD_STRICT_FCFIDU_r(VT, RetVT, Op0);
2763 case PPCISD::STRICT_FCFIDUS: return fastEmit_PPCISD_STRICT_FCFIDUS_r(VT, RetVT, Op0);
2764 case PPCISD::STRICT_FCTIDUZ: return fastEmit_PPCISD_STRICT_FCTIDUZ_r(VT, RetVT, Op0);
2765 case PPCISD::STRICT_FCTIDZ: return fastEmit_PPCISD_STRICT_FCTIDZ_r(VT, RetVT, Op0);
2766 case PPCISD::STRICT_FCTIWUZ: return fastEmit_PPCISD_STRICT_FCTIWUZ_r(VT, RetVT, Op0);
2767 case PPCISD::STRICT_FCTIWZ: return fastEmit_PPCISD_STRICT_FCTIWZ_r(VT, RetVT, Op0);
2768 case PPCISD::TLSLD_AIX: return fastEmit_PPCISD_TLSLD_AIX_r(VT, RetVT, Op0);
2769 case PPCISD::XXMFACC: return fastEmit_PPCISD_XXMFACC_r(VT, RetVT, Op0);
2770 case PPCISD::XXSPLTI_SP_TO_DP: return fastEmit_PPCISD_XXSPLTI_SP_TO_DP_r(VT, RetVT, Op0);
2771 default: return 0;
2772 }
2773}
2774
2775// FastEmit functions for ISD::ABDU.
2776
2777unsigned fastEmit_ISD_ABDU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2778 if (RetVT.SimpleTy != MVT::v16i8)
2779 return 0;
2780 if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) {
2781 return fastEmitInst_rr(MachineInstOpcode: PPC::VABSDUB, RC: &PPC::VRRCRegClass, Op0, Op1);
2782 }
2783 return 0;
2784}
2785
2786unsigned fastEmit_ISD_ABDU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2787 if (RetVT.SimpleTy != MVT::v8i16)
2788 return 0;
2789 if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) {
2790 return fastEmitInst_rr(MachineInstOpcode: PPC::VABSDUH, RC: &PPC::VRRCRegClass, Op0, Op1);
2791 }
2792 return 0;
2793}
2794
2795unsigned fastEmit_ISD_ABDU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2796 if (RetVT.SimpleTy != MVT::v4i32)
2797 return 0;
2798 if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) {
2799 return fastEmitInst_rr(MachineInstOpcode: PPC::VABSDUW, RC: &PPC::VRRCRegClass, Op0, Op1);
2800 }
2801 return 0;
2802}
2803
2804unsigned fastEmit_ISD_ABDU_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2805 switch (VT.SimpleTy) {
2806 case MVT::v16i8: return fastEmit_ISD_ABDU_MVT_v16i8_rr(RetVT, Op0, Op1);
2807 case MVT::v8i16: return fastEmit_ISD_ABDU_MVT_v8i16_rr(RetVT, Op0, Op1);
2808 case MVT::v4i32: return fastEmit_ISD_ABDU_MVT_v4i32_rr(RetVT, Op0, Op1);
2809 default: return 0;
2810 }
2811}
2812
2813// FastEmit functions for ISD::ADD.
2814
2815unsigned fastEmit_ISD_ADD_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2816 if (RetVT.SimpleTy != MVT::i1)
2817 return 0;
2818 return fastEmitInst_rr(MachineInstOpcode: PPC::CRXOR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
2819}
2820
2821unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2822 if (RetVT.SimpleTy != MVT::i32)
2823 return 0;
2824 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD4, RC: &PPC::GPRCRegClass, Op0, Op1);
2825}
2826
2827unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2828 if (RetVT.SimpleTy != MVT::i64)
2829 return 0;
2830 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD8, RC: &PPC::G8RCRegClass, Op0, Op1);
2831}
2832
2833unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2834 if (RetVT.SimpleTy != MVT::v16i8)
2835 return 0;
2836 if ((Subtarget->hasAltivec())) {
2837 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUBM, RC: &PPC::VRRCRegClass, Op0, Op1);
2838 }
2839 return 0;
2840}
2841
2842unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2843 if (RetVT.SimpleTy != MVT::v8i16)
2844 return 0;
2845 if ((Subtarget->hasAltivec())) {
2846 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUHM, RC: &PPC::VRRCRegClass, Op0, Op1);
2847 }
2848 return 0;
2849}
2850
2851unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2852 if (RetVT.SimpleTy != MVT::v4i32)
2853 return 0;
2854 if ((Subtarget->hasAltivec())) {
2855 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUWM, RC: &PPC::VRRCRegClass, Op0, Op1);
2856 }
2857 return 0;
2858}
2859
2860unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2861 if (RetVT.SimpleTy != MVT::v2i64)
2862 return 0;
2863 if ((Subtarget->hasP8Altivec())) {
2864 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUDM, RC: &PPC::VRRCRegClass, Op0, Op1);
2865 }
2866 return 0;
2867}
2868
2869unsigned fastEmit_ISD_ADD_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2870 if (RetVT.SimpleTy != MVT::v1i128)
2871 return 0;
2872 if ((Subtarget->hasP8Altivec())) {
2873 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUQM, RC: &PPC::VRRCRegClass, Op0, Op1);
2874 }
2875 return 0;
2876}
2877
2878unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2879 switch (VT.SimpleTy) {
2880 case MVT::i1: return fastEmit_ISD_ADD_MVT_i1_rr(RetVT, Op0, Op1);
2881 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
2882 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
2883 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
2884 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
2885 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
2886 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
2887 case MVT::v1i128: return fastEmit_ISD_ADD_MVT_v1i128_rr(RetVT, Op0, Op1);
2888 default: return 0;
2889 }
2890}
2891
2892// FastEmit functions for ISD::ADDC.
2893
2894unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2895 if (RetVT.SimpleTy != MVT::i32)
2896 return 0;
2897 return fastEmitInst_rr(MachineInstOpcode: PPC::ADDC, RC: &PPC::GPRCRegClass, Op0, Op1);
2898}
2899
2900unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2901 if (RetVT.SimpleTy != MVT::i64)
2902 return 0;
2903 return fastEmitInst_rr(MachineInstOpcode: PPC::ADDC8, RC: &PPC::G8RCRegClass, Op0, Op1);
2904}
2905
2906unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2907 switch (VT.SimpleTy) {
2908 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op1);
2909 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op1);
2910 default: return 0;
2911 }
2912}
2913
2914// FastEmit functions for ISD::ADDE.
2915
2916unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2917 if (RetVT.SimpleTy != MVT::i32)
2918 return 0;
2919 return fastEmitInst_rr(MachineInstOpcode: PPC::ADDE, RC: &PPC::GPRCRegClass, Op0, Op1);
2920}
2921
2922unsigned fastEmit_ISD_ADDE_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2923 if (RetVT.SimpleTy != MVT::i64)
2924 return 0;
2925 return fastEmitInst_rr(MachineInstOpcode: PPC::ADDE8, RC: &PPC::G8RCRegClass, Op0, Op1);
2926}
2927
2928unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2929 switch (VT.SimpleTy) {
2930 case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op1);
2931 case MVT::i64: return fastEmit_ISD_ADDE_MVT_i64_rr(RetVT, Op0, Op1);
2932 default: return 0;
2933 }
2934}
2935
2936// FastEmit functions for ISD::AND.
2937
2938unsigned fastEmit_ISD_AND_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2939 if (RetVT.SimpleTy != MVT::i1)
2940 return 0;
2941 return fastEmitInst_rr(MachineInstOpcode: PPC::CRAND, RC: &PPC::CRBITRCRegClass, Op0, Op1);
2942}
2943
2944unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2945 if (RetVT.SimpleTy != MVT::i32)
2946 return 0;
2947 return fastEmitInst_rr(MachineInstOpcode: PPC::AND, RC: &PPC::GPRCRegClass, Op0, Op1);
2948}
2949
2950unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2951 if (RetVT.SimpleTy != MVT::i64)
2952 return 0;
2953 return fastEmitInst_rr(MachineInstOpcode: PPC::AND8, RC: &PPC::G8RCRegClass, Op0, Op1);
2954}
2955
2956unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2957 if (RetVT.SimpleTy != MVT::v4i32)
2958 return 0;
2959 if ((Subtarget->hasVSX())) {
2960 return fastEmitInst_rr(MachineInstOpcode: PPC::XXLAND, RC: &PPC::VSRCRegClass, Op0, Op1);
2961 }
2962 if ((Subtarget->hasAltivec())) {
2963 return fastEmitInst_rr(MachineInstOpcode: PPC::VAND, RC: &PPC::VRRCRegClass, Op0, Op1);
2964 }
2965 return 0;
2966}
2967
2968unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2969 switch (VT.SimpleTy) {
2970 case MVT::i1: return fastEmit_ISD_AND_MVT_i1_rr(RetVT, Op0, Op1);
2971 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
2972 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
2973 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
2974 default: return 0;
2975 }
2976}
2977
2978// FastEmit functions for ISD::BUILD_VECTOR.
2979
2980unsigned fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2981 if (RetVT.SimpleTy != MVT::v2i64)
2982 return 0;
2983 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian()) && (Subtarget->isISA3_0()) && (Subtarget->isPPC64())) {
2984 return fastEmitInst_rr(MachineInstOpcode: PPC::MTVSRDD, RC: &PPC::VSRCRegClass, Op0, Op1);
2985 }
2986 return 0;
2987}
2988
2989unsigned fastEmit_ISD_BUILD_VECTOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2990 switch (VT.SimpleTy) {
2991 case MVT::i64: return fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(RetVT, Op0, Op1);
2992 default: return 0;
2993 }
2994}
2995
2996// FastEmit functions for ISD::FADD.
2997
2998unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2999 if (RetVT.SimpleTy != MVT::f32)
3000 return 0;
3001 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3002 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3003 }
3004 if ((Subtarget->hasSPE())) {
3005 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSADD, RC: &PPC::GPRCRegClass, Op0, Op1);
3006 }
3007 if ((Subtarget->hasFPU())) {
3008 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDS, RC: &PPC::F4RCRegClass, Op0, Op1);
3009 }
3010 return 0;
3011}
3012
3013unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3014 if (RetVT.SimpleTy != MVT::f64)
3015 return 0;
3016 if ((Subtarget->hasVSX())) {
3017 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3018 }
3019 if ((Subtarget->hasSPE())) {
3020 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDADD, RC: &PPC::SPERCRegClass, Op0, Op1);
3021 }
3022 if ((Subtarget->hasFPU())) {
3023 return fastEmitInst_rr(MachineInstOpcode: PPC::FADD, RC: &PPC::F8RCRegClass, Op0, Op1);
3024 }
3025 return 0;
3026}
3027
3028unsigned fastEmit_ISD_FADD_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3029 if (RetVT.SimpleTy != MVT::f128)
3030 return 0;
3031 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3032 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3033 }
3034 return 0;
3035}
3036
3037unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3038 if (RetVT.SimpleTy != MVT::v4f32)
3039 return 0;
3040 if ((Subtarget->hasVSX())) {
3041 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3042 }
3043 if ((Subtarget->hasAltivec())) {
3044 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDFP, RC: &PPC::VRRCRegClass, Op0, Op1);
3045 }
3046 return 0;
3047}
3048
3049unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3050 if (RetVT.SimpleTy != MVT::v2f64)
3051 return 0;
3052 if ((Subtarget->hasVSX())) {
3053 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3054 }
3055 return 0;
3056}
3057
3058unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3059 switch (VT.SimpleTy) {
3060 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
3061 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
3062 case MVT::f128: return fastEmit_ISD_FADD_MVT_f128_rr(RetVT, Op0, Op1);
3063 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
3064 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
3065 default: return 0;
3066 }
3067}
3068
3069// FastEmit functions for ISD::FDIV.
3070
3071unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3072 if (RetVT.SimpleTy != MVT::f32)
3073 return 0;
3074 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3075 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3076 }
3077 if ((Subtarget->hasSPE())) {
3078 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSDIV, RC: &PPC::GPRCRegClass, Op0, Op1);
3079 }
3080 if ((Subtarget->hasFPU())) {
3081 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIVS, RC: &PPC::F4RCRegClass, Op0, Op1);
3082 }
3083 return 0;
3084}
3085
3086unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3087 if (RetVT.SimpleTy != MVT::f64)
3088 return 0;
3089 if ((Subtarget->hasVSX())) {
3090 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3091 }
3092 if ((Subtarget->hasSPE())) {
3093 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDDIV, RC: &PPC::SPERCRegClass, Op0, Op1);
3094 }
3095 if ((Subtarget->hasFPU())) {
3096 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIV, RC: &PPC::F8RCRegClass, Op0, Op1);
3097 }
3098 return 0;
3099}
3100
3101unsigned fastEmit_ISD_FDIV_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3102 if (RetVT.SimpleTy != MVT::f128)
3103 return 0;
3104 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3105 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3106 }
3107 return 0;
3108}
3109
3110unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3111 if (RetVT.SimpleTy != MVT::v4f32)
3112 return 0;
3113 if ((Subtarget->hasVSX())) {
3114 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3115 }
3116 return 0;
3117}
3118
3119unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3120 if (RetVT.SimpleTy != MVT::v2f64)
3121 return 0;
3122 if ((Subtarget->hasVSX())) {
3123 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3124 }
3125 return 0;
3126}
3127
3128unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3129 switch (VT.SimpleTy) {
3130 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
3131 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
3132 case MVT::f128: return fastEmit_ISD_FDIV_MVT_f128_rr(RetVT, Op0, Op1);
3133 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
3134 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
3135 default: return 0;
3136 }
3137}
3138
3139// FastEmit functions for ISD::FMAXNUM.
3140
3141unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3142 if (RetVT.SimpleTy != MVT::v4f32)
3143 return 0;
3144 if ((Subtarget->hasVSX())) {
3145 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3146 }
3147 return 0;
3148}
3149
3150unsigned fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3151 if (RetVT.SimpleTy != MVT::v2f64)
3152 return 0;
3153 if ((Subtarget->hasVSX())) {
3154 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3155 }
3156 return 0;
3157}
3158
3159unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3160 switch (VT.SimpleTy) {
3161 case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
3162 case MVT::v2f64: return fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
3163 default: return 0;
3164 }
3165}
3166
3167// FastEmit functions for ISD::FMAXNUM_IEEE.
3168
3169unsigned fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3170 if (RetVT.SimpleTy != MVT::f64)
3171 return 0;
3172 if ((Subtarget->hasVSX())) {
3173 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3174 }
3175 return 0;
3176}
3177
3178unsigned fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3179 switch (VT.SimpleTy) {
3180 case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
3181 default: return 0;
3182 }
3183}
3184
3185// FastEmit functions for ISD::FMINNUM.
3186
3187unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3188 if (RetVT.SimpleTy != MVT::v4f32)
3189 return 0;
3190 if ((Subtarget->hasVSX())) {
3191 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3192 }
3193 return 0;
3194}
3195
3196unsigned fastEmit_ISD_FMINNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3197 if (RetVT.SimpleTy != MVT::v2f64)
3198 return 0;
3199 if ((Subtarget->hasVSX())) {
3200 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3201 }
3202 return 0;
3203}
3204
3205unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3206 switch (VT.SimpleTy) {
3207 case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
3208 case MVT::v2f64: return fastEmit_ISD_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
3209 default: return 0;
3210 }
3211}
3212
3213// FastEmit functions for ISD::FMINNUM_IEEE.
3214
3215unsigned fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3216 if (RetVT.SimpleTy != MVT::f64)
3217 return 0;
3218 if ((Subtarget->hasVSX())) {
3219 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3220 }
3221 return 0;
3222}
3223
3224unsigned fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3225 switch (VT.SimpleTy) {
3226 case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
3227 default: return 0;
3228 }
3229}
3230
3231// FastEmit functions for ISD::FMUL.
3232
3233unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3234 if (RetVT.SimpleTy != MVT::f32)
3235 return 0;
3236 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3237 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3238 }
3239 if ((Subtarget->hasSPE())) {
3240 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSMUL, RC: &PPC::GPRCRegClass, Op0, Op1);
3241 }
3242 if ((Subtarget->hasFPU())) {
3243 return fastEmitInst_rr(MachineInstOpcode: PPC::FMULS, RC: &PPC::F4RCRegClass, Op0, Op1);
3244 }
3245 return 0;
3246}
3247
3248unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3249 if (RetVT.SimpleTy != MVT::f64)
3250 return 0;
3251 if ((Subtarget->hasVSX())) {
3252 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3253 }
3254 if ((Subtarget->hasSPE())) {
3255 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDMUL, RC: &PPC::SPERCRegClass, Op0, Op1);
3256 }
3257 if ((Subtarget->hasFPU())) {
3258 return fastEmitInst_rr(MachineInstOpcode: PPC::FMUL, RC: &PPC::F8RCRegClass, Op0, Op1);
3259 }
3260 return 0;
3261}
3262
3263unsigned fastEmit_ISD_FMUL_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3264 if (RetVT.SimpleTy != MVT::f128)
3265 return 0;
3266 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3267 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3268 }
3269 return 0;
3270}
3271
3272unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3273 if (RetVT.SimpleTy != MVT::v4f32)
3274 return 0;
3275 if ((Subtarget->hasVSX())) {
3276 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3277 }
3278 return 0;
3279}
3280
3281unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3282 if (RetVT.SimpleTy != MVT::v2f64)
3283 return 0;
3284 if ((Subtarget->hasVSX())) {
3285 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3286 }
3287 return 0;
3288}
3289
3290unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3291 switch (VT.SimpleTy) {
3292 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
3293 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
3294 case MVT::f128: return fastEmit_ISD_FMUL_MVT_f128_rr(RetVT, Op0, Op1);
3295 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
3296 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
3297 default: return 0;
3298 }
3299}
3300
3301// FastEmit functions for ISD::FSUB.
3302
3303unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3304 if (RetVT.SimpleTy != MVT::f32)
3305 return 0;
3306 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3307 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3308 }
3309 if ((Subtarget->hasSPE())) {
3310 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSSUB, RC: &PPC::GPRCRegClass, Op0, Op1);
3311 }
3312 if ((Subtarget->hasFPU())) {
3313 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUBS, RC: &PPC::F4RCRegClass, Op0, Op1);
3314 }
3315 return 0;
3316}
3317
3318unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3319 if (RetVT.SimpleTy != MVT::f64)
3320 return 0;
3321 if ((Subtarget->hasVSX())) {
3322 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3323 }
3324 if ((Subtarget->hasSPE())) {
3325 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDSUB, RC: &PPC::SPERCRegClass, Op0, Op1);
3326 }
3327 if ((Subtarget->hasFPU())) {
3328 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUB, RC: &PPC::F8RCRegClass, Op0, Op1);
3329 }
3330 return 0;
3331}
3332
3333unsigned fastEmit_ISD_FSUB_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3334 if (RetVT.SimpleTy != MVT::f128)
3335 return 0;
3336 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3337 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3338 }
3339 return 0;
3340}
3341
3342unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3343 if (RetVT.SimpleTy != MVT::v4f32)
3344 return 0;
3345 if ((Subtarget->hasVSX())) {
3346 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3347 }
3348 if ((Subtarget->hasAltivec())) {
3349 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBFP, RC: &PPC::VRRCRegClass, Op0, Op1);
3350 }
3351 return 0;
3352}
3353
3354unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3355 if (RetVT.SimpleTy != MVT::v2f64)
3356 return 0;
3357 if ((Subtarget->hasVSX())) {
3358 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3359 }
3360 return 0;
3361}
3362
3363unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3364 switch (VT.SimpleTy) {
3365 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
3366 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
3367 case MVT::f128: return fastEmit_ISD_FSUB_MVT_f128_rr(RetVT, Op0, Op1);
3368 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
3369 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
3370 default: return 0;
3371 }
3372}
3373
3374// FastEmit functions for ISD::MUL.
3375
3376unsigned fastEmit_ISD_MUL_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3377 if (RetVT.SimpleTy != MVT::i1)
3378 return 0;
3379 return fastEmitInst_rr(MachineInstOpcode: PPC::CRAND, RC: &PPC::CRBITRCRegClass, Op0, Op1);
3380}
3381
3382unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3383 if (RetVT.SimpleTy != MVT::i32)
3384 return 0;
3385 return fastEmitInst_rr(MachineInstOpcode: PPC::MULLW, RC: &PPC::GPRCRegClass, Op0, Op1);
3386}
3387
3388unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3389 if (RetVT.SimpleTy != MVT::i64)
3390 return 0;
3391 return fastEmitInst_rr(MachineInstOpcode: PPC::MULLD, RC: &PPC::G8RCRegClass, Op0, Op1);
3392}
3393
3394unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3395 if (RetVT.SimpleTy != MVT::v4i32)
3396 return 0;
3397 if ((Subtarget->hasP8Altivec())) {
3398 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULUWM, RC: &PPC::VRRCRegClass, Op0, Op1);
3399 }
3400 return 0;
3401}
3402
3403unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3404 if (RetVT.SimpleTy != MVT::v2i64)
3405 return 0;
3406 if ((Subtarget->isISA3_1())) {
3407 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULLD, RC: &PPC::VRRCRegClass, Op0, Op1);
3408 }
3409 return 0;
3410}
3411
3412unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3413 switch (VT.SimpleTy) {
3414 case MVT::i1: return fastEmit_ISD_MUL_MVT_i1_rr(RetVT, Op0, Op1);
3415 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
3416 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
3417 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
3418 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
3419 default: return 0;
3420 }
3421}
3422
3423// FastEmit functions for ISD::MULHS.
3424
3425unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3426 if (RetVT.SimpleTy != MVT::i32)
3427 return 0;
3428 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHW, RC: &PPC::GPRCRegClass, Op0, Op1);
3429}
3430
3431unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3432 if (RetVT.SimpleTy != MVT::i64)
3433 return 0;
3434 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHD, RC: &PPC::G8RCRegClass, Op0, Op1);
3435}
3436
3437unsigned fastEmit_ISD_MULHS_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3438 if (RetVT.SimpleTy != MVT::v4i32)
3439 return 0;
3440 if ((Subtarget->isISA3_1())) {
3441 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3442 }
3443 return 0;
3444}
3445
3446unsigned fastEmit_ISD_MULHS_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3447 if (RetVT.SimpleTy != MVT::v2i64)
3448 return 0;
3449 if ((Subtarget->isISA3_1())) {
3450 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHSD, RC: &PPC::VRRCRegClass, Op0, Op1);
3451 }
3452 return 0;
3453}
3454
3455unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3456 switch (VT.SimpleTy) {
3457 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1);
3458 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1);
3459 case MVT::v4i32: return fastEmit_ISD_MULHS_MVT_v4i32_rr(RetVT, Op0, Op1);
3460 case MVT::v2i64: return fastEmit_ISD_MULHS_MVT_v2i64_rr(RetVT, Op0, Op1);
3461 default: return 0;
3462 }
3463}
3464
3465// FastEmit functions for ISD::MULHU.
3466
3467unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3468 if (RetVT.SimpleTy != MVT::i32)
3469 return 0;
3470 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHWU, RC: &PPC::GPRCRegClass, Op0, Op1);
3471}
3472
3473unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3474 if (RetVT.SimpleTy != MVT::i64)
3475 return 0;
3476 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHDU, RC: &PPC::G8RCRegClass, Op0, Op1);
3477}
3478
3479unsigned fastEmit_ISD_MULHU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3480 if (RetVT.SimpleTy != MVT::v4i32)
3481 return 0;
3482 if ((Subtarget->isISA3_1())) {
3483 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHUW, RC: &PPC::VRRCRegClass, Op0, Op1);
3484 }
3485 return 0;
3486}
3487
3488unsigned fastEmit_ISD_MULHU_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3489 if (RetVT.SimpleTy != MVT::v2i64)
3490 return 0;
3491 if ((Subtarget->isISA3_1())) {
3492 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHUD, RC: &PPC::VRRCRegClass, Op0, Op1);
3493 }
3494 return 0;
3495}
3496
3497unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3498 switch (VT.SimpleTy) {
3499 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1);
3500 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1);
3501 case MVT::v4i32: return fastEmit_ISD_MULHU_MVT_v4i32_rr(RetVT, Op0, Op1);
3502 case MVT::v2i64: return fastEmit_ISD_MULHU_MVT_v2i64_rr(RetVT, Op0, Op1);
3503 default: return 0;
3504 }
3505}
3506
3507// FastEmit functions for ISD::OR.
3508
3509unsigned fastEmit_ISD_OR_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3510 if (RetVT.SimpleTy != MVT::i1)
3511 return 0;
3512 return fastEmitInst_rr(MachineInstOpcode: PPC::CROR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
3513}
3514
3515unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3516 if (RetVT.SimpleTy != MVT::i32)
3517 return 0;
3518 return fastEmitInst_rr(MachineInstOpcode: PPC::OR, RC: &PPC::GPRCRegClass, Op0, Op1);
3519}
3520
3521unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3522 if (RetVT.SimpleTy != MVT::i64)
3523 return 0;
3524 return fastEmitInst_rr(MachineInstOpcode: PPC::OR8, RC: &PPC::G8RCRegClass, Op0, Op1);
3525}
3526
3527unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3528 if (RetVT.SimpleTy != MVT::v4i32)
3529 return 0;
3530 if ((Subtarget->hasVSX())) {
3531 return fastEmitInst_rr(MachineInstOpcode: PPC::XXLOR, RC: &PPC::VSRCRegClass, Op0, Op1);
3532 }
3533 if ((Subtarget->hasAltivec())) {
3534 return fastEmitInst_rr(MachineInstOpcode: PPC::VOR, RC: &PPC::VRRCRegClass, Op0, Op1);
3535 }
3536 return 0;
3537}
3538
3539unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3540 switch (VT.SimpleTy) {
3541 case MVT::i1: return fastEmit_ISD_OR_MVT_i1_rr(RetVT, Op0, Op1);
3542 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
3543 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
3544 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
3545 default: return 0;
3546 }
3547}
3548
3549// FastEmit functions for ISD::ROTL.
3550
3551unsigned fastEmit_ISD_ROTL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3552 if (RetVT.SimpleTy != MVT::v16i8)
3553 return 0;
3554 if ((Subtarget->hasAltivec())) {
3555 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLB, RC: &PPC::VRRCRegClass, Op0, Op1);
3556 }
3557 return 0;
3558}
3559
3560unsigned fastEmit_ISD_ROTL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3561 if (RetVT.SimpleTy != MVT::v8i16)
3562 return 0;
3563 if ((Subtarget->hasAltivec())) {
3564 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLH, RC: &PPC::VRRCRegClass, Op0, Op1);
3565 }
3566 return 0;
3567}
3568
3569unsigned fastEmit_ISD_ROTL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3570 if (RetVT.SimpleTy != MVT::v4i32)
3571 return 0;
3572 if ((Subtarget->hasAltivec())) {
3573 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLW, RC: &PPC::VRRCRegClass, Op0, Op1);
3574 }
3575 return 0;
3576}
3577
3578unsigned fastEmit_ISD_ROTL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3579 if (RetVT.SimpleTy != MVT::v2i64)
3580 return 0;
3581 if ((Subtarget->hasP8Altivec())) {
3582 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLD, RC: &PPC::VRRCRegClass, Op0, Op1);
3583 }
3584 return 0;
3585}
3586
3587unsigned fastEmit_ISD_ROTL_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3588 if (RetVT.SimpleTy != MVT::v1i128)
3589 return 0;
3590 if ((Subtarget->isISA3_1())) {
3591 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLQ, RC: &PPC::VRRCRegClass, Op0, Op1);
3592 }
3593 return 0;
3594}
3595
3596unsigned fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3597 switch (VT.SimpleTy) {
3598 case MVT::v16i8: return fastEmit_ISD_ROTL_MVT_v16i8_rr(RetVT, Op0, Op1);
3599 case MVT::v8i16: return fastEmit_ISD_ROTL_MVT_v8i16_rr(RetVT, Op0, Op1);
3600 case MVT::v4i32: return fastEmit_ISD_ROTL_MVT_v4i32_rr(RetVT, Op0, Op1);
3601 case MVT::v2i64: return fastEmit_ISD_ROTL_MVT_v2i64_rr(RetVT, Op0, Op1);
3602 case MVT::v1i128: return fastEmit_ISD_ROTL_MVT_v1i128_rr(RetVT, Op0, Op1);
3603 default: return 0;
3604 }
3605}
3606
3607// FastEmit functions for ISD::SADDSAT.
3608
3609unsigned fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3610 if (RetVT.SimpleTy != MVT::v16i8)
3611 return 0;
3612 if ((Subtarget->hasAltivec())) {
3613 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDSBS, RC: &PPC::VRRCRegClass, Op0, Op1);
3614 }
3615 return 0;
3616}
3617
3618unsigned fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3619 if (RetVT.SimpleTy != MVT::v8i16)
3620 return 0;
3621 if ((Subtarget->hasAltivec())) {
3622 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDSHS, RC: &PPC::VRRCRegClass, Op0, Op1);
3623 }
3624 return 0;
3625}
3626
3627unsigned fastEmit_ISD_SADDSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3628 if (RetVT.SimpleTy != MVT::v4i32)
3629 return 0;
3630 if ((Subtarget->hasAltivec())) {
3631 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDSWS, RC: &PPC::VRRCRegClass, Op0, Op1);
3632 }
3633 return 0;
3634}
3635
3636unsigned fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3637 switch (VT.SimpleTy) {
3638 case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
3639 case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
3640 case MVT::v4i32: return fastEmit_ISD_SADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
3641 default: return 0;
3642 }
3643}
3644
3645// FastEmit functions for ISD::SDIV.
3646
3647unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3648 if (RetVT.SimpleTy != MVT::i32)
3649 return 0;
3650 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVW, RC: &PPC::GPRCRegClass, Op0, Op1);
3651}
3652
3653unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3654 if (RetVT.SimpleTy != MVT::i64)
3655 return 0;
3656 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVD, RC: &PPC::G8RCRegClass, Op0, Op1);
3657}
3658
3659unsigned fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3660 if (RetVT.SimpleTy != MVT::v4i32)
3661 return 0;
3662 if ((Subtarget->isISA3_1())) {
3663 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3664 }
3665 return 0;
3666}
3667
3668unsigned fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3669 if (RetVT.SimpleTy != MVT::v2i64)
3670 return 0;
3671 if ((Subtarget->isISA3_1())) {
3672 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVSD, RC: &PPC::VRRCRegClass, Op0, Op1);
3673 }
3674 return 0;
3675}
3676
3677unsigned fastEmit_ISD_SDIV_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3678 if (RetVT.SimpleTy != MVT::v1i128)
3679 return 0;
3680 if ((Subtarget->isISA3_1())) {
3681 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVSQ, RC: &PPC::VRRCRegClass, Op0, Op1);
3682 }
3683 return 0;
3684}
3685
3686unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3687 switch (VT.SimpleTy) {
3688 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
3689 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
3690 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
3691 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
3692 case MVT::v1i128: return fastEmit_ISD_SDIV_MVT_v1i128_rr(RetVT, Op0, Op1);
3693 default: return 0;
3694 }
3695}
3696
3697// FastEmit functions for ISD::SHL.
3698
3699unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3700 if (RetVT.SimpleTy != MVT::i32)
3701 return 0;
3702 return fastEmitInst_rr(MachineInstOpcode: PPC::SLW, RC: &PPC::GPRCRegClass, Op0, Op1);
3703}
3704
3705unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3706 if (RetVT.SimpleTy != MVT::v16i8)
3707 return 0;
3708 if ((Subtarget->hasAltivec())) {
3709 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLB, RC: &PPC::VRRCRegClass, Op0, Op1);
3710 }
3711 return 0;
3712}
3713
3714unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3715 if (RetVT.SimpleTy != MVT::v8i16)
3716 return 0;
3717 if ((Subtarget->hasAltivec())) {
3718 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLH, RC: &PPC::VRRCRegClass, Op0, Op1);
3719 }
3720 return 0;
3721}
3722
3723unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3724 if (RetVT.SimpleTy != MVT::v4i32)
3725 return 0;
3726 if ((Subtarget->hasAltivec())) {
3727 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLW, RC: &PPC::VRRCRegClass, Op0, Op1);
3728 }
3729 return 0;
3730}
3731
3732unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3733 if (RetVT.SimpleTy != MVT::v2i64)
3734 return 0;
3735 if ((Subtarget->hasP8Altivec())) {
3736 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLD, RC: &PPC::VRRCRegClass, Op0, Op1);
3737 }
3738 return 0;
3739}
3740
3741unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3742 switch (VT.SimpleTy) {
3743 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
3744 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
3745 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
3746 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
3747 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
3748 default: return 0;
3749 }
3750}
3751
3752// FastEmit functions for ISD::SMAX.
3753
3754unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3755 if (RetVT.SimpleTy != MVT::v16i8)
3756 return 0;
3757 if ((Subtarget->hasAltivec())) {
3758 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXSB, RC: &PPC::VRRCRegClass, Op0, Op1);
3759 }
3760 return 0;
3761}
3762
3763unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3764 if (RetVT.SimpleTy != MVT::v8i16)
3765 return 0;
3766 if ((Subtarget->hasAltivec())) {
3767 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXSH, RC: &PPC::VRRCRegClass, Op0, Op1);
3768 }
3769 return 0;
3770}
3771
3772unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3773 if (RetVT.SimpleTy != MVT::v4i32)
3774 return 0;
3775 if ((Subtarget->hasAltivec())) {
3776 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3777 }
3778 return 0;
3779}
3780
3781unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3782 switch (VT.SimpleTy) {
3783 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
3784 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
3785 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
3786 default: return 0;
3787 }
3788}
3789
3790// FastEmit functions for ISD::SMIN.
3791
3792unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3793 if (RetVT.SimpleTy != MVT::v16i8)
3794 return 0;
3795 if ((Subtarget->hasAltivec())) {
3796 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINSB, RC: &PPC::VRRCRegClass, Op0, Op1);
3797 }
3798 return 0;
3799}
3800
3801unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3802 if (RetVT.SimpleTy != MVT::v8i16)
3803 return 0;
3804 if ((Subtarget->hasAltivec())) {
3805 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINSH, RC: &PPC::VRRCRegClass, Op0, Op1);
3806 }
3807 return 0;
3808}
3809
3810unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3811 if (RetVT.SimpleTy != MVT::v4i32)
3812 return 0;
3813 if ((Subtarget->hasAltivec())) {
3814 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3815 }
3816 return 0;
3817}
3818
3819unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3820 switch (VT.SimpleTy) {
3821 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
3822 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
3823 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
3824 default: return 0;
3825 }
3826}
3827
3828// FastEmit functions for ISD::SRA.
3829
3830unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3831 if (RetVT.SimpleTy != MVT::i32)
3832 return 0;
3833 return fastEmitInst_rr(MachineInstOpcode: PPC::SRAW, RC: &PPC::GPRCRegClass, Op0, Op1);
3834}
3835
3836unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3837 if (RetVT.SimpleTy != MVT::v16i8)
3838 return 0;
3839 if ((Subtarget->hasAltivec())) {
3840 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAB, RC: &PPC::VRRCRegClass, Op0, Op1);
3841 }
3842 return 0;
3843}
3844
3845unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3846 if (RetVT.SimpleTy != MVT::v8i16)
3847 return 0;
3848 if ((Subtarget->hasAltivec())) {
3849 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAH, RC: &PPC::VRRCRegClass, Op0, Op1);
3850 }
3851 return 0;
3852}
3853
3854unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3855 if (RetVT.SimpleTy != MVT::v4i32)
3856 return 0;
3857 if ((Subtarget->hasAltivec())) {
3858 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAW, RC: &PPC::VRRCRegClass, Op0, Op1);
3859 }
3860 return 0;
3861}
3862
3863unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3864 if (RetVT.SimpleTy != MVT::v2i64)
3865 return 0;
3866 if ((Subtarget->hasP8Altivec())) {
3867 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAD, RC: &PPC::VRRCRegClass, Op0, Op1);
3868 }
3869 return 0;
3870}
3871
3872unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3873 switch (VT.SimpleTy) {
3874 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
3875 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
3876 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
3877 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
3878 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
3879 default: return 0;
3880 }
3881}
3882
3883// FastEmit functions for ISD::SREM.
3884
3885unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3886 if (RetVT.SimpleTy != MVT::i32)
3887 return 0;
3888 if ((Subtarget->isISA3_0())) {
3889 return fastEmitInst_rr(MachineInstOpcode: PPC::MODSW, RC: &PPC::GPRCRegClass, Op0, Op1);
3890 }
3891 return 0;
3892}
3893
3894unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3895 if (RetVT.SimpleTy != MVT::i64)
3896 return 0;
3897 if ((Subtarget->isISA3_0())) {
3898 return fastEmitInst_rr(MachineInstOpcode: PPC::MODSD, RC: &PPC::G8RCRegClass, Op0, Op1);
3899 }
3900 return 0;
3901}
3902
3903unsigned fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3904 if (RetVT.SimpleTy != MVT::v4i32)
3905 return 0;
3906 if ((Subtarget->isISA3_1())) {
3907 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3908 }
3909 return 0;
3910}
3911
3912unsigned fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3913 if (RetVT.SimpleTy != MVT::v2i64)
3914 return 0;
3915 if ((Subtarget->isISA3_1())) {
3916 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODSD, RC: &PPC::VRRCRegClass, Op0, Op1);
3917 }
3918 return 0;
3919}
3920
3921unsigned fastEmit_ISD_SREM_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3922 if (RetVT.SimpleTy != MVT::v1i128)
3923 return 0;
3924 if ((Subtarget->isISA3_1())) {
3925 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODSQ, RC: &PPC::VRRCRegClass, Op0, Op1);
3926 }
3927 return 0;
3928}
3929
3930unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3931 switch (VT.SimpleTy) {
3932 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
3933 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
3934 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1);
3935 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1);
3936 case MVT::v1i128: return fastEmit_ISD_SREM_MVT_v1i128_rr(RetVT, Op0, Op1);
3937 default: return 0;
3938 }
3939}
3940
3941// FastEmit functions for ISD::SRL.
3942
3943unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3944 if (RetVT.SimpleTy != MVT::i32)
3945 return 0;
3946 return fastEmitInst_rr(MachineInstOpcode: PPC::SRW, RC: &PPC::GPRCRegClass, Op0, Op1);
3947}
3948
3949unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3950 if (RetVT.SimpleTy != MVT::v16i8)
3951 return 0;
3952 if ((Subtarget->hasAltivec())) {
3953 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRB, RC: &PPC::VRRCRegClass, Op0, Op1);
3954 }
3955 return 0;
3956}
3957
3958unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3959 if (RetVT.SimpleTy != MVT::v8i16)
3960 return 0;
3961 if ((Subtarget->hasAltivec())) {
3962 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRH, RC: &PPC::VRRCRegClass, Op0, Op1);
3963 }
3964 return 0;
3965}
3966
3967unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3968 if (RetVT.SimpleTy != MVT::v4i32)
3969 return 0;
3970 if ((Subtarget->hasAltivec())) {
3971 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRW, RC: &PPC::VRRCRegClass, Op0, Op1);
3972 }
3973 return 0;
3974}
3975
3976unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3977 if (RetVT.SimpleTy != MVT::v2i64)
3978 return 0;
3979 if ((Subtarget->hasP8Altivec())) {
3980 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRD, RC: &PPC::VRRCRegClass, Op0, Op1);
3981 }
3982 return 0;
3983}
3984
3985unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
3986 switch (VT.SimpleTy) {
3987 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
3988 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
3989 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
3990 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
3991 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
3992 default: return 0;
3993 }
3994}
3995
3996// FastEmit functions for ISD::SSUBSAT.
3997
3998unsigned fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
3999 if (RetVT.SimpleTy != MVT::v16i8)
4000 return 0;
4001 if ((Subtarget->hasAltivec())) {
4002 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBSBS, RC: &PPC::VRRCRegClass, Op0, Op1);
4003 }
4004 return 0;
4005}
4006
4007unsigned fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4008 if (RetVT.SimpleTy != MVT::v8i16)
4009 return 0;
4010 if ((Subtarget->hasAltivec())) {
4011 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBSHS, RC: &PPC::VRRCRegClass, Op0, Op1);
4012 }
4013 return 0;
4014}
4015
4016unsigned fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4017 if (RetVT.SimpleTy != MVT::v4i32)
4018 return 0;
4019 if ((Subtarget->hasAltivec())) {
4020 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBSWS, RC: &PPC::VRRCRegClass, Op0, Op1);
4021 }
4022 return 0;
4023}
4024
4025unsigned fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4026 switch (VT.SimpleTy) {
4027 case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
4028 case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
4029 case MVT::v4i32: return fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
4030 default: return 0;
4031 }
4032}
4033
4034// FastEmit functions for ISD::STRICT_FADD.
4035
4036unsigned fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4037 if (RetVT.SimpleTy != MVT::f32)
4038 return 0;
4039 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4040 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4041 }
4042 if ((Subtarget->hasSPE())) {
4043 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSADD, RC: &PPC::GPRCRegClass, Op0, Op1);
4044 }
4045 if ((Subtarget->hasFPU())) {
4046 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDS, RC: &PPC::F4RCRegClass, Op0, Op1);
4047 }
4048 return 0;
4049}
4050
4051unsigned fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4052 if (RetVT.SimpleTy != MVT::f64)
4053 return 0;
4054 if ((Subtarget->hasVSX())) {
4055 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4056 }
4057 if ((Subtarget->hasSPE())) {
4058 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDADD, RC: &PPC::SPERCRegClass, Op0, Op1);
4059 }
4060 if ((Subtarget->hasFPU())) {
4061 return fastEmitInst_rr(MachineInstOpcode: PPC::FADD, RC: &PPC::F8RCRegClass, Op0, Op1);
4062 }
4063 return 0;
4064}
4065
4066unsigned fastEmit_ISD_STRICT_FADD_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4067 if (RetVT.SimpleTy != MVT::f128)
4068 return 0;
4069 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4070 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4071 }
4072 return 0;
4073}
4074
4075unsigned fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4076 if (RetVT.SimpleTy != MVT::v4f32)
4077 return 0;
4078 if ((Subtarget->hasVSX())) {
4079 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4080 }
4081 return 0;
4082}
4083
4084unsigned fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4085 if (RetVT.SimpleTy != MVT::v2f64)
4086 return 0;
4087 if ((Subtarget->hasVSX())) {
4088 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4089 }
4090 return 0;
4091}
4092
4093unsigned fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4094 switch (VT.SimpleTy) {
4095 case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1);
4096 case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1);
4097 case MVT::f128: return fastEmit_ISD_STRICT_FADD_MVT_f128_rr(RetVT, Op0, Op1);
4098 case MVT::v4f32: return fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
4099 case MVT::v2f64: return fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
4100 default: return 0;
4101 }
4102}
4103
4104// FastEmit functions for ISD::STRICT_FDIV.
4105
4106unsigned fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4107 if (RetVT.SimpleTy != MVT::f32)
4108 return 0;
4109 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4110 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4111 }
4112 if ((Subtarget->hasSPE())) {
4113 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSDIV, RC: &PPC::GPRCRegClass, Op0, Op1);
4114 }
4115 if ((Subtarget->hasFPU())) {
4116 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIVS, RC: &PPC::F4RCRegClass, Op0, Op1);
4117 }
4118 return 0;
4119}
4120
4121unsigned fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4122 if (RetVT.SimpleTy != MVT::f64)
4123 return 0;
4124 if ((Subtarget->hasVSX())) {
4125 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4126 }
4127 if ((Subtarget->hasSPE())) {
4128 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDDIV, RC: &PPC::SPERCRegClass, Op0, Op1);
4129 }
4130 if ((Subtarget->hasFPU())) {
4131 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIV, RC: &PPC::F8RCRegClass, Op0, Op1);
4132 }
4133 return 0;
4134}
4135
4136unsigned fastEmit_ISD_STRICT_FDIV_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4137 if (RetVT.SimpleTy != MVT::f128)
4138 return 0;
4139 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4140 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4141 }
4142 return 0;
4143}
4144
4145unsigned fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4146 if (RetVT.SimpleTy != MVT::v4f32)
4147 return 0;
4148 if ((Subtarget->hasVSX())) {
4149 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4150 }
4151 return 0;
4152}
4153
4154unsigned fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4155 if (RetVT.SimpleTy != MVT::v2f64)
4156 return 0;
4157 if ((Subtarget->hasVSX())) {
4158 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4159 }
4160 return 0;
4161}
4162
4163unsigned fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4164 switch (VT.SimpleTy) {
4165 case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
4166 case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
4167 case MVT::f128: return fastEmit_ISD_STRICT_FDIV_MVT_f128_rr(RetVT, Op0, Op1);
4168 case MVT::v4f32: return fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
4169 case MVT::v2f64: return fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
4170 default: return 0;
4171 }
4172}
4173
4174// FastEmit functions for ISD::STRICT_FMAXNUM.
4175
4176unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4177 if (RetVT.SimpleTy != MVT::v4f32)
4178 return 0;
4179 if ((Subtarget->hasVSX())) {
4180 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4181 }
4182 return 0;
4183}
4184
4185unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4186 if (RetVT.SimpleTy != MVT::v2f64)
4187 return 0;
4188 if ((Subtarget->hasVSX())) {
4189 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4190 }
4191 return 0;
4192}
4193
4194unsigned fastEmit_ISD_STRICT_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4195 switch (VT.SimpleTy) {
4196 case MVT::v4f32: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
4197 case MVT::v2f64: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
4198 default: return 0;
4199 }
4200}
4201
4202// FastEmit functions for ISD::STRICT_FMINNUM.
4203
4204unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4205 if (RetVT.SimpleTy != MVT::v4f32)
4206 return 0;
4207 if ((Subtarget->hasVSX())) {
4208 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4209 }
4210 return 0;
4211}
4212
4213unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4214 if (RetVT.SimpleTy != MVT::v2f64)
4215 return 0;
4216 if ((Subtarget->hasVSX())) {
4217 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4218 }
4219 return 0;
4220}
4221
4222unsigned fastEmit_ISD_STRICT_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4223 switch (VT.SimpleTy) {
4224 case MVT::v4f32: return fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
4225 case MVT::v2f64: return fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
4226 default: return 0;
4227 }
4228}
4229
4230// FastEmit functions for ISD::STRICT_FMUL.
4231
4232unsigned fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4233 if (RetVT.SimpleTy != MVT::f32)
4234 return 0;
4235 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4236 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4237 }
4238 if ((Subtarget->hasSPE())) {
4239 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSMUL, RC: &PPC::GPRCRegClass, Op0, Op1);
4240 }
4241 if ((Subtarget->hasFPU())) {
4242 return fastEmitInst_rr(MachineInstOpcode: PPC::FMULS, RC: &PPC::F4RCRegClass, Op0, Op1);
4243 }
4244 return 0;
4245}
4246
4247unsigned fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4248 if (RetVT.SimpleTy != MVT::f64)
4249 return 0;
4250 if ((Subtarget->hasVSX())) {
4251 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4252 }
4253 if ((Subtarget->hasSPE())) {
4254 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDMUL, RC: &PPC::SPERCRegClass, Op0, Op1);
4255 }
4256 if ((Subtarget->hasFPU())) {
4257 return fastEmitInst_rr(MachineInstOpcode: PPC::FMUL, RC: &PPC::F8RCRegClass, Op0, Op1);
4258 }
4259 return 0;
4260}
4261
4262unsigned fastEmit_ISD_STRICT_FMUL_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4263 if (RetVT.SimpleTy != MVT::f128)
4264 return 0;
4265 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4266 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4267 }
4268 return 0;
4269}
4270
4271unsigned fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4272 if (RetVT.SimpleTy != MVT::v4f32)
4273 return 0;
4274 if ((Subtarget->hasVSX())) {
4275 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4276 }
4277 return 0;
4278}
4279
4280unsigned fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4281 if (RetVT.SimpleTy != MVT::v2f64)
4282 return 0;
4283 if ((Subtarget->hasVSX())) {
4284 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4285 }
4286 return 0;
4287}
4288
4289unsigned fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4290 switch (VT.SimpleTy) {
4291 case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
4292 case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
4293 case MVT::f128: return fastEmit_ISD_STRICT_FMUL_MVT_f128_rr(RetVT, Op0, Op1);
4294 case MVT::v4f32: return fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
4295 case MVT::v2f64: return fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
4296 default: return 0;
4297 }
4298}
4299
4300// FastEmit functions for ISD::STRICT_FSUB.
4301
4302unsigned fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4303 if (RetVT.SimpleTy != MVT::f32)
4304 return 0;
4305 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4306 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4307 }
4308 if ((Subtarget->hasSPE())) {
4309 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSSUB, RC: &PPC::GPRCRegClass, Op0, Op1);
4310 }
4311 if ((Subtarget->hasFPU())) {
4312 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUBS, RC: &PPC::F4RCRegClass, Op0, Op1);
4313 }
4314 return 0;
4315}
4316
4317unsigned fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4318 if (RetVT.SimpleTy != MVT::f64)
4319 return 0;
4320 if ((Subtarget->hasVSX())) {
4321 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4322 }
4323 if ((Subtarget->hasSPE())) {
4324 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDSUB, RC: &PPC::SPERCRegClass, Op0, Op1);
4325 }
4326 if ((Subtarget->hasFPU())) {
4327 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUB, RC: &PPC::F8RCRegClass, Op0, Op1);
4328 }
4329 return 0;
4330}
4331
4332unsigned fastEmit_ISD_STRICT_FSUB_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4333 if (RetVT.SimpleTy != MVT::f128)
4334 return 0;
4335 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4336 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4337 }
4338 return 0;
4339}
4340
4341unsigned fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4342 if (RetVT.SimpleTy != MVT::v4f32)
4343 return 0;
4344 if ((Subtarget->hasVSX())) {
4345 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4346 }
4347 return 0;
4348}
4349
4350unsigned fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4351 if (RetVT.SimpleTy != MVT::v2f64)
4352 return 0;
4353 if ((Subtarget->hasVSX())) {
4354 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4355 }
4356 return 0;
4357}
4358
4359unsigned fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4360 switch (VT.SimpleTy) {
4361 case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
4362 case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
4363 case MVT::f128: return fastEmit_ISD_STRICT_FSUB_MVT_f128_rr(RetVT, Op0, Op1);
4364 case MVT::v4f32: return fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
4365 case MVT::v2f64: return fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
4366 default: return 0;
4367 }
4368}
4369
4370// FastEmit functions for ISD::SUB.
4371
4372unsigned fastEmit_ISD_SUB_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4373 if (RetVT.SimpleTy != MVT::i1)
4374 return 0;
4375 return fastEmitInst_rr(MachineInstOpcode: PPC::CRXOR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
4376}
4377
4378unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4379 if (RetVT.SimpleTy != MVT::v16i8)
4380 return 0;
4381 if ((Subtarget->hasAltivec())) {
4382 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUBM, RC: &PPC::VRRCRegClass, Op0, Op1);
4383 }
4384 return 0;
4385}
4386
4387unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4388 if (RetVT.SimpleTy != MVT::v8i16)
4389 return 0;
4390 if ((Subtarget->hasAltivec())) {
4391 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUHM, RC: &PPC::VRRCRegClass, Op0, Op1);
4392 }
4393 return 0;
4394}
4395
4396unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4397 if (RetVT.SimpleTy != MVT::v4i32)
4398 return 0;
4399 if ((Subtarget->hasAltivec())) {
4400 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUWM, RC: &PPC::VRRCRegClass, Op0, Op1);
4401 }
4402 return 0;
4403}
4404
4405unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4406 if (RetVT.SimpleTy != MVT::v2i64)
4407 return 0;
4408 if ((Subtarget->hasP8Altivec())) {
4409 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUDM, RC: &PPC::VRRCRegClass, Op0, Op1);
4410 }
4411 return 0;
4412}
4413
4414unsigned fastEmit_ISD_SUB_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4415 if (RetVT.SimpleTy != MVT::v1i128)
4416 return 0;
4417 if ((Subtarget->hasP8Altivec())) {
4418 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUQM, RC: &PPC::VRRCRegClass, Op0, Op1);
4419 }
4420 return 0;
4421}
4422
4423unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4424 switch (VT.SimpleTy) {
4425 case MVT::i1: return fastEmit_ISD_SUB_MVT_i1_rr(RetVT, Op0, Op1);
4426 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
4427 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
4428 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
4429 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
4430 case MVT::v1i128: return fastEmit_ISD_SUB_MVT_v1i128_rr(RetVT, Op0, Op1);
4431 default: return 0;
4432 }
4433}
4434
4435// FastEmit functions for ISD::UADDSAT.
4436
4437unsigned fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4438 if (RetVT.SimpleTy != MVT::v16i8)
4439 return 0;
4440 if ((Subtarget->hasAltivec())) {
4441 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUBS, RC: &PPC::VRRCRegClass, Op0, Op1);
4442 }
4443 return 0;
4444}
4445
4446unsigned fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4447 if (RetVT.SimpleTy != MVT::v8i16)
4448 return 0;
4449 if ((Subtarget->hasAltivec())) {
4450 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUHS, RC: &PPC::VRRCRegClass, Op0, Op1);
4451 }
4452 return 0;
4453}
4454
4455unsigned fastEmit_ISD_UADDSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4456 if (RetVT.SimpleTy != MVT::v4i32)
4457 return 0;
4458 if ((Subtarget->hasAltivec())) {
4459 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUWS, RC: &PPC::VRRCRegClass, Op0, Op1);
4460 }
4461 return 0;
4462}
4463
4464unsigned fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4465 switch (VT.SimpleTy) {
4466 case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
4467 case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
4468 case MVT::v4i32: return fastEmit_ISD_UADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
4469 default: return 0;
4470 }
4471}
4472
4473// FastEmit functions for ISD::UDIV.
4474
4475unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4476 if (RetVT.SimpleTy != MVT::i32)
4477 return 0;
4478 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVWU, RC: &PPC::GPRCRegClass, Op0, Op1);
4479}
4480
4481unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4482 if (RetVT.SimpleTy != MVT::i64)
4483 return 0;
4484 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVDU, RC: &PPC::G8RCRegClass, Op0, Op1);
4485}
4486
4487unsigned fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4488 if (RetVT.SimpleTy != MVT::v4i32)
4489 return 0;
4490 if ((Subtarget->isISA3_1())) {
4491 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4492 }
4493 return 0;
4494}
4495
4496unsigned fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4497 if (RetVT.SimpleTy != MVT::v2i64)
4498 return 0;
4499 if ((Subtarget->isISA3_1())) {
4500 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVUD, RC: &PPC::VRRCRegClass, Op0, Op1);
4501 }
4502 return 0;
4503}
4504
4505unsigned fastEmit_ISD_UDIV_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4506 if (RetVT.SimpleTy != MVT::v1i128)
4507 return 0;
4508 if ((Subtarget->isISA3_1())) {
4509 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVUQ, RC: &PPC::VRRCRegClass, Op0, Op1);
4510 }
4511 return 0;
4512}
4513
4514unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4515 switch (VT.SimpleTy) {
4516 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
4517 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
4518 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
4519 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
4520 case MVT::v1i128: return fastEmit_ISD_UDIV_MVT_v1i128_rr(RetVT, Op0, Op1);
4521 default: return 0;
4522 }
4523}
4524
4525// FastEmit functions for ISD::UMAX.
4526
4527unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4528 if (RetVT.SimpleTy != MVT::v16i8)
4529 return 0;
4530 if ((Subtarget->hasAltivec())) {
4531 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXUB, RC: &PPC::VRRCRegClass, Op0, Op1);
4532 }
4533 return 0;
4534}
4535
4536unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4537 if (RetVT.SimpleTy != MVT::v8i16)
4538 return 0;
4539 if ((Subtarget->hasAltivec())) {
4540 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXUH, RC: &PPC::VRRCRegClass, Op0, Op1);
4541 }
4542 return 0;
4543}
4544
4545unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4546 if (RetVT.SimpleTy != MVT::v4i32)
4547 return 0;
4548 if ((Subtarget->hasAltivec())) {
4549 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4550 }
4551 return 0;
4552}
4553
4554unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4555 switch (VT.SimpleTy) {
4556 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
4557 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
4558 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
4559 default: return 0;
4560 }
4561}
4562
4563// FastEmit functions for ISD::UMIN.
4564
4565unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4566 if (RetVT.SimpleTy != MVT::v16i8)
4567 return 0;
4568 if ((Subtarget->hasAltivec())) {
4569 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINUB, RC: &PPC::VRRCRegClass, Op0, Op1);
4570 }
4571 return 0;
4572}
4573
4574unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4575 if (RetVT.SimpleTy != MVT::v8i16)
4576 return 0;
4577 if ((Subtarget->hasAltivec())) {
4578 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINUH, RC: &PPC::VRRCRegClass, Op0, Op1);
4579 }
4580 return 0;
4581}
4582
4583unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4584 if (RetVT.SimpleTy != MVT::v4i32)
4585 return 0;
4586 if ((Subtarget->hasAltivec())) {
4587 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4588 }
4589 return 0;
4590}
4591
4592unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4593 switch (VT.SimpleTy) {
4594 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
4595 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
4596 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
4597 default: return 0;
4598 }
4599}
4600
4601// FastEmit functions for ISD::UREM.
4602
4603unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4604 if (RetVT.SimpleTy != MVT::i32)
4605 return 0;
4606 if ((Subtarget->isISA3_0())) {
4607 return fastEmitInst_rr(MachineInstOpcode: PPC::MODUW, RC: &PPC::GPRCRegClass, Op0, Op1);
4608 }
4609 return 0;
4610}
4611
4612unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4613 if (RetVT.SimpleTy != MVT::i64)
4614 return 0;
4615 if ((Subtarget->isISA3_0())) {
4616 return fastEmitInst_rr(MachineInstOpcode: PPC::MODUD, RC: &PPC::G8RCRegClass, Op0, Op1);
4617 }
4618 return 0;
4619}
4620
4621unsigned fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4622 if (RetVT.SimpleTy != MVT::v4i32)
4623 return 0;
4624 if ((Subtarget->isISA3_1())) {
4625 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4626 }
4627 return 0;
4628}
4629
4630unsigned fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4631 if (RetVT.SimpleTy != MVT::v2i64)
4632 return 0;
4633 if ((Subtarget->isISA3_1())) {
4634 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODUD, RC: &PPC::VRRCRegClass, Op0, Op1);
4635 }
4636 return 0;
4637}
4638
4639unsigned fastEmit_ISD_UREM_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4640 if (RetVT.SimpleTy != MVT::v1i128)
4641 return 0;
4642 if ((Subtarget->isISA3_1())) {
4643 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODUQ, RC: &PPC::VRRCRegClass, Op0, Op1);
4644 }
4645 return 0;
4646}
4647
4648unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4649 switch (VT.SimpleTy) {
4650 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
4651 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
4652 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1);
4653 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1);
4654 case MVT::v1i128: return fastEmit_ISD_UREM_MVT_v1i128_rr(RetVT, Op0, Op1);
4655 default: return 0;
4656 }
4657}
4658
4659// FastEmit functions for ISD::USUBSAT.
4660
4661unsigned fastEmit_ISD_USUBSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4662 if (RetVT.SimpleTy != MVT::v16i8)
4663 return 0;
4664 if ((Subtarget->hasAltivec())) {
4665 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUBS, RC: &PPC::VRRCRegClass, Op0, Op1);
4666 }
4667 return 0;
4668}
4669
4670unsigned fastEmit_ISD_USUBSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4671 if (RetVT.SimpleTy != MVT::v8i16)
4672 return 0;
4673 if ((Subtarget->hasAltivec())) {
4674 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUHS, RC: &PPC::VRRCRegClass, Op0, Op1);
4675 }
4676 return 0;
4677}
4678
4679unsigned fastEmit_ISD_USUBSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4680 if (RetVT.SimpleTy != MVT::v4i32)
4681 return 0;
4682 if ((Subtarget->hasAltivec())) {
4683 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUWS, RC: &PPC::VRRCRegClass, Op0, Op1);
4684 }
4685 return 0;
4686}
4687
4688unsigned fastEmit_ISD_USUBSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4689 switch (VT.SimpleTy) {
4690 case MVT::v16i8: return fastEmit_ISD_USUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
4691 case MVT::v8i16: return fastEmit_ISD_USUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
4692 case MVT::v4i32: return fastEmit_ISD_USUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
4693 default: return 0;
4694 }
4695}
4696
4697// FastEmit functions for ISD::XOR.
4698
4699unsigned fastEmit_ISD_XOR_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4700 if (RetVT.SimpleTy != MVT::i1)
4701 return 0;
4702 return fastEmitInst_rr(MachineInstOpcode: PPC::CRXOR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
4703}
4704
4705unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4706 if (RetVT.SimpleTy != MVT::i32)
4707 return 0;
4708 return fastEmitInst_rr(MachineInstOpcode: PPC::XOR, RC: &PPC::GPRCRegClass, Op0, Op1);
4709}
4710
4711unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4712 if (RetVT.SimpleTy != MVT::i64)
4713 return 0;
4714 return fastEmitInst_rr(MachineInstOpcode: PPC::XOR8, RC: &PPC::G8RCRegClass, Op0, Op1);
4715}
4716
4717unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4718 if (RetVT.SimpleTy != MVT::v4i32)
4719 return 0;
4720 if ((Subtarget->hasVSX())) {
4721 return fastEmitInst_rr(MachineInstOpcode: PPC::XXLXOR, RC: &PPC::VSRCRegClass, Op0, Op1);
4722 }
4723 if ((Subtarget->hasAltivec())) {
4724 return fastEmitInst_rr(MachineInstOpcode: PPC::VXOR, RC: &PPC::VRRCRegClass, Op0, Op1);
4725 }
4726 return 0;
4727}
4728
4729unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4730 switch (VT.SimpleTy) {
4731 case MVT::i1: return fastEmit_ISD_XOR_MVT_i1_rr(RetVT, Op0, Op1);
4732 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
4733 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
4734 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
4735 default: return 0;
4736 }
4737}
4738
4739// FastEmit functions for PPCISD::ADD_TLS.
4740
4741unsigned fastEmit_PPCISD_ADD_TLS_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4742 if (RetVT.SimpleTy != MVT::i32)
4743 return 0;
4744 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD4TLS, RC: &PPC::GPRCRegClass, Op0, Op1);
4745}
4746
4747unsigned fastEmit_PPCISD_ADD_TLS_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4748 if (RetVT.SimpleTy != MVT::i64)
4749 return 0;
4750 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD8TLS, RC: &PPC::G8RCRegClass, Op0, Op1);
4751}
4752
4753unsigned fastEmit_PPCISD_ADD_TLS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4754 switch (VT.SimpleTy) {
4755 case MVT::i32: return fastEmit_PPCISD_ADD_TLS_MVT_i32_rr(RetVT, Op0, Op1);
4756 case MVT::i64: return fastEmit_PPCISD_ADD_TLS_MVT_i64_rr(RetVT, Op0, Op1);
4757 default: return 0;
4758 }
4759}
4760
4761// FastEmit functions for PPCISD::CMPB.
4762
4763unsigned fastEmit_PPCISD_CMPB_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4764 if (RetVT.SimpleTy != MVT::i32)
4765 return 0;
4766 return fastEmitInst_rr(MachineInstOpcode: PPC::CMPB, RC: &PPC::GPRCRegClass, Op0, Op1);
4767}
4768
4769unsigned fastEmit_PPCISD_CMPB_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4770 if (RetVT.SimpleTy != MVT::i64)
4771 return 0;
4772 return fastEmitInst_rr(MachineInstOpcode: PPC::CMPB8, RC: &PPC::G8RCRegClass, Op0, Op1);
4773}
4774
4775unsigned fastEmit_PPCISD_CMPB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4776 switch (VT.SimpleTy) {
4777 case MVT::i32: return fastEmit_PPCISD_CMPB_MVT_i32_rr(RetVT, Op0, Op1);
4778 case MVT::i64: return fastEmit_PPCISD_CMPB_MVT_i64_rr(RetVT, Op0, Op1);
4779 default: return 0;
4780 }
4781}
4782
4783// FastEmit functions for PPCISD::FADDRTZ.
4784
4785unsigned fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4786 if (RetVT.SimpleTy != MVT::f64)
4787 return 0;
4788 if ((Subtarget->hasFPU())) {
4789 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDrtz, RC: &PPC::F8RCRegClass, Op0, Op1);
4790 }
4791 return 0;
4792}
4793
4794unsigned fastEmit_PPCISD_FADDRTZ_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4795 switch (VT.SimpleTy) {
4796 case MVT::f64: return fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op1);
4797 default: return 0;
4798 }
4799}
4800
4801// FastEmit functions for PPCISD::GET_TLS_ADDR.
4802
4803unsigned fastEmit_PPCISD_GET_TLS_ADDR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4804 if (RetVT.SimpleTy != MVT::i32)
4805 return 0;
4806 return fastEmitInst_rr(MachineInstOpcode: PPC::GETtlsADDR32AIX, RC: &PPC::GPRCRegClass, Op0, Op1);
4807}
4808
4809unsigned fastEmit_PPCISD_GET_TLS_ADDR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4810 if (RetVT.SimpleTy != MVT::i64)
4811 return 0;
4812 return fastEmitInst_rr(MachineInstOpcode: PPC::GETtlsADDR64AIX, RC: &PPC::G8RCRegClass, Op0, Op1);
4813}
4814
4815unsigned fastEmit_PPCISD_GET_TLS_ADDR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4816 switch (VT.SimpleTy) {
4817 case MVT::i32: return fastEmit_PPCISD_GET_TLS_ADDR_MVT_i32_rr(RetVT, Op0, Op1);
4818 case MVT::i64: return fastEmit_PPCISD_GET_TLS_ADDR_MVT_i64_rr(RetVT, Op0, Op1);
4819 default: return 0;
4820 }
4821}
4822
4823// FastEmit functions for PPCISD::SHL.
4824
4825unsigned fastEmit_PPCISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4826 if (RetVT.SimpleTy != MVT::i32)
4827 return 0;
4828 return fastEmitInst_rr(MachineInstOpcode: PPC::SLW, RC: &PPC::GPRCRegClass, Op0, Op1);
4829}
4830
4831unsigned fastEmit_PPCISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4832 if (RetVT.SimpleTy != MVT::v16i8)
4833 return 0;
4834 if ((Subtarget->hasAltivec())) {
4835 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLB, RC: &PPC::VRRCRegClass, Op0, Op1);
4836 }
4837 return 0;
4838}
4839
4840unsigned fastEmit_PPCISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4841 if (RetVT.SimpleTy != MVT::v8i16)
4842 return 0;
4843 if ((Subtarget->hasAltivec())) {
4844 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLH, RC: &PPC::VRRCRegClass, Op0, Op1);
4845 }
4846 return 0;
4847}
4848
4849unsigned fastEmit_PPCISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4850 if (RetVT.SimpleTy != MVT::v4i32)
4851 return 0;
4852 if ((Subtarget->hasAltivec())) {
4853 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLW, RC: &PPC::VRRCRegClass, Op0, Op1);
4854 }
4855 return 0;
4856}
4857
4858unsigned fastEmit_PPCISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4859 if (RetVT.SimpleTy != MVT::v2i64)
4860 return 0;
4861 if ((Subtarget->hasP8Altivec())) {
4862 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLD, RC: &PPC::VRRCRegClass, Op0, Op1);
4863 }
4864 return 0;
4865}
4866
4867unsigned fastEmit_PPCISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4868 switch (VT.SimpleTy) {
4869 case MVT::i32: return fastEmit_PPCISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
4870 case MVT::v16i8: return fastEmit_PPCISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
4871 case MVT::v8i16: return fastEmit_PPCISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
4872 case MVT::v4i32: return fastEmit_PPCISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
4873 case MVT::v2i64: return fastEmit_PPCISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
4874 default: return 0;
4875 }
4876}
4877
4878// FastEmit functions for PPCISD::SRA.
4879
4880unsigned fastEmit_PPCISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4881 if (RetVT.SimpleTy != MVT::i32)
4882 return 0;
4883 return fastEmitInst_rr(MachineInstOpcode: PPC::SRAW, RC: &PPC::GPRCRegClass, Op0, Op1);
4884}
4885
4886unsigned fastEmit_PPCISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4887 if (RetVT.SimpleTy != MVT::v16i8)
4888 return 0;
4889 if ((Subtarget->hasAltivec())) {
4890 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAB, RC: &PPC::VRRCRegClass, Op0, Op1);
4891 }
4892 return 0;
4893}
4894
4895unsigned fastEmit_PPCISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4896 if (RetVT.SimpleTy != MVT::v8i16)
4897 return 0;
4898 if ((Subtarget->hasAltivec())) {
4899 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAH, RC: &PPC::VRRCRegClass, Op0, Op1);
4900 }
4901 return 0;
4902}
4903
4904unsigned fastEmit_PPCISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4905 if (RetVT.SimpleTy != MVT::v4i32)
4906 return 0;
4907 if ((Subtarget->hasAltivec())) {
4908 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAW, RC: &PPC::VRRCRegClass, Op0, Op1);
4909 }
4910 return 0;
4911}
4912
4913unsigned fastEmit_PPCISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4914 if (RetVT.SimpleTy != MVT::v2i64)
4915 return 0;
4916 if ((Subtarget->hasP8Altivec())) {
4917 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAD, RC: &PPC::VRRCRegClass, Op0, Op1);
4918 }
4919 return 0;
4920}
4921
4922unsigned fastEmit_PPCISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4923 switch (VT.SimpleTy) {
4924 case MVT::i32: return fastEmit_PPCISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
4925 case MVT::v16i8: return fastEmit_PPCISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
4926 case MVT::v8i16: return fastEmit_PPCISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
4927 case MVT::v4i32: return fastEmit_PPCISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
4928 case MVT::v2i64: return fastEmit_PPCISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
4929 default: return 0;
4930 }
4931}
4932
4933// FastEmit functions for PPCISD::SRL.
4934
4935unsigned fastEmit_PPCISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4936 if (RetVT.SimpleTy != MVT::i32)
4937 return 0;
4938 return fastEmitInst_rr(MachineInstOpcode: PPC::SRW, RC: &PPC::GPRCRegClass, Op0, Op1);
4939}
4940
4941unsigned fastEmit_PPCISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4942 if (RetVT.SimpleTy != MVT::v16i8)
4943 return 0;
4944 if ((Subtarget->hasAltivec())) {
4945 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRB, RC: &PPC::VRRCRegClass, Op0, Op1);
4946 }
4947 return 0;
4948}
4949
4950unsigned fastEmit_PPCISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4951 if (RetVT.SimpleTy != MVT::v8i16)
4952 return 0;
4953 if ((Subtarget->hasAltivec())) {
4954 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRH, RC: &PPC::VRRCRegClass, Op0, Op1);
4955 }
4956 return 0;
4957}
4958
4959unsigned fastEmit_PPCISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4960 if (RetVT.SimpleTy != MVT::v4i32)
4961 return 0;
4962 if ((Subtarget->hasAltivec())) {
4963 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRW, RC: &PPC::VRRCRegClass, Op0, Op1);
4964 }
4965 return 0;
4966}
4967
4968unsigned fastEmit_PPCISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4969 if (RetVT.SimpleTy != MVT::v2i64)
4970 return 0;
4971 if ((Subtarget->hasP8Altivec())) {
4972 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRD, RC: &PPC::VRRCRegClass, Op0, Op1);
4973 }
4974 return 0;
4975}
4976
4977unsigned fastEmit_PPCISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
4978 switch (VT.SimpleTy) {
4979 case MVT::i32: return fastEmit_PPCISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
4980 case MVT::v16i8: return fastEmit_PPCISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
4981 case MVT::v8i16: return fastEmit_PPCISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
4982 case MVT::v4i32: return fastEmit_PPCISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
4983 case MVT::v2i64: return fastEmit_PPCISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
4984 default: return 0;
4985 }
4986}
4987
4988// FastEmit functions for PPCISD::STRICT_FADDRTZ.
4989
4990unsigned fastEmit_PPCISD_STRICT_FADDRTZ_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4991 if (RetVT.SimpleTy != MVT::f64)
4992 return 0;
4993 if ((Subtarget->hasFPU())) {
4994 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDrtz, RC: &PPC::F8RCRegClass, Op0, Op1);
4995 }
4996 return 0;
4997}
4998
4999unsigned fastEmit_PPCISD_STRICT_FADDRTZ_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
5000 switch (VT.SimpleTy) {
5001 case MVT::f64: return fastEmit_PPCISD_STRICT_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op1);
5002 default: return 0;
5003 }
5004}
5005
5006// FastEmit functions for PPCISD::TLSGD_AIX.
5007
5008unsigned fastEmit_PPCISD_TLSGD_AIX_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
5009 if (RetVT.SimpleTy != MVT::i32)
5010 return 0;
5011 return fastEmitInst_rr(MachineInstOpcode: PPC::TLSGDAIX, RC: &PPC::GPRCRegClass, Op0, Op1);
5012}
5013
5014unsigned fastEmit_PPCISD_TLSGD_AIX_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
5015 if (RetVT.SimpleTy != MVT::i64)
5016 return 0;
5017 return fastEmitInst_rr(MachineInstOpcode: PPC::TLSGDAIX8, RC: &PPC::G8RCRegClass, Op0, Op1);
5018}
5019
5020unsigned fastEmit_PPCISD_TLSGD_AIX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
5021 switch (VT.SimpleTy) {
5022 case MVT::i32: return fastEmit_PPCISD_TLSGD_AIX_MVT_i32_rr(RetVT, Op0, Op1);
5023 case MVT::i64: return fastEmit_PPCISD_TLSGD_AIX_MVT_i64_rr(RetVT, Op0, Op1);
5024 default: return 0;
5025 }
5026}
5027
5028// FastEmit functions for PPCISD::XSMAXC.
5029
5030unsigned fastEmit_PPCISD_XSMAXC_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
5031 if (RetVT.SimpleTy != MVT::f64)
5032 return 0;
5033 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
5034 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXCDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
5035 }
5036 return 0;
5037}
5038
5039unsigned fastEmit_PPCISD_XSMAXC_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
5040 if (RetVT.SimpleTy != MVT::f128)
5041 return 0;
5042 if ((Subtarget->hasVSX()) && (Subtarget->isISA3_1())) {
5043 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXCQP, RC: &PPC::VRRCRegClass, Op0, Op1);
5044 }
5045 return 0;
5046}
5047
5048unsigned fastEmit_PPCISD_XSMAXC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
5049 switch (VT.SimpleTy) {
5050 case MVT::f64: return fastEmit_PPCISD_XSMAXC_MVT_f64_rr(RetVT, Op0, Op1);
5051 case MVT::f128: return fastEmit_PPCISD_XSMAXC_MVT_f128_rr(RetVT, Op0, Op1);
5052 default: return 0;
5053 }
5054}
5055
5056// FastEmit functions for PPCISD::XSMINC.
5057
5058unsigned fastEmit_PPCISD_XSMINC_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
5059 if (RetVT.SimpleTy != MVT::f64)
5060 return 0;
5061 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
5062 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINCDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
5063 }
5064 return 0;
5065}
5066
5067unsigned fastEmit_PPCISD_XSMINC_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
5068 if (RetVT.SimpleTy != MVT::f128)
5069 return 0;
5070 if ((Subtarget->hasVSX()) && (Subtarget->isISA3_1())) {
5071 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINCQP, RC: &PPC::VRRCRegClass, Op0, Op1);
5072 }
5073 return 0;
5074}
5075
5076unsigned fastEmit_PPCISD_XSMINC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
5077 switch (VT.SimpleTy) {
5078 case MVT::f64: return fastEmit_PPCISD_XSMINC_MVT_f64_rr(RetVT, Op0, Op1);
5079 case MVT::f128: return fastEmit_PPCISD_XSMINC_MVT_f128_rr(RetVT, Op0, Op1);
5080 default: return 0;
5081 }
5082}
5083
5084// Top-level FastEmit function.
5085
5086unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, unsigned Op1) override {
5087 switch (Opcode) {
5088 case ISD::ABDU: return fastEmit_ISD_ABDU_rr(VT, RetVT, Op0, Op1);
5089 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
5090 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op1);
5091 case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op1);
5092 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
5093 case ISD::BUILD_VECTOR: return fastEmit_ISD_BUILD_VECTOR_rr(VT, RetVT, Op0, Op1);
5094 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
5095 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
5096 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1);
5097 case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1);
5098 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1);
5099 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1);
5100 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
5101 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
5102 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
5103 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1);
5104 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1);
5105 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
5106 case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op1);
5107 case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op1);
5108 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
5109 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
5110 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
5111 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
5112 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
5113 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
5114 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
5115 case ISD::SSUBSAT: return fastEmit_ISD_SSUBSAT_rr(VT, RetVT, Op0, Op1);
5116 case ISD::STRICT_FADD: return fastEmit_ISD_STRICT_FADD_rr(VT, RetVT, Op0, Op1);
5117 case ISD::STRICT_FDIV: return fastEmit_ISD_STRICT_FDIV_rr(VT, RetVT, Op0, Op1);
5118 case ISD::STRICT_FMAXNUM: return fastEmit_ISD_STRICT_FMAXNUM_rr(VT, RetVT, Op0, Op1);
5119 case ISD::STRICT_FMINNUM: return fastEmit_ISD_STRICT_FMINNUM_rr(VT, RetVT, Op0, Op1);
5120 case ISD::STRICT_FMUL: return fastEmit_ISD_STRICT_FMUL_rr(VT, RetVT, Op0, Op1);
5121 case ISD::STRICT_FSUB: return fastEmit_ISD_STRICT_FSUB_rr(VT, RetVT, Op0, Op1);
5122 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
5123 case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op1);
5124 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
5125 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
5126 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
5127 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
5128 case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op1);
5129 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
5130 case PPCISD::ADD_TLS: return fastEmit_PPCISD_ADD_TLS_rr(VT, RetVT, Op0, Op1);
5131 case PPCISD::CMPB: return fastEmit_PPCISD_CMPB_rr(VT, RetVT, Op0, Op1);
5132 case PPCISD::FADDRTZ: return fastEmit_PPCISD_FADDRTZ_rr(VT, RetVT, Op0, Op1);
5133 case PPCISD::GET_TLS_ADDR: return fastEmit_PPCISD_GET_TLS_ADDR_rr(VT, RetVT, Op0, Op1);
5134 case PPCISD::SHL: return fastEmit_PPCISD_SHL_rr(VT, RetVT, Op0, Op1);
5135 case PPCISD::SRA: return fastEmit_PPCISD_SRA_rr(VT, RetVT, Op0, Op1);
5136 case PPCISD::SRL: return fastEmit_PPCISD_SRL_rr(VT, RetVT, Op0, Op1);
5137 case PPCISD::STRICT_FADDRTZ: return fastEmit_PPCISD_STRICT_FADDRTZ_rr(VT, RetVT, Op0, Op1);
5138 case PPCISD::TLSGD_AIX: return fastEmit_PPCISD_TLSGD_AIX_rr(VT, RetVT, Op0, Op1);
5139 case PPCISD::XSMAXC: return fastEmit_PPCISD_XSMAXC_rr(VT, RetVT, Op0, Op1);
5140 case PPCISD::XSMINC: return fastEmit_PPCISD_XSMINC_rr(VT, RetVT, Op0, Op1);
5141 default: return 0;
5142 }
5143}
5144
5145// FastEmit functions for ISD::SRA.
5146
5147unsigned fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
5148 if (RetVT.SimpleTy != MVT::i32)
5149 return 0;
5150 return fastEmitInst_ri(MachineInstOpcode: PPC::SRAWI, RC: &PPC::GPRCRegClass, Op0, Imm: imm1);
5151}
5152
5153unsigned fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
5154 if (RetVT.SimpleTy != MVT::i64)
5155 return 0;
5156 return fastEmitInst_ri(MachineInstOpcode: PPC::SRADI, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5157}
5158
5159unsigned fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
5160 switch (VT.SimpleTy) {
5161 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, imm1);
5162 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, imm1);
5163 default: return 0;
5164 }
5165}
5166
5167// FastEmit functions for PPCISD::EXTSWSLI.
5168
5169unsigned fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
5170 if (RetVT.SimpleTy != MVT::i64)
5171 return 0;
5172 if ((Subtarget->isISA3_0())) {
5173 return fastEmitInst_ri(MachineInstOpcode: PPC::EXTSWSLI_32_64, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5174 }
5175 return 0;
5176}
5177
5178unsigned fastEmit_PPCISD_EXTSWSLI_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
5179 switch (VT.SimpleTy) {
5180 case MVT::i32: return fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(RetVT, Op0, imm1);
5181 default: return 0;
5182 }
5183}
5184
5185// FastEmit functions for PPCISD::TC_RETURN.
5186
5187unsigned fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
5188 if (RetVT.SimpleTy != MVT::isVoid)
5189 return 0;
5190 return fastEmitInst_ri(MachineInstOpcode: PPC::TCRETURNri, RC: &PPC::CTRRCRegClass, Op0, Imm: imm1);
5191}
5192
5193unsigned fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
5194 if (RetVT.SimpleTy != MVT::isVoid)
5195 return 0;
5196 return fastEmitInst_ri(MachineInstOpcode: PPC::TCRETURNri8, RC: &PPC::CTRRC8RegClass, Op0, Imm: imm1);
5197}
5198
5199unsigned fastEmit_PPCISD_TC_RETURN_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
5200 switch (VT.SimpleTy) {
5201 case MVT::i32: return fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(RetVT, Op0, imm1);
5202 case MVT::i64: return fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(RetVT, Op0, imm1);
5203 default: return 0;
5204 }
5205}
5206
5207// Top-level FastEmit function.
5208
5209unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) override {
5210 if (VT == MVT::i32 && Predicate_imm32SExt16(Imm: imm1))
5211 if (unsigned Reg = fastEmit_ri_Predicate_imm32SExt16(VT, RetVT, Opcode, Op0, imm1))
5212 return Reg;
5213
5214 if (VT == MVT::i64 && Predicate_imm64SExt16(Imm: imm1))
5215 if (unsigned Reg = fastEmit_ri_Predicate_imm64SExt16(VT, RetVT, Opcode, Op0, imm1))
5216 return Reg;
5217
5218 switch (Opcode) {
5219 case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, imm1);
5220 case PPCISD::EXTSWSLI: return fastEmit_PPCISD_EXTSWSLI_ri(VT, RetVT, Op0, imm1);
5221 case PPCISD::TC_RETURN: return fastEmit_PPCISD_TC_RETURN_ri(VT, RetVT, Op0, imm1);
5222 default: return 0;
5223 }
5224}
5225
5226// FastEmit functions for ISD::ADD.
5227
5228unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) {
5229 if (RetVT.SimpleTy != MVT::i32)
5230 return 0;
5231 return fastEmitInst_ri(MachineInstOpcode: PPC::ADDI, RC: &PPC::GPRCRegClass, Op0, Imm: imm1);
5232}
5233
5234unsigned fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
5235 switch (VT.SimpleTy) {
5236 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1);
5237 default: return 0;
5238 }
5239}
5240
5241// FastEmit functions for ISD::ADDC.
5242
5243unsigned fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) {
5244 if (RetVT.SimpleTy != MVT::i32)
5245 return 0;
5246 return fastEmitInst_ri(MachineInstOpcode: PPC::ADDIC, RC: &PPC::GPRCRegClass, Op0, Imm: imm1);
5247}
5248
5249unsigned fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
5250 switch (VT.SimpleTy) {
5251 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1);
5252 default: return 0;
5253 }
5254}
5255
5256// FastEmit functions for ISD::MUL.
5257
5258unsigned fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) {
5259 if (RetVT.SimpleTy != MVT::i32)
5260 return 0;
5261 return fastEmitInst_ri(MachineInstOpcode: PPC::MULLI, RC: &PPC::GPRCRegClass, Op0, Imm: imm1);
5262}
5263
5264unsigned fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
5265 switch (VT.SimpleTy) {
5266 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1);
5267 default: return 0;
5268 }
5269}
5270
5271// FastEmit functions for PPCISD::XXSPLT.
5272
5273unsigned fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) {
5274 if (RetVT.SimpleTy != MVT::v4i32)
5275 return 0;
5276 if ((Subtarget->hasVSX())) {
5277 return fastEmitInst_ri(MachineInstOpcode: PPC::XXSPLTW, RC: &PPC::VSRCRegClass, Op0, Imm: imm1);
5278 }
5279 return 0;
5280}
5281
5282unsigned fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
5283 switch (VT.SimpleTy) {
5284 case MVT::v4i32: return fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1);
5285 default: return 0;
5286 }
5287}
5288
5289// Top-level FastEmit function.
5290
5291unsigned fastEmit_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
5292 switch (Opcode) {
5293 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1);
5294 case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1);
5295 case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1);
5296 case PPCISD::XXSPLT: return fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1);
5297 default: return 0;
5298 }
5299}
5300
5301// FastEmit functions for ISD::ADD.
5302
5303unsigned fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) {
5304 if (RetVT.SimpleTy != MVT::i64)
5305 return 0;
5306 return fastEmitInst_ri(MachineInstOpcode: PPC::ADDI8, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5307}
5308
5309unsigned fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
5310 switch (VT.SimpleTy) {
5311 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1);
5312 default: return 0;
5313 }
5314}
5315
5316// FastEmit functions for ISD::ADDC.
5317
5318unsigned fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) {
5319 if (RetVT.SimpleTy != MVT::i64)
5320 return 0;
5321 return fastEmitInst_ri(MachineInstOpcode: PPC::ADDIC8, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5322}
5323
5324unsigned fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
5325 switch (VT.SimpleTy) {
5326 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1);
5327 default: return 0;
5328 }
5329}
5330
5331// FastEmit functions for ISD::MUL.
5332
5333unsigned fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) {
5334 if (RetVT.SimpleTy != MVT::i64)
5335 return 0;
5336 return fastEmitInst_ri(MachineInstOpcode: PPC::MULLI8, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5337}
5338
5339unsigned fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
5340 switch (VT.SimpleTy) {
5341 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1);
5342 default: return 0;
5343 }
5344}
5345
5346// Top-level FastEmit function.
5347
5348unsigned fastEmit_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
5349 switch (Opcode) {
5350 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1);
5351 case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1);
5352 case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1);
5353 default: return 0;
5354 }
5355}
5356
5357