1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the WebAssembly target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_ImmI8(int64_t Imm) {
12return -(1 << (8 - 1)) <= Imm && Imm < (1 << 8);
13}
14static bool Predicate_ImmI16(int64_t Imm) {
15return -(1 << (16 - 1)) <= Imm && Imm < (1 << 16);
16}
17static bool Predicate_LaneIdx32(int64_t Imm) {
18return 0 <= Imm && Imm < 32;
19}
20static bool Predicate_LaneIdx16(int64_t Imm) {
21return 0 <= Imm && Imm < 16;
22}
23static bool Predicate_LaneIdx8(int64_t Imm) {
24return 0 <= Imm && Imm < 8;
25}
26static bool Predicate_LaneIdx4(int64_t Imm) {
27return 0 <= Imm && Imm < 4;
28}
29static bool Predicate_LaneIdx2(int64_t Imm) {
30return 0 <= Imm && Imm < 2;
31}
32
33
34// FastEmit functions for ISD::ABS.
35
36unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
37 if (RetVT.SimpleTy != MVT::v16i8)
38 return 0;
39 if ((Subtarget->hasSIMD128())) {
40 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I8x16, RC: &WebAssembly::V128RegClass, Op0);
41 }
42 return 0;
43}
44
45unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
46 if (RetVT.SimpleTy != MVT::v8i16)
47 return 0;
48 if ((Subtarget->hasSIMD128())) {
49 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I16x8, RC: &WebAssembly::V128RegClass, Op0);
50 }
51 return 0;
52}
53
54unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
55 if (RetVT.SimpleTy != MVT::v4i32)
56 return 0;
57 if ((Subtarget->hasSIMD128())) {
58 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I32x4, RC: &WebAssembly::V128RegClass, Op0);
59 }
60 return 0;
61}
62
63unsigned fastEmit_ISD_ABS_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
64 if (RetVT.SimpleTy != MVT::v2i64)
65 return 0;
66 if ((Subtarget->hasSIMD128())) {
67 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I64x2, RC: &WebAssembly::V128RegClass, Op0);
68 }
69 return 0;
70}
71
72unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0) {
73 switch (VT.SimpleTy) {
74 case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0);
75 case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0);
76 case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0);
77 case MVT::v2i64: return fastEmit_ISD_ABS_MVT_v2i64_r(RetVT, Op0);
78 default: return 0;
79 }
80}
81
82// FastEmit functions for ISD::ANY_EXTEND.
83
84unsigned fastEmit_ISD_ANY_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) {
85 if (RetVT.SimpleTy != MVT::i64)
86 return 0;
87 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_U_I32, RC: &WebAssembly::I64RegClass, Op0);
88}
89
90unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
91 switch (VT.SimpleTy) {
92 case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i32_r(RetVT, Op0);
93 default: return 0;
94 }
95}
96
97// FastEmit functions for ISD::BITCAST.
98
99unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0) {
100 if (RetVT.SimpleTy != MVT::f32)
101 return 0;
102 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_REINTERPRET_I32, RC: &WebAssembly::F32RegClass, Op0);
103}
104
105unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0) {
106 if (RetVT.SimpleTy != MVT::f64)
107 return 0;
108 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_REINTERPRET_I64, RC: &WebAssembly::F64RegClass, Op0);
109}
110
111unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0) {
112 if (RetVT.SimpleTy != MVT::i32)
113 return 0;
114 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_REINTERPRET_F32, RC: &WebAssembly::I32RegClass, Op0);
115}
116
117unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0) {
118 if (RetVT.SimpleTy != MVT::i64)
119 return 0;
120 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_REINTERPRET_F64, RC: &WebAssembly::I64RegClass, Op0);
121}
122
123unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0) {
124 switch (VT.SimpleTy) {
125 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
126 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
127 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
128 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
129 default: return 0;
130 }
131}
132
133// FastEmit functions for ISD::CTLZ.
134
135unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0) {
136 if (RetVT.SimpleTy != MVT::i32)
137 return 0;
138 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CLZ_I32, RC: &WebAssembly::I32RegClass, Op0);
139}
140
141unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0) {
142 if (RetVT.SimpleTy != MVT::i64)
143 return 0;
144 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CLZ_I64, RC: &WebAssembly::I64RegClass, Op0);
145}
146
147unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0) {
148 switch (VT.SimpleTy) {
149 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
150 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
151 default: return 0;
152 }
153}
154
155// FastEmit functions for ISD::CTPOP.
156
157unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0) {
158 if (RetVT.SimpleTy != MVT::i32)
159 return 0;
160 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I32, RC: &WebAssembly::I32RegClass, Op0);
161}
162
163unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0) {
164 if (RetVT.SimpleTy != MVT::i64)
165 return 0;
166 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I64, RC: &WebAssembly::I64RegClass, Op0);
167}
168
169unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
170 if (RetVT.SimpleTy != MVT::v16i8)
171 return 0;
172 if ((Subtarget->hasSIMD128())) {
173 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
174 }
175 return 0;
176}
177
178unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0) {
179 switch (VT.SimpleTy) {
180 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
181 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
182 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
183 default: return 0;
184 }
185}
186
187// FastEmit functions for ISD::CTTZ.
188
189unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0) {
190 if (RetVT.SimpleTy != MVT::i32)
191 return 0;
192 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CTZ_I32, RC: &WebAssembly::I32RegClass, Op0);
193}
194
195unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0) {
196 if (RetVT.SimpleTy != MVT::i64)
197 return 0;
198 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CTZ_I64, RC: &WebAssembly::I64RegClass, Op0);
199}
200
201unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0) {
202 switch (VT.SimpleTy) {
203 case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0);
204 case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0);
205 default: return 0;
206 }
207}
208
209// FastEmit functions for ISD::FABS.
210
211unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0) {
212 if (RetVT.SimpleTy != MVT::f32)
213 return 0;
214 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F32, RC: &WebAssembly::F32RegClass, Op0);
215}
216
217unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0) {
218 if (RetVT.SimpleTy != MVT::f64)
219 return 0;
220 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F64, RC: &WebAssembly::F64RegClass, Op0);
221}
222
223unsigned fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, unsigned Op0) {
224 if (RetVT.SimpleTy != MVT::v8f16)
225 return 0;
226 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
227 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F16x8, RC: &WebAssembly::V128RegClass, Op0);
228 }
229 return 0;
230}
231
232unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
233 if (RetVT.SimpleTy != MVT::v4f32)
234 return 0;
235 if ((Subtarget->hasSIMD128())) {
236 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F32x4, RC: &WebAssembly::V128RegClass, Op0);
237 }
238 return 0;
239}
240
241unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
242 if (RetVT.SimpleTy != MVT::v2f64)
243 return 0;
244 if ((Subtarget->hasSIMD128())) {
245 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F64x2, RC: &WebAssembly::V128RegClass, Op0);
246 }
247 return 0;
248}
249
250unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0) {
251 switch (VT.SimpleTy) {
252 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
253 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
254 case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0);
255 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
256 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
257 default: return 0;
258 }
259}
260
261// FastEmit functions for ISD::FCEIL.
262
263unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0) {
264 if (RetVT.SimpleTy != MVT::f32)
265 return 0;
266 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F32, RC: &WebAssembly::F32RegClass, Op0);
267}
268
269unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0) {
270 if (RetVT.SimpleTy != MVT::f64)
271 return 0;
272 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F64, RC: &WebAssembly::F64RegClass, Op0);
273}
274
275unsigned fastEmit_ISD_FCEIL_MVT_v8f16_r(MVT RetVT, unsigned Op0) {
276 if (RetVT.SimpleTy != MVT::v8f16)
277 return 0;
278 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
279 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F16x8, RC: &WebAssembly::V128RegClass, Op0);
280 }
281 return 0;
282}
283
284unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
285 if (RetVT.SimpleTy != MVT::v4f32)
286 return 0;
287 if ((Subtarget->hasSIMD128())) {
288 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F32x4, RC: &WebAssembly::V128RegClass, Op0);
289 }
290 return 0;
291}
292
293unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
294 if (RetVT.SimpleTy != MVT::v2f64)
295 return 0;
296 if ((Subtarget->hasSIMD128())) {
297 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F64x2, RC: &WebAssembly::V128RegClass, Op0);
298 }
299 return 0;
300}
301
302unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0) {
303 switch (VT.SimpleTy) {
304 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0);
305 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0);
306 case MVT::v8f16: return fastEmit_ISD_FCEIL_MVT_v8f16_r(RetVT, Op0);
307 case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0);
308 case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0);
309 default: return 0;
310 }
311}
312
313// FastEmit functions for ISD::FFLOOR.
314
315unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0) {
316 if (RetVT.SimpleTy != MVT::f32)
317 return 0;
318 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F32, RC: &WebAssembly::F32RegClass, Op0);
319}
320
321unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0) {
322 if (RetVT.SimpleTy != MVT::f64)
323 return 0;
324 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F64, RC: &WebAssembly::F64RegClass, Op0);
325}
326
327unsigned fastEmit_ISD_FFLOOR_MVT_v8f16_r(MVT RetVT, unsigned Op0) {
328 if (RetVT.SimpleTy != MVT::v8f16)
329 return 0;
330 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
331 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F16x8, RC: &WebAssembly::V128RegClass, Op0);
332 }
333 return 0;
334}
335
336unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
337 if (RetVT.SimpleTy != MVT::v4f32)
338 return 0;
339 if ((Subtarget->hasSIMD128())) {
340 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F32x4, RC: &WebAssembly::V128RegClass, Op0);
341 }
342 return 0;
343}
344
345unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
346 if (RetVT.SimpleTy != MVT::v2f64)
347 return 0;
348 if ((Subtarget->hasSIMD128())) {
349 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F64x2, RC: &WebAssembly::V128RegClass, Op0);
350 }
351 return 0;
352}
353
354unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0) {
355 switch (VT.SimpleTy) {
356 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0);
357 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0);
358 case MVT::v8f16: return fastEmit_ISD_FFLOOR_MVT_v8f16_r(RetVT, Op0);
359 case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0);
360 case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0);
361 default: return 0;
362 }
363}
364
365// FastEmit functions for ISD::FNEARBYINT.
366
367unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0) {
368 if (RetVT.SimpleTy != MVT::f32)
369 return 0;
370 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
371}
372
373unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
374 if (RetVT.SimpleTy != MVT::f64)
375 return 0;
376 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
377}
378
379unsigned fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(MVT RetVT, unsigned Op0) {
380 if (RetVT.SimpleTy != MVT::v8f16)
381 return 0;
382 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
383 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
384 }
385 return 0;
386}
387
388unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
389 if (RetVT.SimpleTy != MVT::v4f32)
390 return 0;
391 if ((Subtarget->hasSIMD128())) {
392 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
393 }
394 return 0;
395}
396
397unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
398 if (RetVT.SimpleTy != MVT::v2f64)
399 return 0;
400 if ((Subtarget->hasSIMD128())) {
401 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
402 }
403 return 0;
404}
405
406unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0) {
407 switch (VT.SimpleTy) {
408 case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0);
409 case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0);
410 case MVT::v8f16: return fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(RetVT, Op0);
411 case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0);
412 case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0);
413 default: return 0;
414 }
415}
416
417// FastEmit functions for ISD::FNEG.
418
419unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0) {
420 if (RetVT.SimpleTy != MVT::f32)
421 return 0;
422 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F32, RC: &WebAssembly::F32RegClass, Op0);
423}
424
425unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0) {
426 if (RetVT.SimpleTy != MVT::f64)
427 return 0;
428 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F64, RC: &WebAssembly::F64RegClass, Op0);
429}
430
431unsigned fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, unsigned Op0) {
432 if (RetVT.SimpleTy != MVT::v8f16)
433 return 0;
434 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
435 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F16x8, RC: &WebAssembly::V128RegClass, Op0);
436 }
437 return 0;
438}
439
440unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
441 if (RetVT.SimpleTy != MVT::v4f32)
442 return 0;
443 if ((Subtarget->hasSIMD128())) {
444 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F32x4, RC: &WebAssembly::V128RegClass, Op0);
445 }
446 return 0;
447}
448
449unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
450 if (RetVT.SimpleTy != MVT::v2f64)
451 return 0;
452 if ((Subtarget->hasSIMD128())) {
453 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F64x2, RC: &WebAssembly::V128RegClass, Op0);
454 }
455 return 0;
456}
457
458unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0) {
459 switch (VT.SimpleTy) {
460 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
461 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
462 case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0);
463 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0);
464 case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0);
465 default: return 0;
466 }
467}
468
469// FastEmit functions for ISD::FP_EXTEND.
470
471unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) {
472 if (RetVT.SimpleTy != MVT::f64)
473 return 0;
474 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_PROMOTE_F32, RC: &WebAssembly::F64RegClass, Op0);
475}
476
477unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
478 switch (VT.SimpleTy) {
479 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
480 default: return 0;
481 }
482}
483
484// FastEmit functions for ISD::FP_ROUND.
485
486unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) {
487 if (RetVT.SimpleTy != MVT::f32)
488 return 0;
489 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_DEMOTE_F64, RC: &WebAssembly::F32RegClass, Op0);
490}
491
492unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) {
493 switch (VT.SimpleTy) {
494 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
495 default: return 0;
496 }
497}
498
499// FastEmit functions for ISD::FP_TO_SINT.
500
501unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(unsigned Op0) {
502 if ((!Subtarget->hasNontrappingFPToInt())) {
503 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I32_F32, RC: &WebAssembly::I32RegClass, Op0);
504 }
505 if ((Subtarget->hasNontrappingFPToInt())) {
506 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_S_SAT_F32, RC: &WebAssembly::I32RegClass, Op0);
507 }
508 return 0;
509}
510
511unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(unsigned Op0) {
512 if ((!Subtarget->hasNontrappingFPToInt())) {
513 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I64_F32, RC: &WebAssembly::I64RegClass, Op0);
514 }
515 if ((Subtarget->hasNontrappingFPToInt())) {
516 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_S_SAT_F32, RC: &WebAssembly::I64RegClass, Op0);
517 }
518 return 0;
519}
520
521unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) {
522switch (RetVT.SimpleTy) {
523 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0);
524 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0);
525 default: return 0;
526}
527}
528
529unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(unsigned Op0) {
530 if ((!Subtarget->hasNontrappingFPToInt())) {
531 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I32_F64, RC: &WebAssembly::I32RegClass, Op0);
532 }
533 if ((Subtarget->hasNontrappingFPToInt())) {
534 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_S_SAT_F64, RC: &WebAssembly::I32RegClass, Op0);
535 }
536 return 0;
537}
538
539unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(unsigned Op0) {
540 if ((!Subtarget->hasNontrappingFPToInt())) {
541 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I64_F64, RC: &WebAssembly::I64RegClass, Op0);
542 }
543 if ((Subtarget->hasNontrappingFPToInt())) {
544 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_S_SAT_F64, RC: &WebAssembly::I64RegClass, Op0);
545 }
546 return 0;
547}
548
549unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
550switch (RetVT.SimpleTy) {
551 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0);
552 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0);
553 default: return 0;
554}
555}
556
557unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, unsigned Op0) {
558 if (RetVT.SimpleTy != MVT::v8i16)
559 return 0;
560 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
561 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_sint_I16x8, RC: &WebAssembly::V128RegClass, Op0);
562 }
563 return 0;
564}
565
566unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
567 if (RetVT.SimpleTy != MVT::v4i32)
568 return 0;
569 if ((Subtarget->hasSIMD128())) {
570 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_sint_I32x4, RC: &WebAssembly::V128RegClass, Op0);
571 }
572 return 0;
573}
574
575unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) {
576 switch (VT.SimpleTy) {
577 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
578 case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
579 case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0);
580 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
581 default: return 0;
582 }
583}
584
585// FastEmit functions for ISD::FP_TO_UINT.
586
587unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(unsigned Op0) {
588 if ((!Subtarget->hasNontrappingFPToInt())) {
589 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I32_F32, RC: &WebAssembly::I32RegClass, Op0);
590 }
591 if ((Subtarget->hasNontrappingFPToInt())) {
592 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_U_SAT_F32, RC: &WebAssembly::I32RegClass, Op0);
593 }
594 return 0;
595}
596
597unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(unsigned Op0) {
598 if ((!Subtarget->hasNontrappingFPToInt())) {
599 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I64_F32, RC: &WebAssembly::I64RegClass, Op0);
600 }
601 if ((Subtarget->hasNontrappingFPToInt())) {
602 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_U_SAT_F32, RC: &WebAssembly::I64RegClass, Op0);
603 }
604 return 0;
605}
606
607unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) {
608switch (RetVT.SimpleTy) {
609 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0);
610 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0);
611 default: return 0;
612}
613}
614
615unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(unsigned Op0) {
616 if ((!Subtarget->hasNontrappingFPToInt())) {
617 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I32_F64, RC: &WebAssembly::I32RegClass, Op0);
618 }
619 if ((Subtarget->hasNontrappingFPToInt())) {
620 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_U_SAT_F64, RC: &WebAssembly::I32RegClass, Op0);
621 }
622 return 0;
623}
624
625unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(unsigned Op0) {
626 if ((!Subtarget->hasNontrappingFPToInt())) {
627 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I64_F64, RC: &WebAssembly::I64RegClass, Op0);
628 }
629 if ((Subtarget->hasNontrappingFPToInt())) {
630 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_U_SAT_F64, RC: &WebAssembly::I64RegClass, Op0);
631 }
632 return 0;
633}
634
635unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
636switch (RetVT.SimpleTy) {
637 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0);
638 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0);
639 default: return 0;
640}
641}
642
643unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, unsigned Op0) {
644 if (RetVT.SimpleTy != MVT::v8i16)
645 return 0;
646 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
647 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_uint_I16x8, RC: &WebAssembly::V128RegClass, Op0);
648 }
649 return 0;
650}
651
652unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
653 if (RetVT.SimpleTy != MVT::v4i32)
654 return 0;
655 if ((Subtarget->hasSIMD128())) {
656 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_uint_I32x4, RC: &WebAssembly::V128RegClass, Op0);
657 }
658 return 0;
659}
660
661unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) {
662 switch (VT.SimpleTy) {
663 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
664 case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
665 case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0);
666 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
667 default: return 0;
668 }
669}
670
671// FastEmit functions for ISD::FRINT.
672
673unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0) {
674 if (RetVT.SimpleTy != MVT::f32)
675 return 0;
676 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
677}
678
679unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
680 if (RetVT.SimpleTy != MVT::f64)
681 return 0;
682 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
683}
684
685unsigned fastEmit_ISD_FRINT_MVT_v8f16_r(MVT RetVT, unsigned Op0) {
686 if (RetVT.SimpleTy != MVT::v8f16)
687 return 0;
688 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
689}
690
691unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
692 if (RetVT.SimpleTy != MVT::v4f32)
693 return 0;
694 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
695}
696
697unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
698 if (RetVT.SimpleTy != MVT::v2f64)
699 return 0;
700 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
701}
702
703unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0) {
704 switch (VT.SimpleTy) {
705 case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0);
706 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0);
707 case MVT::v8f16: return fastEmit_ISD_FRINT_MVT_v8f16_r(RetVT, Op0);
708 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
709 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
710 default: return 0;
711 }
712}
713
714// FastEmit functions for ISD::FROUNDEVEN.
715
716unsigned fastEmit_ISD_FROUNDEVEN_MVT_f32_r(MVT RetVT, unsigned Op0) {
717 if (RetVT.SimpleTy != MVT::f32)
718 return 0;
719 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
720}
721
722unsigned fastEmit_ISD_FROUNDEVEN_MVT_f64_r(MVT RetVT, unsigned Op0) {
723 if (RetVT.SimpleTy != MVT::f64)
724 return 0;
725 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
726}
727
728unsigned fastEmit_ISD_FROUNDEVEN_MVT_v8f16_r(MVT RetVT, unsigned Op0) {
729 if (RetVT.SimpleTy != MVT::v8f16)
730 return 0;
731 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
732}
733
734unsigned fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
735 if (RetVT.SimpleTy != MVT::v4f32)
736 return 0;
737 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
738}
739
740unsigned fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
741 if (RetVT.SimpleTy != MVT::v2f64)
742 return 0;
743 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
744}
745
746unsigned fastEmit_ISD_FROUNDEVEN_r(MVT VT, MVT RetVT, unsigned Op0) {
747 switch (VT.SimpleTy) {
748 case MVT::f32: return fastEmit_ISD_FROUNDEVEN_MVT_f32_r(RetVT, Op0);
749 case MVT::f64: return fastEmit_ISD_FROUNDEVEN_MVT_f64_r(RetVT, Op0);
750 case MVT::v8f16: return fastEmit_ISD_FROUNDEVEN_MVT_v8f16_r(RetVT, Op0);
751 case MVT::v4f32: return fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(RetVT, Op0);
752 case MVT::v2f64: return fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(RetVT, Op0);
753 default: return 0;
754 }
755}
756
757// FastEmit functions for ISD::FSQRT.
758
759unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) {
760 if (RetVT.SimpleTy != MVT::f32)
761 return 0;
762 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F32, RC: &WebAssembly::F32RegClass, Op0);
763}
764
765unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) {
766 if (RetVT.SimpleTy != MVT::f64)
767 return 0;
768 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F64, RC: &WebAssembly::F64RegClass, Op0);
769}
770
771unsigned fastEmit_ISD_FSQRT_MVT_v8f16_r(MVT RetVT, unsigned Op0) {
772 if (RetVT.SimpleTy != MVT::v8f16)
773 return 0;
774 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
775 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F16x8, RC: &WebAssembly::V128RegClass, Op0);
776 }
777 return 0;
778}
779
780unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
781 if (RetVT.SimpleTy != MVT::v4f32)
782 return 0;
783 if ((Subtarget->hasSIMD128())) {
784 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
785 }
786 return 0;
787}
788
789unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
790 if (RetVT.SimpleTy != MVT::v2f64)
791 return 0;
792 if ((Subtarget->hasSIMD128())) {
793 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
794 }
795 return 0;
796}
797
798unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) {
799 switch (VT.SimpleTy) {
800 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
801 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
802 case MVT::v8f16: return fastEmit_ISD_FSQRT_MVT_v8f16_r(RetVT, Op0);
803 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
804 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
805 default: return 0;
806 }
807}
808
809// FastEmit functions for ISD::FTRUNC.
810
811unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0) {
812 if (RetVT.SimpleTy != MVT::f32)
813 return 0;
814 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F32, RC: &WebAssembly::F32RegClass, Op0);
815}
816
817unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0) {
818 if (RetVT.SimpleTy != MVT::f64)
819 return 0;
820 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F64, RC: &WebAssembly::F64RegClass, Op0);
821}
822
823unsigned fastEmit_ISD_FTRUNC_MVT_v8f16_r(MVT RetVT, unsigned Op0) {
824 if (RetVT.SimpleTy != MVT::v8f16)
825 return 0;
826 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
827 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F16x8, RC: &WebAssembly::V128RegClass, Op0);
828 }
829 return 0;
830}
831
832unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
833 if (RetVT.SimpleTy != MVT::v4f32)
834 return 0;
835 if ((Subtarget->hasSIMD128())) {
836 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F32x4, RC: &WebAssembly::V128RegClass, Op0);
837 }
838 return 0;
839}
840
841unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
842 if (RetVT.SimpleTy != MVT::v2f64)
843 return 0;
844 if ((Subtarget->hasSIMD128())) {
845 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F64x2, RC: &WebAssembly::V128RegClass, Op0);
846 }
847 return 0;
848}
849
850unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0) {
851 switch (VT.SimpleTy) {
852 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0);
853 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0);
854 case MVT::v8f16: return fastEmit_ISD_FTRUNC_MVT_v8f16_r(RetVT, Op0);
855 case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0);
856 case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0);
857 default: return 0;
858 }
859}
860
861// FastEmit functions for ISD::SCALAR_TO_VECTOR.
862
863unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v16i8_r(unsigned Op0) {
864 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
865}
866
867unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v8i16_r(unsigned Op0) {
868 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I16x8, RC: &WebAssembly::V128RegClass, Op0);
869}
870
871unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(unsigned Op0) {
872 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I32x4, RC: &WebAssembly::V128RegClass, Op0);
873}
874
875unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0) {
876switch (RetVT.SimpleTy) {
877 case MVT::v16i8: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v16i8_r(Op0);
878 case MVT::v8i16: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v8i16_r(Op0);
879 case MVT::v4i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(Op0);
880 default: return 0;
881}
882}
883
884unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(MVT RetVT, unsigned Op0) {
885 if (RetVT.SimpleTy != MVT::v2i64)
886 return 0;
887 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I64x2, RC: &WebAssembly::V128RegClass, Op0);
888}
889
890unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0) {
891 if (RetVT.SimpleTy != MVT::v4f32)
892 return 0;
893 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
894}
895
896unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(MVT RetVT, unsigned Op0) {
897 if (RetVT.SimpleTy != MVT::v2f64)
898 return 0;
899 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
900}
901
902unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0) {
903 switch (VT.SimpleTy) {
904 case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0);
905 case MVT::i64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(RetVT, Op0);
906 case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0);
907 case MVT::f64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(RetVT, Op0);
908 default: return 0;
909 }
910}
911
912// FastEmit functions for ISD::SIGN_EXTEND.
913
914unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) {
915 if (RetVT.SimpleTy != MVT::i64)
916 return 0;
917 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_S_I32, RC: &WebAssembly::I64RegClass, Op0);
918}
919
920unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
921 switch (VT.SimpleTy) {
922 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
923 default: return 0;
924 }
925}
926
927// FastEmit functions for ISD::SINT_TO_FP.
928
929unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) {
930 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_S_I32, RC: &WebAssembly::F32RegClass, Op0);
931}
932
933unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) {
934 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_S_I32, RC: &WebAssembly::F64RegClass, Op0);
935}
936
937unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) {
938switch (RetVT.SimpleTy) {
939 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
940 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
941 default: return 0;
942}
943}
944
945unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0) {
946 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_S_I64, RC: &WebAssembly::F32RegClass, Op0);
947}
948
949unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0) {
950 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_S_I64, RC: &WebAssembly::F64RegClass, Op0);
951}
952
953unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0) {
954switch (RetVT.SimpleTy) {
955 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0);
956 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0);
957 default: return 0;
958}
959}
960
961unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
962 if (RetVT.SimpleTy != MVT::v8f16)
963 return 0;
964 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
965 return fastEmitInst_r(MachineInstOpcode: WebAssembly::sint_to_fp_F16x8, RC: &WebAssembly::V128RegClass, Op0);
966 }
967 return 0;
968}
969
970unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
971 if (RetVT.SimpleTy != MVT::v4f32)
972 return 0;
973 if ((Subtarget->hasSIMD128())) {
974 return fastEmitInst_r(MachineInstOpcode: WebAssembly::sint_to_fp_F32x4, RC: &WebAssembly::V128RegClass, Op0);
975 }
976 return 0;
977}
978
979unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) {
980 switch (VT.SimpleTy) {
981 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
982 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
983 case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0);
984 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
985 default: return 0;
986 }
987}
988
989// FastEmit functions for ISD::SPLAT_VECTOR.
990
991unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v16i8_r(unsigned Op0) {
992 if ((Subtarget->hasSIMD128())) {
993 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
994 }
995 return 0;
996}
997
998unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v8i16_r(unsigned Op0) {
999 if ((Subtarget->hasSIMD128())) {
1000 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1001 }
1002 return 0;
1003}
1004
1005unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v4i32_r(unsigned Op0) {
1006 if ((Subtarget->hasSIMD128())) {
1007 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1008 }
1009 return 0;
1010}
1011
1012unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0) {
1013switch (RetVT.SimpleTy) {
1014 case MVT::v16i8: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v16i8_r(Op0);
1015 case MVT::v8i16: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v8i16_r(Op0);
1016 case MVT::v4i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v4i32_r(Op0);
1017 default: return 0;
1018}
1019}
1020
1021unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(MVT RetVT, unsigned Op0) {
1022 if (RetVT.SimpleTy != MVT::v2i64)
1023 return 0;
1024 if ((Subtarget->hasSIMD128())) {
1025 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1026 }
1027 return 0;
1028}
1029
1030unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0) {
1031 if (RetVT.SimpleTy != MVT::v4f32)
1032 return 0;
1033 if ((Subtarget->hasSIMD128())) {
1034 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1035 }
1036 return 0;
1037}
1038
1039unsigned fastEmit_ISD_SPLAT_VECTOR_MVT_f64_r(MVT RetVT, unsigned Op0) {
1040 if (RetVT.SimpleTy != MVT::v2f64)
1041 return 0;
1042 if ((Subtarget->hasSIMD128())) {
1043 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1044 }
1045 return 0;
1046}
1047
1048unsigned fastEmit_ISD_SPLAT_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0) {
1049 switch (VT.SimpleTy) {
1050 case MVT::i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(RetVT, Op0);
1051 case MVT::i64: return fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(RetVT, Op0);
1052 case MVT::f32: return fastEmit_ISD_SPLAT_VECTOR_MVT_f32_r(RetVT, Op0);
1053 case MVT::f64: return fastEmit_ISD_SPLAT_VECTOR_MVT_f64_r(RetVT, Op0);
1054 default: return 0;
1055 }
1056}
1057
1058// FastEmit functions for ISD::TRUNCATE.
1059
1060unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0) {
1061 if (RetVT.SimpleTy != MVT::i32)
1062 return 0;
1063 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_WRAP_I64, RC: &WebAssembly::I32RegClass, Op0);
1064}
1065
1066unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0) {
1067 switch (VT.SimpleTy) {
1068 case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0);
1069 default: return 0;
1070 }
1071}
1072
1073// FastEmit functions for ISD::UINT_TO_FP.
1074
1075unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) {
1076 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_U_I32, RC: &WebAssembly::F32RegClass, Op0);
1077}
1078
1079unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) {
1080 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_U_I32, RC: &WebAssembly::F64RegClass, Op0);
1081}
1082
1083unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) {
1084switch (RetVT.SimpleTy) {
1085 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1086 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1087 default: return 0;
1088}
1089}
1090
1091unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0) {
1092 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_U_I64, RC: &WebAssembly::F32RegClass, Op0);
1093}
1094
1095unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0) {
1096 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_U_I64, RC: &WebAssembly::F64RegClass, Op0);
1097}
1098
1099unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0) {
1100switch (RetVT.SimpleTy) {
1101 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0);
1102 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Op0);
1103 default: return 0;
1104}
1105}
1106
1107unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
1108 if (RetVT.SimpleTy != MVT::v8f16)
1109 return 0;
1110 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
1111 return fastEmitInst_r(MachineInstOpcode: WebAssembly::uint_to_fp_F16x8, RC: &WebAssembly::V128RegClass, Op0);
1112 }
1113 return 0;
1114}
1115
1116unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1117 if (RetVT.SimpleTy != MVT::v4f32)
1118 return 0;
1119 if ((Subtarget->hasSIMD128())) {
1120 return fastEmitInst_r(MachineInstOpcode: WebAssembly::uint_to_fp_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1121 }
1122 return 0;
1123}
1124
1125unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) {
1126 switch (VT.SimpleTy) {
1127 case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1128 case MVT::i64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_r(RetVT, Op0);
1129 case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0);
1130 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1131 default: return 0;
1132 }
1133}
1134
1135// FastEmit functions for ISD::ZERO_EXTEND.
1136
1137unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) {
1138 if (RetVT.SimpleTy != MVT::i64)
1139 return 0;
1140 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_U_I32, RC: &WebAssembly::I64RegClass, Op0);
1141}
1142
1143unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
1144 switch (VT.SimpleTy) {
1145 case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(RetVT, Op0);
1146 default: return 0;
1147 }
1148}
1149
1150// FastEmit functions for WebAssemblyISD::BR_TABLE.
1151
1152unsigned fastEmit_WebAssemblyISD_BR_TABLE_MVT_i32_r(MVT RetVT, unsigned Op0) {
1153 if (RetVT.SimpleTy != MVT::isVoid)
1154 return 0;
1155 return fastEmitInst_r(MachineInstOpcode: WebAssembly::BR_TABLE_I32, RC: &WebAssembly::I32RegClass, Op0);
1156}
1157
1158unsigned fastEmit_WebAssemblyISD_BR_TABLE_MVT_i64_r(MVT RetVT, unsigned Op0) {
1159 if (RetVT.SimpleTy != MVT::isVoid)
1160 return 0;
1161 return fastEmitInst_r(MachineInstOpcode: WebAssembly::BR_TABLE_I64, RC: &WebAssembly::I64RegClass, Op0);
1162}
1163
1164unsigned fastEmit_WebAssemblyISD_BR_TABLE_r(MVT VT, MVT RetVT, unsigned Op0) {
1165 switch (VT.SimpleTy) {
1166 case MVT::i32: return fastEmit_WebAssemblyISD_BR_TABLE_MVT_i32_r(RetVT, Op0);
1167 case MVT::i64: return fastEmit_WebAssemblyISD_BR_TABLE_MVT_i64_r(RetVT, Op0);
1168 default: return 0;
1169 }
1170}
1171
1172// FastEmit functions for WebAssemblyISD::CONVERT_LOW_S.
1173
1174unsigned fastEmit_WebAssemblyISD_CONVERT_LOW_S_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1175 if (RetVT.SimpleTy != MVT::v2f64)
1176 return 0;
1177 if ((Subtarget->hasSIMD128())) {
1178 return fastEmitInst_r(MachineInstOpcode: WebAssembly::convert_low_s_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1179 }
1180 return 0;
1181}
1182
1183unsigned fastEmit_WebAssemblyISD_CONVERT_LOW_S_r(MVT VT, MVT RetVT, unsigned Op0) {
1184 switch (VT.SimpleTy) {
1185 case MVT::v4i32: return fastEmit_WebAssemblyISD_CONVERT_LOW_S_MVT_v4i32_r(RetVT, Op0);
1186 default: return 0;
1187 }
1188}
1189
1190// FastEmit functions for WebAssemblyISD::CONVERT_LOW_U.
1191
1192unsigned fastEmit_WebAssemblyISD_CONVERT_LOW_U_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1193 if (RetVT.SimpleTy != MVT::v2f64)
1194 return 0;
1195 if ((Subtarget->hasSIMD128())) {
1196 return fastEmitInst_r(MachineInstOpcode: WebAssembly::convert_low_u_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1197 }
1198 return 0;
1199}
1200
1201unsigned fastEmit_WebAssemblyISD_CONVERT_LOW_U_r(MVT VT, MVT RetVT, unsigned Op0) {
1202 switch (VT.SimpleTy) {
1203 case MVT::v4i32: return fastEmit_WebAssemblyISD_CONVERT_LOW_U_MVT_v4i32_r(RetVT, Op0);
1204 default: return 0;
1205 }
1206}
1207
1208// FastEmit functions for WebAssemblyISD::DEMOTE_ZERO.
1209
1210unsigned fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1211 if (RetVT.SimpleTy != MVT::v4f32)
1212 return 0;
1213 if ((Subtarget->hasSIMD128())) {
1214 return fastEmitInst_r(MachineInstOpcode: WebAssembly::demote_zero_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1215 }
1216 return 0;
1217}
1218
1219unsigned fastEmit_WebAssemblyISD_DEMOTE_ZERO_r(MVT VT, MVT RetVT, unsigned Op0) {
1220 switch (VT.SimpleTy) {
1221 case MVT::v2f64: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v2f64_r(RetVT, Op0);
1222 default: return 0;
1223 }
1224}
1225
1226// FastEmit functions for WebAssemblyISD::EXTEND_HIGH_S.
1227
1228unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
1229 if (RetVT.SimpleTy != MVT::v8i16)
1230 return 0;
1231 if ((Subtarget->hasSIMD128())) {
1232 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1233 }
1234 return 0;
1235}
1236
1237unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
1238 if (RetVT.SimpleTy != MVT::v4i32)
1239 return 0;
1240 if ((Subtarget->hasSIMD128())) {
1241 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1242 }
1243 return 0;
1244}
1245
1246unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1247 if (RetVT.SimpleTy != MVT::v2i64)
1248 return 0;
1249 if ((Subtarget->hasSIMD128())) {
1250 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1251 }
1252 return 0;
1253}
1254
1255unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_S_r(MVT VT, MVT RetVT, unsigned Op0) {
1256 switch (VT.SimpleTy) {
1257 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v16i8_r(RetVT, Op0);
1258 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v8i16_r(RetVT, Op0);
1259 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v4i32_r(RetVT, Op0);
1260 default: return 0;
1261 }
1262}
1263
1264// FastEmit functions for WebAssemblyISD::EXTEND_HIGH_U.
1265
1266unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
1267 if (RetVT.SimpleTy != MVT::v8i16)
1268 return 0;
1269 if ((Subtarget->hasSIMD128())) {
1270 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1271 }
1272 return 0;
1273}
1274
1275unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
1276 if (RetVT.SimpleTy != MVT::v4i32)
1277 return 0;
1278 if ((Subtarget->hasSIMD128())) {
1279 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1280 }
1281 return 0;
1282}
1283
1284unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1285 if (RetVT.SimpleTy != MVT::v2i64)
1286 return 0;
1287 if ((Subtarget->hasSIMD128())) {
1288 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1289 }
1290 return 0;
1291}
1292
1293unsigned fastEmit_WebAssemblyISD_EXTEND_HIGH_U_r(MVT VT, MVT RetVT, unsigned Op0) {
1294 switch (VT.SimpleTy) {
1295 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v16i8_r(RetVT, Op0);
1296 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v8i16_r(RetVT, Op0);
1297 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v4i32_r(RetVT, Op0);
1298 default: return 0;
1299 }
1300}
1301
1302// FastEmit functions for WebAssemblyISD::EXTEND_LOW_S.
1303
1304unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
1305 if (RetVT.SimpleTy != MVT::v8i16)
1306 return 0;
1307 if ((Subtarget->hasSIMD128())) {
1308 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1309 }
1310 return 0;
1311}
1312
1313unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
1314 if (RetVT.SimpleTy != MVT::v4i32)
1315 return 0;
1316 if ((Subtarget->hasSIMD128())) {
1317 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1318 }
1319 return 0;
1320}
1321
1322unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1323 if (RetVT.SimpleTy != MVT::v2i64)
1324 return 0;
1325 if ((Subtarget->hasSIMD128())) {
1326 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1327 }
1328 return 0;
1329}
1330
1331unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_S_r(MVT VT, MVT RetVT, unsigned Op0) {
1332 switch (VT.SimpleTy) {
1333 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v16i8_r(RetVT, Op0);
1334 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v8i16_r(RetVT, Op0);
1335 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v4i32_r(RetVT, Op0);
1336 default: return 0;
1337 }
1338}
1339
1340// FastEmit functions for WebAssemblyISD::EXTEND_LOW_U.
1341
1342unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v16i8_r(MVT RetVT, unsigned Op0) {
1343 if (RetVT.SimpleTy != MVT::v8i16)
1344 return 0;
1345 if ((Subtarget->hasSIMD128())) {
1346 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1347 }
1348 return 0;
1349}
1350
1351unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v8i16_r(MVT RetVT, unsigned Op0) {
1352 if (RetVT.SimpleTy != MVT::v4i32)
1353 return 0;
1354 if ((Subtarget->hasSIMD128())) {
1355 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1356 }
1357 return 0;
1358}
1359
1360unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
1361 if (RetVT.SimpleTy != MVT::v2i64)
1362 return 0;
1363 if ((Subtarget->hasSIMD128())) {
1364 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1365 }
1366 return 0;
1367}
1368
1369unsigned fastEmit_WebAssemblyISD_EXTEND_LOW_U_r(MVT VT, MVT RetVT, unsigned Op0) {
1370 switch (VT.SimpleTy) {
1371 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v16i8_r(RetVT, Op0);
1372 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v8i16_r(RetVT, Op0);
1373 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v4i32_r(RetVT, Op0);
1374 default: return 0;
1375 }
1376}
1377
1378// FastEmit functions for WebAssemblyISD::PROMOTE_LOW.
1379
1380unsigned fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
1381 if (RetVT.SimpleTy != MVT::v2f64)
1382 return 0;
1383 if ((Subtarget->hasSIMD128())) {
1384 return fastEmitInst_r(MachineInstOpcode: WebAssembly::promote_low_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1385 }
1386 return 0;
1387}
1388
1389unsigned fastEmit_WebAssemblyISD_PROMOTE_LOW_r(MVT VT, MVT RetVT, unsigned Op0) {
1390 switch (VT.SimpleTy) {
1391 case MVT::v4f32: return fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v4f32_r(RetVT, Op0);
1392 default: return 0;
1393 }
1394}
1395
1396// FastEmit functions for WebAssemblyISD::TRUNC_SAT_ZERO_S.
1397
1398unsigned fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1399 if (RetVT.SimpleTy != MVT::v4i32)
1400 return 0;
1401 if ((Subtarget->hasSIMD128())) {
1402 return fastEmitInst_r(MachineInstOpcode: WebAssembly::trunc_sat_zero_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1403 }
1404 return 0;
1405}
1406
1407unsigned fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_r(MVT VT, MVT RetVT, unsigned Op0) {
1408 switch (VT.SimpleTy) {
1409 case MVT::v2f64: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_MVT_v2f64_r(RetVT, Op0);
1410 default: return 0;
1411 }
1412}
1413
1414// FastEmit functions for WebAssemblyISD::TRUNC_SAT_ZERO_U.
1415
1416unsigned fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
1417 if (RetVT.SimpleTy != MVT::v4i32)
1418 return 0;
1419 if ((Subtarget->hasSIMD128())) {
1420 return fastEmitInst_r(MachineInstOpcode: WebAssembly::trunc_sat_zero_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1421 }
1422 return 0;
1423}
1424
1425unsigned fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_r(MVT VT, MVT RetVT, unsigned Op0) {
1426 switch (VT.SimpleTy) {
1427 case MVT::v2f64: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_MVT_v2f64_r(RetVT, Op0);
1428 default: return 0;
1429 }
1430}
1431
1432// Top-level FastEmit function.
1433
1434unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0) override {
1435 switch (Opcode) {
1436 case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0);
1437 case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0);
1438 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1439 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1440 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1441 case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0);
1442 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1443 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0);
1444 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0);
1445 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0);
1446 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1447 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1448 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1449 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1450 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1451 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1452 case ISD::FROUNDEVEN: return fastEmit_ISD_FROUNDEVEN_r(VT, RetVT, Op0);
1453 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1454 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0);
1455 case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0);
1456 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1457 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1458 case ISD::SPLAT_VECTOR: return fastEmit_ISD_SPLAT_VECTOR_r(VT, RetVT, Op0);
1459 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0);
1460 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1461 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0);
1462 case WebAssemblyISD::BR_TABLE: return fastEmit_WebAssemblyISD_BR_TABLE_r(VT, RetVT, Op0);
1463 case WebAssemblyISD::CONVERT_LOW_S: return fastEmit_WebAssemblyISD_CONVERT_LOW_S_r(VT, RetVT, Op0);
1464 case WebAssemblyISD::CONVERT_LOW_U: return fastEmit_WebAssemblyISD_CONVERT_LOW_U_r(VT, RetVT, Op0);
1465 case WebAssemblyISD::DEMOTE_ZERO: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_r(VT, RetVT, Op0);
1466 case WebAssemblyISD::EXTEND_HIGH_S: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_r(VT, RetVT, Op0);
1467 case WebAssemblyISD::EXTEND_HIGH_U: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_r(VT, RetVT, Op0);
1468 case WebAssemblyISD::EXTEND_LOW_S: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_r(VT, RetVT, Op0);
1469 case WebAssemblyISD::EXTEND_LOW_U: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_r(VT, RetVT, Op0);
1470 case WebAssemblyISD::PROMOTE_LOW: return fastEmit_WebAssemblyISD_PROMOTE_LOW_r(VT, RetVT, Op0);
1471 case WebAssemblyISD::TRUNC_SAT_ZERO_S: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_r(VT, RetVT, Op0);
1472 case WebAssemblyISD::TRUNC_SAT_ZERO_U: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_r(VT, RetVT, Op0);
1473 default: return 0;
1474 }
1475}
1476
1477// FastEmit functions for ISD::ADD.
1478
1479unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1480 if (RetVT.SimpleTy != MVT::i32)
1481 return 0;
1482 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
1483}
1484
1485unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1486 if (RetVT.SimpleTy != MVT::i64)
1487 return 0;
1488 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
1489}
1490
1491unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1492 if (RetVT.SimpleTy != MVT::v16i8)
1493 return 0;
1494 if ((Subtarget->hasSIMD128())) {
1495 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
1496 }
1497 return 0;
1498}
1499
1500unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1501 if (RetVT.SimpleTy != MVT::v8i16)
1502 return 0;
1503 if ((Subtarget->hasSIMD128())) {
1504 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1505 }
1506 return 0;
1507}
1508
1509unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1510 if (RetVT.SimpleTy != MVT::v4i32)
1511 return 0;
1512 if ((Subtarget->hasSIMD128())) {
1513 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1514 }
1515 return 0;
1516}
1517
1518unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1519 if (RetVT.SimpleTy != MVT::v2i64)
1520 return 0;
1521 if ((Subtarget->hasSIMD128())) {
1522 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1523 }
1524 return 0;
1525}
1526
1527unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1528 switch (VT.SimpleTy) {
1529 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1530 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1531 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1532 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1533 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1534 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1535 default: return 0;
1536 }
1537}
1538
1539// FastEmit functions for ISD::AND.
1540
1541unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1542 if (RetVT.SimpleTy != MVT::i32)
1543 return 0;
1544 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
1545}
1546
1547unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1548 if (RetVT.SimpleTy != MVT::i64)
1549 return 0;
1550 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
1551}
1552
1553unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1554 if (RetVT.SimpleTy != MVT::v16i8)
1555 return 0;
1556 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1557}
1558
1559unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1560 if (RetVT.SimpleTy != MVT::v8i16)
1561 return 0;
1562 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1563}
1564
1565unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1566 if (RetVT.SimpleTy != MVT::v4i32)
1567 return 0;
1568 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1569}
1570
1571unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1572 if (RetVT.SimpleTy != MVT::v2i64)
1573 return 0;
1574 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1575}
1576
1577unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1578 switch (VT.SimpleTy) {
1579 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1580 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1581 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1582 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1583 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1584 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1585 default: return 0;
1586 }
1587}
1588
1589// FastEmit functions for ISD::FADD.
1590
1591unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1592 if (RetVT.SimpleTy != MVT::f32)
1593 return 0;
1594 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1595}
1596
1597unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1598 if (RetVT.SimpleTy != MVT::f64)
1599 return 0;
1600 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1601}
1602
1603unsigned fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1604 if (RetVT.SimpleTy != MVT::v8f16)
1605 return 0;
1606 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
1607 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1608 }
1609 return 0;
1610}
1611
1612unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1613 if (RetVT.SimpleTy != MVT::v4f32)
1614 return 0;
1615 if ((Subtarget->hasSIMD128())) {
1616 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1617 }
1618 return 0;
1619}
1620
1621unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1622 if (RetVT.SimpleTy != MVT::v2f64)
1623 return 0;
1624 if ((Subtarget->hasSIMD128())) {
1625 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1626 }
1627 return 0;
1628}
1629
1630unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1631 switch (VT.SimpleTy) {
1632 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1633 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1634 case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op1);
1635 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1636 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1637 default: return 0;
1638 }
1639}
1640
1641// FastEmit functions for ISD::FCOPYSIGN.
1642
1643unsigned fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1644 if (RetVT.SimpleTy != MVT::f32)
1645 return 0;
1646 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::COPYSIGN_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1647}
1648
1649unsigned fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1650 if (RetVT.SimpleTy != MVT::f64)
1651 return 0;
1652 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::COPYSIGN_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1653}
1654
1655unsigned fastEmit_ISD_FCOPYSIGN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1656 switch (VT.SimpleTy) {
1657 case MVT::f32: return fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(RetVT, Op0, Op1);
1658 case MVT::f64: return fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(RetVT, Op0, Op1);
1659 default: return 0;
1660 }
1661}
1662
1663// FastEmit functions for ISD::FDIV.
1664
1665unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1666 if (RetVT.SimpleTy != MVT::f32)
1667 return 0;
1668 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1669}
1670
1671unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1672 if (RetVT.SimpleTy != MVT::f64)
1673 return 0;
1674 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1675}
1676
1677unsigned fastEmit_ISD_FDIV_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1678 if (RetVT.SimpleTy != MVT::v8f16)
1679 return 0;
1680 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
1681 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1682 }
1683 return 0;
1684}
1685
1686unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1687 if (RetVT.SimpleTy != MVT::v4f32)
1688 return 0;
1689 if ((Subtarget->hasSIMD128())) {
1690 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1691 }
1692 return 0;
1693}
1694
1695unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1696 if (RetVT.SimpleTy != MVT::v2f64)
1697 return 0;
1698 if ((Subtarget->hasSIMD128())) {
1699 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1700 }
1701 return 0;
1702}
1703
1704unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1705 switch (VT.SimpleTy) {
1706 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1707 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1708 case MVT::v8f16: return fastEmit_ISD_FDIV_MVT_v8f16_rr(RetVT, Op0, Op1);
1709 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1710 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1711 default: return 0;
1712 }
1713}
1714
1715// FastEmit functions for ISD::FMAXIMUM.
1716
1717unsigned fastEmit_ISD_FMAXIMUM_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1718 if (RetVT.SimpleTy != MVT::f32)
1719 return 0;
1720 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1721}
1722
1723unsigned fastEmit_ISD_FMAXIMUM_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1724 if (RetVT.SimpleTy != MVT::f64)
1725 return 0;
1726 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1727}
1728
1729unsigned fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1730 if (RetVT.SimpleTy != MVT::v8f16)
1731 return 0;
1732 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
1733 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1734 }
1735 return 0;
1736}
1737
1738unsigned fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1739 if (RetVT.SimpleTy != MVT::v4f32)
1740 return 0;
1741 if ((Subtarget->hasSIMD128())) {
1742 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1743 }
1744 return 0;
1745}
1746
1747unsigned fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1748 if (RetVT.SimpleTy != MVT::v2f64)
1749 return 0;
1750 if ((Subtarget->hasSIMD128())) {
1751 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1752 }
1753 return 0;
1754}
1755
1756unsigned fastEmit_ISD_FMAXIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1757 switch (VT.SimpleTy) {
1758 case MVT::f32: return fastEmit_ISD_FMAXIMUM_MVT_f32_rr(RetVT, Op0, Op1);
1759 case MVT::f64: return fastEmit_ISD_FMAXIMUM_MVT_f64_rr(RetVT, Op0, Op1);
1760 case MVT::v8f16: return fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(RetVT, Op0, Op1);
1761 case MVT::v4f32: return fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(RetVT, Op0, Op1);
1762 case MVT::v2f64: return fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(RetVT, Op0, Op1);
1763 default: return 0;
1764 }
1765}
1766
1767// FastEmit functions for ISD::FMINIMUM.
1768
1769unsigned fastEmit_ISD_FMINIMUM_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1770 if (RetVT.SimpleTy != MVT::f32)
1771 return 0;
1772 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1773}
1774
1775unsigned fastEmit_ISD_FMINIMUM_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1776 if (RetVT.SimpleTy != MVT::f64)
1777 return 0;
1778 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1779}
1780
1781unsigned fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1782 if (RetVT.SimpleTy != MVT::v8f16)
1783 return 0;
1784 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
1785 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1786 }
1787 return 0;
1788}
1789
1790unsigned fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1791 if (RetVT.SimpleTy != MVT::v4f32)
1792 return 0;
1793 if ((Subtarget->hasSIMD128())) {
1794 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1795 }
1796 return 0;
1797}
1798
1799unsigned fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1800 if (RetVT.SimpleTy != MVT::v2f64)
1801 return 0;
1802 if ((Subtarget->hasSIMD128())) {
1803 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1804 }
1805 return 0;
1806}
1807
1808unsigned fastEmit_ISD_FMINIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1809 switch (VT.SimpleTy) {
1810 case MVT::f32: return fastEmit_ISD_FMINIMUM_MVT_f32_rr(RetVT, Op0, Op1);
1811 case MVT::f64: return fastEmit_ISD_FMINIMUM_MVT_f64_rr(RetVT, Op0, Op1);
1812 case MVT::v8f16: return fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(RetVT, Op0, Op1);
1813 case MVT::v4f32: return fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(RetVT, Op0, Op1);
1814 case MVT::v2f64: return fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(RetVT, Op0, Op1);
1815 default: return 0;
1816 }
1817}
1818
1819// FastEmit functions for ISD::FMUL.
1820
1821unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1822 if (RetVT.SimpleTy != MVT::f32)
1823 return 0;
1824 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1825}
1826
1827unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1828 if (RetVT.SimpleTy != MVT::f64)
1829 return 0;
1830 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1831}
1832
1833unsigned fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1834 if (RetVT.SimpleTy != MVT::v8f16)
1835 return 0;
1836 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
1837 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1838 }
1839 return 0;
1840}
1841
1842unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1843 if (RetVT.SimpleTy != MVT::v4f32)
1844 return 0;
1845 if ((Subtarget->hasSIMD128())) {
1846 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1847 }
1848 return 0;
1849}
1850
1851unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1852 if (RetVT.SimpleTy != MVT::v2f64)
1853 return 0;
1854 if ((Subtarget->hasSIMD128())) {
1855 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1856 }
1857 return 0;
1858}
1859
1860unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1861 switch (VT.SimpleTy) {
1862 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1863 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1864 case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op1);
1865 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1866 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1867 default: return 0;
1868 }
1869}
1870
1871// FastEmit functions for ISD::FSUB.
1872
1873unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1874 if (RetVT.SimpleTy != MVT::f32)
1875 return 0;
1876 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1877}
1878
1879unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1880 if (RetVT.SimpleTy != MVT::f64)
1881 return 0;
1882 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1883}
1884
1885unsigned fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1886 if (RetVT.SimpleTy != MVT::v8f16)
1887 return 0;
1888 if ((Subtarget->hasHalfPrecision()) && (Subtarget->hasSIMD128())) {
1889 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1890 }
1891 return 0;
1892}
1893
1894unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1895 if (RetVT.SimpleTy != MVT::v4f32)
1896 return 0;
1897 if ((Subtarget->hasSIMD128())) {
1898 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1899 }
1900 return 0;
1901}
1902
1903unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1904 if (RetVT.SimpleTy != MVT::v2f64)
1905 return 0;
1906 if ((Subtarget->hasSIMD128())) {
1907 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1908 }
1909 return 0;
1910}
1911
1912unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1913 switch (VT.SimpleTy) {
1914 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
1915 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
1916 case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op1);
1917 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
1918 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
1919 default: return 0;
1920 }
1921}
1922
1923// FastEmit functions for ISD::MUL.
1924
1925unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1926 if (RetVT.SimpleTy != MVT::i32)
1927 return 0;
1928 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
1929}
1930
1931unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1932 if (RetVT.SimpleTy != MVT::i64)
1933 return 0;
1934 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
1935}
1936
1937unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1938 if (RetVT.SimpleTy != MVT::v8i16)
1939 return 0;
1940 if ((Subtarget->hasSIMD128())) {
1941 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1942 }
1943 return 0;
1944}
1945
1946unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1947 if (RetVT.SimpleTy != MVT::v4i32)
1948 return 0;
1949 if ((Subtarget->hasSIMD128())) {
1950 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1951 }
1952 return 0;
1953}
1954
1955unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1956 if (RetVT.SimpleTy != MVT::v2i64)
1957 return 0;
1958 if ((Subtarget->hasSIMD128())) {
1959 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1960 }
1961 return 0;
1962}
1963
1964unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
1965 switch (VT.SimpleTy) {
1966 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
1967 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
1968 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
1969 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
1970 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
1971 default: return 0;
1972 }
1973}
1974
1975// FastEmit functions for ISD::OR.
1976
1977unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1978 if (RetVT.SimpleTy != MVT::i32)
1979 return 0;
1980 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
1981}
1982
1983unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1984 if (RetVT.SimpleTy != MVT::i64)
1985 return 0;
1986 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
1987}
1988
1989unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1990 if (RetVT.SimpleTy != MVT::v16i8)
1991 return 0;
1992 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
1993}
1994
1995unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
1996 if (RetVT.SimpleTy != MVT::v8i16)
1997 return 0;
1998 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
1999}
2000
2001unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2002 if (RetVT.SimpleTy != MVT::v4i32)
2003 return 0;
2004 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2005}
2006
2007unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2008 if (RetVT.SimpleTy != MVT::v2i64)
2009 return 0;
2010 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2011}
2012
2013unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2014 switch (VT.SimpleTy) {
2015 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
2016 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
2017 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
2018 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
2019 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
2020 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
2021 default: return 0;
2022 }
2023}
2024
2025// FastEmit functions for ISD::ROTL.
2026
2027unsigned fastEmit_ISD_ROTL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2028 if (RetVT.SimpleTy != MVT::i32)
2029 return 0;
2030 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2031}
2032
2033unsigned fastEmit_ISD_ROTL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2034 if (RetVT.SimpleTy != MVT::i64)
2035 return 0;
2036 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2037}
2038
2039unsigned fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2040 switch (VT.SimpleTy) {
2041 case MVT::i32: return fastEmit_ISD_ROTL_MVT_i32_rr(RetVT, Op0, Op1);
2042 case MVT::i64: return fastEmit_ISD_ROTL_MVT_i64_rr(RetVT, Op0, Op1);
2043 default: return 0;
2044 }
2045}
2046
2047// FastEmit functions for ISD::ROTR.
2048
2049unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2050 if (RetVT.SimpleTy != MVT::i32)
2051 return 0;
2052 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2053}
2054
2055unsigned fastEmit_ISD_ROTR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2056 if (RetVT.SimpleTy != MVT::i64)
2057 return 0;
2058 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2059}
2060
2061unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2062 switch (VT.SimpleTy) {
2063 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
2064 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_rr(RetVT, Op0, Op1);
2065 default: return 0;
2066 }
2067}
2068
2069// FastEmit functions for ISD::SADDSAT.
2070
2071unsigned fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2072 if (RetVT.SimpleTy != MVT::v16i8)
2073 return 0;
2074 if ((Subtarget->hasSIMD128())) {
2075 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2076 }
2077 return 0;
2078}
2079
2080unsigned fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2081 if (RetVT.SimpleTy != MVT::v8i16)
2082 return 0;
2083 if ((Subtarget->hasSIMD128())) {
2084 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2085 }
2086 return 0;
2087}
2088
2089unsigned fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2090 switch (VT.SimpleTy) {
2091 case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2092 case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2093 default: return 0;
2094 }
2095}
2096
2097// FastEmit functions for ISD::SDIV.
2098
2099unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2100 if (RetVT.SimpleTy != MVT::i32)
2101 return 0;
2102 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2103}
2104
2105unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2106 if (RetVT.SimpleTy != MVT::i64)
2107 return 0;
2108 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2109}
2110
2111unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2112 switch (VT.SimpleTy) {
2113 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
2114 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
2115 default: return 0;
2116 }
2117}
2118
2119// FastEmit functions for ISD::SHL.
2120
2121unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2122 if (RetVT.SimpleTy != MVT::i32)
2123 return 0;
2124 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2125}
2126
2127unsigned fastEmit_ISD_SHL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2128 if (RetVT.SimpleTy != MVT::i64)
2129 return 0;
2130 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2131}
2132
2133unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2134 switch (VT.SimpleTy) {
2135 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
2136 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_rr(RetVT, Op0, Op1);
2137 default: return 0;
2138 }
2139}
2140
2141// FastEmit functions for ISD::SMAX.
2142
2143unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2144 if (RetVT.SimpleTy != MVT::v16i8)
2145 return 0;
2146 if ((Subtarget->hasSIMD128())) {
2147 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2148 }
2149 return 0;
2150}
2151
2152unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2153 if (RetVT.SimpleTy != MVT::v8i16)
2154 return 0;
2155 if ((Subtarget->hasSIMD128())) {
2156 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2157 }
2158 return 0;
2159}
2160
2161unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2162 if (RetVT.SimpleTy != MVT::v4i32)
2163 return 0;
2164 if ((Subtarget->hasSIMD128())) {
2165 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2166 }
2167 return 0;
2168}
2169
2170unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2171 switch (VT.SimpleTy) {
2172 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2173 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2174 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2175 default: return 0;
2176 }
2177}
2178
2179// FastEmit functions for ISD::SMIN.
2180
2181unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2182 if (RetVT.SimpleTy != MVT::v16i8)
2183 return 0;
2184 if ((Subtarget->hasSIMD128())) {
2185 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2186 }
2187 return 0;
2188}
2189
2190unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2191 if (RetVT.SimpleTy != MVT::v8i16)
2192 return 0;
2193 if ((Subtarget->hasSIMD128())) {
2194 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2195 }
2196 return 0;
2197}
2198
2199unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2200 if (RetVT.SimpleTy != MVT::v4i32)
2201 return 0;
2202 if ((Subtarget->hasSIMD128())) {
2203 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2204 }
2205 return 0;
2206}
2207
2208unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2209 switch (VT.SimpleTy) {
2210 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2211 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2212 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2213 default: return 0;
2214 }
2215}
2216
2217// FastEmit functions for ISD::SRA.
2218
2219unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2220 if (RetVT.SimpleTy != MVT::i32)
2221 return 0;
2222 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2223}
2224
2225unsigned fastEmit_ISD_SRA_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2226 if (RetVT.SimpleTy != MVT::i64)
2227 return 0;
2228 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2229}
2230
2231unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2232 switch (VT.SimpleTy) {
2233 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2234 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_rr(RetVT, Op0, Op1);
2235 default: return 0;
2236 }
2237}
2238
2239// FastEmit functions for ISD::SREM.
2240
2241unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2242 if (RetVT.SimpleTy != MVT::i32)
2243 return 0;
2244 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2245}
2246
2247unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2248 if (RetVT.SimpleTy != MVT::i64)
2249 return 0;
2250 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2251}
2252
2253unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2254 switch (VT.SimpleTy) {
2255 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2256 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2257 default: return 0;
2258 }
2259}
2260
2261// FastEmit functions for ISD::SRL.
2262
2263unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2264 if (RetVT.SimpleTy != MVT::i32)
2265 return 0;
2266 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2267}
2268
2269unsigned fastEmit_ISD_SRL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2270 if (RetVT.SimpleTy != MVT::i64)
2271 return 0;
2272 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2273}
2274
2275unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2276 switch (VT.SimpleTy) {
2277 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2278 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_rr(RetVT, Op0, Op1);
2279 default: return 0;
2280 }
2281}
2282
2283// FastEmit functions for ISD::SUB.
2284
2285unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2286 if (RetVT.SimpleTy != MVT::i32)
2287 return 0;
2288 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2289}
2290
2291unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2292 if (RetVT.SimpleTy != MVT::i64)
2293 return 0;
2294 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2295}
2296
2297unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2298 if (RetVT.SimpleTy != MVT::v16i8)
2299 return 0;
2300 if ((Subtarget->hasSIMD128())) {
2301 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2302 }
2303 return 0;
2304}
2305
2306unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2307 if (RetVT.SimpleTy != MVT::v8i16)
2308 return 0;
2309 if ((Subtarget->hasSIMD128())) {
2310 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2311 }
2312 return 0;
2313}
2314
2315unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2316 if (RetVT.SimpleTy != MVT::v4i32)
2317 return 0;
2318 if ((Subtarget->hasSIMD128())) {
2319 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2320 }
2321 return 0;
2322}
2323
2324unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2325 if (RetVT.SimpleTy != MVT::v2i64)
2326 return 0;
2327 if ((Subtarget->hasSIMD128())) {
2328 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2329 }
2330 return 0;
2331}
2332
2333unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2334 switch (VT.SimpleTy) {
2335 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2336 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2337 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2338 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2339 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2340 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2341 default: return 0;
2342 }
2343}
2344
2345// FastEmit functions for ISD::UADDSAT.
2346
2347unsigned fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2348 if (RetVT.SimpleTy != MVT::v16i8)
2349 return 0;
2350 if ((Subtarget->hasSIMD128())) {
2351 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2352 }
2353 return 0;
2354}
2355
2356unsigned fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2357 if (RetVT.SimpleTy != MVT::v8i16)
2358 return 0;
2359 if ((Subtarget->hasSIMD128())) {
2360 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2361 }
2362 return 0;
2363}
2364
2365unsigned fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2366 switch (VT.SimpleTy) {
2367 case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2368 case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2369 default: return 0;
2370 }
2371}
2372
2373// FastEmit functions for ISD::UDIV.
2374
2375unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2376 if (RetVT.SimpleTy != MVT::i32)
2377 return 0;
2378 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2379}
2380
2381unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2382 if (RetVT.SimpleTy != MVT::i64)
2383 return 0;
2384 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2385}
2386
2387unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2388 switch (VT.SimpleTy) {
2389 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2390 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2391 default: return 0;
2392 }
2393}
2394
2395// FastEmit functions for ISD::UMAX.
2396
2397unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2398 if (RetVT.SimpleTy != MVT::v16i8)
2399 return 0;
2400 if ((Subtarget->hasSIMD128())) {
2401 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2402 }
2403 return 0;
2404}
2405
2406unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2407 if (RetVT.SimpleTy != MVT::v8i16)
2408 return 0;
2409 if ((Subtarget->hasSIMD128())) {
2410 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2411 }
2412 return 0;
2413}
2414
2415unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2416 if (RetVT.SimpleTy != MVT::v4i32)
2417 return 0;
2418 if ((Subtarget->hasSIMD128())) {
2419 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2420 }
2421 return 0;
2422}
2423
2424unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2425 switch (VT.SimpleTy) {
2426 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2427 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2428 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2429 default: return 0;
2430 }
2431}
2432
2433// FastEmit functions for ISD::UMIN.
2434
2435unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2436 if (RetVT.SimpleTy != MVT::v16i8)
2437 return 0;
2438 if ((Subtarget->hasSIMD128())) {
2439 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2440 }
2441 return 0;
2442}
2443
2444unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2445 if (RetVT.SimpleTy != MVT::v8i16)
2446 return 0;
2447 if ((Subtarget->hasSIMD128())) {
2448 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2449 }
2450 return 0;
2451}
2452
2453unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2454 if (RetVT.SimpleTy != MVT::v4i32)
2455 return 0;
2456 if ((Subtarget->hasSIMD128())) {
2457 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2458 }
2459 return 0;
2460}
2461
2462unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2463 switch (VT.SimpleTy) {
2464 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2465 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2466 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2467 default: return 0;
2468 }
2469}
2470
2471// FastEmit functions for ISD::UREM.
2472
2473unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2474 if (RetVT.SimpleTy != MVT::i32)
2475 return 0;
2476 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2477}
2478
2479unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2480 if (RetVT.SimpleTy != MVT::i64)
2481 return 0;
2482 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2483}
2484
2485unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2486 switch (VT.SimpleTy) {
2487 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
2488 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
2489 default: return 0;
2490 }
2491}
2492
2493// FastEmit functions for ISD::XOR.
2494
2495unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2496 if (RetVT.SimpleTy != MVT::i32)
2497 return 0;
2498 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2499}
2500
2501unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2502 if (RetVT.SimpleTy != MVT::i64)
2503 return 0;
2504 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2505}
2506
2507unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2508 if (RetVT.SimpleTy != MVT::v16i8)
2509 return 0;
2510 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2511}
2512
2513unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2514 if (RetVT.SimpleTy != MVT::v8i16)
2515 return 0;
2516 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2517}
2518
2519unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2520 if (RetVT.SimpleTy != MVT::v4i32)
2521 return 0;
2522 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2523}
2524
2525unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2526 if (RetVT.SimpleTy != MVT::v2i64)
2527 return 0;
2528 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2529}
2530
2531unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2532 switch (VT.SimpleTy) {
2533 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
2534 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
2535 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
2536 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
2537 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
2538 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
2539 default: return 0;
2540 }
2541}
2542
2543// FastEmit functions for WebAssemblyISD::NARROW_U.
2544
2545unsigned fastEmit_WebAssemblyISD_NARROW_U_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2546 if (RetVT.SimpleTy != MVT::v16i8)
2547 return 0;
2548 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::NARROW_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2549}
2550
2551unsigned fastEmit_WebAssemblyISD_NARROW_U_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2552 if (RetVT.SimpleTy != MVT::v8i16)
2553 return 0;
2554 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::NARROW_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2555}
2556
2557unsigned fastEmit_WebAssemblyISD_NARROW_U_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2558 switch (VT.SimpleTy) {
2559 case MVT::v8i16: return fastEmit_WebAssemblyISD_NARROW_U_MVT_v8i16_rr(RetVT, Op0, Op1);
2560 case MVT::v4i32: return fastEmit_WebAssemblyISD_NARROW_U_MVT_v4i32_rr(RetVT, Op0, Op1);
2561 default: return 0;
2562 }
2563}
2564
2565// FastEmit functions for WebAssemblyISD::SWIZZLE.
2566
2567unsigned fastEmit_WebAssemblyISD_SWIZZLE_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
2568 if (RetVT.SimpleTy != MVT::v16i8)
2569 return 0;
2570 if ((Subtarget->hasSIMD128())) {
2571 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SWIZZLE, RC: &WebAssembly::V128RegClass, Op0, Op1);
2572 }
2573 return 0;
2574}
2575
2576unsigned fastEmit_WebAssemblyISD_SWIZZLE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
2577 switch (VT.SimpleTy) {
2578 case MVT::v16i8: return fastEmit_WebAssemblyISD_SWIZZLE_MVT_v16i8_rr(RetVT, Op0, Op1);
2579 default: return 0;
2580 }
2581}
2582
2583// Top-level FastEmit function.
2584
2585unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, unsigned Op1) override {
2586 switch (Opcode) {
2587 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
2588 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
2589 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
2590 case ISD::FCOPYSIGN: return fastEmit_ISD_FCOPYSIGN_rr(VT, RetVT, Op0, Op1);
2591 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
2592 case ISD::FMAXIMUM: return fastEmit_ISD_FMAXIMUM_rr(VT, RetVT, Op0, Op1);
2593 case ISD::FMINIMUM: return fastEmit_ISD_FMINIMUM_rr(VT, RetVT, Op0, Op1);
2594 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
2595 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
2596 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
2597 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
2598 case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op1);
2599 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
2600 case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op1);
2601 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
2602 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
2603 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
2604 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
2605 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
2606 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
2607 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
2608 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
2609 case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op1);
2610 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
2611 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
2612 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
2613 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
2614 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
2615 case WebAssemblyISD::NARROW_U: return fastEmit_WebAssemblyISD_NARROW_U_rr(VT, RetVT, Op0, Op1);
2616 case WebAssemblyISD::SWIZZLE: return fastEmit_WebAssemblyISD_SWIZZLE_rr(VT, RetVT, Op0, Op1);
2617 default: return 0;
2618 }
2619}
2620
2621// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2622
2623unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(MVT RetVT, unsigned Op0, uint64_t imm1) {
2624 if (RetVT.SimpleTy != MVT::i32)
2625 return 0;
2626 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I8x16_u, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2627}
2628
2629unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
2630 switch (VT.SimpleTy) {
2631 case MVT::v16i8: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(RetVT, Op0, imm1);
2632 default: return 0;
2633 }
2634}
2635
2636// Top-level FastEmit function.
2637
2638unsigned fastEmit_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
2639 switch (Opcode) {
2640 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(VT, RetVT, Op0, imm1);
2641 default: return 0;
2642 }
2643}
2644
2645// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2646
2647unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(MVT RetVT, unsigned Op0, uint64_t imm1) {
2648 if (RetVT.SimpleTy != MVT::i32)
2649 return 0;
2650 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I16x8_u, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2651}
2652
2653unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
2654 switch (VT.SimpleTy) {
2655 case MVT::v8i16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(RetVT, Op0, imm1);
2656 default: return 0;
2657 }
2658}
2659
2660// Top-level FastEmit function.
2661
2662unsigned fastEmit_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
2663 switch (Opcode) {
2664 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(VT, RetVT, Op0, imm1);
2665 default: return 0;
2666 }
2667}
2668
2669// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2670
2671unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(MVT RetVT, unsigned Op0, uint64_t imm1) {
2672 if (RetVT.SimpleTy != MVT::i32)
2673 return 0;
2674 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I32x4, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2675}
2676
2677unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(MVT RetVT, unsigned Op0, uint64_t imm1) {
2678 if (RetVT.SimpleTy != MVT::f32)
2679 return 0;
2680 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_F32x4, RC: &WebAssembly::F32RegClass, Op0, Imm: imm1);
2681}
2682
2683unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
2684 switch (VT.SimpleTy) {
2685 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(RetVT, Op0, imm1);
2686 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(RetVT, Op0, imm1);
2687 default: return 0;
2688 }
2689}
2690
2691// Top-level FastEmit function.
2692
2693unsigned fastEmit_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
2694 switch (Opcode) {
2695 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(VT, RetVT, Op0, imm1);
2696 default: return 0;
2697 }
2698}
2699
2700// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2701
2702unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(MVT RetVT, unsigned Op0, uint64_t imm1) {
2703 if (RetVT.SimpleTy != MVT::i64)
2704 return 0;
2705 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I64x2, RC: &WebAssembly::I64RegClass, Op0, Imm: imm1);
2706}
2707
2708unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(MVT RetVT, unsigned Op0, uint64_t imm1) {
2709 if (RetVT.SimpleTy != MVT::f64)
2710 return 0;
2711 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_F64x2, RC: &WebAssembly::F64RegClass, Op0, Imm: imm1);
2712}
2713
2714unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
2715 switch (VT.SimpleTy) {
2716 case MVT::v2i64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(RetVT, Op0, imm1);
2717 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(RetVT, Op0, imm1);
2718 default: return 0;
2719 }
2720}
2721
2722// Top-level FastEmit function.
2723
2724unsigned fastEmit_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
2725 switch (Opcode) {
2726 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(VT, RetVT, Op0, imm1);
2727 default: return 0;
2728 }
2729}
2730
2731// FastEmit functions for ISD::ConstantFP.
2732
2733unsigned fastEmit_ISD_ConstantFP_MVT_f32_f(MVT RetVT, const ConstantFP *f0) {
2734 if (RetVT.SimpleTy != MVT::f32)
2735 return 0;
2736 return fastEmitInst_f(MachineInstOpcode: WebAssembly::CONST_F32, RC: &WebAssembly::F32RegClass, FPImm: f0);
2737}
2738
2739unsigned fastEmit_ISD_ConstantFP_MVT_f64_f(MVT RetVT, const ConstantFP *f0) {
2740 if (RetVT.SimpleTy != MVT::f64)
2741 return 0;
2742 return fastEmitInst_f(MachineInstOpcode: WebAssembly::CONST_F64, RC: &WebAssembly::F64RegClass, FPImm: f0);
2743}
2744
2745unsigned fastEmit_ISD_ConstantFP_f(MVT VT, MVT RetVT, const ConstantFP *f0) {
2746 switch (VT.SimpleTy) {
2747 case MVT::f32: return fastEmit_ISD_ConstantFP_MVT_f32_f(RetVT, f0);
2748 case MVT::f64: return fastEmit_ISD_ConstantFP_MVT_f64_f(RetVT, f0);
2749 default: return 0;
2750 }
2751}
2752
2753// Top-level FastEmit function.
2754
2755unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *f0) override {
2756 switch (Opcode) {
2757 case ISD::ConstantFP: return fastEmit_ISD_ConstantFP_f(VT, RetVT, f0);
2758 default: return 0;
2759 }
2760}
2761
2762// FastEmit functions for ISD::Constant.
2763
2764unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
2765 if (RetVT.SimpleTy != MVT::i32)
2766 return 0;
2767 return fastEmitInst_i(MachineInstOpcode: WebAssembly::CONST_I32, RC: &WebAssembly::I32RegClass, Imm: imm0);
2768}
2769
2770unsigned fastEmit_ISD_Constant_MVT_i64_i(MVT RetVT, uint64_t imm0) {
2771 if (RetVT.SimpleTy != MVT::i64)
2772 return 0;
2773 return fastEmitInst_i(MachineInstOpcode: WebAssembly::CONST_I64, RC: &WebAssembly::I64RegClass, Imm: imm0);
2774}
2775
2776unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
2777 switch (VT.SimpleTy) {
2778 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
2779 case MVT::i64: return fastEmit_ISD_Constant_MVT_i64_i(RetVT, imm0);
2780 default: return 0;
2781 }
2782}
2783
2784// Top-level FastEmit function.
2785
2786unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
2787 switch (Opcode) {
2788 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
2789 default: return 0;
2790 }
2791}
2792
2793