1//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineInstr class, which is the
10// basic representation for all target dependent machine instructions used by
11// the back end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H
17
18#include "llvm/ADT/DenseMapInfo.h"
19#include "llvm/ADT/PointerSumType.h"
20#include "llvm/ADT/ilist.h"
21#include "llvm/ADT/ilist_node.h"
22#include "llvm/ADT/iterator_range.h"
23#include "llvm/Analysis/MemoryLocation.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/MachineOperand.h"
26#include "llvm/CodeGen/TargetOpcodes.h"
27#include "llvm/IR/DebugLoc.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/MC/MCInstrDesc.h"
30#include "llvm/MC/MCSymbol.h"
31#include "llvm/Support/ArrayRecycler.h"
32#include "llvm/Support/MathExtras.h"
33#include "llvm/Support/TrailingObjects.h"
34#include <algorithm>
35#include <cassert>
36#include <cstdint>
37#include <utility>
38
39namespace llvm {
40
41class DILabel;
42class Instruction;
43class MDNode;
44class AAResults;
45template <typename T> class ArrayRef;
46class DIExpression;
47class DILocalVariable;
48class MachineBasicBlock;
49class MachineFunction;
50class MachineRegisterInfo;
51class ModuleSlotTracker;
52class raw_ostream;
53template <typename T> class SmallVectorImpl;
54class SmallBitVector;
55class StringRef;
56class TargetInstrInfo;
57class TargetRegisterClass;
58class TargetRegisterInfo;
59
60//===----------------------------------------------------------------------===//
61/// Representation of each machine instruction.
62///
63/// This class isn't a POD type, but it must have a trivial destructor. When a
64/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
65/// without having their destructor called.
66///
67class MachineInstr
68 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
69 ilist_sentinel_tracking<true>> {
70public:
71 using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;
72
73 /// Flags to specify different kinds of comments to output in
74 /// assembly code. These flags carry semantic information not
75 /// otherwise easily derivable from the IR text.
76 ///
77 enum CommentFlag {
78 ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
79 NoSchedComment = 0x2,
80 TAsmComments = 0x4 // Target Asm comments should start from this value.
81 };
82
83 enum MIFlag {
84 NoFlags = 0,
85 FrameSetup = 1 << 0, // Instruction is used as a part of
86 // function frame setup code.
87 FrameDestroy = 1 << 1, // Instruction is used as a part of
88 // function frame destruction code.
89 BundledPred = 1 << 2, // Instruction has bundled predecessors.
90 BundledSucc = 1 << 3, // Instruction has bundled successors.
91 FmNoNans = 1 << 4, // Instruction does not support Fast
92 // math nan values.
93 FmNoInfs = 1 << 5, // Instruction does not support Fast
94 // math infinity values.
95 FmNsz = 1 << 6, // Instruction is not required to retain
96 // signed zero values.
97 FmArcp = 1 << 7, // Instruction supports Fast math
98 // reciprocal approximations.
99 FmContract = 1 << 8, // Instruction supports Fast math
100 // contraction operations like fma.
101 FmAfn = 1 << 9, // Instruction may map to Fast math
102 // intrinsic approximation.
103 FmReassoc = 1 << 10, // Instruction supports Fast math
104 // reassociation of operand order.
105 NoUWrap = 1 << 11, // Instruction supports binary operator
106 // no unsigned wrap.
107 NoSWrap = 1 << 12, // Instruction supports binary operator
108 // no signed wrap.
109 IsExact = 1 << 13, // Instruction supports division is
110 // known to be exact.
111 NoFPExcept = 1 << 14, // Instruction does not raise
112 // floatint-point exceptions.
113 NoMerge = 1 << 15, // Passes that drop source location info
114 // (e.g. branch folding) should skip
115 // this instruction.
116 Unpredictable = 1 << 16, // Instruction with unpredictable condition.
117 NoConvergent = 1 << 17, // Call does not require convergence guarantees.
118 NonNeg = 1 << 18, // The operand is non-negative.
119 Disjoint = 1 << 19, // Each bit is zero in at least one of the inputs.
120 NoUSWrap = 1 << 20, // Instruction supports geps
121 // no unsigned signed wrap.
122 };
123
124private:
125 const MCInstrDesc *MCID; // Instruction descriptor.
126 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
127
128 // Operands are allocated by an ArrayRecycler.
129 MachineOperand *Operands = nullptr; // Pointer to the first operand.
130
131#define LLVM_MI_NUMOPERANDS_BITS 24
132#define LLVM_MI_FLAGS_BITS 24
133#define LLVM_MI_ASMPRINTERFLAGS_BITS 8
134
135 /// Number of operands on instruction.
136 uint32_t NumOperands : LLVM_MI_NUMOPERANDS_BITS;
137
138 // OperandCapacity has uint8_t size, so it should be next to NumOperands
139 // to properly pack.
140 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
141 OperandCapacity CapOperands; // Capacity of the Operands array.
142
143 /// Various bits of additional information about the machine instruction.
144 uint32_t Flags : LLVM_MI_FLAGS_BITS;
145
146 /// Various bits of information used by the AsmPrinter to emit helpful
147 /// comments. This is *not* semantic information. Do not use this for
148 /// anything other than to convey comment information to AsmPrinter.
149 uint8_t AsmPrinterFlags : LLVM_MI_ASMPRINTERFLAGS_BITS;
150
151 /// Internal implementation detail class that provides out-of-line storage for
152 /// extra info used by the machine instruction when this info cannot be stored
153 /// in-line within the instruction itself.
154 ///
155 /// This has to be defined eagerly due to the implementation constraints of
156 /// `PointerSumType` where it is used.
157 class ExtraInfo final : TrailingObjects<ExtraInfo, MachineMemOperand *,
158 MCSymbol *, MDNode *, uint32_t> {
159 public:
160 static ExtraInfo *create(BumpPtrAllocator &Allocator,
161 ArrayRef<MachineMemOperand *> MMOs,
162 MCSymbol *PreInstrSymbol = nullptr,
163 MCSymbol *PostInstrSymbol = nullptr,
164 MDNode *HeapAllocMarker = nullptr,
165 MDNode *PCSections = nullptr, uint32_t CFIType = 0,
166 MDNode *MMRAs = nullptr) {
167 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
168 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
169 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
170 bool HasMMRAs = MMRAs != nullptr;
171 bool HasCFIType = CFIType != 0;
172 bool HasPCSections = PCSections != nullptr;
173 auto *Result = new (Allocator.Allocate(
174 Size: totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *, uint32_t>(
175 Counts: MMOs.size(), Counts: HasPreInstrSymbol + HasPostInstrSymbol,
176 Counts: HasHeapAllocMarker + HasPCSections + HasMMRAs, Counts: HasCFIType),
177 Alignment: alignof(ExtraInfo)))
178 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
179 HasHeapAllocMarker, HasPCSections, HasCFIType, HasMMRAs);
180
181 // Copy the actual data into the trailing objects.
182 std::copy(first: MMOs.begin(), last: MMOs.end(),
183 result: Result->getTrailingObjects<MachineMemOperand *>());
184
185 unsigned MDNodeIdx = 0;
186
187 if (HasPreInstrSymbol)
188 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
189 if (HasPostInstrSymbol)
190 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
191 PostInstrSymbol;
192 if (HasHeapAllocMarker)
193 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = HeapAllocMarker;
194 if (HasPCSections)
195 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = PCSections;
196 if (HasCFIType)
197 Result->getTrailingObjects<uint32_t>()[0] = CFIType;
198 if (HasMMRAs)
199 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = MMRAs;
200
201 return Result;
202 }
203
204 ArrayRef<MachineMemOperand *> getMMOs() const {
205 return ArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
206 }
207
208 MCSymbol *getPreInstrSymbol() const {
209 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
210 }
211
212 MCSymbol *getPostInstrSymbol() const {
213 return HasPostInstrSymbol
214 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
215 : nullptr;
216 }
217
218 MDNode *getHeapAllocMarker() const {
219 return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
220 }
221
222 MDNode *getPCSections() const {
223 return HasPCSections
224 ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker]
225 : nullptr;
226 }
227
228 uint32_t getCFIType() const {
229 return HasCFIType ? getTrailingObjects<uint32_t>()[0] : 0;
230 }
231
232 MDNode *getMMRAMetadata() const {
233 return HasMMRAs ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker +
234 HasPCSections]
235 : nullptr;
236 }
237
238 private:
239 friend TrailingObjects;
240
241 // Description of the extra info, used to interpret the actual optional
242 // data appended.
243 //
244 // Note that this is not terribly space optimized. This leaves a great deal
245 // of flexibility to fit more in here later.
246 const int NumMMOs;
247 const bool HasPreInstrSymbol;
248 const bool HasPostInstrSymbol;
249 const bool HasHeapAllocMarker;
250 const bool HasPCSections;
251 const bool HasCFIType;
252 const bool HasMMRAs;
253
254 // Implement the `TrailingObjects` internal API.
255 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
256 return NumMMOs;
257 }
258 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
259 return HasPreInstrSymbol + HasPostInstrSymbol;
260 }
261 size_t numTrailingObjects(OverloadToken<MDNode *>) const {
262 return HasHeapAllocMarker + HasPCSections;
263 }
264 size_t numTrailingObjects(OverloadToken<uint32_t>) const {
265 return HasCFIType;
266 }
267
268 // Just a boring constructor to allow us to initialize the sizes. Always use
269 // the `create` routine above.
270 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
271 bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType,
272 bool HasMMRAs)
273 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
274 HasPostInstrSymbol(HasPostInstrSymbol),
275 HasHeapAllocMarker(HasHeapAllocMarker), HasPCSections(HasPCSections),
276 HasCFIType(HasCFIType), HasMMRAs(HasMMRAs) {}
277 };
278
279 /// Enumeration of the kinds of inline extra info available. It is important
280 /// that the `MachineMemOperand` inline kind has a tag value of zero to make
281 /// it accessible as an `ArrayRef`.
282 enum ExtraInfoInlineKinds {
283 EIIK_MMO = 0,
284 EIIK_PreInstrSymbol,
285 EIIK_PostInstrSymbol,
286 EIIK_OutOfLine
287 };
288
289 // We store extra information about the instruction here. The common case is
290 // expected to be nothing or a single pointer (typically a MMO or a symbol).
291 // We work to optimize this common case by storing it inline here rather than
292 // requiring a separate allocation, but we fall back to an allocation when
293 // multiple pointers are needed.
294 PointerSumType<ExtraInfoInlineKinds,
295 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
296 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
297 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
298 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
299 Info;
300
301 DebugLoc DbgLoc; // Source line information.
302
303 /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
304 /// defined by this instruction.
305 unsigned DebugInstrNum;
306
307 /// Cached opcode from MCID.
308 uint16_t Opcode;
309
310 // Intrusive list support
311 friend struct ilist_traits<MachineInstr>;
312 friend struct ilist_callback_traits<MachineBasicBlock>;
313 void setParent(MachineBasicBlock *P) { Parent = P; }
314
315 /// This constructor creates a copy of the given
316 /// MachineInstr in the given MachineFunction.
317 MachineInstr(MachineFunction &, const MachineInstr &);
318
319 /// This constructor create a MachineInstr and add the implicit operands.
320 /// It reserves space for number of operands specified by
321 /// MCInstrDesc. An explicit DebugLoc is supplied.
322 MachineInstr(MachineFunction &, const MCInstrDesc &TID, DebugLoc DL,
323 bool NoImp = false);
324
325 // MachineInstrs are pool-allocated and owned by MachineFunction.
326 friend class MachineFunction;
327
328 void
329 dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
330 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
331
332 static bool opIsRegDef(const MachineOperand &Op) {
333 return Op.isReg() && Op.isDef();
334 }
335
336 static bool opIsRegUse(const MachineOperand &Op) {
337 return Op.isReg() && Op.isUse();
338 }
339
340public:
341 MachineInstr(const MachineInstr &) = delete;
342 MachineInstr &operator=(const MachineInstr &) = delete;
343 // Use MachineFunction::DeleteMachineInstr() instead.
344 ~MachineInstr() = delete;
345
346 const MachineBasicBlock* getParent() const { return Parent; }
347 MachineBasicBlock* getParent() { return Parent; }
348
349 /// Move the instruction before \p MovePos.
350 void moveBefore(MachineInstr *MovePos);
351
352 /// Return the function that contains the basic block that this instruction
353 /// belongs to.
354 ///
355 /// Note: this is undefined behaviour if the instruction does not have a
356 /// parent.
357 const MachineFunction *getMF() const;
358 MachineFunction *getMF() {
359 return const_cast<MachineFunction *>(
360 static_cast<const MachineInstr *>(this)->getMF());
361 }
362
363 /// Return the asm printer flags bitvector.
364 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
365
366 /// Clear the AsmPrinter bitvector.
367 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
368
369 /// Return whether an AsmPrinter flag is set.
370 bool getAsmPrinterFlag(CommentFlag Flag) const {
371 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
372 "Flag is out of range for the AsmPrinterFlags field");
373 return AsmPrinterFlags & Flag;
374 }
375
376 /// Set a flag for the AsmPrinter.
377 void setAsmPrinterFlag(uint8_t Flag) {
378 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
379 "Flag is out of range for the AsmPrinterFlags field");
380 AsmPrinterFlags |= Flag;
381 }
382
383 /// Clear specific AsmPrinter flags.
384 void clearAsmPrinterFlag(CommentFlag Flag) {
385 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
386 "Flag is out of range for the AsmPrinterFlags field");
387 AsmPrinterFlags &= ~Flag;
388 }
389
390 /// Return the MI flags bitvector.
391 uint32_t getFlags() const {
392 return Flags;
393 }
394
395 /// Return whether an MI flag is set.
396 bool getFlag(MIFlag Flag) const {
397 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
398 "Flag is out of range for the Flags field");
399 return Flags & Flag;
400 }
401
402 /// Set a MI flag.
403 void setFlag(MIFlag Flag) {
404 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
405 "Flag is out of range for the Flags field");
406 Flags |= (uint32_t)Flag;
407 }
408
409 void setFlags(unsigned flags) {
410 assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
411 "flags to be set are out of range for the Flags field");
412 // Filter out the automatically maintained flags.
413 unsigned Mask = BundledPred | BundledSucc;
414 Flags = (Flags & Mask) | (flags & ~Mask);
415 }
416
417 /// clearFlag - Clear a MI flag.
418 void clearFlag(MIFlag Flag) {
419 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
420 "Flag to clear is out of range for the Flags field");
421 Flags &= ~((uint32_t)Flag);
422 }
423
424 void clearFlags(unsigned flags) {
425 assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
426 "flags to be cleared are out of range for the Flags field");
427 Flags &= ~flags;
428 }
429
430 /// Return true if MI is in a bundle (but not the first MI in a bundle).
431 ///
432 /// A bundle looks like this before it's finalized:
433 /// ----------------
434 /// | MI |
435 /// ----------------
436 /// |
437 /// ----------------
438 /// | MI * |
439 /// ----------------
440 /// |
441 /// ----------------
442 /// | MI * |
443 /// ----------------
444 /// In this case, the first MI starts a bundle but is not inside a bundle, the
445 /// next 2 MIs are considered "inside" the bundle.
446 ///
447 /// After a bundle is finalized, it looks like this:
448 /// ----------------
449 /// | Bundle |
450 /// ----------------
451 /// |
452 /// ----------------
453 /// | MI * |
454 /// ----------------
455 /// |
456 /// ----------------
457 /// | MI * |
458 /// ----------------
459 /// |
460 /// ----------------
461 /// | MI * |
462 /// ----------------
463 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
464 /// a bundle, but the next three MIs are.
465 bool isInsideBundle() const {
466 return getFlag(Flag: BundledPred);
467 }
468
469 /// Return true if this instruction part of a bundle. This is true
470 /// if either itself or its following instruction is marked "InsideBundle".
471 bool isBundled() const {
472 return isBundledWithPred() || isBundledWithSucc();
473 }
474
475 /// Return true if this instruction is part of a bundle, and it is not the
476 /// first instruction in the bundle.
477 bool isBundledWithPred() const { return getFlag(Flag: BundledPred); }
478
479 /// Return true if this instruction is part of a bundle, and it is not the
480 /// last instruction in the bundle.
481 bool isBundledWithSucc() const { return getFlag(Flag: BundledSucc); }
482
483 /// Bundle this instruction with its predecessor. This can be an unbundled
484 /// instruction, or it can be the first instruction in a bundle.
485 void bundleWithPred();
486
487 /// Bundle this instruction with its successor. This can be an unbundled
488 /// instruction, or it can be the last instruction in a bundle.
489 void bundleWithSucc();
490
491 /// Break bundle above this instruction.
492 void unbundleFromPred();
493
494 /// Break bundle below this instruction.
495 void unbundleFromSucc();
496
497 /// Returns the debug location id of this MachineInstr.
498 const DebugLoc &getDebugLoc() const { return DbgLoc; }
499
500 /// Return the operand containing the offset to be used if this DBG_VALUE
501 /// instruction is indirect; will be an invalid register if this value is
502 /// not indirect, and an immediate with value 0 otherwise.
503 const MachineOperand &getDebugOffset() const {
504 assert(isNonListDebugValue() && "not a DBG_VALUE");
505 return getOperand(i: 1);
506 }
507 MachineOperand &getDebugOffset() {
508 assert(isNonListDebugValue() && "not a DBG_VALUE");
509 return getOperand(i: 1);
510 }
511
512 /// Return the operand for the debug variable referenced by
513 /// this DBG_VALUE instruction.
514 const MachineOperand &getDebugVariableOp() const;
515 MachineOperand &getDebugVariableOp();
516
517 /// Return the debug variable referenced by
518 /// this DBG_VALUE instruction.
519 const DILocalVariable *getDebugVariable() const;
520
521 /// Return the operand for the complex address expression referenced by
522 /// this DBG_VALUE instruction.
523 const MachineOperand &getDebugExpressionOp() const;
524 MachineOperand &getDebugExpressionOp();
525
526 /// Return the complex address expression referenced by
527 /// this DBG_VALUE instruction.
528 const DIExpression *getDebugExpression() const;
529
530 /// Return the debug label referenced by
531 /// this DBG_LABEL instruction.
532 const DILabel *getDebugLabel() const;
533
534 /// Fetch the instruction number of this MachineInstr. If it does not have
535 /// one already, a new and unique number will be assigned.
536 unsigned getDebugInstrNum();
537
538 /// Fetch instruction number of this MachineInstr -- but before it's inserted
539 /// into \p MF. Needed for transformations that create an instruction but
540 /// don't immediately insert them.
541 unsigned getDebugInstrNum(MachineFunction &MF);
542
543 /// Examine the instruction number of this MachineInstr. May be zero if
544 /// it hasn't been assigned a number yet.
545 unsigned peekDebugInstrNum() const { return DebugInstrNum; }
546
547 /// Set instruction number of this MachineInstr. Avoid using unless you're
548 /// deserializing this information.
549 void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
550
551 /// Drop any variable location debugging information associated with this
552 /// instruction. Use when an instruction is modified in such a way that it no
553 /// longer defines the value it used to. Variable locations using that value
554 /// will be dropped.
555 void dropDebugNumber() { DebugInstrNum = 0; }
556
557 /// Emit an error referring to the source location of this instruction.
558 /// This should only be used for inline assembly that is somehow
559 /// impossible to compile. Other errors should have been handled much
560 /// earlier.
561 ///
562 /// If this method returns, the caller should try to recover from the error.
563 void emitError(StringRef Msg) const;
564
565 /// Returns the target instruction descriptor of this MachineInstr.
566 const MCInstrDesc &getDesc() const { return *MCID; }
567
568 /// Returns the opcode of this MachineInstr.
569 unsigned getOpcode() const { return Opcode; }
570
571 /// Retuns the total number of operands.
572 unsigned getNumOperands() const { return NumOperands; }
573
574 /// Returns the total number of operands which are debug locations.
575 unsigned getNumDebugOperands() const {
576 return std::distance(first: debug_operands().begin(), last: debug_operands().end());
577 }
578
579 const MachineOperand& getOperand(unsigned i) const {
580 assert(i < getNumOperands() && "getOperand() out of range!");
581 return Operands[i];
582 }
583 MachineOperand& getOperand(unsigned i) {
584 assert(i < getNumOperands() && "getOperand() out of range!");
585 return Operands[i];
586 }
587
588 MachineOperand &getDebugOperand(unsigned Index) {
589 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
590 return *(debug_operands().begin() + Index);
591 }
592 const MachineOperand &getDebugOperand(unsigned Index) const {
593 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
594 return *(debug_operands().begin() + Index);
595 }
596
597 /// Returns whether this debug value has at least one debug operand with the
598 /// register \p Reg.
599 bool hasDebugOperandForReg(Register Reg) const {
600 return any_of(Range: debug_operands(), P: [Reg](const MachineOperand &Op) {
601 return Op.isReg() && Op.getReg() == Reg;
602 });
603 }
604
605 /// Returns a range of all of the operands that correspond to a debug use of
606 /// \p Reg.
607 template <typename Operand, typename Instruction>
608 static iterator_range<
609 filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
610 getDebugOperandsForReg(Instruction *MI, Register Reg) {
611 std::function<bool(Operand & Op)> OpUsesReg(
612 [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
613 return make_filter_range(MI->debug_operands(), OpUsesReg);
614 }
615 iterator_range<filter_iterator<const MachineOperand *,
616 std::function<bool(const MachineOperand &Op)>>>
617 getDebugOperandsForReg(Register Reg) const {
618 return MachineInstr::getDebugOperandsForReg<const MachineOperand,
619 const MachineInstr>(MI: this, Reg);
620 }
621 iterator_range<filter_iterator<MachineOperand *,
622 std::function<bool(MachineOperand &Op)>>>
623 getDebugOperandsForReg(Register Reg) {
624 return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
625 MI: this, Reg);
626 }
627
628 bool isDebugOperand(const MachineOperand *Op) const {
629 return Op >= adl_begin(range: debug_operands()) && Op <= adl_end(range: debug_operands());
630 }
631
632 unsigned getDebugOperandIndex(const MachineOperand *Op) const {
633 assert(isDebugOperand(Op) && "Expected a debug operand.");
634 return std::distance(first: adl_begin(range: debug_operands()), last: Op);
635 }
636
637 /// Returns the total number of definitions.
638 unsigned getNumDefs() const {
639 return getNumExplicitDefs() + MCID->implicit_defs().size();
640 }
641
642 /// Returns true if the instruction has implicit definition.
643 bool hasImplicitDef() const {
644 for (const MachineOperand &MO : implicit_operands())
645 if (MO.isDef() && MO.isImplicit())
646 return true;
647 return false;
648 }
649
650 /// Returns the implicit operands number.
651 unsigned getNumImplicitOperands() const {
652 return getNumOperands() - getNumExplicitOperands();
653 }
654
655 /// Return true if operand \p OpIdx is a subregister index.
656 bool isOperandSubregIdx(unsigned OpIdx) const {
657 assert(getOperand(OpIdx).isImm() && "Expected MO_Immediate operand type.");
658 if (isExtractSubreg() && OpIdx == 2)
659 return true;
660 if (isInsertSubreg() && OpIdx == 3)
661 return true;
662 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
663 return true;
664 if (isSubregToReg() && OpIdx == 3)
665 return true;
666 return false;
667 }
668
669 /// Returns the number of non-implicit operands.
670 unsigned getNumExplicitOperands() const;
671
672 /// Returns the number of non-implicit definitions.
673 unsigned getNumExplicitDefs() const;
674
675 /// iterator/begin/end - Iterate over all operands of a machine instruction.
676 using mop_iterator = MachineOperand *;
677 using const_mop_iterator = const MachineOperand *;
678
679 mop_iterator operands_begin() { return Operands; }
680 mop_iterator operands_end() { return Operands + NumOperands; }
681
682 const_mop_iterator operands_begin() const { return Operands; }
683 const_mop_iterator operands_end() const { return Operands + NumOperands; }
684
685 iterator_range<mop_iterator> operands() {
686 return make_range(x: operands_begin(), y: operands_end());
687 }
688 iterator_range<const_mop_iterator> operands() const {
689 return make_range(x: operands_begin(), y: operands_end());
690 }
691 iterator_range<mop_iterator> explicit_operands() {
692 return make_range(x: operands_begin(),
693 y: operands_begin() + getNumExplicitOperands());
694 }
695 iterator_range<const_mop_iterator> explicit_operands() const {
696 return make_range(x: operands_begin(),
697 y: operands_begin() + getNumExplicitOperands());
698 }
699 iterator_range<mop_iterator> implicit_operands() {
700 return make_range(x: explicit_operands().end(), y: operands_end());
701 }
702 iterator_range<const_mop_iterator> implicit_operands() const {
703 return make_range(x: explicit_operands().end(), y: operands_end());
704 }
705 /// Returns a range over all operands that are used to determine the variable
706 /// location for this DBG_VALUE instruction.
707 iterator_range<mop_iterator> debug_operands() {
708 assert((isDebugValueLike()) && "Must be a debug value instruction.");
709 return isNonListDebugValue()
710 ? make_range(x: operands_begin(), y: operands_begin() + 1)
711 : make_range(x: operands_begin() + 2, y: operands_end());
712 }
713 /// \copydoc debug_operands()
714 iterator_range<const_mop_iterator> debug_operands() const {
715 assert((isDebugValueLike()) && "Must be a debug value instruction.");
716 return isNonListDebugValue()
717 ? make_range(x: operands_begin(), y: operands_begin() + 1)
718 : make_range(x: operands_begin() + 2, y: operands_end());
719 }
720 /// Returns a range over all explicit operands that are register definitions.
721 /// Implicit definition are not included!
722 iterator_range<mop_iterator> defs() {
723 return make_range(x: operands_begin(),
724 y: operands_begin() + getNumExplicitDefs());
725 }
726 /// \copydoc defs()
727 iterator_range<const_mop_iterator> defs() const {
728 return make_range(x: operands_begin(),
729 y: operands_begin() + getNumExplicitDefs());
730 }
731 /// Returns a range that includes all operands that are register uses.
732 /// This may include unrelated operands which are not register uses.
733 iterator_range<mop_iterator> uses() {
734 return make_range(x: operands_begin() + getNumExplicitDefs(), y: operands_end());
735 }
736 /// \copydoc uses()
737 iterator_range<const_mop_iterator> uses() const {
738 return make_range(x: operands_begin() + getNumExplicitDefs(), y: operands_end());
739 }
740 iterator_range<mop_iterator> explicit_uses() {
741 return make_range(x: operands_begin() + getNumExplicitDefs(),
742 y: operands_begin() + getNumExplicitOperands());
743 }
744 iterator_range<const_mop_iterator> explicit_uses() const {
745 return make_range(x: operands_begin() + getNumExplicitDefs(),
746 y: operands_begin() + getNumExplicitOperands());
747 }
748
749 using filtered_mop_iterator =
750 filter_iterator<mop_iterator, bool (*)(const MachineOperand &)>;
751 using filtered_const_mop_iterator =
752 filter_iterator<const_mop_iterator, bool (*)(const MachineOperand &)>;
753
754 /// Returns an iterator range over all operands that are (explicit or
755 /// implicit) register defs.
756 iterator_range<filtered_mop_iterator> all_defs() {
757 return make_filter_range(Range: operands(), Pred: opIsRegDef);
758 }
759 /// \copydoc all_defs()
760 iterator_range<filtered_const_mop_iterator> all_defs() const {
761 return make_filter_range(Range: operands(), Pred: opIsRegDef);
762 }
763
764 /// Returns an iterator range over all operands that are (explicit or
765 /// implicit) register uses.
766 iterator_range<filtered_mop_iterator> all_uses() {
767 return make_filter_range(Range: uses(), Pred: opIsRegUse);
768 }
769 /// \copydoc all_uses()
770 iterator_range<filtered_const_mop_iterator> all_uses() const {
771 return make_filter_range(Range: uses(), Pred: opIsRegUse);
772 }
773
774 /// Returns the number of the operand iterator \p I points to.
775 unsigned getOperandNo(const_mop_iterator I) const {
776 return I - operands_begin();
777 }
778
779 /// Access to memory operands of the instruction. If there are none, that does
780 /// not imply anything about whether the function accesses memory. Instead,
781 /// the caller must behave conservatively.
782 ArrayRef<MachineMemOperand *> memoperands() const {
783 if (!Info)
784 return {};
785
786 if (Info.is<EIIK_MMO>())
787 return ArrayRef(Info.getAddrOfZeroTagPointer(), 1);
788
789 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
790 return EI->getMMOs();
791
792 return {};
793 }
794
795 /// Access to memory operands of the instruction.
796 ///
797 /// If `memoperands_begin() == memoperands_end()`, that does not imply
798 /// anything about whether the function accesses memory. Instead, the caller
799 /// must behave conservatively.
800 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
801
802 /// Access to memory operands of the instruction.
803 ///
804 /// If `memoperands_begin() == memoperands_end()`, that does not imply
805 /// anything about whether the function accesses memory. Instead, the caller
806 /// must behave conservatively.
807 mmo_iterator memoperands_end() const { return memoperands().end(); }
808
809 /// Return true if we don't have any memory operands which described the
810 /// memory access done by this instruction. If this is true, calling code
811 /// must be conservative.
812 bool memoperands_empty() const { return memoperands().empty(); }
813
814 /// Return true if this instruction has exactly one MachineMemOperand.
815 bool hasOneMemOperand() const { return memoperands().size() == 1; }
816
817 /// Return the number of memory operands.
818 unsigned getNumMemOperands() const { return memoperands().size(); }
819
820 /// Helper to extract a pre-instruction symbol if one has been added.
821 MCSymbol *getPreInstrSymbol() const {
822 if (!Info)
823 return nullptr;
824 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
825 return S;
826 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
827 return EI->getPreInstrSymbol();
828
829 return nullptr;
830 }
831
832 /// Helper to extract a post-instruction symbol if one has been added.
833 MCSymbol *getPostInstrSymbol() const {
834 if (!Info)
835 return nullptr;
836 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
837 return S;
838 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
839 return EI->getPostInstrSymbol();
840
841 return nullptr;
842 }
843
844 /// Helper to extract a heap alloc marker if one has been added.
845 MDNode *getHeapAllocMarker() const {
846 if (!Info)
847 return nullptr;
848 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
849 return EI->getHeapAllocMarker();
850
851 return nullptr;
852 }
853
854 /// Helper to extract PCSections metadata target sections.
855 MDNode *getPCSections() const {
856 if (!Info)
857 return nullptr;
858 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
859 return EI->getPCSections();
860
861 return nullptr;
862 }
863
864 /// Helper to extract mmra.op metadata.
865 MDNode *getMMRAMetadata() const {
866 if (!Info)
867 return nullptr;
868 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
869 return EI->getMMRAMetadata();
870 return nullptr;
871 }
872
873 /// Helper to extract a CFI type hash if one has been added.
874 uint32_t getCFIType() const {
875 if (!Info)
876 return 0;
877 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
878 return EI->getCFIType();
879
880 return 0;
881 }
882
883 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
884 /// queries but they are bundle aware.
885
886 enum QueryType {
887 IgnoreBundle, // Ignore bundles
888 AnyInBundle, // Return true if any instruction in bundle has property
889 AllInBundle // Return true if all instructions in bundle have property
890 };
891
892 /// Return true if the instruction (or in the case of a bundle,
893 /// the instructions inside the bundle) has the specified property.
894 /// The first argument is the property being queried.
895 /// The second argument indicates whether the query should look inside
896 /// instruction bundles.
897 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
898 assert(MCFlag < 64 &&
899 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
900 // Inline the fast path for unbundled or bundle-internal instructions.
901 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
902 return getDesc().getFlags() & (1ULL << MCFlag);
903
904 // If this is the first instruction in a bundle, take the slow path.
905 return hasPropertyInBundle(Mask: 1ULL << MCFlag, Type);
906 }
907
908 /// Return true if this is an instruction that should go through the usual
909 /// legalization steps.
910 bool isPreISelOpcode(QueryType Type = IgnoreBundle) const {
911 return hasProperty(MCFlag: MCID::PreISelOpcode, Type);
912 }
913
914 /// Return true if this instruction can have a variable number of operands.
915 /// In this case, the variable operands will be after the normal
916 /// operands but before the implicit definitions and uses (if any are
917 /// present).
918 bool isVariadic(QueryType Type = IgnoreBundle) const {
919 return hasProperty(MCFlag: MCID::Variadic, Type);
920 }
921
922 /// Set if this instruction has an optional definition, e.g.
923 /// ARM instructions which can set condition code if 's' bit is set.
924 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
925 return hasProperty(MCFlag: MCID::HasOptionalDef, Type);
926 }
927
928 /// Return true if this is a pseudo instruction that doesn't
929 /// correspond to a real machine instruction.
930 bool isPseudo(QueryType Type = IgnoreBundle) const {
931 return hasProperty(MCFlag: MCID::Pseudo, Type);
932 }
933
934 /// Return true if this instruction doesn't produce any output in the form of
935 /// executable instructions.
936 bool isMetaInstruction(QueryType Type = IgnoreBundle) const {
937 return hasProperty(MCFlag: MCID::Meta, Type);
938 }
939
940 bool isReturn(QueryType Type = AnyInBundle) const {
941 return hasProperty(MCFlag: MCID::Return, Type);
942 }
943
944 /// Return true if this is an instruction that marks the end of an EH scope,
945 /// i.e., a catchpad or a cleanuppad instruction.
946 bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
947 return hasProperty(MCFlag: MCID::EHScopeReturn, Type);
948 }
949
950 bool isCall(QueryType Type = AnyInBundle) const {
951 return hasProperty(MCFlag: MCID::Call, Type);
952 }
953
954 /// Return true if this is a call instruction that may have an associated
955 /// call site entry in the debug info.
956 bool isCandidateForCallSiteEntry(QueryType Type = IgnoreBundle) const;
957 /// Return true if copying, moving, or erasing this instruction requires
958 /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
959 /// \ref eraseCallSiteInfo).
960 bool shouldUpdateCallSiteInfo() const;
961
962 /// Returns true if the specified instruction stops control flow
963 /// from executing the instruction immediately following it. Examples include
964 /// unconditional branches and return instructions.
965 bool isBarrier(QueryType Type = AnyInBundle) const {
966 return hasProperty(MCFlag: MCID::Barrier, Type);
967 }
968
969 /// Returns true if this instruction part of the terminator for a basic block.
970 /// Typically this is things like return and branch instructions.
971 ///
972 /// Various passes use this to insert code into the bottom of a basic block,
973 /// but before control flow occurs.
974 bool isTerminator(QueryType Type = AnyInBundle) const {
975 return hasProperty(MCFlag: MCID::Terminator, Type);
976 }
977
978 /// Returns true if this is a conditional, unconditional, or indirect branch.
979 /// Predicates below can be used to discriminate between
980 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
981 /// get more information.
982 bool isBranch(QueryType Type = AnyInBundle) const {
983 return hasProperty(MCFlag: MCID::Branch, Type);
984 }
985
986 /// Return true if this is an indirect branch, such as a
987 /// branch through a register.
988 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
989 return hasProperty(MCFlag: MCID::IndirectBranch, Type);
990 }
991
992 /// Return true if this is a branch which may fall
993 /// through to the next instruction or may transfer control flow to some other
994 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
995 /// information about this branch.
996 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
997 return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
998 }
999
1000 /// Return true if this is a branch which always
1001 /// transfers control flow to some other block. The
1002 /// TargetInstrInfo::analyzeBranch method can be used to get more information
1003 /// about this branch.
1004 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
1005 return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
1006 }
1007
1008 /// Return true if this instruction has a predicate operand that
1009 /// controls execution. It may be set to 'always', or may be set to other
1010 /// values. There are various methods in TargetInstrInfo that can be used to
1011 /// control and modify the predicate in this instruction.
1012 bool isPredicable(QueryType Type = AllInBundle) const {
1013 // If it's a bundle than all bundled instructions must be predicable for this
1014 // to return true.
1015 return hasProperty(MCFlag: MCID::Predicable, Type);
1016 }
1017
1018 /// Return true if this instruction is a comparison.
1019 bool isCompare(QueryType Type = IgnoreBundle) const {
1020 return hasProperty(MCFlag: MCID::Compare, Type);
1021 }
1022
1023 /// Return true if this instruction is a move immediate
1024 /// (including conditional moves) instruction.
1025 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
1026 return hasProperty(MCFlag: MCID::MoveImm, Type);
1027 }
1028
1029 /// Return true if this instruction is a register move.
1030 /// (including moving values from subreg to reg)
1031 bool isMoveReg(QueryType Type = IgnoreBundle) const {
1032 return hasProperty(MCFlag: MCID::MoveReg, Type);
1033 }
1034
1035 /// Return true if this instruction is a bitcast instruction.
1036 bool isBitcast(QueryType Type = IgnoreBundle) const {
1037 return hasProperty(MCFlag: MCID::Bitcast, Type);
1038 }
1039
1040 /// Return true if this instruction is a select instruction.
1041 bool isSelect(QueryType Type = IgnoreBundle) const {
1042 return hasProperty(MCFlag: MCID::Select, Type);
1043 }
1044
1045 /// Return true if this instruction cannot be safely duplicated.
1046 /// For example, if the instruction has a unique labels attached
1047 /// to it, duplicating it would cause multiple definition errors.
1048 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
1049 if (getPreInstrSymbol() || getPostInstrSymbol())
1050 return true;
1051 return hasProperty(MCFlag: MCID::NotDuplicable, Type);
1052 }
1053
1054 /// Return true if this instruction is convergent.
1055 /// Convergent instructions can not be made control-dependent on any
1056 /// additional values.
1057 bool isConvergent(QueryType Type = AnyInBundle) const {
1058 if (isInlineAsm()) {
1059 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1060 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1061 return true;
1062 }
1063 if (getFlag(Flag: NoConvergent))
1064 return false;
1065 return hasProperty(MCFlag: MCID::Convergent, Type);
1066 }
1067
1068 /// Returns true if the specified instruction has a delay slot
1069 /// which must be filled by the code generator.
1070 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
1071 return hasProperty(MCFlag: MCID::DelaySlot, Type);
1072 }
1073
1074 /// Return true for instructions that can be folded as
1075 /// memory operands in other instructions. The most common use for this
1076 /// is instructions that are simple loads from memory that don't modify
1077 /// the loaded value in any way, but it can also be used for instructions
1078 /// that can be expressed as constant-pool loads, such as V_SETALLONES
1079 /// on x86, to allow them to be folded when it is beneficial.
1080 /// This should only be set on instructions that return a value in their
1081 /// only virtual register definition.
1082 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
1083 return hasProperty(MCFlag: MCID::FoldableAsLoad, Type);
1084 }
1085
1086 /// Return true if this instruction behaves
1087 /// the same way as the generic REG_SEQUENCE instructions.
1088 /// E.g., on ARM,
1089 /// dX VMOVDRR rY, rZ
1090 /// is equivalent to
1091 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
1092 ///
1093 /// Note that for the optimizers to be able to take advantage of
1094 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
1095 /// override accordingly.
1096 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
1097 return hasProperty(MCFlag: MCID::RegSequence, Type);
1098 }
1099
1100 /// Return true if this instruction behaves
1101 /// the same way as the generic EXTRACT_SUBREG instructions.
1102 /// E.g., on ARM,
1103 /// rX, rY VMOVRRD dZ
1104 /// is equivalent to two EXTRACT_SUBREG:
1105 /// rX = EXTRACT_SUBREG dZ, ssub_0
1106 /// rY = EXTRACT_SUBREG dZ, ssub_1
1107 ///
1108 /// Note that for the optimizers to be able to take advantage of
1109 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
1110 /// override accordingly.
1111 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
1112 return hasProperty(MCFlag: MCID::ExtractSubreg, Type);
1113 }
1114
1115 /// Return true if this instruction behaves
1116 /// the same way as the generic INSERT_SUBREG instructions.
1117 /// E.g., on ARM,
1118 /// dX = VSETLNi32 dY, rZ, Imm
1119 /// is equivalent to a INSERT_SUBREG:
1120 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
1121 ///
1122 /// Note that for the optimizers to be able to take advantage of
1123 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
1124 /// override accordingly.
1125 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
1126 return hasProperty(MCFlag: MCID::InsertSubreg, Type);
1127 }
1128
1129 //===--------------------------------------------------------------------===//
1130 // Side Effect Analysis
1131 //===--------------------------------------------------------------------===//
1132
1133 /// Return true if this instruction could possibly read memory.
1134 /// Instructions with this flag set are not necessarily simple load
1135 /// instructions, they may load a value and modify it, for example.
1136 bool mayLoad(QueryType Type = AnyInBundle) const {
1137 if (isInlineAsm()) {
1138 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1139 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1140 return true;
1141 }
1142 return hasProperty(MCFlag: MCID::MayLoad, Type);
1143 }
1144
1145 /// Return true if this instruction could possibly modify memory.
1146 /// Instructions with this flag set are not necessarily simple store
1147 /// instructions, they may store a modified value based on their operands, or
1148 /// may not actually modify anything, for example.
1149 bool mayStore(QueryType Type = AnyInBundle) const {
1150 if (isInlineAsm()) {
1151 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1152 if (ExtraInfo & InlineAsm::Extra_MayStore)
1153 return true;
1154 }
1155 return hasProperty(MCFlag: MCID::MayStore, Type);
1156 }
1157
1158 /// Return true if this instruction could possibly read or modify memory.
1159 bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
1160 return mayLoad(Type) || mayStore(Type);
1161 }
1162
1163 /// Return true if this instruction could possibly raise a floating-point
1164 /// exception. This is the case if the instruction is a floating-point
1165 /// instruction that can in principle raise an exception, as indicated
1166 /// by the MCID::MayRaiseFPException property, *and* at the same time,
1167 /// the instruction is used in a context where we expect floating-point
1168 /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
1169 bool mayRaiseFPException() const {
1170 return hasProperty(MCFlag: MCID::MayRaiseFPException) &&
1171 !getFlag(Flag: MachineInstr::MIFlag::NoFPExcept);
1172 }
1173
1174 //===--------------------------------------------------------------------===//
1175 // Flags that indicate whether an instruction can be modified by a method.
1176 //===--------------------------------------------------------------------===//
1177
1178 /// Return true if this may be a 2- or 3-address
1179 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
1180 /// result if Y and Z are exchanged. If this flag is set, then the
1181 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
1182 /// instruction.
1183 ///
1184 /// Note that this flag may be set on instructions that are only commutable
1185 /// sometimes. In these cases, the call to commuteInstruction will fail.
1186 /// Also note that some instructions require non-trivial modification to
1187 /// commute them.
1188 bool isCommutable(QueryType Type = IgnoreBundle) const {
1189 return hasProperty(MCFlag: MCID::Commutable, Type);
1190 }
1191
1192 /// Return true if this is a 2-address instruction
1193 /// which can be changed into a 3-address instruction if needed. Doing this
1194 /// transformation can be profitable in the register allocator, because it
1195 /// means that the instruction can use a 2-address form if possible, but
1196 /// degrade into a less efficient form if the source and dest register cannot
1197 /// be assigned to the same register. For example, this allows the x86
1198 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1199 /// is the same speed as the shift but has bigger code size.
1200 ///
1201 /// If this returns true, then the target must implement the
1202 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1203 /// is allowed to fail if the transformation isn't valid for this specific
1204 /// instruction (e.g. shl reg, 4 on x86).
1205 ///
1206 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
1207 return hasProperty(MCFlag: MCID::ConvertibleTo3Addr, Type);
1208 }
1209
1210 /// Return true if this instruction requires
1211 /// custom insertion support when the DAG scheduler is inserting it into a
1212 /// machine basic block. If this is true for the instruction, it basically
1213 /// means that it is a pseudo instruction used at SelectionDAG time that is
1214 /// expanded out into magic code by the target when MachineInstrs are formed.
1215 ///
1216 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1217 /// is used to insert this into the MachineBasicBlock.
1218 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
1219 return hasProperty(MCFlag: MCID::UsesCustomInserter, Type);
1220 }
1221
1222 /// Return true if this instruction requires *adjustment*
1223 /// after instruction selection by calling a target hook. For example, this
1224 /// can be used to fill in ARM 's' optional operand depending on whether
1225 /// the conditional flag register is used.
1226 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
1227 return hasProperty(MCFlag: MCID::HasPostISelHook, Type);
1228 }
1229
1230 /// Returns true if this instruction is a candidate for remat.
1231 /// This flag is deprecated, please don't use it anymore. If this
1232 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
1233 /// verify the instruction is really rematerializable.
1234 bool isRematerializable(QueryType Type = AllInBundle) const {
1235 // It's only possible to re-mat a bundle if all bundled instructions are
1236 // re-materializable.
1237 return hasProperty(MCFlag: MCID::Rematerializable, Type);
1238 }
1239
1240 /// Returns true if this instruction has the same cost (or less) than a move
1241 /// instruction. This is useful during certain types of optimizations
1242 /// (e.g., remat during two-address conversion or machine licm)
1243 /// where we would like to remat or hoist the instruction, but not if it costs
1244 /// more than moving the instruction into the appropriate register. Note, we
1245 /// are not marking copies from and to the same register class with this flag.
1246 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
1247 // Only returns true for a bundle if all bundled instructions are cheap.
1248 return hasProperty(MCFlag: MCID::CheapAsAMove, Type);
1249 }
1250
1251 /// Returns true if this instruction source operands
1252 /// have special register allocation requirements that are not captured by the
1253 /// operand register classes. e.g. ARM::STRD's two source registers must be an
1254 /// even / odd pair, ARM::STM registers have to be in ascending order.
1255 /// Post-register allocation passes should not attempt to change allocations
1256 /// for sources of instructions with this flag.
1257 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
1258 return hasProperty(MCFlag: MCID::ExtraSrcRegAllocReq, Type);
1259 }
1260
1261 /// Returns true if this instruction def operands
1262 /// have special register allocation requirements that are not captured by the
1263 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
1264 /// even / odd pair, ARM::LDM registers have to be in ascending order.
1265 /// Post-register allocation passes should not attempt to change allocations
1266 /// for definitions of instructions with this flag.
1267 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
1268 return hasProperty(MCFlag: MCID::ExtraDefRegAllocReq, Type);
1269 }
1270
1271 enum MICheckType {
1272 CheckDefs, // Check all operands for equality
1273 CheckKillDead, // Check all operands including kill / dead markers
1274 IgnoreDefs, // Ignore all definitions
1275 IgnoreVRegDefs // Ignore virtual register definitions
1276 };
1277
1278 /// Return true if this instruction is identical to \p Other.
1279 /// Two instructions are identical if they have the same opcode and all their
1280 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1281 /// Note that this means liveness related flags (dead, undef, kill) do not
1282 /// affect the notion of identical.
1283 bool isIdenticalTo(const MachineInstr &Other,
1284 MICheckType Check = CheckDefs) const;
1285
1286 /// Returns true if this instruction is a debug instruction that represents an
1287 /// identical debug value to \p Other.
1288 /// This function considers these debug instructions equivalent if they have
1289 /// identical variables, debug locations, and debug operands, and if the
1290 /// DIExpressions combined with the directness flags are equivalent.
1291 bool isEquivalentDbgInstr(const MachineInstr &Other) const;
1292
1293 /// Unlink 'this' from the containing basic block, and return it without
1294 /// deleting it.
1295 ///
1296 /// This function can not be used on bundled instructions, use
1297 /// removeFromBundle() to remove individual instructions from a bundle.
1298 MachineInstr *removeFromParent();
1299
1300 /// Unlink this instruction from its basic block and return it without
1301 /// deleting it.
1302 ///
1303 /// If the instruction is part of a bundle, the other instructions in the
1304 /// bundle remain bundled.
1305 MachineInstr *removeFromBundle();
1306
1307 /// Unlink 'this' from the containing basic block and delete it.
1308 ///
1309 /// If this instruction is the header of a bundle, the whole bundle is erased.
1310 /// This function can not be used for instructions inside a bundle, use
1311 /// eraseFromBundle() to erase individual bundled instructions.
1312 void eraseFromParent();
1313
1314 /// Unlink 'this' from its basic block and delete it.
1315 ///
1316 /// If the instruction is part of a bundle, the other instructions in the
1317 /// bundle remain bundled.
1318 void eraseFromBundle();
1319
1320 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1321 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1322 bool isAnnotationLabel() const {
1323 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1324 }
1325
1326 /// Returns true if the MachineInstr represents a label.
1327 bool isLabel() const {
1328 return isEHLabel() || isGCLabel() || isAnnotationLabel();
1329 }
1330
1331 bool isCFIInstruction() const {
1332 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1333 }
1334
1335 bool isPseudoProbe() const {
1336 return getOpcode() == TargetOpcode::PSEUDO_PROBE;
1337 }
1338
1339 // True if the instruction represents a position in the function.
1340 bool isPosition() const { return isLabel() || isCFIInstruction(); }
1341
1342 bool isNonListDebugValue() const {
1343 return getOpcode() == TargetOpcode::DBG_VALUE;
1344 }
1345 bool isDebugValueList() const {
1346 return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1347 }
1348 bool isDebugValue() const {
1349 return isNonListDebugValue() || isDebugValueList();
1350 }
1351 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1352 bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1353 bool isDebugValueLike() const { return isDebugValue() || isDebugRef(); }
1354 bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
1355 bool isDebugInstr() const {
1356 return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
1357 }
1358 bool isDebugOrPseudoInstr() const {
1359 return isDebugInstr() || isPseudoProbe();
1360 }
1361
1362 bool isDebugOffsetImm() const {
1363 return isNonListDebugValue() && getDebugOffset().isImm();
1364 }
1365
1366 /// A DBG_VALUE is indirect iff the location operand is a register and
1367 /// the offset operand is an immediate.
1368 bool isIndirectDebugValue() const {
1369 return isDebugOffsetImm() && getDebugOperand(Index: 0).isReg();
1370 }
1371
1372 /// A DBG_VALUE is an entry value iff its debug expression contains the
1373 /// DW_OP_LLVM_entry_value operation.
1374 bool isDebugEntryValue() const;
1375
1376 /// Return true if the instruction is a debug value which describes a part of
1377 /// a variable as unavailable.
1378 bool isUndefDebugValue() const {
1379 if (!isDebugValue())
1380 return false;
1381 // If any $noreg locations are given, this DV is undef.
1382 for (const MachineOperand &Op : debug_operands())
1383 if (Op.isReg() && !Op.getReg().isValid())
1384 return true;
1385 return false;
1386 }
1387
1388 bool isJumpTableDebugInfo() const {
1389 return getOpcode() == TargetOpcode::JUMP_TABLE_DEBUG_INFO;
1390 }
1391
1392 bool isPHI() const {
1393 return getOpcode() == TargetOpcode::PHI ||
1394 getOpcode() == TargetOpcode::G_PHI;
1395 }
1396 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1397 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1398 bool isInlineAsm() const {
1399 return getOpcode() == TargetOpcode::INLINEASM ||
1400 getOpcode() == TargetOpcode::INLINEASM_BR;
1401 }
1402 /// Returns true if the register operand can be folded with a load or store
1403 /// into a frame index. Does so by checking the InlineAsm::Flag immediate
1404 /// operand at OpId - 1.
1405 bool mayFoldInlineAsmRegOp(unsigned OpId) const;
1406
1407 bool isStackAligningInlineAsm() const;
1408 InlineAsm::AsmDialect getInlineAsmDialect() const;
1409
1410 bool isInsertSubreg() const {
1411 return getOpcode() == TargetOpcode::INSERT_SUBREG;
1412 }
1413
1414 bool isSubregToReg() const {
1415 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1416 }
1417
1418 bool isRegSequence() const {
1419 return getOpcode() == TargetOpcode::REG_SEQUENCE;
1420 }
1421
1422 bool isBundle() const {
1423 return getOpcode() == TargetOpcode::BUNDLE;
1424 }
1425
1426 bool isCopy() const {
1427 return getOpcode() == TargetOpcode::COPY;
1428 }
1429
1430 bool isFullCopy() const {
1431 return isCopy() && !getOperand(i: 0).getSubReg() && !getOperand(i: 1).getSubReg();
1432 }
1433
1434 bool isExtractSubreg() const {
1435 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1436 }
1437
1438 /// Return true if the instruction behaves like a copy.
1439 /// This does not include native copy instructions.
1440 bool isCopyLike() const {
1441 return isCopy() || isSubregToReg();
1442 }
1443
1444 /// Return true is the instruction is an identity copy.
1445 bool isIdentityCopy() const {
1446 return isCopy() && getOperand(i: 0).getReg() == getOperand(i: 1).getReg() &&
1447 getOperand(i: 0).getSubReg() == getOperand(i: 1).getSubReg();
1448 }
1449
1450 /// Return true if this is a transient instruction that is either very likely
1451 /// to be eliminated during register allocation (such as copy-like
1452 /// instructions), or if this instruction doesn't have an execution-time cost.
1453 bool isTransient() const {
1454 switch (getOpcode()) {
1455 default:
1456 return isMetaInstruction();
1457 // Copy-like instructions are usually eliminated during register allocation.
1458 case TargetOpcode::PHI:
1459 case TargetOpcode::G_PHI:
1460 case TargetOpcode::COPY:
1461 case TargetOpcode::INSERT_SUBREG:
1462 case TargetOpcode::SUBREG_TO_REG:
1463 case TargetOpcode::REG_SEQUENCE:
1464 return true;
1465 }
1466 }
1467
1468 /// Return the number of instructions inside the MI bundle, excluding the
1469 /// bundle header.
1470 ///
1471 /// This is the number of instructions that MachineBasicBlock::iterator
1472 /// skips, 0 for unbundled instructions.
1473 unsigned getBundleSize() const;
1474
1475 /// Return true if the MachineInstr reads the specified register.
1476 /// If TargetRegisterInfo is non-null, then it also checks if there
1477 /// is a read of a super-register.
1478 /// This does not count partial redefines of virtual registers as reads:
1479 /// %reg1024:6 = OP.
1480 bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1481 return findRegisterUseOperandIdx(Reg, TRI, isKill: false) != -1;
1482 }
1483
1484 /// Return true if the MachineInstr reads the specified virtual register.
1485 /// Take into account that a partial define is a
1486 /// read-modify-write operation.
1487 bool readsVirtualRegister(Register Reg) const {
1488 return readsWritesVirtualRegister(Reg).first;
1489 }
1490
1491 /// Return a pair of bools (reads, writes) indicating if this instruction
1492 /// reads or writes Reg. This also considers partial defines.
1493 /// If Ops is not null, all operand indices for Reg are added.
1494 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1495 SmallVectorImpl<unsigned> *Ops = nullptr) const;
1496
1497 /// Return true if the MachineInstr kills the specified register.
1498 /// If TargetRegisterInfo is non-null, then it also checks if there is
1499 /// a kill of a super-register.
1500 bool killsRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1501 return findRegisterUseOperandIdx(Reg, TRI, isKill: true) != -1;
1502 }
1503
1504 /// Return true if the MachineInstr fully defines the specified register.
1505 /// If TargetRegisterInfo is non-null, then it also checks
1506 /// if there is a def of a super-register.
1507 /// NOTE: It's ignoring subreg indices on virtual registers.
1508 bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1509 return findRegisterDefOperandIdx(Reg, TRI, isDead: false, Overlap: false) != -1;
1510 }
1511
1512 /// Return true if the MachineInstr modifies (fully define or partially
1513 /// define) the specified register.
1514 /// NOTE: It's ignoring subreg indices on virtual registers.
1515 bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1516 return findRegisterDefOperandIdx(Reg, TRI, isDead: false, Overlap: true) != -1;
1517 }
1518
1519 /// Returns true if the register is dead in this machine instruction.
1520 /// If TargetRegisterInfo is non-null, then it also checks
1521 /// if there is a dead def of a super-register.
1522 bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const {
1523 return findRegisterDefOperandIdx(Reg, TRI, isDead: true, Overlap: false) != -1;
1524 }
1525
1526 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1527 /// the given register (not considering sub/super-registers).
1528 bool hasRegisterImplicitUseOperand(Register Reg) const;
1529
1530 /// Returns the operand index that is a use of the specific register or -1
1531 /// if it is not found. It further tightens the search criteria to a use
1532 /// that kills the register if isKill is true.
1533 int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI,
1534 bool isKill = false) const;
1535
1536 /// Wrapper for findRegisterUseOperandIdx, it returns
1537 /// a pointer to the MachineOperand rather than an index.
1538 MachineOperand *findRegisterUseOperand(Register Reg,
1539 const TargetRegisterInfo *TRI,
1540 bool isKill = false) {
1541 int Idx = findRegisterUseOperandIdx(Reg, TRI, isKill);
1542 return (Idx == -1) ? nullptr : &getOperand(i: Idx);
1543 }
1544
1545 const MachineOperand *findRegisterUseOperand(Register Reg,
1546 const TargetRegisterInfo *TRI,
1547 bool isKill = false) const {
1548 return const_cast<MachineInstr *>(this)->findRegisterUseOperand(Reg, TRI,
1549 isKill);
1550 }
1551
1552 /// Returns the operand index that is a def of the specified register or
1553 /// -1 if it is not found. If isDead is true, defs that are not dead are
1554 /// skipped. If Overlap is true, then it also looks for defs that merely
1555 /// overlap the specified register. If TargetRegisterInfo is non-null,
1556 /// then it also checks if there is a def of a super-register.
1557 /// This may also return a register mask operand when Overlap is true.
1558 int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI,
1559 bool isDead = false,
1560 bool Overlap = false) const;
1561
1562 /// Wrapper for findRegisterDefOperandIdx, it returns
1563 /// a pointer to the MachineOperand rather than an index.
1564 MachineOperand *findRegisterDefOperand(Register Reg,
1565 const TargetRegisterInfo *TRI,
1566 bool isDead = false,
1567 bool Overlap = false) {
1568 int Idx = findRegisterDefOperandIdx(Reg, TRI, isDead, Overlap);
1569 return (Idx == -1) ? nullptr : &getOperand(i: Idx);
1570 }
1571
1572 const MachineOperand *findRegisterDefOperand(Register Reg,
1573 const TargetRegisterInfo *TRI,
1574 bool isDead = false,
1575 bool Overlap = false) const {
1576 return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1577 Reg, TRI, isDead, Overlap);
1578 }
1579
1580 /// Find the index of the first operand in the
1581 /// operand list that is used to represent the predicate. It returns -1 if
1582 /// none is found.
1583 int findFirstPredOperandIdx() const;
1584
1585 /// Find the index of the flag word operand that
1586 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1587 /// getOperand(OpIdx) does not belong to an inline asm operand group.
1588 ///
1589 /// If GroupNo is not NULL, it will receive the number of the operand group
1590 /// containing OpIdx.
1591 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1592
1593 /// Compute the static register class constraint for operand OpIdx.
1594 /// For normal instructions, this is derived from the MCInstrDesc.
1595 /// For inline assembly it is derived from the flag words.
1596 ///
1597 /// Returns NULL if the static register class constraint cannot be
1598 /// determined.
1599 const TargetRegisterClass*
1600 getRegClassConstraint(unsigned OpIdx,
1601 const TargetInstrInfo *TII,
1602 const TargetRegisterInfo *TRI) const;
1603
1604 /// Applies the constraints (def/use) implied by this MI on \p Reg to
1605 /// the given \p CurRC.
1606 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1607 /// instructions inside the bundle will be taken into account. In other words,
1608 /// this method accumulates all the constraints of the operand of this MI and
1609 /// the related bundle if MI is a bundle or inside a bundle.
1610 ///
1611 /// Returns the register class that satisfies both \p CurRC and the
1612 /// constraints set by MI. Returns NULL if such a register class does not
1613 /// exist.
1614 ///
1615 /// \pre CurRC must not be NULL.
1616 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1617 Register Reg, const TargetRegisterClass *CurRC,
1618 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1619 bool ExploreBundle = false) const;
1620
1621 /// Applies the constraints (def/use) implied by the \p OpIdx operand
1622 /// to the given \p CurRC.
1623 ///
1624 /// Returns the register class that satisfies both \p CurRC and the
1625 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1626 /// does not exist.
1627 ///
1628 /// \pre CurRC must not be NULL.
1629 /// \pre The operand at \p OpIdx must be a register.
1630 const TargetRegisterClass *
1631 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1632 const TargetInstrInfo *TII,
1633 const TargetRegisterInfo *TRI) const;
1634
1635 /// Add a tie between the register operands at DefIdx and UseIdx.
1636 /// The tie will cause the register allocator to ensure that the two
1637 /// operands are assigned the same physical register.
1638 ///
1639 /// Tied operands are managed automatically for explicit operands in the
1640 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1641 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1642
1643 /// Given the index of a tied register operand, find the
1644 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1645 /// index of the tied operand which must exist.
1646 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1647
1648 /// Given the index of a register def operand,
1649 /// check if the register def is tied to a source operand, due to either
1650 /// two-address elimination or inline assembly constraints. Returns the
1651 /// first tied use operand index by reference if UseOpIdx is not null.
1652 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1653 unsigned *UseOpIdx = nullptr) const {
1654 const MachineOperand &MO = getOperand(i: DefOpIdx);
1655 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1656 return false;
1657 if (UseOpIdx)
1658 *UseOpIdx = findTiedOperandIdx(OpIdx: DefOpIdx);
1659 return true;
1660 }
1661
1662 /// Return true if the use operand of the specified index is tied to a def
1663 /// operand. It also returns the def operand index by reference if DefOpIdx
1664 /// is not null.
1665 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1666 unsigned *DefOpIdx = nullptr) const {
1667 const MachineOperand &MO = getOperand(i: UseOpIdx);
1668 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1669 return false;
1670 if (DefOpIdx)
1671 *DefOpIdx = findTiedOperandIdx(OpIdx: UseOpIdx);
1672 return true;
1673 }
1674
1675 /// Clears kill flags on all operands.
1676 void clearKillInfo();
1677
1678 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1679 /// properly composing subreg indices where necessary.
1680 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1681 const TargetRegisterInfo &RegInfo);
1682
1683 /// We have determined MI kills a register. Look for the
1684 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1685 /// add a implicit operand if it's not found. Returns true if the operand
1686 /// exists / is added.
1687 bool addRegisterKilled(Register IncomingReg,
1688 const TargetRegisterInfo *RegInfo,
1689 bool AddIfNotFound = false);
1690
1691 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1692 /// all aliasing registers.
1693 void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);
1694
1695 /// We have determined MI defined a register without a use.
1696 /// Look for the operand that defines it and mark it as IsDead. If
1697 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1698 /// true if the operand exists / is added.
1699 bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
1700 bool AddIfNotFound = false);
1701
1702 /// Clear all dead flags on operands defining register @p Reg.
1703 void clearRegisterDeads(Register Reg);
1704
1705 /// Mark all subregister defs of register @p Reg with the undef flag.
1706 /// This function is used when we determined to have a subregister def in an
1707 /// otherwise undefined super register.
1708 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1709
1710 /// We have determined MI defines a register. Make sure there is an operand
1711 /// defining Reg.
1712 void addRegisterDefined(Register Reg,
1713 const TargetRegisterInfo *RegInfo = nullptr);
1714
1715 /// Mark every physreg used by this instruction as
1716 /// dead except those in the UsedRegs list.
1717 ///
1718 /// On instructions with register mask operands, also add implicit-def
1719 /// operands for all registers in UsedRegs.
1720 void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
1721 const TargetRegisterInfo &TRI);
1722
1723 /// Return true if it is safe to move this instruction. If
1724 /// SawStore is set to true, it means that there is a store (or call) between
1725 /// the instruction's location and its intended destination.
1726 bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1727
1728 /// Returns true if this instruction's memory access aliases the memory
1729 /// access of Other.
1730 //
1731 /// Assumes any physical registers used to compute addresses
1732 /// have the same value for both instructions. Returns false if neither
1733 /// instruction writes to memory.
1734 ///
1735 /// @param AA Optional alias analysis, used to compare memory operands.
1736 /// @param Other MachineInstr to check aliasing against.
1737 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1738 bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1739
1740 /// Return true if this instruction may have an ordered
1741 /// or volatile memory reference, or if the information describing the memory
1742 /// reference is not available. Return false if it is known to have no
1743 /// ordered or volatile memory references.
1744 bool hasOrderedMemoryRef() const;
1745
1746 /// Return true if this load instruction never traps and points to a memory
1747 /// location whose value doesn't change during the execution of this function.
1748 ///
1749 /// Examples include loading a value from the constant pool or from the
1750 /// argument area of a function (if it does not change). If the instruction
1751 /// does multiple loads, this returns true only if all of the loads are
1752 /// dereferenceable and invariant.
1753 bool isDereferenceableInvariantLoad() const;
1754
1755 /// If the specified instruction is a PHI that always merges together the
1756 /// same virtual register, return the register, otherwise return 0.
1757 unsigned isConstantValuePHI() const;
1758
1759 /// Return true if this instruction has side effects that are not modeled
1760 /// by mayLoad / mayStore, etc.
1761 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1762 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1763 /// INLINEASM instruction, in which case the side effect property is encoded
1764 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1765 ///
1766 bool hasUnmodeledSideEffects() const;
1767
1768 /// Returns true if it is illegal to fold a load across this instruction.
1769 bool isLoadFoldBarrier() const;
1770
1771 /// Return true if all the defs of this instruction are dead.
1772 bool allDefsAreDead() const;
1773
1774 /// Return true if all the implicit defs of this instruction are dead.
1775 bool allImplicitDefsAreDead() const;
1776
1777 /// Return a valid size if the instruction is a spill instruction.
1778 std::optional<LocationSize> getSpillSize(const TargetInstrInfo *TII) const;
1779
1780 /// Return a valid size if the instruction is a folded spill instruction.
1781 std::optional<LocationSize>
1782 getFoldedSpillSize(const TargetInstrInfo *TII) const;
1783
1784 /// Return a valid size if the instruction is a restore instruction.
1785 std::optional<LocationSize> getRestoreSize(const TargetInstrInfo *TII) const;
1786
1787 /// Return a valid size if the instruction is a folded restore instruction.
1788 std::optional<LocationSize>
1789 getFoldedRestoreSize(const TargetInstrInfo *TII) const;
1790
1791 /// Copy implicit register operands from specified
1792 /// instruction to this instruction.
1793 void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1794
1795 /// Debugging support
1796 /// @{
1797 /// Determine the generic type to be printed (if needed) on uses and defs.
1798 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1799 const MachineRegisterInfo &MRI) const;
1800
1801 /// Return true when an instruction has tied register that can't be determined
1802 /// by the instruction's descriptor. This is useful for MIR printing, to
1803 /// determine whether we need to print the ties or not.
1804 bool hasComplexRegisterTies() const;
1805
1806 /// Print this MI to \p OS.
1807 /// Don't print information that can be inferred from other instructions if
1808 /// \p IsStandalone is false. It is usually true when only a fragment of the
1809 /// function is printed.
1810 /// Only print the defs and the opcode if \p SkipOpers is true.
1811 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1812 /// Otherwise, also print the debug loc, with a terminating newline.
1813 /// \p TII is used to print the opcode name. If it's not present, but the
1814 /// MI is in a function, the opcode will be printed using the function's TII.
1815 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1816 bool SkipDebugLoc = false, bool AddNewLine = true,
1817 const TargetInstrInfo *TII = nullptr) const;
1818 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1819 bool SkipOpers = false, bool SkipDebugLoc = false,
1820 bool AddNewLine = true,
1821 const TargetInstrInfo *TII = nullptr) const;
1822 void dump() const;
1823 /// Print on dbgs() the current instruction and the instructions defining its
1824 /// operands and so on until we reach \p MaxDepth.
1825 void dumpr(const MachineRegisterInfo &MRI,
1826 unsigned MaxDepth = UINT_MAX) const;
1827 /// @}
1828
1829 //===--------------------------------------------------------------------===//
1830 // Accessors used to build up machine instructions.
1831
1832 /// Add the specified operand to the instruction. If it is an implicit
1833 /// operand, it is added to the end of the operand list. If it is an
1834 /// explicit operand it is added at the end of the explicit operand list
1835 /// (before the first implicit operand).
1836 ///
1837 /// MF must be the machine function that was used to allocate this
1838 /// instruction.
1839 ///
1840 /// MachineInstrBuilder provides a more convenient interface for creating
1841 /// instructions and adding operands.
1842 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1843
1844 /// Add an operand without providing an MF reference. This only works for
1845 /// instructions that are inserted in a basic block.
1846 ///
1847 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1848 /// preferred.
1849 void addOperand(const MachineOperand &Op);
1850
1851 /// Inserts Ops BEFORE It. Can untie/retie tied operands.
1852 void insert(mop_iterator InsertBefore, ArrayRef<MachineOperand> Ops);
1853
1854 /// Replace the instruction descriptor (thus opcode) of
1855 /// the current instruction with a new one.
1856 void setDesc(const MCInstrDesc &TID);
1857
1858 /// Replace current source information with new such.
1859 /// Avoid using this, the constructor argument is preferable.
1860 void setDebugLoc(DebugLoc DL) {
1861 DbgLoc = std::move(DL);
1862 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
1863 }
1864
1865 /// Erase an operand from an instruction, leaving it with one
1866 /// fewer operand than it started with.
1867 void removeOperand(unsigned OpNo);
1868
1869 /// Clear this MachineInstr's memory reference descriptor list. This resets
1870 /// the memrefs to their most conservative state. This should be used only
1871 /// as a last resort since it greatly pessimizes our knowledge of the memory
1872 /// access performed by the instruction.
1873 void dropMemRefs(MachineFunction &MF);
1874
1875 /// Assign this MachineInstr's memory reference descriptor list.
1876 ///
1877 /// Unlike other methods, this *will* allocate them into a new array
1878 /// associated with the provided `MachineFunction`.
1879 void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs);
1880
1881 /// Add a MachineMemOperand to the machine instruction.
1882 /// This function should be used only occasionally. The setMemRefs function
1883 /// is the primary method for setting up a MachineInstr's MemRefs list.
1884 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1885
1886 /// Clone another MachineInstr's memory reference descriptor list and replace
1887 /// ours with it.
1888 ///
1889 /// Note that `*this` may be the incoming MI!
1890 ///
1891 /// Prefer this API whenever possible as it can avoid allocations in common
1892 /// cases.
1893 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1894
1895 /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1896 /// list and replace ours with it.
1897 ///
1898 /// Note that `*this` may be one of the incoming MIs!
1899 ///
1900 /// Prefer this API whenever possible as it can avoid allocations in common
1901 /// cases.
1902 void cloneMergedMemRefs(MachineFunction &MF,
1903 ArrayRef<const MachineInstr *> MIs);
1904
1905 /// Set a symbol that will be emitted just prior to the instruction itself.
1906 ///
1907 /// Setting this to a null pointer will remove any such symbol.
1908 ///
1909 /// FIXME: This is not fully implemented yet.
1910 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1911
1912 /// Set a symbol that will be emitted just after the instruction itself.
1913 ///
1914 /// Setting this to a null pointer will remove any such symbol.
1915 ///
1916 /// FIXME: This is not fully implemented yet.
1917 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1918
1919 /// Clone another MachineInstr's pre- and post- instruction symbols and
1920 /// replace ours with it.
1921 void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);
1922
1923 /// Set a marker on instructions that denotes where we should create and emit
1924 /// heap alloc site labels. This waits until after instruction selection and
1925 /// optimizations to create the label, so it should still work if the
1926 /// instruction is removed or duplicated.
1927 void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);
1928
1929 // Set metadata on instructions that say which sections to emit instruction
1930 // addresses into.
1931 void setPCSections(MachineFunction &MF, MDNode *MD);
1932
1933 void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs);
1934
1935 /// Set the CFI type for the instruction.
1936 void setCFIType(MachineFunction &MF, uint32_t Type);
1937
1938 /// Return the MIFlags which represent both MachineInstrs. This
1939 /// should be used when merging two MachineInstrs into one. This routine does
1940 /// not modify the MIFlags of this MachineInstr.
1941 uint32_t mergeFlagsWith(const MachineInstr& Other) const;
1942
1943 static uint32_t copyFlagsFromInstruction(const Instruction &I);
1944
1945 /// Copy all flags to MachineInst MIFlags
1946 void copyIRFlags(const Instruction &I);
1947
1948 /// Break any tie involving OpIdx.
1949 void untieRegOperand(unsigned OpIdx) {
1950 MachineOperand &MO = getOperand(i: OpIdx);
1951 if (MO.isReg() && MO.isTied()) {
1952 getOperand(i: findTiedOperandIdx(OpIdx)).TiedTo = 0;
1953 MO.TiedTo = 0;
1954 }
1955 }
1956
1957 /// Add all implicit def and use operands to this instruction.
1958 void addImplicitDefUseOperands(MachineFunction &MF);
1959
1960 /// Scan instructions immediately following MI and collect any matching
1961 /// DBG_VALUEs.
1962 void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);
1963
1964 /// Find all DBG_VALUEs that point to the register def in this instruction
1965 /// and point them to \p Reg instead.
1966 void changeDebugValuesDefReg(Register Reg);
1967
1968 /// Sets all register debug operands in this debug value instruction to be
1969 /// undef.
1970 void setDebugValueUndef() {
1971 assert(isDebugValue() && "Must be a debug value instruction.");
1972 for (MachineOperand &MO : debug_operands()) {
1973 if (MO.isReg()) {
1974 MO.setReg(0);
1975 MO.setSubReg(0);
1976 }
1977 }
1978 }
1979
1980 std::tuple<Register, Register> getFirst2Regs() const {
1981 return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg());
1982 }
1983
1984 std::tuple<Register, Register, Register> getFirst3Regs() const {
1985 return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg(),
1986 getOperand(i: 2).getReg());
1987 }
1988
1989 std::tuple<Register, Register, Register, Register> getFirst4Regs() const {
1990 return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg(),
1991 getOperand(i: 2).getReg(), getOperand(i: 3).getReg());
1992 }
1993
1994 std::tuple<Register, Register, Register, Register, Register>
1995 getFirst5Regs() const {
1996 return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg(),
1997 getOperand(i: 2).getReg(), getOperand(i: 3).getReg(),
1998 getOperand(i: 4).getReg());
1999 }
2000
2001 std::tuple<LLT, LLT> getFirst2LLTs() const;
2002 std::tuple<LLT, LLT, LLT> getFirst3LLTs() const;
2003 std::tuple<LLT, LLT, LLT, LLT> getFirst4LLTs() const;
2004 std::tuple<LLT, LLT, LLT, LLT, LLT> getFirst5LLTs() const;
2005
2006 std::tuple<Register, LLT, Register, LLT> getFirst2RegLLTs() const;
2007 std::tuple<Register, LLT, Register, LLT, Register, LLT>
2008 getFirst3RegLLTs() const;
2009 std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2010 getFirst4RegLLTs() const;
2011 std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT,
2012 Register, LLT>
2013 getFirst5RegLLTs() const;
2014
2015private:
2016 /// If this instruction is embedded into a MachineFunction, return the
2017 /// MachineRegisterInfo object for the current function, otherwise
2018 /// return null.
2019 MachineRegisterInfo *getRegInfo();
2020 const MachineRegisterInfo *getRegInfo() const;
2021
2022 /// Unlink all of the register operands in this instruction from their
2023 /// respective use lists. This requires that the operands already be on their
2024 /// use lists.
2025 void removeRegOperandsFromUseLists(MachineRegisterInfo&);
2026
2027 /// Add all of the register operands in this instruction from their
2028 /// respective use lists. This requires that the operands not be on their
2029 /// use lists yet.
2030 void addRegOperandsToUseLists(MachineRegisterInfo&);
2031
2032 /// Slow path for hasProperty when we're dealing with a bundle.
2033 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
2034
2035 /// Implements the logic of getRegClassConstraintEffectForVReg for the
2036 /// this MI and the given operand index \p OpIdx.
2037 /// If the related operand does not constrained Reg, this returns CurRC.
2038 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
2039 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
2040 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
2041
2042 /// Stores extra instruction information inline or allocates as ExtraInfo
2043 /// based on the number of pointers.
2044 void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
2045 MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
2046 MDNode *HeapAllocMarker, MDNode *PCSections,
2047 uint32_t CFIType, MDNode *MMRAs);
2048};
2049
2050/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
2051/// instruction rather than by pointer value.
2052/// The hashing and equality testing functions ignore definitions so this is
2053/// useful for CSE, etc.
2054struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
2055 static inline MachineInstr *getEmptyKey() {
2056 return nullptr;
2057 }
2058
2059 static inline MachineInstr *getTombstoneKey() {
2060 return reinterpret_cast<MachineInstr*>(-1);
2061 }
2062
2063 static unsigned getHashValue(const MachineInstr* const &MI);
2064
2065 static bool isEqual(const MachineInstr* const &LHS,
2066 const MachineInstr* const &RHS) {
2067 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
2068 LHS == getEmptyKey() || LHS == getTombstoneKey())
2069 return LHS == RHS;
2070 return LHS->isIdenticalTo(Other: *RHS, Check: MachineInstr::IgnoreVRegDefs);
2071 }
2072};
2073
2074//===----------------------------------------------------------------------===//
2075// Debugging Support
2076
2077inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
2078 MI.print(OS);
2079 return OS;
2080}
2081
2082} // end namespace llvm
2083
2084#endif // LLVM_CODEGEN_MACHINEINSTR_H
2085