| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Machine Code Emitter *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | uint64_t ARMMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
| 10 | SmallVectorImpl<MCFixup> &Fixups, |
| 11 | const MCSubtargetInfo &STI) const { |
| 12 | static const uint64_t InstBits[] = { |
| 13 | UINT64_C(44040192), // ADCri |
| 14 | UINT64_C(10485760), // ADCrr |
| 15 | UINT64_C(10485760), // ADCrsi |
| 16 | UINT64_C(10485776), // ADCrsr |
| 17 | UINT64_C(41943040), // ADDri |
| 18 | UINT64_C(8388608), // ADDrr |
| 19 | UINT64_C(8388608), // ADDrsi |
| 20 | UINT64_C(8388624), // ADDrsr |
| 21 | UINT64_C(34537472), // ADR |
| 22 | UINT64_C(4088398656), // AESD |
| 23 | UINT64_C(4088398592), // AESE |
| 24 | UINT64_C(4088398784), // AESIMC |
| 25 | UINT64_C(4088398720), // AESMC |
| 26 | UINT64_C(33554432), // ANDri |
| 27 | UINT64_C(0), // ANDrr |
| 28 | UINT64_C(0), // ANDrsi |
| 29 | UINT64_C(16), // ANDrsr |
| 30 | UINT64_C(4261416192), // BF16VDOTI_VDOTD |
| 31 | UINT64_C(4261416256), // BF16VDOTI_VDOTQ |
| 32 | UINT64_C(4227861760), // BF16VDOTS_VDOTD |
| 33 | UINT64_C(4227861824), // BF16VDOTS_VDOTQ |
| 34 | UINT64_C(4088792640), // BF16_VCVT |
| 35 | UINT64_C(246614336), // BF16_VCVTB |
| 36 | UINT64_C(246614464), // BF16_VCVTT |
| 37 | UINT64_C(130023455), // BFC |
| 38 | UINT64_C(130023440), // BFI |
| 39 | UINT64_C(62914560), // BICri |
| 40 | UINT64_C(29360128), // BICrr |
| 41 | UINT64_C(29360128), // BICrsi |
| 42 | UINT64_C(29360144), // BICrsr |
| 43 | UINT64_C(3776970864), // BKPT |
| 44 | UINT64_C(3942645760), // BL |
| 45 | UINT64_C(3778019120), // BLX |
| 46 | UINT64_C(19922736), // BLX_pred |
| 47 | UINT64_C(4194304000), // BLXi |
| 48 | UINT64_C(184549376), // BL_pred |
| 49 | UINT64_C(3778019088), // BX |
| 50 | UINT64_C(19922720), // BXJ |
| 51 | UINT64_C(19922718), // BX_RET |
| 52 | UINT64_C(19922704), // BX_pred |
| 53 | UINT64_C(167772160), // Bcc |
| 54 | UINT64_C(3992977408), // CDE_CX1 |
| 55 | UINT64_C(4261412864), // CDE_CX1A |
| 56 | UINT64_C(3992977472), // CDE_CX1D |
| 57 | UINT64_C(4261412928), // CDE_CX1DA |
| 58 | UINT64_C(3997171712), // CDE_CX2 |
| 59 | UINT64_C(4265607168), // CDE_CX2A |
| 60 | UINT64_C(3997171776), // CDE_CX2D |
| 61 | UINT64_C(4265607232), // CDE_CX2DA |
| 62 | UINT64_C(4001366016), // CDE_CX3 |
| 63 | UINT64_C(4269801472), // CDE_CX3A |
| 64 | UINT64_C(4001366080), // CDE_CX3D |
| 65 | UINT64_C(4269801536), // CDE_CX3DA |
| 66 | UINT64_C(4246732800), // CDE_VCX1A_fpdp |
| 67 | UINT64_C(4229955584), // CDE_VCX1A_fpsp |
| 68 | UINT64_C(4229955648), // CDE_VCX1A_vec |
| 69 | UINT64_C(3978297344), // CDE_VCX1_fpdp |
| 70 | UINT64_C(3961520128), // CDE_VCX1_fpsp |
| 71 | UINT64_C(3961520192), // CDE_VCX1_vec |
| 72 | UINT64_C(4247781376), // CDE_VCX2A_fpdp |
| 73 | UINT64_C(4231004160), // CDE_VCX2A_fpsp |
| 74 | UINT64_C(4231004224), // CDE_VCX2A_vec |
| 75 | UINT64_C(3979345920), // CDE_VCX2_fpdp |
| 76 | UINT64_C(3962568704), // CDE_VCX2_fpsp |
| 77 | UINT64_C(3962568768), // CDE_VCX2_vec |
| 78 | UINT64_C(4253024256), // CDE_VCX3A_fpdp |
| 79 | UINT64_C(4236247040), // CDE_VCX3A_fpsp |
| 80 | UINT64_C(4236247104), // CDE_VCX3A_vec |
| 81 | UINT64_C(3984588800), // CDE_VCX3_fpdp |
| 82 | UINT64_C(3967811584), // CDE_VCX3_fpsp |
| 83 | UINT64_C(3967811648), // CDE_VCX3_vec |
| 84 | UINT64_C(234881024), // CDP |
| 85 | UINT64_C(4261412864), // CDP2 |
| 86 | UINT64_C(4118802463), // CLREX |
| 87 | UINT64_C(24055568), // CLZ |
| 88 | UINT64_C(57671680), // CMNri |
| 89 | UINT64_C(24117248), // CMNzrr |
| 90 | UINT64_C(24117248), // CMNzrsi |
| 91 | UINT64_C(24117264), // CMNzrsr |
| 92 | UINT64_C(55574528), // CMPri |
| 93 | UINT64_C(22020096), // CMPrr |
| 94 | UINT64_C(22020096), // CMPrsi |
| 95 | UINT64_C(22020112), // CMPrsr |
| 96 | UINT64_C(4043440128), // CPS1p |
| 97 | UINT64_C(4043309056), // CPS2p |
| 98 | UINT64_C(4043440128), // CPS3p |
| 99 | UINT64_C(3774873664), // CRC32B |
| 100 | UINT64_C(3774874176), // CRC32CB |
| 101 | UINT64_C(3776971328), // CRC32CH |
| 102 | UINT64_C(3779068480), // CRC32CW |
| 103 | UINT64_C(3776970816), // CRC32H |
| 104 | UINT64_C(3779067968), // CRC32W |
| 105 | UINT64_C(52490480), // DBG |
| 106 | UINT64_C(4118802512), // DMB |
| 107 | UINT64_C(4118802496), // DSB |
| 108 | UINT64_C(35651584), // EORri |
| 109 | UINT64_C(2097152), // EORrr |
| 110 | UINT64_C(2097152), // EORrsi |
| 111 | UINT64_C(2097168), // EORrsr |
| 112 | UINT64_C(23068782), // ERET |
| 113 | UINT64_C(246418176), // FCONSTD |
| 114 | UINT64_C(246417664), // FCONSTH |
| 115 | UINT64_C(246417920), // FCONSTS |
| 116 | UINT64_C(221252353), // FLDMXDB_UPD |
| 117 | UINT64_C(210766593), // FLDMXIA |
| 118 | UINT64_C(212863745), // FLDMXIA_UPD |
| 119 | UINT64_C(250739216), // FMSTAT |
| 120 | UINT64_C(220203777), // FSTMXDB_UPD |
| 121 | UINT64_C(209718017), // FSTMXIA |
| 122 | UINT64_C(211815169), // FSTMXIA_UPD |
| 123 | UINT64_C(52490240), // HINT |
| 124 | UINT64_C(3774873712), // HLT |
| 125 | UINT64_C(3779068016), // HVC |
| 126 | UINT64_C(4118802528), // ISB |
| 127 | UINT64_C(26217631), // LDA |
| 128 | UINT64_C(30411935), // LDAB |
| 129 | UINT64_C(26218143), // LDAEX |
| 130 | UINT64_C(30412447), // LDAEXB |
| 131 | UINT64_C(28315295), // LDAEXD |
| 132 | UINT64_C(32509599), // LDAEXH |
| 133 | UINT64_C(32509087), // LDAH |
| 134 | UINT64_C(4249878528), // LDC2L_OFFSET |
| 135 | UINT64_C(4241489920), // LDC2L_OPTION |
| 136 | UINT64_C(4235198464), // LDC2L_POST |
| 137 | UINT64_C(4251975680), // LDC2L_PRE |
| 138 | UINT64_C(4245684224), // LDC2_OFFSET |
| 139 | UINT64_C(4237295616), // LDC2_OPTION |
| 140 | UINT64_C(4231004160), // LDC2_POST |
| 141 | UINT64_C(4247781376), // LDC2_PRE |
| 142 | UINT64_C(223346688), // LDCL_OFFSET |
| 143 | UINT64_C(214958080), // LDCL_OPTION |
| 144 | UINT64_C(208666624), // LDCL_POST |
| 145 | UINT64_C(225443840), // LDCL_PRE |
| 146 | UINT64_C(219152384), // LDC_OFFSET |
| 147 | UINT64_C(210763776), // LDC_OPTION |
| 148 | UINT64_C(204472320), // LDC_POST |
| 149 | UINT64_C(221249536), // LDC_PRE |
| 150 | UINT64_C(135266304), // LDMDA |
| 151 | UINT64_C(137363456), // LDMDA_UPD |
| 152 | UINT64_C(152043520), // LDMDB |
| 153 | UINT64_C(154140672), // LDMDB_UPD |
| 154 | UINT64_C(143654912), // LDMIA |
| 155 | UINT64_C(145752064), // LDMIA_UPD |
| 156 | UINT64_C(160432128), // LDMIB |
| 157 | UINT64_C(162529280), // LDMIB_UPD |
| 158 | UINT64_C(74448896), // LDRBT_POST_IMM |
| 159 | UINT64_C(108003328), // LDRBT_POST_REG |
| 160 | UINT64_C(72351744), // LDRB_POST_IMM |
| 161 | UINT64_C(105906176), // LDRB_POST_REG |
| 162 | UINT64_C(91226112), // LDRB_PRE_IMM |
| 163 | UINT64_C(124780544), // LDRB_PRE_REG |
| 164 | UINT64_C(89128960), // LDRBi12 |
| 165 | UINT64_C(122683392), // LDRBrs |
| 166 | UINT64_C(16777424), // LDRD |
| 167 | UINT64_C(208), // LDRD_POST |
| 168 | UINT64_C(18874576), // LDRD_PRE |
| 169 | UINT64_C(26218399), // LDREX |
| 170 | UINT64_C(30412703), // LDREXB |
| 171 | UINT64_C(28315551), // LDREXD |
| 172 | UINT64_C(32509855), // LDREXH |
| 173 | UINT64_C(17825968), // LDRH |
| 174 | UINT64_C(7340208), // LDRHTi |
| 175 | UINT64_C(3145904), // LDRHTr |
| 176 | UINT64_C(1048752), // LDRH_POST |
| 177 | UINT64_C(19923120), // LDRH_PRE |
| 178 | UINT64_C(17826000), // LDRSB |
| 179 | UINT64_C(7340240), // LDRSBTi |
| 180 | UINT64_C(3145936), // LDRSBTr |
| 181 | UINT64_C(1048784), // LDRSB_POST |
| 182 | UINT64_C(19923152), // LDRSB_PRE |
| 183 | UINT64_C(17826032), // LDRSH |
| 184 | UINT64_C(7340272), // LDRSHTi |
| 185 | UINT64_C(3145968), // LDRSHTr |
| 186 | UINT64_C(1048816), // LDRSH_POST |
| 187 | UINT64_C(19923184), // LDRSH_PRE |
| 188 | UINT64_C(70254592), // LDRT_POST_IMM |
| 189 | UINT64_C(103809024), // LDRT_POST_REG |
| 190 | UINT64_C(68157440), // LDR_POST_IMM |
| 191 | UINT64_C(101711872), // LDR_POST_REG |
| 192 | UINT64_C(87031808), // LDR_PRE_IMM |
| 193 | UINT64_C(120586240), // LDR_PRE_REG |
| 194 | UINT64_C(85917696), // LDRcp |
| 195 | UINT64_C(84934656), // LDRi12 |
| 196 | UINT64_C(118489088), // LDRrs |
| 197 | UINT64_C(234881040), // MCR |
| 198 | UINT64_C(4261412880), // MCR2 |
| 199 | UINT64_C(205520896), // MCRR |
| 200 | UINT64_C(4232052736), // MCRR2 |
| 201 | UINT64_C(2097296), // MLA |
| 202 | UINT64_C(6291600), // MLS |
| 203 | UINT64_C(27324430), // MOVPCLR |
| 204 | UINT64_C(54525952), // MOVTi16 |
| 205 | UINT64_C(60817408), // MOVi |
| 206 | UINT64_C(50331648), // MOVi16 |
| 207 | UINT64_C(27262976), // MOVr |
| 208 | UINT64_C(27262976), // MOVr_TC |
| 209 | UINT64_C(27262976), // MOVsi |
| 210 | UINT64_C(27262992), // MOVsr |
| 211 | UINT64_C(235929616), // MRC |
| 212 | UINT64_C(4262461456), // MRC2 |
| 213 | UINT64_C(206569472), // MRRC |
| 214 | UINT64_C(4233101312), // MRRC2 |
| 215 | UINT64_C(17760256), // MRS |
| 216 | UINT64_C(16777728), // MRSbanked |
| 217 | UINT64_C(21954560), // MRSsys |
| 218 | UINT64_C(18935808), // MSR |
| 219 | UINT64_C(18936320), // MSRbanked |
| 220 | UINT64_C(52490240), // MSRi |
| 221 | UINT64_C(144), // MUL |
| 222 | UINT64_C(3931111727), // MVE_ASRLi |
| 223 | UINT64_C(3931111725), // MVE_ASRLr |
| 224 | UINT64_C(4027637761), // MVE_DLSTP_16 |
| 225 | UINT64_C(4028686337), // MVE_DLSTP_32 |
| 226 | UINT64_C(4029734913), // MVE_DLSTP_64 |
| 227 | UINT64_C(4026589185), // MVE_DLSTP_8 |
| 228 | UINT64_C(4027572225), // MVE_LCTP |
| 229 | UINT64_C(4028612609), // MVE_LETP |
| 230 | UINT64_C(3931111695), // MVE_LSLLi |
| 231 | UINT64_C(3931111693), // MVE_LSLLr |
| 232 | UINT64_C(3931111711), // MVE_LSRL |
| 233 | UINT64_C(3931115309), // MVE_SQRSHR |
| 234 | UINT64_C(3931177261), // MVE_SQRSHRL |
| 235 | UINT64_C(3931115327), // MVE_SQSHL |
| 236 | UINT64_C(3931177279), // MVE_SQSHLL |
| 237 | UINT64_C(3931115311), // MVE_SRSHR |
| 238 | UINT64_C(3931177263), // MVE_SRSHRL |
| 239 | UINT64_C(3931115277), // MVE_UQRSHL |
| 240 | UINT64_C(3931177229), // MVE_UQRSHLL |
| 241 | UINT64_C(3931115279), // MVE_UQSHL |
| 242 | UINT64_C(3931177231), // MVE_UQSHLL |
| 243 | UINT64_C(3931115295), // MVE_URSHR |
| 244 | UINT64_C(3931177247), // MVE_URSHRL |
| 245 | UINT64_C(4002418433), // MVE_VABAVs16 |
| 246 | UINT64_C(4003467009), // MVE_VABAVs32 |
| 247 | UINT64_C(4001369857), // MVE_VABAVs8 |
| 248 | UINT64_C(4270853889), // MVE_VABAVu16 |
| 249 | UINT64_C(4271902465), // MVE_VABAVu32 |
| 250 | UINT64_C(4269805313), // MVE_VABAVu8 |
| 251 | UINT64_C(4281339200), // MVE_VABDf16 |
| 252 | UINT64_C(4280290624), // MVE_VABDf32 |
| 253 | UINT64_C(4010805056), // MVE_VABDs16 |
| 254 | UINT64_C(4011853632), // MVE_VABDs32 |
| 255 | UINT64_C(4009756480), // MVE_VABDs8 |
| 256 | UINT64_C(4279240512), // MVE_VABDu16 |
| 257 | UINT64_C(4280289088), // MVE_VABDu32 |
| 258 | UINT64_C(4278191936), // MVE_VABDu8 |
| 259 | UINT64_C(4290053952), // MVE_VABSf16 |
| 260 | UINT64_C(4290316096), // MVE_VABSf32 |
| 261 | UINT64_C(4290052928), // MVE_VABSs16 |
| 262 | UINT64_C(4290315072), // MVE_VABSs32 |
| 263 | UINT64_C(4289790784), // MVE_VABSs8 |
| 264 | UINT64_C(3996126976), // MVE_VADC |
| 265 | UINT64_C(3996131072), // MVE_VADCI |
| 266 | UINT64_C(4001959712), // MVE_VADDLVs32acc |
| 267 | UINT64_C(4001959680), // MVE_VADDLVs32no_acc |
| 268 | UINT64_C(4270395168), // MVE_VADDLVu32acc |
| 269 | UINT64_C(4270395136), // MVE_VADDLVu32no_acc |
| 270 | UINT64_C(4009037600), // MVE_VADDVs16acc |
| 271 | UINT64_C(4009037568), // MVE_VADDVs16no_acc |
| 272 | UINT64_C(4009299744), // MVE_VADDVs32acc |
| 273 | UINT64_C(4009299712), // MVE_VADDVs32no_acc |
| 274 | UINT64_C(4008775456), // MVE_VADDVs8acc |
| 275 | UINT64_C(4008775424), // MVE_VADDVs8no_acc |
| 276 | UINT64_C(4277473056), // MVE_VADDVu16acc |
| 277 | UINT64_C(4277473024), // MVE_VADDVu16no_acc |
| 278 | UINT64_C(4277735200), // MVE_VADDVu32acc |
| 279 | UINT64_C(4277735168), // MVE_VADDVu32no_acc |
| 280 | UINT64_C(4277210912), // MVE_VADDVu8acc |
| 281 | UINT64_C(4277210880), // MVE_VADDVu8no_acc |
| 282 | UINT64_C(4264562496), // MVE_VADD_qr_f16 |
| 283 | UINT64_C(3996127040), // MVE_VADD_qr_f32 |
| 284 | UINT64_C(3994095424), // MVE_VADD_qr_i16 |
| 285 | UINT64_C(3995144000), // MVE_VADD_qr_i32 |
| 286 | UINT64_C(3993046848), // MVE_VADD_qr_i8 |
| 287 | UINT64_C(4010806592), // MVE_VADDf16 |
| 288 | UINT64_C(4009758016), // MVE_VADDf32 |
| 289 | UINT64_C(4010805312), // MVE_VADDi16 |
| 290 | UINT64_C(4011853888), // MVE_VADDi32 |
| 291 | UINT64_C(4009756736), // MVE_VADDi8 |
| 292 | UINT64_C(4009754960), // MVE_VAND |
| 293 | UINT64_C(4010803536), // MVE_VBIC |
| 294 | UINT64_C(4018145648), // MVE_VBICimmi16 |
| 295 | UINT64_C(4018143600), // MVE_VBICimmi32 |
| 296 | UINT64_C(4262534752), // MVE_VBRSR16 |
| 297 | UINT64_C(4263583328), // MVE_VBRSR32 |
| 298 | UINT64_C(4261486176), // MVE_VBRSR8 |
| 299 | UINT64_C(4236249152), // MVE_VCADDf16 |
| 300 | UINT64_C(4237297728), // MVE_VCADDf32 |
| 301 | UINT64_C(4262465280), // MVE_VCADDi16 |
| 302 | UINT64_C(4263513856), // MVE_VCADDi32 |
| 303 | UINT64_C(4261416704), // MVE_VCADDi8 |
| 304 | UINT64_C(4289987648), // MVE_VCLSs16 |
| 305 | UINT64_C(4290249792), // MVE_VCLSs32 |
| 306 | UINT64_C(4289725504), // MVE_VCLSs8 |
| 307 | UINT64_C(4289987776), // MVE_VCLZs16 |
| 308 | UINT64_C(4290249920), // MVE_VCLZs32 |
| 309 | UINT64_C(4289725632), // MVE_VCLZs8 |
| 310 | UINT64_C(4229957696), // MVE_VCMLAf16 |
| 311 | UINT64_C(4231006272), // MVE_VCMLAf32 |
| 312 | UINT64_C(4264627968), // MVE_VCMPf16 |
| 313 | UINT64_C(4264628032), // MVE_VCMPf16r |
| 314 | UINT64_C(3996192512), // MVE_VCMPf32 |
| 315 | UINT64_C(3996192576), // MVE_VCMPf32r |
| 316 | UINT64_C(4262530816), // MVE_VCMPi16 |
| 317 | UINT64_C(4262530880), // MVE_VCMPi16r |
| 318 | UINT64_C(4263579392), // MVE_VCMPi32 |
| 319 | UINT64_C(4263579456), // MVE_VCMPi32r |
| 320 | UINT64_C(4261482240), // MVE_VCMPi8 |
| 321 | UINT64_C(4261482304), // MVE_VCMPi8r |
| 322 | UINT64_C(4262534912), // MVE_VCMPs16 |
| 323 | UINT64_C(4262534976), // MVE_VCMPs16r |
| 324 | UINT64_C(4263583488), // MVE_VCMPs32 |
| 325 | UINT64_C(4263583552), // MVE_VCMPs32r |
| 326 | UINT64_C(4261486336), // MVE_VCMPs8 |
| 327 | UINT64_C(4261486400), // MVE_VCMPs8r |
| 328 | UINT64_C(4262530817), // MVE_VCMPu16 |
| 329 | UINT64_C(4262530912), // MVE_VCMPu16r |
| 330 | UINT64_C(4263579393), // MVE_VCMPu32 |
| 331 | UINT64_C(4263579488), // MVE_VCMPu32r |
| 332 | UINT64_C(4261482241), // MVE_VCMPu8 |
| 333 | UINT64_C(4261482336), // MVE_VCMPu8r |
| 334 | UINT64_C(3996126720), // MVE_VCMULf16 |
| 335 | UINT64_C(4264562176), // MVE_VCMULf32 |
| 336 | UINT64_C(4027639809), // MVE_VCTP16 |
| 337 | UINT64_C(4028688385), // MVE_VCTP32 |
| 338 | UINT64_C(4029736961), // MVE_VCTP64 |
| 339 | UINT64_C(4026591233), // MVE_VCTP8 |
| 340 | UINT64_C(3997109761), // MVE_VCVTf16f32bh |
| 341 | UINT64_C(3997113857), // MVE_VCVTf16f32th |
| 342 | UINT64_C(4021292112), // MVE_VCVTf16s16_fix |
| 343 | UINT64_C(4290184768), // MVE_VCVTf16s16n |
| 344 | UINT64_C(4289727568), // MVE_VCVTf16u16_fix |
| 345 | UINT64_C(4290184896), // MVE_VCVTf16u16n |
| 346 | UINT64_C(4265545217), // MVE_VCVTf32f16bh |
| 347 | UINT64_C(4265549313), // MVE_VCVTf32f16th |
| 348 | UINT64_C(4020244048), // MVE_VCVTf32s32_fix |
| 349 | UINT64_C(4290446912), // MVE_VCVTf32s32n |
| 350 | UINT64_C(4288679504), // MVE_VCVTf32u32_fix |
| 351 | UINT64_C(4290447040), // MVE_VCVTf32u32n |
| 352 | UINT64_C(4021292368), // MVE_VCVTs16f16_fix |
| 353 | UINT64_C(4290183232), // MVE_VCVTs16f16a |
| 354 | UINT64_C(4290184000), // MVE_VCVTs16f16m |
| 355 | UINT64_C(4290183488), // MVE_VCVTs16f16n |
| 356 | UINT64_C(4290183744), // MVE_VCVTs16f16p |
| 357 | UINT64_C(4290185024), // MVE_VCVTs16f16z |
| 358 | UINT64_C(4020244304), // MVE_VCVTs32f32_fix |
| 359 | UINT64_C(4290445376), // MVE_VCVTs32f32a |
| 360 | UINT64_C(4290446144), // MVE_VCVTs32f32m |
| 361 | UINT64_C(4290445632), // MVE_VCVTs32f32n |
| 362 | UINT64_C(4290445888), // MVE_VCVTs32f32p |
| 363 | UINT64_C(4290447168), // MVE_VCVTs32f32z |
| 364 | UINT64_C(4289727824), // MVE_VCVTu16f16_fix |
| 365 | UINT64_C(4290183360), // MVE_VCVTu16f16a |
| 366 | UINT64_C(4290184128), // MVE_VCVTu16f16m |
| 367 | UINT64_C(4290183616), // MVE_VCVTu16f16n |
| 368 | UINT64_C(4290183872), // MVE_VCVTu16f16p |
| 369 | UINT64_C(4290185152), // MVE_VCVTu16f16z |
| 370 | UINT64_C(4288679760), // MVE_VCVTu32f32_fix |
| 371 | UINT64_C(4290445504), // MVE_VCVTu32f32a |
| 372 | UINT64_C(4290446272), // MVE_VCVTu32f32m |
| 373 | UINT64_C(4290445760), // MVE_VCVTu32f32n |
| 374 | UINT64_C(4290446016), // MVE_VCVTu32f32p |
| 375 | UINT64_C(4290447296), // MVE_VCVTu32f32z |
| 376 | UINT64_C(3994099566), // MVE_VDDUPu16 |
| 377 | UINT64_C(3995148142), // MVE_VDDUPu32 |
| 378 | UINT64_C(3993050990), // MVE_VDDUPu8 |
| 379 | UINT64_C(4003466032), // MVE_VDUP16 |
| 380 | UINT64_C(4003466000), // MVE_VDUP32 |
| 381 | UINT64_C(4007660304), // MVE_VDUP8 |
| 382 | UINT64_C(3994099552), // MVE_VDWDUPu16 |
| 383 | UINT64_C(3995148128), // MVE_VDWDUPu32 |
| 384 | UINT64_C(3993050976), // MVE_VDWDUPu8 |
| 385 | UINT64_C(4278190416), // MVE_VEOR |
| 386 | UINT64_C(4264631872), // MVE_VFMA_qr_Sf16 |
| 387 | UINT64_C(3996196416), // MVE_VFMA_qr_Sf32 |
| 388 | UINT64_C(4264627776), // MVE_VFMA_qr_f16 |
| 389 | UINT64_C(3996192320), // MVE_VFMA_qr_f32 |
| 390 | UINT64_C(4010806352), // MVE_VFMAf16 |
| 391 | UINT64_C(4009757776), // MVE_VFMAf32 |
| 392 | UINT64_C(4012903504), // MVE_VFMSf16 |
| 393 | UINT64_C(4011854928), // MVE_VFMSf32 |
| 394 | UINT64_C(3994029888), // MVE_VHADD_qr_s16 |
| 395 | UINT64_C(3995078464), // MVE_VHADD_qr_s32 |
| 396 | UINT64_C(3992981312), // MVE_VHADD_qr_s8 |
| 397 | UINT64_C(4262465344), // MVE_VHADD_qr_u16 |
| 398 | UINT64_C(4263513920), // MVE_VHADD_qr_u32 |
| 399 | UINT64_C(4261416768), // MVE_VHADD_qr_u8 |
| 400 | UINT64_C(4010803264), // MVE_VHADDs16 |
| 401 | UINT64_C(4011851840), // MVE_VHADDs32 |
| 402 | UINT64_C(4009754688), // MVE_VHADDs8 |
| 403 | UINT64_C(4279238720), // MVE_VHADDu16 |
| 404 | UINT64_C(4280287296), // MVE_VHADDu32 |
| 405 | UINT64_C(4278190144), // MVE_VHADDu8 |
| 406 | UINT64_C(3994029824), // MVE_VHCADDs16 |
| 407 | UINT64_C(3995078400), // MVE_VHCADDs32 |
| 408 | UINT64_C(3992981248), // MVE_VHCADDs8 |
| 409 | UINT64_C(3994033984), // MVE_VHSUB_qr_s16 |
| 410 | UINT64_C(3995082560), // MVE_VHSUB_qr_s32 |
| 411 | UINT64_C(3992985408), // MVE_VHSUB_qr_s8 |
| 412 | UINT64_C(4262469440), // MVE_VHSUB_qr_u16 |
| 413 | UINT64_C(4263518016), // MVE_VHSUB_qr_u32 |
| 414 | UINT64_C(4261420864), // MVE_VHSUB_qr_u8 |
| 415 | UINT64_C(4010803776), // MVE_VHSUBs16 |
| 416 | UINT64_C(4011852352), // MVE_VHSUBs32 |
| 417 | UINT64_C(4009755200), // MVE_VHSUBs8 |
| 418 | UINT64_C(4279239232), // MVE_VHSUBu16 |
| 419 | UINT64_C(4280287808), // MVE_VHSUBu32 |
| 420 | UINT64_C(4278190656), // MVE_VHSUBu8 |
| 421 | UINT64_C(3994095470), // MVE_VIDUPu16 |
| 422 | UINT64_C(3995144046), // MVE_VIDUPu32 |
| 423 | UINT64_C(3993046894), // MVE_VIDUPu8 |
| 424 | UINT64_C(3994095456), // MVE_VIWDUPu16 |
| 425 | UINT64_C(3995144032), // MVE_VIWDUPu32 |
| 426 | UINT64_C(3993046880), // MVE_VIWDUPu8 |
| 427 | UINT64_C(4237303424), // MVE_VLD20_16 |
| 428 | UINT64_C(4239400576), // MVE_VLD20_16_wb |
| 429 | UINT64_C(4237303552), // MVE_VLD20_32 |
| 430 | UINT64_C(4239400704), // MVE_VLD20_32_wb |
| 431 | UINT64_C(4237303296), // MVE_VLD20_8 |
| 432 | UINT64_C(4239400448), // MVE_VLD20_8_wb |
| 433 | UINT64_C(4237303456), // MVE_VLD21_16 |
| 434 | UINT64_C(4239400608), // MVE_VLD21_16_wb |
| 435 | UINT64_C(4237303584), // MVE_VLD21_32 |
| 436 | UINT64_C(4239400736), // MVE_VLD21_32_wb |
| 437 | UINT64_C(4237303328), // MVE_VLD21_8 |
| 438 | UINT64_C(4239400480), // MVE_VLD21_8_wb |
| 439 | UINT64_C(4237303425), // MVE_VLD40_16 |
| 440 | UINT64_C(4239400577), // MVE_VLD40_16_wb |
| 441 | UINT64_C(4237303553), // MVE_VLD40_32 |
| 442 | UINT64_C(4239400705), // MVE_VLD40_32_wb |
| 443 | UINT64_C(4237303297), // MVE_VLD40_8 |
| 444 | UINT64_C(4239400449), // MVE_VLD40_8_wb |
| 445 | UINT64_C(4237303457), // MVE_VLD41_16 |
| 446 | UINT64_C(4239400609), // MVE_VLD41_16_wb |
| 447 | UINT64_C(4237303585), // MVE_VLD41_32 |
| 448 | UINT64_C(4239400737), // MVE_VLD41_32_wb |
| 449 | UINT64_C(4237303329), // MVE_VLD41_8 |
| 450 | UINT64_C(4239400481), // MVE_VLD41_8_wb |
| 451 | UINT64_C(4237303489), // MVE_VLD42_16 |
| 452 | UINT64_C(4239400641), // MVE_VLD42_16_wb |
| 453 | UINT64_C(4237303617), // MVE_VLD42_32 |
| 454 | UINT64_C(4239400769), // MVE_VLD42_32_wb |
| 455 | UINT64_C(4237303361), // MVE_VLD42_8 |
| 456 | UINT64_C(4239400513), // MVE_VLD42_8_wb |
| 457 | UINT64_C(4237303521), // MVE_VLD43_16 |
| 458 | UINT64_C(4239400673), // MVE_VLD43_16_wb |
| 459 | UINT64_C(4237303649), // MVE_VLD43_32 |
| 460 | UINT64_C(4239400801), // MVE_VLD43_32_wb |
| 461 | UINT64_C(4237303393), // MVE_VLD43_8 |
| 462 | UINT64_C(4239400545), // MVE_VLD43_8_wb |
| 463 | UINT64_C(3977252480), // MVE_VLDRBS16 |
| 464 | UINT64_C(3962572416), // MVE_VLDRBS16_post |
| 465 | UINT64_C(3979349632), // MVE_VLDRBS16_pre |
| 466 | UINT64_C(3968863872), // MVE_VLDRBS16_rq |
| 467 | UINT64_C(3977252608), // MVE_VLDRBS32 |
| 468 | UINT64_C(3962572544), // MVE_VLDRBS32_post |
| 469 | UINT64_C(3979349760), // MVE_VLDRBS32_pre |
| 470 | UINT64_C(3968864000), // MVE_VLDRBS32_rq |
| 471 | UINT64_C(4245687936), // MVE_VLDRBU16 |
| 472 | UINT64_C(4231007872), // MVE_VLDRBU16_post |
| 473 | UINT64_C(4247785088), // MVE_VLDRBU16_pre |
| 474 | UINT64_C(4237299328), // MVE_VLDRBU16_rq |
| 475 | UINT64_C(4245688064), // MVE_VLDRBU32 |
| 476 | UINT64_C(4231008000), // MVE_VLDRBU32_post |
| 477 | UINT64_C(4247785216), // MVE_VLDRBU32_pre |
| 478 | UINT64_C(4237299456), // MVE_VLDRBU32_rq |
| 479 | UINT64_C(3977256448), // MVE_VLDRBU8 |
| 480 | UINT64_C(3962576384), // MVE_VLDRBU8_post |
| 481 | UINT64_C(3979353600), // MVE_VLDRBU8_pre |
| 482 | UINT64_C(4237299200), // MVE_VLDRBU8_rq |
| 483 | UINT64_C(4245692160), // MVE_VLDRDU64_qi |
| 484 | UINT64_C(4247789312), // MVE_VLDRDU64_qi_pre |
| 485 | UINT64_C(4237299665), // MVE_VLDRDU64_rq |
| 486 | UINT64_C(4237299664), // MVE_VLDRDU64_rq_u |
| 487 | UINT64_C(3977776896), // MVE_VLDRHS32 |
| 488 | UINT64_C(3963096832), // MVE_VLDRHS32_post |
| 489 | UINT64_C(3979874048), // MVE_VLDRHS32_pre |
| 490 | UINT64_C(3968864017), // MVE_VLDRHS32_rq |
| 491 | UINT64_C(3968864016), // MVE_VLDRHS32_rq_u |
| 492 | UINT64_C(3977256576), // MVE_VLDRHU16 |
| 493 | UINT64_C(3962576512), // MVE_VLDRHU16_post |
| 494 | UINT64_C(3979353728), // MVE_VLDRHU16_pre |
| 495 | UINT64_C(4237299345), // MVE_VLDRHU16_rq |
| 496 | UINT64_C(4237299344), // MVE_VLDRHU16_rq_u |
| 497 | UINT64_C(4246212352), // MVE_VLDRHU32 |
| 498 | UINT64_C(4231532288), // MVE_VLDRHU32_post |
| 499 | UINT64_C(4248309504), // MVE_VLDRHU32_pre |
| 500 | UINT64_C(4237299473), // MVE_VLDRHU32_rq |
| 501 | UINT64_C(4237299472), // MVE_VLDRHU32_rq_u |
| 502 | UINT64_C(3977256704), // MVE_VLDRWU32 |
| 503 | UINT64_C(3962576640), // MVE_VLDRWU32_post |
| 504 | UINT64_C(3979353856), // MVE_VLDRWU32_pre |
| 505 | UINT64_C(4245691904), // MVE_VLDRWU32_qi |
| 506 | UINT64_C(4247789056), // MVE_VLDRWU32_qi_pre |
| 507 | UINT64_C(4237299521), // MVE_VLDRWU32_rq |
| 508 | UINT64_C(4237299520), // MVE_VLDRWU32_rq_u |
| 509 | UINT64_C(4007923456), // MVE_VMAXAVs16 |
| 510 | UINT64_C(4008185600), // MVE_VMAXAVs32 |
| 511 | UINT64_C(4007661312), // MVE_VMAXAVs8 |
| 512 | UINT64_C(3996585601), // MVE_VMAXAs16 |
| 513 | UINT64_C(3996847745), // MVE_VMAXAs32 |
| 514 | UINT64_C(3996323457), // MVE_VMAXAs8 |
| 515 | UINT64_C(4276883200), // MVE_VMAXNMAVf16 |
| 516 | UINT64_C(4008447744), // MVE_VMAXNMAVf32 |
| 517 | UINT64_C(4265545345), // MVE_VMAXNMAf16 |
| 518 | UINT64_C(3997109889), // MVE_VMAXNMAf32 |
| 519 | UINT64_C(4277014272), // MVE_VMAXNMVf16 |
| 520 | UINT64_C(4008578816), // MVE_VMAXNMVf32 |
| 521 | UINT64_C(4279242576), // MVE_VMAXNMf16 |
| 522 | UINT64_C(4278194000), // MVE_VMAXNMf32 |
| 523 | UINT64_C(4008054528), // MVE_VMAXVs16 |
| 524 | UINT64_C(4008316672), // MVE_VMAXVs32 |
| 525 | UINT64_C(4007792384), // MVE_VMAXVs8 |
| 526 | UINT64_C(4276489984), // MVE_VMAXVu16 |
| 527 | UINT64_C(4276752128), // MVE_VMAXVu32 |
| 528 | UINT64_C(4276227840), // MVE_VMAXVu8 |
| 529 | UINT64_C(4010804800), // MVE_VMAXs16 |
| 530 | UINT64_C(4011853376), // MVE_VMAXs32 |
| 531 | UINT64_C(4009756224), // MVE_VMAXs8 |
| 532 | UINT64_C(4279240256), // MVE_VMAXu16 |
| 533 | UINT64_C(4280288832), // MVE_VMAXu32 |
| 534 | UINT64_C(4278191680), // MVE_VMAXu8 |
| 535 | UINT64_C(4007923584), // MVE_VMINAVs16 |
| 536 | UINT64_C(4008185728), // MVE_VMINAVs32 |
| 537 | UINT64_C(4007661440), // MVE_VMINAVs8 |
| 538 | UINT64_C(3996589697), // MVE_VMINAs16 |
| 539 | UINT64_C(3996851841), // MVE_VMINAs32 |
| 540 | UINT64_C(3996327553), // MVE_VMINAs8 |
| 541 | UINT64_C(4276883328), // MVE_VMINNMAVf16 |
| 542 | UINT64_C(4008447872), // MVE_VMINNMAVf32 |
| 543 | UINT64_C(4265549441), // MVE_VMINNMAf16 |
| 544 | UINT64_C(3997113985), // MVE_VMINNMAf32 |
| 545 | UINT64_C(4277014400), // MVE_VMINNMVf16 |
| 546 | UINT64_C(4008578944), // MVE_VMINNMVf32 |
| 547 | UINT64_C(4281339728), // MVE_VMINNMf16 |
| 548 | UINT64_C(4280291152), // MVE_VMINNMf32 |
| 549 | UINT64_C(4008054656), // MVE_VMINVs16 |
| 550 | UINT64_C(4008316800), // MVE_VMINVs32 |
| 551 | UINT64_C(4007792512), // MVE_VMINVs8 |
| 552 | UINT64_C(4276490112), // MVE_VMINVu16 |
| 553 | UINT64_C(4276752256), // MVE_VMINVu32 |
| 554 | UINT64_C(4276227968), // MVE_VMINVu8 |
| 555 | UINT64_C(4010804816), // MVE_VMINs16 |
| 556 | UINT64_C(4011853392), // MVE_VMINs32 |
| 557 | UINT64_C(4009756240), // MVE_VMINs8 |
| 558 | UINT64_C(4279240272), // MVE_VMINu16 |
| 559 | UINT64_C(4280288848), // MVE_VMINu32 |
| 560 | UINT64_C(4278191696), // MVE_VMINu8 |
| 561 | UINT64_C(4008709664), // MVE_VMLADAVas16 |
| 562 | UINT64_C(4008775200), // MVE_VMLADAVas32 |
| 563 | UINT64_C(4008709920), // MVE_VMLADAVas8 |
| 564 | UINT64_C(4277145120), // MVE_VMLADAVau16 |
| 565 | UINT64_C(4277210656), // MVE_VMLADAVau32 |
| 566 | UINT64_C(4277145376), // MVE_VMLADAVau8 |
| 567 | UINT64_C(4008713760), // MVE_VMLADAVaxs16 |
| 568 | UINT64_C(4008779296), // MVE_VMLADAVaxs32 |
| 569 | UINT64_C(4008714016), // MVE_VMLADAVaxs8 |
| 570 | UINT64_C(4008709632), // MVE_VMLADAVs16 |
| 571 | UINT64_C(4008775168), // MVE_VMLADAVs32 |
| 572 | UINT64_C(4008709888), // MVE_VMLADAVs8 |
| 573 | UINT64_C(4277145088), // MVE_VMLADAVu16 |
| 574 | UINT64_C(4277210624), // MVE_VMLADAVu32 |
| 575 | UINT64_C(4277145344), // MVE_VMLADAVu8 |
| 576 | UINT64_C(4008713728), // MVE_VMLADAVxs16 |
| 577 | UINT64_C(4008779264), // MVE_VMLADAVxs32 |
| 578 | UINT64_C(4008713984), // MVE_VMLADAVxs8 |
| 579 | UINT64_C(4001369632), // MVE_VMLALDAVas16 |
| 580 | UINT64_C(4001435168), // MVE_VMLALDAVas32 |
| 581 | UINT64_C(4269805088), // MVE_VMLALDAVau16 |
| 582 | UINT64_C(4269870624), // MVE_VMLALDAVau32 |
| 583 | UINT64_C(4001373728), // MVE_VMLALDAVaxs16 |
| 584 | UINT64_C(4001439264), // MVE_VMLALDAVaxs32 |
| 585 | UINT64_C(4001369600), // MVE_VMLALDAVs16 |
| 586 | UINT64_C(4001435136), // MVE_VMLALDAVs32 |
| 587 | UINT64_C(4269805056), // MVE_VMLALDAVu16 |
| 588 | UINT64_C(4269870592), // MVE_VMLALDAVu32 |
| 589 | UINT64_C(4001373696), // MVE_VMLALDAVxs16 |
| 590 | UINT64_C(4001439232), // MVE_VMLALDAVxs32 |
| 591 | UINT64_C(3994099264), // MVE_VMLAS_qr_i16 |
| 592 | UINT64_C(3995147840), // MVE_VMLAS_qr_i32 |
| 593 | UINT64_C(3993050688), // MVE_VMLAS_qr_i8 |
| 594 | UINT64_C(3994095168), // MVE_VMLA_qr_i16 |
| 595 | UINT64_C(3995143744), // MVE_VMLA_qr_i32 |
| 596 | UINT64_C(3993046592), // MVE_VMLA_qr_i8 |
| 597 | UINT64_C(4008709665), // MVE_VMLSDAVas16 |
| 598 | UINT64_C(4008775201), // MVE_VMLSDAVas32 |
| 599 | UINT64_C(4277145121), // MVE_VMLSDAVas8 |
| 600 | UINT64_C(4008713761), // MVE_VMLSDAVaxs16 |
| 601 | UINT64_C(4008779297), // MVE_VMLSDAVaxs32 |
| 602 | UINT64_C(4277149217), // MVE_VMLSDAVaxs8 |
| 603 | UINT64_C(4008709633), // MVE_VMLSDAVs16 |
| 604 | UINT64_C(4008775169), // MVE_VMLSDAVs32 |
| 605 | UINT64_C(4277145089), // MVE_VMLSDAVs8 |
| 606 | UINT64_C(4008713729), // MVE_VMLSDAVxs16 |
| 607 | UINT64_C(4008779265), // MVE_VMLSDAVxs32 |
| 608 | UINT64_C(4277149185), // MVE_VMLSDAVxs8 |
| 609 | UINT64_C(4001369633), // MVE_VMLSLDAVas16 |
| 610 | UINT64_C(4001435169), // MVE_VMLSLDAVas32 |
| 611 | UINT64_C(4001373729), // MVE_VMLSLDAVaxs16 |
| 612 | UINT64_C(4001439265), // MVE_VMLSLDAVaxs32 |
| 613 | UINT64_C(4001369601), // MVE_VMLSLDAVs16 |
| 614 | UINT64_C(4001435137), // MVE_VMLSLDAVs32 |
| 615 | UINT64_C(4001373697), // MVE_VMLSLDAVxs16 |
| 616 | UINT64_C(4001439233), // MVE_VMLSLDAVxs32 |
| 617 | UINT64_C(4004515648), // MVE_VMOVLs16bh |
| 618 | UINT64_C(4004519744), // MVE_VMOVLs16th |
| 619 | UINT64_C(4003991360), // MVE_VMOVLs8bh |
| 620 | UINT64_C(4003995456), // MVE_VMOVLs8th |
| 621 | UINT64_C(4272951104), // MVE_VMOVLu16bh |
| 622 | UINT64_C(4272955200), // MVE_VMOVLu16th |
| 623 | UINT64_C(4272426816), // MVE_VMOVLu8bh |
| 624 | UINT64_C(4272430912), // MVE_VMOVLu8th |
| 625 | UINT64_C(4264627841), // MVE_VMOVNi16bh |
| 626 | UINT64_C(4264631937), // MVE_VMOVNi16th |
| 627 | UINT64_C(4264889985), // MVE_VMOVNi32bh |
| 628 | UINT64_C(4264894081), // MVE_VMOVNi32th |
| 629 | UINT64_C(3994028816), // MVE_VMOV_from_lane_32 |
| 630 | UINT64_C(3994028848), // MVE_VMOV_from_lane_s16 |
| 631 | UINT64_C(3998223120), // MVE_VMOV_from_lane_s8 |
| 632 | UINT64_C(4002417456), // MVE_VMOV_from_lane_u16 |
| 633 | UINT64_C(4006611728), // MVE_VMOV_from_lane_u8 |
| 634 | UINT64_C(3960475392), // MVE_VMOV_q_rr |
| 635 | UINT64_C(3959426816), // MVE_VMOV_rr_q |
| 636 | UINT64_C(3992980272), // MVE_VMOV_to_lane_16 |
| 637 | UINT64_C(3992980240), // MVE_VMOV_to_lane_32 |
| 638 | UINT64_C(3997174544), // MVE_VMOV_to_lane_8 |
| 639 | UINT64_C(4018147152), // MVE_VMOVimmf32 |
| 640 | UINT64_C(4018145360), // MVE_VMOVimmi16 |
| 641 | UINT64_C(4018143312), // MVE_VMOVimmi32 |
| 642 | UINT64_C(4018146928), // MVE_VMOVimmi64 |
| 643 | UINT64_C(4018146896), // MVE_VMOVimmi8 |
| 644 | UINT64_C(3994095105), // MVE_VMULHs16 |
| 645 | UINT64_C(3995143681), // MVE_VMULHs32 |
| 646 | UINT64_C(3993046529), // MVE_VMULHs8 |
| 647 | UINT64_C(4262530561), // MVE_VMULHu16 |
| 648 | UINT64_C(4263579137), // MVE_VMULHu32 |
| 649 | UINT64_C(4261481985), // MVE_VMULHu8 |
| 650 | UINT64_C(4264627712), // MVE_VMULLBp16 |
| 651 | UINT64_C(3996192256), // MVE_VMULLBp8 |
| 652 | UINT64_C(3994095104), // MVE_VMULLBs16 |
| 653 | UINT64_C(3995143680), // MVE_VMULLBs32 |
| 654 | UINT64_C(3993046528), // MVE_VMULLBs8 |
| 655 | UINT64_C(4262530560), // MVE_VMULLBu16 |
| 656 | UINT64_C(4263579136), // MVE_VMULLBu32 |
| 657 | UINT64_C(4261481984), // MVE_VMULLBu8 |
| 658 | UINT64_C(4264631808), // MVE_VMULLTp16 |
| 659 | UINT64_C(3996196352), // MVE_VMULLTp8 |
| 660 | UINT64_C(3994099200), // MVE_VMULLTs16 |
| 661 | UINT64_C(3995147776), // MVE_VMULLTs32 |
| 662 | UINT64_C(3993050624), // MVE_VMULLTs8 |
| 663 | UINT64_C(4262534656), // MVE_VMULLTu16 |
| 664 | UINT64_C(4263583232), // MVE_VMULLTu32 |
| 665 | UINT64_C(4261486080), // MVE_VMULLTu8 |
| 666 | UINT64_C(4264627808), // MVE_VMUL_qr_f16 |
| 667 | UINT64_C(3996192352), // MVE_VMUL_qr_f32 |
| 668 | UINT64_C(3994099296), // MVE_VMUL_qr_i16 |
| 669 | UINT64_C(3995147872), // MVE_VMUL_qr_i32 |
| 670 | UINT64_C(3993050720), // MVE_VMUL_qr_i8 |
| 671 | UINT64_C(4279242064), // MVE_VMULf16 |
| 672 | UINT64_C(4278193488), // MVE_VMULf32 |
| 673 | UINT64_C(4010805584), // MVE_VMULi16 |
| 674 | UINT64_C(4011854160), // MVE_VMULi32 |
| 675 | UINT64_C(4009757008), // MVE_VMULi8 |
| 676 | UINT64_C(4289725888), // MVE_VMVN |
| 677 | UINT64_C(4018145392), // MVE_VMVNimmi16 |
| 678 | UINT64_C(4018143344), // MVE_VMVNimmi32 |
| 679 | UINT64_C(4290054080), // MVE_VNEGf16 |
| 680 | UINT64_C(4290316224), // MVE_VNEGf32 |
| 681 | UINT64_C(4290053056), // MVE_VNEGs16 |
| 682 | UINT64_C(4290315200), // MVE_VNEGs32 |
| 683 | UINT64_C(4289790912), // MVE_VNEGs8 |
| 684 | UINT64_C(4012900688), // MVE_VORN |
| 685 | UINT64_C(4011852112), // MVE_VORR |
| 686 | UINT64_C(4018145616), // MVE_VORRimmi16 |
| 687 | UINT64_C(4018143568), // MVE_VORRimmi32 |
| 688 | UINT64_C(4264628045), // MVE_VPNOT |
| 689 | UINT64_C(4264627969), // MVE_VPSEL |
| 690 | UINT64_C(4264628045), // MVE_VPST |
| 691 | UINT64_C(4261482240), // MVE_VPTv16i8 |
| 692 | UINT64_C(4261482304), // MVE_VPTv16i8r |
| 693 | UINT64_C(4261486336), // MVE_VPTv16s8 |
| 694 | UINT64_C(4261486400), // MVE_VPTv16s8r |
| 695 | UINT64_C(4261482241), // MVE_VPTv16u8 |
| 696 | UINT64_C(4261482336), // MVE_VPTv16u8r |
| 697 | UINT64_C(3996192512), // MVE_VPTv4f32 |
| 698 | UINT64_C(3996192576), // MVE_VPTv4f32r |
| 699 | UINT64_C(4263579392), // MVE_VPTv4i32 |
| 700 | UINT64_C(4263579456), // MVE_VPTv4i32r |
| 701 | UINT64_C(4263583488), // MVE_VPTv4s32 |
| 702 | UINT64_C(4263583552), // MVE_VPTv4s32r |
| 703 | UINT64_C(4263579393), // MVE_VPTv4u32 |
| 704 | UINT64_C(4263579488), // MVE_VPTv4u32r |
| 705 | UINT64_C(4264627968), // MVE_VPTv8f16 |
| 706 | UINT64_C(4264628032), // MVE_VPTv8f16r |
| 707 | UINT64_C(4262530816), // MVE_VPTv8i16 |
| 708 | UINT64_C(4262530880), // MVE_VPTv8i16r |
| 709 | UINT64_C(4262534912), // MVE_VPTv8s16 |
| 710 | UINT64_C(4262534976), // MVE_VPTv8s16r |
| 711 | UINT64_C(4262530817), // MVE_VPTv8u16 |
| 712 | UINT64_C(4262530912), // MVE_VPTv8u16r |
| 713 | UINT64_C(4289988416), // MVE_VQABSs16 |
| 714 | UINT64_C(4290250560), // MVE_VQABSs32 |
| 715 | UINT64_C(4289726272), // MVE_VQABSs8 |
| 716 | UINT64_C(3994029920), // MVE_VQADD_qr_s16 |
| 717 | UINT64_C(3995078496), // MVE_VQADD_qr_s32 |
| 718 | UINT64_C(3992981344), // MVE_VQADD_qr_s8 |
| 719 | UINT64_C(4262465376), // MVE_VQADD_qr_u16 |
| 720 | UINT64_C(4263513952), // MVE_VQADD_qr_u32 |
| 721 | UINT64_C(4261416800), // MVE_VQADD_qr_u8 |
| 722 | UINT64_C(4010803280), // MVE_VQADDs16 |
| 723 | UINT64_C(4011851856), // MVE_VQADDs32 |
| 724 | UINT64_C(4009754704), // MVE_VQADDs8 |
| 725 | UINT64_C(4279238736), // MVE_VQADDu16 |
| 726 | UINT64_C(4280287312), // MVE_VQADDu32 |
| 727 | UINT64_C(4278190160), // MVE_VQADDu8 |
| 728 | UINT64_C(3994033664), // MVE_VQDMLADHXs16 |
| 729 | UINT64_C(3995082240), // MVE_VQDMLADHXs32 |
| 730 | UINT64_C(3992985088), // MVE_VQDMLADHXs8 |
| 731 | UINT64_C(3994029568), // MVE_VQDMLADHs16 |
| 732 | UINT64_C(3995078144), // MVE_VQDMLADHs32 |
| 733 | UINT64_C(3992980992), // MVE_VQDMLADHs8 |
| 734 | UINT64_C(3994029664), // MVE_VQDMLAH_qrs16 |
| 735 | UINT64_C(3995078240), // MVE_VQDMLAH_qrs32 |
| 736 | UINT64_C(3992981088), // MVE_VQDMLAH_qrs8 |
| 737 | UINT64_C(3994033760), // MVE_VQDMLASH_qrs16 |
| 738 | UINT64_C(3995082336), // MVE_VQDMLASH_qrs32 |
| 739 | UINT64_C(3992985184), // MVE_VQDMLASH_qrs8 |
| 740 | UINT64_C(4262469120), // MVE_VQDMLSDHXs16 |
| 741 | UINT64_C(4263517696), // MVE_VQDMLSDHXs32 |
| 742 | UINT64_C(4261420544), // MVE_VQDMLSDHXs8 |
| 743 | UINT64_C(4262465024), // MVE_VQDMLSDHs16 |
| 744 | UINT64_C(4263513600), // MVE_VQDMLSDHs32 |
| 745 | UINT64_C(4261416448), // MVE_VQDMLSDHs8 |
| 746 | UINT64_C(3994095200), // MVE_VQDMULH_qr_s16 |
| 747 | UINT64_C(3995143776), // MVE_VQDMULH_qr_s32 |
| 748 | UINT64_C(3993046624), // MVE_VQDMULH_qr_s8 |
| 749 | UINT64_C(4010806080), // MVE_VQDMULHi16 |
| 750 | UINT64_C(4011854656), // MVE_VQDMULHi32 |
| 751 | UINT64_C(4009757504), // MVE_VQDMULHi8 |
| 752 | UINT64_C(3996127072), // MVE_VQDMULL_qr_s16bh |
| 753 | UINT64_C(3996131168), // MVE_VQDMULL_qr_s16th |
| 754 | UINT64_C(4264562528), // MVE_VQDMULL_qr_s32bh |
| 755 | UINT64_C(4264566624), // MVE_VQDMULL_qr_s32th |
| 756 | UINT64_C(3996126977), // MVE_VQDMULLs16bh |
| 757 | UINT64_C(3996131073), // MVE_VQDMULLs16th |
| 758 | UINT64_C(4264562433), // MVE_VQDMULLs32bh |
| 759 | UINT64_C(4264566529), // MVE_VQDMULLs32th |
| 760 | UINT64_C(3996323329), // MVE_VQMOVNs16bh |
| 761 | UINT64_C(3996327425), // MVE_VQMOVNs16th |
| 762 | UINT64_C(3996585473), // MVE_VQMOVNs32bh |
| 763 | UINT64_C(3996589569), // MVE_VQMOVNs32th |
| 764 | UINT64_C(4264758785), // MVE_VQMOVNu16bh |
| 765 | UINT64_C(4264762881), // MVE_VQMOVNu16th |
| 766 | UINT64_C(4265020929), // MVE_VQMOVNu32bh |
| 767 | UINT64_C(4265025025), // MVE_VQMOVNu32th |
| 768 | UINT64_C(3996192385), // MVE_VQMOVUNs16bh |
| 769 | UINT64_C(3996196481), // MVE_VQMOVUNs16th |
| 770 | UINT64_C(3996454529), // MVE_VQMOVUNs32bh |
| 771 | UINT64_C(3996458625), // MVE_VQMOVUNs32th |
| 772 | UINT64_C(4289988544), // MVE_VQNEGs16 |
| 773 | UINT64_C(4290250688), // MVE_VQNEGs32 |
| 774 | UINT64_C(4289726400), // MVE_VQNEGs8 |
| 775 | UINT64_C(3994033665), // MVE_VQRDMLADHXs16 |
| 776 | UINT64_C(3995082241), // MVE_VQRDMLADHXs32 |
| 777 | UINT64_C(3992985089), // MVE_VQRDMLADHXs8 |
| 778 | UINT64_C(3994029569), // MVE_VQRDMLADHs16 |
| 779 | UINT64_C(3995078145), // MVE_VQRDMLADHs32 |
| 780 | UINT64_C(3992980993), // MVE_VQRDMLADHs8 |
| 781 | UINT64_C(3994029632), // MVE_VQRDMLAH_qrs16 |
| 782 | UINT64_C(3995078208), // MVE_VQRDMLAH_qrs32 |
| 783 | UINT64_C(3992981056), // MVE_VQRDMLAH_qrs8 |
| 784 | UINT64_C(3994033728), // MVE_VQRDMLASH_qrs16 |
| 785 | UINT64_C(3995082304), // MVE_VQRDMLASH_qrs32 |
| 786 | UINT64_C(3992985152), // MVE_VQRDMLASH_qrs8 |
| 787 | UINT64_C(4262469121), // MVE_VQRDMLSDHXs16 |
| 788 | UINT64_C(4263517697), // MVE_VQRDMLSDHXs32 |
| 789 | UINT64_C(4261420545), // MVE_VQRDMLSDHXs8 |
| 790 | UINT64_C(4262465025), // MVE_VQRDMLSDHs16 |
| 791 | UINT64_C(4263513601), // MVE_VQRDMLSDHs32 |
| 792 | UINT64_C(4261416449), // MVE_VQRDMLSDHs8 |
| 793 | UINT64_C(4262530656), // MVE_VQRDMULH_qr_s16 |
| 794 | UINT64_C(4263579232), // MVE_VQRDMULH_qr_s32 |
| 795 | UINT64_C(4261482080), // MVE_VQRDMULH_qr_s8 |
| 796 | UINT64_C(4279241536), // MVE_VQRDMULHi16 |
| 797 | UINT64_C(4280290112), // MVE_VQRDMULHi32 |
| 798 | UINT64_C(4278192960), // MVE_VQRDMULHi8 |
| 799 | UINT64_C(4010804560), // MVE_VQRSHL_by_vecs16 |
| 800 | UINT64_C(4011853136), // MVE_VQRSHL_by_vecs32 |
| 801 | UINT64_C(4009755984), // MVE_VQRSHL_by_vecs8 |
| 802 | UINT64_C(4279240016), // MVE_VQRSHL_by_vecu16 |
| 803 | UINT64_C(4280288592), // MVE_VQRSHL_by_vecu32 |
| 804 | UINT64_C(4278191440), // MVE_VQRSHL_by_vecu8 |
| 805 | UINT64_C(3996589792), // MVE_VQRSHL_qrs16 |
| 806 | UINT64_C(3996851936), // MVE_VQRSHL_qrs32 |
| 807 | UINT64_C(3996327648), // MVE_VQRSHL_qrs8 |
| 808 | UINT64_C(4265025248), // MVE_VQRSHL_qru16 |
| 809 | UINT64_C(4265287392), // MVE_VQRSHL_qru32 |
| 810 | UINT64_C(4264763104), // MVE_VQRSHL_qru8 |
| 811 | UINT64_C(4001894209), // MVE_VQRSHRNbhs16 |
| 812 | UINT64_C(4002418497), // MVE_VQRSHRNbhs32 |
| 813 | UINT64_C(4270329665), // MVE_VQRSHRNbhu16 |
| 814 | UINT64_C(4270853953), // MVE_VQRSHRNbhu32 |
| 815 | UINT64_C(4001898305), // MVE_VQRSHRNths16 |
| 816 | UINT64_C(4002422593), // MVE_VQRSHRNths32 |
| 817 | UINT64_C(4270333761), // MVE_VQRSHRNthu16 |
| 818 | UINT64_C(4270858049), // MVE_VQRSHRNthu32 |
| 819 | UINT64_C(4270329792), // MVE_VQRSHRUNs16bh |
| 820 | UINT64_C(4270333888), // MVE_VQRSHRUNs16th |
| 821 | UINT64_C(4270854080), // MVE_VQRSHRUNs32bh |
| 822 | UINT64_C(4270858176), // MVE_VQRSHRUNs32th |
| 823 | UINT64_C(4287628880), // MVE_VQSHLU_imms16 |
| 824 | UINT64_C(4288677456), // MVE_VQSHLU_imms32 |
| 825 | UINT64_C(4287104592), // MVE_VQSHLU_imms8 |
| 826 | UINT64_C(4010804304), // MVE_VQSHL_by_vecs16 |
| 827 | UINT64_C(4011852880), // MVE_VQSHL_by_vecs32 |
| 828 | UINT64_C(4009755728), // MVE_VQSHL_by_vecs8 |
| 829 | UINT64_C(4279239760), // MVE_VQSHL_by_vecu16 |
| 830 | UINT64_C(4280288336), // MVE_VQSHL_by_vecu32 |
| 831 | UINT64_C(4278191184), // MVE_VQSHL_by_vecu8 |
| 832 | UINT64_C(3996458720), // MVE_VQSHL_qrs16 |
| 833 | UINT64_C(3996720864), // MVE_VQSHL_qrs32 |
| 834 | UINT64_C(3996196576), // MVE_VQSHL_qrs8 |
| 835 | UINT64_C(4264894176), // MVE_VQSHL_qru16 |
| 836 | UINT64_C(4265156320), // MVE_VQSHL_qru32 |
| 837 | UINT64_C(4264632032), // MVE_VQSHL_qru8 |
| 838 | UINT64_C(4019193680), // MVE_VQSHLimms16 |
| 839 | UINT64_C(4020242256), // MVE_VQSHLimms32 |
| 840 | UINT64_C(4018669392), // MVE_VQSHLimms8 |
| 841 | UINT64_C(4287629136), // MVE_VQSHLimmu16 |
| 842 | UINT64_C(4288677712), // MVE_VQSHLimmu32 |
| 843 | UINT64_C(4287104848), // MVE_VQSHLimmu8 |
| 844 | UINT64_C(4001894208), // MVE_VQSHRNbhs16 |
| 845 | UINT64_C(4002418496), // MVE_VQSHRNbhs32 |
| 846 | UINT64_C(4270329664), // MVE_VQSHRNbhu16 |
| 847 | UINT64_C(4270853952), // MVE_VQSHRNbhu32 |
| 848 | UINT64_C(4001898304), // MVE_VQSHRNths16 |
| 849 | UINT64_C(4002422592), // MVE_VQSHRNths32 |
| 850 | UINT64_C(4270333760), // MVE_VQSHRNthu16 |
| 851 | UINT64_C(4270858048), // MVE_VQSHRNthu32 |
| 852 | UINT64_C(4001894336), // MVE_VQSHRUNs16bh |
| 853 | UINT64_C(4001898432), // MVE_VQSHRUNs16th |
| 854 | UINT64_C(4002418624), // MVE_VQSHRUNs32bh |
| 855 | UINT64_C(4002422720), // MVE_VQSHRUNs32th |
| 856 | UINT64_C(3994034016), // MVE_VQSUB_qr_s16 |
| 857 | UINT64_C(3995082592), // MVE_VQSUB_qr_s32 |
| 858 | UINT64_C(3992985440), // MVE_VQSUB_qr_s8 |
| 859 | UINT64_C(4262469472), // MVE_VQSUB_qr_u16 |
| 860 | UINT64_C(4263518048), // MVE_VQSUB_qr_u32 |
| 861 | UINT64_C(4261420896), // MVE_VQSUB_qr_u8 |
| 862 | UINT64_C(4010803792), // MVE_VQSUBs16 |
| 863 | UINT64_C(4011852368), // MVE_VQSUBs32 |
| 864 | UINT64_C(4009755216), // MVE_VQSUBs8 |
| 865 | UINT64_C(4279239248), // MVE_VQSUBu16 |
| 866 | UINT64_C(4280287824), // MVE_VQSUBu32 |
| 867 | UINT64_C(4278190672), // MVE_VQSUBu8 |
| 868 | UINT64_C(4289724736), // MVE_VREV16_8 |
| 869 | UINT64_C(4289986752), // MVE_VREV32_16 |
| 870 | UINT64_C(4289724608), // MVE_VREV32_8 |
| 871 | UINT64_C(4289986624), // MVE_VREV64_16 |
| 872 | UINT64_C(4290248768), // MVE_VREV64_32 |
| 873 | UINT64_C(4289724480), // MVE_VREV64_8 |
| 874 | UINT64_C(4010803520), // MVE_VRHADDs16 |
| 875 | UINT64_C(4011852096), // MVE_VRHADDs32 |
| 876 | UINT64_C(4009754944), // MVE_VRHADDs8 |
| 877 | UINT64_C(4279238976), // MVE_VRHADDu16 |
| 878 | UINT64_C(4280287552), // MVE_VRHADDu32 |
| 879 | UINT64_C(4278190400), // MVE_VRHADDu8 |
| 880 | UINT64_C(4290118976), // MVE_VRINTf16A |
| 881 | UINT64_C(4290119360), // MVE_VRINTf16M |
| 882 | UINT64_C(4290118720), // MVE_VRINTf16N |
| 883 | UINT64_C(4290119616), // MVE_VRINTf16P |
| 884 | UINT64_C(4290118848), // MVE_VRINTf16X |
| 885 | UINT64_C(4290119104), // MVE_VRINTf16Z |
| 886 | UINT64_C(4290381120), // MVE_VRINTf32A |
| 887 | UINT64_C(4290381504), // MVE_VRINTf32M |
| 888 | UINT64_C(4290380864), // MVE_VRINTf32N |
| 889 | UINT64_C(4290381760), // MVE_VRINTf32P |
| 890 | UINT64_C(4290380992), // MVE_VRINTf32X |
| 891 | UINT64_C(4290381248), // MVE_VRINTf32Z |
| 892 | UINT64_C(4001369888), // MVE_VRMLALDAVHas32 |
| 893 | UINT64_C(4269805344), // MVE_VRMLALDAVHau32 |
| 894 | UINT64_C(4001373984), // MVE_VRMLALDAVHaxs32 |
| 895 | UINT64_C(4001369856), // MVE_VRMLALDAVHs32 |
| 896 | UINT64_C(4269805312), // MVE_VRMLALDAVHu32 |
| 897 | UINT64_C(4001373952), // MVE_VRMLALDAVHxs32 |
| 898 | UINT64_C(4269805089), // MVE_VRMLSLDAVHas32 |
| 899 | UINT64_C(4269809185), // MVE_VRMLSLDAVHaxs32 |
| 900 | UINT64_C(4269805057), // MVE_VRMLSLDAVHs32 |
| 901 | UINT64_C(4269809153), // MVE_VRMLSLDAVHxs32 |
| 902 | UINT64_C(3994099201), // MVE_VRMULHs16 |
| 903 | UINT64_C(3995147777), // MVE_VRMULHs32 |
| 904 | UINT64_C(3993050625), // MVE_VRMULHs8 |
| 905 | UINT64_C(4262534657), // MVE_VRMULHu16 |
| 906 | UINT64_C(4263583233), // MVE_VRMULHu32 |
| 907 | UINT64_C(4261486081), // MVE_VRMULHu8 |
| 908 | UINT64_C(4010804544), // MVE_VRSHL_by_vecs16 |
| 909 | UINT64_C(4011853120), // MVE_VRSHL_by_vecs32 |
| 910 | UINT64_C(4009755968), // MVE_VRSHL_by_vecs8 |
| 911 | UINT64_C(4279240000), // MVE_VRSHL_by_vecu16 |
| 912 | UINT64_C(4280288576), // MVE_VRSHL_by_vecu32 |
| 913 | UINT64_C(4278191424), // MVE_VRSHL_by_vecu8 |
| 914 | UINT64_C(3996589664), // MVE_VRSHL_qrs16 |
| 915 | UINT64_C(3996851808), // MVE_VRSHL_qrs32 |
| 916 | UINT64_C(3996327520), // MVE_VRSHL_qrs8 |
| 917 | UINT64_C(4265025120), // MVE_VRSHL_qru16 |
| 918 | UINT64_C(4265287264), // MVE_VRSHL_qru32 |
| 919 | UINT64_C(4264762976), // MVE_VRSHL_qru8 |
| 920 | UINT64_C(4270329793), // MVE_VRSHRNi16bh |
| 921 | UINT64_C(4270333889), // MVE_VRSHRNi16th |
| 922 | UINT64_C(4270854081), // MVE_VRSHRNi32bh |
| 923 | UINT64_C(4270858177), // MVE_VRSHRNi32th |
| 924 | UINT64_C(4019192400), // MVE_VRSHR_imms16 |
| 925 | UINT64_C(4020240976), // MVE_VRSHR_imms32 |
| 926 | UINT64_C(4018668112), // MVE_VRSHR_imms8 |
| 927 | UINT64_C(4287627856), // MVE_VRSHR_immu16 |
| 928 | UINT64_C(4288676432), // MVE_VRSHR_immu32 |
| 929 | UINT64_C(4287103568), // MVE_VRSHR_immu8 |
| 930 | UINT64_C(4264562432), // MVE_VSBC |
| 931 | UINT64_C(4264566528), // MVE_VSBCI |
| 932 | UINT64_C(4003467200), // MVE_VSHLC |
| 933 | UINT64_C(4004515648), // MVE_VSHLL_imms16bh |
| 934 | UINT64_C(4004519744), // MVE_VSHLL_imms16th |
| 935 | UINT64_C(4003991360), // MVE_VSHLL_imms8bh |
| 936 | UINT64_C(4003995456), // MVE_VSHLL_imms8th |
| 937 | UINT64_C(4272951104), // MVE_VSHLL_immu16bh |
| 938 | UINT64_C(4272955200), // MVE_VSHLL_immu16th |
| 939 | UINT64_C(4272426816), // MVE_VSHLL_immu8bh |
| 940 | UINT64_C(4272430912), // MVE_VSHLL_immu8th |
| 941 | UINT64_C(3996454401), // MVE_VSHLL_lws16bh |
| 942 | UINT64_C(3996458497), // MVE_VSHLL_lws16th |
| 943 | UINT64_C(3996192257), // MVE_VSHLL_lws8bh |
| 944 | UINT64_C(3996196353), // MVE_VSHLL_lws8th |
| 945 | UINT64_C(4264889857), // MVE_VSHLL_lwu16bh |
| 946 | UINT64_C(4264893953), // MVE_VSHLL_lwu16th |
| 947 | UINT64_C(4264627713), // MVE_VSHLL_lwu8bh |
| 948 | UINT64_C(4264631809), // MVE_VSHLL_lwu8th |
| 949 | UINT64_C(4010804288), // MVE_VSHL_by_vecs16 |
| 950 | UINT64_C(4011852864), // MVE_VSHL_by_vecs32 |
| 951 | UINT64_C(4009755712), // MVE_VSHL_by_vecs8 |
| 952 | UINT64_C(4279239744), // MVE_VSHL_by_vecu16 |
| 953 | UINT64_C(4280288320), // MVE_VSHL_by_vecu32 |
| 954 | UINT64_C(4278191168), // MVE_VSHL_by_vecu8 |
| 955 | UINT64_C(4019193168), // MVE_VSHL_immi16 |
| 956 | UINT64_C(4020241744), // MVE_VSHL_immi32 |
| 957 | UINT64_C(4018668880), // MVE_VSHL_immi8 |
| 958 | UINT64_C(3996458592), // MVE_VSHL_qrs16 |
| 959 | UINT64_C(3996720736), // MVE_VSHL_qrs32 |
| 960 | UINT64_C(3996196448), // MVE_VSHL_qrs8 |
| 961 | UINT64_C(4264894048), // MVE_VSHL_qru16 |
| 962 | UINT64_C(4265156192), // MVE_VSHL_qru32 |
| 963 | UINT64_C(4264631904), // MVE_VSHL_qru8 |
| 964 | UINT64_C(4001894337), // MVE_VSHRNi16bh |
| 965 | UINT64_C(4001898433), // MVE_VSHRNi16th |
| 966 | UINT64_C(4002418625), // MVE_VSHRNi32bh |
| 967 | UINT64_C(4002422721), // MVE_VSHRNi32th |
| 968 | UINT64_C(4019191888), // MVE_VSHR_imms16 |
| 969 | UINT64_C(4020240464), // MVE_VSHR_imms32 |
| 970 | UINT64_C(4018667600), // MVE_VSHR_imms8 |
| 971 | UINT64_C(4287627344), // MVE_VSHR_immu16 |
| 972 | UINT64_C(4288675920), // MVE_VSHR_immu32 |
| 973 | UINT64_C(4287103056), // MVE_VSHR_immu8 |
| 974 | UINT64_C(4287628624), // MVE_VSLIimm16 |
| 975 | UINT64_C(4288677200), // MVE_VSLIimm32 |
| 976 | UINT64_C(4287104336), // MVE_VSLIimm8 |
| 977 | UINT64_C(4287628368), // MVE_VSRIimm16 |
| 978 | UINT64_C(4288676944), // MVE_VSRIimm32 |
| 979 | UINT64_C(4287104080), // MVE_VSRIimm8 |
| 980 | UINT64_C(4236254848), // MVE_VST20_16 |
| 981 | UINT64_C(4238352000), // MVE_VST20_16_wb |
| 982 | UINT64_C(4236254976), // MVE_VST20_32 |
| 983 | UINT64_C(4238352128), // MVE_VST20_32_wb |
| 984 | UINT64_C(4236254720), // MVE_VST20_8 |
| 985 | UINT64_C(4238351872), // MVE_VST20_8_wb |
| 986 | UINT64_C(4236254880), // MVE_VST21_16 |
| 987 | UINT64_C(4238352032), // MVE_VST21_16_wb |
| 988 | UINT64_C(4236255008), // MVE_VST21_32 |
| 989 | UINT64_C(4238352160), // MVE_VST21_32_wb |
| 990 | UINT64_C(4236254752), // MVE_VST21_8 |
| 991 | UINT64_C(4238351904), // MVE_VST21_8_wb |
| 992 | UINT64_C(4236254849), // MVE_VST40_16 |
| 993 | UINT64_C(4238352001), // MVE_VST40_16_wb |
| 994 | UINT64_C(4236254977), // MVE_VST40_32 |
| 995 | UINT64_C(4238352129), // MVE_VST40_32_wb |
| 996 | UINT64_C(4236254721), // MVE_VST40_8 |
| 997 | UINT64_C(4238351873), // MVE_VST40_8_wb |
| 998 | UINT64_C(4236254881), // MVE_VST41_16 |
| 999 | UINT64_C(4238352033), // MVE_VST41_16_wb |
| 1000 | UINT64_C(4236255009), // MVE_VST41_32 |
| 1001 | UINT64_C(4238352161), // MVE_VST41_32_wb |
| 1002 | UINT64_C(4236254753), // MVE_VST41_8 |
| 1003 | UINT64_C(4238351905), // MVE_VST41_8_wb |
| 1004 | UINT64_C(4236254913), // MVE_VST42_16 |
| 1005 | UINT64_C(4238352065), // MVE_VST42_16_wb |
| 1006 | UINT64_C(4236255041), // MVE_VST42_32 |
| 1007 | UINT64_C(4238352193), // MVE_VST42_32_wb |
| 1008 | UINT64_C(4236254785), // MVE_VST42_8 |
| 1009 | UINT64_C(4238351937), // MVE_VST42_8_wb |
| 1010 | UINT64_C(4236254945), // MVE_VST43_16 |
| 1011 | UINT64_C(4238352097), // MVE_VST43_16_wb |
| 1012 | UINT64_C(4236255073), // MVE_VST43_32 |
| 1013 | UINT64_C(4238352225), // MVE_VST43_32_wb |
| 1014 | UINT64_C(4236254817), // MVE_VST43_8 |
| 1015 | UINT64_C(4238351969), // MVE_VST43_8_wb |
| 1016 | UINT64_C(3976203904), // MVE_VSTRB16 |
| 1017 | UINT64_C(3961523840), // MVE_VSTRB16_post |
| 1018 | UINT64_C(3978301056), // MVE_VSTRB16_pre |
| 1019 | UINT64_C(3967815296), // MVE_VSTRB16_rq |
| 1020 | UINT64_C(3976204032), // MVE_VSTRB32 |
| 1021 | UINT64_C(3961523968), // MVE_VSTRB32_post |
| 1022 | UINT64_C(3978301184), // MVE_VSTRB32_pre |
| 1023 | UINT64_C(3967815424), // MVE_VSTRB32_rq |
| 1024 | UINT64_C(3967815168), // MVE_VSTRB8_rq |
| 1025 | UINT64_C(3976207872), // MVE_VSTRBU8 |
| 1026 | UINT64_C(3961527808), // MVE_VSTRBU8_post |
| 1027 | UINT64_C(3978305024), // MVE_VSTRBU8_pre |
| 1028 | UINT64_C(4244643584), // MVE_VSTRD64_qi |
| 1029 | UINT64_C(4246740736), // MVE_VSTRD64_qi_pre |
| 1030 | UINT64_C(3967815633), // MVE_VSTRD64_rq |
| 1031 | UINT64_C(3967815632), // MVE_VSTRD64_rq_u |
| 1032 | UINT64_C(3967815313), // MVE_VSTRH16_rq |
| 1033 | UINT64_C(3967815312), // MVE_VSTRH16_rq_u |
| 1034 | UINT64_C(3976728320), // MVE_VSTRH32 |
| 1035 | UINT64_C(3962048256), // MVE_VSTRH32_post |
| 1036 | UINT64_C(3978825472), // MVE_VSTRH32_pre |
| 1037 | UINT64_C(3967815441), // MVE_VSTRH32_rq |
| 1038 | UINT64_C(3967815440), // MVE_VSTRH32_rq_u |
| 1039 | UINT64_C(3976208000), // MVE_VSTRHU16 |
| 1040 | UINT64_C(3961527936), // MVE_VSTRHU16_post |
| 1041 | UINT64_C(3978305152), // MVE_VSTRHU16_pre |
| 1042 | UINT64_C(4244643328), // MVE_VSTRW32_qi |
| 1043 | UINT64_C(4246740480), // MVE_VSTRW32_qi_pre |
| 1044 | UINT64_C(3967815489), // MVE_VSTRW32_rq |
| 1045 | UINT64_C(3967815488), // MVE_VSTRW32_rq_u |
| 1046 | UINT64_C(3976208128), // MVE_VSTRWU32 |
| 1047 | UINT64_C(3961528064), // MVE_VSTRWU32_post |
| 1048 | UINT64_C(3978305280), // MVE_VSTRWU32_pre |
| 1049 | UINT64_C(4264566592), // MVE_VSUB_qr_f16 |
| 1050 | UINT64_C(3996131136), // MVE_VSUB_qr_f32 |
| 1051 | UINT64_C(3994099520), // MVE_VSUB_qr_i16 |
| 1052 | UINT64_C(3995148096), // MVE_VSUB_qr_i32 |
| 1053 | UINT64_C(3993050944), // MVE_VSUB_qr_i8 |
| 1054 | UINT64_C(4012903744), // MVE_VSUBf16 |
| 1055 | UINT64_C(4011855168), // MVE_VSUBf32 |
| 1056 | UINT64_C(4279240768), // MVE_VSUBi16 |
| 1057 | UINT64_C(4280289344), // MVE_VSUBi32 |
| 1058 | UINT64_C(4278192192), // MVE_VSUBi8 |
| 1059 | UINT64_C(4027629569), // MVE_WLSTP_16 |
| 1060 | UINT64_C(4028678145), // MVE_WLSTP_32 |
| 1061 | UINT64_C(4029726721), // MVE_WLSTP_64 |
| 1062 | UINT64_C(4026580993), // MVE_WLSTP_8 |
| 1063 | UINT64_C(65011712), // MVNi |
| 1064 | UINT64_C(31457280), // MVNr |
| 1065 | UINT64_C(31457280), // MVNsi |
| 1066 | UINT64_C(31457296), // MVNsr |
| 1067 | UINT64_C(4076867344), // NEON_VMAXNMNDf |
| 1068 | UINT64_C(4077915920), // NEON_VMAXNMNDh |
| 1069 | UINT64_C(4076867408), // NEON_VMAXNMNQf |
| 1070 | UINT64_C(4077915984), // NEON_VMAXNMNQh |
| 1071 | UINT64_C(4078964496), // NEON_VMINNMNDf |
| 1072 | UINT64_C(4080013072), // NEON_VMINNMNDh |
| 1073 | UINT64_C(4078964560), // NEON_VMINNMNQf |
| 1074 | UINT64_C(4080013136), // NEON_VMINNMNQh |
| 1075 | UINT64_C(58720256), // ORRri |
| 1076 | UINT64_C(25165824), // ORRrr |
| 1077 | UINT64_C(25165824), // ORRrsi |
| 1078 | UINT64_C(25165840), // ORRrsr |
| 1079 | UINT64_C(109051920), // PKHBT |
| 1080 | UINT64_C(109051984), // PKHTB |
| 1081 | UINT64_C(4111527936), // PLDWi12 |
| 1082 | UINT64_C(4145082368), // PLDWrs |
| 1083 | UINT64_C(4115722240), // PLDi12 |
| 1084 | UINT64_C(4149276672), // PLDrs |
| 1085 | UINT64_C(4098945024), // PLIi12 |
| 1086 | UINT64_C(4132499456), // PLIrs |
| 1087 | UINT64_C(16777296), // QADD |
| 1088 | UINT64_C(102764304), // QADD16 |
| 1089 | UINT64_C(102764432), // QADD8 |
| 1090 | UINT64_C(102764336), // QASX |
| 1091 | UINT64_C(20971600), // QDADD |
| 1092 | UINT64_C(23068752), // QDSUB |
| 1093 | UINT64_C(102764368), // QSAX |
| 1094 | UINT64_C(18874448), // QSUB |
| 1095 | UINT64_C(102764400), // QSUB16 |
| 1096 | UINT64_C(102764528), // QSUB8 |
| 1097 | UINT64_C(117378864), // RBIT |
| 1098 | UINT64_C(113184560), // REV |
| 1099 | UINT64_C(113184688), // REV16 |
| 1100 | UINT64_C(117378992), // REVSH |
| 1101 | UINT64_C(4161800704), // RFEDA |
| 1102 | UINT64_C(4163897856), // RFEDA_UPD |
| 1103 | UINT64_C(4178577920), // RFEDB |
| 1104 | UINT64_C(4180675072), // RFEDB_UPD |
| 1105 | UINT64_C(4170189312), // RFEIA |
| 1106 | UINT64_C(4172286464), // RFEIA_UPD |
| 1107 | UINT64_C(4186966528), // RFEIB |
| 1108 | UINT64_C(4189063680), // RFEIB_UPD |
| 1109 | UINT64_C(39845888), // RSBri |
| 1110 | UINT64_C(6291456), // RSBrr |
| 1111 | UINT64_C(6291456), // RSBrsi |
| 1112 | UINT64_C(6291472), // RSBrsr |
| 1113 | UINT64_C(48234496), // RSCri |
| 1114 | UINT64_C(14680064), // RSCrr |
| 1115 | UINT64_C(14680064), // RSCrsi |
| 1116 | UINT64_C(14680080), // RSCrsr |
| 1117 | UINT64_C(101715728), // SADD16 |
| 1118 | UINT64_C(101715856), // SADD8 |
| 1119 | UINT64_C(101715760), // SASX |
| 1120 | UINT64_C(4118802544), // SB |
| 1121 | UINT64_C(46137344), // SBCri |
| 1122 | UINT64_C(12582912), // SBCrr |
| 1123 | UINT64_C(12582912), // SBCrsi |
| 1124 | UINT64_C(12582928), // SBCrsr |
| 1125 | UINT64_C(127926352), // SBFX |
| 1126 | UINT64_C(118550544), // SDIV |
| 1127 | UINT64_C(109055920), // SEL |
| 1128 | UINT64_C(4043374592), // SETEND |
| 1129 | UINT64_C(4044357632), // SETPAN |
| 1130 | UINT64_C(4060089408), // SHA1C |
| 1131 | UINT64_C(4088988352), // SHA1H |
| 1132 | UINT64_C(4062186560), // SHA1M |
| 1133 | UINT64_C(4061137984), // SHA1P |
| 1134 | UINT64_C(4063235136), // SHA1SU0 |
| 1135 | UINT64_C(4089054080), // SHA1SU1 |
| 1136 | UINT64_C(4076866624), // SHA256H |
| 1137 | UINT64_C(4077915200), // SHA256H2 |
| 1138 | UINT64_C(4089054144), // SHA256SU0 |
| 1139 | UINT64_C(4078963776), // SHA256SU1 |
| 1140 | UINT64_C(103812880), // SHADD16 |
| 1141 | UINT64_C(103813008), // SHADD8 |
| 1142 | UINT64_C(103812912), // SHASX |
| 1143 | UINT64_C(103812944), // SHSAX |
| 1144 | UINT64_C(103812976), // SHSUB16 |
| 1145 | UINT64_C(103813104), // SHSUB8 |
| 1146 | UINT64_C(23068784), // SMC |
| 1147 | UINT64_C(16777344), // SMLABB |
| 1148 | UINT64_C(16777408), // SMLABT |
| 1149 | UINT64_C(117440528), // SMLAD |
| 1150 | UINT64_C(117440560), // SMLADX |
| 1151 | UINT64_C(14680208), // SMLAL |
| 1152 | UINT64_C(20971648), // SMLALBB |
| 1153 | UINT64_C(20971712), // SMLALBT |
| 1154 | UINT64_C(121634832), // SMLALD |
| 1155 | UINT64_C(121634864), // SMLALDX |
| 1156 | UINT64_C(20971680), // SMLALTB |
| 1157 | UINT64_C(20971744), // SMLALTT |
| 1158 | UINT64_C(16777376), // SMLATB |
| 1159 | UINT64_C(16777440), // SMLATT |
| 1160 | UINT64_C(18874496), // SMLAWB |
| 1161 | UINT64_C(18874560), // SMLAWT |
| 1162 | UINT64_C(117440592), // SMLSD |
| 1163 | UINT64_C(117440624), // SMLSDX |
| 1164 | UINT64_C(121634896), // SMLSLD |
| 1165 | UINT64_C(121634928), // SMLSLDX |
| 1166 | UINT64_C(122683408), // SMMLA |
| 1167 | UINT64_C(122683440), // SMMLAR |
| 1168 | UINT64_C(122683600), // SMMLS |
| 1169 | UINT64_C(122683632), // SMMLSR |
| 1170 | UINT64_C(122744848), // SMMUL |
| 1171 | UINT64_C(122744880), // SMMULR |
| 1172 | UINT64_C(117501968), // SMUAD |
| 1173 | UINT64_C(117502000), // SMUADX |
| 1174 | UINT64_C(23068800), // SMULBB |
| 1175 | UINT64_C(23068864), // SMULBT |
| 1176 | UINT64_C(12583056), // SMULL |
| 1177 | UINT64_C(23068832), // SMULTB |
| 1178 | UINT64_C(23068896), // SMULTT |
| 1179 | UINT64_C(18874528), // SMULWB |
| 1180 | UINT64_C(18874592), // SMULWT |
| 1181 | UINT64_C(117502032), // SMUSD |
| 1182 | UINT64_C(117502064), // SMUSDX |
| 1183 | UINT64_C(4165797120), // SRSDA |
| 1184 | UINT64_C(4167894272), // SRSDA_UPD |
| 1185 | UINT64_C(4182574336), // SRSDB |
| 1186 | UINT64_C(4184671488), // SRSDB_UPD |
| 1187 | UINT64_C(4174185728), // SRSIA |
| 1188 | UINT64_C(4176282880), // SRSIA_UPD |
| 1189 | UINT64_C(4190962944), // SRSIB |
| 1190 | UINT64_C(4193060096), // SRSIB_UPD |
| 1191 | UINT64_C(111149072), // SSAT |
| 1192 | UINT64_C(111152944), // SSAT16 |
| 1193 | UINT64_C(101715792), // SSAX |
| 1194 | UINT64_C(101715824), // SSUB16 |
| 1195 | UINT64_C(101715952), // SSUB8 |
| 1196 | UINT64_C(4248829952), // STC2L_OFFSET |
| 1197 | UINT64_C(4240441344), // STC2L_OPTION |
| 1198 | UINT64_C(4234149888), // STC2L_POST |
| 1199 | UINT64_C(4250927104), // STC2L_PRE |
| 1200 | UINT64_C(4244635648), // STC2_OFFSET |
| 1201 | UINT64_C(4236247040), // STC2_OPTION |
| 1202 | UINT64_C(4229955584), // STC2_POST |
| 1203 | UINT64_C(4246732800), // STC2_PRE |
| 1204 | UINT64_C(222298112), // STCL_OFFSET |
| 1205 | UINT64_C(213909504), // STCL_OPTION |
| 1206 | UINT64_C(207618048), // STCL_POST |
| 1207 | UINT64_C(224395264), // STCL_PRE |
| 1208 | UINT64_C(218103808), // STC_OFFSET |
| 1209 | UINT64_C(209715200), // STC_OPTION |
| 1210 | UINT64_C(203423744), // STC_POST |
| 1211 | UINT64_C(220200960), // STC_PRE |
| 1212 | UINT64_C(25230480), // STL |
| 1213 | UINT64_C(29424784), // STLB |
| 1214 | UINT64_C(25169552), // STLEX |
| 1215 | UINT64_C(29363856), // STLEXB |
| 1216 | UINT64_C(27266704), // STLEXD |
| 1217 | UINT64_C(31461008), // STLEXH |
| 1218 | UINT64_C(31521936), // STLH |
| 1219 | UINT64_C(134217728), // STMDA |
| 1220 | UINT64_C(136314880), // STMDA_UPD |
| 1221 | UINT64_C(150994944), // STMDB |
| 1222 | UINT64_C(153092096), // STMDB_UPD |
| 1223 | UINT64_C(142606336), // STMIA |
| 1224 | UINT64_C(144703488), // STMIA_UPD |
| 1225 | UINT64_C(159383552), // STMIB |
| 1226 | UINT64_C(161480704), // STMIB_UPD |
| 1227 | UINT64_C(73400320), // STRBT_POST_IMM |
| 1228 | UINT64_C(106954752), // STRBT_POST_REG |
| 1229 | UINT64_C(71303168), // STRB_POST_IMM |
| 1230 | UINT64_C(104857600), // STRB_POST_REG |
| 1231 | UINT64_C(90177536), // STRB_PRE_IMM |
| 1232 | UINT64_C(123731968), // STRB_PRE_REG |
| 1233 | UINT64_C(88080384), // STRBi12 |
| 1234 | UINT64_C(121634816), // STRBrs |
| 1235 | UINT64_C(16777456), // STRD |
| 1236 | UINT64_C(240), // STRD_POST |
| 1237 | UINT64_C(18874608), // STRD_PRE |
| 1238 | UINT64_C(25169808), // STREX |
| 1239 | UINT64_C(29364112), // STREXB |
| 1240 | UINT64_C(27266960), // STREXD |
| 1241 | UINT64_C(31461264), // STREXH |
| 1242 | UINT64_C(16777392), // STRH |
| 1243 | UINT64_C(6291632), // STRHTi |
| 1244 | UINT64_C(2097328), // STRHTr |
| 1245 | UINT64_C(176), // STRH_POST |
| 1246 | UINT64_C(18874544), // STRH_PRE |
| 1247 | UINT64_C(69206016), // STRT_POST_IMM |
| 1248 | UINT64_C(102760448), // STRT_POST_REG |
| 1249 | UINT64_C(67108864), // STR_POST_IMM |
| 1250 | UINT64_C(100663296), // STR_POST_REG |
| 1251 | UINT64_C(85983232), // STR_PRE_IMM |
| 1252 | UINT64_C(119537664), // STR_PRE_REG |
| 1253 | UINT64_C(83886080), // STRi12 |
| 1254 | UINT64_C(117440512), // STRrs |
| 1255 | UINT64_C(37748736), // SUBri |
| 1256 | UINT64_C(4194304), // SUBrr |
| 1257 | UINT64_C(4194304), // SUBrsi |
| 1258 | UINT64_C(4194320), // SUBrsr |
| 1259 | UINT64_C(251658240), // SVC |
| 1260 | UINT64_C(16777360), // SWP |
| 1261 | UINT64_C(20971664), // SWPB |
| 1262 | UINT64_C(111149168), // SXTAB |
| 1263 | UINT64_C(109052016), // SXTAB16 |
| 1264 | UINT64_C(112197744), // SXTAH |
| 1265 | UINT64_C(112132208), // SXTB |
| 1266 | UINT64_C(110035056), // SXTB16 |
| 1267 | UINT64_C(113180784), // SXTH |
| 1268 | UINT64_C(53477376), // TEQri |
| 1269 | UINT64_C(19922944), // TEQrr |
| 1270 | UINT64_C(19922944), // TEQrsi |
| 1271 | UINT64_C(19922960), // TEQrsr |
| 1272 | UINT64_C(3892305662), // TRAP |
| 1273 | UINT64_C(3810586642), // TSB |
| 1274 | UINT64_C(51380224), // TSTri |
| 1275 | UINT64_C(17825792), // TSTrr |
| 1276 | UINT64_C(17825792), // TSTrsi |
| 1277 | UINT64_C(17825808), // TSTrsr |
| 1278 | UINT64_C(105910032), // UADD16 |
| 1279 | UINT64_C(105910160), // UADD8 |
| 1280 | UINT64_C(105910064), // UASX |
| 1281 | UINT64_C(132120656), // UBFX |
| 1282 | UINT64_C(3891265776), // UDF |
| 1283 | UINT64_C(120647696), // UDIV |
| 1284 | UINT64_C(108007184), // UHADD16 |
| 1285 | UINT64_C(108007312), // UHADD8 |
| 1286 | UINT64_C(108007216), // UHASX |
| 1287 | UINT64_C(108007248), // UHSAX |
| 1288 | UINT64_C(108007280), // UHSUB16 |
| 1289 | UINT64_C(108007408), // UHSUB8 |
| 1290 | UINT64_C(4194448), // UMAAL |
| 1291 | UINT64_C(10485904), // UMLAL |
| 1292 | UINT64_C(8388752), // UMULL |
| 1293 | UINT64_C(106958608), // UQADD16 |
| 1294 | UINT64_C(106958736), // UQADD8 |
| 1295 | UINT64_C(106958640), // UQASX |
| 1296 | UINT64_C(106958672), // UQSAX |
| 1297 | UINT64_C(106958704), // UQSUB16 |
| 1298 | UINT64_C(106958832), // UQSUB8 |
| 1299 | UINT64_C(125890576), // USAD8 |
| 1300 | UINT64_C(125829136), // USADA8 |
| 1301 | UINT64_C(115343376), // USAT |
| 1302 | UINT64_C(115347248), // USAT16 |
| 1303 | UINT64_C(105910096), // USAX |
| 1304 | UINT64_C(105910128), // USUB16 |
| 1305 | UINT64_C(105910256), // USUB8 |
| 1306 | UINT64_C(115343472), // UXTAB |
| 1307 | UINT64_C(113246320), // UXTAB16 |
| 1308 | UINT64_C(116392048), // UXTAH |
| 1309 | UINT64_C(116326512), // UXTB |
| 1310 | UINT64_C(114229360), // UXTB16 |
| 1311 | UINT64_C(117375088), // UXTH |
| 1312 | UINT64_C(4070573312), // VABALsv2i64 |
| 1313 | UINT64_C(4069524736), // VABALsv4i32 |
| 1314 | UINT64_C(4068476160), // VABALsv8i16 |
| 1315 | UINT64_C(4087350528), // VABALuv2i64 |
| 1316 | UINT64_C(4086301952), // VABALuv4i32 |
| 1317 | UINT64_C(4085253376), // VABALuv8i16 |
| 1318 | UINT64_C(4060088144), // VABAsv16i8 |
| 1319 | UINT64_C(4062185232), // VABAsv2i32 |
| 1320 | UINT64_C(4061136656), // VABAsv4i16 |
| 1321 | UINT64_C(4062185296), // VABAsv4i32 |
| 1322 | UINT64_C(4061136720), // VABAsv8i16 |
| 1323 | UINT64_C(4060088080), // VABAsv8i8 |
| 1324 | UINT64_C(4076865360), // VABAuv16i8 |
| 1325 | UINT64_C(4078962448), // VABAuv2i32 |
| 1326 | UINT64_C(4077913872), // VABAuv4i16 |
| 1327 | UINT64_C(4078962512), // VABAuv4i32 |
| 1328 | UINT64_C(4077913936), // VABAuv8i16 |
| 1329 | UINT64_C(4076865296), // VABAuv8i8 |
| 1330 | UINT64_C(4070573824), // VABDLsv2i64 |
| 1331 | UINT64_C(4069525248), // VABDLsv4i32 |
| 1332 | UINT64_C(4068476672), // VABDLsv8i16 |
| 1333 | UINT64_C(4087351040), // VABDLuv2i64 |
| 1334 | UINT64_C(4086302464), // VABDLuv4i32 |
| 1335 | UINT64_C(4085253888), // VABDLuv8i16 |
| 1336 | UINT64_C(4078963968), // VABDfd |
| 1337 | UINT64_C(4078964032), // VABDfq |
| 1338 | UINT64_C(4080012544), // VABDhd |
| 1339 | UINT64_C(4080012608), // VABDhq |
| 1340 | UINT64_C(4060088128), // VABDsv16i8 |
| 1341 | UINT64_C(4062185216), // VABDsv2i32 |
| 1342 | UINT64_C(4061136640), // VABDsv4i16 |
| 1343 | UINT64_C(4062185280), // VABDsv4i32 |
| 1344 | UINT64_C(4061136704), // VABDsv8i16 |
| 1345 | UINT64_C(4060088064), // VABDsv8i8 |
| 1346 | UINT64_C(4076865344), // VABDuv16i8 |
| 1347 | UINT64_C(4078962432), // VABDuv2i32 |
| 1348 | UINT64_C(4077913856), // VABDuv4i16 |
| 1349 | UINT64_C(4078962496), // VABDuv4i32 |
| 1350 | UINT64_C(4077913920), // VABDuv8i16 |
| 1351 | UINT64_C(4076865280), // VABDuv8i8 |
| 1352 | UINT64_C(246418368), // VABSD |
| 1353 | UINT64_C(246417856), // VABSH |
| 1354 | UINT64_C(246418112), // VABSS |
| 1355 | UINT64_C(4088989440), // VABSfd |
| 1356 | UINT64_C(4088989504), // VABSfq |
| 1357 | UINT64_C(4088727296), // VABShd |
| 1358 | UINT64_C(4088727360), // VABShq |
| 1359 | UINT64_C(4088464192), // VABSv16i8 |
| 1360 | UINT64_C(4088988416), // VABSv2i32 |
| 1361 | UINT64_C(4088726272), // VABSv4i16 |
| 1362 | UINT64_C(4088988480), // VABSv4i32 |
| 1363 | UINT64_C(4088726336), // VABSv8i16 |
| 1364 | UINT64_C(4088464128), // VABSv8i8 |
| 1365 | UINT64_C(4076867088), // VACGEfd |
| 1366 | UINT64_C(4076867152), // VACGEfq |
| 1367 | UINT64_C(4077915664), // VACGEhd |
| 1368 | UINT64_C(4077915728), // VACGEhq |
| 1369 | UINT64_C(4078964240), // VACGTfd |
| 1370 | UINT64_C(4078964304), // VACGTfq |
| 1371 | UINT64_C(4080012816), // VACGThd |
| 1372 | UINT64_C(4080012880), // VACGThq |
| 1373 | UINT64_C(238029568), // VADDD |
| 1374 | UINT64_C(238029056), // VADDH |
| 1375 | UINT64_C(4070573056), // VADDHNv2i32 |
| 1376 | UINT64_C(4069524480), // VADDHNv4i16 |
| 1377 | UINT64_C(4068475904), // VADDHNv8i8 |
| 1378 | UINT64_C(4070572032), // VADDLsv2i64 |
| 1379 | UINT64_C(4069523456), // VADDLsv4i32 |
| 1380 | UINT64_C(4068474880), // VADDLsv8i16 |
| 1381 | UINT64_C(4087349248), // VADDLuv2i64 |
| 1382 | UINT64_C(4086300672), // VADDLuv4i32 |
| 1383 | UINT64_C(4085252096), // VADDLuv8i16 |
| 1384 | UINT64_C(238029312), // VADDS |
| 1385 | UINT64_C(4070572288), // VADDWsv2i64 |
| 1386 | UINT64_C(4069523712), // VADDWsv4i32 |
| 1387 | UINT64_C(4068475136), // VADDWsv8i16 |
| 1388 | UINT64_C(4087349504), // VADDWuv2i64 |
| 1389 | UINT64_C(4086300928), // VADDWuv4i32 |
| 1390 | UINT64_C(4085252352), // VADDWuv8i16 |
| 1391 | UINT64_C(4060089600), // VADDfd |
| 1392 | UINT64_C(4060089664), // VADDfq |
| 1393 | UINT64_C(4061138176), // VADDhd |
| 1394 | UINT64_C(4061138240), // VADDhq |
| 1395 | UINT64_C(4060088384), // VADDv16i8 |
| 1396 | UINT64_C(4063234048), // VADDv1i64 |
| 1397 | UINT64_C(4062185472), // VADDv2i32 |
| 1398 | UINT64_C(4063234112), // VADDv2i64 |
| 1399 | UINT64_C(4061136896), // VADDv4i16 |
| 1400 | UINT64_C(4062185536), // VADDv4i32 |
| 1401 | UINT64_C(4061136960), // VADDv8i16 |
| 1402 | UINT64_C(4060088320), // VADDv8i8 |
| 1403 | UINT64_C(4060086544), // VANDd |
| 1404 | UINT64_C(4060086608), // VANDq |
| 1405 | UINT64_C(4231006224), // VBF16MALBQ |
| 1406 | UINT64_C(4264560656), // VBF16MALBQI |
| 1407 | UINT64_C(4231006288), // VBF16MALTQ |
| 1408 | UINT64_C(4264560720), // VBF16MALTQI |
| 1409 | UINT64_C(4061135120), // VBICd |
| 1410 | UINT64_C(4068475184), // VBICiv2i32 |
| 1411 | UINT64_C(4068477232), // VBICiv4i16 |
| 1412 | UINT64_C(4068475248), // VBICiv4i32 |
| 1413 | UINT64_C(4068477296), // VBICiv8i16 |
| 1414 | UINT64_C(4061135184), // VBICq |
| 1415 | UINT64_C(4080009488), // VBIFd |
| 1416 | UINT64_C(4080009552), // VBIFq |
| 1417 | UINT64_C(4078960912), // VBITd |
| 1418 | UINT64_C(4078960976), // VBITq |
| 1419 | UINT64_C(4077912336), // VBSLd |
| 1420 | UINT64_C(4077912400), // VBSLq |
| 1421 | UINT64_C(0), // VBSPd |
| 1422 | UINT64_C(0), // VBSPq |
| 1423 | UINT64_C(4237297664), // VCADDv2f32 |
| 1424 | UINT64_C(4236249088), // VCADDv4f16 |
| 1425 | UINT64_C(4237297728), // VCADDv4f32 |
| 1426 | UINT64_C(4236249152), // VCADDv8f16 |
| 1427 | UINT64_C(4060089856), // VCEQfd |
| 1428 | UINT64_C(4060089920), // VCEQfq |
| 1429 | UINT64_C(4061138432), // VCEQhd |
| 1430 | UINT64_C(4061138496), // VCEQhq |
| 1431 | UINT64_C(4076865616), // VCEQv16i8 |
| 1432 | UINT64_C(4078962704), // VCEQv2i32 |
| 1433 | UINT64_C(4077914128), // VCEQv4i16 |
| 1434 | UINT64_C(4078962768), // VCEQv4i32 |
| 1435 | UINT64_C(4077914192), // VCEQv8i16 |
| 1436 | UINT64_C(4076865552), // VCEQv8i8 |
| 1437 | UINT64_C(4088463680), // VCEQzv16i8 |
| 1438 | UINT64_C(4088988928), // VCEQzv2f32 |
| 1439 | UINT64_C(4088987904), // VCEQzv2i32 |
| 1440 | UINT64_C(4088726784), // VCEQzv4f16 |
| 1441 | UINT64_C(4088988992), // VCEQzv4f32 |
| 1442 | UINT64_C(4088725760), // VCEQzv4i16 |
| 1443 | UINT64_C(4088987968), // VCEQzv4i32 |
| 1444 | UINT64_C(4088726848), // VCEQzv8f16 |
| 1445 | UINT64_C(4088725824), // VCEQzv8i16 |
| 1446 | UINT64_C(4088463616), // VCEQzv8i8 |
| 1447 | UINT64_C(4076867072), // VCGEfd |
| 1448 | UINT64_C(4076867136), // VCGEfq |
| 1449 | UINT64_C(4077915648), // VCGEhd |
| 1450 | UINT64_C(4077915712), // VCGEhq |
| 1451 | UINT64_C(4060087120), // VCGEsv16i8 |
| 1452 | UINT64_C(4062184208), // VCGEsv2i32 |
| 1453 | UINT64_C(4061135632), // VCGEsv4i16 |
| 1454 | UINT64_C(4062184272), // VCGEsv4i32 |
| 1455 | UINT64_C(4061135696), // VCGEsv8i16 |
| 1456 | UINT64_C(4060087056), // VCGEsv8i8 |
| 1457 | UINT64_C(4076864336), // VCGEuv16i8 |
| 1458 | UINT64_C(4078961424), // VCGEuv2i32 |
| 1459 | UINT64_C(4077912848), // VCGEuv4i16 |
| 1460 | UINT64_C(4078961488), // VCGEuv4i32 |
| 1461 | UINT64_C(4077912912), // VCGEuv8i16 |
| 1462 | UINT64_C(4076864272), // VCGEuv8i8 |
| 1463 | UINT64_C(4088463552), // VCGEzv16i8 |
| 1464 | UINT64_C(4088988800), // VCGEzv2f32 |
| 1465 | UINT64_C(4088987776), // VCGEzv2i32 |
| 1466 | UINT64_C(4088726656), // VCGEzv4f16 |
| 1467 | UINT64_C(4088988864), // VCGEzv4f32 |
| 1468 | UINT64_C(4088725632), // VCGEzv4i16 |
| 1469 | UINT64_C(4088987840), // VCGEzv4i32 |
| 1470 | UINT64_C(4088726720), // VCGEzv8f16 |
| 1471 | UINT64_C(4088725696), // VCGEzv8i16 |
| 1472 | UINT64_C(4088463488), // VCGEzv8i8 |
| 1473 | UINT64_C(4078964224), // VCGTfd |
| 1474 | UINT64_C(4078964288), // VCGTfq |
| 1475 | UINT64_C(4080012800), // VCGThd |
| 1476 | UINT64_C(4080012864), // VCGThq |
| 1477 | UINT64_C(4060087104), // VCGTsv16i8 |
| 1478 | UINT64_C(4062184192), // VCGTsv2i32 |
| 1479 | UINT64_C(4061135616), // VCGTsv4i16 |
| 1480 | UINT64_C(4062184256), // VCGTsv4i32 |
| 1481 | UINT64_C(4061135680), // VCGTsv8i16 |
| 1482 | UINT64_C(4060087040), // VCGTsv8i8 |
| 1483 | UINT64_C(4076864320), // VCGTuv16i8 |
| 1484 | UINT64_C(4078961408), // VCGTuv2i32 |
| 1485 | UINT64_C(4077912832), // VCGTuv4i16 |
| 1486 | UINT64_C(4078961472), // VCGTuv4i32 |
| 1487 | UINT64_C(4077912896), // VCGTuv8i16 |
| 1488 | UINT64_C(4076864256), // VCGTuv8i8 |
| 1489 | UINT64_C(4088463424), // VCGTzv16i8 |
| 1490 | UINT64_C(4088988672), // VCGTzv2f32 |
| 1491 | UINT64_C(4088987648), // VCGTzv2i32 |
| 1492 | UINT64_C(4088726528), // VCGTzv4f16 |
| 1493 | UINT64_C(4088988736), // VCGTzv4f32 |
| 1494 | UINT64_C(4088725504), // VCGTzv4i16 |
| 1495 | UINT64_C(4088987712), // VCGTzv4i32 |
| 1496 | UINT64_C(4088726592), // VCGTzv8f16 |
| 1497 | UINT64_C(4088725568), // VCGTzv8i16 |
| 1498 | UINT64_C(4088463360), // VCGTzv8i8 |
| 1499 | UINT64_C(4088463808), // VCLEzv16i8 |
| 1500 | UINT64_C(4088989056), // VCLEzv2f32 |
| 1501 | UINT64_C(4088988032), // VCLEzv2i32 |
| 1502 | UINT64_C(4088726912), // VCLEzv4f16 |
| 1503 | UINT64_C(4088989120), // VCLEzv4f32 |
| 1504 | UINT64_C(4088725888), // VCLEzv4i16 |
| 1505 | UINT64_C(4088988096), // VCLEzv4i32 |
| 1506 | UINT64_C(4088726976), // VCLEzv8f16 |
| 1507 | UINT64_C(4088725952), // VCLEzv8i16 |
| 1508 | UINT64_C(4088463744), // VCLEzv8i8 |
| 1509 | UINT64_C(4088398912), // VCLSv16i8 |
| 1510 | UINT64_C(4088923136), // VCLSv2i32 |
| 1511 | UINT64_C(4088660992), // VCLSv4i16 |
| 1512 | UINT64_C(4088923200), // VCLSv4i32 |
| 1513 | UINT64_C(4088661056), // VCLSv8i16 |
| 1514 | UINT64_C(4088398848), // VCLSv8i8 |
| 1515 | UINT64_C(4088463936), // VCLTzv16i8 |
| 1516 | UINT64_C(4088989184), // VCLTzv2f32 |
| 1517 | UINT64_C(4088988160), // VCLTzv2i32 |
| 1518 | UINT64_C(4088727040), // VCLTzv4f16 |
| 1519 | UINT64_C(4088989248), // VCLTzv4f32 |
| 1520 | UINT64_C(4088726016), // VCLTzv4i16 |
| 1521 | UINT64_C(4088988224), // VCLTzv4i32 |
| 1522 | UINT64_C(4088727104), // VCLTzv8f16 |
| 1523 | UINT64_C(4088726080), // VCLTzv8i16 |
| 1524 | UINT64_C(4088463872), // VCLTzv8i8 |
| 1525 | UINT64_C(4088399040), // VCLZv16i8 |
| 1526 | UINT64_C(4088923264), // VCLZv2i32 |
| 1527 | UINT64_C(4088661120), // VCLZv4i16 |
| 1528 | UINT64_C(4088923328), // VCLZv4i32 |
| 1529 | UINT64_C(4088661184), // VCLZv8i16 |
| 1530 | UINT64_C(4088398976), // VCLZv8i8 |
| 1531 | UINT64_C(4231006208), // VCMLAv2f32 |
| 1532 | UINT64_C(4269803520), // VCMLAv2f32_indexed |
| 1533 | UINT64_C(4229957632), // VCMLAv4f16 |
| 1534 | UINT64_C(4261414912), // VCMLAv4f16_indexed |
| 1535 | UINT64_C(4231006272), // VCMLAv4f32 |
| 1536 | UINT64_C(4269803584), // VCMLAv4f32_indexed |
| 1537 | UINT64_C(4229957696), // VCMLAv8f16 |
| 1538 | UINT64_C(4261414976), // VCMLAv8f16_indexed |
| 1539 | UINT64_C(246680384), // VCMPD |
| 1540 | UINT64_C(246680512), // VCMPED |
| 1541 | UINT64_C(246680000), // VCMPEH |
| 1542 | UINT64_C(246680256), // VCMPES |
| 1543 | UINT64_C(246746048), // VCMPEZD |
| 1544 | UINT64_C(246745536), // VCMPEZH |
| 1545 | UINT64_C(246745792), // VCMPEZS |
| 1546 | UINT64_C(246679872), // VCMPH |
| 1547 | UINT64_C(246680128), // VCMPS |
| 1548 | UINT64_C(246745920), // VCMPZD |
| 1549 | UINT64_C(246745408), // VCMPZH |
| 1550 | UINT64_C(246745664), // VCMPZS |
| 1551 | UINT64_C(4088399104), // VCNTd |
| 1552 | UINT64_C(4088399168), // VCNTq |
| 1553 | UINT64_C(4089118720), // VCVTANSDf |
| 1554 | UINT64_C(4088856576), // VCVTANSDh |
| 1555 | UINT64_C(4089118784), // VCVTANSQf |
| 1556 | UINT64_C(4088856640), // VCVTANSQh |
| 1557 | UINT64_C(4089118848), // VCVTANUDf |
| 1558 | UINT64_C(4088856704), // VCVTANUDh |
| 1559 | UINT64_C(4089118912), // VCVTANUQf |
| 1560 | UINT64_C(4088856768), // VCVTANUQh |
| 1561 | UINT64_C(4273736640), // VCVTASD |
| 1562 | UINT64_C(4273736128), // VCVTASH |
| 1563 | UINT64_C(4273736384), // VCVTASS |
| 1564 | UINT64_C(4273736512), // VCVTAUD |
| 1565 | UINT64_C(4273736000), // VCVTAUH |
| 1566 | UINT64_C(4273736256), // VCVTAUS |
| 1567 | UINT64_C(246614848), // VCVTBDH |
| 1568 | UINT64_C(246549312), // VCVTBHD |
| 1569 | UINT64_C(246549056), // VCVTBHS |
| 1570 | UINT64_C(246614592), // VCVTBSH |
| 1571 | UINT64_C(246876864), // VCVTDS |
| 1572 | UINT64_C(4089119488), // VCVTMNSDf |
| 1573 | UINT64_C(4088857344), // VCVTMNSDh |
| 1574 | UINT64_C(4089119552), // VCVTMNSQf |
| 1575 | UINT64_C(4088857408), // VCVTMNSQh |
| 1576 | UINT64_C(4089119616), // VCVTMNUDf |
| 1577 | UINT64_C(4088857472), // VCVTMNUDh |
| 1578 | UINT64_C(4089119680), // VCVTMNUQf |
| 1579 | UINT64_C(4088857536), // VCVTMNUQh |
| 1580 | UINT64_C(4273933248), // VCVTMSD |
| 1581 | UINT64_C(4273932736), // VCVTMSH |
| 1582 | UINT64_C(4273932992), // VCVTMSS |
| 1583 | UINT64_C(4273933120), // VCVTMUD |
| 1584 | UINT64_C(4273932608), // VCVTMUH |
| 1585 | UINT64_C(4273932864), // VCVTMUS |
| 1586 | UINT64_C(4089118976), // VCVTNNSDf |
| 1587 | UINT64_C(4088856832), // VCVTNNSDh |
| 1588 | UINT64_C(4089119040), // VCVTNNSQf |
| 1589 | UINT64_C(4088856896), // VCVTNNSQh |
| 1590 | UINT64_C(4089119104), // VCVTNNUDf |
| 1591 | UINT64_C(4088856960), // VCVTNNUDh |
| 1592 | UINT64_C(4089119168), // VCVTNNUQf |
| 1593 | UINT64_C(4088857024), // VCVTNNUQh |
| 1594 | UINT64_C(4273802176), // VCVTNSD |
| 1595 | UINT64_C(4273801664), // VCVTNSH |
| 1596 | UINT64_C(4273801920), // VCVTNSS |
| 1597 | UINT64_C(4273802048), // VCVTNUD |
| 1598 | UINT64_C(4273801536), // VCVTNUH |
| 1599 | UINT64_C(4273801792), // VCVTNUS |
| 1600 | UINT64_C(4089119232), // VCVTPNSDf |
| 1601 | UINT64_C(4088857088), // VCVTPNSDh |
| 1602 | UINT64_C(4089119296), // VCVTPNSQf |
| 1603 | UINT64_C(4088857152), // VCVTPNSQh |
| 1604 | UINT64_C(4089119360), // VCVTPNUDf |
| 1605 | UINT64_C(4088857216), // VCVTPNUDh |
| 1606 | UINT64_C(4089119424), // VCVTPNUQf |
| 1607 | UINT64_C(4088857280), // VCVTPNUQh |
| 1608 | UINT64_C(4273867712), // VCVTPSD |
| 1609 | UINT64_C(4273867200), // VCVTPSH |
| 1610 | UINT64_C(4273867456), // VCVTPSS |
| 1611 | UINT64_C(4273867584), // VCVTPUD |
| 1612 | UINT64_C(4273867072), // VCVTPUH |
| 1613 | UINT64_C(4273867328), // VCVTPUS |
| 1614 | UINT64_C(246877120), // VCVTSD |
| 1615 | UINT64_C(246614976), // VCVTTDH |
| 1616 | UINT64_C(246549440), // VCVTTHD |
| 1617 | UINT64_C(246549184), // VCVTTHS |
| 1618 | UINT64_C(246614720), // VCVTTSH |
| 1619 | UINT64_C(4088792576), // VCVTf2h |
| 1620 | UINT64_C(4089120512), // VCVTf2sd |
| 1621 | UINT64_C(4089120576), // VCVTf2sq |
| 1622 | UINT64_C(4089120640), // VCVTf2ud |
| 1623 | UINT64_C(4089120704), // VCVTf2uq |
| 1624 | UINT64_C(4068478736), // VCVTf2xsd |
| 1625 | UINT64_C(4068478800), // VCVTf2xsq |
| 1626 | UINT64_C(4085255952), // VCVTf2xud |
| 1627 | UINT64_C(4085256016), // VCVTf2xuq |
| 1628 | UINT64_C(4088792832), // VCVTh2f |
| 1629 | UINT64_C(4088858368), // VCVTh2sd |
| 1630 | UINT64_C(4088858432), // VCVTh2sq |
| 1631 | UINT64_C(4088858496), // VCVTh2ud |
| 1632 | UINT64_C(4088858560), // VCVTh2uq |
| 1633 | UINT64_C(4068478224), // VCVTh2xsd |
| 1634 | UINT64_C(4068478288), // VCVTh2xsq |
| 1635 | UINT64_C(4085255440), // VCVTh2xud |
| 1636 | UINT64_C(4085255504), // VCVTh2xuq |
| 1637 | UINT64_C(4089120256), // VCVTs2fd |
| 1638 | UINT64_C(4089120320), // VCVTs2fq |
| 1639 | UINT64_C(4088858112), // VCVTs2hd |
| 1640 | UINT64_C(4088858176), // VCVTs2hq |
| 1641 | UINT64_C(4089120384), // VCVTu2fd |
| 1642 | UINT64_C(4089120448), // VCVTu2fq |
| 1643 | UINT64_C(4088858240), // VCVTu2hd |
| 1644 | UINT64_C(4088858304), // VCVTu2hq |
| 1645 | UINT64_C(4068478480), // VCVTxs2fd |
| 1646 | UINT64_C(4068478544), // VCVTxs2fq |
| 1647 | UINT64_C(4068477968), // VCVTxs2hd |
| 1648 | UINT64_C(4068478032), // VCVTxs2hq |
| 1649 | UINT64_C(4085255696), // VCVTxu2fd |
| 1650 | UINT64_C(4085255760), // VCVTxu2fq |
| 1651 | UINT64_C(4085255184), // VCVTxu2hd |
| 1652 | UINT64_C(4085255248), // VCVTxu2hq |
| 1653 | UINT64_C(243272448), // VDIVD |
| 1654 | UINT64_C(243271936), // VDIVH |
| 1655 | UINT64_C(243272192), // VDIVS |
| 1656 | UINT64_C(243272496), // VDUP16d |
| 1657 | UINT64_C(245369648), // VDUP16q |
| 1658 | UINT64_C(243272464), // VDUP32d |
| 1659 | UINT64_C(245369616), // VDUP32q |
| 1660 | UINT64_C(247466768), // VDUP8d |
| 1661 | UINT64_C(249563920), // VDUP8q |
| 1662 | UINT64_C(4088531968), // VDUPLN16d |
| 1663 | UINT64_C(4088532032), // VDUPLN16q |
| 1664 | UINT64_C(4088663040), // VDUPLN32d |
| 1665 | UINT64_C(4088663104), // VDUPLN32q |
| 1666 | UINT64_C(4088466432), // VDUPLN8d |
| 1667 | UINT64_C(4088466496), // VDUPLN8q |
| 1668 | UINT64_C(4076863760), // VEORd |
| 1669 | UINT64_C(4076863824), // VEORq |
| 1670 | UINT64_C(4071620608), // VEXTd16 |
| 1671 | UINT64_C(4071620608), // VEXTd32 |
| 1672 | UINT64_C(4071620608), // VEXTd8 |
| 1673 | UINT64_C(4071620672), // VEXTq16 |
| 1674 | UINT64_C(4071620672), // VEXTq32 |
| 1675 | UINT64_C(4071620672), // VEXTq64 |
| 1676 | UINT64_C(4071620672), // VEXTq8 |
| 1677 | UINT64_C(245369600), // VFMAD |
| 1678 | UINT64_C(245369088), // VFMAH |
| 1679 | UINT64_C(4229957648), // VFMALD |
| 1680 | UINT64_C(4261414928), // VFMALDI |
| 1681 | UINT64_C(4229957712), // VFMALQ |
| 1682 | UINT64_C(4261414992), // VFMALQI |
| 1683 | UINT64_C(245369344), // VFMAS |
| 1684 | UINT64_C(4060089360), // VFMAfd |
| 1685 | UINT64_C(4060089424), // VFMAfq |
| 1686 | UINT64_C(4061137936), // VFMAhd |
| 1687 | UINT64_C(4061138000), // VFMAhq |
| 1688 | UINT64_C(245369664), // VFMSD |
| 1689 | UINT64_C(245369152), // VFMSH |
| 1690 | UINT64_C(4238346256), // VFMSLD |
| 1691 | UINT64_C(4262463504), // VFMSLDI |
| 1692 | UINT64_C(4238346320), // VFMSLQ |
| 1693 | UINT64_C(4262463568), // VFMSLQI |
| 1694 | UINT64_C(245369408), // VFMSS |
| 1695 | UINT64_C(4062186512), // VFMSfd |
| 1696 | UINT64_C(4062186576), // VFMSfq |
| 1697 | UINT64_C(4063235088), // VFMShd |
| 1698 | UINT64_C(4063235152), // VFMShq |
| 1699 | UINT64_C(244321088), // VFNMAD |
| 1700 | UINT64_C(244320576), // VFNMAH |
| 1701 | UINT64_C(244320832), // VFNMAS |
| 1702 | UINT64_C(244321024), // VFNMSD |
| 1703 | UINT64_C(244320512), // VFNMSH |
| 1704 | UINT64_C(244320768), // VFNMSS |
| 1705 | UINT64_C(4269804288), // VFP_VMAXNMD |
| 1706 | UINT64_C(4269803776), // VFP_VMAXNMH |
| 1707 | UINT64_C(4269804032), // VFP_VMAXNMS |
| 1708 | UINT64_C(4269804352), // VFP_VMINNMD |
| 1709 | UINT64_C(4269803840), // VFP_VMINNMH |
| 1710 | UINT64_C(4269804096), // VFP_VMINNMS |
| 1711 | UINT64_C(235932432), // VGETLNi32 |
| 1712 | UINT64_C(235932464), // VGETLNs16 |
| 1713 | UINT64_C(240126736), // VGETLNs8 |
| 1714 | UINT64_C(244321072), // VGETLNu16 |
| 1715 | UINT64_C(248515344), // VGETLNu8 |
| 1716 | UINT64_C(4060086336), // VHADDsv16i8 |
| 1717 | UINT64_C(4062183424), // VHADDsv2i32 |
| 1718 | UINT64_C(4061134848), // VHADDsv4i16 |
| 1719 | UINT64_C(4062183488), // VHADDsv4i32 |
| 1720 | UINT64_C(4061134912), // VHADDsv8i16 |
| 1721 | UINT64_C(4060086272), // VHADDsv8i8 |
| 1722 | UINT64_C(4076863552), // VHADDuv16i8 |
| 1723 | UINT64_C(4078960640), // VHADDuv2i32 |
| 1724 | UINT64_C(4077912064), // VHADDuv4i16 |
| 1725 | UINT64_C(4078960704), // VHADDuv4i32 |
| 1726 | UINT64_C(4077912128), // VHADDuv8i16 |
| 1727 | UINT64_C(4076863488), // VHADDuv8i8 |
| 1728 | UINT64_C(4060086848), // VHSUBsv16i8 |
| 1729 | UINT64_C(4062183936), // VHSUBsv2i32 |
| 1730 | UINT64_C(4061135360), // VHSUBsv4i16 |
| 1731 | UINT64_C(4062184000), // VHSUBsv4i32 |
| 1732 | UINT64_C(4061135424), // VHSUBsv8i16 |
| 1733 | UINT64_C(4060086784), // VHSUBsv8i8 |
| 1734 | UINT64_C(4076864064), // VHSUBuv16i8 |
| 1735 | UINT64_C(4078961152), // VHSUBuv2i32 |
| 1736 | UINT64_C(4077912576), // VHSUBuv4i16 |
| 1737 | UINT64_C(4078961216), // VHSUBuv4i32 |
| 1738 | UINT64_C(4077912640), // VHSUBuv8i16 |
| 1739 | UINT64_C(4076864000), // VHSUBuv8i8 |
| 1740 | UINT64_C(4272949952), // VINSH |
| 1741 | UINT64_C(247008192), // VJCVT |
| 1742 | UINT64_C(4104129615), // VLD1DUPd16 |
| 1743 | UINT64_C(4104129613), // VLD1DUPd16wb_fixed |
| 1744 | UINT64_C(4104129600), // VLD1DUPd16wb_register |
| 1745 | UINT64_C(4104129679), // VLD1DUPd32 |
| 1746 | UINT64_C(4104129677), // VLD1DUPd32wb_fixed |
| 1747 | UINT64_C(4104129664), // VLD1DUPd32wb_register |
| 1748 | UINT64_C(4104129551), // VLD1DUPd8 |
| 1749 | UINT64_C(4104129549), // VLD1DUPd8wb_fixed |
| 1750 | UINT64_C(4104129536), // VLD1DUPd8wb_register |
| 1751 | UINT64_C(4104129647), // VLD1DUPq16 |
| 1752 | UINT64_C(4104129645), // VLD1DUPq16wb_fixed |
| 1753 | UINT64_C(4104129632), // VLD1DUPq16wb_register |
| 1754 | UINT64_C(4104129711), // VLD1DUPq32 |
| 1755 | UINT64_C(4104129709), // VLD1DUPq32wb_fixed |
| 1756 | UINT64_C(4104129696), // VLD1DUPq32wb_register |
| 1757 | UINT64_C(4104129583), // VLD1DUPq8 |
| 1758 | UINT64_C(4104129581), // VLD1DUPq8wb_fixed |
| 1759 | UINT64_C(4104129568), // VLD1DUPq8wb_register |
| 1760 | UINT64_C(4104127503), // VLD1LNd16 |
| 1761 | UINT64_C(4104127488), // VLD1LNd16_UPD |
| 1762 | UINT64_C(4104128527), // VLD1LNd32 |
| 1763 | UINT64_C(4104128512), // VLD1LNd32_UPD |
| 1764 | UINT64_C(4104126479), // VLD1LNd8 |
| 1765 | UINT64_C(4104126464), // VLD1LNd8_UPD |
| 1766 | UINT64_C(0), // VLD1LNq16Pseudo |
| 1767 | UINT64_C(0), // VLD1LNq16Pseudo_UPD |
| 1768 | UINT64_C(0), // VLD1LNq32Pseudo |
| 1769 | UINT64_C(0), // VLD1LNq32Pseudo_UPD |
| 1770 | UINT64_C(0), // VLD1LNq8Pseudo |
| 1771 | UINT64_C(0), // VLD1LNq8Pseudo_UPD |
| 1772 | UINT64_C(4095739727), // VLD1d16 |
| 1773 | UINT64_C(4095738447), // VLD1d16Q |
| 1774 | UINT64_C(0), // VLD1d16QPseudo |
| 1775 | UINT64_C(0), // VLD1d16QPseudoWB_fixed |
| 1776 | UINT64_C(0), // VLD1d16QPseudoWB_register |
| 1777 | UINT64_C(4095738445), // VLD1d16Qwb_fixed |
| 1778 | UINT64_C(4095738432), // VLD1d16Qwb_register |
| 1779 | UINT64_C(4095739471), // VLD1d16T |
| 1780 | UINT64_C(0), // VLD1d16TPseudo |
| 1781 | UINT64_C(0), // VLD1d16TPseudoWB_fixed |
| 1782 | UINT64_C(0), // VLD1d16TPseudoWB_register |
| 1783 | UINT64_C(4095739469), // VLD1d16Twb_fixed |
| 1784 | UINT64_C(4095739456), // VLD1d16Twb_register |
| 1785 | UINT64_C(4095739725), // VLD1d16wb_fixed |
| 1786 | UINT64_C(4095739712), // VLD1d16wb_register |
| 1787 | UINT64_C(4095739791), // VLD1d32 |
| 1788 | UINT64_C(4095738511), // VLD1d32Q |
| 1789 | UINT64_C(0), // VLD1d32QPseudo |
| 1790 | UINT64_C(0), // VLD1d32QPseudoWB_fixed |
| 1791 | UINT64_C(0), // VLD1d32QPseudoWB_register |
| 1792 | UINT64_C(4095738509), // VLD1d32Qwb_fixed |
| 1793 | UINT64_C(4095738496), // VLD1d32Qwb_register |
| 1794 | UINT64_C(4095739535), // VLD1d32T |
| 1795 | UINT64_C(0), // VLD1d32TPseudo |
| 1796 | UINT64_C(0), // VLD1d32TPseudoWB_fixed |
| 1797 | UINT64_C(0), // VLD1d32TPseudoWB_register |
| 1798 | UINT64_C(4095739533), // VLD1d32Twb_fixed |
| 1799 | UINT64_C(4095739520), // VLD1d32Twb_register |
| 1800 | UINT64_C(4095739789), // VLD1d32wb_fixed |
| 1801 | UINT64_C(4095739776), // VLD1d32wb_register |
| 1802 | UINT64_C(4095739855), // VLD1d64 |
| 1803 | UINT64_C(4095738575), // VLD1d64Q |
| 1804 | UINT64_C(0), // VLD1d64QPseudo |
| 1805 | UINT64_C(0), // VLD1d64QPseudoWB_fixed |
| 1806 | UINT64_C(0), // VLD1d64QPseudoWB_register |
| 1807 | UINT64_C(4095738573), // VLD1d64Qwb_fixed |
| 1808 | UINT64_C(4095738560), // VLD1d64Qwb_register |
| 1809 | UINT64_C(4095739599), // VLD1d64T |
| 1810 | UINT64_C(0), // VLD1d64TPseudo |
| 1811 | UINT64_C(0), // VLD1d64TPseudoWB_fixed |
| 1812 | UINT64_C(0), // VLD1d64TPseudoWB_register |
| 1813 | UINT64_C(4095739597), // VLD1d64Twb_fixed |
| 1814 | UINT64_C(4095739584), // VLD1d64Twb_register |
| 1815 | UINT64_C(4095739853), // VLD1d64wb_fixed |
| 1816 | UINT64_C(4095739840), // VLD1d64wb_register |
| 1817 | UINT64_C(4095739663), // VLD1d8 |
| 1818 | UINT64_C(4095738383), // VLD1d8Q |
| 1819 | UINT64_C(0), // VLD1d8QPseudo |
| 1820 | UINT64_C(0), // VLD1d8QPseudoWB_fixed |
| 1821 | UINT64_C(0), // VLD1d8QPseudoWB_register |
| 1822 | UINT64_C(4095738381), // VLD1d8Qwb_fixed |
| 1823 | UINT64_C(4095738368), // VLD1d8Qwb_register |
| 1824 | UINT64_C(4095739407), // VLD1d8T |
| 1825 | UINT64_C(0), // VLD1d8TPseudo |
| 1826 | UINT64_C(0), // VLD1d8TPseudoWB_fixed |
| 1827 | UINT64_C(0), // VLD1d8TPseudoWB_register |
| 1828 | UINT64_C(4095739405), // VLD1d8Twb_fixed |
| 1829 | UINT64_C(4095739392), // VLD1d8Twb_register |
| 1830 | UINT64_C(4095739661), // VLD1d8wb_fixed |
| 1831 | UINT64_C(4095739648), // VLD1d8wb_register |
| 1832 | UINT64_C(4095740495), // VLD1q16 |
| 1833 | UINT64_C(0), // VLD1q16HighQPseudo |
| 1834 | UINT64_C(0), // VLD1q16HighQPseudo_UPD |
| 1835 | UINT64_C(0), // VLD1q16HighTPseudo |
| 1836 | UINT64_C(0), // VLD1q16HighTPseudo_UPD |
| 1837 | UINT64_C(0), // VLD1q16LowQPseudo_UPD |
| 1838 | UINT64_C(0), // VLD1q16LowTPseudo_UPD |
| 1839 | UINT64_C(4095740493), // VLD1q16wb_fixed |
| 1840 | UINT64_C(4095740480), // VLD1q16wb_register |
| 1841 | UINT64_C(4095740559), // VLD1q32 |
| 1842 | UINT64_C(0), // VLD1q32HighQPseudo |
| 1843 | UINT64_C(0), // VLD1q32HighQPseudo_UPD |
| 1844 | UINT64_C(0), // VLD1q32HighTPseudo |
| 1845 | UINT64_C(0), // VLD1q32HighTPseudo_UPD |
| 1846 | UINT64_C(0), // VLD1q32LowQPseudo_UPD |
| 1847 | UINT64_C(0), // VLD1q32LowTPseudo_UPD |
| 1848 | UINT64_C(4095740557), // VLD1q32wb_fixed |
| 1849 | UINT64_C(4095740544), // VLD1q32wb_register |
| 1850 | UINT64_C(4095740623), // VLD1q64 |
| 1851 | UINT64_C(0), // VLD1q64HighQPseudo |
| 1852 | UINT64_C(0), // VLD1q64HighQPseudo_UPD |
| 1853 | UINT64_C(0), // VLD1q64HighTPseudo |
| 1854 | UINT64_C(0), // VLD1q64HighTPseudo_UPD |
| 1855 | UINT64_C(0), // VLD1q64LowQPseudo_UPD |
| 1856 | UINT64_C(0), // VLD1q64LowTPseudo_UPD |
| 1857 | UINT64_C(4095740621), // VLD1q64wb_fixed |
| 1858 | UINT64_C(4095740608), // VLD1q64wb_register |
| 1859 | UINT64_C(4095740431), // VLD1q8 |
| 1860 | UINT64_C(0), // VLD1q8HighQPseudo |
| 1861 | UINT64_C(0), // VLD1q8HighQPseudo_UPD |
| 1862 | UINT64_C(0), // VLD1q8HighTPseudo |
| 1863 | UINT64_C(0), // VLD1q8HighTPseudo_UPD |
| 1864 | UINT64_C(0), // VLD1q8LowQPseudo_UPD |
| 1865 | UINT64_C(0), // VLD1q8LowTPseudo_UPD |
| 1866 | UINT64_C(4095740429), // VLD1q8wb_fixed |
| 1867 | UINT64_C(4095740416), // VLD1q8wb_register |
| 1868 | UINT64_C(4104129871), // VLD2DUPd16 |
| 1869 | UINT64_C(4104129869), // VLD2DUPd16wb_fixed |
| 1870 | UINT64_C(4104129856), // VLD2DUPd16wb_register |
| 1871 | UINT64_C(4104129903), // VLD2DUPd16x2 |
| 1872 | UINT64_C(4104129901), // VLD2DUPd16x2wb_fixed |
| 1873 | UINT64_C(4104129888), // VLD2DUPd16x2wb_register |
| 1874 | UINT64_C(4104129935), // VLD2DUPd32 |
| 1875 | UINT64_C(4104129933), // VLD2DUPd32wb_fixed |
| 1876 | UINT64_C(4104129920), // VLD2DUPd32wb_register |
| 1877 | UINT64_C(4104129967), // VLD2DUPd32x2 |
| 1878 | UINT64_C(4104129965), // VLD2DUPd32x2wb_fixed |
| 1879 | UINT64_C(4104129952), // VLD2DUPd32x2wb_register |
| 1880 | UINT64_C(4104129807), // VLD2DUPd8 |
| 1881 | UINT64_C(4104129805), // VLD2DUPd8wb_fixed |
| 1882 | UINT64_C(4104129792), // VLD2DUPd8wb_register |
| 1883 | UINT64_C(4104129839), // VLD2DUPd8x2 |
| 1884 | UINT64_C(4104129837), // VLD2DUPd8x2wb_fixed |
| 1885 | UINT64_C(4104129824), // VLD2DUPd8x2wb_register |
| 1886 | UINT64_C(0), // VLD2DUPq16EvenPseudo |
| 1887 | UINT64_C(0), // VLD2DUPq16OddPseudo |
| 1888 | UINT64_C(0), // VLD2DUPq16OddPseudoWB_fixed |
| 1889 | UINT64_C(0), // VLD2DUPq16OddPseudoWB_register |
| 1890 | UINT64_C(0), // VLD2DUPq32EvenPseudo |
| 1891 | UINT64_C(0), // VLD2DUPq32OddPseudo |
| 1892 | UINT64_C(0), // VLD2DUPq32OddPseudoWB_fixed |
| 1893 | UINT64_C(0), // VLD2DUPq32OddPseudoWB_register |
| 1894 | UINT64_C(0), // VLD2DUPq8EvenPseudo |
| 1895 | UINT64_C(0), // VLD2DUPq8OddPseudo |
| 1896 | UINT64_C(0), // VLD2DUPq8OddPseudoWB_fixed |
| 1897 | UINT64_C(0), // VLD2DUPq8OddPseudoWB_register |
| 1898 | UINT64_C(4104127759), // VLD2LNd16 |
| 1899 | UINT64_C(0), // VLD2LNd16Pseudo |
| 1900 | UINT64_C(0), // VLD2LNd16Pseudo_UPD |
| 1901 | UINT64_C(4104127744), // VLD2LNd16_UPD |
| 1902 | UINT64_C(4104128783), // VLD2LNd32 |
| 1903 | UINT64_C(0), // VLD2LNd32Pseudo |
| 1904 | UINT64_C(0), // VLD2LNd32Pseudo_UPD |
| 1905 | UINT64_C(4104128768), // VLD2LNd32_UPD |
| 1906 | UINT64_C(4104126735), // VLD2LNd8 |
| 1907 | UINT64_C(0), // VLD2LNd8Pseudo |
| 1908 | UINT64_C(0), // VLD2LNd8Pseudo_UPD |
| 1909 | UINT64_C(4104126720), // VLD2LNd8_UPD |
| 1910 | UINT64_C(4104127791), // VLD2LNq16 |
| 1911 | UINT64_C(0), // VLD2LNq16Pseudo |
| 1912 | UINT64_C(0), // VLD2LNq16Pseudo_UPD |
| 1913 | UINT64_C(4104127776), // VLD2LNq16_UPD |
| 1914 | UINT64_C(4104128847), // VLD2LNq32 |
| 1915 | UINT64_C(0), // VLD2LNq32Pseudo |
| 1916 | UINT64_C(0), // VLD2LNq32Pseudo_UPD |
| 1917 | UINT64_C(4104128832), // VLD2LNq32_UPD |
| 1918 | UINT64_C(4095740239), // VLD2b16 |
| 1919 | UINT64_C(4095740237), // VLD2b16wb_fixed |
| 1920 | UINT64_C(4095740224), // VLD2b16wb_register |
| 1921 | UINT64_C(4095740303), // VLD2b32 |
| 1922 | UINT64_C(4095740301), // VLD2b32wb_fixed |
| 1923 | UINT64_C(4095740288), // VLD2b32wb_register |
| 1924 | UINT64_C(4095740175), // VLD2b8 |
| 1925 | UINT64_C(4095740173), // VLD2b8wb_fixed |
| 1926 | UINT64_C(4095740160), // VLD2b8wb_register |
| 1927 | UINT64_C(4095739983), // VLD2d16 |
| 1928 | UINT64_C(4095739981), // VLD2d16wb_fixed |
| 1929 | UINT64_C(4095739968), // VLD2d16wb_register |
| 1930 | UINT64_C(4095740047), // VLD2d32 |
| 1931 | UINT64_C(4095740045), // VLD2d32wb_fixed |
| 1932 | UINT64_C(4095740032), // VLD2d32wb_register |
| 1933 | UINT64_C(4095739919), // VLD2d8 |
| 1934 | UINT64_C(4095739917), // VLD2d8wb_fixed |
| 1935 | UINT64_C(4095739904), // VLD2d8wb_register |
| 1936 | UINT64_C(4095738703), // VLD2q16 |
| 1937 | UINT64_C(0), // VLD2q16Pseudo |
| 1938 | UINT64_C(0), // VLD2q16PseudoWB_fixed |
| 1939 | UINT64_C(0), // VLD2q16PseudoWB_register |
| 1940 | UINT64_C(4095738701), // VLD2q16wb_fixed |
| 1941 | UINT64_C(4095738688), // VLD2q16wb_register |
| 1942 | UINT64_C(4095738767), // VLD2q32 |
| 1943 | UINT64_C(0), // VLD2q32Pseudo |
| 1944 | UINT64_C(0), // VLD2q32PseudoWB_fixed |
| 1945 | UINT64_C(0), // VLD2q32PseudoWB_register |
| 1946 | UINT64_C(4095738765), // VLD2q32wb_fixed |
| 1947 | UINT64_C(4095738752), // VLD2q32wb_register |
| 1948 | UINT64_C(4095738639), // VLD2q8 |
| 1949 | UINT64_C(0), // VLD2q8Pseudo |
| 1950 | UINT64_C(0), // VLD2q8PseudoWB_fixed |
| 1951 | UINT64_C(0), // VLD2q8PseudoWB_register |
| 1952 | UINT64_C(4095738637), // VLD2q8wb_fixed |
| 1953 | UINT64_C(4095738624), // VLD2q8wb_register |
| 1954 | UINT64_C(4104130127), // VLD3DUPd16 |
| 1955 | UINT64_C(0), // VLD3DUPd16Pseudo |
| 1956 | UINT64_C(0), // VLD3DUPd16Pseudo_UPD |
| 1957 | UINT64_C(4104130112), // VLD3DUPd16_UPD |
| 1958 | UINT64_C(4104130191), // VLD3DUPd32 |
| 1959 | UINT64_C(0), // VLD3DUPd32Pseudo |
| 1960 | UINT64_C(0), // VLD3DUPd32Pseudo_UPD |
| 1961 | UINT64_C(4104130176), // VLD3DUPd32_UPD |
| 1962 | UINT64_C(4104130063), // VLD3DUPd8 |
| 1963 | UINT64_C(0), // VLD3DUPd8Pseudo |
| 1964 | UINT64_C(0), // VLD3DUPd8Pseudo_UPD |
| 1965 | UINT64_C(4104130048), // VLD3DUPd8_UPD |
| 1966 | UINT64_C(4104130159), // VLD3DUPq16 |
| 1967 | UINT64_C(0), // VLD3DUPq16EvenPseudo |
| 1968 | UINT64_C(0), // VLD3DUPq16OddPseudo |
| 1969 | UINT64_C(0), // VLD3DUPq16OddPseudo_UPD |
| 1970 | UINT64_C(4104130144), // VLD3DUPq16_UPD |
| 1971 | UINT64_C(4104130223), // VLD3DUPq32 |
| 1972 | UINT64_C(0), // VLD3DUPq32EvenPseudo |
| 1973 | UINT64_C(0), // VLD3DUPq32OddPseudo |
| 1974 | UINT64_C(0), // VLD3DUPq32OddPseudo_UPD |
| 1975 | UINT64_C(4104130208), // VLD3DUPq32_UPD |
| 1976 | UINT64_C(4104130095), // VLD3DUPq8 |
| 1977 | UINT64_C(0), // VLD3DUPq8EvenPseudo |
| 1978 | UINT64_C(0), // VLD3DUPq8OddPseudo |
| 1979 | UINT64_C(0), // VLD3DUPq8OddPseudo_UPD |
| 1980 | UINT64_C(4104130080), // VLD3DUPq8_UPD |
| 1981 | UINT64_C(4104128015), // VLD3LNd16 |
| 1982 | UINT64_C(0), // VLD3LNd16Pseudo |
| 1983 | UINT64_C(0), // VLD3LNd16Pseudo_UPD |
| 1984 | UINT64_C(4104128000), // VLD3LNd16_UPD |
| 1985 | UINT64_C(4104129039), // VLD3LNd32 |
| 1986 | UINT64_C(0), // VLD3LNd32Pseudo |
| 1987 | UINT64_C(0), // VLD3LNd32Pseudo_UPD |
| 1988 | UINT64_C(4104129024), // VLD3LNd32_UPD |
| 1989 | UINT64_C(4104126991), // VLD3LNd8 |
| 1990 | UINT64_C(0), // VLD3LNd8Pseudo |
| 1991 | UINT64_C(0), // VLD3LNd8Pseudo_UPD |
| 1992 | UINT64_C(4104126976), // VLD3LNd8_UPD |
| 1993 | UINT64_C(4104128047), // VLD3LNq16 |
| 1994 | UINT64_C(0), // VLD3LNq16Pseudo |
| 1995 | UINT64_C(0), // VLD3LNq16Pseudo_UPD |
| 1996 | UINT64_C(4104128032), // VLD3LNq16_UPD |
| 1997 | UINT64_C(4104129103), // VLD3LNq32 |
| 1998 | UINT64_C(0), // VLD3LNq32Pseudo |
| 1999 | UINT64_C(0), // VLD3LNq32Pseudo_UPD |
| 2000 | UINT64_C(4104129088), // VLD3LNq32_UPD |
| 2001 | UINT64_C(4095738959), // VLD3d16 |
| 2002 | UINT64_C(0), // VLD3d16Pseudo |
| 2003 | UINT64_C(0), // VLD3d16Pseudo_UPD |
| 2004 | UINT64_C(4095738944), // VLD3d16_UPD |
| 2005 | UINT64_C(4095739023), // VLD3d32 |
| 2006 | UINT64_C(0), // VLD3d32Pseudo |
| 2007 | UINT64_C(0), // VLD3d32Pseudo_UPD |
| 2008 | UINT64_C(4095739008), // VLD3d32_UPD |
| 2009 | UINT64_C(4095738895), // VLD3d8 |
| 2010 | UINT64_C(0), // VLD3d8Pseudo |
| 2011 | UINT64_C(0), // VLD3d8Pseudo_UPD |
| 2012 | UINT64_C(4095738880), // VLD3d8_UPD |
| 2013 | UINT64_C(4095739215), // VLD3q16 |
| 2014 | UINT64_C(0), // VLD3q16Pseudo_UPD |
| 2015 | UINT64_C(4095739200), // VLD3q16_UPD |
| 2016 | UINT64_C(0), // VLD3q16oddPseudo |
| 2017 | UINT64_C(0), // VLD3q16oddPseudo_UPD |
| 2018 | UINT64_C(4095739279), // VLD3q32 |
| 2019 | UINT64_C(0), // VLD3q32Pseudo_UPD |
| 2020 | UINT64_C(4095739264), // VLD3q32_UPD |
| 2021 | UINT64_C(0), // VLD3q32oddPseudo |
| 2022 | UINT64_C(0), // VLD3q32oddPseudo_UPD |
| 2023 | UINT64_C(4095739151), // VLD3q8 |
| 2024 | UINT64_C(0), // VLD3q8Pseudo_UPD |
| 2025 | UINT64_C(4095739136), // VLD3q8_UPD |
| 2026 | UINT64_C(0), // VLD3q8oddPseudo |
| 2027 | UINT64_C(0), // VLD3q8oddPseudo_UPD |
| 2028 | UINT64_C(4104130383), // VLD4DUPd16 |
| 2029 | UINT64_C(0), // VLD4DUPd16Pseudo |
| 2030 | UINT64_C(0), // VLD4DUPd16Pseudo_UPD |
| 2031 | UINT64_C(4104130368), // VLD4DUPd16_UPD |
| 2032 | UINT64_C(4104130447), // VLD4DUPd32 |
| 2033 | UINT64_C(0), // VLD4DUPd32Pseudo |
| 2034 | UINT64_C(0), // VLD4DUPd32Pseudo_UPD |
| 2035 | UINT64_C(4104130432), // VLD4DUPd32_UPD |
| 2036 | UINT64_C(4104130319), // VLD4DUPd8 |
| 2037 | UINT64_C(0), // VLD4DUPd8Pseudo |
| 2038 | UINT64_C(0), // VLD4DUPd8Pseudo_UPD |
| 2039 | UINT64_C(4104130304), // VLD4DUPd8_UPD |
| 2040 | UINT64_C(4104130415), // VLD4DUPq16 |
| 2041 | UINT64_C(0), // VLD4DUPq16EvenPseudo |
| 2042 | UINT64_C(0), // VLD4DUPq16OddPseudo |
| 2043 | UINT64_C(0), // VLD4DUPq16OddPseudo_UPD |
| 2044 | UINT64_C(4104130400), // VLD4DUPq16_UPD |
| 2045 | UINT64_C(4104130479), // VLD4DUPq32 |
| 2046 | UINT64_C(0), // VLD4DUPq32EvenPseudo |
| 2047 | UINT64_C(0), // VLD4DUPq32OddPseudo |
| 2048 | UINT64_C(0), // VLD4DUPq32OddPseudo_UPD |
| 2049 | UINT64_C(4104130464), // VLD4DUPq32_UPD |
| 2050 | UINT64_C(4104130351), // VLD4DUPq8 |
| 2051 | UINT64_C(0), // VLD4DUPq8EvenPseudo |
| 2052 | UINT64_C(0), // VLD4DUPq8OddPseudo |
| 2053 | UINT64_C(0), // VLD4DUPq8OddPseudo_UPD |
| 2054 | UINT64_C(4104130336), // VLD4DUPq8_UPD |
| 2055 | UINT64_C(4104128271), // VLD4LNd16 |
| 2056 | UINT64_C(0), // VLD4LNd16Pseudo |
| 2057 | UINT64_C(0), // VLD4LNd16Pseudo_UPD |
| 2058 | UINT64_C(4104128256), // VLD4LNd16_UPD |
| 2059 | UINT64_C(4104129295), // VLD4LNd32 |
| 2060 | UINT64_C(0), // VLD4LNd32Pseudo |
| 2061 | UINT64_C(0), // VLD4LNd32Pseudo_UPD |
| 2062 | UINT64_C(4104129280), // VLD4LNd32_UPD |
| 2063 | UINT64_C(4104127247), // VLD4LNd8 |
| 2064 | UINT64_C(0), // VLD4LNd8Pseudo |
| 2065 | UINT64_C(0), // VLD4LNd8Pseudo_UPD |
| 2066 | UINT64_C(4104127232), // VLD4LNd8_UPD |
| 2067 | UINT64_C(4104128303), // VLD4LNq16 |
| 2068 | UINT64_C(0), // VLD4LNq16Pseudo |
| 2069 | UINT64_C(0), // VLD4LNq16Pseudo_UPD |
| 2070 | UINT64_C(4104128288), // VLD4LNq16_UPD |
| 2071 | UINT64_C(4104129359), // VLD4LNq32 |
| 2072 | UINT64_C(0), // VLD4LNq32Pseudo |
| 2073 | UINT64_C(0), // VLD4LNq32Pseudo_UPD |
| 2074 | UINT64_C(4104129344), // VLD4LNq32_UPD |
| 2075 | UINT64_C(4095737935), // VLD4d16 |
| 2076 | UINT64_C(0), // VLD4d16Pseudo |
| 2077 | UINT64_C(0), // VLD4d16Pseudo_UPD |
| 2078 | UINT64_C(4095737920), // VLD4d16_UPD |
| 2079 | UINT64_C(4095737999), // VLD4d32 |
| 2080 | UINT64_C(0), // VLD4d32Pseudo |
| 2081 | UINT64_C(0), // VLD4d32Pseudo_UPD |
| 2082 | UINT64_C(4095737984), // VLD4d32_UPD |
| 2083 | UINT64_C(4095737871), // VLD4d8 |
| 2084 | UINT64_C(0), // VLD4d8Pseudo |
| 2085 | UINT64_C(0), // VLD4d8Pseudo_UPD |
| 2086 | UINT64_C(4095737856), // VLD4d8_UPD |
| 2087 | UINT64_C(4095738191), // VLD4q16 |
| 2088 | UINT64_C(0), // VLD4q16Pseudo_UPD |
| 2089 | UINT64_C(4095738176), // VLD4q16_UPD |
| 2090 | UINT64_C(0), // VLD4q16oddPseudo |
| 2091 | UINT64_C(0), // VLD4q16oddPseudo_UPD |
| 2092 | UINT64_C(4095738255), // VLD4q32 |
| 2093 | UINT64_C(0), // VLD4q32Pseudo_UPD |
| 2094 | UINT64_C(4095738240), // VLD4q32_UPD |
| 2095 | UINT64_C(0), // VLD4q32oddPseudo |
| 2096 | UINT64_C(0), // VLD4q32oddPseudo_UPD |
| 2097 | UINT64_C(4095738127), // VLD4q8 |
| 2098 | UINT64_C(0), // VLD4q8Pseudo_UPD |
| 2099 | UINT64_C(4095738112), // VLD4q8_UPD |
| 2100 | UINT64_C(0), // VLD4q8oddPseudo |
| 2101 | UINT64_C(0), // VLD4q8oddPseudo_UPD |
| 2102 | UINT64_C(221252352), // VLDMDDB_UPD |
| 2103 | UINT64_C(210766592), // VLDMDIA |
| 2104 | UINT64_C(212863744), // VLDMDIA_UPD |
| 2105 | UINT64_C(0), // VLDMQIA |
| 2106 | UINT64_C(221252096), // VLDMSDB_UPD |
| 2107 | UINT64_C(210766336), // VLDMSIA |
| 2108 | UINT64_C(212863488), // VLDMSIA_UPD |
| 2109 | UINT64_C(219155200), // VLDRD |
| 2110 | UINT64_C(219154688), // VLDRH |
| 2111 | UINT64_C(219154944), // VLDRS |
| 2112 | UINT64_C(223399808), // VLDR_FPCXTNS_off |
| 2113 | UINT64_C(208719744), // VLDR_FPCXTNS_post |
| 2114 | UINT64_C(225496960), // VLDR_FPCXTNS_pre |
| 2115 | UINT64_C(223408000), // VLDR_FPCXTS_off |
| 2116 | UINT64_C(208727936), // VLDR_FPCXTS_post |
| 2117 | UINT64_C(225505152), // VLDR_FPCXTS_pre |
| 2118 | UINT64_C(219172736), // VLDR_FPSCR_NZCVQC_off |
| 2119 | UINT64_C(204492672), // VLDR_FPSCR_NZCVQC_post |
| 2120 | UINT64_C(221269888), // VLDR_FPSCR_NZCVQC_pre |
| 2121 | UINT64_C(219164544), // VLDR_FPSCR_off |
| 2122 | UINT64_C(204484480), // VLDR_FPSCR_post |
| 2123 | UINT64_C(221261696), // VLDR_FPSCR_pre |
| 2124 | UINT64_C(223391616), // VLDR_P0_off |
| 2125 | UINT64_C(208711552), // VLDR_P0_post |
| 2126 | UINT64_C(225488768), // VLDR_P0_pre |
| 2127 | UINT64_C(223383424), // VLDR_VPR_off |
| 2128 | UINT64_C(208703360), // VLDR_VPR_post |
| 2129 | UINT64_C(225480576), // VLDR_VPR_pre |
| 2130 | UINT64_C(3962571264), // VLLDM |
| 2131 | UINT64_C(3962571392), // VLLDM_T2 |
| 2132 | UINT64_C(3961522688), // VLSTM |
| 2133 | UINT64_C(3961522816), // VLSTM_T2 |
| 2134 | UINT64_C(4060090112), // VMAXfd |
| 2135 | UINT64_C(4060090176), // VMAXfq |
| 2136 | UINT64_C(4061138688), // VMAXhd |
| 2137 | UINT64_C(4061138752), // VMAXhq |
| 2138 | UINT64_C(4060087872), // VMAXsv16i8 |
| 2139 | UINT64_C(4062184960), // VMAXsv2i32 |
| 2140 | UINT64_C(4061136384), // VMAXsv4i16 |
| 2141 | UINT64_C(4062185024), // VMAXsv4i32 |
| 2142 | UINT64_C(4061136448), // VMAXsv8i16 |
| 2143 | UINT64_C(4060087808), // VMAXsv8i8 |
| 2144 | UINT64_C(4076865088), // VMAXuv16i8 |
| 2145 | UINT64_C(4078962176), // VMAXuv2i32 |
| 2146 | UINT64_C(4077913600), // VMAXuv4i16 |
| 2147 | UINT64_C(4078962240), // VMAXuv4i32 |
| 2148 | UINT64_C(4077913664), // VMAXuv8i16 |
| 2149 | UINT64_C(4076865024), // VMAXuv8i8 |
| 2150 | UINT64_C(4062187264), // VMINfd |
| 2151 | UINT64_C(4062187328), // VMINfq |
| 2152 | UINT64_C(4063235840), // VMINhd |
| 2153 | UINT64_C(4063235904), // VMINhq |
| 2154 | UINT64_C(4060087888), // VMINsv16i8 |
| 2155 | UINT64_C(4062184976), // VMINsv2i32 |
| 2156 | UINT64_C(4061136400), // VMINsv4i16 |
| 2157 | UINT64_C(4062185040), // VMINsv4i32 |
| 2158 | UINT64_C(4061136464), // VMINsv8i16 |
| 2159 | UINT64_C(4060087824), // VMINsv8i8 |
| 2160 | UINT64_C(4076865104), // VMINuv16i8 |
| 2161 | UINT64_C(4078962192), // VMINuv2i32 |
| 2162 | UINT64_C(4077913616), // VMINuv4i16 |
| 2163 | UINT64_C(4078962256), // VMINuv4i32 |
| 2164 | UINT64_C(4077913680), // VMINuv8i16 |
| 2165 | UINT64_C(4076865040), // VMINuv8i8 |
| 2166 | UINT64_C(234883840), // VMLAD |
| 2167 | UINT64_C(234883328), // VMLAH |
| 2168 | UINT64_C(4070572608), // VMLALslsv2i32 |
| 2169 | UINT64_C(4069524032), // VMLALslsv4i16 |
| 2170 | UINT64_C(4087349824), // VMLALsluv2i32 |
| 2171 | UINT64_C(4086301248), // VMLALsluv4i16 |
| 2172 | UINT64_C(4070574080), // VMLALsv2i64 |
| 2173 | UINT64_C(4069525504), // VMLALsv4i32 |
| 2174 | UINT64_C(4068476928), // VMLALsv8i16 |
| 2175 | UINT64_C(4087351296), // VMLALuv2i64 |
| 2176 | UINT64_C(4086302720), // VMLALuv4i32 |
| 2177 | UINT64_C(4085254144), // VMLALuv8i16 |
| 2178 | UINT64_C(234883584), // VMLAS |
| 2179 | UINT64_C(4060089616), // VMLAfd |
| 2180 | UINT64_C(4060089680), // VMLAfq |
| 2181 | UINT64_C(4061138192), // VMLAhd |
| 2182 | UINT64_C(4061138256), // VMLAhq |
| 2183 | UINT64_C(4070572352), // VMLAslfd |
| 2184 | UINT64_C(4087349568), // VMLAslfq |
| 2185 | UINT64_C(4069523776), // VMLAslhd |
| 2186 | UINT64_C(4086300992), // VMLAslhq |
| 2187 | UINT64_C(4070572096), // VMLAslv2i32 |
| 2188 | UINT64_C(4069523520), // VMLAslv4i16 |
| 2189 | UINT64_C(4087349312), // VMLAslv4i32 |
| 2190 | UINT64_C(4086300736), // VMLAslv8i16 |
| 2191 | UINT64_C(4060088640), // VMLAv16i8 |
| 2192 | UINT64_C(4062185728), // VMLAv2i32 |
| 2193 | UINT64_C(4061137152), // VMLAv4i16 |
| 2194 | UINT64_C(4062185792), // VMLAv4i32 |
| 2195 | UINT64_C(4061137216), // VMLAv8i16 |
| 2196 | UINT64_C(4060088576), // VMLAv8i8 |
| 2197 | UINT64_C(234883904), // VMLSD |
| 2198 | UINT64_C(234883392), // VMLSH |
| 2199 | UINT64_C(4070573632), // VMLSLslsv2i32 |
| 2200 | UINT64_C(4069525056), // VMLSLslsv4i16 |
| 2201 | UINT64_C(4087350848), // VMLSLsluv2i32 |
| 2202 | UINT64_C(4086302272), // VMLSLsluv4i16 |
| 2203 | UINT64_C(4070574592), // VMLSLsv2i64 |
| 2204 | UINT64_C(4069526016), // VMLSLsv4i32 |
| 2205 | UINT64_C(4068477440), // VMLSLsv8i16 |
| 2206 | UINT64_C(4087351808), // VMLSLuv2i64 |
| 2207 | UINT64_C(4086303232), // VMLSLuv4i32 |
| 2208 | UINT64_C(4085254656), // VMLSLuv8i16 |
| 2209 | UINT64_C(234883648), // VMLSS |
| 2210 | UINT64_C(4062186768), // VMLSfd |
| 2211 | UINT64_C(4062186832), // VMLSfq |
| 2212 | UINT64_C(4063235344), // VMLShd |
| 2213 | UINT64_C(4063235408), // VMLShq |
| 2214 | UINT64_C(4070573376), // VMLSslfd |
| 2215 | UINT64_C(4087350592), // VMLSslfq |
| 2216 | UINT64_C(4069524800), // VMLSslhd |
| 2217 | UINT64_C(4086302016), // VMLSslhq |
| 2218 | UINT64_C(4070573120), // VMLSslv2i32 |
| 2219 | UINT64_C(4069524544), // VMLSslv4i16 |
| 2220 | UINT64_C(4087350336), // VMLSslv4i32 |
| 2221 | UINT64_C(4086301760), // VMLSslv8i16 |
| 2222 | UINT64_C(4076865856), // VMLSv16i8 |
| 2223 | UINT64_C(4078962944), // VMLSv2i32 |
| 2224 | UINT64_C(4077914368), // VMLSv4i16 |
| 2225 | UINT64_C(4078963008), // VMLSv4i32 |
| 2226 | UINT64_C(4077914432), // VMLSv8i16 |
| 2227 | UINT64_C(4076865792), // VMLSv8i8 |
| 2228 | UINT64_C(4227861568), // VMMLA |
| 2229 | UINT64_C(246418240), // VMOVD |
| 2230 | UINT64_C(205523728), // VMOVDRR |
| 2231 | UINT64_C(4272949824), // VMOVH |
| 2232 | UINT64_C(234883344), // VMOVHR |
| 2233 | UINT64_C(4070574608), // VMOVLsv2i64 |
| 2234 | UINT64_C(4069526032), // VMOVLsv4i32 |
| 2235 | UINT64_C(4069001744), // VMOVLsv8i16 |
| 2236 | UINT64_C(4087351824), // VMOVLuv2i64 |
| 2237 | UINT64_C(4086303248), // VMOVLuv4i32 |
| 2238 | UINT64_C(4085778960), // VMOVLuv8i16 |
| 2239 | UINT64_C(4089053696), // VMOVNv2i32 |
| 2240 | UINT64_C(4088791552), // VMOVNv4i16 |
| 2241 | UINT64_C(4088529408), // VMOVNv8i8 |
| 2242 | UINT64_C(235931920), // VMOVRH |
| 2243 | UINT64_C(206572304), // VMOVRRD |
| 2244 | UINT64_C(206572048), // VMOVRRS |
| 2245 | UINT64_C(235932176), // VMOVRS |
| 2246 | UINT64_C(246417984), // VMOVS |
| 2247 | UINT64_C(234883600), // VMOVSR |
| 2248 | UINT64_C(205523472), // VMOVSRR |
| 2249 | UINT64_C(4068478544), // VMOVv16i8 |
| 2250 | UINT64_C(4068478512), // VMOVv1i64 |
| 2251 | UINT64_C(4068478736), // VMOVv2f32 |
| 2252 | UINT64_C(4068474896), // VMOVv2i32 |
| 2253 | UINT64_C(4068478576), // VMOVv2i64 |
| 2254 | UINT64_C(4068478800), // VMOVv4f32 |
| 2255 | UINT64_C(4068476944), // VMOVv4i16 |
| 2256 | UINT64_C(4068474960), // VMOVv4i32 |
| 2257 | UINT64_C(4068477008), // VMOVv8i16 |
| 2258 | UINT64_C(4068478480), // VMOVv8i8 |
| 2259 | UINT64_C(250677776), // VMRS |
| 2260 | UINT64_C(251529744), // VMRS_FPCXTNS |
| 2261 | UINT64_C(251595280), // VMRS_FPCXTS |
| 2262 | UINT64_C(251136528), // VMRS_FPEXC |
| 2263 | UINT64_C(251202064), // VMRS_FPINST |
| 2264 | UINT64_C(251267600), // VMRS_FPINST2 |
| 2265 | UINT64_C(250743312), // VMRS_FPSCR_NZCVQC |
| 2266 | UINT64_C(250612240), // VMRS_FPSID |
| 2267 | UINT64_C(251070992), // VMRS_MVFR0 |
| 2268 | UINT64_C(251005456), // VMRS_MVFR1 |
| 2269 | UINT64_C(250939920), // VMRS_MVFR2 |
| 2270 | UINT64_C(251464208), // VMRS_P0 |
| 2271 | UINT64_C(251398672), // VMRS_VPR |
| 2272 | UINT64_C(249629200), // VMSR |
| 2273 | UINT64_C(250481168), // VMSR_FPCXTNS |
| 2274 | UINT64_C(250546704), // VMSR_FPCXTS |
| 2275 | UINT64_C(250087952), // VMSR_FPEXC |
| 2276 | UINT64_C(250153488), // VMSR_FPINST |
| 2277 | UINT64_C(250219024), // VMSR_FPINST2 |
| 2278 | UINT64_C(249694736), // VMSR_FPSCR_NZCVQC |
| 2279 | UINT64_C(249563664), // VMSR_FPSID |
| 2280 | UINT64_C(250415632), // VMSR_P0 |
| 2281 | UINT64_C(250350096), // VMSR_VPR |
| 2282 | UINT64_C(236980992), // VMULD |
| 2283 | UINT64_C(236980480), // VMULH |
| 2284 | UINT64_C(4070575616), // VMULLp64 |
| 2285 | UINT64_C(4068478464), // VMULLp8 |
| 2286 | UINT64_C(4070574656), // VMULLslsv2i32 |
| 2287 | UINT64_C(4069526080), // VMULLslsv4i16 |
| 2288 | UINT64_C(4087351872), // VMULLsluv2i32 |
| 2289 | UINT64_C(4086303296), // VMULLsluv4i16 |
| 2290 | UINT64_C(4070575104), // VMULLsv2i64 |
| 2291 | UINT64_C(4069526528), // VMULLsv4i32 |
| 2292 | UINT64_C(4068477952), // VMULLsv8i16 |
| 2293 | UINT64_C(4087352320), // VMULLuv2i64 |
| 2294 | UINT64_C(4086303744), // VMULLuv4i32 |
| 2295 | UINT64_C(4085255168), // VMULLuv8i16 |
| 2296 | UINT64_C(236980736), // VMULS |
| 2297 | UINT64_C(4076866832), // VMULfd |
| 2298 | UINT64_C(4076866896), // VMULfq |
| 2299 | UINT64_C(4077915408), // VMULhd |
| 2300 | UINT64_C(4077915472), // VMULhq |
| 2301 | UINT64_C(4076865808), // VMULpd |
| 2302 | UINT64_C(4076865872), // VMULpq |
| 2303 | UINT64_C(4070574400), // VMULslfd |
| 2304 | UINT64_C(4087351616), // VMULslfq |
| 2305 | UINT64_C(4069525824), // VMULslhd |
| 2306 | UINT64_C(4086303040), // VMULslhq |
| 2307 | UINT64_C(4070574144), // VMULslv2i32 |
| 2308 | UINT64_C(4069525568), // VMULslv4i16 |
| 2309 | UINT64_C(4087351360), // VMULslv4i32 |
| 2310 | UINT64_C(4086302784), // VMULslv8i16 |
| 2311 | UINT64_C(4060088656), // VMULv16i8 |
| 2312 | UINT64_C(4062185744), // VMULv2i32 |
| 2313 | UINT64_C(4061137168), // VMULv4i16 |
| 2314 | UINT64_C(4062185808), // VMULv4i32 |
| 2315 | UINT64_C(4061137232), // VMULv8i16 |
| 2316 | UINT64_C(4060088592), // VMULv8i8 |
| 2317 | UINT64_C(4088399232), // VMVNd |
| 2318 | UINT64_C(4088399296), // VMVNq |
| 2319 | UINT64_C(4068474928), // VMVNv2i32 |
| 2320 | UINT64_C(4068476976), // VMVNv4i16 |
| 2321 | UINT64_C(4068474992), // VMVNv4i32 |
| 2322 | UINT64_C(4068477040), // VMVNv8i16 |
| 2323 | UINT64_C(246483776), // VNEGD |
| 2324 | UINT64_C(246483264), // VNEGH |
| 2325 | UINT64_C(246483520), // VNEGS |
| 2326 | UINT64_C(4088989632), // VNEGf32q |
| 2327 | UINT64_C(4088989568), // VNEGfd |
| 2328 | UINT64_C(4088727424), // VNEGhd |
| 2329 | UINT64_C(4088727488), // VNEGhq |
| 2330 | UINT64_C(4088726400), // VNEGs16d |
| 2331 | UINT64_C(4088726464), // VNEGs16q |
| 2332 | UINT64_C(4088988544), // VNEGs32d |
| 2333 | UINT64_C(4088988608), // VNEGs32q |
| 2334 | UINT64_C(4088464256), // VNEGs8d |
| 2335 | UINT64_C(4088464320), // VNEGs8q |
| 2336 | UINT64_C(235932480), // VNMLAD |
| 2337 | UINT64_C(235931968), // VNMLAH |
| 2338 | UINT64_C(235932224), // VNMLAS |
| 2339 | UINT64_C(235932416), // VNMLSD |
| 2340 | UINT64_C(235931904), // VNMLSH |
| 2341 | UINT64_C(235932160), // VNMLSS |
| 2342 | UINT64_C(236981056), // VNMULD |
| 2343 | UINT64_C(236980544), // VNMULH |
| 2344 | UINT64_C(236980800), // VNMULS |
| 2345 | UINT64_C(4063232272), // VORNd |
| 2346 | UINT64_C(4063232336), // VORNq |
| 2347 | UINT64_C(4062183696), // VORRd |
| 2348 | UINT64_C(4068475152), // VORRiv2i32 |
| 2349 | UINT64_C(4068477200), // VORRiv4i16 |
| 2350 | UINT64_C(4068475216), // VORRiv4i32 |
| 2351 | UINT64_C(4068477264), // VORRiv8i16 |
| 2352 | UINT64_C(4062183760), // VORRq |
| 2353 | UINT64_C(4088399424), // VPADALsv16i8 |
| 2354 | UINT64_C(4088923648), // VPADALsv2i32 |
| 2355 | UINT64_C(4088661504), // VPADALsv4i16 |
| 2356 | UINT64_C(4088923712), // VPADALsv4i32 |
| 2357 | UINT64_C(4088661568), // VPADALsv8i16 |
| 2358 | UINT64_C(4088399360), // VPADALsv8i8 |
| 2359 | UINT64_C(4088399552), // VPADALuv16i8 |
| 2360 | UINT64_C(4088923776), // VPADALuv2i32 |
| 2361 | UINT64_C(4088661632), // VPADALuv4i16 |
| 2362 | UINT64_C(4088923840), // VPADALuv4i32 |
| 2363 | UINT64_C(4088661696), // VPADALuv8i16 |
| 2364 | UINT64_C(4088399488), // VPADALuv8i8 |
| 2365 | UINT64_C(4088398400), // VPADDLsv16i8 |
| 2366 | UINT64_C(4088922624), // VPADDLsv2i32 |
| 2367 | UINT64_C(4088660480), // VPADDLsv4i16 |
| 2368 | UINT64_C(4088922688), // VPADDLsv4i32 |
| 2369 | UINT64_C(4088660544), // VPADDLsv8i16 |
| 2370 | UINT64_C(4088398336), // VPADDLsv8i8 |
| 2371 | UINT64_C(4088398528), // VPADDLuv16i8 |
| 2372 | UINT64_C(4088922752), // VPADDLuv2i32 |
| 2373 | UINT64_C(4088660608), // VPADDLuv4i16 |
| 2374 | UINT64_C(4088922816), // VPADDLuv4i32 |
| 2375 | UINT64_C(4088660672), // VPADDLuv8i16 |
| 2376 | UINT64_C(4088398464), // VPADDLuv8i8 |
| 2377 | UINT64_C(4076866816), // VPADDf |
| 2378 | UINT64_C(4077915392), // VPADDh |
| 2379 | UINT64_C(4061137680), // VPADDi16 |
| 2380 | UINT64_C(4062186256), // VPADDi32 |
| 2381 | UINT64_C(4060089104), // VPADDi8 |
| 2382 | UINT64_C(4076867328), // VPMAXf |
| 2383 | UINT64_C(4077915904), // VPMAXh |
| 2384 | UINT64_C(4061137408), // VPMAXs16 |
| 2385 | UINT64_C(4062185984), // VPMAXs32 |
| 2386 | UINT64_C(4060088832), // VPMAXs8 |
| 2387 | UINT64_C(4077914624), // VPMAXu16 |
| 2388 | UINT64_C(4078963200), // VPMAXu32 |
| 2389 | UINT64_C(4076866048), // VPMAXu8 |
| 2390 | UINT64_C(4078964480), // VPMINf |
| 2391 | UINT64_C(4080013056), // VPMINh |
| 2392 | UINT64_C(4061137424), // VPMINs16 |
| 2393 | UINT64_C(4062186000), // VPMINs32 |
| 2394 | UINT64_C(4060088848), // VPMINs8 |
| 2395 | UINT64_C(4077914640), // VPMINu16 |
| 2396 | UINT64_C(4078963216), // VPMINu32 |
| 2397 | UINT64_C(4076866064), // VPMINu8 |
| 2398 | UINT64_C(4088399680), // VQABSv16i8 |
| 2399 | UINT64_C(4088923904), // VQABSv2i32 |
| 2400 | UINT64_C(4088661760), // VQABSv4i16 |
| 2401 | UINT64_C(4088923968), // VQABSv4i32 |
| 2402 | UINT64_C(4088661824), // VQABSv8i16 |
| 2403 | UINT64_C(4088399616), // VQABSv8i8 |
| 2404 | UINT64_C(4060086352), // VQADDsv16i8 |
| 2405 | UINT64_C(4063232016), // VQADDsv1i64 |
| 2406 | UINT64_C(4062183440), // VQADDsv2i32 |
| 2407 | UINT64_C(4063232080), // VQADDsv2i64 |
| 2408 | UINT64_C(4061134864), // VQADDsv4i16 |
| 2409 | UINT64_C(4062183504), // VQADDsv4i32 |
| 2410 | UINT64_C(4061134928), // VQADDsv8i16 |
| 2411 | UINT64_C(4060086288), // VQADDsv8i8 |
| 2412 | UINT64_C(4076863568), // VQADDuv16i8 |
| 2413 | UINT64_C(4080009232), // VQADDuv1i64 |
| 2414 | UINT64_C(4078960656), // VQADDuv2i32 |
| 2415 | UINT64_C(4080009296), // VQADDuv2i64 |
| 2416 | UINT64_C(4077912080), // VQADDuv4i16 |
| 2417 | UINT64_C(4078960720), // VQADDuv4i32 |
| 2418 | UINT64_C(4077912144), // VQADDuv8i16 |
| 2419 | UINT64_C(4076863504), // VQADDuv8i8 |
| 2420 | UINT64_C(4070572864), // VQDMLALslv2i32 |
| 2421 | UINT64_C(4069524288), // VQDMLALslv4i16 |
| 2422 | UINT64_C(4070574336), // VQDMLALv2i64 |
| 2423 | UINT64_C(4069525760), // VQDMLALv4i32 |
| 2424 | UINT64_C(4070573888), // VQDMLSLslv2i32 |
| 2425 | UINT64_C(4069525312), // VQDMLSLslv4i16 |
| 2426 | UINT64_C(4070574848), // VQDMLSLv2i64 |
| 2427 | UINT64_C(4069526272), // VQDMLSLv4i32 |
| 2428 | UINT64_C(4070575168), // VQDMULHslv2i32 |
| 2429 | UINT64_C(4069526592), // VQDMULHslv4i16 |
| 2430 | UINT64_C(4087352384), // VQDMULHslv4i32 |
| 2431 | UINT64_C(4086303808), // VQDMULHslv8i16 |
| 2432 | UINT64_C(4062186240), // VQDMULHv2i32 |
| 2433 | UINT64_C(4061137664), // VQDMULHv4i16 |
| 2434 | UINT64_C(4062186304), // VQDMULHv4i32 |
| 2435 | UINT64_C(4061137728), // VQDMULHv8i16 |
| 2436 | UINT64_C(4070574912), // VQDMULLslv2i32 |
| 2437 | UINT64_C(4069526336), // VQDMULLslv4i16 |
| 2438 | UINT64_C(4070575360), // VQDMULLv2i64 |
| 2439 | UINT64_C(4069526784), // VQDMULLv4i32 |
| 2440 | UINT64_C(4089053760), // VQMOVNsuv2i32 |
| 2441 | UINT64_C(4088791616), // VQMOVNsuv4i16 |
| 2442 | UINT64_C(4088529472), // VQMOVNsuv8i8 |
| 2443 | UINT64_C(4089053824), // VQMOVNsv2i32 |
| 2444 | UINT64_C(4088791680), // VQMOVNsv4i16 |
| 2445 | UINT64_C(4088529536), // VQMOVNsv8i8 |
| 2446 | UINT64_C(4089053888), // VQMOVNuv2i32 |
| 2447 | UINT64_C(4088791744), // VQMOVNuv4i16 |
| 2448 | UINT64_C(4088529600), // VQMOVNuv8i8 |
| 2449 | UINT64_C(4088399808), // VQNEGv16i8 |
| 2450 | UINT64_C(4088924032), // VQNEGv2i32 |
| 2451 | UINT64_C(4088661888), // VQNEGv4i16 |
| 2452 | UINT64_C(4088924096), // VQNEGv4i32 |
| 2453 | UINT64_C(4088661952), // VQNEGv8i16 |
| 2454 | UINT64_C(4088399744), // VQNEGv8i8 |
| 2455 | UINT64_C(4070575680), // VQRDMLAHslv2i32 |
| 2456 | UINT64_C(4069527104), // VQRDMLAHslv4i16 |
| 2457 | UINT64_C(4087352896), // VQRDMLAHslv4i32 |
| 2458 | UINT64_C(4086304320), // VQRDMLAHslv8i16 |
| 2459 | UINT64_C(4078963472), // VQRDMLAHv2i32 |
| 2460 | UINT64_C(4077914896), // VQRDMLAHv4i16 |
| 2461 | UINT64_C(4078963536), // VQRDMLAHv4i32 |
| 2462 | UINT64_C(4077914960), // VQRDMLAHv8i16 |
| 2463 | UINT64_C(4070575936), // VQRDMLSHslv2i32 |
| 2464 | UINT64_C(4069527360), // VQRDMLSHslv4i16 |
| 2465 | UINT64_C(4087353152), // VQRDMLSHslv4i32 |
| 2466 | UINT64_C(4086304576), // VQRDMLSHslv8i16 |
| 2467 | UINT64_C(4078963728), // VQRDMLSHv2i32 |
| 2468 | UINT64_C(4077915152), // VQRDMLSHv4i16 |
| 2469 | UINT64_C(4078963792), // VQRDMLSHv4i32 |
| 2470 | UINT64_C(4077915216), // VQRDMLSHv8i16 |
| 2471 | UINT64_C(4070575424), // VQRDMULHslv2i32 |
| 2472 | UINT64_C(4069526848), // VQRDMULHslv4i16 |
| 2473 | UINT64_C(4087352640), // VQRDMULHslv4i32 |
| 2474 | UINT64_C(4086304064), // VQRDMULHslv8i16 |
| 2475 | UINT64_C(4078963456), // VQRDMULHv2i32 |
| 2476 | UINT64_C(4077914880), // VQRDMULHv4i16 |
| 2477 | UINT64_C(4078963520), // VQRDMULHv4i32 |
| 2478 | UINT64_C(4077914944), // VQRDMULHv8i16 |
| 2479 | UINT64_C(4060087632), // VQRSHLsv16i8 |
| 2480 | UINT64_C(4063233296), // VQRSHLsv1i64 |
| 2481 | UINT64_C(4062184720), // VQRSHLsv2i32 |
| 2482 | UINT64_C(4063233360), // VQRSHLsv2i64 |
| 2483 | UINT64_C(4061136144), // VQRSHLsv4i16 |
| 2484 | UINT64_C(4062184784), // VQRSHLsv4i32 |
| 2485 | UINT64_C(4061136208), // VQRSHLsv8i16 |
| 2486 | UINT64_C(4060087568), // VQRSHLsv8i8 |
| 2487 | UINT64_C(4076864848), // VQRSHLuv16i8 |
| 2488 | UINT64_C(4080010512), // VQRSHLuv1i64 |
| 2489 | UINT64_C(4078961936), // VQRSHLuv2i32 |
| 2490 | UINT64_C(4080010576), // VQRSHLuv2i64 |
| 2491 | UINT64_C(4077913360), // VQRSHLuv4i16 |
| 2492 | UINT64_C(4078962000), // VQRSHLuv4i32 |
| 2493 | UINT64_C(4077913424), // VQRSHLuv8i16 |
| 2494 | UINT64_C(4076864784), // VQRSHLuv8i8 |
| 2495 | UINT64_C(4070574416), // VQRSHRNsv2i32 |
| 2496 | UINT64_C(4069525840), // VQRSHRNsv4i16 |
| 2497 | UINT64_C(4069001552), // VQRSHRNsv8i8 |
| 2498 | UINT64_C(4087351632), // VQRSHRNuv2i32 |
| 2499 | UINT64_C(4086303056), // VQRSHRNuv4i16 |
| 2500 | UINT64_C(4085778768), // VQRSHRNuv8i8 |
| 2501 | UINT64_C(4087351376), // VQRSHRUNv2i32 |
| 2502 | UINT64_C(4086302800), // VQRSHRUNv4i16 |
| 2503 | UINT64_C(4085778512), // VQRSHRUNv8i8 |
| 2504 | UINT64_C(4069001040), // VQSHLsiv16i8 |
| 2505 | UINT64_C(4068476816), // VQSHLsiv1i64 |
| 2506 | UINT64_C(4070573840), // VQSHLsiv2i32 |
| 2507 | UINT64_C(4068476880), // VQSHLsiv2i64 |
| 2508 | UINT64_C(4069525264), // VQSHLsiv4i16 |
| 2509 | UINT64_C(4070573904), // VQSHLsiv4i32 |
| 2510 | UINT64_C(4069525328), // VQSHLsiv8i16 |
| 2511 | UINT64_C(4069000976), // VQSHLsiv8i8 |
| 2512 | UINT64_C(4085778000), // VQSHLsuv16i8 |
| 2513 | UINT64_C(4085253776), // VQSHLsuv1i64 |
| 2514 | UINT64_C(4087350800), // VQSHLsuv2i32 |
| 2515 | UINT64_C(4085253840), // VQSHLsuv2i64 |
| 2516 | UINT64_C(4086302224), // VQSHLsuv4i16 |
| 2517 | UINT64_C(4087350864), // VQSHLsuv4i32 |
| 2518 | UINT64_C(4086302288), // VQSHLsuv8i16 |
| 2519 | UINT64_C(4085777936), // VQSHLsuv8i8 |
| 2520 | UINT64_C(4060087376), // VQSHLsv16i8 |
| 2521 | UINT64_C(4063233040), // VQSHLsv1i64 |
| 2522 | UINT64_C(4062184464), // VQSHLsv2i32 |
| 2523 | UINT64_C(4063233104), // VQSHLsv2i64 |
| 2524 | UINT64_C(4061135888), // VQSHLsv4i16 |
| 2525 | UINT64_C(4062184528), // VQSHLsv4i32 |
| 2526 | UINT64_C(4061135952), // VQSHLsv8i16 |
| 2527 | UINT64_C(4060087312), // VQSHLsv8i8 |
| 2528 | UINT64_C(4085778256), // VQSHLuiv16i8 |
| 2529 | UINT64_C(4085254032), // VQSHLuiv1i64 |
| 2530 | UINT64_C(4087351056), // VQSHLuiv2i32 |
| 2531 | UINT64_C(4085254096), // VQSHLuiv2i64 |
| 2532 | UINT64_C(4086302480), // VQSHLuiv4i16 |
| 2533 | UINT64_C(4087351120), // VQSHLuiv4i32 |
| 2534 | UINT64_C(4086302544), // VQSHLuiv8i16 |
| 2535 | UINT64_C(4085778192), // VQSHLuiv8i8 |
| 2536 | UINT64_C(4076864592), // VQSHLuv16i8 |
| 2537 | UINT64_C(4080010256), // VQSHLuv1i64 |
| 2538 | UINT64_C(4078961680), // VQSHLuv2i32 |
| 2539 | UINT64_C(4080010320), // VQSHLuv2i64 |
| 2540 | UINT64_C(4077913104), // VQSHLuv4i16 |
| 2541 | UINT64_C(4078961744), // VQSHLuv4i32 |
| 2542 | UINT64_C(4077913168), // VQSHLuv8i16 |
| 2543 | UINT64_C(4076864528), // VQSHLuv8i8 |
| 2544 | UINT64_C(4070574352), // VQSHRNsv2i32 |
| 2545 | UINT64_C(4069525776), // VQSHRNsv4i16 |
| 2546 | UINT64_C(4069001488), // VQSHRNsv8i8 |
| 2547 | UINT64_C(4087351568), // VQSHRNuv2i32 |
| 2548 | UINT64_C(4086302992), // VQSHRNuv4i16 |
| 2549 | UINT64_C(4085778704), // VQSHRNuv8i8 |
| 2550 | UINT64_C(4087351312), // VQSHRUNv2i32 |
| 2551 | UINT64_C(4086302736), // VQSHRUNv4i16 |
| 2552 | UINT64_C(4085778448), // VQSHRUNv8i8 |
| 2553 | UINT64_C(4060086864), // VQSUBsv16i8 |
| 2554 | UINT64_C(4063232528), // VQSUBsv1i64 |
| 2555 | UINT64_C(4062183952), // VQSUBsv2i32 |
| 2556 | UINT64_C(4063232592), // VQSUBsv2i64 |
| 2557 | UINT64_C(4061135376), // VQSUBsv4i16 |
| 2558 | UINT64_C(4062184016), // VQSUBsv4i32 |
| 2559 | UINT64_C(4061135440), // VQSUBsv8i16 |
| 2560 | UINT64_C(4060086800), // VQSUBsv8i8 |
| 2561 | UINT64_C(4076864080), // VQSUBuv16i8 |
| 2562 | UINT64_C(4080009744), // VQSUBuv1i64 |
| 2563 | UINT64_C(4078961168), // VQSUBuv2i32 |
| 2564 | UINT64_C(4080009808), // VQSUBuv2i64 |
| 2565 | UINT64_C(4077912592), // VQSUBuv4i16 |
| 2566 | UINT64_C(4078961232), // VQSUBuv4i32 |
| 2567 | UINT64_C(4077912656), // VQSUBuv8i16 |
| 2568 | UINT64_C(4076864016), // VQSUBuv8i8 |
| 2569 | UINT64_C(4087350272), // VRADDHNv2i32 |
| 2570 | UINT64_C(4086301696), // VRADDHNv4i16 |
| 2571 | UINT64_C(4085253120), // VRADDHNv8i8 |
| 2572 | UINT64_C(4089119744), // VRECPEd |
| 2573 | UINT64_C(4089120000), // VRECPEfd |
| 2574 | UINT64_C(4089120064), // VRECPEfq |
| 2575 | UINT64_C(4088857856), // VRECPEhd |
| 2576 | UINT64_C(4088857920), // VRECPEhq |
| 2577 | UINT64_C(4089119808), // VRECPEq |
| 2578 | UINT64_C(4060090128), // VRECPSfd |
| 2579 | UINT64_C(4060090192), // VRECPSfq |
| 2580 | UINT64_C(4061138704), // VRECPShd |
| 2581 | UINT64_C(4061138768), // VRECPShq |
| 2582 | UINT64_C(4088398080), // VREV16d8 |
| 2583 | UINT64_C(4088398144), // VREV16q8 |
| 2584 | UINT64_C(4088660096), // VREV32d16 |
| 2585 | UINT64_C(4088397952), // VREV32d8 |
| 2586 | UINT64_C(4088660160), // VREV32q16 |
| 2587 | UINT64_C(4088398016), // VREV32q8 |
| 2588 | UINT64_C(4088659968), // VREV64d16 |
| 2589 | UINT64_C(4088922112), // VREV64d32 |
| 2590 | UINT64_C(4088397824), // VREV64d8 |
| 2591 | UINT64_C(4088660032), // VREV64q16 |
| 2592 | UINT64_C(4088922176), // VREV64q32 |
| 2593 | UINT64_C(4088397888), // VREV64q8 |
| 2594 | UINT64_C(4060086592), // VRHADDsv16i8 |
| 2595 | UINT64_C(4062183680), // VRHADDsv2i32 |
| 2596 | UINT64_C(4061135104), // VRHADDsv4i16 |
| 2597 | UINT64_C(4062183744), // VRHADDsv4i32 |
| 2598 | UINT64_C(4061135168), // VRHADDsv8i16 |
| 2599 | UINT64_C(4060086528), // VRHADDsv8i8 |
| 2600 | UINT64_C(4076863808), // VRHADDuv16i8 |
| 2601 | UINT64_C(4078960896), // VRHADDuv2i32 |
| 2602 | UINT64_C(4077912320), // VRHADDuv4i16 |
| 2603 | UINT64_C(4078960960), // VRHADDuv4i32 |
| 2604 | UINT64_C(4077912384), // VRHADDuv8i16 |
| 2605 | UINT64_C(4076863744), // VRHADDuv8i8 |
| 2606 | UINT64_C(4273474368), // VRINTAD |
| 2607 | UINT64_C(4273473856), // VRINTAH |
| 2608 | UINT64_C(4089054464), // VRINTANDf |
| 2609 | UINT64_C(4088792320), // VRINTANDh |
| 2610 | UINT64_C(4089054528), // VRINTANQf |
| 2611 | UINT64_C(4088792384), // VRINTANQh |
| 2612 | UINT64_C(4273474112), // VRINTAS |
| 2613 | UINT64_C(4273670976), // VRINTMD |
| 2614 | UINT64_C(4273670464), // VRINTMH |
| 2615 | UINT64_C(4089054848), // VRINTMNDf |
| 2616 | UINT64_C(4088792704), // VRINTMNDh |
| 2617 | UINT64_C(4089054912), // VRINTMNQf |
| 2618 | UINT64_C(4088792768), // VRINTMNQh |
| 2619 | UINT64_C(4273670720), // VRINTMS |
| 2620 | UINT64_C(4273539904), // VRINTND |
| 2621 | UINT64_C(4273539392), // VRINTNH |
| 2622 | UINT64_C(4089054208), // VRINTNNDf |
| 2623 | UINT64_C(4088792064), // VRINTNNDh |
| 2624 | UINT64_C(4089054272), // VRINTNNQf |
| 2625 | UINT64_C(4088792128), // VRINTNNQh |
| 2626 | UINT64_C(4273539648), // VRINTNS |
| 2627 | UINT64_C(4273605440), // VRINTPD |
| 2628 | UINT64_C(4273604928), // VRINTPH |
| 2629 | UINT64_C(4089055104), // VRINTPNDf |
| 2630 | UINT64_C(4088792960), // VRINTPNDh |
| 2631 | UINT64_C(4089055168), // VRINTPNQf |
| 2632 | UINT64_C(4088793024), // VRINTPNQh |
| 2633 | UINT64_C(4273605184), // VRINTPS |
| 2634 | UINT64_C(246811456), // VRINTRD |
| 2635 | UINT64_C(246810944), // VRINTRH |
| 2636 | UINT64_C(246811200), // VRINTRS |
| 2637 | UINT64_C(246876992), // VRINTXD |
| 2638 | UINT64_C(246876480), // VRINTXH |
| 2639 | UINT64_C(4089054336), // VRINTXNDf |
| 2640 | UINT64_C(4088792192), // VRINTXNDh |
| 2641 | UINT64_C(4089054400), // VRINTXNQf |
| 2642 | UINT64_C(4088792256), // VRINTXNQh |
| 2643 | UINT64_C(246876736), // VRINTXS |
| 2644 | UINT64_C(246811584), // VRINTZD |
| 2645 | UINT64_C(246811072), // VRINTZH |
| 2646 | UINT64_C(4089054592), // VRINTZNDf |
| 2647 | UINT64_C(4088792448), // VRINTZNDh |
| 2648 | UINT64_C(4089054656), // VRINTZNQf |
| 2649 | UINT64_C(4088792512), // VRINTZNQh |
| 2650 | UINT64_C(246811328), // VRINTZS |
| 2651 | UINT64_C(4060087616), // VRSHLsv16i8 |
| 2652 | UINT64_C(4063233280), // VRSHLsv1i64 |
| 2653 | UINT64_C(4062184704), // VRSHLsv2i32 |
| 2654 | UINT64_C(4063233344), // VRSHLsv2i64 |
| 2655 | UINT64_C(4061136128), // VRSHLsv4i16 |
| 2656 | UINT64_C(4062184768), // VRSHLsv4i32 |
| 2657 | UINT64_C(4061136192), // VRSHLsv8i16 |
| 2658 | UINT64_C(4060087552), // VRSHLsv8i8 |
| 2659 | UINT64_C(4076864832), // VRSHLuv16i8 |
| 2660 | UINT64_C(4080010496), // VRSHLuv1i64 |
| 2661 | UINT64_C(4078961920), // VRSHLuv2i32 |
| 2662 | UINT64_C(4080010560), // VRSHLuv2i64 |
| 2663 | UINT64_C(4077913344), // VRSHLuv4i16 |
| 2664 | UINT64_C(4078961984), // VRSHLuv4i32 |
| 2665 | UINT64_C(4077913408), // VRSHLuv8i16 |
| 2666 | UINT64_C(4076864768), // VRSHLuv8i8 |
| 2667 | UINT64_C(4070574160), // VRSHRNv2i32 |
| 2668 | UINT64_C(4069525584), // VRSHRNv4i16 |
| 2669 | UINT64_C(4069001296), // VRSHRNv8i8 |
| 2670 | UINT64_C(4068999760), // VRSHRsv16i8 |
| 2671 | UINT64_C(4068475536), // VRSHRsv1i64 |
| 2672 | UINT64_C(4070572560), // VRSHRsv2i32 |
| 2673 | UINT64_C(4068475600), // VRSHRsv2i64 |
| 2674 | UINT64_C(4069523984), // VRSHRsv4i16 |
| 2675 | UINT64_C(4070572624), // VRSHRsv4i32 |
| 2676 | UINT64_C(4069524048), // VRSHRsv8i16 |
| 2677 | UINT64_C(4068999696), // VRSHRsv8i8 |
| 2678 | UINT64_C(4085776976), // VRSHRuv16i8 |
| 2679 | UINT64_C(4085252752), // VRSHRuv1i64 |
| 2680 | UINT64_C(4087349776), // VRSHRuv2i32 |
| 2681 | UINT64_C(4085252816), // VRSHRuv2i64 |
| 2682 | UINT64_C(4086301200), // VRSHRuv4i16 |
| 2683 | UINT64_C(4087349840), // VRSHRuv4i32 |
| 2684 | UINT64_C(4086301264), // VRSHRuv8i16 |
| 2685 | UINT64_C(4085776912), // VRSHRuv8i8 |
| 2686 | UINT64_C(4089119872), // VRSQRTEd |
| 2687 | UINT64_C(4089120128), // VRSQRTEfd |
| 2688 | UINT64_C(4089120192), // VRSQRTEfq |
| 2689 | UINT64_C(4088857984), // VRSQRTEhd |
| 2690 | UINT64_C(4088858048), // VRSQRTEhq |
| 2691 | UINT64_C(4089119936), // VRSQRTEq |
| 2692 | UINT64_C(4062187280), // VRSQRTSfd |
| 2693 | UINT64_C(4062187344), // VRSQRTSfq |
| 2694 | UINT64_C(4063235856), // VRSQRTShd |
| 2695 | UINT64_C(4063235920), // VRSQRTShq |
| 2696 | UINT64_C(4069000016), // VRSRAsv16i8 |
| 2697 | UINT64_C(4068475792), // VRSRAsv1i64 |
| 2698 | UINT64_C(4070572816), // VRSRAsv2i32 |
| 2699 | UINT64_C(4068475856), // VRSRAsv2i64 |
| 2700 | UINT64_C(4069524240), // VRSRAsv4i16 |
| 2701 | UINT64_C(4070572880), // VRSRAsv4i32 |
| 2702 | UINT64_C(4069524304), // VRSRAsv8i16 |
| 2703 | UINT64_C(4068999952), // VRSRAsv8i8 |
| 2704 | UINT64_C(4085777232), // VRSRAuv16i8 |
| 2705 | UINT64_C(4085253008), // VRSRAuv1i64 |
| 2706 | UINT64_C(4087350032), // VRSRAuv2i32 |
| 2707 | UINT64_C(4085253072), // VRSRAuv2i64 |
| 2708 | UINT64_C(4086301456), // VRSRAuv4i16 |
| 2709 | UINT64_C(4087350096), // VRSRAuv4i32 |
| 2710 | UINT64_C(4086301520), // VRSRAuv8i16 |
| 2711 | UINT64_C(4085777168), // VRSRAuv8i8 |
| 2712 | UINT64_C(4087350784), // VRSUBHNv2i32 |
| 2713 | UINT64_C(4086302208), // VRSUBHNv4i16 |
| 2714 | UINT64_C(4085253632), // VRSUBHNv8i8 |
| 2715 | UINT64_C(3969846016), // VSCCLRMD |
| 2716 | UINT64_C(3969845760), // VSCCLRMS |
| 2717 | UINT64_C(4229958912), // VSDOTD |
| 2718 | UINT64_C(4263513344), // VSDOTDI |
| 2719 | UINT64_C(4229958976), // VSDOTQ |
| 2720 | UINT64_C(4263513408), // VSDOTQI |
| 2721 | UINT64_C(4261415680), // VSELEQD |
| 2722 | UINT64_C(4261415168), // VSELEQH |
| 2723 | UINT64_C(4261415424), // VSELEQS |
| 2724 | UINT64_C(4263512832), // VSELGED |
| 2725 | UINT64_C(4263512320), // VSELGEH |
| 2726 | UINT64_C(4263512576), // VSELGES |
| 2727 | UINT64_C(4264561408), // VSELGTD |
| 2728 | UINT64_C(4264560896), // VSELGTH |
| 2729 | UINT64_C(4264561152), // VSELGTS |
| 2730 | UINT64_C(4262464256), // VSELVSD |
| 2731 | UINT64_C(4262463744), // VSELVSH |
| 2732 | UINT64_C(4262464000), // VSELVSS |
| 2733 | UINT64_C(234883888), // VSETLNi16 |
| 2734 | UINT64_C(234883856), // VSETLNi32 |
| 2735 | UINT64_C(239078160), // VSETLNi8 |
| 2736 | UINT64_C(4088791808), // VSHLLi16 |
| 2737 | UINT64_C(4089053952), // VSHLLi32 |
| 2738 | UINT64_C(4088529664), // VSHLLi8 |
| 2739 | UINT64_C(4070574608), // VSHLLsv2i64 |
| 2740 | UINT64_C(4069526032), // VSHLLsv4i32 |
| 2741 | UINT64_C(4069001744), // VSHLLsv8i16 |
| 2742 | UINT64_C(4087351824), // VSHLLuv2i64 |
| 2743 | UINT64_C(4086303248), // VSHLLuv4i32 |
| 2744 | UINT64_C(4085778960), // VSHLLuv8i16 |
| 2745 | UINT64_C(4069000528), // VSHLiv16i8 |
| 2746 | UINT64_C(4068476304), // VSHLiv1i64 |
| 2747 | UINT64_C(4070573328), // VSHLiv2i32 |
| 2748 | UINT64_C(4068476368), // VSHLiv2i64 |
| 2749 | UINT64_C(4069524752), // VSHLiv4i16 |
| 2750 | UINT64_C(4070573392), // VSHLiv4i32 |
| 2751 | UINT64_C(4069524816), // VSHLiv8i16 |
| 2752 | UINT64_C(4069000464), // VSHLiv8i8 |
| 2753 | UINT64_C(4060087360), // VSHLsv16i8 |
| 2754 | UINT64_C(4063233024), // VSHLsv1i64 |
| 2755 | UINT64_C(4062184448), // VSHLsv2i32 |
| 2756 | UINT64_C(4063233088), // VSHLsv2i64 |
| 2757 | UINT64_C(4061135872), // VSHLsv4i16 |
| 2758 | UINT64_C(4062184512), // VSHLsv4i32 |
| 2759 | UINT64_C(4061135936), // VSHLsv8i16 |
| 2760 | UINT64_C(4060087296), // VSHLsv8i8 |
| 2761 | UINT64_C(4076864576), // VSHLuv16i8 |
| 2762 | UINT64_C(4080010240), // VSHLuv1i64 |
| 2763 | UINT64_C(4078961664), // VSHLuv2i32 |
| 2764 | UINT64_C(4080010304), // VSHLuv2i64 |
| 2765 | UINT64_C(4077913088), // VSHLuv4i16 |
| 2766 | UINT64_C(4078961728), // VSHLuv4i32 |
| 2767 | UINT64_C(4077913152), // VSHLuv8i16 |
| 2768 | UINT64_C(4076864512), // VSHLuv8i8 |
| 2769 | UINT64_C(4070574096), // VSHRNv2i32 |
| 2770 | UINT64_C(4069525520), // VSHRNv4i16 |
| 2771 | UINT64_C(4069001232), // VSHRNv8i8 |
| 2772 | UINT64_C(4068999248), // VSHRsv16i8 |
| 2773 | UINT64_C(4068475024), // VSHRsv1i64 |
| 2774 | UINT64_C(4070572048), // VSHRsv2i32 |
| 2775 | UINT64_C(4068475088), // VSHRsv2i64 |
| 2776 | UINT64_C(4069523472), // VSHRsv4i16 |
| 2777 | UINT64_C(4070572112), // VSHRsv4i32 |
| 2778 | UINT64_C(4069523536), // VSHRsv8i16 |
| 2779 | UINT64_C(4068999184), // VSHRsv8i8 |
| 2780 | UINT64_C(4085776464), // VSHRuv16i8 |
| 2781 | UINT64_C(4085252240), // VSHRuv1i64 |
| 2782 | UINT64_C(4087349264), // VSHRuv2i32 |
| 2783 | UINT64_C(4085252304), // VSHRuv2i64 |
| 2784 | UINT64_C(4086300688), // VSHRuv4i16 |
| 2785 | UINT64_C(4087349328), // VSHRuv4i32 |
| 2786 | UINT64_C(4086300752), // VSHRuv8i16 |
| 2787 | UINT64_C(4085776400), // VSHRuv8i8 |
| 2788 | UINT64_C(247073600), // VSHTOD |
| 2789 | UINT64_C(247073088), // VSHTOH |
| 2790 | UINT64_C(247073344), // VSHTOS |
| 2791 | UINT64_C(246942656), // VSITOD |
| 2792 | UINT64_C(246942144), // VSITOH |
| 2793 | UINT64_C(246942400), // VSITOS |
| 2794 | UINT64_C(4085777744), // VSLIv16i8 |
| 2795 | UINT64_C(4085253520), // VSLIv1i64 |
| 2796 | UINT64_C(4087350544), // VSLIv2i32 |
| 2797 | UINT64_C(4085253584), // VSLIv2i64 |
| 2798 | UINT64_C(4086301968), // VSLIv4i16 |
| 2799 | UINT64_C(4087350608), // VSLIv4i32 |
| 2800 | UINT64_C(4086302032), // VSLIv8i16 |
| 2801 | UINT64_C(4085777680), // VSLIv8i8 |
| 2802 | UINT64_C(247073728), // VSLTOD |
| 2803 | UINT64_C(247073216), // VSLTOH |
| 2804 | UINT64_C(247073472), // VSLTOS |
| 2805 | UINT64_C(4229958720), // VSMMLA |
| 2806 | UINT64_C(246483904), // VSQRTD |
| 2807 | UINT64_C(246483392), // VSQRTH |
| 2808 | UINT64_C(246483648), // VSQRTS |
| 2809 | UINT64_C(4068999504), // VSRAsv16i8 |
| 2810 | UINT64_C(4068475280), // VSRAsv1i64 |
| 2811 | UINT64_C(4070572304), // VSRAsv2i32 |
| 2812 | UINT64_C(4068475344), // VSRAsv2i64 |
| 2813 | UINT64_C(4069523728), // VSRAsv4i16 |
| 2814 | UINT64_C(4070572368), // VSRAsv4i32 |
| 2815 | UINT64_C(4069523792), // VSRAsv8i16 |
| 2816 | UINT64_C(4068999440), // VSRAsv8i8 |
| 2817 | UINT64_C(4085776720), // VSRAuv16i8 |
| 2818 | UINT64_C(4085252496), // VSRAuv1i64 |
| 2819 | UINT64_C(4087349520), // VSRAuv2i32 |
| 2820 | UINT64_C(4085252560), // VSRAuv2i64 |
| 2821 | UINT64_C(4086300944), // VSRAuv4i16 |
| 2822 | UINT64_C(4087349584), // VSRAuv4i32 |
| 2823 | UINT64_C(4086301008), // VSRAuv8i16 |
| 2824 | UINT64_C(4085776656), // VSRAuv8i8 |
| 2825 | UINT64_C(4085777488), // VSRIv16i8 |
| 2826 | UINT64_C(4085253264), // VSRIv1i64 |
| 2827 | UINT64_C(4087350288), // VSRIv2i32 |
| 2828 | UINT64_C(4085253328), // VSRIv2i64 |
| 2829 | UINT64_C(4086301712), // VSRIv4i16 |
| 2830 | UINT64_C(4087350352), // VSRIv4i32 |
| 2831 | UINT64_C(4086301776), // VSRIv8i16 |
| 2832 | UINT64_C(4085777424), // VSRIv8i8 |
| 2833 | UINT64_C(4102030351), // VST1LNd16 |
| 2834 | UINT64_C(4102030336), // VST1LNd16_UPD |
| 2835 | UINT64_C(4102031375), // VST1LNd32 |
| 2836 | UINT64_C(4102031360), // VST1LNd32_UPD |
| 2837 | UINT64_C(4102029327), // VST1LNd8 |
| 2838 | UINT64_C(4102029312), // VST1LNd8_UPD |
| 2839 | UINT64_C(0), // VST1LNq16Pseudo |
| 2840 | UINT64_C(0), // VST1LNq16Pseudo_UPD |
| 2841 | UINT64_C(0), // VST1LNq32Pseudo |
| 2842 | UINT64_C(0), // VST1LNq32Pseudo_UPD |
| 2843 | UINT64_C(0), // VST1LNq8Pseudo |
| 2844 | UINT64_C(0), // VST1LNq8Pseudo_UPD |
| 2845 | UINT64_C(4093642575), // VST1d16 |
| 2846 | UINT64_C(4093641295), // VST1d16Q |
| 2847 | UINT64_C(0), // VST1d16QPseudo |
| 2848 | UINT64_C(0), // VST1d16QPseudoWB_fixed |
| 2849 | UINT64_C(0), // VST1d16QPseudoWB_register |
| 2850 | UINT64_C(4093641293), // VST1d16Qwb_fixed |
| 2851 | UINT64_C(4093641280), // VST1d16Qwb_register |
| 2852 | UINT64_C(4093642319), // VST1d16T |
| 2853 | UINT64_C(0), // VST1d16TPseudo |
| 2854 | UINT64_C(0), // VST1d16TPseudoWB_fixed |
| 2855 | UINT64_C(0), // VST1d16TPseudoWB_register |
| 2856 | UINT64_C(4093642317), // VST1d16Twb_fixed |
| 2857 | UINT64_C(4093642304), // VST1d16Twb_register |
| 2858 | UINT64_C(4093642573), // VST1d16wb_fixed |
| 2859 | UINT64_C(4093642560), // VST1d16wb_register |
| 2860 | UINT64_C(4093642639), // VST1d32 |
| 2861 | UINT64_C(4093641359), // VST1d32Q |
| 2862 | UINT64_C(0), // VST1d32QPseudo |
| 2863 | UINT64_C(0), // VST1d32QPseudoWB_fixed |
| 2864 | UINT64_C(0), // VST1d32QPseudoWB_register |
| 2865 | UINT64_C(4093641357), // VST1d32Qwb_fixed |
| 2866 | UINT64_C(4093641344), // VST1d32Qwb_register |
| 2867 | UINT64_C(4093642383), // VST1d32T |
| 2868 | UINT64_C(0), // VST1d32TPseudo |
| 2869 | UINT64_C(0), // VST1d32TPseudoWB_fixed |
| 2870 | UINT64_C(0), // VST1d32TPseudoWB_register |
| 2871 | UINT64_C(4093642381), // VST1d32Twb_fixed |
| 2872 | UINT64_C(4093642368), // VST1d32Twb_register |
| 2873 | UINT64_C(4093642637), // VST1d32wb_fixed |
| 2874 | UINT64_C(4093642624), // VST1d32wb_register |
| 2875 | UINT64_C(4093642703), // VST1d64 |
| 2876 | UINT64_C(4093641423), // VST1d64Q |
| 2877 | UINT64_C(0), // VST1d64QPseudo |
| 2878 | UINT64_C(0), // VST1d64QPseudoWB_fixed |
| 2879 | UINT64_C(0), // VST1d64QPseudoWB_register |
| 2880 | UINT64_C(4093641421), // VST1d64Qwb_fixed |
| 2881 | UINT64_C(4093641408), // VST1d64Qwb_register |
| 2882 | UINT64_C(4093642447), // VST1d64T |
| 2883 | UINT64_C(0), // VST1d64TPseudo |
| 2884 | UINT64_C(0), // VST1d64TPseudoWB_fixed |
| 2885 | UINT64_C(0), // VST1d64TPseudoWB_register |
| 2886 | UINT64_C(4093642445), // VST1d64Twb_fixed |
| 2887 | UINT64_C(4093642432), // VST1d64Twb_register |
| 2888 | UINT64_C(4093642701), // VST1d64wb_fixed |
| 2889 | UINT64_C(4093642688), // VST1d64wb_register |
| 2890 | UINT64_C(4093642511), // VST1d8 |
| 2891 | UINT64_C(4093641231), // VST1d8Q |
| 2892 | UINT64_C(0), // VST1d8QPseudo |
| 2893 | UINT64_C(0), // VST1d8QPseudoWB_fixed |
| 2894 | UINT64_C(0), // VST1d8QPseudoWB_register |
| 2895 | UINT64_C(4093641229), // VST1d8Qwb_fixed |
| 2896 | UINT64_C(4093641216), // VST1d8Qwb_register |
| 2897 | UINT64_C(4093642255), // VST1d8T |
| 2898 | UINT64_C(0), // VST1d8TPseudo |
| 2899 | UINT64_C(0), // VST1d8TPseudoWB_fixed |
| 2900 | UINT64_C(0), // VST1d8TPseudoWB_register |
| 2901 | UINT64_C(4093642253), // VST1d8Twb_fixed |
| 2902 | UINT64_C(4093642240), // VST1d8Twb_register |
| 2903 | UINT64_C(4093642509), // VST1d8wb_fixed |
| 2904 | UINT64_C(4093642496), // VST1d8wb_register |
| 2905 | UINT64_C(4093643343), // VST1q16 |
| 2906 | UINT64_C(0), // VST1q16HighQPseudo |
| 2907 | UINT64_C(0), // VST1q16HighQPseudo_UPD |
| 2908 | UINT64_C(0), // VST1q16HighTPseudo |
| 2909 | UINT64_C(0), // VST1q16HighTPseudo_UPD |
| 2910 | UINT64_C(0), // VST1q16LowQPseudo_UPD |
| 2911 | UINT64_C(0), // VST1q16LowTPseudo_UPD |
| 2912 | UINT64_C(4093643341), // VST1q16wb_fixed |
| 2913 | UINT64_C(4093643328), // VST1q16wb_register |
| 2914 | UINT64_C(4093643407), // VST1q32 |
| 2915 | UINT64_C(0), // VST1q32HighQPseudo |
| 2916 | UINT64_C(0), // VST1q32HighQPseudo_UPD |
| 2917 | UINT64_C(0), // VST1q32HighTPseudo |
| 2918 | UINT64_C(0), // VST1q32HighTPseudo_UPD |
| 2919 | UINT64_C(0), // VST1q32LowQPseudo_UPD |
| 2920 | UINT64_C(0), // VST1q32LowTPseudo_UPD |
| 2921 | UINT64_C(4093643405), // VST1q32wb_fixed |
| 2922 | UINT64_C(4093643392), // VST1q32wb_register |
| 2923 | UINT64_C(4093643471), // VST1q64 |
| 2924 | UINT64_C(0), // VST1q64HighQPseudo |
| 2925 | UINT64_C(0), // VST1q64HighQPseudo_UPD |
| 2926 | UINT64_C(0), // VST1q64HighTPseudo |
| 2927 | UINT64_C(0), // VST1q64HighTPseudo_UPD |
| 2928 | UINT64_C(0), // VST1q64LowQPseudo_UPD |
| 2929 | UINT64_C(0), // VST1q64LowTPseudo_UPD |
| 2930 | UINT64_C(4093643469), // VST1q64wb_fixed |
| 2931 | UINT64_C(4093643456), // VST1q64wb_register |
| 2932 | UINT64_C(4093643279), // VST1q8 |
| 2933 | UINT64_C(0), // VST1q8HighQPseudo |
| 2934 | UINT64_C(0), // VST1q8HighQPseudo_UPD |
| 2935 | UINT64_C(0), // VST1q8HighTPseudo |
| 2936 | UINT64_C(0), // VST1q8HighTPseudo_UPD |
| 2937 | UINT64_C(0), // VST1q8LowQPseudo_UPD |
| 2938 | UINT64_C(0), // VST1q8LowTPseudo_UPD |
| 2939 | UINT64_C(4093643277), // VST1q8wb_fixed |
| 2940 | UINT64_C(4093643264), // VST1q8wb_register |
| 2941 | UINT64_C(4102030607), // VST2LNd16 |
| 2942 | UINT64_C(0), // VST2LNd16Pseudo |
| 2943 | UINT64_C(0), // VST2LNd16Pseudo_UPD |
| 2944 | UINT64_C(4102030592), // VST2LNd16_UPD |
| 2945 | UINT64_C(4102031631), // VST2LNd32 |
| 2946 | UINT64_C(0), // VST2LNd32Pseudo |
| 2947 | UINT64_C(0), // VST2LNd32Pseudo_UPD |
| 2948 | UINT64_C(4102031616), // VST2LNd32_UPD |
| 2949 | UINT64_C(4102029583), // VST2LNd8 |
| 2950 | UINT64_C(0), // VST2LNd8Pseudo |
| 2951 | UINT64_C(0), // VST2LNd8Pseudo_UPD |
| 2952 | UINT64_C(4102029568), // VST2LNd8_UPD |
| 2953 | UINT64_C(4102030639), // VST2LNq16 |
| 2954 | UINT64_C(0), // VST2LNq16Pseudo |
| 2955 | UINT64_C(0), // VST2LNq16Pseudo_UPD |
| 2956 | UINT64_C(4102030624), // VST2LNq16_UPD |
| 2957 | UINT64_C(4102031695), // VST2LNq32 |
| 2958 | UINT64_C(0), // VST2LNq32Pseudo |
| 2959 | UINT64_C(0), // VST2LNq32Pseudo_UPD |
| 2960 | UINT64_C(4102031680), // VST2LNq32_UPD |
| 2961 | UINT64_C(4093643087), // VST2b16 |
| 2962 | UINT64_C(4093643085), // VST2b16wb_fixed |
| 2963 | UINT64_C(4093643072), // VST2b16wb_register |
| 2964 | UINT64_C(4093643151), // VST2b32 |
| 2965 | UINT64_C(4093643149), // VST2b32wb_fixed |
| 2966 | UINT64_C(4093643136), // VST2b32wb_register |
| 2967 | UINT64_C(4093643023), // VST2b8 |
| 2968 | UINT64_C(4093643021), // VST2b8wb_fixed |
| 2969 | UINT64_C(4093643008), // VST2b8wb_register |
| 2970 | UINT64_C(4093642831), // VST2d16 |
| 2971 | UINT64_C(4093642829), // VST2d16wb_fixed |
| 2972 | UINT64_C(4093642816), // VST2d16wb_register |
| 2973 | UINT64_C(4093642895), // VST2d32 |
| 2974 | UINT64_C(4093642893), // VST2d32wb_fixed |
| 2975 | UINT64_C(4093642880), // VST2d32wb_register |
| 2976 | UINT64_C(4093642767), // VST2d8 |
| 2977 | UINT64_C(4093642765), // VST2d8wb_fixed |
| 2978 | UINT64_C(4093642752), // VST2d8wb_register |
| 2979 | UINT64_C(4093641551), // VST2q16 |
| 2980 | UINT64_C(0), // VST2q16Pseudo |
| 2981 | UINT64_C(0), // VST2q16PseudoWB_fixed |
| 2982 | UINT64_C(0), // VST2q16PseudoWB_register |
| 2983 | UINT64_C(4093641549), // VST2q16wb_fixed |
| 2984 | UINT64_C(4093641536), // VST2q16wb_register |
| 2985 | UINT64_C(4093641615), // VST2q32 |
| 2986 | UINT64_C(0), // VST2q32Pseudo |
| 2987 | UINT64_C(0), // VST2q32PseudoWB_fixed |
| 2988 | UINT64_C(0), // VST2q32PseudoWB_register |
| 2989 | UINT64_C(4093641613), // VST2q32wb_fixed |
| 2990 | UINT64_C(4093641600), // VST2q32wb_register |
| 2991 | UINT64_C(4093641487), // VST2q8 |
| 2992 | UINT64_C(0), // VST2q8Pseudo |
| 2993 | UINT64_C(0), // VST2q8PseudoWB_fixed |
| 2994 | UINT64_C(0), // VST2q8PseudoWB_register |
| 2995 | UINT64_C(4093641485), // VST2q8wb_fixed |
| 2996 | UINT64_C(4093641472), // VST2q8wb_register |
| 2997 | UINT64_C(4102030863), // VST3LNd16 |
| 2998 | UINT64_C(0), // VST3LNd16Pseudo |
| 2999 | UINT64_C(0), // VST3LNd16Pseudo_UPD |
| 3000 | UINT64_C(4102030848), // VST3LNd16_UPD |
| 3001 | UINT64_C(4102031887), // VST3LNd32 |
| 3002 | UINT64_C(0), // VST3LNd32Pseudo |
| 3003 | UINT64_C(0), // VST3LNd32Pseudo_UPD |
| 3004 | UINT64_C(4102031872), // VST3LNd32_UPD |
| 3005 | UINT64_C(4102029839), // VST3LNd8 |
| 3006 | UINT64_C(0), // VST3LNd8Pseudo |
| 3007 | UINT64_C(0), // VST3LNd8Pseudo_UPD |
| 3008 | UINT64_C(4102029824), // VST3LNd8_UPD |
| 3009 | UINT64_C(4102030895), // VST3LNq16 |
| 3010 | UINT64_C(0), // VST3LNq16Pseudo |
| 3011 | UINT64_C(0), // VST3LNq16Pseudo_UPD |
| 3012 | UINT64_C(4102030880), // VST3LNq16_UPD |
| 3013 | UINT64_C(4102031951), // VST3LNq32 |
| 3014 | UINT64_C(0), // VST3LNq32Pseudo |
| 3015 | UINT64_C(0), // VST3LNq32Pseudo_UPD |
| 3016 | UINT64_C(4102031936), // VST3LNq32_UPD |
| 3017 | UINT64_C(4093641807), // VST3d16 |
| 3018 | UINT64_C(0), // VST3d16Pseudo |
| 3019 | UINT64_C(0), // VST3d16Pseudo_UPD |
| 3020 | UINT64_C(4093641792), // VST3d16_UPD |
| 3021 | UINT64_C(4093641871), // VST3d32 |
| 3022 | UINT64_C(0), // VST3d32Pseudo |
| 3023 | UINT64_C(0), // VST3d32Pseudo_UPD |
| 3024 | UINT64_C(4093641856), // VST3d32_UPD |
| 3025 | UINT64_C(4093641743), // VST3d8 |
| 3026 | UINT64_C(0), // VST3d8Pseudo |
| 3027 | UINT64_C(0), // VST3d8Pseudo_UPD |
| 3028 | UINT64_C(4093641728), // VST3d8_UPD |
| 3029 | UINT64_C(4093642063), // VST3q16 |
| 3030 | UINT64_C(0), // VST3q16Pseudo_UPD |
| 3031 | UINT64_C(4093642048), // VST3q16_UPD |
| 3032 | UINT64_C(0), // VST3q16oddPseudo |
| 3033 | UINT64_C(0), // VST3q16oddPseudo_UPD |
| 3034 | UINT64_C(4093642127), // VST3q32 |
| 3035 | UINT64_C(0), // VST3q32Pseudo_UPD |
| 3036 | UINT64_C(4093642112), // VST3q32_UPD |
| 3037 | UINT64_C(0), // VST3q32oddPseudo |
| 3038 | UINT64_C(0), // VST3q32oddPseudo_UPD |
| 3039 | UINT64_C(4093641999), // VST3q8 |
| 3040 | UINT64_C(0), // VST3q8Pseudo_UPD |
| 3041 | UINT64_C(4093641984), // VST3q8_UPD |
| 3042 | UINT64_C(0), // VST3q8oddPseudo |
| 3043 | UINT64_C(0), // VST3q8oddPseudo_UPD |
| 3044 | UINT64_C(4102031119), // VST4LNd16 |
| 3045 | UINT64_C(0), // VST4LNd16Pseudo |
| 3046 | UINT64_C(0), // VST4LNd16Pseudo_UPD |
| 3047 | UINT64_C(4102031104), // VST4LNd16_UPD |
| 3048 | UINT64_C(4102032143), // VST4LNd32 |
| 3049 | UINT64_C(0), // VST4LNd32Pseudo |
| 3050 | UINT64_C(0), // VST4LNd32Pseudo_UPD |
| 3051 | UINT64_C(4102032128), // VST4LNd32_UPD |
| 3052 | UINT64_C(4102030095), // VST4LNd8 |
| 3053 | UINT64_C(0), // VST4LNd8Pseudo |
| 3054 | UINT64_C(0), // VST4LNd8Pseudo_UPD |
| 3055 | UINT64_C(4102030080), // VST4LNd8_UPD |
| 3056 | UINT64_C(4102031151), // VST4LNq16 |
| 3057 | UINT64_C(0), // VST4LNq16Pseudo |
| 3058 | UINT64_C(0), // VST4LNq16Pseudo_UPD |
| 3059 | UINT64_C(4102031136), // VST4LNq16_UPD |
| 3060 | UINT64_C(4102032207), // VST4LNq32 |
| 3061 | UINT64_C(0), // VST4LNq32Pseudo |
| 3062 | UINT64_C(0), // VST4LNq32Pseudo_UPD |
| 3063 | UINT64_C(4102032192), // VST4LNq32_UPD |
| 3064 | UINT64_C(4093640783), // VST4d16 |
| 3065 | UINT64_C(0), // VST4d16Pseudo |
| 3066 | UINT64_C(0), // VST4d16Pseudo_UPD |
| 3067 | UINT64_C(4093640768), // VST4d16_UPD |
| 3068 | UINT64_C(4093640847), // VST4d32 |
| 3069 | UINT64_C(0), // VST4d32Pseudo |
| 3070 | UINT64_C(0), // VST4d32Pseudo_UPD |
| 3071 | UINT64_C(4093640832), // VST4d32_UPD |
| 3072 | UINT64_C(4093640719), // VST4d8 |
| 3073 | UINT64_C(0), // VST4d8Pseudo |
| 3074 | UINT64_C(0), // VST4d8Pseudo_UPD |
| 3075 | UINT64_C(4093640704), // VST4d8_UPD |
| 3076 | UINT64_C(4093641039), // VST4q16 |
| 3077 | UINT64_C(0), // VST4q16Pseudo_UPD |
| 3078 | UINT64_C(4093641024), // VST4q16_UPD |
| 3079 | UINT64_C(0), // VST4q16oddPseudo |
| 3080 | UINT64_C(0), // VST4q16oddPseudo_UPD |
| 3081 | UINT64_C(4093641103), // VST4q32 |
| 3082 | UINT64_C(0), // VST4q32Pseudo_UPD |
| 3083 | UINT64_C(4093641088), // VST4q32_UPD |
| 3084 | UINT64_C(0), // VST4q32oddPseudo |
| 3085 | UINT64_C(0), // VST4q32oddPseudo_UPD |
| 3086 | UINT64_C(4093640975), // VST4q8 |
| 3087 | UINT64_C(0), // VST4q8Pseudo_UPD |
| 3088 | UINT64_C(4093640960), // VST4q8_UPD |
| 3089 | UINT64_C(0), // VST4q8oddPseudo |
| 3090 | UINT64_C(0), // VST4q8oddPseudo_UPD |
| 3091 | UINT64_C(220203776), // VSTMDDB_UPD |
| 3092 | UINT64_C(209718016), // VSTMDIA |
| 3093 | UINT64_C(211815168), // VSTMDIA_UPD |
| 3094 | UINT64_C(0), // VSTMQIA |
| 3095 | UINT64_C(220203520), // VSTMSDB_UPD |
| 3096 | UINT64_C(209717760), // VSTMSIA |
| 3097 | UINT64_C(211814912), // VSTMSIA_UPD |
| 3098 | UINT64_C(218106624), // VSTRD |
| 3099 | UINT64_C(218106112), // VSTRH |
| 3100 | UINT64_C(218106368), // VSTRS |
| 3101 | UINT64_C(222351232), // VSTR_FPCXTNS_off |
| 3102 | UINT64_C(207671168), // VSTR_FPCXTNS_post |
| 3103 | UINT64_C(224448384), // VSTR_FPCXTNS_pre |
| 3104 | UINT64_C(222359424), // VSTR_FPCXTS_off |
| 3105 | UINT64_C(207679360), // VSTR_FPCXTS_post |
| 3106 | UINT64_C(224456576), // VSTR_FPCXTS_pre |
| 3107 | UINT64_C(218124160), // VSTR_FPSCR_NZCVQC_off |
| 3108 | UINT64_C(203444096), // VSTR_FPSCR_NZCVQC_post |
| 3109 | UINT64_C(220221312), // VSTR_FPSCR_NZCVQC_pre |
| 3110 | UINT64_C(218115968), // VSTR_FPSCR_off |
| 3111 | UINT64_C(203435904), // VSTR_FPSCR_post |
| 3112 | UINT64_C(220213120), // VSTR_FPSCR_pre |
| 3113 | UINT64_C(222343040), // VSTR_P0_off |
| 3114 | UINT64_C(207662976), // VSTR_P0_post |
| 3115 | UINT64_C(224440192), // VSTR_P0_pre |
| 3116 | UINT64_C(222334848), // VSTR_VPR_off |
| 3117 | UINT64_C(207654784), // VSTR_VPR_post |
| 3118 | UINT64_C(224432000), // VSTR_VPR_pre |
| 3119 | UINT64_C(238029632), // VSUBD |
| 3120 | UINT64_C(238029120), // VSUBH |
| 3121 | UINT64_C(4070573568), // VSUBHNv2i32 |
| 3122 | UINT64_C(4069524992), // VSUBHNv4i16 |
| 3123 | UINT64_C(4068476416), // VSUBHNv8i8 |
| 3124 | UINT64_C(4070572544), // VSUBLsv2i64 |
| 3125 | UINT64_C(4069523968), // VSUBLsv4i32 |
| 3126 | UINT64_C(4068475392), // VSUBLsv8i16 |
| 3127 | UINT64_C(4087349760), // VSUBLuv2i64 |
| 3128 | UINT64_C(4086301184), // VSUBLuv4i32 |
| 3129 | UINT64_C(4085252608), // VSUBLuv8i16 |
| 3130 | UINT64_C(238029376), // VSUBS |
| 3131 | UINT64_C(4070572800), // VSUBWsv2i64 |
| 3132 | UINT64_C(4069524224), // VSUBWsv4i32 |
| 3133 | UINT64_C(4068475648), // VSUBWsv8i16 |
| 3134 | UINT64_C(4087350016), // VSUBWuv2i64 |
| 3135 | UINT64_C(4086301440), // VSUBWuv4i32 |
| 3136 | UINT64_C(4085252864), // VSUBWuv8i16 |
| 3137 | UINT64_C(4062186752), // VSUBfd |
| 3138 | UINT64_C(4062186816), // VSUBfq |
| 3139 | UINT64_C(4063235328), // VSUBhd |
| 3140 | UINT64_C(4063235392), // VSUBhq |
| 3141 | UINT64_C(4076865600), // VSUBv16i8 |
| 3142 | UINT64_C(4080011264), // VSUBv1i64 |
| 3143 | UINT64_C(4078962688), // VSUBv2i32 |
| 3144 | UINT64_C(4080011328), // VSUBv2i64 |
| 3145 | UINT64_C(4077914112), // VSUBv4i16 |
| 3146 | UINT64_C(4078962752), // VSUBv4i32 |
| 3147 | UINT64_C(4077914176), // VSUBv8i16 |
| 3148 | UINT64_C(4076865536), // VSUBv8i8 |
| 3149 | UINT64_C(4269804816), // VSUDOTDI |
| 3150 | UINT64_C(4269804880), // VSUDOTQI |
| 3151 | UINT64_C(4088528896), // VSWPd |
| 3152 | UINT64_C(4088528960), // VSWPq |
| 3153 | UINT64_C(4088399872), // VTBL1 |
| 3154 | UINT64_C(4088400128), // VTBL2 |
| 3155 | UINT64_C(4088400384), // VTBL3 |
| 3156 | UINT64_C(0), // VTBL3Pseudo |
| 3157 | UINT64_C(4088400640), // VTBL4 |
| 3158 | UINT64_C(0), // VTBL4Pseudo |
| 3159 | UINT64_C(4088399936), // VTBX1 |
| 3160 | UINT64_C(4088400192), // VTBX2 |
| 3161 | UINT64_C(4088400448), // VTBX3 |
| 3162 | UINT64_C(0), // VTBX3Pseudo |
| 3163 | UINT64_C(4088400704), // VTBX4 |
| 3164 | UINT64_C(0), // VTBX4Pseudo |
| 3165 | UINT64_C(247335744), // VTOSHD |
| 3166 | UINT64_C(247335232), // VTOSHH |
| 3167 | UINT64_C(247335488), // VTOSHS |
| 3168 | UINT64_C(247270208), // VTOSIRD |
| 3169 | UINT64_C(247269696), // VTOSIRH |
| 3170 | UINT64_C(247269952), // VTOSIRS |
| 3171 | UINT64_C(247270336), // VTOSIZD |
| 3172 | UINT64_C(247269824), // VTOSIZH |
| 3173 | UINT64_C(247270080), // VTOSIZS |
| 3174 | UINT64_C(247335872), // VTOSLD |
| 3175 | UINT64_C(247335360), // VTOSLH |
| 3176 | UINT64_C(247335616), // VTOSLS |
| 3177 | UINT64_C(247401280), // VTOUHD |
| 3178 | UINT64_C(247400768), // VTOUHH |
| 3179 | UINT64_C(247401024), // VTOUHS |
| 3180 | UINT64_C(247204672), // VTOUIRD |
| 3181 | UINT64_C(247204160), // VTOUIRH |
| 3182 | UINT64_C(247204416), // VTOUIRS |
| 3183 | UINT64_C(247204800), // VTOUIZD |
| 3184 | UINT64_C(247204288), // VTOUIZH |
| 3185 | UINT64_C(247204544), // VTOUIZS |
| 3186 | UINT64_C(247401408), // VTOULD |
| 3187 | UINT64_C(247400896), // VTOULH |
| 3188 | UINT64_C(247401152), // VTOULS |
| 3189 | UINT64_C(4088791168), // VTRNd16 |
| 3190 | UINT64_C(4089053312), // VTRNd32 |
| 3191 | UINT64_C(4088529024), // VTRNd8 |
| 3192 | UINT64_C(4088791232), // VTRNq16 |
| 3193 | UINT64_C(4089053376), // VTRNq32 |
| 3194 | UINT64_C(4088529088), // VTRNq8 |
| 3195 | UINT64_C(4060088400), // VTSTv16i8 |
| 3196 | UINT64_C(4062185488), // VTSTv2i32 |
| 3197 | UINT64_C(4061136912), // VTSTv4i16 |
| 3198 | UINT64_C(4062185552), // VTSTv4i32 |
| 3199 | UINT64_C(4061136976), // VTSTv8i16 |
| 3200 | UINT64_C(4060088336), // VTSTv8i8 |
| 3201 | UINT64_C(4229958928), // VUDOTD |
| 3202 | UINT64_C(4263513360), // VUDOTDI |
| 3203 | UINT64_C(4229958992), // VUDOTQ |
| 3204 | UINT64_C(4263513424), // VUDOTQI |
| 3205 | UINT64_C(247139136), // VUHTOD |
| 3206 | UINT64_C(247138624), // VUHTOH |
| 3207 | UINT64_C(247138880), // VUHTOS |
| 3208 | UINT64_C(246942528), // VUITOD |
| 3209 | UINT64_C(246942016), // VUITOH |
| 3210 | UINT64_C(246942272), // VUITOS |
| 3211 | UINT64_C(247139264), // VULTOD |
| 3212 | UINT64_C(247138752), // VULTOH |
| 3213 | UINT64_C(247139008), // VULTOS |
| 3214 | UINT64_C(4229958736), // VUMMLA |
| 3215 | UINT64_C(4238347520), // VUSDOTD |
| 3216 | UINT64_C(4269804800), // VUSDOTDI |
| 3217 | UINT64_C(4238347584), // VUSDOTQ |
| 3218 | UINT64_C(4269804864), // VUSDOTQI |
| 3219 | UINT64_C(4238347328), // VUSMMLA |
| 3220 | UINT64_C(4088791296), // VUZPd16 |
| 3221 | UINT64_C(4088529152), // VUZPd8 |
| 3222 | UINT64_C(4088791360), // VUZPq16 |
| 3223 | UINT64_C(4089053504), // VUZPq32 |
| 3224 | UINT64_C(4088529216), // VUZPq8 |
| 3225 | UINT64_C(4088791424), // VZIPd16 |
| 3226 | UINT64_C(4088529280), // VZIPd8 |
| 3227 | UINT64_C(4088791488), // VZIPq16 |
| 3228 | UINT64_C(4089053632), // VZIPq32 |
| 3229 | UINT64_C(4088529344), // VZIPq8 |
| 3230 | UINT64_C(139460608), // sysLDMDA |
| 3231 | UINT64_C(141557760), // sysLDMDA_UPD |
| 3232 | UINT64_C(156237824), // sysLDMDB |
| 3233 | UINT64_C(158334976), // sysLDMDB_UPD |
| 3234 | UINT64_C(147849216), // sysLDMIA |
| 3235 | UINT64_C(149946368), // sysLDMIA_UPD |
| 3236 | UINT64_C(164626432), // sysLDMIB |
| 3237 | UINT64_C(166723584), // sysLDMIB_UPD |
| 3238 | UINT64_C(138412032), // sysSTMDA |
| 3239 | UINT64_C(140509184), // sysSTMDA_UPD |
| 3240 | UINT64_C(155189248), // sysSTMDB |
| 3241 | UINT64_C(157286400), // sysSTMDB_UPD |
| 3242 | UINT64_C(146800640), // sysSTMIA |
| 3243 | UINT64_C(148897792), // sysSTMIA_UPD |
| 3244 | UINT64_C(163577856), // sysSTMIB |
| 3245 | UINT64_C(165675008), // sysSTMIB_UPD |
| 3246 | UINT64_C(4047503360), // t2ADCri |
| 3247 | UINT64_C(3946840064), // t2ADCrr |
| 3248 | UINT64_C(3946840064), // t2ADCrs |
| 3249 | UINT64_C(4043309056), // t2ADDri |
| 3250 | UINT64_C(4060086272), // t2ADDri12 |
| 3251 | UINT64_C(3942645760), // t2ADDrr |
| 3252 | UINT64_C(3942645760), // t2ADDrs |
| 3253 | UINT64_C(4044164352), // t2ADDspImm |
| 3254 | UINT64_C(4060941568), // t2ADDspImm12 |
| 3255 | UINT64_C(4061069312), // t2ADR |
| 3256 | UINT64_C(4026531840), // t2ANDri |
| 3257 | UINT64_C(3925868544), // t2ANDrr |
| 3258 | UINT64_C(3925868544), // t2ANDrs |
| 3259 | UINT64_C(3931045920), // t2ASRri |
| 3260 | UINT64_C(4198559744), // t2ASRrr |
| 3261 | UINT64_C(3932094560), // t2ASRs1 |
| 3262 | UINT64_C(4088365101), // t2AUT |
| 3263 | UINT64_C(4216327936), // t2AUTG |
| 3264 | UINT64_C(4026568704), // t2B |
| 3265 | UINT64_C(4084137984), // t2BFC |
| 3266 | UINT64_C(4083154944), // t2BFI |
| 3267 | UINT64_C(4026580993), // t2BFLi |
| 3268 | UINT64_C(4033929217), // t2BFLr |
| 3269 | UINT64_C(4030783489), // t2BFi |
| 3270 | UINT64_C(4026589185), // t2BFic |
| 3271 | UINT64_C(4032880641), // t2BFr |
| 3272 | UINT64_C(4028628992), // t2BICri |
| 3273 | UINT64_C(3927965696), // t2BICrr |
| 3274 | UINT64_C(3927965696), // t2BICrs |
| 3275 | UINT64_C(4088365071), // t2BTI |
| 3276 | UINT64_C(4216327952), // t2BXAUT |
| 3277 | UINT64_C(4089483008), // t2BXJ |
| 3278 | UINT64_C(4026564608), // t2Bcc |
| 3279 | UINT64_C(3992977408), // t2CDP |
| 3280 | UINT64_C(4261412864), // t2CDP2 |
| 3281 | UINT64_C(4089417519), // t2CLREX |
| 3282 | UINT64_C(3902734336), // t2CLRM |
| 3283 | UINT64_C(4205899904), // t2CLZ |
| 3284 | UINT64_C(4044361472), // t2CMNri |
| 3285 | UINT64_C(3943698176), // t2CMNzrr |
| 3286 | UINT64_C(3943698176), // t2CMNzrs |
| 3287 | UINT64_C(4054847232), // t2CMPri |
| 3288 | UINT64_C(3954183936), // t2CMPrr |
| 3289 | UINT64_C(3954183936), // t2CMPrs |
| 3290 | UINT64_C(4088365312), // t2CPS1p |
| 3291 | UINT64_C(4088365056), // t2CPS2p |
| 3292 | UINT64_C(4088365312), // t2CPS3p |
| 3293 | UINT64_C(4206948480), // t2CRC32B |
| 3294 | UINT64_C(4207997056), // t2CRC32CB |
| 3295 | UINT64_C(4207997072), // t2CRC32CH |
| 3296 | UINT64_C(4207997088), // t2CRC32CW |
| 3297 | UINT64_C(4206948496), // t2CRC32H |
| 3298 | UINT64_C(4206948512), // t2CRC32W |
| 3299 | UINT64_C(3931144192), // t2CSEL |
| 3300 | UINT64_C(3931148288), // t2CSINC |
| 3301 | UINT64_C(3931152384), // t2CSINV |
| 3302 | UINT64_C(3931156480), // t2CSNEG |
| 3303 | UINT64_C(4088365296), // t2DBG |
| 3304 | UINT64_C(4153376769), // t2DCPS1 |
| 3305 | UINT64_C(4153376770), // t2DCPS2 |
| 3306 | UINT64_C(4153376771), // t2DCPS3 |
| 3307 | UINT64_C(4030783489), // t2DLS |
| 3308 | UINT64_C(4089417552), // t2DMB |
| 3309 | UINT64_C(4089417536), // t2DSB |
| 3310 | UINT64_C(4034920448), // t2EORri |
| 3311 | UINT64_C(3934257152), // t2EORrr |
| 3312 | UINT64_C(3934257152), // t2EORrs |
| 3313 | UINT64_C(4088365056), // t2HINT |
| 3314 | UINT64_C(4158685184), // t2HVC |
| 3315 | UINT64_C(4089417568), // t2ISB |
| 3316 | UINT64_C(48896), // t2IT |
| 3317 | UINT64_C(0), // t2Int_eh_sjlj_setjmp |
| 3318 | UINT64_C(0), // t2Int_eh_sjlj_setjmp_nofp |
| 3319 | UINT64_C(3905949615), // t2LDA |
| 3320 | UINT64_C(3905949583), // t2LDAB |
| 3321 | UINT64_C(3905949679), // t2LDAEX |
| 3322 | UINT64_C(3905949647), // t2LDAEXB |
| 3323 | UINT64_C(3905945855), // t2LDAEXD |
| 3324 | UINT64_C(3905949663), // t2LDAEXH |
| 3325 | UINT64_C(3905949599), // t2LDAH |
| 3326 | UINT64_C(4249878528), // t2LDC2L_OFFSET |
| 3327 | UINT64_C(4241489920), // t2LDC2L_OPTION |
| 3328 | UINT64_C(4235198464), // t2LDC2L_POST |
| 3329 | UINT64_C(4251975680), // t2LDC2L_PRE |
| 3330 | UINT64_C(4245684224), // t2LDC2_OFFSET |
| 3331 | UINT64_C(4237295616), // t2LDC2_OPTION |
| 3332 | UINT64_C(4231004160), // t2LDC2_POST |
| 3333 | UINT64_C(4247781376), // t2LDC2_PRE |
| 3334 | UINT64_C(3981443072), // t2LDCL_OFFSET |
| 3335 | UINT64_C(3973054464), // t2LDCL_OPTION |
| 3336 | UINT64_C(3966763008), // t2LDCL_POST |
| 3337 | UINT64_C(3983540224), // t2LDCL_PRE |
| 3338 | UINT64_C(3977248768), // t2LDC_OFFSET |
| 3339 | UINT64_C(3968860160), // t2LDC_OPTION |
| 3340 | UINT64_C(3962568704), // t2LDC_POST |
| 3341 | UINT64_C(3979345920), // t2LDC_PRE |
| 3342 | UINT64_C(3910139904), // t2LDMDB |
| 3343 | UINT64_C(3912237056), // t2LDMDB_UPD |
| 3344 | UINT64_C(3901751296), // t2LDMIA |
| 3345 | UINT64_C(3903848448), // t2LDMIA_UPD |
| 3346 | UINT64_C(4161801728), // t2LDRBT |
| 3347 | UINT64_C(4161800448), // t2LDRB_POST |
| 3348 | UINT64_C(4161801472), // t2LDRB_PRE |
| 3349 | UINT64_C(4170186752), // t2LDRBi12 |
| 3350 | UINT64_C(4161801216), // t2LDRBi8 |
| 3351 | UINT64_C(4162781184), // t2LDRBpci |
| 3352 | UINT64_C(4161798144), // t2LDRBs |
| 3353 | UINT64_C(3899654144), // t2LDRD_POST |
| 3354 | UINT64_C(3916431360), // t2LDRD_PRE |
| 3355 | UINT64_C(3914334208), // t2LDRDi8 |
| 3356 | UINT64_C(3897560832), // t2LDREX |
| 3357 | UINT64_C(3905949519), // t2LDREXB |
| 3358 | UINT64_C(3905945727), // t2LDREXD |
| 3359 | UINT64_C(3905949535), // t2LDREXH |
| 3360 | UINT64_C(4163898880), // t2LDRHT |
| 3361 | UINT64_C(4163897600), // t2LDRH_POST |
| 3362 | UINT64_C(4163898624), // t2LDRH_PRE |
| 3363 | UINT64_C(4172283904), // t2LDRHi12 |
| 3364 | UINT64_C(4163898368), // t2LDRHi8 |
| 3365 | UINT64_C(4164878336), // t2LDRHpci |
| 3366 | UINT64_C(4163895296), // t2LDRHs |
| 3367 | UINT64_C(4178578944), // t2LDRSBT |
| 3368 | UINT64_C(4178577664), // t2LDRSB_POST |
| 3369 | UINT64_C(4178578688), // t2LDRSB_PRE |
| 3370 | UINT64_C(4186963968), // t2LDRSBi12 |
| 3371 | UINT64_C(4178578432), // t2LDRSBi8 |
| 3372 | UINT64_C(4179558400), // t2LDRSBpci |
| 3373 | UINT64_C(4178575360), // t2LDRSBs |
| 3374 | UINT64_C(4180676096), // t2LDRSHT |
| 3375 | UINT64_C(4180674816), // t2LDRSH_POST |
| 3376 | UINT64_C(4180675840), // t2LDRSH_PRE |
| 3377 | UINT64_C(4189061120), // t2LDRSHi12 |
| 3378 | UINT64_C(4180675584), // t2LDRSHi8 |
| 3379 | UINT64_C(4181655552), // t2LDRSHpci |
| 3380 | UINT64_C(4180672512), // t2LDRSHs |
| 3381 | UINT64_C(4165996032), // t2LDRT |
| 3382 | UINT64_C(4165994752), // t2LDR_POST |
| 3383 | UINT64_C(4165995776), // t2LDR_PRE |
| 3384 | UINT64_C(4174381056), // t2LDRi12 |
| 3385 | UINT64_C(4165995520), // t2LDRi8 |
| 3386 | UINT64_C(4166975488), // t2LDRpci |
| 3387 | UINT64_C(4165992448), // t2LDRs |
| 3388 | UINT64_C(4029661185), // t2LE |
| 3389 | UINT64_C(4027564033), // t2LEUpdate |
| 3390 | UINT64_C(3931045888), // t2LSLri |
| 3391 | UINT64_C(4194365440), // t2LSLrr |
| 3392 | UINT64_C(3931045904), // t2LSRri |
| 3393 | UINT64_C(4196462592), // t2LSRrr |
| 3394 | UINT64_C(3932094544), // t2LSRs1 |
| 3395 | UINT64_C(3992977424), // t2MCR |
| 3396 | UINT64_C(4261412880), // t2MCR2 |
| 3397 | UINT64_C(3963617280), // t2MCRR |
| 3398 | UINT64_C(4232052736), // t2MCRR2 |
| 3399 | UINT64_C(4211081216), // t2MLA |
| 3400 | UINT64_C(4211081232), // t2MLS |
| 3401 | UINT64_C(4072669184), // t2MOVTi16 |
| 3402 | UINT64_C(4031709184), // t2MOVi |
| 3403 | UINT64_C(4064280576), // t2MOVi16 |
| 3404 | UINT64_C(3931045888), // t2MOVr |
| 3405 | UINT64_C(3994026000), // t2MRC |
| 3406 | UINT64_C(4262461456), // t2MRC2 |
| 3407 | UINT64_C(3964665856), // t2MRRC |
| 3408 | UINT64_C(4233101312), // t2MRRC2 |
| 3409 | UINT64_C(4092559360), // t2MRS_AR |
| 3410 | UINT64_C(4092559360), // t2MRS_M |
| 3411 | UINT64_C(4091576352), // t2MRSbanked |
| 3412 | UINT64_C(4093607936), // t2MRSsys_AR |
| 3413 | UINT64_C(4085284864), // t2MSR_AR |
| 3414 | UINT64_C(4085284864), // t2MSR_M |
| 3415 | UINT64_C(4085284896), // t2MSRbanked |
| 3416 | UINT64_C(4211142656), // t2MUL |
| 3417 | UINT64_C(4033806336), // t2MVNi |
| 3418 | UINT64_C(3933143040), // t2MVNr |
| 3419 | UINT64_C(3933143040), // t2MVNs |
| 3420 | UINT64_C(4032823296), // t2ORNri |
| 3421 | UINT64_C(3932160000), // t2ORNrr |
| 3422 | UINT64_C(3932160000), // t2ORNrs |
| 3423 | UINT64_C(4030726144), // t2ORRri |
| 3424 | UINT64_C(3930062848), // t2ORRrr |
| 3425 | UINT64_C(3930062848), // t2ORRrs |
| 3426 | UINT64_C(4088365085), // t2PAC |
| 3427 | UINT64_C(4088365069), // t2PACBTI |
| 3428 | UINT64_C(4217434112), // t2PACG |
| 3429 | UINT64_C(3938451456), // t2PKHBT |
| 3430 | UINT64_C(3938451488), // t2PKHTB |
| 3431 | UINT64_C(4172345344), // t2PLDWi12 |
| 3432 | UINT64_C(4163959808), // t2PLDWi8 |
| 3433 | UINT64_C(4163956736), // t2PLDWs |
| 3434 | UINT64_C(4170248192), // t2PLDi12 |
| 3435 | UINT64_C(4161862656), // t2PLDi8 |
| 3436 | UINT64_C(4162842624), // t2PLDpci |
| 3437 | UINT64_C(4161859584), // t2PLDs |
| 3438 | UINT64_C(4187025408), // t2PLIi12 |
| 3439 | UINT64_C(4178639872), // t2PLIi8 |
| 3440 | UINT64_C(4179619840), // t2PLIpci |
| 3441 | UINT64_C(4178636800), // t2PLIs |
| 3442 | UINT64_C(4202754176), // t2QADD |
| 3443 | UINT64_C(4203802640), // t2QADD16 |
| 3444 | UINT64_C(4202754064), // t2QADD8 |
| 3445 | UINT64_C(4204851216), // t2QASX |
| 3446 | UINT64_C(4202754192), // t2QDADD |
| 3447 | UINT64_C(4202754224), // t2QDSUB |
| 3448 | UINT64_C(4209045520), // t2QSAX |
| 3449 | UINT64_C(4202754208), // t2QSUB |
| 3450 | UINT64_C(4207996944), // t2QSUB16 |
| 3451 | UINT64_C(4206948368), // t2QSUB8 |
| 3452 | UINT64_C(4203802784), // t2RBIT |
| 3453 | UINT64_C(4203802752), // t2REV |
| 3454 | UINT64_C(4203802768), // t2REV16 |
| 3455 | UINT64_C(4203802800), // t2REVSH |
| 3456 | UINT64_C(3893411840), // t2RFEDB |
| 3457 | UINT64_C(3895508992), // t2RFEDBW |
| 3458 | UINT64_C(3918577664), // t2RFEIA |
| 3459 | UINT64_C(3920674816), // t2RFEIAW |
| 3460 | UINT64_C(3931045936), // t2RORri |
| 3461 | UINT64_C(4200656896), // t2RORrr |
| 3462 | UINT64_C(3931045936), // t2RRX |
| 3463 | UINT64_C(4055891968), // t2RSBri |
| 3464 | UINT64_C(3955228672), // t2RSBrr |
| 3465 | UINT64_C(3955228672), // t2RSBrs |
| 3466 | UINT64_C(4203802624), // t2SADD16 |
| 3467 | UINT64_C(4202754048), // t2SADD8 |
| 3468 | UINT64_C(4204851200), // t2SASX |
| 3469 | UINT64_C(4089417584), // t2SB |
| 3470 | UINT64_C(4049600512), // t2SBCri |
| 3471 | UINT64_C(3948937216), // t2SBCrr |
| 3472 | UINT64_C(3948937216), // t2SBCrs |
| 3473 | UINT64_C(4081057792), // t2SBFX |
| 3474 | UINT64_C(4220580080), // t2SDIV |
| 3475 | UINT64_C(4204851328), // t2SEL |
| 3476 | UINT64_C(46608), // t2SETPAN |
| 3477 | UINT64_C(3917474175), // t2SG |
| 3478 | UINT64_C(4203802656), // t2SHADD16 |
| 3479 | UINT64_C(4202754080), // t2SHADD8 |
| 3480 | UINT64_C(4204851232), // t2SHASX |
| 3481 | UINT64_C(4209045536), // t2SHSAX |
| 3482 | UINT64_C(4207996960), // t2SHSUB16 |
| 3483 | UINT64_C(4206948384), // t2SHSUB8 |
| 3484 | UINT64_C(4159733760), // t2SMC |
| 3485 | UINT64_C(4212129792), // t2SMLABB |
| 3486 | UINT64_C(4212129808), // t2SMLABT |
| 3487 | UINT64_C(4213178368), // t2SMLAD |
| 3488 | UINT64_C(4213178384), // t2SMLADX |
| 3489 | UINT64_C(4223664128), // t2SMLAL |
| 3490 | UINT64_C(4223664256), // t2SMLALBB |
| 3491 | UINT64_C(4223664272), // t2SMLALBT |
| 3492 | UINT64_C(4223664320), // t2SMLALD |
| 3493 | UINT64_C(4223664336), // t2SMLALDX |
| 3494 | UINT64_C(4223664288), // t2SMLALTB |
| 3495 | UINT64_C(4223664304), // t2SMLALTT |
| 3496 | UINT64_C(4212129824), // t2SMLATB |
| 3497 | UINT64_C(4212129840), // t2SMLATT |
| 3498 | UINT64_C(4214226944), // t2SMLAWB |
| 3499 | UINT64_C(4214226960), // t2SMLAWT |
| 3500 | UINT64_C(4215275520), // t2SMLSD |
| 3501 | UINT64_C(4215275536), // t2SMLSDX |
| 3502 | UINT64_C(4224712896), // t2SMLSLD |
| 3503 | UINT64_C(4224712912), // t2SMLSLDX |
| 3504 | UINT64_C(4216324096), // t2SMMLA |
| 3505 | UINT64_C(4216324112), // t2SMMLAR |
| 3506 | UINT64_C(4217372672), // t2SMMLS |
| 3507 | UINT64_C(4217372688), // t2SMMLSR |
| 3508 | UINT64_C(4216385536), // t2SMMUL |
| 3509 | UINT64_C(4216385552), // t2SMMULR |
| 3510 | UINT64_C(4213239808), // t2SMUAD |
| 3511 | UINT64_C(4213239824), // t2SMUADX |
| 3512 | UINT64_C(4212191232), // t2SMULBB |
| 3513 | UINT64_C(4212191248), // t2SMULBT |
| 3514 | UINT64_C(4219469824), // t2SMULL |
| 3515 | UINT64_C(4212191264), // t2SMULTB |
| 3516 | UINT64_C(4212191280), // t2SMULTT |
| 3517 | UINT64_C(4214288384), // t2SMULWB |
| 3518 | UINT64_C(4214288400), // t2SMULWT |
| 3519 | UINT64_C(4215336960), // t2SMUSD |
| 3520 | UINT64_C(4215336976), // t2SMUSDX |
| 3521 | UINT64_C(3893215232), // t2SRSDB |
| 3522 | UINT64_C(3895312384), // t2SRSDB_UPD |
| 3523 | UINT64_C(3918381056), // t2SRSIA |
| 3524 | UINT64_C(3920478208), // t2SRSIA_UPD |
| 3525 | UINT64_C(4076863488), // t2SSAT |
| 3526 | UINT64_C(4078960640), // t2SSAT16 |
| 3527 | UINT64_C(4209045504), // t2SSAX |
| 3528 | UINT64_C(4207996928), // t2SSUB16 |
| 3529 | UINT64_C(4206948352), // t2SSUB8 |
| 3530 | UINT64_C(4248829952), // t2STC2L_OFFSET |
| 3531 | UINT64_C(4240441344), // t2STC2L_OPTION |
| 3532 | UINT64_C(4234149888), // t2STC2L_POST |
| 3533 | UINT64_C(4250927104), // t2STC2L_PRE |
| 3534 | UINT64_C(4244635648), // t2STC2_OFFSET |
| 3535 | UINT64_C(4236247040), // t2STC2_OPTION |
| 3536 | UINT64_C(4229955584), // t2STC2_POST |
| 3537 | UINT64_C(4246732800), // t2STC2_PRE |
| 3538 | UINT64_C(3980394496), // t2STCL_OFFSET |
| 3539 | UINT64_C(3972005888), // t2STCL_OPTION |
| 3540 | UINT64_C(3965714432), // t2STCL_POST |
| 3541 | UINT64_C(3982491648), // t2STCL_PRE |
| 3542 | UINT64_C(3976200192), // t2STC_OFFSET |
| 3543 | UINT64_C(3967811584), // t2STC_OPTION |
| 3544 | UINT64_C(3961520128), // t2STC_POST |
| 3545 | UINT64_C(3978297344), // t2STC_PRE |
| 3546 | UINT64_C(3904901039), // t2STL |
| 3547 | UINT64_C(3904901007), // t2STLB |
| 3548 | UINT64_C(3904901088), // t2STLEX |
| 3549 | UINT64_C(3904901056), // t2STLEXB |
| 3550 | UINT64_C(3904897264), // t2STLEXD |
| 3551 | UINT64_C(3904901072), // t2STLEXH |
| 3552 | UINT64_C(3904901023), // t2STLH |
| 3553 | UINT64_C(3909091328), // t2STMDB |
| 3554 | UINT64_C(3911188480), // t2STMDB_UPD |
| 3555 | UINT64_C(3900702720), // t2STMIA |
| 3556 | UINT64_C(3902799872), // t2STMIA_UPD |
| 3557 | UINT64_C(4160753152), // t2STRBT |
| 3558 | UINT64_C(4160751872), // t2STRB_POST |
| 3559 | UINT64_C(4160752896), // t2STRB_PRE |
| 3560 | UINT64_C(4169138176), // t2STRBi12 |
| 3561 | UINT64_C(4160752640), // t2STRBi8 |
| 3562 | UINT64_C(4160749568), // t2STRBs |
| 3563 | UINT64_C(3898605568), // t2STRD_POST |
| 3564 | UINT64_C(3915382784), // t2STRD_PRE |
| 3565 | UINT64_C(3913285632), // t2STRDi8 |
| 3566 | UINT64_C(3896508416), // t2STREX |
| 3567 | UINT64_C(3904900928), // t2STREXB |
| 3568 | UINT64_C(3904897136), // t2STREXD |
| 3569 | UINT64_C(3904900944), // t2STREXH |
| 3570 | UINT64_C(4162850304), // t2STRHT |
| 3571 | UINT64_C(4162849024), // t2STRH_POST |
| 3572 | UINT64_C(4162850048), // t2STRH_PRE |
| 3573 | UINT64_C(4171235328), // t2STRHi12 |
| 3574 | UINT64_C(4162849792), // t2STRHi8 |
| 3575 | UINT64_C(4162846720), // t2STRHs |
| 3576 | UINT64_C(4164947456), // t2STRT |
| 3577 | UINT64_C(4164946176), // t2STR_POST |
| 3578 | UINT64_C(4164947200), // t2STR_PRE |
| 3579 | UINT64_C(4173332480), // t2STRi12 |
| 3580 | UINT64_C(4164946944), // t2STRi8 |
| 3581 | UINT64_C(4164943872), // t2STRs |
| 3582 | UINT64_C(4091449088), // t2SUBS_PC_LR |
| 3583 | UINT64_C(4053794816), // t2SUBri |
| 3584 | UINT64_C(4070572032), // t2SUBri12 |
| 3585 | UINT64_C(3953131520), // t2SUBrr |
| 3586 | UINT64_C(3953131520), // t2SUBrs |
| 3587 | UINT64_C(4054650112), // t2SUBspImm |
| 3588 | UINT64_C(4071427328), // t2SUBspImm12 |
| 3589 | UINT64_C(4198559872), // t2SXTAB |
| 3590 | UINT64_C(4196462720), // t2SXTAB16 |
| 3591 | UINT64_C(4194365568), // t2SXTAH |
| 3592 | UINT64_C(4199542912), // t2SXTB |
| 3593 | UINT64_C(4197445760), // t2SXTB16 |
| 3594 | UINT64_C(4195348608), // t2SXTH |
| 3595 | UINT64_C(3906007040), // t2TBB |
| 3596 | UINT64_C(3906007056), // t2TBH |
| 3597 | UINT64_C(4035972864), // t2TEQri |
| 3598 | UINT64_C(3935309568), // t2TEQrr |
| 3599 | UINT64_C(3935309568), // t2TEQrs |
| 3600 | UINT64_C(4088365074), // t2TSB |
| 3601 | UINT64_C(4027584256), // t2TSTri |
| 3602 | UINT64_C(3926920960), // t2TSTrr |
| 3603 | UINT64_C(3926920960), // t2TSTrs |
| 3604 | UINT64_C(3896569856), // t2TT |
| 3605 | UINT64_C(3896569984), // t2TTA |
| 3606 | UINT64_C(3896570048), // t2TTAT |
| 3607 | UINT64_C(3896569920), // t2TTT |
| 3608 | UINT64_C(4203802688), // t2UADD16 |
| 3609 | UINT64_C(4202754112), // t2UADD8 |
| 3610 | UINT64_C(4204851264), // t2UASX |
| 3611 | UINT64_C(4089446400), // t2UBFX |
| 3612 | UINT64_C(4159741952), // t2UDF |
| 3613 | UINT64_C(4222677232), // t2UDIV |
| 3614 | UINT64_C(4203802720), // t2UHADD16 |
| 3615 | UINT64_C(4202754144), // t2UHADD8 |
| 3616 | UINT64_C(4204851296), // t2UHASX |
| 3617 | UINT64_C(4209045600), // t2UHSAX |
| 3618 | UINT64_C(4207997024), // t2UHSUB16 |
| 3619 | UINT64_C(4206948448), // t2UHSUB8 |
| 3620 | UINT64_C(4225761376), // t2UMAAL |
| 3621 | UINT64_C(4225761280), // t2UMLAL |
| 3622 | UINT64_C(4221566976), // t2UMULL |
| 3623 | UINT64_C(4203802704), // t2UQADD16 |
| 3624 | UINT64_C(4202754128), // t2UQADD8 |
| 3625 | UINT64_C(4204851280), // t2UQASX |
| 3626 | UINT64_C(4209045584), // t2UQSAX |
| 3627 | UINT64_C(4207997008), // t2UQSUB16 |
| 3628 | UINT64_C(4206948432), // t2UQSUB8 |
| 3629 | UINT64_C(4218482688), // t2USAD8 |
| 3630 | UINT64_C(4218421248), // t2USADA8 |
| 3631 | UINT64_C(4085252096), // t2USAT |
| 3632 | UINT64_C(4087349248), // t2USAT16 |
| 3633 | UINT64_C(4209045568), // t2USAX |
| 3634 | UINT64_C(4207996992), // t2USUB16 |
| 3635 | UINT64_C(4206948416), // t2USUB8 |
| 3636 | UINT64_C(4199608448), // t2UXTAB |
| 3637 | UINT64_C(4197511296), // t2UXTAB16 |
| 3638 | UINT64_C(4195414144), // t2UXTAH |
| 3639 | UINT64_C(4200591488), // t2UXTB |
| 3640 | UINT64_C(4198494336), // t2UXTB16 |
| 3641 | UINT64_C(4196397184), // t2UXTH |
| 3642 | UINT64_C(4030775297), // t2WLS |
| 3643 | UINT64_C(16704), // tADC |
| 3644 | UINT64_C(17408), // tADDhirr |
| 3645 | UINT64_C(7168), // tADDi3 |
| 3646 | UINT64_C(12288), // tADDi8 |
| 3647 | UINT64_C(17512), // tADDrSP |
| 3648 | UINT64_C(43008), // tADDrSPi |
| 3649 | UINT64_C(6144), // tADDrr |
| 3650 | UINT64_C(45056), // tADDspi |
| 3651 | UINT64_C(17541), // tADDspr |
| 3652 | UINT64_C(40960), // tADR |
| 3653 | UINT64_C(16384), // tAND |
| 3654 | UINT64_C(4096), // tASRri |
| 3655 | UINT64_C(16640), // tASRrr |
| 3656 | UINT64_C(57344), // tB |
| 3657 | UINT64_C(17280), // tBIC |
| 3658 | UINT64_C(48640), // tBKPT |
| 3659 | UINT64_C(4026585088), // tBL |
| 3660 | UINT64_C(18308), // tBLXNSr |
| 3661 | UINT64_C(4026580992), // tBLXi |
| 3662 | UINT64_C(18304), // tBLXr |
| 3663 | UINT64_C(18176), // tBX |
| 3664 | UINT64_C(18180), // tBXNS |
| 3665 | UINT64_C(53248), // tBcc |
| 3666 | UINT64_C(47360), // tCBNZ |
| 3667 | UINT64_C(45312), // tCBZ |
| 3668 | UINT64_C(17088), // tCMNz |
| 3669 | UINT64_C(17664), // tCMPhir |
| 3670 | UINT64_C(10240), // tCMPi8 |
| 3671 | UINT64_C(17024), // tCMPr |
| 3672 | UINT64_C(46688), // tCPS |
| 3673 | UINT64_C(16448), // tEOR |
| 3674 | UINT64_C(48896), // tHINT |
| 3675 | UINT64_C(47744), // tHLT |
| 3676 | UINT64_C(0), // tInt_WIN_eh_sjlj_longjmp |
| 3677 | UINT64_C(0), // tInt_eh_sjlj_longjmp |
| 3678 | UINT64_C(0), // tInt_eh_sjlj_setjmp |
| 3679 | UINT64_C(51200), // tLDMIA |
| 3680 | UINT64_C(30720), // tLDRBi |
| 3681 | UINT64_C(23552), // tLDRBr |
| 3682 | UINT64_C(34816), // tLDRHi |
| 3683 | UINT64_C(23040), // tLDRHr |
| 3684 | UINT64_C(22016), // tLDRSB |
| 3685 | UINT64_C(24064), // tLDRSH |
| 3686 | UINT64_C(26624), // tLDRi |
| 3687 | UINT64_C(18432), // tLDRpci |
| 3688 | UINT64_C(22528), // tLDRr |
| 3689 | UINT64_C(38912), // tLDRspi |
| 3690 | UINT64_C(0), // tLSLri |
| 3691 | UINT64_C(16512), // tLSLrr |
| 3692 | UINT64_C(2048), // tLSRri |
| 3693 | UINT64_C(16576), // tLSRrr |
| 3694 | UINT64_C(0), // tMOVSr |
| 3695 | UINT64_C(8192), // tMOVi8 |
| 3696 | UINT64_C(17920), // tMOVr |
| 3697 | UINT64_C(17216), // tMUL |
| 3698 | UINT64_C(17344), // tMVN |
| 3699 | UINT64_C(17152), // tORR |
| 3700 | UINT64_C(17528), // tPICADD |
| 3701 | UINT64_C(48128), // tPOP |
| 3702 | UINT64_C(46080), // tPUSH |
| 3703 | UINT64_C(47616), // tREV |
| 3704 | UINT64_C(47680), // tREV16 |
| 3705 | UINT64_C(47808), // tREVSH |
| 3706 | UINT64_C(16832), // tROR |
| 3707 | UINT64_C(16960), // tRSB |
| 3708 | UINT64_C(16768), // tSBC |
| 3709 | UINT64_C(46672), // tSETEND |
| 3710 | UINT64_C(49152), // tSTMIA_UPD |
| 3711 | UINT64_C(28672), // tSTRBi |
| 3712 | UINT64_C(21504), // tSTRBr |
| 3713 | UINT64_C(32768), // tSTRHi |
| 3714 | UINT64_C(20992), // tSTRHr |
| 3715 | UINT64_C(24576), // tSTRi |
| 3716 | UINT64_C(20480), // tSTRr |
| 3717 | UINT64_C(36864), // tSTRspi |
| 3718 | UINT64_C(7680), // tSUBi3 |
| 3719 | UINT64_C(14336), // tSUBi8 |
| 3720 | UINT64_C(6656), // tSUBrr |
| 3721 | UINT64_C(45184), // tSUBspi |
| 3722 | UINT64_C(57088), // tSVC |
| 3723 | UINT64_C(45632), // tSXTB |
| 3724 | UINT64_C(45568), // tSXTH |
| 3725 | UINT64_C(57086), // tTRAP |
| 3726 | UINT64_C(16896), // tTST |
| 3727 | UINT64_C(56832), // tUDF |
| 3728 | UINT64_C(45760), // tUXTB |
| 3729 | UINT64_C(45696), // tUXTH |
| 3730 | UINT64_C(57081), // t__brkdiv0 |
| 3731 | }; |
| 3732 | constexpr unsigned FirstSupportedOpcode = 802; |
| 3733 | |
| 3734 | const unsigned opcode = MI.getOpcode(); |
| 3735 | if (opcode < FirstSupportedOpcode) |
| 3736 | reportUnsupportedInst(Inst: MI); |
| 3737 | unsigned TableIndex = opcode - FirstSupportedOpcode; |
| 3738 | uint64_t Value = InstBits[TableIndex]; |
| 3739 | uint64_t op = 0; |
| 3740 | (void)op; // suppress warning |
| 3741 | switch (opcode) { |
| 3742 | case ARM::CLREX: |
| 3743 | case ARM::MVE_LCTP: |
| 3744 | case ARM::MVE_VPNOT: |
| 3745 | case ARM::SB: |
| 3746 | case ARM::TRAP: |
| 3747 | case ARM::TSB: |
| 3748 | case ARM::VBSPd: |
| 3749 | case ARM::VBSPq: |
| 3750 | case ARM::VLD1LNq16Pseudo: |
| 3751 | case ARM::VLD1LNq16Pseudo_UPD: |
| 3752 | case ARM::VLD1LNq32Pseudo: |
| 3753 | case ARM::VLD1LNq32Pseudo_UPD: |
| 3754 | case ARM::VLD1LNq8Pseudo: |
| 3755 | case ARM::VLD1LNq8Pseudo_UPD: |
| 3756 | case ARM::VLD1d16QPseudo: |
| 3757 | case ARM::VLD1d16QPseudoWB_fixed: |
| 3758 | case ARM::VLD1d16QPseudoWB_register: |
| 3759 | case ARM::VLD1d16TPseudo: |
| 3760 | case ARM::VLD1d16TPseudoWB_fixed: |
| 3761 | case ARM::VLD1d16TPseudoWB_register: |
| 3762 | case ARM::VLD1d32QPseudo: |
| 3763 | case ARM::VLD1d32QPseudoWB_fixed: |
| 3764 | case ARM::VLD1d32QPseudoWB_register: |
| 3765 | case ARM::VLD1d32TPseudo: |
| 3766 | case ARM::VLD1d32TPseudoWB_fixed: |
| 3767 | case ARM::VLD1d32TPseudoWB_register: |
| 3768 | case ARM::VLD1d64QPseudo: |
| 3769 | case ARM::VLD1d64QPseudoWB_fixed: |
| 3770 | case ARM::VLD1d64QPseudoWB_register: |
| 3771 | case ARM::VLD1d64TPseudo: |
| 3772 | case ARM::VLD1d64TPseudoWB_fixed: |
| 3773 | case ARM::VLD1d64TPseudoWB_register: |
| 3774 | case ARM::VLD1d8QPseudo: |
| 3775 | case ARM::VLD1d8QPseudoWB_fixed: |
| 3776 | case ARM::VLD1d8QPseudoWB_register: |
| 3777 | case ARM::VLD1d8TPseudo: |
| 3778 | case ARM::VLD1d8TPseudoWB_fixed: |
| 3779 | case ARM::VLD1d8TPseudoWB_register: |
| 3780 | case ARM::VLD1q16HighQPseudo: |
| 3781 | case ARM::VLD1q16HighQPseudo_UPD: |
| 3782 | case ARM::VLD1q16HighTPseudo: |
| 3783 | case ARM::VLD1q16HighTPseudo_UPD: |
| 3784 | case ARM::VLD1q16LowQPseudo_UPD: |
| 3785 | case ARM::VLD1q16LowTPseudo_UPD: |
| 3786 | case ARM::VLD1q32HighQPseudo: |
| 3787 | case ARM::VLD1q32HighQPseudo_UPD: |
| 3788 | case ARM::VLD1q32HighTPseudo: |
| 3789 | case ARM::VLD1q32HighTPseudo_UPD: |
| 3790 | case ARM::VLD1q32LowQPseudo_UPD: |
| 3791 | case ARM::VLD1q32LowTPseudo_UPD: |
| 3792 | case ARM::VLD1q64HighQPseudo: |
| 3793 | case ARM::VLD1q64HighQPseudo_UPD: |
| 3794 | case ARM::VLD1q64HighTPseudo: |
| 3795 | case ARM::VLD1q64HighTPseudo_UPD: |
| 3796 | case ARM::VLD1q64LowQPseudo_UPD: |
| 3797 | case ARM::VLD1q64LowTPseudo_UPD: |
| 3798 | case ARM::VLD1q8HighQPseudo: |
| 3799 | case ARM::VLD1q8HighQPseudo_UPD: |
| 3800 | case ARM::VLD1q8HighTPseudo: |
| 3801 | case ARM::VLD1q8HighTPseudo_UPD: |
| 3802 | case ARM::VLD1q8LowQPseudo_UPD: |
| 3803 | case ARM::VLD1q8LowTPseudo_UPD: |
| 3804 | case ARM::VLD2DUPq16EvenPseudo: |
| 3805 | case ARM::VLD2DUPq16OddPseudo: |
| 3806 | case ARM::VLD2DUPq16OddPseudoWB_fixed: |
| 3807 | case ARM::VLD2DUPq16OddPseudoWB_register: |
| 3808 | case ARM::VLD2DUPq32EvenPseudo: |
| 3809 | case ARM::VLD2DUPq32OddPseudo: |
| 3810 | case ARM::VLD2DUPq32OddPseudoWB_fixed: |
| 3811 | case ARM::VLD2DUPq32OddPseudoWB_register: |
| 3812 | case ARM::VLD2DUPq8EvenPseudo: |
| 3813 | case ARM::VLD2DUPq8OddPseudo: |
| 3814 | case ARM::VLD2DUPq8OddPseudoWB_fixed: |
| 3815 | case ARM::VLD2DUPq8OddPseudoWB_register: |
| 3816 | case ARM::VLD2LNd16Pseudo: |
| 3817 | case ARM::VLD2LNd16Pseudo_UPD: |
| 3818 | case ARM::VLD2LNd32Pseudo: |
| 3819 | case ARM::VLD2LNd32Pseudo_UPD: |
| 3820 | case ARM::VLD2LNd8Pseudo: |
| 3821 | case ARM::VLD2LNd8Pseudo_UPD: |
| 3822 | case ARM::VLD2LNq16Pseudo: |
| 3823 | case ARM::VLD2LNq16Pseudo_UPD: |
| 3824 | case ARM::VLD2LNq32Pseudo: |
| 3825 | case ARM::VLD2LNq32Pseudo_UPD: |
| 3826 | case ARM::VLD2q16Pseudo: |
| 3827 | case ARM::VLD2q16PseudoWB_fixed: |
| 3828 | case ARM::VLD2q16PseudoWB_register: |
| 3829 | case ARM::VLD2q32Pseudo: |
| 3830 | case ARM::VLD2q32PseudoWB_fixed: |
| 3831 | case ARM::VLD2q32PseudoWB_register: |
| 3832 | case ARM::VLD2q8Pseudo: |
| 3833 | case ARM::VLD2q8PseudoWB_fixed: |
| 3834 | case ARM::VLD2q8PseudoWB_register: |
| 3835 | case ARM::VLD3DUPd16Pseudo: |
| 3836 | case ARM::VLD3DUPd16Pseudo_UPD: |
| 3837 | case ARM::VLD3DUPd32Pseudo: |
| 3838 | case ARM::VLD3DUPd32Pseudo_UPD: |
| 3839 | case ARM::VLD3DUPd8Pseudo: |
| 3840 | case ARM::VLD3DUPd8Pseudo_UPD: |
| 3841 | case ARM::VLD3DUPq16EvenPseudo: |
| 3842 | case ARM::VLD3DUPq16OddPseudo: |
| 3843 | case ARM::VLD3DUPq16OddPseudo_UPD: |
| 3844 | case ARM::VLD3DUPq32EvenPseudo: |
| 3845 | case ARM::VLD3DUPq32OddPseudo: |
| 3846 | case ARM::VLD3DUPq32OddPseudo_UPD: |
| 3847 | case ARM::VLD3DUPq8EvenPseudo: |
| 3848 | case ARM::VLD3DUPq8OddPseudo: |
| 3849 | case ARM::VLD3DUPq8OddPseudo_UPD: |
| 3850 | case ARM::VLD3LNd16Pseudo: |
| 3851 | case ARM::VLD3LNd16Pseudo_UPD: |
| 3852 | case ARM::VLD3LNd32Pseudo: |
| 3853 | case ARM::VLD3LNd32Pseudo_UPD: |
| 3854 | case ARM::VLD3LNd8Pseudo: |
| 3855 | case ARM::VLD3LNd8Pseudo_UPD: |
| 3856 | case ARM::VLD3LNq16Pseudo: |
| 3857 | case ARM::VLD3LNq16Pseudo_UPD: |
| 3858 | case ARM::VLD3LNq32Pseudo: |
| 3859 | case ARM::VLD3LNq32Pseudo_UPD: |
| 3860 | case ARM::VLD3d16Pseudo: |
| 3861 | case ARM::VLD3d16Pseudo_UPD: |
| 3862 | case ARM::VLD3d32Pseudo: |
| 3863 | case ARM::VLD3d32Pseudo_UPD: |
| 3864 | case ARM::VLD3d8Pseudo: |
| 3865 | case ARM::VLD3d8Pseudo_UPD: |
| 3866 | case ARM::VLD3q16Pseudo_UPD: |
| 3867 | case ARM::VLD3q16oddPseudo: |
| 3868 | case ARM::VLD3q16oddPseudo_UPD: |
| 3869 | case ARM::VLD3q32Pseudo_UPD: |
| 3870 | case ARM::VLD3q32oddPseudo: |
| 3871 | case ARM::VLD3q32oddPseudo_UPD: |
| 3872 | case ARM::VLD3q8Pseudo_UPD: |
| 3873 | case ARM::VLD3q8oddPseudo: |
| 3874 | case ARM::VLD3q8oddPseudo_UPD: |
| 3875 | case ARM::VLD4DUPd16Pseudo: |
| 3876 | case ARM::VLD4DUPd16Pseudo_UPD: |
| 3877 | case ARM::VLD4DUPd32Pseudo: |
| 3878 | case ARM::VLD4DUPd32Pseudo_UPD: |
| 3879 | case ARM::VLD4DUPd8Pseudo: |
| 3880 | case ARM::VLD4DUPd8Pseudo_UPD: |
| 3881 | case ARM::VLD4DUPq16EvenPseudo: |
| 3882 | case ARM::VLD4DUPq16OddPseudo: |
| 3883 | case ARM::VLD4DUPq16OddPseudo_UPD: |
| 3884 | case ARM::VLD4DUPq32EvenPseudo: |
| 3885 | case ARM::VLD4DUPq32OddPseudo: |
| 3886 | case ARM::VLD4DUPq32OddPseudo_UPD: |
| 3887 | case ARM::VLD4DUPq8EvenPseudo: |
| 3888 | case ARM::VLD4DUPq8OddPseudo: |
| 3889 | case ARM::VLD4DUPq8OddPseudo_UPD: |
| 3890 | case ARM::VLD4LNd16Pseudo: |
| 3891 | case ARM::VLD4LNd16Pseudo_UPD: |
| 3892 | case ARM::VLD4LNd32Pseudo: |
| 3893 | case ARM::VLD4LNd32Pseudo_UPD: |
| 3894 | case ARM::VLD4LNd8Pseudo: |
| 3895 | case ARM::VLD4LNd8Pseudo_UPD: |
| 3896 | case ARM::VLD4LNq16Pseudo: |
| 3897 | case ARM::VLD4LNq16Pseudo_UPD: |
| 3898 | case ARM::VLD4LNq32Pseudo: |
| 3899 | case ARM::VLD4LNq32Pseudo_UPD: |
| 3900 | case ARM::VLD4d16Pseudo: |
| 3901 | case ARM::VLD4d16Pseudo_UPD: |
| 3902 | case ARM::VLD4d32Pseudo: |
| 3903 | case ARM::VLD4d32Pseudo_UPD: |
| 3904 | case ARM::VLD4d8Pseudo: |
| 3905 | case ARM::VLD4d8Pseudo_UPD: |
| 3906 | case ARM::VLD4q16Pseudo_UPD: |
| 3907 | case ARM::VLD4q16oddPseudo: |
| 3908 | case ARM::VLD4q16oddPseudo_UPD: |
| 3909 | case ARM::VLD4q32Pseudo_UPD: |
| 3910 | case ARM::VLD4q32oddPseudo: |
| 3911 | case ARM::VLD4q32oddPseudo_UPD: |
| 3912 | case ARM::VLD4q8Pseudo_UPD: |
| 3913 | case ARM::VLD4q8oddPseudo: |
| 3914 | case ARM::VLD4q8oddPseudo_UPD: |
| 3915 | case ARM::VLDMQIA: |
| 3916 | case ARM::VST1LNq16Pseudo: |
| 3917 | case ARM::VST1LNq16Pseudo_UPD: |
| 3918 | case ARM::VST1LNq32Pseudo: |
| 3919 | case ARM::VST1LNq32Pseudo_UPD: |
| 3920 | case ARM::VST1LNq8Pseudo: |
| 3921 | case ARM::VST1LNq8Pseudo_UPD: |
| 3922 | case ARM::VST1d16QPseudo: |
| 3923 | case ARM::VST1d16QPseudoWB_fixed: |
| 3924 | case ARM::VST1d16QPseudoWB_register: |
| 3925 | case ARM::VST1d16TPseudo: |
| 3926 | case ARM::VST1d16TPseudoWB_fixed: |
| 3927 | case ARM::VST1d16TPseudoWB_register: |
| 3928 | case ARM::VST1d32QPseudo: |
| 3929 | case ARM::VST1d32QPseudoWB_fixed: |
| 3930 | case ARM::VST1d32QPseudoWB_register: |
| 3931 | case ARM::VST1d32TPseudo: |
| 3932 | case ARM::VST1d32TPseudoWB_fixed: |
| 3933 | case ARM::VST1d32TPseudoWB_register: |
| 3934 | case ARM::VST1d64QPseudo: |
| 3935 | case ARM::VST1d64QPseudoWB_fixed: |
| 3936 | case ARM::VST1d64QPseudoWB_register: |
| 3937 | case ARM::VST1d64TPseudo: |
| 3938 | case ARM::VST1d64TPseudoWB_fixed: |
| 3939 | case ARM::VST1d64TPseudoWB_register: |
| 3940 | case ARM::VST1d8QPseudo: |
| 3941 | case ARM::VST1d8QPseudoWB_fixed: |
| 3942 | case ARM::VST1d8QPseudoWB_register: |
| 3943 | case ARM::VST1d8TPseudo: |
| 3944 | case ARM::VST1d8TPseudoWB_fixed: |
| 3945 | case ARM::VST1d8TPseudoWB_register: |
| 3946 | case ARM::VST1q16HighQPseudo: |
| 3947 | case ARM::VST1q16HighQPseudo_UPD: |
| 3948 | case ARM::VST1q16HighTPseudo: |
| 3949 | case ARM::VST1q16HighTPseudo_UPD: |
| 3950 | case ARM::VST1q16LowQPseudo_UPD: |
| 3951 | case ARM::VST1q16LowTPseudo_UPD: |
| 3952 | case ARM::VST1q32HighQPseudo: |
| 3953 | case ARM::VST1q32HighQPseudo_UPD: |
| 3954 | case ARM::VST1q32HighTPseudo: |
| 3955 | case ARM::VST1q32HighTPseudo_UPD: |
| 3956 | case ARM::VST1q32LowQPseudo_UPD: |
| 3957 | case ARM::VST1q32LowTPseudo_UPD: |
| 3958 | case ARM::VST1q64HighQPseudo: |
| 3959 | case ARM::VST1q64HighQPseudo_UPD: |
| 3960 | case ARM::VST1q64HighTPseudo: |
| 3961 | case ARM::VST1q64HighTPseudo_UPD: |
| 3962 | case ARM::VST1q64LowQPseudo_UPD: |
| 3963 | case ARM::VST1q64LowTPseudo_UPD: |
| 3964 | case ARM::VST1q8HighQPseudo: |
| 3965 | case ARM::VST1q8HighQPseudo_UPD: |
| 3966 | case ARM::VST1q8HighTPseudo: |
| 3967 | case ARM::VST1q8HighTPseudo_UPD: |
| 3968 | case ARM::VST1q8LowQPseudo_UPD: |
| 3969 | case ARM::VST1q8LowTPseudo_UPD: |
| 3970 | case ARM::VST2LNd16Pseudo: |
| 3971 | case ARM::VST2LNd16Pseudo_UPD: |
| 3972 | case ARM::VST2LNd32Pseudo: |
| 3973 | case ARM::VST2LNd32Pseudo_UPD: |
| 3974 | case ARM::VST2LNd8Pseudo: |
| 3975 | case ARM::VST2LNd8Pseudo_UPD: |
| 3976 | case ARM::VST2LNq16Pseudo: |
| 3977 | case ARM::VST2LNq16Pseudo_UPD: |
| 3978 | case ARM::VST2LNq32Pseudo: |
| 3979 | case ARM::VST2LNq32Pseudo_UPD: |
| 3980 | case ARM::VST2q16Pseudo: |
| 3981 | case ARM::VST2q16PseudoWB_fixed: |
| 3982 | case ARM::VST2q16PseudoWB_register: |
| 3983 | case ARM::VST2q32Pseudo: |
| 3984 | case ARM::VST2q32PseudoWB_fixed: |
| 3985 | case ARM::VST2q32PseudoWB_register: |
| 3986 | case ARM::VST2q8Pseudo: |
| 3987 | case ARM::VST2q8PseudoWB_fixed: |
| 3988 | case ARM::VST2q8PseudoWB_register: |
| 3989 | case ARM::VST3LNd16Pseudo: |
| 3990 | case ARM::VST3LNd16Pseudo_UPD: |
| 3991 | case ARM::VST3LNd32Pseudo: |
| 3992 | case ARM::VST3LNd32Pseudo_UPD: |
| 3993 | case ARM::VST3LNd8Pseudo: |
| 3994 | case ARM::VST3LNd8Pseudo_UPD: |
| 3995 | case ARM::VST3LNq16Pseudo: |
| 3996 | case ARM::VST3LNq16Pseudo_UPD: |
| 3997 | case ARM::VST3LNq32Pseudo: |
| 3998 | case ARM::VST3LNq32Pseudo_UPD: |
| 3999 | case ARM::VST3d16Pseudo: |
| 4000 | case ARM::VST3d16Pseudo_UPD: |
| 4001 | case ARM::VST3d32Pseudo: |
| 4002 | case ARM::VST3d32Pseudo_UPD: |
| 4003 | case ARM::VST3d8Pseudo: |
| 4004 | case ARM::VST3d8Pseudo_UPD: |
| 4005 | case ARM::VST3q16Pseudo_UPD: |
| 4006 | case ARM::VST3q16oddPseudo: |
| 4007 | case ARM::VST3q16oddPseudo_UPD: |
| 4008 | case ARM::VST3q32Pseudo_UPD: |
| 4009 | case ARM::VST3q32oddPseudo: |
| 4010 | case ARM::VST3q32oddPseudo_UPD: |
| 4011 | case ARM::VST3q8Pseudo_UPD: |
| 4012 | case ARM::VST3q8oddPseudo: |
| 4013 | case ARM::VST3q8oddPseudo_UPD: |
| 4014 | case ARM::VST4LNd16Pseudo: |
| 4015 | case ARM::VST4LNd16Pseudo_UPD: |
| 4016 | case ARM::VST4LNd32Pseudo: |
| 4017 | case ARM::VST4LNd32Pseudo_UPD: |
| 4018 | case ARM::VST4LNd8Pseudo: |
| 4019 | case ARM::VST4LNd8Pseudo_UPD: |
| 4020 | case ARM::VST4LNq16Pseudo: |
| 4021 | case ARM::VST4LNq16Pseudo_UPD: |
| 4022 | case ARM::VST4LNq32Pseudo: |
| 4023 | case ARM::VST4LNq32Pseudo_UPD: |
| 4024 | case ARM::VST4d16Pseudo: |
| 4025 | case ARM::VST4d16Pseudo_UPD: |
| 4026 | case ARM::VST4d32Pseudo: |
| 4027 | case ARM::VST4d32Pseudo_UPD: |
| 4028 | case ARM::VST4d8Pseudo: |
| 4029 | case ARM::VST4d8Pseudo_UPD: |
| 4030 | case ARM::VST4q16Pseudo_UPD: |
| 4031 | case ARM::VST4q16oddPseudo: |
| 4032 | case ARM::VST4q16oddPseudo_UPD: |
| 4033 | case ARM::VST4q32Pseudo_UPD: |
| 4034 | case ARM::VST4q32oddPseudo: |
| 4035 | case ARM::VST4q32oddPseudo_UPD: |
| 4036 | case ARM::VST4q8Pseudo_UPD: |
| 4037 | case ARM::VST4q8oddPseudo: |
| 4038 | case ARM::VST4q8oddPseudo_UPD: |
| 4039 | case ARM::VSTMQIA: |
| 4040 | case ARM::VTBL3Pseudo: |
| 4041 | case ARM::VTBL4Pseudo: |
| 4042 | case ARM::VTBX3Pseudo: |
| 4043 | case ARM::VTBX4Pseudo: |
| 4044 | case ARM::t2AUT: |
| 4045 | case ARM::t2BTI: |
| 4046 | case ARM::t2CLREX: |
| 4047 | case ARM::t2DCPS1: |
| 4048 | case ARM::t2DCPS2: |
| 4049 | case ARM::t2DCPS3: |
| 4050 | case ARM::t2Int_eh_sjlj_setjmp: |
| 4051 | case ARM::t2Int_eh_sjlj_setjmp_nofp: |
| 4052 | case ARM::t2PAC: |
| 4053 | case ARM::t2PACBTI: |
| 4054 | case ARM::t2SB: |
| 4055 | case ARM::t2SG: |
| 4056 | case ARM::t2TSB: |
| 4057 | case ARM::tInt_WIN_eh_sjlj_longjmp: |
| 4058 | case ARM::tInt_eh_sjlj_longjmp: |
| 4059 | case ARM::tInt_eh_sjlj_setjmp: |
| 4060 | case ARM::tTRAP: |
| 4061 | case ARM::t__brkdiv0: { |
| 4062 | break; |
| 4063 | } |
| 4064 | case ARM::VRINTAD: |
| 4065 | case ARM::VRINTMD: |
| 4066 | case ARM::VRINTND: |
| 4067 | case ARM::VRINTPD: { |
| 4068 | // op: Dd |
| 4069 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4070 | Value |= (op & 0x10) << 18; |
| 4071 | Value |= (op & 0xf) << 12; |
| 4072 | // op: Dm |
| 4073 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4074 | Value |= (op & 0x10) << 1; |
| 4075 | Value |= (op & 0xf); |
| 4076 | break; |
| 4077 | } |
| 4078 | case ARM::VFP_VMAXNMD: |
| 4079 | case ARM::VFP_VMINNMD: |
| 4080 | case ARM::VSELEQD: |
| 4081 | case ARM::VSELGED: |
| 4082 | case ARM::VSELGTD: |
| 4083 | case ARM::VSELVSD: { |
| 4084 | // op: Dd |
| 4085 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4086 | Value |= (op & 0x10) << 18; |
| 4087 | Value |= (op & 0xf) << 12; |
| 4088 | // op: Dn |
| 4089 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4090 | Value |= (op & 0xf) << 16; |
| 4091 | Value |= (op & 0x10) << 3; |
| 4092 | // op: Dm |
| 4093 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4094 | Value |= (op & 0x10) << 1; |
| 4095 | Value |= (op & 0xf); |
| 4096 | break; |
| 4097 | } |
| 4098 | case ARM::MVE_VPST: { |
| 4099 | // op: Mk |
| 4100 | op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI); |
| 4101 | Value |= (op & 0x8) << 19; |
| 4102 | Value |= (op & 0x7) << 13; |
| 4103 | break; |
| 4104 | } |
| 4105 | case ARM::MVE_VLDRWU32_qi: |
| 4106 | case ARM::MVE_VSTRW32_qi: { |
| 4107 | // op: Qd |
| 4108 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4109 | Value |= (op & 0x7) << 13; |
| 4110 | // op: addr |
| 4111 | op = getMveAddrModeQOpValue<2>(MI, OpIdx: 1, Fixups, STI); |
| 4112 | Value |= (op & 0x80) << 16; |
| 4113 | Value |= (op & 0x700) << 9; |
| 4114 | Value |= (op & 0x7f); |
| 4115 | break; |
| 4116 | } |
| 4117 | case ARM::MVE_VLDRDU64_qi: |
| 4118 | case ARM::MVE_VSTRD64_qi: { |
| 4119 | // op: Qd |
| 4120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4121 | Value |= (op & 0x7) << 13; |
| 4122 | // op: addr |
| 4123 | op = getMveAddrModeQOpValue<3>(MI, OpIdx: 1, Fixups, STI); |
| 4124 | Value |= (op & 0x80) << 16; |
| 4125 | Value |= (op & 0x700) << 9; |
| 4126 | Value |= (op & 0x7f); |
| 4127 | break; |
| 4128 | } |
| 4129 | case ARM::MVE_VLDRBS16_rq: |
| 4130 | case ARM::MVE_VLDRBS32_rq: |
| 4131 | case ARM::MVE_VLDRBU16_rq: |
| 4132 | case ARM::MVE_VLDRBU32_rq: |
| 4133 | case ARM::MVE_VLDRBU8_rq: |
| 4134 | case ARM::MVE_VLDRDU64_rq: |
| 4135 | case ARM::MVE_VLDRDU64_rq_u: |
| 4136 | case ARM::MVE_VLDRHS32_rq: |
| 4137 | case ARM::MVE_VLDRHS32_rq_u: |
| 4138 | case ARM::MVE_VLDRHU16_rq: |
| 4139 | case ARM::MVE_VLDRHU16_rq_u: |
| 4140 | case ARM::MVE_VLDRHU32_rq: |
| 4141 | case ARM::MVE_VLDRHU32_rq_u: |
| 4142 | case ARM::MVE_VLDRWU32_rq: |
| 4143 | case ARM::MVE_VLDRWU32_rq_u: |
| 4144 | case ARM::MVE_VSTRB16_rq: |
| 4145 | case ARM::MVE_VSTRB32_rq: |
| 4146 | case ARM::MVE_VSTRB8_rq: |
| 4147 | case ARM::MVE_VSTRD64_rq: |
| 4148 | case ARM::MVE_VSTRD64_rq_u: |
| 4149 | case ARM::MVE_VSTRH16_rq: |
| 4150 | case ARM::MVE_VSTRH16_rq_u: |
| 4151 | case ARM::MVE_VSTRH32_rq: |
| 4152 | case ARM::MVE_VSTRH32_rq_u: |
| 4153 | case ARM::MVE_VSTRW32_rq: |
| 4154 | case ARM::MVE_VSTRW32_rq_u: { |
| 4155 | // op: Qd |
| 4156 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4157 | Value |= (op & 0x7) << 13; |
| 4158 | // op: addr |
| 4159 | op = getMveAddrModeRQOpValue(MI, OpIdx: 1, Fixups, STI); |
| 4160 | Value |= (op & 0x78) << 13; |
| 4161 | Value |= (op & 0x7) << 1; |
| 4162 | break; |
| 4163 | } |
| 4164 | case ARM::MVE_VLDRBS16: |
| 4165 | case ARM::MVE_VLDRBS32: |
| 4166 | case ARM::MVE_VLDRBU16: |
| 4167 | case ARM::MVE_VLDRBU32: |
| 4168 | case ARM::MVE_VSTRB16: |
| 4169 | case ARM::MVE_VSTRB32: { |
| 4170 | // op: Qd |
| 4171 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4172 | Value |= (op & 0x7) << 13; |
| 4173 | // op: addr |
| 4174 | op = getT2AddrModeImmOpValue<7,0>(MI, OpNum: 1, Fixups, STI); |
| 4175 | Value |= (op & 0x80) << 16; |
| 4176 | Value |= (op & 0x700) << 8; |
| 4177 | Value |= (op & 0x7f); |
| 4178 | break; |
| 4179 | } |
| 4180 | case ARM::MVE_VLDRBU8: |
| 4181 | case ARM::MVE_VSTRBU8: { |
| 4182 | // op: Qd |
| 4183 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4184 | Value |= (op & 0x7) << 13; |
| 4185 | // op: addr |
| 4186 | op = getT2AddrModeImmOpValue<7,0>(MI, OpNum: 1, Fixups, STI); |
| 4187 | Value |= (op & 0x80) << 16; |
| 4188 | Value |= (op & 0xf00) << 8; |
| 4189 | Value |= (op & 0x7f); |
| 4190 | break; |
| 4191 | } |
| 4192 | case ARM::MVE_VLDRHS32: |
| 4193 | case ARM::MVE_VLDRHU32: |
| 4194 | case ARM::MVE_VSTRH32: { |
| 4195 | // op: Qd |
| 4196 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4197 | Value |= (op & 0x7) << 13; |
| 4198 | // op: addr |
| 4199 | op = getT2AddrModeImmOpValue<7,1>(MI, OpNum: 1, Fixups, STI); |
| 4200 | Value |= (op & 0x80) << 16; |
| 4201 | Value |= (op & 0x700) << 8; |
| 4202 | Value |= (op & 0x7f); |
| 4203 | break; |
| 4204 | } |
| 4205 | case ARM::MVE_VLDRHU16: |
| 4206 | case ARM::MVE_VSTRHU16: { |
| 4207 | // op: Qd |
| 4208 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4209 | Value |= (op & 0x7) << 13; |
| 4210 | // op: addr |
| 4211 | op = getT2AddrModeImmOpValue<7,1>(MI, OpNum: 1, Fixups, STI); |
| 4212 | Value |= (op & 0x80) << 16; |
| 4213 | Value |= (op & 0xf00) << 8; |
| 4214 | Value |= (op & 0x7f); |
| 4215 | break; |
| 4216 | } |
| 4217 | case ARM::MVE_VLDRWU32: |
| 4218 | case ARM::MVE_VSTRWU32: { |
| 4219 | // op: Qd |
| 4220 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4221 | Value |= (op & 0x7) << 13; |
| 4222 | // op: addr |
| 4223 | op = getT2AddrModeImmOpValue<7,2>(MI, OpNum: 1, Fixups, STI); |
| 4224 | Value |= (op & 0x80) << 16; |
| 4225 | Value |= (op & 0xf00) << 8; |
| 4226 | Value |= (op & 0x7f); |
| 4227 | break; |
| 4228 | } |
| 4229 | case ARM::MVE_VDUP16: |
| 4230 | case ARM::MVE_VDUP32: |
| 4231 | case ARM::MVE_VDUP8: { |
| 4232 | // op: Qd |
| 4233 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4234 | Value |= (op & 0x7) << 17; |
| 4235 | Value |= (op & 0x8) << 4; |
| 4236 | // op: Rt |
| 4237 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4238 | Value |= (op & 0xf) << 12; |
| 4239 | break; |
| 4240 | } |
| 4241 | case ARM::MVE_VMOV_to_lane_32: { |
| 4242 | // op: Qd |
| 4243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4244 | Value |= (op & 0x7) << 17; |
| 4245 | Value |= (op & 0x8) << 4; |
| 4246 | // op: Rt |
| 4247 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4248 | Value |= (op & 0xf) << 12; |
| 4249 | // op: Idx |
| 4250 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4251 | Value |= (op & 0x1) << 21; |
| 4252 | Value |= (op & 0x2) << 15; |
| 4253 | break; |
| 4254 | } |
| 4255 | case ARM::MVE_VMOV_to_lane_16: { |
| 4256 | // op: Qd |
| 4257 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4258 | Value |= (op & 0x7) << 17; |
| 4259 | Value |= (op & 0x8) << 4; |
| 4260 | // op: Rt |
| 4261 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4262 | Value |= (op & 0xf) << 12; |
| 4263 | // op: Idx |
| 4264 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4265 | Value |= (op & 0x2) << 20; |
| 4266 | Value |= (op & 0x4) << 14; |
| 4267 | Value |= (op & 0x1) << 6; |
| 4268 | break; |
| 4269 | } |
| 4270 | case ARM::MVE_VMOV_to_lane_8: { |
| 4271 | // op: Qd |
| 4272 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4273 | Value |= (op & 0x7) << 17; |
| 4274 | Value |= (op & 0x8) << 4; |
| 4275 | // op: Rt |
| 4276 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4277 | Value |= (op & 0xf) << 12; |
| 4278 | // op: Idx |
| 4279 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4280 | Value |= (op & 0x4) << 19; |
| 4281 | Value |= (op & 0x8) << 13; |
| 4282 | Value |= (op & 0x3) << 5; |
| 4283 | break; |
| 4284 | } |
| 4285 | case ARM::MVE_VABSs16: |
| 4286 | case ARM::MVE_VABSs32: |
| 4287 | case ARM::MVE_VABSs8: |
| 4288 | case ARM::MVE_VCLSs16: |
| 4289 | case ARM::MVE_VCLSs32: |
| 4290 | case ARM::MVE_VCLSs8: |
| 4291 | case ARM::MVE_VCLZs16: |
| 4292 | case ARM::MVE_VCLZs32: |
| 4293 | case ARM::MVE_VCLZs8: |
| 4294 | case ARM::MVE_VCVTf32f16bh: |
| 4295 | case ARM::MVE_VCVTf32f16th: |
| 4296 | case ARM::MVE_VMOVLs16bh: |
| 4297 | case ARM::MVE_VMOVLs16th: |
| 4298 | case ARM::MVE_VMOVLs8bh: |
| 4299 | case ARM::MVE_VMOVLs8th: |
| 4300 | case ARM::MVE_VMOVLu16bh: |
| 4301 | case ARM::MVE_VMOVLu16th: |
| 4302 | case ARM::MVE_VMOVLu8bh: |
| 4303 | case ARM::MVE_VMOVLu8th: |
| 4304 | case ARM::MVE_VMVN: |
| 4305 | case ARM::MVE_VNEGs16: |
| 4306 | case ARM::MVE_VNEGs32: |
| 4307 | case ARM::MVE_VNEGs8: |
| 4308 | case ARM::MVE_VQABSs16: |
| 4309 | case ARM::MVE_VQABSs32: |
| 4310 | case ARM::MVE_VQABSs8: |
| 4311 | case ARM::MVE_VQNEGs16: |
| 4312 | case ARM::MVE_VQNEGs32: |
| 4313 | case ARM::MVE_VQNEGs8: |
| 4314 | case ARM::MVE_VREV16_8: |
| 4315 | case ARM::MVE_VREV32_16: |
| 4316 | case ARM::MVE_VREV32_8: |
| 4317 | case ARM::MVE_VREV64_16: |
| 4318 | case ARM::MVE_VREV64_32: |
| 4319 | case ARM::MVE_VREV64_8: |
| 4320 | case ARM::MVE_VSHLL_lws16bh: |
| 4321 | case ARM::MVE_VSHLL_lws16th: |
| 4322 | case ARM::MVE_VSHLL_lws8bh: |
| 4323 | case ARM::MVE_VSHLL_lws8th: |
| 4324 | case ARM::MVE_VSHLL_lwu16bh: |
| 4325 | case ARM::MVE_VSHLL_lwu16th: |
| 4326 | case ARM::MVE_VSHLL_lwu8bh: |
| 4327 | case ARM::MVE_VSHLL_lwu8th: { |
| 4328 | // op: Qd |
| 4329 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4330 | Value |= (op & 0x8) << 19; |
| 4331 | Value |= (op & 0x7) << 13; |
| 4332 | // op: Qm |
| 4333 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4334 | Value |= (op & 0x8) << 2; |
| 4335 | Value |= (op & 0x7) << 1; |
| 4336 | break; |
| 4337 | } |
| 4338 | case ARM::MVE_VQRSHL_by_vecs16: |
| 4339 | case ARM::MVE_VQRSHL_by_vecs32: |
| 4340 | case ARM::MVE_VQRSHL_by_vecs8: |
| 4341 | case ARM::MVE_VQRSHL_by_vecu16: |
| 4342 | case ARM::MVE_VQRSHL_by_vecu32: |
| 4343 | case ARM::MVE_VQRSHL_by_vecu8: |
| 4344 | case ARM::MVE_VQSHL_by_vecs16: |
| 4345 | case ARM::MVE_VQSHL_by_vecs32: |
| 4346 | case ARM::MVE_VQSHL_by_vecs8: |
| 4347 | case ARM::MVE_VQSHL_by_vecu16: |
| 4348 | case ARM::MVE_VQSHL_by_vecu32: |
| 4349 | case ARM::MVE_VQSHL_by_vecu8: |
| 4350 | case ARM::MVE_VRSHL_by_vecs16: |
| 4351 | case ARM::MVE_VRSHL_by_vecs32: |
| 4352 | case ARM::MVE_VRSHL_by_vecs8: |
| 4353 | case ARM::MVE_VRSHL_by_vecu16: |
| 4354 | case ARM::MVE_VRSHL_by_vecu32: |
| 4355 | case ARM::MVE_VRSHL_by_vecu8: |
| 4356 | case ARM::MVE_VSHL_by_vecs16: |
| 4357 | case ARM::MVE_VSHL_by_vecs32: |
| 4358 | case ARM::MVE_VSHL_by_vecs8: |
| 4359 | case ARM::MVE_VSHL_by_vecu16: |
| 4360 | case ARM::MVE_VSHL_by_vecu32: |
| 4361 | case ARM::MVE_VSHL_by_vecu8: { |
| 4362 | // op: Qd |
| 4363 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4364 | Value |= (op & 0x8) << 19; |
| 4365 | Value |= (op & 0x7) << 13; |
| 4366 | // op: Qm |
| 4367 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4368 | Value |= (op & 0x8) << 2; |
| 4369 | Value |= (op & 0x7) << 1; |
| 4370 | // op: Qn |
| 4371 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4372 | Value |= (op & 0x7) << 17; |
| 4373 | Value |= (op & 0x8) << 4; |
| 4374 | break; |
| 4375 | } |
| 4376 | case ARM::MVE_VSHLL_imms8bh: |
| 4377 | case ARM::MVE_VSHLL_imms8th: |
| 4378 | case ARM::MVE_VSHLL_immu8bh: |
| 4379 | case ARM::MVE_VSHLL_immu8th: { |
| 4380 | // op: Qd |
| 4381 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4382 | Value |= (op & 0x8) << 19; |
| 4383 | Value |= (op & 0x7) << 13; |
| 4384 | // op: Qm |
| 4385 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4386 | Value |= (op & 0x8) << 2; |
| 4387 | Value |= (op & 0x7) << 1; |
| 4388 | // op: imm |
| 4389 | op = getMVEShiftImmOpValue(MI, OpIdx: 2, Fixups, STI); |
| 4390 | Value |= (op & 0x7) << 16; |
| 4391 | break; |
| 4392 | } |
| 4393 | case ARM::MVE_VSHLL_imms16bh: |
| 4394 | case ARM::MVE_VSHLL_imms16th: |
| 4395 | case ARM::MVE_VSHLL_immu16bh: |
| 4396 | case ARM::MVE_VSHLL_immu16th: { |
| 4397 | // op: Qd |
| 4398 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4399 | Value |= (op & 0x8) << 19; |
| 4400 | Value |= (op & 0x7) << 13; |
| 4401 | // op: Qm |
| 4402 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4403 | Value |= (op & 0x8) << 2; |
| 4404 | Value |= (op & 0x7) << 1; |
| 4405 | // op: imm |
| 4406 | op = getMVEShiftImmOpValue(MI, OpIdx: 2, Fixups, STI); |
| 4407 | Value |= (op & 0xf) << 16; |
| 4408 | break; |
| 4409 | } |
| 4410 | case ARM::MVE_VQSHLU_imms32: |
| 4411 | case ARM::MVE_VQSHLimms32: |
| 4412 | case ARM::MVE_VQSHLimmu32: |
| 4413 | case ARM::MVE_VSHL_immi32: { |
| 4414 | // op: Qd |
| 4415 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4416 | Value |= (op & 0x8) << 19; |
| 4417 | Value |= (op & 0x7) << 13; |
| 4418 | // op: Qm |
| 4419 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4420 | Value |= (op & 0x8) << 2; |
| 4421 | Value |= (op & 0x7) << 1; |
| 4422 | // op: imm |
| 4423 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4424 | Value |= (op & 0x1f) << 16; |
| 4425 | break; |
| 4426 | } |
| 4427 | case ARM::MVE_VQSHLU_imms8: |
| 4428 | case ARM::MVE_VQSHLimms8: |
| 4429 | case ARM::MVE_VQSHLimmu8: |
| 4430 | case ARM::MVE_VSHL_immi8: { |
| 4431 | // op: Qd |
| 4432 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4433 | Value |= (op & 0x8) << 19; |
| 4434 | Value |= (op & 0x7) << 13; |
| 4435 | // op: Qm |
| 4436 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4437 | Value |= (op & 0x8) << 2; |
| 4438 | Value |= (op & 0x7) << 1; |
| 4439 | // op: imm |
| 4440 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4441 | Value |= (op & 0x7) << 16; |
| 4442 | break; |
| 4443 | } |
| 4444 | case ARM::MVE_VQSHLU_imms16: |
| 4445 | case ARM::MVE_VQSHLimms16: |
| 4446 | case ARM::MVE_VQSHLimmu16: |
| 4447 | case ARM::MVE_VSHL_immi16: { |
| 4448 | // op: Qd |
| 4449 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4450 | Value |= (op & 0x8) << 19; |
| 4451 | Value |= (op & 0x7) << 13; |
| 4452 | // op: Qm |
| 4453 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4454 | Value |= (op & 0x8) << 2; |
| 4455 | Value |= (op & 0x7) << 1; |
| 4456 | // op: imm |
| 4457 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4458 | Value |= (op & 0xf) << 16; |
| 4459 | break; |
| 4460 | } |
| 4461 | case ARM::MVE_VRSHR_imms16: |
| 4462 | case ARM::MVE_VRSHR_immu16: |
| 4463 | case ARM::MVE_VSHR_imms16: |
| 4464 | case ARM::MVE_VSHR_immu16: { |
| 4465 | // op: Qd |
| 4466 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4467 | Value |= (op & 0x8) << 19; |
| 4468 | Value |= (op & 0x7) << 13; |
| 4469 | // op: Qm |
| 4470 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4471 | Value |= (op & 0x8) << 2; |
| 4472 | Value |= (op & 0x7) << 1; |
| 4473 | // op: imm |
| 4474 | op = getShiftRight16Imm(MI, Op: 2, Fixups, STI); |
| 4475 | Value |= (op & 0xf) << 16; |
| 4476 | break; |
| 4477 | } |
| 4478 | case ARM::MVE_VRSHR_imms32: |
| 4479 | case ARM::MVE_VRSHR_immu32: |
| 4480 | case ARM::MVE_VSHR_imms32: |
| 4481 | case ARM::MVE_VSHR_immu32: { |
| 4482 | // op: Qd |
| 4483 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4484 | Value |= (op & 0x8) << 19; |
| 4485 | Value |= (op & 0x7) << 13; |
| 4486 | // op: Qm |
| 4487 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4488 | Value |= (op & 0x8) << 2; |
| 4489 | Value |= (op & 0x7) << 1; |
| 4490 | // op: imm |
| 4491 | op = getShiftRight32Imm(MI, Op: 2, Fixups, STI); |
| 4492 | Value |= (op & 0x1f) << 16; |
| 4493 | break; |
| 4494 | } |
| 4495 | case ARM::MVE_VRSHR_imms8: |
| 4496 | case ARM::MVE_VRSHR_immu8: |
| 4497 | case ARM::MVE_VSHR_imms8: |
| 4498 | case ARM::MVE_VSHR_immu8: { |
| 4499 | // op: Qd |
| 4500 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4501 | Value |= (op & 0x8) << 19; |
| 4502 | Value |= (op & 0x7) << 13; |
| 4503 | // op: Qm |
| 4504 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4505 | Value |= (op & 0x8) << 2; |
| 4506 | Value |= (op & 0x7) << 1; |
| 4507 | // op: imm |
| 4508 | op = getShiftRight8Imm(MI, Op: 2, Fixups, STI); |
| 4509 | Value |= (op & 0x7) << 16; |
| 4510 | break; |
| 4511 | } |
| 4512 | case ARM::MVE_VCVTf16f32bh: |
| 4513 | case ARM::MVE_VCVTf16f32th: |
| 4514 | case ARM::MVE_VMAXAs16: |
| 4515 | case ARM::MVE_VMAXAs32: |
| 4516 | case ARM::MVE_VMAXAs8: |
| 4517 | case ARM::MVE_VMAXNMAf16: |
| 4518 | case ARM::MVE_VMAXNMAf32: |
| 4519 | case ARM::MVE_VMINAs16: |
| 4520 | case ARM::MVE_VMINAs32: |
| 4521 | case ARM::MVE_VMINAs8: |
| 4522 | case ARM::MVE_VMINNMAf16: |
| 4523 | case ARM::MVE_VMINNMAf32: |
| 4524 | case ARM::MVE_VMOVNi16bh: |
| 4525 | case ARM::MVE_VMOVNi16th: |
| 4526 | case ARM::MVE_VMOVNi32bh: |
| 4527 | case ARM::MVE_VMOVNi32th: |
| 4528 | case ARM::MVE_VQMOVNs16bh: |
| 4529 | case ARM::MVE_VQMOVNs16th: |
| 4530 | case ARM::MVE_VQMOVNs32bh: |
| 4531 | case ARM::MVE_VQMOVNs32th: |
| 4532 | case ARM::MVE_VQMOVNu16bh: |
| 4533 | case ARM::MVE_VQMOVNu16th: |
| 4534 | case ARM::MVE_VQMOVNu32bh: |
| 4535 | case ARM::MVE_VQMOVNu32th: |
| 4536 | case ARM::MVE_VQMOVUNs16bh: |
| 4537 | case ARM::MVE_VQMOVUNs16th: |
| 4538 | case ARM::MVE_VQMOVUNs32bh: |
| 4539 | case ARM::MVE_VQMOVUNs32th: { |
| 4540 | // op: Qd |
| 4541 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4542 | Value |= (op & 0x8) << 19; |
| 4543 | Value |= (op & 0x7) << 13; |
| 4544 | // op: Qm |
| 4545 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4546 | Value |= (op & 0x8) << 2; |
| 4547 | Value |= (op & 0x7) << 1; |
| 4548 | break; |
| 4549 | } |
| 4550 | case ARM::MVE_VAND: |
| 4551 | case ARM::MVE_VBIC: |
| 4552 | case ARM::MVE_VEOR: |
| 4553 | case ARM::MVE_VMULHs16: |
| 4554 | case ARM::MVE_VMULHs32: |
| 4555 | case ARM::MVE_VMULHs8: |
| 4556 | case ARM::MVE_VMULHu16: |
| 4557 | case ARM::MVE_VMULHu32: |
| 4558 | case ARM::MVE_VMULHu8: |
| 4559 | case ARM::MVE_VMULLBp16: |
| 4560 | case ARM::MVE_VMULLBp8: |
| 4561 | case ARM::MVE_VMULLBs16: |
| 4562 | case ARM::MVE_VMULLBs32: |
| 4563 | case ARM::MVE_VMULLBs8: |
| 4564 | case ARM::MVE_VMULLBu16: |
| 4565 | case ARM::MVE_VMULLBu32: |
| 4566 | case ARM::MVE_VMULLBu8: |
| 4567 | case ARM::MVE_VMULLTp16: |
| 4568 | case ARM::MVE_VMULLTp8: |
| 4569 | case ARM::MVE_VMULLTs16: |
| 4570 | case ARM::MVE_VMULLTs32: |
| 4571 | case ARM::MVE_VMULLTs8: |
| 4572 | case ARM::MVE_VMULLTu16: |
| 4573 | case ARM::MVE_VMULLTu32: |
| 4574 | case ARM::MVE_VMULLTu8: |
| 4575 | case ARM::MVE_VORN: |
| 4576 | case ARM::MVE_VORR: |
| 4577 | case ARM::MVE_VQDMULLs16bh: |
| 4578 | case ARM::MVE_VQDMULLs16th: |
| 4579 | case ARM::MVE_VQDMULLs32bh: |
| 4580 | case ARM::MVE_VQDMULLs32th: |
| 4581 | case ARM::MVE_VRMULHs16: |
| 4582 | case ARM::MVE_VRMULHs32: |
| 4583 | case ARM::MVE_VRMULHs8: |
| 4584 | case ARM::MVE_VRMULHu16: |
| 4585 | case ARM::MVE_VRMULHu32: |
| 4586 | case ARM::MVE_VRMULHu8: { |
| 4587 | // op: Qd |
| 4588 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4589 | Value |= (op & 0x8) << 19; |
| 4590 | Value |= (op & 0x7) << 13; |
| 4591 | // op: Qm |
| 4592 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4593 | Value |= (op & 0x8) << 2; |
| 4594 | Value |= (op & 0x7) << 1; |
| 4595 | // op: Qn |
| 4596 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4597 | Value |= (op & 0x7) << 17; |
| 4598 | Value |= (op & 0x8) << 4; |
| 4599 | break; |
| 4600 | } |
| 4601 | case ARM::MVE_VCADDi16: |
| 4602 | case ARM::MVE_VCADDi32: |
| 4603 | case ARM::MVE_VCADDi8: |
| 4604 | case ARM::MVE_VHCADDs16: |
| 4605 | case ARM::MVE_VHCADDs32: |
| 4606 | case ARM::MVE_VHCADDs8: { |
| 4607 | // op: Qd |
| 4608 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4609 | Value |= (op & 0x8) << 19; |
| 4610 | Value |= (op & 0x7) << 13; |
| 4611 | // op: Qm |
| 4612 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4613 | Value |= (op & 0x8) << 2; |
| 4614 | Value |= (op & 0x7) << 1; |
| 4615 | // op: Qn |
| 4616 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4617 | Value |= (op & 0x7) << 17; |
| 4618 | Value |= (op & 0x8) << 4; |
| 4619 | // op: rot |
| 4620 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4621 | Value |= (op & 0x1) << 12; |
| 4622 | break; |
| 4623 | } |
| 4624 | case ARM::MVE_VCMULf16: |
| 4625 | case ARM::MVE_VCMULf32: { |
| 4626 | // op: Qd |
| 4627 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4628 | Value |= (op & 0x8) << 19; |
| 4629 | Value |= (op & 0x7) << 13; |
| 4630 | // op: Qm |
| 4631 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4632 | Value |= (op & 0x8) << 2; |
| 4633 | Value |= (op & 0x7) << 1; |
| 4634 | // op: Qn |
| 4635 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4636 | Value |= (op & 0x7) << 17; |
| 4637 | Value |= (op & 0x8) << 4; |
| 4638 | // op: rot |
| 4639 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4640 | Value |= (op & 0x2) << 11; |
| 4641 | Value |= (op & 0x1); |
| 4642 | break; |
| 4643 | } |
| 4644 | case ARM::MVE_VSLIimm32: { |
| 4645 | // op: Qd |
| 4646 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4647 | Value |= (op & 0x8) << 19; |
| 4648 | Value |= (op & 0x7) << 13; |
| 4649 | // op: Qm |
| 4650 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4651 | Value |= (op & 0x8) << 2; |
| 4652 | Value |= (op & 0x7) << 1; |
| 4653 | // op: imm |
| 4654 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4655 | Value |= (op & 0x1f) << 16; |
| 4656 | break; |
| 4657 | } |
| 4658 | case ARM::MVE_VSLIimm8: { |
| 4659 | // op: Qd |
| 4660 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4661 | Value |= (op & 0x8) << 19; |
| 4662 | Value |= (op & 0x7) << 13; |
| 4663 | // op: Qm |
| 4664 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4665 | Value |= (op & 0x8) << 2; |
| 4666 | Value |= (op & 0x7) << 1; |
| 4667 | // op: imm |
| 4668 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4669 | Value |= (op & 0x7) << 16; |
| 4670 | break; |
| 4671 | } |
| 4672 | case ARM::MVE_VSLIimm16: { |
| 4673 | // op: Qd |
| 4674 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4675 | Value |= (op & 0x8) << 19; |
| 4676 | Value |= (op & 0x7) << 13; |
| 4677 | // op: Qm |
| 4678 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4679 | Value |= (op & 0x8) << 2; |
| 4680 | Value |= (op & 0x7) << 1; |
| 4681 | // op: imm |
| 4682 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4683 | Value |= (op & 0xf) << 16; |
| 4684 | break; |
| 4685 | } |
| 4686 | case ARM::MVE_VQRSHRNbhs32: |
| 4687 | case ARM::MVE_VQRSHRNbhu32: |
| 4688 | case ARM::MVE_VQRSHRNths32: |
| 4689 | case ARM::MVE_VQRSHRNthu32: |
| 4690 | case ARM::MVE_VQRSHRUNs32bh: |
| 4691 | case ARM::MVE_VQRSHRUNs32th: |
| 4692 | case ARM::MVE_VQSHRNbhs32: |
| 4693 | case ARM::MVE_VQSHRNbhu32: |
| 4694 | case ARM::MVE_VQSHRNths32: |
| 4695 | case ARM::MVE_VQSHRNthu32: |
| 4696 | case ARM::MVE_VQSHRUNs32bh: |
| 4697 | case ARM::MVE_VQSHRUNs32th: |
| 4698 | case ARM::MVE_VRSHRNi32bh: |
| 4699 | case ARM::MVE_VRSHRNi32th: |
| 4700 | case ARM::MVE_VSHRNi32bh: |
| 4701 | case ARM::MVE_VSHRNi32th: |
| 4702 | case ARM::MVE_VSRIimm16: { |
| 4703 | // op: Qd |
| 4704 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4705 | Value |= (op & 0x8) << 19; |
| 4706 | Value |= (op & 0x7) << 13; |
| 4707 | // op: Qm |
| 4708 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4709 | Value |= (op & 0x8) << 2; |
| 4710 | Value |= (op & 0x7) << 1; |
| 4711 | // op: imm |
| 4712 | op = getShiftRight16Imm(MI, Op: 3, Fixups, STI); |
| 4713 | Value |= (op & 0xf) << 16; |
| 4714 | break; |
| 4715 | } |
| 4716 | case ARM::MVE_VSRIimm32: { |
| 4717 | // op: Qd |
| 4718 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4719 | Value |= (op & 0x8) << 19; |
| 4720 | Value |= (op & 0x7) << 13; |
| 4721 | // op: Qm |
| 4722 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4723 | Value |= (op & 0x8) << 2; |
| 4724 | Value |= (op & 0x7) << 1; |
| 4725 | // op: imm |
| 4726 | op = getShiftRight32Imm(MI, Op: 3, Fixups, STI); |
| 4727 | Value |= (op & 0x1f) << 16; |
| 4728 | break; |
| 4729 | } |
| 4730 | case ARM::MVE_VQRSHRNbhs16: |
| 4731 | case ARM::MVE_VQRSHRNbhu16: |
| 4732 | case ARM::MVE_VQRSHRNths16: |
| 4733 | case ARM::MVE_VQRSHRNthu16: |
| 4734 | case ARM::MVE_VQRSHRUNs16bh: |
| 4735 | case ARM::MVE_VQRSHRUNs16th: |
| 4736 | case ARM::MVE_VQSHRNbhs16: |
| 4737 | case ARM::MVE_VQSHRNbhu16: |
| 4738 | case ARM::MVE_VQSHRNths16: |
| 4739 | case ARM::MVE_VQSHRNthu16: |
| 4740 | case ARM::MVE_VQSHRUNs16bh: |
| 4741 | case ARM::MVE_VQSHRUNs16th: |
| 4742 | case ARM::MVE_VRSHRNi16bh: |
| 4743 | case ARM::MVE_VRSHRNi16th: |
| 4744 | case ARM::MVE_VSHRNi16bh: |
| 4745 | case ARM::MVE_VSHRNi16th: |
| 4746 | case ARM::MVE_VSRIimm8: { |
| 4747 | // op: Qd |
| 4748 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4749 | Value |= (op & 0x8) << 19; |
| 4750 | Value |= (op & 0x7) << 13; |
| 4751 | // op: Qm |
| 4752 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4753 | Value |= (op & 0x8) << 2; |
| 4754 | Value |= (op & 0x7) << 1; |
| 4755 | // op: imm |
| 4756 | op = getShiftRight8Imm(MI, Op: 3, Fixups, STI); |
| 4757 | Value |= (op & 0x7) << 16; |
| 4758 | break; |
| 4759 | } |
| 4760 | case ARM::MVE_VADC: |
| 4761 | case ARM::MVE_VADCI: |
| 4762 | case ARM::MVE_VQDMLADHXs16: |
| 4763 | case ARM::MVE_VQDMLADHXs32: |
| 4764 | case ARM::MVE_VQDMLADHXs8: |
| 4765 | case ARM::MVE_VQDMLADHs16: |
| 4766 | case ARM::MVE_VQDMLADHs32: |
| 4767 | case ARM::MVE_VQDMLADHs8: |
| 4768 | case ARM::MVE_VQDMLSDHXs16: |
| 4769 | case ARM::MVE_VQDMLSDHXs32: |
| 4770 | case ARM::MVE_VQDMLSDHXs8: |
| 4771 | case ARM::MVE_VQDMLSDHs16: |
| 4772 | case ARM::MVE_VQDMLSDHs32: |
| 4773 | case ARM::MVE_VQDMLSDHs8: |
| 4774 | case ARM::MVE_VQRDMLADHXs16: |
| 4775 | case ARM::MVE_VQRDMLADHXs32: |
| 4776 | case ARM::MVE_VQRDMLADHXs8: |
| 4777 | case ARM::MVE_VQRDMLADHs16: |
| 4778 | case ARM::MVE_VQRDMLADHs32: |
| 4779 | case ARM::MVE_VQRDMLADHs8: |
| 4780 | case ARM::MVE_VQRDMLSDHXs16: |
| 4781 | case ARM::MVE_VQRDMLSDHXs32: |
| 4782 | case ARM::MVE_VQRDMLSDHXs8: |
| 4783 | case ARM::MVE_VQRDMLSDHs16: |
| 4784 | case ARM::MVE_VQRDMLSDHs32: |
| 4785 | case ARM::MVE_VQRDMLSDHs8: |
| 4786 | case ARM::MVE_VSBC: |
| 4787 | case ARM::MVE_VSBCI: { |
| 4788 | // op: Qd |
| 4789 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4790 | Value |= (op & 0x8) << 19; |
| 4791 | Value |= (op & 0x7) << 13; |
| 4792 | // op: Qm |
| 4793 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4794 | Value |= (op & 0x8) << 2; |
| 4795 | Value |= (op & 0x7) << 1; |
| 4796 | // op: Qn |
| 4797 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4798 | Value |= (op & 0x7) << 17; |
| 4799 | Value |= (op & 0x8) << 4; |
| 4800 | break; |
| 4801 | } |
| 4802 | case ARM::MVE_VABDs16: |
| 4803 | case ARM::MVE_VABDs32: |
| 4804 | case ARM::MVE_VABDs8: |
| 4805 | case ARM::MVE_VABDu16: |
| 4806 | case ARM::MVE_VABDu32: |
| 4807 | case ARM::MVE_VABDu8: |
| 4808 | case ARM::MVE_VADDi16: |
| 4809 | case ARM::MVE_VADDi32: |
| 4810 | case ARM::MVE_VADDi8: |
| 4811 | case ARM::MVE_VHADDs16: |
| 4812 | case ARM::MVE_VHADDs32: |
| 4813 | case ARM::MVE_VHADDs8: |
| 4814 | case ARM::MVE_VHADDu16: |
| 4815 | case ARM::MVE_VHADDu32: |
| 4816 | case ARM::MVE_VHADDu8: |
| 4817 | case ARM::MVE_VHSUBs16: |
| 4818 | case ARM::MVE_VHSUBs32: |
| 4819 | case ARM::MVE_VHSUBs8: |
| 4820 | case ARM::MVE_VHSUBu16: |
| 4821 | case ARM::MVE_VHSUBu32: |
| 4822 | case ARM::MVE_VHSUBu8: |
| 4823 | case ARM::MVE_VMAXNMf16: |
| 4824 | case ARM::MVE_VMAXNMf32: |
| 4825 | case ARM::MVE_VMAXs16: |
| 4826 | case ARM::MVE_VMAXs32: |
| 4827 | case ARM::MVE_VMAXs8: |
| 4828 | case ARM::MVE_VMAXu16: |
| 4829 | case ARM::MVE_VMAXu32: |
| 4830 | case ARM::MVE_VMAXu8: |
| 4831 | case ARM::MVE_VMINNMf16: |
| 4832 | case ARM::MVE_VMINNMf32: |
| 4833 | case ARM::MVE_VMINs16: |
| 4834 | case ARM::MVE_VMINs32: |
| 4835 | case ARM::MVE_VMINs8: |
| 4836 | case ARM::MVE_VMINu16: |
| 4837 | case ARM::MVE_VMINu32: |
| 4838 | case ARM::MVE_VMINu8: |
| 4839 | case ARM::MVE_VMULi16: |
| 4840 | case ARM::MVE_VMULi32: |
| 4841 | case ARM::MVE_VMULi8: |
| 4842 | case ARM::MVE_VQADDs16: |
| 4843 | case ARM::MVE_VQADDs32: |
| 4844 | case ARM::MVE_VQADDs8: |
| 4845 | case ARM::MVE_VQADDu16: |
| 4846 | case ARM::MVE_VQADDu32: |
| 4847 | case ARM::MVE_VQADDu8: |
| 4848 | case ARM::MVE_VQDMULHi16: |
| 4849 | case ARM::MVE_VQDMULHi32: |
| 4850 | case ARM::MVE_VQDMULHi8: |
| 4851 | case ARM::MVE_VQRDMULHi16: |
| 4852 | case ARM::MVE_VQRDMULHi32: |
| 4853 | case ARM::MVE_VQRDMULHi8: |
| 4854 | case ARM::MVE_VQSUBs16: |
| 4855 | case ARM::MVE_VQSUBs32: |
| 4856 | case ARM::MVE_VQSUBs8: |
| 4857 | case ARM::MVE_VQSUBu16: |
| 4858 | case ARM::MVE_VQSUBu32: |
| 4859 | case ARM::MVE_VQSUBu8: |
| 4860 | case ARM::MVE_VRHADDs16: |
| 4861 | case ARM::MVE_VRHADDs32: |
| 4862 | case ARM::MVE_VRHADDs8: |
| 4863 | case ARM::MVE_VRHADDu16: |
| 4864 | case ARM::MVE_VRHADDu32: |
| 4865 | case ARM::MVE_VRHADDu8: |
| 4866 | case ARM::MVE_VSUBi16: |
| 4867 | case ARM::MVE_VSUBi32: |
| 4868 | case ARM::MVE_VSUBi8: { |
| 4869 | // op: Qd |
| 4870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4871 | Value |= (op & 0x8) << 19; |
| 4872 | Value |= (op & 0x7) << 13; |
| 4873 | // op: Qn |
| 4874 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4875 | Value |= (op & 0x7) << 17; |
| 4876 | Value |= (op & 0x8) << 4; |
| 4877 | // op: Qm |
| 4878 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4879 | Value |= (op & 0x8) << 2; |
| 4880 | Value |= (op & 0x7) << 1; |
| 4881 | break; |
| 4882 | } |
| 4883 | case ARM::MVE_VADD_qr_f16: |
| 4884 | case ARM::MVE_VADD_qr_f32: |
| 4885 | case ARM::MVE_VADD_qr_i16: |
| 4886 | case ARM::MVE_VADD_qr_i32: |
| 4887 | case ARM::MVE_VADD_qr_i8: |
| 4888 | case ARM::MVE_VBRSR16: |
| 4889 | case ARM::MVE_VBRSR32: |
| 4890 | case ARM::MVE_VBRSR8: |
| 4891 | case ARM::MVE_VHADD_qr_s16: |
| 4892 | case ARM::MVE_VHADD_qr_s32: |
| 4893 | case ARM::MVE_VHADD_qr_s8: |
| 4894 | case ARM::MVE_VHADD_qr_u16: |
| 4895 | case ARM::MVE_VHADD_qr_u32: |
| 4896 | case ARM::MVE_VHADD_qr_u8: |
| 4897 | case ARM::MVE_VHSUB_qr_s16: |
| 4898 | case ARM::MVE_VHSUB_qr_s32: |
| 4899 | case ARM::MVE_VHSUB_qr_s8: |
| 4900 | case ARM::MVE_VHSUB_qr_u16: |
| 4901 | case ARM::MVE_VHSUB_qr_u32: |
| 4902 | case ARM::MVE_VHSUB_qr_u8: |
| 4903 | case ARM::MVE_VMUL_qr_f16: |
| 4904 | case ARM::MVE_VMUL_qr_f32: |
| 4905 | case ARM::MVE_VMUL_qr_i16: |
| 4906 | case ARM::MVE_VMUL_qr_i32: |
| 4907 | case ARM::MVE_VMUL_qr_i8: |
| 4908 | case ARM::MVE_VQADD_qr_s16: |
| 4909 | case ARM::MVE_VQADD_qr_s32: |
| 4910 | case ARM::MVE_VQADD_qr_s8: |
| 4911 | case ARM::MVE_VQADD_qr_u16: |
| 4912 | case ARM::MVE_VQADD_qr_u32: |
| 4913 | case ARM::MVE_VQADD_qr_u8: |
| 4914 | case ARM::MVE_VQDMULH_qr_s16: |
| 4915 | case ARM::MVE_VQDMULH_qr_s32: |
| 4916 | case ARM::MVE_VQDMULH_qr_s8: |
| 4917 | case ARM::MVE_VQDMULL_qr_s16bh: |
| 4918 | case ARM::MVE_VQDMULL_qr_s16th: |
| 4919 | case ARM::MVE_VQDMULL_qr_s32bh: |
| 4920 | case ARM::MVE_VQDMULL_qr_s32th: |
| 4921 | case ARM::MVE_VQRDMULH_qr_s16: |
| 4922 | case ARM::MVE_VQRDMULH_qr_s32: |
| 4923 | case ARM::MVE_VQRDMULH_qr_s8: |
| 4924 | case ARM::MVE_VQSUB_qr_s16: |
| 4925 | case ARM::MVE_VQSUB_qr_s32: |
| 4926 | case ARM::MVE_VQSUB_qr_s8: |
| 4927 | case ARM::MVE_VQSUB_qr_u16: |
| 4928 | case ARM::MVE_VQSUB_qr_u32: |
| 4929 | case ARM::MVE_VQSUB_qr_u8: |
| 4930 | case ARM::MVE_VSUB_qr_f16: |
| 4931 | case ARM::MVE_VSUB_qr_f32: |
| 4932 | case ARM::MVE_VSUB_qr_i16: |
| 4933 | case ARM::MVE_VSUB_qr_i32: |
| 4934 | case ARM::MVE_VSUB_qr_i8: { |
| 4935 | // op: Qd |
| 4936 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4937 | Value |= (op & 0x8) << 19; |
| 4938 | Value |= (op & 0x7) << 13; |
| 4939 | // op: Qn |
| 4940 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4941 | Value |= (op & 0x7) << 17; |
| 4942 | Value |= (op & 0x8) << 4; |
| 4943 | // op: Rm |
| 4944 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4945 | Value |= (op & 0xf); |
| 4946 | break; |
| 4947 | } |
| 4948 | case ARM::MVE_VFMA_qr_Sf16: |
| 4949 | case ARM::MVE_VFMA_qr_Sf32: |
| 4950 | case ARM::MVE_VFMA_qr_f16: |
| 4951 | case ARM::MVE_VFMA_qr_f32: |
| 4952 | case ARM::MVE_VMLAS_qr_i16: |
| 4953 | case ARM::MVE_VMLAS_qr_i32: |
| 4954 | case ARM::MVE_VMLAS_qr_i8: |
| 4955 | case ARM::MVE_VMLA_qr_i16: |
| 4956 | case ARM::MVE_VMLA_qr_i32: |
| 4957 | case ARM::MVE_VMLA_qr_i8: |
| 4958 | case ARM::MVE_VQDMLAH_qrs16: |
| 4959 | case ARM::MVE_VQDMLAH_qrs32: |
| 4960 | case ARM::MVE_VQDMLAH_qrs8: |
| 4961 | case ARM::MVE_VQDMLASH_qrs16: |
| 4962 | case ARM::MVE_VQDMLASH_qrs32: |
| 4963 | case ARM::MVE_VQDMLASH_qrs8: |
| 4964 | case ARM::MVE_VQRDMLAH_qrs16: |
| 4965 | case ARM::MVE_VQRDMLAH_qrs32: |
| 4966 | case ARM::MVE_VQRDMLAH_qrs8: |
| 4967 | case ARM::MVE_VQRDMLASH_qrs16: |
| 4968 | case ARM::MVE_VQRDMLASH_qrs32: |
| 4969 | case ARM::MVE_VQRDMLASH_qrs8: { |
| 4970 | // op: Qd |
| 4971 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4972 | Value |= (op & 0x8) << 19; |
| 4973 | Value |= (op & 0x7) << 13; |
| 4974 | // op: Qn |
| 4975 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4976 | Value |= (op & 0x7) << 17; |
| 4977 | Value |= (op & 0x8) << 4; |
| 4978 | // op: Rm |
| 4979 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4980 | Value |= (op & 0xf); |
| 4981 | break; |
| 4982 | } |
| 4983 | case ARM::MVE_VQRSHL_qrs16: |
| 4984 | case ARM::MVE_VQRSHL_qrs32: |
| 4985 | case ARM::MVE_VQRSHL_qrs8: |
| 4986 | case ARM::MVE_VQRSHL_qru16: |
| 4987 | case ARM::MVE_VQRSHL_qru32: |
| 4988 | case ARM::MVE_VQRSHL_qru8: |
| 4989 | case ARM::MVE_VQSHL_qrs16: |
| 4990 | case ARM::MVE_VQSHL_qrs32: |
| 4991 | case ARM::MVE_VQSHL_qrs8: |
| 4992 | case ARM::MVE_VQSHL_qru16: |
| 4993 | case ARM::MVE_VQSHL_qru32: |
| 4994 | case ARM::MVE_VQSHL_qru8: |
| 4995 | case ARM::MVE_VRSHL_qrs16: |
| 4996 | case ARM::MVE_VRSHL_qrs32: |
| 4997 | case ARM::MVE_VRSHL_qrs8: |
| 4998 | case ARM::MVE_VRSHL_qru16: |
| 4999 | case ARM::MVE_VRSHL_qru32: |
| 5000 | case ARM::MVE_VRSHL_qru8: |
| 5001 | case ARM::MVE_VSHL_qrs16: |
| 5002 | case ARM::MVE_VSHL_qrs32: |
| 5003 | case ARM::MVE_VSHL_qrs8: |
| 5004 | case ARM::MVE_VSHL_qru16: |
| 5005 | case ARM::MVE_VSHL_qru32: |
| 5006 | case ARM::MVE_VSHL_qru8: { |
| 5007 | // op: Qd |
| 5008 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5009 | Value |= (op & 0x8) << 19; |
| 5010 | Value |= (op & 0x7) << 13; |
| 5011 | // op: Rm |
| 5012 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5013 | Value |= (op & 0xf); |
| 5014 | break; |
| 5015 | } |
| 5016 | case ARM::MVE_VDWDUPu16: |
| 5017 | case ARM::MVE_VDWDUPu32: |
| 5018 | case ARM::MVE_VDWDUPu8: |
| 5019 | case ARM::MVE_VIWDUPu16: |
| 5020 | case ARM::MVE_VIWDUPu32: |
| 5021 | case ARM::MVE_VIWDUPu8: { |
| 5022 | // op: Qd |
| 5023 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5024 | Value |= (op & 0x8) << 19; |
| 5025 | Value |= (op & 0x7) << 13; |
| 5026 | // op: Rm |
| 5027 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5028 | Value |= (op & 0xe); |
| 5029 | // op: Rn |
| 5030 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5031 | Value |= (op & 0xe) << 16; |
| 5032 | // op: imm |
| 5033 | op = getPowerTwoOpValue(MI, OpIdx: 4, Fixups, STI); |
| 5034 | Value |= (op & 0x2) << 6; |
| 5035 | Value |= (op & 0x1); |
| 5036 | break; |
| 5037 | } |
| 5038 | case ARM::MVE_VDDUPu16: |
| 5039 | case ARM::MVE_VDDUPu32: |
| 5040 | case ARM::MVE_VDDUPu8: |
| 5041 | case ARM::MVE_VIDUPu16: |
| 5042 | case ARM::MVE_VIDUPu32: |
| 5043 | case ARM::MVE_VIDUPu8: { |
| 5044 | // op: Qd |
| 5045 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5046 | Value |= (op & 0x8) << 19; |
| 5047 | Value |= (op & 0x7) << 13; |
| 5048 | // op: Rn |
| 5049 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5050 | Value |= (op & 0xe) << 16; |
| 5051 | // op: imm |
| 5052 | op = getPowerTwoOpValue(MI, OpIdx: 3, Fixups, STI); |
| 5053 | Value |= (op & 0x2) << 6; |
| 5054 | Value |= (op & 0x1); |
| 5055 | break; |
| 5056 | } |
| 5057 | case ARM::MVE_VLDRWU32_qi_pre: |
| 5058 | case ARM::MVE_VSTRW32_qi_pre: { |
| 5059 | // op: Qd |
| 5060 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5061 | Value |= (op & 0x7) << 13; |
| 5062 | // op: addr |
| 5063 | op = getMveAddrModeQOpValue<2>(MI, OpIdx: 2, Fixups, STI); |
| 5064 | Value |= (op & 0x80) << 16; |
| 5065 | Value |= (op & 0x700) << 9; |
| 5066 | Value |= (op & 0x7f); |
| 5067 | break; |
| 5068 | } |
| 5069 | case ARM::MVE_VLDRDU64_qi_pre: |
| 5070 | case ARM::MVE_VSTRD64_qi_pre: { |
| 5071 | // op: Qd |
| 5072 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5073 | Value |= (op & 0x7) << 13; |
| 5074 | // op: addr |
| 5075 | op = getMveAddrModeQOpValue<3>(MI, OpIdx: 2, Fixups, STI); |
| 5076 | Value |= (op & 0x80) << 16; |
| 5077 | Value |= (op & 0x700) << 9; |
| 5078 | Value |= (op & 0x7f); |
| 5079 | break; |
| 5080 | } |
| 5081 | case ARM::MVE_VLDRBS16_pre: |
| 5082 | case ARM::MVE_VLDRBS32_pre: |
| 5083 | case ARM::MVE_VLDRBU16_pre: |
| 5084 | case ARM::MVE_VLDRBU32_pre: |
| 5085 | case ARM::MVE_VSTRB16_pre: |
| 5086 | case ARM::MVE_VSTRB32_pre: { |
| 5087 | // op: Qd |
| 5088 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5089 | Value |= (op & 0x7) << 13; |
| 5090 | // op: addr |
| 5091 | op = getT2AddrModeImmOpValue<7,0>(MI, OpNum: 2, Fixups, STI); |
| 5092 | Value |= (op & 0x80) << 16; |
| 5093 | Value |= (op & 0x700) << 8; |
| 5094 | Value |= (op & 0x7f); |
| 5095 | break; |
| 5096 | } |
| 5097 | case ARM::MVE_VLDRBU8_pre: |
| 5098 | case ARM::MVE_VSTRBU8_pre: { |
| 5099 | // op: Qd |
| 5100 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5101 | Value |= (op & 0x7) << 13; |
| 5102 | // op: addr |
| 5103 | op = getT2AddrModeImmOpValue<7,0>(MI, OpNum: 2, Fixups, STI); |
| 5104 | Value |= (op & 0x80) << 16; |
| 5105 | Value |= (op & 0xf00) << 8; |
| 5106 | Value |= (op & 0x7f); |
| 5107 | break; |
| 5108 | } |
| 5109 | case ARM::MVE_VLDRHS32_pre: |
| 5110 | case ARM::MVE_VLDRHU32_pre: |
| 5111 | case ARM::MVE_VSTRH32_pre: { |
| 5112 | // op: Qd |
| 5113 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5114 | Value |= (op & 0x7) << 13; |
| 5115 | // op: addr |
| 5116 | op = getT2AddrModeImmOpValue<7,1>(MI, OpNum: 2, Fixups, STI); |
| 5117 | Value |= (op & 0x80) << 16; |
| 5118 | Value |= (op & 0x700) << 8; |
| 5119 | Value |= (op & 0x7f); |
| 5120 | break; |
| 5121 | } |
| 5122 | case ARM::MVE_VLDRHU16_pre: |
| 5123 | case ARM::MVE_VSTRHU16_pre: { |
| 5124 | // op: Qd |
| 5125 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5126 | Value |= (op & 0x7) << 13; |
| 5127 | // op: addr |
| 5128 | op = getT2AddrModeImmOpValue<7,1>(MI, OpNum: 2, Fixups, STI); |
| 5129 | Value |= (op & 0x80) << 16; |
| 5130 | Value |= (op & 0xf00) << 8; |
| 5131 | Value |= (op & 0x7f); |
| 5132 | break; |
| 5133 | } |
| 5134 | case ARM::MVE_VLDRWU32_pre: |
| 5135 | case ARM::MVE_VSTRWU32_pre: { |
| 5136 | // op: Qd |
| 5137 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5138 | Value |= (op & 0x7) << 13; |
| 5139 | // op: addr |
| 5140 | op = getT2AddrModeImmOpValue<7,2>(MI, OpNum: 2, Fixups, STI); |
| 5141 | Value |= (op & 0x80) << 16; |
| 5142 | Value |= (op & 0xf00) << 8; |
| 5143 | Value |= (op & 0x7f); |
| 5144 | break; |
| 5145 | } |
| 5146 | case ARM::MVE_VLDRBS16_post: |
| 5147 | case ARM::MVE_VLDRBS32_post: |
| 5148 | case ARM::MVE_VLDRBU16_post: |
| 5149 | case ARM::MVE_VLDRBU32_post: |
| 5150 | case ARM::MVE_VSTRB16_post: |
| 5151 | case ARM::MVE_VSTRB32_post: { |
| 5152 | // op: Qd |
| 5153 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5154 | Value |= (op & 0x7) << 13; |
| 5155 | // op: addr |
| 5156 | op = getT2ScaledImmOpValue<7,0>(MI, OpIdx: 3, Fixups, STI); |
| 5157 | Value |= (op & 0x80) << 16; |
| 5158 | Value |= (op & 0x7f); |
| 5159 | // op: Rn |
| 5160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5161 | Value |= (op & 0x7) << 16; |
| 5162 | break; |
| 5163 | } |
| 5164 | case ARM::MVE_VLDRBU8_post: |
| 5165 | case ARM::MVE_VSTRBU8_post: { |
| 5166 | // op: Qd |
| 5167 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5168 | Value |= (op & 0x7) << 13; |
| 5169 | // op: addr |
| 5170 | op = getT2ScaledImmOpValue<7,0>(MI, OpIdx: 3, Fixups, STI); |
| 5171 | Value |= (op & 0x80) << 16; |
| 5172 | Value |= (op & 0x7f); |
| 5173 | // op: Rn |
| 5174 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5175 | Value |= (op & 0xf) << 16; |
| 5176 | break; |
| 5177 | } |
| 5178 | case ARM::MVE_VLDRHS32_post: |
| 5179 | case ARM::MVE_VLDRHU32_post: |
| 5180 | case ARM::MVE_VSTRH32_post: { |
| 5181 | // op: Qd |
| 5182 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5183 | Value |= (op & 0x7) << 13; |
| 5184 | // op: addr |
| 5185 | op = getT2ScaledImmOpValue<7,1>(MI, OpIdx: 3, Fixups, STI); |
| 5186 | Value |= (op & 0x80) << 16; |
| 5187 | Value |= (op & 0x7f); |
| 5188 | // op: Rn |
| 5189 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5190 | Value |= (op & 0x7) << 16; |
| 5191 | break; |
| 5192 | } |
| 5193 | case ARM::MVE_VLDRHU16_post: |
| 5194 | case ARM::MVE_VSTRHU16_post: { |
| 5195 | // op: Qd |
| 5196 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5197 | Value |= (op & 0x7) << 13; |
| 5198 | // op: addr |
| 5199 | op = getT2ScaledImmOpValue<7,1>(MI, OpIdx: 3, Fixups, STI); |
| 5200 | Value |= (op & 0x80) << 16; |
| 5201 | Value |= (op & 0x7f); |
| 5202 | // op: Rn |
| 5203 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5204 | Value |= (op & 0xf) << 16; |
| 5205 | break; |
| 5206 | } |
| 5207 | case ARM::MVE_VLDRWU32_post: |
| 5208 | case ARM::MVE_VSTRWU32_post: { |
| 5209 | // op: Qd |
| 5210 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5211 | Value |= (op & 0x7) << 13; |
| 5212 | // op: addr |
| 5213 | op = getT2ScaledImmOpValue<7,2>(MI, OpIdx: 3, Fixups, STI); |
| 5214 | Value |= (op & 0x80) << 16; |
| 5215 | Value |= (op & 0x7f); |
| 5216 | // op: Rn |
| 5217 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5218 | Value |= (op & 0xf) << 16; |
| 5219 | break; |
| 5220 | } |
| 5221 | case ARM::MVE_VMOV_from_lane_32: { |
| 5222 | // op: Qd |
| 5223 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5224 | Value |= (op & 0x7) << 17; |
| 5225 | Value |= (op & 0x8) << 4; |
| 5226 | // op: Rt |
| 5227 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5228 | Value |= (op & 0xf) << 12; |
| 5229 | // op: Idx |
| 5230 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5231 | Value |= (op & 0x1) << 21; |
| 5232 | Value |= (op & 0x2) << 15; |
| 5233 | break; |
| 5234 | } |
| 5235 | case ARM::MVE_VMOV_from_lane_s16: |
| 5236 | case ARM::MVE_VMOV_from_lane_u16: { |
| 5237 | // op: Qd |
| 5238 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5239 | Value |= (op & 0x7) << 17; |
| 5240 | Value |= (op & 0x8) << 4; |
| 5241 | // op: Rt |
| 5242 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5243 | Value |= (op & 0xf) << 12; |
| 5244 | // op: Idx |
| 5245 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5246 | Value |= (op & 0x2) << 20; |
| 5247 | Value |= (op & 0x4) << 14; |
| 5248 | Value |= (op & 0x1) << 6; |
| 5249 | break; |
| 5250 | } |
| 5251 | case ARM::MVE_VMOV_from_lane_s8: |
| 5252 | case ARM::MVE_VMOV_from_lane_u8: { |
| 5253 | // op: Qd |
| 5254 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5255 | Value |= (op & 0x7) << 17; |
| 5256 | Value |= (op & 0x8) << 4; |
| 5257 | // op: Rt |
| 5258 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5259 | Value |= (op & 0xf) << 12; |
| 5260 | // op: Idx |
| 5261 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5262 | Value |= (op & 0x4) << 19; |
| 5263 | Value |= (op & 0x8) << 13; |
| 5264 | Value |= (op & 0x3) << 5; |
| 5265 | break; |
| 5266 | } |
| 5267 | case ARM::MVE_VADDVs16no_acc: |
| 5268 | case ARM::MVE_VADDVs32no_acc: |
| 5269 | case ARM::MVE_VADDVs8no_acc: |
| 5270 | case ARM::MVE_VADDVu16no_acc: |
| 5271 | case ARM::MVE_VADDVu32no_acc: |
| 5272 | case ARM::MVE_VADDVu8no_acc: { |
| 5273 | // op: Qm |
| 5274 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5275 | Value |= (op & 0x7) << 1; |
| 5276 | // op: Rda |
| 5277 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5278 | Value |= (op & 0xe) << 12; |
| 5279 | break; |
| 5280 | } |
| 5281 | case ARM::MVE_VABSf16: |
| 5282 | case ARM::MVE_VABSf32: |
| 5283 | case ARM::MVE_VCVTf16s16n: |
| 5284 | case ARM::MVE_VCVTf16u16n: |
| 5285 | case ARM::MVE_VCVTf32s32n: |
| 5286 | case ARM::MVE_VCVTf32u32n: |
| 5287 | case ARM::MVE_VCVTs16f16a: |
| 5288 | case ARM::MVE_VCVTs16f16m: |
| 5289 | case ARM::MVE_VCVTs16f16n: |
| 5290 | case ARM::MVE_VCVTs16f16p: |
| 5291 | case ARM::MVE_VCVTs16f16z: |
| 5292 | case ARM::MVE_VCVTs32f32a: |
| 5293 | case ARM::MVE_VCVTs32f32m: |
| 5294 | case ARM::MVE_VCVTs32f32n: |
| 5295 | case ARM::MVE_VCVTs32f32p: |
| 5296 | case ARM::MVE_VCVTs32f32z: |
| 5297 | case ARM::MVE_VCVTu16f16a: |
| 5298 | case ARM::MVE_VCVTu16f16m: |
| 5299 | case ARM::MVE_VCVTu16f16n: |
| 5300 | case ARM::MVE_VCVTu16f16p: |
| 5301 | case ARM::MVE_VCVTu16f16z: |
| 5302 | case ARM::MVE_VCVTu32f32a: |
| 5303 | case ARM::MVE_VCVTu32f32m: |
| 5304 | case ARM::MVE_VCVTu32f32n: |
| 5305 | case ARM::MVE_VCVTu32f32p: |
| 5306 | case ARM::MVE_VCVTu32f32z: |
| 5307 | case ARM::MVE_VNEGf16: |
| 5308 | case ARM::MVE_VNEGf32: |
| 5309 | case ARM::MVE_VRINTf16A: |
| 5310 | case ARM::MVE_VRINTf16M: |
| 5311 | case ARM::MVE_VRINTf16N: |
| 5312 | case ARM::MVE_VRINTf16P: |
| 5313 | case ARM::MVE_VRINTf16X: |
| 5314 | case ARM::MVE_VRINTf16Z: |
| 5315 | case ARM::MVE_VRINTf32A: |
| 5316 | case ARM::MVE_VRINTf32M: |
| 5317 | case ARM::MVE_VRINTf32N: |
| 5318 | case ARM::MVE_VRINTf32P: |
| 5319 | case ARM::MVE_VRINTf32X: |
| 5320 | case ARM::MVE_VRINTf32Z: { |
| 5321 | // op: Qm |
| 5322 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5323 | Value |= (op & 0x8) << 2; |
| 5324 | Value |= (op & 0x7) << 1; |
| 5325 | // op: Qd |
| 5326 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5327 | Value |= (op & 0x8) << 19; |
| 5328 | Value |= (op & 0x7) << 13; |
| 5329 | break; |
| 5330 | } |
| 5331 | case ARM::MVE_VCVTf32s32_fix: |
| 5332 | case ARM::MVE_VCVTf32u32_fix: |
| 5333 | case ARM::MVE_VCVTs32f32_fix: |
| 5334 | case ARM::MVE_VCVTu32f32_fix: { |
| 5335 | // op: Qm |
| 5336 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5337 | Value |= (op & 0x8) << 2; |
| 5338 | Value |= (op & 0x7) << 1; |
| 5339 | // op: Qd |
| 5340 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5341 | Value |= (op & 0x8) << 19; |
| 5342 | Value |= (op & 0x7) << 13; |
| 5343 | // op: imm6 |
| 5344 | op = getNEONVcvtImm32OpValue(MI, Op: 2, Fixups, STI); |
| 5345 | Value |= (op & 0x1f) << 16; |
| 5346 | break; |
| 5347 | } |
| 5348 | case ARM::MVE_VCVTf16s16_fix: |
| 5349 | case ARM::MVE_VCVTf16u16_fix: |
| 5350 | case ARM::MVE_VCVTs16f16_fix: |
| 5351 | case ARM::MVE_VCVTu16f16_fix: { |
| 5352 | // op: Qm |
| 5353 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5354 | Value |= (op & 0x8) << 2; |
| 5355 | Value |= (op & 0x7) << 1; |
| 5356 | // op: Qd |
| 5357 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5358 | Value |= (op & 0x8) << 19; |
| 5359 | Value |= (op & 0x7) << 13; |
| 5360 | // op: imm6 |
| 5361 | op = getNEONVcvtImm32OpValue(MI, Op: 2, Fixups, STI); |
| 5362 | Value |= (op & 0xf) << 16; |
| 5363 | break; |
| 5364 | } |
| 5365 | case ARM::MVE_VADDVs16acc: |
| 5366 | case ARM::MVE_VADDVs32acc: |
| 5367 | case ARM::MVE_VADDVs8acc: |
| 5368 | case ARM::MVE_VADDVu16acc: |
| 5369 | case ARM::MVE_VADDVu32acc: |
| 5370 | case ARM::MVE_VADDVu8acc: { |
| 5371 | // op: Qm |
| 5372 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5373 | Value |= (op & 0x7) << 1; |
| 5374 | // op: Rda |
| 5375 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5376 | Value |= (op & 0xe) << 12; |
| 5377 | break; |
| 5378 | } |
| 5379 | case ARM::MVE_VMAXAVs16: |
| 5380 | case ARM::MVE_VMAXAVs32: |
| 5381 | case ARM::MVE_VMAXAVs8: |
| 5382 | case ARM::MVE_VMAXNMAVf16: |
| 5383 | case ARM::MVE_VMAXNMAVf32: |
| 5384 | case ARM::MVE_VMAXNMVf16: |
| 5385 | case ARM::MVE_VMAXNMVf32: |
| 5386 | case ARM::MVE_VMAXVs16: |
| 5387 | case ARM::MVE_VMAXVs32: |
| 5388 | case ARM::MVE_VMAXVs8: |
| 5389 | case ARM::MVE_VMAXVu16: |
| 5390 | case ARM::MVE_VMAXVu32: |
| 5391 | case ARM::MVE_VMAXVu8: |
| 5392 | case ARM::MVE_VMINAVs16: |
| 5393 | case ARM::MVE_VMINAVs32: |
| 5394 | case ARM::MVE_VMINAVs8: |
| 5395 | case ARM::MVE_VMINNMAVf16: |
| 5396 | case ARM::MVE_VMINNMAVf32: |
| 5397 | case ARM::MVE_VMINNMVf16: |
| 5398 | case ARM::MVE_VMINNMVf32: |
| 5399 | case ARM::MVE_VMINVs16: |
| 5400 | case ARM::MVE_VMINVs32: |
| 5401 | case ARM::MVE_VMINVs8: |
| 5402 | case ARM::MVE_VMINVu16: |
| 5403 | case ARM::MVE_VMINVu32: |
| 5404 | case ARM::MVE_VMINVu8: { |
| 5405 | // op: Qm |
| 5406 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5407 | Value |= (op & 0x7) << 1; |
| 5408 | // op: RdaDest |
| 5409 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5410 | Value |= (op & 0xf) << 12; |
| 5411 | break; |
| 5412 | } |
| 5413 | case ARM::MVE_VADDLVs32no_acc: |
| 5414 | case ARM::MVE_VADDLVu32no_acc: { |
| 5415 | // op: Qm |
| 5416 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5417 | Value |= (op & 0x7) << 1; |
| 5418 | // op: RdaLo |
| 5419 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5420 | Value |= (op & 0xe) << 12; |
| 5421 | // op: RdaHi |
| 5422 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5423 | Value |= (op & 0xe) << 19; |
| 5424 | break; |
| 5425 | } |
| 5426 | case ARM::MVE_VABDf16: |
| 5427 | case ARM::MVE_VABDf32: |
| 5428 | case ARM::MVE_VADDf16: |
| 5429 | case ARM::MVE_VADDf32: |
| 5430 | case ARM::MVE_VMULf16: |
| 5431 | case ARM::MVE_VMULf32: |
| 5432 | case ARM::MVE_VSUBf16: |
| 5433 | case ARM::MVE_VSUBf32: { |
| 5434 | // op: Qm |
| 5435 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5436 | Value |= (op & 0x8) << 2; |
| 5437 | Value |= (op & 0x7) << 1; |
| 5438 | // op: Qd |
| 5439 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5440 | Value |= (op & 0x8) << 19; |
| 5441 | Value |= (op & 0x7) << 13; |
| 5442 | // op: Qn |
| 5443 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5444 | Value |= (op & 0x7) << 17; |
| 5445 | Value |= (op & 0x8) << 4; |
| 5446 | break; |
| 5447 | } |
| 5448 | case ARM::MVE_VCADDf16: |
| 5449 | case ARM::MVE_VCADDf32: { |
| 5450 | // op: Qm |
| 5451 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5452 | Value |= (op & 0x8) << 2; |
| 5453 | Value |= (op & 0x7) << 1; |
| 5454 | // op: Qd |
| 5455 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5456 | Value |= (op & 0x8) << 19; |
| 5457 | Value |= (op & 0x7) << 13; |
| 5458 | // op: Qn |
| 5459 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5460 | Value |= (op & 0x7) << 17; |
| 5461 | Value |= (op & 0x8) << 4; |
| 5462 | // op: rot |
| 5463 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5464 | Value |= (op & 0x1) << 24; |
| 5465 | break; |
| 5466 | } |
| 5467 | case ARM::MVE_VFMAf16: |
| 5468 | case ARM::MVE_VFMAf32: |
| 5469 | case ARM::MVE_VFMSf16: |
| 5470 | case ARM::MVE_VFMSf32: { |
| 5471 | // op: Qm |
| 5472 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5473 | Value |= (op & 0x8) << 2; |
| 5474 | Value |= (op & 0x7) << 1; |
| 5475 | // op: Qd |
| 5476 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5477 | Value |= (op & 0x8) << 19; |
| 5478 | Value |= (op & 0x7) << 13; |
| 5479 | // op: Qn |
| 5480 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5481 | Value |= (op & 0x7) << 17; |
| 5482 | Value |= (op & 0x8) << 4; |
| 5483 | break; |
| 5484 | } |
| 5485 | case ARM::MVE_VCMLAf16: |
| 5486 | case ARM::MVE_VCMLAf32: { |
| 5487 | // op: Qm |
| 5488 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5489 | Value |= (op & 0x8) << 2; |
| 5490 | Value |= (op & 0x7) << 1; |
| 5491 | // op: Qd |
| 5492 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5493 | Value |= (op & 0x8) << 19; |
| 5494 | Value |= (op & 0x7) << 13; |
| 5495 | // op: Qn |
| 5496 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5497 | Value |= (op & 0x7) << 17; |
| 5498 | Value |= (op & 0x8) << 4; |
| 5499 | // op: rot |
| 5500 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5501 | Value |= (op & 0x3) << 23; |
| 5502 | break; |
| 5503 | } |
| 5504 | case ARM::MVE_VABAVs16: |
| 5505 | case ARM::MVE_VABAVs32: |
| 5506 | case ARM::MVE_VABAVs8: |
| 5507 | case ARM::MVE_VABAVu16: |
| 5508 | case ARM::MVE_VABAVu32: |
| 5509 | case ARM::MVE_VABAVu8: { |
| 5510 | // op: Qm |
| 5511 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5512 | Value |= (op & 0x8) << 2; |
| 5513 | Value |= (op & 0x7) << 1; |
| 5514 | // op: Qn |
| 5515 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5516 | Value |= (op & 0x7) << 17; |
| 5517 | Value |= (op & 0x8) << 4; |
| 5518 | // op: Rda |
| 5519 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5520 | Value |= (op & 0xf) << 12; |
| 5521 | break; |
| 5522 | } |
| 5523 | case ARM::MVE_VADDLVs32acc: |
| 5524 | case ARM::MVE_VADDLVu32acc: { |
| 5525 | // op: Qm |
| 5526 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5527 | Value |= (op & 0x7) << 1; |
| 5528 | // op: RdaLo |
| 5529 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5530 | Value |= (op & 0xe) << 12; |
| 5531 | // op: RdaHi |
| 5532 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5533 | Value |= (op & 0xe) << 19; |
| 5534 | break; |
| 5535 | } |
| 5536 | case ARM::MVE_VPSEL: { |
| 5537 | // op: Qn |
| 5538 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5539 | Value |= (op & 0x7) << 17; |
| 5540 | Value |= (op & 0x8) << 4; |
| 5541 | // op: Qd |
| 5542 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5543 | Value |= (op & 0x8) << 19; |
| 5544 | Value |= (op & 0x7) << 13; |
| 5545 | // op: Qm |
| 5546 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5547 | Value |= (op & 0x8) << 2; |
| 5548 | Value |= (op & 0x7) << 1; |
| 5549 | break; |
| 5550 | } |
| 5551 | case ARM::t2AUTG: |
| 5552 | case ARM::t2BXAUT: { |
| 5553 | // op: Ra |
| 5554 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5555 | Value |= (op & 0xf) << 12; |
| 5556 | // op: Rn |
| 5557 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5558 | Value |= (op & 0xf) << 16; |
| 5559 | // op: Rm |
| 5560 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5561 | Value |= (op & 0xf); |
| 5562 | break; |
| 5563 | } |
| 5564 | case ARM::tADR: { |
| 5565 | // op: Rd |
| 5566 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5567 | Value |= (op & 0x7) << 8; |
| 5568 | // op: addr |
| 5569 | op = getThumbAdrLabelOpValue(MI, OpIdx: 1, Fixups, STI); |
| 5570 | Value |= (op & 0xff); |
| 5571 | break; |
| 5572 | } |
| 5573 | case ARM::tMOVi8: { |
| 5574 | // op: Rd |
| 5575 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5576 | Value |= (op & 0x7) << 8; |
| 5577 | // op: imm8 |
| 5578 | op = getHiLoImmOpValue(MI, OpIdx: 2, Fixups, STI); |
| 5579 | Value |= (op & 0xff); |
| 5580 | break; |
| 5581 | } |
| 5582 | case ARM::tMOVSr: { |
| 5583 | // op: Rd |
| 5584 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5585 | Value |= (op & 0x7); |
| 5586 | // op: Rm |
| 5587 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5588 | Value |= (op & 0x7) << 3; |
| 5589 | break; |
| 5590 | } |
| 5591 | case ARM::tADDi3: |
| 5592 | case ARM::tSUBi3: { |
| 5593 | // op: Rd |
| 5594 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5595 | Value |= (op & 0x7); |
| 5596 | // op: Rm |
| 5597 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5598 | Value |= (op & 0x7) << 3; |
| 5599 | // op: imm3 |
| 5600 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5601 | Value |= (op & 0x7) << 6; |
| 5602 | break; |
| 5603 | } |
| 5604 | case ARM::tASRri: |
| 5605 | case ARM::tLSLri: |
| 5606 | case ARM::tLSRri: { |
| 5607 | // op: Rd |
| 5608 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5609 | Value |= (op & 0x7); |
| 5610 | // op: Rm |
| 5611 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5612 | Value |= (op & 0x7) << 3; |
| 5613 | // op: imm5 |
| 5614 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5615 | Value |= (op & 0x1f) << 6; |
| 5616 | break; |
| 5617 | } |
| 5618 | case ARM::tMUL: |
| 5619 | case ARM::tMVN: |
| 5620 | case ARM::tRSB: { |
| 5621 | // op: Rd |
| 5622 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5623 | Value |= (op & 0x7); |
| 5624 | // op: Rn |
| 5625 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5626 | Value |= (op & 0x7) << 3; |
| 5627 | break; |
| 5628 | } |
| 5629 | case ARM::tMOVr: { |
| 5630 | // op: Rd |
| 5631 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5632 | Value |= (op & 0x8) << 4; |
| 5633 | Value |= (op & 0x7); |
| 5634 | // op: Rm |
| 5635 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5636 | Value |= (op & 0xf) << 3; |
| 5637 | break; |
| 5638 | } |
| 5639 | case ARM::CRC32B: |
| 5640 | case ARM::CRC32CB: |
| 5641 | case ARM::CRC32CH: |
| 5642 | case ARM::CRC32CW: |
| 5643 | case ARM::CRC32H: |
| 5644 | case ARM::CRC32W: { |
| 5645 | // op: Rd |
| 5646 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5647 | Value |= (op & 0xf) << 12; |
| 5648 | // op: Rn |
| 5649 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5650 | Value |= (op & 0xf) << 16; |
| 5651 | // op: Rm |
| 5652 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5653 | Value |= (op & 0xf); |
| 5654 | break; |
| 5655 | } |
| 5656 | case ARM::t2MRS_AR: |
| 5657 | case ARM::t2MRSsys_AR: { |
| 5658 | // op: Rd |
| 5659 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5660 | Value |= (op & 0xf) << 8; |
| 5661 | break; |
| 5662 | } |
| 5663 | case ARM::t2CLZ: |
| 5664 | case ARM::t2RBIT: |
| 5665 | case ARM::t2REV: |
| 5666 | case ARM::t2REV16: |
| 5667 | case ARM::t2REVSH: { |
| 5668 | // op: Rd |
| 5669 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5670 | Value |= (op & 0xf) << 8; |
| 5671 | // op: Rm |
| 5672 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5673 | Value |= (op & 0xf) << 16; |
| 5674 | Value |= (op & 0xf); |
| 5675 | break; |
| 5676 | } |
| 5677 | case ARM::t2ASRs1: |
| 5678 | case ARM::t2LSRs1: { |
| 5679 | // op: Rd |
| 5680 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5681 | Value |= (op & 0xf) << 8; |
| 5682 | // op: Rm |
| 5683 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5684 | Value |= (op & 0xf); |
| 5685 | break; |
| 5686 | } |
| 5687 | case ARM::t2SXTB: |
| 5688 | case ARM::t2SXTB16: |
| 5689 | case ARM::t2SXTH: |
| 5690 | case ARM::t2UXTB: |
| 5691 | case ARM::t2UXTB16: |
| 5692 | case ARM::t2UXTH: { |
| 5693 | // op: Rd |
| 5694 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5695 | Value |= (op & 0xf) << 8; |
| 5696 | // op: Rm |
| 5697 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5698 | Value |= (op & 0xf); |
| 5699 | // op: rot |
| 5700 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5701 | Value |= (op & 0x3) << 4; |
| 5702 | break; |
| 5703 | } |
| 5704 | case ARM::t2CSEL: |
| 5705 | case ARM::t2CSINC: |
| 5706 | case ARM::t2CSINV: |
| 5707 | case ARM::t2CSNEG: { |
| 5708 | // op: Rd |
| 5709 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5710 | Value |= (op & 0xf) << 8; |
| 5711 | // op: Rm |
| 5712 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5713 | Value |= (op & 0xf); |
| 5714 | // op: Rn |
| 5715 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5716 | Value |= (op & 0xf) << 16; |
| 5717 | // op: fcond |
| 5718 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5719 | Value |= (op & 0xf) << 4; |
| 5720 | break; |
| 5721 | } |
| 5722 | case ARM::t2CRC32B: |
| 5723 | case ARM::t2CRC32CB: |
| 5724 | case ARM::t2CRC32CH: |
| 5725 | case ARM::t2CRC32CW: |
| 5726 | case ARM::t2CRC32H: |
| 5727 | case ARM::t2CRC32W: |
| 5728 | case ARM::t2MUL: |
| 5729 | case ARM::t2QADD16: |
| 5730 | case ARM::t2QADD8: |
| 5731 | case ARM::t2QASX: |
| 5732 | case ARM::t2QSAX: |
| 5733 | case ARM::t2QSUB16: |
| 5734 | case ARM::t2QSUB8: |
| 5735 | case ARM::t2SADD16: |
| 5736 | case ARM::t2SADD8: |
| 5737 | case ARM::t2SASX: |
| 5738 | case ARM::t2SDIV: |
| 5739 | case ARM::t2SEL: |
| 5740 | case ARM::t2SHADD16: |
| 5741 | case ARM::t2SHADD8: |
| 5742 | case ARM::t2SHASX: |
| 5743 | case ARM::t2SHSAX: |
| 5744 | case ARM::t2SHSUB16: |
| 5745 | case ARM::t2SHSUB8: |
| 5746 | case ARM::t2SMMUL: |
| 5747 | case ARM::t2SMMULR: |
| 5748 | case ARM::t2SMUAD: |
| 5749 | case ARM::t2SMUADX: |
| 5750 | case ARM::t2SMULBB: |
| 5751 | case ARM::t2SMULBT: |
| 5752 | case ARM::t2SMULTB: |
| 5753 | case ARM::t2SMULTT: |
| 5754 | case ARM::t2SMULWB: |
| 5755 | case ARM::t2SMULWT: |
| 5756 | case ARM::t2SMUSD: |
| 5757 | case ARM::t2SMUSDX: |
| 5758 | case ARM::t2SSAX: |
| 5759 | case ARM::t2SSUB16: |
| 5760 | case ARM::t2SSUB8: |
| 5761 | case ARM::t2UADD16: |
| 5762 | case ARM::t2UADD8: |
| 5763 | case ARM::t2UASX: |
| 5764 | case ARM::t2UDIV: |
| 5765 | case ARM::t2UHADD16: |
| 5766 | case ARM::t2UHADD8: |
| 5767 | case ARM::t2UHASX: |
| 5768 | case ARM::t2UHSAX: |
| 5769 | case ARM::t2UHSUB16: |
| 5770 | case ARM::t2UHSUB8: |
| 5771 | case ARM::t2UQADD16: |
| 5772 | case ARM::t2UQADD8: |
| 5773 | case ARM::t2UQASX: |
| 5774 | case ARM::t2UQSAX: |
| 5775 | case ARM::t2UQSUB16: |
| 5776 | case ARM::t2UQSUB8: |
| 5777 | case ARM::t2USAD8: |
| 5778 | case ARM::t2USAX: |
| 5779 | case ARM::t2USUB16: |
| 5780 | case ARM::t2USUB8: { |
| 5781 | // op: Rd |
| 5782 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5783 | Value |= (op & 0xf) << 8; |
| 5784 | // op: Rn |
| 5785 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5786 | Value |= (op & 0xf) << 16; |
| 5787 | // op: Rm |
| 5788 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5789 | Value |= (op & 0xf); |
| 5790 | break; |
| 5791 | } |
| 5792 | case ARM::t2MLA: |
| 5793 | case ARM::t2MLS: |
| 5794 | case ARM::t2SMLABB: |
| 5795 | case ARM::t2SMLABT: |
| 5796 | case ARM::t2SMLAD: |
| 5797 | case ARM::t2SMLADX: |
| 5798 | case ARM::t2SMLATB: |
| 5799 | case ARM::t2SMLATT: |
| 5800 | case ARM::t2SMLAWB: |
| 5801 | case ARM::t2SMLAWT: |
| 5802 | case ARM::t2SMLSD: |
| 5803 | case ARM::t2SMLSDX: |
| 5804 | case ARM::t2SMMLA: |
| 5805 | case ARM::t2SMMLAR: |
| 5806 | case ARM::t2SMMLS: |
| 5807 | case ARM::t2SMMLSR: |
| 5808 | case ARM::t2USADA8: { |
| 5809 | // op: Rd |
| 5810 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5811 | Value |= (op & 0xf) << 8; |
| 5812 | // op: Rn |
| 5813 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5814 | Value |= (op & 0xf) << 16; |
| 5815 | // op: Rm |
| 5816 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5817 | Value |= (op & 0xf); |
| 5818 | // op: Ra |
| 5819 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5820 | Value |= (op & 0xf) << 12; |
| 5821 | break; |
| 5822 | } |
| 5823 | case ARM::t2SXTAB: |
| 5824 | case ARM::t2SXTAB16: |
| 5825 | case ARM::t2SXTAH: |
| 5826 | case ARM::t2UXTAB: |
| 5827 | case ARM::t2UXTAB16: |
| 5828 | case ARM::t2UXTAH: { |
| 5829 | // op: Rd |
| 5830 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5831 | Value |= (op & 0xf) << 8; |
| 5832 | // op: Rn |
| 5833 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5834 | Value |= (op & 0xf) << 16; |
| 5835 | // op: Rm |
| 5836 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5837 | Value |= (op & 0xf); |
| 5838 | // op: rot |
| 5839 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5840 | Value |= (op & 0x3) << 4; |
| 5841 | break; |
| 5842 | } |
| 5843 | case ARM::t2PKHBT: |
| 5844 | case ARM::t2PKHTB: { |
| 5845 | // op: Rd |
| 5846 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5847 | Value |= (op & 0xf) << 8; |
| 5848 | // op: Rn |
| 5849 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5850 | Value |= (op & 0xf) << 16; |
| 5851 | // op: Rm |
| 5852 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5853 | Value |= (op & 0xf); |
| 5854 | // op: sh |
| 5855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5856 | Value |= (op & 0x1c) << 10; |
| 5857 | Value |= (op & 0x3) << 6; |
| 5858 | break; |
| 5859 | } |
| 5860 | case ARM::t2ADDri12: |
| 5861 | case ARM::t2SUBri12: { |
| 5862 | // op: Rd |
| 5863 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5864 | Value |= (op & 0xf) << 8; |
| 5865 | // op: Rn |
| 5866 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5867 | Value |= (op & 0xf) << 16; |
| 5868 | // op: imm |
| 5869 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5870 | Value |= (op & 0x800) << 15; |
| 5871 | Value |= (op & 0x700) << 4; |
| 5872 | Value |= (op & 0xff); |
| 5873 | break; |
| 5874 | } |
| 5875 | case ARM::t2QADD: |
| 5876 | case ARM::t2QDADD: |
| 5877 | case ARM::t2QDSUB: |
| 5878 | case ARM::t2QSUB: { |
| 5879 | // op: Rd |
| 5880 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5881 | Value |= (op & 0xf) << 8; |
| 5882 | // op: Rn |
| 5883 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5884 | Value |= (op & 0xf) << 16; |
| 5885 | // op: Rm |
| 5886 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5887 | Value |= (op & 0xf); |
| 5888 | break; |
| 5889 | } |
| 5890 | case ARM::t2BFI: { |
| 5891 | // op: Rd |
| 5892 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5893 | Value |= (op & 0xf) << 8; |
| 5894 | // op: Rn |
| 5895 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5896 | Value |= (op & 0xf) << 16; |
| 5897 | // op: imm |
| 5898 | op = getBitfieldInvertedMaskOpValue(MI, Op: 3, Fixups, STI); |
| 5899 | Value |= (op & 0x1c) << 10; |
| 5900 | Value |= (op & 0x3) << 6; |
| 5901 | Value |= (op & 0x3e0) >> 5; |
| 5902 | break; |
| 5903 | } |
| 5904 | case ARM::t2SSAT: |
| 5905 | case ARM::t2USAT: { |
| 5906 | // op: Rd |
| 5907 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5908 | Value |= (op & 0xf) << 8; |
| 5909 | // op: Rn |
| 5910 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5911 | Value |= (op & 0xf) << 16; |
| 5912 | // op: sat_imm |
| 5913 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5914 | Value |= (op & 0x1f); |
| 5915 | // op: sh |
| 5916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5917 | Value |= (op & 0x20) << 16; |
| 5918 | Value |= (op & 0x1c) << 10; |
| 5919 | Value |= (op & 0x3) << 6; |
| 5920 | break; |
| 5921 | } |
| 5922 | case ARM::t2SSAT16: |
| 5923 | case ARM::t2USAT16: { |
| 5924 | // op: Rd |
| 5925 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5926 | Value |= (op & 0xf) << 8; |
| 5927 | // op: Rn |
| 5928 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5929 | Value |= (op & 0xf) << 16; |
| 5930 | // op: sat_imm |
| 5931 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5932 | Value |= (op & 0xf); |
| 5933 | break; |
| 5934 | } |
| 5935 | case ARM::t2PACG: { |
| 5936 | // op: Rd |
| 5937 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5938 | Value |= (op & 0xf) << 8; |
| 5939 | // op: Rn |
| 5940 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5941 | Value |= (op & 0xf) << 16; |
| 5942 | // op: Rm |
| 5943 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5944 | Value |= (op & 0xf); |
| 5945 | break; |
| 5946 | } |
| 5947 | case ARM::t2STREX: { |
| 5948 | // op: Rd |
| 5949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5950 | Value |= (op & 0xf) << 8; |
| 5951 | // op: Rt |
| 5952 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5953 | Value |= (op & 0xf) << 12; |
| 5954 | // op: addr |
| 5955 | op = getT2AddrModeImm0_1020s4OpValue(MI, OpIdx: 2, Fixups, STI); |
| 5956 | Value |= (op & 0xf00) << 8; |
| 5957 | Value |= (op & 0xff); |
| 5958 | break; |
| 5959 | } |
| 5960 | case ARM::t2MRS_M: { |
| 5961 | // op: Rd |
| 5962 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5963 | Value |= (op & 0xf) << 8; |
| 5964 | // op: SYSm |
| 5965 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5966 | Value |= (op & 0xff); |
| 5967 | break; |
| 5968 | } |
| 5969 | case ARM::t2ADR: { |
| 5970 | // op: Rd |
| 5971 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5972 | Value |= (op & 0xf) << 8; |
| 5973 | // op: addr |
| 5974 | op = getT2AdrLabelOpValue(MI, OpIdx: 1, Fixups, STI); |
| 5975 | Value |= (op & 0x800) << 15; |
| 5976 | Value |= (op & 0x1000) << 11; |
| 5977 | Value |= (op & 0x1000) << 9; |
| 5978 | Value |= (op & 0x700) << 4; |
| 5979 | Value |= (op & 0xff); |
| 5980 | break; |
| 5981 | } |
| 5982 | case ARM::t2BFC: { |
| 5983 | // op: Rd |
| 5984 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5985 | Value |= (op & 0xf) << 8; |
| 5986 | // op: imm |
| 5987 | op = getBitfieldInvertedMaskOpValue(MI, Op: 2, Fixups, STI); |
| 5988 | Value |= (op & 0x1c) << 10; |
| 5989 | Value |= (op & 0x3) << 6; |
| 5990 | Value |= (op & 0x3e0) >> 5; |
| 5991 | break; |
| 5992 | } |
| 5993 | case ARM::t2MOVi16: { |
| 5994 | // op: Rd |
| 5995 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5996 | Value |= (op & 0xf) << 8; |
| 5997 | // op: imm |
| 5998 | op = getHiLoImmOpValue(MI, OpIdx: 1, Fixups, STI); |
| 5999 | Value |= (op & 0x800) << 15; |
| 6000 | Value |= (op & 0xf000) << 4; |
| 6001 | Value |= (op & 0x700) << 4; |
| 6002 | Value |= (op & 0xff); |
| 6003 | break; |
| 6004 | } |
| 6005 | case ARM::t2MOVTi16: { |
| 6006 | // op: Rd |
| 6007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6008 | Value |= (op & 0xf) << 8; |
| 6009 | // op: imm |
| 6010 | op = getHiLoImmOpValue(MI, OpIdx: 2, Fixups, STI); |
| 6011 | Value |= (op & 0x800) << 15; |
| 6012 | Value |= (op & 0xf000) << 4; |
| 6013 | Value |= (op & 0x700) << 4; |
| 6014 | Value |= (op & 0xff); |
| 6015 | break; |
| 6016 | } |
| 6017 | case ARM::t2SBFX: |
| 6018 | case ARM::t2UBFX: { |
| 6019 | // op: Rd |
| 6020 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6021 | Value |= (op & 0xf) << 8; |
| 6022 | // op: msb |
| 6023 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6024 | Value |= (op & 0x1f); |
| 6025 | // op: lsb |
| 6026 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6027 | Value |= (op & 0x1c) << 10; |
| 6028 | Value |= (op & 0x3) << 6; |
| 6029 | // op: Rn |
| 6030 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6031 | Value |= (op & 0xf) << 16; |
| 6032 | break; |
| 6033 | } |
| 6034 | case ARM::t2STLEX: { |
| 6035 | // op: Rd |
| 6036 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6037 | Value |= (op & 0xf); |
| 6038 | // op: Rt |
| 6039 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6040 | Value |= (op & 0xf) << 12; |
| 6041 | // op: addr |
| 6042 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6043 | Value |= (op & 0xf) << 16; |
| 6044 | break; |
| 6045 | } |
| 6046 | case ARM::t2STLEXB: |
| 6047 | case ARM::t2STLEXH: |
| 6048 | case ARM::t2STREXB: |
| 6049 | case ARM::t2STREXH: { |
| 6050 | // op: Rd |
| 6051 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6052 | Value |= (op & 0xf); |
| 6053 | // op: addr |
| 6054 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6055 | Value |= (op & 0xf) << 16; |
| 6056 | // op: Rt |
| 6057 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6058 | Value |= (op & 0xf) << 12; |
| 6059 | break; |
| 6060 | } |
| 6061 | case ARM::t2STLEXD: |
| 6062 | case ARM::t2STREXD: { |
| 6063 | // op: Rd |
| 6064 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6065 | Value |= (op & 0xf); |
| 6066 | // op: addr |
| 6067 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6068 | Value |= (op & 0xf) << 16; |
| 6069 | // op: Rt |
| 6070 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6071 | Value |= (op & 0xf) << 12; |
| 6072 | // op: Rt2 |
| 6073 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6074 | Value |= (op & 0xf) << 8; |
| 6075 | break; |
| 6076 | } |
| 6077 | case ARM::t2SMLALD: |
| 6078 | case ARM::t2SMLALDX: |
| 6079 | case ARM::t2SMLSLD: |
| 6080 | case ARM::t2SMLSLDX: { |
| 6081 | // op: Rd |
| 6082 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6083 | Value |= (op & 0xf) << 8; |
| 6084 | // op: Rn |
| 6085 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6086 | Value |= (op & 0xf) << 16; |
| 6087 | // op: Rm |
| 6088 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6089 | Value |= (op & 0xf); |
| 6090 | // op: Ra |
| 6091 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6092 | Value |= (op & 0xf) << 12; |
| 6093 | break; |
| 6094 | } |
| 6095 | case ARM::t2SMLAL: |
| 6096 | case ARM::t2SMLALBB: |
| 6097 | case ARM::t2SMLALBT: |
| 6098 | case ARM::t2SMLALTB: |
| 6099 | case ARM::t2SMLALTT: |
| 6100 | case ARM::t2SMULL: |
| 6101 | case ARM::t2UMAAL: |
| 6102 | case ARM::t2UMLAL: |
| 6103 | case ARM::t2UMULL: { |
| 6104 | // op: RdLo |
| 6105 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6106 | Value |= (op & 0xf) << 12; |
| 6107 | // op: RdHi |
| 6108 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6109 | Value |= (op & 0xf) << 8; |
| 6110 | // op: Rn |
| 6111 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6112 | Value |= (op & 0xf) << 16; |
| 6113 | // op: Rm |
| 6114 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6115 | Value |= (op & 0xf); |
| 6116 | break; |
| 6117 | } |
| 6118 | case ARM::MVE_VMLADAVs16: |
| 6119 | case ARM::MVE_VMLADAVs32: |
| 6120 | case ARM::MVE_VMLADAVs8: |
| 6121 | case ARM::MVE_VMLADAVu16: |
| 6122 | case ARM::MVE_VMLADAVu32: |
| 6123 | case ARM::MVE_VMLADAVu8: |
| 6124 | case ARM::MVE_VMLADAVxs16: |
| 6125 | case ARM::MVE_VMLADAVxs32: |
| 6126 | case ARM::MVE_VMLADAVxs8: |
| 6127 | case ARM::MVE_VMLSDAVs16: |
| 6128 | case ARM::MVE_VMLSDAVs32: |
| 6129 | case ARM::MVE_VMLSDAVs8: |
| 6130 | case ARM::MVE_VMLSDAVxs16: |
| 6131 | case ARM::MVE_VMLSDAVxs32: |
| 6132 | case ARM::MVE_VMLSDAVxs8: { |
| 6133 | // op: RdaDest |
| 6134 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6135 | Value |= (op & 0xe) << 12; |
| 6136 | // op: Qm |
| 6137 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6138 | Value |= (op & 0x7) << 1; |
| 6139 | // op: Qn |
| 6140 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6141 | Value |= (op & 0x7) << 17; |
| 6142 | break; |
| 6143 | } |
| 6144 | case ARM::MVE_VMLADAVas16: |
| 6145 | case ARM::MVE_VMLADAVas32: |
| 6146 | case ARM::MVE_VMLADAVas8: |
| 6147 | case ARM::MVE_VMLADAVau16: |
| 6148 | case ARM::MVE_VMLADAVau32: |
| 6149 | case ARM::MVE_VMLADAVau8: |
| 6150 | case ARM::MVE_VMLADAVaxs16: |
| 6151 | case ARM::MVE_VMLADAVaxs32: |
| 6152 | case ARM::MVE_VMLADAVaxs8: |
| 6153 | case ARM::MVE_VMLSDAVas16: |
| 6154 | case ARM::MVE_VMLSDAVas32: |
| 6155 | case ARM::MVE_VMLSDAVas8: |
| 6156 | case ARM::MVE_VMLSDAVaxs16: |
| 6157 | case ARM::MVE_VMLSDAVaxs32: |
| 6158 | case ARM::MVE_VMLSDAVaxs8: { |
| 6159 | // op: RdaDest |
| 6160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6161 | Value |= (op & 0xe) << 12; |
| 6162 | // op: Qm |
| 6163 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6164 | Value |= (op & 0x7) << 1; |
| 6165 | // op: Qn |
| 6166 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6167 | Value |= (op & 0x7) << 17; |
| 6168 | break; |
| 6169 | } |
| 6170 | case ARM::MVE_SQRSHR: |
| 6171 | case ARM::MVE_UQRSHL: { |
| 6172 | // op: RdaDest |
| 6173 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6174 | Value |= (op & 0xf) << 16; |
| 6175 | // op: Rm |
| 6176 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6177 | Value |= (op & 0xf) << 12; |
| 6178 | break; |
| 6179 | } |
| 6180 | case ARM::MVE_SQSHL: |
| 6181 | case ARM::MVE_SRSHR: |
| 6182 | case ARM::MVE_UQSHL: |
| 6183 | case ARM::MVE_URSHR: { |
| 6184 | // op: RdaDest |
| 6185 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6186 | Value |= (op & 0xf) << 16; |
| 6187 | // op: imm |
| 6188 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6189 | Value |= (op & 0x1c) << 10; |
| 6190 | Value |= (op & 0x3) << 6; |
| 6191 | break; |
| 6192 | } |
| 6193 | case ARM::MVE_ASRLr: |
| 6194 | case ARM::MVE_LSLLr: { |
| 6195 | // op: RdaLo |
| 6196 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6197 | Value |= (op & 0xe) << 16; |
| 6198 | // op: RdaHi |
| 6199 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6200 | Value |= (op & 0xe) << 8; |
| 6201 | // op: Rm |
| 6202 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6203 | Value |= (op & 0xf) << 12; |
| 6204 | break; |
| 6205 | } |
| 6206 | case ARM::MVE_SQRSHRL: |
| 6207 | case ARM::MVE_UQRSHLL: { |
| 6208 | // op: RdaLo |
| 6209 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6210 | Value |= (op & 0xe) << 16; |
| 6211 | // op: RdaHi |
| 6212 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6213 | Value |= (op & 0xe) << 8; |
| 6214 | // op: Rm |
| 6215 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6216 | Value |= (op & 0xf) << 12; |
| 6217 | // op: sat |
| 6218 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 6219 | Value |= (op & 0x1) << 7; |
| 6220 | break; |
| 6221 | } |
| 6222 | case ARM::MVE_ASRLi: |
| 6223 | case ARM::MVE_LSLLi: |
| 6224 | case ARM::MVE_LSRL: |
| 6225 | case ARM::MVE_SQSHLL: |
| 6226 | case ARM::MVE_SRSHRL: |
| 6227 | case ARM::MVE_UQSHLL: |
| 6228 | case ARM::MVE_URSHRL: { |
| 6229 | // op: RdaLo |
| 6230 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6231 | Value |= (op & 0xe) << 16; |
| 6232 | // op: RdaHi |
| 6233 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6234 | Value |= (op & 0xe) << 8; |
| 6235 | // op: imm |
| 6236 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6237 | Value |= (op & 0x1c) << 10; |
| 6238 | Value |= (op & 0x3) << 6; |
| 6239 | break; |
| 6240 | } |
| 6241 | case ARM::MVE_VMLALDAVs16: |
| 6242 | case ARM::MVE_VMLALDAVs32: |
| 6243 | case ARM::MVE_VMLALDAVu16: |
| 6244 | case ARM::MVE_VMLALDAVu32: |
| 6245 | case ARM::MVE_VMLALDAVxs16: |
| 6246 | case ARM::MVE_VMLALDAVxs32: |
| 6247 | case ARM::MVE_VMLSLDAVs16: |
| 6248 | case ARM::MVE_VMLSLDAVs32: |
| 6249 | case ARM::MVE_VMLSLDAVxs16: |
| 6250 | case ARM::MVE_VMLSLDAVxs32: |
| 6251 | case ARM::MVE_VRMLALDAVHs32: |
| 6252 | case ARM::MVE_VRMLALDAVHu32: |
| 6253 | case ARM::MVE_VRMLALDAVHxs32: |
| 6254 | case ARM::MVE_VRMLSLDAVHs32: |
| 6255 | case ARM::MVE_VRMLSLDAVHxs32: { |
| 6256 | // op: RdaLoDest |
| 6257 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6258 | Value |= (op & 0xe) << 12; |
| 6259 | // op: RdaHiDest |
| 6260 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6261 | Value |= (op & 0xe) << 19; |
| 6262 | // op: Qm |
| 6263 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6264 | Value |= (op & 0x7) << 1; |
| 6265 | // op: Qn |
| 6266 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6267 | Value |= (op & 0x7) << 17; |
| 6268 | break; |
| 6269 | } |
| 6270 | case ARM::MVE_VMLALDAVas16: |
| 6271 | case ARM::MVE_VMLALDAVas32: |
| 6272 | case ARM::MVE_VMLALDAVau16: |
| 6273 | case ARM::MVE_VMLALDAVau32: |
| 6274 | case ARM::MVE_VMLALDAVaxs16: |
| 6275 | case ARM::MVE_VMLALDAVaxs32: |
| 6276 | case ARM::MVE_VMLSLDAVas16: |
| 6277 | case ARM::MVE_VMLSLDAVas32: |
| 6278 | case ARM::MVE_VMLSLDAVaxs16: |
| 6279 | case ARM::MVE_VMLSLDAVaxs32: |
| 6280 | case ARM::MVE_VRMLALDAVHas32: |
| 6281 | case ARM::MVE_VRMLALDAVHau32: |
| 6282 | case ARM::MVE_VRMLALDAVHaxs32: |
| 6283 | case ARM::MVE_VRMLSLDAVHas32: |
| 6284 | case ARM::MVE_VRMLSLDAVHaxs32: { |
| 6285 | // op: RdaLoDest |
| 6286 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6287 | Value |= (op & 0xe) << 12; |
| 6288 | // op: RdaHiDest |
| 6289 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6290 | Value |= (op & 0xe) << 19; |
| 6291 | // op: Qm |
| 6292 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 6293 | Value |= (op & 0x7) << 1; |
| 6294 | // op: Qn |
| 6295 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6296 | Value |= (op & 0x7) << 17; |
| 6297 | break; |
| 6298 | } |
| 6299 | case ARM::tADDi8: { |
| 6300 | // op: Rdn |
| 6301 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6302 | Value |= (op & 0x7) << 8; |
| 6303 | // op: imm8 |
| 6304 | op = getHiLoImmOpValue(MI, OpIdx: 3, Fixups, STI); |
| 6305 | Value |= (op & 0xff); |
| 6306 | break; |
| 6307 | } |
| 6308 | case ARM::tSUBi8: { |
| 6309 | // op: Rdn |
| 6310 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6311 | Value |= (op & 0x7) << 8; |
| 6312 | // op: imm8 |
| 6313 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6314 | Value |= (op & 0xff); |
| 6315 | break; |
| 6316 | } |
| 6317 | case ARM::tADC: |
| 6318 | case ARM::tAND: |
| 6319 | case ARM::tASRrr: |
| 6320 | case ARM::tBIC: |
| 6321 | case ARM::tEOR: |
| 6322 | case ARM::tLSLrr: |
| 6323 | case ARM::tLSRrr: |
| 6324 | case ARM::tORR: |
| 6325 | case ARM::tROR: |
| 6326 | case ARM::tSBC: { |
| 6327 | // op: Rdn |
| 6328 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6329 | Value |= (op & 0x7); |
| 6330 | // op: Rm |
| 6331 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6332 | Value |= (op & 0x7) << 3; |
| 6333 | break; |
| 6334 | } |
| 6335 | case ARM::tADDrSP: { |
| 6336 | // op: Rdn |
| 6337 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6338 | Value |= (op & 0x8) << 4; |
| 6339 | Value |= (op & 0x7); |
| 6340 | break; |
| 6341 | } |
| 6342 | case ARM::tADDhirr: { |
| 6343 | // op: Rdn |
| 6344 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6345 | Value |= (op & 0x8) << 4; |
| 6346 | Value |= (op & 0x7); |
| 6347 | // op: Rm |
| 6348 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6349 | Value |= (op & 0xf) << 3; |
| 6350 | break; |
| 6351 | } |
| 6352 | case ARM::tBX: |
| 6353 | case ARM::tBXNS: { |
| 6354 | // op: Rm |
| 6355 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6356 | Value |= (op & 0xf) << 3; |
| 6357 | break; |
| 6358 | } |
| 6359 | case ARM::tREV: |
| 6360 | case ARM::tREV16: |
| 6361 | case ARM::tREVSH: |
| 6362 | case ARM::tSXTB: |
| 6363 | case ARM::tSXTH: |
| 6364 | case ARM::tUXTB: |
| 6365 | case ARM::tUXTH: { |
| 6366 | // op: Rm |
| 6367 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6368 | Value |= (op & 0x7) << 3; |
| 6369 | // op: Rd |
| 6370 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6371 | Value |= (op & 0x7); |
| 6372 | break; |
| 6373 | } |
| 6374 | case ARM::tCMNz: |
| 6375 | case ARM::tCMPr: |
| 6376 | case ARM::tTST: { |
| 6377 | // op: Rm |
| 6378 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6379 | Value |= (op & 0x7) << 3; |
| 6380 | // op: Rn |
| 6381 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6382 | Value |= (op & 0x7); |
| 6383 | break; |
| 6384 | } |
| 6385 | case ARM::tCMPhir: { |
| 6386 | // op: Rm |
| 6387 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6388 | Value |= (op & 0xf) << 3; |
| 6389 | // op: Rn |
| 6390 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6391 | Value |= (op & 0x8) << 4; |
| 6392 | Value |= (op & 0x7); |
| 6393 | break; |
| 6394 | } |
| 6395 | case ARM::tADDspr: { |
| 6396 | // op: Rm |
| 6397 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6398 | Value |= (op & 0xf) << 3; |
| 6399 | break; |
| 6400 | } |
| 6401 | case ARM::tADDrr: |
| 6402 | case ARM::tSUBrr: { |
| 6403 | // op: Rm |
| 6404 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6405 | Value |= (op & 0x7) << 6; |
| 6406 | // op: Rn |
| 6407 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6408 | Value |= (op & 0x7) << 3; |
| 6409 | // op: Rd |
| 6410 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6411 | Value |= (op & 0x7); |
| 6412 | break; |
| 6413 | } |
| 6414 | case ARM::tCMPi8: { |
| 6415 | // op: Rn |
| 6416 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6417 | Value |= (op & 0x7) << 8; |
| 6418 | // op: imm8 |
| 6419 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6420 | Value |= (op & 0xff); |
| 6421 | break; |
| 6422 | } |
| 6423 | case ARM::tLDMIA: { |
| 6424 | // op: Rn |
| 6425 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6426 | Value |= (op & 0x7) << 8; |
| 6427 | // op: regs |
| 6428 | op = getRegisterListOpValue(MI, Op: 3, Fixups, STI); |
| 6429 | Value |= (op & 0xff); |
| 6430 | break; |
| 6431 | } |
| 6432 | case ARM::RFEDA: |
| 6433 | case ARM::RFEDA_UPD: |
| 6434 | case ARM::RFEDB: |
| 6435 | case ARM::RFEDB_UPD: |
| 6436 | case ARM::RFEIA: |
| 6437 | case ARM::RFEIA_UPD: |
| 6438 | case ARM::RFEIB: |
| 6439 | case ARM::RFEIB_UPD: |
| 6440 | case ARM::VLLDM: |
| 6441 | case ARM::VLLDM_T2: |
| 6442 | case ARM::VLSTM: |
| 6443 | case ARM::VLSTM_T2: |
| 6444 | case ARM::t2RFEDB: |
| 6445 | case ARM::t2RFEDBW: |
| 6446 | case ARM::t2RFEIA: |
| 6447 | case ARM::t2RFEIAW: { |
| 6448 | // op: Rn |
| 6449 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6450 | Value |= (op & 0xf) << 16; |
| 6451 | break; |
| 6452 | } |
| 6453 | case ARM::t2CMNzrr: |
| 6454 | case ARM::t2CMPrr: |
| 6455 | case ARM::t2TBB: |
| 6456 | case ARM::t2TBH: |
| 6457 | case ARM::t2TEQrr: |
| 6458 | case ARM::t2TSTrr: { |
| 6459 | // op: Rn |
| 6460 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6461 | Value |= (op & 0xf) << 16; |
| 6462 | // op: Rm |
| 6463 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6464 | Value |= (op & 0xf); |
| 6465 | break; |
| 6466 | } |
| 6467 | case ARM::t2CMNzrs: |
| 6468 | case ARM::t2CMPrs: |
| 6469 | case ARM::t2TEQrs: |
| 6470 | case ARM::t2TSTrs: { |
| 6471 | // op: Rn |
| 6472 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6473 | Value |= (op & 0xf) << 16; |
| 6474 | // op: ShiftedRm |
| 6475 | op = getT2SORegOpValue(MI, OpIdx: 1, Fixups, STI); |
| 6476 | Value |= (op & 0xe00) << 3; |
| 6477 | Value |= (op & 0x1e0) >> 1; |
| 6478 | Value |= (op & 0xf); |
| 6479 | break; |
| 6480 | } |
| 6481 | case ARM::t2CMNri: |
| 6482 | case ARM::t2CMPri: |
| 6483 | case ARM::t2TEQri: |
| 6484 | case ARM::t2TSTri: { |
| 6485 | // op: Rn |
| 6486 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6487 | Value |= (op & 0xf) << 16; |
| 6488 | // op: imm |
| 6489 | op = getT2SOImmOpValue(MI, Op: 1, Fixups, STI); |
| 6490 | Value |= (op & 0x800) << 15; |
| 6491 | Value |= (op & 0x700) << 4; |
| 6492 | Value |= (op & 0xff); |
| 6493 | break; |
| 6494 | } |
| 6495 | case ARM::t2STMDB: |
| 6496 | case ARM::t2STMIA: { |
| 6497 | // op: Rn |
| 6498 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6499 | Value |= (op & 0xf) << 16; |
| 6500 | // op: regs |
| 6501 | op = getRegisterListOpValue(MI, Op: 3, Fixups, STI); |
| 6502 | Value |= (op & 0x4000); |
| 6503 | Value |= (op & 0x1fff); |
| 6504 | break; |
| 6505 | } |
| 6506 | case ARM::t2LDMDB: |
| 6507 | case ARM::t2LDMIA: { |
| 6508 | // op: Rn |
| 6509 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6510 | Value |= (op & 0xf) << 16; |
| 6511 | // op: regs |
| 6512 | op = getRegisterListOpValue(MI, Op: 3, Fixups, STI); |
| 6513 | Value |= (op & 0xffff); |
| 6514 | break; |
| 6515 | } |
| 6516 | case ARM::tSTMIA_UPD: { |
| 6517 | // op: Rn |
| 6518 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6519 | Value |= (op & 0x7) << 8; |
| 6520 | // op: regs |
| 6521 | op = getRegisterListOpValue(MI, Op: 4, Fixups, STI); |
| 6522 | Value |= (op & 0xff); |
| 6523 | break; |
| 6524 | } |
| 6525 | case ARM::MVE_DLSTP_16: |
| 6526 | case ARM::MVE_DLSTP_32: |
| 6527 | case ARM::MVE_DLSTP_64: |
| 6528 | case ARM::MVE_DLSTP_8: |
| 6529 | case ARM::MVE_VCTP16: |
| 6530 | case ARM::MVE_VCTP32: |
| 6531 | case ARM::MVE_VCTP64: |
| 6532 | case ARM::MVE_VCTP8: |
| 6533 | case ARM::t2DLS: { |
| 6534 | // op: Rn |
| 6535 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6536 | Value |= (op & 0xf) << 16; |
| 6537 | break; |
| 6538 | } |
| 6539 | case ARM::t2TT: |
| 6540 | case ARM::t2TTA: |
| 6541 | case ARM::t2TTAT: |
| 6542 | case ARM::t2TTT: { |
| 6543 | // op: Rn |
| 6544 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6545 | Value |= (op & 0xf) << 16; |
| 6546 | // op: Rt |
| 6547 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6548 | Value |= (op & 0xf) << 8; |
| 6549 | break; |
| 6550 | } |
| 6551 | case ARM::MVE_WLSTP_16: |
| 6552 | case ARM::MVE_WLSTP_32: |
| 6553 | case ARM::MVE_WLSTP_64: |
| 6554 | case ARM::MVE_WLSTP_8: |
| 6555 | case ARM::t2WLS: { |
| 6556 | // op: Rn |
| 6557 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6558 | Value |= (op & 0xf) << 16; |
| 6559 | // op: label |
| 6560 | op = getBFTargetOpValue<false, ARM::fixup_wls>(MI, OpIdx: 2, Fixups, STI); |
| 6561 | Value |= (op & 0x1) << 11; |
| 6562 | Value |= (op & 0x7fe); |
| 6563 | break; |
| 6564 | } |
| 6565 | case ARM::t2STMDB_UPD: |
| 6566 | case ARM::t2STMIA_UPD: { |
| 6567 | // op: Rn |
| 6568 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6569 | Value |= (op & 0xf) << 16; |
| 6570 | // op: regs |
| 6571 | op = getRegisterListOpValue(MI, Op: 4, Fixups, STI); |
| 6572 | Value |= (op & 0x4000); |
| 6573 | Value |= (op & 0x1fff); |
| 6574 | break; |
| 6575 | } |
| 6576 | case ARM::t2LDMDB_UPD: |
| 6577 | case ARM::t2LDMIA_UPD: { |
| 6578 | // op: Rn |
| 6579 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6580 | Value |= (op & 0xf) << 16; |
| 6581 | // op: regs |
| 6582 | op = getRegisterListOpValue(MI, Op: 4, Fixups, STI); |
| 6583 | Value |= (op & 0xffff); |
| 6584 | break; |
| 6585 | } |
| 6586 | case ARM::tLDRpci: { |
| 6587 | // op: Rt |
| 6588 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6589 | Value |= (op & 0x7) << 8; |
| 6590 | // op: addr |
| 6591 | op = getAddrModePCOpValue(MI, OpIdx: 1, Fixups, STI); |
| 6592 | Value |= (op & 0xff); |
| 6593 | break; |
| 6594 | } |
| 6595 | case ARM::tLDRspi: |
| 6596 | case ARM::tSTRspi: { |
| 6597 | // op: Rt |
| 6598 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6599 | Value |= (op & 0x7) << 8; |
| 6600 | // op: addr |
| 6601 | op = getAddrModeThumbSPOpValue(MI, OpIdx: 1, Fixups, STI); |
| 6602 | Value |= (op & 0xff); |
| 6603 | break; |
| 6604 | } |
| 6605 | case ARM::tLDRBi: |
| 6606 | case ARM::tLDRHi: |
| 6607 | case ARM::tLDRi: |
| 6608 | case ARM::tSTRBi: |
| 6609 | case ARM::tSTRHi: |
| 6610 | case ARM::tSTRi: { |
| 6611 | // op: Rt |
| 6612 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6613 | Value |= (op & 0x7); |
| 6614 | // op: addr |
| 6615 | op = getAddrModeISOpValue(MI, OpIdx: 1, Fixups, STI); |
| 6616 | Value |= (op & 0xff) << 3; |
| 6617 | break; |
| 6618 | } |
| 6619 | case ARM::tLDRBr: |
| 6620 | case ARM::tLDRHr: |
| 6621 | case ARM::tLDRSB: |
| 6622 | case ARM::tLDRSH: |
| 6623 | case ARM::tLDRr: |
| 6624 | case ARM::tSTRBr: |
| 6625 | case ARM::tSTRHr: |
| 6626 | case ARM::tSTRr: { |
| 6627 | // op: Rt |
| 6628 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6629 | Value |= (op & 0x7); |
| 6630 | // op: addr |
| 6631 | op = getThumbAddrModeRegRegOpValue(MI, OpIdx: 1, Fixups, STI); |
| 6632 | Value |= (op & 0x3f) << 3; |
| 6633 | break; |
| 6634 | } |
| 6635 | case ARM::t2LDRB_POST: |
| 6636 | case ARM::t2LDRH_POST: |
| 6637 | case ARM::t2LDRSB_POST: |
| 6638 | case ARM::t2LDRSH_POST: |
| 6639 | case ARM::t2LDR_POST: { |
| 6640 | // op: Rt |
| 6641 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6642 | Value |= (op & 0xf) << 12; |
| 6643 | // op: Rn |
| 6644 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6645 | Value |= (op & 0xf) << 16; |
| 6646 | // op: offset |
| 6647 | op = getT2AddrModeImm8OffsetOpValue(MI, OpNum: 3, Fixups, STI); |
| 6648 | Value |= (op & 0x100) << 1; |
| 6649 | Value |= (op & 0xff); |
| 6650 | break; |
| 6651 | } |
| 6652 | case ARM::MRRC2: |
| 6653 | case ARM::t2MRRC: |
| 6654 | case ARM::t2MRRC2: { |
| 6655 | // op: Rt |
| 6656 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6657 | Value |= (op & 0xf) << 12; |
| 6658 | // op: Rt2 |
| 6659 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6660 | Value |= (op & 0xf) << 16; |
| 6661 | // op: cop |
| 6662 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6663 | Value |= (op & 0xf) << 8; |
| 6664 | // op: opc1 |
| 6665 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6666 | Value |= (op & 0xf) << 4; |
| 6667 | // op: CRm |
| 6668 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6669 | Value |= (op & 0xf); |
| 6670 | break; |
| 6671 | } |
| 6672 | case ARM::t2LDRD_POST: { |
| 6673 | // op: Rt |
| 6674 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6675 | Value |= (op & 0xf) << 12; |
| 6676 | // op: Rt2 |
| 6677 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6678 | Value |= (op & 0xf) << 8; |
| 6679 | // op: addr |
| 6680 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6681 | Value |= (op & 0xf) << 16; |
| 6682 | // op: imm |
| 6683 | op = getT2ScaledImmOpValue<8,2>(MI, OpIdx: 4, Fixups, STI); |
| 6684 | Value |= (op & 0x100) << 15; |
| 6685 | Value |= (op & 0xff); |
| 6686 | break; |
| 6687 | } |
| 6688 | case ARM::t2LDRDi8: |
| 6689 | case ARM::t2STRDi8: { |
| 6690 | // op: Rt |
| 6691 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6692 | Value |= (op & 0xf) << 12; |
| 6693 | // op: Rt2 |
| 6694 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6695 | Value |= (op & 0xf) << 8; |
| 6696 | // op: addr |
| 6697 | op = getT2AddrModeImm8s4OpValue(MI, OpIdx: 2, Fixups, STI); |
| 6698 | Value |= (op & 0x100) << 15; |
| 6699 | Value |= (op & 0x1e00) << 7; |
| 6700 | Value |= (op & 0xff); |
| 6701 | break; |
| 6702 | } |
| 6703 | case ARM::t2LDRD_PRE: { |
| 6704 | // op: Rt |
| 6705 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6706 | Value |= (op & 0xf) << 12; |
| 6707 | // op: Rt2 |
| 6708 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6709 | Value |= (op & 0xf) << 8; |
| 6710 | // op: addr |
| 6711 | op = getT2AddrModeImm8s4OpValue(MI, OpIdx: 3, Fixups, STI); |
| 6712 | Value |= (op & 0x100) << 15; |
| 6713 | Value |= (op & 0x1e00) << 7; |
| 6714 | Value |= (op & 0xff); |
| 6715 | break; |
| 6716 | } |
| 6717 | case ARM::t2LDRBpci: |
| 6718 | case ARM::t2LDRHpci: |
| 6719 | case ARM::t2LDRSBpci: |
| 6720 | case ARM::t2LDRSHpci: |
| 6721 | case ARM::t2LDRpci: { |
| 6722 | // op: Rt |
| 6723 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6724 | Value |= (op & 0xf) << 12; |
| 6725 | // op: addr |
| 6726 | op = getAddrModeImm12OpValue(MI, OpIdx: 1, Fixups, STI); |
| 6727 | Value |= (op & 0x1000) << 11; |
| 6728 | Value |= (op & 0xfff); |
| 6729 | break; |
| 6730 | } |
| 6731 | case ARM::t2LDRBi12: |
| 6732 | case ARM::t2LDRHi12: |
| 6733 | case ARM::t2LDRSBi12: |
| 6734 | case ARM::t2LDRSHi12: |
| 6735 | case ARM::t2LDRi12: |
| 6736 | case ARM::t2STRBi12: |
| 6737 | case ARM::t2STRHi12: |
| 6738 | case ARM::t2STRi12: { |
| 6739 | // op: Rt |
| 6740 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6741 | Value |= (op & 0xf) << 12; |
| 6742 | // op: addr |
| 6743 | op = getAddrModeImm12OpValue(MI, OpIdx: 1, Fixups, STI); |
| 6744 | Value |= (op & 0x1e000) << 3; |
| 6745 | Value |= (op & 0xfff); |
| 6746 | break; |
| 6747 | } |
| 6748 | case ARM::t2LDA: |
| 6749 | case ARM::t2LDAB: |
| 6750 | case ARM::t2LDAEX: |
| 6751 | case ARM::t2LDAH: |
| 6752 | case ARM::t2STL: |
| 6753 | case ARM::t2STLB: |
| 6754 | case ARM::t2STLH: { |
| 6755 | // op: Rt |
| 6756 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6757 | Value |= (op & 0xf) << 12; |
| 6758 | // op: addr |
| 6759 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6760 | Value |= (op & 0xf) << 16; |
| 6761 | break; |
| 6762 | } |
| 6763 | case ARM::t2LDREX: { |
| 6764 | // op: Rt |
| 6765 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6766 | Value |= (op & 0xf) << 12; |
| 6767 | // op: addr |
| 6768 | op = getT2AddrModeImm0_1020s4OpValue(MI, OpIdx: 1, Fixups, STI); |
| 6769 | Value |= (op & 0xf00) << 8; |
| 6770 | Value |= (op & 0xff); |
| 6771 | break; |
| 6772 | } |
| 6773 | case ARM::t2LDRBi8: |
| 6774 | case ARM::t2LDRHi8: |
| 6775 | case ARM::t2LDRSBi8: |
| 6776 | case ARM::t2LDRSHi8: |
| 6777 | case ARM::t2LDRi8: |
| 6778 | case ARM::t2STRBi8: |
| 6779 | case ARM::t2STRHi8: |
| 6780 | case ARM::t2STRi8: { |
| 6781 | // op: Rt |
| 6782 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6783 | Value |= (op & 0xf) << 12; |
| 6784 | // op: addr |
| 6785 | op = getT2AddrModeImmOpValue<8,0>(MI, OpNum: 1, Fixups, STI); |
| 6786 | Value |= (op & 0x1e00) << 7; |
| 6787 | Value |= (op & 0x100) << 1; |
| 6788 | Value |= (op & 0xff); |
| 6789 | break; |
| 6790 | } |
| 6791 | case ARM::t2LDRBT: |
| 6792 | case ARM::t2LDRHT: |
| 6793 | case ARM::t2LDRSBT: |
| 6794 | case ARM::t2LDRSHT: |
| 6795 | case ARM::t2LDRT: |
| 6796 | case ARM::t2STRBT: |
| 6797 | case ARM::t2STRHT: |
| 6798 | case ARM::t2STRT: { |
| 6799 | // op: Rt |
| 6800 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6801 | Value |= (op & 0xf) << 12; |
| 6802 | // op: addr |
| 6803 | op = getT2AddrModeImmOpValue<8,0>(MI, OpNum: 1, Fixups, STI); |
| 6804 | Value |= (op & 0x1e00) << 7; |
| 6805 | Value |= (op & 0xff); |
| 6806 | break; |
| 6807 | } |
| 6808 | case ARM::t2LDRB_PRE: |
| 6809 | case ARM::t2LDRH_PRE: |
| 6810 | case ARM::t2LDRSB_PRE: |
| 6811 | case ARM::t2LDRSH_PRE: |
| 6812 | case ARM::t2LDR_PRE: { |
| 6813 | // op: Rt |
| 6814 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6815 | Value |= (op & 0xf) << 12; |
| 6816 | // op: addr |
| 6817 | op = getT2AddrModeImmOpValue<8,0>(MI, OpNum: 2, Fixups, STI); |
| 6818 | Value |= (op & 0x1e00) << 7; |
| 6819 | Value |= (op & 0x100) << 1; |
| 6820 | Value |= (op & 0xff); |
| 6821 | break; |
| 6822 | } |
| 6823 | case ARM::t2LDRBs: |
| 6824 | case ARM::t2LDRHs: |
| 6825 | case ARM::t2LDRSBs: |
| 6826 | case ARM::t2LDRSHs: |
| 6827 | case ARM::t2LDRs: |
| 6828 | case ARM::t2STRBs: |
| 6829 | case ARM::t2STRHs: |
| 6830 | case ARM::t2STRs: { |
| 6831 | // op: Rt |
| 6832 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6833 | Value |= (op & 0xf) << 12; |
| 6834 | // op: addr |
| 6835 | op = getT2AddrModeSORegOpValue(MI, OpNum: 1, Fixups, STI); |
| 6836 | Value |= (op & 0x3c0) << 10; |
| 6837 | Value |= (op & 0x3) << 4; |
| 6838 | Value |= (op & 0x3c) >> 2; |
| 6839 | break; |
| 6840 | } |
| 6841 | case ARM::MRC2: |
| 6842 | case ARM::t2MRC: |
| 6843 | case ARM::t2MRC2: { |
| 6844 | // op: Rt |
| 6845 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6846 | Value |= (op & 0xf) << 12; |
| 6847 | // op: cop |
| 6848 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6849 | Value |= (op & 0xf) << 8; |
| 6850 | // op: opc1 |
| 6851 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6852 | Value |= (op & 0x7) << 21; |
| 6853 | // op: opc2 |
| 6854 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 6855 | Value |= (op & 0x7) << 5; |
| 6856 | // op: CRm |
| 6857 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6858 | Value |= (op & 0xf); |
| 6859 | // op: CRn |
| 6860 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6861 | Value |= (op & 0xf) << 16; |
| 6862 | break; |
| 6863 | } |
| 6864 | case ARM::MVE_VMOV_rr_q: { |
| 6865 | // op: Rt |
| 6866 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6867 | Value |= (op & 0xf); |
| 6868 | // op: Rt2 |
| 6869 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6870 | Value |= (op & 0xf) << 16; |
| 6871 | // op: Qd |
| 6872 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6873 | Value |= (op & 0x8) << 19; |
| 6874 | Value |= (op & 0x7) << 13; |
| 6875 | // op: idx2 |
| 6876 | op = getMVEPairVectorIndexOpValue<0>(MI, OpIdx: 4, Fixups, STI); |
| 6877 | Value |= (op & 0x1) << 4; |
| 6878 | break; |
| 6879 | } |
| 6880 | case ARM::t2STRB_POST: |
| 6881 | case ARM::t2STRH_POST: |
| 6882 | case ARM::t2STR_POST: { |
| 6883 | // op: Rt |
| 6884 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6885 | Value |= (op & 0xf) << 12; |
| 6886 | // op: Rn |
| 6887 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6888 | Value |= (op & 0xf) << 16; |
| 6889 | // op: offset |
| 6890 | op = getT2AddrModeImm8OffsetOpValue(MI, OpNum: 3, Fixups, STI); |
| 6891 | Value |= (op & 0x100) << 1; |
| 6892 | Value |= (op & 0xff); |
| 6893 | break; |
| 6894 | } |
| 6895 | case ARM::t2STRD_POST: { |
| 6896 | // op: Rt |
| 6897 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6898 | Value |= (op & 0xf) << 12; |
| 6899 | // op: Rt2 |
| 6900 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6901 | Value |= (op & 0xf) << 8; |
| 6902 | // op: addr |
| 6903 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6904 | Value |= (op & 0xf) << 16; |
| 6905 | // op: imm |
| 6906 | op = getT2ScaledImmOpValue<8,2>(MI, OpIdx: 4, Fixups, STI); |
| 6907 | Value |= (op & 0x100) << 15; |
| 6908 | Value |= (op & 0xff); |
| 6909 | break; |
| 6910 | } |
| 6911 | case ARM::t2STRD_PRE: { |
| 6912 | // op: Rt |
| 6913 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6914 | Value |= (op & 0xf) << 12; |
| 6915 | // op: Rt2 |
| 6916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6917 | Value |= (op & 0xf) << 8; |
| 6918 | // op: addr |
| 6919 | op = getT2AddrModeImm8s4OpValue(MI, OpIdx: 3, Fixups, STI); |
| 6920 | Value |= (op & 0x100) << 15; |
| 6921 | Value |= (op & 0x1e00) << 7; |
| 6922 | Value |= (op & 0xff); |
| 6923 | break; |
| 6924 | } |
| 6925 | case ARM::t2STRB_PRE: |
| 6926 | case ARM::t2STRH_PRE: |
| 6927 | case ARM::t2STR_PRE: { |
| 6928 | // op: Rt |
| 6929 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6930 | Value |= (op & 0xf) << 12; |
| 6931 | // op: addr |
| 6932 | op = getT2AddrModeImmOpValue<8,0>(MI, OpNum: 2, Fixups, STI); |
| 6933 | Value |= (op & 0x1e00) << 7; |
| 6934 | Value |= (op & 0x100) << 1; |
| 6935 | Value |= (op & 0xff); |
| 6936 | break; |
| 6937 | } |
| 6938 | case ARM::MCRR2: |
| 6939 | case ARM::t2MCRR: |
| 6940 | case ARM::t2MCRR2: { |
| 6941 | // op: Rt |
| 6942 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6943 | Value |= (op & 0xf) << 12; |
| 6944 | // op: Rt2 |
| 6945 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6946 | Value |= (op & 0xf) << 16; |
| 6947 | // op: cop |
| 6948 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6949 | Value |= (op & 0xf) << 8; |
| 6950 | // op: opc1 |
| 6951 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6952 | Value |= (op & 0xf) << 4; |
| 6953 | // op: CRm |
| 6954 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6955 | Value |= (op & 0xf); |
| 6956 | break; |
| 6957 | } |
| 6958 | case ARM::MCR2: |
| 6959 | case ARM::t2MCR: |
| 6960 | case ARM::t2MCR2: { |
| 6961 | // op: Rt |
| 6962 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6963 | Value |= (op & 0xf) << 12; |
| 6964 | // op: cop |
| 6965 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6966 | Value |= (op & 0xf) << 8; |
| 6967 | // op: opc1 |
| 6968 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6969 | Value |= (op & 0x7) << 21; |
| 6970 | // op: opc2 |
| 6971 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 6972 | Value |= (op & 0x7) << 5; |
| 6973 | // op: CRm |
| 6974 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6975 | Value |= (op & 0xf); |
| 6976 | // op: CRn |
| 6977 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6978 | Value |= (op & 0xf) << 16; |
| 6979 | break; |
| 6980 | } |
| 6981 | case ARM::MVE_VMOV_q_rr: { |
| 6982 | // op: Rt |
| 6983 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6984 | Value |= (op & 0xf); |
| 6985 | // op: Rt2 |
| 6986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6987 | Value |= (op & 0xf) << 16; |
| 6988 | // op: Qd |
| 6989 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6990 | Value |= (op & 0x8) << 19; |
| 6991 | Value |= (op & 0x7) << 13; |
| 6992 | // op: idx2 |
| 6993 | op = getMVEPairVectorIndexOpValue<0>(MI, OpIdx: 5, Fixups, STI); |
| 6994 | Value |= (op & 0x1) << 4; |
| 6995 | break; |
| 6996 | } |
| 6997 | case ARM::t2MSR_M: { |
| 6998 | // op: SYSm |
| 6999 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7000 | Value |= (op & 0xc00); |
| 7001 | Value |= (op & 0xff); |
| 7002 | // op: Rn |
| 7003 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7004 | Value |= (op & 0xf) << 16; |
| 7005 | break; |
| 7006 | } |
| 7007 | case ARM::VCVTASD: |
| 7008 | case ARM::VCVTAUD: |
| 7009 | case ARM::VCVTMSD: |
| 7010 | case ARM::VCVTMUD: |
| 7011 | case ARM::VCVTNSD: |
| 7012 | case ARM::VCVTNUD: |
| 7013 | case ARM::VCVTPSD: |
| 7014 | case ARM::VCVTPUD: { |
| 7015 | // op: Sd |
| 7016 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7017 | Value |= (op & 0x1) << 22; |
| 7018 | Value |= (op & 0x1e) << 11; |
| 7019 | // op: Dm |
| 7020 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7021 | Value |= (op & 0x10) << 1; |
| 7022 | Value |= (op & 0xf); |
| 7023 | break; |
| 7024 | } |
| 7025 | case ARM::VCVTASH: |
| 7026 | case ARM::VCVTASS: |
| 7027 | case ARM::VCVTAUH: |
| 7028 | case ARM::VCVTAUS: |
| 7029 | case ARM::VCVTMSH: |
| 7030 | case ARM::VCVTMSS: |
| 7031 | case ARM::VCVTMUH: |
| 7032 | case ARM::VCVTMUS: |
| 7033 | case ARM::VCVTNSH: |
| 7034 | case ARM::VCVTNSS: |
| 7035 | case ARM::VCVTNUH: |
| 7036 | case ARM::VCVTNUS: |
| 7037 | case ARM::VCVTPSH: |
| 7038 | case ARM::VCVTPSS: |
| 7039 | case ARM::VCVTPUH: |
| 7040 | case ARM::VCVTPUS: |
| 7041 | case ARM::VMOVH: |
| 7042 | case ARM::VRINTAH: |
| 7043 | case ARM::VRINTAS: |
| 7044 | case ARM::VRINTMH: |
| 7045 | case ARM::VRINTMS: |
| 7046 | case ARM::VRINTNH: |
| 7047 | case ARM::VRINTNS: |
| 7048 | case ARM::VRINTPH: |
| 7049 | case ARM::VRINTPS: { |
| 7050 | // op: Sd |
| 7051 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7052 | Value |= (op & 0x1) << 22; |
| 7053 | Value |= (op & 0x1e) << 11; |
| 7054 | // op: Sm |
| 7055 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7056 | Value |= (op & 0x1) << 5; |
| 7057 | Value |= (op & 0x1e) >> 1; |
| 7058 | break; |
| 7059 | } |
| 7060 | case ARM::VINSH: { |
| 7061 | // op: Sd |
| 7062 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7063 | Value |= (op & 0x1) << 22; |
| 7064 | Value |= (op & 0x1e) << 11; |
| 7065 | // op: Sm |
| 7066 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7067 | Value |= (op & 0x1) << 5; |
| 7068 | Value |= (op & 0x1e) >> 1; |
| 7069 | break; |
| 7070 | } |
| 7071 | case ARM::VFP_VMAXNMH: |
| 7072 | case ARM::VFP_VMAXNMS: |
| 7073 | case ARM::VFP_VMINNMH: |
| 7074 | case ARM::VFP_VMINNMS: |
| 7075 | case ARM::VSELEQH: |
| 7076 | case ARM::VSELEQS: |
| 7077 | case ARM::VSELGEH: |
| 7078 | case ARM::VSELGES: |
| 7079 | case ARM::VSELGTH: |
| 7080 | case ARM::VSELGTS: |
| 7081 | case ARM::VSELVSH: |
| 7082 | case ARM::VSELVSS: { |
| 7083 | // op: Sd |
| 7084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7085 | Value |= (op & 0x1) << 22; |
| 7086 | Value |= (op & 0x1e) << 11; |
| 7087 | // op: Sn |
| 7088 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7089 | Value |= (op & 0x1e) << 15; |
| 7090 | Value |= (op & 0x1) << 7; |
| 7091 | // op: Sm |
| 7092 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7093 | Value |= (op & 0x1) << 5; |
| 7094 | Value |= (op & 0x1e) >> 1; |
| 7095 | break; |
| 7096 | } |
| 7097 | case ARM::VDUP16d: |
| 7098 | case ARM::VDUP16q: |
| 7099 | case ARM::VDUP32d: |
| 7100 | case ARM::VDUP32q: |
| 7101 | case ARM::VDUP8d: |
| 7102 | case ARM::VDUP8q: { |
| 7103 | // op: V |
| 7104 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7105 | Value |= (op & 0xf) << 16; |
| 7106 | Value |= (op & 0x10) << 3; |
| 7107 | // op: R |
| 7108 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7109 | Value |= (op & 0xf) << 12; |
| 7110 | // op: p |
| 7111 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7112 | Value |= (op & 0xf) << 28; |
| 7113 | Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI); |
| 7114 | break; |
| 7115 | } |
| 7116 | case ARM::VSETLNi32: { |
| 7117 | // op: V |
| 7118 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7119 | Value |= (op & 0xf) << 16; |
| 7120 | Value |= (op & 0x10) << 3; |
| 7121 | // op: R |
| 7122 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7123 | Value |= (op & 0xf) << 12; |
| 7124 | // op: p |
| 7125 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 7126 | Value |= (op & 0xf) << 28; |
| 7127 | // op: lane |
| 7128 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7129 | Value |= (op & 0x1) << 21; |
| 7130 | Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI); |
| 7131 | break; |
| 7132 | } |
| 7133 | case ARM::VSETLNi16: { |
| 7134 | // op: V |
| 7135 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7136 | Value |= (op & 0xf) << 16; |
| 7137 | Value |= (op & 0x10) << 3; |
| 7138 | // op: R |
| 7139 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7140 | Value |= (op & 0xf) << 12; |
| 7141 | // op: p |
| 7142 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 7143 | Value |= (op & 0xf) << 28; |
| 7144 | // op: lane |
| 7145 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7146 | Value |= (op & 0x2) << 20; |
| 7147 | Value |= (op & 0x1) << 6; |
| 7148 | Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI); |
| 7149 | break; |
| 7150 | } |
| 7151 | case ARM::VSETLNi8: { |
| 7152 | // op: V |
| 7153 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7154 | Value |= (op & 0xf) << 16; |
| 7155 | Value |= (op & 0x10) << 3; |
| 7156 | // op: R |
| 7157 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7158 | Value |= (op & 0xf) << 12; |
| 7159 | // op: p |
| 7160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 7161 | Value |= (op & 0xf) << 28; |
| 7162 | // op: lane |
| 7163 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7164 | Value |= (op & 0x4) << 19; |
| 7165 | Value |= (op & 0x3) << 5; |
| 7166 | Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI); |
| 7167 | break; |
| 7168 | } |
| 7169 | case ARM::VGETLNi32: { |
| 7170 | // op: V |
| 7171 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7172 | Value |= (op & 0xf) << 16; |
| 7173 | Value |= (op & 0x10) << 3; |
| 7174 | // op: R |
| 7175 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7176 | Value |= (op & 0xf) << 12; |
| 7177 | // op: p |
| 7178 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7179 | Value |= (op & 0xf) << 28; |
| 7180 | // op: lane |
| 7181 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7182 | Value |= (op & 0x1) << 21; |
| 7183 | Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI); |
| 7184 | break; |
| 7185 | } |
| 7186 | case ARM::VGETLNs16: |
| 7187 | case ARM::VGETLNu16: { |
| 7188 | // op: V |
| 7189 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7190 | Value |= (op & 0xf) << 16; |
| 7191 | Value |= (op & 0x10) << 3; |
| 7192 | // op: R |
| 7193 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7194 | Value |= (op & 0xf) << 12; |
| 7195 | // op: p |
| 7196 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7197 | Value |= (op & 0xf) << 28; |
| 7198 | // op: lane |
| 7199 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7200 | Value |= (op & 0x2) << 20; |
| 7201 | Value |= (op & 0x1) << 6; |
| 7202 | Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI); |
| 7203 | break; |
| 7204 | } |
| 7205 | case ARM::VGETLNs8: |
| 7206 | case ARM::VGETLNu8: { |
| 7207 | // op: V |
| 7208 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7209 | Value |= (op & 0xf) << 16; |
| 7210 | Value |= (op & 0x10) << 3; |
| 7211 | // op: R |
| 7212 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7213 | Value |= (op & 0xf) << 12; |
| 7214 | // op: p |
| 7215 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7216 | Value |= (op & 0xf) << 28; |
| 7217 | // op: lane |
| 7218 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7219 | Value |= (op & 0x4) << 19; |
| 7220 | Value |= (op & 0x3) << 5; |
| 7221 | Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI); |
| 7222 | break; |
| 7223 | } |
| 7224 | case ARM::MVE_VST20_16: |
| 7225 | case ARM::MVE_VST20_32: |
| 7226 | case ARM::MVE_VST20_8: |
| 7227 | case ARM::MVE_VST21_16: |
| 7228 | case ARM::MVE_VST21_32: |
| 7229 | case ARM::MVE_VST21_8: |
| 7230 | case ARM::MVE_VST40_16: |
| 7231 | case ARM::MVE_VST40_32: |
| 7232 | case ARM::MVE_VST40_8: |
| 7233 | case ARM::MVE_VST41_16: |
| 7234 | case ARM::MVE_VST41_32: |
| 7235 | case ARM::MVE_VST41_8: |
| 7236 | case ARM::MVE_VST42_16: |
| 7237 | case ARM::MVE_VST42_32: |
| 7238 | case ARM::MVE_VST42_8: |
| 7239 | case ARM::MVE_VST43_16: |
| 7240 | case ARM::MVE_VST43_32: |
| 7241 | case ARM::MVE_VST43_8: { |
| 7242 | // op: VQd |
| 7243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7244 | Value |= (op & 0x7) << 13; |
| 7245 | // op: Rn |
| 7246 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7247 | Value |= (op & 0xf) << 16; |
| 7248 | break; |
| 7249 | } |
| 7250 | case ARM::MVE_VLD20_16: |
| 7251 | case ARM::MVE_VLD20_32: |
| 7252 | case ARM::MVE_VLD20_8: |
| 7253 | case ARM::MVE_VLD21_16: |
| 7254 | case ARM::MVE_VLD21_32: |
| 7255 | case ARM::MVE_VLD21_8: |
| 7256 | case ARM::MVE_VLD40_16: |
| 7257 | case ARM::MVE_VLD40_32: |
| 7258 | case ARM::MVE_VLD40_8: |
| 7259 | case ARM::MVE_VLD41_16: |
| 7260 | case ARM::MVE_VLD41_32: |
| 7261 | case ARM::MVE_VLD41_8: |
| 7262 | case ARM::MVE_VLD42_16: |
| 7263 | case ARM::MVE_VLD42_32: |
| 7264 | case ARM::MVE_VLD42_8: |
| 7265 | case ARM::MVE_VLD43_16: |
| 7266 | case ARM::MVE_VLD43_32: |
| 7267 | case ARM::MVE_VLD43_8: { |
| 7268 | // op: VQd |
| 7269 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7270 | Value |= (op & 0x7) << 13; |
| 7271 | // op: Rn |
| 7272 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7273 | Value |= (op & 0xf) << 16; |
| 7274 | break; |
| 7275 | } |
| 7276 | case ARM::MVE_VLD20_16_wb: |
| 7277 | case ARM::MVE_VLD20_32_wb: |
| 7278 | case ARM::MVE_VLD20_8_wb: |
| 7279 | case ARM::MVE_VLD21_16_wb: |
| 7280 | case ARM::MVE_VLD21_32_wb: |
| 7281 | case ARM::MVE_VLD21_8_wb: |
| 7282 | case ARM::MVE_VLD40_16_wb: |
| 7283 | case ARM::MVE_VLD40_32_wb: |
| 7284 | case ARM::MVE_VLD40_8_wb: |
| 7285 | case ARM::MVE_VLD41_16_wb: |
| 7286 | case ARM::MVE_VLD41_32_wb: |
| 7287 | case ARM::MVE_VLD41_8_wb: |
| 7288 | case ARM::MVE_VLD42_16_wb: |
| 7289 | case ARM::MVE_VLD42_32_wb: |
| 7290 | case ARM::MVE_VLD42_8_wb: |
| 7291 | case ARM::MVE_VLD43_16_wb: |
| 7292 | case ARM::MVE_VLD43_32_wb: |
| 7293 | case ARM::MVE_VLD43_8_wb: { |
| 7294 | // op: VQd |
| 7295 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7296 | Value |= (op & 0x7) << 13; |
| 7297 | // op: Rn |
| 7298 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7299 | Value |= (op & 0xf) << 16; |
| 7300 | break; |
| 7301 | } |
| 7302 | case ARM::MVE_VST20_16_wb: |
| 7303 | case ARM::MVE_VST20_32_wb: |
| 7304 | case ARM::MVE_VST20_8_wb: |
| 7305 | case ARM::MVE_VST21_16_wb: |
| 7306 | case ARM::MVE_VST21_32_wb: |
| 7307 | case ARM::MVE_VST21_8_wb: |
| 7308 | case ARM::MVE_VST40_16_wb: |
| 7309 | case ARM::MVE_VST40_32_wb: |
| 7310 | case ARM::MVE_VST40_8_wb: |
| 7311 | case ARM::MVE_VST41_16_wb: |
| 7312 | case ARM::MVE_VST41_32_wb: |
| 7313 | case ARM::MVE_VST41_8_wb: |
| 7314 | case ARM::MVE_VST42_16_wb: |
| 7315 | case ARM::MVE_VST42_32_wb: |
| 7316 | case ARM::MVE_VST42_8_wb: |
| 7317 | case ARM::MVE_VST43_16_wb: |
| 7318 | case ARM::MVE_VST43_32_wb: |
| 7319 | case ARM::MVE_VST43_8_wb: { |
| 7320 | // op: VQd |
| 7321 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7322 | Value |= (op & 0x7) << 13; |
| 7323 | // op: Rn |
| 7324 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7325 | Value |= (op & 0xf) << 16; |
| 7326 | break; |
| 7327 | } |
| 7328 | case ARM::VLD1LNd8: { |
| 7329 | // op: Vd |
| 7330 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7331 | Value |= (op & 0x10) << 18; |
| 7332 | Value |= (op & 0xf) << 12; |
| 7333 | // op: Rn |
| 7334 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 7335 | Value |= (op & 0xf) << 16; |
| 7336 | // op: lane |
| 7337 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 7338 | Value |= (op & 0x7) << 5; |
| 7339 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7340 | break; |
| 7341 | } |
| 7342 | case ARM::VLD1d16: |
| 7343 | case ARM::VLD1d16T: |
| 7344 | case ARM::VLD1d32: |
| 7345 | case ARM::VLD1d32T: |
| 7346 | case ARM::VLD1d64: |
| 7347 | case ARM::VLD1d64T: |
| 7348 | case ARM::VLD1d8: |
| 7349 | case ARM::VLD1d8T: { |
| 7350 | // op: Vd |
| 7351 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7352 | Value |= (op & 0x10) << 18; |
| 7353 | Value |= (op & 0xf) << 12; |
| 7354 | // op: Rn |
| 7355 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 7356 | Value |= (op & 0xf) << 16; |
| 7357 | Value |= (op & 0x10); |
| 7358 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7359 | break; |
| 7360 | } |
| 7361 | case ARM::VLD1LNd16: { |
| 7362 | // op: Vd |
| 7363 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7364 | Value |= (op & 0x10) << 18; |
| 7365 | Value |= (op & 0xf) << 12; |
| 7366 | // op: Rn |
| 7367 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 7368 | Value |= (op & 0xf) << 16; |
| 7369 | Value |= (op & 0x30); |
| 7370 | // op: lane |
| 7371 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 7372 | Value |= (op & 0x3) << 6; |
| 7373 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7374 | break; |
| 7375 | } |
| 7376 | case ARM::VLD1d16Q: |
| 7377 | case ARM::VLD1d32Q: |
| 7378 | case ARM::VLD1d64Q: |
| 7379 | case ARM::VLD1d8Q: |
| 7380 | case ARM::VLD1q16: |
| 7381 | case ARM::VLD1q32: |
| 7382 | case ARM::VLD1q64: |
| 7383 | case ARM::VLD1q8: |
| 7384 | case ARM::VLD2b16: |
| 7385 | case ARM::VLD2b32: |
| 7386 | case ARM::VLD2b8: |
| 7387 | case ARM::VLD2d16: |
| 7388 | case ARM::VLD2d32: |
| 7389 | case ARM::VLD2d8: |
| 7390 | case ARM::VLD2q16: |
| 7391 | case ARM::VLD2q32: |
| 7392 | case ARM::VLD2q8: { |
| 7393 | // op: Vd |
| 7394 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7395 | Value |= (op & 0x10) << 18; |
| 7396 | Value |= (op & 0xf) << 12; |
| 7397 | // op: Rn |
| 7398 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 7399 | Value |= (op & 0xf) << 16; |
| 7400 | Value |= (op & 0x30); |
| 7401 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7402 | break; |
| 7403 | } |
| 7404 | case ARM::VLD1LNd8_UPD: { |
| 7405 | // op: Vd |
| 7406 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7407 | Value |= (op & 0x10) << 18; |
| 7408 | Value |= (op & 0xf) << 12; |
| 7409 | // op: Rn |
| 7410 | op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI); |
| 7411 | Value |= (op & 0xf) << 16; |
| 7412 | // op: Rm |
| 7413 | op = getAddrMode6OffsetOpValue(MI, Op: 4, Fixups, STI); |
| 7414 | Value |= (op & 0xf); |
| 7415 | // op: lane |
| 7416 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 7417 | Value |= (op & 0x7) << 5; |
| 7418 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7419 | break; |
| 7420 | } |
| 7421 | case ARM::VLD1LNd32_UPD: { |
| 7422 | // op: Vd |
| 7423 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7424 | Value |= (op & 0x10) << 18; |
| 7425 | Value |= (op & 0xf) << 12; |
| 7426 | // op: Rn |
| 7427 | op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI); |
| 7428 | Value |= (op & 0xf) << 16; |
| 7429 | Value |= (op & 0x10) << 1; |
| 7430 | Value |= (op & 0x10); |
| 7431 | // op: Rm |
| 7432 | op = getAddrMode6OffsetOpValue(MI, Op: 4, Fixups, STI); |
| 7433 | Value |= (op & 0xf); |
| 7434 | // op: lane |
| 7435 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 7436 | Value |= (op & 0x1) << 7; |
| 7437 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7438 | break; |
| 7439 | } |
| 7440 | case ARM::VLD1LNd16_UPD: { |
| 7441 | // op: Vd |
| 7442 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7443 | Value |= (op & 0x10) << 18; |
| 7444 | Value |= (op & 0xf) << 12; |
| 7445 | // op: Rn |
| 7446 | op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI); |
| 7447 | Value |= (op & 0xf) << 16; |
| 7448 | Value |= (op & 0x10); |
| 7449 | // op: Rm |
| 7450 | op = getAddrMode6OffsetOpValue(MI, Op: 4, Fixups, STI); |
| 7451 | Value |= (op & 0xf); |
| 7452 | // op: lane |
| 7453 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 7454 | Value |= (op & 0x3) << 6; |
| 7455 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7456 | break; |
| 7457 | } |
| 7458 | case ARM::VLD1d16Twb_register: |
| 7459 | case ARM::VLD1d16wb_register: |
| 7460 | case ARM::VLD1d32Twb_register: |
| 7461 | case ARM::VLD1d32wb_register: |
| 7462 | case ARM::VLD1d64Twb_register: |
| 7463 | case ARM::VLD1d64wb_register: |
| 7464 | case ARM::VLD1d8Twb_register: |
| 7465 | case ARM::VLD1d8wb_register: { |
| 7466 | // op: Vd |
| 7467 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7468 | Value |= (op & 0x10) << 18; |
| 7469 | Value |= (op & 0xf) << 12; |
| 7470 | // op: Rn |
| 7471 | op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI); |
| 7472 | Value |= (op & 0xf) << 16; |
| 7473 | Value |= (op & 0x10); |
| 7474 | // op: Rm |
| 7475 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 7476 | Value |= (op & 0xf); |
| 7477 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7478 | break; |
| 7479 | } |
| 7480 | case ARM::VLD2LNd32: |
| 7481 | case ARM::VLD2LNq32: { |
| 7482 | // op: Vd |
| 7483 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7484 | Value |= (op & 0x10) << 18; |
| 7485 | Value |= (op & 0xf) << 12; |
| 7486 | // op: Rn |
| 7487 | op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI); |
| 7488 | Value |= (op & 0xf) << 16; |
| 7489 | Value |= (op & 0x10); |
| 7490 | // op: lane |
| 7491 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 7492 | Value |= (op & 0x1) << 7; |
| 7493 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7494 | break; |
| 7495 | } |
| 7496 | case ARM::VLD2LNd16: |
| 7497 | case ARM::VLD2LNq16: { |
| 7498 | // op: Vd |
| 7499 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7500 | Value |= (op & 0x10) << 18; |
| 7501 | Value |= (op & 0xf) << 12; |
| 7502 | // op: Rn |
| 7503 | op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI); |
| 7504 | Value |= (op & 0xf) << 16; |
| 7505 | Value |= (op & 0x10); |
| 7506 | // op: lane |
| 7507 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 7508 | Value |= (op & 0x3) << 6; |
| 7509 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7510 | break; |
| 7511 | } |
| 7512 | case ARM::VLD2LNd8: { |
| 7513 | // op: Vd |
| 7514 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7515 | Value |= (op & 0x10) << 18; |
| 7516 | Value |= (op & 0xf) << 12; |
| 7517 | // op: Rn |
| 7518 | op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI); |
| 7519 | Value |= (op & 0xf) << 16; |
| 7520 | Value |= (op & 0x10); |
| 7521 | // op: lane |
| 7522 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 7523 | Value |= (op & 0x7) << 5; |
| 7524 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7525 | break; |
| 7526 | } |
| 7527 | case ARM::VLD1d16Twb_fixed: |
| 7528 | case ARM::VLD1d16wb_fixed: |
| 7529 | case ARM::VLD1d32Twb_fixed: |
| 7530 | case ARM::VLD1d32wb_fixed: |
| 7531 | case ARM::VLD1d64Twb_fixed: |
| 7532 | case ARM::VLD1d64wb_fixed: |
| 7533 | case ARM::VLD1d8Twb_fixed: |
| 7534 | case ARM::VLD1d8wb_fixed: { |
| 7535 | // op: Vd |
| 7536 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7537 | Value |= (op & 0x10) << 18; |
| 7538 | Value |= (op & 0xf) << 12; |
| 7539 | // op: Rn |
| 7540 | op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI); |
| 7541 | Value |= (op & 0xf) << 16; |
| 7542 | Value |= (op & 0x10); |
| 7543 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7544 | break; |
| 7545 | } |
| 7546 | case ARM::VLD1d16Qwb_register: |
| 7547 | case ARM::VLD1d32Qwb_register: |
| 7548 | case ARM::VLD1d64Qwb_register: |
| 7549 | case ARM::VLD1d8Qwb_register: |
| 7550 | case ARM::VLD1q16wb_register: |
| 7551 | case ARM::VLD1q32wb_register: |
| 7552 | case ARM::VLD1q64wb_register: |
| 7553 | case ARM::VLD1q8wb_register: |
| 7554 | case ARM::VLD2b16wb_register: |
| 7555 | case ARM::VLD2b32wb_register: |
| 7556 | case ARM::VLD2b8wb_register: |
| 7557 | case ARM::VLD2d16wb_register: |
| 7558 | case ARM::VLD2d32wb_register: |
| 7559 | case ARM::VLD2d8wb_register: |
| 7560 | case ARM::VLD2q16wb_register: |
| 7561 | case ARM::VLD2q32wb_register: |
| 7562 | case ARM::VLD2q8wb_register: { |
| 7563 | // op: Vd |
| 7564 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7565 | Value |= (op & 0x10) << 18; |
| 7566 | Value |= (op & 0xf) << 12; |
| 7567 | // op: Rn |
| 7568 | op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI); |
| 7569 | Value |= (op & 0xf) << 16; |
| 7570 | Value |= (op & 0x30); |
| 7571 | // op: Rm |
| 7572 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 7573 | Value |= (op & 0xf); |
| 7574 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7575 | break; |
| 7576 | } |
| 7577 | case ARM::VLD1d16Qwb_fixed: |
| 7578 | case ARM::VLD1d32Qwb_fixed: |
| 7579 | case ARM::VLD1d64Qwb_fixed: |
| 7580 | case ARM::VLD1d8Qwb_fixed: |
| 7581 | case ARM::VLD1q16wb_fixed: |
| 7582 | case ARM::VLD1q32wb_fixed: |
| 7583 | case ARM::VLD1q64wb_fixed: |
| 7584 | case ARM::VLD1q8wb_fixed: |
| 7585 | case ARM::VLD2b16wb_fixed: |
| 7586 | case ARM::VLD2b32wb_fixed: |
| 7587 | case ARM::VLD2b8wb_fixed: |
| 7588 | case ARM::VLD2d16wb_fixed: |
| 7589 | case ARM::VLD2d32wb_fixed: |
| 7590 | case ARM::VLD2d8wb_fixed: |
| 7591 | case ARM::VLD2q16wb_fixed: |
| 7592 | case ARM::VLD2q32wb_fixed: |
| 7593 | case ARM::VLD2q8wb_fixed: { |
| 7594 | // op: Vd |
| 7595 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7596 | Value |= (op & 0x10) << 18; |
| 7597 | Value |= (op & 0xf) << 12; |
| 7598 | // op: Rn |
| 7599 | op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI); |
| 7600 | Value |= (op & 0xf) << 16; |
| 7601 | Value |= (op & 0x30); |
| 7602 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7603 | break; |
| 7604 | } |
| 7605 | case ARM::VLD3LNd32: |
| 7606 | case ARM::VLD3LNq32: { |
| 7607 | // op: Vd |
| 7608 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7609 | Value |= (op & 0x10) << 18; |
| 7610 | Value |= (op & 0xf) << 12; |
| 7611 | // op: Rn |
| 7612 | op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI); |
| 7613 | Value |= (op & 0xf) << 16; |
| 7614 | // op: lane |
| 7615 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI); |
| 7616 | Value |= (op & 0x1) << 7; |
| 7617 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7618 | break; |
| 7619 | } |
| 7620 | case ARM::VLD3LNd16: |
| 7621 | case ARM::VLD3LNq16: { |
| 7622 | // op: Vd |
| 7623 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7624 | Value |= (op & 0x10) << 18; |
| 7625 | Value |= (op & 0xf) << 12; |
| 7626 | // op: Rn |
| 7627 | op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI); |
| 7628 | Value |= (op & 0xf) << 16; |
| 7629 | // op: lane |
| 7630 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI); |
| 7631 | Value |= (op & 0x3) << 6; |
| 7632 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7633 | break; |
| 7634 | } |
| 7635 | case ARM::VLD3LNd8: { |
| 7636 | // op: Vd |
| 7637 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7638 | Value |= (op & 0x10) << 18; |
| 7639 | Value |= (op & 0xf) << 12; |
| 7640 | // op: Rn |
| 7641 | op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI); |
| 7642 | Value |= (op & 0xf) << 16; |
| 7643 | // op: lane |
| 7644 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI); |
| 7645 | Value |= (op & 0x7) << 5; |
| 7646 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7647 | break; |
| 7648 | } |
| 7649 | case ARM::VLD2LNd32_UPD: |
| 7650 | case ARM::VLD2LNq32_UPD: { |
| 7651 | // op: Vd |
| 7652 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7653 | Value |= (op & 0x10) << 18; |
| 7654 | Value |= (op & 0xf) << 12; |
| 7655 | // op: Rn |
| 7656 | op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI); |
| 7657 | Value |= (op & 0xf) << 16; |
| 7658 | Value |= (op & 0x10); |
| 7659 | // op: Rm |
| 7660 | op = getAddrMode6OffsetOpValue(MI, Op: 5, Fixups, STI); |
| 7661 | Value |= (op & 0xf); |
| 7662 | // op: lane |
| 7663 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI); |
| 7664 | Value |= (op & 0x1) << 7; |
| 7665 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7666 | break; |
| 7667 | } |
| 7668 | case ARM::VLD2LNd16_UPD: |
| 7669 | case ARM::VLD2LNq16_UPD: { |
| 7670 | // op: Vd |
| 7671 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7672 | Value |= (op & 0x10) << 18; |
| 7673 | Value |= (op & 0xf) << 12; |
| 7674 | // op: Rn |
| 7675 | op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI); |
| 7676 | Value |= (op & 0xf) << 16; |
| 7677 | Value |= (op & 0x10); |
| 7678 | // op: Rm |
| 7679 | op = getAddrMode6OffsetOpValue(MI, Op: 5, Fixups, STI); |
| 7680 | Value |= (op & 0xf); |
| 7681 | // op: lane |
| 7682 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI); |
| 7683 | Value |= (op & 0x3) << 6; |
| 7684 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7685 | break; |
| 7686 | } |
| 7687 | case ARM::VLD2LNd8_UPD: { |
| 7688 | // op: Vd |
| 7689 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7690 | Value |= (op & 0x10) << 18; |
| 7691 | Value |= (op & 0xf) << 12; |
| 7692 | // op: Rn |
| 7693 | op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI); |
| 7694 | Value |= (op & 0xf) << 16; |
| 7695 | Value |= (op & 0x10); |
| 7696 | // op: Rm |
| 7697 | op = getAddrMode6OffsetOpValue(MI, Op: 5, Fixups, STI); |
| 7698 | Value |= (op & 0xf); |
| 7699 | // op: lane |
| 7700 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI); |
| 7701 | Value |= (op & 0x7) << 5; |
| 7702 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7703 | break; |
| 7704 | } |
| 7705 | case ARM::VLD3d16: |
| 7706 | case ARM::VLD3d32: |
| 7707 | case ARM::VLD3d8: |
| 7708 | case ARM::VLD3q16: |
| 7709 | case ARM::VLD3q32: |
| 7710 | case ARM::VLD3q8: { |
| 7711 | // op: Vd |
| 7712 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7713 | Value |= (op & 0x10) << 18; |
| 7714 | Value |= (op & 0xf) << 12; |
| 7715 | // op: Rn |
| 7716 | op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI); |
| 7717 | Value |= (op & 0xf) << 16; |
| 7718 | Value |= (op & 0x10); |
| 7719 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7720 | break; |
| 7721 | } |
| 7722 | case ARM::VLD3LNd32_UPD: |
| 7723 | case ARM::VLD3LNq32_UPD: { |
| 7724 | // op: Vd |
| 7725 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7726 | Value |= (op & 0x10) << 18; |
| 7727 | Value |= (op & 0xf) << 12; |
| 7728 | // op: Rn |
| 7729 | op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI); |
| 7730 | Value |= (op & 0xf) << 16; |
| 7731 | // op: Rm |
| 7732 | op = getAddrMode6OffsetOpValue(MI, Op: 6, Fixups, STI); |
| 7733 | Value |= (op & 0xf); |
| 7734 | // op: lane |
| 7735 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 10), Fixups, STI); |
| 7736 | Value |= (op & 0x1) << 7; |
| 7737 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7738 | break; |
| 7739 | } |
| 7740 | case ARM::VLD3LNd16_UPD: |
| 7741 | case ARM::VLD3LNq16_UPD: { |
| 7742 | // op: Vd |
| 7743 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7744 | Value |= (op & 0x10) << 18; |
| 7745 | Value |= (op & 0xf) << 12; |
| 7746 | // op: Rn |
| 7747 | op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI); |
| 7748 | Value |= (op & 0xf) << 16; |
| 7749 | // op: Rm |
| 7750 | op = getAddrMode6OffsetOpValue(MI, Op: 6, Fixups, STI); |
| 7751 | Value |= (op & 0xf); |
| 7752 | // op: lane |
| 7753 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 10), Fixups, STI); |
| 7754 | Value |= (op & 0x3) << 6; |
| 7755 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7756 | break; |
| 7757 | } |
| 7758 | case ARM::VLD3LNd8_UPD: { |
| 7759 | // op: Vd |
| 7760 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7761 | Value |= (op & 0x10) << 18; |
| 7762 | Value |= (op & 0xf) << 12; |
| 7763 | // op: Rn |
| 7764 | op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI); |
| 7765 | Value |= (op & 0xf) << 16; |
| 7766 | // op: Rm |
| 7767 | op = getAddrMode6OffsetOpValue(MI, Op: 6, Fixups, STI); |
| 7768 | Value |= (op & 0xf); |
| 7769 | // op: lane |
| 7770 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 10), Fixups, STI); |
| 7771 | Value |= (op & 0x7) << 5; |
| 7772 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7773 | break; |
| 7774 | } |
| 7775 | case ARM::VLD3d16_UPD: |
| 7776 | case ARM::VLD3d32_UPD: |
| 7777 | case ARM::VLD3d8_UPD: |
| 7778 | case ARM::VLD3q16_UPD: |
| 7779 | case ARM::VLD3q32_UPD: |
| 7780 | case ARM::VLD3q8_UPD: { |
| 7781 | // op: Vd |
| 7782 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7783 | Value |= (op & 0x10) << 18; |
| 7784 | Value |= (op & 0xf) << 12; |
| 7785 | // op: Rn |
| 7786 | op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI); |
| 7787 | Value |= (op & 0xf) << 16; |
| 7788 | Value |= (op & 0x10); |
| 7789 | // op: Rm |
| 7790 | op = getAddrMode6OffsetOpValue(MI, Op: 6, Fixups, STI); |
| 7791 | Value |= (op & 0xf); |
| 7792 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7793 | break; |
| 7794 | } |
| 7795 | case ARM::VLD4LNd16: |
| 7796 | case ARM::VLD4LNq16: { |
| 7797 | // op: Vd |
| 7798 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7799 | Value |= (op & 0x10) << 18; |
| 7800 | Value |= (op & 0xf) << 12; |
| 7801 | // op: Rn |
| 7802 | op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI); |
| 7803 | Value |= (op & 0xf) << 16; |
| 7804 | Value |= (op & 0x10); |
| 7805 | // op: lane |
| 7806 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 10), Fixups, STI); |
| 7807 | Value |= (op & 0x3) << 6; |
| 7808 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7809 | break; |
| 7810 | } |
| 7811 | case ARM::VLD4LNd8: { |
| 7812 | // op: Vd |
| 7813 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7814 | Value |= (op & 0x10) << 18; |
| 7815 | Value |= (op & 0xf) << 12; |
| 7816 | // op: Rn |
| 7817 | op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI); |
| 7818 | Value |= (op & 0xf) << 16; |
| 7819 | Value |= (op & 0x10); |
| 7820 | // op: lane |
| 7821 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 10), Fixups, STI); |
| 7822 | Value |= (op & 0x7) << 5; |
| 7823 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7824 | break; |
| 7825 | } |
| 7826 | case ARM::VLD4LNd32: |
| 7827 | case ARM::VLD4LNq32: { |
| 7828 | // op: Vd |
| 7829 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7830 | Value |= (op & 0x10) << 18; |
| 7831 | Value |= (op & 0xf) << 12; |
| 7832 | // op: Rn |
| 7833 | op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI); |
| 7834 | Value |= (op & 0xf) << 16; |
| 7835 | Value |= (op & 0x30); |
| 7836 | // op: lane |
| 7837 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 10), Fixups, STI); |
| 7838 | Value |= (op & 0x1) << 7; |
| 7839 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7840 | break; |
| 7841 | } |
| 7842 | case ARM::VLD4d16: |
| 7843 | case ARM::VLD4d32: |
| 7844 | case ARM::VLD4d8: |
| 7845 | case ARM::VLD4q16: |
| 7846 | case ARM::VLD4q32: |
| 7847 | case ARM::VLD4q8: { |
| 7848 | // op: Vd |
| 7849 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7850 | Value |= (op & 0x10) << 18; |
| 7851 | Value |= (op & 0xf) << 12; |
| 7852 | // op: Rn |
| 7853 | op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI); |
| 7854 | Value |= (op & 0xf) << 16; |
| 7855 | Value |= (op & 0x30); |
| 7856 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7857 | break; |
| 7858 | } |
| 7859 | case ARM::VLD4LNd16_UPD: |
| 7860 | case ARM::VLD4LNq16_UPD: { |
| 7861 | // op: Vd |
| 7862 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7863 | Value |= (op & 0x10) << 18; |
| 7864 | Value |= (op & 0xf) << 12; |
| 7865 | // op: Rn |
| 7866 | op = getAddrMode6AddressOpValue(MI, Op: 5, Fixups, STI); |
| 7867 | Value |= (op & 0xf) << 16; |
| 7868 | Value |= (op & 0x10); |
| 7869 | // op: Rm |
| 7870 | op = getAddrMode6OffsetOpValue(MI, Op: 7, Fixups, STI); |
| 7871 | Value |= (op & 0xf); |
| 7872 | // op: lane |
| 7873 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 12), Fixups, STI); |
| 7874 | Value |= (op & 0x3) << 6; |
| 7875 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7876 | break; |
| 7877 | } |
| 7878 | case ARM::VLD4LNd8_UPD: { |
| 7879 | // op: Vd |
| 7880 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7881 | Value |= (op & 0x10) << 18; |
| 7882 | Value |= (op & 0xf) << 12; |
| 7883 | // op: Rn |
| 7884 | op = getAddrMode6AddressOpValue(MI, Op: 5, Fixups, STI); |
| 7885 | Value |= (op & 0xf) << 16; |
| 7886 | Value |= (op & 0x10); |
| 7887 | // op: Rm |
| 7888 | op = getAddrMode6OffsetOpValue(MI, Op: 7, Fixups, STI); |
| 7889 | Value |= (op & 0xf); |
| 7890 | // op: lane |
| 7891 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 12), Fixups, STI); |
| 7892 | Value |= (op & 0x7) << 5; |
| 7893 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7894 | break; |
| 7895 | } |
| 7896 | case ARM::VLD4LNd32_UPD: |
| 7897 | case ARM::VLD4LNq32_UPD: { |
| 7898 | // op: Vd |
| 7899 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7900 | Value |= (op & 0x10) << 18; |
| 7901 | Value |= (op & 0xf) << 12; |
| 7902 | // op: Rn |
| 7903 | op = getAddrMode6AddressOpValue(MI, Op: 5, Fixups, STI); |
| 7904 | Value |= (op & 0xf) << 16; |
| 7905 | Value |= (op & 0x30); |
| 7906 | // op: Rm |
| 7907 | op = getAddrMode6OffsetOpValue(MI, Op: 7, Fixups, STI); |
| 7908 | Value |= (op & 0xf); |
| 7909 | // op: lane |
| 7910 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 12), Fixups, STI); |
| 7911 | Value |= (op & 0x1) << 7; |
| 7912 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7913 | break; |
| 7914 | } |
| 7915 | case ARM::VLD4d16_UPD: |
| 7916 | case ARM::VLD4d32_UPD: |
| 7917 | case ARM::VLD4d8_UPD: |
| 7918 | case ARM::VLD4q16_UPD: |
| 7919 | case ARM::VLD4q32_UPD: |
| 7920 | case ARM::VLD4q8_UPD: { |
| 7921 | // op: Vd |
| 7922 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7923 | Value |= (op & 0x10) << 18; |
| 7924 | Value |= (op & 0xf) << 12; |
| 7925 | // op: Rn |
| 7926 | op = getAddrMode6AddressOpValue(MI, Op: 5, Fixups, STI); |
| 7927 | Value |= (op & 0xf) << 16; |
| 7928 | Value |= (op & 0x30); |
| 7929 | // op: Rm |
| 7930 | op = getAddrMode6OffsetOpValue(MI, Op: 7, Fixups, STI); |
| 7931 | Value |= (op & 0xf); |
| 7932 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7933 | break; |
| 7934 | } |
| 7935 | case ARM::VLD1DUPd16: |
| 7936 | case ARM::VLD1DUPd32: |
| 7937 | case ARM::VLD1DUPd8: |
| 7938 | case ARM::VLD1DUPq16: |
| 7939 | case ARM::VLD1DUPq32: |
| 7940 | case ARM::VLD1DUPq8: |
| 7941 | case ARM::VLD2DUPd16: |
| 7942 | case ARM::VLD2DUPd16x2: |
| 7943 | case ARM::VLD2DUPd32: |
| 7944 | case ARM::VLD2DUPd32x2: |
| 7945 | case ARM::VLD2DUPd8: |
| 7946 | case ARM::VLD2DUPd8x2: { |
| 7947 | // op: Vd |
| 7948 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7949 | Value |= (op & 0x10) << 18; |
| 7950 | Value |= (op & 0xf) << 12; |
| 7951 | // op: Rn |
| 7952 | op = getAddrMode6DupAddressOpValue(MI, Op: 1, Fixups, STI); |
| 7953 | Value |= (op & 0xf) << 16; |
| 7954 | Value |= (op & 0x10); |
| 7955 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7956 | break; |
| 7957 | } |
| 7958 | case ARM::VLD1DUPd16wb_register: |
| 7959 | case ARM::VLD1DUPd32wb_register: |
| 7960 | case ARM::VLD1DUPd8wb_register: |
| 7961 | case ARM::VLD1DUPq16wb_register: |
| 7962 | case ARM::VLD1DUPq32wb_register: |
| 7963 | case ARM::VLD1DUPq8wb_register: |
| 7964 | case ARM::VLD2DUPd16wb_register: |
| 7965 | case ARM::VLD2DUPd16x2wb_register: |
| 7966 | case ARM::VLD2DUPd32wb_register: |
| 7967 | case ARM::VLD2DUPd32x2wb_register: |
| 7968 | case ARM::VLD2DUPd8wb_register: |
| 7969 | case ARM::VLD2DUPd8x2wb_register: { |
| 7970 | // op: Vd |
| 7971 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7972 | Value |= (op & 0x10) << 18; |
| 7973 | Value |= (op & 0xf) << 12; |
| 7974 | // op: Rn |
| 7975 | op = getAddrMode6DupAddressOpValue(MI, Op: 2, Fixups, STI); |
| 7976 | Value |= (op & 0xf) << 16; |
| 7977 | Value |= (op & 0x10); |
| 7978 | // op: Rm |
| 7979 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 7980 | Value |= (op & 0xf); |
| 7981 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 7982 | break; |
| 7983 | } |
| 7984 | case ARM::VLD1DUPd16wb_fixed: |
| 7985 | case ARM::VLD1DUPd32wb_fixed: |
| 7986 | case ARM::VLD1DUPd8wb_fixed: |
| 7987 | case ARM::VLD1DUPq16wb_fixed: |
| 7988 | case ARM::VLD1DUPq32wb_fixed: |
| 7989 | case ARM::VLD1DUPq8wb_fixed: |
| 7990 | case ARM::VLD2DUPd16wb_fixed: |
| 7991 | case ARM::VLD2DUPd16x2wb_fixed: |
| 7992 | case ARM::VLD2DUPd32wb_fixed: |
| 7993 | case ARM::VLD2DUPd32x2wb_fixed: |
| 7994 | case ARM::VLD2DUPd8wb_fixed: |
| 7995 | case ARM::VLD2DUPd8x2wb_fixed: { |
| 7996 | // op: Vd |
| 7997 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7998 | Value |= (op & 0x10) << 18; |
| 7999 | Value |= (op & 0xf) << 12; |
| 8000 | // op: Rn |
| 8001 | op = getAddrMode6DupAddressOpValue(MI, Op: 2, Fixups, STI); |
| 8002 | Value |= (op & 0xf) << 16; |
| 8003 | Value |= (op & 0x10); |
| 8004 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 8005 | break; |
| 8006 | } |
| 8007 | case ARM::VLD3DUPd16: |
| 8008 | case ARM::VLD3DUPd32: |
| 8009 | case ARM::VLD3DUPd8: |
| 8010 | case ARM::VLD3DUPq16: |
| 8011 | case ARM::VLD3DUPq32: |
| 8012 | case ARM::VLD3DUPq8: { |
| 8013 | // op: Vd |
| 8014 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8015 | Value |= (op & 0x10) << 18; |
| 8016 | Value |= (op & 0xf) << 12; |
| 8017 | // op: Rn |
| 8018 | op = getAddrMode6DupAddressOpValue(MI, Op: 3, Fixups, STI); |
| 8019 | Value |= (op & 0xf) << 16; |
| 8020 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 8021 | break; |
| 8022 | } |
| 8023 | case ARM::VLD3DUPd16_UPD: |
| 8024 | case ARM::VLD3DUPd32_UPD: |
| 8025 | case ARM::VLD3DUPd8_UPD: |
| 8026 | case ARM::VLD3DUPq16_UPD: |
| 8027 | case ARM::VLD3DUPq32_UPD: |
| 8028 | case ARM::VLD3DUPq8_UPD: { |
| 8029 | // op: Vd |
| 8030 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8031 | Value |= (op & 0x10) << 18; |
| 8032 | Value |= (op & 0xf) << 12; |
| 8033 | // op: Rn |
| 8034 | op = getAddrMode6DupAddressOpValue(MI, Op: 4, Fixups, STI); |
| 8035 | Value |= (op & 0xf) << 16; |
| 8036 | // op: Rm |
| 8037 | op = getAddrMode6OffsetOpValue(MI, Op: 6, Fixups, STI); |
| 8038 | Value |= (op & 0xf); |
| 8039 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 8040 | break; |
| 8041 | } |
| 8042 | case ARM::VLD4DUPd16: |
| 8043 | case ARM::VLD4DUPd8: |
| 8044 | case ARM::VLD4DUPq16: |
| 8045 | case ARM::VLD4DUPq8: { |
| 8046 | // op: Vd |
| 8047 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8048 | Value |= (op & 0x10) << 18; |
| 8049 | Value |= (op & 0xf) << 12; |
| 8050 | // op: Rn |
| 8051 | op = getAddrMode6DupAddressOpValue(MI, Op: 4, Fixups, STI); |
| 8052 | Value |= (op & 0xf) << 16; |
| 8053 | Value |= (op & 0x10); |
| 8054 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 8055 | break; |
| 8056 | } |
| 8057 | case ARM::VLD4DUPd32: |
| 8058 | case ARM::VLD4DUPq32: { |
| 8059 | // op: Vd |
| 8060 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8061 | Value |= (op & 0x10) << 18; |
| 8062 | Value |= (op & 0xf) << 12; |
| 8063 | // op: Rn |
| 8064 | op = getAddrMode6DupAddressOpValue(MI, Op: 4, Fixups, STI); |
| 8065 | Value |= (op & 0xf) << 16; |
| 8066 | Value |= (op & 0x20) << 1; |
| 8067 | Value |= (op & 0x10); |
| 8068 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 8069 | break; |
| 8070 | } |
| 8071 | case ARM::VLD4DUPd16_UPD: |
| 8072 | case ARM::VLD4DUPd8_UPD: |
| 8073 | case ARM::VLD4DUPq16_UPD: |
| 8074 | case ARM::VLD4DUPq8_UPD: { |
| 8075 | // op: Vd |
| 8076 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8077 | Value |= (op & 0x10) << 18; |
| 8078 | Value |= (op & 0xf) << 12; |
| 8079 | // op: Rn |
| 8080 | op = getAddrMode6DupAddressOpValue(MI, Op: 5, Fixups, STI); |
| 8081 | Value |= (op & 0xf) << 16; |
| 8082 | Value |= (op & 0x10); |
| 8083 | // op: Rm |
| 8084 | op = getAddrMode6OffsetOpValue(MI, Op: 7, Fixups, STI); |
| 8085 | Value |= (op & 0xf); |
| 8086 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 8087 | break; |
| 8088 | } |
| 8089 | case ARM::VLD4DUPd32_UPD: |
| 8090 | case ARM::VLD4DUPq32_UPD: { |
| 8091 | // op: Vd |
| 8092 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8093 | Value |= (op & 0x10) << 18; |
| 8094 | Value |= (op & 0xf) << 12; |
| 8095 | // op: Rn |
| 8096 | op = getAddrMode6DupAddressOpValue(MI, Op: 5, Fixups, STI); |
| 8097 | Value |= (op & 0xf) << 16; |
| 8098 | Value |= (op & 0x20) << 1; |
| 8099 | Value |= (op & 0x10); |
| 8100 | // op: Rm |
| 8101 | op = getAddrMode6OffsetOpValue(MI, Op: 7, Fixups, STI); |
| 8102 | Value |= (op & 0xf); |
| 8103 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 8104 | break; |
| 8105 | } |
| 8106 | case ARM::VLD1LNd32: { |
| 8107 | // op: Vd |
| 8108 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8109 | Value |= (op & 0x10) << 18; |
| 8110 | Value |= (op & 0xf) << 12; |
| 8111 | // op: Rn |
| 8112 | op = getAddrMode6OneLane32AddressOpValue(MI, Op: 1, Fixups, STI); |
| 8113 | Value |= (op & 0xf) << 16; |
| 8114 | Value |= (op & 0x30); |
| 8115 | // op: lane |
| 8116 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8117 | Value |= (op & 0x1) << 7; |
| 8118 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 8119 | break; |
| 8120 | } |
| 8121 | case ARM::VBICiv4i16: |
| 8122 | case ARM::VBICiv8i16: |
| 8123 | case ARM::VMOVv4i16: |
| 8124 | case ARM::VMOVv8i16: |
| 8125 | case ARM::VMVNv4i16: |
| 8126 | case ARM::VMVNv8i16: |
| 8127 | case ARM::VORRiv4i16: |
| 8128 | case ARM::VORRiv8i16: { |
| 8129 | // op: Vd |
| 8130 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8131 | Value |= (op & 0x10) << 18; |
| 8132 | Value |= (op & 0xf) << 12; |
| 8133 | // op: SIMM |
| 8134 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8135 | Value |= (op & 0x80) << 17; |
| 8136 | Value |= (op & 0x70) << 12; |
| 8137 | Value |= (op & 0x200); |
| 8138 | Value |= (op & 0xf); |
| 8139 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8140 | break; |
| 8141 | } |
| 8142 | case ARM::VBICiv2i32: |
| 8143 | case ARM::VBICiv4i32: |
| 8144 | case ARM::VORRiv2i32: |
| 8145 | case ARM::VORRiv4i32: { |
| 8146 | // op: Vd |
| 8147 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8148 | Value |= (op & 0x10) << 18; |
| 8149 | Value |= (op & 0xf) << 12; |
| 8150 | // op: SIMM |
| 8151 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8152 | Value |= (op & 0x80) << 17; |
| 8153 | Value |= (op & 0x70) << 12; |
| 8154 | Value |= (op & 0x600); |
| 8155 | Value |= (op & 0xf); |
| 8156 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8157 | break; |
| 8158 | } |
| 8159 | case ARM::VMOVv16i8: |
| 8160 | case ARM::VMOVv1i64: |
| 8161 | case ARM::VMOVv2f32: |
| 8162 | case ARM::VMOVv2i64: |
| 8163 | case ARM::VMOVv4f32: |
| 8164 | case ARM::VMOVv8i8: { |
| 8165 | // op: Vd |
| 8166 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8167 | Value |= (op & 0x10) << 18; |
| 8168 | Value |= (op & 0xf) << 12; |
| 8169 | // op: SIMM |
| 8170 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8171 | Value |= (op & 0x80) << 17; |
| 8172 | Value |= (op & 0x70) << 12; |
| 8173 | Value |= (op & 0xf); |
| 8174 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8175 | break; |
| 8176 | } |
| 8177 | case ARM::VMOVv2i32: |
| 8178 | case ARM::VMOVv4i32: |
| 8179 | case ARM::VMVNv2i32: |
| 8180 | case ARM::VMVNv4i32: { |
| 8181 | // op: Vd |
| 8182 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8183 | Value |= (op & 0x10) << 18; |
| 8184 | Value |= (op & 0xf) << 12; |
| 8185 | // op: SIMM |
| 8186 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8187 | Value |= (op & 0x80) << 17; |
| 8188 | Value |= (op & 0x70) << 12; |
| 8189 | Value |= (op & 0xf00); |
| 8190 | Value |= (op & 0xf); |
| 8191 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8192 | break; |
| 8193 | } |
| 8194 | case ARM::VQSHLsiv2i32: |
| 8195 | case ARM::VQSHLsiv4i32: |
| 8196 | case ARM::VQSHLsuv2i32: |
| 8197 | case ARM::VQSHLsuv4i32: |
| 8198 | case ARM::VQSHLuiv2i32: |
| 8199 | case ARM::VQSHLuiv4i32: |
| 8200 | case ARM::VSHLLsv2i64: |
| 8201 | case ARM::VSHLLuv2i64: |
| 8202 | case ARM::VSHLiv2i32: |
| 8203 | case ARM::VSHLiv4i32: { |
| 8204 | // op: Vd |
| 8205 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8206 | Value |= (op & 0x10) << 18; |
| 8207 | Value |= (op & 0xf) << 12; |
| 8208 | // op: Vm |
| 8209 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8210 | Value |= (op & 0x10) << 1; |
| 8211 | Value |= (op & 0xf); |
| 8212 | // op: SIMM |
| 8213 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8214 | Value |= (op & 0x1f) << 16; |
| 8215 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8216 | break; |
| 8217 | } |
| 8218 | case ARM::VQSHLsiv1i64: |
| 8219 | case ARM::VQSHLsiv2i64: |
| 8220 | case ARM::VQSHLsuv1i64: |
| 8221 | case ARM::VQSHLsuv2i64: |
| 8222 | case ARM::VQSHLuiv1i64: |
| 8223 | case ARM::VQSHLuiv2i64: |
| 8224 | case ARM::VSHLiv1i64: |
| 8225 | case ARM::VSHLiv2i64: { |
| 8226 | // op: Vd |
| 8227 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8228 | Value |= (op & 0x10) << 18; |
| 8229 | Value |= (op & 0xf) << 12; |
| 8230 | // op: Vm |
| 8231 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8232 | Value |= (op & 0x10) << 1; |
| 8233 | Value |= (op & 0xf); |
| 8234 | // op: SIMM |
| 8235 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8236 | Value |= (op & 0x3f) << 16; |
| 8237 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8238 | break; |
| 8239 | } |
| 8240 | case ARM::VQSHLsiv16i8: |
| 8241 | case ARM::VQSHLsiv8i8: |
| 8242 | case ARM::VQSHLsuv16i8: |
| 8243 | case ARM::VQSHLsuv8i8: |
| 8244 | case ARM::VQSHLuiv16i8: |
| 8245 | case ARM::VQSHLuiv8i8: |
| 8246 | case ARM::VSHLLsv8i16: |
| 8247 | case ARM::VSHLLuv8i16: |
| 8248 | case ARM::VSHLiv16i8: |
| 8249 | case ARM::VSHLiv8i8: { |
| 8250 | // op: Vd |
| 8251 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8252 | Value |= (op & 0x10) << 18; |
| 8253 | Value |= (op & 0xf) << 12; |
| 8254 | // op: Vm |
| 8255 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8256 | Value |= (op & 0x10) << 1; |
| 8257 | Value |= (op & 0xf); |
| 8258 | // op: SIMM |
| 8259 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8260 | Value |= (op & 0x7) << 16; |
| 8261 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8262 | break; |
| 8263 | } |
| 8264 | case ARM::VQSHLsiv4i16: |
| 8265 | case ARM::VQSHLsiv8i16: |
| 8266 | case ARM::VQSHLsuv4i16: |
| 8267 | case ARM::VQSHLsuv8i16: |
| 8268 | case ARM::VQSHLuiv4i16: |
| 8269 | case ARM::VQSHLuiv8i16: |
| 8270 | case ARM::VSHLLsv4i32: |
| 8271 | case ARM::VSHLLuv4i32: |
| 8272 | case ARM::VSHLiv4i16: |
| 8273 | case ARM::VSHLiv8i16: { |
| 8274 | // op: Vd |
| 8275 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8276 | Value |= (op & 0x10) << 18; |
| 8277 | Value |= (op & 0xf) << 12; |
| 8278 | // op: Vm |
| 8279 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8280 | Value |= (op & 0x10) << 1; |
| 8281 | Value |= (op & 0xf); |
| 8282 | // op: SIMM |
| 8283 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8284 | Value |= (op & 0xf) << 16; |
| 8285 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8286 | break; |
| 8287 | } |
| 8288 | case ARM::VCVTf2xsd: |
| 8289 | case ARM::VCVTf2xsq: |
| 8290 | case ARM::VCVTf2xud: |
| 8291 | case ARM::VCVTf2xuq: |
| 8292 | case ARM::VCVTh2xsd: |
| 8293 | case ARM::VCVTh2xsq: |
| 8294 | case ARM::VCVTh2xud: |
| 8295 | case ARM::VCVTh2xuq: |
| 8296 | case ARM::VCVTxs2fd: |
| 8297 | case ARM::VCVTxs2fq: |
| 8298 | case ARM::VCVTxs2hd: |
| 8299 | case ARM::VCVTxs2hq: |
| 8300 | case ARM::VCVTxu2fd: |
| 8301 | case ARM::VCVTxu2fq: |
| 8302 | case ARM::VCVTxu2hd: |
| 8303 | case ARM::VCVTxu2hq: { |
| 8304 | // op: Vd |
| 8305 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8306 | Value |= (op & 0x10) << 18; |
| 8307 | Value |= (op & 0xf) << 12; |
| 8308 | // op: Vm |
| 8309 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8310 | Value |= (op & 0x10) << 1; |
| 8311 | Value |= (op & 0xf); |
| 8312 | // op: SIMM |
| 8313 | op = getNEONVcvtImm32OpValue(MI, Op: 2, Fixups, STI); |
| 8314 | Value |= (op & 0x3f) << 16; |
| 8315 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8316 | break; |
| 8317 | } |
| 8318 | case ARM::VQRSHRNsv4i16: |
| 8319 | case ARM::VQRSHRNuv4i16: |
| 8320 | case ARM::VQRSHRUNv4i16: |
| 8321 | case ARM::VQSHRNsv4i16: |
| 8322 | case ARM::VQSHRNuv4i16: |
| 8323 | case ARM::VQSHRUNv4i16: |
| 8324 | case ARM::VRSHRNv4i16: |
| 8325 | case ARM::VRSHRsv4i16: |
| 8326 | case ARM::VRSHRsv8i16: |
| 8327 | case ARM::VRSHRuv4i16: |
| 8328 | case ARM::VRSHRuv8i16: |
| 8329 | case ARM::VSHRNv4i16: |
| 8330 | case ARM::VSHRsv4i16: |
| 8331 | case ARM::VSHRsv8i16: |
| 8332 | case ARM::VSHRuv4i16: |
| 8333 | case ARM::VSHRuv8i16: { |
| 8334 | // op: Vd |
| 8335 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8336 | Value |= (op & 0x10) << 18; |
| 8337 | Value |= (op & 0xf) << 12; |
| 8338 | // op: Vm |
| 8339 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8340 | Value |= (op & 0x10) << 1; |
| 8341 | Value |= (op & 0xf); |
| 8342 | // op: SIMM |
| 8343 | op = getShiftRight16Imm(MI, Op: 2, Fixups, STI); |
| 8344 | Value |= (op & 0xf) << 16; |
| 8345 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8346 | break; |
| 8347 | } |
| 8348 | case ARM::VQRSHRNsv2i32: |
| 8349 | case ARM::VQRSHRNuv2i32: |
| 8350 | case ARM::VQRSHRUNv2i32: |
| 8351 | case ARM::VQSHRNsv2i32: |
| 8352 | case ARM::VQSHRNuv2i32: |
| 8353 | case ARM::VQSHRUNv2i32: |
| 8354 | case ARM::VRSHRNv2i32: |
| 8355 | case ARM::VRSHRsv2i32: |
| 8356 | case ARM::VRSHRsv4i32: |
| 8357 | case ARM::VRSHRuv2i32: |
| 8358 | case ARM::VRSHRuv4i32: |
| 8359 | case ARM::VSHRNv2i32: |
| 8360 | case ARM::VSHRsv2i32: |
| 8361 | case ARM::VSHRsv4i32: |
| 8362 | case ARM::VSHRuv2i32: |
| 8363 | case ARM::VSHRuv4i32: { |
| 8364 | // op: Vd |
| 8365 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8366 | Value |= (op & 0x10) << 18; |
| 8367 | Value |= (op & 0xf) << 12; |
| 8368 | // op: Vm |
| 8369 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8370 | Value |= (op & 0x10) << 1; |
| 8371 | Value |= (op & 0xf); |
| 8372 | // op: SIMM |
| 8373 | op = getShiftRight32Imm(MI, Op: 2, Fixups, STI); |
| 8374 | Value |= (op & 0x1f) << 16; |
| 8375 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8376 | break; |
| 8377 | } |
| 8378 | case ARM::VRSHRsv1i64: |
| 8379 | case ARM::VRSHRsv2i64: |
| 8380 | case ARM::VRSHRuv1i64: |
| 8381 | case ARM::VRSHRuv2i64: |
| 8382 | case ARM::VSHRsv1i64: |
| 8383 | case ARM::VSHRsv2i64: |
| 8384 | case ARM::VSHRuv1i64: |
| 8385 | case ARM::VSHRuv2i64: { |
| 8386 | // op: Vd |
| 8387 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8388 | Value |= (op & 0x10) << 18; |
| 8389 | Value |= (op & 0xf) << 12; |
| 8390 | // op: Vm |
| 8391 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8392 | Value |= (op & 0x10) << 1; |
| 8393 | Value |= (op & 0xf); |
| 8394 | // op: SIMM |
| 8395 | op = getShiftRight64Imm(MI, Op: 2, Fixups, STI); |
| 8396 | Value |= (op & 0x3f) << 16; |
| 8397 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8398 | break; |
| 8399 | } |
| 8400 | case ARM::VQRSHRNsv8i8: |
| 8401 | case ARM::VQRSHRNuv8i8: |
| 8402 | case ARM::VQRSHRUNv8i8: |
| 8403 | case ARM::VQSHRNsv8i8: |
| 8404 | case ARM::VQSHRNuv8i8: |
| 8405 | case ARM::VQSHRUNv8i8: |
| 8406 | case ARM::VRSHRNv8i8: |
| 8407 | case ARM::VRSHRsv16i8: |
| 8408 | case ARM::VRSHRsv8i8: |
| 8409 | case ARM::VRSHRuv16i8: |
| 8410 | case ARM::VRSHRuv8i8: |
| 8411 | case ARM::VSHRNv8i8: |
| 8412 | case ARM::VSHRsv16i8: |
| 8413 | case ARM::VSHRsv8i8: |
| 8414 | case ARM::VSHRuv16i8: |
| 8415 | case ARM::VSHRuv8i8: { |
| 8416 | // op: Vd |
| 8417 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8418 | Value |= (op & 0x10) << 18; |
| 8419 | Value |= (op & 0xf) << 12; |
| 8420 | // op: Vm |
| 8421 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8422 | Value |= (op & 0x10) << 1; |
| 8423 | Value |= (op & 0xf); |
| 8424 | // op: SIMM |
| 8425 | op = getShiftRight8Imm(MI, Op: 2, Fixups, STI); |
| 8426 | Value |= (op & 0x7) << 16; |
| 8427 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8428 | break; |
| 8429 | } |
| 8430 | case ARM::VDUPLN32d: |
| 8431 | case ARM::VDUPLN32q: { |
| 8432 | // op: Vd |
| 8433 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8434 | Value |= (op & 0x10) << 18; |
| 8435 | Value |= (op & 0xf) << 12; |
| 8436 | // op: Vm |
| 8437 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8438 | Value |= (op & 0x10) << 1; |
| 8439 | Value |= (op & 0xf); |
| 8440 | // op: lane |
| 8441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8442 | Value |= (op & 0x1) << 19; |
| 8443 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8444 | break; |
| 8445 | } |
| 8446 | case ARM::VDUPLN16d: |
| 8447 | case ARM::VDUPLN16q: { |
| 8448 | // op: Vd |
| 8449 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8450 | Value |= (op & 0x10) << 18; |
| 8451 | Value |= (op & 0xf) << 12; |
| 8452 | // op: Vm |
| 8453 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8454 | Value |= (op & 0x10) << 1; |
| 8455 | Value |= (op & 0xf); |
| 8456 | // op: lane |
| 8457 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8458 | Value |= (op & 0x3) << 18; |
| 8459 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8460 | break; |
| 8461 | } |
| 8462 | case ARM::VDUPLN8d: |
| 8463 | case ARM::VDUPLN8q: { |
| 8464 | // op: Vd |
| 8465 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8466 | Value |= (op & 0x10) << 18; |
| 8467 | Value |= (op & 0xf) << 12; |
| 8468 | // op: Vm |
| 8469 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8470 | Value |= (op & 0x10) << 1; |
| 8471 | Value |= (op & 0xf); |
| 8472 | // op: lane |
| 8473 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8474 | Value |= (op & 0x7) << 17; |
| 8475 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8476 | break; |
| 8477 | } |
| 8478 | case ARM::AESIMC: |
| 8479 | case ARM::AESMC: |
| 8480 | case ARM::BF16_VCVT: |
| 8481 | case ARM::SHA1H: |
| 8482 | case ARM::VABSfd: |
| 8483 | case ARM::VABSfq: |
| 8484 | case ARM::VABShd: |
| 8485 | case ARM::VABShq: |
| 8486 | case ARM::VABSv16i8: |
| 8487 | case ARM::VABSv2i32: |
| 8488 | case ARM::VABSv4i16: |
| 8489 | case ARM::VABSv4i32: |
| 8490 | case ARM::VABSv8i16: |
| 8491 | case ARM::VABSv8i8: |
| 8492 | case ARM::VCEQzv16i8: |
| 8493 | case ARM::VCEQzv2f32: |
| 8494 | case ARM::VCEQzv2i32: |
| 8495 | case ARM::VCEQzv4f16: |
| 8496 | case ARM::VCEQzv4f32: |
| 8497 | case ARM::VCEQzv4i16: |
| 8498 | case ARM::VCEQzv4i32: |
| 8499 | case ARM::VCEQzv8f16: |
| 8500 | case ARM::VCEQzv8i16: |
| 8501 | case ARM::VCEQzv8i8: |
| 8502 | case ARM::VCGEzv16i8: |
| 8503 | case ARM::VCGEzv2f32: |
| 8504 | case ARM::VCGEzv2i32: |
| 8505 | case ARM::VCGEzv4f16: |
| 8506 | case ARM::VCGEzv4f32: |
| 8507 | case ARM::VCGEzv4i16: |
| 8508 | case ARM::VCGEzv4i32: |
| 8509 | case ARM::VCGEzv8f16: |
| 8510 | case ARM::VCGEzv8i16: |
| 8511 | case ARM::VCGEzv8i8: |
| 8512 | case ARM::VCGTzv16i8: |
| 8513 | case ARM::VCGTzv2f32: |
| 8514 | case ARM::VCGTzv2i32: |
| 8515 | case ARM::VCGTzv4f16: |
| 8516 | case ARM::VCGTzv4f32: |
| 8517 | case ARM::VCGTzv4i16: |
| 8518 | case ARM::VCGTzv4i32: |
| 8519 | case ARM::VCGTzv8f16: |
| 8520 | case ARM::VCGTzv8i16: |
| 8521 | case ARM::VCGTzv8i8: |
| 8522 | case ARM::VCLEzv16i8: |
| 8523 | case ARM::VCLEzv2f32: |
| 8524 | case ARM::VCLEzv2i32: |
| 8525 | case ARM::VCLEzv4f16: |
| 8526 | case ARM::VCLEzv4f32: |
| 8527 | case ARM::VCLEzv4i16: |
| 8528 | case ARM::VCLEzv4i32: |
| 8529 | case ARM::VCLEzv8f16: |
| 8530 | case ARM::VCLEzv8i16: |
| 8531 | case ARM::VCLEzv8i8: |
| 8532 | case ARM::VCLSv16i8: |
| 8533 | case ARM::VCLSv2i32: |
| 8534 | case ARM::VCLSv4i16: |
| 8535 | case ARM::VCLSv4i32: |
| 8536 | case ARM::VCLSv8i16: |
| 8537 | case ARM::VCLSv8i8: |
| 8538 | case ARM::VCLTzv16i8: |
| 8539 | case ARM::VCLTzv2f32: |
| 8540 | case ARM::VCLTzv2i32: |
| 8541 | case ARM::VCLTzv4f16: |
| 8542 | case ARM::VCLTzv4f32: |
| 8543 | case ARM::VCLTzv4i16: |
| 8544 | case ARM::VCLTzv4i32: |
| 8545 | case ARM::VCLTzv8f16: |
| 8546 | case ARM::VCLTzv8i16: |
| 8547 | case ARM::VCLTzv8i8: |
| 8548 | case ARM::VCLZv16i8: |
| 8549 | case ARM::VCLZv2i32: |
| 8550 | case ARM::VCLZv4i16: |
| 8551 | case ARM::VCLZv4i32: |
| 8552 | case ARM::VCLZv8i16: |
| 8553 | case ARM::VCLZv8i8: |
| 8554 | case ARM::VCNTd: |
| 8555 | case ARM::VCNTq: |
| 8556 | case ARM::VCVTf2h: |
| 8557 | case ARM::VCVTf2sd: |
| 8558 | case ARM::VCVTf2sq: |
| 8559 | case ARM::VCVTf2ud: |
| 8560 | case ARM::VCVTf2uq: |
| 8561 | case ARM::VCVTh2f: |
| 8562 | case ARM::VCVTh2sd: |
| 8563 | case ARM::VCVTh2sq: |
| 8564 | case ARM::VCVTh2ud: |
| 8565 | case ARM::VCVTh2uq: |
| 8566 | case ARM::VCVTs2fd: |
| 8567 | case ARM::VCVTs2fq: |
| 8568 | case ARM::VCVTs2hd: |
| 8569 | case ARM::VCVTs2hq: |
| 8570 | case ARM::VCVTu2fd: |
| 8571 | case ARM::VCVTu2fq: |
| 8572 | case ARM::VCVTu2hd: |
| 8573 | case ARM::VCVTu2hq: |
| 8574 | case ARM::VMOVLsv2i64: |
| 8575 | case ARM::VMOVLsv4i32: |
| 8576 | case ARM::VMOVLsv8i16: |
| 8577 | case ARM::VMOVLuv2i64: |
| 8578 | case ARM::VMOVLuv4i32: |
| 8579 | case ARM::VMOVLuv8i16: |
| 8580 | case ARM::VMOVNv2i32: |
| 8581 | case ARM::VMOVNv4i16: |
| 8582 | case ARM::VMOVNv8i8: |
| 8583 | case ARM::VMVNd: |
| 8584 | case ARM::VMVNq: |
| 8585 | case ARM::VNEGf32q: |
| 8586 | case ARM::VNEGfd: |
| 8587 | case ARM::VNEGhd: |
| 8588 | case ARM::VNEGhq: |
| 8589 | case ARM::VNEGs16d: |
| 8590 | case ARM::VNEGs16q: |
| 8591 | case ARM::VNEGs32d: |
| 8592 | case ARM::VNEGs32q: |
| 8593 | case ARM::VNEGs8d: |
| 8594 | case ARM::VNEGs8q: |
| 8595 | case ARM::VPADDLsv16i8: |
| 8596 | case ARM::VPADDLsv2i32: |
| 8597 | case ARM::VPADDLsv4i16: |
| 8598 | case ARM::VPADDLsv4i32: |
| 8599 | case ARM::VPADDLsv8i16: |
| 8600 | case ARM::VPADDLsv8i8: |
| 8601 | case ARM::VPADDLuv16i8: |
| 8602 | case ARM::VPADDLuv2i32: |
| 8603 | case ARM::VPADDLuv4i16: |
| 8604 | case ARM::VPADDLuv4i32: |
| 8605 | case ARM::VPADDLuv8i16: |
| 8606 | case ARM::VPADDLuv8i8: |
| 8607 | case ARM::VQABSv16i8: |
| 8608 | case ARM::VQABSv2i32: |
| 8609 | case ARM::VQABSv4i16: |
| 8610 | case ARM::VQABSv4i32: |
| 8611 | case ARM::VQABSv8i16: |
| 8612 | case ARM::VQABSv8i8: |
| 8613 | case ARM::VQMOVNsuv2i32: |
| 8614 | case ARM::VQMOVNsuv4i16: |
| 8615 | case ARM::VQMOVNsuv8i8: |
| 8616 | case ARM::VQMOVNsv2i32: |
| 8617 | case ARM::VQMOVNsv4i16: |
| 8618 | case ARM::VQMOVNsv8i8: |
| 8619 | case ARM::VQMOVNuv2i32: |
| 8620 | case ARM::VQMOVNuv4i16: |
| 8621 | case ARM::VQMOVNuv8i8: |
| 8622 | case ARM::VQNEGv16i8: |
| 8623 | case ARM::VQNEGv2i32: |
| 8624 | case ARM::VQNEGv4i16: |
| 8625 | case ARM::VQNEGv4i32: |
| 8626 | case ARM::VQNEGv8i16: |
| 8627 | case ARM::VQNEGv8i8: |
| 8628 | case ARM::VRECPEd: |
| 8629 | case ARM::VRECPEfd: |
| 8630 | case ARM::VRECPEfq: |
| 8631 | case ARM::VRECPEhd: |
| 8632 | case ARM::VRECPEhq: |
| 8633 | case ARM::VRECPEq: |
| 8634 | case ARM::VREV16d8: |
| 8635 | case ARM::VREV16q8: |
| 8636 | case ARM::VREV32d16: |
| 8637 | case ARM::VREV32d8: |
| 8638 | case ARM::VREV32q16: |
| 8639 | case ARM::VREV32q8: |
| 8640 | case ARM::VREV64d16: |
| 8641 | case ARM::VREV64d32: |
| 8642 | case ARM::VREV64d8: |
| 8643 | case ARM::VREV64q16: |
| 8644 | case ARM::VREV64q32: |
| 8645 | case ARM::VREV64q8: |
| 8646 | case ARM::VRSQRTEd: |
| 8647 | case ARM::VRSQRTEfd: |
| 8648 | case ARM::VRSQRTEfq: |
| 8649 | case ARM::VRSQRTEhd: |
| 8650 | case ARM::VRSQRTEhq: |
| 8651 | case ARM::VRSQRTEq: |
| 8652 | case ARM::VSHLLi16: |
| 8653 | case ARM::VSHLLi32: |
| 8654 | case ARM::VSHLLi8: |
| 8655 | case ARM::VSWPd: |
| 8656 | case ARM::VSWPq: |
| 8657 | case ARM::VTRNd16: |
| 8658 | case ARM::VTRNd32: |
| 8659 | case ARM::VTRNd8: |
| 8660 | case ARM::VTRNq16: |
| 8661 | case ARM::VTRNq32: |
| 8662 | case ARM::VTRNq8: |
| 8663 | case ARM::VUZPd16: |
| 8664 | case ARM::VUZPd8: |
| 8665 | case ARM::VUZPq16: |
| 8666 | case ARM::VUZPq32: |
| 8667 | case ARM::VUZPq8: |
| 8668 | case ARM::VZIPd16: |
| 8669 | case ARM::VZIPd8: |
| 8670 | case ARM::VZIPq16: |
| 8671 | case ARM::VZIPq32: |
| 8672 | case ARM::VZIPq8: { |
| 8673 | // op: Vd |
| 8674 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8675 | Value |= (op & 0x10) << 18; |
| 8676 | Value |= (op & 0xf) << 12; |
| 8677 | // op: Vm |
| 8678 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8679 | Value |= (op & 0x10) << 1; |
| 8680 | Value |= (op & 0xf); |
| 8681 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8682 | break; |
| 8683 | } |
| 8684 | case ARM::VCVTANSDf: |
| 8685 | case ARM::VCVTANSDh: |
| 8686 | case ARM::VCVTANSQf: |
| 8687 | case ARM::VCVTANSQh: |
| 8688 | case ARM::VCVTANUDf: |
| 8689 | case ARM::VCVTANUDh: |
| 8690 | case ARM::VCVTANUQf: |
| 8691 | case ARM::VCVTANUQh: |
| 8692 | case ARM::VCVTMNSDf: |
| 8693 | case ARM::VCVTMNSDh: |
| 8694 | case ARM::VCVTMNSQf: |
| 8695 | case ARM::VCVTMNSQh: |
| 8696 | case ARM::VCVTMNUDf: |
| 8697 | case ARM::VCVTMNUDh: |
| 8698 | case ARM::VCVTMNUQf: |
| 8699 | case ARM::VCVTMNUQh: |
| 8700 | case ARM::VCVTNNSDf: |
| 8701 | case ARM::VCVTNNSDh: |
| 8702 | case ARM::VCVTNNSQf: |
| 8703 | case ARM::VCVTNNSQh: |
| 8704 | case ARM::VCVTNNUDf: |
| 8705 | case ARM::VCVTNNUDh: |
| 8706 | case ARM::VCVTNNUQf: |
| 8707 | case ARM::VCVTNNUQh: |
| 8708 | case ARM::VCVTPNSDf: |
| 8709 | case ARM::VCVTPNSDh: |
| 8710 | case ARM::VCVTPNSQf: |
| 8711 | case ARM::VCVTPNSQh: |
| 8712 | case ARM::VCVTPNUDf: |
| 8713 | case ARM::VCVTPNUDh: |
| 8714 | case ARM::VCVTPNUQf: |
| 8715 | case ARM::VCVTPNUQh: |
| 8716 | case ARM::VRINTANDf: |
| 8717 | case ARM::VRINTANDh: |
| 8718 | case ARM::VRINTANQf: |
| 8719 | case ARM::VRINTANQh: |
| 8720 | case ARM::VRINTMNDf: |
| 8721 | case ARM::VRINTMNDh: |
| 8722 | case ARM::VRINTMNQf: |
| 8723 | case ARM::VRINTMNQh: |
| 8724 | case ARM::VRINTNNDf: |
| 8725 | case ARM::VRINTNNDh: |
| 8726 | case ARM::VRINTNNQf: |
| 8727 | case ARM::VRINTNNQh: |
| 8728 | case ARM::VRINTPNDf: |
| 8729 | case ARM::VRINTPNDh: |
| 8730 | case ARM::VRINTPNQf: |
| 8731 | case ARM::VRINTPNQh: |
| 8732 | case ARM::VRINTXNDf: |
| 8733 | case ARM::VRINTXNDh: |
| 8734 | case ARM::VRINTXNQf: |
| 8735 | case ARM::VRINTXNQh: |
| 8736 | case ARM::VRINTZNDf: |
| 8737 | case ARM::VRINTZNDh: |
| 8738 | case ARM::VRINTZNQf: |
| 8739 | case ARM::VRINTZNQh: { |
| 8740 | // op: Vd |
| 8741 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8742 | Value |= (op & 0x10) << 18; |
| 8743 | Value |= (op & 0xf) << 12; |
| 8744 | // op: Vm |
| 8745 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8746 | Value |= (op & 0x10) << 1; |
| 8747 | Value |= (op & 0xf); |
| 8748 | Value = NEONThumb2V8PostEncoder(MI, EncodedValue: Value, STI); |
| 8749 | break; |
| 8750 | } |
| 8751 | case ARM::VSLIv2i32: |
| 8752 | case ARM::VSLIv4i32: { |
| 8753 | // op: Vd |
| 8754 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8755 | Value |= (op & 0x10) << 18; |
| 8756 | Value |= (op & 0xf) << 12; |
| 8757 | // op: Vm |
| 8758 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8759 | Value |= (op & 0x10) << 1; |
| 8760 | Value |= (op & 0xf); |
| 8761 | // op: SIMM |
| 8762 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8763 | Value |= (op & 0x1f) << 16; |
| 8764 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8765 | break; |
| 8766 | } |
| 8767 | case ARM::VSLIv1i64: |
| 8768 | case ARM::VSLIv2i64: { |
| 8769 | // op: Vd |
| 8770 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8771 | Value |= (op & 0x10) << 18; |
| 8772 | Value |= (op & 0xf) << 12; |
| 8773 | // op: Vm |
| 8774 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8775 | Value |= (op & 0x10) << 1; |
| 8776 | Value |= (op & 0xf); |
| 8777 | // op: SIMM |
| 8778 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8779 | Value |= (op & 0x3f) << 16; |
| 8780 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8781 | break; |
| 8782 | } |
| 8783 | case ARM::VSLIv16i8: |
| 8784 | case ARM::VSLIv8i8: { |
| 8785 | // op: Vd |
| 8786 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8787 | Value |= (op & 0x10) << 18; |
| 8788 | Value |= (op & 0xf) << 12; |
| 8789 | // op: Vm |
| 8790 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8791 | Value |= (op & 0x10) << 1; |
| 8792 | Value |= (op & 0xf); |
| 8793 | // op: SIMM |
| 8794 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8795 | Value |= (op & 0x7) << 16; |
| 8796 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8797 | break; |
| 8798 | } |
| 8799 | case ARM::VSLIv4i16: |
| 8800 | case ARM::VSLIv8i16: { |
| 8801 | // op: Vd |
| 8802 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8803 | Value |= (op & 0x10) << 18; |
| 8804 | Value |= (op & 0xf) << 12; |
| 8805 | // op: Vm |
| 8806 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8807 | Value |= (op & 0x10) << 1; |
| 8808 | Value |= (op & 0xf); |
| 8809 | // op: SIMM |
| 8810 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8811 | Value |= (op & 0xf) << 16; |
| 8812 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8813 | break; |
| 8814 | } |
| 8815 | case ARM::VRSRAsv4i16: |
| 8816 | case ARM::VRSRAsv8i16: |
| 8817 | case ARM::VRSRAuv4i16: |
| 8818 | case ARM::VRSRAuv8i16: |
| 8819 | case ARM::VSRAsv4i16: |
| 8820 | case ARM::VSRAsv8i16: |
| 8821 | case ARM::VSRAuv4i16: |
| 8822 | case ARM::VSRAuv8i16: |
| 8823 | case ARM::VSRIv4i16: |
| 8824 | case ARM::VSRIv8i16: { |
| 8825 | // op: Vd |
| 8826 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8827 | Value |= (op & 0x10) << 18; |
| 8828 | Value |= (op & 0xf) << 12; |
| 8829 | // op: Vm |
| 8830 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8831 | Value |= (op & 0x10) << 1; |
| 8832 | Value |= (op & 0xf); |
| 8833 | // op: SIMM |
| 8834 | op = getShiftRight16Imm(MI, Op: 3, Fixups, STI); |
| 8835 | Value |= (op & 0xf) << 16; |
| 8836 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8837 | break; |
| 8838 | } |
| 8839 | case ARM::VRSRAsv2i32: |
| 8840 | case ARM::VRSRAsv4i32: |
| 8841 | case ARM::VRSRAuv2i32: |
| 8842 | case ARM::VRSRAuv4i32: |
| 8843 | case ARM::VSRAsv2i32: |
| 8844 | case ARM::VSRAsv4i32: |
| 8845 | case ARM::VSRAuv2i32: |
| 8846 | case ARM::VSRAuv4i32: |
| 8847 | case ARM::VSRIv2i32: |
| 8848 | case ARM::VSRIv4i32: { |
| 8849 | // op: Vd |
| 8850 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8851 | Value |= (op & 0x10) << 18; |
| 8852 | Value |= (op & 0xf) << 12; |
| 8853 | // op: Vm |
| 8854 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8855 | Value |= (op & 0x10) << 1; |
| 8856 | Value |= (op & 0xf); |
| 8857 | // op: SIMM |
| 8858 | op = getShiftRight32Imm(MI, Op: 3, Fixups, STI); |
| 8859 | Value |= (op & 0x1f) << 16; |
| 8860 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8861 | break; |
| 8862 | } |
| 8863 | case ARM::VRSRAsv1i64: |
| 8864 | case ARM::VRSRAsv2i64: |
| 8865 | case ARM::VRSRAuv1i64: |
| 8866 | case ARM::VRSRAuv2i64: |
| 8867 | case ARM::VSRAsv1i64: |
| 8868 | case ARM::VSRAsv2i64: |
| 8869 | case ARM::VSRAuv1i64: |
| 8870 | case ARM::VSRAuv2i64: |
| 8871 | case ARM::VSRIv1i64: |
| 8872 | case ARM::VSRIv2i64: { |
| 8873 | // op: Vd |
| 8874 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8875 | Value |= (op & 0x10) << 18; |
| 8876 | Value |= (op & 0xf) << 12; |
| 8877 | // op: Vm |
| 8878 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8879 | Value |= (op & 0x10) << 1; |
| 8880 | Value |= (op & 0xf); |
| 8881 | // op: SIMM |
| 8882 | op = getShiftRight64Imm(MI, Op: 3, Fixups, STI); |
| 8883 | Value |= (op & 0x3f) << 16; |
| 8884 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8885 | break; |
| 8886 | } |
| 8887 | case ARM::VRSRAsv16i8: |
| 8888 | case ARM::VRSRAsv8i8: |
| 8889 | case ARM::VRSRAuv16i8: |
| 8890 | case ARM::VRSRAuv8i8: |
| 8891 | case ARM::VSRAsv16i8: |
| 8892 | case ARM::VSRAsv8i8: |
| 8893 | case ARM::VSRAuv16i8: |
| 8894 | case ARM::VSRAuv8i8: |
| 8895 | case ARM::VSRIv16i8: |
| 8896 | case ARM::VSRIv8i8: { |
| 8897 | // op: Vd |
| 8898 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8899 | Value |= (op & 0x10) << 18; |
| 8900 | Value |= (op & 0xf) << 12; |
| 8901 | // op: Vm |
| 8902 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8903 | Value |= (op & 0x10) << 1; |
| 8904 | Value |= (op & 0xf); |
| 8905 | // op: SIMM |
| 8906 | op = getShiftRight8Imm(MI, Op: 3, Fixups, STI); |
| 8907 | Value |= (op & 0x7) << 16; |
| 8908 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8909 | break; |
| 8910 | } |
| 8911 | case ARM::AESD: |
| 8912 | case ARM::AESE: |
| 8913 | case ARM::SHA1SU1: |
| 8914 | case ARM::SHA256SU0: |
| 8915 | case ARM::VPADALsv16i8: |
| 8916 | case ARM::VPADALsv2i32: |
| 8917 | case ARM::VPADALsv4i16: |
| 8918 | case ARM::VPADALsv4i32: |
| 8919 | case ARM::VPADALsv8i16: |
| 8920 | case ARM::VPADALsv8i8: |
| 8921 | case ARM::VPADALuv16i8: |
| 8922 | case ARM::VPADALuv2i32: |
| 8923 | case ARM::VPADALuv4i16: |
| 8924 | case ARM::VPADALuv4i32: |
| 8925 | case ARM::VPADALuv8i16: |
| 8926 | case ARM::VPADALuv8i8: { |
| 8927 | // op: Vd |
| 8928 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8929 | Value |= (op & 0x10) << 18; |
| 8930 | Value |= (op & 0xf) << 12; |
| 8931 | // op: Vm |
| 8932 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8933 | Value |= (op & 0x10) << 1; |
| 8934 | Value |= (op & 0xf); |
| 8935 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 8936 | break; |
| 8937 | } |
| 8938 | case ARM::VFMALD: |
| 8939 | case ARM::VFMSLD: { |
| 8940 | // op: Vd |
| 8941 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8942 | Value |= (op & 0x10) << 18; |
| 8943 | Value |= (op & 0xf) << 12; |
| 8944 | // op: Vn |
| 8945 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8946 | Value |= (op & 0x1e) << 15; |
| 8947 | Value |= (op & 0x1) << 7; |
| 8948 | // op: Vm |
| 8949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8950 | Value |= (op & 0x1) << 5; |
| 8951 | Value |= (op & 0x1e) >> 1; |
| 8952 | break; |
| 8953 | } |
| 8954 | case ARM::VFMALDI: |
| 8955 | case ARM::VFMSLDI: { |
| 8956 | // op: Vd |
| 8957 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8958 | Value |= (op & 0x10) << 18; |
| 8959 | Value |= (op & 0xf) << 12; |
| 8960 | // op: Vn |
| 8961 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8962 | Value |= (op & 0x1e) << 15; |
| 8963 | Value |= (op & 0x1) << 7; |
| 8964 | // op: Vm |
| 8965 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8966 | Value |= (op & 0x1) << 5; |
| 8967 | Value |= (op & 0xe) >> 1; |
| 8968 | // op: idx |
| 8969 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8970 | Value |= (op & 0x1) << 3; |
| 8971 | break; |
| 8972 | } |
| 8973 | case ARM::VFMALQ: |
| 8974 | case ARM::VFMSLQ: { |
| 8975 | // op: Vd |
| 8976 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8977 | Value |= (op & 0x10) << 18; |
| 8978 | Value |= (op & 0xf) << 12; |
| 8979 | // op: Vn |
| 8980 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8981 | Value |= (op & 0xf) << 16; |
| 8982 | Value |= (op & 0x10) << 3; |
| 8983 | // op: Vm |
| 8984 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8985 | Value |= (op & 0x10) << 1; |
| 8986 | Value |= (op & 0xf); |
| 8987 | break; |
| 8988 | } |
| 8989 | case ARM::VEXTd32: { |
| 8990 | // op: Vd |
| 8991 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8992 | Value |= (op & 0x10) << 18; |
| 8993 | Value |= (op & 0xf) << 12; |
| 8994 | // op: Vn |
| 8995 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8996 | Value |= (op & 0xf) << 16; |
| 8997 | Value |= (op & 0x10) << 3; |
| 8998 | // op: Vm |
| 8999 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9000 | Value |= (op & 0x10) << 1; |
| 9001 | Value |= (op & 0xf); |
| 9002 | // op: index |
| 9003 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9004 | Value |= (op & 0x1) << 10; |
| 9005 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9006 | break; |
| 9007 | } |
| 9008 | case ARM::VEXTq64: { |
| 9009 | // op: Vd |
| 9010 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9011 | Value |= (op & 0x10) << 18; |
| 9012 | Value |= (op & 0xf) << 12; |
| 9013 | // op: Vn |
| 9014 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9015 | Value |= (op & 0xf) << 16; |
| 9016 | Value |= (op & 0x10) << 3; |
| 9017 | // op: Vm |
| 9018 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9019 | Value |= (op & 0x10) << 1; |
| 9020 | Value |= (op & 0xf); |
| 9021 | // op: index |
| 9022 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9023 | Value |= (op & 0x1) << 11; |
| 9024 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9025 | break; |
| 9026 | } |
| 9027 | case ARM::VEXTq32: { |
| 9028 | // op: Vd |
| 9029 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9030 | Value |= (op & 0x10) << 18; |
| 9031 | Value |= (op & 0xf) << 12; |
| 9032 | // op: Vn |
| 9033 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9034 | Value |= (op & 0xf) << 16; |
| 9035 | Value |= (op & 0x10) << 3; |
| 9036 | // op: Vm |
| 9037 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9038 | Value |= (op & 0x10) << 1; |
| 9039 | Value |= (op & 0xf); |
| 9040 | // op: index |
| 9041 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9042 | Value |= (op & 0x3) << 10; |
| 9043 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9044 | break; |
| 9045 | } |
| 9046 | case ARM::VEXTd16: { |
| 9047 | // op: Vd |
| 9048 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9049 | Value |= (op & 0x10) << 18; |
| 9050 | Value |= (op & 0xf) << 12; |
| 9051 | // op: Vn |
| 9052 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9053 | Value |= (op & 0xf) << 16; |
| 9054 | Value |= (op & 0x10) << 3; |
| 9055 | // op: Vm |
| 9056 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9057 | Value |= (op & 0x10) << 1; |
| 9058 | Value |= (op & 0xf); |
| 9059 | // op: index |
| 9060 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9061 | Value |= (op & 0x3) << 9; |
| 9062 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9063 | break; |
| 9064 | } |
| 9065 | case ARM::VEXTd8: { |
| 9066 | // op: Vd |
| 9067 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9068 | Value |= (op & 0x10) << 18; |
| 9069 | Value |= (op & 0xf) << 12; |
| 9070 | // op: Vn |
| 9071 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9072 | Value |= (op & 0xf) << 16; |
| 9073 | Value |= (op & 0x10) << 3; |
| 9074 | // op: Vm |
| 9075 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9076 | Value |= (op & 0x10) << 1; |
| 9077 | Value |= (op & 0xf); |
| 9078 | // op: index |
| 9079 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9080 | Value |= (op & 0x7) << 8; |
| 9081 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9082 | break; |
| 9083 | } |
| 9084 | case ARM::VEXTq16: { |
| 9085 | // op: Vd |
| 9086 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9087 | Value |= (op & 0x10) << 18; |
| 9088 | Value |= (op & 0xf) << 12; |
| 9089 | // op: Vn |
| 9090 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9091 | Value |= (op & 0xf) << 16; |
| 9092 | Value |= (op & 0x10) << 3; |
| 9093 | // op: Vm |
| 9094 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9095 | Value |= (op & 0x10) << 1; |
| 9096 | Value |= (op & 0xf); |
| 9097 | // op: index |
| 9098 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9099 | Value |= (op & 0x7) << 9; |
| 9100 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9101 | break; |
| 9102 | } |
| 9103 | case ARM::VEXTq8: { |
| 9104 | // op: Vd |
| 9105 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9106 | Value |= (op & 0x10) << 18; |
| 9107 | Value |= (op & 0xf) << 12; |
| 9108 | // op: Vn |
| 9109 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9110 | Value |= (op & 0xf) << 16; |
| 9111 | Value |= (op & 0x10) << 3; |
| 9112 | // op: Vm |
| 9113 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9114 | Value |= (op & 0x10) << 1; |
| 9115 | Value |= (op & 0xf); |
| 9116 | // op: index |
| 9117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9118 | Value |= (op & 0xf) << 8; |
| 9119 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9120 | break; |
| 9121 | } |
| 9122 | case ARM::VCADDv2f32: |
| 9123 | case ARM::VCADDv4f16: |
| 9124 | case ARM::VCADDv4f32: |
| 9125 | case ARM::VCADDv8f16: { |
| 9126 | // op: Vd |
| 9127 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9128 | Value |= (op & 0x10) << 18; |
| 9129 | Value |= (op & 0xf) << 12; |
| 9130 | // op: Vn |
| 9131 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9132 | Value |= (op & 0xf) << 16; |
| 9133 | Value |= (op & 0x10) << 3; |
| 9134 | // op: Vm |
| 9135 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9136 | Value |= (op & 0x10) << 1; |
| 9137 | Value |= (op & 0xf); |
| 9138 | // op: rot |
| 9139 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9140 | Value |= (op & 0x1) << 24; |
| 9141 | break; |
| 9142 | } |
| 9143 | case ARM::VABDLsv2i64: |
| 9144 | case ARM::VABDLsv4i32: |
| 9145 | case ARM::VABDLsv8i16: |
| 9146 | case ARM::VABDLuv2i64: |
| 9147 | case ARM::VABDLuv4i32: |
| 9148 | case ARM::VABDLuv8i16: |
| 9149 | case ARM::VABDfd: |
| 9150 | case ARM::VABDfq: |
| 9151 | case ARM::VABDhd: |
| 9152 | case ARM::VABDhq: |
| 9153 | case ARM::VABDsv16i8: |
| 9154 | case ARM::VABDsv2i32: |
| 9155 | case ARM::VABDsv4i16: |
| 9156 | case ARM::VABDsv4i32: |
| 9157 | case ARM::VABDsv8i16: |
| 9158 | case ARM::VABDsv8i8: |
| 9159 | case ARM::VABDuv16i8: |
| 9160 | case ARM::VABDuv2i32: |
| 9161 | case ARM::VABDuv4i16: |
| 9162 | case ARM::VABDuv4i32: |
| 9163 | case ARM::VABDuv8i16: |
| 9164 | case ARM::VABDuv8i8: |
| 9165 | case ARM::VACGEfd: |
| 9166 | case ARM::VACGEfq: |
| 9167 | case ARM::VACGEhd: |
| 9168 | case ARM::VACGEhq: |
| 9169 | case ARM::VACGTfd: |
| 9170 | case ARM::VACGTfq: |
| 9171 | case ARM::VACGThd: |
| 9172 | case ARM::VACGThq: |
| 9173 | case ARM::VADDHNv2i32: |
| 9174 | case ARM::VADDHNv4i16: |
| 9175 | case ARM::VADDHNv8i8: |
| 9176 | case ARM::VADDLsv2i64: |
| 9177 | case ARM::VADDLsv4i32: |
| 9178 | case ARM::VADDLsv8i16: |
| 9179 | case ARM::VADDLuv2i64: |
| 9180 | case ARM::VADDLuv4i32: |
| 9181 | case ARM::VADDLuv8i16: |
| 9182 | case ARM::VADDWsv2i64: |
| 9183 | case ARM::VADDWsv4i32: |
| 9184 | case ARM::VADDWsv8i16: |
| 9185 | case ARM::VADDWuv2i64: |
| 9186 | case ARM::VADDWuv4i32: |
| 9187 | case ARM::VADDWuv8i16: |
| 9188 | case ARM::VADDfd: |
| 9189 | case ARM::VADDfq: |
| 9190 | case ARM::VADDhd: |
| 9191 | case ARM::VADDhq: |
| 9192 | case ARM::VADDv16i8: |
| 9193 | case ARM::VADDv1i64: |
| 9194 | case ARM::VADDv2i32: |
| 9195 | case ARM::VADDv2i64: |
| 9196 | case ARM::VADDv4i16: |
| 9197 | case ARM::VADDv4i32: |
| 9198 | case ARM::VADDv8i16: |
| 9199 | case ARM::VADDv8i8: |
| 9200 | case ARM::VANDd: |
| 9201 | case ARM::VANDq: |
| 9202 | case ARM::VBICd: |
| 9203 | case ARM::VBICq: |
| 9204 | case ARM::VCEQfd: |
| 9205 | case ARM::VCEQfq: |
| 9206 | case ARM::VCEQhd: |
| 9207 | case ARM::VCEQhq: |
| 9208 | case ARM::VCEQv16i8: |
| 9209 | case ARM::VCEQv2i32: |
| 9210 | case ARM::VCEQv4i16: |
| 9211 | case ARM::VCEQv4i32: |
| 9212 | case ARM::VCEQv8i16: |
| 9213 | case ARM::VCEQv8i8: |
| 9214 | case ARM::VCGEfd: |
| 9215 | case ARM::VCGEfq: |
| 9216 | case ARM::VCGEhd: |
| 9217 | case ARM::VCGEhq: |
| 9218 | case ARM::VCGEsv16i8: |
| 9219 | case ARM::VCGEsv2i32: |
| 9220 | case ARM::VCGEsv4i16: |
| 9221 | case ARM::VCGEsv4i32: |
| 9222 | case ARM::VCGEsv8i16: |
| 9223 | case ARM::VCGEsv8i8: |
| 9224 | case ARM::VCGEuv16i8: |
| 9225 | case ARM::VCGEuv2i32: |
| 9226 | case ARM::VCGEuv4i16: |
| 9227 | case ARM::VCGEuv4i32: |
| 9228 | case ARM::VCGEuv8i16: |
| 9229 | case ARM::VCGEuv8i8: |
| 9230 | case ARM::VCGTfd: |
| 9231 | case ARM::VCGTfq: |
| 9232 | case ARM::VCGThd: |
| 9233 | case ARM::VCGThq: |
| 9234 | case ARM::VCGTsv16i8: |
| 9235 | case ARM::VCGTsv2i32: |
| 9236 | case ARM::VCGTsv4i16: |
| 9237 | case ARM::VCGTsv4i32: |
| 9238 | case ARM::VCGTsv8i16: |
| 9239 | case ARM::VCGTsv8i8: |
| 9240 | case ARM::VCGTuv16i8: |
| 9241 | case ARM::VCGTuv2i32: |
| 9242 | case ARM::VCGTuv4i16: |
| 9243 | case ARM::VCGTuv4i32: |
| 9244 | case ARM::VCGTuv8i16: |
| 9245 | case ARM::VCGTuv8i8: |
| 9246 | case ARM::VEORd: |
| 9247 | case ARM::VEORq: |
| 9248 | case ARM::VHADDsv16i8: |
| 9249 | case ARM::VHADDsv2i32: |
| 9250 | case ARM::VHADDsv4i16: |
| 9251 | case ARM::VHADDsv4i32: |
| 9252 | case ARM::VHADDsv8i16: |
| 9253 | case ARM::VHADDsv8i8: |
| 9254 | case ARM::VHADDuv16i8: |
| 9255 | case ARM::VHADDuv2i32: |
| 9256 | case ARM::VHADDuv4i16: |
| 9257 | case ARM::VHADDuv4i32: |
| 9258 | case ARM::VHADDuv8i16: |
| 9259 | case ARM::VHADDuv8i8: |
| 9260 | case ARM::VHSUBsv16i8: |
| 9261 | case ARM::VHSUBsv2i32: |
| 9262 | case ARM::VHSUBsv4i16: |
| 9263 | case ARM::VHSUBsv4i32: |
| 9264 | case ARM::VHSUBsv8i16: |
| 9265 | case ARM::VHSUBsv8i8: |
| 9266 | case ARM::VHSUBuv16i8: |
| 9267 | case ARM::VHSUBuv2i32: |
| 9268 | case ARM::VHSUBuv4i16: |
| 9269 | case ARM::VHSUBuv4i32: |
| 9270 | case ARM::VHSUBuv8i16: |
| 9271 | case ARM::VHSUBuv8i8: |
| 9272 | case ARM::VMAXfd: |
| 9273 | case ARM::VMAXfq: |
| 9274 | case ARM::VMAXhd: |
| 9275 | case ARM::VMAXhq: |
| 9276 | case ARM::VMAXsv16i8: |
| 9277 | case ARM::VMAXsv2i32: |
| 9278 | case ARM::VMAXsv4i16: |
| 9279 | case ARM::VMAXsv4i32: |
| 9280 | case ARM::VMAXsv8i16: |
| 9281 | case ARM::VMAXsv8i8: |
| 9282 | case ARM::VMAXuv16i8: |
| 9283 | case ARM::VMAXuv2i32: |
| 9284 | case ARM::VMAXuv4i16: |
| 9285 | case ARM::VMAXuv4i32: |
| 9286 | case ARM::VMAXuv8i16: |
| 9287 | case ARM::VMAXuv8i8: |
| 9288 | case ARM::VMINfd: |
| 9289 | case ARM::VMINfq: |
| 9290 | case ARM::VMINhd: |
| 9291 | case ARM::VMINhq: |
| 9292 | case ARM::VMINsv16i8: |
| 9293 | case ARM::VMINsv2i32: |
| 9294 | case ARM::VMINsv4i16: |
| 9295 | case ARM::VMINsv4i32: |
| 9296 | case ARM::VMINsv8i16: |
| 9297 | case ARM::VMINsv8i8: |
| 9298 | case ARM::VMINuv16i8: |
| 9299 | case ARM::VMINuv2i32: |
| 9300 | case ARM::VMINuv4i16: |
| 9301 | case ARM::VMINuv4i32: |
| 9302 | case ARM::VMINuv8i16: |
| 9303 | case ARM::VMINuv8i8: |
| 9304 | case ARM::VMULLp64: |
| 9305 | case ARM::VMULLp8: |
| 9306 | case ARM::VMULLsv2i64: |
| 9307 | case ARM::VMULLsv4i32: |
| 9308 | case ARM::VMULLsv8i16: |
| 9309 | case ARM::VMULLuv2i64: |
| 9310 | case ARM::VMULLuv4i32: |
| 9311 | case ARM::VMULLuv8i16: |
| 9312 | case ARM::VMULfd: |
| 9313 | case ARM::VMULfq: |
| 9314 | case ARM::VMULhd: |
| 9315 | case ARM::VMULhq: |
| 9316 | case ARM::VMULpd: |
| 9317 | case ARM::VMULpq: |
| 9318 | case ARM::VMULv16i8: |
| 9319 | case ARM::VMULv2i32: |
| 9320 | case ARM::VMULv4i16: |
| 9321 | case ARM::VMULv4i32: |
| 9322 | case ARM::VMULv8i16: |
| 9323 | case ARM::VMULv8i8: |
| 9324 | case ARM::VORNd: |
| 9325 | case ARM::VORNq: |
| 9326 | case ARM::VORRd: |
| 9327 | case ARM::VORRq: |
| 9328 | case ARM::VPADDf: |
| 9329 | case ARM::VPADDh: |
| 9330 | case ARM::VPADDi16: |
| 9331 | case ARM::VPADDi32: |
| 9332 | case ARM::VPADDi8: |
| 9333 | case ARM::VPMAXf: |
| 9334 | case ARM::VPMAXh: |
| 9335 | case ARM::VPMAXs16: |
| 9336 | case ARM::VPMAXs32: |
| 9337 | case ARM::VPMAXs8: |
| 9338 | case ARM::VPMAXu16: |
| 9339 | case ARM::VPMAXu32: |
| 9340 | case ARM::VPMAXu8: |
| 9341 | case ARM::VPMINf: |
| 9342 | case ARM::VPMINh: |
| 9343 | case ARM::VPMINs16: |
| 9344 | case ARM::VPMINs32: |
| 9345 | case ARM::VPMINs8: |
| 9346 | case ARM::VPMINu16: |
| 9347 | case ARM::VPMINu32: |
| 9348 | case ARM::VPMINu8: |
| 9349 | case ARM::VQADDsv16i8: |
| 9350 | case ARM::VQADDsv1i64: |
| 9351 | case ARM::VQADDsv2i32: |
| 9352 | case ARM::VQADDsv2i64: |
| 9353 | case ARM::VQADDsv4i16: |
| 9354 | case ARM::VQADDsv4i32: |
| 9355 | case ARM::VQADDsv8i16: |
| 9356 | case ARM::VQADDsv8i8: |
| 9357 | case ARM::VQADDuv16i8: |
| 9358 | case ARM::VQADDuv1i64: |
| 9359 | case ARM::VQADDuv2i32: |
| 9360 | case ARM::VQADDuv2i64: |
| 9361 | case ARM::VQADDuv4i16: |
| 9362 | case ARM::VQADDuv4i32: |
| 9363 | case ARM::VQADDuv8i16: |
| 9364 | case ARM::VQADDuv8i8: |
| 9365 | case ARM::VQDMULHv2i32: |
| 9366 | case ARM::VQDMULHv4i16: |
| 9367 | case ARM::VQDMULHv4i32: |
| 9368 | case ARM::VQDMULHv8i16: |
| 9369 | case ARM::VQDMULLv2i64: |
| 9370 | case ARM::VQDMULLv4i32: |
| 9371 | case ARM::VQRDMULHv2i32: |
| 9372 | case ARM::VQRDMULHv4i16: |
| 9373 | case ARM::VQRDMULHv4i32: |
| 9374 | case ARM::VQRDMULHv8i16: |
| 9375 | case ARM::VQSUBsv16i8: |
| 9376 | case ARM::VQSUBsv1i64: |
| 9377 | case ARM::VQSUBsv2i32: |
| 9378 | case ARM::VQSUBsv2i64: |
| 9379 | case ARM::VQSUBsv4i16: |
| 9380 | case ARM::VQSUBsv4i32: |
| 9381 | case ARM::VQSUBsv8i16: |
| 9382 | case ARM::VQSUBsv8i8: |
| 9383 | case ARM::VQSUBuv16i8: |
| 9384 | case ARM::VQSUBuv1i64: |
| 9385 | case ARM::VQSUBuv2i32: |
| 9386 | case ARM::VQSUBuv2i64: |
| 9387 | case ARM::VQSUBuv4i16: |
| 9388 | case ARM::VQSUBuv4i32: |
| 9389 | case ARM::VQSUBuv8i16: |
| 9390 | case ARM::VQSUBuv8i8: |
| 9391 | case ARM::VRADDHNv2i32: |
| 9392 | case ARM::VRADDHNv4i16: |
| 9393 | case ARM::VRADDHNv8i8: |
| 9394 | case ARM::VRECPSfd: |
| 9395 | case ARM::VRECPSfq: |
| 9396 | case ARM::VRECPShd: |
| 9397 | case ARM::VRECPShq: |
| 9398 | case ARM::VRHADDsv16i8: |
| 9399 | case ARM::VRHADDsv2i32: |
| 9400 | case ARM::VRHADDsv4i16: |
| 9401 | case ARM::VRHADDsv4i32: |
| 9402 | case ARM::VRHADDsv8i16: |
| 9403 | case ARM::VRHADDsv8i8: |
| 9404 | case ARM::VRHADDuv16i8: |
| 9405 | case ARM::VRHADDuv2i32: |
| 9406 | case ARM::VRHADDuv4i16: |
| 9407 | case ARM::VRHADDuv4i32: |
| 9408 | case ARM::VRHADDuv8i16: |
| 9409 | case ARM::VRHADDuv8i8: |
| 9410 | case ARM::VRSQRTSfd: |
| 9411 | case ARM::VRSQRTSfq: |
| 9412 | case ARM::VRSQRTShd: |
| 9413 | case ARM::VRSQRTShq: |
| 9414 | case ARM::VRSUBHNv2i32: |
| 9415 | case ARM::VRSUBHNv4i16: |
| 9416 | case ARM::VRSUBHNv8i8: |
| 9417 | case ARM::VSUBHNv2i32: |
| 9418 | case ARM::VSUBHNv4i16: |
| 9419 | case ARM::VSUBHNv8i8: |
| 9420 | case ARM::VSUBLsv2i64: |
| 9421 | case ARM::VSUBLsv4i32: |
| 9422 | case ARM::VSUBLsv8i16: |
| 9423 | case ARM::VSUBLuv2i64: |
| 9424 | case ARM::VSUBLuv4i32: |
| 9425 | case ARM::VSUBLuv8i16: |
| 9426 | case ARM::VSUBWsv2i64: |
| 9427 | case ARM::VSUBWsv4i32: |
| 9428 | case ARM::VSUBWsv8i16: |
| 9429 | case ARM::VSUBWuv2i64: |
| 9430 | case ARM::VSUBWuv4i32: |
| 9431 | case ARM::VSUBWuv8i16: |
| 9432 | case ARM::VSUBfd: |
| 9433 | case ARM::VSUBfq: |
| 9434 | case ARM::VSUBhd: |
| 9435 | case ARM::VSUBhq: |
| 9436 | case ARM::VSUBv16i8: |
| 9437 | case ARM::VSUBv1i64: |
| 9438 | case ARM::VSUBv2i32: |
| 9439 | case ARM::VSUBv2i64: |
| 9440 | case ARM::VSUBv4i16: |
| 9441 | case ARM::VSUBv4i32: |
| 9442 | case ARM::VSUBv8i16: |
| 9443 | case ARM::VSUBv8i8: |
| 9444 | case ARM::VTBL1: |
| 9445 | case ARM::VTBL2: |
| 9446 | case ARM::VTBL3: |
| 9447 | case ARM::VTBL4: |
| 9448 | case ARM::VTSTv16i8: |
| 9449 | case ARM::VTSTv2i32: |
| 9450 | case ARM::VTSTv4i16: |
| 9451 | case ARM::VTSTv4i32: |
| 9452 | case ARM::VTSTv8i16: |
| 9453 | case ARM::VTSTv8i8: { |
| 9454 | // op: Vd |
| 9455 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9456 | Value |= (op & 0x10) << 18; |
| 9457 | Value |= (op & 0xf) << 12; |
| 9458 | // op: Vn |
| 9459 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9460 | Value |= (op & 0xf) << 16; |
| 9461 | Value |= (op & 0x10) << 3; |
| 9462 | // op: Vm |
| 9463 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9464 | Value |= (op & 0x10) << 1; |
| 9465 | Value |= (op & 0xf); |
| 9466 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9467 | break; |
| 9468 | } |
| 9469 | case ARM::NEON_VMAXNMNDf: |
| 9470 | case ARM::NEON_VMAXNMNDh: |
| 9471 | case ARM::NEON_VMAXNMNQf: |
| 9472 | case ARM::NEON_VMAXNMNQh: |
| 9473 | case ARM::NEON_VMINNMNDf: |
| 9474 | case ARM::NEON_VMINNMNDh: |
| 9475 | case ARM::NEON_VMINNMNQf: |
| 9476 | case ARM::NEON_VMINNMNQh: { |
| 9477 | // op: Vd |
| 9478 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9479 | Value |= (op & 0x10) << 18; |
| 9480 | Value |= (op & 0xf) << 12; |
| 9481 | // op: Vn |
| 9482 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9483 | Value |= (op & 0xf) << 16; |
| 9484 | Value |= (op & 0x10) << 3; |
| 9485 | // op: Vm |
| 9486 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9487 | Value |= (op & 0x10) << 1; |
| 9488 | Value |= (op & 0xf); |
| 9489 | Value = NEONThumb2V8PostEncoder(MI, EncodedValue: Value, STI); |
| 9490 | break; |
| 9491 | } |
| 9492 | case ARM::VFMALQI: |
| 9493 | case ARM::VFMSLQI: { |
| 9494 | // op: Vd |
| 9495 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9496 | Value |= (op & 0x10) << 18; |
| 9497 | Value |= (op & 0xf) << 12; |
| 9498 | // op: Vn |
| 9499 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9500 | Value |= (op & 0xf) << 16; |
| 9501 | Value |= (op & 0x10) << 3; |
| 9502 | // op: Vm |
| 9503 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9504 | Value |= (op & 0x7); |
| 9505 | // op: idx |
| 9506 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9507 | Value |= (op & 0x2) << 4; |
| 9508 | Value |= (op & 0x1) << 3; |
| 9509 | break; |
| 9510 | } |
| 9511 | case ARM::VMULLslsv4i16: |
| 9512 | case ARM::VMULLsluv4i16: |
| 9513 | case ARM::VMULslhd: |
| 9514 | case ARM::VMULslhq: |
| 9515 | case ARM::VMULslv4i16: |
| 9516 | case ARM::VMULslv8i16: |
| 9517 | case ARM::VQDMULHslv4i16: |
| 9518 | case ARM::VQDMULHslv8i16: |
| 9519 | case ARM::VQDMULLslv4i16: |
| 9520 | case ARM::VQRDMULHslv4i16: |
| 9521 | case ARM::VQRDMULHslv8i16: { |
| 9522 | // op: Vd |
| 9523 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9524 | Value |= (op & 0x10) << 18; |
| 9525 | Value |= (op & 0xf) << 12; |
| 9526 | // op: Vn |
| 9527 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9528 | Value |= (op & 0xf) << 16; |
| 9529 | Value |= (op & 0x10) << 3; |
| 9530 | // op: Vm |
| 9531 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9532 | Value |= (op & 0x7); |
| 9533 | // op: lane |
| 9534 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9535 | Value |= (op & 0x2) << 4; |
| 9536 | Value |= (op & 0x1) << 3; |
| 9537 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9538 | break; |
| 9539 | } |
| 9540 | case ARM::VMULLslsv2i32: |
| 9541 | case ARM::VMULLsluv2i32: |
| 9542 | case ARM::VMULslfd: |
| 9543 | case ARM::VMULslfq: |
| 9544 | case ARM::VMULslv2i32: |
| 9545 | case ARM::VMULslv4i32: |
| 9546 | case ARM::VQDMULHslv2i32: |
| 9547 | case ARM::VQDMULHslv4i32: |
| 9548 | case ARM::VQDMULLslv2i32: |
| 9549 | case ARM::VQRDMULHslv2i32: |
| 9550 | case ARM::VQRDMULHslv4i32: { |
| 9551 | // op: Vd |
| 9552 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9553 | Value |= (op & 0x10) << 18; |
| 9554 | Value |= (op & 0xf) << 12; |
| 9555 | // op: Vn |
| 9556 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9557 | Value |= (op & 0xf) << 16; |
| 9558 | Value |= (op & 0x10) << 3; |
| 9559 | // op: Vm |
| 9560 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9561 | Value |= (op & 0xf); |
| 9562 | // op: lane |
| 9563 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9564 | Value |= (op & 0x1) << 5; |
| 9565 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9566 | break; |
| 9567 | } |
| 9568 | case ARM::VQRSHLsv16i8: |
| 9569 | case ARM::VQRSHLsv1i64: |
| 9570 | case ARM::VQRSHLsv2i32: |
| 9571 | case ARM::VQRSHLsv2i64: |
| 9572 | case ARM::VQRSHLsv4i16: |
| 9573 | case ARM::VQRSHLsv4i32: |
| 9574 | case ARM::VQRSHLsv8i16: |
| 9575 | case ARM::VQRSHLsv8i8: |
| 9576 | case ARM::VQRSHLuv16i8: |
| 9577 | case ARM::VQRSHLuv1i64: |
| 9578 | case ARM::VQRSHLuv2i32: |
| 9579 | case ARM::VQRSHLuv2i64: |
| 9580 | case ARM::VQRSHLuv4i16: |
| 9581 | case ARM::VQRSHLuv4i32: |
| 9582 | case ARM::VQRSHLuv8i16: |
| 9583 | case ARM::VQRSHLuv8i8: |
| 9584 | case ARM::VQSHLsv16i8: |
| 9585 | case ARM::VQSHLsv1i64: |
| 9586 | case ARM::VQSHLsv2i32: |
| 9587 | case ARM::VQSHLsv2i64: |
| 9588 | case ARM::VQSHLsv4i16: |
| 9589 | case ARM::VQSHLsv4i32: |
| 9590 | case ARM::VQSHLsv8i16: |
| 9591 | case ARM::VQSHLsv8i8: |
| 9592 | case ARM::VQSHLuv16i8: |
| 9593 | case ARM::VQSHLuv1i64: |
| 9594 | case ARM::VQSHLuv2i32: |
| 9595 | case ARM::VQSHLuv2i64: |
| 9596 | case ARM::VQSHLuv4i16: |
| 9597 | case ARM::VQSHLuv4i32: |
| 9598 | case ARM::VQSHLuv8i16: |
| 9599 | case ARM::VQSHLuv8i8: |
| 9600 | case ARM::VRSHLsv16i8: |
| 9601 | case ARM::VRSHLsv1i64: |
| 9602 | case ARM::VRSHLsv2i32: |
| 9603 | case ARM::VRSHLsv2i64: |
| 9604 | case ARM::VRSHLsv4i16: |
| 9605 | case ARM::VRSHLsv4i32: |
| 9606 | case ARM::VRSHLsv8i16: |
| 9607 | case ARM::VRSHLsv8i8: |
| 9608 | case ARM::VRSHLuv16i8: |
| 9609 | case ARM::VRSHLuv1i64: |
| 9610 | case ARM::VRSHLuv2i32: |
| 9611 | case ARM::VRSHLuv2i64: |
| 9612 | case ARM::VRSHLuv4i16: |
| 9613 | case ARM::VRSHLuv4i32: |
| 9614 | case ARM::VRSHLuv8i16: |
| 9615 | case ARM::VRSHLuv8i8: |
| 9616 | case ARM::VSHLsv16i8: |
| 9617 | case ARM::VSHLsv1i64: |
| 9618 | case ARM::VSHLsv2i32: |
| 9619 | case ARM::VSHLsv2i64: |
| 9620 | case ARM::VSHLsv4i16: |
| 9621 | case ARM::VSHLsv4i32: |
| 9622 | case ARM::VSHLsv8i16: |
| 9623 | case ARM::VSHLsv8i8: |
| 9624 | case ARM::VSHLuv16i8: |
| 9625 | case ARM::VSHLuv1i64: |
| 9626 | case ARM::VSHLuv2i32: |
| 9627 | case ARM::VSHLuv2i64: |
| 9628 | case ARM::VSHLuv4i16: |
| 9629 | case ARM::VSHLuv4i32: |
| 9630 | case ARM::VSHLuv8i16: |
| 9631 | case ARM::VSHLuv8i8: { |
| 9632 | // op: Vd |
| 9633 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9634 | Value |= (op & 0x10) << 18; |
| 9635 | Value |= (op & 0xf) << 12; |
| 9636 | // op: Vn |
| 9637 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9638 | Value |= (op & 0xf) << 16; |
| 9639 | Value |= (op & 0x10) << 3; |
| 9640 | // op: Vm |
| 9641 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9642 | Value |= (op & 0x10) << 1; |
| 9643 | Value |= (op & 0xf); |
| 9644 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9645 | break; |
| 9646 | } |
| 9647 | case ARM::VCMLAv2f32: |
| 9648 | case ARM::VCMLAv4f16: |
| 9649 | case ARM::VCMLAv4f32: |
| 9650 | case ARM::VCMLAv8f16: { |
| 9651 | // op: Vd |
| 9652 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9653 | Value |= (op & 0x10) << 18; |
| 9654 | Value |= (op & 0xf) << 12; |
| 9655 | // op: Vn |
| 9656 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9657 | Value |= (op & 0xf) << 16; |
| 9658 | Value |= (op & 0x10) << 3; |
| 9659 | // op: Vm |
| 9660 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9661 | Value |= (op & 0x10) << 1; |
| 9662 | Value |= (op & 0xf); |
| 9663 | // op: rot |
| 9664 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9665 | Value |= (op & 0x3) << 23; |
| 9666 | break; |
| 9667 | } |
| 9668 | case ARM::VCMLAv2f32_indexed: |
| 9669 | case ARM::VCMLAv4f32_indexed: { |
| 9670 | // op: Vd |
| 9671 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9672 | Value |= (op & 0x10) << 18; |
| 9673 | Value |= (op & 0xf) << 12; |
| 9674 | // op: Vn |
| 9675 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9676 | Value |= (op & 0xf) << 16; |
| 9677 | Value |= (op & 0x10) << 3; |
| 9678 | // op: Vm |
| 9679 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9680 | Value |= (op & 0x10) << 1; |
| 9681 | Value |= (op & 0xf); |
| 9682 | // op: rot |
| 9683 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 9684 | Value |= (op & 0x3) << 20; |
| 9685 | break; |
| 9686 | } |
| 9687 | case ARM::SHA1C: |
| 9688 | case ARM::SHA1M: |
| 9689 | case ARM::SHA1P: |
| 9690 | case ARM::SHA1SU0: |
| 9691 | case ARM::SHA256H: |
| 9692 | case ARM::SHA256H2: |
| 9693 | case ARM::SHA256SU1: |
| 9694 | case ARM::VABALsv2i64: |
| 9695 | case ARM::VABALsv4i32: |
| 9696 | case ARM::VABALsv8i16: |
| 9697 | case ARM::VABALuv2i64: |
| 9698 | case ARM::VABALuv4i32: |
| 9699 | case ARM::VABALuv8i16: |
| 9700 | case ARM::VABAsv16i8: |
| 9701 | case ARM::VABAsv2i32: |
| 9702 | case ARM::VABAsv4i16: |
| 9703 | case ARM::VABAsv4i32: |
| 9704 | case ARM::VABAsv8i16: |
| 9705 | case ARM::VABAsv8i8: |
| 9706 | case ARM::VABAuv16i8: |
| 9707 | case ARM::VABAuv2i32: |
| 9708 | case ARM::VABAuv4i16: |
| 9709 | case ARM::VABAuv4i32: |
| 9710 | case ARM::VABAuv8i16: |
| 9711 | case ARM::VABAuv8i8: |
| 9712 | case ARM::VBIFd: |
| 9713 | case ARM::VBIFq: |
| 9714 | case ARM::VBITd: |
| 9715 | case ARM::VBITq: |
| 9716 | case ARM::VBSLd: |
| 9717 | case ARM::VBSLq: |
| 9718 | case ARM::VFMAfd: |
| 9719 | case ARM::VFMAfq: |
| 9720 | case ARM::VFMAhd: |
| 9721 | case ARM::VFMAhq: |
| 9722 | case ARM::VFMSfd: |
| 9723 | case ARM::VFMSfq: |
| 9724 | case ARM::VFMShd: |
| 9725 | case ARM::VFMShq: |
| 9726 | case ARM::VMLALsv2i64: |
| 9727 | case ARM::VMLALsv4i32: |
| 9728 | case ARM::VMLALsv8i16: |
| 9729 | case ARM::VMLALuv2i64: |
| 9730 | case ARM::VMLALuv4i32: |
| 9731 | case ARM::VMLALuv8i16: |
| 9732 | case ARM::VMLAfd: |
| 9733 | case ARM::VMLAfq: |
| 9734 | case ARM::VMLAhd: |
| 9735 | case ARM::VMLAhq: |
| 9736 | case ARM::VMLAv16i8: |
| 9737 | case ARM::VMLAv2i32: |
| 9738 | case ARM::VMLAv4i16: |
| 9739 | case ARM::VMLAv4i32: |
| 9740 | case ARM::VMLAv8i16: |
| 9741 | case ARM::VMLAv8i8: |
| 9742 | case ARM::VMLSLsv2i64: |
| 9743 | case ARM::VMLSLsv4i32: |
| 9744 | case ARM::VMLSLsv8i16: |
| 9745 | case ARM::VMLSLuv2i64: |
| 9746 | case ARM::VMLSLuv4i32: |
| 9747 | case ARM::VMLSLuv8i16: |
| 9748 | case ARM::VMLSfd: |
| 9749 | case ARM::VMLSfq: |
| 9750 | case ARM::VMLShd: |
| 9751 | case ARM::VMLShq: |
| 9752 | case ARM::VMLSv16i8: |
| 9753 | case ARM::VMLSv2i32: |
| 9754 | case ARM::VMLSv4i16: |
| 9755 | case ARM::VMLSv4i32: |
| 9756 | case ARM::VMLSv8i16: |
| 9757 | case ARM::VMLSv8i8: |
| 9758 | case ARM::VQDMLALv2i64: |
| 9759 | case ARM::VQDMLALv4i32: |
| 9760 | case ARM::VQDMLSLv2i64: |
| 9761 | case ARM::VQDMLSLv4i32: |
| 9762 | case ARM::VQRDMLAHv2i32: |
| 9763 | case ARM::VQRDMLAHv4i16: |
| 9764 | case ARM::VQRDMLAHv4i32: |
| 9765 | case ARM::VQRDMLAHv8i16: |
| 9766 | case ARM::VQRDMLSHv2i32: |
| 9767 | case ARM::VQRDMLSHv4i16: |
| 9768 | case ARM::VQRDMLSHv4i32: |
| 9769 | case ARM::VQRDMLSHv8i16: |
| 9770 | case ARM::VTBX1: |
| 9771 | case ARM::VTBX2: |
| 9772 | case ARM::VTBX3: |
| 9773 | case ARM::VTBX4: { |
| 9774 | // op: Vd |
| 9775 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9776 | Value |= (op & 0x10) << 18; |
| 9777 | Value |= (op & 0xf) << 12; |
| 9778 | // op: Vn |
| 9779 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9780 | Value |= (op & 0xf) << 16; |
| 9781 | Value |= (op & 0x10) << 3; |
| 9782 | // op: Vm |
| 9783 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9784 | Value |= (op & 0x10) << 1; |
| 9785 | Value |= (op & 0xf); |
| 9786 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9787 | break; |
| 9788 | } |
| 9789 | case ARM::VMLALslsv4i16: |
| 9790 | case ARM::VMLALsluv4i16: |
| 9791 | case ARM::VMLAslhd: |
| 9792 | case ARM::VMLAslhq: |
| 9793 | case ARM::VMLAslv4i16: |
| 9794 | case ARM::VMLAslv8i16: |
| 9795 | case ARM::VMLSLslsv4i16: |
| 9796 | case ARM::VMLSLsluv4i16: |
| 9797 | case ARM::VMLSslhd: |
| 9798 | case ARM::VMLSslhq: |
| 9799 | case ARM::VMLSslv4i16: |
| 9800 | case ARM::VMLSslv8i16: |
| 9801 | case ARM::VQDMLALslv4i16: |
| 9802 | case ARM::VQDMLSLslv4i16: |
| 9803 | case ARM::VQRDMLAHslv4i16: |
| 9804 | case ARM::VQRDMLAHslv8i16: |
| 9805 | case ARM::VQRDMLSHslv4i16: |
| 9806 | case ARM::VQRDMLSHslv8i16: { |
| 9807 | // op: Vd |
| 9808 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9809 | Value |= (op & 0x10) << 18; |
| 9810 | Value |= (op & 0xf) << 12; |
| 9811 | // op: Vn |
| 9812 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9813 | Value |= (op & 0xf) << 16; |
| 9814 | Value |= (op & 0x10) << 3; |
| 9815 | // op: Vm |
| 9816 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9817 | Value |= (op & 0x7); |
| 9818 | // op: lane |
| 9819 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9820 | Value |= (op & 0x2) << 4; |
| 9821 | Value |= (op & 0x1) << 3; |
| 9822 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9823 | break; |
| 9824 | } |
| 9825 | case ARM::VMLALslsv2i32: |
| 9826 | case ARM::VMLALsluv2i32: |
| 9827 | case ARM::VMLAslfd: |
| 9828 | case ARM::VMLAslfq: |
| 9829 | case ARM::VMLAslv2i32: |
| 9830 | case ARM::VMLAslv4i32: |
| 9831 | case ARM::VMLSLslsv2i32: |
| 9832 | case ARM::VMLSLsluv2i32: |
| 9833 | case ARM::VMLSslfd: |
| 9834 | case ARM::VMLSslfq: |
| 9835 | case ARM::VMLSslv2i32: |
| 9836 | case ARM::VMLSslv4i32: |
| 9837 | case ARM::VQDMLALslv2i32: |
| 9838 | case ARM::VQDMLSLslv2i32: |
| 9839 | case ARM::VQRDMLAHslv2i32: |
| 9840 | case ARM::VQRDMLAHslv4i32: |
| 9841 | case ARM::VQRDMLSHslv2i32: |
| 9842 | case ARM::VQRDMLSHslv4i32: { |
| 9843 | // op: Vd |
| 9844 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9845 | Value |= (op & 0x10) << 18; |
| 9846 | Value |= (op & 0xf) << 12; |
| 9847 | // op: Vn |
| 9848 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9849 | Value |= (op & 0xf) << 16; |
| 9850 | Value |= (op & 0x10) << 3; |
| 9851 | // op: Vm |
| 9852 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9853 | Value |= (op & 0xf); |
| 9854 | // op: lane |
| 9855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9856 | Value |= (op & 0x1) << 5; |
| 9857 | Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI); |
| 9858 | break; |
| 9859 | } |
| 9860 | case ARM::VCMLAv4f16_indexed: |
| 9861 | case ARM::VCMLAv8f16_indexed: { |
| 9862 | // op: Vd |
| 9863 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9864 | Value |= (op & 0x10) << 18; |
| 9865 | Value |= (op & 0xf) << 12; |
| 9866 | // op: Vn |
| 9867 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9868 | Value |= (op & 0xf) << 16; |
| 9869 | Value |= (op & 0x10) << 3; |
| 9870 | // op: Vm |
| 9871 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9872 | Value |= (op & 0xf); |
| 9873 | // op: rot |
| 9874 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 9875 | Value |= (op & 0x3) << 20; |
| 9876 | // op: lane |
| 9877 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9878 | Value |= (op & 0x1) << 5; |
| 9879 | break; |
| 9880 | } |
| 9881 | case ARM::BF16VDOTS_VDOTD: |
| 9882 | case ARM::BF16VDOTS_VDOTQ: |
| 9883 | case ARM::VBF16MALBQ: |
| 9884 | case ARM::VBF16MALTQ: |
| 9885 | case ARM::VMMLA: |
| 9886 | case ARM::VSDOTD: |
| 9887 | case ARM::VSDOTQ: |
| 9888 | case ARM::VSMMLA: |
| 9889 | case ARM::VUDOTD: |
| 9890 | case ARM::VUDOTQ: |
| 9891 | case ARM::VUMMLA: |
| 9892 | case ARM::VUSDOTD: |
| 9893 | case ARM::VUSDOTQ: |
| 9894 | case ARM::VUSMMLA: { |
| 9895 | // op: Vd |
| 9896 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9897 | Value |= (op & 0x10) << 18; |
| 9898 | Value |= (op & 0xf) << 12; |
| 9899 | // op: Vn |
| 9900 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9901 | Value |= (op & 0xf) << 16; |
| 9902 | Value |= (op & 0x10) << 3; |
| 9903 | // op: Vm |
| 9904 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9905 | Value |= (op & 0x10) << 1; |
| 9906 | Value |= (op & 0xf); |
| 9907 | break; |
| 9908 | } |
| 9909 | case ARM::VBF16MALBQI: |
| 9910 | case ARM::VBF16MALTQI: { |
| 9911 | // op: Vd |
| 9912 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9913 | Value |= (op & 0x10) << 18; |
| 9914 | Value |= (op & 0xf) << 12; |
| 9915 | // op: Vn |
| 9916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9917 | Value |= (op & 0xf) << 16; |
| 9918 | Value |= (op & 0x10) << 3; |
| 9919 | // op: Vm |
| 9920 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9921 | Value |= (op & 0x7); |
| 9922 | // op: idx |
| 9923 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9924 | Value |= (op & 0x2) << 4; |
| 9925 | Value |= (op & 0x1) << 3; |
| 9926 | break; |
| 9927 | } |
| 9928 | case ARM::BF16VDOTI_VDOTD: |
| 9929 | case ARM::BF16VDOTI_VDOTQ: |
| 9930 | case ARM::VSDOTDI: |
| 9931 | case ARM::VSDOTQI: |
| 9932 | case ARM::VSUDOTDI: |
| 9933 | case ARM::VSUDOTQI: |
| 9934 | case ARM::VUDOTDI: |
| 9935 | case ARM::VUDOTQI: |
| 9936 | case ARM::VUSDOTDI: |
| 9937 | case ARM::VUSDOTQI: { |
| 9938 | // op: Vd |
| 9939 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9940 | Value |= (op & 0x10) << 18; |
| 9941 | Value |= (op & 0xf) << 12; |
| 9942 | // op: Vn |
| 9943 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9944 | Value |= (op & 0xf) << 16; |
| 9945 | Value |= (op & 0x10) << 3; |
| 9946 | // op: Vm |
| 9947 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9948 | Value |= (op & 0xf); |
| 9949 | // op: lane |
| 9950 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9951 | Value |= (op & 0x1) << 5; |
| 9952 | break; |
| 9953 | } |
| 9954 | case ARM::VST1LNd8: { |
| 9955 | // op: Vd |
| 9956 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9957 | Value |= (op & 0x10) << 18; |
| 9958 | Value |= (op & 0xf) << 12; |
| 9959 | // op: Rn |
| 9960 | op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI); |
| 9961 | Value |= (op & 0xf) << 16; |
| 9962 | // op: lane |
| 9963 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9964 | Value |= (op & 0x7) << 5; |
| 9965 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 9966 | break; |
| 9967 | } |
| 9968 | case ARM::VST3LNd32: |
| 9969 | case ARM::VST3LNq32: { |
| 9970 | // op: Vd |
| 9971 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9972 | Value |= (op & 0x10) << 18; |
| 9973 | Value |= (op & 0xf) << 12; |
| 9974 | // op: Rn |
| 9975 | op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI); |
| 9976 | Value |= (op & 0xf) << 16; |
| 9977 | // op: lane |
| 9978 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 9979 | Value |= (op & 0x1) << 7; |
| 9980 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 9981 | break; |
| 9982 | } |
| 9983 | case ARM::VST3LNd16: |
| 9984 | case ARM::VST3LNq16: { |
| 9985 | // op: Vd |
| 9986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9987 | Value |= (op & 0x10) << 18; |
| 9988 | Value |= (op & 0xf) << 12; |
| 9989 | // op: Rn |
| 9990 | op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI); |
| 9991 | Value |= (op & 0xf) << 16; |
| 9992 | // op: lane |
| 9993 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 9994 | Value |= (op & 0x3) << 6; |
| 9995 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 9996 | break; |
| 9997 | } |
| 9998 | case ARM::VST3LNd8: { |
| 9999 | // op: Vd |
| 10000 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10001 | Value |= (op & 0x10) << 18; |
| 10002 | Value |= (op & 0xf) << 12; |
| 10003 | // op: Rn |
| 10004 | op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI); |
| 10005 | Value |= (op & 0xf) << 16; |
| 10006 | // op: lane |
| 10007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 10008 | Value |= (op & 0x7) << 5; |
| 10009 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10010 | break; |
| 10011 | } |
| 10012 | case ARM::VST1LNd16: { |
| 10013 | // op: Vd |
| 10014 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10015 | Value |= (op & 0x10) << 18; |
| 10016 | Value |= (op & 0xf) << 12; |
| 10017 | // op: Rn |
| 10018 | op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI); |
| 10019 | Value |= (op & 0xf) << 16; |
| 10020 | Value |= (op & 0x10); |
| 10021 | // op: lane |
| 10022 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10023 | Value |= (op & 0x3) << 6; |
| 10024 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10025 | break; |
| 10026 | } |
| 10027 | case ARM::VST2LNd32: |
| 10028 | case ARM::VST2LNq32: { |
| 10029 | // op: Vd |
| 10030 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10031 | Value |= (op & 0x10) << 18; |
| 10032 | Value |= (op & 0xf) << 12; |
| 10033 | // op: Rn |
| 10034 | op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI); |
| 10035 | Value |= (op & 0xf) << 16; |
| 10036 | Value |= (op & 0x10); |
| 10037 | // op: lane |
| 10038 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10039 | Value |= (op & 0x1) << 7; |
| 10040 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10041 | break; |
| 10042 | } |
| 10043 | case ARM::VST2LNd16: |
| 10044 | case ARM::VST2LNq16: { |
| 10045 | // op: Vd |
| 10046 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10047 | Value |= (op & 0x10) << 18; |
| 10048 | Value |= (op & 0xf) << 12; |
| 10049 | // op: Rn |
| 10050 | op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI); |
| 10051 | Value |= (op & 0xf) << 16; |
| 10052 | Value |= (op & 0x10); |
| 10053 | // op: lane |
| 10054 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10055 | Value |= (op & 0x3) << 6; |
| 10056 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10057 | break; |
| 10058 | } |
| 10059 | case ARM::VST2LNd8: { |
| 10060 | // op: Vd |
| 10061 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10062 | Value |= (op & 0x10) << 18; |
| 10063 | Value |= (op & 0xf) << 12; |
| 10064 | // op: Rn |
| 10065 | op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI); |
| 10066 | Value |= (op & 0xf) << 16; |
| 10067 | Value |= (op & 0x10); |
| 10068 | // op: lane |
| 10069 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10070 | Value |= (op & 0x7) << 5; |
| 10071 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10072 | break; |
| 10073 | } |
| 10074 | case ARM::VST4LNd16: |
| 10075 | case ARM::VST4LNq16: { |
| 10076 | // op: Vd |
| 10077 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10078 | Value |= (op & 0x10) << 18; |
| 10079 | Value |= (op & 0xf) << 12; |
| 10080 | // op: Rn |
| 10081 | op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI); |
| 10082 | Value |= (op & 0xf) << 16; |
| 10083 | Value |= (op & 0x10); |
| 10084 | // op: lane |
| 10085 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 10086 | Value |= (op & 0x3) << 6; |
| 10087 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10088 | break; |
| 10089 | } |
| 10090 | case ARM::VST4LNd8: { |
| 10091 | // op: Vd |
| 10092 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10093 | Value |= (op & 0x10) << 18; |
| 10094 | Value |= (op & 0xf) << 12; |
| 10095 | // op: Rn |
| 10096 | op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI); |
| 10097 | Value |= (op & 0xf) << 16; |
| 10098 | Value |= (op & 0x10); |
| 10099 | // op: lane |
| 10100 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 10101 | Value |= (op & 0x7) << 5; |
| 10102 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10103 | break; |
| 10104 | } |
| 10105 | case ARM::VST1d16: |
| 10106 | case ARM::VST1d16T: |
| 10107 | case ARM::VST1d32: |
| 10108 | case ARM::VST1d32T: |
| 10109 | case ARM::VST1d64: |
| 10110 | case ARM::VST1d64T: |
| 10111 | case ARM::VST1d8: |
| 10112 | case ARM::VST1d8T: |
| 10113 | case ARM::VST3d16: |
| 10114 | case ARM::VST3d32: |
| 10115 | case ARM::VST3d8: |
| 10116 | case ARM::VST3q16: |
| 10117 | case ARM::VST3q32: |
| 10118 | case ARM::VST3q8: { |
| 10119 | // op: Vd |
| 10120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10121 | Value |= (op & 0x10) << 18; |
| 10122 | Value |= (op & 0xf) << 12; |
| 10123 | // op: Rn |
| 10124 | op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI); |
| 10125 | Value |= (op & 0xf) << 16; |
| 10126 | Value |= (op & 0x10); |
| 10127 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10128 | break; |
| 10129 | } |
| 10130 | case ARM::VST4LNd32: |
| 10131 | case ARM::VST4LNq32: { |
| 10132 | // op: Vd |
| 10133 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10134 | Value |= (op & 0x10) << 18; |
| 10135 | Value |= (op & 0xf) << 12; |
| 10136 | // op: Rn |
| 10137 | op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI); |
| 10138 | Value |= (op & 0xf) << 16; |
| 10139 | Value |= (op & 0x30); |
| 10140 | // op: lane |
| 10141 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 10142 | Value |= (op & 0x1) << 7; |
| 10143 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10144 | break; |
| 10145 | } |
| 10146 | case ARM::VST1d16Q: |
| 10147 | case ARM::VST1d32Q: |
| 10148 | case ARM::VST1d64Q: |
| 10149 | case ARM::VST1d8Q: |
| 10150 | case ARM::VST1q16: |
| 10151 | case ARM::VST1q32: |
| 10152 | case ARM::VST1q64: |
| 10153 | case ARM::VST1q8: |
| 10154 | case ARM::VST2b16: |
| 10155 | case ARM::VST2b32: |
| 10156 | case ARM::VST2b8: |
| 10157 | case ARM::VST2d16: |
| 10158 | case ARM::VST2d32: |
| 10159 | case ARM::VST2d8: |
| 10160 | case ARM::VST2q16: |
| 10161 | case ARM::VST2q32: |
| 10162 | case ARM::VST2q8: |
| 10163 | case ARM::VST4d16: |
| 10164 | case ARM::VST4d32: |
| 10165 | case ARM::VST4d8: |
| 10166 | case ARM::VST4q16: |
| 10167 | case ARM::VST4q32: |
| 10168 | case ARM::VST4q8: { |
| 10169 | // op: Vd |
| 10170 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10171 | Value |= (op & 0x10) << 18; |
| 10172 | Value |= (op & 0xf) << 12; |
| 10173 | // op: Rn |
| 10174 | op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI); |
| 10175 | Value |= (op & 0xf) << 16; |
| 10176 | Value |= (op & 0x30); |
| 10177 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10178 | break; |
| 10179 | } |
| 10180 | case ARM::VST1LNd32: { |
| 10181 | // op: Vd |
| 10182 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10183 | Value |= (op & 0x10) << 18; |
| 10184 | Value |= (op & 0xf) << 12; |
| 10185 | // op: Rn |
| 10186 | op = getAddrMode6OneLane32AddressOpValue(MI, Op: 0, Fixups, STI); |
| 10187 | Value |= (op & 0xf) << 16; |
| 10188 | Value |= (op & 0x30); |
| 10189 | // op: lane |
| 10190 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10191 | Value |= (op & 0x1) << 7; |
| 10192 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10193 | break; |
| 10194 | } |
| 10195 | case ARM::VST1d16wb_fixed: |
| 10196 | case ARM::VST1d32wb_fixed: |
| 10197 | case ARM::VST1d64wb_fixed: |
| 10198 | case ARM::VST1d8wb_fixed: { |
| 10199 | // op: Vd |
| 10200 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10201 | Value |= (op & 0x10) << 18; |
| 10202 | Value |= (op & 0xf) << 12; |
| 10203 | // op: Rn |
| 10204 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10205 | Value |= (op & 0xf) << 16; |
| 10206 | Value |= (op & 0x10); |
| 10207 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10208 | break; |
| 10209 | } |
| 10210 | case ARM::VST1d16Qwb_fixed: |
| 10211 | case ARM::VST1d16Twb_fixed: |
| 10212 | case ARM::VST1d32Qwb_fixed: |
| 10213 | case ARM::VST1d32Twb_fixed: |
| 10214 | case ARM::VST1d64Qwb_fixed: |
| 10215 | case ARM::VST1d64Twb_fixed: |
| 10216 | case ARM::VST1d8Qwb_fixed: |
| 10217 | case ARM::VST1d8Twb_fixed: |
| 10218 | case ARM::VST1q16wb_fixed: |
| 10219 | case ARM::VST1q32wb_fixed: |
| 10220 | case ARM::VST1q64wb_fixed: |
| 10221 | case ARM::VST1q8wb_fixed: |
| 10222 | case ARM::VST2b16wb_fixed: |
| 10223 | case ARM::VST2b32wb_fixed: |
| 10224 | case ARM::VST2b8wb_fixed: |
| 10225 | case ARM::VST2d16wb_fixed: |
| 10226 | case ARM::VST2d32wb_fixed: |
| 10227 | case ARM::VST2d8wb_fixed: |
| 10228 | case ARM::VST2q16wb_fixed: |
| 10229 | case ARM::VST2q32wb_fixed: |
| 10230 | case ARM::VST2q8wb_fixed: { |
| 10231 | // op: Vd |
| 10232 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10233 | Value |= (op & 0x10) << 18; |
| 10234 | Value |= (op & 0xf) << 12; |
| 10235 | // op: Rn |
| 10236 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10237 | Value |= (op & 0xf) << 16; |
| 10238 | Value |= (op & 0x30); |
| 10239 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10240 | break; |
| 10241 | } |
| 10242 | case ARM::VST1LNd8_UPD: { |
| 10243 | // op: Vd |
| 10244 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10245 | Value |= (op & 0x10) << 18; |
| 10246 | Value |= (op & 0xf) << 12; |
| 10247 | // op: Rn |
| 10248 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10249 | Value |= (op & 0xf) << 16; |
| 10250 | // op: Rm |
| 10251 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10252 | Value |= (op & 0xf); |
| 10253 | // op: lane |
| 10254 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 10255 | Value |= (op & 0x7) << 5; |
| 10256 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10257 | break; |
| 10258 | } |
| 10259 | case ARM::VST3LNd32_UPD: |
| 10260 | case ARM::VST3LNq32_UPD: { |
| 10261 | // op: Vd |
| 10262 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10263 | Value |= (op & 0x10) << 18; |
| 10264 | Value |= (op & 0xf) << 12; |
| 10265 | // op: Rn |
| 10266 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10267 | Value |= (op & 0xf) << 16; |
| 10268 | // op: Rm |
| 10269 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10270 | Value |= (op & 0xf); |
| 10271 | // op: lane |
| 10272 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 7), Fixups, STI); |
| 10273 | Value |= (op & 0x1) << 7; |
| 10274 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10275 | break; |
| 10276 | } |
| 10277 | case ARM::VST3LNd16_UPD: |
| 10278 | case ARM::VST3LNq16_UPD: { |
| 10279 | // op: Vd |
| 10280 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10281 | Value |= (op & 0x10) << 18; |
| 10282 | Value |= (op & 0xf) << 12; |
| 10283 | // op: Rn |
| 10284 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10285 | Value |= (op & 0xf) << 16; |
| 10286 | // op: Rm |
| 10287 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10288 | Value |= (op & 0xf); |
| 10289 | // op: lane |
| 10290 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 7), Fixups, STI); |
| 10291 | Value |= (op & 0x3) << 6; |
| 10292 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10293 | break; |
| 10294 | } |
| 10295 | case ARM::VST3LNd8_UPD: { |
| 10296 | // op: Vd |
| 10297 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10298 | Value |= (op & 0x10) << 18; |
| 10299 | Value |= (op & 0xf) << 12; |
| 10300 | // op: Rn |
| 10301 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10302 | Value |= (op & 0xf) << 16; |
| 10303 | // op: Rm |
| 10304 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10305 | Value |= (op & 0xf); |
| 10306 | // op: lane |
| 10307 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 7), Fixups, STI); |
| 10308 | Value |= (op & 0x7) << 5; |
| 10309 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10310 | break; |
| 10311 | } |
| 10312 | case ARM::VST1LNd16_UPD: { |
| 10313 | // op: Vd |
| 10314 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10315 | Value |= (op & 0x10) << 18; |
| 10316 | Value |= (op & 0xf) << 12; |
| 10317 | // op: Rn |
| 10318 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10319 | Value |= (op & 0xf) << 16; |
| 10320 | Value |= (op & 0x10); |
| 10321 | // op: Rm |
| 10322 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10323 | Value |= (op & 0xf); |
| 10324 | // op: lane |
| 10325 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 10326 | Value |= (op & 0x3) << 6; |
| 10327 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10328 | break; |
| 10329 | } |
| 10330 | case ARM::VST2LNd32_UPD: |
| 10331 | case ARM::VST2LNq32_UPD: { |
| 10332 | // op: Vd |
| 10333 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10334 | Value |= (op & 0x10) << 18; |
| 10335 | Value |= (op & 0xf) << 12; |
| 10336 | // op: Rn |
| 10337 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10338 | Value |= (op & 0xf) << 16; |
| 10339 | Value |= (op & 0x10); |
| 10340 | // op: Rm |
| 10341 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10342 | Value |= (op & 0xf); |
| 10343 | // op: lane |
| 10344 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 10345 | Value |= (op & 0x1) << 7; |
| 10346 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10347 | break; |
| 10348 | } |
| 10349 | case ARM::VST2LNd16_UPD: |
| 10350 | case ARM::VST2LNq16_UPD: { |
| 10351 | // op: Vd |
| 10352 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10353 | Value |= (op & 0x10) << 18; |
| 10354 | Value |= (op & 0xf) << 12; |
| 10355 | // op: Rn |
| 10356 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10357 | Value |= (op & 0xf) << 16; |
| 10358 | Value |= (op & 0x10); |
| 10359 | // op: Rm |
| 10360 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10361 | Value |= (op & 0xf); |
| 10362 | // op: lane |
| 10363 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 10364 | Value |= (op & 0x3) << 6; |
| 10365 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10366 | break; |
| 10367 | } |
| 10368 | case ARM::VST2LNd8_UPD: { |
| 10369 | // op: Vd |
| 10370 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10371 | Value |= (op & 0x10) << 18; |
| 10372 | Value |= (op & 0xf) << 12; |
| 10373 | // op: Rn |
| 10374 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10375 | Value |= (op & 0xf) << 16; |
| 10376 | Value |= (op & 0x10); |
| 10377 | // op: Rm |
| 10378 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10379 | Value |= (op & 0xf); |
| 10380 | // op: lane |
| 10381 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 10382 | Value |= (op & 0x7) << 5; |
| 10383 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10384 | break; |
| 10385 | } |
| 10386 | case ARM::VST4LNd16_UPD: |
| 10387 | case ARM::VST4LNq16_UPD: { |
| 10388 | // op: Vd |
| 10389 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10390 | Value |= (op & 0x10) << 18; |
| 10391 | Value |= (op & 0xf) << 12; |
| 10392 | // op: Rn |
| 10393 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10394 | Value |= (op & 0xf) << 16; |
| 10395 | Value |= (op & 0x10); |
| 10396 | // op: Rm |
| 10397 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10398 | Value |= (op & 0xf); |
| 10399 | // op: lane |
| 10400 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI); |
| 10401 | Value |= (op & 0x3) << 6; |
| 10402 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10403 | break; |
| 10404 | } |
| 10405 | case ARM::VST4LNd8_UPD: { |
| 10406 | // op: Vd |
| 10407 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10408 | Value |= (op & 0x10) << 18; |
| 10409 | Value |= (op & 0xf) << 12; |
| 10410 | // op: Rn |
| 10411 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10412 | Value |= (op & 0xf) << 16; |
| 10413 | Value |= (op & 0x10); |
| 10414 | // op: Rm |
| 10415 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10416 | Value |= (op & 0xf); |
| 10417 | // op: lane |
| 10418 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI); |
| 10419 | Value |= (op & 0x7) << 5; |
| 10420 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10421 | break; |
| 10422 | } |
| 10423 | case ARM::VST3d16_UPD: |
| 10424 | case ARM::VST3d32_UPD: |
| 10425 | case ARM::VST3d8_UPD: |
| 10426 | case ARM::VST3q16_UPD: |
| 10427 | case ARM::VST3q32_UPD: |
| 10428 | case ARM::VST3q8_UPD: { |
| 10429 | // op: Vd |
| 10430 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10431 | Value |= (op & 0x10) << 18; |
| 10432 | Value |= (op & 0xf) << 12; |
| 10433 | // op: Rn |
| 10434 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10435 | Value |= (op & 0xf) << 16; |
| 10436 | Value |= (op & 0x10); |
| 10437 | // op: Rm |
| 10438 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10439 | Value |= (op & 0xf); |
| 10440 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10441 | break; |
| 10442 | } |
| 10443 | case ARM::VST1d16wb_register: |
| 10444 | case ARM::VST1d32wb_register: |
| 10445 | case ARM::VST1d64wb_register: |
| 10446 | case ARM::VST1d8wb_register: { |
| 10447 | // op: Vd |
| 10448 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10449 | Value |= (op & 0x10) << 18; |
| 10450 | Value |= (op & 0xf) << 12; |
| 10451 | // op: Rn |
| 10452 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10453 | Value |= (op & 0xf) << 16; |
| 10454 | Value |= (op & 0x10); |
| 10455 | // op: Rm |
| 10456 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10457 | Value |= (op & 0xf); |
| 10458 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10459 | break; |
| 10460 | } |
| 10461 | case ARM::VST4LNd32_UPD: |
| 10462 | case ARM::VST4LNq32_UPD: { |
| 10463 | // op: Vd |
| 10464 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10465 | Value |= (op & 0x10) << 18; |
| 10466 | Value |= (op & 0xf) << 12; |
| 10467 | // op: Rn |
| 10468 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10469 | Value |= (op & 0xf) << 16; |
| 10470 | Value |= (op & 0x30); |
| 10471 | // op: Rm |
| 10472 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10473 | Value |= (op & 0xf); |
| 10474 | // op: lane |
| 10475 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI); |
| 10476 | Value |= (op & 0x1) << 7; |
| 10477 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10478 | break; |
| 10479 | } |
| 10480 | case ARM::VST4d16_UPD: |
| 10481 | case ARM::VST4d32_UPD: |
| 10482 | case ARM::VST4d8_UPD: |
| 10483 | case ARM::VST4q16_UPD: |
| 10484 | case ARM::VST4q32_UPD: |
| 10485 | case ARM::VST4q8_UPD: { |
| 10486 | // op: Vd |
| 10487 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10488 | Value |= (op & 0x10) << 18; |
| 10489 | Value |= (op & 0xf) << 12; |
| 10490 | // op: Rn |
| 10491 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10492 | Value |= (op & 0xf) << 16; |
| 10493 | Value |= (op & 0x30); |
| 10494 | // op: Rm |
| 10495 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10496 | Value |= (op & 0xf); |
| 10497 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10498 | break; |
| 10499 | } |
| 10500 | case ARM::VST1d16Qwb_register: |
| 10501 | case ARM::VST1d16Twb_register: |
| 10502 | case ARM::VST1d32Qwb_register: |
| 10503 | case ARM::VST1d32Twb_register: |
| 10504 | case ARM::VST1d64Qwb_register: |
| 10505 | case ARM::VST1d64Twb_register: |
| 10506 | case ARM::VST1d8Qwb_register: |
| 10507 | case ARM::VST1d8Twb_register: |
| 10508 | case ARM::VST1q16wb_register: |
| 10509 | case ARM::VST1q32wb_register: |
| 10510 | case ARM::VST1q64wb_register: |
| 10511 | case ARM::VST1q8wb_register: |
| 10512 | case ARM::VST2b16wb_register: |
| 10513 | case ARM::VST2b32wb_register: |
| 10514 | case ARM::VST2b8wb_register: |
| 10515 | case ARM::VST2d16wb_register: |
| 10516 | case ARM::VST2d32wb_register: |
| 10517 | case ARM::VST2d8wb_register: |
| 10518 | case ARM::VST2q16wb_register: |
| 10519 | case ARM::VST2q32wb_register: |
| 10520 | case ARM::VST2q8wb_register: { |
| 10521 | // op: Vd |
| 10522 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10523 | Value |= (op & 0x10) << 18; |
| 10524 | Value |= (op & 0xf) << 12; |
| 10525 | // op: Rn |
| 10526 | op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10527 | Value |= (op & 0xf) << 16; |
| 10528 | Value |= (op & 0x30); |
| 10529 | // op: Rm |
| 10530 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10531 | Value |= (op & 0xf); |
| 10532 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10533 | break; |
| 10534 | } |
| 10535 | case ARM::VST1LNd32_UPD: { |
| 10536 | // op: Vd |
| 10537 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10538 | Value |= (op & 0x10) << 18; |
| 10539 | Value |= (op & 0xf) << 12; |
| 10540 | // op: Rn |
| 10541 | op = getAddrMode6OneLane32AddressOpValue(MI, Op: 1, Fixups, STI); |
| 10542 | Value |= (op & 0xf) << 16; |
| 10543 | Value |= (op & 0x30); |
| 10544 | // op: Rm |
| 10545 | op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI); |
| 10546 | Value |= (op & 0xf); |
| 10547 | // op: lane |
| 10548 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 10549 | Value |= (op & 0x1) << 7; |
| 10550 | Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI); |
| 10551 | break; |
| 10552 | } |
| 10553 | case ARM::LDC2L_OFFSET: |
| 10554 | case ARM::LDC2L_PRE: |
| 10555 | case ARM::LDC2_OFFSET: |
| 10556 | case ARM::LDC2_PRE: |
| 10557 | case ARM::STC2L_OFFSET: |
| 10558 | case ARM::STC2L_PRE: |
| 10559 | case ARM::STC2_OFFSET: |
| 10560 | case ARM::STC2_PRE: |
| 10561 | case ARM::t2LDC2L_OFFSET: |
| 10562 | case ARM::t2LDC2L_PRE: |
| 10563 | case ARM::t2LDC2_OFFSET: |
| 10564 | case ARM::t2LDC2_PRE: |
| 10565 | case ARM::t2LDCL_OFFSET: |
| 10566 | case ARM::t2LDCL_PRE: |
| 10567 | case ARM::t2LDC_OFFSET: |
| 10568 | case ARM::t2LDC_PRE: |
| 10569 | case ARM::t2STC2L_OFFSET: |
| 10570 | case ARM::t2STC2L_PRE: |
| 10571 | case ARM::t2STC2_OFFSET: |
| 10572 | case ARM::t2STC2_PRE: |
| 10573 | case ARM::t2STCL_OFFSET: |
| 10574 | case ARM::t2STCL_PRE: |
| 10575 | case ARM::t2STC_OFFSET: |
| 10576 | case ARM::t2STC_PRE: { |
| 10577 | // op: addr |
| 10578 | op = getAddrMode5OpValue(MI, OpIdx: 2, Fixups, STI); |
| 10579 | Value |= (op & 0x100) << 15; |
| 10580 | Value |= (op & 0x1e00) << 7; |
| 10581 | Value |= (op & 0xff); |
| 10582 | // op: cop |
| 10583 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10584 | Value |= (op & 0xf) << 8; |
| 10585 | // op: CRd |
| 10586 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10587 | Value |= (op & 0xf) << 12; |
| 10588 | break; |
| 10589 | } |
| 10590 | case ARM::PLDWi12: |
| 10591 | case ARM::PLDi12: |
| 10592 | case ARM::PLIi12: { |
| 10593 | // op: addr |
| 10594 | op = getAddrModeImm12OpValue(MI, OpIdx: 0, Fixups, STI); |
| 10595 | Value |= (op & 0x1000) << 11; |
| 10596 | Value |= (op & 0x1e000) << 3; |
| 10597 | Value |= (op & 0xfff); |
| 10598 | break; |
| 10599 | } |
| 10600 | case ARM::t2PLDpci: |
| 10601 | case ARM::t2PLIpci: { |
| 10602 | // op: addr |
| 10603 | op = getAddrModeImm12OpValue(MI, OpIdx: 0, Fixups, STI); |
| 10604 | Value |= (op & 0x1000) << 11; |
| 10605 | Value |= (op & 0xfff); |
| 10606 | break; |
| 10607 | } |
| 10608 | case ARM::t2PLDWi12: |
| 10609 | case ARM::t2PLDi12: |
| 10610 | case ARM::t2PLIi12: { |
| 10611 | // op: addr |
| 10612 | op = getAddrModeImm12OpValue(MI, OpIdx: 0, Fixups, STI); |
| 10613 | Value |= (op & 0x1e000) << 3; |
| 10614 | Value |= (op & 0xfff); |
| 10615 | break; |
| 10616 | } |
| 10617 | case ARM::t2LDAEXB: |
| 10618 | case ARM::t2LDAEXH: |
| 10619 | case ARM::t2LDREXB: |
| 10620 | case ARM::t2LDREXH: { |
| 10621 | // op: addr |
| 10622 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10623 | Value |= (op & 0xf) << 16; |
| 10624 | // op: Rt |
| 10625 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10626 | Value |= (op & 0xf) << 12; |
| 10627 | break; |
| 10628 | } |
| 10629 | case ARM::t2LDAEXD: |
| 10630 | case ARM::t2LDREXD: { |
| 10631 | // op: addr |
| 10632 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10633 | Value |= (op & 0xf) << 16; |
| 10634 | // op: Rt |
| 10635 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10636 | Value |= (op & 0xf) << 12; |
| 10637 | // op: Rt2 |
| 10638 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10639 | Value |= (op & 0xf) << 8; |
| 10640 | break; |
| 10641 | } |
| 10642 | case ARM::t2PLDWi8: |
| 10643 | case ARM::t2PLDi8: |
| 10644 | case ARM::t2PLIi8: { |
| 10645 | // op: addr |
| 10646 | op = getT2AddrModeImmOpValue<8,0>(MI, OpNum: 0, Fixups, STI); |
| 10647 | Value |= (op & 0x1e00) << 7; |
| 10648 | Value |= (op & 0xff); |
| 10649 | break; |
| 10650 | } |
| 10651 | case ARM::t2PLDWs: |
| 10652 | case ARM::t2PLDs: |
| 10653 | case ARM::t2PLIs: { |
| 10654 | // op: addr |
| 10655 | op = getT2AddrModeSORegOpValue(MI, OpNum: 0, Fixups, STI); |
| 10656 | Value |= (op & 0x3c0) << 10; |
| 10657 | Value |= (op & 0x3) << 4; |
| 10658 | Value |= (op & 0x3c) >> 2; |
| 10659 | break; |
| 10660 | } |
| 10661 | case ARM::t2BFLr: |
| 10662 | case ARM::t2BFr: { |
| 10663 | // op: b_label |
| 10664 | op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, OpIdx: 0, Fixups, STI); |
| 10665 | Value |= (op & 0xf) << 23; |
| 10666 | // op: Rn |
| 10667 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10668 | Value |= (op & 0xf) << 16; |
| 10669 | break; |
| 10670 | } |
| 10671 | case ARM::t2BFi: { |
| 10672 | // op: b_label |
| 10673 | op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, OpIdx: 0, Fixups, STI); |
| 10674 | Value |= (op & 0xf) << 23; |
| 10675 | // op: label |
| 10676 | op = getBFTargetOpValue<false, ARM::fixup_bf_target>(MI, OpIdx: 1, Fixups, STI); |
| 10677 | Value |= (op & 0xf800) << 5; |
| 10678 | Value |= (op & 0x1) << 11; |
| 10679 | Value |= (op & 0x7fe); |
| 10680 | break; |
| 10681 | } |
| 10682 | case ARM::t2BFLi: { |
| 10683 | // op: b_label |
| 10684 | op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, OpIdx: 0, Fixups, STI); |
| 10685 | Value |= (op & 0xf) << 23; |
| 10686 | // op: label |
| 10687 | op = getBFTargetOpValue<false, ARM::fixup_bfl_target>(MI, OpIdx: 1, Fixups, STI); |
| 10688 | Value |= (op & 0x3f800) << 5; |
| 10689 | Value |= (op & 0x1) << 11; |
| 10690 | Value |= (op & 0x7fe); |
| 10691 | break; |
| 10692 | } |
| 10693 | case ARM::t2MSRbanked: { |
| 10694 | // op: banked |
| 10695 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10696 | Value |= (op & 0x20) << 15; |
| 10697 | Value |= (op & 0xf) << 8; |
| 10698 | Value |= (op & 0x10); |
| 10699 | // op: Rn |
| 10700 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10701 | Value |= (op & 0xf) << 16; |
| 10702 | break; |
| 10703 | } |
| 10704 | case ARM::t2MRSbanked: { |
| 10705 | // op: banked |
| 10706 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10707 | Value |= (op & 0x20) << 15; |
| 10708 | Value |= (op & 0xf) << 16; |
| 10709 | Value |= (op & 0x10); |
| 10710 | // op: Rd |
| 10711 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10712 | Value |= (op & 0xf) << 8; |
| 10713 | break; |
| 10714 | } |
| 10715 | case ARM::t2BFic: { |
| 10716 | // op: bcond |
| 10717 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10718 | Value |= (op & 0xf) << 18; |
| 10719 | // op: label |
| 10720 | op = getBFTargetOpValue<false, ARM::fixup_bfc_target>(MI, OpIdx: 1, Fixups, STI); |
| 10721 | Value |= (op & 0x800) << 5; |
| 10722 | Value |= (op & 0x1) << 11; |
| 10723 | Value |= (op & 0x7fe); |
| 10724 | // op: ba_label |
| 10725 | op = getBFAfterTargetOpValue(MI, OpIdx: 2, Fixups, STI); |
| 10726 | Value |= (op & 0x1) << 17; |
| 10727 | // op: b_label |
| 10728 | op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, OpIdx: 0, Fixups, STI); |
| 10729 | Value |= (op & 0xf) << 23; |
| 10730 | break; |
| 10731 | } |
| 10732 | case ARM::t2IT: { |
| 10733 | // op: cc |
| 10734 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10735 | Value |= (op & 0xf) << 4; |
| 10736 | // op: mask |
| 10737 | op = getITMaskOpValue(MI, OpIdx: 1, Fixups, STI); |
| 10738 | Value |= (op & 0xf); |
| 10739 | break; |
| 10740 | } |
| 10741 | case ARM::CDE_CX1: |
| 10742 | case ARM::CDE_CX1D: { |
| 10743 | // op: coproc |
| 10744 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10745 | Value |= (op & 0x7) << 8; |
| 10746 | // op: imm |
| 10747 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10748 | Value |= (op & 0x1f80) << 9; |
| 10749 | Value |= (op & 0x40) << 1; |
| 10750 | Value |= (op & 0x3f); |
| 10751 | // op: Rd |
| 10752 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10753 | Value |= (op & 0xf) << 12; |
| 10754 | break; |
| 10755 | } |
| 10756 | case ARM::CDE_VCX1_fpsp: { |
| 10757 | // op: coproc |
| 10758 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10759 | Value |= (op & 0x7) << 8; |
| 10760 | // op: imm |
| 10761 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10762 | Value |= (op & 0x780) << 9; |
| 10763 | Value |= (op & 0x40) << 1; |
| 10764 | Value |= (op & 0x3f); |
| 10765 | // op: Vd |
| 10766 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10767 | Value |= (op & 0x1) << 22; |
| 10768 | Value |= (op & 0x1e) << 11; |
| 10769 | break; |
| 10770 | } |
| 10771 | case ARM::CDE_VCX1_fpdp: { |
| 10772 | // op: coproc |
| 10773 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10774 | Value |= (op & 0x7) << 8; |
| 10775 | // op: imm |
| 10776 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10777 | Value |= (op & 0x780) << 9; |
| 10778 | Value |= (op & 0x40) << 1; |
| 10779 | Value |= (op & 0x3f); |
| 10780 | // op: Vd |
| 10781 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10782 | Value |= (op & 0x10) << 18; |
| 10783 | Value |= (op & 0xf) << 12; |
| 10784 | break; |
| 10785 | } |
| 10786 | case ARM::CDE_VCX1_vec: { |
| 10787 | // op: coproc |
| 10788 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10789 | Value |= (op & 0x7) << 8; |
| 10790 | // op: imm |
| 10791 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10792 | Value |= (op & 0x800) << 13; |
| 10793 | Value |= (op & 0x780) << 9; |
| 10794 | Value |= (op & 0x40) << 1; |
| 10795 | Value |= (op & 0x3f); |
| 10796 | // op: Qd |
| 10797 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10798 | Value |= (op & 0x7) << 13; |
| 10799 | break; |
| 10800 | } |
| 10801 | case ARM::CDE_CX2: |
| 10802 | case ARM::CDE_CX2D: { |
| 10803 | // op: coproc |
| 10804 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10805 | Value |= (op & 0x7) << 8; |
| 10806 | // op: imm |
| 10807 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10808 | Value |= (op & 0x180) << 13; |
| 10809 | Value |= (op & 0x40) << 1; |
| 10810 | Value |= (op & 0x3f); |
| 10811 | // op: Rd |
| 10812 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10813 | Value |= (op & 0xf) << 12; |
| 10814 | // op: Rn |
| 10815 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10816 | Value |= (op & 0xf) << 16; |
| 10817 | break; |
| 10818 | } |
| 10819 | case ARM::CDE_CX1A: |
| 10820 | case ARM::CDE_CX1DA: { |
| 10821 | // op: coproc |
| 10822 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10823 | Value |= (op & 0x7) << 8; |
| 10824 | // op: imm |
| 10825 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10826 | Value |= (op & 0x1f80) << 9; |
| 10827 | Value |= (op & 0x40) << 1; |
| 10828 | Value |= (op & 0x3f); |
| 10829 | // op: Rd |
| 10830 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10831 | Value |= (op & 0xf) << 12; |
| 10832 | break; |
| 10833 | } |
| 10834 | case ARM::CDE_VCX2_fpsp: { |
| 10835 | // op: coproc |
| 10836 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10837 | Value |= (op & 0x7) << 8; |
| 10838 | // op: imm |
| 10839 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10840 | Value |= (op & 0x3c) << 14; |
| 10841 | Value |= (op & 0x2) << 6; |
| 10842 | Value |= (op & 0x1) << 4; |
| 10843 | // op: Vd |
| 10844 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10845 | Value |= (op & 0x1) << 22; |
| 10846 | Value |= (op & 0x1e) << 11; |
| 10847 | // op: Vm |
| 10848 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10849 | Value |= (op & 0x1) << 5; |
| 10850 | Value |= (op & 0x1e) >> 1; |
| 10851 | break; |
| 10852 | } |
| 10853 | case ARM::CDE_VCX2_fpdp: { |
| 10854 | // op: coproc |
| 10855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10856 | Value |= (op & 0x7) << 8; |
| 10857 | // op: imm |
| 10858 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10859 | Value |= (op & 0x3c) << 14; |
| 10860 | Value |= (op & 0x2) << 6; |
| 10861 | Value |= (op & 0x1) << 4; |
| 10862 | // op: Vd |
| 10863 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10864 | Value |= (op & 0x10) << 18; |
| 10865 | Value |= (op & 0xf) << 12; |
| 10866 | // op: Vm |
| 10867 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10868 | Value |= (op & 0x10) << 1; |
| 10869 | Value |= (op & 0xf); |
| 10870 | break; |
| 10871 | } |
| 10872 | case ARM::CDE_VCX2_vec: { |
| 10873 | // op: coproc |
| 10874 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10875 | Value |= (op & 0x7) << 8; |
| 10876 | // op: imm |
| 10877 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10878 | Value |= (op & 0x40) << 18; |
| 10879 | Value |= (op & 0x3c) << 14; |
| 10880 | Value |= (op & 0x2) << 6; |
| 10881 | Value |= (op & 0x1) << 4; |
| 10882 | // op: Qd |
| 10883 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10884 | Value |= (op & 0x7) << 13; |
| 10885 | // op: Qm |
| 10886 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10887 | Value |= (op & 0x7) << 1; |
| 10888 | break; |
| 10889 | } |
| 10890 | case ARM::CDE_VCX1A_fpsp: { |
| 10891 | // op: coproc |
| 10892 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10893 | Value |= (op & 0x7) << 8; |
| 10894 | // op: imm |
| 10895 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10896 | Value |= (op & 0x780) << 9; |
| 10897 | Value |= (op & 0x40) << 1; |
| 10898 | Value |= (op & 0x3f); |
| 10899 | // op: Vd |
| 10900 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10901 | Value |= (op & 0x1) << 22; |
| 10902 | Value |= (op & 0x1e) << 11; |
| 10903 | break; |
| 10904 | } |
| 10905 | case ARM::CDE_VCX1A_fpdp: { |
| 10906 | // op: coproc |
| 10907 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10908 | Value |= (op & 0x7) << 8; |
| 10909 | // op: imm |
| 10910 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10911 | Value |= (op & 0x780) << 9; |
| 10912 | Value |= (op & 0x40) << 1; |
| 10913 | Value |= (op & 0x3f); |
| 10914 | // op: Vd |
| 10915 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10916 | Value |= (op & 0x10) << 18; |
| 10917 | Value |= (op & 0xf) << 12; |
| 10918 | break; |
| 10919 | } |
| 10920 | case ARM::CDE_VCX1A_vec: { |
| 10921 | // op: coproc |
| 10922 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10923 | Value |= (op & 0x7) << 8; |
| 10924 | // op: imm |
| 10925 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10926 | Value |= (op & 0x800) << 13; |
| 10927 | Value |= (op & 0x780) << 9; |
| 10928 | Value |= (op & 0x40) << 1; |
| 10929 | Value |= (op & 0x3f); |
| 10930 | // op: Qd |
| 10931 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10932 | Value |= (op & 0x7) << 13; |
| 10933 | break; |
| 10934 | } |
| 10935 | case ARM::CDE_CX2A: |
| 10936 | case ARM::CDE_CX2DA: { |
| 10937 | // op: coproc |
| 10938 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10939 | Value |= (op & 0x7) << 8; |
| 10940 | // op: imm |
| 10941 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10942 | Value |= (op & 0x180) << 13; |
| 10943 | Value |= (op & 0x40) << 1; |
| 10944 | Value |= (op & 0x3f); |
| 10945 | // op: Rd |
| 10946 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10947 | Value |= (op & 0xf) << 12; |
| 10948 | // op: Rn |
| 10949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10950 | Value |= (op & 0xf) << 16; |
| 10951 | break; |
| 10952 | } |
| 10953 | case ARM::CDE_CX3: |
| 10954 | case ARM::CDE_CX3D: { |
| 10955 | // op: coproc |
| 10956 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10957 | Value |= (op & 0x7) << 8; |
| 10958 | // op: imm |
| 10959 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10960 | Value |= (op & 0x38) << 17; |
| 10961 | Value |= (op & 0x4) << 5; |
| 10962 | Value |= (op & 0x3) << 4; |
| 10963 | // op: Rd |
| 10964 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10965 | Value |= (op & 0xf); |
| 10966 | // op: Rn |
| 10967 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10968 | Value |= (op & 0xf) << 16; |
| 10969 | // op: Rm |
| 10970 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10971 | Value |= (op & 0xf) << 12; |
| 10972 | break; |
| 10973 | } |
| 10974 | case ARM::CDE_VCX2A_fpsp: { |
| 10975 | // op: coproc |
| 10976 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10977 | Value |= (op & 0x7) << 8; |
| 10978 | // op: imm |
| 10979 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10980 | Value |= (op & 0x3c) << 14; |
| 10981 | Value |= (op & 0x2) << 6; |
| 10982 | Value |= (op & 0x1) << 4; |
| 10983 | // op: Vd |
| 10984 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10985 | Value |= (op & 0x1) << 22; |
| 10986 | Value |= (op & 0x1e) << 11; |
| 10987 | // op: Vm |
| 10988 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10989 | Value |= (op & 0x1) << 5; |
| 10990 | Value |= (op & 0x1e) >> 1; |
| 10991 | break; |
| 10992 | } |
| 10993 | case ARM::CDE_VCX2A_fpdp: { |
| 10994 | // op: coproc |
| 10995 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10996 | Value |= (op & 0x7) << 8; |
| 10997 | // op: imm |
| 10998 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10999 | Value |= (op & 0x3c) << 14; |
| 11000 | Value |= (op & 0x2) << 6; |
| 11001 | Value |= (op & 0x1) << 4; |
| 11002 | // op: Vd |
| 11003 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11004 | Value |= (op & 0x10) << 18; |
| 11005 | Value |= (op & 0xf) << 12; |
| 11006 | // op: Vm |
| 11007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11008 | Value |= (op & 0x10) << 1; |
| 11009 | Value |= (op & 0xf); |
| 11010 | break; |
| 11011 | } |
| 11012 | case ARM::CDE_VCX2A_vec: { |
| 11013 | // op: coproc |
| 11014 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11015 | Value |= (op & 0x7) << 8; |
| 11016 | // op: imm |
| 11017 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 11018 | Value |= (op & 0x40) << 18; |
| 11019 | Value |= (op & 0x3c) << 14; |
| 11020 | Value |= (op & 0x2) << 6; |
| 11021 | Value |= (op & 0x1) << 4; |
| 11022 | // op: Qd |
| 11023 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11024 | Value |= (op & 0x7) << 13; |
| 11025 | // op: Qm |
| 11026 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11027 | Value |= (op & 0x7) << 1; |
| 11028 | break; |
| 11029 | } |
| 11030 | case ARM::CDE_VCX3_fpsp: { |
| 11031 | // op: coproc |
| 11032 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11033 | Value |= (op & 0x7) << 8; |
| 11034 | // op: imm |
| 11035 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 11036 | Value |= (op & 0x6) << 19; |
| 11037 | Value |= (op & 0x1) << 4; |
| 11038 | // op: Vd |
| 11039 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11040 | Value |= (op & 0x1) << 22; |
| 11041 | Value |= (op & 0x1e) << 11; |
| 11042 | // op: Vm |
| 11043 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11044 | Value |= (op & 0x1) << 5; |
| 11045 | Value |= (op & 0x1e) >> 1; |
| 11046 | // op: Vn |
| 11047 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11048 | Value |= (op & 0x1e) << 15; |
| 11049 | Value |= (op & 0x1) << 7; |
| 11050 | break; |
| 11051 | } |
| 11052 | case ARM::CDE_VCX3_fpdp: { |
| 11053 | // op: coproc |
| 11054 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11055 | Value |= (op & 0x7) << 8; |
| 11056 | // op: imm |
| 11057 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 11058 | Value |= (op & 0x6) << 19; |
| 11059 | Value |= (op & 0x1) << 4; |
| 11060 | // op: Vd |
| 11061 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11062 | Value |= (op & 0x10) << 18; |
| 11063 | Value |= (op & 0xf) << 12; |
| 11064 | // op: Vm |
| 11065 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11066 | Value |= (op & 0x10) << 1; |
| 11067 | Value |= (op & 0xf); |
| 11068 | // op: Vn |
| 11069 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11070 | Value |= (op & 0xf) << 16; |
| 11071 | Value |= (op & 0x10) << 3; |
| 11072 | break; |
| 11073 | } |
| 11074 | case ARM::CDE_VCX3_vec: { |
| 11075 | // op: coproc |
| 11076 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11077 | Value |= (op & 0x7) << 8; |
| 11078 | // op: imm |
| 11079 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 11080 | Value |= (op & 0x8) << 21; |
| 11081 | Value |= (op & 0x6) << 19; |
| 11082 | Value |= (op & 0x1) << 4; |
| 11083 | // op: Qd |
| 11084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11085 | Value |= (op & 0x7) << 13; |
| 11086 | // op: Qm |
| 11087 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11088 | Value |= (op & 0x7) << 1; |
| 11089 | // op: Qn |
| 11090 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11091 | Value |= (op & 0x7) << 17; |
| 11092 | break; |
| 11093 | } |
| 11094 | case ARM::CDE_CX3A: |
| 11095 | case ARM::CDE_CX3DA: { |
| 11096 | // op: coproc |
| 11097 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11098 | Value |= (op & 0x7) << 8; |
| 11099 | // op: imm |
| 11100 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 11101 | Value |= (op & 0x38) << 17; |
| 11102 | Value |= (op & 0x4) << 5; |
| 11103 | Value |= (op & 0x3) << 4; |
| 11104 | // op: Rd |
| 11105 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11106 | Value |= (op & 0xf); |
| 11107 | // op: Rn |
| 11108 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11109 | Value |= (op & 0xf) << 16; |
| 11110 | // op: Rm |
| 11111 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 11112 | Value |= (op & 0xf) << 12; |
| 11113 | break; |
| 11114 | } |
| 11115 | case ARM::CDE_VCX3A_fpsp: { |
| 11116 | // op: coproc |
| 11117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11118 | Value |= (op & 0x7) << 8; |
| 11119 | // op: imm |
| 11120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 11121 | Value |= (op & 0x6) << 19; |
| 11122 | Value |= (op & 0x1) << 4; |
| 11123 | // op: Vd |
| 11124 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11125 | Value |= (op & 0x1) << 22; |
| 11126 | Value |= (op & 0x1e) << 11; |
| 11127 | // op: Vm |
| 11128 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 11129 | Value |= (op & 0x1) << 5; |
| 11130 | Value |= (op & 0x1e) >> 1; |
| 11131 | // op: Vn |
| 11132 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11133 | Value |= (op & 0x1e) << 15; |
| 11134 | Value |= (op & 0x1) << 7; |
| 11135 | break; |
| 11136 | } |
| 11137 | case ARM::CDE_VCX3A_fpdp: { |
| 11138 | // op: coproc |
| 11139 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11140 | Value |= (op & 0x7) << 8; |
| 11141 | // op: imm |
| 11142 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 11143 | Value |= (op & 0x6) << 19; |
| 11144 | Value |= (op & 0x1) << 4; |
| 11145 | // op: Vd |
| 11146 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11147 | Value |= (op & 0x10) << 18; |
| 11148 | Value |= (op & 0xf) << 12; |
| 11149 | // op: Vm |
| 11150 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 11151 | Value |= (op & 0x10) << 1; |
| 11152 | Value |= (op & 0xf); |
| 11153 | // op: Vn |
| 11154 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11155 | Value |= (op & 0xf) << 16; |
| 11156 | Value |= (op & 0x10) << 3; |
| 11157 | break; |
| 11158 | } |
| 11159 | case ARM::CDE_VCX3A_vec: { |
| 11160 | // op: coproc |
| 11161 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11162 | Value |= (op & 0x7) << 8; |
| 11163 | // op: imm |
| 11164 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 11165 | Value |= (op & 0x8) << 21; |
| 11166 | Value |= (op & 0x6) << 19; |
| 11167 | Value |= (op & 0x1) << 4; |
| 11168 | // op: Qd |
| 11169 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11170 | Value |= (op & 0x7) << 13; |
| 11171 | // op: Qm |
| 11172 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 11173 | Value |= (op & 0x7) << 1; |
| 11174 | // op: Qn |
| 11175 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11176 | Value |= (op & 0x7) << 17; |
| 11177 | break; |
| 11178 | } |
| 11179 | case ARM::tADDrSPi: { |
| 11180 | // op: dst |
| 11181 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11182 | Value |= (op & 0x7) << 8; |
| 11183 | // op: imm |
| 11184 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11185 | Value |= (op & 0xff); |
| 11186 | break; |
| 11187 | } |
| 11188 | case ARM::tPICADD: { |
| 11189 | // op: dst |
| 11190 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11191 | Value |= (op & 0x7); |
| 11192 | break; |
| 11193 | } |
| 11194 | case ARM::BX: { |
| 11195 | // op: dst |
| 11196 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11197 | Value |= (op & 0xf); |
| 11198 | break; |
| 11199 | } |
| 11200 | case ARM::tSETEND: { |
| 11201 | // op: end |
| 11202 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11203 | Value |= (op & 0x1) << 3; |
| 11204 | break; |
| 11205 | } |
| 11206 | case ARM::SETEND: { |
| 11207 | // op: end |
| 11208 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11209 | Value |= (op & 0x1) << 9; |
| 11210 | break; |
| 11211 | } |
| 11212 | case ARM::MVE_VPTv16i8: |
| 11213 | case ARM::MVE_VPTv16u8: |
| 11214 | case ARM::MVE_VPTv4i32: |
| 11215 | case ARM::MVE_VPTv4u32: |
| 11216 | case ARM::MVE_VPTv8i16: |
| 11217 | case ARM::MVE_VPTv8u16: { |
| 11218 | // op: fc |
| 11219 | op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI); |
| 11220 | Value |= (op & 0x1) << 7; |
| 11221 | // op: Mk |
| 11222 | op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI); |
| 11223 | Value |= (op & 0x8) << 19; |
| 11224 | Value |= (op & 0x7) << 13; |
| 11225 | // op: Qn |
| 11226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11227 | Value |= (op & 0x7) << 17; |
| 11228 | // op: Qm |
| 11229 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11230 | Value |= (op & 0x8) << 2; |
| 11231 | Value |= (op & 0x7) << 1; |
| 11232 | break; |
| 11233 | } |
| 11234 | case ARM::MVE_VPTv16i8r: |
| 11235 | case ARM::MVE_VPTv16u8r: |
| 11236 | case ARM::MVE_VPTv4i32r: |
| 11237 | case ARM::MVE_VPTv4u32r: |
| 11238 | case ARM::MVE_VPTv8i16r: |
| 11239 | case ARM::MVE_VPTv8u16r: { |
| 11240 | // op: fc |
| 11241 | op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI); |
| 11242 | Value |= (op & 0x1) << 7; |
| 11243 | // op: Mk |
| 11244 | op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI); |
| 11245 | Value |= (op & 0x8) << 19; |
| 11246 | Value |= (op & 0x7) << 13; |
| 11247 | // op: Qn |
| 11248 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11249 | Value |= (op & 0x7) << 17; |
| 11250 | // op: Rm |
| 11251 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11252 | Value |= (op & 0xf); |
| 11253 | break; |
| 11254 | } |
| 11255 | case ARM::MVE_VCMPi16: |
| 11256 | case ARM::MVE_VCMPi32: |
| 11257 | case ARM::MVE_VCMPi8: |
| 11258 | case ARM::MVE_VCMPu16: |
| 11259 | case ARM::MVE_VCMPu32: |
| 11260 | case ARM::MVE_VCMPu8: { |
| 11261 | // op: fc |
| 11262 | op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI); |
| 11263 | Value |= (op & 0x1) << 7; |
| 11264 | // op: Qn |
| 11265 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11266 | Value |= (op & 0x7) << 17; |
| 11267 | // op: Qm |
| 11268 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11269 | Value |= (op & 0x8) << 2; |
| 11270 | Value |= (op & 0x7) << 1; |
| 11271 | break; |
| 11272 | } |
| 11273 | case ARM::MVE_VCMPi16r: |
| 11274 | case ARM::MVE_VCMPi32r: |
| 11275 | case ARM::MVE_VCMPi8r: |
| 11276 | case ARM::MVE_VCMPu16r: |
| 11277 | case ARM::MVE_VCMPu32r: |
| 11278 | case ARM::MVE_VCMPu8r: { |
| 11279 | // op: fc |
| 11280 | op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI); |
| 11281 | Value |= (op & 0x1) << 7; |
| 11282 | // op: Qn |
| 11283 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11284 | Value |= (op & 0x7) << 17; |
| 11285 | // op: Rm |
| 11286 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11287 | Value |= (op & 0xf); |
| 11288 | break; |
| 11289 | } |
| 11290 | case ARM::MVE_VPTv16s8r: |
| 11291 | case ARM::MVE_VPTv4s32r: |
| 11292 | case ARM::MVE_VPTv8s16r: { |
| 11293 | // op: fc |
| 11294 | op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI); |
| 11295 | Value |= (op & 0x1) << 7; |
| 11296 | Value |= (op & 0x2) << 4; |
| 11297 | // op: Mk |
| 11298 | op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI); |
| 11299 | Value |= (op & 0x8) << 19; |
| 11300 | Value |= (op & 0x7) << 13; |
| 11301 | // op: Qn |
| 11302 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11303 | Value |= (op & 0x7) << 17; |
| 11304 | // op: Rm |
| 11305 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11306 | Value |= (op & 0xf); |
| 11307 | break; |
| 11308 | } |
| 11309 | case ARM::MVE_VCMPs16r: |
| 11310 | case ARM::MVE_VCMPs32r: |
| 11311 | case ARM::MVE_VCMPs8r: { |
| 11312 | // op: fc |
| 11313 | op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI); |
| 11314 | Value |= (op & 0x1) << 7; |
| 11315 | Value |= (op & 0x2) << 4; |
| 11316 | // op: Qn |
| 11317 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11318 | Value |= (op & 0x7) << 17; |
| 11319 | // op: Rm |
| 11320 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11321 | Value |= (op & 0xf); |
| 11322 | break; |
| 11323 | } |
| 11324 | case ARM::MVE_VPTv16s8: |
| 11325 | case ARM::MVE_VPTv4s32: |
| 11326 | case ARM::MVE_VPTv8s16: { |
| 11327 | // op: fc |
| 11328 | op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI); |
| 11329 | Value |= (op & 0x1) << 7; |
| 11330 | Value |= (op & 0x2) >> 1; |
| 11331 | // op: Mk |
| 11332 | op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI); |
| 11333 | Value |= (op & 0x8) << 19; |
| 11334 | Value |= (op & 0x7) << 13; |
| 11335 | // op: Qn |
| 11336 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11337 | Value |= (op & 0x7) << 17; |
| 11338 | // op: Qm |
| 11339 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11340 | Value |= (op & 0x8) << 2; |
| 11341 | Value |= (op & 0x7) << 1; |
| 11342 | break; |
| 11343 | } |
| 11344 | case ARM::MVE_VCMPs16: |
| 11345 | case ARM::MVE_VCMPs32: |
| 11346 | case ARM::MVE_VCMPs8: { |
| 11347 | // op: fc |
| 11348 | op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI); |
| 11349 | Value |= (op & 0x1) << 7; |
| 11350 | Value |= (op & 0x2) >> 1; |
| 11351 | // op: Qn |
| 11352 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11353 | Value |= (op & 0x7) << 17; |
| 11354 | // op: Qm |
| 11355 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11356 | Value |= (op & 0x8) << 2; |
| 11357 | Value |= (op & 0x7) << 1; |
| 11358 | break; |
| 11359 | } |
| 11360 | case ARM::MVE_VPTv4f32r: |
| 11361 | case ARM::MVE_VPTv8f16r: { |
| 11362 | // op: fc |
| 11363 | op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI); |
| 11364 | Value |= (op & 0x4) << 10; |
| 11365 | Value |= (op & 0x1) << 7; |
| 11366 | Value |= (op & 0x2) << 4; |
| 11367 | // op: Mk |
| 11368 | op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI); |
| 11369 | Value |= (op & 0x8) << 19; |
| 11370 | Value |= (op & 0x7) << 13; |
| 11371 | // op: Qn |
| 11372 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11373 | Value |= (op & 0x7) << 17; |
| 11374 | // op: Rm |
| 11375 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11376 | Value |= (op & 0xf); |
| 11377 | break; |
| 11378 | } |
| 11379 | case ARM::MVE_VCMPf16r: |
| 11380 | case ARM::MVE_VCMPf32r: { |
| 11381 | // op: fc |
| 11382 | op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI); |
| 11383 | Value |= (op & 0x4) << 10; |
| 11384 | Value |= (op & 0x1) << 7; |
| 11385 | Value |= (op & 0x2) << 4; |
| 11386 | // op: Qn |
| 11387 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11388 | Value |= (op & 0x7) << 17; |
| 11389 | // op: Rm |
| 11390 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11391 | Value |= (op & 0xf); |
| 11392 | break; |
| 11393 | } |
| 11394 | case ARM::MVE_VPTv4f32: |
| 11395 | case ARM::MVE_VPTv8f16: { |
| 11396 | // op: fc |
| 11397 | op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI); |
| 11398 | Value |= (op & 0x4) << 10; |
| 11399 | Value |= (op & 0x1) << 7; |
| 11400 | Value |= (op & 0x2) >> 1; |
| 11401 | // op: Mk |
| 11402 | op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI); |
| 11403 | Value |= (op & 0x8) << 19; |
| 11404 | Value |= (op & 0x7) << 13; |
| 11405 | // op: Qn |
| 11406 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11407 | Value |= (op & 0x7) << 17; |
| 11408 | // op: Qm |
| 11409 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11410 | Value |= (op & 0x8) << 2; |
| 11411 | Value |= (op & 0x7) << 1; |
| 11412 | break; |
| 11413 | } |
| 11414 | case ARM::MVE_VCMPf16: |
| 11415 | case ARM::MVE_VCMPf32: { |
| 11416 | // op: fc |
| 11417 | op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI); |
| 11418 | Value |= (op & 0x4) << 10; |
| 11419 | Value |= (op & 0x1) << 7; |
| 11420 | Value |= (op & 0x2) >> 1; |
| 11421 | // op: Qn |
| 11422 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11423 | Value |= (op & 0x7) << 17; |
| 11424 | // op: Qm |
| 11425 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11426 | Value |= (op & 0x8) << 2; |
| 11427 | Value |= (op & 0x7) << 1; |
| 11428 | break; |
| 11429 | } |
| 11430 | case ARM::BL: { |
| 11431 | // op: func |
| 11432 | op = getARMBLTargetOpValue(MI, OpIdx: 0, Fixups, STI); |
| 11433 | Value |= (op & 0xffffff); |
| 11434 | break; |
| 11435 | } |
| 11436 | case ARM::t2BXJ: { |
| 11437 | // op: func |
| 11438 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11439 | Value |= (op & 0xf) << 16; |
| 11440 | break; |
| 11441 | } |
| 11442 | case ARM::BLX: { |
| 11443 | // op: func |
| 11444 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11445 | Value |= (op & 0xf); |
| 11446 | break; |
| 11447 | } |
| 11448 | case ARM::tBLXNSr: |
| 11449 | case ARM::tBLXr: { |
| 11450 | // op: func |
| 11451 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11452 | Value |= (op & 0xf) << 3; |
| 11453 | break; |
| 11454 | } |
| 11455 | case ARM::tBL: { |
| 11456 | // op: func |
| 11457 | op = getThumbBLTargetOpValue(MI, OpIdx: 2, Fixups, STI); |
| 11458 | Value |= (op & 0x800000) << 3; |
| 11459 | Value |= (op & 0x1ff800) << 5; |
| 11460 | Value |= (op & 0x400000) >> 9; |
| 11461 | Value |= (op & 0x200000) >> 10; |
| 11462 | Value |= (op & 0x7ff); |
| 11463 | break; |
| 11464 | } |
| 11465 | case ARM::tBLXi: { |
| 11466 | // op: func |
| 11467 | op = getThumbBLXTargetOpValue(MI, OpIdx: 2, Fixups, STI); |
| 11468 | Value |= (op & 0x800000) << 3; |
| 11469 | Value |= (op & 0x1ff800) << 5; |
| 11470 | Value |= (op & 0x400000) >> 9; |
| 11471 | Value |= (op & 0x200000) >> 10; |
| 11472 | Value |= (op & 0x7fe); |
| 11473 | break; |
| 11474 | } |
| 11475 | case ARM::t2SETPAN: { |
| 11476 | // op: imm |
| 11477 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11478 | Value |= (op & 0x1) << 3; |
| 11479 | break; |
| 11480 | } |
| 11481 | case ARM::SETPAN: { |
| 11482 | // op: imm |
| 11483 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11484 | Value |= (op & 0x1) << 9; |
| 11485 | break; |
| 11486 | } |
| 11487 | case ARM::tHINT: { |
| 11488 | // op: imm |
| 11489 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11490 | Value |= (op & 0xf) << 4; |
| 11491 | break; |
| 11492 | } |
| 11493 | case ARM::t2HINT: |
| 11494 | case ARM::t2SUBS_PC_LR: |
| 11495 | case ARM::tSVC: { |
| 11496 | // op: imm |
| 11497 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11498 | Value |= (op & 0xff); |
| 11499 | break; |
| 11500 | } |
| 11501 | case ARM::HVC: { |
| 11502 | // op: imm |
| 11503 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11504 | Value |= (op & 0xfff0) << 4; |
| 11505 | Value |= (op & 0xf); |
| 11506 | break; |
| 11507 | } |
| 11508 | case ARM::MVE_VMOVimmi16: |
| 11509 | case ARM::MVE_VMVNimmi16: { |
| 11510 | // op: imm |
| 11511 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11512 | Value |= (op & 0x80) << 21; |
| 11513 | Value |= (op & 0x70) << 12; |
| 11514 | Value |= (op & 0x200); |
| 11515 | Value |= (op & 0xf); |
| 11516 | // op: Qd |
| 11517 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11518 | Value |= (op & 0x8) << 19; |
| 11519 | Value |= (op & 0x7) << 13; |
| 11520 | break; |
| 11521 | } |
| 11522 | case ARM::MVE_VMOVimmf32: |
| 11523 | case ARM::MVE_VMOVimmi64: |
| 11524 | case ARM::MVE_VMOVimmi8: { |
| 11525 | // op: imm |
| 11526 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11527 | Value |= (op & 0x80) << 21; |
| 11528 | Value |= (op & 0x70) << 12; |
| 11529 | Value |= (op & 0xf); |
| 11530 | // op: Qd |
| 11531 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11532 | Value |= (op & 0x8) << 19; |
| 11533 | Value |= (op & 0x7) << 13; |
| 11534 | break; |
| 11535 | } |
| 11536 | case ARM::MVE_VMOVimmi32: |
| 11537 | case ARM::MVE_VMVNimmi32: { |
| 11538 | // op: imm |
| 11539 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11540 | Value |= (op & 0x80) << 21; |
| 11541 | Value |= (op & 0x70) << 12; |
| 11542 | Value |= (op & 0xf00); |
| 11543 | Value |= (op & 0xf); |
| 11544 | // op: Qd |
| 11545 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11546 | Value |= (op & 0x8) << 19; |
| 11547 | Value |= (op & 0x7) << 13; |
| 11548 | break; |
| 11549 | } |
| 11550 | case ARM::tADDspi: |
| 11551 | case ARM::tSUBspi: { |
| 11552 | // op: imm |
| 11553 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11554 | Value |= (op & 0x7f); |
| 11555 | break; |
| 11556 | } |
| 11557 | case ARM::MVE_VBICimmi16: |
| 11558 | case ARM::MVE_VORRimmi16: { |
| 11559 | // op: imm |
| 11560 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11561 | Value |= (op & 0x80) << 21; |
| 11562 | Value |= (op & 0x70) << 12; |
| 11563 | Value |= (op & 0x200); |
| 11564 | Value |= (op & 0xf); |
| 11565 | // op: Qd |
| 11566 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11567 | Value |= (op & 0x8) << 19; |
| 11568 | Value |= (op & 0x7) << 13; |
| 11569 | break; |
| 11570 | } |
| 11571 | case ARM::MVE_VBICimmi32: |
| 11572 | case ARM::MVE_VORRimmi32: { |
| 11573 | // op: imm |
| 11574 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11575 | Value |= (op & 0x80) << 21; |
| 11576 | Value |= (op & 0x70) << 12; |
| 11577 | Value |= (op & 0x600); |
| 11578 | Value |= (op & 0xf); |
| 11579 | // op: Qd |
| 11580 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11581 | Value |= (op & 0x8) << 19; |
| 11582 | Value |= (op & 0x7) << 13; |
| 11583 | break; |
| 11584 | } |
| 11585 | case ARM::t2ADDspImm12: |
| 11586 | case ARM::t2SUBspImm12: { |
| 11587 | // op: imm |
| 11588 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11589 | Value |= (op & 0x800) << 15; |
| 11590 | Value |= (op & 0x700) << 4; |
| 11591 | Value |= (op & 0xff); |
| 11592 | break; |
| 11593 | } |
| 11594 | case ARM::MVE_VSHLC: { |
| 11595 | // op: imm |
| 11596 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 11597 | Value |= (op & 0x1f) << 16; |
| 11598 | // op: Qd |
| 11599 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11600 | Value |= (op & 0x8) << 19; |
| 11601 | Value |= (op & 0x7) << 13; |
| 11602 | // op: RdmDest |
| 11603 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11604 | Value |= (op & 0xf); |
| 11605 | break; |
| 11606 | } |
| 11607 | case ARM::t2HVC: |
| 11608 | case ARM::t2UDF: { |
| 11609 | // op: imm16 |
| 11610 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11611 | Value |= (op & 0xf000) << 4; |
| 11612 | Value |= (op & 0xfff); |
| 11613 | break; |
| 11614 | } |
| 11615 | case ARM::UDF: { |
| 11616 | // op: imm16 |
| 11617 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11618 | Value |= (op & 0xfff0) << 4; |
| 11619 | Value |= (op & 0xf); |
| 11620 | break; |
| 11621 | } |
| 11622 | case ARM::tUDF: { |
| 11623 | // op: imm8 |
| 11624 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11625 | Value |= (op & 0xff); |
| 11626 | break; |
| 11627 | } |
| 11628 | case ARM::tCPS: { |
| 11629 | // op: imod |
| 11630 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11631 | Value |= (op & 0x1) << 4; |
| 11632 | // op: iflags |
| 11633 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11634 | Value |= (op & 0x7); |
| 11635 | break; |
| 11636 | } |
| 11637 | case ARM::CPS2p: { |
| 11638 | // op: imod |
| 11639 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11640 | Value |= (op & 0x3) << 18; |
| 11641 | // op: iflags |
| 11642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11643 | Value |= (op & 0x7) << 6; |
| 11644 | break; |
| 11645 | } |
| 11646 | case ARM::CPS3p: { |
| 11647 | // op: imod |
| 11648 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11649 | Value |= (op & 0x3) << 18; |
| 11650 | // op: iflags |
| 11651 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11652 | Value |= (op & 0x7) << 6; |
| 11653 | // op: mode |
| 11654 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11655 | Value |= (op & 0x1f); |
| 11656 | break; |
| 11657 | } |
| 11658 | case ARM::t2CPS2p: { |
| 11659 | // op: imod |
| 11660 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11661 | Value |= (op & 0x3) << 9; |
| 11662 | // op: iflags |
| 11663 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11664 | Value |= (op & 0x7) << 5; |
| 11665 | break; |
| 11666 | } |
| 11667 | case ARM::t2CPS3p: { |
| 11668 | // op: imod |
| 11669 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11670 | Value |= (op & 0x3) << 9; |
| 11671 | // op: iflags |
| 11672 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11673 | Value |= (op & 0x7) << 5; |
| 11674 | // op: mode |
| 11675 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11676 | Value |= (op & 0x1f); |
| 11677 | break; |
| 11678 | } |
| 11679 | case ARM::t2LE: { |
| 11680 | // op: label |
| 11681 | op = getBFTargetOpValue<true, ARM::fixup_le>(MI, OpIdx: 0, Fixups, STI); |
| 11682 | Value |= (op & 0x1) << 11; |
| 11683 | Value |= (op & 0x7fe); |
| 11684 | break; |
| 11685 | } |
| 11686 | case ARM::MVE_LETP: |
| 11687 | case ARM::t2LEUpdate: { |
| 11688 | // op: label |
| 11689 | op = getBFTargetOpValue<true, ARM::fixup_le>(MI, OpIdx: 2, Fixups, STI); |
| 11690 | Value |= (op & 0x1) << 11; |
| 11691 | Value |= (op & 0x7fe); |
| 11692 | break; |
| 11693 | } |
| 11694 | case ARM::t2MSR_AR: { |
| 11695 | // op: mask |
| 11696 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11697 | Value |= (op & 0x10) << 16; |
| 11698 | Value |= (op & 0xf) << 8; |
| 11699 | // op: Rn |
| 11700 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11701 | Value |= (op & 0xf) << 16; |
| 11702 | break; |
| 11703 | } |
| 11704 | case ARM::CPS1p: |
| 11705 | case ARM::SRSDA: |
| 11706 | case ARM::SRSDA_UPD: |
| 11707 | case ARM::SRSDB: |
| 11708 | case ARM::SRSDB_UPD: |
| 11709 | case ARM::SRSIA: |
| 11710 | case ARM::SRSIA_UPD: |
| 11711 | case ARM::SRSIB: |
| 11712 | case ARM::SRSIB_UPD: |
| 11713 | case ARM::t2CPS1p: |
| 11714 | case ARM::t2SRSDB: |
| 11715 | case ARM::t2SRSDB_UPD: |
| 11716 | case ARM::t2SRSIA: |
| 11717 | case ARM::t2SRSIA_UPD: { |
| 11718 | // op: mode |
| 11719 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11720 | Value |= (op & 0x1f); |
| 11721 | break; |
| 11722 | } |
| 11723 | case ARM::LDC2L_POST: |
| 11724 | case ARM::LDC2_POST: |
| 11725 | case ARM::STC2L_POST: |
| 11726 | case ARM::STC2_POST: |
| 11727 | case ARM::t2LDC2L_POST: |
| 11728 | case ARM::t2LDC2_POST: |
| 11729 | case ARM::t2LDCL_POST: |
| 11730 | case ARM::t2LDC_POST: |
| 11731 | case ARM::t2STC2L_POST: |
| 11732 | case ARM::t2STC2_POST: |
| 11733 | case ARM::t2STCL_POST: |
| 11734 | case ARM::t2STC_POST: { |
| 11735 | // op: offset |
| 11736 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11737 | Value |= (op & 0x100) << 15; |
| 11738 | Value |= (op & 0xff); |
| 11739 | // op: addr |
| 11740 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11741 | Value |= (op & 0xf) << 16; |
| 11742 | // op: cop |
| 11743 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11744 | Value |= (op & 0xf) << 8; |
| 11745 | // op: CRd |
| 11746 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11747 | Value |= (op & 0xf) << 12; |
| 11748 | break; |
| 11749 | } |
| 11750 | case ARM::CDP2: |
| 11751 | case ARM::t2CDP: |
| 11752 | case ARM::t2CDP2: { |
| 11753 | // op: opc1 |
| 11754 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11755 | Value |= (op & 0xf) << 20; |
| 11756 | // op: CRn |
| 11757 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11758 | Value |= (op & 0xf) << 16; |
| 11759 | // op: CRd |
| 11760 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11761 | Value |= (op & 0xf) << 12; |
| 11762 | // op: cop |
| 11763 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11764 | Value |= (op & 0xf) << 8; |
| 11765 | // op: opc2 |
| 11766 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 11767 | Value |= (op & 0x7) << 5; |
| 11768 | // op: CRm |
| 11769 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 11770 | Value |= (op & 0xf); |
| 11771 | break; |
| 11772 | } |
| 11773 | case ARM::t2SMC: { |
| 11774 | // op: opt |
| 11775 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11776 | Value |= (op & 0xf) << 16; |
| 11777 | break; |
| 11778 | } |
| 11779 | case ARM::DMB: |
| 11780 | case ARM::DSB: |
| 11781 | case ARM::ISB: |
| 11782 | case ARM::t2DBG: |
| 11783 | case ARM::t2DMB: |
| 11784 | case ARM::t2DSB: |
| 11785 | case ARM::t2ISB: { |
| 11786 | // op: opt |
| 11787 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11788 | Value |= (op & 0xf); |
| 11789 | break; |
| 11790 | } |
| 11791 | case ARM::LDC2L_OPTION: |
| 11792 | case ARM::LDC2_OPTION: |
| 11793 | case ARM::STC2L_OPTION: |
| 11794 | case ARM::STC2_OPTION: |
| 11795 | case ARM::t2LDC2L_OPTION: |
| 11796 | case ARM::t2LDC2_OPTION: |
| 11797 | case ARM::t2LDCL_OPTION: |
| 11798 | case ARM::t2LDC_OPTION: |
| 11799 | case ARM::t2STC2L_OPTION: |
| 11800 | case ARM::t2STC2_OPTION: |
| 11801 | case ARM::t2STCL_OPTION: |
| 11802 | case ARM::t2STC_OPTION: { |
| 11803 | // op: option |
| 11804 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11805 | Value |= (op & 0xff); |
| 11806 | // op: addr |
| 11807 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11808 | Value |= (op & 0xf) << 16; |
| 11809 | // op: cop |
| 11810 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11811 | Value |= (op & 0xf) << 8; |
| 11812 | // op: CRd |
| 11813 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11814 | Value |= (op & 0xf) << 12; |
| 11815 | break; |
| 11816 | } |
| 11817 | case ARM::BX_RET: |
| 11818 | case ARM::ERET: |
| 11819 | case ARM::MOVPCLR: { |
| 11820 | // op: p |
| 11821 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11822 | Value |= (op & 0xf) << 28; |
| 11823 | break; |
| 11824 | } |
| 11825 | case ARM::FMSTAT: { |
| 11826 | // op: p |
| 11827 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11828 | Value |= (op & 0xf) << 28; |
| 11829 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 11830 | break; |
| 11831 | } |
| 11832 | case ARM::t2Bcc: { |
| 11833 | // op: p |
| 11834 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11835 | Value |= (op & 0xf) << 22; |
| 11836 | // op: target |
| 11837 | op = getBranchTargetOpValue(MI, OpIdx: 0, Fixups, STI); |
| 11838 | Value |= (op & 0x100000) << 6; |
| 11839 | Value |= (op & 0x3f000) << 4; |
| 11840 | Value |= (op & 0x40000) >> 5; |
| 11841 | Value |= (op & 0x80000) >> 8; |
| 11842 | Value |= (op & 0xffe) >> 1; |
| 11843 | break; |
| 11844 | } |
| 11845 | case ARM::VCMPEZD: |
| 11846 | case ARM::VCMPZD: { |
| 11847 | // op: p |
| 11848 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11849 | Value |= (op & 0xf) << 28; |
| 11850 | // op: Dd |
| 11851 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11852 | Value |= (op & 0x10) << 18; |
| 11853 | Value |= (op & 0xf) << 12; |
| 11854 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 11855 | break; |
| 11856 | } |
| 11857 | case ARM::MRS: |
| 11858 | case ARM::MRSsys: { |
| 11859 | // op: p |
| 11860 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11861 | Value |= (op & 0xf) << 28; |
| 11862 | // op: Rd |
| 11863 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11864 | Value |= (op & 0xf) << 12; |
| 11865 | break; |
| 11866 | } |
| 11867 | case ARM::VLDMSIA: |
| 11868 | case ARM::VSTMSIA: { |
| 11869 | // op: p |
| 11870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11871 | Value |= (op & 0xf) << 28; |
| 11872 | // op: Rn |
| 11873 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11874 | Value |= (op & 0xf) << 16; |
| 11875 | // op: regs |
| 11876 | op = getRegisterListOpValue(MI, Op: 3, Fixups, STI); |
| 11877 | Value |= (op & 0x100) << 14; |
| 11878 | Value |= (op & 0x1e00) << 3; |
| 11879 | Value |= (op & 0xff); |
| 11880 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 11881 | break; |
| 11882 | } |
| 11883 | case ARM::VLDMDIA: |
| 11884 | case ARM::VSTMDIA: { |
| 11885 | // op: p |
| 11886 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11887 | Value |= (op & 0xf) << 28; |
| 11888 | // op: Rn |
| 11889 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11890 | Value |= (op & 0xf) << 16; |
| 11891 | // op: regs |
| 11892 | op = getRegisterListOpValue(MI, Op: 3, Fixups, STI); |
| 11893 | Value |= (op & 0x1000) << 10; |
| 11894 | Value |= (op & 0xf00) << 4; |
| 11895 | Value |= (op & 0xfe); |
| 11896 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 11897 | break; |
| 11898 | } |
| 11899 | case ARM::FLDMXIA: |
| 11900 | case ARM::FSTMXIA: { |
| 11901 | // op: p |
| 11902 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11903 | Value |= (op & 0xf) << 28; |
| 11904 | // op: Rn |
| 11905 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11906 | Value |= (op & 0xf) << 16; |
| 11907 | // op: regs |
| 11908 | op = getRegisterListOpValue(MI, Op: 3, Fixups, STI); |
| 11909 | Value |= (op & 0xf00) << 4; |
| 11910 | Value |= (op & 0xfe); |
| 11911 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 11912 | break; |
| 11913 | } |
| 11914 | case ARM::VMRS: |
| 11915 | case ARM::VMRS_FPCXTNS: |
| 11916 | case ARM::VMRS_FPCXTS: |
| 11917 | case ARM::VMRS_FPEXC: |
| 11918 | case ARM::VMRS_FPINST: |
| 11919 | case ARM::VMRS_FPINST2: |
| 11920 | case ARM::VMRS_FPSID: |
| 11921 | case ARM::VMRS_MVFR0: |
| 11922 | case ARM::VMRS_MVFR1: |
| 11923 | case ARM::VMRS_MVFR2: |
| 11924 | case ARM::VMRS_VPR: |
| 11925 | case ARM::VMSR: |
| 11926 | case ARM::VMSR_FPCXTNS: |
| 11927 | case ARM::VMSR_FPCXTS: |
| 11928 | case ARM::VMSR_FPEXC: |
| 11929 | case ARM::VMSR_FPINST: |
| 11930 | case ARM::VMSR_FPINST2: |
| 11931 | case ARM::VMSR_FPSID: |
| 11932 | case ARM::VMSR_VPR: { |
| 11933 | // op: p |
| 11934 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11935 | Value |= (op & 0xf) << 28; |
| 11936 | // op: Rt |
| 11937 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11938 | Value |= (op & 0xf) << 12; |
| 11939 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 11940 | break; |
| 11941 | } |
| 11942 | case ARM::VCMPEZH: |
| 11943 | case ARM::VCMPEZS: |
| 11944 | case ARM::VCMPZH: |
| 11945 | case ARM::VCMPZS: { |
| 11946 | // op: p |
| 11947 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11948 | Value |= (op & 0xf) << 28; |
| 11949 | // op: Sd |
| 11950 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11951 | Value |= (op & 0x1) << 22; |
| 11952 | Value |= (op & 0x1e) << 11; |
| 11953 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 11954 | break; |
| 11955 | } |
| 11956 | case ARM::BX_pred: { |
| 11957 | // op: p |
| 11958 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11959 | Value |= (op & 0xf) << 28; |
| 11960 | // op: dst |
| 11961 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11962 | Value |= (op & 0xf); |
| 11963 | break; |
| 11964 | } |
| 11965 | case ARM::BL_pred: { |
| 11966 | // op: p |
| 11967 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11968 | Value |= (op & 0xf) << 28; |
| 11969 | // op: func |
| 11970 | op = getARMBLTargetOpValue(MI, OpIdx: 0, Fixups, STI); |
| 11971 | Value |= (op & 0xffffff); |
| 11972 | break; |
| 11973 | } |
| 11974 | case ARM::BLX_pred: |
| 11975 | case ARM::BXJ: { |
| 11976 | // op: p |
| 11977 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11978 | Value |= (op & 0xf) << 28; |
| 11979 | // op: func |
| 11980 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11981 | Value |= (op & 0xf); |
| 11982 | break; |
| 11983 | } |
| 11984 | case ARM::HINT: { |
| 11985 | // op: p |
| 11986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11987 | Value |= (op & 0xf) << 28; |
| 11988 | // op: imm |
| 11989 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11990 | Value |= (op & 0xff); |
| 11991 | break; |
| 11992 | } |
| 11993 | case ARM::DBG: |
| 11994 | case ARM::SMC: { |
| 11995 | // op: p |
| 11996 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11997 | Value |= (op & 0xf) << 28; |
| 11998 | // op: opt |
| 11999 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12000 | Value |= (op & 0xf); |
| 12001 | break; |
| 12002 | } |
| 12003 | case ARM::LDMDA: |
| 12004 | case ARM::LDMDB: |
| 12005 | case ARM::LDMIA: |
| 12006 | case ARM::LDMIB: |
| 12007 | case ARM::STMDA: |
| 12008 | case ARM::STMDB: |
| 12009 | case ARM::STMIA: |
| 12010 | case ARM::STMIB: |
| 12011 | case ARM::sysLDMDA: |
| 12012 | case ARM::sysLDMDB: |
| 12013 | case ARM::sysLDMIA: |
| 12014 | case ARM::sysLDMIB: |
| 12015 | case ARM::sysSTMDA: |
| 12016 | case ARM::sysSTMDB: |
| 12017 | case ARM::sysSTMIA: |
| 12018 | case ARM::sysSTMIB: { |
| 12019 | // op: p |
| 12020 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12021 | Value |= (op & 0xf) << 28; |
| 12022 | // op: regs |
| 12023 | op = getRegisterListOpValue(MI, Op: 3, Fixups, STI); |
| 12024 | Value |= (op & 0xffff); |
| 12025 | // op: Rn |
| 12026 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12027 | Value |= (op & 0xf) << 16; |
| 12028 | break; |
| 12029 | } |
| 12030 | case ARM::SVC: { |
| 12031 | // op: p |
| 12032 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12033 | Value |= (op & 0xf) << 28; |
| 12034 | // op: svc |
| 12035 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12036 | Value |= (op & 0xffffff); |
| 12037 | break; |
| 12038 | } |
| 12039 | case ARM::Bcc: { |
| 12040 | // op: p |
| 12041 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12042 | Value |= (op & 0xf) << 28; |
| 12043 | // op: target |
| 12044 | op = getARMBranchTargetOpValue(MI, OpIdx: 0, Fixups, STI); |
| 12045 | Value |= (op & 0xffffff); |
| 12046 | break; |
| 12047 | } |
| 12048 | case ARM::tBcc: { |
| 12049 | // op: p |
| 12050 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12051 | Value |= (op & 0xf) << 8; |
| 12052 | // op: target |
| 12053 | op = getThumbBCCTargetOpValue(MI, OpIdx: 0, Fixups, STI); |
| 12054 | Value |= (op & 0xff); |
| 12055 | break; |
| 12056 | } |
| 12057 | case ARM::VABSD: |
| 12058 | case ARM::VCMPD: |
| 12059 | case ARM::VCMPED: |
| 12060 | case ARM::VMOVD: |
| 12061 | case ARM::VNEGD: |
| 12062 | case ARM::VRINTRD: |
| 12063 | case ARM::VRINTXD: |
| 12064 | case ARM::VRINTZD: |
| 12065 | case ARM::VSQRTD: { |
| 12066 | // op: p |
| 12067 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12068 | Value |= (op & 0xf) << 28; |
| 12069 | // op: Dd |
| 12070 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12071 | Value |= (op & 0x10) << 18; |
| 12072 | Value |= (op & 0xf) << 12; |
| 12073 | // op: Dm |
| 12074 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12075 | Value |= (op & 0x10) << 1; |
| 12076 | Value |= (op & 0xf); |
| 12077 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12078 | break; |
| 12079 | } |
| 12080 | case ARM::VCVTBHD: |
| 12081 | case ARM::VCVTTHD: |
| 12082 | case ARM::VSITOD: |
| 12083 | case ARM::VUITOD: { |
| 12084 | // op: p |
| 12085 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12086 | Value |= (op & 0xf) << 28; |
| 12087 | // op: Dd |
| 12088 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12089 | Value |= (op & 0x10) << 18; |
| 12090 | Value |= (op & 0xf) << 12; |
| 12091 | // op: Sm |
| 12092 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12093 | Value |= (op & 0x1) << 5; |
| 12094 | Value |= (op & 0x1e) >> 1; |
| 12095 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12096 | break; |
| 12097 | } |
| 12098 | case ARM::FCONSTD: { |
| 12099 | // op: p |
| 12100 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12101 | Value |= (op & 0xf) << 28; |
| 12102 | // op: Dd |
| 12103 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12104 | Value |= (op & 0x10) << 18; |
| 12105 | Value |= (op & 0xf) << 12; |
| 12106 | // op: imm |
| 12107 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12108 | Value |= (op & 0xf0) << 12; |
| 12109 | Value |= (op & 0xf); |
| 12110 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12111 | break; |
| 12112 | } |
| 12113 | case ARM::CLZ: |
| 12114 | case ARM::RBIT: |
| 12115 | case ARM::REV: |
| 12116 | case ARM::REV16: |
| 12117 | case ARM::REVSH: { |
| 12118 | // op: p |
| 12119 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12120 | Value |= (op & 0xf) << 28; |
| 12121 | // op: Rd |
| 12122 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12123 | Value |= (op & 0xf) << 12; |
| 12124 | // op: Rm |
| 12125 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12126 | Value |= (op & 0xf); |
| 12127 | break; |
| 12128 | } |
| 12129 | case ARM::MOVi16: { |
| 12130 | // op: p |
| 12131 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12132 | Value |= (op & 0xf) << 28; |
| 12133 | // op: Rd |
| 12134 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12135 | Value |= (op & 0xf) << 12; |
| 12136 | // op: imm |
| 12137 | op = getHiLoImmOpValue(MI, OpIdx: 1, Fixups, STI); |
| 12138 | Value |= (op & 0xf000) << 4; |
| 12139 | Value |= (op & 0xfff); |
| 12140 | break; |
| 12141 | } |
| 12142 | case ARM::ADR: { |
| 12143 | // op: p |
| 12144 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12145 | Value |= (op & 0xf) << 28; |
| 12146 | // op: Rd |
| 12147 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12148 | Value |= (op & 0xf) << 12; |
| 12149 | // op: label |
| 12150 | op = getAdrLabelOpValue(MI, OpIdx: 1, Fixups, STI); |
| 12151 | Value |= (op & 0x3000) << 10; |
| 12152 | Value |= (op & 0xfff); |
| 12153 | break; |
| 12154 | } |
| 12155 | case ARM::CMNzrr: |
| 12156 | case ARM::CMPrr: |
| 12157 | case ARM::TEQrr: |
| 12158 | case ARM::TSTrr: { |
| 12159 | // op: p |
| 12160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12161 | Value |= (op & 0xf) << 28; |
| 12162 | // op: Rn |
| 12163 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12164 | Value |= (op & 0xf) << 16; |
| 12165 | // op: Rm |
| 12166 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12167 | Value |= (op & 0xf); |
| 12168 | break; |
| 12169 | } |
| 12170 | case ARM::CMNri: |
| 12171 | case ARM::CMPri: |
| 12172 | case ARM::TEQri: |
| 12173 | case ARM::TSTri: { |
| 12174 | // op: p |
| 12175 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12176 | Value |= (op & 0xf) << 28; |
| 12177 | // op: Rn |
| 12178 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12179 | Value |= (op & 0xf) << 16; |
| 12180 | // op: imm |
| 12181 | op = getModImmOpValue(MI, Op: 1, Fixups, ST: STI); |
| 12182 | Value |= (op & 0xfff); |
| 12183 | break; |
| 12184 | } |
| 12185 | case ARM::VLDMSDB_UPD: |
| 12186 | case ARM::VLDMSIA_UPD: |
| 12187 | case ARM::VSTMSDB_UPD: |
| 12188 | case ARM::VSTMSIA_UPD: { |
| 12189 | // op: p |
| 12190 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12191 | Value |= (op & 0xf) << 28; |
| 12192 | // op: Rn |
| 12193 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12194 | Value |= (op & 0xf) << 16; |
| 12195 | // op: regs |
| 12196 | op = getRegisterListOpValue(MI, Op: 4, Fixups, STI); |
| 12197 | Value |= (op & 0x100) << 14; |
| 12198 | Value |= (op & 0x1e00) << 3; |
| 12199 | Value |= (op & 0xff); |
| 12200 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12201 | break; |
| 12202 | } |
| 12203 | case ARM::VLDMDDB_UPD: |
| 12204 | case ARM::VLDMDIA_UPD: |
| 12205 | case ARM::VSTMDDB_UPD: |
| 12206 | case ARM::VSTMDIA_UPD: { |
| 12207 | // op: p |
| 12208 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12209 | Value |= (op & 0xf) << 28; |
| 12210 | // op: Rn |
| 12211 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12212 | Value |= (op & 0xf) << 16; |
| 12213 | // op: regs |
| 12214 | op = getRegisterListOpValue(MI, Op: 4, Fixups, STI); |
| 12215 | Value |= (op & 0x1000) << 10; |
| 12216 | Value |= (op & 0xf00) << 4; |
| 12217 | Value |= (op & 0xfe); |
| 12218 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12219 | break; |
| 12220 | } |
| 12221 | case ARM::FLDMXDB_UPD: |
| 12222 | case ARM::FLDMXIA_UPD: |
| 12223 | case ARM::FSTMXDB_UPD: |
| 12224 | case ARM::FSTMXIA_UPD: { |
| 12225 | // op: p |
| 12226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12227 | Value |= (op & 0xf) << 28; |
| 12228 | // op: Rn |
| 12229 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12230 | Value |= (op & 0xf) << 16; |
| 12231 | // op: regs |
| 12232 | op = getRegisterListOpValue(MI, Op: 4, Fixups, STI); |
| 12233 | Value |= (op & 0xf00) << 4; |
| 12234 | Value |= (op & 0xfe); |
| 12235 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12236 | break; |
| 12237 | } |
| 12238 | case ARM::VMOVRH: |
| 12239 | case ARM::VMOVRS: { |
| 12240 | // op: p |
| 12241 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12242 | Value |= (op & 0xf) << 28; |
| 12243 | // op: Rt |
| 12244 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12245 | Value |= (op & 0xf) << 12; |
| 12246 | // op: Sn |
| 12247 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12248 | Value |= (op & 0x1e) << 15; |
| 12249 | Value |= (op & 0x1) << 7; |
| 12250 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12251 | break; |
| 12252 | } |
| 12253 | case ARM::LDA: |
| 12254 | case ARM::LDAB: |
| 12255 | case ARM::LDAEX: |
| 12256 | case ARM::LDAEXB: |
| 12257 | case ARM::LDAEXD: |
| 12258 | case ARM::LDAEXH: |
| 12259 | case ARM::LDAH: |
| 12260 | case ARM::LDREX: |
| 12261 | case ARM::LDREXB: |
| 12262 | case ARM::LDREXD: |
| 12263 | case ARM::LDREXH: { |
| 12264 | // op: p |
| 12265 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12266 | Value |= (op & 0xf) << 28; |
| 12267 | // op: Rt |
| 12268 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12269 | Value |= (op & 0xf) << 12; |
| 12270 | // op: addr |
| 12271 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12272 | Value |= (op & 0xf) << 16; |
| 12273 | break; |
| 12274 | } |
| 12275 | case ARM::VMRS_FPSCR_NZCVQC: |
| 12276 | case ARM::VMRS_P0: { |
| 12277 | // op: p |
| 12278 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12279 | Value |= (op & 0xf) << 28; |
| 12280 | // op: Rt |
| 12281 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12282 | Value |= (op & 0xf) << 12; |
| 12283 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12284 | break; |
| 12285 | } |
| 12286 | case ARM::STL: |
| 12287 | case ARM::STLB: |
| 12288 | case ARM::STLH: { |
| 12289 | // op: p |
| 12290 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12291 | Value |= (op & 0xf) << 28; |
| 12292 | // op: Rt |
| 12293 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12294 | Value |= (op & 0xf); |
| 12295 | // op: addr |
| 12296 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12297 | Value |= (op & 0xf) << 16; |
| 12298 | break; |
| 12299 | } |
| 12300 | case ARM::VMSR_FPSCR_NZCVQC: |
| 12301 | case ARM::VMSR_P0: { |
| 12302 | // op: p |
| 12303 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12304 | Value |= (op & 0xf) << 28; |
| 12305 | // op: Rt |
| 12306 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12307 | Value |= (op & 0xf) << 12; |
| 12308 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12309 | break; |
| 12310 | } |
| 12311 | case ARM::VCVTSD: |
| 12312 | case ARM::VJCVT: |
| 12313 | case ARM::VTOSIRD: |
| 12314 | case ARM::VTOSIZD: |
| 12315 | case ARM::VTOUIRD: |
| 12316 | case ARM::VTOUIZD: { |
| 12317 | // op: p |
| 12318 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12319 | Value |= (op & 0xf) << 28; |
| 12320 | // op: Sd |
| 12321 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12322 | Value |= (op & 0x1) << 22; |
| 12323 | Value |= (op & 0x1e) << 11; |
| 12324 | // op: Dm |
| 12325 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12326 | Value |= (op & 0x10) << 1; |
| 12327 | Value |= (op & 0xf); |
| 12328 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12329 | break; |
| 12330 | } |
| 12331 | case ARM::VABSH: |
| 12332 | case ARM::VABSS: |
| 12333 | case ARM::VCMPEH: |
| 12334 | case ARM::VCMPES: |
| 12335 | case ARM::VCMPH: |
| 12336 | case ARM::VCMPS: |
| 12337 | case ARM::VCVTBHS: |
| 12338 | case ARM::VCVTTHS: |
| 12339 | case ARM::VMOVS: |
| 12340 | case ARM::VNEGH: |
| 12341 | case ARM::VNEGS: |
| 12342 | case ARM::VRINTRH: |
| 12343 | case ARM::VRINTRS: |
| 12344 | case ARM::VRINTXH: |
| 12345 | case ARM::VRINTXS: |
| 12346 | case ARM::VRINTZH: |
| 12347 | case ARM::VRINTZS: |
| 12348 | case ARM::VSITOH: |
| 12349 | case ARM::VSITOS: |
| 12350 | case ARM::VSQRTH: |
| 12351 | case ARM::VSQRTS: |
| 12352 | case ARM::VTOSIRH: |
| 12353 | case ARM::VTOSIRS: |
| 12354 | case ARM::VTOSIZH: |
| 12355 | case ARM::VTOSIZS: |
| 12356 | case ARM::VTOUIRH: |
| 12357 | case ARM::VTOUIRS: |
| 12358 | case ARM::VTOUIZH: |
| 12359 | case ARM::VTOUIZS: |
| 12360 | case ARM::VUITOH: |
| 12361 | case ARM::VUITOS: { |
| 12362 | // op: p |
| 12363 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12364 | Value |= (op & 0xf) << 28; |
| 12365 | // op: Sd |
| 12366 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12367 | Value |= (op & 0x1) << 22; |
| 12368 | Value |= (op & 0x1e) << 11; |
| 12369 | // op: Sm |
| 12370 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12371 | Value |= (op & 0x1) << 5; |
| 12372 | Value |= (op & 0x1e) >> 1; |
| 12373 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12374 | break; |
| 12375 | } |
| 12376 | case ARM::FCONSTH: |
| 12377 | case ARM::FCONSTS: { |
| 12378 | // op: p |
| 12379 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12380 | Value |= (op & 0xf) << 28; |
| 12381 | // op: Sd |
| 12382 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12383 | Value |= (op & 0x1) << 22; |
| 12384 | Value |= (op & 0x1e) << 11; |
| 12385 | // op: imm |
| 12386 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12387 | Value |= (op & 0xf0) << 12; |
| 12388 | Value |= (op & 0xf); |
| 12389 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12390 | break; |
| 12391 | } |
| 12392 | case ARM::VCVTDS: { |
| 12393 | // op: p |
| 12394 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12395 | Value |= (op & 0xf) << 28; |
| 12396 | // op: Sm |
| 12397 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12398 | Value |= (op & 0x1) << 5; |
| 12399 | Value |= (op & 0x1e) >> 1; |
| 12400 | // op: Dd |
| 12401 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12402 | Value |= (op & 0x10) << 18; |
| 12403 | Value |= (op & 0xf) << 12; |
| 12404 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12405 | break; |
| 12406 | } |
| 12407 | case ARM::VMOVHR: |
| 12408 | case ARM::VMOVSR: { |
| 12409 | // op: p |
| 12410 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12411 | Value |= (op & 0xf) << 28; |
| 12412 | // op: Sn |
| 12413 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12414 | Value |= (op & 0x1e) << 15; |
| 12415 | Value |= (op & 0x1) << 7; |
| 12416 | // op: Rt |
| 12417 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12418 | Value |= (op & 0xf) << 12; |
| 12419 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12420 | break; |
| 12421 | } |
| 12422 | case ARM::VLDR_FPCXTNS_off: |
| 12423 | case ARM::VLDR_FPCXTS_off: |
| 12424 | case ARM::VLDR_FPSCR_off: |
| 12425 | case ARM::VLDR_VPR_off: |
| 12426 | case ARM::VSTR_FPCXTNS_off: |
| 12427 | case ARM::VSTR_FPCXTS_off: |
| 12428 | case ARM::VSTR_FPSCR_off: |
| 12429 | case ARM::VSTR_VPR_off: { |
| 12430 | // op: p |
| 12431 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12432 | Value |= (op & 0xf) << 28; |
| 12433 | // op: addr |
| 12434 | op = getT2AddrModeImm7s4OpValue(MI, OpIdx: 0, Fixups, STI); |
| 12435 | Value |= (op & 0x80) << 16; |
| 12436 | Value |= (op & 0xf00) << 8; |
| 12437 | Value |= (op & 0x7f); |
| 12438 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12439 | break; |
| 12440 | } |
| 12441 | case ARM::MSRbanked: { |
| 12442 | // op: p |
| 12443 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12444 | Value |= (op & 0xf) << 28; |
| 12445 | // op: banked |
| 12446 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12447 | Value |= (op & 0x20) << 17; |
| 12448 | Value |= (op & 0xf) << 16; |
| 12449 | Value |= (op & 0x10) << 4; |
| 12450 | // op: Rn |
| 12451 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12452 | Value |= (op & 0xf); |
| 12453 | break; |
| 12454 | } |
| 12455 | case ARM::MRSbanked: { |
| 12456 | // op: p |
| 12457 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12458 | Value |= (op & 0xf) << 28; |
| 12459 | // op: banked |
| 12460 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12461 | Value |= (op & 0x20) << 17; |
| 12462 | Value |= (op & 0xf) << 16; |
| 12463 | Value |= (op & 0x10) << 4; |
| 12464 | // op: Rd |
| 12465 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12466 | Value |= (op & 0xf) << 12; |
| 12467 | break; |
| 12468 | } |
| 12469 | case ARM::MSR: { |
| 12470 | // op: p |
| 12471 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12472 | Value |= (op & 0xf) << 28; |
| 12473 | // op: mask |
| 12474 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12475 | Value |= (op & 0x10) << 18; |
| 12476 | Value |= (op & 0xf) << 16; |
| 12477 | // op: Rn |
| 12478 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12479 | Value |= (op & 0xf); |
| 12480 | break; |
| 12481 | } |
| 12482 | case ARM::MSRi: { |
| 12483 | // op: p |
| 12484 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12485 | Value |= (op & 0xf) << 28; |
| 12486 | // op: mask |
| 12487 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12488 | Value |= (op & 0x10) << 18; |
| 12489 | Value |= (op & 0xf) << 16; |
| 12490 | // op: imm |
| 12491 | op = getModImmOpValue(MI, Op: 1, Fixups, ST: STI); |
| 12492 | Value |= (op & 0xfff); |
| 12493 | break; |
| 12494 | } |
| 12495 | case ARM::LDMDA_UPD: |
| 12496 | case ARM::LDMDB_UPD: |
| 12497 | case ARM::LDMIA_UPD: |
| 12498 | case ARM::LDMIB_UPD: |
| 12499 | case ARM::STMDA_UPD: |
| 12500 | case ARM::STMDB_UPD: |
| 12501 | case ARM::STMIA_UPD: |
| 12502 | case ARM::STMIB_UPD: |
| 12503 | case ARM::sysLDMDA_UPD: |
| 12504 | case ARM::sysLDMDB_UPD: |
| 12505 | case ARM::sysLDMIA_UPD: |
| 12506 | case ARM::sysLDMIB_UPD: |
| 12507 | case ARM::sysSTMDA_UPD: |
| 12508 | case ARM::sysSTMDB_UPD: |
| 12509 | case ARM::sysSTMIA_UPD: |
| 12510 | case ARM::sysSTMIB_UPD: { |
| 12511 | // op: p |
| 12512 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12513 | Value |= (op & 0xf) << 28; |
| 12514 | // op: regs |
| 12515 | op = getRegisterListOpValue(MI, Op: 4, Fixups, STI); |
| 12516 | Value |= (op & 0xffff); |
| 12517 | // op: Rn |
| 12518 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12519 | Value |= (op & 0xf) << 16; |
| 12520 | break; |
| 12521 | } |
| 12522 | case ARM::MOVr: |
| 12523 | case ARM::MOVr_TC: |
| 12524 | case ARM::MVNr: { |
| 12525 | // op: p |
| 12526 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12527 | Value |= (op & 0xf) << 28; |
| 12528 | // op: s |
| 12529 | op = getCCOutOpValue(MI, Op: 4, Fixups, STI); |
| 12530 | Value |= (op & 0x1) << 20; |
| 12531 | // op: Rd |
| 12532 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12533 | Value |= (op & 0xf) << 12; |
| 12534 | // op: Rm |
| 12535 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12536 | Value |= (op & 0xf); |
| 12537 | break; |
| 12538 | } |
| 12539 | case ARM::MOVi: |
| 12540 | case ARM::MVNi: { |
| 12541 | // op: p |
| 12542 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12543 | Value |= (op & 0xf) << 28; |
| 12544 | // op: s |
| 12545 | op = getCCOutOpValue(MI, Op: 4, Fixups, STI); |
| 12546 | Value |= (op & 0x1) << 20; |
| 12547 | // op: Rd |
| 12548 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12549 | Value |= (op & 0xf) << 12; |
| 12550 | // op: imm |
| 12551 | op = getModImmOpValue(MI, Op: 1, Fixups, ST: STI); |
| 12552 | Value |= (op & 0xfff); |
| 12553 | break; |
| 12554 | } |
| 12555 | case ARM::VADDD: |
| 12556 | case ARM::VDIVD: |
| 12557 | case ARM::VMULD: |
| 12558 | case ARM::VNMULD: |
| 12559 | case ARM::VSUBD: { |
| 12560 | // op: p |
| 12561 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12562 | Value |= (op & 0xf) << 28; |
| 12563 | // op: Dd |
| 12564 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12565 | Value |= (op & 0x10) << 18; |
| 12566 | Value |= (op & 0xf) << 12; |
| 12567 | // op: Dn |
| 12568 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12569 | Value |= (op & 0xf) << 16; |
| 12570 | Value |= (op & 0x10) << 3; |
| 12571 | // op: Dm |
| 12572 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12573 | Value |= (op & 0x10) << 1; |
| 12574 | Value |= (op & 0xf); |
| 12575 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12576 | break; |
| 12577 | } |
| 12578 | case ARM::VLDRD: |
| 12579 | case ARM::VSTRD: { |
| 12580 | // op: p |
| 12581 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12582 | Value |= (op & 0xf) << 28; |
| 12583 | // op: Dd |
| 12584 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12585 | Value |= (op & 0x10) << 18; |
| 12586 | Value |= (op & 0xf) << 12; |
| 12587 | // op: addr |
| 12588 | op = getAddrMode5OpValue(MI, OpIdx: 1, Fixups, STI); |
| 12589 | Value |= (op & 0x100) << 15; |
| 12590 | Value |= (op & 0x1e00) << 7; |
| 12591 | Value |= (op & 0xff); |
| 12592 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12593 | break; |
| 12594 | } |
| 12595 | case ARM::VMOVDRR: { |
| 12596 | // op: p |
| 12597 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12598 | Value |= (op & 0xf) << 28; |
| 12599 | // op: Dm |
| 12600 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12601 | Value |= (op & 0x10) << 1; |
| 12602 | Value |= (op & 0xf); |
| 12603 | // op: Rt |
| 12604 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12605 | Value |= (op & 0xf) << 12; |
| 12606 | // op: Rt2 |
| 12607 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12608 | Value |= (op & 0xf) << 16; |
| 12609 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12610 | break; |
| 12611 | } |
| 12612 | case ARM::VMOVRRD: { |
| 12613 | // op: p |
| 12614 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12615 | Value |= (op & 0xf) << 28; |
| 12616 | // op: Dm |
| 12617 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12618 | Value |= (op & 0x10) << 1; |
| 12619 | Value |= (op & 0xf); |
| 12620 | // op: Rt |
| 12621 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12622 | Value |= (op & 0xf) << 12; |
| 12623 | // op: Rt2 |
| 12624 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12625 | Value |= (op & 0xf) << 16; |
| 12626 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12627 | break; |
| 12628 | } |
| 12629 | case ARM::VCVTBDH: |
| 12630 | case ARM::VCVTTDH: { |
| 12631 | // op: p |
| 12632 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12633 | Value |= (op & 0xf) << 28; |
| 12634 | // op: Dm |
| 12635 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12636 | Value |= (op & 0x10) << 1; |
| 12637 | Value |= (op & 0xf); |
| 12638 | // op: Sd |
| 12639 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12640 | Value |= (op & 0x1) << 22; |
| 12641 | Value |= (op & 0x1e) << 11; |
| 12642 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12643 | break; |
| 12644 | } |
| 12645 | case ARM::SXTB: |
| 12646 | case ARM::SXTB16: |
| 12647 | case ARM::SXTH: |
| 12648 | case ARM::UXTB: |
| 12649 | case ARM::UXTB16: |
| 12650 | case ARM::UXTH: { |
| 12651 | // op: p |
| 12652 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12653 | Value |= (op & 0xf) << 28; |
| 12654 | // op: Rd |
| 12655 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12656 | Value |= (op & 0xf) << 12; |
| 12657 | // op: Rm |
| 12658 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12659 | Value |= (op & 0xf); |
| 12660 | // op: rot |
| 12661 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12662 | Value |= (op & 0x3) << 10; |
| 12663 | break; |
| 12664 | } |
| 12665 | case ARM::SEL: { |
| 12666 | // op: p |
| 12667 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12668 | Value |= (op & 0xf) << 28; |
| 12669 | // op: Rd |
| 12670 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12671 | Value |= (op & 0xf) << 12; |
| 12672 | // op: Rn |
| 12673 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12674 | Value |= (op & 0xf) << 16; |
| 12675 | // op: Rm |
| 12676 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12677 | Value |= (op & 0xf); |
| 12678 | break; |
| 12679 | } |
| 12680 | case ARM::BFC: { |
| 12681 | // op: p |
| 12682 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12683 | Value |= (op & 0xf) << 28; |
| 12684 | // op: Rd |
| 12685 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12686 | Value |= (op & 0xf) << 12; |
| 12687 | // op: imm |
| 12688 | op = getBitfieldInvertedMaskOpValue(MI, Op: 2, Fixups, STI); |
| 12689 | Value |= (op & 0x3e0) << 11; |
| 12690 | Value |= (op & 0x1f) << 7; |
| 12691 | break; |
| 12692 | } |
| 12693 | case ARM::MOVTi16: { |
| 12694 | // op: p |
| 12695 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12696 | Value |= (op & 0xf) << 28; |
| 12697 | // op: Rd |
| 12698 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12699 | Value |= (op & 0xf) << 12; |
| 12700 | // op: imm |
| 12701 | op = getHiLoImmOpValue(MI, OpIdx: 2, Fixups, STI); |
| 12702 | Value |= (op & 0xf000) << 4; |
| 12703 | Value |= (op & 0xfff); |
| 12704 | break; |
| 12705 | } |
| 12706 | case ARM::SSAT16: |
| 12707 | case ARM::USAT16: { |
| 12708 | // op: p |
| 12709 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12710 | Value |= (op & 0xf) << 28; |
| 12711 | // op: Rd |
| 12712 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12713 | Value |= (op & 0xf) << 12; |
| 12714 | // op: sat_imm |
| 12715 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12716 | Value |= (op & 0xf) << 16; |
| 12717 | // op: Rn |
| 12718 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12719 | Value |= (op & 0xf); |
| 12720 | break; |
| 12721 | } |
| 12722 | case ARM::SDIV: |
| 12723 | case ARM::SMMUL: |
| 12724 | case ARM::SMMULR: |
| 12725 | case ARM::UDIV: |
| 12726 | case ARM::USAD8: { |
| 12727 | // op: p |
| 12728 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12729 | Value |= (op & 0xf) << 28; |
| 12730 | // op: Rd |
| 12731 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12732 | Value |= (op & 0xf) << 16; |
| 12733 | // op: Rn |
| 12734 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12735 | Value |= (op & 0xf); |
| 12736 | // op: Rm |
| 12737 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12738 | Value |= (op & 0xf) << 8; |
| 12739 | break; |
| 12740 | } |
| 12741 | case ARM::CMNzrsi: |
| 12742 | case ARM::CMPrsi: |
| 12743 | case ARM::TEQrsi: |
| 12744 | case ARM::TSTrsi: { |
| 12745 | // op: p |
| 12746 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12747 | Value |= (op & 0xf) << 28; |
| 12748 | // op: Rn |
| 12749 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12750 | Value |= (op & 0xf) << 16; |
| 12751 | // op: shift |
| 12752 | op = getSORegImmOpValue(MI, OpIdx: 1, Fixups, STI); |
| 12753 | Value |= (op & 0xfe0); |
| 12754 | Value |= (op & 0xf); |
| 12755 | break; |
| 12756 | } |
| 12757 | case ARM::QADD16: |
| 12758 | case ARM::QADD8: |
| 12759 | case ARM::QASX: |
| 12760 | case ARM::QSAX: |
| 12761 | case ARM::QSUB16: |
| 12762 | case ARM::QSUB8: |
| 12763 | case ARM::SADD16: |
| 12764 | case ARM::SADD8: |
| 12765 | case ARM::SASX: |
| 12766 | case ARM::SHADD16: |
| 12767 | case ARM::SHADD8: |
| 12768 | case ARM::SHASX: |
| 12769 | case ARM::SHSAX: |
| 12770 | case ARM::SHSUB16: |
| 12771 | case ARM::SHSUB8: |
| 12772 | case ARM::SSAX: |
| 12773 | case ARM::SSUB16: |
| 12774 | case ARM::SSUB8: |
| 12775 | case ARM::UADD16: |
| 12776 | case ARM::UADD8: |
| 12777 | case ARM::UASX: |
| 12778 | case ARM::UHADD16: |
| 12779 | case ARM::UHADD8: |
| 12780 | case ARM::UHASX: |
| 12781 | case ARM::UHSAX: |
| 12782 | case ARM::UHSUB16: |
| 12783 | case ARM::UHSUB8: |
| 12784 | case ARM::UQADD16: |
| 12785 | case ARM::UQADD8: |
| 12786 | case ARM::UQASX: |
| 12787 | case ARM::UQSAX: |
| 12788 | case ARM::UQSUB16: |
| 12789 | case ARM::UQSUB8: |
| 12790 | case ARM::USAX: |
| 12791 | case ARM::USUB16: |
| 12792 | case ARM::USUB8: { |
| 12793 | // op: p |
| 12794 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12795 | Value |= (op & 0xf) << 28; |
| 12796 | // op: Rn |
| 12797 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12798 | Value |= (op & 0xf) << 16; |
| 12799 | // op: Rd |
| 12800 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12801 | Value |= (op & 0xf) << 12; |
| 12802 | // op: Rm |
| 12803 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12804 | Value |= (op & 0xf); |
| 12805 | break; |
| 12806 | } |
| 12807 | case ARM::SMUAD: |
| 12808 | case ARM::SMUADX: |
| 12809 | case ARM::SMULBB: |
| 12810 | case ARM::SMULBT: |
| 12811 | case ARM::SMULTB: |
| 12812 | case ARM::SMULTT: |
| 12813 | case ARM::SMULWB: |
| 12814 | case ARM::SMULWT: |
| 12815 | case ARM::SMUSD: |
| 12816 | case ARM::SMUSDX: { |
| 12817 | // op: p |
| 12818 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12819 | Value |= (op & 0xf) << 28; |
| 12820 | // op: Rn |
| 12821 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12822 | Value |= (op & 0xf); |
| 12823 | // op: Rm |
| 12824 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12825 | Value |= (op & 0xf) << 8; |
| 12826 | // op: Rd |
| 12827 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12828 | Value |= (op & 0xf) << 16; |
| 12829 | break; |
| 12830 | } |
| 12831 | case ARM::QADD: |
| 12832 | case ARM::QDADD: |
| 12833 | case ARM::QDSUB: |
| 12834 | case ARM::QSUB: { |
| 12835 | // op: p |
| 12836 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12837 | Value |= (op & 0xf) << 28; |
| 12838 | // op: Rn |
| 12839 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12840 | Value |= (op & 0xf) << 16; |
| 12841 | // op: Rd |
| 12842 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12843 | Value |= (op & 0xf) << 12; |
| 12844 | // op: Rm |
| 12845 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12846 | Value |= (op & 0xf); |
| 12847 | break; |
| 12848 | } |
| 12849 | case ARM::SWP: |
| 12850 | case ARM::SWPB: { |
| 12851 | // op: p |
| 12852 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12853 | Value |= (op & 0xf) << 28; |
| 12854 | // op: Rt |
| 12855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12856 | Value |= (op & 0xf) << 12; |
| 12857 | // op: Rt2 |
| 12858 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12859 | Value |= (op & 0xf); |
| 12860 | // op: addr |
| 12861 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12862 | Value |= (op & 0xf) << 16; |
| 12863 | break; |
| 12864 | } |
| 12865 | case ARM::LDRBi12: |
| 12866 | case ARM::LDRi12: |
| 12867 | case ARM::STRBi12: |
| 12868 | case ARM::STRi12: { |
| 12869 | // op: p |
| 12870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12871 | Value |= (op & 0xf) << 28; |
| 12872 | // op: Rt |
| 12873 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12874 | Value |= (op & 0xf) << 12; |
| 12875 | // op: addr |
| 12876 | op = getAddrModeImm12OpValue(MI, OpIdx: 1, Fixups, STI); |
| 12877 | Value |= (op & 0x1000) << 11; |
| 12878 | Value |= (op & 0x1e000) << 3; |
| 12879 | Value |= (op & 0xfff); |
| 12880 | break; |
| 12881 | } |
| 12882 | case ARM::LDRcp: { |
| 12883 | // op: p |
| 12884 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12885 | Value |= (op & 0xf) << 28; |
| 12886 | // op: Rt |
| 12887 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12888 | Value |= (op & 0xf) << 12; |
| 12889 | // op: addr |
| 12890 | op = getAddrModeImm12OpValue(MI, OpIdx: 1, Fixups, STI); |
| 12891 | Value |= (op & 0x1000) << 11; |
| 12892 | Value |= (op & 0xfff); |
| 12893 | break; |
| 12894 | } |
| 12895 | case ARM::STLEX: |
| 12896 | case ARM::STLEXB: |
| 12897 | case ARM::STLEXD: |
| 12898 | case ARM::STLEXH: |
| 12899 | case ARM::STREX: |
| 12900 | case ARM::STREXB: |
| 12901 | case ARM::STREXD: |
| 12902 | case ARM::STREXH: { |
| 12903 | // op: p |
| 12904 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12905 | Value |= (op & 0xf) << 28; |
| 12906 | // op: Rt |
| 12907 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12908 | Value |= (op & 0xf); |
| 12909 | // op: addr |
| 12910 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12911 | Value |= (op & 0xf) << 16; |
| 12912 | // op: Rd |
| 12913 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12914 | Value |= (op & 0xf) << 12; |
| 12915 | break; |
| 12916 | } |
| 12917 | case ARM::BF16_VCVTB: |
| 12918 | case ARM::BF16_VCVTT: |
| 12919 | case ARM::VCVTBSH: |
| 12920 | case ARM::VCVTTSH: { |
| 12921 | // op: p |
| 12922 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12923 | Value |= (op & 0xf) << 28; |
| 12924 | // op: Sd |
| 12925 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12926 | Value |= (op & 0x1) << 22; |
| 12927 | Value |= (op & 0x1e) << 11; |
| 12928 | // op: Sm |
| 12929 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12930 | Value |= (op & 0x1) << 5; |
| 12931 | Value |= (op & 0x1e) >> 1; |
| 12932 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12933 | break; |
| 12934 | } |
| 12935 | case ARM::VADDH: |
| 12936 | case ARM::VADDS: |
| 12937 | case ARM::VDIVH: |
| 12938 | case ARM::VDIVS: |
| 12939 | case ARM::VMULH: |
| 12940 | case ARM::VMULS: |
| 12941 | case ARM::VNMULH: |
| 12942 | case ARM::VNMULS: |
| 12943 | case ARM::VSUBH: |
| 12944 | case ARM::VSUBS: { |
| 12945 | // op: p |
| 12946 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12947 | Value |= (op & 0xf) << 28; |
| 12948 | // op: Sd |
| 12949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12950 | Value |= (op & 0x1) << 22; |
| 12951 | Value |= (op & 0x1e) << 11; |
| 12952 | // op: Sn |
| 12953 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12954 | Value |= (op & 0x1e) << 15; |
| 12955 | Value |= (op & 0x1) << 7; |
| 12956 | // op: Sm |
| 12957 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12958 | Value |= (op & 0x1) << 5; |
| 12959 | Value |= (op & 0x1e) >> 1; |
| 12960 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12961 | break; |
| 12962 | } |
| 12963 | case ARM::VLDRH: |
| 12964 | case ARM::VSTRH: { |
| 12965 | // op: p |
| 12966 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12967 | Value |= (op & 0xf) << 28; |
| 12968 | // op: Sd |
| 12969 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12970 | Value |= (op & 0x1) << 22; |
| 12971 | Value |= (op & 0x1e) << 11; |
| 12972 | // op: addr |
| 12973 | op = getAddrMode5FP16OpValue(MI, OpIdx: 1, Fixups, STI); |
| 12974 | Value |= (op & 0x100) << 15; |
| 12975 | Value |= (op & 0x1e00) << 7; |
| 12976 | Value |= (op & 0xff); |
| 12977 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12978 | break; |
| 12979 | } |
| 12980 | case ARM::VLDRS: |
| 12981 | case ARM::VSTRS: { |
| 12982 | // op: p |
| 12983 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12984 | Value |= (op & 0xf) << 28; |
| 12985 | // op: Sd |
| 12986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12987 | Value |= (op & 0x1) << 22; |
| 12988 | Value |= (op & 0x1e) << 11; |
| 12989 | // op: addr |
| 12990 | op = getAddrMode5OpValue(MI, OpIdx: 1, Fixups, STI); |
| 12991 | Value |= (op & 0x100) << 15; |
| 12992 | Value |= (op & 0x1e00) << 7; |
| 12993 | Value |= (op & 0xff); |
| 12994 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 12995 | break; |
| 12996 | } |
| 12997 | case ARM::VLDR_FPCXTNS_pre: |
| 12998 | case ARM::VLDR_FPCXTS_pre: |
| 12999 | case ARM::VLDR_FPSCR_NZCVQC_off: |
| 13000 | case ARM::VLDR_FPSCR_pre: |
| 13001 | case ARM::VLDR_P0_off: |
| 13002 | case ARM::VLDR_VPR_pre: |
| 13003 | case ARM::VSTR_FPCXTNS_pre: |
| 13004 | case ARM::VSTR_FPCXTS_pre: |
| 13005 | case ARM::VSTR_FPSCR_NZCVQC_off: |
| 13006 | case ARM::VSTR_FPSCR_pre: |
| 13007 | case ARM::VSTR_P0_off: |
| 13008 | case ARM::VSTR_VPR_pre: { |
| 13009 | // op: p |
| 13010 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13011 | Value |= (op & 0xf) << 28; |
| 13012 | // op: addr |
| 13013 | op = getT2AddrModeImm7s4OpValue(MI, OpIdx: 1, Fixups, STI); |
| 13014 | Value |= (op & 0x80) << 16; |
| 13015 | Value |= (op & 0xf00) << 8; |
| 13016 | Value |= (op & 0x7f); |
| 13017 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 13018 | break; |
| 13019 | } |
| 13020 | case ARM::VLDR_FPCXTNS_post: |
| 13021 | case ARM::VLDR_FPCXTS_post: |
| 13022 | case ARM::VLDR_FPSCR_post: |
| 13023 | case ARM::VLDR_VPR_post: |
| 13024 | case ARM::VSTR_FPCXTNS_post: |
| 13025 | case ARM::VSTR_FPCXTS_post: |
| 13026 | case ARM::VSTR_FPSCR_post: |
| 13027 | case ARM::VSTR_VPR_post: { |
| 13028 | // op: p |
| 13029 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13030 | Value |= (op & 0xf) << 28; |
| 13031 | // op: addr |
| 13032 | op = getT2ScaledImmOpValue<7,2>(MI, OpIdx: 2, Fixups, STI); |
| 13033 | Value |= (op & 0x80) << 16; |
| 13034 | Value |= (op & 0x7f); |
| 13035 | // op: Rn |
| 13036 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13037 | Value |= (op & 0xf) << 16; |
| 13038 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 13039 | break; |
| 13040 | } |
| 13041 | case ARM::VSHTOH: |
| 13042 | case ARM::VSHTOS: |
| 13043 | case ARM::VSLTOH: |
| 13044 | case ARM::VSLTOS: |
| 13045 | case ARM::VTOSHH: |
| 13046 | case ARM::VTOSHS: |
| 13047 | case ARM::VTOSLH: |
| 13048 | case ARM::VTOSLS: |
| 13049 | case ARM::VTOUHH: |
| 13050 | case ARM::VTOUHS: |
| 13051 | case ARM::VTOULH: |
| 13052 | case ARM::VTOULS: |
| 13053 | case ARM::VUHTOH: |
| 13054 | case ARM::VUHTOS: |
| 13055 | case ARM::VULTOH: |
| 13056 | case ARM::VULTOS: { |
| 13057 | // op: p |
| 13058 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13059 | Value |= (op & 0xf) << 28; |
| 13060 | // op: fbits |
| 13061 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13062 | Value |= (op & 0x1) << 5; |
| 13063 | Value |= (op & 0x1e) >> 1; |
| 13064 | // op: dst |
| 13065 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13066 | Value |= (op & 0x1) << 22; |
| 13067 | Value |= (op & 0x1e) << 11; |
| 13068 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 13069 | break; |
| 13070 | } |
| 13071 | case ARM::VSHTOD: |
| 13072 | case ARM::VSLTOD: |
| 13073 | case ARM::VTOSHD: |
| 13074 | case ARM::VTOSLD: |
| 13075 | case ARM::VTOUHD: |
| 13076 | case ARM::VTOULD: |
| 13077 | case ARM::VUHTOD: |
| 13078 | case ARM::VULTOD: { |
| 13079 | // op: p |
| 13080 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13081 | Value |= (op & 0xf) << 28; |
| 13082 | // op: fbits |
| 13083 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13084 | Value |= (op & 0x1) << 5; |
| 13085 | Value |= (op & 0x1e) >> 1; |
| 13086 | // op: dst |
| 13087 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13088 | Value |= (op & 0x10) << 18; |
| 13089 | Value |= (op & 0xf) << 12; |
| 13090 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 13091 | break; |
| 13092 | } |
| 13093 | case ARM::ADCrr: |
| 13094 | case ARM::ADDrr: |
| 13095 | case ARM::ANDrr: |
| 13096 | case ARM::BICrr: |
| 13097 | case ARM::EORrr: |
| 13098 | case ARM::ORRrr: |
| 13099 | case ARM::RSBrr: |
| 13100 | case ARM::RSCrr: |
| 13101 | case ARM::SBCrr: |
| 13102 | case ARM::SUBrr: { |
| 13103 | // op: p |
| 13104 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13105 | Value |= (op & 0xf) << 28; |
| 13106 | // op: s |
| 13107 | op = getCCOutOpValue(MI, Op: 5, Fixups, STI); |
| 13108 | Value |= (op & 0x1) << 20; |
| 13109 | // op: Rd |
| 13110 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13111 | Value |= (op & 0xf) << 12; |
| 13112 | // op: Rn |
| 13113 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13114 | Value |= (op & 0xf) << 16; |
| 13115 | // op: Rm |
| 13116 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13117 | Value |= (op & 0xf); |
| 13118 | break; |
| 13119 | } |
| 13120 | case ARM::ADCri: |
| 13121 | case ARM::ADDri: |
| 13122 | case ARM::ANDri: |
| 13123 | case ARM::BICri: |
| 13124 | case ARM::EORri: |
| 13125 | case ARM::ORRri: |
| 13126 | case ARM::RSBri: |
| 13127 | case ARM::RSCri: |
| 13128 | case ARM::SBCri: |
| 13129 | case ARM::SUBri: { |
| 13130 | // op: p |
| 13131 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13132 | Value |= (op & 0xf) << 28; |
| 13133 | // op: s |
| 13134 | op = getCCOutOpValue(MI, Op: 5, Fixups, STI); |
| 13135 | Value |= (op & 0x1) << 20; |
| 13136 | // op: Rd |
| 13137 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13138 | Value |= (op & 0xf) << 12; |
| 13139 | // op: Rn |
| 13140 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13141 | Value |= (op & 0xf) << 16; |
| 13142 | // op: imm |
| 13143 | op = getModImmOpValue(MI, Op: 2, Fixups, ST: STI); |
| 13144 | Value |= (op & 0xfff); |
| 13145 | break; |
| 13146 | } |
| 13147 | case ARM::MVNsi: { |
| 13148 | // op: p |
| 13149 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13150 | Value |= (op & 0xf) << 28; |
| 13151 | // op: s |
| 13152 | op = getCCOutOpValue(MI, Op: 5, Fixups, STI); |
| 13153 | Value |= (op & 0x1) << 20; |
| 13154 | // op: Rd |
| 13155 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13156 | Value |= (op & 0xf) << 12; |
| 13157 | // op: shift |
| 13158 | op = getSORegImmOpValue(MI, OpIdx: 1, Fixups, STI); |
| 13159 | Value |= (op & 0xfe0); |
| 13160 | Value |= (op & 0xf); |
| 13161 | break; |
| 13162 | } |
| 13163 | case ARM::MOVsi: { |
| 13164 | // op: p |
| 13165 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13166 | Value |= (op & 0xf) << 28; |
| 13167 | // op: s |
| 13168 | op = getCCOutOpValue(MI, Op: 5, Fixups, STI); |
| 13169 | Value |= (op & 0x1) << 20; |
| 13170 | // op: Rd |
| 13171 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13172 | Value |= (op & 0xf) << 12; |
| 13173 | // op: src |
| 13174 | op = getSORegImmOpValue(MI, OpIdx: 1, Fixups, STI); |
| 13175 | Value |= (op & 0xfe0); |
| 13176 | Value |= (op & 0xf); |
| 13177 | break; |
| 13178 | } |
| 13179 | case ARM::MUL: { |
| 13180 | // op: p |
| 13181 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13182 | Value |= (op & 0xf) << 28; |
| 13183 | // op: s |
| 13184 | op = getCCOutOpValue(MI, Op: 5, Fixups, STI); |
| 13185 | Value |= (op & 0x1) << 20; |
| 13186 | // op: Rd |
| 13187 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13188 | Value |= (op & 0xf) << 16; |
| 13189 | // op: Rm |
| 13190 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13191 | Value |= (op & 0xf) << 8; |
| 13192 | // op: Rn |
| 13193 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13194 | Value |= (op & 0xf); |
| 13195 | break; |
| 13196 | } |
| 13197 | case ARM::VFMAD: |
| 13198 | case ARM::VFMSD: |
| 13199 | case ARM::VFNMAD: |
| 13200 | case ARM::VFNMSD: |
| 13201 | case ARM::VMLAD: |
| 13202 | case ARM::VMLSD: |
| 13203 | case ARM::VNMLAD: |
| 13204 | case ARM::VNMLSD: { |
| 13205 | // op: p |
| 13206 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13207 | Value |= (op & 0xf) << 28; |
| 13208 | // op: Dd |
| 13209 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13210 | Value |= (op & 0x10) << 18; |
| 13211 | Value |= (op & 0xf) << 12; |
| 13212 | // op: Dn |
| 13213 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13214 | Value |= (op & 0xf) << 16; |
| 13215 | Value |= (op & 0x10) << 3; |
| 13216 | // op: Dm |
| 13217 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13218 | Value |= (op & 0x10) << 1; |
| 13219 | Value |= (op & 0xf); |
| 13220 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 13221 | break; |
| 13222 | } |
| 13223 | case ARM::SXTAB: |
| 13224 | case ARM::SXTAB16: |
| 13225 | case ARM::SXTAH: |
| 13226 | case ARM::UXTAB: |
| 13227 | case ARM::UXTAB16: |
| 13228 | case ARM::UXTAH: { |
| 13229 | // op: p |
| 13230 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13231 | Value |= (op & 0xf) << 28; |
| 13232 | // op: Rd |
| 13233 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13234 | Value |= (op & 0xf) << 12; |
| 13235 | // op: Rm |
| 13236 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13237 | Value |= (op & 0xf); |
| 13238 | // op: Rn |
| 13239 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13240 | Value |= (op & 0xf) << 16; |
| 13241 | // op: rot |
| 13242 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13243 | Value |= (op & 0x3) << 10; |
| 13244 | break; |
| 13245 | } |
| 13246 | case ARM::PKHBT: |
| 13247 | case ARM::PKHTB: { |
| 13248 | // op: p |
| 13249 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13250 | Value |= (op & 0xf) << 28; |
| 13251 | // op: Rd |
| 13252 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13253 | Value |= (op & 0xf) << 12; |
| 13254 | // op: Rn |
| 13255 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13256 | Value |= (op & 0xf) << 16; |
| 13257 | // op: Rm |
| 13258 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13259 | Value |= (op & 0xf); |
| 13260 | // op: sh |
| 13261 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13262 | Value |= (op & 0x1f) << 7; |
| 13263 | break; |
| 13264 | } |
| 13265 | case ARM::SBFX: |
| 13266 | case ARM::UBFX: { |
| 13267 | // op: p |
| 13268 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13269 | Value |= (op & 0xf) << 28; |
| 13270 | // op: Rd |
| 13271 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13272 | Value |= (op & 0xf) << 12; |
| 13273 | // op: Rn |
| 13274 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13275 | Value |= (op & 0xf); |
| 13276 | // op: lsb |
| 13277 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13278 | Value |= (op & 0x1f) << 7; |
| 13279 | // op: width |
| 13280 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13281 | Value |= (op & 0x1f) << 16; |
| 13282 | break; |
| 13283 | } |
| 13284 | case ARM::BFI: { |
| 13285 | // op: p |
| 13286 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13287 | Value |= (op & 0xf) << 28; |
| 13288 | // op: Rd |
| 13289 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13290 | Value |= (op & 0xf) << 12; |
| 13291 | // op: Rn |
| 13292 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13293 | Value |= (op & 0xf); |
| 13294 | // op: imm |
| 13295 | op = getBitfieldInvertedMaskOpValue(MI, Op: 3, Fixups, STI); |
| 13296 | Value |= (op & 0x3e0) << 11; |
| 13297 | Value |= (op & 0x1f) << 7; |
| 13298 | break; |
| 13299 | } |
| 13300 | case ARM::SSAT: |
| 13301 | case ARM::USAT: { |
| 13302 | // op: p |
| 13303 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13304 | Value |= (op & 0xf) << 28; |
| 13305 | // op: Rd |
| 13306 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13307 | Value |= (op & 0xf) << 12; |
| 13308 | // op: sat_imm |
| 13309 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13310 | Value |= (op & 0x1f) << 16; |
| 13311 | // op: Rn |
| 13312 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13313 | Value |= (op & 0xf); |
| 13314 | // op: sh |
| 13315 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13316 | Value |= (op & 0x1f) << 7; |
| 13317 | Value |= (op & 0x20) << 1; |
| 13318 | break; |
| 13319 | } |
| 13320 | case ARM::MLS: { |
| 13321 | // op: p |
| 13322 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13323 | Value |= (op & 0xf) << 28; |
| 13324 | // op: Rd |
| 13325 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13326 | Value |= (op & 0xf) << 16; |
| 13327 | // op: Rm |
| 13328 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13329 | Value |= (op & 0xf) << 8; |
| 13330 | // op: Rn |
| 13331 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13332 | Value |= (op & 0xf); |
| 13333 | // op: Ra |
| 13334 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13335 | Value |= (op & 0xf) << 12; |
| 13336 | break; |
| 13337 | } |
| 13338 | case ARM::SMMLA: |
| 13339 | case ARM::SMMLAR: |
| 13340 | case ARM::SMMLS: |
| 13341 | case ARM::SMMLSR: |
| 13342 | case ARM::USADA8: { |
| 13343 | // op: p |
| 13344 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13345 | Value |= (op & 0xf) << 28; |
| 13346 | // op: Rd |
| 13347 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13348 | Value |= (op & 0xf) << 16; |
| 13349 | // op: Rn |
| 13350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13351 | Value |= (op & 0xf); |
| 13352 | // op: Rm |
| 13353 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13354 | Value |= (op & 0xf) << 8; |
| 13355 | // op: Ra |
| 13356 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13357 | Value |= (op & 0xf) << 12; |
| 13358 | break; |
| 13359 | } |
| 13360 | case ARM::CMNzrsr: |
| 13361 | case ARM::CMPrsr: |
| 13362 | case ARM::TEQrsr: |
| 13363 | case ARM::TSTrsr: { |
| 13364 | // op: p |
| 13365 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13366 | Value |= (op & 0xf) << 28; |
| 13367 | // op: Rn |
| 13368 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13369 | Value |= (op & 0xf) << 16; |
| 13370 | // op: shift |
| 13371 | op = getSORegRegOpValue(MI, OpIdx: 1, Fixups, STI); |
| 13372 | Value |= (op & 0xf00); |
| 13373 | Value |= (op & 0x60); |
| 13374 | Value |= (op & 0xf); |
| 13375 | break; |
| 13376 | } |
| 13377 | case ARM::SMLAD: |
| 13378 | case ARM::SMLADX: |
| 13379 | case ARM::SMLSD: |
| 13380 | case ARM::SMLSDX: { |
| 13381 | // op: p |
| 13382 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13383 | Value |= (op & 0xf) << 28; |
| 13384 | // op: Rn |
| 13385 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13386 | Value |= (op & 0xf); |
| 13387 | // op: Rm |
| 13388 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13389 | Value |= (op & 0xf) << 8; |
| 13390 | // op: Ra |
| 13391 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13392 | Value |= (op & 0xf) << 12; |
| 13393 | // op: Rd |
| 13394 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13395 | Value |= (op & 0xf) << 16; |
| 13396 | break; |
| 13397 | } |
| 13398 | case ARM::SMLABB: |
| 13399 | case ARM::SMLABT: |
| 13400 | case ARM::SMLATB: |
| 13401 | case ARM::SMLATT: |
| 13402 | case ARM::SMLAWB: |
| 13403 | case ARM::SMLAWT: { |
| 13404 | // op: p |
| 13405 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13406 | Value |= (op & 0xf) << 28; |
| 13407 | // op: Rn |
| 13408 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13409 | Value |= (op & 0xf); |
| 13410 | // op: Rm |
| 13411 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13412 | Value |= (op & 0xf) << 8; |
| 13413 | // op: Rd |
| 13414 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13415 | Value |= (op & 0xf) << 16; |
| 13416 | // op: Ra |
| 13417 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13418 | Value |= (op & 0xf) << 12; |
| 13419 | break; |
| 13420 | } |
| 13421 | case ARM::LDRB_PRE_IMM: |
| 13422 | case ARM::LDR_PRE_IMM: { |
| 13423 | // op: p |
| 13424 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13425 | Value |= (op & 0xf) << 28; |
| 13426 | // op: Rt |
| 13427 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13428 | Value |= (op & 0xf) << 12; |
| 13429 | // op: addr |
| 13430 | op = getAddrModeImm12OpValue(MI, OpIdx: 2, Fixups, STI); |
| 13431 | Value |= (op & 0x1000) << 11; |
| 13432 | Value |= (op & 0x1e000) << 3; |
| 13433 | Value |= (op & 0xfff); |
| 13434 | break; |
| 13435 | } |
| 13436 | case ARM::LDRBrs: |
| 13437 | case ARM::LDRrs: |
| 13438 | case ARM::STRBrs: |
| 13439 | case ARM::STRrs: { |
| 13440 | // op: p |
| 13441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13442 | Value |= (op & 0xf) << 28; |
| 13443 | // op: Rt |
| 13444 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13445 | Value |= (op & 0xf) << 12; |
| 13446 | // op: shift |
| 13447 | op = getLdStSORegOpValue(MI, OpIdx: 1, Fixups, STI); |
| 13448 | Value |= (op & 0x1000) << 11; |
| 13449 | Value |= (op & 0x1e000) << 3; |
| 13450 | Value |= (op & 0xfe0); |
| 13451 | Value |= (op & 0xf); |
| 13452 | break; |
| 13453 | } |
| 13454 | case ARM::STRB_PRE_IMM: |
| 13455 | case ARM::STR_PRE_IMM: { |
| 13456 | // op: p |
| 13457 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13458 | Value |= (op & 0xf) << 28; |
| 13459 | // op: Rt |
| 13460 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13461 | Value |= (op & 0xf) << 12; |
| 13462 | // op: addr |
| 13463 | op = getAddrModeImm12OpValue(MI, OpIdx: 2, Fixups, STI); |
| 13464 | Value |= (op & 0x1000) << 11; |
| 13465 | Value |= (op & 0x1e000) << 3; |
| 13466 | Value |= (op & 0xfff); |
| 13467 | break; |
| 13468 | } |
| 13469 | case ARM::VFMAH: |
| 13470 | case ARM::VFMAS: |
| 13471 | case ARM::VFMSH: |
| 13472 | case ARM::VFMSS: |
| 13473 | case ARM::VFNMAH: |
| 13474 | case ARM::VFNMAS: |
| 13475 | case ARM::VFNMSH: |
| 13476 | case ARM::VFNMSS: |
| 13477 | case ARM::VMLAH: |
| 13478 | case ARM::VMLAS: |
| 13479 | case ARM::VMLSH: |
| 13480 | case ARM::VMLSS: |
| 13481 | case ARM::VNMLAH: |
| 13482 | case ARM::VNMLAS: |
| 13483 | case ARM::VNMLSH: |
| 13484 | case ARM::VNMLSS: { |
| 13485 | // op: p |
| 13486 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13487 | Value |= (op & 0xf) << 28; |
| 13488 | // op: Sd |
| 13489 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13490 | Value |= (op & 0x1) << 22; |
| 13491 | Value |= (op & 0x1e) << 11; |
| 13492 | // op: Sn |
| 13493 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13494 | Value |= (op & 0x1e) << 15; |
| 13495 | Value |= (op & 0x1) << 7; |
| 13496 | // op: Sm |
| 13497 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13498 | Value |= (op & 0x1) << 5; |
| 13499 | Value |= (op & 0x1e) >> 1; |
| 13500 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 13501 | break; |
| 13502 | } |
| 13503 | case ARM::LDRH: |
| 13504 | case ARM::LDRSB: |
| 13505 | case ARM::LDRSH: |
| 13506 | case ARM::STRH: { |
| 13507 | // op: p |
| 13508 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13509 | Value |= (op & 0xf) << 28; |
| 13510 | // op: addr |
| 13511 | op = getAddrMode3OpValue(MI, OpIdx: 1, Fixups, STI); |
| 13512 | Value |= (op & 0x100) << 15; |
| 13513 | Value |= (op & 0x2000) << 9; |
| 13514 | Value |= (op & 0x1e00) << 7; |
| 13515 | Value |= (op & 0xf0) << 4; |
| 13516 | Value |= (op & 0xf); |
| 13517 | // op: Rt |
| 13518 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13519 | Value |= (op & 0xf) << 12; |
| 13520 | break; |
| 13521 | } |
| 13522 | case ARM::LDCL_OFFSET: |
| 13523 | case ARM::LDCL_PRE: |
| 13524 | case ARM::LDC_OFFSET: |
| 13525 | case ARM::LDC_PRE: |
| 13526 | case ARM::STCL_OFFSET: |
| 13527 | case ARM::STCL_PRE: |
| 13528 | case ARM::STC_OFFSET: |
| 13529 | case ARM::STC_PRE: { |
| 13530 | // op: p |
| 13531 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13532 | Value |= (op & 0xf) << 28; |
| 13533 | // op: addr |
| 13534 | op = getAddrMode5OpValue(MI, OpIdx: 2, Fixups, STI); |
| 13535 | Value |= (op & 0x100) << 15; |
| 13536 | Value |= (op & 0x1e00) << 7; |
| 13537 | Value |= (op & 0xff); |
| 13538 | // op: cop |
| 13539 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13540 | Value |= (op & 0xf) << 8; |
| 13541 | // op: CRd |
| 13542 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13543 | Value |= (op & 0xf) << 12; |
| 13544 | break; |
| 13545 | } |
| 13546 | case ARM::LDRHTi: |
| 13547 | case ARM::LDRSBTi: |
| 13548 | case ARM::LDRSHTi: { |
| 13549 | // op: p |
| 13550 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13551 | Value |= (op & 0xf) << 28; |
| 13552 | // op: addr |
| 13553 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13554 | Value |= (op & 0xf) << 16; |
| 13555 | // op: Rt |
| 13556 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13557 | Value |= (op & 0xf) << 12; |
| 13558 | // op: offset |
| 13559 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13560 | Value |= (op & 0x100) << 15; |
| 13561 | Value |= (op & 0xf0) << 4; |
| 13562 | Value |= (op & 0xf); |
| 13563 | break; |
| 13564 | } |
| 13565 | case ARM::STRHTi: { |
| 13566 | // op: p |
| 13567 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13568 | Value |= (op & 0xf) << 28; |
| 13569 | // op: addr |
| 13570 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13571 | Value |= (op & 0xf) << 16; |
| 13572 | // op: Rt |
| 13573 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13574 | Value |= (op & 0xf) << 12; |
| 13575 | // op: offset |
| 13576 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13577 | Value |= (op & 0x100) << 15; |
| 13578 | Value |= (op & 0xf0) << 4; |
| 13579 | Value |= (op & 0xf); |
| 13580 | break; |
| 13581 | } |
| 13582 | case ARM::VLDR_FPSCR_NZCVQC_pre: |
| 13583 | case ARM::VLDR_P0_pre: |
| 13584 | case ARM::VSTR_FPSCR_NZCVQC_pre: |
| 13585 | case ARM::VSTR_P0_pre: { |
| 13586 | // op: p |
| 13587 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13588 | Value |= (op & 0xf) << 28; |
| 13589 | // op: addr |
| 13590 | op = getT2AddrModeImm7s4OpValue(MI, OpIdx: 2, Fixups, STI); |
| 13591 | Value |= (op & 0x80) << 16; |
| 13592 | Value |= (op & 0xf00) << 8; |
| 13593 | Value |= (op & 0x7f); |
| 13594 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 13595 | break; |
| 13596 | } |
| 13597 | case ARM::VLDR_FPSCR_NZCVQC_post: |
| 13598 | case ARM::VLDR_P0_post: |
| 13599 | case ARM::VSTR_FPSCR_NZCVQC_post: |
| 13600 | case ARM::VSTR_P0_post: { |
| 13601 | // op: p |
| 13602 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13603 | Value |= (op & 0xf) << 28; |
| 13604 | // op: addr |
| 13605 | op = getT2ScaledImmOpValue<7,2>(MI, OpIdx: 3, Fixups, STI); |
| 13606 | Value |= (op & 0x80) << 16; |
| 13607 | Value |= (op & 0x7f); |
| 13608 | // op: Rn |
| 13609 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13610 | Value |= (op & 0xf) << 16; |
| 13611 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 13612 | break; |
| 13613 | } |
| 13614 | case ARM::VMOVSRR: { |
| 13615 | // op: p |
| 13616 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13617 | Value |= (op & 0xf) << 28; |
| 13618 | // op: dst1 |
| 13619 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13620 | Value |= (op & 0x1) << 5; |
| 13621 | Value |= (op & 0x1e) >> 1; |
| 13622 | // op: src1 |
| 13623 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13624 | Value |= (op & 0xf) << 12; |
| 13625 | // op: src2 |
| 13626 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13627 | Value |= (op & 0xf) << 16; |
| 13628 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 13629 | break; |
| 13630 | } |
| 13631 | case ARM::LDCL_POST: |
| 13632 | case ARM::LDC_POST: |
| 13633 | case ARM::STCL_POST: |
| 13634 | case ARM::STC_POST: { |
| 13635 | // op: p |
| 13636 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13637 | Value |= (op & 0xf) << 28; |
| 13638 | // op: offset |
| 13639 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13640 | Value |= (op & 0x100) << 15; |
| 13641 | Value |= (op & 0xff); |
| 13642 | // op: addr |
| 13643 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13644 | Value |= (op & 0xf) << 16; |
| 13645 | // op: cop |
| 13646 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13647 | Value |= (op & 0xf) << 8; |
| 13648 | // op: CRd |
| 13649 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13650 | Value |= (op & 0xf) << 12; |
| 13651 | break; |
| 13652 | } |
| 13653 | case ARM::LDCL_OPTION: |
| 13654 | case ARM::LDC_OPTION: |
| 13655 | case ARM::STCL_OPTION: |
| 13656 | case ARM::STC_OPTION: { |
| 13657 | // op: p |
| 13658 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13659 | Value |= (op & 0xf) << 28; |
| 13660 | // op: option |
| 13661 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13662 | Value |= (op & 0xff); |
| 13663 | // op: addr |
| 13664 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13665 | Value |= (op & 0xf) << 16; |
| 13666 | // op: cop |
| 13667 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13668 | Value |= (op & 0xf) << 8; |
| 13669 | // op: CRd |
| 13670 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13671 | Value |= (op & 0xf) << 12; |
| 13672 | break; |
| 13673 | } |
| 13674 | case ARM::ADCrsi: |
| 13675 | case ARM::ADDrsi: |
| 13676 | case ARM::ANDrsi: |
| 13677 | case ARM::BICrsi: |
| 13678 | case ARM::EORrsi: |
| 13679 | case ARM::ORRrsi: |
| 13680 | case ARM::RSBrsi: |
| 13681 | case ARM::RSCrsi: |
| 13682 | case ARM::SBCrsi: |
| 13683 | case ARM::SUBrsi: { |
| 13684 | // op: p |
| 13685 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13686 | Value |= (op & 0xf) << 28; |
| 13687 | // op: s |
| 13688 | op = getCCOutOpValue(MI, Op: 6, Fixups, STI); |
| 13689 | Value |= (op & 0x1) << 20; |
| 13690 | // op: Rd |
| 13691 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13692 | Value |= (op & 0xf) << 12; |
| 13693 | // op: Rn |
| 13694 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13695 | Value |= (op & 0xf) << 16; |
| 13696 | // op: shift |
| 13697 | op = getSORegImmOpValue(MI, OpIdx: 2, Fixups, STI); |
| 13698 | Value |= (op & 0xfe0); |
| 13699 | Value |= (op & 0xf); |
| 13700 | break; |
| 13701 | } |
| 13702 | case ARM::MVNsr: { |
| 13703 | // op: p |
| 13704 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13705 | Value |= (op & 0xf) << 28; |
| 13706 | // op: s |
| 13707 | op = getCCOutOpValue(MI, Op: 6, Fixups, STI); |
| 13708 | Value |= (op & 0x1) << 20; |
| 13709 | // op: Rd |
| 13710 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13711 | Value |= (op & 0xf) << 12; |
| 13712 | // op: shift |
| 13713 | op = getSORegRegOpValue(MI, OpIdx: 1, Fixups, STI); |
| 13714 | Value |= (op & 0xf00); |
| 13715 | Value |= (op & 0x60); |
| 13716 | Value |= (op & 0xf); |
| 13717 | break; |
| 13718 | } |
| 13719 | case ARM::MOVsr: { |
| 13720 | // op: p |
| 13721 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13722 | Value |= (op & 0xf) << 28; |
| 13723 | // op: s |
| 13724 | op = getCCOutOpValue(MI, Op: 6, Fixups, STI); |
| 13725 | Value |= (op & 0x1) << 20; |
| 13726 | // op: Rd |
| 13727 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13728 | Value |= (op & 0xf) << 12; |
| 13729 | // op: src |
| 13730 | op = getSORegRegOpValue(MI, OpIdx: 1, Fixups, STI); |
| 13731 | Value |= (op & 0xf00); |
| 13732 | Value |= (op & 0x60); |
| 13733 | Value |= (op & 0xf); |
| 13734 | break; |
| 13735 | } |
| 13736 | case ARM::MLA: { |
| 13737 | // op: p |
| 13738 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13739 | Value |= (op & 0xf) << 28; |
| 13740 | // op: s |
| 13741 | op = getCCOutOpValue(MI, Op: 6, Fixups, STI); |
| 13742 | Value |= (op & 0x1) << 20; |
| 13743 | // op: Rd |
| 13744 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13745 | Value |= (op & 0xf) << 16; |
| 13746 | // op: Rm |
| 13747 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13748 | Value |= (op & 0xf) << 8; |
| 13749 | // op: Rn |
| 13750 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13751 | Value |= (op & 0xf); |
| 13752 | // op: Ra |
| 13753 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13754 | Value |= (op & 0xf) << 12; |
| 13755 | break; |
| 13756 | } |
| 13757 | case ARM::SMULL: |
| 13758 | case ARM::UMULL: { |
| 13759 | // op: p |
| 13760 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13761 | Value |= (op & 0xf) << 28; |
| 13762 | // op: s |
| 13763 | op = getCCOutOpValue(MI, Op: 6, Fixups, STI); |
| 13764 | Value |= (op & 0x1) << 20; |
| 13765 | // op: RdLo |
| 13766 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13767 | Value |= (op & 0xf) << 12; |
| 13768 | // op: RdHi |
| 13769 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13770 | Value |= (op & 0xf) << 16; |
| 13771 | // op: Rm |
| 13772 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13773 | Value |= (op & 0xf) << 8; |
| 13774 | // op: Rn |
| 13775 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13776 | Value |= (op & 0xf); |
| 13777 | break; |
| 13778 | } |
| 13779 | case ARM::VMOVRRS: { |
| 13780 | // op: p |
| 13781 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13782 | Value |= (op & 0xf) << 28; |
| 13783 | // op: src1 |
| 13784 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13785 | Value |= (op & 0x1) << 5; |
| 13786 | Value |= (op & 0x1e) >> 1; |
| 13787 | // op: Rt |
| 13788 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13789 | Value |= (op & 0xf) << 12; |
| 13790 | // op: Rt2 |
| 13791 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13792 | Value |= (op & 0xf) << 16; |
| 13793 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 13794 | break; |
| 13795 | } |
| 13796 | case ARM::MRRC: { |
| 13797 | // op: p |
| 13798 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13799 | Value |= (op & 0xf) << 28; |
| 13800 | // op: Rt |
| 13801 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13802 | Value |= (op & 0xf) << 12; |
| 13803 | // op: Rt2 |
| 13804 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13805 | Value |= (op & 0xf) << 16; |
| 13806 | // op: cop |
| 13807 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13808 | Value |= (op & 0xf) << 8; |
| 13809 | // op: opc1 |
| 13810 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13811 | Value |= (op & 0xf) << 4; |
| 13812 | // op: CRm |
| 13813 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13814 | Value |= (op & 0xf); |
| 13815 | break; |
| 13816 | } |
| 13817 | case ARM::LDRH_PRE: |
| 13818 | case ARM::LDRSB_PRE: |
| 13819 | case ARM::LDRSH_PRE: { |
| 13820 | // op: p |
| 13821 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13822 | Value |= (op & 0xf) << 28; |
| 13823 | // op: Rt |
| 13824 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13825 | Value |= (op & 0xf) << 12; |
| 13826 | // op: addr |
| 13827 | op = getAddrMode3OpValue(MI, OpIdx: 2, Fixups, STI); |
| 13828 | Value |= (op & 0x100) << 15; |
| 13829 | Value |= (op & 0x2000) << 9; |
| 13830 | Value |= (op & 0x1e00) << 7; |
| 13831 | Value |= (op & 0xf0) << 4; |
| 13832 | Value |= (op & 0xf); |
| 13833 | break; |
| 13834 | } |
| 13835 | case ARM::LDRB_PRE_REG: |
| 13836 | case ARM::LDR_PRE_REG: { |
| 13837 | // op: p |
| 13838 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13839 | Value |= (op & 0xf) << 28; |
| 13840 | // op: Rt |
| 13841 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13842 | Value |= (op & 0xf) << 12; |
| 13843 | // op: addr |
| 13844 | op = getLdStSORegOpValue(MI, OpIdx: 2, Fixups, STI); |
| 13845 | Value |= (op & 0x1000) << 11; |
| 13846 | Value |= (op & 0x1e000) << 3; |
| 13847 | Value |= (op & 0xfe0); |
| 13848 | Value |= (op & 0xf); |
| 13849 | break; |
| 13850 | } |
| 13851 | case ARM::LDRBT_POST_REG: |
| 13852 | case ARM::LDRB_POST_REG: |
| 13853 | case ARM::LDRT_POST_REG: |
| 13854 | case ARM::LDR_POST_REG: { |
| 13855 | // op: p |
| 13856 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13857 | Value |= (op & 0xf) << 28; |
| 13858 | // op: Rt |
| 13859 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13860 | Value |= (op & 0xf) << 12; |
| 13861 | // op: offset |
| 13862 | op = getAddrMode2OffsetOpValue(MI, OpIdx: 3, Fixups, STI); |
| 13863 | Value |= (op & 0x1000) << 11; |
| 13864 | Value |= (op & 0xfe0); |
| 13865 | Value |= (op & 0xf); |
| 13866 | // op: addr |
| 13867 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13868 | Value |= (op & 0xf) << 16; |
| 13869 | break; |
| 13870 | } |
| 13871 | case ARM::LDRBT_POST_IMM: |
| 13872 | case ARM::LDRB_POST_IMM: |
| 13873 | case ARM::LDRT_POST_IMM: |
| 13874 | case ARM::LDR_POST_IMM: { |
| 13875 | // op: p |
| 13876 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13877 | Value |= (op & 0xf) << 28; |
| 13878 | // op: Rt |
| 13879 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13880 | Value |= (op & 0xf) << 12; |
| 13881 | // op: offset |
| 13882 | op = getAddrMode2OffsetOpValue(MI, OpIdx: 3, Fixups, STI); |
| 13883 | Value |= (op & 0x1000) << 11; |
| 13884 | Value |= (op & 0xfff); |
| 13885 | // op: addr |
| 13886 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13887 | Value |= (op & 0xf) << 16; |
| 13888 | break; |
| 13889 | } |
| 13890 | case ARM::LDRH_POST: |
| 13891 | case ARM::LDRSB_POST: |
| 13892 | case ARM::LDRSH_POST: { |
| 13893 | // op: p |
| 13894 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13895 | Value |= (op & 0xf) << 28; |
| 13896 | // op: Rt |
| 13897 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13898 | Value |= (op & 0xf) << 12; |
| 13899 | // op: offset |
| 13900 | op = getAddrMode3OffsetOpValue(MI, OpIdx: 3, Fixups, STI); |
| 13901 | Value |= (op & 0x100) << 15; |
| 13902 | Value |= (op & 0x200) << 13; |
| 13903 | Value |= (op & 0xf0) << 4; |
| 13904 | Value |= (op & 0xf); |
| 13905 | // op: addr |
| 13906 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13907 | Value |= (op & 0xf) << 16; |
| 13908 | break; |
| 13909 | } |
| 13910 | case ARM::STRH_PRE: { |
| 13911 | // op: p |
| 13912 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13913 | Value |= (op & 0xf) << 28; |
| 13914 | // op: Rt |
| 13915 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13916 | Value |= (op & 0xf) << 12; |
| 13917 | // op: addr |
| 13918 | op = getAddrMode3OpValue(MI, OpIdx: 2, Fixups, STI); |
| 13919 | Value |= (op & 0x100) << 15; |
| 13920 | Value |= (op & 0x2000) << 9; |
| 13921 | Value |= (op & 0x1e00) << 7; |
| 13922 | Value |= (op & 0xf0) << 4; |
| 13923 | Value |= (op & 0xf); |
| 13924 | break; |
| 13925 | } |
| 13926 | case ARM::STRB_PRE_REG: |
| 13927 | case ARM::STR_PRE_REG: { |
| 13928 | // op: p |
| 13929 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13930 | Value |= (op & 0xf) << 28; |
| 13931 | // op: Rt |
| 13932 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13933 | Value |= (op & 0xf) << 12; |
| 13934 | // op: addr |
| 13935 | op = getLdStSORegOpValue(MI, OpIdx: 2, Fixups, STI); |
| 13936 | Value |= (op & 0x1000) << 11; |
| 13937 | Value |= (op & 0x1e000) << 3; |
| 13938 | Value |= (op & 0xfe0); |
| 13939 | Value |= (op & 0xf); |
| 13940 | break; |
| 13941 | } |
| 13942 | case ARM::STRBT_POST_REG: |
| 13943 | case ARM::STRB_POST_REG: |
| 13944 | case ARM::STRT_POST_REG: |
| 13945 | case ARM::STR_POST_REG: { |
| 13946 | // op: p |
| 13947 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13948 | Value |= (op & 0xf) << 28; |
| 13949 | // op: Rt |
| 13950 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13951 | Value |= (op & 0xf) << 12; |
| 13952 | // op: offset |
| 13953 | op = getAddrMode2OffsetOpValue(MI, OpIdx: 3, Fixups, STI); |
| 13954 | Value |= (op & 0x1000) << 11; |
| 13955 | Value |= (op & 0xfe0); |
| 13956 | Value |= (op & 0xf); |
| 13957 | // op: addr |
| 13958 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13959 | Value |= (op & 0xf) << 16; |
| 13960 | break; |
| 13961 | } |
| 13962 | case ARM::STRBT_POST_IMM: |
| 13963 | case ARM::STRB_POST_IMM: |
| 13964 | case ARM::STRT_POST_IMM: |
| 13965 | case ARM::STR_POST_IMM: { |
| 13966 | // op: p |
| 13967 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13968 | Value |= (op & 0xf) << 28; |
| 13969 | // op: Rt |
| 13970 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13971 | Value |= (op & 0xf) << 12; |
| 13972 | // op: offset |
| 13973 | op = getAddrMode2OffsetOpValue(MI, OpIdx: 3, Fixups, STI); |
| 13974 | Value |= (op & 0x1000) << 11; |
| 13975 | Value |= (op & 0xfff); |
| 13976 | // op: addr |
| 13977 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13978 | Value |= (op & 0xf) << 16; |
| 13979 | break; |
| 13980 | } |
| 13981 | case ARM::STRH_POST: { |
| 13982 | // op: p |
| 13983 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13984 | Value |= (op & 0xf) << 28; |
| 13985 | // op: Rt |
| 13986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13987 | Value |= (op & 0xf) << 12; |
| 13988 | // op: offset |
| 13989 | op = getAddrMode3OffsetOpValue(MI, OpIdx: 3, Fixups, STI); |
| 13990 | Value |= (op & 0x100) << 15; |
| 13991 | Value |= (op & 0x200) << 13; |
| 13992 | Value |= (op & 0xf0) << 4; |
| 13993 | Value |= (op & 0xf); |
| 13994 | // op: addr |
| 13995 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13996 | Value |= (op & 0xf) << 16; |
| 13997 | break; |
| 13998 | } |
| 13999 | case ARM::MCRR: { |
| 14000 | // op: p |
| 14001 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 14002 | Value |= (op & 0xf) << 28; |
| 14003 | // op: Rt |
| 14004 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14005 | Value |= (op & 0xf) << 12; |
| 14006 | // op: Rt2 |
| 14007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14008 | Value |= (op & 0xf) << 16; |
| 14009 | // op: cop |
| 14010 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14011 | Value |= (op & 0xf) << 8; |
| 14012 | // op: opc1 |
| 14013 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14014 | Value |= (op & 0xf) << 4; |
| 14015 | // op: CRm |
| 14016 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 14017 | Value |= (op & 0xf); |
| 14018 | break; |
| 14019 | } |
| 14020 | case ARM::LDRD: |
| 14021 | case ARM::STRD: { |
| 14022 | // op: p |
| 14023 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 14024 | Value |= (op & 0xf) << 28; |
| 14025 | // op: addr |
| 14026 | op = getAddrMode3OpValue(MI, OpIdx: 2, Fixups, STI); |
| 14027 | Value |= (op & 0x100) << 15; |
| 14028 | Value |= (op & 0x2000) << 9; |
| 14029 | Value |= (op & 0x1e00) << 7; |
| 14030 | Value |= (op & 0xf0) << 4; |
| 14031 | Value |= (op & 0xf); |
| 14032 | // op: Rt |
| 14033 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14034 | Value |= (op & 0xf) << 12; |
| 14035 | break; |
| 14036 | } |
| 14037 | case ARM::LDRHTr: |
| 14038 | case ARM::LDRSBTr: |
| 14039 | case ARM::LDRSHTr: { |
| 14040 | // op: p |
| 14041 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 14042 | Value |= (op & 0xf) << 28; |
| 14043 | // op: addr |
| 14044 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14045 | Value |= (op & 0xf) << 16; |
| 14046 | // op: Rt |
| 14047 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14048 | Value |= (op & 0xf) << 12; |
| 14049 | // op: Rm |
| 14050 | op = getPostIdxRegOpValue(MI, OpIdx: 3, Fixups, STI); |
| 14051 | Value |= (op & 0x10) << 19; |
| 14052 | Value |= (op & 0xf); |
| 14053 | break; |
| 14054 | } |
| 14055 | case ARM::STRHTr: { |
| 14056 | // op: p |
| 14057 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 14058 | Value |= (op & 0xf) << 28; |
| 14059 | // op: addr |
| 14060 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14061 | Value |= (op & 0xf) << 16; |
| 14062 | // op: Rt |
| 14063 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14064 | Value |= (op & 0xf) << 12; |
| 14065 | // op: Rm |
| 14066 | op = getPostIdxRegOpValue(MI, OpIdx: 3, Fixups, STI); |
| 14067 | Value |= (op & 0x10) << 19; |
| 14068 | Value |= (op & 0xf); |
| 14069 | break; |
| 14070 | } |
| 14071 | case ARM::ADCrsr: |
| 14072 | case ARM::ADDrsr: |
| 14073 | case ARM::ANDrsr: |
| 14074 | case ARM::BICrsr: |
| 14075 | case ARM::EORrsr: |
| 14076 | case ARM::ORRrsr: |
| 14077 | case ARM::RSBrsr: |
| 14078 | case ARM::RSCrsr: |
| 14079 | case ARM::SBCrsr: |
| 14080 | case ARM::SUBrsr: { |
| 14081 | // op: p |
| 14082 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 14083 | Value |= (op & 0xf) << 28; |
| 14084 | // op: s |
| 14085 | op = getCCOutOpValue(MI, Op: 7, Fixups, STI); |
| 14086 | Value |= (op & 0x1) << 20; |
| 14087 | // op: Rd |
| 14088 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14089 | Value |= (op & 0xf) << 12; |
| 14090 | // op: Rn |
| 14091 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14092 | Value |= (op & 0xf) << 16; |
| 14093 | // op: shift |
| 14094 | op = getSORegRegOpValue(MI, OpIdx: 2, Fixups, STI); |
| 14095 | Value |= (op & 0xf00); |
| 14096 | Value |= (op & 0x60); |
| 14097 | Value |= (op & 0xf); |
| 14098 | break; |
| 14099 | } |
| 14100 | case ARM::UMAAL: { |
| 14101 | // op: p |
| 14102 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 14103 | Value |= (op & 0xf) << 28; |
| 14104 | // op: RdLo |
| 14105 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14106 | Value |= (op & 0xf) << 12; |
| 14107 | // op: RdHi |
| 14108 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14109 | Value |= (op & 0xf) << 16; |
| 14110 | // op: Rm |
| 14111 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14112 | Value |= (op & 0xf) << 8; |
| 14113 | // op: Rn |
| 14114 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14115 | Value |= (op & 0xf); |
| 14116 | break; |
| 14117 | } |
| 14118 | case ARM::SMLALBB: |
| 14119 | case ARM::SMLALBT: |
| 14120 | case ARM::SMLALD: |
| 14121 | case ARM::SMLALDX: |
| 14122 | case ARM::SMLALTB: |
| 14123 | case ARM::SMLALTT: |
| 14124 | case ARM::SMLSLD: |
| 14125 | case ARM::SMLSLDX: { |
| 14126 | // op: p |
| 14127 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 14128 | Value |= (op & 0xf) << 28; |
| 14129 | // op: Rn |
| 14130 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14131 | Value |= (op & 0xf); |
| 14132 | // op: Rm |
| 14133 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14134 | Value |= (op & 0xf) << 8; |
| 14135 | // op: RdLo |
| 14136 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14137 | Value |= (op & 0xf) << 12; |
| 14138 | // op: RdHi |
| 14139 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14140 | Value |= (op & 0xf) << 16; |
| 14141 | break; |
| 14142 | } |
| 14143 | case ARM::LDRD_PRE: { |
| 14144 | // op: p |
| 14145 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 14146 | Value |= (op & 0xf) << 28; |
| 14147 | // op: Rt |
| 14148 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14149 | Value |= (op & 0xf) << 12; |
| 14150 | // op: addr |
| 14151 | op = getAddrMode3OpValue(MI, OpIdx: 3, Fixups, STI); |
| 14152 | Value |= (op & 0x100) << 15; |
| 14153 | Value |= (op & 0x2000) << 9; |
| 14154 | Value |= (op & 0x1e00) << 7; |
| 14155 | Value |= (op & 0xf0) << 4; |
| 14156 | Value |= (op & 0xf); |
| 14157 | break; |
| 14158 | } |
| 14159 | case ARM::MRC: { |
| 14160 | // op: p |
| 14161 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 14162 | Value |= (op & 0xf) << 28; |
| 14163 | // op: Rt |
| 14164 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14165 | Value |= (op & 0xf) << 12; |
| 14166 | // op: cop |
| 14167 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14168 | Value |= (op & 0xf) << 8; |
| 14169 | // op: opc1 |
| 14170 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14171 | Value |= (op & 0x7) << 21; |
| 14172 | // op: opc2 |
| 14173 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 14174 | Value |= (op & 0x7) << 5; |
| 14175 | // op: CRm |
| 14176 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 14177 | Value |= (op & 0xf); |
| 14178 | // op: CRn |
| 14179 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14180 | Value |= (op & 0xf) << 16; |
| 14181 | break; |
| 14182 | } |
| 14183 | case ARM::LDRD_POST: { |
| 14184 | // op: p |
| 14185 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 14186 | Value |= (op & 0xf) << 28; |
| 14187 | // op: Rt |
| 14188 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14189 | Value |= (op & 0xf) << 12; |
| 14190 | // op: offset |
| 14191 | op = getAddrMode3OffsetOpValue(MI, OpIdx: 4, Fixups, STI); |
| 14192 | Value |= (op & 0x100) << 15; |
| 14193 | Value |= (op & 0x200) << 13; |
| 14194 | Value |= (op & 0xf0) << 4; |
| 14195 | Value |= (op & 0xf); |
| 14196 | // op: addr |
| 14197 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14198 | Value |= (op & 0xf) << 16; |
| 14199 | break; |
| 14200 | } |
| 14201 | case ARM::STRD_PRE: { |
| 14202 | // op: p |
| 14203 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 14204 | Value |= (op & 0xf) << 28; |
| 14205 | // op: Rt |
| 14206 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14207 | Value |= (op & 0xf) << 12; |
| 14208 | // op: addr |
| 14209 | op = getAddrMode3OpValue(MI, OpIdx: 3, Fixups, STI); |
| 14210 | Value |= (op & 0x100) << 15; |
| 14211 | Value |= (op & 0x2000) << 9; |
| 14212 | Value |= (op & 0x1e00) << 7; |
| 14213 | Value |= (op & 0xf0) << 4; |
| 14214 | Value |= (op & 0xf); |
| 14215 | break; |
| 14216 | } |
| 14217 | case ARM::STRD_POST: { |
| 14218 | // op: p |
| 14219 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 14220 | Value |= (op & 0xf) << 28; |
| 14221 | // op: Rt |
| 14222 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14223 | Value |= (op & 0xf) << 12; |
| 14224 | // op: offset |
| 14225 | op = getAddrMode3OffsetOpValue(MI, OpIdx: 4, Fixups, STI); |
| 14226 | Value |= (op & 0x100) << 15; |
| 14227 | Value |= (op & 0x200) << 13; |
| 14228 | Value |= (op & 0xf0) << 4; |
| 14229 | Value |= (op & 0xf); |
| 14230 | // op: addr |
| 14231 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14232 | Value |= (op & 0xf) << 16; |
| 14233 | break; |
| 14234 | } |
| 14235 | case ARM::MCR: { |
| 14236 | // op: p |
| 14237 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 14238 | Value |= (op & 0xf) << 28; |
| 14239 | // op: Rt |
| 14240 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14241 | Value |= (op & 0xf) << 12; |
| 14242 | // op: cop |
| 14243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14244 | Value |= (op & 0xf) << 8; |
| 14245 | // op: opc1 |
| 14246 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14247 | Value |= (op & 0x7) << 21; |
| 14248 | // op: opc2 |
| 14249 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 14250 | Value |= (op & 0x7) << 5; |
| 14251 | // op: CRm |
| 14252 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 14253 | Value |= (op & 0xf); |
| 14254 | // op: CRn |
| 14255 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14256 | Value |= (op & 0xf) << 16; |
| 14257 | break; |
| 14258 | } |
| 14259 | case ARM::CDP: { |
| 14260 | // op: p |
| 14261 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 14262 | Value |= (op & 0xf) << 28; |
| 14263 | // op: opc1 |
| 14264 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14265 | Value |= (op & 0xf) << 20; |
| 14266 | // op: CRn |
| 14267 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14268 | Value |= (op & 0xf) << 16; |
| 14269 | // op: CRd |
| 14270 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14271 | Value |= (op & 0xf) << 12; |
| 14272 | // op: cop |
| 14273 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14274 | Value |= (op & 0xf) << 8; |
| 14275 | // op: opc2 |
| 14276 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 14277 | Value |= (op & 0x7) << 5; |
| 14278 | // op: CRm |
| 14279 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 14280 | Value |= (op & 0xf); |
| 14281 | break; |
| 14282 | } |
| 14283 | case ARM::SMLAL: |
| 14284 | case ARM::UMLAL: { |
| 14285 | // op: p |
| 14286 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 14287 | Value |= (op & 0xf) << 28; |
| 14288 | // op: s |
| 14289 | op = getCCOutOpValue(MI, Op: 8, Fixups, STI); |
| 14290 | Value |= (op & 0x1) << 20; |
| 14291 | // op: RdLo |
| 14292 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14293 | Value |= (op & 0xf) << 12; |
| 14294 | // op: RdHi |
| 14295 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14296 | Value |= (op & 0xf) << 16; |
| 14297 | // op: Rm |
| 14298 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14299 | Value |= (op & 0xf) << 8; |
| 14300 | // op: Rn |
| 14301 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14302 | Value |= (op & 0xf); |
| 14303 | break; |
| 14304 | } |
| 14305 | case ARM::VSCCLRMS: { |
| 14306 | // op: regs |
| 14307 | op = getRegisterListOpValue(MI, Op: 2, Fixups, STI); |
| 14308 | Value |= (op & 0x100) << 14; |
| 14309 | Value |= (op & 0x1e00) << 3; |
| 14310 | Value |= (op & 0xff); |
| 14311 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 14312 | break; |
| 14313 | } |
| 14314 | case ARM::VSCCLRMD: { |
| 14315 | // op: regs |
| 14316 | op = getRegisterListOpValue(MI, Op: 2, Fixups, STI); |
| 14317 | Value |= (op & 0x1000) << 10; |
| 14318 | Value |= (op & 0xf00) << 4; |
| 14319 | Value |= (op & 0xfe); |
| 14320 | Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI); |
| 14321 | break; |
| 14322 | } |
| 14323 | case ARM::tPUSH: { |
| 14324 | // op: regs |
| 14325 | op = getRegisterListOpValue(MI, Op: 2, Fixups, STI); |
| 14326 | Value |= (op & 0x4000) >> 6; |
| 14327 | Value |= (op & 0xff); |
| 14328 | break; |
| 14329 | } |
| 14330 | case ARM::tPOP: { |
| 14331 | // op: regs |
| 14332 | op = getRegisterListOpValue(MI, Op: 2, Fixups, STI); |
| 14333 | Value |= (op & 0x8000) >> 7; |
| 14334 | Value |= (op & 0xff); |
| 14335 | break; |
| 14336 | } |
| 14337 | case ARM::t2CLRM: { |
| 14338 | // op: regs |
| 14339 | op = getRegisterListOpValue(MI, Op: 2, Fixups, STI); |
| 14340 | Value |= (op & 0xc000); |
| 14341 | Value |= (op & 0x1fff); |
| 14342 | break; |
| 14343 | } |
| 14344 | case ARM::t2MOVr: |
| 14345 | case ARM::t2MVNr: |
| 14346 | case ARM::t2RRX: { |
| 14347 | // op: s |
| 14348 | op = getCCOutOpValue(MI, Op: 4, Fixups, STI); |
| 14349 | Value |= (op & 0x1) << 20; |
| 14350 | // op: Rd |
| 14351 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14352 | Value |= (op & 0xf) << 8; |
| 14353 | // op: Rm |
| 14354 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14355 | Value |= (op & 0xf); |
| 14356 | break; |
| 14357 | } |
| 14358 | case ARM::t2MOVi: |
| 14359 | case ARM::t2MVNi: { |
| 14360 | // op: s |
| 14361 | op = getCCOutOpValue(MI, Op: 4, Fixups, STI); |
| 14362 | Value |= (op & 0x1) << 20; |
| 14363 | // op: Rd |
| 14364 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14365 | Value |= (op & 0xf) << 8; |
| 14366 | // op: imm |
| 14367 | op = getT2SOImmOpValue(MI, Op: 1, Fixups, STI); |
| 14368 | Value |= (op & 0x800) << 15; |
| 14369 | Value |= (op & 0x700) << 4; |
| 14370 | Value |= (op & 0xff); |
| 14371 | break; |
| 14372 | } |
| 14373 | case ARM::t2ASRri: |
| 14374 | case ARM::t2LSLri: |
| 14375 | case ARM::t2LSRri: |
| 14376 | case ARM::t2RORri: { |
| 14377 | // op: s |
| 14378 | op = getCCOutOpValue(MI, Op: 5, Fixups, STI); |
| 14379 | Value |= (op & 0x1) << 20; |
| 14380 | // op: Rd |
| 14381 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14382 | Value |= (op & 0xf) << 8; |
| 14383 | // op: Rm |
| 14384 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14385 | Value |= (op & 0xf); |
| 14386 | // op: imm |
| 14387 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14388 | Value |= (op & 0x1c) << 10; |
| 14389 | Value |= (op & 0x3) << 6; |
| 14390 | break; |
| 14391 | } |
| 14392 | case ARM::t2ADCrr: |
| 14393 | case ARM::t2ADDrr: |
| 14394 | case ARM::t2ANDrr: |
| 14395 | case ARM::t2ASRrr: |
| 14396 | case ARM::t2BICrr: |
| 14397 | case ARM::t2EORrr: |
| 14398 | case ARM::t2LSLrr: |
| 14399 | case ARM::t2LSRrr: |
| 14400 | case ARM::t2ORNrr: |
| 14401 | case ARM::t2ORRrr: |
| 14402 | case ARM::t2RORrr: |
| 14403 | case ARM::t2RSBrr: |
| 14404 | case ARM::t2SBCrr: |
| 14405 | case ARM::t2SUBrr: { |
| 14406 | // op: s |
| 14407 | op = getCCOutOpValue(MI, Op: 5, Fixups, STI); |
| 14408 | Value |= (op & 0x1) << 20; |
| 14409 | // op: Rd |
| 14410 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14411 | Value |= (op & 0xf) << 8; |
| 14412 | // op: Rn |
| 14413 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14414 | Value |= (op & 0xf) << 16; |
| 14415 | // op: Rm |
| 14416 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14417 | Value |= (op & 0xf); |
| 14418 | break; |
| 14419 | } |
| 14420 | case ARM::t2ADCri: |
| 14421 | case ARM::t2ADDri: |
| 14422 | case ARM::t2ANDri: |
| 14423 | case ARM::t2BICri: |
| 14424 | case ARM::t2EORri: |
| 14425 | case ARM::t2ORNri: |
| 14426 | case ARM::t2ORRri: |
| 14427 | case ARM::t2RSBri: |
| 14428 | case ARM::t2SBCri: |
| 14429 | case ARM::t2SUBri: { |
| 14430 | // op: s |
| 14431 | op = getCCOutOpValue(MI, Op: 5, Fixups, STI); |
| 14432 | Value |= (op & 0x1) << 20; |
| 14433 | // op: Rd |
| 14434 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14435 | Value |= (op & 0xf) << 8; |
| 14436 | // op: Rn |
| 14437 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14438 | Value |= (op & 0xf) << 16; |
| 14439 | // op: imm |
| 14440 | op = getT2SOImmOpValue(MI, Op: 2, Fixups, STI); |
| 14441 | Value |= (op & 0x800) << 15; |
| 14442 | Value |= (op & 0x700) << 4; |
| 14443 | Value |= (op & 0xff); |
| 14444 | break; |
| 14445 | } |
| 14446 | case ARM::t2MVNs: { |
| 14447 | // op: s |
| 14448 | op = getCCOutOpValue(MI, Op: 5, Fixups, STI); |
| 14449 | Value |= (op & 0x1) << 20; |
| 14450 | // op: Rd |
| 14451 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14452 | Value |= (op & 0xf) << 8; |
| 14453 | // op: ShiftedRm |
| 14454 | op = getT2SORegOpValue(MI, OpIdx: 1, Fixups, STI); |
| 14455 | Value |= (op & 0xe00) << 3; |
| 14456 | Value |= (op & 0x1e0) >> 1; |
| 14457 | Value |= (op & 0xf); |
| 14458 | break; |
| 14459 | } |
| 14460 | case ARM::t2ADDspImm: |
| 14461 | case ARM::t2SUBspImm: { |
| 14462 | // op: s |
| 14463 | op = getCCOutOpValue(MI, Op: 5, Fixups, STI); |
| 14464 | Value |= (op & 0x1) << 20; |
| 14465 | // op: imm |
| 14466 | op = getT2SOImmOpValue(MI, Op: 2, Fixups, STI); |
| 14467 | Value |= (op & 0x800) << 15; |
| 14468 | Value |= (op & 0x700) << 4; |
| 14469 | Value |= (op & 0xff); |
| 14470 | break; |
| 14471 | } |
| 14472 | case ARM::t2ADCrs: |
| 14473 | case ARM::t2ADDrs: |
| 14474 | case ARM::t2ANDrs: |
| 14475 | case ARM::t2BICrs: |
| 14476 | case ARM::t2EORrs: |
| 14477 | case ARM::t2ORNrs: |
| 14478 | case ARM::t2ORRrs: |
| 14479 | case ARM::t2RSBrs: |
| 14480 | case ARM::t2SBCrs: |
| 14481 | case ARM::t2SUBrs: { |
| 14482 | // op: s |
| 14483 | op = getCCOutOpValue(MI, Op: 6, Fixups, STI); |
| 14484 | Value |= (op & 0x1) << 20; |
| 14485 | // op: Rd |
| 14486 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14487 | Value |= (op & 0xf) << 8; |
| 14488 | // op: Rn |
| 14489 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14490 | Value |= (op & 0xf) << 16; |
| 14491 | // op: ShiftedRm |
| 14492 | op = getT2SORegOpValue(MI, OpIdx: 2, Fixups, STI); |
| 14493 | Value |= (op & 0xe00) << 3; |
| 14494 | Value |= (op & 0x1e0) >> 1; |
| 14495 | Value |= (op & 0xf); |
| 14496 | break; |
| 14497 | } |
| 14498 | case ARM::PLDWrs: |
| 14499 | case ARM::PLDrs: |
| 14500 | case ARM::PLIrs: { |
| 14501 | // op: shift |
| 14502 | op = getLdStSORegOpValue(MI, OpIdx: 0, Fixups, STI); |
| 14503 | Value |= (op & 0x1000) << 11; |
| 14504 | Value |= (op & 0x1e000) << 3; |
| 14505 | Value |= (op & 0xfe0); |
| 14506 | Value |= (op & 0xf); |
| 14507 | break; |
| 14508 | } |
| 14509 | case ARM::BLXi: { |
| 14510 | // op: target |
| 14511 | op = getARMBLXTargetOpValue(MI, OpIdx: 0, Fixups, STI); |
| 14512 | Value |= (op & 0x1) << 24; |
| 14513 | Value |= (op & 0x1fffffe) >> 1; |
| 14514 | break; |
| 14515 | } |
| 14516 | case ARM::tB: { |
| 14517 | // op: target |
| 14518 | op = getThumbBRTargetOpValue(MI, OpIdx: 0, Fixups, STI); |
| 14519 | Value |= (op & 0x7ff); |
| 14520 | break; |
| 14521 | } |
| 14522 | case ARM::t2B: { |
| 14523 | // op: target |
| 14524 | op = getThumbBranchTargetOpValue(MI, OpIdx: 0, Fixups, STI); |
| 14525 | Value |= (op & 0x800000) << 3; |
| 14526 | Value |= (op & 0x1ff800) << 5; |
| 14527 | Value |= (op & 0x400000) >> 9; |
| 14528 | Value |= (op & 0x200000) >> 10; |
| 14529 | Value |= (op & 0x7ff); |
| 14530 | break; |
| 14531 | } |
| 14532 | case ARM::tCBNZ: |
| 14533 | case ARM::tCBZ: { |
| 14534 | // op: target |
| 14535 | op = getThumbCBTargetOpValue(MI, OpIdx: 1, Fixups, STI); |
| 14536 | Value |= (op & 0x20) << 4; |
| 14537 | Value |= (op & 0x1f) << 3; |
| 14538 | // op: Rn |
| 14539 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14540 | Value |= (op & 0x7); |
| 14541 | break; |
| 14542 | } |
| 14543 | case ARM::tHLT: { |
| 14544 | // op: val |
| 14545 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14546 | Value |= (op & 0x3f); |
| 14547 | break; |
| 14548 | } |
| 14549 | case ARM::tBKPT: { |
| 14550 | // op: val |
| 14551 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14552 | Value |= (op & 0xff); |
| 14553 | break; |
| 14554 | } |
| 14555 | case ARM::BKPT: |
| 14556 | case ARM::HLT: { |
| 14557 | // op: val |
| 14558 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14559 | Value |= (op & 0xfff0) << 4; |
| 14560 | Value |= (op & 0xf); |
| 14561 | break; |
| 14562 | } |
| 14563 | default: |
| 14564 | reportUnsupportedInst(Inst: MI); |
| 14565 | } |
| 14566 | return Value; |
| 14567 | } |
| 14568 | |
| 14569 | #ifdef GET_OPERAND_BIT_OFFSET |
| 14570 | #undef GET_OPERAND_BIT_OFFSET |
| 14571 | |
| 14572 | uint32_t ARMMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
| 14573 | unsigned OpNum, |
| 14574 | const MCSubtargetInfo &STI) const { |
| 14575 | switch (MI.getOpcode()) { |
| 14576 | case ARM::CLREX: |
| 14577 | case ARM::MVE_LCTP: |
| 14578 | case ARM::MVE_VPNOT: |
| 14579 | case ARM::SB: |
| 14580 | case ARM::TRAP: |
| 14581 | case ARM::TSB: |
| 14582 | case ARM::VBSPd: |
| 14583 | case ARM::VBSPq: |
| 14584 | case ARM::VLD1LNq16Pseudo: |
| 14585 | case ARM::VLD1LNq16Pseudo_UPD: |
| 14586 | case ARM::VLD1LNq32Pseudo: |
| 14587 | case ARM::VLD1LNq32Pseudo_UPD: |
| 14588 | case ARM::VLD1LNq8Pseudo: |
| 14589 | case ARM::VLD1LNq8Pseudo_UPD: |
| 14590 | case ARM::VLD1d16QPseudo: |
| 14591 | case ARM::VLD1d16QPseudoWB_fixed: |
| 14592 | case ARM::VLD1d16QPseudoWB_register: |
| 14593 | case ARM::VLD1d16TPseudo: |
| 14594 | case ARM::VLD1d16TPseudoWB_fixed: |
| 14595 | case ARM::VLD1d16TPseudoWB_register: |
| 14596 | case ARM::VLD1d32QPseudo: |
| 14597 | case ARM::VLD1d32QPseudoWB_fixed: |
| 14598 | case ARM::VLD1d32QPseudoWB_register: |
| 14599 | case ARM::VLD1d32TPseudo: |
| 14600 | case ARM::VLD1d32TPseudoWB_fixed: |
| 14601 | case ARM::VLD1d32TPseudoWB_register: |
| 14602 | case ARM::VLD1d64QPseudo: |
| 14603 | case ARM::VLD1d64QPseudoWB_fixed: |
| 14604 | case ARM::VLD1d64QPseudoWB_register: |
| 14605 | case ARM::VLD1d64TPseudo: |
| 14606 | case ARM::VLD1d64TPseudoWB_fixed: |
| 14607 | case ARM::VLD1d64TPseudoWB_register: |
| 14608 | case ARM::VLD1d8QPseudo: |
| 14609 | case ARM::VLD1d8QPseudoWB_fixed: |
| 14610 | case ARM::VLD1d8QPseudoWB_register: |
| 14611 | case ARM::VLD1d8TPseudo: |
| 14612 | case ARM::VLD1d8TPseudoWB_fixed: |
| 14613 | case ARM::VLD1d8TPseudoWB_register: |
| 14614 | case ARM::VLD1q16HighQPseudo: |
| 14615 | case ARM::VLD1q16HighQPseudo_UPD: |
| 14616 | case ARM::VLD1q16HighTPseudo: |
| 14617 | case ARM::VLD1q16HighTPseudo_UPD: |
| 14618 | case ARM::VLD1q16LowQPseudo_UPD: |
| 14619 | case ARM::VLD1q16LowTPseudo_UPD: |
| 14620 | case ARM::VLD1q32HighQPseudo: |
| 14621 | case ARM::VLD1q32HighQPseudo_UPD: |
| 14622 | case ARM::VLD1q32HighTPseudo: |
| 14623 | case ARM::VLD1q32HighTPseudo_UPD: |
| 14624 | case ARM::VLD1q32LowQPseudo_UPD: |
| 14625 | case ARM::VLD1q32LowTPseudo_UPD: |
| 14626 | case ARM::VLD1q64HighQPseudo: |
| 14627 | case ARM::VLD1q64HighQPseudo_UPD: |
| 14628 | case ARM::VLD1q64HighTPseudo: |
| 14629 | case ARM::VLD1q64HighTPseudo_UPD: |
| 14630 | case ARM::VLD1q64LowQPseudo_UPD: |
| 14631 | case ARM::VLD1q64LowTPseudo_UPD: |
| 14632 | case ARM::VLD1q8HighQPseudo: |
| 14633 | case ARM::VLD1q8HighQPseudo_UPD: |
| 14634 | case ARM::VLD1q8HighTPseudo: |
| 14635 | case ARM::VLD1q8HighTPseudo_UPD: |
| 14636 | case ARM::VLD1q8LowQPseudo_UPD: |
| 14637 | case ARM::VLD1q8LowTPseudo_UPD: |
| 14638 | case ARM::VLD2DUPq16EvenPseudo: |
| 14639 | case ARM::VLD2DUPq16OddPseudo: |
| 14640 | case ARM::VLD2DUPq16OddPseudoWB_fixed: |
| 14641 | case ARM::VLD2DUPq16OddPseudoWB_register: |
| 14642 | case ARM::VLD2DUPq32EvenPseudo: |
| 14643 | case ARM::VLD2DUPq32OddPseudo: |
| 14644 | case ARM::VLD2DUPq32OddPseudoWB_fixed: |
| 14645 | case ARM::VLD2DUPq32OddPseudoWB_register: |
| 14646 | case ARM::VLD2DUPq8EvenPseudo: |
| 14647 | case ARM::VLD2DUPq8OddPseudo: |
| 14648 | case ARM::VLD2DUPq8OddPseudoWB_fixed: |
| 14649 | case ARM::VLD2DUPq8OddPseudoWB_register: |
| 14650 | case ARM::VLD2LNd16Pseudo: |
| 14651 | case ARM::VLD2LNd16Pseudo_UPD: |
| 14652 | case ARM::VLD2LNd32Pseudo: |
| 14653 | case ARM::VLD2LNd32Pseudo_UPD: |
| 14654 | case ARM::VLD2LNd8Pseudo: |
| 14655 | case ARM::VLD2LNd8Pseudo_UPD: |
| 14656 | case ARM::VLD2LNq16Pseudo: |
| 14657 | case ARM::VLD2LNq16Pseudo_UPD: |
| 14658 | case ARM::VLD2LNq32Pseudo: |
| 14659 | case ARM::VLD2LNq32Pseudo_UPD: |
| 14660 | case ARM::VLD2q16Pseudo: |
| 14661 | case ARM::VLD2q16PseudoWB_fixed: |
| 14662 | case ARM::VLD2q16PseudoWB_register: |
| 14663 | case ARM::VLD2q32Pseudo: |
| 14664 | case ARM::VLD2q32PseudoWB_fixed: |
| 14665 | case ARM::VLD2q32PseudoWB_register: |
| 14666 | case ARM::VLD2q8Pseudo: |
| 14667 | case ARM::VLD2q8PseudoWB_fixed: |
| 14668 | case ARM::VLD2q8PseudoWB_register: |
| 14669 | case ARM::VLD3DUPd16Pseudo: |
| 14670 | case ARM::VLD3DUPd16Pseudo_UPD: |
| 14671 | case ARM::VLD3DUPd32Pseudo: |
| 14672 | case ARM::VLD3DUPd32Pseudo_UPD: |
| 14673 | case ARM::VLD3DUPd8Pseudo: |
| 14674 | case ARM::VLD3DUPd8Pseudo_UPD: |
| 14675 | case ARM::VLD3DUPq16EvenPseudo: |
| 14676 | case ARM::VLD3DUPq16OddPseudo: |
| 14677 | case ARM::VLD3DUPq16OddPseudo_UPD: |
| 14678 | case ARM::VLD3DUPq32EvenPseudo: |
| 14679 | case ARM::VLD3DUPq32OddPseudo: |
| 14680 | case ARM::VLD3DUPq32OddPseudo_UPD: |
| 14681 | case ARM::VLD3DUPq8EvenPseudo: |
| 14682 | case ARM::VLD3DUPq8OddPseudo: |
| 14683 | case ARM::VLD3DUPq8OddPseudo_UPD: |
| 14684 | case ARM::VLD3LNd16Pseudo: |
| 14685 | case ARM::VLD3LNd16Pseudo_UPD: |
| 14686 | case ARM::VLD3LNd32Pseudo: |
| 14687 | case ARM::VLD3LNd32Pseudo_UPD: |
| 14688 | case ARM::VLD3LNd8Pseudo: |
| 14689 | case ARM::VLD3LNd8Pseudo_UPD: |
| 14690 | case ARM::VLD3LNq16Pseudo: |
| 14691 | case ARM::VLD3LNq16Pseudo_UPD: |
| 14692 | case ARM::VLD3LNq32Pseudo: |
| 14693 | case ARM::VLD3LNq32Pseudo_UPD: |
| 14694 | case ARM::VLD3d16Pseudo: |
| 14695 | case ARM::VLD3d16Pseudo_UPD: |
| 14696 | case ARM::VLD3d32Pseudo: |
| 14697 | case ARM::VLD3d32Pseudo_UPD: |
| 14698 | case ARM::VLD3d8Pseudo: |
| 14699 | case ARM::VLD3d8Pseudo_UPD: |
| 14700 | case ARM::VLD3q16Pseudo_UPD: |
| 14701 | case ARM::VLD3q16oddPseudo: |
| 14702 | case ARM::VLD3q16oddPseudo_UPD: |
| 14703 | case ARM::VLD3q32Pseudo_UPD: |
| 14704 | case ARM::VLD3q32oddPseudo: |
| 14705 | case ARM::VLD3q32oddPseudo_UPD: |
| 14706 | case ARM::VLD3q8Pseudo_UPD: |
| 14707 | case ARM::VLD3q8oddPseudo: |
| 14708 | case ARM::VLD3q8oddPseudo_UPD: |
| 14709 | case ARM::VLD4DUPd16Pseudo: |
| 14710 | case ARM::VLD4DUPd16Pseudo_UPD: |
| 14711 | case ARM::VLD4DUPd32Pseudo: |
| 14712 | case ARM::VLD4DUPd32Pseudo_UPD: |
| 14713 | case ARM::VLD4DUPd8Pseudo: |
| 14714 | case ARM::VLD4DUPd8Pseudo_UPD: |
| 14715 | case ARM::VLD4DUPq16EvenPseudo: |
| 14716 | case ARM::VLD4DUPq16OddPseudo: |
| 14717 | case ARM::VLD4DUPq16OddPseudo_UPD: |
| 14718 | case ARM::VLD4DUPq32EvenPseudo: |
| 14719 | case ARM::VLD4DUPq32OddPseudo: |
| 14720 | case ARM::VLD4DUPq32OddPseudo_UPD: |
| 14721 | case ARM::VLD4DUPq8EvenPseudo: |
| 14722 | case ARM::VLD4DUPq8OddPseudo: |
| 14723 | case ARM::VLD4DUPq8OddPseudo_UPD: |
| 14724 | case ARM::VLD4LNd16Pseudo: |
| 14725 | case ARM::VLD4LNd16Pseudo_UPD: |
| 14726 | case ARM::VLD4LNd32Pseudo: |
| 14727 | case ARM::VLD4LNd32Pseudo_UPD: |
| 14728 | case ARM::VLD4LNd8Pseudo: |
| 14729 | case ARM::VLD4LNd8Pseudo_UPD: |
| 14730 | case ARM::VLD4LNq16Pseudo: |
| 14731 | case ARM::VLD4LNq16Pseudo_UPD: |
| 14732 | case ARM::VLD4LNq32Pseudo: |
| 14733 | case ARM::VLD4LNq32Pseudo_UPD: |
| 14734 | case ARM::VLD4d16Pseudo: |
| 14735 | case ARM::VLD4d16Pseudo_UPD: |
| 14736 | case ARM::VLD4d32Pseudo: |
| 14737 | case ARM::VLD4d32Pseudo_UPD: |
| 14738 | case ARM::VLD4d8Pseudo: |
| 14739 | case ARM::VLD4d8Pseudo_UPD: |
| 14740 | case ARM::VLD4q16Pseudo_UPD: |
| 14741 | case ARM::VLD4q16oddPseudo: |
| 14742 | case ARM::VLD4q16oddPseudo_UPD: |
| 14743 | case ARM::VLD4q32Pseudo_UPD: |
| 14744 | case ARM::VLD4q32oddPseudo: |
| 14745 | case ARM::VLD4q32oddPseudo_UPD: |
| 14746 | case ARM::VLD4q8Pseudo_UPD: |
| 14747 | case ARM::VLD4q8oddPseudo: |
| 14748 | case ARM::VLD4q8oddPseudo_UPD: |
| 14749 | case ARM::VLDMQIA: |
| 14750 | case ARM::VST1LNq16Pseudo: |
| 14751 | case ARM::VST1LNq16Pseudo_UPD: |
| 14752 | case ARM::VST1LNq32Pseudo: |
| 14753 | case ARM::VST1LNq32Pseudo_UPD: |
| 14754 | case ARM::VST1LNq8Pseudo: |
| 14755 | case ARM::VST1LNq8Pseudo_UPD: |
| 14756 | case ARM::VST1d16QPseudo: |
| 14757 | case ARM::VST1d16QPseudoWB_fixed: |
| 14758 | case ARM::VST1d16QPseudoWB_register: |
| 14759 | case ARM::VST1d16TPseudo: |
| 14760 | case ARM::VST1d16TPseudoWB_fixed: |
| 14761 | case ARM::VST1d16TPseudoWB_register: |
| 14762 | case ARM::VST1d32QPseudo: |
| 14763 | case ARM::VST1d32QPseudoWB_fixed: |
| 14764 | case ARM::VST1d32QPseudoWB_register: |
| 14765 | case ARM::VST1d32TPseudo: |
| 14766 | case ARM::VST1d32TPseudoWB_fixed: |
| 14767 | case ARM::VST1d32TPseudoWB_register: |
| 14768 | case ARM::VST1d64QPseudo: |
| 14769 | case ARM::VST1d64QPseudoWB_fixed: |
| 14770 | case ARM::VST1d64QPseudoWB_register: |
| 14771 | case ARM::VST1d64TPseudo: |
| 14772 | case ARM::VST1d64TPseudoWB_fixed: |
| 14773 | case ARM::VST1d64TPseudoWB_register: |
| 14774 | case ARM::VST1d8QPseudo: |
| 14775 | case ARM::VST1d8QPseudoWB_fixed: |
| 14776 | case ARM::VST1d8QPseudoWB_register: |
| 14777 | case ARM::VST1d8TPseudo: |
| 14778 | case ARM::VST1d8TPseudoWB_fixed: |
| 14779 | case ARM::VST1d8TPseudoWB_register: |
| 14780 | case ARM::VST1q16HighQPseudo: |
| 14781 | case ARM::VST1q16HighQPseudo_UPD: |
| 14782 | case ARM::VST1q16HighTPseudo: |
| 14783 | case ARM::VST1q16HighTPseudo_UPD: |
| 14784 | case ARM::VST1q16LowQPseudo_UPD: |
| 14785 | case ARM::VST1q16LowTPseudo_UPD: |
| 14786 | case ARM::VST1q32HighQPseudo: |
| 14787 | case ARM::VST1q32HighQPseudo_UPD: |
| 14788 | case ARM::VST1q32HighTPseudo: |
| 14789 | case ARM::VST1q32HighTPseudo_UPD: |
| 14790 | case ARM::VST1q32LowQPseudo_UPD: |
| 14791 | case ARM::VST1q32LowTPseudo_UPD: |
| 14792 | case ARM::VST1q64HighQPseudo: |
| 14793 | case ARM::VST1q64HighQPseudo_UPD: |
| 14794 | case ARM::VST1q64HighTPseudo: |
| 14795 | case ARM::VST1q64HighTPseudo_UPD: |
| 14796 | case ARM::VST1q64LowQPseudo_UPD: |
| 14797 | case ARM::VST1q64LowTPseudo_UPD: |
| 14798 | case ARM::VST1q8HighQPseudo: |
| 14799 | case ARM::VST1q8HighQPseudo_UPD: |
| 14800 | case ARM::VST1q8HighTPseudo: |
| 14801 | case ARM::VST1q8HighTPseudo_UPD: |
| 14802 | case ARM::VST1q8LowQPseudo_UPD: |
| 14803 | case ARM::VST1q8LowTPseudo_UPD: |
| 14804 | case ARM::VST2LNd16Pseudo: |
| 14805 | case ARM::VST2LNd16Pseudo_UPD: |
| 14806 | case ARM::VST2LNd32Pseudo: |
| 14807 | case ARM::VST2LNd32Pseudo_UPD: |
| 14808 | case ARM::VST2LNd8Pseudo: |
| 14809 | case ARM::VST2LNd8Pseudo_UPD: |
| 14810 | case ARM::VST2LNq16Pseudo: |
| 14811 | case ARM::VST2LNq16Pseudo_UPD: |
| 14812 | case ARM::VST2LNq32Pseudo: |
| 14813 | case ARM::VST2LNq32Pseudo_UPD: |
| 14814 | case ARM::VST2q16Pseudo: |
| 14815 | case ARM::VST2q16PseudoWB_fixed: |
| 14816 | case ARM::VST2q16PseudoWB_register: |
| 14817 | case ARM::VST2q32Pseudo: |
| 14818 | case ARM::VST2q32PseudoWB_fixed: |
| 14819 | case ARM::VST2q32PseudoWB_register: |
| 14820 | case ARM::VST2q8Pseudo: |
| 14821 | case ARM::VST2q8PseudoWB_fixed: |
| 14822 | case ARM::VST2q8PseudoWB_register: |
| 14823 | case ARM::VST3LNd16Pseudo: |
| 14824 | case ARM::VST3LNd16Pseudo_UPD: |
| 14825 | case ARM::VST3LNd32Pseudo: |
| 14826 | case ARM::VST3LNd32Pseudo_UPD: |
| 14827 | case ARM::VST3LNd8Pseudo: |
| 14828 | case ARM::VST3LNd8Pseudo_UPD: |
| 14829 | case ARM::VST3LNq16Pseudo: |
| 14830 | case ARM::VST3LNq16Pseudo_UPD: |
| 14831 | case ARM::VST3LNq32Pseudo: |
| 14832 | case ARM::VST3LNq32Pseudo_UPD: |
| 14833 | case ARM::VST3d16Pseudo: |
| 14834 | case ARM::VST3d16Pseudo_UPD: |
| 14835 | case ARM::VST3d32Pseudo: |
| 14836 | case ARM::VST3d32Pseudo_UPD: |
| 14837 | case ARM::VST3d8Pseudo: |
| 14838 | case ARM::VST3d8Pseudo_UPD: |
| 14839 | case ARM::VST3q16Pseudo_UPD: |
| 14840 | case ARM::VST3q16oddPseudo: |
| 14841 | case ARM::VST3q16oddPseudo_UPD: |
| 14842 | case ARM::VST3q32Pseudo_UPD: |
| 14843 | case ARM::VST3q32oddPseudo: |
| 14844 | case ARM::VST3q32oddPseudo_UPD: |
| 14845 | case ARM::VST3q8Pseudo_UPD: |
| 14846 | case ARM::VST3q8oddPseudo: |
| 14847 | case ARM::VST3q8oddPseudo_UPD: |
| 14848 | case ARM::VST4LNd16Pseudo: |
| 14849 | case ARM::VST4LNd16Pseudo_UPD: |
| 14850 | case ARM::VST4LNd32Pseudo: |
| 14851 | case ARM::VST4LNd32Pseudo_UPD: |
| 14852 | case ARM::VST4LNd8Pseudo: |
| 14853 | case ARM::VST4LNd8Pseudo_UPD: |
| 14854 | case ARM::VST4LNq16Pseudo: |
| 14855 | case ARM::VST4LNq16Pseudo_UPD: |
| 14856 | case ARM::VST4LNq32Pseudo: |
| 14857 | case ARM::VST4LNq32Pseudo_UPD: |
| 14858 | case ARM::VST4d16Pseudo: |
| 14859 | case ARM::VST4d16Pseudo_UPD: |
| 14860 | case ARM::VST4d32Pseudo: |
| 14861 | case ARM::VST4d32Pseudo_UPD: |
| 14862 | case ARM::VST4d8Pseudo: |
| 14863 | case ARM::VST4d8Pseudo_UPD: |
| 14864 | case ARM::VST4q16Pseudo_UPD: |
| 14865 | case ARM::VST4q16oddPseudo: |
| 14866 | case ARM::VST4q16oddPseudo_UPD: |
| 14867 | case ARM::VST4q32Pseudo_UPD: |
| 14868 | case ARM::VST4q32oddPseudo: |
| 14869 | case ARM::VST4q32oddPseudo_UPD: |
| 14870 | case ARM::VST4q8Pseudo_UPD: |
| 14871 | case ARM::VST4q8oddPseudo: |
| 14872 | case ARM::VST4q8oddPseudo_UPD: |
| 14873 | case ARM::VSTMQIA: |
| 14874 | case ARM::VTBL3Pseudo: |
| 14875 | case ARM::VTBL4Pseudo: |
| 14876 | case ARM::VTBX3Pseudo: |
| 14877 | case ARM::VTBX4Pseudo: |
| 14878 | case ARM::t2AUT: |
| 14879 | case ARM::t2BTI: |
| 14880 | case ARM::t2CLREX: |
| 14881 | case ARM::t2DCPS1: |
| 14882 | case ARM::t2DCPS2: |
| 14883 | case ARM::t2DCPS3: |
| 14884 | case ARM::t2Int_eh_sjlj_setjmp: |
| 14885 | case ARM::t2Int_eh_sjlj_setjmp_nofp: |
| 14886 | case ARM::t2PAC: |
| 14887 | case ARM::t2PACBTI: |
| 14888 | case ARM::t2SB: |
| 14889 | case ARM::t2SG: |
| 14890 | case ARM::t2TSB: |
| 14891 | case ARM::tInt_WIN_eh_sjlj_longjmp: |
| 14892 | case ARM::tInt_eh_sjlj_longjmp: |
| 14893 | case ARM::tInt_eh_sjlj_setjmp: |
| 14894 | case ARM::tTRAP: |
| 14895 | case ARM::t__brkdiv0: { |
| 14896 | break; |
| 14897 | } |
| 14898 | case ARM::VRINTAD: |
| 14899 | case ARM::VRINTMD: |
| 14900 | case ARM::VRINTND: |
| 14901 | case ARM::VRINTPD: { |
| 14902 | switch (OpNum) { |
| 14903 | case 0: |
| 14904 | // op: Dd |
| 14905 | return 12; |
| 14906 | case 1: |
| 14907 | // op: Dm |
| 14908 | return 0; |
| 14909 | } |
| 14910 | break; |
| 14911 | } |
| 14912 | case ARM::VFP_VMAXNMD: |
| 14913 | case ARM::VFP_VMINNMD: |
| 14914 | case ARM::VSELEQD: |
| 14915 | case ARM::VSELGED: |
| 14916 | case ARM::VSELGTD: |
| 14917 | case ARM::VSELVSD: { |
| 14918 | switch (OpNum) { |
| 14919 | case 0: |
| 14920 | // op: Dd |
| 14921 | return 12; |
| 14922 | case 1: |
| 14923 | // op: Dn |
| 14924 | return 7; |
| 14925 | case 2: |
| 14926 | // op: Dm |
| 14927 | return 0; |
| 14928 | } |
| 14929 | break; |
| 14930 | } |
| 14931 | case ARM::MVE_VPST: { |
| 14932 | switch (OpNum) { |
| 14933 | case 0: |
| 14934 | // op: Mk |
| 14935 | return 13; |
| 14936 | } |
| 14937 | break; |
| 14938 | } |
| 14939 | case ARM::MVE_VQRSHL_by_vecs16: |
| 14940 | case ARM::MVE_VQRSHL_by_vecs32: |
| 14941 | case ARM::MVE_VQRSHL_by_vecs8: |
| 14942 | case ARM::MVE_VQRSHL_by_vecu16: |
| 14943 | case ARM::MVE_VQRSHL_by_vecu32: |
| 14944 | case ARM::MVE_VQRSHL_by_vecu8: |
| 14945 | case ARM::MVE_VQSHL_by_vecs16: |
| 14946 | case ARM::MVE_VQSHL_by_vecs32: |
| 14947 | case ARM::MVE_VQSHL_by_vecs8: |
| 14948 | case ARM::MVE_VQSHL_by_vecu16: |
| 14949 | case ARM::MVE_VQSHL_by_vecu32: |
| 14950 | case ARM::MVE_VQSHL_by_vecu8: |
| 14951 | case ARM::MVE_VRSHL_by_vecs16: |
| 14952 | case ARM::MVE_VRSHL_by_vecs32: |
| 14953 | case ARM::MVE_VRSHL_by_vecs8: |
| 14954 | case ARM::MVE_VRSHL_by_vecu16: |
| 14955 | case ARM::MVE_VRSHL_by_vecu32: |
| 14956 | case ARM::MVE_VRSHL_by_vecu8: |
| 14957 | case ARM::MVE_VSHL_by_vecs16: |
| 14958 | case ARM::MVE_VSHL_by_vecs32: |
| 14959 | case ARM::MVE_VSHL_by_vecs8: |
| 14960 | case ARM::MVE_VSHL_by_vecu16: |
| 14961 | case ARM::MVE_VSHL_by_vecu32: |
| 14962 | case ARM::MVE_VSHL_by_vecu8: { |
| 14963 | switch (OpNum) { |
| 14964 | case 0: |
| 14965 | // op: Qd |
| 14966 | return 13; |
| 14967 | case 1: |
| 14968 | // op: Qm |
| 14969 | return 1; |
| 14970 | case 2: |
| 14971 | // op: Qn |
| 14972 | return 7; |
| 14973 | } |
| 14974 | break; |
| 14975 | } |
| 14976 | case ARM::MVE_VQSHLU_imms16: |
| 14977 | case ARM::MVE_VQSHLU_imms32: |
| 14978 | case ARM::MVE_VQSHLU_imms8: |
| 14979 | case ARM::MVE_VQSHLimms16: |
| 14980 | case ARM::MVE_VQSHLimms32: |
| 14981 | case ARM::MVE_VQSHLimms8: |
| 14982 | case ARM::MVE_VQSHLimmu16: |
| 14983 | case ARM::MVE_VQSHLimmu32: |
| 14984 | case ARM::MVE_VQSHLimmu8: |
| 14985 | case ARM::MVE_VRSHR_imms16: |
| 14986 | case ARM::MVE_VRSHR_imms32: |
| 14987 | case ARM::MVE_VRSHR_imms8: |
| 14988 | case ARM::MVE_VRSHR_immu16: |
| 14989 | case ARM::MVE_VRSHR_immu32: |
| 14990 | case ARM::MVE_VRSHR_immu8: |
| 14991 | case ARM::MVE_VSHLL_imms16bh: |
| 14992 | case ARM::MVE_VSHLL_imms16th: |
| 14993 | case ARM::MVE_VSHLL_imms8bh: |
| 14994 | case ARM::MVE_VSHLL_imms8th: |
| 14995 | case ARM::MVE_VSHLL_immu16bh: |
| 14996 | case ARM::MVE_VSHLL_immu16th: |
| 14997 | case ARM::MVE_VSHLL_immu8bh: |
| 14998 | case ARM::MVE_VSHLL_immu8th: |
| 14999 | case ARM::MVE_VSHL_immi16: |
| 15000 | case ARM::MVE_VSHL_immi32: |
| 15001 | case ARM::MVE_VSHL_immi8: |
| 15002 | case ARM::MVE_VSHR_imms16: |
| 15003 | case ARM::MVE_VSHR_imms32: |
| 15004 | case ARM::MVE_VSHR_imms8: |
| 15005 | case ARM::MVE_VSHR_immu16: |
| 15006 | case ARM::MVE_VSHR_immu32: |
| 15007 | case ARM::MVE_VSHR_immu8: { |
| 15008 | switch (OpNum) { |
| 15009 | case 0: |
| 15010 | // op: Qd |
| 15011 | return 13; |
| 15012 | case 1: |
| 15013 | // op: Qm |
| 15014 | return 1; |
| 15015 | case 2: |
| 15016 | // op: imm |
| 15017 | return 16; |
| 15018 | } |
| 15019 | break; |
| 15020 | } |
| 15021 | case ARM::MVE_VABSs16: |
| 15022 | case ARM::MVE_VABSs32: |
| 15023 | case ARM::MVE_VABSs8: |
| 15024 | case ARM::MVE_VCLSs16: |
| 15025 | case ARM::MVE_VCLSs32: |
| 15026 | case ARM::MVE_VCLSs8: |
| 15027 | case ARM::MVE_VCLZs16: |
| 15028 | case ARM::MVE_VCLZs32: |
| 15029 | case ARM::MVE_VCLZs8: |
| 15030 | case ARM::MVE_VCVTf32f16bh: |
| 15031 | case ARM::MVE_VCVTf32f16th: |
| 15032 | case ARM::MVE_VMOVLs16bh: |
| 15033 | case ARM::MVE_VMOVLs16th: |
| 15034 | case ARM::MVE_VMOVLs8bh: |
| 15035 | case ARM::MVE_VMOVLs8th: |
| 15036 | case ARM::MVE_VMOVLu16bh: |
| 15037 | case ARM::MVE_VMOVLu16th: |
| 15038 | case ARM::MVE_VMOVLu8bh: |
| 15039 | case ARM::MVE_VMOVLu8th: |
| 15040 | case ARM::MVE_VMVN: |
| 15041 | case ARM::MVE_VNEGs16: |
| 15042 | case ARM::MVE_VNEGs32: |
| 15043 | case ARM::MVE_VNEGs8: |
| 15044 | case ARM::MVE_VQABSs16: |
| 15045 | case ARM::MVE_VQABSs32: |
| 15046 | case ARM::MVE_VQABSs8: |
| 15047 | case ARM::MVE_VQNEGs16: |
| 15048 | case ARM::MVE_VQNEGs32: |
| 15049 | case ARM::MVE_VQNEGs8: |
| 15050 | case ARM::MVE_VREV16_8: |
| 15051 | case ARM::MVE_VREV32_16: |
| 15052 | case ARM::MVE_VREV32_8: |
| 15053 | case ARM::MVE_VREV64_16: |
| 15054 | case ARM::MVE_VREV64_32: |
| 15055 | case ARM::MVE_VREV64_8: |
| 15056 | case ARM::MVE_VSHLL_lws16bh: |
| 15057 | case ARM::MVE_VSHLL_lws16th: |
| 15058 | case ARM::MVE_VSHLL_lws8bh: |
| 15059 | case ARM::MVE_VSHLL_lws8th: |
| 15060 | case ARM::MVE_VSHLL_lwu16bh: |
| 15061 | case ARM::MVE_VSHLL_lwu16th: |
| 15062 | case ARM::MVE_VSHLL_lwu8bh: |
| 15063 | case ARM::MVE_VSHLL_lwu8th: { |
| 15064 | switch (OpNum) { |
| 15065 | case 0: |
| 15066 | // op: Qd |
| 15067 | return 13; |
| 15068 | case 1: |
| 15069 | // op: Qm |
| 15070 | return 1; |
| 15071 | } |
| 15072 | break; |
| 15073 | } |
| 15074 | case ARM::MVE_VABDs16: |
| 15075 | case ARM::MVE_VABDs32: |
| 15076 | case ARM::MVE_VABDs8: |
| 15077 | case ARM::MVE_VABDu16: |
| 15078 | case ARM::MVE_VABDu32: |
| 15079 | case ARM::MVE_VABDu8: |
| 15080 | case ARM::MVE_VADDi16: |
| 15081 | case ARM::MVE_VADDi32: |
| 15082 | case ARM::MVE_VADDi8: |
| 15083 | case ARM::MVE_VHADDs16: |
| 15084 | case ARM::MVE_VHADDs32: |
| 15085 | case ARM::MVE_VHADDs8: |
| 15086 | case ARM::MVE_VHADDu16: |
| 15087 | case ARM::MVE_VHADDu32: |
| 15088 | case ARM::MVE_VHADDu8: |
| 15089 | case ARM::MVE_VHSUBs16: |
| 15090 | case ARM::MVE_VHSUBs32: |
| 15091 | case ARM::MVE_VHSUBs8: |
| 15092 | case ARM::MVE_VHSUBu16: |
| 15093 | case ARM::MVE_VHSUBu32: |
| 15094 | case ARM::MVE_VHSUBu8: |
| 15095 | case ARM::MVE_VMAXNMf16: |
| 15096 | case ARM::MVE_VMAXNMf32: |
| 15097 | case ARM::MVE_VMAXs16: |
| 15098 | case ARM::MVE_VMAXs32: |
| 15099 | case ARM::MVE_VMAXs8: |
| 15100 | case ARM::MVE_VMAXu16: |
| 15101 | case ARM::MVE_VMAXu32: |
| 15102 | case ARM::MVE_VMAXu8: |
| 15103 | case ARM::MVE_VMINNMf16: |
| 15104 | case ARM::MVE_VMINNMf32: |
| 15105 | case ARM::MVE_VMINs16: |
| 15106 | case ARM::MVE_VMINs32: |
| 15107 | case ARM::MVE_VMINs8: |
| 15108 | case ARM::MVE_VMINu16: |
| 15109 | case ARM::MVE_VMINu32: |
| 15110 | case ARM::MVE_VMINu8: |
| 15111 | case ARM::MVE_VMULi16: |
| 15112 | case ARM::MVE_VMULi32: |
| 15113 | case ARM::MVE_VMULi8: |
| 15114 | case ARM::MVE_VQADDs16: |
| 15115 | case ARM::MVE_VQADDs32: |
| 15116 | case ARM::MVE_VQADDs8: |
| 15117 | case ARM::MVE_VQADDu16: |
| 15118 | case ARM::MVE_VQADDu32: |
| 15119 | case ARM::MVE_VQADDu8: |
| 15120 | case ARM::MVE_VQDMULHi16: |
| 15121 | case ARM::MVE_VQDMULHi32: |
| 15122 | case ARM::MVE_VQDMULHi8: |
| 15123 | case ARM::MVE_VQRDMULHi16: |
| 15124 | case ARM::MVE_VQRDMULHi32: |
| 15125 | case ARM::MVE_VQRDMULHi8: |
| 15126 | case ARM::MVE_VQSUBs16: |
| 15127 | case ARM::MVE_VQSUBs32: |
| 15128 | case ARM::MVE_VQSUBs8: |
| 15129 | case ARM::MVE_VQSUBu16: |
| 15130 | case ARM::MVE_VQSUBu32: |
| 15131 | case ARM::MVE_VQSUBu8: |
| 15132 | case ARM::MVE_VRHADDs16: |
| 15133 | case ARM::MVE_VRHADDs32: |
| 15134 | case ARM::MVE_VRHADDs8: |
| 15135 | case ARM::MVE_VRHADDu16: |
| 15136 | case ARM::MVE_VRHADDu32: |
| 15137 | case ARM::MVE_VRHADDu8: |
| 15138 | case ARM::MVE_VSUBi16: |
| 15139 | case ARM::MVE_VSUBi32: |
| 15140 | case ARM::MVE_VSUBi8: { |
| 15141 | switch (OpNum) { |
| 15142 | case 0: |
| 15143 | // op: Qd |
| 15144 | return 13; |
| 15145 | case 1: |
| 15146 | // op: Qn |
| 15147 | return 7; |
| 15148 | case 2: |
| 15149 | // op: Qm |
| 15150 | return 1; |
| 15151 | } |
| 15152 | break; |
| 15153 | } |
| 15154 | case ARM::MVE_VADD_qr_f16: |
| 15155 | case ARM::MVE_VADD_qr_f32: |
| 15156 | case ARM::MVE_VADD_qr_i16: |
| 15157 | case ARM::MVE_VADD_qr_i32: |
| 15158 | case ARM::MVE_VADD_qr_i8: |
| 15159 | case ARM::MVE_VBRSR16: |
| 15160 | case ARM::MVE_VBRSR32: |
| 15161 | case ARM::MVE_VBRSR8: |
| 15162 | case ARM::MVE_VHADD_qr_s16: |
| 15163 | case ARM::MVE_VHADD_qr_s32: |
| 15164 | case ARM::MVE_VHADD_qr_s8: |
| 15165 | case ARM::MVE_VHADD_qr_u16: |
| 15166 | case ARM::MVE_VHADD_qr_u32: |
| 15167 | case ARM::MVE_VHADD_qr_u8: |
| 15168 | case ARM::MVE_VHSUB_qr_s16: |
| 15169 | case ARM::MVE_VHSUB_qr_s32: |
| 15170 | case ARM::MVE_VHSUB_qr_s8: |
| 15171 | case ARM::MVE_VHSUB_qr_u16: |
| 15172 | case ARM::MVE_VHSUB_qr_u32: |
| 15173 | case ARM::MVE_VHSUB_qr_u8: |
| 15174 | case ARM::MVE_VMUL_qr_f16: |
| 15175 | case ARM::MVE_VMUL_qr_f32: |
| 15176 | case ARM::MVE_VMUL_qr_i16: |
| 15177 | case ARM::MVE_VMUL_qr_i32: |
| 15178 | case ARM::MVE_VMUL_qr_i8: |
| 15179 | case ARM::MVE_VQADD_qr_s16: |
| 15180 | case ARM::MVE_VQADD_qr_s32: |
| 15181 | case ARM::MVE_VQADD_qr_s8: |
| 15182 | case ARM::MVE_VQADD_qr_u16: |
| 15183 | case ARM::MVE_VQADD_qr_u32: |
| 15184 | case ARM::MVE_VQADD_qr_u8: |
| 15185 | case ARM::MVE_VQDMULH_qr_s16: |
| 15186 | case ARM::MVE_VQDMULH_qr_s32: |
| 15187 | case ARM::MVE_VQDMULH_qr_s8: |
| 15188 | case ARM::MVE_VQDMULL_qr_s16bh: |
| 15189 | case ARM::MVE_VQDMULL_qr_s16th: |
| 15190 | case ARM::MVE_VQDMULL_qr_s32bh: |
| 15191 | case ARM::MVE_VQDMULL_qr_s32th: |
| 15192 | case ARM::MVE_VQRDMULH_qr_s16: |
| 15193 | case ARM::MVE_VQRDMULH_qr_s32: |
| 15194 | case ARM::MVE_VQRDMULH_qr_s8: |
| 15195 | case ARM::MVE_VQSUB_qr_s16: |
| 15196 | case ARM::MVE_VQSUB_qr_s32: |
| 15197 | case ARM::MVE_VQSUB_qr_s8: |
| 15198 | case ARM::MVE_VQSUB_qr_u16: |
| 15199 | case ARM::MVE_VQSUB_qr_u32: |
| 15200 | case ARM::MVE_VQSUB_qr_u8: |
| 15201 | case ARM::MVE_VSUB_qr_f16: |
| 15202 | case ARM::MVE_VSUB_qr_f32: |
| 15203 | case ARM::MVE_VSUB_qr_i16: |
| 15204 | case ARM::MVE_VSUB_qr_i32: |
| 15205 | case ARM::MVE_VSUB_qr_i8: { |
| 15206 | switch (OpNum) { |
| 15207 | case 0: |
| 15208 | // op: Qd |
| 15209 | return 13; |
| 15210 | case 1: |
| 15211 | // op: Qn |
| 15212 | return 7; |
| 15213 | case 2: |
| 15214 | // op: Rm |
| 15215 | return 0; |
| 15216 | } |
| 15217 | break; |
| 15218 | } |
| 15219 | case ARM::MVE_VDDUPu16: |
| 15220 | case ARM::MVE_VDDUPu32: |
| 15221 | case ARM::MVE_VDDUPu8: |
| 15222 | case ARM::MVE_VIDUPu16: |
| 15223 | case ARM::MVE_VIDUPu32: |
| 15224 | case ARM::MVE_VIDUPu8: { |
| 15225 | switch (OpNum) { |
| 15226 | case 0: |
| 15227 | // op: Qd |
| 15228 | return 13; |
| 15229 | case 1: |
| 15230 | // op: Rn |
| 15231 | return 17; |
| 15232 | case 3: |
| 15233 | // op: imm |
| 15234 | return 0; |
| 15235 | } |
| 15236 | break; |
| 15237 | } |
| 15238 | case ARM::MVE_VLDRBS16: |
| 15239 | case ARM::MVE_VLDRBS32: |
| 15240 | case ARM::MVE_VLDRBU16: |
| 15241 | case ARM::MVE_VLDRBU32: |
| 15242 | case ARM::MVE_VLDRBU8: |
| 15243 | case ARM::MVE_VLDRDU64_qi: |
| 15244 | case ARM::MVE_VLDRHS32: |
| 15245 | case ARM::MVE_VLDRHU16: |
| 15246 | case ARM::MVE_VLDRHU32: |
| 15247 | case ARM::MVE_VLDRWU32: |
| 15248 | case ARM::MVE_VLDRWU32_qi: |
| 15249 | case ARM::MVE_VSTRB16: |
| 15250 | case ARM::MVE_VSTRB32: |
| 15251 | case ARM::MVE_VSTRBU8: |
| 15252 | case ARM::MVE_VSTRD64_qi: |
| 15253 | case ARM::MVE_VSTRH32: |
| 15254 | case ARM::MVE_VSTRHU16: |
| 15255 | case ARM::MVE_VSTRW32_qi: |
| 15256 | case ARM::MVE_VSTRWU32: { |
| 15257 | switch (OpNum) { |
| 15258 | case 0: |
| 15259 | // op: Qd |
| 15260 | return 13; |
| 15261 | case 1: |
| 15262 | // op: addr |
| 15263 | return 0; |
| 15264 | } |
| 15265 | break; |
| 15266 | } |
| 15267 | case ARM::MVE_VLDRBS16_rq: |
| 15268 | case ARM::MVE_VLDRBS32_rq: |
| 15269 | case ARM::MVE_VLDRBU16_rq: |
| 15270 | case ARM::MVE_VLDRBU32_rq: |
| 15271 | case ARM::MVE_VLDRBU8_rq: |
| 15272 | case ARM::MVE_VLDRDU64_rq: |
| 15273 | case ARM::MVE_VLDRDU64_rq_u: |
| 15274 | case ARM::MVE_VLDRHS32_rq: |
| 15275 | case ARM::MVE_VLDRHS32_rq_u: |
| 15276 | case ARM::MVE_VLDRHU16_rq: |
| 15277 | case ARM::MVE_VLDRHU16_rq_u: |
| 15278 | case ARM::MVE_VLDRHU32_rq: |
| 15279 | case ARM::MVE_VLDRHU32_rq_u: |
| 15280 | case ARM::MVE_VLDRWU32_rq: |
| 15281 | case ARM::MVE_VLDRWU32_rq_u: |
| 15282 | case ARM::MVE_VSTRB16_rq: |
| 15283 | case ARM::MVE_VSTRB32_rq: |
| 15284 | case ARM::MVE_VSTRB8_rq: |
| 15285 | case ARM::MVE_VSTRD64_rq: |
| 15286 | case ARM::MVE_VSTRD64_rq_u: |
| 15287 | case ARM::MVE_VSTRH16_rq: |
| 15288 | case ARM::MVE_VSTRH16_rq_u: |
| 15289 | case ARM::MVE_VSTRH32_rq: |
| 15290 | case ARM::MVE_VSTRH32_rq_u: |
| 15291 | case ARM::MVE_VSTRW32_rq: |
| 15292 | case ARM::MVE_VSTRW32_rq_u: { |
| 15293 | switch (OpNum) { |
| 15294 | case 0: |
| 15295 | // op: Qd |
| 15296 | return 13; |
| 15297 | case 1: |
| 15298 | // op: addr |
| 15299 | return 1; |
| 15300 | } |
| 15301 | break; |
| 15302 | } |
| 15303 | case ARM::MVE_VCMULf16: |
| 15304 | case ARM::MVE_VCMULf32: { |
| 15305 | switch (OpNum) { |
| 15306 | case 0: |
| 15307 | // op: Qd |
| 15308 | return 13; |
| 15309 | case 2: |
| 15310 | // op: Qm |
| 15311 | return 1; |
| 15312 | case 1: |
| 15313 | // op: Qn |
| 15314 | return 7; |
| 15315 | case 3: |
| 15316 | // op: rot |
| 15317 | return 0; |
| 15318 | } |
| 15319 | break; |
| 15320 | } |
| 15321 | case ARM::MVE_VCADDi16: |
| 15322 | case ARM::MVE_VCADDi32: |
| 15323 | case ARM::MVE_VCADDi8: |
| 15324 | case ARM::MVE_VHCADDs16: |
| 15325 | case ARM::MVE_VHCADDs32: |
| 15326 | case ARM::MVE_VHCADDs8: { |
| 15327 | switch (OpNum) { |
| 15328 | case 0: |
| 15329 | // op: Qd |
| 15330 | return 13; |
| 15331 | case 2: |
| 15332 | // op: Qm |
| 15333 | return 1; |
| 15334 | case 1: |
| 15335 | // op: Qn |
| 15336 | return 7; |
| 15337 | case 3: |
| 15338 | // op: rot |
| 15339 | return 12; |
| 15340 | } |
| 15341 | break; |
| 15342 | } |
| 15343 | case ARM::MVE_VAND: |
| 15344 | case ARM::MVE_VBIC: |
| 15345 | case ARM::MVE_VEOR: |
| 15346 | case ARM::MVE_VMULHs16: |
| 15347 | case ARM::MVE_VMULHs32: |
| 15348 | case ARM::MVE_VMULHs8: |
| 15349 | case ARM::MVE_VMULHu16: |
| 15350 | case ARM::MVE_VMULHu32: |
| 15351 | case ARM::MVE_VMULHu8: |
| 15352 | case ARM::MVE_VMULLBp16: |
| 15353 | case ARM::MVE_VMULLBp8: |
| 15354 | case ARM::MVE_VMULLBs16: |
| 15355 | case ARM::MVE_VMULLBs32: |
| 15356 | case ARM::MVE_VMULLBs8: |
| 15357 | case ARM::MVE_VMULLBu16: |
| 15358 | case ARM::MVE_VMULLBu32: |
| 15359 | case ARM::MVE_VMULLBu8: |
| 15360 | case ARM::MVE_VMULLTp16: |
| 15361 | case ARM::MVE_VMULLTp8: |
| 15362 | case ARM::MVE_VMULLTs16: |
| 15363 | case ARM::MVE_VMULLTs32: |
| 15364 | case ARM::MVE_VMULLTs8: |
| 15365 | case ARM::MVE_VMULLTu16: |
| 15366 | case ARM::MVE_VMULLTu32: |
| 15367 | case ARM::MVE_VMULLTu8: |
| 15368 | case ARM::MVE_VORN: |
| 15369 | case ARM::MVE_VORR: |
| 15370 | case ARM::MVE_VQDMULLs16bh: |
| 15371 | case ARM::MVE_VQDMULLs16th: |
| 15372 | case ARM::MVE_VQDMULLs32bh: |
| 15373 | case ARM::MVE_VQDMULLs32th: |
| 15374 | case ARM::MVE_VRMULHs16: |
| 15375 | case ARM::MVE_VRMULHs32: |
| 15376 | case ARM::MVE_VRMULHs8: |
| 15377 | case ARM::MVE_VRMULHu16: |
| 15378 | case ARM::MVE_VRMULHu32: |
| 15379 | case ARM::MVE_VRMULHu8: { |
| 15380 | switch (OpNum) { |
| 15381 | case 0: |
| 15382 | // op: Qd |
| 15383 | return 13; |
| 15384 | case 2: |
| 15385 | // op: Qm |
| 15386 | return 1; |
| 15387 | case 1: |
| 15388 | // op: Qn |
| 15389 | return 7; |
| 15390 | } |
| 15391 | break; |
| 15392 | } |
| 15393 | case ARM::MVE_VQRSHRNbhs16: |
| 15394 | case ARM::MVE_VQRSHRNbhs32: |
| 15395 | case ARM::MVE_VQRSHRNbhu16: |
| 15396 | case ARM::MVE_VQRSHRNbhu32: |
| 15397 | case ARM::MVE_VQRSHRNths16: |
| 15398 | case ARM::MVE_VQRSHRNths32: |
| 15399 | case ARM::MVE_VQRSHRNthu16: |
| 15400 | case ARM::MVE_VQRSHRNthu32: |
| 15401 | case ARM::MVE_VQRSHRUNs16bh: |
| 15402 | case ARM::MVE_VQRSHRUNs16th: |
| 15403 | case ARM::MVE_VQRSHRUNs32bh: |
| 15404 | case ARM::MVE_VQRSHRUNs32th: |
| 15405 | case ARM::MVE_VQSHRNbhs16: |
| 15406 | case ARM::MVE_VQSHRNbhs32: |
| 15407 | case ARM::MVE_VQSHRNbhu16: |
| 15408 | case ARM::MVE_VQSHRNbhu32: |
| 15409 | case ARM::MVE_VQSHRNths16: |
| 15410 | case ARM::MVE_VQSHRNths32: |
| 15411 | case ARM::MVE_VQSHRNthu16: |
| 15412 | case ARM::MVE_VQSHRNthu32: |
| 15413 | case ARM::MVE_VQSHRUNs16bh: |
| 15414 | case ARM::MVE_VQSHRUNs16th: |
| 15415 | case ARM::MVE_VQSHRUNs32bh: |
| 15416 | case ARM::MVE_VQSHRUNs32th: |
| 15417 | case ARM::MVE_VRSHRNi16bh: |
| 15418 | case ARM::MVE_VRSHRNi16th: |
| 15419 | case ARM::MVE_VRSHRNi32bh: |
| 15420 | case ARM::MVE_VRSHRNi32th: |
| 15421 | case ARM::MVE_VSHRNi16bh: |
| 15422 | case ARM::MVE_VSHRNi16th: |
| 15423 | case ARM::MVE_VSHRNi32bh: |
| 15424 | case ARM::MVE_VSHRNi32th: |
| 15425 | case ARM::MVE_VSLIimm16: |
| 15426 | case ARM::MVE_VSLIimm32: |
| 15427 | case ARM::MVE_VSLIimm8: |
| 15428 | case ARM::MVE_VSRIimm16: |
| 15429 | case ARM::MVE_VSRIimm32: |
| 15430 | case ARM::MVE_VSRIimm8: { |
| 15431 | switch (OpNum) { |
| 15432 | case 0: |
| 15433 | // op: Qd |
| 15434 | return 13; |
| 15435 | case 2: |
| 15436 | // op: Qm |
| 15437 | return 1; |
| 15438 | case 3: |
| 15439 | // op: imm |
| 15440 | return 16; |
| 15441 | } |
| 15442 | break; |
| 15443 | } |
| 15444 | case ARM::MVE_VCVTf16f32bh: |
| 15445 | case ARM::MVE_VCVTf16f32th: |
| 15446 | case ARM::MVE_VMAXAs16: |
| 15447 | case ARM::MVE_VMAXAs32: |
| 15448 | case ARM::MVE_VMAXAs8: |
| 15449 | case ARM::MVE_VMAXNMAf16: |
| 15450 | case ARM::MVE_VMAXNMAf32: |
| 15451 | case ARM::MVE_VMINAs16: |
| 15452 | case ARM::MVE_VMINAs32: |
| 15453 | case ARM::MVE_VMINAs8: |
| 15454 | case ARM::MVE_VMINNMAf16: |
| 15455 | case ARM::MVE_VMINNMAf32: |
| 15456 | case ARM::MVE_VMOVNi16bh: |
| 15457 | case ARM::MVE_VMOVNi16th: |
| 15458 | case ARM::MVE_VMOVNi32bh: |
| 15459 | case ARM::MVE_VMOVNi32th: |
| 15460 | case ARM::MVE_VQMOVNs16bh: |
| 15461 | case ARM::MVE_VQMOVNs16th: |
| 15462 | case ARM::MVE_VQMOVNs32bh: |
| 15463 | case ARM::MVE_VQMOVNs32th: |
| 15464 | case ARM::MVE_VQMOVNu16bh: |
| 15465 | case ARM::MVE_VQMOVNu16th: |
| 15466 | case ARM::MVE_VQMOVNu32bh: |
| 15467 | case ARM::MVE_VQMOVNu32th: |
| 15468 | case ARM::MVE_VQMOVUNs16bh: |
| 15469 | case ARM::MVE_VQMOVUNs16th: |
| 15470 | case ARM::MVE_VQMOVUNs32bh: |
| 15471 | case ARM::MVE_VQMOVUNs32th: { |
| 15472 | switch (OpNum) { |
| 15473 | case 0: |
| 15474 | // op: Qd |
| 15475 | return 13; |
| 15476 | case 2: |
| 15477 | // op: Qm |
| 15478 | return 1; |
| 15479 | } |
| 15480 | break; |
| 15481 | } |
| 15482 | case ARM::MVE_VFMA_qr_Sf16: |
| 15483 | case ARM::MVE_VFMA_qr_Sf32: |
| 15484 | case ARM::MVE_VFMA_qr_f16: |
| 15485 | case ARM::MVE_VFMA_qr_f32: |
| 15486 | case ARM::MVE_VMLAS_qr_i16: |
| 15487 | case ARM::MVE_VMLAS_qr_i32: |
| 15488 | case ARM::MVE_VMLAS_qr_i8: |
| 15489 | case ARM::MVE_VMLA_qr_i16: |
| 15490 | case ARM::MVE_VMLA_qr_i32: |
| 15491 | case ARM::MVE_VMLA_qr_i8: |
| 15492 | case ARM::MVE_VQDMLAH_qrs16: |
| 15493 | case ARM::MVE_VQDMLAH_qrs32: |
| 15494 | case ARM::MVE_VQDMLAH_qrs8: |
| 15495 | case ARM::MVE_VQDMLASH_qrs16: |
| 15496 | case ARM::MVE_VQDMLASH_qrs32: |
| 15497 | case ARM::MVE_VQDMLASH_qrs8: |
| 15498 | case ARM::MVE_VQRDMLAH_qrs16: |
| 15499 | case ARM::MVE_VQRDMLAH_qrs32: |
| 15500 | case ARM::MVE_VQRDMLAH_qrs8: |
| 15501 | case ARM::MVE_VQRDMLASH_qrs16: |
| 15502 | case ARM::MVE_VQRDMLASH_qrs32: |
| 15503 | case ARM::MVE_VQRDMLASH_qrs8: { |
| 15504 | switch (OpNum) { |
| 15505 | case 0: |
| 15506 | // op: Qd |
| 15507 | return 13; |
| 15508 | case 2: |
| 15509 | // op: Qn |
| 15510 | return 7; |
| 15511 | case 3: |
| 15512 | // op: Rm |
| 15513 | return 0; |
| 15514 | } |
| 15515 | break; |
| 15516 | } |
| 15517 | case ARM::MVE_VQRSHL_qrs16: |
| 15518 | case ARM::MVE_VQRSHL_qrs32: |
| 15519 | case ARM::MVE_VQRSHL_qrs8: |
| 15520 | case ARM::MVE_VQRSHL_qru16: |
| 15521 | case ARM::MVE_VQRSHL_qru32: |
| 15522 | case ARM::MVE_VQRSHL_qru8: |
| 15523 | case ARM::MVE_VQSHL_qrs16: |
| 15524 | case ARM::MVE_VQSHL_qrs32: |
| 15525 | case ARM::MVE_VQSHL_qrs8: |
| 15526 | case ARM::MVE_VQSHL_qru16: |
| 15527 | case ARM::MVE_VQSHL_qru32: |
| 15528 | case ARM::MVE_VQSHL_qru8: |
| 15529 | case ARM::MVE_VRSHL_qrs16: |
| 15530 | case ARM::MVE_VRSHL_qrs32: |
| 15531 | case ARM::MVE_VRSHL_qrs8: |
| 15532 | case ARM::MVE_VRSHL_qru16: |
| 15533 | case ARM::MVE_VRSHL_qru32: |
| 15534 | case ARM::MVE_VRSHL_qru8: |
| 15535 | case ARM::MVE_VSHL_qrs16: |
| 15536 | case ARM::MVE_VSHL_qrs32: |
| 15537 | case ARM::MVE_VSHL_qrs8: |
| 15538 | case ARM::MVE_VSHL_qru16: |
| 15539 | case ARM::MVE_VSHL_qru32: |
| 15540 | case ARM::MVE_VSHL_qru8: { |
| 15541 | switch (OpNum) { |
| 15542 | case 0: |
| 15543 | // op: Qd |
| 15544 | return 13; |
| 15545 | case 2: |
| 15546 | // op: Rm |
| 15547 | return 0; |
| 15548 | } |
| 15549 | break; |
| 15550 | } |
| 15551 | case ARM::MVE_VADC: |
| 15552 | case ARM::MVE_VADCI: |
| 15553 | case ARM::MVE_VQDMLADHXs16: |
| 15554 | case ARM::MVE_VQDMLADHXs32: |
| 15555 | case ARM::MVE_VQDMLADHXs8: |
| 15556 | case ARM::MVE_VQDMLADHs16: |
| 15557 | case ARM::MVE_VQDMLADHs32: |
| 15558 | case ARM::MVE_VQDMLADHs8: |
| 15559 | case ARM::MVE_VQDMLSDHXs16: |
| 15560 | case ARM::MVE_VQDMLSDHXs32: |
| 15561 | case ARM::MVE_VQDMLSDHXs8: |
| 15562 | case ARM::MVE_VQDMLSDHs16: |
| 15563 | case ARM::MVE_VQDMLSDHs32: |
| 15564 | case ARM::MVE_VQDMLSDHs8: |
| 15565 | case ARM::MVE_VQRDMLADHXs16: |
| 15566 | case ARM::MVE_VQRDMLADHXs32: |
| 15567 | case ARM::MVE_VQRDMLADHXs8: |
| 15568 | case ARM::MVE_VQRDMLADHs16: |
| 15569 | case ARM::MVE_VQRDMLADHs32: |
| 15570 | case ARM::MVE_VQRDMLADHs8: |
| 15571 | case ARM::MVE_VQRDMLSDHXs16: |
| 15572 | case ARM::MVE_VQRDMLSDHXs32: |
| 15573 | case ARM::MVE_VQRDMLSDHXs8: |
| 15574 | case ARM::MVE_VQRDMLSDHs16: |
| 15575 | case ARM::MVE_VQRDMLSDHs32: |
| 15576 | case ARM::MVE_VQRDMLSDHs8: |
| 15577 | case ARM::MVE_VSBC: |
| 15578 | case ARM::MVE_VSBCI: { |
| 15579 | switch (OpNum) { |
| 15580 | case 0: |
| 15581 | // op: Qd |
| 15582 | return 13; |
| 15583 | case 3: |
| 15584 | // op: Qm |
| 15585 | return 1; |
| 15586 | case 2: |
| 15587 | // op: Qn |
| 15588 | return 7; |
| 15589 | } |
| 15590 | break; |
| 15591 | } |
| 15592 | case ARM::MVE_VDWDUPu16: |
| 15593 | case ARM::MVE_VDWDUPu32: |
| 15594 | case ARM::MVE_VDWDUPu8: |
| 15595 | case ARM::MVE_VIWDUPu16: |
| 15596 | case ARM::MVE_VIWDUPu32: |
| 15597 | case ARM::MVE_VIWDUPu8: { |
| 15598 | switch (OpNum) { |
| 15599 | case 0: |
| 15600 | // op: Qd |
| 15601 | return 13; |
| 15602 | case 3: |
| 15603 | // op: Rm |
| 15604 | return 1; |
| 15605 | case 1: |
| 15606 | // op: Rn |
| 15607 | return 17; |
| 15608 | case 4: |
| 15609 | // op: imm |
| 15610 | return 0; |
| 15611 | } |
| 15612 | break; |
| 15613 | } |
| 15614 | case ARM::MVE_VDUP16: |
| 15615 | case ARM::MVE_VDUP32: |
| 15616 | case ARM::MVE_VDUP8: { |
| 15617 | switch (OpNum) { |
| 15618 | case 0: |
| 15619 | // op: Qd |
| 15620 | return 7; |
| 15621 | case 1: |
| 15622 | // op: Rt |
| 15623 | return 12; |
| 15624 | } |
| 15625 | break; |
| 15626 | } |
| 15627 | case ARM::MVE_VMOV_to_lane_32: { |
| 15628 | switch (OpNum) { |
| 15629 | case 0: |
| 15630 | // op: Qd |
| 15631 | return 7; |
| 15632 | case 2: |
| 15633 | // op: Rt |
| 15634 | return 12; |
| 15635 | case 3: |
| 15636 | // op: Idx |
| 15637 | return 16; |
| 15638 | } |
| 15639 | break; |
| 15640 | } |
| 15641 | case ARM::MVE_VMOV_to_lane_8: { |
| 15642 | switch (OpNum) { |
| 15643 | case 0: |
| 15644 | // op: Qd |
| 15645 | return 7; |
| 15646 | case 2: |
| 15647 | // op: Rt |
| 15648 | return 12; |
| 15649 | case 3: |
| 15650 | // op: Idx |
| 15651 | return 5; |
| 15652 | } |
| 15653 | break; |
| 15654 | } |
| 15655 | case ARM::MVE_VMOV_to_lane_16: { |
| 15656 | switch (OpNum) { |
| 15657 | case 0: |
| 15658 | // op: Qd |
| 15659 | return 7; |
| 15660 | case 2: |
| 15661 | // op: Rt |
| 15662 | return 12; |
| 15663 | case 3: |
| 15664 | // op: Idx |
| 15665 | return 6; |
| 15666 | } |
| 15667 | break; |
| 15668 | } |
| 15669 | case ARM::tMOVSr: |
| 15670 | case ARM::tMOVr: { |
| 15671 | switch (OpNum) { |
| 15672 | case 0: |
| 15673 | // op: Rd |
| 15674 | return 0; |
| 15675 | case 1: |
| 15676 | // op: Rm |
| 15677 | return 3; |
| 15678 | } |
| 15679 | break; |
| 15680 | } |
| 15681 | case ARM::t2STLEX: { |
| 15682 | switch (OpNum) { |
| 15683 | case 0: |
| 15684 | // op: Rd |
| 15685 | return 0; |
| 15686 | case 1: |
| 15687 | // op: Rt |
| 15688 | return 12; |
| 15689 | case 2: |
| 15690 | // op: addr |
| 15691 | return 16; |
| 15692 | } |
| 15693 | break; |
| 15694 | } |
| 15695 | case ARM::tADDi3: |
| 15696 | case ARM::tSUBi3: { |
| 15697 | switch (OpNum) { |
| 15698 | case 0: |
| 15699 | // op: Rd |
| 15700 | return 0; |
| 15701 | case 2: |
| 15702 | // op: Rm |
| 15703 | return 3; |
| 15704 | case 3: |
| 15705 | // op: imm3 |
| 15706 | return 6; |
| 15707 | } |
| 15708 | break; |
| 15709 | } |
| 15710 | case ARM::tASRri: |
| 15711 | case ARM::tLSLri: |
| 15712 | case ARM::tLSRri: { |
| 15713 | switch (OpNum) { |
| 15714 | case 0: |
| 15715 | // op: Rd |
| 15716 | return 0; |
| 15717 | case 2: |
| 15718 | // op: Rm |
| 15719 | return 3; |
| 15720 | case 3: |
| 15721 | // op: imm5 |
| 15722 | return 6; |
| 15723 | } |
| 15724 | break; |
| 15725 | } |
| 15726 | case ARM::tMUL: |
| 15727 | case ARM::tMVN: |
| 15728 | case ARM::tRSB: { |
| 15729 | switch (OpNum) { |
| 15730 | case 0: |
| 15731 | // op: Rd |
| 15732 | return 0; |
| 15733 | case 2: |
| 15734 | // op: Rn |
| 15735 | return 3; |
| 15736 | } |
| 15737 | break; |
| 15738 | } |
| 15739 | case ARM::t2STLEXB: |
| 15740 | case ARM::t2STLEXH: |
| 15741 | case ARM::t2STREXB: |
| 15742 | case ARM::t2STREXH: { |
| 15743 | switch (OpNum) { |
| 15744 | case 0: |
| 15745 | // op: Rd |
| 15746 | return 0; |
| 15747 | case 2: |
| 15748 | // op: addr |
| 15749 | return 16; |
| 15750 | case 1: |
| 15751 | // op: Rt |
| 15752 | return 12; |
| 15753 | } |
| 15754 | break; |
| 15755 | } |
| 15756 | case ARM::t2STLEXD: |
| 15757 | case ARM::t2STREXD: { |
| 15758 | switch (OpNum) { |
| 15759 | case 0: |
| 15760 | // op: Rd |
| 15761 | return 0; |
| 15762 | case 3: |
| 15763 | // op: addr |
| 15764 | return 16; |
| 15765 | case 1: |
| 15766 | // op: Rt |
| 15767 | return 12; |
| 15768 | case 2: |
| 15769 | // op: Rt2 |
| 15770 | return 8; |
| 15771 | } |
| 15772 | break; |
| 15773 | } |
| 15774 | case ARM::CRC32B: |
| 15775 | case ARM::CRC32CB: |
| 15776 | case ARM::CRC32CH: |
| 15777 | case ARM::CRC32CW: |
| 15778 | case ARM::CRC32H: |
| 15779 | case ARM::CRC32W: { |
| 15780 | switch (OpNum) { |
| 15781 | case 0: |
| 15782 | // op: Rd |
| 15783 | return 12; |
| 15784 | case 1: |
| 15785 | // op: Rn |
| 15786 | return 16; |
| 15787 | case 2: |
| 15788 | // op: Rm |
| 15789 | return 0; |
| 15790 | } |
| 15791 | break; |
| 15792 | } |
| 15793 | case ARM::t2SXTB: |
| 15794 | case ARM::t2SXTB16: |
| 15795 | case ARM::t2SXTH: |
| 15796 | case ARM::t2UXTB: |
| 15797 | case ARM::t2UXTB16: |
| 15798 | case ARM::t2UXTH: { |
| 15799 | switch (OpNum) { |
| 15800 | case 0: |
| 15801 | // op: Rd |
| 15802 | return 8; |
| 15803 | case 1: |
| 15804 | // op: Rm |
| 15805 | return 0; |
| 15806 | case 2: |
| 15807 | // op: rot |
| 15808 | return 4; |
| 15809 | } |
| 15810 | break; |
| 15811 | } |
| 15812 | case ARM::t2ASRs1: |
| 15813 | case ARM::t2CLZ: |
| 15814 | case ARM::t2LSRs1: |
| 15815 | case ARM::t2RBIT: |
| 15816 | case ARM::t2REV: |
| 15817 | case ARM::t2REV16: |
| 15818 | case ARM::t2REVSH: { |
| 15819 | switch (OpNum) { |
| 15820 | case 0: |
| 15821 | // op: Rd |
| 15822 | return 8; |
| 15823 | case 1: |
| 15824 | // op: Rm |
| 15825 | return 0; |
| 15826 | } |
| 15827 | break; |
| 15828 | } |
| 15829 | case ARM::t2MLA: |
| 15830 | case ARM::t2MLS: |
| 15831 | case ARM::t2SMLABB: |
| 15832 | case ARM::t2SMLABT: |
| 15833 | case ARM::t2SMLAD: |
| 15834 | case ARM::t2SMLADX: |
| 15835 | case ARM::t2SMLATB: |
| 15836 | case ARM::t2SMLATT: |
| 15837 | case ARM::t2SMLAWB: |
| 15838 | case ARM::t2SMLAWT: |
| 15839 | case ARM::t2SMLSD: |
| 15840 | case ARM::t2SMLSDX: |
| 15841 | case ARM::t2SMMLA: |
| 15842 | case ARM::t2SMMLAR: |
| 15843 | case ARM::t2SMMLS: |
| 15844 | case ARM::t2SMMLSR: |
| 15845 | case ARM::t2USADA8: { |
| 15846 | switch (OpNum) { |
| 15847 | case 0: |
| 15848 | // op: Rd |
| 15849 | return 8; |
| 15850 | case 1: |
| 15851 | // op: Rn |
| 15852 | return 16; |
| 15853 | case 2: |
| 15854 | // op: Rm |
| 15855 | return 0; |
| 15856 | case 3: |
| 15857 | // op: Ra |
| 15858 | return 12; |
| 15859 | } |
| 15860 | break; |
| 15861 | } |
| 15862 | case ARM::t2SXTAB: |
| 15863 | case ARM::t2SXTAB16: |
| 15864 | case ARM::t2SXTAH: |
| 15865 | case ARM::t2UXTAB: |
| 15866 | case ARM::t2UXTAB16: |
| 15867 | case ARM::t2UXTAH: { |
| 15868 | switch (OpNum) { |
| 15869 | case 0: |
| 15870 | // op: Rd |
| 15871 | return 8; |
| 15872 | case 1: |
| 15873 | // op: Rn |
| 15874 | return 16; |
| 15875 | case 2: |
| 15876 | // op: Rm |
| 15877 | return 0; |
| 15878 | case 3: |
| 15879 | // op: rot |
| 15880 | return 4; |
| 15881 | } |
| 15882 | break; |
| 15883 | } |
| 15884 | case ARM::t2PKHBT: |
| 15885 | case ARM::t2PKHTB: { |
| 15886 | switch (OpNum) { |
| 15887 | case 0: |
| 15888 | // op: Rd |
| 15889 | return 8; |
| 15890 | case 1: |
| 15891 | // op: Rn |
| 15892 | return 16; |
| 15893 | case 2: |
| 15894 | // op: Rm |
| 15895 | return 0; |
| 15896 | case 3: |
| 15897 | // op: sh |
| 15898 | return 6; |
| 15899 | } |
| 15900 | break; |
| 15901 | } |
| 15902 | case ARM::t2CRC32B: |
| 15903 | case ARM::t2CRC32CB: |
| 15904 | case ARM::t2CRC32CH: |
| 15905 | case ARM::t2CRC32CW: |
| 15906 | case ARM::t2CRC32H: |
| 15907 | case ARM::t2CRC32W: |
| 15908 | case ARM::t2MUL: |
| 15909 | case ARM::t2QADD16: |
| 15910 | case ARM::t2QADD8: |
| 15911 | case ARM::t2QASX: |
| 15912 | case ARM::t2QSAX: |
| 15913 | case ARM::t2QSUB16: |
| 15914 | case ARM::t2QSUB8: |
| 15915 | case ARM::t2SADD16: |
| 15916 | case ARM::t2SADD8: |
| 15917 | case ARM::t2SASX: |
| 15918 | case ARM::t2SDIV: |
| 15919 | case ARM::t2SEL: |
| 15920 | case ARM::t2SHADD16: |
| 15921 | case ARM::t2SHADD8: |
| 15922 | case ARM::t2SHASX: |
| 15923 | case ARM::t2SHSAX: |
| 15924 | case ARM::t2SHSUB16: |
| 15925 | case ARM::t2SHSUB8: |
| 15926 | case ARM::t2SMMUL: |
| 15927 | case ARM::t2SMMULR: |
| 15928 | case ARM::t2SMUAD: |
| 15929 | case ARM::t2SMUADX: |
| 15930 | case ARM::t2SMULBB: |
| 15931 | case ARM::t2SMULBT: |
| 15932 | case ARM::t2SMULTB: |
| 15933 | case ARM::t2SMULTT: |
| 15934 | case ARM::t2SMULWB: |
| 15935 | case ARM::t2SMULWT: |
| 15936 | case ARM::t2SMUSD: |
| 15937 | case ARM::t2SMUSDX: |
| 15938 | case ARM::t2SSAX: |
| 15939 | case ARM::t2SSUB16: |
| 15940 | case ARM::t2SSUB8: |
| 15941 | case ARM::t2UADD16: |
| 15942 | case ARM::t2UADD8: |
| 15943 | case ARM::t2UASX: |
| 15944 | case ARM::t2UDIV: |
| 15945 | case ARM::t2UHADD16: |
| 15946 | case ARM::t2UHADD8: |
| 15947 | case ARM::t2UHASX: |
| 15948 | case ARM::t2UHSAX: |
| 15949 | case ARM::t2UHSUB16: |
| 15950 | case ARM::t2UHSUB8: |
| 15951 | case ARM::t2UQADD16: |
| 15952 | case ARM::t2UQADD8: |
| 15953 | case ARM::t2UQASX: |
| 15954 | case ARM::t2UQSAX: |
| 15955 | case ARM::t2UQSUB16: |
| 15956 | case ARM::t2UQSUB8: |
| 15957 | case ARM::t2USAD8: |
| 15958 | case ARM::t2USAX: |
| 15959 | case ARM::t2USUB16: |
| 15960 | case ARM::t2USUB8: { |
| 15961 | switch (OpNum) { |
| 15962 | case 0: |
| 15963 | // op: Rd |
| 15964 | return 8; |
| 15965 | case 1: |
| 15966 | // op: Rn |
| 15967 | return 16; |
| 15968 | case 2: |
| 15969 | // op: Rm |
| 15970 | return 0; |
| 15971 | } |
| 15972 | break; |
| 15973 | } |
| 15974 | case ARM::t2ADDri12: |
| 15975 | case ARM::t2SUBri12: { |
| 15976 | switch (OpNum) { |
| 15977 | case 0: |
| 15978 | // op: Rd |
| 15979 | return 8; |
| 15980 | case 1: |
| 15981 | // op: Rn |
| 15982 | return 16; |
| 15983 | case 2: |
| 15984 | // op: imm |
| 15985 | return 0; |
| 15986 | } |
| 15987 | break; |
| 15988 | } |
| 15989 | case ARM::t2STREX: { |
| 15990 | switch (OpNum) { |
| 15991 | case 0: |
| 15992 | // op: Rd |
| 15993 | return 8; |
| 15994 | case 1: |
| 15995 | // op: Rt |
| 15996 | return 12; |
| 15997 | case 2: |
| 15998 | // op: addr |
| 15999 | return 0; |
| 16000 | } |
| 16001 | break; |
| 16002 | } |
| 16003 | case ARM::t2MRS_M: { |
| 16004 | switch (OpNum) { |
| 16005 | case 0: |
| 16006 | // op: Rd |
| 16007 | return 8; |
| 16008 | case 1: |
| 16009 | // op: SYSm |
| 16010 | return 0; |
| 16011 | } |
| 16012 | break; |
| 16013 | } |
| 16014 | case ARM::t2ADR: |
| 16015 | case ARM::tADR: { |
| 16016 | switch (OpNum) { |
| 16017 | case 0: |
| 16018 | // op: Rd |
| 16019 | return 8; |
| 16020 | case 1: |
| 16021 | // op: addr |
| 16022 | return 0; |
| 16023 | } |
| 16024 | break; |
| 16025 | } |
| 16026 | case ARM::t2MOVi16: { |
| 16027 | switch (OpNum) { |
| 16028 | case 0: |
| 16029 | // op: Rd |
| 16030 | return 8; |
| 16031 | case 1: |
| 16032 | // op: imm |
| 16033 | return 0; |
| 16034 | } |
| 16035 | break; |
| 16036 | } |
| 16037 | case ARM::t2CSEL: |
| 16038 | case ARM::t2CSINC: |
| 16039 | case ARM::t2CSINV: |
| 16040 | case ARM::t2CSNEG: { |
| 16041 | switch (OpNum) { |
| 16042 | case 0: |
| 16043 | // op: Rd |
| 16044 | return 8; |
| 16045 | case 2: |
| 16046 | // op: Rm |
| 16047 | return 0; |
| 16048 | case 1: |
| 16049 | // op: Rn |
| 16050 | return 16; |
| 16051 | case 3: |
| 16052 | // op: fcond |
| 16053 | return 4; |
| 16054 | } |
| 16055 | break; |
| 16056 | } |
| 16057 | case ARM::t2QADD: |
| 16058 | case ARM::t2QDADD: |
| 16059 | case ARM::t2QDSUB: |
| 16060 | case ARM::t2QSUB: { |
| 16061 | switch (OpNum) { |
| 16062 | case 0: |
| 16063 | // op: Rd |
| 16064 | return 8; |
| 16065 | case 2: |
| 16066 | // op: Rn |
| 16067 | return 16; |
| 16068 | case 1: |
| 16069 | // op: Rm |
| 16070 | return 0; |
| 16071 | } |
| 16072 | break; |
| 16073 | } |
| 16074 | case ARM::t2SSAT: |
| 16075 | case ARM::t2USAT: { |
| 16076 | switch (OpNum) { |
| 16077 | case 0: |
| 16078 | // op: Rd |
| 16079 | return 8; |
| 16080 | case 2: |
| 16081 | // op: Rn |
| 16082 | return 16; |
| 16083 | case 1: |
| 16084 | // op: sat_imm |
| 16085 | return 0; |
| 16086 | case 3: |
| 16087 | // op: sh |
| 16088 | return 6; |
| 16089 | } |
| 16090 | break; |
| 16091 | } |
| 16092 | case ARM::t2SSAT16: |
| 16093 | case ARM::t2USAT16: { |
| 16094 | switch (OpNum) { |
| 16095 | case 0: |
| 16096 | // op: Rd |
| 16097 | return 8; |
| 16098 | case 2: |
| 16099 | // op: Rn |
| 16100 | return 16; |
| 16101 | case 1: |
| 16102 | // op: sat_imm |
| 16103 | return 0; |
| 16104 | } |
| 16105 | break; |
| 16106 | } |
| 16107 | case ARM::t2BFI: { |
| 16108 | switch (OpNum) { |
| 16109 | case 0: |
| 16110 | // op: Rd |
| 16111 | return 8; |
| 16112 | case 2: |
| 16113 | // op: Rn |
| 16114 | return 16; |
| 16115 | case 3: |
| 16116 | // op: imm |
| 16117 | return 0; |
| 16118 | } |
| 16119 | break; |
| 16120 | } |
| 16121 | case ARM::t2BFC: |
| 16122 | case ARM::t2MOVTi16: { |
| 16123 | switch (OpNum) { |
| 16124 | case 0: |
| 16125 | // op: Rd |
| 16126 | return 8; |
| 16127 | case 2: |
| 16128 | // op: imm |
| 16129 | return 0; |
| 16130 | } |
| 16131 | break; |
| 16132 | } |
| 16133 | case ARM::tMOVi8: { |
| 16134 | switch (OpNum) { |
| 16135 | case 0: |
| 16136 | // op: Rd |
| 16137 | return 8; |
| 16138 | case 2: |
| 16139 | // op: imm8 |
| 16140 | return 0; |
| 16141 | } |
| 16142 | break; |
| 16143 | } |
| 16144 | case ARM::t2PACG: { |
| 16145 | switch (OpNum) { |
| 16146 | case 0: |
| 16147 | // op: Rd |
| 16148 | return 8; |
| 16149 | case 3: |
| 16150 | // op: Rn |
| 16151 | return 16; |
| 16152 | case 4: |
| 16153 | // op: Rm |
| 16154 | return 0; |
| 16155 | } |
| 16156 | break; |
| 16157 | } |
| 16158 | case ARM::t2SBFX: |
| 16159 | case ARM::t2UBFX: { |
| 16160 | switch (OpNum) { |
| 16161 | case 0: |
| 16162 | // op: Rd |
| 16163 | return 8; |
| 16164 | case 3: |
| 16165 | // op: msb |
| 16166 | return 0; |
| 16167 | case 2: |
| 16168 | // op: lsb |
| 16169 | return 6; |
| 16170 | case 1: |
| 16171 | // op: Rn |
| 16172 | return 16; |
| 16173 | } |
| 16174 | break; |
| 16175 | } |
| 16176 | case ARM::t2MRS_AR: |
| 16177 | case ARM::t2MRSsys_AR: { |
| 16178 | switch (OpNum) { |
| 16179 | case 0: |
| 16180 | // op: Rd |
| 16181 | return 8; |
| 16182 | } |
| 16183 | break; |
| 16184 | } |
| 16185 | case ARM::t2SMLAL: |
| 16186 | case ARM::t2SMLALBB: |
| 16187 | case ARM::t2SMLALBT: |
| 16188 | case ARM::t2SMLALTB: |
| 16189 | case ARM::t2SMLALTT: |
| 16190 | case ARM::t2SMULL: |
| 16191 | case ARM::t2UMAAL: |
| 16192 | case ARM::t2UMLAL: |
| 16193 | case ARM::t2UMULL: { |
| 16194 | switch (OpNum) { |
| 16195 | case 0: |
| 16196 | // op: RdLo |
| 16197 | return 12; |
| 16198 | case 1: |
| 16199 | // op: RdHi |
| 16200 | return 8; |
| 16201 | case 2: |
| 16202 | // op: Rn |
| 16203 | return 16; |
| 16204 | case 3: |
| 16205 | // op: Rm |
| 16206 | return 0; |
| 16207 | } |
| 16208 | break; |
| 16209 | } |
| 16210 | case ARM::MVE_VMLADAVs16: |
| 16211 | case ARM::MVE_VMLADAVs32: |
| 16212 | case ARM::MVE_VMLADAVs8: |
| 16213 | case ARM::MVE_VMLADAVu16: |
| 16214 | case ARM::MVE_VMLADAVu32: |
| 16215 | case ARM::MVE_VMLADAVu8: |
| 16216 | case ARM::MVE_VMLADAVxs16: |
| 16217 | case ARM::MVE_VMLADAVxs32: |
| 16218 | case ARM::MVE_VMLADAVxs8: |
| 16219 | case ARM::MVE_VMLSDAVs16: |
| 16220 | case ARM::MVE_VMLSDAVs32: |
| 16221 | case ARM::MVE_VMLSDAVs8: |
| 16222 | case ARM::MVE_VMLSDAVxs16: |
| 16223 | case ARM::MVE_VMLSDAVxs32: |
| 16224 | case ARM::MVE_VMLSDAVxs8: { |
| 16225 | switch (OpNum) { |
| 16226 | case 0: |
| 16227 | // op: RdaDest |
| 16228 | return 13; |
| 16229 | case 2: |
| 16230 | // op: Qm |
| 16231 | return 1; |
| 16232 | case 1: |
| 16233 | // op: Qn |
| 16234 | return 17; |
| 16235 | } |
| 16236 | break; |
| 16237 | } |
| 16238 | case ARM::MVE_VMLADAVas16: |
| 16239 | case ARM::MVE_VMLADAVas32: |
| 16240 | case ARM::MVE_VMLADAVas8: |
| 16241 | case ARM::MVE_VMLADAVau16: |
| 16242 | case ARM::MVE_VMLADAVau32: |
| 16243 | case ARM::MVE_VMLADAVau8: |
| 16244 | case ARM::MVE_VMLADAVaxs16: |
| 16245 | case ARM::MVE_VMLADAVaxs32: |
| 16246 | case ARM::MVE_VMLADAVaxs8: |
| 16247 | case ARM::MVE_VMLSDAVas16: |
| 16248 | case ARM::MVE_VMLSDAVas32: |
| 16249 | case ARM::MVE_VMLSDAVas8: |
| 16250 | case ARM::MVE_VMLSDAVaxs16: |
| 16251 | case ARM::MVE_VMLSDAVaxs32: |
| 16252 | case ARM::MVE_VMLSDAVaxs8: { |
| 16253 | switch (OpNum) { |
| 16254 | case 0: |
| 16255 | // op: RdaDest |
| 16256 | return 13; |
| 16257 | case 3: |
| 16258 | // op: Qm |
| 16259 | return 1; |
| 16260 | case 2: |
| 16261 | // op: Qn |
| 16262 | return 17; |
| 16263 | } |
| 16264 | break; |
| 16265 | } |
| 16266 | case ARM::MVE_SQRSHR: |
| 16267 | case ARM::MVE_UQRSHL: { |
| 16268 | switch (OpNum) { |
| 16269 | case 0: |
| 16270 | // op: RdaDest |
| 16271 | return 16; |
| 16272 | case 2: |
| 16273 | // op: Rm |
| 16274 | return 12; |
| 16275 | } |
| 16276 | break; |
| 16277 | } |
| 16278 | case ARM::MVE_SQSHL: |
| 16279 | case ARM::MVE_SRSHR: |
| 16280 | case ARM::MVE_UQSHL: |
| 16281 | case ARM::MVE_URSHR: { |
| 16282 | switch (OpNum) { |
| 16283 | case 0: |
| 16284 | // op: RdaDest |
| 16285 | return 16; |
| 16286 | case 2: |
| 16287 | // op: imm |
| 16288 | return 6; |
| 16289 | } |
| 16290 | break; |
| 16291 | } |
| 16292 | case ARM::MVE_SQRSHRL: |
| 16293 | case ARM::MVE_UQRSHLL: { |
| 16294 | switch (OpNum) { |
| 16295 | case 0: |
| 16296 | // op: RdaLo |
| 16297 | return 17; |
| 16298 | case 1: |
| 16299 | // op: RdaHi |
| 16300 | return 9; |
| 16301 | case 4: |
| 16302 | // op: Rm |
| 16303 | return 12; |
| 16304 | case 5: |
| 16305 | // op: sat |
| 16306 | return 7; |
| 16307 | } |
| 16308 | break; |
| 16309 | } |
| 16310 | case ARM::MVE_ASRLr: |
| 16311 | case ARM::MVE_LSLLr: { |
| 16312 | switch (OpNum) { |
| 16313 | case 0: |
| 16314 | // op: RdaLo |
| 16315 | return 17; |
| 16316 | case 1: |
| 16317 | // op: RdaHi |
| 16318 | return 9; |
| 16319 | case 4: |
| 16320 | // op: Rm |
| 16321 | return 12; |
| 16322 | } |
| 16323 | break; |
| 16324 | } |
| 16325 | case ARM::MVE_ASRLi: |
| 16326 | case ARM::MVE_LSLLi: |
| 16327 | case ARM::MVE_LSRL: |
| 16328 | case ARM::MVE_SQSHLL: |
| 16329 | case ARM::MVE_SRSHRL: |
| 16330 | case ARM::MVE_UQSHLL: |
| 16331 | case ARM::MVE_URSHRL: { |
| 16332 | switch (OpNum) { |
| 16333 | case 0: |
| 16334 | // op: RdaLo |
| 16335 | return 17; |
| 16336 | case 1: |
| 16337 | // op: RdaHi |
| 16338 | return 9; |
| 16339 | case 4: |
| 16340 | // op: imm |
| 16341 | return 6; |
| 16342 | } |
| 16343 | break; |
| 16344 | } |
| 16345 | case ARM::MVE_VMLALDAVs16: |
| 16346 | case ARM::MVE_VMLALDAVs32: |
| 16347 | case ARM::MVE_VMLALDAVu16: |
| 16348 | case ARM::MVE_VMLALDAVu32: |
| 16349 | case ARM::MVE_VMLALDAVxs16: |
| 16350 | case ARM::MVE_VMLALDAVxs32: |
| 16351 | case ARM::MVE_VMLSLDAVs16: |
| 16352 | case ARM::MVE_VMLSLDAVs32: |
| 16353 | case ARM::MVE_VMLSLDAVxs16: |
| 16354 | case ARM::MVE_VMLSLDAVxs32: |
| 16355 | case ARM::MVE_VRMLALDAVHs32: |
| 16356 | case ARM::MVE_VRMLALDAVHu32: |
| 16357 | case ARM::MVE_VRMLALDAVHxs32: |
| 16358 | case ARM::MVE_VRMLSLDAVHs32: |
| 16359 | case ARM::MVE_VRMLSLDAVHxs32: { |
| 16360 | switch (OpNum) { |
| 16361 | case 0: |
| 16362 | // op: RdaLoDest |
| 16363 | return 13; |
| 16364 | case 1: |
| 16365 | // op: RdaHiDest |
| 16366 | return 20; |
| 16367 | case 3: |
| 16368 | // op: Qm |
| 16369 | return 1; |
| 16370 | case 2: |
| 16371 | // op: Qn |
| 16372 | return 17; |
| 16373 | } |
| 16374 | break; |
| 16375 | } |
| 16376 | case ARM::MVE_VMLALDAVas16: |
| 16377 | case ARM::MVE_VMLALDAVas32: |
| 16378 | case ARM::MVE_VMLALDAVau16: |
| 16379 | case ARM::MVE_VMLALDAVau32: |
| 16380 | case ARM::MVE_VMLALDAVaxs16: |
| 16381 | case ARM::MVE_VMLALDAVaxs32: |
| 16382 | case ARM::MVE_VMLSLDAVas16: |
| 16383 | case ARM::MVE_VMLSLDAVas32: |
| 16384 | case ARM::MVE_VMLSLDAVaxs16: |
| 16385 | case ARM::MVE_VMLSLDAVaxs32: |
| 16386 | case ARM::MVE_VRMLALDAVHas32: |
| 16387 | case ARM::MVE_VRMLALDAVHau32: |
| 16388 | case ARM::MVE_VRMLALDAVHaxs32: |
| 16389 | case ARM::MVE_VRMLSLDAVHas32: |
| 16390 | case ARM::MVE_VRMLSLDAVHaxs32: { |
| 16391 | switch (OpNum) { |
| 16392 | case 0: |
| 16393 | // op: RdaLoDest |
| 16394 | return 13; |
| 16395 | case 1: |
| 16396 | // op: RdaHiDest |
| 16397 | return 20; |
| 16398 | case 5: |
| 16399 | // op: Qm |
| 16400 | return 1; |
| 16401 | case 4: |
| 16402 | // op: Qn |
| 16403 | return 17; |
| 16404 | } |
| 16405 | break; |
| 16406 | } |
| 16407 | case ARM::tADDhirr: { |
| 16408 | switch (OpNum) { |
| 16409 | case 0: |
| 16410 | // op: Rdn |
| 16411 | return 0; |
| 16412 | case 2: |
| 16413 | // op: Rm |
| 16414 | return 3; |
| 16415 | } |
| 16416 | break; |
| 16417 | } |
| 16418 | case ARM::tADC: |
| 16419 | case ARM::tAND: |
| 16420 | case ARM::tASRrr: |
| 16421 | case ARM::tBIC: |
| 16422 | case ARM::tEOR: |
| 16423 | case ARM::tLSLrr: |
| 16424 | case ARM::tLSRrr: |
| 16425 | case ARM::tORR: |
| 16426 | case ARM::tROR: |
| 16427 | case ARM::tSBC: { |
| 16428 | switch (OpNum) { |
| 16429 | case 0: |
| 16430 | // op: Rdn |
| 16431 | return 0; |
| 16432 | case 3: |
| 16433 | // op: Rm |
| 16434 | return 3; |
| 16435 | } |
| 16436 | break; |
| 16437 | } |
| 16438 | case ARM::tADDrSP: { |
| 16439 | switch (OpNum) { |
| 16440 | case 0: |
| 16441 | // op: Rdn |
| 16442 | return 0; |
| 16443 | } |
| 16444 | break; |
| 16445 | } |
| 16446 | case ARM::tADDi8: |
| 16447 | case ARM::tSUBi8: { |
| 16448 | switch (OpNum) { |
| 16449 | case 0: |
| 16450 | // op: Rdn |
| 16451 | return 8; |
| 16452 | case 3: |
| 16453 | // op: imm8 |
| 16454 | return 0; |
| 16455 | } |
| 16456 | break; |
| 16457 | } |
| 16458 | case ARM::tBX: |
| 16459 | case ARM::tBXNS: { |
| 16460 | switch (OpNum) { |
| 16461 | case 0: |
| 16462 | // op: Rm |
| 16463 | return 3; |
| 16464 | } |
| 16465 | break; |
| 16466 | } |
| 16467 | case ARM::t2CMNzrr: |
| 16468 | case ARM::t2CMPrr: |
| 16469 | case ARM::t2TBB: |
| 16470 | case ARM::t2TBH: |
| 16471 | case ARM::t2TEQrr: |
| 16472 | case ARM::t2TSTrr: { |
| 16473 | switch (OpNum) { |
| 16474 | case 0: |
| 16475 | // op: Rn |
| 16476 | return 16; |
| 16477 | case 1: |
| 16478 | // op: Rm |
| 16479 | return 0; |
| 16480 | } |
| 16481 | break; |
| 16482 | } |
| 16483 | case ARM::t2CMNzrs: |
| 16484 | case ARM::t2CMPrs: |
| 16485 | case ARM::t2TEQrs: |
| 16486 | case ARM::t2TSTrs: { |
| 16487 | switch (OpNum) { |
| 16488 | case 0: |
| 16489 | // op: Rn |
| 16490 | return 16; |
| 16491 | case 1: |
| 16492 | // op: ShiftedRm |
| 16493 | return 0; |
| 16494 | } |
| 16495 | break; |
| 16496 | } |
| 16497 | case ARM::t2CMNri: |
| 16498 | case ARM::t2CMPri: |
| 16499 | case ARM::t2TEQri: |
| 16500 | case ARM::t2TSTri: { |
| 16501 | switch (OpNum) { |
| 16502 | case 0: |
| 16503 | // op: Rn |
| 16504 | return 16; |
| 16505 | case 1: |
| 16506 | // op: imm |
| 16507 | return 0; |
| 16508 | } |
| 16509 | break; |
| 16510 | } |
| 16511 | case ARM::t2LDMDB: |
| 16512 | case ARM::t2LDMIA: |
| 16513 | case ARM::t2STMDB: |
| 16514 | case ARM::t2STMIA: { |
| 16515 | switch (OpNum) { |
| 16516 | case 0: |
| 16517 | // op: Rn |
| 16518 | return 16; |
| 16519 | case 3: |
| 16520 | // op: regs |
| 16521 | return 0; |
| 16522 | } |
| 16523 | break; |
| 16524 | } |
| 16525 | case ARM::RFEDA: |
| 16526 | case ARM::RFEDA_UPD: |
| 16527 | case ARM::RFEDB: |
| 16528 | case ARM::RFEDB_UPD: |
| 16529 | case ARM::RFEIA: |
| 16530 | case ARM::RFEIA_UPD: |
| 16531 | case ARM::RFEIB: |
| 16532 | case ARM::RFEIB_UPD: |
| 16533 | case ARM::VLLDM: |
| 16534 | case ARM::VLLDM_T2: |
| 16535 | case ARM::VLSTM: |
| 16536 | case ARM::VLSTM_T2: |
| 16537 | case ARM::t2RFEDB: |
| 16538 | case ARM::t2RFEDBW: |
| 16539 | case ARM::t2RFEIA: |
| 16540 | case ARM::t2RFEIAW: { |
| 16541 | switch (OpNum) { |
| 16542 | case 0: |
| 16543 | // op: Rn |
| 16544 | return 16; |
| 16545 | } |
| 16546 | break; |
| 16547 | } |
| 16548 | case ARM::tCMPi8: { |
| 16549 | switch (OpNum) { |
| 16550 | case 0: |
| 16551 | // op: Rn |
| 16552 | return 8; |
| 16553 | case 1: |
| 16554 | // op: imm8 |
| 16555 | return 0; |
| 16556 | } |
| 16557 | break; |
| 16558 | } |
| 16559 | case ARM::tLDMIA: { |
| 16560 | switch (OpNum) { |
| 16561 | case 0: |
| 16562 | // op: Rn |
| 16563 | return 8; |
| 16564 | case 3: |
| 16565 | // op: regs |
| 16566 | return 0; |
| 16567 | } |
| 16568 | break; |
| 16569 | } |
| 16570 | case ARM::MVE_VMOV_rr_q: { |
| 16571 | switch (OpNum) { |
| 16572 | case 0: |
| 16573 | // op: Rt |
| 16574 | return 0; |
| 16575 | case 1: |
| 16576 | // op: Rt2 |
| 16577 | return 16; |
| 16578 | case 2: |
| 16579 | // op: Qd |
| 16580 | return 13; |
| 16581 | case 4: |
| 16582 | // op: idx2 |
| 16583 | return 4; |
| 16584 | } |
| 16585 | break; |
| 16586 | } |
| 16587 | case ARM::tLDRBi: |
| 16588 | case ARM::tLDRBr: |
| 16589 | case ARM::tLDRHi: |
| 16590 | case ARM::tLDRHr: |
| 16591 | case ARM::tLDRSB: |
| 16592 | case ARM::tLDRSH: |
| 16593 | case ARM::tLDRi: |
| 16594 | case ARM::tLDRr: |
| 16595 | case ARM::tSTRBi: |
| 16596 | case ARM::tSTRBr: |
| 16597 | case ARM::tSTRHi: |
| 16598 | case ARM::tSTRHr: |
| 16599 | case ARM::tSTRi: |
| 16600 | case ARM::tSTRr: { |
| 16601 | switch (OpNum) { |
| 16602 | case 0: |
| 16603 | // op: Rt |
| 16604 | return 0; |
| 16605 | case 1: |
| 16606 | // op: addr |
| 16607 | return 3; |
| 16608 | } |
| 16609 | break; |
| 16610 | } |
| 16611 | case ARM::MRRC2: |
| 16612 | case ARM::t2MRRC: |
| 16613 | case ARM::t2MRRC2: { |
| 16614 | switch (OpNum) { |
| 16615 | case 0: |
| 16616 | // op: Rt |
| 16617 | return 12; |
| 16618 | case 1: |
| 16619 | // op: Rt2 |
| 16620 | return 16; |
| 16621 | case 2: |
| 16622 | // op: cop |
| 16623 | return 8; |
| 16624 | case 3: |
| 16625 | // op: opc1 |
| 16626 | return 4; |
| 16627 | case 4: |
| 16628 | // op: CRm |
| 16629 | return 0; |
| 16630 | } |
| 16631 | break; |
| 16632 | } |
| 16633 | case ARM::t2LDRDi8: |
| 16634 | case ARM::t2STRDi8: { |
| 16635 | switch (OpNum) { |
| 16636 | case 0: |
| 16637 | // op: Rt |
| 16638 | return 12; |
| 16639 | case 1: |
| 16640 | // op: Rt2 |
| 16641 | return 8; |
| 16642 | case 2: |
| 16643 | // op: addr |
| 16644 | return 0; |
| 16645 | } |
| 16646 | break; |
| 16647 | } |
| 16648 | case ARM::t2LDRD_PRE: { |
| 16649 | switch (OpNum) { |
| 16650 | case 0: |
| 16651 | // op: Rt |
| 16652 | return 12; |
| 16653 | case 1: |
| 16654 | // op: Rt2 |
| 16655 | return 8; |
| 16656 | case 3: |
| 16657 | // op: addr |
| 16658 | return 0; |
| 16659 | } |
| 16660 | break; |
| 16661 | } |
| 16662 | case ARM::t2LDRD_POST: { |
| 16663 | switch (OpNum) { |
| 16664 | case 0: |
| 16665 | // op: Rt |
| 16666 | return 12; |
| 16667 | case 1: |
| 16668 | // op: Rt2 |
| 16669 | return 8; |
| 16670 | case 3: |
| 16671 | // op: addr |
| 16672 | return 16; |
| 16673 | case 4: |
| 16674 | // op: imm |
| 16675 | return 0; |
| 16676 | } |
| 16677 | break; |
| 16678 | } |
| 16679 | case ARM::t2LDRBT: |
| 16680 | case ARM::t2LDRBi12: |
| 16681 | case ARM::t2LDRBi8: |
| 16682 | case ARM::t2LDRBpci: |
| 16683 | case ARM::t2LDRBs: |
| 16684 | case ARM::t2LDREX: |
| 16685 | case ARM::t2LDRHT: |
| 16686 | case ARM::t2LDRHi12: |
| 16687 | case ARM::t2LDRHi8: |
| 16688 | case ARM::t2LDRHpci: |
| 16689 | case ARM::t2LDRHs: |
| 16690 | case ARM::t2LDRSBT: |
| 16691 | case ARM::t2LDRSBi12: |
| 16692 | case ARM::t2LDRSBi8: |
| 16693 | case ARM::t2LDRSBpci: |
| 16694 | case ARM::t2LDRSBs: |
| 16695 | case ARM::t2LDRSHT: |
| 16696 | case ARM::t2LDRSHi12: |
| 16697 | case ARM::t2LDRSHi8: |
| 16698 | case ARM::t2LDRSHpci: |
| 16699 | case ARM::t2LDRSHs: |
| 16700 | case ARM::t2LDRT: |
| 16701 | case ARM::t2LDRi12: |
| 16702 | case ARM::t2LDRi8: |
| 16703 | case ARM::t2LDRpci: |
| 16704 | case ARM::t2LDRs: |
| 16705 | case ARM::t2STRBT: |
| 16706 | case ARM::t2STRBi12: |
| 16707 | case ARM::t2STRBi8: |
| 16708 | case ARM::t2STRBs: |
| 16709 | case ARM::t2STRHT: |
| 16710 | case ARM::t2STRHi12: |
| 16711 | case ARM::t2STRHi8: |
| 16712 | case ARM::t2STRHs: |
| 16713 | case ARM::t2STRT: |
| 16714 | case ARM::t2STRi12: |
| 16715 | case ARM::t2STRi8: |
| 16716 | case ARM::t2STRs: { |
| 16717 | switch (OpNum) { |
| 16718 | case 0: |
| 16719 | // op: Rt |
| 16720 | return 12; |
| 16721 | case 1: |
| 16722 | // op: addr |
| 16723 | return 0; |
| 16724 | } |
| 16725 | break; |
| 16726 | } |
| 16727 | case ARM::t2LDA: |
| 16728 | case ARM::t2LDAB: |
| 16729 | case ARM::t2LDAEX: |
| 16730 | case ARM::t2LDAH: |
| 16731 | case ARM::t2STL: |
| 16732 | case ARM::t2STLB: |
| 16733 | case ARM::t2STLH: { |
| 16734 | switch (OpNum) { |
| 16735 | case 0: |
| 16736 | // op: Rt |
| 16737 | return 12; |
| 16738 | case 1: |
| 16739 | // op: addr |
| 16740 | return 16; |
| 16741 | } |
| 16742 | break; |
| 16743 | } |
| 16744 | case ARM::MRC2: |
| 16745 | case ARM::t2MRC: |
| 16746 | case ARM::t2MRC2: { |
| 16747 | switch (OpNum) { |
| 16748 | case 0: |
| 16749 | // op: Rt |
| 16750 | return 12; |
| 16751 | case 1: |
| 16752 | // op: cop |
| 16753 | return 8; |
| 16754 | case 2: |
| 16755 | // op: opc1 |
| 16756 | return 21; |
| 16757 | case 5: |
| 16758 | // op: opc2 |
| 16759 | return 5; |
| 16760 | case 4: |
| 16761 | // op: CRm |
| 16762 | return 0; |
| 16763 | case 3: |
| 16764 | // op: CRn |
| 16765 | return 16; |
| 16766 | } |
| 16767 | break; |
| 16768 | } |
| 16769 | case ARM::t2LDRB_POST: |
| 16770 | case ARM::t2LDRH_POST: |
| 16771 | case ARM::t2LDRSB_POST: |
| 16772 | case ARM::t2LDRSH_POST: |
| 16773 | case ARM::t2LDR_POST: { |
| 16774 | switch (OpNum) { |
| 16775 | case 0: |
| 16776 | // op: Rt |
| 16777 | return 12; |
| 16778 | case 2: |
| 16779 | // op: Rn |
| 16780 | return 16; |
| 16781 | case 3: |
| 16782 | // op: offset |
| 16783 | return 0; |
| 16784 | } |
| 16785 | break; |
| 16786 | } |
| 16787 | case ARM::t2LDRB_PRE: |
| 16788 | case ARM::t2LDRH_PRE: |
| 16789 | case ARM::t2LDRSB_PRE: |
| 16790 | case ARM::t2LDRSH_PRE: |
| 16791 | case ARM::t2LDR_PRE: { |
| 16792 | switch (OpNum) { |
| 16793 | case 0: |
| 16794 | // op: Rt |
| 16795 | return 12; |
| 16796 | case 2: |
| 16797 | // op: addr |
| 16798 | return 0; |
| 16799 | } |
| 16800 | break; |
| 16801 | } |
| 16802 | case ARM::tLDRpci: |
| 16803 | case ARM::tLDRspi: |
| 16804 | case ARM::tSTRspi: { |
| 16805 | switch (OpNum) { |
| 16806 | case 0: |
| 16807 | // op: Rt |
| 16808 | return 8; |
| 16809 | case 1: |
| 16810 | // op: addr |
| 16811 | return 0; |
| 16812 | } |
| 16813 | break; |
| 16814 | } |
| 16815 | case ARM::t2MSR_M: { |
| 16816 | switch (OpNum) { |
| 16817 | case 0: |
| 16818 | // op: SYSm |
| 16819 | return 0; |
| 16820 | case 1: |
| 16821 | // op: Rn |
| 16822 | return 16; |
| 16823 | } |
| 16824 | break; |
| 16825 | } |
| 16826 | case ARM::VCVTASD: |
| 16827 | case ARM::VCVTAUD: |
| 16828 | case ARM::VCVTMSD: |
| 16829 | case ARM::VCVTMUD: |
| 16830 | case ARM::VCVTNSD: |
| 16831 | case ARM::VCVTNUD: |
| 16832 | case ARM::VCVTPSD: |
| 16833 | case ARM::VCVTPUD: { |
| 16834 | switch (OpNum) { |
| 16835 | case 0: |
| 16836 | // op: Sd |
| 16837 | return 12; |
| 16838 | case 1: |
| 16839 | // op: Dm |
| 16840 | return 0; |
| 16841 | } |
| 16842 | break; |
| 16843 | } |
| 16844 | case ARM::VCVTASH: |
| 16845 | case ARM::VCVTASS: |
| 16846 | case ARM::VCVTAUH: |
| 16847 | case ARM::VCVTAUS: |
| 16848 | case ARM::VCVTMSH: |
| 16849 | case ARM::VCVTMSS: |
| 16850 | case ARM::VCVTMUH: |
| 16851 | case ARM::VCVTMUS: |
| 16852 | case ARM::VCVTNSH: |
| 16853 | case ARM::VCVTNSS: |
| 16854 | case ARM::VCVTNUH: |
| 16855 | case ARM::VCVTNUS: |
| 16856 | case ARM::VCVTPSH: |
| 16857 | case ARM::VCVTPSS: |
| 16858 | case ARM::VCVTPUH: |
| 16859 | case ARM::VCVTPUS: |
| 16860 | case ARM::VMOVH: |
| 16861 | case ARM::VRINTAH: |
| 16862 | case ARM::VRINTAS: |
| 16863 | case ARM::VRINTMH: |
| 16864 | case ARM::VRINTMS: |
| 16865 | case ARM::VRINTNH: |
| 16866 | case ARM::VRINTNS: |
| 16867 | case ARM::VRINTPH: |
| 16868 | case ARM::VRINTPS: { |
| 16869 | switch (OpNum) { |
| 16870 | case 0: |
| 16871 | // op: Sd |
| 16872 | return 12; |
| 16873 | case 1: |
| 16874 | // op: Sm |
| 16875 | return 0; |
| 16876 | } |
| 16877 | break; |
| 16878 | } |
| 16879 | case ARM::VFP_VMAXNMH: |
| 16880 | case ARM::VFP_VMAXNMS: |
| 16881 | case ARM::VFP_VMINNMH: |
| 16882 | case ARM::VFP_VMINNMS: |
| 16883 | case ARM::VSELEQH: |
| 16884 | case ARM::VSELEQS: |
| 16885 | case ARM::VSELGEH: |
| 16886 | case ARM::VSELGES: |
| 16887 | case ARM::VSELGTH: |
| 16888 | case ARM::VSELGTS: |
| 16889 | case ARM::VSELVSH: |
| 16890 | case ARM::VSELVSS: { |
| 16891 | switch (OpNum) { |
| 16892 | case 0: |
| 16893 | // op: Sd |
| 16894 | return 12; |
| 16895 | case 1: |
| 16896 | // op: Sn |
| 16897 | return 7; |
| 16898 | case 2: |
| 16899 | // op: Sm |
| 16900 | return 0; |
| 16901 | } |
| 16902 | break; |
| 16903 | } |
| 16904 | case ARM::VINSH: { |
| 16905 | switch (OpNum) { |
| 16906 | case 0: |
| 16907 | // op: Sd |
| 16908 | return 12; |
| 16909 | case 2: |
| 16910 | // op: Sm |
| 16911 | return 0; |
| 16912 | } |
| 16913 | break; |
| 16914 | } |
| 16915 | case ARM::VDUP16d: |
| 16916 | case ARM::VDUP16q: |
| 16917 | case ARM::VDUP32d: |
| 16918 | case ARM::VDUP32q: |
| 16919 | case ARM::VDUP8d: |
| 16920 | case ARM::VDUP8q: { |
| 16921 | switch (OpNum) { |
| 16922 | case 0: |
| 16923 | // op: V |
| 16924 | return 7; |
| 16925 | case 1: |
| 16926 | // op: R |
| 16927 | return 12; |
| 16928 | case 2: |
| 16929 | // op: p |
| 16930 | return 28; |
| 16931 | } |
| 16932 | break; |
| 16933 | } |
| 16934 | case ARM::VSETLNi32: { |
| 16935 | switch (OpNum) { |
| 16936 | case 0: |
| 16937 | // op: V |
| 16938 | return 7; |
| 16939 | case 2: |
| 16940 | // op: R |
| 16941 | return 12; |
| 16942 | case 4: |
| 16943 | // op: p |
| 16944 | return 28; |
| 16945 | case 3: |
| 16946 | // op: lane |
| 16947 | return 21; |
| 16948 | } |
| 16949 | break; |
| 16950 | } |
| 16951 | case ARM::VSETLNi8: { |
| 16952 | switch (OpNum) { |
| 16953 | case 0: |
| 16954 | // op: V |
| 16955 | return 7; |
| 16956 | case 2: |
| 16957 | // op: R |
| 16958 | return 12; |
| 16959 | case 4: |
| 16960 | // op: p |
| 16961 | return 28; |
| 16962 | case 3: |
| 16963 | // op: lane |
| 16964 | return 5; |
| 16965 | } |
| 16966 | break; |
| 16967 | } |
| 16968 | case ARM::VSETLNi16: { |
| 16969 | switch (OpNum) { |
| 16970 | case 0: |
| 16971 | // op: V |
| 16972 | return 7; |
| 16973 | case 2: |
| 16974 | // op: R |
| 16975 | return 12; |
| 16976 | case 4: |
| 16977 | // op: p |
| 16978 | return 28; |
| 16979 | case 3: |
| 16980 | // op: lane |
| 16981 | return 6; |
| 16982 | } |
| 16983 | break; |
| 16984 | } |
| 16985 | case ARM::MVE_VST20_16: |
| 16986 | case ARM::MVE_VST20_32: |
| 16987 | case ARM::MVE_VST20_8: |
| 16988 | case ARM::MVE_VST21_16: |
| 16989 | case ARM::MVE_VST21_32: |
| 16990 | case ARM::MVE_VST21_8: |
| 16991 | case ARM::MVE_VST40_16: |
| 16992 | case ARM::MVE_VST40_32: |
| 16993 | case ARM::MVE_VST40_8: |
| 16994 | case ARM::MVE_VST41_16: |
| 16995 | case ARM::MVE_VST41_32: |
| 16996 | case ARM::MVE_VST41_8: |
| 16997 | case ARM::MVE_VST42_16: |
| 16998 | case ARM::MVE_VST42_32: |
| 16999 | case ARM::MVE_VST42_8: |
| 17000 | case ARM::MVE_VST43_16: |
| 17001 | case ARM::MVE_VST43_32: |
| 17002 | case ARM::MVE_VST43_8: { |
| 17003 | switch (OpNum) { |
| 17004 | case 0: |
| 17005 | // op: VQd |
| 17006 | return 13; |
| 17007 | case 1: |
| 17008 | // op: Rn |
| 17009 | return 16; |
| 17010 | } |
| 17011 | break; |
| 17012 | } |
| 17013 | case ARM::MVE_VLD20_16: |
| 17014 | case ARM::MVE_VLD20_32: |
| 17015 | case ARM::MVE_VLD20_8: |
| 17016 | case ARM::MVE_VLD21_16: |
| 17017 | case ARM::MVE_VLD21_32: |
| 17018 | case ARM::MVE_VLD21_8: |
| 17019 | case ARM::MVE_VLD40_16: |
| 17020 | case ARM::MVE_VLD40_32: |
| 17021 | case ARM::MVE_VLD40_8: |
| 17022 | case ARM::MVE_VLD41_16: |
| 17023 | case ARM::MVE_VLD41_32: |
| 17024 | case ARM::MVE_VLD41_8: |
| 17025 | case ARM::MVE_VLD42_16: |
| 17026 | case ARM::MVE_VLD42_32: |
| 17027 | case ARM::MVE_VLD42_8: |
| 17028 | case ARM::MVE_VLD43_16: |
| 17029 | case ARM::MVE_VLD43_32: |
| 17030 | case ARM::MVE_VLD43_8: { |
| 17031 | switch (OpNum) { |
| 17032 | case 0: |
| 17033 | // op: VQd |
| 17034 | return 13; |
| 17035 | case 2: |
| 17036 | // op: Rn |
| 17037 | return 16; |
| 17038 | } |
| 17039 | break; |
| 17040 | } |
| 17041 | case ARM::MVE_VLD20_16_wb: |
| 17042 | case ARM::MVE_VLD20_32_wb: |
| 17043 | case ARM::MVE_VLD20_8_wb: |
| 17044 | case ARM::MVE_VLD21_16_wb: |
| 17045 | case ARM::MVE_VLD21_32_wb: |
| 17046 | case ARM::MVE_VLD21_8_wb: |
| 17047 | case ARM::MVE_VLD40_16_wb: |
| 17048 | case ARM::MVE_VLD40_32_wb: |
| 17049 | case ARM::MVE_VLD40_8_wb: |
| 17050 | case ARM::MVE_VLD41_16_wb: |
| 17051 | case ARM::MVE_VLD41_32_wb: |
| 17052 | case ARM::MVE_VLD41_8_wb: |
| 17053 | case ARM::MVE_VLD42_16_wb: |
| 17054 | case ARM::MVE_VLD42_32_wb: |
| 17055 | case ARM::MVE_VLD42_8_wb: |
| 17056 | case ARM::MVE_VLD43_16_wb: |
| 17057 | case ARM::MVE_VLD43_32_wb: |
| 17058 | case ARM::MVE_VLD43_8_wb: { |
| 17059 | switch (OpNum) { |
| 17060 | case 0: |
| 17061 | // op: VQd |
| 17062 | return 13; |
| 17063 | case 3: |
| 17064 | // op: Rn |
| 17065 | return 16; |
| 17066 | } |
| 17067 | break; |
| 17068 | } |
| 17069 | case ARM::VLD1LNd8: { |
| 17070 | switch (OpNum) { |
| 17071 | case 0: |
| 17072 | // op: Vd |
| 17073 | return 12; |
| 17074 | case 1: |
| 17075 | // op: Rn |
| 17076 | return 16; |
| 17077 | case 4: |
| 17078 | // op: lane |
| 17079 | return 5; |
| 17080 | } |
| 17081 | break; |
| 17082 | } |
| 17083 | case ARM::VLD1LNd16: { |
| 17084 | switch (OpNum) { |
| 17085 | case 0: |
| 17086 | // op: Vd |
| 17087 | return 12; |
| 17088 | case 1: |
| 17089 | // op: Rn |
| 17090 | return 4; |
| 17091 | case 4: |
| 17092 | // op: lane |
| 17093 | return 6; |
| 17094 | } |
| 17095 | break; |
| 17096 | } |
| 17097 | case ARM::VLD1LNd32: { |
| 17098 | switch (OpNum) { |
| 17099 | case 0: |
| 17100 | // op: Vd |
| 17101 | return 12; |
| 17102 | case 1: |
| 17103 | // op: Rn |
| 17104 | return 4; |
| 17105 | case 4: |
| 17106 | // op: lane |
| 17107 | return 7; |
| 17108 | } |
| 17109 | break; |
| 17110 | } |
| 17111 | case ARM::VLD1DUPd16: |
| 17112 | case ARM::VLD1DUPd32: |
| 17113 | case ARM::VLD1DUPd8: |
| 17114 | case ARM::VLD1DUPq16: |
| 17115 | case ARM::VLD1DUPq32: |
| 17116 | case ARM::VLD1DUPq8: |
| 17117 | case ARM::VLD1d16: |
| 17118 | case ARM::VLD1d16Q: |
| 17119 | case ARM::VLD1d16T: |
| 17120 | case ARM::VLD1d32: |
| 17121 | case ARM::VLD1d32Q: |
| 17122 | case ARM::VLD1d32T: |
| 17123 | case ARM::VLD1d64: |
| 17124 | case ARM::VLD1d64Q: |
| 17125 | case ARM::VLD1d64T: |
| 17126 | case ARM::VLD1d8: |
| 17127 | case ARM::VLD1d8Q: |
| 17128 | case ARM::VLD1d8T: |
| 17129 | case ARM::VLD1q16: |
| 17130 | case ARM::VLD1q32: |
| 17131 | case ARM::VLD1q64: |
| 17132 | case ARM::VLD1q8: |
| 17133 | case ARM::VLD2DUPd16: |
| 17134 | case ARM::VLD2DUPd16x2: |
| 17135 | case ARM::VLD2DUPd32: |
| 17136 | case ARM::VLD2DUPd32x2: |
| 17137 | case ARM::VLD2DUPd8: |
| 17138 | case ARM::VLD2DUPd8x2: |
| 17139 | case ARM::VLD2b16: |
| 17140 | case ARM::VLD2b32: |
| 17141 | case ARM::VLD2b8: |
| 17142 | case ARM::VLD2d16: |
| 17143 | case ARM::VLD2d32: |
| 17144 | case ARM::VLD2d8: |
| 17145 | case ARM::VLD2q16: |
| 17146 | case ARM::VLD2q32: |
| 17147 | case ARM::VLD2q8: { |
| 17148 | switch (OpNum) { |
| 17149 | case 0: |
| 17150 | // op: Vd |
| 17151 | return 12; |
| 17152 | case 1: |
| 17153 | // op: Rn |
| 17154 | return 4; |
| 17155 | } |
| 17156 | break; |
| 17157 | } |
| 17158 | case ARM::VBICiv2i32: |
| 17159 | case ARM::VBICiv4i16: |
| 17160 | case ARM::VBICiv4i32: |
| 17161 | case ARM::VBICiv8i16: |
| 17162 | case ARM::VMOVv16i8: |
| 17163 | case ARM::VMOVv1i64: |
| 17164 | case ARM::VMOVv2f32: |
| 17165 | case ARM::VMOVv2i32: |
| 17166 | case ARM::VMOVv2i64: |
| 17167 | case ARM::VMOVv4f32: |
| 17168 | case ARM::VMOVv4i16: |
| 17169 | case ARM::VMOVv4i32: |
| 17170 | case ARM::VMOVv8i16: |
| 17171 | case ARM::VMOVv8i8: |
| 17172 | case ARM::VMVNv2i32: |
| 17173 | case ARM::VMVNv4i16: |
| 17174 | case ARM::VMVNv4i32: |
| 17175 | case ARM::VMVNv8i16: |
| 17176 | case ARM::VORRiv2i32: |
| 17177 | case ARM::VORRiv4i16: |
| 17178 | case ARM::VORRiv4i32: |
| 17179 | case ARM::VORRiv8i16: { |
| 17180 | switch (OpNum) { |
| 17181 | case 0: |
| 17182 | // op: Vd |
| 17183 | return 12; |
| 17184 | case 1: |
| 17185 | // op: SIMM |
| 17186 | return 0; |
| 17187 | } |
| 17188 | break; |
| 17189 | } |
| 17190 | case ARM::VCVTf2xsd: |
| 17191 | case ARM::VCVTf2xsq: |
| 17192 | case ARM::VCVTf2xud: |
| 17193 | case ARM::VCVTf2xuq: |
| 17194 | case ARM::VCVTh2xsd: |
| 17195 | case ARM::VCVTh2xsq: |
| 17196 | case ARM::VCVTh2xud: |
| 17197 | case ARM::VCVTh2xuq: |
| 17198 | case ARM::VCVTxs2fd: |
| 17199 | case ARM::VCVTxs2fq: |
| 17200 | case ARM::VCVTxs2hd: |
| 17201 | case ARM::VCVTxs2hq: |
| 17202 | case ARM::VCVTxu2fd: |
| 17203 | case ARM::VCVTxu2fq: |
| 17204 | case ARM::VCVTxu2hd: |
| 17205 | case ARM::VCVTxu2hq: |
| 17206 | case ARM::VQRSHRNsv2i32: |
| 17207 | case ARM::VQRSHRNsv4i16: |
| 17208 | case ARM::VQRSHRNsv8i8: |
| 17209 | case ARM::VQRSHRNuv2i32: |
| 17210 | case ARM::VQRSHRNuv4i16: |
| 17211 | case ARM::VQRSHRNuv8i8: |
| 17212 | case ARM::VQRSHRUNv2i32: |
| 17213 | case ARM::VQRSHRUNv4i16: |
| 17214 | case ARM::VQRSHRUNv8i8: |
| 17215 | case ARM::VQSHLsiv16i8: |
| 17216 | case ARM::VQSHLsiv1i64: |
| 17217 | case ARM::VQSHLsiv2i32: |
| 17218 | case ARM::VQSHLsiv2i64: |
| 17219 | case ARM::VQSHLsiv4i16: |
| 17220 | case ARM::VQSHLsiv4i32: |
| 17221 | case ARM::VQSHLsiv8i16: |
| 17222 | case ARM::VQSHLsiv8i8: |
| 17223 | case ARM::VQSHLsuv16i8: |
| 17224 | case ARM::VQSHLsuv1i64: |
| 17225 | case ARM::VQSHLsuv2i32: |
| 17226 | case ARM::VQSHLsuv2i64: |
| 17227 | case ARM::VQSHLsuv4i16: |
| 17228 | case ARM::VQSHLsuv4i32: |
| 17229 | case ARM::VQSHLsuv8i16: |
| 17230 | case ARM::VQSHLsuv8i8: |
| 17231 | case ARM::VQSHLuiv16i8: |
| 17232 | case ARM::VQSHLuiv1i64: |
| 17233 | case ARM::VQSHLuiv2i32: |
| 17234 | case ARM::VQSHLuiv2i64: |
| 17235 | case ARM::VQSHLuiv4i16: |
| 17236 | case ARM::VQSHLuiv4i32: |
| 17237 | case ARM::VQSHLuiv8i16: |
| 17238 | case ARM::VQSHLuiv8i8: |
| 17239 | case ARM::VQSHRNsv2i32: |
| 17240 | case ARM::VQSHRNsv4i16: |
| 17241 | case ARM::VQSHRNsv8i8: |
| 17242 | case ARM::VQSHRNuv2i32: |
| 17243 | case ARM::VQSHRNuv4i16: |
| 17244 | case ARM::VQSHRNuv8i8: |
| 17245 | case ARM::VQSHRUNv2i32: |
| 17246 | case ARM::VQSHRUNv4i16: |
| 17247 | case ARM::VQSHRUNv8i8: |
| 17248 | case ARM::VRSHRNv2i32: |
| 17249 | case ARM::VRSHRNv4i16: |
| 17250 | case ARM::VRSHRNv8i8: |
| 17251 | case ARM::VRSHRsv16i8: |
| 17252 | case ARM::VRSHRsv1i64: |
| 17253 | case ARM::VRSHRsv2i32: |
| 17254 | case ARM::VRSHRsv2i64: |
| 17255 | case ARM::VRSHRsv4i16: |
| 17256 | case ARM::VRSHRsv4i32: |
| 17257 | case ARM::VRSHRsv8i16: |
| 17258 | case ARM::VRSHRsv8i8: |
| 17259 | case ARM::VRSHRuv16i8: |
| 17260 | case ARM::VRSHRuv1i64: |
| 17261 | case ARM::VRSHRuv2i32: |
| 17262 | case ARM::VRSHRuv2i64: |
| 17263 | case ARM::VRSHRuv4i16: |
| 17264 | case ARM::VRSHRuv4i32: |
| 17265 | case ARM::VRSHRuv8i16: |
| 17266 | case ARM::VRSHRuv8i8: |
| 17267 | case ARM::VSHLLsv2i64: |
| 17268 | case ARM::VSHLLsv4i32: |
| 17269 | case ARM::VSHLLsv8i16: |
| 17270 | case ARM::VSHLLuv2i64: |
| 17271 | case ARM::VSHLLuv4i32: |
| 17272 | case ARM::VSHLLuv8i16: |
| 17273 | case ARM::VSHLiv16i8: |
| 17274 | case ARM::VSHLiv1i64: |
| 17275 | case ARM::VSHLiv2i32: |
| 17276 | case ARM::VSHLiv2i64: |
| 17277 | case ARM::VSHLiv4i16: |
| 17278 | case ARM::VSHLiv4i32: |
| 17279 | case ARM::VSHLiv8i16: |
| 17280 | case ARM::VSHLiv8i8: |
| 17281 | case ARM::VSHRNv2i32: |
| 17282 | case ARM::VSHRNv4i16: |
| 17283 | case ARM::VSHRNv8i8: |
| 17284 | case ARM::VSHRsv16i8: |
| 17285 | case ARM::VSHRsv1i64: |
| 17286 | case ARM::VSHRsv2i32: |
| 17287 | case ARM::VSHRsv2i64: |
| 17288 | case ARM::VSHRsv4i16: |
| 17289 | case ARM::VSHRsv4i32: |
| 17290 | case ARM::VSHRsv8i16: |
| 17291 | case ARM::VSHRsv8i8: |
| 17292 | case ARM::VSHRuv16i8: |
| 17293 | case ARM::VSHRuv1i64: |
| 17294 | case ARM::VSHRuv2i32: |
| 17295 | case ARM::VSHRuv2i64: |
| 17296 | case ARM::VSHRuv4i16: |
| 17297 | case ARM::VSHRuv4i32: |
| 17298 | case ARM::VSHRuv8i16: |
| 17299 | case ARM::VSHRuv8i8: { |
| 17300 | switch (OpNum) { |
| 17301 | case 0: |
| 17302 | // op: Vd |
| 17303 | return 12; |
| 17304 | case 1: |
| 17305 | // op: Vm |
| 17306 | return 0; |
| 17307 | case 2: |
| 17308 | // op: SIMM |
| 17309 | return 16; |
| 17310 | } |
| 17311 | break; |
| 17312 | } |
| 17313 | case ARM::VDUPLN8d: |
| 17314 | case ARM::VDUPLN8q: { |
| 17315 | switch (OpNum) { |
| 17316 | case 0: |
| 17317 | // op: Vd |
| 17318 | return 12; |
| 17319 | case 1: |
| 17320 | // op: Vm |
| 17321 | return 0; |
| 17322 | case 2: |
| 17323 | // op: lane |
| 17324 | return 17; |
| 17325 | } |
| 17326 | break; |
| 17327 | } |
| 17328 | case ARM::VDUPLN16d: |
| 17329 | case ARM::VDUPLN16q: { |
| 17330 | switch (OpNum) { |
| 17331 | case 0: |
| 17332 | // op: Vd |
| 17333 | return 12; |
| 17334 | case 1: |
| 17335 | // op: Vm |
| 17336 | return 0; |
| 17337 | case 2: |
| 17338 | // op: lane |
| 17339 | return 18; |
| 17340 | } |
| 17341 | break; |
| 17342 | } |
| 17343 | case ARM::VDUPLN32d: |
| 17344 | case ARM::VDUPLN32q: { |
| 17345 | switch (OpNum) { |
| 17346 | case 0: |
| 17347 | // op: Vd |
| 17348 | return 12; |
| 17349 | case 1: |
| 17350 | // op: Vm |
| 17351 | return 0; |
| 17352 | case 2: |
| 17353 | // op: lane |
| 17354 | return 19; |
| 17355 | } |
| 17356 | break; |
| 17357 | } |
| 17358 | case ARM::AESIMC: |
| 17359 | case ARM::AESMC: |
| 17360 | case ARM::BF16_VCVT: |
| 17361 | case ARM::SHA1H: |
| 17362 | case ARM::VABSfd: |
| 17363 | case ARM::VABSfq: |
| 17364 | case ARM::VABShd: |
| 17365 | case ARM::VABShq: |
| 17366 | case ARM::VABSv16i8: |
| 17367 | case ARM::VABSv2i32: |
| 17368 | case ARM::VABSv4i16: |
| 17369 | case ARM::VABSv4i32: |
| 17370 | case ARM::VABSv8i16: |
| 17371 | case ARM::VABSv8i8: |
| 17372 | case ARM::VCEQzv16i8: |
| 17373 | case ARM::VCEQzv2f32: |
| 17374 | case ARM::VCEQzv2i32: |
| 17375 | case ARM::VCEQzv4f16: |
| 17376 | case ARM::VCEQzv4f32: |
| 17377 | case ARM::VCEQzv4i16: |
| 17378 | case ARM::VCEQzv4i32: |
| 17379 | case ARM::VCEQzv8f16: |
| 17380 | case ARM::VCEQzv8i16: |
| 17381 | case ARM::VCEQzv8i8: |
| 17382 | case ARM::VCGEzv16i8: |
| 17383 | case ARM::VCGEzv2f32: |
| 17384 | case ARM::VCGEzv2i32: |
| 17385 | case ARM::VCGEzv4f16: |
| 17386 | case ARM::VCGEzv4f32: |
| 17387 | case ARM::VCGEzv4i16: |
| 17388 | case ARM::VCGEzv4i32: |
| 17389 | case ARM::VCGEzv8f16: |
| 17390 | case ARM::VCGEzv8i16: |
| 17391 | case ARM::VCGEzv8i8: |
| 17392 | case ARM::VCGTzv16i8: |
| 17393 | case ARM::VCGTzv2f32: |
| 17394 | case ARM::VCGTzv2i32: |
| 17395 | case ARM::VCGTzv4f16: |
| 17396 | case ARM::VCGTzv4f32: |
| 17397 | case ARM::VCGTzv4i16: |
| 17398 | case ARM::VCGTzv4i32: |
| 17399 | case ARM::VCGTzv8f16: |
| 17400 | case ARM::VCGTzv8i16: |
| 17401 | case ARM::VCGTzv8i8: |
| 17402 | case ARM::VCLEzv16i8: |
| 17403 | case ARM::VCLEzv2f32: |
| 17404 | case ARM::VCLEzv2i32: |
| 17405 | case ARM::VCLEzv4f16: |
| 17406 | case ARM::VCLEzv4f32: |
| 17407 | case ARM::VCLEzv4i16: |
| 17408 | case ARM::VCLEzv4i32: |
| 17409 | case ARM::VCLEzv8f16: |
| 17410 | case ARM::VCLEzv8i16: |
| 17411 | case ARM::VCLEzv8i8: |
| 17412 | case ARM::VCLSv16i8: |
| 17413 | case ARM::VCLSv2i32: |
| 17414 | case ARM::VCLSv4i16: |
| 17415 | case ARM::VCLSv4i32: |
| 17416 | case ARM::VCLSv8i16: |
| 17417 | case ARM::VCLSv8i8: |
| 17418 | case ARM::VCLTzv16i8: |
| 17419 | case ARM::VCLTzv2f32: |
| 17420 | case ARM::VCLTzv2i32: |
| 17421 | case ARM::VCLTzv4f16: |
| 17422 | case ARM::VCLTzv4f32: |
| 17423 | case ARM::VCLTzv4i16: |
| 17424 | case ARM::VCLTzv4i32: |
| 17425 | case ARM::VCLTzv8f16: |
| 17426 | case ARM::VCLTzv8i16: |
| 17427 | case ARM::VCLTzv8i8: |
| 17428 | case ARM::VCLZv16i8: |
| 17429 | case ARM::VCLZv2i32: |
| 17430 | case ARM::VCLZv4i16: |
| 17431 | case ARM::VCLZv4i32: |
| 17432 | case ARM::VCLZv8i16: |
| 17433 | case ARM::VCLZv8i8: |
| 17434 | case ARM::VCNTd: |
| 17435 | case ARM::VCNTq: |
| 17436 | case ARM::VCVTANSDf: |
| 17437 | case ARM::VCVTANSDh: |
| 17438 | case ARM::VCVTANSQf: |
| 17439 | case ARM::VCVTANSQh: |
| 17440 | case ARM::VCVTANUDf: |
| 17441 | case ARM::VCVTANUDh: |
| 17442 | case ARM::VCVTANUQf: |
| 17443 | case ARM::VCVTANUQh: |
| 17444 | case ARM::VCVTMNSDf: |
| 17445 | case ARM::VCVTMNSDh: |
| 17446 | case ARM::VCVTMNSQf: |
| 17447 | case ARM::VCVTMNSQh: |
| 17448 | case ARM::VCVTMNUDf: |
| 17449 | case ARM::VCVTMNUDh: |
| 17450 | case ARM::VCVTMNUQf: |
| 17451 | case ARM::VCVTMNUQh: |
| 17452 | case ARM::VCVTNNSDf: |
| 17453 | case ARM::VCVTNNSDh: |
| 17454 | case ARM::VCVTNNSQf: |
| 17455 | case ARM::VCVTNNSQh: |
| 17456 | case ARM::VCVTNNUDf: |
| 17457 | case ARM::VCVTNNUDh: |
| 17458 | case ARM::VCVTNNUQf: |
| 17459 | case ARM::VCVTNNUQh: |
| 17460 | case ARM::VCVTPNSDf: |
| 17461 | case ARM::VCVTPNSDh: |
| 17462 | case ARM::VCVTPNSQf: |
| 17463 | case ARM::VCVTPNSQh: |
| 17464 | case ARM::VCVTPNUDf: |
| 17465 | case ARM::VCVTPNUDh: |
| 17466 | case ARM::VCVTPNUQf: |
| 17467 | case ARM::VCVTPNUQh: |
| 17468 | case ARM::VCVTf2h: |
| 17469 | case ARM::VCVTf2sd: |
| 17470 | case ARM::VCVTf2sq: |
| 17471 | case ARM::VCVTf2ud: |
| 17472 | case ARM::VCVTf2uq: |
| 17473 | case ARM::VCVTh2f: |
| 17474 | case ARM::VCVTh2sd: |
| 17475 | case ARM::VCVTh2sq: |
| 17476 | case ARM::VCVTh2ud: |
| 17477 | case ARM::VCVTh2uq: |
| 17478 | case ARM::VCVTs2fd: |
| 17479 | case ARM::VCVTs2fq: |
| 17480 | case ARM::VCVTs2hd: |
| 17481 | case ARM::VCVTs2hq: |
| 17482 | case ARM::VCVTu2fd: |
| 17483 | case ARM::VCVTu2fq: |
| 17484 | case ARM::VCVTu2hd: |
| 17485 | case ARM::VCVTu2hq: |
| 17486 | case ARM::VMOVLsv2i64: |
| 17487 | case ARM::VMOVLsv4i32: |
| 17488 | case ARM::VMOVLsv8i16: |
| 17489 | case ARM::VMOVLuv2i64: |
| 17490 | case ARM::VMOVLuv4i32: |
| 17491 | case ARM::VMOVLuv8i16: |
| 17492 | case ARM::VMOVNv2i32: |
| 17493 | case ARM::VMOVNv4i16: |
| 17494 | case ARM::VMOVNv8i8: |
| 17495 | case ARM::VMVNd: |
| 17496 | case ARM::VMVNq: |
| 17497 | case ARM::VNEGf32q: |
| 17498 | case ARM::VNEGfd: |
| 17499 | case ARM::VNEGhd: |
| 17500 | case ARM::VNEGhq: |
| 17501 | case ARM::VNEGs16d: |
| 17502 | case ARM::VNEGs16q: |
| 17503 | case ARM::VNEGs32d: |
| 17504 | case ARM::VNEGs32q: |
| 17505 | case ARM::VNEGs8d: |
| 17506 | case ARM::VNEGs8q: |
| 17507 | case ARM::VPADDLsv16i8: |
| 17508 | case ARM::VPADDLsv2i32: |
| 17509 | case ARM::VPADDLsv4i16: |
| 17510 | case ARM::VPADDLsv4i32: |
| 17511 | case ARM::VPADDLsv8i16: |
| 17512 | case ARM::VPADDLsv8i8: |
| 17513 | case ARM::VPADDLuv16i8: |
| 17514 | case ARM::VPADDLuv2i32: |
| 17515 | case ARM::VPADDLuv4i16: |
| 17516 | case ARM::VPADDLuv4i32: |
| 17517 | case ARM::VPADDLuv8i16: |
| 17518 | case ARM::VPADDLuv8i8: |
| 17519 | case ARM::VQABSv16i8: |
| 17520 | case ARM::VQABSv2i32: |
| 17521 | case ARM::VQABSv4i16: |
| 17522 | case ARM::VQABSv4i32: |
| 17523 | case ARM::VQABSv8i16: |
| 17524 | case ARM::VQABSv8i8: |
| 17525 | case ARM::VQMOVNsuv2i32: |
| 17526 | case ARM::VQMOVNsuv4i16: |
| 17527 | case ARM::VQMOVNsuv8i8: |
| 17528 | case ARM::VQMOVNsv2i32: |
| 17529 | case ARM::VQMOVNsv4i16: |
| 17530 | case ARM::VQMOVNsv8i8: |
| 17531 | case ARM::VQMOVNuv2i32: |
| 17532 | case ARM::VQMOVNuv4i16: |
| 17533 | case ARM::VQMOVNuv8i8: |
| 17534 | case ARM::VQNEGv16i8: |
| 17535 | case ARM::VQNEGv2i32: |
| 17536 | case ARM::VQNEGv4i16: |
| 17537 | case ARM::VQNEGv4i32: |
| 17538 | case ARM::VQNEGv8i16: |
| 17539 | case ARM::VQNEGv8i8: |
| 17540 | case ARM::VRECPEd: |
| 17541 | case ARM::VRECPEfd: |
| 17542 | case ARM::VRECPEfq: |
| 17543 | case ARM::VRECPEhd: |
| 17544 | case ARM::VRECPEhq: |
| 17545 | case ARM::VRECPEq: |
| 17546 | case ARM::VREV16d8: |
| 17547 | case ARM::VREV16q8: |
| 17548 | case ARM::VREV32d16: |
| 17549 | case ARM::VREV32d8: |
| 17550 | case ARM::VREV32q16: |
| 17551 | case ARM::VREV32q8: |
| 17552 | case ARM::VREV64d16: |
| 17553 | case ARM::VREV64d32: |
| 17554 | case ARM::VREV64d8: |
| 17555 | case ARM::VREV64q16: |
| 17556 | case ARM::VREV64q32: |
| 17557 | case ARM::VREV64q8: |
| 17558 | case ARM::VRINTANDf: |
| 17559 | case ARM::VRINTANDh: |
| 17560 | case ARM::VRINTANQf: |
| 17561 | case ARM::VRINTANQh: |
| 17562 | case ARM::VRINTMNDf: |
| 17563 | case ARM::VRINTMNDh: |
| 17564 | case ARM::VRINTMNQf: |
| 17565 | case ARM::VRINTMNQh: |
| 17566 | case ARM::VRINTNNDf: |
| 17567 | case ARM::VRINTNNDh: |
| 17568 | case ARM::VRINTNNQf: |
| 17569 | case ARM::VRINTNNQh: |
| 17570 | case ARM::VRINTPNDf: |
| 17571 | case ARM::VRINTPNDh: |
| 17572 | case ARM::VRINTPNQf: |
| 17573 | case ARM::VRINTPNQh: |
| 17574 | case ARM::VRINTXNDf: |
| 17575 | case ARM::VRINTXNDh: |
| 17576 | case ARM::VRINTXNQf: |
| 17577 | case ARM::VRINTXNQh: |
| 17578 | case ARM::VRINTZNDf: |
| 17579 | case ARM::VRINTZNDh: |
| 17580 | case ARM::VRINTZNQf: |
| 17581 | case ARM::VRINTZNQh: |
| 17582 | case ARM::VRSQRTEd: |
| 17583 | case ARM::VRSQRTEfd: |
| 17584 | case ARM::VRSQRTEfq: |
| 17585 | case ARM::VRSQRTEhd: |
| 17586 | case ARM::VRSQRTEhq: |
| 17587 | case ARM::VRSQRTEq: |
| 17588 | case ARM::VSHLLi16: |
| 17589 | case ARM::VSHLLi32: |
| 17590 | case ARM::VSHLLi8: |
| 17591 | case ARM::VSWPd: |
| 17592 | case ARM::VSWPq: |
| 17593 | case ARM::VTRNd16: |
| 17594 | case ARM::VTRNd32: |
| 17595 | case ARM::VTRNd8: |
| 17596 | case ARM::VTRNq16: |
| 17597 | case ARM::VTRNq32: |
| 17598 | case ARM::VTRNq8: |
| 17599 | case ARM::VUZPd16: |
| 17600 | case ARM::VUZPd8: |
| 17601 | case ARM::VUZPq16: |
| 17602 | case ARM::VUZPq32: |
| 17603 | case ARM::VUZPq8: |
| 17604 | case ARM::VZIPd16: |
| 17605 | case ARM::VZIPd8: |
| 17606 | case ARM::VZIPq16: |
| 17607 | case ARM::VZIPq32: |
| 17608 | case ARM::VZIPq8: { |
| 17609 | switch (OpNum) { |
| 17610 | case 0: |
| 17611 | // op: Vd |
| 17612 | return 12; |
| 17613 | case 1: |
| 17614 | // op: Vm |
| 17615 | return 0; |
| 17616 | } |
| 17617 | break; |
| 17618 | } |
| 17619 | case ARM::VFMALDI: |
| 17620 | case ARM::VFMALQI: |
| 17621 | case ARM::VFMSLDI: |
| 17622 | case ARM::VFMSLQI: { |
| 17623 | switch (OpNum) { |
| 17624 | case 0: |
| 17625 | // op: Vd |
| 17626 | return 12; |
| 17627 | case 1: |
| 17628 | // op: Vn |
| 17629 | return 7; |
| 17630 | case 2: |
| 17631 | // op: Vm |
| 17632 | return 0; |
| 17633 | case 3: |
| 17634 | // op: idx |
| 17635 | return 3; |
| 17636 | } |
| 17637 | break; |
| 17638 | } |
| 17639 | case ARM::VEXTd32: |
| 17640 | case ARM::VEXTq32: { |
| 17641 | switch (OpNum) { |
| 17642 | case 0: |
| 17643 | // op: Vd |
| 17644 | return 12; |
| 17645 | case 1: |
| 17646 | // op: Vn |
| 17647 | return 7; |
| 17648 | case 2: |
| 17649 | // op: Vm |
| 17650 | return 0; |
| 17651 | case 3: |
| 17652 | // op: index |
| 17653 | return 10; |
| 17654 | } |
| 17655 | break; |
| 17656 | } |
| 17657 | case ARM::VEXTq64: { |
| 17658 | switch (OpNum) { |
| 17659 | case 0: |
| 17660 | // op: Vd |
| 17661 | return 12; |
| 17662 | case 1: |
| 17663 | // op: Vn |
| 17664 | return 7; |
| 17665 | case 2: |
| 17666 | // op: Vm |
| 17667 | return 0; |
| 17668 | case 3: |
| 17669 | // op: index |
| 17670 | return 11; |
| 17671 | } |
| 17672 | break; |
| 17673 | } |
| 17674 | case ARM::VEXTd8: |
| 17675 | case ARM::VEXTq8: { |
| 17676 | switch (OpNum) { |
| 17677 | case 0: |
| 17678 | // op: Vd |
| 17679 | return 12; |
| 17680 | case 1: |
| 17681 | // op: Vn |
| 17682 | return 7; |
| 17683 | case 2: |
| 17684 | // op: Vm |
| 17685 | return 0; |
| 17686 | case 3: |
| 17687 | // op: index |
| 17688 | return 8; |
| 17689 | } |
| 17690 | break; |
| 17691 | } |
| 17692 | case ARM::VEXTd16: |
| 17693 | case ARM::VEXTq16: { |
| 17694 | switch (OpNum) { |
| 17695 | case 0: |
| 17696 | // op: Vd |
| 17697 | return 12; |
| 17698 | case 1: |
| 17699 | // op: Vn |
| 17700 | return 7; |
| 17701 | case 2: |
| 17702 | // op: Vm |
| 17703 | return 0; |
| 17704 | case 3: |
| 17705 | // op: index |
| 17706 | return 9; |
| 17707 | } |
| 17708 | break; |
| 17709 | } |
| 17710 | case ARM::VMULLslsv4i16: |
| 17711 | case ARM::VMULLsluv4i16: |
| 17712 | case ARM::VMULslhd: |
| 17713 | case ARM::VMULslhq: |
| 17714 | case ARM::VMULslv4i16: |
| 17715 | case ARM::VMULslv8i16: |
| 17716 | case ARM::VQDMULHslv4i16: |
| 17717 | case ARM::VQDMULHslv8i16: |
| 17718 | case ARM::VQDMULLslv4i16: |
| 17719 | case ARM::VQRDMULHslv4i16: |
| 17720 | case ARM::VQRDMULHslv8i16: { |
| 17721 | switch (OpNum) { |
| 17722 | case 0: |
| 17723 | // op: Vd |
| 17724 | return 12; |
| 17725 | case 1: |
| 17726 | // op: Vn |
| 17727 | return 7; |
| 17728 | case 2: |
| 17729 | // op: Vm |
| 17730 | return 0; |
| 17731 | case 3: |
| 17732 | // op: lane |
| 17733 | return 3; |
| 17734 | } |
| 17735 | break; |
| 17736 | } |
| 17737 | case ARM::VMULLslsv2i32: |
| 17738 | case ARM::VMULLsluv2i32: |
| 17739 | case ARM::VMULslfd: |
| 17740 | case ARM::VMULslfq: |
| 17741 | case ARM::VMULslv2i32: |
| 17742 | case ARM::VMULslv4i32: |
| 17743 | case ARM::VQDMULHslv2i32: |
| 17744 | case ARM::VQDMULHslv4i32: |
| 17745 | case ARM::VQDMULLslv2i32: |
| 17746 | case ARM::VQRDMULHslv2i32: |
| 17747 | case ARM::VQRDMULHslv4i32: { |
| 17748 | switch (OpNum) { |
| 17749 | case 0: |
| 17750 | // op: Vd |
| 17751 | return 12; |
| 17752 | case 1: |
| 17753 | // op: Vn |
| 17754 | return 7; |
| 17755 | case 2: |
| 17756 | // op: Vm |
| 17757 | return 0; |
| 17758 | case 3: |
| 17759 | // op: lane |
| 17760 | return 5; |
| 17761 | } |
| 17762 | break; |
| 17763 | } |
| 17764 | case ARM::VCADDv2f32: |
| 17765 | case ARM::VCADDv4f16: |
| 17766 | case ARM::VCADDv4f32: |
| 17767 | case ARM::VCADDv8f16: { |
| 17768 | switch (OpNum) { |
| 17769 | case 0: |
| 17770 | // op: Vd |
| 17771 | return 12; |
| 17772 | case 1: |
| 17773 | // op: Vn |
| 17774 | return 7; |
| 17775 | case 2: |
| 17776 | // op: Vm |
| 17777 | return 0; |
| 17778 | case 3: |
| 17779 | // op: rot |
| 17780 | return 24; |
| 17781 | } |
| 17782 | break; |
| 17783 | } |
| 17784 | case ARM::NEON_VMAXNMNDf: |
| 17785 | case ARM::NEON_VMAXNMNDh: |
| 17786 | case ARM::NEON_VMAXNMNQf: |
| 17787 | case ARM::NEON_VMAXNMNQh: |
| 17788 | case ARM::NEON_VMINNMNDf: |
| 17789 | case ARM::NEON_VMINNMNDh: |
| 17790 | case ARM::NEON_VMINNMNQf: |
| 17791 | case ARM::NEON_VMINNMNQh: |
| 17792 | case ARM::VABDLsv2i64: |
| 17793 | case ARM::VABDLsv4i32: |
| 17794 | case ARM::VABDLsv8i16: |
| 17795 | case ARM::VABDLuv2i64: |
| 17796 | case ARM::VABDLuv4i32: |
| 17797 | case ARM::VABDLuv8i16: |
| 17798 | case ARM::VABDfd: |
| 17799 | case ARM::VABDfq: |
| 17800 | case ARM::VABDhd: |
| 17801 | case ARM::VABDhq: |
| 17802 | case ARM::VABDsv16i8: |
| 17803 | case ARM::VABDsv2i32: |
| 17804 | case ARM::VABDsv4i16: |
| 17805 | case ARM::VABDsv4i32: |
| 17806 | case ARM::VABDsv8i16: |
| 17807 | case ARM::VABDsv8i8: |
| 17808 | case ARM::VABDuv16i8: |
| 17809 | case ARM::VABDuv2i32: |
| 17810 | case ARM::VABDuv4i16: |
| 17811 | case ARM::VABDuv4i32: |
| 17812 | case ARM::VABDuv8i16: |
| 17813 | case ARM::VABDuv8i8: |
| 17814 | case ARM::VACGEfd: |
| 17815 | case ARM::VACGEfq: |
| 17816 | case ARM::VACGEhd: |
| 17817 | case ARM::VACGEhq: |
| 17818 | case ARM::VACGTfd: |
| 17819 | case ARM::VACGTfq: |
| 17820 | case ARM::VACGThd: |
| 17821 | case ARM::VACGThq: |
| 17822 | case ARM::VADDHNv2i32: |
| 17823 | case ARM::VADDHNv4i16: |
| 17824 | case ARM::VADDHNv8i8: |
| 17825 | case ARM::VADDLsv2i64: |
| 17826 | case ARM::VADDLsv4i32: |
| 17827 | case ARM::VADDLsv8i16: |
| 17828 | case ARM::VADDLuv2i64: |
| 17829 | case ARM::VADDLuv4i32: |
| 17830 | case ARM::VADDLuv8i16: |
| 17831 | case ARM::VADDWsv2i64: |
| 17832 | case ARM::VADDWsv4i32: |
| 17833 | case ARM::VADDWsv8i16: |
| 17834 | case ARM::VADDWuv2i64: |
| 17835 | case ARM::VADDWuv4i32: |
| 17836 | case ARM::VADDWuv8i16: |
| 17837 | case ARM::VADDfd: |
| 17838 | case ARM::VADDfq: |
| 17839 | case ARM::VADDhd: |
| 17840 | case ARM::VADDhq: |
| 17841 | case ARM::VADDv16i8: |
| 17842 | case ARM::VADDv1i64: |
| 17843 | case ARM::VADDv2i32: |
| 17844 | case ARM::VADDv2i64: |
| 17845 | case ARM::VADDv4i16: |
| 17846 | case ARM::VADDv4i32: |
| 17847 | case ARM::VADDv8i16: |
| 17848 | case ARM::VADDv8i8: |
| 17849 | case ARM::VANDd: |
| 17850 | case ARM::VANDq: |
| 17851 | case ARM::VBICd: |
| 17852 | case ARM::VBICq: |
| 17853 | case ARM::VCEQfd: |
| 17854 | case ARM::VCEQfq: |
| 17855 | case ARM::VCEQhd: |
| 17856 | case ARM::VCEQhq: |
| 17857 | case ARM::VCEQv16i8: |
| 17858 | case ARM::VCEQv2i32: |
| 17859 | case ARM::VCEQv4i16: |
| 17860 | case ARM::VCEQv4i32: |
| 17861 | case ARM::VCEQv8i16: |
| 17862 | case ARM::VCEQv8i8: |
| 17863 | case ARM::VCGEfd: |
| 17864 | case ARM::VCGEfq: |
| 17865 | case ARM::VCGEhd: |
| 17866 | case ARM::VCGEhq: |
| 17867 | case ARM::VCGEsv16i8: |
| 17868 | case ARM::VCGEsv2i32: |
| 17869 | case ARM::VCGEsv4i16: |
| 17870 | case ARM::VCGEsv4i32: |
| 17871 | case ARM::VCGEsv8i16: |
| 17872 | case ARM::VCGEsv8i8: |
| 17873 | case ARM::VCGEuv16i8: |
| 17874 | case ARM::VCGEuv2i32: |
| 17875 | case ARM::VCGEuv4i16: |
| 17876 | case ARM::VCGEuv4i32: |
| 17877 | case ARM::VCGEuv8i16: |
| 17878 | case ARM::VCGEuv8i8: |
| 17879 | case ARM::VCGTfd: |
| 17880 | case ARM::VCGTfq: |
| 17881 | case ARM::VCGThd: |
| 17882 | case ARM::VCGThq: |
| 17883 | case ARM::VCGTsv16i8: |
| 17884 | case ARM::VCGTsv2i32: |
| 17885 | case ARM::VCGTsv4i16: |
| 17886 | case ARM::VCGTsv4i32: |
| 17887 | case ARM::VCGTsv8i16: |
| 17888 | case ARM::VCGTsv8i8: |
| 17889 | case ARM::VCGTuv16i8: |
| 17890 | case ARM::VCGTuv2i32: |
| 17891 | case ARM::VCGTuv4i16: |
| 17892 | case ARM::VCGTuv4i32: |
| 17893 | case ARM::VCGTuv8i16: |
| 17894 | case ARM::VCGTuv8i8: |
| 17895 | case ARM::VEORd: |
| 17896 | case ARM::VEORq: |
| 17897 | case ARM::VFMALD: |
| 17898 | case ARM::VFMALQ: |
| 17899 | case ARM::VFMSLD: |
| 17900 | case ARM::VFMSLQ: |
| 17901 | case ARM::VHADDsv16i8: |
| 17902 | case ARM::VHADDsv2i32: |
| 17903 | case ARM::VHADDsv4i16: |
| 17904 | case ARM::VHADDsv4i32: |
| 17905 | case ARM::VHADDsv8i16: |
| 17906 | case ARM::VHADDsv8i8: |
| 17907 | case ARM::VHADDuv16i8: |
| 17908 | case ARM::VHADDuv2i32: |
| 17909 | case ARM::VHADDuv4i16: |
| 17910 | case ARM::VHADDuv4i32: |
| 17911 | case ARM::VHADDuv8i16: |
| 17912 | case ARM::VHADDuv8i8: |
| 17913 | case ARM::VHSUBsv16i8: |
| 17914 | case ARM::VHSUBsv2i32: |
| 17915 | case ARM::VHSUBsv4i16: |
| 17916 | case ARM::VHSUBsv4i32: |
| 17917 | case ARM::VHSUBsv8i16: |
| 17918 | case ARM::VHSUBsv8i8: |
| 17919 | case ARM::VHSUBuv16i8: |
| 17920 | case ARM::VHSUBuv2i32: |
| 17921 | case ARM::VHSUBuv4i16: |
| 17922 | case ARM::VHSUBuv4i32: |
| 17923 | case ARM::VHSUBuv8i16: |
| 17924 | case ARM::VHSUBuv8i8: |
| 17925 | case ARM::VMAXfd: |
| 17926 | case ARM::VMAXfq: |
| 17927 | case ARM::VMAXhd: |
| 17928 | case ARM::VMAXhq: |
| 17929 | case ARM::VMAXsv16i8: |
| 17930 | case ARM::VMAXsv2i32: |
| 17931 | case ARM::VMAXsv4i16: |
| 17932 | case ARM::VMAXsv4i32: |
| 17933 | case ARM::VMAXsv8i16: |
| 17934 | case ARM::VMAXsv8i8: |
| 17935 | case ARM::VMAXuv16i8: |
| 17936 | case ARM::VMAXuv2i32: |
| 17937 | case ARM::VMAXuv4i16: |
| 17938 | case ARM::VMAXuv4i32: |
| 17939 | case ARM::VMAXuv8i16: |
| 17940 | case ARM::VMAXuv8i8: |
| 17941 | case ARM::VMINfd: |
| 17942 | case ARM::VMINfq: |
| 17943 | case ARM::VMINhd: |
| 17944 | case ARM::VMINhq: |
| 17945 | case ARM::VMINsv16i8: |
| 17946 | case ARM::VMINsv2i32: |
| 17947 | case ARM::VMINsv4i16: |
| 17948 | case ARM::VMINsv4i32: |
| 17949 | case ARM::VMINsv8i16: |
| 17950 | case ARM::VMINsv8i8: |
| 17951 | case ARM::VMINuv16i8: |
| 17952 | case ARM::VMINuv2i32: |
| 17953 | case ARM::VMINuv4i16: |
| 17954 | case ARM::VMINuv4i32: |
| 17955 | case ARM::VMINuv8i16: |
| 17956 | case ARM::VMINuv8i8: |
| 17957 | case ARM::VMULLp64: |
| 17958 | case ARM::VMULLp8: |
| 17959 | case ARM::VMULLsv2i64: |
| 17960 | case ARM::VMULLsv4i32: |
| 17961 | case ARM::VMULLsv8i16: |
| 17962 | case ARM::VMULLuv2i64: |
| 17963 | case ARM::VMULLuv4i32: |
| 17964 | case ARM::VMULLuv8i16: |
| 17965 | case ARM::VMULfd: |
| 17966 | case ARM::VMULfq: |
| 17967 | case ARM::VMULhd: |
| 17968 | case ARM::VMULhq: |
| 17969 | case ARM::VMULpd: |
| 17970 | case ARM::VMULpq: |
| 17971 | case ARM::VMULv16i8: |
| 17972 | case ARM::VMULv2i32: |
| 17973 | case ARM::VMULv4i16: |
| 17974 | case ARM::VMULv4i32: |
| 17975 | case ARM::VMULv8i16: |
| 17976 | case ARM::VMULv8i8: |
| 17977 | case ARM::VORNd: |
| 17978 | case ARM::VORNq: |
| 17979 | case ARM::VORRd: |
| 17980 | case ARM::VORRq: |
| 17981 | case ARM::VPADDf: |
| 17982 | case ARM::VPADDh: |
| 17983 | case ARM::VPADDi16: |
| 17984 | case ARM::VPADDi32: |
| 17985 | case ARM::VPADDi8: |
| 17986 | case ARM::VPMAXf: |
| 17987 | case ARM::VPMAXh: |
| 17988 | case ARM::VPMAXs16: |
| 17989 | case ARM::VPMAXs32: |
| 17990 | case ARM::VPMAXs8: |
| 17991 | case ARM::VPMAXu16: |
| 17992 | case ARM::VPMAXu32: |
| 17993 | case ARM::VPMAXu8: |
| 17994 | case ARM::VPMINf: |
| 17995 | case ARM::VPMINh: |
| 17996 | case ARM::VPMINs16: |
| 17997 | case ARM::VPMINs32: |
| 17998 | case ARM::VPMINs8: |
| 17999 | case ARM::VPMINu16: |
| 18000 | case ARM::VPMINu32: |
| 18001 | case ARM::VPMINu8: |
| 18002 | case ARM::VQADDsv16i8: |
| 18003 | case ARM::VQADDsv1i64: |
| 18004 | case ARM::VQADDsv2i32: |
| 18005 | case ARM::VQADDsv2i64: |
| 18006 | case ARM::VQADDsv4i16: |
| 18007 | case ARM::VQADDsv4i32: |
| 18008 | case ARM::VQADDsv8i16: |
| 18009 | case ARM::VQADDsv8i8: |
| 18010 | case ARM::VQADDuv16i8: |
| 18011 | case ARM::VQADDuv1i64: |
| 18012 | case ARM::VQADDuv2i32: |
| 18013 | case ARM::VQADDuv2i64: |
| 18014 | case ARM::VQADDuv4i16: |
| 18015 | case ARM::VQADDuv4i32: |
| 18016 | case ARM::VQADDuv8i16: |
| 18017 | case ARM::VQADDuv8i8: |
| 18018 | case ARM::VQDMULHv2i32: |
| 18019 | case ARM::VQDMULHv4i16: |
| 18020 | case ARM::VQDMULHv4i32: |
| 18021 | case ARM::VQDMULHv8i16: |
| 18022 | case ARM::VQDMULLv2i64: |
| 18023 | case ARM::VQDMULLv4i32: |
| 18024 | case ARM::VQRDMULHv2i32: |
| 18025 | case ARM::VQRDMULHv4i16: |
| 18026 | case ARM::VQRDMULHv4i32: |
| 18027 | case ARM::VQRDMULHv8i16: |
| 18028 | case ARM::VQSUBsv16i8: |
| 18029 | case ARM::VQSUBsv1i64: |
| 18030 | case ARM::VQSUBsv2i32: |
| 18031 | case ARM::VQSUBsv2i64: |
| 18032 | case ARM::VQSUBsv4i16: |
| 18033 | case ARM::VQSUBsv4i32: |
| 18034 | case ARM::VQSUBsv8i16: |
| 18035 | case ARM::VQSUBsv8i8: |
| 18036 | case ARM::VQSUBuv16i8: |
| 18037 | case ARM::VQSUBuv1i64: |
| 18038 | case ARM::VQSUBuv2i32: |
| 18039 | case ARM::VQSUBuv2i64: |
| 18040 | case ARM::VQSUBuv4i16: |
| 18041 | case ARM::VQSUBuv4i32: |
| 18042 | case ARM::VQSUBuv8i16: |
| 18043 | case ARM::VQSUBuv8i8: |
| 18044 | case ARM::VRADDHNv2i32: |
| 18045 | case ARM::VRADDHNv4i16: |
| 18046 | case ARM::VRADDHNv8i8: |
| 18047 | case ARM::VRECPSfd: |
| 18048 | case ARM::VRECPSfq: |
| 18049 | case ARM::VRECPShd: |
| 18050 | case ARM::VRECPShq: |
| 18051 | case ARM::VRHADDsv16i8: |
| 18052 | case ARM::VRHADDsv2i32: |
| 18053 | case ARM::VRHADDsv4i16: |
| 18054 | case ARM::VRHADDsv4i32: |
| 18055 | case ARM::VRHADDsv8i16: |
| 18056 | case ARM::VRHADDsv8i8: |
| 18057 | case ARM::VRHADDuv16i8: |
| 18058 | case ARM::VRHADDuv2i32: |
| 18059 | case ARM::VRHADDuv4i16: |
| 18060 | case ARM::VRHADDuv4i32: |
| 18061 | case ARM::VRHADDuv8i16: |
| 18062 | case ARM::VRHADDuv8i8: |
| 18063 | case ARM::VRSQRTSfd: |
| 18064 | case ARM::VRSQRTSfq: |
| 18065 | case ARM::VRSQRTShd: |
| 18066 | case ARM::VRSQRTShq: |
| 18067 | case ARM::VRSUBHNv2i32: |
| 18068 | case ARM::VRSUBHNv4i16: |
| 18069 | case ARM::VRSUBHNv8i8: |
| 18070 | case ARM::VSUBHNv2i32: |
| 18071 | case ARM::VSUBHNv4i16: |
| 18072 | case ARM::VSUBHNv8i8: |
| 18073 | case ARM::VSUBLsv2i64: |
| 18074 | case ARM::VSUBLsv4i32: |
| 18075 | case ARM::VSUBLsv8i16: |
| 18076 | case ARM::VSUBLuv2i64: |
| 18077 | case ARM::VSUBLuv4i32: |
| 18078 | case ARM::VSUBLuv8i16: |
| 18079 | case ARM::VSUBWsv2i64: |
| 18080 | case ARM::VSUBWsv4i32: |
| 18081 | case ARM::VSUBWsv8i16: |
| 18082 | case ARM::VSUBWuv2i64: |
| 18083 | case ARM::VSUBWuv4i32: |
| 18084 | case ARM::VSUBWuv8i16: |
| 18085 | case ARM::VSUBfd: |
| 18086 | case ARM::VSUBfq: |
| 18087 | case ARM::VSUBhd: |
| 18088 | case ARM::VSUBhq: |
| 18089 | case ARM::VSUBv16i8: |
| 18090 | case ARM::VSUBv1i64: |
| 18091 | case ARM::VSUBv2i32: |
| 18092 | case ARM::VSUBv2i64: |
| 18093 | case ARM::VSUBv4i16: |
| 18094 | case ARM::VSUBv4i32: |
| 18095 | case ARM::VSUBv8i16: |
| 18096 | case ARM::VSUBv8i8: |
| 18097 | case ARM::VTBL1: |
| 18098 | case ARM::VTBL2: |
| 18099 | case ARM::VTBL3: |
| 18100 | case ARM::VTBL4: |
| 18101 | case ARM::VTSTv16i8: |
| 18102 | case ARM::VTSTv2i32: |
| 18103 | case ARM::VTSTv4i16: |
| 18104 | case ARM::VTSTv4i32: |
| 18105 | case ARM::VTSTv8i16: |
| 18106 | case ARM::VTSTv8i8: { |
| 18107 | switch (OpNum) { |
| 18108 | case 0: |
| 18109 | // op: Vd |
| 18110 | return 12; |
| 18111 | case 1: |
| 18112 | // op: Vn |
| 18113 | return 7; |
| 18114 | case 2: |
| 18115 | // op: Vm |
| 18116 | return 0; |
| 18117 | } |
| 18118 | break; |
| 18119 | } |
| 18120 | case ARM::VLD1LNd8_UPD: { |
| 18121 | switch (OpNum) { |
| 18122 | case 0: |
| 18123 | // op: Vd |
| 18124 | return 12; |
| 18125 | case 2: |
| 18126 | // op: Rn |
| 18127 | return 16; |
| 18128 | case 4: |
| 18129 | // op: Rm |
| 18130 | return 0; |
| 18131 | case 6: |
| 18132 | // op: lane |
| 18133 | return 5; |
| 18134 | } |
| 18135 | break; |
| 18136 | } |
| 18137 | case ARM::VLD1LNd16_UPD: { |
| 18138 | switch (OpNum) { |
| 18139 | case 0: |
| 18140 | // op: Vd |
| 18141 | return 12; |
| 18142 | case 2: |
| 18143 | // op: Rn |
| 18144 | return 4; |
| 18145 | case 4: |
| 18146 | // op: Rm |
| 18147 | return 0; |
| 18148 | case 6: |
| 18149 | // op: lane |
| 18150 | return 6; |
| 18151 | } |
| 18152 | break; |
| 18153 | } |
| 18154 | case ARM::VLD1LNd32_UPD: { |
| 18155 | switch (OpNum) { |
| 18156 | case 0: |
| 18157 | // op: Vd |
| 18158 | return 12; |
| 18159 | case 2: |
| 18160 | // op: Rn |
| 18161 | return 4; |
| 18162 | case 4: |
| 18163 | // op: Rm |
| 18164 | return 0; |
| 18165 | case 6: |
| 18166 | // op: lane |
| 18167 | return 7; |
| 18168 | } |
| 18169 | break; |
| 18170 | } |
| 18171 | case ARM::VLD1DUPd16wb_register: |
| 18172 | case ARM::VLD1DUPd32wb_register: |
| 18173 | case ARM::VLD1DUPd8wb_register: |
| 18174 | case ARM::VLD1DUPq16wb_register: |
| 18175 | case ARM::VLD1DUPq32wb_register: |
| 18176 | case ARM::VLD1DUPq8wb_register: |
| 18177 | case ARM::VLD1d16Qwb_register: |
| 18178 | case ARM::VLD1d16Twb_register: |
| 18179 | case ARM::VLD1d16wb_register: |
| 18180 | case ARM::VLD1d32Qwb_register: |
| 18181 | case ARM::VLD1d32Twb_register: |
| 18182 | case ARM::VLD1d32wb_register: |
| 18183 | case ARM::VLD1d64Qwb_register: |
| 18184 | case ARM::VLD1d64Twb_register: |
| 18185 | case ARM::VLD1d64wb_register: |
| 18186 | case ARM::VLD1d8Qwb_register: |
| 18187 | case ARM::VLD1d8Twb_register: |
| 18188 | case ARM::VLD1d8wb_register: |
| 18189 | case ARM::VLD1q16wb_register: |
| 18190 | case ARM::VLD1q32wb_register: |
| 18191 | case ARM::VLD1q64wb_register: |
| 18192 | case ARM::VLD1q8wb_register: |
| 18193 | case ARM::VLD2DUPd16wb_register: |
| 18194 | case ARM::VLD2DUPd16x2wb_register: |
| 18195 | case ARM::VLD2DUPd32wb_register: |
| 18196 | case ARM::VLD2DUPd32x2wb_register: |
| 18197 | case ARM::VLD2DUPd8wb_register: |
| 18198 | case ARM::VLD2DUPd8x2wb_register: |
| 18199 | case ARM::VLD2b16wb_register: |
| 18200 | case ARM::VLD2b32wb_register: |
| 18201 | case ARM::VLD2b8wb_register: |
| 18202 | case ARM::VLD2d16wb_register: |
| 18203 | case ARM::VLD2d32wb_register: |
| 18204 | case ARM::VLD2d8wb_register: |
| 18205 | case ARM::VLD2q16wb_register: |
| 18206 | case ARM::VLD2q32wb_register: |
| 18207 | case ARM::VLD2q8wb_register: { |
| 18208 | switch (OpNum) { |
| 18209 | case 0: |
| 18210 | // op: Vd |
| 18211 | return 12; |
| 18212 | case 2: |
| 18213 | // op: Rn |
| 18214 | return 4; |
| 18215 | case 4: |
| 18216 | // op: Rm |
| 18217 | return 0; |
| 18218 | } |
| 18219 | break; |
| 18220 | } |
| 18221 | case ARM::VLD2LNd8: { |
| 18222 | switch (OpNum) { |
| 18223 | case 0: |
| 18224 | // op: Vd |
| 18225 | return 12; |
| 18226 | case 2: |
| 18227 | // op: Rn |
| 18228 | return 4; |
| 18229 | case 6: |
| 18230 | // op: lane |
| 18231 | return 5; |
| 18232 | } |
| 18233 | break; |
| 18234 | } |
| 18235 | case ARM::VLD2LNd16: |
| 18236 | case ARM::VLD2LNq16: { |
| 18237 | switch (OpNum) { |
| 18238 | case 0: |
| 18239 | // op: Vd |
| 18240 | return 12; |
| 18241 | case 2: |
| 18242 | // op: Rn |
| 18243 | return 4; |
| 18244 | case 6: |
| 18245 | // op: lane |
| 18246 | return 6; |
| 18247 | } |
| 18248 | break; |
| 18249 | } |
| 18250 | case ARM::VLD2LNd32: |
| 18251 | case ARM::VLD2LNq32: { |
| 18252 | switch (OpNum) { |
| 18253 | case 0: |
| 18254 | // op: Vd |
| 18255 | return 12; |
| 18256 | case 2: |
| 18257 | // op: Rn |
| 18258 | return 4; |
| 18259 | case 6: |
| 18260 | // op: lane |
| 18261 | return 7; |
| 18262 | } |
| 18263 | break; |
| 18264 | } |
| 18265 | case ARM::VLD1DUPd16wb_fixed: |
| 18266 | case ARM::VLD1DUPd32wb_fixed: |
| 18267 | case ARM::VLD1DUPd8wb_fixed: |
| 18268 | case ARM::VLD1DUPq16wb_fixed: |
| 18269 | case ARM::VLD1DUPq32wb_fixed: |
| 18270 | case ARM::VLD1DUPq8wb_fixed: |
| 18271 | case ARM::VLD1d16Qwb_fixed: |
| 18272 | case ARM::VLD1d16Twb_fixed: |
| 18273 | case ARM::VLD1d16wb_fixed: |
| 18274 | case ARM::VLD1d32Qwb_fixed: |
| 18275 | case ARM::VLD1d32Twb_fixed: |
| 18276 | case ARM::VLD1d32wb_fixed: |
| 18277 | case ARM::VLD1d64Qwb_fixed: |
| 18278 | case ARM::VLD1d64Twb_fixed: |
| 18279 | case ARM::VLD1d64wb_fixed: |
| 18280 | case ARM::VLD1d8Qwb_fixed: |
| 18281 | case ARM::VLD1d8Twb_fixed: |
| 18282 | case ARM::VLD1d8wb_fixed: |
| 18283 | case ARM::VLD1q16wb_fixed: |
| 18284 | case ARM::VLD1q32wb_fixed: |
| 18285 | case ARM::VLD1q64wb_fixed: |
| 18286 | case ARM::VLD1q8wb_fixed: |
| 18287 | case ARM::VLD2DUPd16wb_fixed: |
| 18288 | case ARM::VLD2DUPd16x2wb_fixed: |
| 18289 | case ARM::VLD2DUPd32wb_fixed: |
| 18290 | case ARM::VLD2DUPd32x2wb_fixed: |
| 18291 | case ARM::VLD2DUPd8wb_fixed: |
| 18292 | case ARM::VLD2DUPd8x2wb_fixed: |
| 18293 | case ARM::VLD2b16wb_fixed: |
| 18294 | case ARM::VLD2b32wb_fixed: |
| 18295 | case ARM::VLD2b8wb_fixed: |
| 18296 | case ARM::VLD2d16wb_fixed: |
| 18297 | case ARM::VLD2d32wb_fixed: |
| 18298 | case ARM::VLD2d8wb_fixed: |
| 18299 | case ARM::VLD2q16wb_fixed: |
| 18300 | case ARM::VLD2q32wb_fixed: |
| 18301 | case ARM::VLD2q8wb_fixed: { |
| 18302 | switch (OpNum) { |
| 18303 | case 0: |
| 18304 | // op: Vd |
| 18305 | return 12; |
| 18306 | case 2: |
| 18307 | // op: Rn |
| 18308 | return 4; |
| 18309 | } |
| 18310 | break; |
| 18311 | } |
| 18312 | case ARM::VRSRAsv16i8: |
| 18313 | case ARM::VRSRAsv1i64: |
| 18314 | case ARM::VRSRAsv2i32: |
| 18315 | case ARM::VRSRAsv2i64: |
| 18316 | case ARM::VRSRAsv4i16: |
| 18317 | case ARM::VRSRAsv4i32: |
| 18318 | case ARM::VRSRAsv8i16: |
| 18319 | case ARM::VRSRAsv8i8: |
| 18320 | case ARM::VRSRAuv16i8: |
| 18321 | case ARM::VRSRAuv1i64: |
| 18322 | case ARM::VRSRAuv2i32: |
| 18323 | case ARM::VRSRAuv2i64: |
| 18324 | case ARM::VRSRAuv4i16: |
| 18325 | case ARM::VRSRAuv4i32: |
| 18326 | case ARM::VRSRAuv8i16: |
| 18327 | case ARM::VRSRAuv8i8: |
| 18328 | case ARM::VSLIv16i8: |
| 18329 | case ARM::VSLIv1i64: |
| 18330 | case ARM::VSLIv2i32: |
| 18331 | case ARM::VSLIv2i64: |
| 18332 | case ARM::VSLIv4i16: |
| 18333 | case ARM::VSLIv4i32: |
| 18334 | case ARM::VSLIv8i16: |
| 18335 | case ARM::VSLIv8i8: |
| 18336 | case ARM::VSRAsv16i8: |
| 18337 | case ARM::VSRAsv1i64: |
| 18338 | case ARM::VSRAsv2i32: |
| 18339 | case ARM::VSRAsv2i64: |
| 18340 | case ARM::VSRAsv4i16: |
| 18341 | case ARM::VSRAsv4i32: |
| 18342 | case ARM::VSRAsv8i16: |
| 18343 | case ARM::VSRAsv8i8: |
| 18344 | case ARM::VSRAuv16i8: |
| 18345 | case ARM::VSRAuv1i64: |
| 18346 | case ARM::VSRAuv2i32: |
| 18347 | case ARM::VSRAuv2i64: |
| 18348 | case ARM::VSRAuv4i16: |
| 18349 | case ARM::VSRAuv4i32: |
| 18350 | case ARM::VSRAuv8i16: |
| 18351 | case ARM::VSRAuv8i8: |
| 18352 | case ARM::VSRIv16i8: |
| 18353 | case ARM::VSRIv1i64: |
| 18354 | case ARM::VSRIv2i32: |
| 18355 | case ARM::VSRIv2i64: |
| 18356 | case ARM::VSRIv4i16: |
| 18357 | case ARM::VSRIv4i32: |
| 18358 | case ARM::VSRIv8i16: |
| 18359 | case ARM::VSRIv8i8: { |
| 18360 | switch (OpNum) { |
| 18361 | case 0: |
| 18362 | // op: Vd |
| 18363 | return 12; |
| 18364 | case 2: |
| 18365 | // op: Vm |
| 18366 | return 0; |
| 18367 | case 3: |
| 18368 | // op: SIMM |
| 18369 | return 16; |
| 18370 | } |
| 18371 | break; |
| 18372 | } |
| 18373 | case ARM::AESD: |
| 18374 | case ARM::AESE: |
| 18375 | case ARM::SHA1SU1: |
| 18376 | case ARM::SHA256SU0: |
| 18377 | case ARM::VPADALsv16i8: |
| 18378 | case ARM::VPADALsv2i32: |
| 18379 | case ARM::VPADALsv4i16: |
| 18380 | case ARM::VPADALsv4i32: |
| 18381 | case ARM::VPADALsv8i16: |
| 18382 | case ARM::VPADALsv8i8: |
| 18383 | case ARM::VPADALuv16i8: |
| 18384 | case ARM::VPADALuv2i32: |
| 18385 | case ARM::VPADALuv4i16: |
| 18386 | case ARM::VPADALuv4i32: |
| 18387 | case ARM::VPADALuv8i16: |
| 18388 | case ARM::VPADALuv8i8: { |
| 18389 | switch (OpNum) { |
| 18390 | case 0: |
| 18391 | // op: Vd |
| 18392 | return 12; |
| 18393 | case 2: |
| 18394 | // op: Vm |
| 18395 | return 0; |
| 18396 | } |
| 18397 | break; |
| 18398 | } |
| 18399 | case ARM::VQRSHLsv16i8: |
| 18400 | case ARM::VQRSHLsv1i64: |
| 18401 | case ARM::VQRSHLsv2i32: |
| 18402 | case ARM::VQRSHLsv2i64: |
| 18403 | case ARM::VQRSHLsv4i16: |
| 18404 | case ARM::VQRSHLsv4i32: |
| 18405 | case ARM::VQRSHLsv8i16: |
| 18406 | case ARM::VQRSHLsv8i8: |
| 18407 | case ARM::VQRSHLuv16i8: |
| 18408 | case ARM::VQRSHLuv1i64: |
| 18409 | case ARM::VQRSHLuv2i32: |
| 18410 | case ARM::VQRSHLuv2i64: |
| 18411 | case ARM::VQRSHLuv4i16: |
| 18412 | case ARM::VQRSHLuv4i32: |
| 18413 | case ARM::VQRSHLuv8i16: |
| 18414 | case ARM::VQRSHLuv8i8: |
| 18415 | case ARM::VQSHLsv16i8: |
| 18416 | case ARM::VQSHLsv1i64: |
| 18417 | case ARM::VQSHLsv2i32: |
| 18418 | case ARM::VQSHLsv2i64: |
| 18419 | case ARM::VQSHLsv4i16: |
| 18420 | case ARM::VQSHLsv4i32: |
| 18421 | case ARM::VQSHLsv8i16: |
| 18422 | case ARM::VQSHLsv8i8: |
| 18423 | case ARM::VQSHLuv16i8: |
| 18424 | case ARM::VQSHLuv1i64: |
| 18425 | case ARM::VQSHLuv2i32: |
| 18426 | case ARM::VQSHLuv2i64: |
| 18427 | case ARM::VQSHLuv4i16: |
| 18428 | case ARM::VQSHLuv4i32: |
| 18429 | case ARM::VQSHLuv8i16: |
| 18430 | case ARM::VQSHLuv8i8: |
| 18431 | case ARM::VRSHLsv16i8: |
| 18432 | case ARM::VRSHLsv1i64: |
| 18433 | case ARM::VRSHLsv2i32: |
| 18434 | case ARM::VRSHLsv2i64: |
| 18435 | case ARM::VRSHLsv4i16: |
| 18436 | case ARM::VRSHLsv4i32: |
| 18437 | case ARM::VRSHLsv8i16: |
| 18438 | case ARM::VRSHLsv8i8: |
| 18439 | case ARM::VRSHLuv16i8: |
| 18440 | case ARM::VRSHLuv1i64: |
| 18441 | case ARM::VRSHLuv2i32: |
| 18442 | case ARM::VRSHLuv2i64: |
| 18443 | case ARM::VRSHLuv4i16: |
| 18444 | case ARM::VRSHLuv4i32: |
| 18445 | case ARM::VRSHLuv8i16: |
| 18446 | case ARM::VRSHLuv8i8: |
| 18447 | case ARM::VSHLsv16i8: |
| 18448 | case ARM::VSHLsv1i64: |
| 18449 | case ARM::VSHLsv2i32: |
| 18450 | case ARM::VSHLsv2i64: |
| 18451 | case ARM::VSHLsv4i16: |
| 18452 | case ARM::VSHLsv4i32: |
| 18453 | case ARM::VSHLsv8i16: |
| 18454 | case ARM::VSHLsv8i8: |
| 18455 | case ARM::VSHLuv16i8: |
| 18456 | case ARM::VSHLuv1i64: |
| 18457 | case ARM::VSHLuv2i32: |
| 18458 | case ARM::VSHLuv2i64: |
| 18459 | case ARM::VSHLuv4i16: |
| 18460 | case ARM::VSHLuv4i32: |
| 18461 | case ARM::VSHLuv8i16: |
| 18462 | case ARM::VSHLuv8i8: { |
| 18463 | switch (OpNum) { |
| 18464 | case 0: |
| 18465 | // op: Vd |
| 18466 | return 12; |
| 18467 | case 2: |
| 18468 | // op: Vn |
| 18469 | return 7; |
| 18470 | case 1: |
| 18471 | // op: Vm |
| 18472 | return 0; |
| 18473 | } |
| 18474 | break; |
| 18475 | } |
| 18476 | case ARM::VMLALslsv4i16: |
| 18477 | case ARM::VMLALsluv4i16: |
| 18478 | case ARM::VMLAslhd: |
| 18479 | case ARM::VMLAslhq: |
| 18480 | case ARM::VMLAslv4i16: |
| 18481 | case ARM::VMLAslv8i16: |
| 18482 | case ARM::VMLSLslsv4i16: |
| 18483 | case ARM::VMLSLsluv4i16: |
| 18484 | case ARM::VMLSslhd: |
| 18485 | case ARM::VMLSslhq: |
| 18486 | case ARM::VMLSslv4i16: |
| 18487 | case ARM::VMLSslv8i16: |
| 18488 | case ARM::VQDMLALslv4i16: |
| 18489 | case ARM::VQDMLSLslv4i16: |
| 18490 | case ARM::VQRDMLAHslv4i16: |
| 18491 | case ARM::VQRDMLAHslv8i16: |
| 18492 | case ARM::VQRDMLSHslv4i16: |
| 18493 | case ARM::VQRDMLSHslv8i16: { |
| 18494 | switch (OpNum) { |
| 18495 | case 0: |
| 18496 | // op: Vd |
| 18497 | return 12; |
| 18498 | case 2: |
| 18499 | // op: Vn |
| 18500 | return 7; |
| 18501 | case 3: |
| 18502 | // op: Vm |
| 18503 | return 0; |
| 18504 | case 4: |
| 18505 | // op: lane |
| 18506 | return 3; |
| 18507 | } |
| 18508 | break; |
| 18509 | } |
| 18510 | case ARM::VMLALslsv2i32: |
| 18511 | case ARM::VMLALsluv2i32: |
| 18512 | case ARM::VMLAslfd: |
| 18513 | case ARM::VMLAslfq: |
| 18514 | case ARM::VMLAslv2i32: |
| 18515 | case ARM::VMLAslv4i32: |
| 18516 | case ARM::VMLSLslsv2i32: |
| 18517 | case ARM::VMLSLsluv2i32: |
| 18518 | case ARM::VMLSslfd: |
| 18519 | case ARM::VMLSslfq: |
| 18520 | case ARM::VMLSslv2i32: |
| 18521 | case ARM::VMLSslv4i32: |
| 18522 | case ARM::VQDMLALslv2i32: |
| 18523 | case ARM::VQDMLSLslv2i32: |
| 18524 | case ARM::VQRDMLAHslv2i32: |
| 18525 | case ARM::VQRDMLAHslv4i32: |
| 18526 | case ARM::VQRDMLSHslv2i32: |
| 18527 | case ARM::VQRDMLSHslv4i32: { |
| 18528 | switch (OpNum) { |
| 18529 | case 0: |
| 18530 | // op: Vd |
| 18531 | return 12; |
| 18532 | case 2: |
| 18533 | // op: Vn |
| 18534 | return 7; |
| 18535 | case 3: |
| 18536 | // op: Vm |
| 18537 | return 0; |
| 18538 | case 4: |
| 18539 | // op: lane |
| 18540 | return 5; |
| 18541 | } |
| 18542 | break; |
| 18543 | } |
| 18544 | case ARM::VCMLAv2f32: |
| 18545 | case ARM::VCMLAv4f16: |
| 18546 | case ARM::VCMLAv4f32: |
| 18547 | case ARM::VCMLAv8f16: { |
| 18548 | switch (OpNum) { |
| 18549 | case 0: |
| 18550 | // op: Vd |
| 18551 | return 12; |
| 18552 | case 2: |
| 18553 | // op: Vn |
| 18554 | return 7; |
| 18555 | case 3: |
| 18556 | // op: Vm |
| 18557 | return 0; |
| 18558 | case 4: |
| 18559 | // op: rot |
| 18560 | return 23; |
| 18561 | } |
| 18562 | break; |
| 18563 | } |
| 18564 | case ARM::VCMLAv4f16_indexed: |
| 18565 | case ARM::VCMLAv8f16_indexed: { |
| 18566 | switch (OpNum) { |
| 18567 | case 0: |
| 18568 | // op: Vd |
| 18569 | return 12; |
| 18570 | case 2: |
| 18571 | // op: Vn |
| 18572 | return 7; |
| 18573 | case 3: |
| 18574 | // op: Vm |
| 18575 | return 0; |
| 18576 | case 5: |
| 18577 | // op: rot |
| 18578 | return 20; |
| 18579 | case 4: |
| 18580 | // op: lane |
| 18581 | return 5; |
| 18582 | } |
| 18583 | break; |
| 18584 | } |
| 18585 | case ARM::VCMLAv2f32_indexed: |
| 18586 | case ARM::VCMLAv4f32_indexed: { |
| 18587 | switch (OpNum) { |
| 18588 | case 0: |
| 18589 | // op: Vd |
| 18590 | return 12; |
| 18591 | case 2: |
| 18592 | // op: Vn |
| 18593 | return 7; |
| 18594 | case 3: |
| 18595 | // op: Vm |
| 18596 | return 0; |
| 18597 | case 5: |
| 18598 | // op: rot |
| 18599 | return 20; |
| 18600 | } |
| 18601 | break; |
| 18602 | } |
| 18603 | case ARM::SHA1C: |
| 18604 | case ARM::SHA1M: |
| 18605 | case ARM::SHA1P: |
| 18606 | case ARM::SHA1SU0: |
| 18607 | case ARM::SHA256H: |
| 18608 | case ARM::SHA256H2: |
| 18609 | case ARM::SHA256SU1: |
| 18610 | case ARM::VABALsv2i64: |
| 18611 | case ARM::VABALsv4i32: |
| 18612 | case ARM::VABALsv8i16: |
| 18613 | case ARM::VABALuv2i64: |
| 18614 | case ARM::VABALuv4i32: |
| 18615 | case ARM::VABALuv8i16: |
| 18616 | case ARM::VABAsv16i8: |
| 18617 | case ARM::VABAsv2i32: |
| 18618 | case ARM::VABAsv4i16: |
| 18619 | case ARM::VABAsv4i32: |
| 18620 | case ARM::VABAsv8i16: |
| 18621 | case ARM::VABAsv8i8: |
| 18622 | case ARM::VABAuv16i8: |
| 18623 | case ARM::VABAuv2i32: |
| 18624 | case ARM::VABAuv4i16: |
| 18625 | case ARM::VABAuv4i32: |
| 18626 | case ARM::VABAuv8i16: |
| 18627 | case ARM::VABAuv8i8: |
| 18628 | case ARM::VBIFd: |
| 18629 | case ARM::VBIFq: |
| 18630 | case ARM::VBITd: |
| 18631 | case ARM::VBITq: |
| 18632 | case ARM::VBSLd: |
| 18633 | case ARM::VBSLq: |
| 18634 | case ARM::VFMAfd: |
| 18635 | case ARM::VFMAfq: |
| 18636 | case ARM::VFMAhd: |
| 18637 | case ARM::VFMAhq: |
| 18638 | case ARM::VFMSfd: |
| 18639 | case ARM::VFMSfq: |
| 18640 | case ARM::VFMShd: |
| 18641 | case ARM::VFMShq: |
| 18642 | case ARM::VMLALsv2i64: |
| 18643 | case ARM::VMLALsv4i32: |
| 18644 | case ARM::VMLALsv8i16: |
| 18645 | case ARM::VMLALuv2i64: |
| 18646 | case ARM::VMLALuv4i32: |
| 18647 | case ARM::VMLALuv8i16: |
| 18648 | case ARM::VMLAfd: |
| 18649 | case ARM::VMLAfq: |
| 18650 | case ARM::VMLAhd: |
| 18651 | case ARM::VMLAhq: |
| 18652 | case ARM::VMLAv16i8: |
| 18653 | case ARM::VMLAv2i32: |
| 18654 | case ARM::VMLAv4i16: |
| 18655 | case ARM::VMLAv4i32: |
| 18656 | case ARM::VMLAv8i16: |
| 18657 | case ARM::VMLAv8i8: |
| 18658 | case ARM::VMLSLsv2i64: |
| 18659 | case ARM::VMLSLsv4i32: |
| 18660 | case ARM::VMLSLsv8i16: |
| 18661 | case ARM::VMLSLuv2i64: |
| 18662 | case ARM::VMLSLuv4i32: |
| 18663 | case ARM::VMLSLuv8i16: |
| 18664 | case ARM::VMLSfd: |
| 18665 | case ARM::VMLSfq: |
| 18666 | case ARM::VMLShd: |
| 18667 | case ARM::VMLShq: |
| 18668 | case ARM::VMLSv16i8: |
| 18669 | case ARM::VMLSv2i32: |
| 18670 | case ARM::VMLSv4i16: |
| 18671 | case ARM::VMLSv4i32: |
| 18672 | case ARM::VMLSv8i16: |
| 18673 | case ARM::VMLSv8i8: |
| 18674 | case ARM::VQDMLALv2i64: |
| 18675 | case ARM::VQDMLALv4i32: |
| 18676 | case ARM::VQDMLSLv2i64: |
| 18677 | case ARM::VQDMLSLv4i32: |
| 18678 | case ARM::VQRDMLAHv2i32: |
| 18679 | case ARM::VQRDMLAHv4i16: |
| 18680 | case ARM::VQRDMLAHv4i32: |
| 18681 | case ARM::VQRDMLAHv8i16: |
| 18682 | case ARM::VQRDMLSHv2i32: |
| 18683 | case ARM::VQRDMLSHv4i16: |
| 18684 | case ARM::VQRDMLSHv4i32: |
| 18685 | case ARM::VQRDMLSHv8i16: |
| 18686 | case ARM::VTBX1: |
| 18687 | case ARM::VTBX2: |
| 18688 | case ARM::VTBX3: |
| 18689 | case ARM::VTBX4: { |
| 18690 | switch (OpNum) { |
| 18691 | case 0: |
| 18692 | // op: Vd |
| 18693 | return 12; |
| 18694 | case 2: |
| 18695 | // op: Vn |
| 18696 | return 7; |
| 18697 | case 3: |
| 18698 | // op: Vm |
| 18699 | return 0; |
| 18700 | } |
| 18701 | break; |
| 18702 | } |
| 18703 | case ARM::VLD3LNd8: { |
| 18704 | switch (OpNum) { |
| 18705 | case 0: |
| 18706 | // op: Vd |
| 18707 | return 12; |
| 18708 | case 3: |
| 18709 | // op: Rn |
| 18710 | return 16; |
| 18711 | case 8: |
| 18712 | // op: lane |
| 18713 | return 5; |
| 18714 | } |
| 18715 | break; |
| 18716 | } |
| 18717 | case ARM::VLD3LNd16: |
| 18718 | case ARM::VLD3LNq16: { |
| 18719 | switch (OpNum) { |
| 18720 | case 0: |
| 18721 | // op: Vd |
| 18722 | return 12; |
| 18723 | case 3: |
| 18724 | // op: Rn |
| 18725 | return 16; |
| 18726 | case 8: |
| 18727 | // op: lane |
| 18728 | return 6; |
| 18729 | } |
| 18730 | break; |
| 18731 | } |
| 18732 | case ARM::VLD3LNd32: |
| 18733 | case ARM::VLD3LNq32: { |
| 18734 | switch (OpNum) { |
| 18735 | case 0: |
| 18736 | // op: Vd |
| 18737 | return 12; |
| 18738 | case 3: |
| 18739 | // op: Rn |
| 18740 | return 16; |
| 18741 | case 8: |
| 18742 | // op: lane |
| 18743 | return 7; |
| 18744 | } |
| 18745 | break; |
| 18746 | } |
| 18747 | case ARM::VLD3DUPd16: |
| 18748 | case ARM::VLD3DUPd32: |
| 18749 | case ARM::VLD3DUPd8: |
| 18750 | case ARM::VLD3DUPq16: |
| 18751 | case ARM::VLD3DUPq32: |
| 18752 | case ARM::VLD3DUPq8: { |
| 18753 | switch (OpNum) { |
| 18754 | case 0: |
| 18755 | // op: Vd |
| 18756 | return 12; |
| 18757 | case 3: |
| 18758 | // op: Rn |
| 18759 | return 16; |
| 18760 | } |
| 18761 | break; |
| 18762 | } |
| 18763 | case ARM::VLD2LNd8_UPD: { |
| 18764 | switch (OpNum) { |
| 18765 | case 0: |
| 18766 | // op: Vd |
| 18767 | return 12; |
| 18768 | case 3: |
| 18769 | // op: Rn |
| 18770 | return 4; |
| 18771 | case 5: |
| 18772 | // op: Rm |
| 18773 | return 0; |
| 18774 | case 8: |
| 18775 | // op: lane |
| 18776 | return 5; |
| 18777 | } |
| 18778 | break; |
| 18779 | } |
| 18780 | case ARM::VLD2LNd16_UPD: |
| 18781 | case ARM::VLD2LNq16_UPD: { |
| 18782 | switch (OpNum) { |
| 18783 | case 0: |
| 18784 | // op: Vd |
| 18785 | return 12; |
| 18786 | case 3: |
| 18787 | // op: Rn |
| 18788 | return 4; |
| 18789 | case 5: |
| 18790 | // op: Rm |
| 18791 | return 0; |
| 18792 | case 8: |
| 18793 | // op: lane |
| 18794 | return 6; |
| 18795 | } |
| 18796 | break; |
| 18797 | } |
| 18798 | case ARM::VLD2LNd32_UPD: |
| 18799 | case ARM::VLD2LNq32_UPD: { |
| 18800 | switch (OpNum) { |
| 18801 | case 0: |
| 18802 | // op: Vd |
| 18803 | return 12; |
| 18804 | case 3: |
| 18805 | // op: Rn |
| 18806 | return 4; |
| 18807 | case 5: |
| 18808 | // op: Rm |
| 18809 | return 0; |
| 18810 | case 8: |
| 18811 | // op: lane |
| 18812 | return 7; |
| 18813 | } |
| 18814 | break; |
| 18815 | } |
| 18816 | case ARM::VLD3d16: |
| 18817 | case ARM::VLD3d32: |
| 18818 | case ARM::VLD3d8: |
| 18819 | case ARM::VLD3q16: |
| 18820 | case ARM::VLD3q32: |
| 18821 | case ARM::VLD3q8: { |
| 18822 | switch (OpNum) { |
| 18823 | case 0: |
| 18824 | // op: Vd |
| 18825 | return 12; |
| 18826 | case 3: |
| 18827 | // op: Rn |
| 18828 | return 4; |
| 18829 | } |
| 18830 | break; |
| 18831 | } |
| 18832 | case ARM::VLD3LNd8_UPD: { |
| 18833 | switch (OpNum) { |
| 18834 | case 0: |
| 18835 | // op: Vd |
| 18836 | return 12; |
| 18837 | case 4: |
| 18838 | // op: Rn |
| 18839 | return 16; |
| 18840 | case 6: |
| 18841 | // op: Rm |
| 18842 | return 0; |
| 18843 | case 10: |
| 18844 | // op: lane |
| 18845 | return 5; |
| 18846 | } |
| 18847 | break; |
| 18848 | } |
| 18849 | case ARM::VLD3LNd16_UPD: |
| 18850 | case ARM::VLD3LNq16_UPD: { |
| 18851 | switch (OpNum) { |
| 18852 | case 0: |
| 18853 | // op: Vd |
| 18854 | return 12; |
| 18855 | case 4: |
| 18856 | // op: Rn |
| 18857 | return 16; |
| 18858 | case 6: |
| 18859 | // op: Rm |
| 18860 | return 0; |
| 18861 | case 10: |
| 18862 | // op: lane |
| 18863 | return 6; |
| 18864 | } |
| 18865 | break; |
| 18866 | } |
| 18867 | case ARM::VLD3LNd32_UPD: |
| 18868 | case ARM::VLD3LNq32_UPD: { |
| 18869 | switch (OpNum) { |
| 18870 | case 0: |
| 18871 | // op: Vd |
| 18872 | return 12; |
| 18873 | case 4: |
| 18874 | // op: Rn |
| 18875 | return 16; |
| 18876 | case 6: |
| 18877 | // op: Rm |
| 18878 | return 0; |
| 18879 | case 10: |
| 18880 | // op: lane |
| 18881 | return 7; |
| 18882 | } |
| 18883 | break; |
| 18884 | } |
| 18885 | case ARM::VLD3DUPd16_UPD: |
| 18886 | case ARM::VLD3DUPd32_UPD: |
| 18887 | case ARM::VLD3DUPd8_UPD: |
| 18888 | case ARM::VLD3DUPq16_UPD: |
| 18889 | case ARM::VLD3DUPq32_UPD: |
| 18890 | case ARM::VLD3DUPq8_UPD: { |
| 18891 | switch (OpNum) { |
| 18892 | case 0: |
| 18893 | // op: Vd |
| 18894 | return 12; |
| 18895 | case 4: |
| 18896 | // op: Rn |
| 18897 | return 16; |
| 18898 | case 6: |
| 18899 | // op: Rm |
| 18900 | return 0; |
| 18901 | } |
| 18902 | break; |
| 18903 | } |
| 18904 | case ARM::VLD4LNd8: { |
| 18905 | switch (OpNum) { |
| 18906 | case 0: |
| 18907 | // op: Vd |
| 18908 | return 12; |
| 18909 | case 4: |
| 18910 | // op: Rn |
| 18911 | return 4; |
| 18912 | case 10: |
| 18913 | // op: lane |
| 18914 | return 5; |
| 18915 | } |
| 18916 | break; |
| 18917 | } |
| 18918 | case ARM::VLD4LNd16: |
| 18919 | case ARM::VLD4LNq16: { |
| 18920 | switch (OpNum) { |
| 18921 | case 0: |
| 18922 | // op: Vd |
| 18923 | return 12; |
| 18924 | case 4: |
| 18925 | // op: Rn |
| 18926 | return 4; |
| 18927 | case 10: |
| 18928 | // op: lane |
| 18929 | return 6; |
| 18930 | } |
| 18931 | break; |
| 18932 | } |
| 18933 | case ARM::VLD4LNd32: |
| 18934 | case ARM::VLD4LNq32: { |
| 18935 | switch (OpNum) { |
| 18936 | case 0: |
| 18937 | // op: Vd |
| 18938 | return 12; |
| 18939 | case 4: |
| 18940 | // op: Rn |
| 18941 | return 4; |
| 18942 | case 10: |
| 18943 | // op: lane |
| 18944 | return 7; |
| 18945 | } |
| 18946 | break; |
| 18947 | } |
| 18948 | case ARM::VLD3d16_UPD: |
| 18949 | case ARM::VLD3d32_UPD: |
| 18950 | case ARM::VLD3d8_UPD: |
| 18951 | case ARM::VLD3q16_UPD: |
| 18952 | case ARM::VLD3q32_UPD: |
| 18953 | case ARM::VLD3q8_UPD: { |
| 18954 | switch (OpNum) { |
| 18955 | case 0: |
| 18956 | // op: Vd |
| 18957 | return 12; |
| 18958 | case 4: |
| 18959 | // op: Rn |
| 18960 | return 4; |
| 18961 | case 6: |
| 18962 | // op: Rm |
| 18963 | return 0; |
| 18964 | } |
| 18965 | break; |
| 18966 | } |
| 18967 | case ARM::VLD4DUPd16: |
| 18968 | case ARM::VLD4DUPd32: |
| 18969 | case ARM::VLD4DUPd8: |
| 18970 | case ARM::VLD4DUPq16: |
| 18971 | case ARM::VLD4DUPq32: |
| 18972 | case ARM::VLD4DUPq8: |
| 18973 | case ARM::VLD4d16: |
| 18974 | case ARM::VLD4d32: |
| 18975 | case ARM::VLD4d8: |
| 18976 | case ARM::VLD4q16: |
| 18977 | case ARM::VLD4q32: |
| 18978 | case ARM::VLD4q8: { |
| 18979 | switch (OpNum) { |
| 18980 | case 0: |
| 18981 | // op: Vd |
| 18982 | return 12; |
| 18983 | case 4: |
| 18984 | // op: Rn |
| 18985 | return 4; |
| 18986 | } |
| 18987 | break; |
| 18988 | } |
| 18989 | case ARM::VLD4LNd8_UPD: { |
| 18990 | switch (OpNum) { |
| 18991 | case 0: |
| 18992 | // op: Vd |
| 18993 | return 12; |
| 18994 | case 5: |
| 18995 | // op: Rn |
| 18996 | return 4; |
| 18997 | case 7: |
| 18998 | // op: Rm |
| 18999 | return 0; |
| 19000 | case 12: |
| 19001 | // op: lane |
| 19002 | return 5; |
| 19003 | } |
| 19004 | break; |
| 19005 | } |
| 19006 | case ARM::VLD4LNd16_UPD: |
| 19007 | case ARM::VLD4LNq16_UPD: { |
| 19008 | switch (OpNum) { |
| 19009 | case 0: |
| 19010 | // op: Vd |
| 19011 | return 12; |
| 19012 | case 5: |
| 19013 | // op: Rn |
| 19014 | return 4; |
| 19015 | case 7: |
| 19016 | // op: Rm |
| 19017 | return 0; |
| 19018 | case 12: |
| 19019 | // op: lane |
| 19020 | return 6; |
| 19021 | } |
| 19022 | break; |
| 19023 | } |
| 19024 | case ARM::VLD4LNd32_UPD: |
| 19025 | case ARM::VLD4LNq32_UPD: { |
| 19026 | switch (OpNum) { |
| 19027 | case 0: |
| 19028 | // op: Vd |
| 19029 | return 12; |
| 19030 | case 5: |
| 19031 | // op: Rn |
| 19032 | return 4; |
| 19033 | case 7: |
| 19034 | // op: Rm |
| 19035 | return 0; |
| 19036 | case 12: |
| 19037 | // op: lane |
| 19038 | return 7; |
| 19039 | } |
| 19040 | break; |
| 19041 | } |
| 19042 | case ARM::VLD4DUPd16_UPD: |
| 19043 | case ARM::VLD4DUPd32_UPD: |
| 19044 | case ARM::VLD4DUPd8_UPD: |
| 19045 | case ARM::VLD4DUPq16_UPD: |
| 19046 | case ARM::VLD4DUPq32_UPD: |
| 19047 | case ARM::VLD4DUPq8_UPD: |
| 19048 | case ARM::VLD4d16_UPD: |
| 19049 | case ARM::VLD4d32_UPD: |
| 19050 | case ARM::VLD4d8_UPD: |
| 19051 | case ARM::VLD4q16_UPD: |
| 19052 | case ARM::VLD4q32_UPD: |
| 19053 | case ARM::VLD4q8_UPD: { |
| 19054 | switch (OpNum) { |
| 19055 | case 0: |
| 19056 | // op: Vd |
| 19057 | return 12; |
| 19058 | case 5: |
| 19059 | // op: Rn |
| 19060 | return 4; |
| 19061 | case 7: |
| 19062 | // op: Rm |
| 19063 | return 0; |
| 19064 | } |
| 19065 | break; |
| 19066 | } |
| 19067 | case ARM::PLDWi12: |
| 19068 | case ARM::PLDi12: |
| 19069 | case ARM::PLIi12: |
| 19070 | case ARM::t2PLDWi12: |
| 19071 | case ARM::t2PLDWi8: |
| 19072 | case ARM::t2PLDWs: |
| 19073 | case ARM::t2PLDi12: |
| 19074 | case ARM::t2PLDi8: |
| 19075 | case ARM::t2PLDpci: |
| 19076 | case ARM::t2PLDs: |
| 19077 | case ARM::t2PLIi12: |
| 19078 | case ARM::t2PLIi8: |
| 19079 | case ARM::t2PLIpci: |
| 19080 | case ARM::t2PLIs: { |
| 19081 | switch (OpNum) { |
| 19082 | case 0: |
| 19083 | // op: addr |
| 19084 | return 0; |
| 19085 | } |
| 19086 | break; |
| 19087 | } |
| 19088 | case ARM::t2BFLr: |
| 19089 | case ARM::t2BFr: { |
| 19090 | switch (OpNum) { |
| 19091 | case 0: |
| 19092 | // op: b_label |
| 19093 | return 23; |
| 19094 | case 1: |
| 19095 | // op: Rn |
| 19096 | return 16; |
| 19097 | } |
| 19098 | break; |
| 19099 | } |
| 19100 | case ARM::t2BFLi: |
| 19101 | case ARM::t2BFi: { |
| 19102 | switch (OpNum) { |
| 19103 | case 0: |
| 19104 | // op: b_label |
| 19105 | return 23; |
| 19106 | case 1: |
| 19107 | // op: label |
| 19108 | return 1; |
| 19109 | } |
| 19110 | break; |
| 19111 | } |
| 19112 | case ARM::t2MSRbanked: { |
| 19113 | switch (OpNum) { |
| 19114 | case 0: |
| 19115 | // op: banked |
| 19116 | return 4; |
| 19117 | case 1: |
| 19118 | // op: Rn |
| 19119 | return 16; |
| 19120 | } |
| 19121 | break; |
| 19122 | } |
| 19123 | case ARM::t2IT: { |
| 19124 | switch (OpNum) { |
| 19125 | case 0: |
| 19126 | // op: cc |
| 19127 | return 4; |
| 19128 | case 1: |
| 19129 | // op: mask |
| 19130 | return 0; |
| 19131 | } |
| 19132 | break; |
| 19133 | } |
| 19134 | case ARM::BX: |
| 19135 | case ARM::tPICADD: { |
| 19136 | switch (OpNum) { |
| 19137 | case 0: |
| 19138 | // op: dst |
| 19139 | return 0; |
| 19140 | } |
| 19141 | break; |
| 19142 | } |
| 19143 | case ARM::tADDrSPi: { |
| 19144 | switch (OpNum) { |
| 19145 | case 0: |
| 19146 | // op: dst |
| 19147 | return 8; |
| 19148 | case 2: |
| 19149 | // op: imm |
| 19150 | return 0; |
| 19151 | } |
| 19152 | break; |
| 19153 | } |
| 19154 | case ARM::tSETEND: { |
| 19155 | switch (OpNum) { |
| 19156 | case 0: |
| 19157 | // op: end |
| 19158 | return 3; |
| 19159 | } |
| 19160 | break; |
| 19161 | } |
| 19162 | case ARM::SETEND: { |
| 19163 | switch (OpNum) { |
| 19164 | case 0: |
| 19165 | // op: end |
| 19166 | return 9; |
| 19167 | } |
| 19168 | break; |
| 19169 | } |
| 19170 | case ARM::BL: |
| 19171 | case ARM::BLX: { |
| 19172 | switch (OpNum) { |
| 19173 | case 0: |
| 19174 | // op: func |
| 19175 | return 0; |
| 19176 | } |
| 19177 | break; |
| 19178 | } |
| 19179 | case ARM::t2BXJ: { |
| 19180 | switch (OpNum) { |
| 19181 | case 0: |
| 19182 | // op: func |
| 19183 | return 16; |
| 19184 | } |
| 19185 | break; |
| 19186 | } |
| 19187 | case ARM::HVC: |
| 19188 | case ARM::t2HINT: |
| 19189 | case ARM::t2SUBS_PC_LR: |
| 19190 | case ARM::tSVC: { |
| 19191 | switch (OpNum) { |
| 19192 | case 0: |
| 19193 | // op: imm |
| 19194 | return 0; |
| 19195 | } |
| 19196 | break; |
| 19197 | } |
| 19198 | case ARM::t2SETPAN: { |
| 19199 | switch (OpNum) { |
| 19200 | case 0: |
| 19201 | // op: imm |
| 19202 | return 3; |
| 19203 | } |
| 19204 | break; |
| 19205 | } |
| 19206 | case ARM::tHINT: { |
| 19207 | switch (OpNum) { |
| 19208 | case 0: |
| 19209 | // op: imm |
| 19210 | return 4; |
| 19211 | } |
| 19212 | break; |
| 19213 | } |
| 19214 | case ARM::SETPAN: { |
| 19215 | switch (OpNum) { |
| 19216 | case 0: |
| 19217 | // op: imm |
| 19218 | return 9; |
| 19219 | } |
| 19220 | break; |
| 19221 | } |
| 19222 | case ARM::UDF: |
| 19223 | case ARM::t2HVC: |
| 19224 | case ARM::t2UDF: { |
| 19225 | switch (OpNum) { |
| 19226 | case 0: |
| 19227 | // op: imm16 |
| 19228 | return 0; |
| 19229 | } |
| 19230 | break; |
| 19231 | } |
| 19232 | case ARM::tUDF: { |
| 19233 | switch (OpNum) { |
| 19234 | case 0: |
| 19235 | // op: imm8 |
| 19236 | return 0; |
| 19237 | } |
| 19238 | break; |
| 19239 | } |
| 19240 | case ARM::CPS3p: { |
| 19241 | switch (OpNum) { |
| 19242 | case 0: |
| 19243 | // op: imod |
| 19244 | return 18; |
| 19245 | case 1: |
| 19246 | // op: iflags |
| 19247 | return 6; |
| 19248 | case 2: |
| 19249 | // op: mode |
| 19250 | return 0; |
| 19251 | } |
| 19252 | break; |
| 19253 | } |
| 19254 | case ARM::CPS2p: { |
| 19255 | switch (OpNum) { |
| 19256 | case 0: |
| 19257 | // op: imod |
| 19258 | return 18; |
| 19259 | case 1: |
| 19260 | // op: iflags |
| 19261 | return 6; |
| 19262 | } |
| 19263 | break; |
| 19264 | } |
| 19265 | case ARM::tCPS: { |
| 19266 | switch (OpNum) { |
| 19267 | case 0: |
| 19268 | // op: imod |
| 19269 | return 4; |
| 19270 | case 1: |
| 19271 | // op: iflags |
| 19272 | return 0; |
| 19273 | } |
| 19274 | break; |
| 19275 | } |
| 19276 | case ARM::t2CPS3p: { |
| 19277 | switch (OpNum) { |
| 19278 | case 0: |
| 19279 | // op: imod |
| 19280 | return 9; |
| 19281 | case 1: |
| 19282 | // op: iflags |
| 19283 | return 5; |
| 19284 | case 2: |
| 19285 | // op: mode |
| 19286 | return 0; |
| 19287 | } |
| 19288 | break; |
| 19289 | } |
| 19290 | case ARM::t2CPS2p: { |
| 19291 | switch (OpNum) { |
| 19292 | case 0: |
| 19293 | // op: imod |
| 19294 | return 9; |
| 19295 | case 1: |
| 19296 | // op: iflags |
| 19297 | return 5; |
| 19298 | } |
| 19299 | break; |
| 19300 | } |
| 19301 | case ARM::t2LE: { |
| 19302 | switch (OpNum) { |
| 19303 | case 0: |
| 19304 | // op: label |
| 19305 | return 1; |
| 19306 | } |
| 19307 | break; |
| 19308 | } |
| 19309 | case ARM::t2MSR_AR: { |
| 19310 | switch (OpNum) { |
| 19311 | case 0: |
| 19312 | // op: mask |
| 19313 | return 8; |
| 19314 | case 1: |
| 19315 | // op: Rn |
| 19316 | return 16; |
| 19317 | } |
| 19318 | break; |
| 19319 | } |
| 19320 | case ARM::CPS1p: |
| 19321 | case ARM::SRSDA: |
| 19322 | case ARM::SRSDA_UPD: |
| 19323 | case ARM::SRSDB: |
| 19324 | case ARM::SRSDB_UPD: |
| 19325 | case ARM::SRSIA: |
| 19326 | case ARM::SRSIA_UPD: |
| 19327 | case ARM::SRSIB: |
| 19328 | case ARM::SRSIB_UPD: |
| 19329 | case ARM::t2CPS1p: |
| 19330 | case ARM::t2SRSDB: |
| 19331 | case ARM::t2SRSDB_UPD: |
| 19332 | case ARM::t2SRSIA: |
| 19333 | case ARM::t2SRSIA_UPD: { |
| 19334 | switch (OpNum) { |
| 19335 | case 0: |
| 19336 | // op: mode |
| 19337 | return 0; |
| 19338 | } |
| 19339 | break; |
| 19340 | } |
| 19341 | case ARM::DMB: |
| 19342 | case ARM::DSB: |
| 19343 | case ARM::ISB: |
| 19344 | case ARM::t2DBG: |
| 19345 | case ARM::t2DMB: |
| 19346 | case ARM::t2DSB: |
| 19347 | case ARM::t2ISB: { |
| 19348 | switch (OpNum) { |
| 19349 | case 0: |
| 19350 | // op: opt |
| 19351 | return 0; |
| 19352 | } |
| 19353 | break; |
| 19354 | } |
| 19355 | case ARM::t2SMC: { |
| 19356 | switch (OpNum) { |
| 19357 | case 0: |
| 19358 | // op: opt |
| 19359 | return 16; |
| 19360 | } |
| 19361 | break; |
| 19362 | } |
| 19363 | case ARM::BX_RET: |
| 19364 | case ARM::ERET: |
| 19365 | case ARM::FMSTAT: |
| 19366 | case ARM::MOVPCLR: { |
| 19367 | switch (OpNum) { |
| 19368 | case 0: |
| 19369 | // op: p |
| 19370 | return 28; |
| 19371 | } |
| 19372 | break; |
| 19373 | } |
| 19374 | case ARM::PLDWrs: |
| 19375 | case ARM::PLDrs: |
| 19376 | case ARM::PLIrs: { |
| 19377 | switch (OpNum) { |
| 19378 | case 0: |
| 19379 | // op: shift |
| 19380 | return 0; |
| 19381 | } |
| 19382 | break; |
| 19383 | } |
| 19384 | case ARM::BLXi: |
| 19385 | case ARM::t2B: |
| 19386 | case ARM::tB: { |
| 19387 | switch (OpNum) { |
| 19388 | case 0: |
| 19389 | // op: target |
| 19390 | return 0; |
| 19391 | } |
| 19392 | break; |
| 19393 | } |
| 19394 | case ARM::BKPT: |
| 19395 | case ARM::HLT: |
| 19396 | case ARM::tBKPT: |
| 19397 | case ARM::tHLT: { |
| 19398 | switch (OpNum) { |
| 19399 | case 0: |
| 19400 | // op: val |
| 19401 | return 0; |
| 19402 | } |
| 19403 | break; |
| 19404 | } |
| 19405 | case ARM::MVE_VLDRBS16_pre: |
| 19406 | case ARM::MVE_VLDRBS32_pre: |
| 19407 | case ARM::MVE_VLDRBU16_pre: |
| 19408 | case ARM::MVE_VLDRBU32_pre: |
| 19409 | case ARM::MVE_VLDRBU8_pre: |
| 19410 | case ARM::MVE_VLDRDU64_qi_pre: |
| 19411 | case ARM::MVE_VLDRHS32_pre: |
| 19412 | case ARM::MVE_VLDRHU16_pre: |
| 19413 | case ARM::MVE_VLDRHU32_pre: |
| 19414 | case ARM::MVE_VLDRWU32_pre: |
| 19415 | case ARM::MVE_VLDRWU32_qi_pre: |
| 19416 | case ARM::MVE_VSTRB16_pre: |
| 19417 | case ARM::MVE_VSTRB32_pre: |
| 19418 | case ARM::MVE_VSTRBU8_pre: |
| 19419 | case ARM::MVE_VSTRD64_qi_pre: |
| 19420 | case ARM::MVE_VSTRH32_pre: |
| 19421 | case ARM::MVE_VSTRHU16_pre: |
| 19422 | case ARM::MVE_VSTRW32_qi_pre: |
| 19423 | case ARM::MVE_VSTRWU32_pre: { |
| 19424 | switch (OpNum) { |
| 19425 | case 1: |
| 19426 | // op: Qd |
| 19427 | return 13; |
| 19428 | case 2: |
| 19429 | // op: addr |
| 19430 | return 0; |
| 19431 | } |
| 19432 | break; |
| 19433 | } |
| 19434 | case ARM::MVE_VLDRBS16_post: |
| 19435 | case ARM::MVE_VLDRBS32_post: |
| 19436 | case ARM::MVE_VLDRBU16_post: |
| 19437 | case ARM::MVE_VLDRBU32_post: |
| 19438 | case ARM::MVE_VLDRBU8_post: |
| 19439 | case ARM::MVE_VLDRHS32_post: |
| 19440 | case ARM::MVE_VLDRHU16_post: |
| 19441 | case ARM::MVE_VLDRHU32_post: |
| 19442 | case ARM::MVE_VLDRWU32_post: |
| 19443 | case ARM::MVE_VSTRB16_post: |
| 19444 | case ARM::MVE_VSTRB32_post: |
| 19445 | case ARM::MVE_VSTRBU8_post: |
| 19446 | case ARM::MVE_VSTRH32_post: |
| 19447 | case ARM::MVE_VSTRHU16_post: |
| 19448 | case ARM::MVE_VSTRWU32_post: { |
| 19449 | switch (OpNum) { |
| 19450 | case 1: |
| 19451 | // op: Qd |
| 19452 | return 13; |
| 19453 | case 3: |
| 19454 | // op: addr |
| 19455 | return 0; |
| 19456 | case 2: |
| 19457 | // op: Rn |
| 19458 | return 16; |
| 19459 | } |
| 19460 | break; |
| 19461 | } |
| 19462 | case ARM::MVE_VMOV_from_lane_32: { |
| 19463 | switch (OpNum) { |
| 19464 | case 1: |
| 19465 | // op: Qd |
| 19466 | return 7; |
| 19467 | case 0: |
| 19468 | // op: Rt |
| 19469 | return 12; |
| 19470 | case 2: |
| 19471 | // op: Idx |
| 19472 | return 16; |
| 19473 | } |
| 19474 | break; |
| 19475 | } |
| 19476 | case ARM::MVE_VMOV_from_lane_s8: |
| 19477 | case ARM::MVE_VMOV_from_lane_u8: { |
| 19478 | switch (OpNum) { |
| 19479 | case 1: |
| 19480 | // op: Qd |
| 19481 | return 7; |
| 19482 | case 0: |
| 19483 | // op: Rt |
| 19484 | return 12; |
| 19485 | case 2: |
| 19486 | // op: Idx |
| 19487 | return 5; |
| 19488 | } |
| 19489 | break; |
| 19490 | } |
| 19491 | case ARM::MVE_VMOV_from_lane_s16: |
| 19492 | case ARM::MVE_VMOV_from_lane_u16: { |
| 19493 | switch (OpNum) { |
| 19494 | case 1: |
| 19495 | // op: Qd |
| 19496 | return 7; |
| 19497 | case 0: |
| 19498 | // op: Rt |
| 19499 | return 12; |
| 19500 | case 2: |
| 19501 | // op: Idx |
| 19502 | return 6; |
| 19503 | } |
| 19504 | break; |
| 19505 | } |
| 19506 | case ARM::MVE_VCVTf16s16_fix: |
| 19507 | case ARM::MVE_VCVTf16u16_fix: |
| 19508 | case ARM::MVE_VCVTf32s32_fix: |
| 19509 | case ARM::MVE_VCVTf32u32_fix: |
| 19510 | case ARM::MVE_VCVTs16f16_fix: |
| 19511 | case ARM::MVE_VCVTs32f32_fix: |
| 19512 | case ARM::MVE_VCVTu16f16_fix: |
| 19513 | case ARM::MVE_VCVTu32f32_fix: { |
| 19514 | switch (OpNum) { |
| 19515 | case 1: |
| 19516 | // op: Qm |
| 19517 | return 1; |
| 19518 | case 0: |
| 19519 | // op: Qd |
| 19520 | return 13; |
| 19521 | case 2: |
| 19522 | // op: imm6 |
| 19523 | return 16; |
| 19524 | } |
| 19525 | break; |
| 19526 | } |
| 19527 | case ARM::MVE_VABSf16: |
| 19528 | case ARM::MVE_VABSf32: |
| 19529 | case ARM::MVE_VCVTf16s16n: |
| 19530 | case ARM::MVE_VCVTf16u16n: |
| 19531 | case ARM::MVE_VCVTf32s32n: |
| 19532 | case ARM::MVE_VCVTf32u32n: |
| 19533 | case ARM::MVE_VCVTs16f16a: |
| 19534 | case ARM::MVE_VCVTs16f16m: |
| 19535 | case ARM::MVE_VCVTs16f16n: |
| 19536 | case ARM::MVE_VCVTs16f16p: |
| 19537 | case ARM::MVE_VCVTs16f16z: |
| 19538 | case ARM::MVE_VCVTs32f32a: |
| 19539 | case ARM::MVE_VCVTs32f32m: |
| 19540 | case ARM::MVE_VCVTs32f32n: |
| 19541 | case ARM::MVE_VCVTs32f32p: |
| 19542 | case ARM::MVE_VCVTs32f32z: |
| 19543 | case ARM::MVE_VCVTu16f16a: |
| 19544 | case ARM::MVE_VCVTu16f16m: |
| 19545 | case ARM::MVE_VCVTu16f16n: |
| 19546 | case ARM::MVE_VCVTu16f16p: |
| 19547 | case ARM::MVE_VCVTu16f16z: |
| 19548 | case ARM::MVE_VCVTu32f32a: |
| 19549 | case ARM::MVE_VCVTu32f32m: |
| 19550 | case ARM::MVE_VCVTu32f32n: |
| 19551 | case ARM::MVE_VCVTu32f32p: |
| 19552 | case ARM::MVE_VCVTu32f32z: |
| 19553 | case ARM::MVE_VNEGf16: |
| 19554 | case ARM::MVE_VNEGf32: |
| 19555 | case ARM::MVE_VRINTf16A: |
| 19556 | case ARM::MVE_VRINTf16M: |
| 19557 | case ARM::MVE_VRINTf16N: |
| 19558 | case ARM::MVE_VRINTf16P: |
| 19559 | case ARM::MVE_VRINTf16X: |
| 19560 | case ARM::MVE_VRINTf16Z: |
| 19561 | case ARM::MVE_VRINTf32A: |
| 19562 | case ARM::MVE_VRINTf32M: |
| 19563 | case ARM::MVE_VRINTf32N: |
| 19564 | case ARM::MVE_VRINTf32P: |
| 19565 | case ARM::MVE_VRINTf32X: |
| 19566 | case ARM::MVE_VRINTf32Z: { |
| 19567 | switch (OpNum) { |
| 19568 | case 1: |
| 19569 | // op: Qm |
| 19570 | return 1; |
| 19571 | case 0: |
| 19572 | // op: Qd |
| 19573 | return 13; |
| 19574 | } |
| 19575 | break; |
| 19576 | } |
| 19577 | case ARM::MVE_VADDVs16no_acc: |
| 19578 | case ARM::MVE_VADDVs32no_acc: |
| 19579 | case ARM::MVE_VADDVs8no_acc: |
| 19580 | case ARM::MVE_VADDVu16no_acc: |
| 19581 | case ARM::MVE_VADDVu32no_acc: |
| 19582 | case ARM::MVE_VADDVu8no_acc: { |
| 19583 | switch (OpNum) { |
| 19584 | case 1: |
| 19585 | // op: Qm |
| 19586 | return 1; |
| 19587 | case 0: |
| 19588 | // op: Rda |
| 19589 | return 13; |
| 19590 | } |
| 19591 | break; |
| 19592 | } |
| 19593 | case ARM::MVE_VPSEL: { |
| 19594 | switch (OpNum) { |
| 19595 | case 1: |
| 19596 | // op: Qn |
| 19597 | return 7; |
| 19598 | case 0: |
| 19599 | // op: Qd |
| 19600 | return 13; |
| 19601 | case 2: |
| 19602 | // op: Qm |
| 19603 | return 1; |
| 19604 | } |
| 19605 | break; |
| 19606 | } |
| 19607 | case ARM::t2SMLALD: |
| 19608 | case ARM::t2SMLALDX: |
| 19609 | case ARM::t2SMLSLD: |
| 19610 | case ARM::t2SMLSLDX: { |
| 19611 | switch (OpNum) { |
| 19612 | case 1: |
| 19613 | // op: Rd |
| 19614 | return 8; |
| 19615 | case 2: |
| 19616 | // op: Rn |
| 19617 | return 16; |
| 19618 | case 3: |
| 19619 | // op: Rm |
| 19620 | return 0; |
| 19621 | case 0: |
| 19622 | // op: Ra |
| 19623 | return 12; |
| 19624 | } |
| 19625 | break; |
| 19626 | } |
| 19627 | case ARM::tREV: |
| 19628 | case ARM::tREV16: |
| 19629 | case ARM::tREVSH: |
| 19630 | case ARM::tSXTB: |
| 19631 | case ARM::tSXTH: |
| 19632 | case ARM::tUXTB: |
| 19633 | case ARM::tUXTH: { |
| 19634 | switch (OpNum) { |
| 19635 | case 1: |
| 19636 | // op: Rm |
| 19637 | return 3; |
| 19638 | case 0: |
| 19639 | // op: Rd |
| 19640 | return 0; |
| 19641 | } |
| 19642 | break; |
| 19643 | } |
| 19644 | case ARM::tCMNz: |
| 19645 | case ARM::tCMPhir: |
| 19646 | case ARM::tCMPr: |
| 19647 | case ARM::tTST: { |
| 19648 | switch (OpNum) { |
| 19649 | case 1: |
| 19650 | // op: Rm |
| 19651 | return 3; |
| 19652 | case 0: |
| 19653 | // op: Rn |
| 19654 | return 0; |
| 19655 | } |
| 19656 | break; |
| 19657 | } |
| 19658 | case ARM::t2TT: |
| 19659 | case ARM::t2TTA: |
| 19660 | case ARM::t2TTAT: |
| 19661 | case ARM::t2TTT: { |
| 19662 | switch (OpNum) { |
| 19663 | case 1: |
| 19664 | // op: Rn |
| 19665 | return 16; |
| 19666 | case 0: |
| 19667 | // op: Rt |
| 19668 | return 8; |
| 19669 | } |
| 19670 | break; |
| 19671 | } |
| 19672 | case ARM::MVE_WLSTP_16: |
| 19673 | case ARM::MVE_WLSTP_32: |
| 19674 | case ARM::MVE_WLSTP_64: |
| 19675 | case ARM::MVE_WLSTP_8: |
| 19676 | case ARM::t2WLS: { |
| 19677 | switch (OpNum) { |
| 19678 | case 1: |
| 19679 | // op: Rn |
| 19680 | return 16; |
| 19681 | case 2: |
| 19682 | // op: label |
| 19683 | return 1; |
| 19684 | } |
| 19685 | break; |
| 19686 | } |
| 19687 | case ARM::t2LDMDB_UPD: |
| 19688 | case ARM::t2LDMIA_UPD: |
| 19689 | case ARM::t2STMDB_UPD: |
| 19690 | case ARM::t2STMIA_UPD: { |
| 19691 | switch (OpNum) { |
| 19692 | case 1: |
| 19693 | // op: Rn |
| 19694 | return 16; |
| 19695 | case 4: |
| 19696 | // op: regs |
| 19697 | return 0; |
| 19698 | } |
| 19699 | break; |
| 19700 | } |
| 19701 | case ARM::MVE_DLSTP_16: |
| 19702 | case ARM::MVE_DLSTP_32: |
| 19703 | case ARM::MVE_DLSTP_64: |
| 19704 | case ARM::MVE_DLSTP_8: |
| 19705 | case ARM::MVE_VCTP16: |
| 19706 | case ARM::MVE_VCTP32: |
| 19707 | case ARM::MVE_VCTP64: |
| 19708 | case ARM::MVE_VCTP8: |
| 19709 | case ARM::t2DLS: { |
| 19710 | switch (OpNum) { |
| 19711 | case 1: |
| 19712 | // op: Rn |
| 19713 | return 16; |
| 19714 | } |
| 19715 | break; |
| 19716 | } |
| 19717 | case ARM::tSTMIA_UPD: { |
| 19718 | switch (OpNum) { |
| 19719 | case 1: |
| 19720 | // op: Rn |
| 19721 | return 8; |
| 19722 | case 4: |
| 19723 | // op: regs |
| 19724 | return 0; |
| 19725 | } |
| 19726 | break; |
| 19727 | } |
| 19728 | case ARM::t2STRB_POST: |
| 19729 | case ARM::t2STRH_POST: |
| 19730 | case ARM::t2STR_POST: { |
| 19731 | switch (OpNum) { |
| 19732 | case 1: |
| 19733 | // op: Rt |
| 19734 | return 12; |
| 19735 | case 2: |
| 19736 | // op: Rn |
| 19737 | return 16; |
| 19738 | case 3: |
| 19739 | // op: offset |
| 19740 | return 0; |
| 19741 | } |
| 19742 | break; |
| 19743 | } |
| 19744 | case ARM::t2STRD_PRE: { |
| 19745 | switch (OpNum) { |
| 19746 | case 1: |
| 19747 | // op: Rt |
| 19748 | return 12; |
| 19749 | case 2: |
| 19750 | // op: Rt2 |
| 19751 | return 8; |
| 19752 | case 3: |
| 19753 | // op: addr |
| 19754 | return 0; |
| 19755 | } |
| 19756 | break; |
| 19757 | } |
| 19758 | case ARM::t2STRD_POST: { |
| 19759 | switch (OpNum) { |
| 19760 | case 1: |
| 19761 | // op: Rt |
| 19762 | return 12; |
| 19763 | case 2: |
| 19764 | // op: Rt2 |
| 19765 | return 8; |
| 19766 | case 3: |
| 19767 | // op: addr |
| 19768 | return 16; |
| 19769 | case 4: |
| 19770 | // op: imm |
| 19771 | return 0; |
| 19772 | } |
| 19773 | break; |
| 19774 | } |
| 19775 | case ARM::t2STRB_PRE: |
| 19776 | case ARM::t2STRH_PRE: |
| 19777 | case ARM::t2STR_PRE: { |
| 19778 | switch (OpNum) { |
| 19779 | case 1: |
| 19780 | // op: Rt |
| 19781 | return 12; |
| 19782 | case 2: |
| 19783 | // op: addr |
| 19784 | return 0; |
| 19785 | } |
| 19786 | break; |
| 19787 | } |
| 19788 | case ARM::VGETLNi32: { |
| 19789 | switch (OpNum) { |
| 19790 | case 1: |
| 19791 | // op: V |
| 19792 | return 7; |
| 19793 | case 0: |
| 19794 | // op: R |
| 19795 | return 12; |
| 19796 | case 3: |
| 19797 | // op: p |
| 19798 | return 28; |
| 19799 | case 2: |
| 19800 | // op: lane |
| 19801 | return 21; |
| 19802 | } |
| 19803 | break; |
| 19804 | } |
| 19805 | case ARM::VGETLNs8: |
| 19806 | case ARM::VGETLNu8: { |
| 19807 | switch (OpNum) { |
| 19808 | case 1: |
| 19809 | // op: V |
| 19810 | return 7; |
| 19811 | case 0: |
| 19812 | // op: R |
| 19813 | return 12; |
| 19814 | case 3: |
| 19815 | // op: p |
| 19816 | return 28; |
| 19817 | case 2: |
| 19818 | // op: lane |
| 19819 | return 5; |
| 19820 | } |
| 19821 | break; |
| 19822 | } |
| 19823 | case ARM::VGETLNs16: |
| 19824 | case ARM::VGETLNu16: { |
| 19825 | switch (OpNum) { |
| 19826 | case 1: |
| 19827 | // op: V |
| 19828 | return 7; |
| 19829 | case 0: |
| 19830 | // op: R |
| 19831 | return 12; |
| 19832 | case 3: |
| 19833 | // op: p |
| 19834 | return 28; |
| 19835 | case 2: |
| 19836 | // op: lane |
| 19837 | return 6; |
| 19838 | } |
| 19839 | break; |
| 19840 | } |
| 19841 | case ARM::MVE_VST20_16_wb: |
| 19842 | case ARM::MVE_VST20_32_wb: |
| 19843 | case ARM::MVE_VST20_8_wb: |
| 19844 | case ARM::MVE_VST21_16_wb: |
| 19845 | case ARM::MVE_VST21_32_wb: |
| 19846 | case ARM::MVE_VST21_8_wb: |
| 19847 | case ARM::MVE_VST40_16_wb: |
| 19848 | case ARM::MVE_VST40_32_wb: |
| 19849 | case ARM::MVE_VST40_8_wb: |
| 19850 | case ARM::MVE_VST41_16_wb: |
| 19851 | case ARM::MVE_VST41_32_wb: |
| 19852 | case ARM::MVE_VST41_8_wb: |
| 19853 | case ARM::MVE_VST42_16_wb: |
| 19854 | case ARM::MVE_VST42_32_wb: |
| 19855 | case ARM::MVE_VST42_8_wb: |
| 19856 | case ARM::MVE_VST43_16_wb: |
| 19857 | case ARM::MVE_VST43_32_wb: |
| 19858 | case ARM::MVE_VST43_8_wb: { |
| 19859 | switch (OpNum) { |
| 19860 | case 1: |
| 19861 | // op: VQd |
| 19862 | return 13; |
| 19863 | case 2: |
| 19864 | // op: Rn |
| 19865 | return 16; |
| 19866 | } |
| 19867 | break; |
| 19868 | } |
| 19869 | case ARM::VBF16MALBQI: |
| 19870 | case ARM::VBF16MALTQI: { |
| 19871 | switch (OpNum) { |
| 19872 | case 1: |
| 19873 | // op: Vd |
| 19874 | return 12; |
| 19875 | case 2: |
| 19876 | // op: Vn |
| 19877 | return 7; |
| 19878 | case 3: |
| 19879 | // op: Vm |
| 19880 | return 0; |
| 19881 | case 4: |
| 19882 | // op: idx |
| 19883 | return 3; |
| 19884 | } |
| 19885 | break; |
| 19886 | } |
| 19887 | case ARM::BF16VDOTI_VDOTD: |
| 19888 | case ARM::BF16VDOTI_VDOTQ: |
| 19889 | case ARM::VSDOTDI: |
| 19890 | case ARM::VSDOTQI: |
| 19891 | case ARM::VSUDOTDI: |
| 19892 | case ARM::VSUDOTQI: |
| 19893 | case ARM::VUDOTDI: |
| 19894 | case ARM::VUDOTQI: |
| 19895 | case ARM::VUSDOTDI: |
| 19896 | case ARM::VUSDOTQI: { |
| 19897 | switch (OpNum) { |
| 19898 | case 1: |
| 19899 | // op: Vd |
| 19900 | return 12; |
| 19901 | case 2: |
| 19902 | // op: Vn |
| 19903 | return 7; |
| 19904 | case 3: |
| 19905 | // op: Vm |
| 19906 | return 0; |
| 19907 | case 4: |
| 19908 | // op: lane |
| 19909 | return 5; |
| 19910 | } |
| 19911 | break; |
| 19912 | } |
| 19913 | case ARM::BF16VDOTS_VDOTD: |
| 19914 | case ARM::BF16VDOTS_VDOTQ: |
| 19915 | case ARM::VBF16MALBQ: |
| 19916 | case ARM::VBF16MALTQ: |
| 19917 | case ARM::VMMLA: |
| 19918 | case ARM::VSDOTD: |
| 19919 | case ARM::VSDOTQ: |
| 19920 | case ARM::VSMMLA: |
| 19921 | case ARM::VUDOTD: |
| 19922 | case ARM::VUDOTQ: |
| 19923 | case ARM::VUMMLA: |
| 19924 | case ARM::VUSDOTD: |
| 19925 | case ARM::VUSDOTQ: |
| 19926 | case ARM::VUSMMLA: { |
| 19927 | switch (OpNum) { |
| 19928 | case 1: |
| 19929 | // op: Vd |
| 19930 | return 12; |
| 19931 | case 2: |
| 19932 | // op: Vn |
| 19933 | return 7; |
| 19934 | case 3: |
| 19935 | // op: Vm |
| 19936 | return 0; |
| 19937 | } |
| 19938 | break; |
| 19939 | } |
| 19940 | case ARM::t2LDAEXB: |
| 19941 | case ARM::t2LDAEXH: |
| 19942 | case ARM::t2LDREXB: |
| 19943 | case ARM::t2LDREXH: { |
| 19944 | switch (OpNum) { |
| 19945 | case 1: |
| 19946 | // op: addr |
| 19947 | return 16; |
| 19948 | case 0: |
| 19949 | // op: Rt |
| 19950 | return 12; |
| 19951 | } |
| 19952 | break; |
| 19953 | } |
| 19954 | case ARM::t2MRSbanked: { |
| 19955 | switch (OpNum) { |
| 19956 | case 1: |
| 19957 | // op: banked |
| 19958 | return 4; |
| 19959 | case 0: |
| 19960 | // op: Rd |
| 19961 | return 8; |
| 19962 | } |
| 19963 | break; |
| 19964 | } |
| 19965 | case ARM::CDE_VCX1_vec: { |
| 19966 | switch (OpNum) { |
| 19967 | case 1: |
| 19968 | // op: coproc |
| 19969 | return 8; |
| 19970 | case 2: |
| 19971 | // op: imm |
| 19972 | return 0; |
| 19973 | case 0: |
| 19974 | // op: Qd |
| 19975 | return 13; |
| 19976 | } |
| 19977 | break; |
| 19978 | } |
| 19979 | case ARM::CDE_CX1: |
| 19980 | case ARM::CDE_CX1D: { |
| 19981 | switch (OpNum) { |
| 19982 | case 1: |
| 19983 | // op: coproc |
| 19984 | return 8; |
| 19985 | case 2: |
| 19986 | // op: imm |
| 19987 | return 0; |
| 19988 | case 0: |
| 19989 | // op: Rd |
| 19990 | return 12; |
| 19991 | } |
| 19992 | break; |
| 19993 | } |
| 19994 | case ARM::CDE_VCX1_fpdp: |
| 19995 | case ARM::CDE_VCX1_fpsp: { |
| 19996 | switch (OpNum) { |
| 19997 | case 1: |
| 19998 | // op: coproc |
| 19999 | return 8; |
| 20000 | case 2: |
| 20001 | // op: imm |
| 20002 | return 0; |
| 20003 | case 0: |
| 20004 | // op: Vd |
| 20005 | return 12; |
| 20006 | } |
| 20007 | break; |
| 20008 | } |
| 20009 | case ARM::CDE_VCX1A_vec: { |
| 20010 | switch (OpNum) { |
| 20011 | case 1: |
| 20012 | // op: coproc |
| 20013 | return 8; |
| 20014 | case 3: |
| 20015 | // op: imm |
| 20016 | return 0; |
| 20017 | case 0: |
| 20018 | // op: Qd |
| 20019 | return 13; |
| 20020 | } |
| 20021 | break; |
| 20022 | } |
| 20023 | case ARM::CDE_CX2: |
| 20024 | case ARM::CDE_CX2D: { |
| 20025 | switch (OpNum) { |
| 20026 | case 1: |
| 20027 | // op: coproc |
| 20028 | return 8; |
| 20029 | case 3: |
| 20030 | // op: imm |
| 20031 | return 0; |
| 20032 | case 0: |
| 20033 | // op: Rd |
| 20034 | return 12; |
| 20035 | case 2: |
| 20036 | // op: Rn |
| 20037 | return 16; |
| 20038 | } |
| 20039 | break; |
| 20040 | } |
| 20041 | case ARM::CDE_CX1A: |
| 20042 | case ARM::CDE_CX1DA: { |
| 20043 | switch (OpNum) { |
| 20044 | case 1: |
| 20045 | // op: coproc |
| 20046 | return 8; |
| 20047 | case 3: |
| 20048 | // op: imm |
| 20049 | return 0; |
| 20050 | case 0: |
| 20051 | // op: Rd |
| 20052 | return 12; |
| 20053 | } |
| 20054 | break; |
| 20055 | } |
| 20056 | case ARM::CDE_VCX1A_fpdp: |
| 20057 | case ARM::CDE_VCX1A_fpsp: { |
| 20058 | switch (OpNum) { |
| 20059 | case 1: |
| 20060 | // op: coproc |
| 20061 | return 8; |
| 20062 | case 3: |
| 20063 | // op: imm |
| 20064 | return 0; |
| 20065 | case 0: |
| 20066 | // op: Vd |
| 20067 | return 12; |
| 20068 | } |
| 20069 | break; |
| 20070 | } |
| 20071 | case ARM::CDE_VCX2_vec: { |
| 20072 | switch (OpNum) { |
| 20073 | case 1: |
| 20074 | // op: coproc |
| 20075 | return 8; |
| 20076 | case 3: |
| 20077 | // op: imm |
| 20078 | return 4; |
| 20079 | case 0: |
| 20080 | // op: Qd |
| 20081 | return 13; |
| 20082 | case 2: |
| 20083 | // op: Qm |
| 20084 | return 1; |
| 20085 | } |
| 20086 | break; |
| 20087 | } |
| 20088 | case ARM::CDE_VCX2_fpdp: |
| 20089 | case ARM::CDE_VCX2_fpsp: { |
| 20090 | switch (OpNum) { |
| 20091 | case 1: |
| 20092 | // op: coproc |
| 20093 | return 8; |
| 20094 | case 3: |
| 20095 | // op: imm |
| 20096 | return 4; |
| 20097 | case 0: |
| 20098 | // op: Vd |
| 20099 | return 12; |
| 20100 | case 2: |
| 20101 | // op: Vm |
| 20102 | return 0; |
| 20103 | } |
| 20104 | break; |
| 20105 | } |
| 20106 | case ARM::CDE_CX2A: |
| 20107 | case ARM::CDE_CX2DA: { |
| 20108 | switch (OpNum) { |
| 20109 | case 1: |
| 20110 | // op: coproc |
| 20111 | return 8; |
| 20112 | case 4: |
| 20113 | // op: imm |
| 20114 | return 0; |
| 20115 | case 0: |
| 20116 | // op: Rd |
| 20117 | return 12; |
| 20118 | case 3: |
| 20119 | // op: Rn |
| 20120 | return 16; |
| 20121 | } |
| 20122 | break; |
| 20123 | } |
| 20124 | case ARM::CDE_VCX3_vec: { |
| 20125 | switch (OpNum) { |
| 20126 | case 1: |
| 20127 | // op: coproc |
| 20128 | return 8; |
| 20129 | case 4: |
| 20130 | // op: imm |
| 20131 | return 4; |
| 20132 | case 0: |
| 20133 | // op: Qd |
| 20134 | return 13; |
| 20135 | case 3: |
| 20136 | // op: Qm |
| 20137 | return 1; |
| 20138 | case 2: |
| 20139 | // op: Qn |
| 20140 | return 17; |
| 20141 | } |
| 20142 | break; |
| 20143 | } |
| 20144 | case ARM::CDE_VCX2A_vec: { |
| 20145 | switch (OpNum) { |
| 20146 | case 1: |
| 20147 | // op: coproc |
| 20148 | return 8; |
| 20149 | case 4: |
| 20150 | // op: imm |
| 20151 | return 4; |
| 20152 | case 0: |
| 20153 | // op: Qd |
| 20154 | return 13; |
| 20155 | case 3: |
| 20156 | // op: Qm |
| 20157 | return 1; |
| 20158 | } |
| 20159 | break; |
| 20160 | } |
| 20161 | case ARM::CDE_CX3: |
| 20162 | case ARM::CDE_CX3D: { |
| 20163 | switch (OpNum) { |
| 20164 | case 1: |
| 20165 | // op: coproc |
| 20166 | return 8; |
| 20167 | case 4: |
| 20168 | // op: imm |
| 20169 | return 4; |
| 20170 | case 0: |
| 20171 | // op: Rd |
| 20172 | return 0; |
| 20173 | case 2: |
| 20174 | // op: Rn |
| 20175 | return 16; |
| 20176 | case 3: |
| 20177 | // op: Rm |
| 20178 | return 12; |
| 20179 | } |
| 20180 | break; |
| 20181 | } |
| 20182 | case ARM::CDE_VCX3_fpdp: |
| 20183 | case ARM::CDE_VCX3_fpsp: { |
| 20184 | switch (OpNum) { |
| 20185 | case 1: |
| 20186 | // op: coproc |
| 20187 | return 8; |
| 20188 | case 4: |
| 20189 | // op: imm |
| 20190 | return 4; |
| 20191 | case 0: |
| 20192 | // op: Vd |
| 20193 | return 12; |
| 20194 | case 3: |
| 20195 | // op: Vm |
| 20196 | return 0; |
| 20197 | case 2: |
| 20198 | // op: Vn |
| 20199 | return 7; |
| 20200 | } |
| 20201 | break; |
| 20202 | } |
| 20203 | case ARM::CDE_VCX2A_fpdp: |
| 20204 | case ARM::CDE_VCX2A_fpsp: { |
| 20205 | switch (OpNum) { |
| 20206 | case 1: |
| 20207 | // op: coproc |
| 20208 | return 8; |
| 20209 | case 4: |
| 20210 | // op: imm |
| 20211 | return 4; |
| 20212 | case 0: |
| 20213 | // op: Vd |
| 20214 | return 12; |
| 20215 | case 3: |
| 20216 | // op: Vm |
| 20217 | return 0; |
| 20218 | } |
| 20219 | break; |
| 20220 | } |
| 20221 | case ARM::CDE_VCX3A_vec: { |
| 20222 | switch (OpNum) { |
| 20223 | case 1: |
| 20224 | // op: coproc |
| 20225 | return 8; |
| 20226 | case 5: |
| 20227 | // op: imm |
| 20228 | return 4; |
| 20229 | case 0: |
| 20230 | // op: Qd |
| 20231 | return 13; |
| 20232 | case 4: |
| 20233 | // op: Qm |
| 20234 | return 1; |
| 20235 | case 3: |
| 20236 | // op: Qn |
| 20237 | return 17; |
| 20238 | } |
| 20239 | break; |
| 20240 | } |
| 20241 | case ARM::CDE_CX3A: |
| 20242 | case ARM::CDE_CX3DA: { |
| 20243 | switch (OpNum) { |
| 20244 | case 1: |
| 20245 | // op: coproc |
| 20246 | return 8; |
| 20247 | case 5: |
| 20248 | // op: imm |
| 20249 | return 4; |
| 20250 | case 0: |
| 20251 | // op: Rd |
| 20252 | return 0; |
| 20253 | case 3: |
| 20254 | // op: Rn |
| 20255 | return 16; |
| 20256 | case 4: |
| 20257 | // op: Rm |
| 20258 | return 12; |
| 20259 | } |
| 20260 | break; |
| 20261 | } |
| 20262 | case ARM::CDE_VCX3A_fpdp: |
| 20263 | case ARM::CDE_VCX3A_fpsp: { |
| 20264 | switch (OpNum) { |
| 20265 | case 1: |
| 20266 | // op: coproc |
| 20267 | return 8; |
| 20268 | case 5: |
| 20269 | // op: imm |
| 20270 | return 4; |
| 20271 | case 0: |
| 20272 | // op: Vd |
| 20273 | return 12; |
| 20274 | case 4: |
| 20275 | // op: Vm |
| 20276 | return 0; |
| 20277 | case 3: |
| 20278 | // op: Vn |
| 20279 | return 7; |
| 20280 | } |
| 20281 | break; |
| 20282 | } |
| 20283 | case ARM::MVE_VMOVimmf32: |
| 20284 | case ARM::MVE_VMOVimmi16: |
| 20285 | case ARM::MVE_VMOVimmi32: |
| 20286 | case ARM::MVE_VMOVimmi64: |
| 20287 | case ARM::MVE_VMOVimmi8: |
| 20288 | case ARM::MVE_VMVNimmi16: |
| 20289 | case ARM::MVE_VMVNimmi32: { |
| 20290 | switch (OpNum) { |
| 20291 | case 1: |
| 20292 | // op: imm |
| 20293 | return 0; |
| 20294 | case 0: |
| 20295 | // op: Qd |
| 20296 | return 13; |
| 20297 | } |
| 20298 | break; |
| 20299 | } |
| 20300 | case ARM::CDP2: |
| 20301 | case ARM::t2CDP: |
| 20302 | case ARM::t2CDP2: { |
| 20303 | switch (OpNum) { |
| 20304 | case 1: |
| 20305 | // op: opc1 |
| 20306 | return 20; |
| 20307 | case 3: |
| 20308 | // op: CRn |
| 20309 | return 16; |
| 20310 | case 2: |
| 20311 | // op: CRd |
| 20312 | return 12; |
| 20313 | case 0: |
| 20314 | // op: cop |
| 20315 | return 8; |
| 20316 | case 5: |
| 20317 | // op: opc2 |
| 20318 | return 5; |
| 20319 | case 4: |
| 20320 | // op: CRm |
| 20321 | return 0; |
| 20322 | } |
| 20323 | break; |
| 20324 | } |
| 20325 | case ARM::t2Bcc: { |
| 20326 | switch (OpNum) { |
| 20327 | case 1: |
| 20328 | // op: p |
| 20329 | return 22; |
| 20330 | case 0: |
| 20331 | // op: target |
| 20332 | return 0; |
| 20333 | } |
| 20334 | break; |
| 20335 | } |
| 20336 | case ARM::VCMPEZD: |
| 20337 | case ARM::VCMPZD: { |
| 20338 | switch (OpNum) { |
| 20339 | case 1: |
| 20340 | // op: p |
| 20341 | return 28; |
| 20342 | case 0: |
| 20343 | // op: Dd |
| 20344 | return 12; |
| 20345 | } |
| 20346 | break; |
| 20347 | } |
| 20348 | case ARM::MRS: |
| 20349 | case ARM::MRSsys: { |
| 20350 | switch (OpNum) { |
| 20351 | case 1: |
| 20352 | // op: p |
| 20353 | return 28; |
| 20354 | case 0: |
| 20355 | // op: Rd |
| 20356 | return 12; |
| 20357 | } |
| 20358 | break; |
| 20359 | } |
| 20360 | case ARM::VLDMSIA: |
| 20361 | case ARM::VSTMSIA: { |
| 20362 | switch (OpNum) { |
| 20363 | case 1: |
| 20364 | // op: p |
| 20365 | return 28; |
| 20366 | case 0: |
| 20367 | // op: Rn |
| 20368 | return 16; |
| 20369 | case 3: |
| 20370 | // op: regs |
| 20371 | return 0; |
| 20372 | } |
| 20373 | break; |
| 20374 | } |
| 20375 | case ARM::FLDMXIA: |
| 20376 | case ARM::FSTMXIA: |
| 20377 | case ARM::VLDMDIA: |
| 20378 | case ARM::VSTMDIA: { |
| 20379 | switch (OpNum) { |
| 20380 | case 1: |
| 20381 | // op: p |
| 20382 | return 28; |
| 20383 | case 0: |
| 20384 | // op: Rn |
| 20385 | return 16; |
| 20386 | case 3: |
| 20387 | // op: regs |
| 20388 | return 1; |
| 20389 | } |
| 20390 | break; |
| 20391 | } |
| 20392 | case ARM::VMRS: |
| 20393 | case ARM::VMRS_FPCXTNS: |
| 20394 | case ARM::VMRS_FPCXTS: |
| 20395 | case ARM::VMRS_FPEXC: |
| 20396 | case ARM::VMRS_FPINST: |
| 20397 | case ARM::VMRS_FPINST2: |
| 20398 | case ARM::VMRS_FPSID: |
| 20399 | case ARM::VMRS_MVFR0: |
| 20400 | case ARM::VMRS_MVFR1: |
| 20401 | case ARM::VMRS_MVFR2: |
| 20402 | case ARM::VMRS_VPR: |
| 20403 | case ARM::VMSR: |
| 20404 | case ARM::VMSR_FPCXTNS: |
| 20405 | case ARM::VMSR_FPCXTS: |
| 20406 | case ARM::VMSR_FPEXC: |
| 20407 | case ARM::VMSR_FPINST: |
| 20408 | case ARM::VMSR_FPINST2: |
| 20409 | case ARM::VMSR_FPSID: |
| 20410 | case ARM::VMSR_VPR: { |
| 20411 | switch (OpNum) { |
| 20412 | case 1: |
| 20413 | // op: p |
| 20414 | return 28; |
| 20415 | case 0: |
| 20416 | // op: Rt |
| 20417 | return 12; |
| 20418 | } |
| 20419 | break; |
| 20420 | } |
| 20421 | case ARM::VCMPEZH: |
| 20422 | case ARM::VCMPEZS: |
| 20423 | case ARM::VCMPZH: |
| 20424 | case ARM::VCMPZS: { |
| 20425 | switch (OpNum) { |
| 20426 | case 1: |
| 20427 | // op: p |
| 20428 | return 28; |
| 20429 | case 0: |
| 20430 | // op: Sd |
| 20431 | return 12; |
| 20432 | } |
| 20433 | break; |
| 20434 | } |
| 20435 | case ARM::BX_pred: { |
| 20436 | switch (OpNum) { |
| 20437 | case 1: |
| 20438 | // op: p |
| 20439 | return 28; |
| 20440 | case 0: |
| 20441 | // op: dst |
| 20442 | return 0; |
| 20443 | } |
| 20444 | break; |
| 20445 | } |
| 20446 | case ARM::BLX_pred: |
| 20447 | case ARM::BL_pred: |
| 20448 | case ARM::BXJ: { |
| 20449 | switch (OpNum) { |
| 20450 | case 1: |
| 20451 | // op: p |
| 20452 | return 28; |
| 20453 | case 0: |
| 20454 | // op: func |
| 20455 | return 0; |
| 20456 | } |
| 20457 | break; |
| 20458 | } |
| 20459 | case ARM::HINT: { |
| 20460 | switch (OpNum) { |
| 20461 | case 1: |
| 20462 | // op: p |
| 20463 | return 28; |
| 20464 | case 0: |
| 20465 | // op: imm |
| 20466 | return 0; |
| 20467 | } |
| 20468 | break; |
| 20469 | } |
| 20470 | case ARM::DBG: |
| 20471 | case ARM::SMC: { |
| 20472 | switch (OpNum) { |
| 20473 | case 1: |
| 20474 | // op: p |
| 20475 | return 28; |
| 20476 | case 0: |
| 20477 | // op: opt |
| 20478 | return 0; |
| 20479 | } |
| 20480 | break; |
| 20481 | } |
| 20482 | case ARM::SVC: { |
| 20483 | switch (OpNum) { |
| 20484 | case 1: |
| 20485 | // op: p |
| 20486 | return 28; |
| 20487 | case 0: |
| 20488 | // op: svc |
| 20489 | return 0; |
| 20490 | } |
| 20491 | break; |
| 20492 | } |
| 20493 | case ARM::Bcc: { |
| 20494 | switch (OpNum) { |
| 20495 | case 1: |
| 20496 | // op: p |
| 20497 | return 28; |
| 20498 | case 0: |
| 20499 | // op: target |
| 20500 | return 0; |
| 20501 | } |
| 20502 | break; |
| 20503 | } |
| 20504 | case ARM::LDMDA: |
| 20505 | case ARM::LDMDB: |
| 20506 | case ARM::LDMIA: |
| 20507 | case ARM::LDMIB: |
| 20508 | case ARM::STMDA: |
| 20509 | case ARM::STMDB: |
| 20510 | case ARM::STMIA: |
| 20511 | case ARM::STMIB: |
| 20512 | case ARM::sysLDMDA: |
| 20513 | case ARM::sysLDMDB: |
| 20514 | case ARM::sysLDMIA: |
| 20515 | case ARM::sysLDMIB: |
| 20516 | case ARM::sysSTMDA: |
| 20517 | case ARM::sysSTMDB: |
| 20518 | case ARM::sysSTMIA: |
| 20519 | case ARM::sysSTMIB: { |
| 20520 | switch (OpNum) { |
| 20521 | case 1: |
| 20522 | // op: p |
| 20523 | return 28; |
| 20524 | case 3: |
| 20525 | // op: regs |
| 20526 | return 0; |
| 20527 | case 0: |
| 20528 | // op: Rn |
| 20529 | return 16; |
| 20530 | } |
| 20531 | break; |
| 20532 | } |
| 20533 | case ARM::tBcc: { |
| 20534 | switch (OpNum) { |
| 20535 | case 1: |
| 20536 | // op: p |
| 20537 | return 8; |
| 20538 | case 0: |
| 20539 | // op: target |
| 20540 | return 0; |
| 20541 | } |
| 20542 | break; |
| 20543 | } |
| 20544 | case ARM::tCBNZ: |
| 20545 | case ARM::tCBZ: { |
| 20546 | switch (OpNum) { |
| 20547 | case 1: |
| 20548 | // op: target |
| 20549 | return 3; |
| 20550 | case 0: |
| 20551 | // op: Rn |
| 20552 | return 0; |
| 20553 | } |
| 20554 | break; |
| 20555 | } |
| 20556 | case ARM::MVE_VCADDf16: |
| 20557 | case ARM::MVE_VCADDf32: { |
| 20558 | switch (OpNum) { |
| 20559 | case 2: |
| 20560 | // op: Qm |
| 20561 | return 1; |
| 20562 | case 0: |
| 20563 | // op: Qd |
| 20564 | return 13; |
| 20565 | case 1: |
| 20566 | // op: Qn |
| 20567 | return 7; |
| 20568 | case 3: |
| 20569 | // op: rot |
| 20570 | return 24; |
| 20571 | } |
| 20572 | break; |
| 20573 | } |
| 20574 | case ARM::MVE_VABDf16: |
| 20575 | case ARM::MVE_VABDf32: |
| 20576 | case ARM::MVE_VADDf16: |
| 20577 | case ARM::MVE_VADDf32: |
| 20578 | case ARM::MVE_VMULf16: |
| 20579 | case ARM::MVE_VMULf32: |
| 20580 | case ARM::MVE_VSUBf16: |
| 20581 | case ARM::MVE_VSUBf32: { |
| 20582 | switch (OpNum) { |
| 20583 | case 2: |
| 20584 | // op: Qm |
| 20585 | return 1; |
| 20586 | case 0: |
| 20587 | // op: Qd |
| 20588 | return 13; |
| 20589 | case 1: |
| 20590 | // op: Qn |
| 20591 | return 7; |
| 20592 | } |
| 20593 | break; |
| 20594 | } |
| 20595 | case ARM::MVE_VADDVs16acc: |
| 20596 | case ARM::MVE_VADDVs32acc: |
| 20597 | case ARM::MVE_VADDVs8acc: |
| 20598 | case ARM::MVE_VADDVu16acc: |
| 20599 | case ARM::MVE_VADDVu32acc: |
| 20600 | case ARM::MVE_VADDVu8acc: { |
| 20601 | switch (OpNum) { |
| 20602 | case 2: |
| 20603 | // op: Qm |
| 20604 | return 1; |
| 20605 | case 0: |
| 20606 | // op: Rda |
| 20607 | return 13; |
| 20608 | } |
| 20609 | break; |
| 20610 | } |
| 20611 | case ARM::MVE_VMAXAVs16: |
| 20612 | case ARM::MVE_VMAXAVs32: |
| 20613 | case ARM::MVE_VMAXAVs8: |
| 20614 | case ARM::MVE_VMAXNMAVf16: |
| 20615 | case ARM::MVE_VMAXNMAVf32: |
| 20616 | case ARM::MVE_VMAXNMVf16: |
| 20617 | case ARM::MVE_VMAXNMVf32: |
| 20618 | case ARM::MVE_VMAXVs16: |
| 20619 | case ARM::MVE_VMAXVs32: |
| 20620 | case ARM::MVE_VMAXVs8: |
| 20621 | case ARM::MVE_VMAXVu16: |
| 20622 | case ARM::MVE_VMAXVu32: |
| 20623 | case ARM::MVE_VMAXVu8: |
| 20624 | case ARM::MVE_VMINAVs16: |
| 20625 | case ARM::MVE_VMINAVs32: |
| 20626 | case ARM::MVE_VMINAVs8: |
| 20627 | case ARM::MVE_VMINNMAVf16: |
| 20628 | case ARM::MVE_VMINNMAVf32: |
| 20629 | case ARM::MVE_VMINNMVf16: |
| 20630 | case ARM::MVE_VMINNMVf32: |
| 20631 | case ARM::MVE_VMINVs16: |
| 20632 | case ARM::MVE_VMINVs32: |
| 20633 | case ARM::MVE_VMINVs8: |
| 20634 | case ARM::MVE_VMINVu16: |
| 20635 | case ARM::MVE_VMINVu32: |
| 20636 | case ARM::MVE_VMINVu8: { |
| 20637 | switch (OpNum) { |
| 20638 | case 2: |
| 20639 | // op: Qm |
| 20640 | return 1; |
| 20641 | case 0: |
| 20642 | // op: RdaDest |
| 20643 | return 12; |
| 20644 | } |
| 20645 | break; |
| 20646 | } |
| 20647 | case ARM::MVE_VADDLVs32no_acc: |
| 20648 | case ARM::MVE_VADDLVu32no_acc: { |
| 20649 | switch (OpNum) { |
| 20650 | case 2: |
| 20651 | // op: Qm |
| 20652 | return 1; |
| 20653 | case 0: |
| 20654 | // op: RdaLo |
| 20655 | return 13; |
| 20656 | case 1: |
| 20657 | // op: RdaHi |
| 20658 | return 20; |
| 20659 | } |
| 20660 | break; |
| 20661 | } |
| 20662 | case ARM::t2AUTG: |
| 20663 | case ARM::t2BXAUT: { |
| 20664 | switch (OpNum) { |
| 20665 | case 2: |
| 20666 | // op: Ra |
| 20667 | return 12; |
| 20668 | case 3: |
| 20669 | // op: Rn |
| 20670 | return 16; |
| 20671 | case 4: |
| 20672 | // op: Rm |
| 20673 | return 0; |
| 20674 | } |
| 20675 | break; |
| 20676 | } |
| 20677 | case ARM::tADDspr: { |
| 20678 | switch (OpNum) { |
| 20679 | case 2: |
| 20680 | // op: Rm |
| 20681 | return 3; |
| 20682 | } |
| 20683 | break; |
| 20684 | } |
| 20685 | case ARM::MVE_VMOV_q_rr: { |
| 20686 | switch (OpNum) { |
| 20687 | case 2: |
| 20688 | // op: Rt |
| 20689 | return 0; |
| 20690 | case 3: |
| 20691 | // op: Rt2 |
| 20692 | return 16; |
| 20693 | case 0: |
| 20694 | // op: Qd |
| 20695 | return 13; |
| 20696 | case 5: |
| 20697 | // op: idx2 |
| 20698 | return 4; |
| 20699 | } |
| 20700 | break; |
| 20701 | } |
| 20702 | case ARM::MCR2: |
| 20703 | case ARM::t2MCR: |
| 20704 | case ARM::t2MCR2: { |
| 20705 | switch (OpNum) { |
| 20706 | case 2: |
| 20707 | // op: Rt |
| 20708 | return 12; |
| 20709 | case 0: |
| 20710 | // op: cop |
| 20711 | return 8; |
| 20712 | case 1: |
| 20713 | // op: opc1 |
| 20714 | return 21; |
| 20715 | case 5: |
| 20716 | // op: opc2 |
| 20717 | return 5; |
| 20718 | case 4: |
| 20719 | // op: CRm |
| 20720 | return 0; |
| 20721 | case 3: |
| 20722 | // op: CRn |
| 20723 | return 16; |
| 20724 | } |
| 20725 | break; |
| 20726 | } |
| 20727 | case ARM::MCRR2: |
| 20728 | case ARM::t2MCRR: |
| 20729 | case ARM::t2MCRR2: { |
| 20730 | switch (OpNum) { |
| 20731 | case 2: |
| 20732 | // op: Rt |
| 20733 | return 12; |
| 20734 | case 3: |
| 20735 | // op: Rt2 |
| 20736 | return 16; |
| 20737 | case 0: |
| 20738 | // op: cop |
| 20739 | return 8; |
| 20740 | case 1: |
| 20741 | // op: opc1 |
| 20742 | return 4; |
| 20743 | case 4: |
| 20744 | // op: CRm |
| 20745 | return 0; |
| 20746 | } |
| 20747 | break; |
| 20748 | } |
| 20749 | case ARM::VST1LNd8: { |
| 20750 | switch (OpNum) { |
| 20751 | case 2: |
| 20752 | // op: Vd |
| 20753 | return 12; |
| 20754 | case 0: |
| 20755 | // op: Rn |
| 20756 | return 16; |
| 20757 | case 3: |
| 20758 | // op: lane |
| 20759 | return 5; |
| 20760 | } |
| 20761 | break; |
| 20762 | } |
| 20763 | case ARM::VST3LNd8: { |
| 20764 | switch (OpNum) { |
| 20765 | case 2: |
| 20766 | // op: Vd |
| 20767 | return 12; |
| 20768 | case 0: |
| 20769 | // op: Rn |
| 20770 | return 16; |
| 20771 | case 5: |
| 20772 | // op: lane |
| 20773 | return 5; |
| 20774 | } |
| 20775 | break; |
| 20776 | } |
| 20777 | case ARM::VST3LNd16: |
| 20778 | case ARM::VST3LNq16: { |
| 20779 | switch (OpNum) { |
| 20780 | case 2: |
| 20781 | // op: Vd |
| 20782 | return 12; |
| 20783 | case 0: |
| 20784 | // op: Rn |
| 20785 | return 16; |
| 20786 | case 5: |
| 20787 | // op: lane |
| 20788 | return 6; |
| 20789 | } |
| 20790 | break; |
| 20791 | } |
| 20792 | case ARM::VST3LNd32: |
| 20793 | case ARM::VST3LNq32: { |
| 20794 | switch (OpNum) { |
| 20795 | case 2: |
| 20796 | // op: Vd |
| 20797 | return 12; |
| 20798 | case 0: |
| 20799 | // op: Rn |
| 20800 | return 16; |
| 20801 | case 5: |
| 20802 | // op: lane |
| 20803 | return 7; |
| 20804 | } |
| 20805 | break; |
| 20806 | } |
| 20807 | case ARM::VST1LNd16: { |
| 20808 | switch (OpNum) { |
| 20809 | case 2: |
| 20810 | // op: Vd |
| 20811 | return 12; |
| 20812 | case 0: |
| 20813 | // op: Rn |
| 20814 | return 4; |
| 20815 | case 3: |
| 20816 | // op: lane |
| 20817 | return 6; |
| 20818 | } |
| 20819 | break; |
| 20820 | } |
| 20821 | case ARM::VST1LNd32: { |
| 20822 | switch (OpNum) { |
| 20823 | case 2: |
| 20824 | // op: Vd |
| 20825 | return 12; |
| 20826 | case 0: |
| 20827 | // op: Rn |
| 20828 | return 4; |
| 20829 | case 3: |
| 20830 | // op: lane |
| 20831 | return 7; |
| 20832 | } |
| 20833 | break; |
| 20834 | } |
| 20835 | case ARM::VST2LNd8: { |
| 20836 | switch (OpNum) { |
| 20837 | case 2: |
| 20838 | // op: Vd |
| 20839 | return 12; |
| 20840 | case 0: |
| 20841 | // op: Rn |
| 20842 | return 4; |
| 20843 | case 4: |
| 20844 | // op: lane |
| 20845 | return 5; |
| 20846 | } |
| 20847 | break; |
| 20848 | } |
| 20849 | case ARM::VST2LNd16: |
| 20850 | case ARM::VST2LNq16: { |
| 20851 | switch (OpNum) { |
| 20852 | case 2: |
| 20853 | // op: Vd |
| 20854 | return 12; |
| 20855 | case 0: |
| 20856 | // op: Rn |
| 20857 | return 4; |
| 20858 | case 4: |
| 20859 | // op: lane |
| 20860 | return 6; |
| 20861 | } |
| 20862 | break; |
| 20863 | } |
| 20864 | case ARM::VST2LNd32: |
| 20865 | case ARM::VST2LNq32: { |
| 20866 | switch (OpNum) { |
| 20867 | case 2: |
| 20868 | // op: Vd |
| 20869 | return 12; |
| 20870 | case 0: |
| 20871 | // op: Rn |
| 20872 | return 4; |
| 20873 | case 4: |
| 20874 | // op: lane |
| 20875 | return 7; |
| 20876 | } |
| 20877 | break; |
| 20878 | } |
| 20879 | case ARM::VST4LNd8: { |
| 20880 | switch (OpNum) { |
| 20881 | case 2: |
| 20882 | // op: Vd |
| 20883 | return 12; |
| 20884 | case 0: |
| 20885 | // op: Rn |
| 20886 | return 4; |
| 20887 | case 6: |
| 20888 | // op: lane |
| 20889 | return 5; |
| 20890 | } |
| 20891 | break; |
| 20892 | } |
| 20893 | case ARM::VST4LNd16: |
| 20894 | case ARM::VST4LNq16: { |
| 20895 | switch (OpNum) { |
| 20896 | case 2: |
| 20897 | // op: Vd |
| 20898 | return 12; |
| 20899 | case 0: |
| 20900 | // op: Rn |
| 20901 | return 4; |
| 20902 | case 6: |
| 20903 | // op: lane |
| 20904 | return 6; |
| 20905 | } |
| 20906 | break; |
| 20907 | } |
| 20908 | case ARM::VST4LNd32: |
| 20909 | case ARM::VST4LNq32: { |
| 20910 | switch (OpNum) { |
| 20911 | case 2: |
| 20912 | // op: Vd |
| 20913 | return 12; |
| 20914 | case 0: |
| 20915 | // op: Rn |
| 20916 | return 4; |
| 20917 | case 6: |
| 20918 | // op: lane |
| 20919 | return 7; |
| 20920 | } |
| 20921 | break; |
| 20922 | } |
| 20923 | case ARM::VST1d16: |
| 20924 | case ARM::VST1d16Q: |
| 20925 | case ARM::VST1d16T: |
| 20926 | case ARM::VST1d32: |
| 20927 | case ARM::VST1d32Q: |
| 20928 | case ARM::VST1d32T: |
| 20929 | case ARM::VST1d64: |
| 20930 | case ARM::VST1d64Q: |
| 20931 | case ARM::VST1d64T: |
| 20932 | case ARM::VST1d8: |
| 20933 | case ARM::VST1d8Q: |
| 20934 | case ARM::VST1d8T: |
| 20935 | case ARM::VST1q16: |
| 20936 | case ARM::VST1q32: |
| 20937 | case ARM::VST1q64: |
| 20938 | case ARM::VST1q8: |
| 20939 | case ARM::VST2b16: |
| 20940 | case ARM::VST2b32: |
| 20941 | case ARM::VST2b8: |
| 20942 | case ARM::VST2d16: |
| 20943 | case ARM::VST2d32: |
| 20944 | case ARM::VST2d8: |
| 20945 | case ARM::VST2q16: |
| 20946 | case ARM::VST2q32: |
| 20947 | case ARM::VST2q8: |
| 20948 | case ARM::VST3d16: |
| 20949 | case ARM::VST3d32: |
| 20950 | case ARM::VST3d8: |
| 20951 | case ARM::VST3q16: |
| 20952 | case ARM::VST3q32: |
| 20953 | case ARM::VST3q8: |
| 20954 | case ARM::VST4d16: |
| 20955 | case ARM::VST4d32: |
| 20956 | case ARM::VST4d8: |
| 20957 | case ARM::VST4q16: |
| 20958 | case ARM::VST4q32: |
| 20959 | case ARM::VST4q8: { |
| 20960 | switch (OpNum) { |
| 20961 | case 2: |
| 20962 | // op: Vd |
| 20963 | return 12; |
| 20964 | case 0: |
| 20965 | // op: Rn |
| 20966 | return 4; |
| 20967 | } |
| 20968 | break; |
| 20969 | } |
| 20970 | case ARM::LDC2L_OFFSET: |
| 20971 | case ARM::LDC2L_PRE: |
| 20972 | case ARM::LDC2_OFFSET: |
| 20973 | case ARM::LDC2_PRE: |
| 20974 | case ARM::STC2L_OFFSET: |
| 20975 | case ARM::STC2L_PRE: |
| 20976 | case ARM::STC2_OFFSET: |
| 20977 | case ARM::STC2_PRE: |
| 20978 | case ARM::t2LDC2L_OFFSET: |
| 20979 | case ARM::t2LDC2L_PRE: |
| 20980 | case ARM::t2LDC2_OFFSET: |
| 20981 | case ARM::t2LDC2_PRE: |
| 20982 | case ARM::t2LDCL_OFFSET: |
| 20983 | case ARM::t2LDCL_PRE: |
| 20984 | case ARM::t2LDC_OFFSET: |
| 20985 | case ARM::t2LDC_PRE: |
| 20986 | case ARM::t2STC2L_OFFSET: |
| 20987 | case ARM::t2STC2L_PRE: |
| 20988 | case ARM::t2STC2_OFFSET: |
| 20989 | case ARM::t2STC2_PRE: |
| 20990 | case ARM::t2STCL_OFFSET: |
| 20991 | case ARM::t2STCL_PRE: |
| 20992 | case ARM::t2STC_OFFSET: |
| 20993 | case ARM::t2STC_PRE: { |
| 20994 | switch (OpNum) { |
| 20995 | case 2: |
| 20996 | // op: addr |
| 20997 | return 0; |
| 20998 | case 0: |
| 20999 | // op: cop |
| 21000 | return 8; |
| 21001 | case 1: |
| 21002 | // op: CRd |
| 21003 | return 12; |
| 21004 | } |
| 21005 | break; |
| 21006 | } |
| 21007 | case ARM::t2LDAEXD: |
| 21008 | case ARM::t2LDREXD: { |
| 21009 | switch (OpNum) { |
| 21010 | case 2: |
| 21011 | // op: addr |
| 21012 | return 16; |
| 21013 | case 0: |
| 21014 | // op: Rt |
| 21015 | return 12; |
| 21016 | case 1: |
| 21017 | // op: Rt2 |
| 21018 | return 8; |
| 21019 | } |
| 21020 | break; |
| 21021 | } |
| 21022 | case ARM::tBL: { |
| 21023 | switch (OpNum) { |
| 21024 | case 2: |
| 21025 | // op: func |
| 21026 | return 0; |
| 21027 | } |
| 21028 | break; |
| 21029 | } |
| 21030 | case ARM::tBLXi: { |
| 21031 | switch (OpNum) { |
| 21032 | case 2: |
| 21033 | // op: func |
| 21034 | return 1; |
| 21035 | } |
| 21036 | break; |
| 21037 | } |
| 21038 | case ARM::tBLXNSr: |
| 21039 | case ARM::tBLXr: { |
| 21040 | switch (OpNum) { |
| 21041 | case 2: |
| 21042 | // op: func |
| 21043 | return 3; |
| 21044 | } |
| 21045 | break; |
| 21046 | } |
| 21047 | case ARM::MVE_VBICimmi16: |
| 21048 | case ARM::MVE_VBICimmi32: |
| 21049 | case ARM::MVE_VORRimmi16: |
| 21050 | case ARM::MVE_VORRimmi32: { |
| 21051 | switch (OpNum) { |
| 21052 | case 2: |
| 21053 | // op: imm |
| 21054 | return 0; |
| 21055 | case 0: |
| 21056 | // op: Qd |
| 21057 | return 13; |
| 21058 | } |
| 21059 | break; |
| 21060 | } |
| 21061 | case ARM::t2ADDspImm12: |
| 21062 | case ARM::t2SUBspImm12: |
| 21063 | case ARM::tADDspi: |
| 21064 | case ARM::tSUBspi: { |
| 21065 | switch (OpNum) { |
| 21066 | case 2: |
| 21067 | // op: imm |
| 21068 | return 0; |
| 21069 | } |
| 21070 | break; |
| 21071 | } |
| 21072 | case ARM::MVE_LETP: |
| 21073 | case ARM::t2LEUpdate: { |
| 21074 | switch (OpNum) { |
| 21075 | case 2: |
| 21076 | // op: label |
| 21077 | return 1; |
| 21078 | } |
| 21079 | break; |
| 21080 | } |
| 21081 | case ARM::VABSD: |
| 21082 | case ARM::VCMPD: |
| 21083 | case ARM::VCMPED: |
| 21084 | case ARM::VMOVD: |
| 21085 | case ARM::VNEGD: |
| 21086 | case ARM::VRINTRD: |
| 21087 | case ARM::VRINTXD: |
| 21088 | case ARM::VRINTZD: |
| 21089 | case ARM::VSQRTD: { |
| 21090 | switch (OpNum) { |
| 21091 | case 2: |
| 21092 | // op: p |
| 21093 | return 28; |
| 21094 | case 0: |
| 21095 | // op: Dd |
| 21096 | return 12; |
| 21097 | case 1: |
| 21098 | // op: Dm |
| 21099 | return 0; |
| 21100 | } |
| 21101 | break; |
| 21102 | } |
| 21103 | case ARM::VCVTBHD: |
| 21104 | case ARM::VCVTTHD: |
| 21105 | case ARM::VSITOD: |
| 21106 | case ARM::VUITOD: { |
| 21107 | switch (OpNum) { |
| 21108 | case 2: |
| 21109 | // op: p |
| 21110 | return 28; |
| 21111 | case 0: |
| 21112 | // op: Dd |
| 21113 | return 12; |
| 21114 | case 1: |
| 21115 | // op: Sm |
| 21116 | return 0; |
| 21117 | } |
| 21118 | break; |
| 21119 | } |
| 21120 | case ARM::FCONSTD: { |
| 21121 | switch (OpNum) { |
| 21122 | case 2: |
| 21123 | // op: p |
| 21124 | return 28; |
| 21125 | case 0: |
| 21126 | // op: Dd |
| 21127 | return 12; |
| 21128 | case 1: |
| 21129 | // op: imm |
| 21130 | return 0; |
| 21131 | } |
| 21132 | break; |
| 21133 | } |
| 21134 | case ARM::CLZ: |
| 21135 | case ARM::RBIT: |
| 21136 | case ARM::REV: |
| 21137 | case ARM::REV16: |
| 21138 | case ARM::REVSH: { |
| 21139 | switch (OpNum) { |
| 21140 | case 2: |
| 21141 | // op: p |
| 21142 | return 28; |
| 21143 | case 0: |
| 21144 | // op: Rd |
| 21145 | return 12; |
| 21146 | case 1: |
| 21147 | // op: Rm |
| 21148 | return 0; |
| 21149 | } |
| 21150 | break; |
| 21151 | } |
| 21152 | case ARM::MOVi16: { |
| 21153 | switch (OpNum) { |
| 21154 | case 2: |
| 21155 | // op: p |
| 21156 | return 28; |
| 21157 | case 0: |
| 21158 | // op: Rd |
| 21159 | return 12; |
| 21160 | case 1: |
| 21161 | // op: imm |
| 21162 | return 0; |
| 21163 | } |
| 21164 | break; |
| 21165 | } |
| 21166 | case ARM::ADR: { |
| 21167 | switch (OpNum) { |
| 21168 | case 2: |
| 21169 | // op: p |
| 21170 | return 28; |
| 21171 | case 0: |
| 21172 | // op: Rd |
| 21173 | return 12; |
| 21174 | case 1: |
| 21175 | // op: label |
| 21176 | return 0; |
| 21177 | } |
| 21178 | break; |
| 21179 | } |
| 21180 | case ARM::CMNzrr: |
| 21181 | case ARM::CMPrr: |
| 21182 | case ARM::TEQrr: |
| 21183 | case ARM::TSTrr: { |
| 21184 | switch (OpNum) { |
| 21185 | case 2: |
| 21186 | // op: p |
| 21187 | return 28; |
| 21188 | case 0: |
| 21189 | // op: Rn |
| 21190 | return 16; |
| 21191 | case 1: |
| 21192 | // op: Rm |
| 21193 | return 0; |
| 21194 | } |
| 21195 | break; |
| 21196 | } |
| 21197 | case ARM::CMNri: |
| 21198 | case ARM::CMPri: |
| 21199 | case ARM::TEQri: |
| 21200 | case ARM::TSTri: { |
| 21201 | switch (OpNum) { |
| 21202 | case 2: |
| 21203 | // op: p |
| 21204 | return 28; |
| 21205 | case 0: |
| 21206 | // op: Rn |
| 21207 | return 16; |
| 21208 | case 1: |
| 21209 | // op: imm |
| 21210 | return 0; |
| 21211 | } |
| 21212 | break; |
| 21213 | } |
| 21214 | case ARM::STL: |
| 21215 | case ARM::STLB: |
| 21216 | case ARM::STLH: { |
| 21217 | switch (OpNum) { |
| 21218 | case 2: |
| 21219 | // op: p |
| 21220 | return 28; |
| 21221 | case 0: |
| 21222 | // op: Rt |
| 21223 | return 0; |
| 21224 | case 1: |
| 21225 | // op: addr |
| 21226 | return 16; |
| 21227 | } |
| 21228 | break; |
| 21229 | } |
| 21230 | case ARM::VMOVRH: |
| 21231 | case ARM::VMOVRS: { |
| 21232 | switch (OpNum) { |
| 21233 | case 2: |
| 21234 | // op: p |
| 21235 | return 28; |
| 21236 | case 0: |
| 21237 | // op: Rt |
| 21238 | return 12; |
| 21239 | case 1: |
| 21240 | // op: Sn |
| 21241 | return 7; |
| 21242 | } |
| 21243 | break; |
| 21244 | } |
| 21245 | case ARM::LDA: |
| 21246 | case ARM::LDAB: |
| 21247 | case ARM::LDAEX: |
| 21248 | case ARM::LDAEXB: |
| 21249 | case ARM::LDAEXD: |
| 21250 | case ARM::LDAEXH: |
| 21251 | case ARM::LDAH: |
| 21252 | case ARM::LDREX: |
| 21253 | case ARM::LDREXB: |
| 21254 | case ARM::LDREXD: |
| 21255 | case ARM::LDREXH: { |
| 21256 | switch (OpNum) { |
| 21257 | case 2: |
| 21258 | // op: p |
| 21259 | return 28; |
| 21260 | case 0: |
| 21261 | // op: Rt |
| 21262 | return 12; |
| 21263 | case 1: |
| 21264 | // op: addr |
| 21265 | return 16; |
| 21266 | } |
| 21267 | break; |
| 21268 | } |
| 21269 | case ARM::VMRS_FPSCR_NZCVQC: |
| 21270 | case ARM::VMRS_P0: { |
| 21271 | switch (OpNum) { |
| 21272 | case 2: |
| 21273 | // op: p |
| 21274 | return 28; |
| 21275 | case 0: |
| 21276 | // op: Rt |
| 21277 | return 12; |
| 21278 | } |
| 21279 | break; |
| 21280 | } |
| 21281 | case ARM::VCVTSD: |
| 21282 | case ARM::VJCVT: |
| 21283 | case ARM::VTOSIRD: |
| 21284 | case ARM::VTOSIZD: |
| 21285 | case ARM::VTOUIRD: |
| 21286 | case ARM::VTOUIZD: { |
| 21287 | switch (OpNum) { |
| 21288 | case 2: |
| 21289 | // op: p |
| 21290 | return 28; |
| 21291 | case 0: |
| 21292 | // op: Sd |
| 21293 | return 12; |
| 21294 | case 1: |
| 21295 | // op: Dm |
| 21296 | return 0; |
| 21297 | } |
| 21298 | break; |
| 21299 | } |
| 21300 | case ARM::VABSH: |
| 21301 | case ARM::VABSS: |
| 21302 | case ARM::VCMPEH: |
| 21303 | case ARM::VCMPES: |
| 21304 | case ARM::VCMPH: |
| 21305 | case ARM::VCMPS: |
| 21306 | case ARM::VCVTBHS: |
| 21307 | case ARM::VCVTTHS: |
| 21308 | case ARM::VMOVS: |
| 21309 | case ARM::VNEGH: |
| 21310 | case ARM::VNEGS: |
| 21311 | case ARM::VRINTRH: |
| 21312 | case ARM::VRINTRS: |
| 21313 | case ARM::VRINTXH: |
| 21314 | case ARM::VRINTXS: |
| 21315 | case ARM::VRINTZH: |
| 21316 | case ARM::VRINTZS: |
| 21317 | case ARM::VSITOH: |
| 21318 | case ARM::VSITOS: |
| 21319 | case ARM::VSQRTH: |
| 21320 | case ARM::VSQRTS: |
| 21321 | case ARM::VTOSIRH: |
| 21322 | case ARM::VTOSIRS: |
| 21323 | case ARM::VTOSIZH: |
| 21324 | case ARM::VTOSIZS: |
| 21325 | case ARM::VTOUIRH: |
| 21326 | case ARM::VTOUIRS: |
| 21327 | case ARM::VTOUIZH: |
| 21328 | case ARM::VTOUIZS: |
| 21329 | case ARM::VUITOH: |
| 21330 | case ARM::VUITOS: { |
| 21331 | switch (OpNum) { |
| 21332 | case 2: |
| 21333 | // op: p |
| 21334 | return 28; |
| 21335 | case 0: |
| 21336 | // op: Sd |
| 21337 | return 12; |
| 21338 | case 1: |
| 21339 | // op: Sm |
| 21340 | return 0; |
| 21341 | } |
| 21342 | break; |
| 21343 | } |
| 21344 | case ARM::FCONSTH: |
| 21345 | case ARM::FCONSTS: { |
| 21346 | switch (OpNum) { |
| 21347 | case 2: |
| 21348 | // op: p |
| 21349 | return 28; |
| 21350 | case 0: |
| 21351 | // op: Sd |
| 21352 | return 12; |
| 21353 | case 1: |
| 21354 | // op: imm |
| 21355 | return 0; |
| 21356 | } |
| 21357 | break; |
| 21358 | } |
| 21359 | case ARM::VMOVHR: |
| 21360 | case ARM::VMOVSR: { |
| 21361 | switch (OpNum) { |
| 21362 | case 2: |
| 21363 | // op: p |
| 21364 | return 28; |
| 21365 | case 0: |
| 21366 | // op: Sn |
| 21367 | return 7; |
| 21368 | case 1: |
| 21369 | // op: Rt |
| 21370 | return 12; |
| 21371 | } |
| 21372 | break; |
| 21373 | } |
| 21374 | case ARM::VLDR_FPCXTNS_off: |
| 21375 | case ARM::VLDR_FPCXTS_off: |
| 21376 | case ARM::VLDR_FPSCR_off: |
| 21377 | case ARM::VLDR_VPR_off: |
| 21378 | case ARM::VSTR_FPCXTNS_off: |
| 21379 | case ARM::VSTR_FPCXTS_off: |
| 21380 | case ARM::VSTR_FPSCR_off: |
| 21381 | case ARM::VSTR_VPR_off: { |
| 21382 | switch (OpNum) { |
| 21383 | case 2: |
| 21384 | // op: p |
| 21385 | return 28; |
| 21386 | case 0: |
| 21387 | // op: addr |
| 21388 | return 0; |
| 21389 | } |
| 21390 | break; |
| 21391 | } |
| 21392 | case ARM::MSRbanked: { |
| 21393 | switch (OpNum) { |
| 21394 | case 2: |
| 21395 | // op: p |
| 21396 | return 28; |
| 21397 | case 0: |
| 21398 | // op: banked |
| 21399 | return 8; |
| 21400 | case 1: |
| 21401 | // op: Rn |
| 21402 | return 0; |
| 21403 | } |
| 21404 | break; |
| 21405 | } |
| 21406 | case ARM::MSR: { |
| 21407 | switch (OpNum) { |
| 21408 | case 2: |
| 21409 | // op: p |
| 21410 | return 28; |
| 21411 | case 0: |
| 21412 | // op: mask |
| 21413 | return 16; |
| 21414 | case 1: |
| 21415 | // op: Rn |
| 21416 | return 0; |
| 21417 | } |
| 21418 | break; |
| 21419 | } |
| 21420 | case ARM::MSRi: { |
| 21421 | switch (OpNum) { |
| 21422 | case 2: |
| 21423 | // op: p |
| 21424 | return 28; |
| 21425 | case 0: |
| 21426 | // op: mask |
| 21427 | return 16; |
| 21428 | case 1: |
| 21429 | // op: imm |
| 21430 | return 0; |
| 21431 | } |
| 21432 | break; |
| 21433 | } |
| 21434 | case ARM::VLDMSDB_UPD: |
| 21435 | case ARM::VLDMSIA_UPD: |
| 21436 | case ARM::VSTMSDB_UPD: |
| 21437 | case ARM::VSTMSIA_UPD: { |
| 21438 | switch (OpNum) { |
| 21439 | case 2: |
| 21440 | // op: p |
| 21441 | return 28; |
| 21442 | case 1: |
| 21443 | // op: Rn |
| 21444 | return 16; |
| 21445 | case 4: |
| 21446 | // op: regs |
| 21447 | return 0; |
| 21448 | } |
| 21449 | break; |
| 21450 | } |
| 21451 | case ARM::FLDMXDB_UPD: |
| 21452 | case ARM::FLDMXIA_UPD: |
| 21453 | case ARM::FSTMXDB_UPD: |
| 21454 | case ARM::FSTMXIA_UPD: |
| 21455 | case ARM::VLDMDDB_UPD: |
| 21456 | case ARM::VLDMDIA_UPD: |
| 21457 | case ARM::VSTMDDB_UPD: |
| 21458 | case ARM::VSTMDIA_UPD: { |
| 21459 | switch (OpNum) { |
| 21460 | case 2: |
| 21461 | // op: p |
| 21462 | return 28; |
| 21463 | case 1: |
| 21464 | // op: Rn |
| 21465 | return 16; |
| 21466 | case 4: |
| 21467 | // op: regs |
| 21468 | return 1; |
| 21469 | } |
| 21470 | break; |
| 21471 | } |
| 21472 | case ARM::VMSR_FPSCR_NZCVQC: |
| 21473 | case ARM::VMSR_P0: { |
| 21474 | switch (OpNum) { |
| 21475 | case 2: |
| 21476 | // op: p |
| 21477 | return 28; |
| 21478 | case 1: |
| 21479 | // op: Rt |
| 21480 | return 12; |
| 21481 | } |
| 21482 | break; |
| 21483 | } |
| 21484 | case ARM::VCVTDS: { |
| 21485 | switch (OpNum) { |
| 21486 | case 2: |
| 21487 | // op: p |
| 21488 | return 28; |
| 21489 | case 1: |
| 21490 | // op: Sm |
| 21491 | return 0; |
| 21492 | case 0: |
| 21493 | // op: Dd |
| 21494 | return 12; |
| 21495 | } |
| 21496 | break; |
| 21497 | } |
| 21498 | case ARM::MRSbanked: { |
| 21499 | switch (OpNum) { |
| 21500 | case 2: |
| 21501 | // op: p |
| 21502 | return 28; |
| 21503 | case 1: |
| 21504 | // op: banked |
| 21505 | return 8; |
| 21506 | case 0: |
| 21507 | // op: Rd |
| 21508 | return 12; |
| 21509 | } |
| 21510 | break; |
| 21511 | } |
| 21512 | case ARM::LDMDA_UPD: |
| 21513 | case ARM::LDMDB_UPD: |
| 21514 | case ARM::LDMIA_UPD: |
| 21515 | case ARM::LDMIB_UPD: |
| 21516 | case ARM::STMDA_UPD: |
| 21517 | case ARM::STMDB_UPD: |
| 21518 | case ARM::STMIA_UPD: |
| 21519 | case ARM::STMIB_UPD: |
| 21520 | case ARM::sysLDMDA_UPD: |
| 21521 | case ARM::sysLDMDB_UPD: |
| 21522 | case ARM::sysLDMIA_UPD: |
| 21523 | case ARM::sysLDMIB_UPD: |
| 21524 | case ARM::sysSTMDA_UPD: |
| 21525 | case ARM::sysSTMDB_UPD: |
| 21526 | case ARM::sysSTMIA_UPD: |
| 21527 | case ARM::sysSTMIB_UPD: { |
| 21528 | switch (OpNum) { |
| 21529 | case 2: |
| 21530 | // op: p |
| 21531 | return 28; |
| 21532 | case 4: |
| 21533 | // op: regs |
| 21534 | return 0; |
| 21535 | case 1: |
| 21536 | // op: Rn |
| 21537 | return 16; |
| 21538 | } |
| 21539 | break; |
| 21540 | } |
| 21541 | case ARM::MOVr: |
| 21542 | case ARM::MOVr_TC: |
| 21543 | case ARM::MVNr: { |
| 21544 | switch (OpNum) { |
| 21545 | case 2: |
| 21546 | // op: p |
| 21547 | return 28; |
| 21548 | case 4: |
| 21549 | // op: s |
| 21550 | return 20; |
| 21551 | case 0: |
| 21552 | // op: Rd |
| 21553 | return 12; |
| 21554 | case 1: |
| 21555 | // op: Rm |
| 21556 | return 0; |
| 21557 | } |
| 21558 | break; |
| 21559 | } |
| 21560 | case ARM::MOVi: |
| 21561 | case ARM::MVNi: { |
| 21562 | switch (OpNum) { |
| 21563 | case 2: |
| 21564 | // op: p |
| 21565 | return 28; |
| 21566 | case 4: |
| 21567 | // op: s |
| 21568 | return 20; |
| 21569 | case 0: |
| 21570 | // op: Rd |
| 21571 | return 12; |
| 21572 | case 1: |
| 21573 | // op: imm |
| 21574 | return 0; |
| 21575 | } |
| 21576 | break; |
| 21577 | } |
| 21578 | case ARM::VSCCLRMS: |
| 21579 | case ARM::t2CLRM: |
| 21580 | case ARM::tPOP: |
| 21581 | case ARM::tPUSH: { |
| 21582 | switch (OpNum) { |
| 21583 | case 2: |
| 21584 | // op: regs |
| 21585 | return 0; |
| 21586 | } |
| 21587 | break; |
| 21588 | } |
| 21589 | case ARM::VSCCLRMD: { |
| 21590 | switch (OpNum) { |
| 21591 | case 2: |
| 21592 | // op: regs |
| 21593 | return 1; |
| 21594 | } |
| 21595 | break; |
| 21596 | } |
| 21597 | case ARM::MVE_VCMLAf16: |
| 21598 | case ARM::MVE_VCMLAf32: { |
| 21599 | switch (OpNum) { |
| 21600 | case 3: |
| 21601 | // op: Qm |
| 21602 | return 1; |
| 21603 | case 0: |
| 21604 | // op: Qd |
| 21605 | return 13; |
| 21606 | case 2: |
| 21607 | // op: Qn |
| 21608 | return 7; |
| 21609 | case 4: |
| 21610 | // op: rot |
| 21611 | return 23; |
| 21612 | } |
| 21613 | break; |
| 21614 | } |
| 21615 | case ARM::MVE_VFMAf16: |
| 21616 | case ARM::MVE_VFMAf32: |
| 21617 | case ARM::MVE_VFMSf16: |
| 21618 | case ARM::MVE_VFMSf32: { |
| 21619 | switch (OpNum) { |
| 21620 | case 3: |
| 21621 | // op: Qm |
| 21622 | return 1; |
| 21623 | case 0: |
| 21624 | // op: Qd |
| 21625 | return 13; |
| 21626 | case 2: |
| 21627 | // op: Qn |
| 21628 | return 7; |
| 21629 | } |
| 21630 | break; |
| 21631 | } |
| 21632 | case ARM::MVE_VABAVs16: |
| 21633 | case ARM::MVE_VABAVs32: |
| 21634 | case ARM::MVE_VABAVs8: |
| 21635 | case ARM::MVE_VABAVu16: |
| 21636 | case ARM::MVE_VABAVu32: |
| 21637 | case ARM::MVE_VABAVu8: { |
| 21638 | switch (OpNum) { |
| 21639 | case 3: |
| 21640 | // op: Qm |
| 21641 | return 1; |
| 21642 | case 2: |
| 21643 | // op: Qn |
| 21644 | return 7; |
| 21645 | case 0: |
| 21646 | // op: Rda |
| 21647 | return 12; |
| 21648 | } |
| 21649 | break; |
| 21650 | } |
| 21651 | case ARM::tADDrr: |
| 21652 | case ARM::tSUBrr: { |
| 21653 | switch (OpNum) { |
| 21654 | case 3: |
| 21655 | // op: Rm |
| 21656 | return 6; |
| 21657 | case 2: |
| 21658 | // op: Rn |
| 21659 | return 3; |
| 21660 | case 0: |
| 21661 | // op: Rd |
| 21662 | return 0; |
| 21663 | } |
| 21664 | break; |
| 21665 | } |
| 21666 | case ARM::VST1d16Qwb_fixed: |
| 21667 | case ARM::VST1d16Twb_fixed: |
| 21668 | case ARM::VST1d16wb_fixed: |
| 21669 | case ARM::VST1d32Qwb_fixed: |
| 21670 | case ARM::VST1d32Twb_fixed: |
| 21671 | case ARM::VST1d32wb_fixed: |
| 21672 | case ARM::VST1d64Qwb_fixed: |
| 21673 | case ARM::VST1d64Twb_fixed: |
| 21674 | case ARM::VST1d64wb_fixed: |
| 21675 | case ARM::VST1d8Qwb_fixed: |
| 21676 | case ARM::VST1d8Twb_fixed: |
| 21677 | case ARM::VST1d8wb_fixed: |
| 21678 | case ARM::VST1q16wb_fixed: |
| 21679 | case ARM::VST1q32wb_fixed: |
| 21680 | case ARM::VST1q64wb_fixed: |
| 21681 | case ARM::VST1q8wb_fixed: |
| 21682 | case ARM::VST2b16wb_fixed: |
| 21683 | case ARM::VST2b32wb_fixed: |
| 21684 | case ARM::VST2b8wb_fixed: |
| 21685 | case ARM::VST2d16wb_fixed: |
| 21686 | case ARM::VST2d32wb_fixed: |
| 21687 | case ARM::VST2d8wb_fixed: |
| 21688 | case ARM::VST2q16wb_fixed: |
| 21689 | case ARM::VST2q32wb_fixed: |
| 21690 | case ARM::VST2q8wb_fixed: { |
| 21691 | switch (OpNum) { |
| 21692 | case 3: |
| 21693 | // op: Vd |
| 21694 | return 12; |
| 21695 | case 1: |
| 21696 | // op: Rn |
| 21697 | return 4; |
| 21698 | } |
| 21699 | break; |
| 21700 | } |
| 21701 | case ARM::t2BFic: { |
| 21702 | switch (OpNum) { |
| 21703 | case 3: |
| 21704 | // op: bcond |
| 21705 | return 18; |
| 21706 | case 1: |
| 21707 | // op: label |
| 21708 | return 1; |
| 21709 | case 2: |
| 21710 | // op: ba_label |
| 21711 | return 17; |
| 21712 | case 0: |
| 21713 | // op: b_label |
| 21714 | return 23; |
| 21715 | } |
| 21716 | break; |
| 21717 | } |
| 21718 | case ARM::MVE_VPTv16s8: |
| 21719 | case ARM::MVE_VPTv4f32: |
| 21720 | case ARM::MVE_VPTv4s32: |
| 21721 | case ARM::MVE_VPTv8f16: |
| 21722 | case ARM::MVE_VPTv8s16: { |
| 21723 | switch (OpNum) { |
| 21724 | case 3: |
| 21725 | // op: fc |
| 21726 | return 0; |
| 21727 | case 0: |
| 21728 | // op: Mk |
| 21729 | return 13; |
| 21730 | case 1: |
| 21731 | // op: Qn |
| 21732 | return 17; |
| 21733 | case 2: |
| 21734 | // op: Qm |
| 21735 | return 1; |
| 21736 | } |
| 21737 | break; |
| 21738 | } |
| 21739 | case ARM::MVE_VCMPf16: |
| 21740 | case ARM::MVE_VCMPf32: |
| 21741 | case ARM::MVE_VCMPs16: |
| 21742 | case ARM::MVE_VCMPs32: |
| 21743 | case ARM::MVE_VCMPs8: { |
| 21744 | switch (OpNum) { |
| 21745 | case 3: |
| 21746 | // op: fc |
| 21747 | return 0; |
| 21748 | case 1: |
| 21749 | // op: Qn |
| 21750 | return 17; |
| 21751 | case 2: |
| 21752 | // op: Qm |
| 21753 | return 1; |
| 21754 | } |
| 21755 | break; |
| 21756 | } |
| 21757 | case ARM::MVE_VPTv16s8r: |
| 21758 | case ARM::MVE_VPTv4f32r: |
| 21759 | case ARM::MVE_VPTv4s32r: |
| 21760 | case ARM::MVE_VPTv8f16r: |
| 21761 | case ARM::MVE_VPTv8s16r: { |
| 21762 | switch (OpNum) { |
| 21763 | case 3: |
| 21764 | // op: fc |
| 21765 | return 5; |
| 21766 | case 0: |
| 21767 | // op: Mk |
| 21768 | return 13; |
| 21769 | case 1: |
| 21770 | // op: Qn |
| 21771 | return 17; |
| 21772 | case 2: |
| 21773 | // op: Rm |
| 21774 | return 0; |
| 21775 | } |
| 21776 | break; |
| 21777 | } |
| 21778 | case ARM::MVE_VCMPf16r: |
| 21779 | case ARM::MVE_VCMPf32r: |
| 21780 | case ARM::MVE_VCMPs16r: |
| 21781 | case ARM::MVE_VCMPs32r: |
| 21782 | case ARM::MVE_VCMPs8r: { |
| 21783 | switch (OpNum) { |
| 21784 | case 3: |
| 21785 | // op: fc |
| 21786 | return 5; |
| 21787 | case 1: |
| 21788 | // op: Qn |
| 21789 | return 17; |
| 21790 | case 2: |
| 21791 | // op: Rm |
| 21792 | return 0; |
| 21793 | } |
| 21794 | break; |
| 21795 | } |
| 21796 | case ARM::MVE_VPTv16i8: |
| 21797 | case ARM::MVE_VPTv16u8: |
| 21798 | case ARM::MVE_VPTv4i32: |
| 21799 | case ARM::MVE_VPTv4u32: |
| 21800 | case ARM::MVE_VPTv8i16: |
| 21801 | case ARM::MVE_VPTv8u16: { |
| 21802 | switch (OpNum) { |
| 21803 | case 3: |
| 21804 | // op: fc |
| 21805 | return 7; |
| 21806 | case 0: |
| 21807 | // op: Mk |
| 21808 | return 13; |
| 21809 | case 1: |
| 21810 | // op: Qn |
| 21811 | return 17; |
| 21812 | case 2: |
| 21813 | // op: Qm |
| 21814 | return 1; |
| 21815 | } |
| 21816 | break; |
| 21817 | } |
| 21818 | case ARM::MVE_VPTv16i8r: |
| 21819 | case ARM::MVE_VPTv16u8r: |
| 21820 | case ARM::MVE_VPTv4i32r: |
| 21821 | case ARM::MVE_VPTv4u32r: |
| 21822 | case ARM::MVE_VPTv8i16r: |
| 21823 | case ARM::MVE_VPTv8u16r: { |
| 21824 | switch (OpNum) { |
| 21825 | case 3: |
| 21826 | // op: fc |
| 21827 | return 7; |
| 21828 | case 0: |
| 21829 | // op: Mk |
| 21830 | return 13; |
| 21831 | case 1: |
| 21832 | // op: Qn |
| 21833 | return 17; |
| 21834 | case 2: |
| 21835 | // op: Rm |
| 21836 | return 0; |
| 21837 | } |
| 21838 | break; |
| 21839 | } |
| 21840 | case ARM::MVE_VCMPi16: |
| 21841 | case ARM::MVE_VCMPi32: |
| 21842 | case ARM::MVE_VCMPi8: |
| 21843 | case ARM::MVE_VCMPu16: |
| 21844 | case ARM::MVE_VCMPu32: |
| 21845 | case ARM::MVE_VCMPu8: { |
| 21846 | switch (OpNum) { |
| 21847 | case 3: |
| 21848 | // op: fc |
| 21849 | return 7; |
| 21850 | case 1: |
| 21851 | // op: Qn |
| 21852 | return 17; |
| 21853 | case 2: |
| 21854 | // op: Qm |
| 21855 | return 1; |
| 21856 | } |
| 21857 | break; |
| 21858 | } |
| 21859 | case ARM::MVE_VCMPi16r: |
| 21860 | case ARM::MVE_VCMPi32r: |
| 21861 | case ARM::MVE_VCMPi8r: |
| 21862 | case ARM::MVE_VCMPu16r: |
| 21863 | case ARM::MVE_VCMPu32r: |
| 21864 | case ARM::MVE_VCMPu8r: { |
| 21865 | switch (OpNum) { |
| 21866 | case 3: |
| 21867 | // op: fc |
| 21868 | return 7; |
| 21869 | case 1: |
| 21870 | // op: Qn |
| 21871 | return 17; |
| 21872 | case 2: |
| 21873 | // op: Rm |
| 21874 | return 0; |
| 21875 | } |
| 21876 | break; |
| 21877 | } |
| 21878 | case ARM::LDC2L_POST: |
| 21879 | case ARM::LDC2_POST: |
| 21880 | case ARM::STC2L_POST: |
| 21881 | case ARM::STC2_POST: |
| 21882 | case ARM::t2LDC2L_POST: |
| 21883 | case ARM::t2LDC2_POST: |
| 21884 | case ARM::t2LDCL_POST: |
| 21885 | case ARM::t2LDC_POST: |
| 21886 | case ARM::t2STC2L_POST: |
| 21887 | case ARM::t2STC2_POST: |
| 21888 | case ARM::t2STCL_POST: |
| 21889 | case ARM::t2STC_POST: { |
| 21890 | switch (OpNum) { |
| 21891 | case 3: |
| 21892 | // op: offset |
| 21893 | return 0; |
| 21894 | case 2: |
| 21895 | // op: addr |
| 21896 | return 16; |
| 21897 | case 0: |
| 21898 | // op: cop |
| 21899 | return 8; |
| 21900 | case 1: |
| 21901 | // op: CRd |
| 21902 | return 12; |
| 21903 | } |
| 21904 | break; |
| 21905 | } |
| 21906 | case ARM::LDC2L_OPTION: |
| 21907 | case ARM::LDC2_OPTION: |
| 21908 | case ARM::STC2L_OPTION: |
| 21909 | case ARM::STC2_OPTION: |
| 21910 | case ARM::t2LDC2L_OPTION: |
| 21911 | case ARM::t2LDC2_OPTION: |
| 21912 | case ARM::t2LDCL_OPTION: |
| 21913 | case ARM::t2LDC_OPTION: |
| 21914 | case ARM::t2STC2L_OPTION: |
| 21915 | case ARM::t2STC2_OPTION: |
| 21916 | case ARM::t2STCL_OPTION: |
| 21917 | case ARM::t2STC_OPTION: { |
| 21918 | switch (OpNum) { |
| 21919 | case 3: |
| 21920 | // op: option |
| 21921 | return 0; |
| 21922 | case 2: |
| 21923 | // op: addr |
| 21924 | return 16; |
| 21925 | case 0: |
| 21926 | // op: cop |
| 21927 | return 8; |
| 21928 | case 1: |
| 21929 | // op: CRd |
| 21930 | return 12; |
| 21931 | } |
| 21932 | break; |
| 21933 | } |
| 21934 | case ARM::VADDD: |
| 21935 | case ARM::VDIVD: |
| 21936 | case ARM::VMULD: |
| 21937 | case ARM::VNMULD: |
| 21938 | case ARM::VSUBD: { |
| 21939 | switch (OpNum) { |
| 21940 | case 3: |
| 21941 | // op: p |
| 21942 | return 28; |
| 21943 | case 0: |
| 21944 | // op: Dd |
| 21945 | return 12; |
| 21946 | case 1: |
| 21947 | // op: Dn |
| 21948 | return 7; |
| 21949 | case 2: |
| 21950 | // op: Dm |
| 21951 | return 0; |
| 21952 | } |
| 21953 | break; |
| 21954 | } |
| 21955 | case ARM::VLDRD: |
| 21956 | case ARM::VSTRD: { |
| 21957 | switch (OpNum) { |
| 21958 | case 3: |
| 21959 | // op: p |
| 21960 | return 28; |
| 21961 | case 0: |
| 21962 | // op: Dd |
| 21963 | return 12; |
| 21964 | case 1: |
| 21965 | // op: addr |
| 21966 | return 0; |
| 21967 | } |
| 21968 | break; |
| 21969 | } |
| 21970 | case ARM::VMOVDRR: { |
| 21971 | switch (OpNum) { |
| 21972 | case 3: |
| 21973 | // op: p |
| 21974 | return 28; |
| 21975 | case 0: |
| 21976 | // op: Dm |
| 21977 | return 0; |
| 21978 | case 1: |
| 21979 | // op: Rt |
| 21980 | return 12; |
| 21981 | case 2: |
| 21982 | // op: Rt2 |
| 21983 | return 16; |
| 21984 | } |
| 21985 | break; |
| 21986 | } |
| 21987 | case ARM::SXTB: |
| 21988 | case ARM::SXTB16: |
| 21989 | case ARM::SXTH: |
| 21990 | case ARM::UXTB: |
| 21991 | case ARM::UXTB16: |
| 21992 | case ARM::UXTH: { |
| 21993 | switch (OpNum) { |
| 21994 | case 3: |
| 21995 | // op: p |
| 21996 | return 28; |
| 21997 | case 0: |
| 21998 | // op: Rd |
| 21999 | return 12; |
| 22000 | case 1: |
| 22001 | // op: Rm |
| 22002 | return 0; |
| 22003 | case 2: |
| 22004 | // op: rot |
| 22005 | return 10; |
| 22006 | } |
| 22007 | break; |
| 22008 | } |
| 22009 | case ARM::SEL: { |
| 22010 | switch (OpNum) { |
| 22011 | case 3: |
| 22012 | // op: p |
| 22013 | return 28; |
| 22014 | case 0: |
| 22015 | // op: Rd |
| 22016 | return 12; |
| 22017 | case 1: |
| 22018 | // op: Rn |
| 22019 | return 16; |
| 22020 | case 2: |
| 22021 | // op: Rm |
| 22022 | return 0; |
| 22023 | } |
| 22024 | break; |
| 22025 | } |
| 22026 | case ARM::SSAT16: |
| 22027 | case ARM::USAT16: { |
| 22028 | switch (OpNum) { |
| 22029 | case 3: |
| 22030 | // op: p |
| 22031 | return 28; |
| 22032 | case 0: |
| 22033 | // op: Rd |
| 22034 | return 12; |
| 22035 | case 1: |
| 22036 | // op: sat_imm |
| 22037 | return 16; |
| 22038 | case 2: |
| 22039 | // op: Rn |
| 22040 | return 0; |
| 22041 | } |
| 22042 | break; |
| 22043 | } |
| 22044 | case ARM::MOVTi16: { |
| 22045 | switch (OpNum) { |
| 22046 | case 3: |
| 22047 | // op: p |
| 22048 | return 28; |
| 22049 | case 0: |
| 22050 | // op: Rd |
| 22051 | return 12; |
| 22052 | case 2: |
| 22053 | // op: imm |
| 22054 | return 0; |
| 22055 | } |
| 22056 | break; |
| 22057 | } |
| 22058 | case ARM::BFC: { |
| 22059 | switch (OpNum) { |
| 22060 | case 3: |
| 22061 | // op: p |
| 22062 | return 28; |
| 22063 | case 0: |
| 22064 | // op: Rd |
| 22065 | return 12; |
| 22066 | case 2: |
| 22067 | // op: imm |
| 22068 | return 7; |
| 22069 | } |
| 22070 | break; |
| 22071 | } |
| 22072 | case ARM::SDIV: |
| 22073 | case ARM::SMMUL: |
| 22074 | case ARM::SMMULR: |
| 22075 | case ARM::UDIV: |
| 22076 | case ARM::USAD8: { |
| 22077 | switch (OpNum) { |
| 22078 | case 3: |
| 22079 | // op: p |
| 22080 | return 28; |
| 22081 | case 0: |
| 22082 | // op: Rd |
| 22083 | return 16; |
| 22084 | case 1: |
| 22085 | // op: Rn |
| 22086 | return 0; |
| 22087 | case 2: |
| 22088 | // op: Rm |
| 22089 | return 8; |
| 22090 | } |
| 22091 | break; |
| 22092 | } |
| 22093 | case ARM::CMNzrsi: |
| 22094 | case ARM::CMPrsi: |
| 22095 | case ARM::TEQrsi: |
| 22096 | case ARM::TSTrsi: { |
| 22097 | switch (OpNum) { |
| 22098 | case 3: |
| 22099 | // op: p |
| 22100 | return 28; |
| 22101 | case 0: |
| 22102 | // op: Rn |
| 22103 | return 16; |
| 22104 | case 1: |
| 22105 | // op: shift |
| 22106 | return 0; |
| 22107 | } |
| 22108 | break; |
| 22109 | } |
| 22110 | case ARM::SWP: |
| 22111 | case ARM::SWPB: { |
| 22112 | switch (OpNum) { |
| 22113 | case 3: |
| 22114 | // op: p |
| 22115 | return 28; |
| 22116 | case 0: |
| 22117 | // op: Rt |
| 22118 | return 12; |
| 22119 | case 1: |
| 22120 | // op: Rt2 |
| 22121 | return 0; |
| 22122 | case 2: |
| 22123 | // op: addr |
| 22124 | return 16; |
| 22125 | } |
| 22126 | break; |
| 22127 | } |
| 22128 | case ARM::LDRBi12: |
| 22129 | case ARM::LDRcp: |
| 22130 | case ARM::LDRi12: |
| 22131 | case ARM::STRBi12: |
| 22132 | case ARM::STRi12: { |
| 22133 | switch (OpNum) { |
| 22134 | case 3: |
| 22135 | // op: p |
| 22136 | return 28; |
| 22137 | case 0: |
| 22138 | // op: Rt |
| 22139 | return 12; |
| 22140 | case 1: |
| 22141 | // op: addr |
| 22142 | return 0; |
| 22143 | } |
| 22144 | break; |
| 22145 | } |
| 22146 | case ARM::VADDH: |
| 22147 | case ARM::VADDS: |
| 22148 | case ARM::VDIVH: |
| 22149 | case ARM::VDIVS: |
| 22150 | case ARM::VMULH: |
| 22151 | case ARM::VMULS: |
| 22152 | case ARM::VNMULH: |
| 22153 | case ARM::VNMULS: |
| 22154 | case ARM::VSUBH: |
| 22155 | case ARM::VSUBS: { |
| 22156 | switch (OpNum) { |
| 22157 | case 3: |
| 22158 | // op: p |
| 22159 | return 28; |
| 22160 | case 0: |
| 22161 | // op: Sd |
| 22162 | return 12; |
| 22163 | case 1: |
| 22164 | // op: Sn |
| 22165 | return 7; |
| 22166 | case 2: |
| 22167 | // op: Sm |
| 22168 | return 0; |
| 22169 | } |
| 22170 | break; |
| 22171 | } |
| 22172 | case ARM::VLDRH: |
| 22173 | case ARM::VLDRS: |
| 22174 | case ARM::VSTRH: |
| 22175 | case ARM::VSTRS: { |
| 22176 | switch (OpNum) { |
| 22177 | case 3: |
| 22178 | // op: p |
| 22179 | return 28; |
| 22180 | case 0: |
| 22181 | // op: Sd |
| 22182 | return 12; |
| 22183 | case 1: |
| 22184 | // op: addr |
| 22185 | return 0; |
| 22186 | } |
| 22187 | break; |
| 22188 | } |
| 22189 | case ARM::BF16_VCVTB: |
| 22190 | case ARM::BF16_VCVTT: |
| 22191 | case ARM::VCVTBSH: |
| 22192 | case ARM::VCVTTSH: { |
| 22193 | switch (OpNum) { |
| 22194 | case 3: |
| 22195 | // op: p |
| 22196 | return 28; |
| 22197 | case 0: |
| 22198 | // op: Sd |
| 22199 | return 12; |
| 22200 | case 2: |
| 22201 | // op: Sm |
| 22202 | return 0; |
| 22203 | } |
| 22204 | break; |
| 22205 | } |
| 22206 | case ARM::SMUAD: |
| 22207 | case ARM::SMUADX: |
| 22208 | case ARM::SMULBB: |
| 22209 | case ARM::SMULBT: |
| 22210 | case ARM::SMULTB: |
| 22211 | case ARM::SMULTT: |
| 22212 | case ARM::SMULWB: |
| 22213 | case ARM::SMULWT: |
| 22214 | case ARM::SMUSD: |
| 22215 | case ARM::SMUSDX: { |
| 22216 | switch (OpNum) { |
| 22217 | case 3: |
| 22218 | // op: p |
| 22219 | return 28; |
| 22220 | case 1: |
| 22221 | // op: Rn |
| 22222 | return 0; |
| 22223 | case 2: |
| 22224 | // op: Rm |
| 22225 | return 8; |
| 22226 | case 0: |
| 22227 | // op: Rd |
| 22228 | return 16; |
| 22229 | } |
| 22230 | break; |
| 22231 | } |
| 22232 | case ARM::QADD16: |
| 22233 | case ARM::QADD8: |
| 22234 | case ARM::QASX: |
| 22235 | case ARM::QSAX: |
| 22236 | case ARM::QSUB16: |
| 22237 | case ARM::QSUB8: |
| 22238 | case ARM::SADD16: |
| 22239 | case ARM::SADD8: |
| 22240 | case ARM::SASX: |
| 22241 | case ARM::SHADD16: |
| 22242 | case ARM::SHADD8: |
| 22243 | case ARM::SHASX: |
| 22244 | case ARM::SHSAX: |
| 22245 | case ARM::SHSUB16: |
| 22246 | case ARM::SHSUB8: |
| 22247 | case ARM::SSAX: |
| 22248 | case ARM::SSUB16: |
| 22249 | case ARM::SSUB8: |
| 22250 | case ARM::UADD16: |
| 22251 | case ARM::UADD8: |
| 22252 | case ARM::UASX: |
| 22253 | case ARM::UHADD16: |
| 22254 | case ARM::UHADD8: |
| 22255 | case ARM::UHASX: |
| 22256 | case ARM::UHSAX: |
| 22257 | case ARM::UHSUB16: |
| 22258 | case ARM::UHSUB8: |
| 22259 | case ARM::UQADD16: |
| 22260 | case ARM::UQADD8: |
| 22261 | case ARM::UQASX: |
| 22262 | case ARM::UQSAX: |
| 22263 | case ARM::UQSUB16: |
| 22264 | case ARM::UQSUB8: |
| 22265 | case ARM::USAX: |
| 22266 | case ARM::USUB16: |
| 22267 | case ARM::USUB8: { |
| 22268 | switch (OpNum) { |
| 22269 | case 3: |
| 22270 | // op: p |
| 22271 | return 28; |
| 22272 | case 1: |
| 22273 | // op: Rn |
| 22274 | return 16; |
| 22275 | case 0: |
| 22276 | // op: Rd |
| 22277 | return 12; |
| 22278 | case 2: |
| 22279 | // op: Rm |
| 22280 | return 0; |
| 22281 | } |
| 22282 | break; |
| 22283 | } |
| 22284 | case ARM::STLEX: |
| 22285 | case ARM::STLEXB: |
| 22286 | case ARM::STLEXD: |
| 22287 | case ARM::STLEXH: |
| 22288 | case ARM::STREX: |
| 22289 | case ARM::STREXB: |
| 22290 | case ARM::STREXD: |
| 22291 | case ARM::STREXH: { |
| 22292 | switch (OpNum) { |
| 22293 | case 3: |
| 22294 | // op: p |
| 22295 | return 28; |
| 22296 | case 1: |
| 22297 | // op: Rt |
| 22298 | return 0; |
| 22299 | case 2: |
| 22300 | // op: addr |
| 22301 | return 16; |
| 22302 | case 0: |
| 22303 | // op: Rd |
| 22304 | return 12; |
| 22305 | } |
| 22306 | break; |
| 22307 | } |
| 22308 | case ARM::VLDR_FPCXTNS_pre: |
| 22309 | case ARM::VLDR_FPCXTS_pre: |
| 22310 | case ARM::VLDR_FPSCR_NZCVQC_off: |
| 22311 | case ARM::VLDR_FPSCR_pre: |
| 22312 | case ARM::VLDR_P0_off: |
| 22313 | case ARM::VLDR_VPR_pre: |
| 22314 | case ARM::VSTR_FPCXTNS_pre: |
| 22315 | case ARM::VSTR_FPCXTS_pre: |
| 22316 | case ARM::VSTR_FPSCR_NZCVQC_off: |
| 22317 | case ARM::VSTR_FPSCR_pre: |
| 22318 | case ARM::VSTR_P0_off: |
| 22319 | case ARM::VSTR_VPR_pre: { |
| 22320 | switch (OpNum) { |
| 22321 | case 3: |
| 22322 | // op: p |
| 22323 | return 28; |
| 22324 | case 1: |
| 22325 | // op: addr |
| 22326 | return 0; |
| 22327 | } |
| 22328 | break; |
| 22329 | } |
| 22330 | case ARM::VMOVRRD: { |
| 22331 | switch (OpNum) { |
| 22332 | case 3: |
| 22333 | // op: p |
| 22334 | return 28; |
| 22335 | case 2: |
| 22336 | // op: Dm |
| 22337 | return 0; |
| 22338 | case 0: |
| 22339 | // op: Rt |
| 22340 | return 12; |
| 22341 | case 1: |
| 22342 | // op: Rt2 |
| 22343 | return 16; |
| 22344 | } |
| 22345 | break; |
| 22346 | } |
| 22347 | case ARM::VCVTBDH: |
| 22348 | case ARM::VCVTTDH: { |
| 22349 | switch (OpNum) { |
| 22350 | case 3: |
| 22351 | // op: p |
| 22352 | return 28; |
| 22353 | case 2: |
| 22354 | // op: Dm |
| 22355 | return 0; |
| 22356 | case 0: |
| 22357 | // op: Sd |
| 22358 | return 12; |
| 22359 | } |
| 22360 | break; |
| 22361 | } |
| 22362 | case ARM::QADD: |
| 22363 | case ARM::QDADD: |
| 22364 | case ARM::QDSUB: |
| 22365 | case ARM::QSUB: { |
| 22366 | switch (OpNum) { |
| 22367 | case 3: |
| 22368 | // op: p |
| 22369 | return 28; |
| 22370 | case 2: |
| 22371 | // op: Rn |
| 22372 | return 16; |
| 22373 | case 0: |
| 22374 | // op: Rd |
| 22375 | return 12; |
| 22376 | case 1: |
| 22377 | // op: Rm |
| 22378 | return 0; |
| 22379 | } |
| 22380 | break; |
| 22381 | } |
| 22382 | case ARM::VLDR_FPCXTNS_post: |
| 22383 | case ARM::VLDR_FPCXTS_post: |
| 22384 | case ARM::VLDR_FPSCR_post: |
| 22385 | case ARM::VLDR_VPR_post: |
| 22386 | case ARM::VSTR_FPCXTNS_post: |
| 22387 | case ARM::VSTR_FPCXTS_post: |
| 22388 | case ARM::VSTR_FPSCR_post: |
| 22389 | case ARM::VSTR_VPR_post: { |
| 22390 | switch (OpNum) { |
| 22391 | case 3: |
| 22392 | // op: p |
| 22393 | return 28; |
| 22394 | case 2: |
| 22395 | // op: addr |
| 22396 | return 0; |
| 22397 | case 1: |
| 22398 | // op: Rn |
| 22399 | return 16; |
| 22400 | } |
| 22401 | break; |
| 22402 | } |
| 22403 | case ARM::VSHTOD: |
| 22404 | case ARM::VSHTOH: |
| 22405 | case ARM::VSHTOS: |
| 22406 | case ARM::VSLTOD: |
| 22407 | case ARM::VSLTOH: |
| 22408 | case ARM::VSLTOS: |
| 22409 | case ARM::VTOSHD: |
| 22410 | case ARM::VTOSHH: |
| 22411 | case ARM::VTOSHS: |
| 22412 | case ARM::VTOSLD: |
| 22413 | case ARM::VTOSLH: |
| 22414 | case ARM::VTOSLS: |
| 22415 | case ARM::VTOUHD: |
| 22416 | case ARM::VTOUHH: |
| 22417 | case ARM::VTOUHS: |
| 22418 | case ARM::VTOULD: |
| 22419 | case ARM::VTOULH: |
| 22420 | case ARM::VTOULS: |
| 22421 | case ARM::VUHTOD: |
| 22422 | case ARM::VUHTOH: |
| 22423 | case ARM::VUHTOS: |
| 22424 | case ARM::VULTOD: |
| 22425 | case ARM::VULTOH: |
| 22426 | case ARM::VULTOS: { |
| 22427 | switch (OpNum) { |
| 22428 | case 3: |
| 22429 | // op: p |
| 22430 | return 28; |
| 22431 | case 2: |
| 22432 | // op: fbits |
| 22433 | return 0; |
| 22434 | case 0: |
| 22435 | // op: dst |
| 22436 | return 12; |
| 22437 | } |
| 22438 | break; |
| 22439 | } |
| 22440 | case ARM::ADCrr: |
| 22441 | case ARM::ADDrr: |
| 22442 | case ARM::ANDrr: |
| 22443 | case ARM::BICrr: |
| 22444 | case ARM::EORrr: |
| 22445 | case ARM::ORRrr: |
| 22446 | case ARM::RSBrr: |
| 22447 | case ARM::RSCrr: |
| 22448 | case ARM::SBCrr: |
| 22449 | case ARM::SUBrr: { |
| 22450 | switch (OpNum) { |
| 22451 | case 3: |
| 22452 | // op: p |
| 22453 | return 28; |
| 22454 | case 5: |
| 22455 | // op: s |
| 22456 | return 20; |
| 22457 | case 0: |
| 22458 | // op: Rd |
| 22459 | return 12; |
| 22460 | case 1: |
| 22461 | // op: Rn |
| 22462 | return 16; |
| 22463 | case 2: |
| 22464 | // op: Rm |
| 22465 | return 0; |
| 22466 | } |
| 22467 | break; |
| 22468 | } |
| 22469 | case ARM::ADCri: |
| 22470 | case ARM::ADDri: |
| 22471 | case ARM::ANDri: |
| 22472 | case ARM::BICri: |
| 22473 | case ARM::EORri: |
| 22474 | case ARM::ORRri: |
| 22475 | case ARM::RSBri: |
| 22476 | case ARM::RSCri: |
| 22477 | case ARM::SBCri: |
| 22478 | case ARM::SUBri: { |
| 22479 | switch (OpNum) { |
| 22480 | case 3: |
| 22481 | // op: p |
| 22482 | return 28; |
| 22483 | case 5: |
| 22484 | // op: s |
| 22485 | return 20; |
| 22486 | case 0: |
| 22487 | // op: Rd |
| 22488 | return 12; |
| 22489 | case 1: |
| 22490 | // op: Rn |
| 22491 | return 16; |
| 22492 | case 2: |
| 22493 | // op: imm |
| 22494 | return 0; |
| 22495 | } |
| 22496 | break; |
| 22497 | } |
| 22498 | case ARM::MVNsi: { |
| 22499 | switch (OpNum) { |
| 22500 | case 3: |
| 22501 | // op: p |
| 22502 | return 28; |
| 22503 | case 5: |
| 22504 | // op: s |
| 22505 | return 20; |
| 22506 | case 0: |
| 22507 | // op: Rd |
| 22508 | return 12; |
| 22509 | case 1: |
| 22510 | // op: shift |
| 22511 | return 0; |
| 22512 | } |
| 22513 | break; |
| 22514 | } |
| 22515 | case ARM::MOVsi: { |
| 22516 | switch (OpNum) { |
| 22517 | case 3: |
| 22518 | // op: p |
| 22519 | return 28; |
| 22520 | case 5: |
| 22521 | // op: s |
| 22522 | return 20; |
| 22523 | case 0: |
| 22524 | // op: Rd |
| 22525 | return 12; |
| 22526 | case 1: |
| 22527 | // op: src |
| 22528 | return 0; |
| 22529 | } |
| 22530 | break; |
| 22531 | } |
| 22532 | case ARM::MUL: { |
| 22533 | switch (OpNum) { |
| 22534 | case 3: |
| 22535 | // op: p |
| 22536 | return 28; |
| 22537 | case 5: |
| 22538 | // op: s |
| 22539 | return 20; |
| 22540 | case 0: |
| 22541 | // op: Rd |
| 22542 | return 16; |
| 22543 | case 2: |
| 22544 | // op: Rm |
| 22545 | return 8; |
| 22546 | case 1: |
| 22547 | // op: Rn |
| 22548 | return 0; |
| 22549 | } |
| 22550 | break; |
| 22551 | } |
| 22552 | case ARM::MVE_VADDLVs32acc: |
| 22553 | case ARM::MVE_VADDLVu32acc: { |
| 22554 | switch (OpNum) { |
| 22555 | case 4: |
| 22556 | // op: Qm |
| 22557 | return 1; |
| 22558 | case 0: |
| 22559 | // op: RdaLo |
| 22560 | return 13; |
| 22561 | case 1: |
| 22562 | // op: RdaHi |
| 22563 | return 20; |
| 22564 | } |
| 22565 | break; |
| 22566 | } |
| 22567 | case ARM::VST1LNd8_UPD: { |
| 22568 | switch (OpNum) { |
| 22569 | case 4: |
| 22570 | // op: Vd |
| 22571 | return 12; |
| 22572 | case 1: |
| 22573 | // op: Rn |
| 22574 | return 16; |
| 22575 | case 3: |
| 22576 | // op: Rm |
| 22577 | return 0; |
| 22578 | case 5: |
| 22579 | // op: lane |
| 22580 | return 5; |
| 22581 | } |
| 22582 | break; |
| 22583 | } |
| 22584 | case ARM::VST3LNd8_UPD: { |
| 22585 | switch (OpNum) { |
| 22586 | case 4: |
| 22587 | // op: Vd |
| 22588 | return 12; |
| 22589 | case 1: |
| 22590 | // op: Rn |
| 22591 | return 16; |
| 22592 | case 3: |
| 22593 | // op: Rm |
| 22594 | return 0; |
| 22595 | case 7: |
| 22596 | // op: lane |
| 22597 | return 5; |
| 22598 | } |
| 22599 | break; |
| 22600 | } |
| 22601 | case ARM::VST3LNd16_UPD: |
| 22602 | case ARM::VST3LNq16_UPD: { |
| 22603 | switch (OpNum) { |
| 22604 | case 4: |
| 22605 | // op: Vd |
| 22606 | return 12; |
| 22607 | case 1: |
| 22608 | // op: Rn |
| 22609 | return 16; |
| 22610 | case 3: |
| 22611 | // op: Rm |
| 22612 | return 0; |
| 22613 | case 7: |
| 22614 | // op: lane |
| 22615 | return 6; |
| 22616 | } |
| 22617 | break; |
| 22618 | } |
| 22619 | case ARM::VST3LNd32_UPD: |
| 22620 | case ARM::VST3LNq32_UPD: { |
| 22621 | switch (OpNum) { |
| 22622 | case 4: |
| 22623 | // op: Vd |
| 22624 | return 12; |
| 22625 | case 1: |
| 22626 | // op: Rn |
| 22627 | return 16; |
| 22628 | case 3: |
| 22629 | // op: Rm |
| 22630 | return 0; |
| 22631 | case 7: |
| 22632 | // op: lane |
| 22633 | return 7; |
| 22634 | } |
| 22635 | break; |
| 22636 | } |
| 22637 | case ARM::VST1LNd16_UPD: { |
| 22638 | switch (OpNum) { |
| 22639 | case 4: |
| 22640 | // op: Vd |
| 22641 | return 12; |
| 22642 | case 1: |
| 22643 | // op: Rn |
| 22644 | return 4; |
| 22645 | case 3: |
| 22646 | // op: Rm |
| 22647 | return 0; |
| 22648 | case 5: |
| 22649 | // op: lane |
| 22650 | return 6; |
| 22651 | } |
| 22652 | break; |
| 22653 | } |
| 22654 | case ARM::VST1LNd32_UPD: { |
| 22655 | switch (OpNum) { |
| 22656 | case 4: |
| 22657 | // op: Vd |
| 22658 | return 12; |
| 22659 | case 1: |
| 22660 | // op: Rn |
| 22661 | return 4; |
| 22662 | case 3: |
| 22663 | // op: Rm |
| 22664 | return 0; |
| 22665 | case 5: |
| 22666 | // op: lane |
| 22667 | return 7; |
| 22668 | } |
| 22669 | break; |
| 22670 | } |
| 22671 | case ARM::VST2LNd8_UPD: { |
| 22672 | switch (OpNum) { |
| 22673 | case 4: |
| 22674 | // op: Vd |
| 22675 | return 12; |
| 22676 | case 1: |
| 22677 | // op: Rn |
| 22678 | return 4; |
| 22679 | case 3: |
| 22680 | // op: Rm |
| 22681 | return 0; |
| 22682 | case 6: |
| 22683 | // op: lane |
| 22684 | return 5; |
| 22685 | } |
| 22686 | break; |
| 22687 | } |
| 22688 | case ARM::VST2LNd16_UPD: |
| 22689 | case ARM::VST2LNq16_UPD: { |
| 22690 | switch (OpNum) { |
| 22691 | case 4: |
| 22692 | // op: Vd |
| 22693 | return 12; |
| 22694 | case 1: |
| 22695 | // op: Rn |
| 22696 | return 4; |
| 22697 | case 3: |
| 22698 | // op: Rm |
| 22699 | return 0; |
| 22700 | case 6: |
| 22701 | // op: lane |
| 22702 | return 6; |
| 22703 | } |
| 22704 | break; |
| 22705 | } |
| 22706 | case ARM::VST2LNd32_UPD: |
| 22707 | case ARM::VST2LNq32_UPD: { |
| 22708 | switch (OpNum) { |
| 22709 | case 4: |
| 22710 | // op: Vd |
| 22711 | return 12; |
| 22712 | case 1: |
| 22713 | // op: Rn |
| 22714 | return 4; |
| 22715 | case 3: |
| 22716 | // op: Rm |
| 22717 | return 0; |
| 22718 | case 6: |
| 22719 | // op: lane |
| 22720 | return 7; |
| 22721 | } |
| 22722 | break; |
| 22723 | } |
| 22724 | case ARM::VST4LNd8_UPD: { |
| 22725 | switch (OpNum) { |
| 22726 | case 4: |
| 22727 | // op: Vd |
| 22728 | return 12; |
| 22729 | case 1: |
| 22730 | // op: Rn |
| 22731 | return 4; |
| 22732 | case 3: |
| 22733 | // op: Rm |
| 22734 | return 0; |
| 22735 | case 8: |
| 22736 | // op: lane |
| 22737 | return 5; |
| 22738 | } |
| 22739 | break; |
| 22740 | } |
| 22741 | case ARM::VST4LNd16_UPD: |
| 22742 | case ARM::VST4LNq16_UPD: { |
| 22743 | switch (OpNum) { |
| 22744 | case 4: |
| 22745 | // op: Vd |
| 22746 | return 12; |
| 22747 | case 1: |
| 22748 | // op: Rn |
| 22749 | return 4; |
| 22750 | case 3: |
| 22751 | // op: Rm |
| 22752 | return 0; |
| 22753 | case 8: |
| 22754 | // op: lane |
| 22755 | return 6; |
| 22756 | } |
| 22757 | break; |
| 22758 | } |
| 22759 | case ARM::VST4LNd32_UPD: |
| 22760 | case ARM::VST4LNq32_UPD: { |
| 22761 | switch (OpNum) { |
| 22762 | case 4: |
| 22763 | // op: Vd |
| 22764 | return 12; |
| 22765 | case 1: |
| 22766 | // op: Rn |
| 22767 | return 4; |
| 22768 | case 3: |
| 22769 | // op: Rm |
| 22770 | return 0; |
| 22771 | case 8: |
| 22772 | // op: lane |
| 22773 | return 7; |
| 22774 | } |
| 22775 | break; |
| 22776 | } |
| 22777 | case ARM::VST1d16Qwb_register: |
| 22778 | case ARM::VST1d16Twb_register: |
| 22779 | case ARM::VST1d16wb_register: |
| 22780 | case ARM::VST1d32Qwb_register: |
| 22781 | case ARM::VST1d32Twb_register: |
| 22782 | case ARM::VST1d32wb_register: |
| 22783 | case ARM::VST1d64Qwb_register: |
| 22784 | case ARM::VST1d64Twb_register: |
| 22785 | case ARM::VST1d64wb_register: |
| 22786 | case ARM::VST1d8Qwb_register: |
| 22787 | case ARM::VST1d8Twb_register: |
| 22788 | case ARM::VST1d8wb_register: |
| 22789 | case ARM::VST1q16wb_register: |
| 22790 | case ARM::VST1q32wb_register: |
| 22791 | case ARM::VST1q64wb_register: |
| 22792 | case ARM::VST1q8wb_register: |
| 22793 | case ARM::VST2b16wb_register: |
| 22794 | case ARM::VST2b32wb_register: |
| 22795 | case ARM::VST2b8wb_register: |
| 22796 | case ARM::VST2d16wb_register: |
| 22797 | case ARM::VST2d32wb_register: |
| 22798 | case ARM::VST2d8wb_register: |
| 22799 | case ARM::VST2q16wb_register: |
| 22800 | case ARM::VST2q32wb_register: |
| 22801 | case ARM::VST2q8wb_register: |
| 22802 | case ARM::VST3d16_UPD: |
| 22803 | case ARM::VST3d32_UPD: |
| 22804 | case ARM::VST3d8_UPD: |
| 22805 | case ARM::VST3q16_UPD: |
| 22806 | case ARM::VST3q32_UPD: |
| 22807 | case ARM::VST3q8_UPD: |
| 22808 | case ARM::VST4d16_UPD: |
| 22809 | case ARM::VST4d32_UPD: |
| 22810 | case ARM::VST4d8_UPD: |
| 22811 | case ARM::VST4q16_UPD: |
| 22812 | case ARM::VST4q32_UPD: |
| 22813 | case ARM::VST4q8_UPD: { |
| 22814 | switch (OpNum) { |
| 22815 | case 4: |
| 22816 | // op: Vd |
| 22817 | return 12; |
| 22818 | case 1: |
| 22819 | // op: Rn |
| 22820 | return 4; |
| 22821 | case 3: |
| 22822 | // op: Rm |
| 22823 | return 0; |
| 22824 | } |
| 22825 | break; |
| 22826 | } |
| 22827 | case ARM::MVE_VSHLC: { |
| 22828 | switch (OpNum) { |
| 22829 | case 4: |
| 22830 | // op: imm |
| 22831 | return 16; |
| 22832 | case 1: |
| 22833 | // op: Qd |
| 22834 | return 13; |
| 22835 | case 0: |
| 22836 | // op: RdmDest |
| 22837 | return 0; |
| 22838 | } |
| 22839 | break; |
| 22840 | } |
| 22841 | case ARM::VFMAD: |
| 22842 | case ARM::VFMSD: |
| 22843 | case ARM::VFNMAD: |
| 22844 | case ARM::VFNMSD: |
| 22845 | case ARM::VMLAD: |
| 22846 | case ARM::VMLSD: |
| 22847 | case ARM::VNMLAD: |
| 22848 | case ARM::VNMLSD: { |
| 22849 | switch (OpNum) { |
| 22850 | case 4: |
| 22851 | // op: p |
| 22852 | return 28; |
| 22853 | case 0: |
| 22854 | // op: Dd |
| 22855 | return 12; |
| 22856 | case 2: |
| 22857 | // op: Dn |
| 22858 | return 7; |
| 22859 | case 3: |
| 22860 | // op: Dm |
| 22861 | return 0; |
| 22862 | } |
| 22863 | break; |
| 22864 | } |
| 22865 | case ARM::SBFX: |
| 22866 | case ARM::UBFX: { |
| 22867 | switch (OpNum) { |
| 22868 | case 4: |
| 22869 | // op: p |
| 22870 | return 28; |
| 22871 | case 0: |
| 22872 | // op: Rd |
| 22873 | return 12; |
| 22874 | case 1: |
| 22875 | // op: Rn |
| 22876 | return 0; |
| 22877 | case 2: |
| 22878 | // op: lsb |
| 22879 | return 7; |
| 22880 | case 3: |
| 22881 | // op: width |
| 22882 | return 16; |
| 22883 | } |
| 22884 | break; |
| 22885 | } |
| 22886 | case ARM::PKHBT: |
| 22887 | case ARM::PKHTB: { |
| 22888 | switch (OpNum) { |
| 22889 | case 4: |
| 22890 | // op: p |
| 22891 | return 28; |
| 22892 | case 0: |
| 22893 | // op: Rd |
| 22894 | return 12; |
| 22895 | case 1: |
| 22896 | // op: Rn |
| 22897 | return 16; |
| 22898 | case 2: |
| 22899 | // op: Rm |
| 22900 | return 0; |
| 22901 | case 3: |
| 22902 | // op: sh |
| 22903 | return 7; |
| 22904 | } |
| 22905 | break; |
| 22906 | } |
| 22907 | case ARM::SSAT: |
| 22908 | case ARM::USAT: { |
| 22909 | switch (OpNum) { |
| 22910 | case 4: |
| 22911 | // op: p |
| 22912 | return 28; |
| 22913 | case 0: |
| 22914 | // op: Rd |
| 22915 | return 12; |
| 22916 | case 1: |
| 22917 | // op: sat_imm |
| 22918 | return 16; |
| 22919 | case 2: |
| 22920 | // op: Rn |
| 22921 | return 0; |
| 22922 | case 3: |
| 22923 | // op: sh |
| 22924 | return 6; |
| 22925 | } |
| 22926 | break; |
| 22927 | } |
| 22928 | case ARM::SXTAB: |
| 22929 | case ARM::SXTAB16: |
| 22930 | case ARM::SXTAH: |
| 22931 | case ARM::UXTAB: |
| 22932 | case ARM::UXTAB16: |
| 22933 | case ARM::UXTAH: { |
| 22934 | switch (OpNum) { |
| 22935 | case 4: |
| 22936 | // op: p |
| 22937 | return 28; |
| 22938 | case 0: |
| 22939 | // op: Rd |
| 22940 | return 12; |
| 22941 | case 2: |
| 22942 | // op: Rm |
| 22943 | return 0; |
| 22944 | case 1: |
| 22945 | // op: Rn |
| 22946 | return 16; |
| 22947 | case 3: |
| 22948 | // op: rot |
| 22949 | return 10; |
| 22950 | } |
| 22951 | break; |
| 22952 | } |
| 22953 | case ARM::BFI: { |
| 22954 | switch (OpNum) { |
| 22955 | case 4: |
| 22956 | // op: p |
| 22957 | return 28; |
| 22958 | case 0: |
| 22959 | // op: Rd |
| 22960 | return 12; |
| 22961 | case 2: |
| 22962 | // op: Rn |
| 22963 | return 0; |
| 22964 | case 3: |
| 22965 | // op: imm |
| 22966 | return 7; |
| 22967 | } |
| 22968 | break; |
| 22969 | } |
| 22970 | case ARM::SMMLA: |
| 22971 | case ARM::SMMLAR: |
| 22972 | case ARM::SMMLS: |
| 22973 | case ARM::SMMLSR: |
| 22974 | case ARM::USADA8: { |
| 22975 | switch (OpNum) { |
| 22976 | case 4: |
| 22977 | // op: p |
| 22978 | return 28; |
| 22979 | case 0: |
| 22980 | // op: Rd |
| 22981 | return 16; |
| 22982 | case 1: |
| 22983 | // op: Rn |
| 22984 | return 0; |
| 22985 | case 2: |
| 22986 | // op: Rm |
| 22987 | return 8; |
| 22988 | case 3: |
| 22989 | // op: Ra |
| 22990 | return 12; |
| 22991 | } |
| 22992 | break; |
| 22993 | } |
| 22994 | case ARM::MLS: { |
| 22995 | switch (OpNum) { |
| 22996 | case 4: |
| 22997 | // op: p |
| 22998 | return 28; |
| 22999 | case 0: |
| 23000 | // op: Rd |
| 23001 | return 16; |
| 23002 | case 2: |
| 23003 | // op: Rm |
| 23004 | return 8; |
| 23005 | case 1: |
| 23006 | // op: Rn |
| 23007 | return 0; |
| 23008 | case 3: |
| 23009 | // op: Ra |
| 23010 | return 12; |
| 23011 | } |
| 23012 | break; |
| 23013 | } |
| 23014 | case ARM::CMNzrsr: |
| 23015 | case ARM::CMPrsr: |
| 23016 | case ARM::TEQrsr: |
| 23017 | case ARM::TSTrsr: { |
| 23018 | switch (OpNum) { |
| 23019 | case 4: |
| 23020 | // op: p |
| 23021 | return 28; |
| 23022 | case 0: |
| 23023 | // op: Rn |
| 23024 | return 16; |
| 23025 | case 1: |
| 23026 | // op: shift |
| 23027 | return 0; |
| 23028 | } |
| 23029 | break; |
| 23030 | } |
| 23031 | case ARM::LDRBrs: |
| 23032 | case ARM::LDRrs: |
| 23033 | case ARM::STRBrs: |
| 23034 | case ARM::STRrs: { |
| 23035 | switch (OpNum) { |
| 23036 | case 4: |
| 23037 | // op: p |
| 23038 | return 28; |
| 23039 | case 0: |
| 23040 | // op: Rt |
| 23041 | return 12; |
| 23042 | case 1: |
| 23043 | // op: shift |
| 23044 | return 0; |
| 23045 | } |
| 23046 | break; |
| 23047 | } |
| 23048 | case ARM::LDRB_PRE_IMM: |
| 23049 | case ARM::LDR_PRE_IMM: { |
| 23050 | switch (OpNum) { |
| 23051 | case 4: |
| 23052 | // op: p |
| 23053 | return 28; |
| 23054 | case 0: |
| 23055 | // op: Rt |
| 23056 | return 12; |
| 23057 | case 2: |
| 23058 | // op: addr |
| 23059 | return 0; |
| 23060 | } |
| 23061 | break; |
| 23062 | } |
| 23063 | case ARM::VFMAH: |
| 23064 | case ARM::VFMAS: |
| 23065 | case ARM::VFMSH: |
| 23066 | case ARM::VFMSS: |
| 23067 | case ARM::VFNMAH: |
| 23068 | case ARM::VFNMAS: |
| 23069 | case ARM::VFNMSH: |
| 23070 | case ARM::VFNMSS: |
| 23071 | case ARM::VMLAH: |
| 23072 | case ARM::VMLAS: |
| 23073 | case ARM::VMLSH: |
| 23074 | case ARM::VMLSS: |
| 23075 | case ARM::VNMLAH: |
| 23076 | case ARM::VNMLAS: |
| 23077 | case ARM::VNMLSH: |
| 23078 | case ARM::VNMLSS: { |
| 23079 | switch (OpNum) { |
| 23080 | case 4: |
| 23081 | // op: p |
| 23082 | return 28; |
| 23083 | case 0: |
| 23084 | // op: Sd |
| 23085 | return 12; |
| 23086 | case 2: |
| 23087 | // op: Sn |
| 23088 | return 7; |
| 23089 | case 3: |
| 23090 | // op: Sm |
| 23091 | return 0; |
| 23092 | } |
| 23093 | break; |
| 23094 | } |
| 23095 | case ARM::VMOVSRR: { |
| 23096 | switch (OpNum) { |
| 23097 | case 4: |
| 23098 | // op: p |
| 23099 | return 28; |
| 23100 | case 0: |
| 23101 | // op: dst1 |
| 23102 | return 0; |
| 23103 | case 2: |
| 23104 | // op: src1 |
| 23105 | return 12; |
| 23106 | case 3: |
| 23107 | // op: src2 |
| 23108 | return 16; |
| 23109 | } |
| 23110 | break; |
| 23111 | } |
| 23112 | case ARM::SMLABB: |
| 23113 | case ARM::SMLABT: |
| 23114 | case ARM::SMLATB: |
| 23115 | case ARM::SMLATT: |
| 23116 | case ARM::SMLAWB: |
| 23117 | case ARM::SMLAWT: { |
| 23118 | switch (OpNum) { |
| 23119 | case 4: |
| 23120 | // op: p |
| 23121 | return 28; |
| 23122 | case 1: |
| 23123 | // op: Rn |
| 23124 | return 0; |
| 23125 | case 2: |
| 23126 | // op: Rm |
| 23127 | return 8; |
| 23128 | case 0: |
| 23129 | // op: Rd |
| 23130 | return 16; |
| 23131 | case 3: |
| 23132 | // op: Ra |
| 23133 | return 12; |
| 23134 | } |
| 23135 | break; |
| 23136 | } |
| 23137 | case ARM::SMLAD: |
| 23138 | case ARM::SMLADX: |
| 23139 | case ARM::SMLSD: |
| 23140 | case ARM::SMLSDX: { |
| 23141 | switch (OpNum) { |
| 23142 | case 4: |
| 23143 | // op: p |
| 23144 | return 28; |
| 23145 | case 1: |
| 23146 | // op: Rn |
| 23147 | return 0; |
| 23148 | case 2: |
| 23149 | // op: Rm |
| 23150 | return 8; |
| 23151 | case 3: |
| 23152 | // op: Ra |
| 23153 | return 12; |
| 23154 | case 0: |
| 23155 | // op: Rd |
| 23156 | return 16; |
| 23157 | } |
| 23158 | break; |
| 23159 | } |
| 23160 | case ARM::STRB_PRE_IMM: |
| 23161 | case ARM::STR_PRE_IMM: { |
| 23162 | switch (OpNum) { |
| 23163 | case 4: |
| 23164 | // op: p |
| 23165 | return 28; |
| 23166 | case 1: |
| 23167 | // op: Rt |
| 23168 | return 12; |
| 23169 | case 2: |
| 23170 | // op: addr |
| 23171 | return 0; |
| 23172 | } |
| 23173 | break; |
| 23174 | } |
| 23175 | case ARM::LDRH: |
| 23176 | case ARM::LDRSB: |
| 23177 | case ARM::LDRSH: |
| 23178 | case ARM::STRH: { |
| 23179 | switch (OpNum) { |
| 23180 | case 4: |
| 23181 | // op: p |
| 23182 | return 28; |
| 23183 | case 1: |
| 23184 | // op: addr |
| 23185 | return 0; |
| 23186 | case 0: |
| 23187 | // op: Rt |
| 23188 | return 12; |
| 23189 | } |
| 23190 | break; |
| 23191 | } |
| 23192 | case ARM::LDCL_OFFSET: |
| 23193 | case ARM::LDCL_PRE: |
| 23194 | case ARM::LDC_OFFSET: |
| 23195 | case ARM::LDC_PRE: |
| 23196 | case ARM::STCL_OFFSET: |
| 23197 | case ARM::STCL_PRE: |
| 23198 | case ARM::STC_OFFSET: |
| 23199 | case ARM::STC_PRE: { |
| 23200 | switch (OpNum) { |
| 23201 | case 4: |
| 23202 | // op: p |
| 23203 | return 28; |
| 23204 | case 2: |
| 23205 | // op: addr |
| 23206 | return 0; |
| 23207 | case 0: |
| 23208 | // op: cop |
| 23209 | return 8; |
| 23210 | case 1: |
| 23211 | // op: CRd |
| 23212 | return 12; |
| 23213 | } |
| 23214 | break; |
| 23215 | } |
| 23216 | case ARM::VLDR_FPSCR_NZCVQC_pre: |
| 23217 | case ARM::VLDR_P0_pre: |
| 23218 | case ARM::VSTR_FPSCR_NZCVQC_pre: |
| 23219 | case ARM::VSTR_P0_pre: { |
| 23220 | switch (OpNum) { |
| 23221 | case 4: |
| 23222 | // op: p |
| 23223 | return 28; |
| 23224 | case 2: |
| 23225 | // op: addr |
| 23226 | return 0; |
| 23227 | } |
| 23228 | break; |
| 23229 | } |
| 23230 | case ARM::LDRHTi: |
| 23231 | case ARM::LDRSBTi: |
| 23232 | case ARM::LDRSHTi: { |
| 23233 | switch (OpNum) { |
| 23234 | case 4: |
| 23235 | // op: p |
| 23236 | return 28; |
| 23237 | case 2: |
| 23238 | // op: addr |
| 23239 | return 16; |
| 23240 | case 0: |
| 23241 | // op: Rt |
| 23242 | return 12; |
| 23243 | case 3: |
| 23244 | // op: offset |
| 23245 | return 0; |
| 23246 | } |
| 23247 | break; |
| 23248 | } |
| 23249 | case ARM::STRHTi: { |
| 23250 | switch (OpNum) { |
| 23251 | case 4: |
| 23252 | // op: p |
| 23253 | return 28; |
| 23254 | case 2: |
| 23255 | // op: addr |
| 23256 | return 16; |
| 23257 | case 1: |
| 23258 | // op: Rt |
| 23259 | return 12; |
| 23260 | case 3: |
| 23261 | // op: offset |
| 23262 | return 0; |
| 23263 | } |
| 23264 | break; |
| 23265 | } |
| 23266 | case ARM::VMOVRRS: { |
| 23267 | switch (OpNum) { |
| 23268 | case 4: |
| 23269 | // op: p |
| 23270 | return 28; |
| 23271 | case 2: |
| 23272 | // op: src1 |
| 23273 | return 0; |
| 23274 | case 0: |
| 23275 | // op: Rt |
| 23276 | return 12; |
| 23277 | case 1: |
| 23278 | // op: Rt2 |
| 23279 | return 16; |
| 23280 | } |
| 23281 | break; |
| 23282 | } |
| 23283 | case ARM::VLDR_FPSCR_NZCVQC_post: |
| 23284 | case ARM::VLDR_P0_post: |
| 23285 | case ARM::VSTR_FPSCR_NZCVQC_post: |
| 23286 | case ARM::VSTR_P0_post: { |
| 23287 | switch (OpNum) { |
| 23288 | case 4: |
| 23289 | // op: p |
| 23290 | return 28; |
| 23291 | case 3: |
| 23292 | // op: addr |
| 23293 | return 0; |
| 23294 | case 2: |
| 23295 | // op: Rn |
| 23296 | return 16; |
| 23297 | } |
| 23298 | break; |
| 23299 | } |
| 23300 | case ARM::LDCL_POST: |
| 23301 | case ARM::LDC_POST: |
| 23302 | case ARM::STCL_POST: |
| 23303 | case ARM::STC_POST: { |
| 23304 | switch (OpNum) { |
| 23305 | case 4: |
| 23306 | // op: p |
| 23307 | return 28; |
| 23308 | case 3: |
| 23309 | // op: offset |
| 23310 | return 0; |
| 23311 | case 2: |
| 23312 | // op: addr |
| 23313 | return 16; |
| 23314 | case 0: |
| 23315 | // op: cop |
| 23316 | return 8; |
| 23317 | case 1: |
| 23318 | // op: CRd |
| 23319 | return 12; |
| 23320 | } |
| 23321 | break; |
| 23322 | } |
| 23323 | case ARM::LDCL_OPTION: |
| 23324 | case ARM::LDC_OPTION: |
| 23325 | case ARM::STCL_OPTION: |
| 23326 | case ARM::STC_OPTION: { |
| 23327 | switch (OpNum) { |
| 23328 | case 4: |
| 23329 | // op: p |
| 23330 | return 28; |
| 23331 | case 3: |
| 23332 | // op: option |
| 23333 | return 0; |
| 23334 | case 2: |
| 23335 | // op: addr |
| 23336 | return 16; |
| 23337 | case 0: |
| 23338 | // op: cop |
| 23339 | return 8; |
| 23340 | case 1: |
| 23341 | // op: CRd |
| 23342 | return 12; |
| 23343 | } |
| 23344 | break; |
| 23345 | } |
| 23346 | case ARM::ADCrsi: |
| 23347 | case ARM::ADDrsi: |
| 23348 | case ARM::ANDrsi: |
| 23349 | case ARM::BICrsi: |
| 23350 | case ARM::EORrsi: |
| 23351 | case ARM::ORRrsi: |
| 23352 | case ARM::RSBrsi: |
| 23353 | case ARM::RSCrsi: |
| 23354 | case ARM::SBCrsi: |
| 23355 | case ARM::SUBrsi: { |
| 23356 | switch (OpNum) { |
| 23357 | case 4: |
| 23358 | // op: p |
| 23359 | return 28; |
| 23360 | case 6: |
| 23361 | // op: s |
| 23362 | return 20; |
| 23363 | case 0: |
| 23364 | // op: Rd |
| 23365 | return 12; |
| 23366 | case 1: |
| 23367 | // op: Rn |
| 23368 | return 16; |
| 23369 | case 2: |
| 23370 | // op: shift |
| 23371 | return 0; |
| 23372 | } |
| 23373 | break; |
| 23374 | } |
| 23375 | case ARM::MVNsr: { |
| 23376 | switch (OpNum) { |
| 23377 | case 4: |
| 23378 | // op: p |
| 23379 | return 28; |
| 23380 | case 6: |
| 23381 | // op: s |
| 23382 | return 20; |
| 23383 | case 0: |
| 23384 | // op: Rd |
| 23385 | return 12; |
| 23386 | case 1: |
| 23387 | // op: shift |
| 23388 | return 0; |
| 23389 | } |
| 23390 | break; |
| 23391 | } |
| 23392 | case ARM::MOVsr: { |
| 23393 | switch (OpNum) { |
| 23394 | case 4: |
| 23395 | // op: p |
| 23396 | return 28; |
| 23397 | case 6: |
| 23398 | // op: s |
| 23399 | return 20; |
| 23400 | case 0: |
| 23401 | // op: Rd |
| 23402 | return 12; |
| 23403 | case 1: |
| 23404 | // op: src |
| 23405 | return 0; |
| 23406 | } |
| 23407 | break; |
| 23408 | } |
| 23409 | case ARM::MLA: { |
| 23410 | switch (OpNum) { |
| 23411 | case 4: |
| 23412 | // op: p |
| 23413 | return 28; |
| 23414 | case 6: |
| 23415 | // op: s |
| 23416 | return 20; |
| 23417 | case 0: |
| 23418 | // op: Rd |
| 23419 | return 16; |
| 23420 | case 2: |
| 23421 | // op: Rm |
| 23422 | return 8; |
| 23423 | case 1: |
| 23424 | // op: Rn |
| 23425 | return 0; |
| 23426 | case 3: |
| 23427 | // op: Ra |
| 23428 | return 12; |
| 23429 | } |
| 23430 | break; |
| 23431 | } |
| 23432 | case ARM::SMULL: |
| 23433 | case ARM::UMULL: { |
| 23434 | switch (OpNum) { |
| 23435 | case 4: |
| 23436 | // op: p |
| 23437 | return 28; |
| 23438 | case 6: |
| 23439 | // op: s |
| 23440 | return 20; |
| 23441 | case 0: |
| 23442 | // op: RdLo |
| 23443 | return 12; |
| 23444 | case 1: |
| 23445 | // op: RdHi |
| 23446 | return 16; |
| 23447 | case 3: |
| 23448 | // op: Rm |
| 23449 | return 8; |
| 23450 | case 2: |
| 23451 | // op: Rn |
| 23452 | return 0; |
| 23453 | } |
| 23454 | break; |
| 23455 | } |
| 23456 | case ARM::t2MOVr: |
| 23457 | case ARM::t2MVNr: |
| 23458 | case ARM::t2RRX: { |
| 23459 | switch (OpNum) { |
| 23460 | case 4: |
| 23461 | // op: s |
| 23462 | return 20; |
| 23463 | case 0: |
| 23464 | // op: Rd |
| 23465 | return 8; |
| 23466 | case 1: |
| 23467 | // op: Rm |
| 23468 | return 0; |
| 23469 | } |
| 23470 | break; |
| 23471 | } |
| 23472 | case ARM::t2MOVi: |
| 23473 | case ARM::t2MVNi: { |
| 23474 | switch (OpNum) { |
| 23475 | case 4: |
| 23476 | // op: s |
| 23477 | return 20; |
| 23478 | case 0: |
| 23479 | // op: Rd |
| 23480 | return 8; |
| 23481 | case 1: |
| 23482 | // op: imm |
| 23483 | return 0; |
| 23484 | } |
| 23485 | break; |
| 23486 | } |
| 23487 | case ARM::MRRC: { |
| 23488 | switch (OpNum) { |
| 23489 | case 5: |
| 23490 | // op: p |
| 23491 | return 28; |
| 23492 | case 0: |
| 23493 | // op: Rt |
| 23494 | return 12; |
| 23495 | case 1: |
| 23496 | // op: Rt2 |
| 23497 | return 16; |
| 23498 | case 2: |
| 23499 | // op: cop |
| 23500 | return 8; |
| 23501 | case 3: |
| 23502 | // op: opc1 |
| 23503 | return 4; |
| 23504 | case 4: |
| 23505 | // op: CRm |
| 23506 | return 0; |
| 23507 | } |
| 23508 | break; |
| 23509 | } |
| 23510 | case ARM::LDRB_PRE_REG: |
| 23511 | case ARM::LDRH_PRE: |
| 23512 | case ARM::LDRSB_PRE: |
| 23513 | case ARM::LDRSH_PRE: |
| 23514 | case ARM::LDR_PRE_REG: { |
| 23515 | switch (OpNum) { |
| 23516 | case 5: |
| 23517 | // op: p |
| 23518 | return 28; |
| 23519 | case 0: |
| 23520 | // op: Rt |
| 23521 | return 12; |
| 23522 | case 2: |
| 23523 | // op: addr |
| 23524 | return 0; |
| 23525 | } |
| 23526 | break; |
| 23527 | } |
| 23528 | case ARM::LDRBT_POST_IMM: |
| 23529 | case ARM::LDRBT_POST_REG: |
| 23530 | case ARM::LDRB_POST_IMM: |
| 23531 | case ARM::LDRB_POST_REG: |
| 23532 | case ARM::LDRH_POST: |
| 23533 | case ARM::LDRSB_POST: |
| 23534 | case ARM::LDRSH_POST: |
| 23535 | case ARM::LDRT_POST_IMM: |
| 23536 | case ARM::LDRT_POST_REG: |
| 23537 | case ARM::LDR_POST_IMM: |
| 23538 | case ARM::LDR_POST_REG: { |
| 23539 | switch (OpNum) { |
| 23540 | case 5: |
| 23541 | // op: p |
| 23542 | return 28; |
| 23543 | case 0: |
| 23544 | // op: Rt |
| 23545 | return 12; |
| 23546 | case 3: |
| 23547 | // op: offset |
| 23548 | return 0; |
| 23549 | case 2: |
| 23550 | // op: addr |
| 23551 | return 16; |
| 23552 | } |
| 23553 | break; |
| 23554 | } |
| 23555 | case ARM::STRB_PRE_REG: |
| 23556 | case ARM::STRH_PRE: |
| 23557 | case ARM::STR_PRE_REG: { |
| 23558 | switch (OpNum) { |
| 23559 | case 5: |
| 23560 | // op: p |
| 23561 | return 28; |
| 23562 | case 1: |
| 23563 | // op: Rt |
| 23564 | return 12; |
| 23565 | case 2: |
| 23566 | // op: addr |
| 23567 | return 0; |
| 23568 | } |
| 23569 | break; |
| 23570 | } |
| 23571 | case ARM::STRBT_POST_IMM: |
| 23572 | case ARM::STRBT_POST_REG: |
| 23573 | case ARM::STRB_POST_IMM: |
| 23574 | case ARM::STRB_POST_REG: |
| 23575 | case ARM::STRH_POST: |
| 23576 | case ARM::STRT_POST_IMM: |
| 23577 | case ARM::STRT_POST_REG: |
| 23578 | case ARM::STR_POST_IMM: |
| 23579 | case ARM::STR_POST_REG: { |
| 23580 | switch (OpNum) { |
| 23581 | case 5: |
| 23582 | // op: p |
| 23583 | return 28; |
| 23584 | case 1: |
| 23585 | // op: Rt |
| 23586 | return 12; |
| 23587 | case 3: |
| 23588 | // op: offset |
| 23589 | return 0; |
| 23590 | case 2: |
| 23591 | // op: addr |
| 23592 | return 16; |
| 23593 | } |
| 23594 | break; |
| 23595 | } |
| 23596 | case ARM::MCRR: { |
| 23597 | switch (OpNum) { |
| 23598 | case 5: |
| 23599 | // op: p |
| 23600 | return 28; |
| 23601 | case 2: |
| 23602 | // op: Rt |
| 23603 | return 12; |
| 23604 | case 3: |
| 23605 | // op: Rt2 |
| 23606 | return 16; |
| 23607 | case 0: |
| 23608 | // op: cop |
| 23609 | return 8; |
| 23610 | case 1: |
| 23611 | // op: opc1 |
| 23612 | return 4; |
| 23613 | case 4: |
| 23614 | // op: CRm |
| 23615 | return 0; |
| 23616 | } |
| 23617 | break; |
| 23618 | } |
| 23619 | case ARM::LDRD: |
| 23620 | case ARM::STRD: { |
| 23621 | switch (OpNum) { |
| 23622 | case 5: |
| 23623 | // op: p |
| 23624 | return 28; |
| 23625 | case 2: |
| 23626 | // op: addr |
| 23627 | return 0; |
| 23628 | case 0: |
| 23629 | // op: Rt |
| 23630 | return 12; |
| 23631 | } |
| 23632 | break; |
| 23633 | } |
| 23634 | case ARM::LDRHTr: |
| 23635 | case ARM::LDRSBTr: |
| 23636 | case ARM::LDRSHTr: { |
| 23637 | switch (OpNum) { |
| 23638 | case 5: |
| 23639 | // op: p |
| 23640 | return 28; |
| 23641 | case 2: |
| 23642 | // op: addr |
| 23643 | return 16; |
| 23644 | case 0: |
| 23645 | // op: Rt |
| 23646 | return 12; |
| 23647 | case 3: |
| 23648 | // op: Rm |
| 23649 | return 0; |
| 23650 | } |
| 23651 | break; |
| 23652 | } |
| 23653 | case ARM::STRHTr: { |
| 23654 | switch (OpNum) { |
| 23655 | case 5: |
| 23656 | // op: p |
| 23657 | return 28; |
| 23658 | case 2: |
| 23659 | // op: addr |
| 23660 | return 16; |
| 23661 | case 1: |
| 23662 | // op: Rt |
| 23663 | return 12; |
| 23664 | case 3: |
| 23665 | // op: Rm |
| 23666 | return 0; |
| 23667 | } |
| 23668 | break; |
| 23669 | } |
| 23670 | case ARM::ADCrsr: |
| 23671 | case ARM::ADDrsr: |
| 23672 | case ARM::ANDrsr: |
| 23673 | case ARM::BICrsr: |
| 23674 | case ARM::EORrsr: |
| 23675 | case ARM::ORRrsr: |
| 23676 | case ARM::RSBrsr: |
| 23677 | case ARM::RSCrsr: |
| 23678 | case ARM::SBCrsr: |
| 23679 | case ARM::SUBrsr: { |
| 23680 | switch (OpNum) { |
| 23681 | case 5: |
| 23682 | // op: p |
| 23683 | return 28; |
| 23684 | case 7: |
| 23685 | // op: s |
| 23686 | return 20; |
| 23687 | case 0: |
| 23688 | // op: Rd |
| 23689 | return 12; |
| 23690 | case 1: |
| 23691 | // op: Rn |
| 23692 | return 16; |
| 23693 | case 2: |
| 23694 | // op: shift |
| 23695 | return 0; |
| 23696 | } |
| 23697 | break; |
| 23698 | } |
| 23699 | case ARM::t2ASRri: |
| 23700 | case ARM::t2LSLri: |
| 23701 | case ARM::t2LSRri: |
| 23702 | case ARM::t2RORri: { |
| 23703 | switch (OpNum) { |
| 23704 | case 5: |
| 23705 | // op: s |
| 23706 | return 20; |
| 23707 | case 0: |
| 23708 | // op: Rd |
| 23709 | return 8; |
| 23710 | case 1: |
| 23711 | // op: Rm |
| 23712 | return 0; |
| 23713 | case 2: |
| 23714 | // op: imm |
| 23715 | return 6; |
| 23716 | } |
| 23717 | break; |
| 23718 | } |
| 23719 | case ARM::t2ADCrr: |
| 23720 | case ARM::t2ADDrr: |
| 23721 | case ARM::t2ANDrr: |
| 23722 | case ARM::t2ASRrr: |
| 23723 | case ARM::t2BICrr: |
| 23724 | case ARM::t2EORrr: |
| 23725 | case ARM::t2LSLrr: |
| 23726 | case ARM::t2LSRrr: |
| 23727 | case ARM::t2ORNrr: |
| 23728 | case ARM::t2ORRrr: |
| 23729 | case ARM::t2RORrr: |
| 23730 | case ARM::t2RSBrr: |
| 23731 | case ARM::t2SBCrr: |
| 23732 | case ARM::t2SUBrr: { |
| 23733 | switch (OpNum) { |
| 23734 | case 5: |
| 23735 | // op: s |
| 23736 | return 20; |
| 23737 | case 0: |
| 23738 | // op: Rd |
| 23739 | return 8; |
| 23740 | case 1: |
| 23741 | // op: Rn |
| 23742 | return 16; |
| 23743 | case 2: |
| 23744 | // op: Rm |
| 23745 | return 0; |
| 23746 | } |
| 23747 | break; |
| 23748 | } |
| 23749 | case ARM::t2ADCri: |
| 23750 | case ARM::t2ADDri: |
| 23751 | case ARM::t2ANDri: |
| 23752 | case ARM::t2BICri: |
| 23753 | case ARM::t2EORri: |
| 23754 | case ARM::t2ORNri: |
| 23755 | case ARM::t2ORRri: |
| 23756 | case ARM::t2RSBri: |
| 23757 | case ARM::t2SBCri: |
| 23758 | case ARM::t2SUBri: { |
| 23759 | switch (OpNum) { |
| 23760 | case 5: |
| 23761 | // op: s |
| 23762 | return 20; |
| 23763 | case 0: |
| 23764 | // op: Rd |
| 23765 | return 8; |
| 23766 | case 1: |
| 23767 | // op: Rn |
| 23768 | return 16; |
| 23769 | case 2: |
| 23770 | // op: imm |
| 23771 | return 0; |
| 23772 | } |
| 23773 | break; |
| 23774 | } |
| 23775 | case ARM::t2MVNs: { |
| 23776 | switch (OpNum) { |
| 23777 | case 5: |
| 23778 | // op: s |
| 23779 | return 20; |
| 23780 | case 0: |
| 23781 | // op: Rd |
| 23782 | return 8; |
| 23783 | case 1: |
| 23784 | // op: ShiftedRm |
| 23785 | return 0; |
| 23786 | } |
| 23787 | break; |
| 23788 | } |
| 23789 | case ARM::t2ADDspImm: |
| 23790 | case ARM::t2SUBspImm: { |
| 23791 | switch (OpNum) { |
| 23792 | case 5: |
| 23793 | // op: s |
| 23794 | return 20; |
| 23795 | case 2: |
| 23796 | // op: imm |
| 23797 | return 0; |
| 23798 | } |
| 23799 | break; |
| 23800 | } |
| 23801 | case ARM::UMAAL: { |
| 23802 | switch (OpNum) { |
| 23803 | case 6: |
| 23804 | // op: p |
| 23805 | return 28; |
| 23806 | case 0: |
| 23807 | // op: RdLo |
| 23808 | return 12; |
| 23809 | case 1: |
| 23810 | // op: RdHi |
| 23811 | return 16; |
| 23812 | case 3: |
| 23813 | // op: Rm |
| 23814 | return 8; |
| 23815 | case 2: |
| 23816 | // op: Rn |
| 23817 | return 0; |
| 23818 | } |
| 23819 | break; |
| 23820 | } |
| 23821 | case ARM::MRC: { |
| 23822 | switch (OpNum) { |
| 23823 | case 6: |
| 23824 | // op: p |
| 23825 | return 28; |
| 23826 | case 0: |
| 23827 | // op: Rt |
| 23828 | return 12; |
| 23829 | case 1: |
| 23830 | // op: cop |
| 23831 | return 8; |
| 23832 | case 2: |
| 23833 | // op: opc1 |
| 23834 | return 21; |
| 23835 | case 5: |
| 23836 | // op: opc2 |
| 23837 | return 5; |
| 23838 | case 4: |
| 23839 | // op: CRm |
| 23840 | return 0; |
| 23841 | case 3: |
| 23842 | // op: CRn |
| 23843 | return 16; |
| 23844 | } |
| 23845 | break; |
| 23846 | } |
| 23847 | case ARM::LDRD_PRE: { |
| 23848 | switch (OpNum) { |
| 23849 | case 6: |
| 23850 | // op: p |
| 23851 | return 28; |
| 23852 | case 0: |
| 23853 | // op: Rt |
| 23854 | return 12; |
| 23855 | case 3: |
| 23856 | // op: addr |
| 23857 | return 0; |
| 23858 | } |
| 23859 | break; |
| 23860 | } |
| 23861 | case ARM::LDRD_POST: { |
| 23862 | switch (OpNum) { |
| 23863 | case 6: |
| 23864 | // op: p |
| 23865 | return 28; |
| 23866 | case 0: |
| 23867 | // op: Rt |
| 23868 | return 12; |
| 23869 | case 4: |
| 23870 | // op: offset |
| 23871 | return 0; |
| 23872 | case 3: |
| 23873 | // op: addr |
| 23874 | return 16; |
| 23875 | } |
| 23876 | break; |
| 23877 | } |
| 23878 | case ARM::STRD_PRE: { |
| 23879 | switch (OpNum) { |
| 23880 | case 6: |
| 23881 | // op: p |
| 23882 | return 28; |
| 23883 | case 1: |
| 23884 | // op: Rt |
| 23885 | return 12; |
| 23886 | case 3: |
| 23887 | // op: addr |
| 23888 | return 0; |
| 23889 | } |
| 23890 | break; |
| 23891 | } |
| 23892 | case ARM::STRD_POST: { |
| 23893 | switch (OpNum) { |
| 23894 | case 6: |
| 23895 | // op: p |
| 23896 | return 28; |
| 23897 | case 1: |
| 23898 | // op: Rt |
| 23899 | return 12; |
| 23900 | case 4: |
| 23901 | // op: offset |
| 23902 | return 0; |
| 23903 | case 3: |
| 23904 | // op: addr |
| 23905 | return 16; |
| 23906 | } |
| 23907 | break; |
| 23908 | } |
| 23909 | case ARM::CDP: { |
| 23910 | switch (OpNum) { |
| 23911 | case 6: |
| 23912 | // op: p |
| 23913 | return 28; |
| 23914 | case 1: |
| 23915 | // op: opc1 |
| 23916 | return 20; |
| 23917 | case 3: |
| 23918 | // op: CRn |
| 23919 | return 16; |
| 23920 | case 2: |
| 23921 | // op: CRd |
| 23922 | return 12; |
| 23923 | case 0: |
| 23924 | // op: cop |
| 23925 | return 8; |
| 23926 | case 5: |
| 23927 | // op: opc2 |
| 23928 | return 5; |
| 23929 | case 4: |
| 23930 | // op: CRm |
| 23931 | return 0; |
| 23932 | } |
| 23933 | break; |
| 23934 | } |
| 23935 | case ARM::SMLALBB: |
| 23936 | case ARM::SMLALBT: |
| 23937 | case ARM::SMLALD: |
| 23938 | case ARM::SMLALDX: |
| 23939 | case ARM::SMLALTB: |
| 23940 | case ARM::SMLALTT: |
| 23941 | case ARM::SMLSLD: |
| 23942 | case ARM::SMLSLDX: { |
| 23943 | switch (OpNum) { |
| 23944 | case 6: |
| 23945 | // op: p |
| 23946 | return 28; |
| 23947 | case 2: |
| 23948 | // op: Rn |
| 23949 | return 0; |
| 23950 | case 3: |
| 23951 | // op: Rm |
| 23952 | return 8; |
| 23953 | case 0: |
| 23954 | // op: RdLo |
| 23955 | return 12; |
| 23956 | case 1: |
| 23957 | // op: RdHi |
| 23958 | return 16; |
| 23959 | } |
| 23960 | break; |
| 23961 | } |
| 23962 | case ARM::MCR: { |
| 23963 | switch (OpNum) { |
| 23964 | case 6: |
| 23965 | // op: p |
| 23966 | return 28; |
| 23967 | case 2: |
| 23968 | // op: Rt |
| 23969 | return 12; |
| 23970 | case 0: |
| 23971 | // op: cop |
| 23972 | return 8; |
| 23973 | case 1: |
| 23974 | // op: opc1 |
| 23975 | return 21; |
| 23976 | case 5: |
| 23977 | // op: opc2 |
| 23978 | return 5; |
| 23979 | case 4: |
| 23980 | // op: CRm |
| 23981 | return 0; |
| 23982 | case 3: |
| 23983 | // op: CRn |
| 23984 | return 16; |
| 23985 | } |
| 23986 | break; |
| 23987 | } |
| 23988 | case ARM::SMLAL: |
| 23989 | case ARM::UMLAL: { |
| 23990 | switch (OpNum) { |
| 23991 | case 6: |
| 23992 | // op: p |
| 23993 | return 28; |
| 23994 | case 8: |
| 23995 | // op: s |
| 23996 | return 20; |
| 23997 | case 0: |
| 23998 | // op: RdLo |
| 23999 | return 12; |
| 24000 | case 1: |
| 24001 | // op: RdHi |
| 24002 | return 16; |
| 24003 | case 3: |
| 24004 | // op: Rm |
| 24005 | return 8; |
| 24006 | case 2: |
| 24007 | // op: Rn |
| 24008 | return 0; |
| 24009 | } |
| 24010 | break; |
| 24011 | } |
| 24012 | case ARM::t2ADCrs: |
| 24013 | case ARM::t2ADDrs: |
| 24014 | case ARM::t2ANDrs: |
| 24015 | case ARM::t2BICrs: |
| 24016 | case ARM::t2EORrs: |
| 24017 | case ARM::t2ORNrs: |
| 24018 | case ARM::t2ORRrs: |
| 24019 | case ARM::t2RSBrs: |
| 24020 | case ARM::t2SBCrs: |
| 24021 | case ARM::t2SUBrs: { |
| 24022 | switch (OpNum) { |
| 24023 | case 6: |
| 24024 | // op: s |
| 24025 | return 20; |
| 24026 | case 0: |
| 24027 | // op: Rd |
| 24028 | return 8; |
| 24029 | case 1: |
| 24030 | // op: Rn |
| 24031 | return 16; |
| 24032 | case 2: |
| 24033 | // op: ShiftedRm |
| 24034 | return 0; |
| 24035 | } |
| 24036 | break; |
| 24037 | } |
| 24038 | default: |
| 24039 | reportUnsupportedInst(MI); |
| 24040 | } |
| 24041 | reportUnsupportedOperand(MI, OpNum); |
| 24042 | } |
| 24043 | |
| 24044 | #endif // GET_OPERAND_BIT_OFFSET |
| 24045 | |
| 24046 |
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