1//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the ARMMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/ARMAddressingModes.h"
14#include "MCTargetDesc/ARMBaseInfo.h"
15#include "MCTargetDesc/ARMFixupKinds.h"
16#include "MCTargetDesc/ARMMCAsmInfo.h"
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/ADT/Statistic.h"
21#include "llvm/MC/MCCodeEmitter.h"
22#include "llvm/MC/MCContext.h"
23#include "llvm/MC/MCExpr.h"
24#include "llvm/MC/MCFixup.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrDesc.h"
27#include "llvm/MC/MCInstrInfo.h"
28#include "llvm/MC/MCRegisterInfo.h"
29#include "llvm/MC/MCSubtargetInfo.h"
30#include "llvm/Support/Casting.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Support/EndianStream.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/TargetParser/Triple.h"
35#include <cassert>
36#include <cstdint>
37#include <cstdlib>
38
39using namespace llvm;
40
41#define DEBUG_TYPE "mccodeemitter"
42
43STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
44STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
45
46namespace {
47
48class ARMMCCodeEmitter : public MCCodeEmitter {
49 const MCInstrInfo &MCII;
50 MCContext &CTX;
51 bool IsLittleEndian;
52
53public:
54 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
55 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
56 }
57 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
58 ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete;
59 ~ARMMCCodeEmitter() override = default;
60
61 bool isThumb(const MCSubtargetInfo &STI) const {
62 return STI.hasFeature(Feature: ARM::ModeThumb);
63 }
64
65 bool isThumb2(const MCSubtargetInfo &STI) const {
66 return isThumb(STI) && STI.hasFeature(Feature: ARM::FeatureThumb2);
67 }
68
69 bool isTargetMachO(const MCSubtargetInfo &STI) const {
70 const Triple &TT = STI.getTargetTriple();
71 return TT.isOSBinFormatMachO();
72 }
73
74 // getBinaryCodeForInstr - TableGen'erated function for getting the
75 // binary encoding for an instruction.
76 uint64_t getBinaryCodeForInstr(const MCInst &MI,
77 SmallVectorImpl<MCFixup> &Fixups,
78 const MCSubtargetInfo &STI) const;
79
80 /// getMachineOpValue - Return binary encoding of operand. If the machine
81 /// operand requires relocation, record the relocation and return zero.
82 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
83 SmallVectorImpl<MCFixup> &Fixups,
84 const MCSubtargetInfo &STI) const;
85
86 /// getHiLoImmOpValue - Return the encoding for either the hi / low 16-bit, or
87 /// high/middle-high/middle-low/low 8 bits of the specified operand. This is
88 /// used for operands with :lower16:, :upper16: :lower0_7:, :lower8_15:,
89 /// :higher0_7:, and :higher8_15: prefixes.
90 uint32_t getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
91 SmallVectorImpl<MCFixup> &Fixups,
92 const MCSubtargetInfo &STI) const;
93
94 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
95 unsigned &Reg, unsigned &Imm,
96 SmallVectorImpl<MCFixup> &Fixups,
97 const MCSubtargetInfo &STI) const;
98
99 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
100 /// BL branch target.
101 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
102 SmallVectorImpl<MCFixup> &Fixups,
103 const MCSubtargetInfo &STI) const;
104
105 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
106 /// BLX branch target.
107 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 SmallVectorImpl<MCFixup> &Fixups,
109 const MCSubtargetInfo &STI) const;
110
111 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
112 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 SmallVectorImpl<MCFixup> &Fixups,
114 const MCSubtargetInfo &STI) const;
115
116 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
117 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
118 SmallVectorImpl<MCFixup> &Fixups,
119 const MCSubtargetInfo &STI) const;
120
121 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
122 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
123 SmallVectorImpl<MCFixup> &Fixups,
124 const MCSubtargetInfo &STI) const;
125
126 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
127 /// branch target.
128 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups,
130 const MCSubtargetInfo &STI) const;
131
132 /// getThumbBranchTargetOpValue - Return encoding info for 24-bit
133 /// immediate Thumb2 direct branch target.
134 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups,
136 const MCSubtargetInfo &STI) const;
137
138 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
139 /// branch target.
140 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
141 SmallVectorImpl<MCFixup> &Fixups,
142 const MCSubtargetInfo &STI) const;
143 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
144 SmallVectorImpl<MCFixup> &Fixups,
145 const MCSubtargetInfo &STI) const;
146 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
147 SmallVectorImpl<MCFixup> &Fixups,
148 const MCSubtargetInfo &STI) const;
149
150 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
151 /// ADR label target.
152 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
153 SmallVectorImpl<MCFixup> &Fixups,
154 const MCSubtargetInfo &STI) const;
155 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
156 SmallVectorImpl<MCFixup> &Fixups,
157 const MCSubtargetInfo &STI) const;
158 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
159 SmallVectorImpl<MCFixup> &Fixups,
160 const MCSubtargetInfo &STI) const;
161
162 uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
163 SmallVectorImpl<MCFixup> &Fixups,
164 const MCSubtargetInfo &STI) const;
165
166 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
167 /// operand.
168 uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
169 SmallVectorImpl<MCFixup> &Fixups,
170 const MCSubtargetInfo &STI) const;
171
172 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
173 /// operand.
174 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
175 SmallVectorImpl<MCFixup> &Fixups,
176 const MCSubtargetInfo &STI) const;
177
178 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
179 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
180 SmallVectorImpl<MCFixup> &Fixups,
181 const MCSubtargetInfo &STI) const;
182
183 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
184 /// operand.
185 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
186 SmallVectorImpl<MCFixup> &Fixups,
187 const MCSubtargetInfo &STI) const;
188
189 /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2'
190 /// operand.
191 uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
192 SmallVectorImpl<MCFixup> &Fixups,
193 const MCSubtargetInfo &STI) const;
194
195 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
196 /// operand.
197 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
198 SmallVectorImpl<MCFixup> &Fixups,
199 const MCSubtargetInfo &STI) const;
200
201 /// getT2ScaledImmOpValue - Return encoding info for '+/- immX<<Y'
202 /// operand.
203 template<unsigned Bits, unsigned Shift>
204 uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
205 SmallVectorImpl<MCFixup> &Fixups,
206 const MCSubtargetInfo &STI) const;
207
208 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
209 /// operand.
210 uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
211 SmallVectorImpl<MCFixup> &Fixups,
212 const MCSubtargetInfo &STI) const;
213
214 /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}'
215 /// operand.
216 template<int shift>
217 uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
218 SmallVectorImpl<MCFixup> &Fixups,
219 const MCSubtargetInfo &STI) const;
220
221 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
222 /// operand as needed by load/store instructions.
223 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
224 SmallVectorImpl<MCFixup> &Fixups,
225 const MCSubtargetInfo &STI) const;
226
227 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
228 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
229 SmallVectorImpl<MCFixup> &Fixups,
230 const MCSubtargetInfo &STI) const {
231 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(i: OpIdx).getImm();
232 switch (Mode) {
233 default: llvm_unreachable("Unknown addressing sub-mode!");
234 case ARM_AM::da: return 0;
235 case ARM_AM::ia: return 1;
236 case ARM_AM::db: return 2;
237 case ARM_AM::ib: return 3;
238 }
239 }
240
241 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
242 ///
243 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
244 switch (ShOpc) {
245 case ARM_AM::no_shift:
246 case ARM_AM::lsl: return 0;
247 case ARM_AM::lsr: return 1;
248 case ARM_AM::asr: return 2;
249 case ARM_AM::ror:
250 case ARM_AM::rrx: return 3;
251 default:
252 llvm_unreachable("Invalid ShiftOpc!");
253 }
254 }
255
256 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
257 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
258 SmallVectorImpl<MCFixup> &Fixups,
259 const MCSubtargetInfo &STI) const;
260
261 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
262 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
263 SmallVectorImpl<MCFixup> &Fixups,
264 const MCSubtargetInfo &STI) const;
265
266 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
267 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
268 SmallVectorImpl<MCFixup> &Fixups,
269 const MCSubtargetInfo &STI) const;
270
271 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
272 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
273 SmallVectorImpl<MCFixup> &Fixups,
274 const MCSubtargetInfo &STI) const;
275
276 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
277 /// operand.
278 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
279 SmallVectorImpl<MCFixup> &Fixups,
280 const MCSubtargetInfo &STI) const;
281
282 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
283 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
284 SmallVectorImpl<MCFixup> &Fixups,
285 const MCSubtargetInfo &STI) const;
286
287 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
288 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
289 SmallVectorImpl<MCFixup> &Fixups,
290 const MCSubtargetInfo &STI) const;
291
292 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
293 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
294 SmallVectorImpl<MCFixup> &Fixups,
295 const MCSubtargetInfo &STI) const;
296
297 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
298 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
299 SmallVectorImpl<MCFixup> &Fixups,
300 const MCSubtargetInfo &STI) const;
301
302 /// getCCOutOpValue - Return encoding of the 's' bit.
303 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
304 SmallVectorImpl<MCFixup> &Fixups,
305 const MCSubtargetInfo &STI) const {
306 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
307 // '1' respectively.
308 return MI.getOperand(i: Op).getReg() == ARM::CPSR;
309 }
310
311 unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
312 SmallVectorImpl<MCFixup> &Fixups,
313 const MCSubtargetInfo &ST) const;
314
315 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
316 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
317 SmallVectorImpl<MCFixup> &Fixups,
318 const MCSubtargetInfo &STI) const;
319
320 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
321 SmallVectorImpl<MCFixup> &Fixups,
322 const MCSubtargetInfo &STI) const;
323 template<unsigned Bits, unsigned Shift>
324 unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
325 SmallVectorImpl<MCFixup> &Fixups,
326 const MCSubtargetInfo &STI) const;
327 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
328 SmallVectorImpl<MCFixup> &Fixups,
329 const MCSubtargetInfo &STI) const;
330
331 /// getSORegOpValue - Return an encoded so_reg shifted register value.
332 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
333 SmallVectorImpl<MCFixup> &Fixups,
334 const MCSubtargetInfo &STI) const;
335 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
336 SmallVectorImpl<MCFixup> &Fixups,
337 const MCSubtargetInfo &STI) const;
338 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
339 SmallVectorImpl<MCFixup> &Fixups,
340 const MCSubtargetInfo &STI) const;
341
342 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
343 SmallVectorImpl<MCFixup> &Fixups,
344 const MCSubtargetInfo &STI) const {
345 return 64 - MI.getOperand(i: Op).getImm();
346 }
347
348 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
349 SmallVectorImpl<MCFixup> &Fixups,
350 const MCSubtargetInfo &STI) const;
351
352 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
353 SmallVectorImpl<MCFixup> &Fixups,
354 const MCSubtargetInfo &STI) const;
355 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
356 SmallVectorImpl<MCFixup> &Fixups,
357 const MCSubtargetInfo &STI) const;
358 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
359 SmallVectorImpl<MCFixup> &Fixups,
360 const MCSubtargetInfo &STI) const;
361 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
362 SmallVectorImpl<MCFixup> &Fixups,
363 const MCSubtargetInfo &STI) const;
364 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
365 SmallVectorImpl<MCFixup> &Fixups,
366 const MCSubtargetInfo &STI) const;
367
368 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
369 SmallVectorImpl<MCFixup> &Fixups,
370 const MCSubtargetInfo &STI) const;
371 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
372 SmallVectorImpl<MCFixup> &Fixups,
373 const MCSubtargetInfo &STI) const;
374 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
375 SmallVectorImpl<MCFixup> &Fixups,
376 const MCSubtargetInfo &STI) const;
377 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
378 SmallVectorImpl<MCFixup> &Fixups,
379 const MCSubtargetInfo &STI) const;
380
381 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
382 unsigned EncodedValue,
383 const MCSubtargetInfo &STI) const;
384 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
385 unsigned EncodedValue,
386 const MCSubtargetInfo &STI) const;
387 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
388 unsigned EncodedValue,
389 const MCSubtargetInfo &STI) const;
390 unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
391 unsigned EncodedValue,
392 const MCSubtargetInfo &STI) const;
393
394 unsigned VFPThumb2PostEncoder(const MCInst &MI,
395 unsigned EncodedValue,
396 const MCSubtargetInfo &STI) const;
397
398 uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
399 SmallVectorImpl<MCFixup> &Fixups,
400 const MCSubtargetInfo &STI) const;
401
402 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
403 SmallVectorImpl<MCFixup> &Fixups,
404 const MCSubtargetInfo &STI) const override;
405
406 template <bool isNeg, ARM::Fixups fixup>
407 uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
408 SmallVectorImpl<MCFixup> &Fixups,
409 const MCSubtargetInfo &STI) const;
410
411 uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
412 SmallVectorImpl<MCFixup> &Fixups,
413 const MCSubtargetInfo &STI) const;
414
415 uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
416 SmallVectorImpl<MCFixup> &Fixups,
417 const MCSubtargetInfo &STI) const;
418 uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
419 SmallVectorImpl<MCFixup> &Fixups,
420 const MCSubtargetInfo &STI) const;
421 template <unsigned size>
422 uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
423 SmallVectorImpl<MCFixup> &Fixups,
424 const MCSubtargetInfo &STI) const;
425};
426
427} // end anonymous namespace
428
429static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
430 const MCExpr *Value, uint16_t Kind) {
431 bool PCRel = false;
432 switch (Kind) {
433 case ARM::fixup_arm_ldst_pcrel_12:
434 case ARM::fixup_t2_ldst_pcrel_12:
435 case ARM::fixup_arm_pcrel_10_unscaled:
436 case ARM::fixup_arm_pcrel_10:
437 case ARM::fixup_t2_pcrel_10:
438 case ARM::fixup_arm_pcrel_9:
439 case ARM::fixup_t2_pcrel_9:
440 case ARM::fixup_thumb_adr_pcrel_10:
441 case ARM::fixup_arm_adr_pcrel_12:
442 case ARM::fixup_t2_adr_pcrel_12:
443 case ARM::fixup_arm_condbranch:
444 case ARM::fixup_arm_uncondbranch:
445 case ARM::fixup_t2_condbranch:
446 case ARM::fixup_t2_uncondbranch:
447 case ARM::fixup_arm_thumb_br:
448 case ARM::fixup_arm_uncondbl:
449 case ARM::fixup_arm_condbl:
450 case ARM::fixup_arm_blx:
451 case ARM::fixup_arm_thumb_bl:
452 case ARM::fixup_arm_thumb_blx:
453 case ARM::fixup_arm_thumb_cb:
454 case ARM::fixup_arm_thumb_cp:
455 case ARM::fixup_arm_thumb_bcc:
456 case ARM::fixup_bf_branch:
457 case ARM::fixup_bf_target:
458 case ARM::fixup_bfl_target:
459 case ARM::fixup_bfc_target:
460 case ARM::fixup_wls:
461 case ARM::fixup_le:
462 PCRel = true;
463 }
464 Fixups.push_back(Elt: MCFixup::create(Offset, Value, Kind, PCRel));
465}
466
467/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
468/// instructions, and rewrite them to their Thumb2 form if we are currently in
469/// Thumb2 mode.
470unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
471 unsigned EncodedValue,
472 const MCSubtargetInfo &STI) const {
473 if (isThumb2(STI)) {
474 // NEON Thumb2 data-processing encodings are very simple: bit 24 is moved
475 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
476 // set to 1111.
477 unsigned Bit24 = EncodedValue & 0x01000000;
478 unsigned Bit28 = Bit24 << 4;
479 EncodedValue &= 0xEFFFFFFF;
480 EncodedValue |= Bit28;
481 EncodedValue |= 0x0F000000;
482 }
483
484 return EncodedValue;
485}
486
487/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
488/// instructions, and rewrite them to their Thumb2 form if we are currently in
489/// Thumb2 mode.
490unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
491 unsigned EncodedValue,
492 const MCSubtargetInfo &STI) const {
493 if (isThumb2(STI)) {
494 EncodedValue &= 0xF0FFFFFF;
495 EncodedValue |= 0x09000000;
496 }
497
498 return EncodedValue;
499}
500
501/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
502/// instructions, and rewrite them to their Thumb2 form if we are currently in
503/// Thumb2 mode.
504unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
505 unsigned EncodedValue,
506 const MCSubtargetInfo &STI) const {
507 if (isThumb2(STI)) {
508 EncodedValue &= 0x00FFFFFF;
509 EncodedValue |= 0xEE000000;
510 }
511
512 return EncodedValue;
513}
514
515/// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
516/// if we are in Thumb2.
517unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
518 unsigned EncodedValue,
519 const MCSubtargetInfo &STI) const {
520 if (isThumb2(STI)) {
521 EncodedValue |= 0xC000000; // Set bits 27-26
522 }
523
524 return EncodedValue;
525}
526
527/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
528/// them to their Thumb2 form if we are currently in Thumb2 mode.
529unsigned ARMMCCodeEmitter::
530VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
531 const MCSubtargetInfo &STI) const {
532 if (isThumb2(STI)) {
533 EncodedValue &= 0x0FFFFFFF;
534 EncodedValue |= 0xE0000000;
535 }
536 return EncodedValue;
537}
538
539/// getMachineOpValue - Return binary encoding of operand. If the machine
540/// operand requires relocation, record the relocation and return zero.
541unsigned ARMMCCodeEmitter::
542getMachineOpValue(const MCInst &MI, const MCOperand &MO,
543 SmallVectorImpl<MCFixup> &Fixups,
544 const MCSubtargetInfo &STI) const {
545 if (MO.isReg()) {
546 MCRegister Reg = MO.getReg();
547 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
548
549 // In NEON, Q registers are encoded as 2x their register number,
550 // because they're using the same indices as the D registers they
551 // overlap. In MVE, there are no 64-bit vector instructions, so
552 // the encodings all refer to Q-registers by their literal
553 // register number.
554
555 if (STI.hasFeature(Feature: ARM::HasMVEIntegerOps))
556 return RegNo;
557
558 switch (Reg.id()) {
559 default:
560 return RegNo;
561 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
562 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
563 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
564 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
565 return 2 * RegNo;
566 }
567 } else if (MO.isImm()) {
568 return static_cast<unsigned>(MO.getImm());
569 } else if (MO.isDFPImm()) {
570 return static_cast<unsigned>(APFloat(bit_cast<double>(from: MO.getDFPImm()))
571 .bitcastToAPInt()
572 .getHiBits(numBits: 32)
573 .getLimitedValue());
574 }
575
576 llvm_unreachable("Unable to encode MCOperand!");
577}
578
579/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
580bool ARMMCCodeEmitter::
581EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
582 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
583 const MCSubtargetInfo &STI) const {
584 const MCOperand &MO = MI.getOperand(i: OpIdx);
585 const MCOperand &MO1 = MI.getOperand(i: OpIdx + 1);
586
587 Reg = CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
588
589 int32_t SImm = MO1.getImm();
590 bool isAdd = true;
591
592 // Special value for #-0
593 if (SImm == INT32_MIN) {
594 SImm = 0;
595 isAdd = false;
596 }
597
598 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
599 if (SImm < 0) {
600 SImm = -SImm;
601 isAdd = false;
602 }
603
604 Imm = SImm;
605 return isAdd;
606}
607
608/// getBranchTargetOpValue - Helper function to get the branch target operand,
609/// which is either an immediate or requires a fixup.
610static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
611 unsigned FixupKind,
612 SmallVectorImpl<MCFixup> &Fixups,
613 const MCSubtargetInfo &STI) {
614 const MCOperand &MO = MI.getOperand(i: OpIdx);
615
616 // If the destination is an immediate, we have nothing to do.
617 if (MO.isImm()) return MO.getImm();
618 assert(MO.isExpr() && "Unexpected branch target type!");
619 const MCExpr *Expr = MO.getExpr();
620 MCFixupKind Kind = MCFixupKind(FixupKind);
621 addFixup(Fixups, Offset: 0, Value: Expr, Kind);
622
623 // All of the information is in the fixup.
624 return 0;
625}
626
627// Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
628// determined by negating them and XOR'ing them with bit 23.
629static int32_t encodeThumbBLOffset(int32_t offset) {
630 offset >>= 1;
631 uint32_t S = (offset & 0x800000) >> 23;
632 uint32_t J1 = (offset & 0x400000) >> 22;
633 uint32_t J2 = (offset & 0x200000) >> 21;
634 J1 = (~J1 & 0x1);
635 J2 = (~J2 & 0x1);
636 J1 ^= S;
637 J2 ^= S;
638
639 offset &= ~0x600000;
640 offset |= J1 << 22;
641 offset |= J2 << 21;
642
643 return offset;
644}
645
646/// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
647uint32_t ARMMCCodeEmitter::
648getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
649 SmallVectorImpl<MCFixup> &Fixups,
650 const MCSubtargetInfo &STI) const {
651 const MCOperand MO = MI.getOperand(i: OpIdx);
652 if (MO.isExpr())
653 return ::getBranchTargetOpValue(MI, OpIdx, FixupKind: ARM::fixup_arm_thumb_bl,
654 Fixups, STI);
655 return encodeThumbBLOffset(offset: MO.getImm());
656}
657
658/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
659/// BLX branch target.
660uint32_t ARMMCCodeEmitter::
661getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
662 SmallVectorImpl<MCFixup> &Fixups,
663 const MCSubtargetInfo &STI) const {
664 const MCOperand MO = MI.getOperand(i: OpIdx);
665 if (MO.isExpr())
666 return ::getBranchTargetOpValue(MI, OpIdx, FixupKind: ARM::fixup_arm_thumb_blx,
667 Fixups, STI);
668 return encodeThumbBLOffset(offset: MO.getImm());
669}
670
671/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
672uint32_t ARMMCCodeEmitter::
673getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
674 SmallVectorImpl<MCFixup> &Fixups,
675 const MCSubtargetInfo &STI) const {
676 const MCOperand MO = MI.getOperand(i: OpIdx);
677 if (MO.isExpr())
678 return ::getBranchTargetOpValue(MI, OpIdx, FixupKind: ARM::fixup_arm_thumb_br,
679 Fixups, STI);
680 return (MO.getImm() >> 1);
681}
682
683/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
684uint32_t ARMMCCodeEmitter::
685getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
686 SmallVectorImpl<MCFixup> &Fixups,
687 const MCSubtargetInfo &STI) const {
688 const MCOperand MO = MI.getOperand(i: OpIdx);
689 if (MO.isExpr())
690 return ::getBranchTargetOpValue(MI, OpIdx, FixupKind: ARM::fixup_arm_thumb_bcc,
691 Fixups, STI);
692 return (MO.getImm() >> 1);
693}
694
695/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
696uint32_t ARMMCCodeEmitter::
697getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
698 SmallVectorImpl<MCFixup> &Fixups,
699 const MCSubtargetInfo &STI) const {
700 const MCOperand MO = MI.getOperand(i: OpIdx);
701 if (MO.isExpr())
702 return ::getBranchTargetOpValue(MI, OpIdx, FixupKind: ARM::fixup_arm_thumb_cb, Fixups, STI);
703 return (MO.getImm() >> 1);
704}
705
706/// Return true if this branch has a non-always predication
707static bool HasConditionalBranch(const MCInst &MI) {
708 int NumOp = MI.getNumOperands();
709 if (NumOp >= 2) {
710 for (int i = 0; i < NumOp-1; ++i) {
711 const MCOperand &MCOp1 = MI.getOperand(i);
712 const MCOperand &MCOp2 = MI.getOperand(i: i + 1);
713 if (MCOp1.isImm() && MCOp2.isReg() &&
714 (!MCOp2.getReg() || MCOp2.getReg() == ARM::CPSR)) {
715 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
716 return true;
717 }
718 }
719 }
720 return false;
721}
722
723/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
724/// target.
725uint32_t ARMMCCodeEmitter::
726getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
727 SmallVectorImpl<MCFixup> &Fixups,
728 const MCSubtargetInfo &STI) const {
729 // FIXME: This really, really shouldn't use TargetMachine. We don't want
730 // coupling between MC and TM anywhere we can help it.
731 if (isThumb2(STI))
732 return
733 ::getBranchTargetOpValue(MI, OpIdx, FixupKind: ARM::fixup_t2_condbranch, Fixups, STI);
734 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
735}
736
737/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
738/// target.
739uint32_t ARMMCCodeEmitter::
740getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
741 SmallVectorImpl<MCFixup> &Fixups,
742 const MCSubtargetInfo &STI) const {
743 const MCOperand MO = MI.getOperand(i: OpIdx);
744 if (MO.isExpr()) {
745 if (HasConditionalBranch(MI))
746 return ::getBranchTargetOpValue(MI, OpIdx,
747 FixupKind: ARM::fixup_arm_condbranch, Fixups, STI);
748 return ::getBranchTargetOpValue(MI, OpIdx,
749 FixupKind: ARM::fixup_arm_uncondbranch, Fixups, STI);
750 }
751
752 return MO.getImm() >> 2;
753}
754
755uint32_t ARMMCCodeEmitter::
756getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
757 SmallVectorImpl<MCFixup> &Fixups,
758 const MCSubtargetInfo &STI) const {
759 const MCOperand MO = MI.getOperand(i: OpIdx);
760 if (MO.isExpr()) {
761 if (HasConditionalBranch(MI))
762 return ::getBranchTargetOpValue(MI, OpIdx,
763 FixupKind: ARM::fixup_arm_condbl, Fixups, STI);
764 return ::getBranchTargetOpValue(MI, OpIdx, FixupKind: ARM::fixup_arm_uncondbl, Fixups, STI);
765 }
766
767 return MO.getImm() >> 2;
768}
769
770uint32_t ARMMCCodeEmitter::
771getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
772 SmallVectorImpl<MCFixup> &Fixups,
773 const MCSubtargetInfo &STI) const {
774 const MCOperand MO = MI.getOperand(i: OpIdx);
775 if (MO.isExpr())
776 return ::getBranchTargetOpValue(MI, OpIdx, FixupKind: ARM::fixup_arm_blx, Fixups, STI);
777
778 return MO.getImm() >> 1;
779}
780
781/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
782/// immediate branch target.
783uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
784 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
785 const MCSubtargetInfo &STI) const {
786 unsigned Val = 0;
787 const MCOperand MO = MI.getOperand(i: OpIdx);
788
789 if(MO.isExpr())
790 return ::getBranchTargetOpValue(MI, OpIdx, FixupKind: ARM::fixup_t2_uncondbranch, Fixups, STI);
791 else
792 Val = MO.getImm() >> 1;
793
794 bool I = (Val & 0x800000);
795 bool J1 = (Val & 0x400000);
796 bool J2 = (Val & 0x200000);
797 if (I ^ J1)
798 Val &= ~0x400000;
799 else
800 Val |= 0x400000;
801
802 if (I ^ J2)
803 Val &= ~0x200000;
804 else
805 Val |= 0x200000;
806
807 return Val;
808}
809
810/// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
811/// ADR label target.
812uint32_t ARMMCCodeEmitter::
813getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
814 SmallVectorImpl<MCFixup> &Fixups,
815 const MCSubtargetInfo &STI) const {
816 const MCOperand MO = MI.getOperand(i: OpIdx);
817 if (MO.isExpr())
818 return ::getBranchTargetOpValue(MI, OpIdx, FixupKind: ARM::fixup_arm_adr_pcrel_12,
819 Fixups, STI);
820 int64_t offset = MO.getImm();
821 uint32_t Val = 0x2000;
822
823 int SoImmVal;
824 if (offset == INT32_MIN) {
825 Val = 0x1000;
826 SoImmVal = 0;
827 } else if (offset < 0) {
828 Val = 0x1000;
829 offset *= -1;
830 SoImmVal = ARM_AM::getSOImmVal(Arg: offset);
831 if(SoImmVal == -1) {
832 Val = 0x2000;
833 offset *= -1;
834 SoImmVal = ARM_AM::getSOImmVal(Arg: offset);
835 }
836 } else {
837 SoImmVal = ARM_AM::getSOImmVal(Arg: offset);
838 if(SoImmVal == -1) {
839 Val = 0x1000;
840 offset *= -1;
841 SoImmVal = ARM_AM::getSOImmVal(Arg: offset);
842 }
843 }
844
845 assert(SoImmVal != -1 && "Not a valid so_imm value!");
846
847 Val |= SoImmVal;
848 return Val;
849}
850
851/// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
852/// target.
853uint32_t ARMMCCodeEmitter::
854getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
855 SmallVectorImpl<MCFixup> &Fixups,
856 const MCSubtargetInfo &STI) const {
857 const MCOperand MO = MI.getOperand(i: OpIdx);
858 if (MO.isExpr())
859 return ::getBranchTargetOpValue(MI, OpIdx, FixupKind: ARM::fixup_t2_adr_pcrel_12,
860 Fixups, STI);
861 int32_t Val = MO.getImm();
862 if (Val == INT32_MIN)
863 Val = 0x1000;
864 else if (Val < 0) {
865 Val *= -1;
866 Val |= 0x1000;
867 }
868 return Val;
869}
870
871/// getITMaskOpValue - Return the architectural encoding of an IT
872/// predication mask, given the MCOperand format.
873uint32_t ARMMCCodeEmitter::
874getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
875 SmallVectorImpl<MCFixup> &Fixups,
876 const MCSubtargetInfo &STI) const {
877 const MCOperand MaskMO = MI.getOperand(i: OpIdx);
878 assert(MaskMO.isImm() && "Unexpected operand type!");
879
880 unsigned Mask = MaskMO.getImm();
881
882 // IT masks are encoded as a sequence of replacement low-order bits
883 // for the condition code. So if the low bit of the starting
884 // condition code is 1, then we have to flip all the bits above the
885 // terminating bit (which is the lowest 1 bit).
886 assert(OpIdx > 0 && "IT mask appears first!");
887 const MCOperand CondMO = MI.getOperand(i: OpIdx-1);
888 assert(CondMO.isImm() && "Unexpected operand type!");
889 if (CondMO.getImm() & 1) {
890 unsigned LowBit = Mask & -Mask;
891 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
892 Mask ^= BitsAboveLowBit;
893 }
894
895 return Mask;
896}
897
898/// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
899/// target.
900uint32_t ARMMCCodeEmitter::
901getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
902 SmallVectorImpl<MCFixup> &Fixups,
903 const MCSubtargetInfo &STI) const {
904 const MCOperand MO = MI.getOperand(i: OpIdx);
905 if (MO.isExpr())
906 return ::getBranchTargetOpValue(MI, OpIdx, FixupKind: ARM::fixup_thumb_adr_pcrel_10,
907 Fixups, STI);
908 return MO.getImm();
909}
910
911/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
912/// operand.
913uint32_t ARMMCCodeEmitter::
914getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
915 SmallVectorImpl<MCFixup> &,
916 const MCSubtargetInfo &STI) const {
917 // [Rn, Rm]
918 // {5-3} = Rm
919 // {2-0} = Rn
920 const MCOperand &MO1 = MI.getOperand(i: OpIdx);
921 const MCOperand &MO2 = MI.getOperand(i: OpIdx + 1);
922 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(Reg: MO1.getReg());
923 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(Reg: MO2.getReg());
924 return (Rm << 3) | Rn;
925}
926
927/// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
928/// operand.
929uint32_t
930ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
931 SmallVectorImpl<MCFixup> &Fixups,
932 const MCSubtargetInfo &STI) const {
933 // {4-0} = szimm5
934 // The value we are trying to encode is an immediate between either the
935 // range of [1-7] or [1-15] depending on whether we are dealing with the
936 // u8/s8 or the u16/s16 variants respectively.
937 // This value is encoded as follows, if ShiftImm is the value within those
938 // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
939 // or 16.
940
941 unsigned Size, ShiftImm;
942 switch(MI.getOpcode()) {
943 case ARM::MVE_VSHLL_imms16bh:
944 case ARM::MVE_VSHLL_imms16th:
945 case ARM::MVE_VSHLL_immu16bh:
946 case ARM::MVE_VSHLL_immu16th:
947 Size = 16;
948 break;
949 case ARM::MVE_VSHLL_imms8bh:
950 case ARM::MVE_VSHLL_imms8th:
951 case ARM::MVE_VSHLL_immu8bh:
952 case ARM::MVE_VSHLL_immu8th:
953 Size = 8;
954 break;
955 default:
956 llvm_unreachable("Use of operand not supported by this instruction");
957 }
958 ShiftImm = MI.getOperand(i: OpIdx).getImm();
959 return Size + ShiftImm;
960}
961
962/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
963uint32_t ARMMCCodeEmitter::
964getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
965 SmallVectorImpl<MCFixup> &Fixups,
966 const MCSubtargetInfo &STI) const {
967 // {17-13} = reg
968 // {12} = (U)nsigned (add == '1', sub == '0')
969 // {11-0} = imm12
970 unsigned Reg = 0, Imm12 = 0;
971 bool isAdd = true;
972 // If The first operand isn't a register, we have a label reference.
973 const MCOperand &MO = MI.getOperand(i: OpIdx);
974 if (MO.isReg()) {
975 const MCOperand &MO1 = MI.getOperand(i: OpIdx + 1);
976 if (MO1.isImm()) {
977 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm&: Imm12, Fixups, STI);
978 } else if (MO1.isExpr()) {
979 assert(!isThumb(STI) && !isThumb2(STI) &&
980 "Thumb mode requires different encoding");
981 Reg = CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
982 isAdd = false; // 'U' bit is set as part of the fixup.
983 MCFixupKind Kind = ARM::fixup_arm_ldst_abs_12;
984 addFixup(Fixups, Offset: 0, Value: MO1.getExpr(), Kind);
985 }
986 } else if (MO.isExpr()) {
987 Reg = CTX.getRegisterInfo()->getEncodingValue(Reg: ARM::PC); // Rn is PC.
988 isAdd = false; // 'U' bit is set as part of the fixup.
989 MCFixupKind Kind;
990 if (isThumb2(STI))
991 Kind = ARM::fixup_t2_ldst_pcrel_12;
992 else
993 Kind = ARM::fixup_arm_ldst_pcrel_12;
994 addFixup(Fixups, Offset: 0, Value: MO.getExpr(), Kind);
995
996 ++MCNumCPRelocations;
997 } else {
998 Reg = ARM::PC;
999 int32_t Offset = MO.getImm();
1000 if (Offset == INT32_MIN) {
1001 Offset = 0;
1002 isAdd = false;
1003 } else if (Offset < 0) {
1004 Offset *= -1;
1005 isAdd = false;
1006 }
1007 Imm12 = Offset;
1008 }
1009 uint32_t Binary = Imm12 & 0xfff;
1010 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1011 if (isAdd)
1012 Binary |= (1 << 12);
1013 Binary |= (Reg << 13);
1014 return Binary;
1015}
1016
1017template<unsigned Bits, unsigned Shift>
1018uint32_t ARMMCCodeEmitter::
1019getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
1020 SmallVectorImpl<MCFixup> &Fixups,
1021 const MCSubtargetInfo &STI) const {
1022 // FIXME: The immediate operand should have already been encoded like this
1023 // before ever getting here. The encoder method should just need to combine
1024 // the MI operands for the register and the offset into a single
1025 // representation for the complex operand in the .td file. This isn't just
1026 // style, unfortunately. As-is, we can't represent the distinct encoding
1027 // for #-0.
1028
1029 // {Bits} = (U)nsigned (add == '1', sub == '0')
1030 // {(Bits-1)-0} = immediate
1031 int32_t Imm = MI.getOperand(i: OpIdx).getImm();
1032 bool isAdd = Imm >= 0;
1033
1034 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1035 if (Imm < 0)
1036 Imm = -(uint32_t)Imm;
1037
1038 Imm >>= Shift;
1039
1040 uint32_t Binary = Imm & ((1U << Bits) - 1);
1041 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1042 if (isAdd)
1043 Binary |= (1U << Bits);
1044 return Binary;
1045}
1046
1047/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1048/// operand.
1049uint32_t ARMMCCodeEmitter::
1050getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
1051 SmallVectorImpl<MCFixup> &Fixups,
1052 const MCSubtargetInfo &STI) const {
1053 // {6-3} Rn
1054 // {2-0} Qm
1055 const MCOperand &M0 = MI.getOperand(i: OpIdx);
1056 const MCOperand &M1 = MI.getOperand(i: OpIdx + 1);
1057
1058 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(Reg: M0.getReg());
1059 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(Reg: M1.getReg());
1060
1061 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1062
1063 return (Rn << 3) | Qm;
1064}
1065
1066/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1067/// operand.
1068template<int shift>
1069uint32_t ARMMCCodeEmitter::
1070getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
1071 SmallVectorImpl<MCFixup> &Fixups,
1072 const MCSubtargetInfo &STI) const {
1073 // {10-8} Qm
1074 // {7-0} Imm
1075 const MCOperand &M0 = MI.getOperand(i: OpIdx);
1076 const MCOperand &M1 = MI.getOperand(i: OpIdx + 1);
1077
1078 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(Reg: M0.getReg());
1079 int32_t Imm = M1.getImm();
1080
1081 bool isAdd = Imm >= 0;
1082
1083 Imm >>= shift;
1084
1085 if (!isAdd)
1086 Imm = -(uint32_t)Imm;
1087
1088 Imm &= 0x7f;
1089
1090 if (isAdd)
1091 Imm |= 0x80;
1092
1093 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1094
1095 return (Qm << 8) | Imm;
1096}
1097
1098/// getT2AddrModeImm8s4OpValue - Return encoding info for
1099/// 'reg +/- imm8<<2' operand.
1100uint32_t ARMMCCodeEmitter::
1101getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
1102 SmallVectorImpl<MCFixup> &Fixups,
1103 const MCSubtargetInfo &STI) const {
1104 // {12-9} = reg
1105 // {8} = (U)nsigned (add == '1', sub == '0')
1106 // {7-0} = imm8
1107 unsigned Reg, Imm8;
1108 bool isAdd = true;
1109 // If The first operand isn't a register, we have a label reference.
1110 const MCOperand &MO = MI.getOperand(i: OpIdx);
1111 if (!MO.isReg()) {
1112 Reg = CTX.getRegisterInfo()->getEncodingValue(Reg: ARM::PC); // Rn is PC.
1113 Imm8 = 0;
1114 isAdd = false ; // 'U' bit is set as part of the fixup.
1115
1116 assert(MO.isExpr() && "Unexpected machine operand type!");
1117 const MCExpr *Expr = MO.getExpr();
1118 MCFixupKind Kind = ARM::fixup_t2_pcrel_10;
1119 addFixup(Fixups, Offset: 0, Value: Expr, Kind);
1120
1121 ++MCNumCPRelocations;
1122 } else
1123 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm&: Imm8, Fixups, STI);
1124
1125 // FIXME: The immediate operand should have already been encoded like this
1126 // before ever getting here. The encoder method should just need to combine
1127 // the MI operands for the register and the offset into a single
1128 // representation for the complex operand in the .td file. This isn't just
1129 // style, unfortunately. As-is, we can't represent the distinct encoding
1130 // for #-0.
1131 assert(((Imm8 & 0x3) == 0) && "Not a valid immediate!");
1132 uint32_t Binary = (Imm8 >> 2) & 0xff;
1133 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1134 if (isAdd)
1135 Binary |= (1 << 8);
1136 Binary |= (Reg << 9);
1137 return Binary;
1138}
1139
1140/// getT2AddrModeImm7s4OpValue - Return encoding info for
1141/// 'reg +/- imm7<<2' operand.
1142uint32_t
1143ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1144 SmallVectorImpl<MCFixup> &Fixups,
1145 const MCSubtargetInfo &STI) const {
1146 // {11-8} = reg
1147 // {7} = (A)dd (add == '1', sub == '0')
1148 // {6-0} = imm7
1149 unsigned Reg, Imm7;
1150 // If The first operand isn't a register, we have a label reference.
1151 bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm&: Imm7, Fixups, STI);
1152
1153 // FIXME: The immediate operand should have already been encoded like this
1154 // before ever getting here. The encoder method should just need to combine
1155 // the MI operands for the register and the offset into a single
1156 // representation for the complex operand in the .td file. This isn't just
1157 // style, unfortunately. As-is, we can't represent the distinct encoding
1158 // for #-0.
1159 uint32_t Binary = (Imm7 >> 2) & 0xff;
1160 // Immediate is always encoded as positive. The 'A' bit controls add vs sub.
1161 if (isAdd)
1162 Binary |= (1 << 7);
1163 Binary |= (Reg << 8);
1164 return Binary;
1165}
1166
1167/// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1168/// 'reg + imm8<<2' operand.
1169uint32_t ARMMCCodeEmitter::
1170getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1171 SmallVectorImpl<MCFixup> &Fixups,
1172 const MCSubtargetInfo &STI) const {
1173 // {11-8} = reg
1174 // {7-0} = imm8
1175 const MCOperand &MO = MI.getOperand(i: OpIdx);
1176 const MCOperand &MO1 = MI.getOperand(i: OpIdx + 1);
1177 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
1178 unsigned Imm8 = MO1.getImm();
1179 return (Reg << 8) | Imm8;
1180}
1181
1182uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
1183 SmallVectorImpl<MCFixup> &Fixups,
1184 const MCSubtargetInfo &STI) const {
1185 // {20-16} = imm{15-12}
1186 // {11-0} = imm{11-0}
1187 const MCOperand &MO = MI.getOperand(i: OpIdx);
1188 if (MO.isImm())
1189 // Hi / lo bits already extracted during earlier passes.
1190 return static_cast<unsigned>(MO.getImm());
1191
1192 // Handle :upper16:, :lower16:, :upper8_15:, :upper0_7:, :lower8_15:
1193 // :lower0_7: assembly prefixes.
1194 const MCExpr *E = MO.getExpr();
1195 MCFixupKind Kind;
1196 if (E->getKind() == MCExpr::Specifier) {
1197 auto *ARM16Expr = cast<MCSpecifierExpr>(Val: E);
1198 E = ARM16Expr->getSubExpr();
1199
1200 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Val: E)) {
1201 const int64_t Value = MCE->getValue();
1202 if (Value > UINT32_MAX)
1203 report_fatal_error(reason: "constant value truncated (limited to 32-bit)");
1204
1205 switch (ARM16Expr->getSpecifier()) {
1206 case ARM::S_HI16:
1207 return (int32_t(Value) & 0xffff0000) >> 16;
1208 case ARM::S_LO16:
1209 return (int32_t(Value) & 0x0000ffff);
1210
1211 case ARM::S_HI_8_15:
1212 return (int32_t(Value) & 0xff000000) >> 24;
1213 case ARM::S_HI_0_7:
1214 return (int32_t(Value) & 0x00ff0000) >> 16;
1215 case ARM::S_LO_8_15:
1216 return (int32_t(Value) & 0x0000ff00) >> 8;
1217 case ARM::S_LO_0_7:
1218 return (int32_t(Value) & 0x000000ff);
1219
1220 default: llvm_unreachable("Unsupported ARMFixup");
1221 }
1222 }
1223
1224 switch (ARM16Expr->getSpecifier()) {
1225 default: llvm_unreachable("Unsupported ARMFixup");
1226 case ARM::S_HI16:
1227 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16
1228 : ARM::fixup_arm_movt_hi16);
1229 break;
1230 case ARM::S_LO16:
1231 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16
1232 : ARM::fixup_arm_movw_lo16);
1233 break;
1234 case ARM::S_HI_8_15:
1235 if (!isThumb(STI))
1236 llvm_unreachable(":upper_8_15: not supported in Arm state");
1237 Kind = ARM::fixup_arm_thumb_upper_8_15;
1238 break;
1239 case ARM::S_HI_0_7:
1240 if (!isThumb(STI))
1241 llvm_unreachable(":upper_0_7: not supported in Arm state");
1242 Kind = ARM::fixup_arm_thumb_upper_0_7;
1243 break;
1244 case ARM::S_LO_8_15:
1245 if (!isThumb(STI))
1246 llvm_unreachable(":lower_8_15: not supported in Arm state");
1247 Kind = ARM::fixup_arm_thumb_lower_8_15;
1248 break;
1249 case ARM::S_LO_0_7:
1250 if (!isThumb(STI))
1251 llvm_unreachable(":lower_0_7: not supported in Arm state");
1252 Kind = ARM::fixup_arm_thumb_lower_0_7;
1253 break;
1254 }
1255
1256 addFixup(Fixups, Offset: 0, Value: E, Kind);
1257 return 0;
1258 }
1259 // If the expression doesn't have :upper16:, :lower16: on it, it's just a
1260 // plain immediate expression, previously those evaluated to the lower 16 bits
1261 // of the expression regardless of whether we have a movt or a movw, but that
1262 // led to misleadingly results. This is disallowed in the AsmParser in
1263 // validateInstruction() so this should never happen. The same holds for
1264 // thumb1 :upper8_15:, :upper0_7:, lower8_15: or :lower0_7: with movs or adds.
1265 llvm_unreachable("expression without :upper16:, :lower16:, :upper8_15:,"
1266 ":upper0_7:, lower8_15: or :lower0_7:");
1267}
1268
1269uint32_t ARMMCCodeEmitter::
1270getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1271 SmallVectorImpl<MCFixup> &Fixups,
1272 const MCSubtargetInfo &STI) const {
1273 const MCOperand &MO = MI.getOperand(i: OpIdx);
1274 const MCOperand &MO1 = MI.getOperand(i: OpIdx+1);
1275 const MCOperand &MO2 = MI.getOperand(i: OpIdx+2);
1276 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
1277 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(Reg: MO1.getReg());
1278 unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc: MO2.getImm());
1279 bool isAdd = ARM_AM::getAM2Op(AM2Opc: MO2.getImm()) == ARM_AM::add;
1280 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(AM2Opc: MO2.getImm());
1281 unsigned SBits = getShiftOp(ShOpc: ShOp);
1282
1283 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1284 // amount. However, it would be an easy mistake to make so check here.
1285 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1286
1287 // {16-13} = Rn
1288 // {12} = isAdd
1289 // {11-0} = shifter
1290 // {3-0} = Rm
1291 // {4} = 0
1292 // {6-5} = type
1293 // {11-7} = imm
1294 uint32_t Binary = Rm;
1295 Binary |= Rn << 13;
1296 Binary |= SBits << 5;
1297 Binary |= ShImm << 7;
1298 if (isAdd)
1299 Binary |= 1 << 12;
1300 return Binary;
1301}
1302
1303uint32_t ARMMCCodeEmitter::
1304getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1305 SmallVectorImpl<MCFixup> &Fixups,
1306 const MCSubtargetInfo &STI) const {
1307 // {13} 1 == imm12, 0 == Rm
1308 // {12} isAdd
1309 // {11-0} imm12/Rm
1310 const MCOperand &MO = MI.getOperand(i: OpIdx);
1311 const MCOperand &MO1 = MI.getOperand(i: OpIdx+1);
1312 unsigned Imm = MO1.getImm();
1313 bool isAdd = ARM_AM::getAM2Op(AM2Opc: Imm) == ARM_AM::add;
1314 bool isReg = MO.getReg().isValid();
1315 uint32_t Binary = ARM_AM::getAM2Offset(AM2Opc: Imm);
1316 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1317 if (isReg) {
1318 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(AM2Opc: Imm);
1319 Binary <<= 7; // Shift amount is bits [11:7]
1320 Binary |= getShiftOp(ShOpc: ShOp) << 5; // Shift type is bits [6:5]
1321 Binary |= CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg()); // Rm is bits [3:0]
1322 }
1323 return Binary | (isAdd << 12) | (isReg << 13);
1324}
1325
1326uint32_t ARMMCCodeEmitter::
1327getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1328 SmallVectorImpl<MCFixup> &Fixups,
1329 const MCSubtargetInfo &STI) const {
1330 // {4} isAdd
1331 // {3-0} Rm
1332 const MCOperand &MO = MI.getOperand(i: OpIdx);
1333 const MCOperand &MO1 = MI.getOperand(i: OpIdx+1);
1334 bool isAdd = MO1.getImm() != 0;
1335 return CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg()) | (isAdd << 4);
1336}
1337
1338uint32_t ARMMCCodeEmitter::
1339getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1340 SmallVectorImpl<MCFixup> &Fixups,
1341 const MCSubtargetInfo &STI) const {
1342 // {9} 1 == imm8, 0 == Rm
1343 // {8} isAdd
1344 // {7-4} imm7_4/zero
1345 // {3-0} imm3_0/Rm
1346 const MCOperand &MO = MI.getOperand(i: OpIdx);
1347 const MCOperand &MO1 = MI.getOperand(i: OpIdx+1);
1348 unsigned Imm = MO1.getImm();
1349 bool isAdd = ARM_AM::getAM3Op(AM3Opc: Imm) == ARM_AM::add;
1350 bool isImm = !MO.getReg().isValid();
1351 uint32_t Imm8 = ARM_AM::getAM3Offset(AM3Opc: Imm);
1352 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1353 if (!isImm)
1354 Imm8 = CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
1355 return Imm8 | (isAdd << 8) | (isImm << 9);
1356}
1357
1358uint32_t ARMMCCodeEmitter::
1359getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1360 SmallVectorImpl<MCFixup> &Fixups,
1361 const MCSubtargetInfo &STI) const {
1362 // {13} 1 == imm8, 0 == Rm
1363 // {12-9} Rn
1364 // {8} isAdd
1365 // {7-4} imm7_4/zero
1366 // {3-0} imm3_0/Rm
1367 const MCOperand &MO = MI.getOperand(i: OpIdx);
1368 const MCOperand &MO1 = MI.getOperand(i: OpIdx+1);
1369 const MCOperand &MO2 = MI.getOperand(i: OpIdx+2);
1370
1371 // If The first operand isn't a register, we have a label reference.
1372 if (!MO.isReg()) {
1373 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(Reg: ARM::PC); // Rn is PC.
1374
1375 assert(MO.isExpr() && "Unexpected machine operand type!");
1376 const MCExpr *Expr = MO.getExpr();
1377 MCFixupKind Kind = ARM::fixup_arm_pcrel_10_unscaled;
1378 addFixup(Fixups, Offset: 0, Value: Expr, Kind);
1379
1380 ++MCNumCPRelocations;
1381 return (Rn << 9) | (1 << 13);
1382 }
1383 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
1384 unsigned Imm = MO2.getImm();
1385 bool isAdd = ARM_AM::getAM3Op(AM3Opc: Imm) == ARM_AM::add;
1386 bool isImm = !MO1.getReg().isValid();
1387 uint32_t Imm8 = ARM_AM::getAM3Offset(AM3Opc: Imm);
1388 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1389 if (!isImm)
1390 Imm8 = CTX.getRegisterInfo()->getEncodingValue(Reg: MO1.getReg());
1391 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1392}
1393
1394/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1395uint32_t ARMMCCodeEmitter::
1396getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1397 SmallVectorImpl<MCFixup> &Fixups,
1398 const MCSubtargetInfo &STI) const {
1399 // [SP, #imm]
1400 // {7-0} = imm8
1401 const MCOperand &MO1 = MI.getOperand(i: OpIdx + 1);
1402 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1403 "Unexpected base register!");
1404
1405 // The immediate is already shifted for the implicit zeroes, so no change
1406 // here.
1407 return MO1.getImm() & 0xff;
1408}
1409
1410/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1411uint32_t ARMMCCodeEmitter::
1412getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1413 SmallVectorImpl<MCFixup> &Fixups,
1414 const MCSubtargetInfo &STI) const {
1415 // [Rn, #imm]
1416 // {7-3} = imm5
1417 // {2-0} = Rn
1418 const MCOperand &MO = MI.getOperand(i: OpIdx);
1419 const MCOperand &MO1 = MI.getOperand(i: OpIdx + 1);
1420 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
1421 unsigned Imm5 = MO1.getImm();
1422 return ((Imm5 & 0x1f) << 3) | Rn;
1423}
1424
1425/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1426uint32_t ARMMCCodeEmitter::
1427getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1428 SmallVectorImpl<MCFixup> &Fixups,
1429 const MCSubtargetInfo &STI) const {
1430 const MCOperand MO = MI.getOperand(i: OpIdx);
1431 if (MO.isExpr())
1432 return ::getBranchTargetOpValue(MI, OpIdx, FixupKind: ARM::fixup_arm_thumb_cp, Fixups, STI);
1433 return (MO.getImm() >> 2);
1434}
1435
1436/// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
1437uint32_t ARMMCCodeEmitter::
1438getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1439 SmallVectorImpl<MCFixup> &Fixups,
1440 const MCSubtargetInfo &STI) const {
1441 // {12-9} = reg
1442 // {8} = (U)nsigned (add == '1', sub == '0')
1443 // {7-0} = imm8
1444 unsigned Reg, Imm8;
1445 bool isAdd;
1446 // If The first operand isn't a register, we have a label reference.
1447 const MCOperand &MO = MI.getOperand(i: OpIdx);
1448 if (!MO.isReg()) {
1449 Reg = CTX.getRegisterInfo()->getEncodingValue(Reg: ARM::PC); // Rn is PC.
1450 Imm8 = 0;
1451 isAdd = false; // 'U' bit is handled as part of the fixup.
1452
1453 assert(MO.isExpr() && "Unexpected machine operand type!");
1454 const MCExpr *Expr = MO.getExpr();
1455 MCFixupKind Kind;
1456 if (isThumb2(STI))
1457 Kind = ARM::fixup_t2_pcrel_10;
1458 else
1459 Kind = ARM::fixup_arm_pcrel_10;
1460 addFixup(Fixups, Offset: 0, Value: Expr, Kind);
1461
1462 ++MCNumCPRelocations;
1463 } else {
1464 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm&: Imm8, Fixups, STI);
1465 isAdd = ARM_AM::getAM5Op(AM5Opc: Imm8) == ARM_AM::add;
1466 }
1467
1468 uint32_t Binary = ARM_AM::getAM5Offset(AM5Opc: Imm8);
1469 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1470 if (isAdd)
1471 Binary |= (1 << 8);
1472 Binary |= (Reg << 9);
1473 return Binary;
1474}
1475
1476/// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1477uint32_t ARMMCCodeEmitter::
1478getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1479 SmallVectorImpl<MCFixup> &Fixups,
1480 const MCSubtargetInfo &STI) const {
1481 // {12-9} = reg
1482 // {8} = (U)nsigned (add == '1', sub == '0')
1483 // {7-0} = imm8
1484 unsigned Reg, Imm8;
1485 bool isAdd;
1486 // If The first operand isn't a register, we have a label reference.
1487 const MCOperand &MO = MI.getOperand(i: OpIdx);
1488 if (!MO.isReg()) {
1489 Reg = CTX.getRegisterInfo()->getEncodingValue(Reg: ARM::PC); // Rn is PC.
1490 Imm8 = 0;
1491 isAdd = false; // 'U' bit is handled as part of the fixup.
1492
1493 assert(MO.isExpr() && "Unexpected machine operand type!");
1494 const MCExpr *Expr = MO.getExpr();
1495 MCFixupKind Kind;
1496 if (isThumb2(STI))
1497 Kind = ARM::fixup_t2_pcrel_9;
1498 else
1499 Kind = ARM::fixup_arm_pcrel_9;
1500 addFixup(Fixups, Offset: 0, Value: Expr, Kind);
1501
1502 ++MCNumCPRelocations;
1503 } else {
1504 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm&: Imm8, Fixups, STI);
1505 isAdd = ARM_AM::getAM5Op(AM5Opc: Imm8) == ARM_AM::add;
1506 }
1507
1508 uint32_t Binary = ARM_AM::getAM5Offset(AM5Opc: Imm8);
1509 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1510 if (isAdd)
1511 Binary |= (1 << 8);
1512 Binary |= (Reg << 9);
1513 return Binary;
1514}
1515
1516unsigned ARMMCCodeEmitter::getModImmOpValue(const MCInst &MI, unsigned Op,
1517 SmallVectorImpl<MCFixup> &Fixups,
1518 const MCSubtargetInfo &ST) const {
1519 const MCOperand &MO = MI.getOperand(i: Op);
1520
1521 // Support for fixups (MCFixup)
1522 if (MO.isExpr()) {
1523 const MCExpr *Expr = MO.getExpr();
1524 // Fixups resolve to plain values that need to be encoded.
1525 MCFixupKind Kind = ARM::fixup_arm_mod_imm;
1526 addFixup(Fixups, Offset: 0, Value: Expr, Kind);
1527 return 0;
1528 }
1529
1530 // Immediate is already in its encoded format
1531 return MO.getImm();
1532}
1533
1534unsigned ARMMCCodeEmitter::getT2SOImmOpValue(const MCInst &MI, unsigned Op,
1535 SmallVectorImpl<MCFixup> &Fixups,
1536 const MCSubtargetInfo &STI) const {
1537 const MCOperand &MO = MI.getOperand(i: Op);
1538
1539 // Support for fixups (MCFixup)
1540 if (MO.isExpr()) {
1541 const MCExpr *Expr = MO.getExpr();
1542 // Fixups resolve to plain values that need to be encoded.
1543 MCFixupKind Kind = ARM::fixup_t2_so_imm;
1544 addFixup(Fixups, Offset: 0, Value: Expr, Kind);
1545 return 0;
1546 }
1547 unsigned SoImm = MO.getImm();
1548 unsigned Encoded = ARM_AM::getT2SOImmVal(Arg: SoImm);
1549 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
1550 return Encoded;
1551}
1552
1553unsigned ARMMCCodeEmitter::
1554getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1555 SmallVectorImpl<MCFixup> &Fixups,
1556 const MCSubtargetInfo &STI) const {
1557 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1558 // shifted. The second is Rs, the amount to shift by, and the third specifies
1559 // the type of the shift.
1560 //
1561 // {3-0} = Rm.
1562 // {4} = 1
1563 // {6-5} = type
1564 // {11-8} = Rs
1565 // {7} = 0
1566
1567 const MCOperand &MO = MI.getOperand(i: OpIdx);
1568 const MCOperand &MO1 = MI.getOperand(i: OpIdx + 1);
1569 const MCOperand &MO2 = MI.getOperand(i: OpIdx + 2);
1570 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Op: MO2.getImm());
1571
1572 // Encode Rm.
1573 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
1574
1575 // Encode the shift opcode.
1576 unsigned SBits = 0;
1577 MCRegister Rs = MO1.getReg();
1578 if (Rs) {
1579 // Set shift operand (bit[7:4]).
1580 // LSL - 0001
1581 // LSR - 0011
1582 // ASR - 0101
1583 // ROR - 0111
1584 switch (SOpc) {
1585 default: llvm_unreachable("Unknown shift opc!");
1586 case ARM_AM::lsl: SBits = 0x1; break;
1587 case ARM_AM::lsr: SBits = 0x3; break;
1588 case ARM_AM::asr: SBits = 0x5; break;
1589 case ARM_AM::ror: SBits = 0x7; break;
1590 }
1591 }
1592
1593 Binary |= SBits << 4;
1594
1595 // Encode the shift operation Rs.
1596 // Encode Rs bit[11:8].
1597 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1598 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Reg: Rs) << ARMII::RegRsShift);
1599}
1600
1601unsigned ARMMCCodeEmitter::
1602getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1603 SmallVectorImpl<MCFixup> &Fixups,
1604 const MCSubtargetInfo &STI) const {
1605 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1606 // shifted. The second is the amount to shift by.
1607 //
1608 // {3-0} = Rm.
1609 // {4} = 0
1610 // {6-5} = type
1611 // {11-7} = imm
1612
1613 const MCOperand &MO = MI.getOperand(i: OpIdx);
1614 const MCOperand &MO1 = MI.getOperand(i: OpIdx + 1);
1615 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Op: MO1.getImm());
1616
1617 // Encode Rm.
1618 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
1619
1620 // Encode the shift opcode.
1621 unsigned SBits = 0;
1622
1623 // Set shift operand (bit[6:4]).
1624 // LSL - 000
1625 // LSR - 010
1626 // ASR - 100
1627 // ROR - 110
1628 // RRX - 110 and bit[11:8] clear.
1629 switch (SOpc) {
1630 default: llvm_unreachable("Unknown shift opc!");
1631 case ARM_AM::lsl: SBits = 0x0; break;
1632 case ARM_AM::lsr: SBits = 0x2; break;
1633 case ARM_AM::asr: SBits = 0x4; break;
1634 case ARM_AM::ror: SBits = 0x6; break;
1635 case ARM_AM::rrx:
1636 Binary |= 0x60;
1637 return Binary;
1638 }
1639
1640 // Encode shift_imm bit[11:7].
1641 Binary |= SBits << 4;
1642 unsigned Offset = ARM_AM::getSORegOffset(Op: MO1.getImm());
1643 assert(Offset < 32 && "Offset must be in range 0-31!");
1644 return Binary | (Offset << 7);
1645}
1646
1647
1648unsigned ARMMCCodeEmitter::
1649getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1650 SmallVectorImpl<MCFixup> &Fixups,
1651 const MCSubtargetInfo &STI) const {
1652 const MCOperand &MO1 = MI.getOperand(i: OpNum);
1653 const MCOperand &MO2 = MI.getOperand(i: OpNum+1);
1654 const MCOperand &MO3 = MI.getOperand(i: OpNum+2);
1655
1656 // Encoded as [Rn, Rm, imm].
1657 // FIXME: Needs fixup support.
1658 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(Reg: MO1.getReg());
1659 Value <<= 4;
1660 Value |= CTX.getRegisterInfo()->getEncodingValue(Reg: MO2.getReg());
1661 Value <<= 2;
1662 Value |= MO3.getImm();
1663
1664 return Value;
1665}
1666
1667template<unsigned Bits, unsigned Shift>
1668unsigned ARMMCCodeEmitter::
1669getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
1670 SmallVectorImpl<MCFixup> &Fixups,
1671 const MCSubtargetInfo &STI) const {
1672 const MCOperand &MO1 = MI.getOperand(i: OpNum);
1673 const MCOperand &MO2 = MI.getOperand(i: OpNum+1);
1674
1675 // FIXME: Needs fixup support.
1676 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(Reg: MO1.getReg());
1677
1678 // If the immediate is B bits long, we need B+1 bits in order
1679 // to represent the (inverse of the) sign bit.
1680 Value <<= (Bits + 1);
1681 int32_t tmp = (int32_t)MO2.getImm();
1682 if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it
1683 tmp = 0;
1684 } else if (tmp < 0) {
1685 tmp = abs(x: tmp);
1686 } else {
1687 Value |= (1U << Bits); // Set the ADD bit
1688 }
1689 Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1690 return Value;
1691}
1692
1693unsigned ARMMCCodeEmitter::
1694getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1695 SmallVectorImpl<MCFixup> &Fixups,
1696 const MCSubtargetInfo &STI) const {
1697 const MCOperand &MO1 = MI.getOperand(i: OpNum);
1698
1699 // FIXME: Needs fixup support.
1700 unsigned Value = 0;
1701 auto tmp = static_cast<uint32_t>(MO1.getImm());
1702 if (static_cast<int32_t>(tmp) < 0)
1703 tmp = -tmp;
1704 else
1705 Value |= 256; // Set the ADD bit
1706 Value |= tmp & 255;
1707 return Value;
1708}
1709
1710unsigned ARMMCCodeEmitter::
1711getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1712 SmallVectorImpl<MCFixup> &Fixups,
1713 const MCSubtargetInfo &STI) const {
1714 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1715 // shifted. The second is the amount to shift by.
1716 //
1717 // {3-0} = Rm.
1718 // {4} = 0
1719 // {6-5} = type
1720 // {11-7} = imm
1721
1722 const MCOperand &MO = MI.getOperand(i: OpIdx);
1723 const MCOperand &MO1 = MI.getOperand(i: OpIdx + 1);
1724 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Op: MO1.getImm());
1725
1726 // Encode Rm.
1727 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
1728
1729 // Encode the shift opcode.
1730 unsigned SBits = 0;
1731 // Set shift operand (bit[6:4]).
1732 // LSL - 000
1733 // LSR - 010
1734 // ASR - 100
1735 // ROR - 110
1736 switch (SOpc) {
1737 default: llvm_unreachable("Unknown shift opc!");
1738 case ARM_AM::lsl: SBits = 0x0; break;
1739 case ARM_AM::lsr: SBits = 0x2; break;
1740 case ARM_AM::asr: SBits = 0x4; break;
1741 case ARM_AM::rrx: [[fallthrough]];
1742 case ARM_AM::ror: SBits = 0x6; break;
1743 }
1744
1745 Binary |= SBits << 4;
1746 if (SOpc == ARM_AM::rrx)
1747 return Binary;
1748
1749 // Encode shift_imm bit[11:7].
1750 return Binary | ARM_AM::getSORegOffset(Op: MO1.getImm()) << 7;
1751}
1752
1753unsigned ARMMCCodeEmitter::
1754getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1755 SmallVectorImpl<MCFixup> &Fixups,
1756 const MCSubtargetInfo &STI) const {
1757 // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the
1758 // msb of the mask.
1759 const MCOperand &MO = MI.getOperand(i: Op);
1760 uint32_t v = ~MO.getImm();
1761 uint32_t lsb = llvm::countr_zero(Val: v);
1762 uint32_t msb = llvm::Log2_32(Value: v);
1763 assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1764 return lsb | (msb << 5);
1765}
1766
1767unsigned ARMMCCodeEmitter::
1768getRegisterListOpValue(const MCInst &MI, unsigned Op,
1769 SmallVectorImpl<MCFixup> &Fixups,
1770 const MCSubtargetInfo &STI) const {
1771 // VLDM/VSTM/VSCCLRM:
1772 // {12-8} = Vd
1773 // {7-0} = Number of registers
1774 //
1775 // LDM/STM:
1776 // {15-0} = Bitfield of GPRs.
1777 MCRegister Reg = MI.getOperand(i: Op).getReg();
1778 bool SPRRegs = getARMMCRegisterClass(RC: ARM::SPRRegClassID).contains(Reg);
1779 bool DPRRegs = getARMMCRegisterClass(RC: ARM::DPRRegClassID).contains(Reg);
1780
1781 unsigned Binary = 0;
1782
1783 if (SPRRegs || DPRRegs || Reg == ARM::VPR) {
1784 // VLDM/VSTM/VSCCLRM
1785 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1786 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1787 Binary |= (RegNo & 0x1f) << 8;
1788
1789 if (MI.getOpcode() == ARM::VSCCLRMD)
1790 // Ignore VPR
1791 --NumRegs;
1792 else if (MI.getOpcode() == ARM::VSCCLRMS) {
1793 // The register list can contain both S registers and D registers, with D
1794 // registers counting as two registers. VPR doesn't count towards the
1795 // number of registers.
1796 NumRegs = 0;
1797 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1798 Reg = MI.getOperand(i: I).getReg();
1799 if (getARMMCRegisterClass(RC: ARM::SPRRegClassID).contains(Reg))
1800 NumRegs += 1;
1801 else if (getARMMCRegisterClass(RC: ARM::DPRRegClassID).contains(Reg))
1802 NumRegs += 2;
1803 }
1804 }
1805 if (SPRRegs)
1806 Binary |= NumRegs;
1807 else
1808 Binary |= NumRegs * 2;
1809 } else {
1810 const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1811 assert(is_sorted(drop_begin(MI, Op),
1812 [&](const MCOperand &LHS, const MCOperand &RHS) {
1813 return MRI.getEncodingValue(LHS.getReg()) <
1814 MRI.getEncodingValue(RHS.getReg());
1815 }));
1816 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1817 unsigned RegNo = MRI.getEncodingValue(Reg: MI.getOperand(i: I).getReg());
1818 Binary |= 1 << RegNo;
1819 }
1820 }
1821
1822 return Binary;
1823}
1824
1825/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1826/// with the alignment operand.
1827unsigned ARMMCCodeEmitter::
1828getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1829 SmallVectorImpl<MCFixup> &Fixups,
1830 const MCSubtargetInfo &STI) const {
1831 const MCOperand &Reg = MI.getOperand(i: Op);
1832 const MCOperand &Imm = MI.getOperand(i: Op + 1);
1833
1834 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg: Reg.getReg());
1835 unsigned Align = 0;
1836
1837 switch (Imm.getImm()) {
1838 default: break;
1839 case 2:
1840 case 4:
1841 case 8: Align = 0x01; break;
1842 case 16: Align = 0x02; break;
1843 case 32: Align = 0x03; break;
1844 }
1845
1846 return RegNo | (Align << 4);
1847}
1848
1849/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1850/// along with the alignment operand for use in VST1 and VLD1 with size 32.
1851unsigned ARMMCCodeEmitter::
1852getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1853 SmallVectorImpl<MCFixup> &Fixups,
1854 const MCSubtargetInfo &STI) const {
1855 const MCOperand &Reg = MI.getOperand(i: Op);
1856 const MCOperand &Imm = MI.getOperand(i: Op + 1);
1857
1858 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg: Reg.getReg());
1859 unsigned Align = 0;
1860
1861 switch (Imm.getImm()) {
1862 default: break;
1863 case 8:
1864 case 16:
1865 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1866 case 2: Align = 0x00; break;
1867 case 4: Align = 0x03; break;
1868 }
1869
1870 return RegNo | (Align << 4);
1871}
1872
1873
1874/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1875/// alignment operand for use in VLD-dup instructions. This is the same as
1876/// getAddrMode6AddressOpValue except for the alignment encoding, which is
1877/// different for VLD4-dup.
1878unsigned ARMMCCodeEmitter::
1879getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1880 SmallVectorImpl<MCFixup> &Fixups,
1881 const MCSubtargetInfo &STI) const {
1882 const MCOperand &Reg = MI.getOperand(i: Op);
1883 const MCOperand &Imm = MI.getOperand(i: Op + 1);
1884
1885 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg: Reg.getReg());
1886 unsigned Align = 0;
1887
1888 switch (Imm.getImm()) {
1889 default: break;
1890 case 2:
1891 case 4:
1892 case 8: Align = 0x01; break;
1893 case 16: Align = 0x03; break;
1894 }
1895
1896 return RegNo | (Align << 4);
1897}
1898
1899unsigned ARMMCCodeEmitter::
1900getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1901 SmallVectorImpl<MCFixup> &Fixups,
1902 const MCSubtargetInfo &STI) const {
1903 const MCOperand &MO = MI.getOperand(i: Op);
1904 if (!MO.getReg())
1905 return 0x0D;
1906 return CTX.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
1907}
1908
1909unsigned ARMMCCodeEmitter::
1910getShiftRight8Imm(const MCInst &MI, unsigned Op,
1911 SmallVectorImpl<MCFixup> &Fixups,
1912 const MCSubtargetInfo &STI) const {
1913 return 8 - MI.getOperand(i: Op).getImm();
1914}
1915
1916unsigned ARMMCCodeEmitter::
1917getShiftRight16Imm(const MCInst &MI, unsigned Op,
1918 SmallVectorImpl<MCFixup> &Fixups,
1919 const MCSubtargetInfo &STI) const {
1920 return 16 - MI.getOperand(i: Op).getImm();
1921}
1922
1923unsigned ARMMCCodeEmitter::
1924getShiftRight32Imm(const MCInst &MI, unsigned Op,
1925 SmallVectorImpl<MCFixup> &Fixups,
1926 const MCSubtargetInfo &STI) const {
1927 return 32 - MI.getOperand(i: Op).getImm();
1928}
1929
1930unsigned ARMMCCodeEmitter::
1931getShiftRight64Imm(const MCInst &MI, unsigned Op,
1932 SmallVectorImpl<MCFixup> &Fixups,
1933 const MCSubtargetInfo &STI) const {
1934 return 64 - MI.getOperand(i: Op).getImm();
1935}
1936
1937void ARMMCCodeEmitter::encodeInstruction(const MCInst &MI,
1938 SmallVectorImpl<char> &CB,
1939 SmallVectorImpl<MCFixup> &Fixups,
1940 const MCSubtargetInfo &STI) const {
1941 // Pseudo instructions don't get encoded.
1942 const MCInstrDesc &Desc = MCII.get(Opcode: MI.getOpcode());
1943 uint64_t TSFlags = Desc.TSFlags;
1944 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1945 return;
1946
1947 int Size;
1948 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1949 Size = Desc.getSize();
1950 else
1951 llvm_unreachable("Unexpected instruction size!");
1952
1953 auto Endian =
1954 IsLittleEndian ? llvm::endianness::little : llvm::endianness::big;
1955 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1956 if (Size == 2) {
1957 support::endian::write<uint16_t>(Out&: CB, V: Binary, E: Endian);
1958 } else if (isThumb(STI)) {
1959 // Thumb 32-bit wide instructions need to emit the high order halfword
1960 // first.
1961 support::endian::write<uint16_t>(Out&: CB, V: Binary >> 16, E: Endian);
1962 support::endian::write<uint16_t>(Out&: CB, V: Binary & 0xffff, E: Endian);
1963 } else {
1964 support::endian::write<uint32_t>(Out&: CB, V: Binary, E: Endian);
1965 }
1966 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1967}
1968
1969template <bool isNeg, ARM::Fixups fixup>
1970uint32_t
1971ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1972 SmallVectorImpl<MCFixup> &Fixups,
1973 const MCSubtargetInfo &STI) const {
1974 const MCOperand MO = MI.getOperand(i: OpIdx);
1975 if (MO.isExpr())
1976 return ::getBranchTargetOpValue(MI, OpIdx, FixupKind: fixup, Fixups, STI);
1977 return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1);
1978}
1979
1980uint32_t
1981ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1982 SmallVectorImpl<MCFixup> &Fixups,
1983 const MCSubtargetInfo &STI) const {
1984 const MCOperand MO = MI.getOperand(i: OpIdx);
1985 const MCOperand BranchMO = MI.getOperand(i: 0);
1986
1987 if (MO.isExpr()) {
1988 assert(BranchMO.isExpr());
1989 const MCExpr *DiffExpr = MCBinaryExpr::createSub(
1990 LHS: MO.getExpr(), RHS: BranchMO.getExpr(), Ctx&: CTX);
1991 MCFixupKind Kind = ARM::fixup_bfcsel_else_target;
1992 addFixup(Fixups, Offset: 0, Value: DiffExpr, Kind);
1993 return 0;
1994 }
1995
1996 assert(MO.isImm() && BranchMO.isImm());
1997 int Diff = MO.getImm() - BranchMO.getImm();
1998 assert(Diff == 4 || Diff == 2);
1999
2000 return Diff == 4;
2001}
2002
2003uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
2004 SmallVectorImpl<MCFixup> &Fixups,
2005 const MCSubtargetInfo &STI)const {
2006 const MCOperand MO = MI.getOperand(i: OpIdx);
2007 assert(MO.isImm() && "Unexpected operand type!");
2008
2009 int Value = MO.getImm();
2010 int Imm = 0;
2011
2012 // VPT Masks are actually encoded as a series of invert/don't invert bits,
2013 // rather than true/false bits.
2014 unsigned PrevBit = 0;
2015 for (int i = 3; i >= 0; --i) {
2016 unsigned Bit = (Value >> i) & 1;
2017
2018 // Check if we are at the end of the mask.
2019 if ((Value & ~(~0U << i)) == 0) {
2020 Imm |= (1 << i);
2021 break;
2022 }
2023
2024 // Convert the bit in the mask based on the previous bit.
2025 if (Bit != PrevBit)
2026 Imm |= (1 << i);
2027
2028 PrevBit = Bit;
2029 }
2030
2031 return Imm;
2032}
2033
2034uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue(
2035 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
2036 const MCSubtargetInfo &STI) const {
2037
2038 const MCOperand MO = MI.getOperand(i: OpIdx);
2039 assert(MO.isImm() && "Unexpected operand type!");
2040
2041 switch (MO.getImm()) {
2042 default:
2043 assert(0 && "Unexpected Condition!");
2044 return 0;
2045 case ARMCC::HS:
2046 case ARMCC::EQ:
2047 return 0;
2048 case ARMCC::HI:
2049 case ARMCC::NE:
2050 return 1;
2051 case ARMCC::GE:
2052 return 4;
2053 case ARMCC::LT:
2054 return 5;
2055 case ARMCC::GT:
2056 return 6;
2057 case ARMCC::LE:
2058 return 7;
2059 }
2060}
2061
2062uint32_t ARMMCCodeEmitter::
2063getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
2064 SmallVectorImpl<MCFixup> &Fixups,
2065 const MCSubtargetInfo &STI) const {
2066 const MCOperand &MO = MI.getOperand(i: OpIdx);
2067 assert(MO.isImm() && "Unexpected operand type!");
2068 return llvm::countr_zero(Val: (uint64_t)MO.getImm());
2069}
2070
2071template <unsigned start>
2072uint32_t ARMMCCodeEmitter::
2073getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
2074 SmallVectorImpl<MCFixup> &Fixups,
2075 const MCSubtargetInfo &STI) const {
2076 const MCOperand MO = MI.getOperand(i: OpIdx);
2077 assert(MO.isImm() && "Unexpected operand type!");
2078
2079 int Value = MO.getImm();
2080 return Value - start;
2081}
2082
2083#include "ARMGenMCCodeEmitter.inc"
2084
2085MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
2086 MCContext &Ctx) {
2087 return new ARMMCCodeEmitter(MCII, Ctx, true);
2088}
2089
2090MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
2091 MCContext &Ctx) {
2092 return new ARMMCCodeEmitter(MCII, Ctx, false);
2093}
2094