1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t ARMRegDiffLists[] = {
12 /* 0 */ -248, 1, 1, 1, 230, 1, -136, 65, -64, 65, -140, 0,
13 /* 12 */ -249, 1, 1, 1, 231, 1, -137, 65, -64, 65, -139, 0,
14 /* 24 */ -250, 1, 1, 1, 232, 1, -138, 65, -64, 65, -138, 0,
15 /* 36 */ -251, 1, 1, 1, 233, 1, -139, 65, -64, 65, -137, 0,
16 /* 48 */ -252, 1, 1, 1, 234, 1, -140, 65, -64, 65, -136, 0,
17 /* 60 */ -253, 1, 1, 1, 235, 1, -141, 65, -64, 65, -135, 0,
18 /* 72 */ -15, -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, -117, -91, -23, 1, 23, -22, 1, 95, 65, -64, 65, 69, -44, 28, -27, 28, 28, -150, 65, 30, -94, 65, 30, 40, 15, -134, 0,
19 /* 111 */ -15, -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, -117, -91, -24, 1, 24, -23, 1, 95, 65, -64, 65, 70, -45, 28, -27, 28, 29, -151, 65, 30, -94, 65, 30, 41, 15, -134, 0,
20 /* 150 */ -15, -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, -117, -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, -46, 28, -27, 28, 30, -152, 65, 30, -94, 65, 30, 42, 15, -134, 0,
21 /* 189 */ -15, -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, -117, -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, -47, 28, -27, 28, 31, -153, 65, 30, -94, 65, 30, 43, 15, -134, 0,
22 /* 228 */ -15, -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, -117, -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, -48, 28, -27, 28, 32, -154, 65, 30, -94, 65, 30, 44, 15, -134, 0,
23 /* 267 */ -15, -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, -117, -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, -49, 28, -27, 28, 33, -155, 65, 30, -94, 65, 30, 45, 15, -134, 0,
24 /* 310 */ -15, -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, -117, -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, -50, 28, -27, 28, 34, -156, 65, 30, -94, 65, 30, 46, 15, -134, 0,
25 /* 357 */ -15, -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, -117, -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, -51, 28, -27, 28, 35, -157, 65, 30, -94, 65, 30, 47, 15, -134, 0,
26 /* 408 */ -15, -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, -117, -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, -52, 28, -27, 28, 36, -158, 65, 30, -94, 65, 30, 48, 15, -134, 0,
27 /* 463 */ -15, -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, -117, -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, -53, 28, -27, 28, 37, -159, 65, 30, -94, 65, 30, 49, 15, -134, 0,
28 /* 518 */ -15, -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, -117, -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, -54, 28, -27, 28, 38, -160, 65, 30, -94, 65, 30, 50, 15, -134, 0,
29 /* 573 */ -15, -91, -36, 68, 1, -68, 69, 1, -34, -35, 70, 1, -70, 71, 1, 23, 65, -64, 65, 82, -117, -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, -55, 28, -27, 28, 39, -161, 65, 30, -94, 65, 30, 51, 15, -134, 0,
30 /* 628 */ -15, -91, -37, 66, 1, -66, 67, 1, -31, -36, 68, 1, -68, 69, 1, 25, 65, -64, 65, 83, -117, -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, -56, 28, -27, 28, 40, -162, 65, 30, -94, 65, 30, 52, 15, -134, 0,
31 /* 683 */ -254, 81, 1, -81, 1, 1, 236, 1, -142, 65, -64, 65, -134, 0,
32 /* 697 */ -255, 79, 1, -79, 80, 1, -80, 81, 1, -81, 237, 1, -143, 65, -64, 65, -133, 0,
33 /* 715 */ -256, 77, 1, -77, 78, 1, -78, 79, 1, -79, 80, 1, 157, 1, -144, 65, -64, 65, -132, 0,
34 /* 735 */ -257, 75, 1, -75, 76, 1, -76, 77, 1, -77, 78, 1, 160, 1, -145, 65, -64, 65, -131, 0,
35 /* 755 */ -258, 73, 1, -73, 74, 1, -74, 75, 1, -75, 76, 1, 163, 1, -146, 65, -64, 65, -130, 0,
36 /* 775 */ -259, 71, 1, -71, 72, 1, -72, 73, 1, -73, 74, 1, 166, 1, -147, 65, -64, 65, -129, 0,
37 /* 795 */ -260, 69, 1, -69, 70, 1, -70, 71, 1, -71, 72, 1, 169, 1, -148, 65, -64, 65, -128, 0,
38 /* 815 */ -261, 67, 1, -67, 68, 1, -68, 69, 1, -69, 70, 1, 172, 1, -149, 65, -64, 65, -127, 0,
39 /* 835 */ 23, 73, 2, 63, -48, 120, -71, 1, -49, 75, 26, -89, 65, 26, 30, -120, 66, 26, 29, -120, 0,
40 /* 856 */ 22, 74, 2, 63, -49, 120, -70, 1, -50, 76, 26, -90, 66, 26, 29, -120, 0,
41 /* 873 */ 65, -49, 77, 26, -90, 66, 26, 29, -120, 0,
42 /* 883 */ 23, 73, 2, 134, -71, 1, -49, 50, -49, 75, 26, 31, -120, 65, 26, 30, -120, 0,
43 /* 901 */ 22, 74, 135, -70, 1, -50, 77, 26, 30, -120, 0,
44 /* 912 */ 65, -49, 77, 26, 30, -120, 0,
45 /* 919 */ -71, 1, -49, 133, -120, 121, -120, 0,
46 /* 927 */ 139, -49, 50, -49, 12, 121, -120, 0,
47 /* 935 */ -49, 13, 121, -120, 0,
48 /* 940 */ -70, 1, -50, 133, -120, 0,
49 /* 946 */ -49, 133, -120, 0,
50 /* 950 */ -68, 36, 62, 148, -84, 1, -36, 66, 28, 40, -119, 0,
51 /* 962 */ -67, 36, 62, 148, -84, 1, -36, 66, 28, 40, -119, 0,
52 /* 974 */ 65, -36, 66, 28, 40, -119, 0,
53 /* 981 */ -84, 1, -36, 134, -119, 0,
54 /* 987 */ -221, 75, 1, -74, 77, 1, -76, 79, 1, -78, 81, 1, 10, 95, -93, 95, -93, 0,
55 /* 1005 */ -221, 74, 1, -73, 76, 1, -75, 78, 1, -77, 80, 1, 11, 95, -93, 95, -93, 0,
56 /* 1023 */ -221, 73, 1, -72, 75, 1, -74, 77, 1, -76, 79, 1, 12, 95, -93, 95, -93, 0,
57 /* 1041 */ -221, 72, 1, -71, 74, 1, -73, 76, 1, -75, 78, 1, 13, 95, -93, 95, -93, 0,
58 /* 1059 */ -221, 71, 1, -70, 73, 1, -72, 75, 1, -74, 77, 1, 14, 95, -93, 95, -93, 0,
59 /* 1077 */ -221, 70, 1, -69, 72, 1, -71, 74, 1, -73, 76, 1, 15, 95, -93, 95, -93, 0,
60 /* 1095 */ -221, 69, 1, -68, 71, 1, -70, 73, 1, -72, 75, 1, 16, 95, -93, 95, -93, 0,
61 /* 1113 */ -221, 68, 1, -67, 70, 1, -69, 72, 1, -71, 74, 1, 17, 95, -93, 95, -93, 0,
62 /* 1131 */ -221, 67, 1, -66, 69, 1, -68, 71, 1, -70, 73, 1, 18, 95, -93, 95, -93, 0,
63 /* 1149 */ -221, 66, 1, -65, 68, 1, -67, 70, 1, -69, 72, 1, 19, 95, -93, 95, -93, 0,
64 /* 1167 */ -221, 77, 1, -76, 79, 1, -78, 81, 1, -80, 92, 95, -93, 95, -93, 0,
65 /* 1183 */ -221, 76, 1, -75, 78, 1, -77, 80, 1, -79, 92, 95, -93, 95, -93, 0,
66 /* 1199 */ -221, 79, 1, -78, 81, 1, -80, 2, 92, 95, -93, 95, -93, 0,
67 /* 1213 */ -221, 78, 1, -77, 80, 1, -79, 2, 92, 95, -93, 95, -93, 0,
68 /* 1227 */ -221, 81, 1, -80, 2, 2, 92, 95, -93, 95, -93, 0,
69 /* 1239 */ -221, 80, 1, -79, 2, 2, 92, 95, -93, 95, -93, 0,
70 /* 1251 */ -221, 2, 2, 2, 92, 95, -93, 95, -93, 0,
71 /* 1261 */ 21, 75, 65, -50, 78, 26, -91, 0,
72 /* 1269 */ 24, 72, 2, 63, -47, 120, -72, 1, -48, 74, 26, -88, 64, 26, 31, -120, 65, 26, 30, -120, 92, -91, 0,
73 /* 1292 */ 65, -48, 76, 26, -89, 65, 26, 30, -120, 92, -91, 0,
74 /* 1304 */ 26, -90, 92, -91, 0,
75 /* 1309 */ 24, 72, 2, 135, -72, 1, -48, 49, -48, 74, 26, 32, -120, 64, 26, 31, -120, 65, 26, -90, 0,
76 /* 1330 */ 65, -48, 76, 26, 31, -120, 65, 26, -90, 0,
77 /* 1340 */ 25, 71, 2, 63, -46, 120, -73, 1, -47, 73, 26, -87, 63, 26, 32, -120, 64, 26, 31, -120, 91, -90, 0,
78 /* 1363 */ 65, -47, 75, 26, -88, 64, 26, 31, -120, 91, -90, 0,
79 /* 1375 */ 25, 71, 2, 136, -73, 1, -47, 48, -47, 73, 26, 33, -120, 63, 26, 32, -120, 64, 26, -89, 91, -90, 0,
80 /* 1398 */ 65, -47, 75, 26, 32, -120, 64, 26, -89, 91, -90, 0,
81 /* 1410 */ 26, 70, 2, 63, -45, 120, -74, 1, -46, 72, 26, -86, 62, 26, 33, -120, 63, 26, 32, -120, 90, -89, 0,
82 /* 1433 */ 65, -46, 74, 26, -87, 63, 26, 32, -120, 90, -89, 0,
83 /* 1445 */ 26, 70, 2, 137, -74, 1, -46, 47, -46, 72, 26, 34, -120, 62, 26, 33, -120, 63, 26, -88, 90, -89, 0,
84 /* 1468 */ 65, -46, 74, 26, 33, -120, 63, 26, -88, 90, -89, 0,
85 /* 1480 */ 27, 69, 2, 63, -44, 120, -75, 1, -45, 71, 26, -85, 61, 26, 34, -120, 62, 26, 33, -120, 89, -88, 0,
86 /* 1503 */ 65, -45, 73, 26, -86, 62, 26, 33, -120, 89, -88, 0,
87 /* 1515 */ 27, 69, 2, 138, -75, 1, -45, 46, -45, 71, 26, 35, -120, 61, 26, 34, -120, 62, 26, -87, 89, -88, 0,
88 /* 1538 */ 65, -45, 73, 26, 34, -120, 62, 26, -87, 89, -88, 0,
89 /* 1550 */ 28, 68, 2, 63, -43, 120, -76, 1, -44, 70, 26, -84, 60, 26, 35, -120, 61, 26, 34, -120, 88, -87, 0,
90 /* 1573 */ 65, -44, 72, 26, -85, 61, 26, 34, -120, 88, -87, 0,
91 /* 1585 */ 28, 68, 2, 139, -76, 1, -44, 45, -44, 70, 26, 36, -120, 60, 26, 35, -120, 61, 26, -86, 88, -87, 0,
92 /* 1608 */ 65, -44, 72, 26, 35, -120, 61, 26, -86, 88, -87, 0,
93 /* 1620 */ -82, 29, 67, 2, 63, -42, 120, -77, 1, -43, 69, 26, -83, 59, 26, 36, -120, 60, 26, 35, -120, 87, -86, 0,
94 /* 1644 */ -81, 29, 67, 2, 63, -42, 120, -77, 1, -43, 69, 26, -83, 59, 26, 36, -120, 60, 26, 35, -120, 87, -86, 0,
95 /* 1668 */ 65, -43, 71, 26, -84, 60, 26, 35, -120, 87, -86, 0,
96 /* 1680 */ 29, 67, 2, 140, -77, 1, -43, 44, -43, 69, 26, 37, -120, 59, 26, 36, -120, 60, 26, -85, 87, -86, 0,
97 /* 1703 */ 65, -43, 71, 26, 36, -120, 60, 26, -85, 87, -86, 0,
98 /* 1715 */ -80, 30, 66, 2, 63, -41, 120, -78, 1, -42, 68, 26, -82, 58, 26, 37, -120, 59, 26, 36, -120, 86, -85, 0,
99 /* 1739 */ -79, 30, 66, 2, 63, -41, 120, -78, 1, -42, 68, 26, -82, 58, 26, 37, -120, 59, 26, 36, -120, 86, -85, 0,
100 /* 1763 */ 65, -42, 70, 26, -83, 59, 26, 36, -120, 86, -85, 0,
101 /* 1775 */ -81, 30, 66, 2, 141, -78, 1, -42, 43, -42, 68, 26, 38, -120, 58, 26, 37, -120, 59, 26, -84, 86, -85, 0,
102 /* 1799 */ -80, 30, 66, 2, 141, -78, 1, -42, 43, -42, 68, 26, 38, -120, 58, 26, 37, -120, 59, 26, -84, 86, -85, 0,
103 /* 1823 */ 65, -42, 70, 26, 37, -120, 59, 26, -84, 86, -85, 0,
104 /* 1835 */ -78, 31, 65, 2, 63, -40, 120, -79, 1, -41, 67, 26, -81, 57, 26, 38, -120, 58, 26, 37, -120, 85, -84, 0,
105 /* 1859 */ -77, 31, 65, 2, 63, -40, 120, -79, 1, -41, 67, 26, -81, 57, 26, 38, -120, 58, 26, 37, -120, 85, -84, 0,
106 /* 1883 */ 65, -41, 69, 26, -82, 58, 26, 37, -120, 85, -84, 0,
107 /* 1895 */ -79, 31, 65, 2, 142, -79, 1, -41, 42, -41, 67, 26, 39, -120, 57, 26, 38, -120, 58, 26, -83, 85, -84, 0,
108 /* 1919 */ -78, 31, 65, 2, 142, -79, 1, -41, 42, -41, 67, 26, 39, -120, 57, 26, 38, -120, 58, 26, -83, 85, -84, 0,
109 /* 1943 */ 65, -41, 69, 26, 38, -120, 58, 26, -83, 85, -84, 0,
110 /* 1955 */ -76, 32, 64, 2, 63, -39, 120, -80, 1, -40, 66, 26, -80, 56, 26, 39, -120, 57, 26, 38, -120, 84, -83, 0,
111 /* 1979 */ -75, 32, 64, 2, 63, -39, 120, -80, 1, -40, 66, 26, -80, 56, 26, 39, -120, 57, 26, 38, -120, 84, -83, 0,
112 /* 2003 */ 65, -40, 68, 26, -81, 57, 26, 38, -120, 84, -83, 0,
113 /* 2015 */ -77, 32, 64, 2, 143, -80, 1, -40, 41, -40, 66, 26, 40, -120, 56, 26, 39, -120, 57, 26, -82, 84, -83, 0,
114 /* 2039 */ -76, 32, 64, 2, 143, -80, 1, -40, 41, -40, 66, 26, 40, -120, 56, 26, 39, -120, 57, 26, -82, 84, -83, 0,
115 /* 2063 */ 65, -40, 68, 26, 39, -120, 57, 26, -82, 84, -83, 0,
116 /* 2075 */ -74, 33, 63, 2, 63, -38, 120, -81, 1, -39, 65, 26, -79, 55, 26, 40, -120, 56, 26, 39, -120, 83, -82, 0,
117 /* 2099 */ -73, 33, 63, 2, 63, -38, 120, -81, 1, -39, 65, 26, -79, 55, 26, 40, -120, 56, 26, 39, -120, 83, -82, 0,
118 /* 2123 */ 65, -39, 67, 26, -80, 56, 26, 39, -120, 83, -82, 0,
119 /* 2135 */ -75, 33, 63, 2, 144, -81, 1, -39, 40, -39, 65, 26, 41, -120, 55, 26, 40, -120, 56, 26, -81, 83, -82, 0,
120 /* 2159 */ -74, 33, 63, 2, 144, -81, 1, -39, 40, -39, 65, 26, 41, -120, 55, 26, 40, -120, 56, 26, -81, 83, -82, 0,
121 /* 2183 */ 65, -39, 67, 26, 40, -120, 56, 26, -81, 83, -82, 0,
122 /* 2195 */ -239, 81, 1, -81, 0,
123 /* 2200 */ -72, 34, 62, 2, 63, -37, 120, -82, 1, -38, 64, 2, 26, 41, -120, 55, 26, 40, -120, 82, -81, 0,
124 /* 2222 */ -71, 34, 62, 2, 63, -37, 120, -82, 1, -38, 64, 2, 26, 41, -120, 55, 26, 40, -120, 82, -81, 0,
125 /* 2244 */ 65, -38, 66, 26, -79, 55, 26, 40, -120, 82, -81, 0,
126 /* 2256 */ -73, 34, 62, 2, 145, -82, 1, -38, 39, -38, 64, 26, 42, -120, 54, 26, 41, -120, 55, 26, -80, 82, -81, 0,
127 /* 2280 */ -72, 34, 62, 2, 145, -82, 1, -38, 39, -38, 64, 26, 42, -120, 54, 26, 41, -120, 55, 26, -80, 82, -81, 0,
128 /* 2304 */ 65, -38, 66, 26, 41, -120, 55, 26, -80, 82, -81, 0,
129 /* 2316 */ -98, 81, 1, -80, 0,
130 /* 2321 */ -70, 35, 61, 2, 63, -36, 120, -83, 1, -37, 65, 2, 26, 40, 1, -120, 81, -80, 0,
131 /* 2340 */ -69, 35, 61, 2, 63, -36, 120, -83, 1, -37, 65, 2, 26, 40, 1, -120, 81, -80, 0,
132 /* 2359 */ 65, -37, 65, 2, 26, 41, -120, 81, -80, 0,
133 /* 2369 */ -71, 35, 61, 2, 146, -83, 1, -37, 38, -37, 63, 2, 26, 41, 1, -120, 54, 26, -79, 81, -80, 0,
134 /* 2391 */ -70, 35, 61, 2, 146, -83, 1, -37, 38, -37, 63, 2, 26, 41, 1, -120, 54, 26, -79, 81, -80, 0,
135 /* 2413 */ 65, -37, 65, 26, 42, -120, 54, 26, -79, 81, -80, 0,
136 /* 2425 */ -98, 80, 1, -79, 0,
137 /* 2430 */ 28, -79, 0,
138 /* 2433 */ -69, 36, 60, 2, 147, -84, 1, -36, 37, -36, 64, 2, 26, 41, -119, 80, -79, 0,
139 /* 2451 */ -68, 36, 60, 2, 147, -84, 1, -36, 37, -36, 64, 2, 26, 41, -119, 80, -79, 0,
140 /* 2469 */ 65, -36, 64, 2, 26, 41, -119, 80, -79, 0,
141 /* 2479 */ 26, -78, 80, -79, 0,
142 /* 2484 */ -67, 37, 61, 65, -35, 65, 28, -78, 0,
143 /* 2493 */ -66, 37, 61, 65, -35, 65, 28, -78, 0,
144 /* 2502 */ -163, 1, 1, 230, -134, -75, 0,
145 /* 2509 */ -163, 1, 1, 231, -135, -74, 0,
146 /* 2516 */ -163, 1, 1, 232, -136, -73, 0,
147 /* 2523 */ -163, 1, 1, 233, -137, -72, 0,
148 /* 2530 */ -163, 1, 1, 234, -138, -71, 0,
149 /* 2537 */ -163, 1, 1, 235, -139, -70, 0,
150 /* 2544 */ -163, 1, 1, 236, -140, -69, 0,
151 /* 2551 */ -97, -69, 0,
152 /* 2554 */ -163, 81, 1, -81, 1, 237, -141, -68, 0,
153 /* 2563 */ -163, 79, 1, -79, 80, 1, -80, 81, 1, 156, -142, -67, 0,
154 /* 2576 */ -163, 77, 1, -77, 78, 1, -78, 79, 1, 159, -143, -66, 0,
155 /* 2589 */ -163, 75, 1, -75, 76, 1, -76, 77, 1, 162, -144, -65, 0,
156 /* 2602 */ -163, 73, 1, -73, 74, 1, -74, 75, 1, 165, -145, -64, 0,
157 /* 2615 */ -163, 71, 1, -71, 72, 1, -72, 73, 1, 168, -146, -63, 0,
158 /* 2628 */ -163, 69, 1, -69, 70, 1, -70, 71, 1, 171, -147, -62, 0,
159 /* 2641 */ -163, 67, 1, -67, 68, 1, -68, 69, 1, 174, -148, -61, 0,
160 /* 2654 */ -238, 1, 0,
161 /* 2657 */ -237, 1, 0,
162 /* 2660 */ -236, 1, 0,
163 /* 2663 */ -235, 1, 0,
164 /* 2666 */ -234, 1, 0,
165 /* 2669 */ -233, 1, 0,
166 /* 2672 */ -232, 1, 0,
167 /* 2675 */ -83, 1, -37, 133, 1, -120, 1, 0,
168 /* 2683 */ -72, 1, -48, 133, -120, 121, -120, 1, 0,
169 /* 2692 */ -73, 1, -47, 133, -120, 121, -120, 1, 0,
170 /* 2701 */ -74, 1, -46, 133, -120, 121, -120, 1, 0,
171 /* 2710 */ -75, 1, -45, 133, -120, 121, -120, 1, 0,
172 /* 2719 */ -76, 1, -44, 133, -120, 121, -120, 1, 0,
173 /* 2728 */ -77, 1, -43, 133, -120, 121, -120, 1, 0,
174 /* 2737 */ -78, 1, -42, 133, -120, 121, -120, 1, 0,
175 /* 2746 */ -79, 1, -41, 133, -120, 121, -120, 1, 0,
176 /* 2755 */ -80, 1, -40, 133, -120, 121, -120, 1, 0,
177 /* 2764 */ -81, 1, -39, 133, -120, 121, -120, 1, 0,
178 /* 2773 */ -82, 1, -38, 133, -120, 121, -120, 1, 0,
179 /* 2782 */ 138, -48, 49, -48, 12, 121, -120, 1, 0,
180 /* 2791 */ -48, 13, 121, -120, 1, 0,
181 /* 2797 */ -47, 13, 121, -120, 1, 0,
182 /* 2803 */ -46, 13, 121, -120, 1, 0,
183 /* 2809 */ -45, 13, 121, -120, 1, 0,
184 /* 2815 */ -44, 13, 121, -120, 1, 0,
185 /* 2821 */ -43, 13, 121, -120, 1, 0,
186 /* 2827 */ -42, 13, 121, -120, 1, 0,
187 /* 2833 */ -41, 13, 121, -120, 1, 0,
188 /* 2839 */ -40, 13, 121, -120, 1, 0,
189 /* 2845 */ -39, 13, 121, -120, 1, 0,
190 /* 2851 */ -38, 13, 121, -120, 1, 0,
191 /* 2857 */ -48, 133, -120, 1, 0,
192 /* 2862 */ -37, 134, -120, 1, 0,
193 /* 2867 */ 126, -36, 37, -36, 133, -119, 1, 0,
194 /* 2875 */ -103, 1, 0,
195 /* 2878 */ -102, 1, 0,
196 /* 2881 */ -101, 1, 0,
197 /* 2884 */ -100, 1, 0,
198 /* 2887 */ -99, 1, 0,
199 /* 2890 */ -98, 1, 0,
200 /* 2893 */ -29, 1, 0,
201 /* 2896 */ -28, 1, 0,
202 /* 2899 */ -27, 1, 0,
203 /* 2902 */ -26, 1, 0,
204 /* 2905 */ -25, 1, 0,
205 /* 2908 */ -24, 1, 0,
206 /* 2911 */ -23, 1, 0,
207 /* 2914 */ -22, 1, 0,
208 /* 2917 */ 137, -47, 48, -47, 12, 121, -120, 1, 1, 0,
209 /* 2927 */ 136, -46, 47, -46, 12, 121, -120, 1, 1, 0,
210 /* 2937 */ 135, -45, 46, -45, 12, 121, -120, 1, 1, 0,
211 /* 2947 */ 134, -44, 45, -44, 12, 121, -120, 1, 1, 0,
212 /* 2957 */ 133, -43, 44, -43, 12, 121, -120, 1, 1, 0,
213 /* 2967 */ 132, -42, 43, -42, 12, 121, -120, 1, 1, 0,
214 /* 2977 */ 131, -41, 42, -41, 12, 121, -120, 1, 1, 0,
215 /* 2987 */ 130, -40, 41, -40, 12, 121, -120, 1, 1, 0,
216 /* 2997 */ 129, -39, 40, -39, 12, 121, -120, 1, 1, 0,
217 /* 3007 */ 128, -38, 39, -38, 12, 121, -120, 1, 1, 0,
218 /* 3017 */ -47, 133, -120, 1, 1, 0,
219 /* 3023 */ -46, 133, -120, 1, 1, 0,
220 /* 3029 */ -45, 133, -120, 1, 1, 0,
221 /* 3035 */ -44, 133, -120, 1, 1, 0,
222 /* 3041 */ -43, 133, -120, 1, 1, 0,
223 /* 3047 */ -42, 133, -120, 1, 1, 0,
224 /* 3053 */ -41, 133, -120, 1, 1, 0,
225 /* 3059 */ -40, 133, -120, 1, 1, 0,
226 /* 3065 */ -39, 133, -120, 1, 1, 0,
227 /* 3071 */ -38, 133, -120, 1, 1, 0,
228 /* 3077 */ 127, -37, 38, -37, 133, -120, 1, 1, 0,
229 /* 3086 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
230 /* 3102 */ 13, 1, 1, 0,
231 /* 3106 */ 1, 3, 1, 3, 1, 3, 1, 0,
232 /* 3114 */ 13, 1, 0,
233 /* 3117 */ 14, 1, 0,
234 /* 3120 */ 66, 1, 0,
235 /* 3123 */ -37, 66, 1, -66, 67, 1, 0,
236 /* 3130 */ -246, 67, 1, -67, 68, 1, 0,
237 /* 3137 */ -98, 66, 1, -65, 68, 1, 0,
238 /* 3144 */ -36, 68, 1, -68, 69, 1, 0,
239 /* 3151 */ -98, 67, 1, -66, 69, 1, 0,
240 /* 3158 */ -245, 69, 1, -69, 70, 1, 0,
241 /* 3165 */ -98, 68, 1, -67, 70, 1, 0,
242 /* 3172 */ -35, 70, 1, -70, 71, 1, 0,
243 /* 3179 */ -98, 69, 1, -68, 71, 1, 0,
244 /* 3186 */ -244, 71, 1, -71, 72, 1, 0,
245 /* 3193 */ -98, 70, 1, -69, 72, 1, 0,
246 /* 3200 */ -34, 72, 1, -72, 73, 1, 0,
247 /* 3207 */ -98, 71, 1, -70, 73, 1, 0,
248 /* 3214 */ -243, 73, 1, -73, 74, 1, 0,
249 /* 3221 */ -98, 72, 1, -71, 74, 1, 0,
250 /* 3228 */ -33, 74, 1, -74, 75, 1, 0,
251 /* 3235 */ -98, 73, 1, -72, 75, 1, 0,
252 /* 3242 */ -242, 75, 1, -75, 76, 1, 0,
253 /* 3249 */ -98, 74, 1, -73, 76, 1, 0,
254 /* 3256 */ -32, 76, 1, -76, 77, 1, 0,
255 /* 3263 */ -98, 75, 1, -74, 77, 1, 0,
256 /* 3270 */ -241, 77, 1, -77, 78, 1, 0,
257 /* 3277 */ -98, 76, 1, -75, 78, 1, 0,
258 /* 3284 */ -31, 78, 1, -78, 79, 1, 0,
259 /* 3291 */ -98, 77, 1, -76, 79, 1, 0,
260 /* 3298 */ -240, 79, 1, -79, 80, 1, 0,
261 /* 3305 */ -98, 78, 1, -77, 80, 1, 0,
262 /* 3312 */ -30, 80, 1, -80, 81, 1, 0,
263 /* 3319 */ -98, 79, 1, -78, 81, 1, 0,
264 /* 3326 */ -98, 2, 0,
265 /* 3329 */ 1, 3, 1, 3, 1, 2, 0,
266 /* 3336 */ 1, 3, 1, 2, 2, 0,
267 /* 3342 */ 1, 2, 2, 2, 0,
268 /* 3347 */ 1, 3, 2, 2, 0,
269 /* 3352 */ 1, 3, 1, 3, 2, 0,
270 /* 3358 */ -193, 77, 1, -76, 79, 1, -78, 81, 1, 12, 2, 0,
271 /* 3370 */ -193, 76, 1, -75, 78, 1, -77, 80, 1, 13, 2, 0,
272 /* 3382 */ -193, 75, 1, -74, 77, 1, -76, 79, 1, 14, 2, 0,
273 /* 3394 */ -193, 74, 1, -73, 76, 1, -75, 78, 1, 15, 2, 0,
274 /* 3406 */ -193, 73, 1, -72, 75, 1, -74, 77, 1, 16, 2, 0,
275 /* 3418 */ -193, 72, 1, -71, 74, 1, -73, 76, 1, 17, 2, 0,
276 /* 3430 */ -193, 71, 1, -70, 73, 1, -72, 75, 1, 18, 2, 0,
277 /* 3442 */ -193, 70, 1, -69, 72, 1, -71, 74, 1, 19, 2, 0,
278 /* 3454 */ -193, 69, 1, -68, 71, 1, -70, 73, 1, 20, 2, 0,
279 /* 3466 */ -193, 68, 1, -67, 70, 1, -69, 72, 1, 21, 2, 0,
280 /* 3478 */ -193, 67, 1, -66, 69, 1, -68, 71, 1, 22, 2, 0,
281 /* 3490 */ -193, 66, 1, -65, 68, 1, -67, 70, 1, 23, 2, 0,
282 /* 3502 */ -193, 79, 1, -78, 81, 1, -80, 94, 2, 0,
283 /* 3512 */ -193, 78, 1, -77, 80, 1, -79, 94, 2, 0,
284 /* 3522 */ -193, 81, 1, -80, 2, 94, 2, 0,
285 /* 3530 */ -193, 80, 1, -79, 2, 94, 2, 0,
286 /* 3538 */ -193, 2, 2, 94, 2, 0,
287 /* 3544 */ 1, 3, 1, 3, 1, 3, 0,
288 /* 3551 */ 140, -50, 13, 0,
289 /* 3555 */ 126, -35, 15, 0,
290 /* 3559 */ -91, -23, 1, 23, -22, 1, 95, 65, -64, 65, 69, 0,
291 /* 3571 */ -91, -24, 1, 24, -23, 1, 95, 65, -64, 65, 70, 0,
292 /* 3583 */ -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, 0,
293 /* 3595 */ -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, 0,
294 /* 3607 */ -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, 0,
295 /* 3619 */ -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, 0,
296 /* 3631 */ -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, 0,
297 /* 3643 */ -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, 0,
298 /* 3659 */ -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, 0,
299 /* 3679 */ -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, 0,
300 /* 3699 */ -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, 0,
301 /* 3719 */ -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, 0,
302 /* 3739 */ -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, 0,
303 /* 3759 */ -91, -36, 68, 1, -68, 69, 1, -34, -35, 70, 1, -70, 71, 1, 23, 65, -64, 65, 82, 0,
304 /* 3779 */ -91, -37, 66, 1, -66, 67, 1, -31, -36, 68, 1, -68, 69, 1, 25, 65, -64, 65, 83, 0,
305 /* 3799 */ 97, 0,
306 /* 3801 */ 98, 0,
307 /* 3803 */ 99, 0,
308 /* 3805 */ 100, 0,
309 /* 3807 */ 101, 0,
310 /* 3809 */ 102, 0,
311 /* 3811 */ 103, 0,
312 /* 3813 */ -163, 1, 1, 21, 75, 135, 0,
313 /* 3820 */ -163, 1, 1, 22, 74, 136, 0,
314 /* 3827 */ -163, 1, 1, 23, 73, 137, 0,
315 /* 3834 */ -163, 1, 1, 24, 72, 138, 0,
316 /* 3841 */ -163, 1, 1, 25, 71, 139, 0,
317 /* 3848 */ -163, 1, 1, 26, 70, 140, 0,
318 /* 3855 */ -163, 1, 1, 27, 69, 141, 0,
319 /* 3862 */ -163, 80, 1, -80, 81, 1, -81, 28, 68, 142, 0,
320 /* 3873 */ -163, 78, 1, -78, 79, 1, -79, 80, 1, -52, 67, 143, 0,
321 /* 3886 */ -163, 76, 1, -76, 77, 1, -77, 78, 1, -49, 66, 144, 0,
322 /* 3899 */ -163, 74, 1, -74, 75, 1, -75, 76, 1, -46, 65, 145, 0,
323 /* 3912 */ -163, 72, 1, -72, 73, 1, -73, 74, 1, -43, 64, 146, 0,
324 /* 3925 */ -163, 70, 1, -70, 71, 1, -71, 72, 1, -40, 63, 147, 0,
325 /* 3938 */ -163, 68, 1, -68, 69, 1, -69, 70, 1, -37, 62, 148, 0,
326 /* 3951 */ -163, 66, 1, -66, 67, 1, -67, 68, 1, -34, 61, 149, 0,
327 /* 3964 */ 166, 0,
328};
329
330extern const LaneBitmask ARMLaneMaskLists[] = {
331 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
332 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002),
333 /* 4 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
334 /* 6 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020),
335 /* 10 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000030),
336 /* 13 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030),
337 /* 15 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080),
338 /* 19 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080),
339 /* 25 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x00000000000000C0),
340 /* 28 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x00000000000000C0),
341 /* 30 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x00000000000000C0),
342 /* 35 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0),
343 /* 39 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0),
344 /* 42 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200),
345 /* 50 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000300),
346 /* 57 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300),
347 /* 63 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300),
348 /* 68 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300),
349 /* 72 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800),
350 /* 78 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000C00),
351 /* 83 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00),
352 /* 87 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00),
353 /* 90 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000),
354 /* 98 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x000000000000C000),
355 /* 105 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000C00), LaneBitmask(0x000000000000C000),
356 /* 111 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00), LaneBitmask(0x000000000000C000),
357 /* 116 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00), LaneBitmask(0x000000000000C000),
358 /* 120 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000020000),
359 /* 136 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
360 /* 150 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000C00), LaneBitmask(0x0000000000003000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
361 /* 162 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300), LaneBitmask(0x0000000000000C00), LaneBitmask(0x0000000000003000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
362 /* 172 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300), LaneBitmask(0x0000000000000C00), LaneBitmask(0x0000000000003000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
363 /* 180 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF),
364};
365
366extern const uint16_t ARMSubRegIdxLists[] = {
367 /* 0 */ 1, 2,
368 /* 2 */ 1, 17, 18, 2,
369 /* 6 */ 1, 3,
370 /* 8 */ 1, 17, 18, 3,
371 /* 12 */ 9, 10,
372 /* 14 */ 17, 18,
373 /* 16 */ 1, 17, 18, 2, 19, 20,
374 /* 22 */ 1, 17, 18, 3, 21, 22,
375 /* 28 */ 1, 2, 3, 13, 33, 37,
376 /* 34 */ 1, 17, 18, 2, 3, 13, 33, 37,
377 /* 42 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37,
378 /* 52 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37,
379 /* 64 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37,
380 /* 75 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37,
381 /* 90 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37,
382 /* 101 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37,
383 /* 114 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37,
384 /* 131 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37,
385 /* 150 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37,
386 /* 169 */ 1, 3, 5, 33, 43,
387 /* 174 */ 1, 17, 18, 3, 5, 33, 43,
388 /* 181 */ 1, 17, 18, 3, 21, 22, 5, 33, 43,
389 /* 190 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43,
390 /* 201 */ 1, 3, 5, 7, 33, 38, 43, 45, 51,
391 /* 210 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51,
392 /* 221 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51,
393 /* 234 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51,
394 /* 249 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51,
395 /* 266 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
396 /* 304 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
397 /* 346 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
398 /* 392 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
399 /* 442 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
400};
401
402
403#ifdef __GNUC__
404#pragma GCC diagnostic push
405#pragma GCC diagnostic ignored "-Woverlength-strings"
406#endif
407extern const char ARMRegStrings[] = {
408 /* 0 */ "D4_D6_D8_D10\000"
409 /* 13 */ "D7_D8_D9_D10\000"
410 /* 26 */ "Q7_Q8_Q9_Q10\000"
411 /* 39 */ "R10\000"
412 /* 43 */ "S10\000"
413 /* 47 */ "D14_D16_D18_D20\000"
414 /* 63 */ "D17_D18_D19_D20\000"
415 /* 79 */ "S20\000"
416 /* 83 */ "D24_D26_D28_D30\000"
417 /* 99 */ "D27_D28_D29_D30\000"
418 /* 115 */ "S30\000"
419 /* 119 */ "D0\000"
420 /* 122 */ "P0\000"
421 /* 125 */ "Q0\000"
422 /* 128 */ "MVFR0\000"
423 /* 134 */ "S0\000"
424 /* 137 */ "D9_D10_D11\000"
425 /* 148 */ "D5_D7_D9_D11\000"
426 /* 161 */ "Q8_Q9_Q10_Q11\000"
427 /* 175 */ "R10_R11\000"
428 /* 183 */ "S11\000"
429 /* 187 */ "D19_D20_D21\000"
430 /* 199 */ "D15_D17_D19_D21\000"
431 /* 215 */ "S21\000"
432 /* 219 */ "D29_D30_D31\000"
433 /* 231 */ "D25_D27_D29_D31\000"
434 /* 247 */ "S31\000"
435 /* 251 */ "D1\000"
436 /* 254 */ "Q0_Q1\000"
437 /* 260 */ "MVFR1\000"
438 /* 266 */ "R0_R1\000"
439 /* 272 */ "S1\000"
440 /* 275 */ "D6_D8_D10_D12\000"
441 /* 289 */ "D9_D10_D11_D12\000"
442 /* 304 */ "Q9_Q10_Q11_Q12\000"
443 /* 319 */ "R12\000"
444 /* 323 */ "S12\000"
445 /* 327 */ "D16_D18_D20_D22\000"
446 /* 343 */ "D19_D20_D21_D22\000"
447 /* 359 */ "S22\000"
448 /* 363 */ "D0_D2\000"
449 /* 369 */ "D0_D1_D2\000"
450 /* 378 */ "Q1_Q2\000"
451 /* 384 */ "MVFR2\000"
452 /* 390 */ "S2\000"
453 /* 393 */ "FPINST2\000"
454 /* 401 */ "D7_D9_D11_D13\000"
455 /* 415 */ "D11_D12_D13\000"
456 /* 427 */ "Q10_Q11_Q12_Q13\000"
457 /* 443 */ "S13\000"
458 /* 447 */ "D17_D19_D21_D23\000"
459 /* 463 */ "D21_D22_D23\000"
460 /* 475 */ "S23\000"
461 /* 479 */ "D1_D3\000"
462 /* 485 */ "D1_D2_D3\000"
463 /* 494 */ "Q0_Q1_Q2_Q3\000"
464 /* 506 */ "R2_R3\000"
465 /* 512 */ "S3\000"
466 /* 515 */ "D8_D10_D12_D14\000"
467 /* 530 */ "D11_D12_D13_D14\000"
468 /* 546 */ "Q11_Q12_Q13_Q14\000"
469 /* 562 */ "S14\000"
470 /* 566 */ "D18_D20_D22_D24\000"
471 /* 582 */ "D21_D22_D23_D24\000"
472 /* 598 */ "S24\000"
473 /* 602 */ "D0_D2_D4\000"
474 /* 611 */ "D1_D2_D3_D4\000"
475 /* 623 */ "Q1_Q2_Q3_Q4\000"
476 /* 635 */ "R4\000"
477 /* 638 */ "S4\000"
478 /* 641 */ "D9_D11_D13_D15\000"
479 /* 656 */ "D13_D14_D15\000"
480 /* 668 */ "Q12_Q13_Q14_Q15\000"
481 /* 684 */ "S15\000"
482 /* 688 */ "D19_D21_D23_D25\000"
483 /* 704 */ "D23_D24_D25\000"
484 /* 716 */ "S25\000"
485 /* 720 */ "D1_D3_D5\000"
486 /* 729 */ "D3_D4_D5\000"
487 /* 738 */ "Q2_Q3_Q4_Q5\000"
488 /* 750 */ "R4_R5\000"
489 /* 756 */ "S5\000"
490 /* 759 */ "D10_D12_D14_D16\000"
491 /* 775 */ "D13_D14_D15_D16\000"
492 /* 791 */ "S16\000"
493 /* 795 */ "D20_D22_D24_D26\000"
494 /* 811 */ "D23_D24_D25_D26\000"
495 /* 827 */ "S26\000"
496 /* 831 */ "D0_D2_D4_D6\000"
497 /* 843 */ "D3_D4_D5_D6\000"
498 /* 855 */ "Q3_Q4_Q5_Q6\000"
499 /* 867 */ "R6\000"
500 /* 870 */ "S6\000"
501 /* 873 */ "D11_D13_D15_D17\000"
502 /* 889 */ "D15_D16_D17\000"
503 /* 901 */ "S17\000"
504 /* 905 */ "D21_D23_D25_D27\000"
505 /* 921 */ "D25_D26_D27\000"
506 /* 933 */ "S27\000"
507 /* 937 */ "D1_D3_D5_D7\000"
508 /* 949 */ "D5_D6_D7\000"
509 /* 958 */ "Q4_Q5_Q6_Q7\000"
510 /* 970 */ "R6_R7\000"
511 /* 976 */ "S7\000"
512 /* 979 */ "D12_D14_D16_D18\000"
513 /* 995 */ "D15_D16_D17_D18\000"
514 /* 1011 */ "S18\000"
515 /* 1015 */ "D22_D24_D26_D28\000"
516 /* 1031 */ "D25_D26_D27_D28\000"
517 /* 1047 */ "S28\000"
518 /* 1051 */ "D2_D4_D6_D8\000"
519 /* 1063 */ "D5_D6_D7_D8\000"
520 /* 1075 */ "Q5_Q6_Q7_Q8\000"
521 /* 1087 */ "R8\000"
522 /* 1090 */ "S8\000"
523 /* 1093 */ "D13_D15_D17_D19\000"
524 /* 1109 */ "D17_D18_D19\000"
525 /* 1121 */ "S19\000"
526 /* 1125 */ "D23_D25_D27_D29\000"
527 /* 1141 */ "D27_D28_D29\000"
528 /* 1153 */ "S29\000"
529 /* 1157 */ "D3_D5_D7_D9\000"
530 /* 1169 */ "D7_D8_D9\000"
531 /* 1178 */ "Q6_Q7_Q8_Q9\000"
532 /* 1190 */ "R8_R9\000"
533 /* 1196 */ "S9\000"
534 /* 1199 */ "PC\000"
535 /* 1202 */ "FPSCR_NZCVQC\000"
536 /* 1215 */ "FPEXC\000"
537 /* 1221 */ "FPSID\000"
538 /* 1227 */ "RA_AUTH_CODE\000"
539 /* 1240 */ "ITSTATE\000"
540 /* 1248 */ "FPSCR_RM\000"
541 /* 1257 */ "R12_SP\000"
542 /* 1264 */ "FPSCR\000"
543 /* 1270 */ "LR\000"
544 /* 1273 */ "VPR\000"
545 /* 1277 */ "APSR\000"
546 /* 1282 */ "CPSR\000"
547 /* 1287 */ "SPSR\000"
548 /* 1292 */ "ZR\000"
549 /* 1295 */ "FPCXTNS\000"
550 /* 1303 */ "FPCXTS\000"
551 /* 1310 */ "FPINST\000"
552 /* 1317 */ "FPSCR_NZCV\000"
553 /* 1328 */ "APSR_NZCV\000"
554};
555#ifdef __GNUC__
556#pragma GCC diagnostic pop
557#endif
558
559extern const MCRegisterDesc ARMRegDesc[] = { // Descriptors
560 { .Name: 12, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
561 { .Name: 1277, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45056, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
562 { .Name: 1328, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45057, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
563 { .Name: 1282, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45058, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
564 { .Name: 1295, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45059, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
565 { .Name: 1303, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45060, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
566 { .Name: 1215, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45061, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
567 { .Name: 1310, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45062, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
568 { .Name: 1264, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 11976711, .RegUnitLaneMasks: 180, .IsConstant: 0, .IsArtificial: 0 },
569 { .Name: 1317, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 13627400, .RegUnitLaneMasks: 181, .IsConstant: 0, .IsArtificial: 0 },
570 { .Name: 1202, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45067, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
571 { .Name: 1248, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 14536713, .RegUnitLaneMasks: 181, .IsConstant: 0, .IsArtificial: 0 },
572 { .Name: 1221, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45069, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
573 { .Name: 1240, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45070, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
574 { .Name: 1270, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45071, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
575 { .Name: 1199, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45072, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
576 { .Name: 1227, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45073, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
577 { .Name: 1261, .SubRegs: 11, .SuperRegs: 3964, .SubRegIndices: 2, .RegUnits: 45074, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
578 { .Name: 1287, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45075, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
579 { .Name: 1273, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45076, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
580 { .Name: 1292, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45077, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
581 { .Name: 119, .SubRegs: 3120, .SuperRegs: 2485, .SubRegIndices: 14, .RegUnits: 10874902, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
582 { .Name: 251, .SubRegs: 3127, .SuperRegs: 951, .SubRegIndices: 14, .RegUnits: 10874904, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
583 { .Name: 366, .SubRegs: 3134, .SuperRegs: 2434, .SubRegIndices: 14, .RegUnits: 10874906, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
584 { .Name: 482, .SubRegs: 3148, .SuperRegs: 2322, .SubRegIndices: 14, .RegUnits: 10874908, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
585 { .Name: 608, .SubRegs: 3162, .SuperRegs: 2370, .SubRegIndices: 14, .RegUnits: 10874910, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
586 { .Name: 726, .SubRegs: 3176, .SuperRegs: 2201, .SubRegIndices: 14, .RegUnits: 10874912, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
587 { .Name: 840, .SubRegs: 3190, .SuperRegs: 2257, .SubRegIndices: 14, .RegUnits: 10874914, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
588 { .Name: 946, .SubRegs: 3204, .SuperRegs: 2076, .SubRegIndices: 14, .RegUnits: 10874916, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
589 { .Name: 1060, .SubRegs: 3218, .SuperRegs: 2136, .SubRegIndices: 14, .RegUnits: 10874918, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
590 { .Name: 1166, .SubRegs: 3232, .SuperRegs: 1956, .SubRegIndices: 14, .RegUnits: 10874920, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
591 { .Name: 9, .SubRegs: 3246, .SuperRegs: 2016, .SubRegIndices: 14, .RegUnits: 10874922, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
592 { .Name: 144, .SubRegs: 3260, .SuperRegs: 1836, .SubRegIndices: 14, .RegUnits: 10874924, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
593 { .Name: 285, .SubRegs: 3274, .SuperRegs: 1896, .SubRegIndices: 14, .RegUnits: 10874926, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
594 { .Name: 411, .SubRegs: 3288, .SuperRegs: 1716, .SubRegIndices: 14, .RegUnits: 10874928, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
595 { .Name: 526, .SubRegs: 3302, .SuperRegs: 1776, .SubRegIndices: 14, .RegUnits: 10874930, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
596 { .Name: 652, .SubRegs: 3316, .SuperRegs: 1621, .SubRegIndices: 14, .RegUnits: 10874932, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
597 { .Name: 771, .SubRegs: 11, .SuperRegs: 1680, .SubRegIndices: 2, .RegUnits: 45110, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
598 { .Name: 885, .SubRegs: 11, .SuperRegs: 1550, .SubRegIndices: 2, .RegUnits: 45111, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
599 { .Name: 991, .SubRegs: 11, .SuperRegs: 1585, .SubRegIndices: 2, .RegUnits: 45112, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
600 { .Name: 1105, .SubRegs: 11, .SuperRegs: 1480, .SubRegIndices: 2, .RegUnits: 45113, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
601 { .Name: 59, .SubRegs: 11, .SuperRegs: 1515, .SubRegIndices: 2, .RegUnits: 45114, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
602 { .Name: 195, .SubRegs: 11, .SuperRegs: 1410, .SubRegIndices: 2, .RegUnits: 45115, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
603 { .Name: 339, .SubRegs: 11, .SuperRegs: 1445, .SubRegIndices: 2, .RegUnits: 45116, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
604 { .Name: 459, .SubRegs: 11, .SuperRegs: 1340, .SubRegIndices: 2, .RegUnits: 45117, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
605 { .Name: 578, .SubRegs: 11, .SuperRegs: 1375, .SubRegIndices: 2, .RegUnits: 45118, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
606 { .Name: 700, .SubRegs: 11, .SuperRegs: 1269, .SubRegIndices: 2, .RegUnits: 45119, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
607 { .Name: 807, .SubRegs: 11, .SuperRegs: 1309, .SubRegIndices: 2, .RegUnits: 45120, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
608 { .Name: 917, .SubRegs: 11, .SuperRegs: 835, .SubRegIndices: 2, .RegUnits: 45121, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
609 { .Name: 1027, .SubRegs: 11, .SuperRegs: 883, .SubRegIndices: 2, .RegUnits: 45122, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
610 { .Name: 1137, .SubRegs: 11, .SuperRegs: 856, .SubRegIndices: 2, .RegUnits: 45123, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
611 { .Name: 95, .SubRegs: 11, .SuperRegs: 901, .SubRegIndices: 2, .RegUnits: 45124, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
612 { .Name: 227, .SubRegs: 11, .SuperRegs: 1261, .SubRegIndices: 2, .RegUnits: 45125, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
613 { .Name: 393, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45126, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
614 { .Name: 128, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45127, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
615 { .Name: 260, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45128, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
616 { .Name: 384, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45129, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
617 { .Name: 122, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45130, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
618 { .Name: 125, .SubRegs: 3123, .SuperRegs: 3555, .SubRegIndices: 16, .RegUnits: 12689430, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
619 { .Name: 257, .SubRegs: 3144, .SuperRegs: 2867, .SubRegIndices: 16, .RegUnits: 12689434, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
620 { .Name: 381, .SubRegs: 3172, .SuperRegs: 3077, .SubRegIndices: 16, .RegUnits: 12689438, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
621 { .Name: 503, .SubRegs: 3200, .SuperRegs: 3007, .SubRegIndices: 16, .RegUnits: 12689442, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
622 { .Name: 632, .SubRegs: 3228, .SuperRegs: 2997, .SubRegIndices: 16, .RegUnits: 12689446, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
623 { .Name: 747, .SubRegs: 3256, .SuperRegs: 2987, .SubRegIndices: 16, .RegUnits: 12689450, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
624 { .Name: 864, .SubRegs: 3284, .SuperRegs: 2977, .SubRegIndices: 16, .RegUnits: 12689454, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
625 { .Name: 967, .SubRegs: 3312, .SuperRegs: 2967, .SubRegIndices: 16, .RegUnits: 12689458, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
626 { .Name: 1084, .SubRegs: 2893, .SuperRegs: 2957, .SubRegIndices: 0, .RegUnits: 10874934, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
627 { .Name: 1187, .SubRegs: 2896, .SuperRegs: 2947, .SubRegIndices: 0, .RegUnits: 10874936, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
628 { .Name: 35, .SubRegs: 2899, .SuperRegs: 2937, .SubRegIndices: 0, .RegUnits: 10874938, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
629 { .Name: 171, .SubRegs: 2902, .SuperRegs: 2927, .SubRegIndices: 0, .RegUnits: 10874940, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
630 { .Name: 315, .SubRegs: 2905, .SuperRegs: 2917, .SubRegIndices: 0, .RegUnits: 10874942, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
631 { .Name: 439, .SubRegs: 2908, .SuperRegs: 2782, .SubRegIndices: 0, .RegUnits: 10874944, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
632 { .Name: 558, .SubRegs: 2911, .SuperRegs: 927, .SubRegIndices: 0, .RegUnits: 10874946, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
633 { .Name: 680, .SubRegs: 2914, .SuperRegs: 3551, .SubRegIndices: 0, .RegUnits: 10874948, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
634 { .Name: 131, .SubRegs: 11, .SuperRegs: 3811, .SubRegIndices: 2, .RegUnits: 45131, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
635 { .Name: 263, .SubRegs: 11, .SuperRegs: 3809, .SubRegIndices: 2, .RegUnits: 45132, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
636 { .Name: 387, .SubRegs: 11, .SuperRegs: 3809, .SubRegIndices: 2, .RegUnits: 45133, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
637 { .Name: 509, .SubRegs: 11, .SuperRegs: 3807, .SubRegIndices: 2, .RegUnits: 45134, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
638 { .Name: 635, .SubRegs: 11, .SuperRegs: 3807, .SubRegIndices: 2, .RegUnits: 45135, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
639 { .Name: 753, .SubRegs: 11, .SuperRegs: 3805, .SubRegIndices: 2, .RegUnits: 45136, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
640 { .Name: 867, .SubRegs: 11, .SuperRegs: 3805, .SubRegIndices: 2, .RegUnits: 45137, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
641 { .Name: 973, .SubRegs: 11, .SuperRegs: 3803, .SubRegIndices: 2, .RegUnits: 45138, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
642 { .Name: 1087, .SubRegs: 11, .SuperRegs: 3803, .SubRegIndices: 2, .RegUnits: 45139, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
643 { .Name: 1193, .SubRegs: 11, .SuperRegs: 3801, .SubRegIndices: 2, .RegUnits: 45140, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
644 { .Name: 39, .SubRegs: 11, .SuperRegs: 3801, .SubRegIndices: 2, .RegUnits: 45141, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
645 { .Name: 179, .SubRegs: 11, .SuperRegs: 3799, .SubRegIndices: 2, .RegUnits: 45142, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
646 { .Name: 319, .SubRegs: 11, .SuperRegs: 3799, .SubRegIndices: 2, .RegUnits: 45143, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
647 { .Name: 134, .SubRegs: 11, .SuperRegs: 2493, .SubRegIndices: 2, .RegUnits: 45078, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
648 { .Name: 272, .SubRegs: 11, .SuperRegs: 2484, .SubRegIndices: 2, .RegUnits: 45079, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
649 { .Name: 390, .SubRegs: 11, .SuperRegs: 962, .SubRegIndices: 2, .RegUnits: 45080, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
650 { .Name: 512, .SubRegs: 11, .SuperRegs: 950, .SubRegIndices: 2, .RegUnits: 45081, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
651 { .Name: 638, .SubRegs: 11, .SuperRegs: 2451, .SubRegIndices: 2, .RegUnits: 45082, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
652 { .Name: 756, .SubRegs: 11, .SuperRegs: 2433, .SubRegIndices: 2, .RegUnits: 45083, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
653 { .Name: 870, .SubRegs: 11, .SuperRegs: 2340, .SubRegIndices: 2, .RegUnits: 45084, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
654 { .Name: 976, .SubRegs: 11, .SuperRegs: 2321, .SubRegIndices: 2, .RegUnits: 45085, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
655 { .Name: 1090, .SubRegs: 11, .SuperRegs: 2391, .SubRegIndices: 2, .RegUnits: 45086, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
656 { .Name: 1196, .SubRegs: 11, .SuperRegs: 2369, .SubRegIndices: 2, .RegUnits: 45087, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
657 { .Name: 43, .SubRegs: 11, .SuperRegs: 2222, .SubRegIndices: 2, .RegUnits: 45088, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
658 { .Name: 183, .SubRegs: 11, .SuperRegs: 2200, .SubRegIndices: 2, .RegUnits: 45089, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
659 { .Name: 323, .SubRegs: 11, .SuperRegs: 2280, .SubRegIndices: 2, .RegUnits: 45090, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
660 { .Name: 443, .SubRegs: 11, .SuperRegs: 2256, .SubRegIndices: 2, .RegUnits: 45091, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
661 { .Name: 562, .SubRegs: 11, .SuperRegs: 2099, .SubRegIndices: 2, .RegUnits: 45092, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
662 { .Name: 684, .SubRegs: 11, .SuperRegs: 2075, .SubRegIndices: 2, .RegUnits: 45093, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
663 { .Name: 791, .SubRegs: 11, .SuperRegs: 2159, .SubRegIndices: 2, .RegUnits: 45094, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
664 { .Name: 901, .SubRegs: 11, .SuperRegs: 2135, .SubRegIndices: 2, .RegUnits: 45095, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
665 { .Name: 1011, .SubRegs: 11, .SuperRegs: 1979, .SubRegIndices: 2, .RegUnits: 45096, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
666 { .Name: 1121, .SubRegs: 11, .SuperRegs: 1955, .SubRegIndices: 2, .RegUnits: 45097, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
667 { .Name: 79, .SubRegs: 11, .SuperRegs: 2039, .SubRegIndices: 2, .RegUnits: 45098, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
668 { .Name: 215, .SubRegs: 11, .SuperRegs: 2015, .SubRegIndices: 2, .RegUnits: 45099, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
669 { .Name: 359, .SubRegs: 11, .SuperRegs: 1859, .SubRegIndices: 2, .RegUnits: 45100, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
670 { .Name: 475, .SubRegs: 11, .SuperRegs: 1835, .SubRegIndices: 2, .RegUnits: 45101, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
671 { .Name: 598, .SubRegs: 11, .SuperRegs: 1919, .SubRegIndices: 2, .RegUnits: 45102, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
672 { .Name: 716, .SubRegs: 11, .SuperRegs: 1895, .SubRegIndices: 2, .RegUnits: 45103, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
673 { .Name: 827, .SubRegs: 11, .SuperRegs: 1739, .SubRegIndices: 2, .RegUnits: 45104, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
674 { .Name: 933, .SubRegs: 11, .SuperRegs: 1715, .SubRegIndices: 2, .RegUnits: 45105, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
675 { .Name: 1047, .SubRegs: 11, .SuperRegs: 1799, .SubRegIndices: 2, .RegUnits: 45106, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
676 { .Name: 1153, .SubRegs: 11, .SuperRegs: 1775, .SubRegIndices: 2, .RegUnits: 45107, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
677 { .Name: 115, .SubRegs: 11, .SuperRegs: 1644, .SubRegIndices: 2, .RegUnits: 45108, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
678 { .Name: 247, .SubRegs: 11, .SuperRegs: 1620, .SubRegIndices: 2, .RegUnits: 45109, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
679 { .Name: 363, .SubRegs: 3137, .SuperRegs: 2487, .SubRegIndices: 22, .RegUnits: 12738582, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
680 { .Name: 479, .SubRegs: 3151, .SuperRegs: 974, .SubRegIndices: 22, .RegUnits: 12738584, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
681 { .Name: 605, .SubRegs: 3165, .SuperRegs: 2469, .SubRegIndices: 22, .RegUnits: 12738586, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
682 { .Name: 723, .SubRegs: 3179, .SuperRegs: 2359, .SubRegIndices: 22, .RegUnits: 12738588, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
683 { .Name: 837, .SubRegs: 3193, .SuperRegs: 2413, .SubRegIndices: 22, .RegUnits: 12738590, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
684 { .Name: 943, .SubRegs: 3207, .SuperRegs: 2244, .SubRegIndices: 22, .RegUnits: 12738592, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
685 { .Name: 1057, .SubRegs: 3221, .SuperRegs: 2304, .SubRegIndices: 22, .RegUnits: 12738594, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
686 { .Name: 1163, .SubRegs: 3235, .SuperRegs: 2123, .SubRegIndices: 22, .RegUnits: 12738596, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
687 { .Name: 6, .SubRegs: 3249, .SuperRegs: 2183, .SubRegIndices: 22, .RegUnits: 12738598, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
688 { .Name: 154, .SubRegs: 3263, .SuperRegs: 2003, .SubRegIndices: 22, .RegUnits: 12738600, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
689 { .Name: 281, .SubRegs: 3277, .SuperRegs: 2063, .SubRegIndices: 22, .RegUnits: 12738602, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
690 { .Name: 407, .SubRegs: 3291, .SuperRegs: 1883, .SubRegIndices: 22, .RegUnits: 12738604, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
691 { .Name: 522, .SubRegs: 3305, .SuperRegs: 1943, .SubRegIndices: 22, .RegUnits: 12738606, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
692 { .Name: 648, .SubRegs: 3319, .SuperRegs: 1763, .SubRegIndices: 22, .RegUnits: 12738608, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
693 { .Name: 767, .SubRegs: 2425, .SuperRegs: 1823, .SubRegIndices: 8, .RegUnits: 14532658, .RegUnitLaneMasks: 25, .IsConstant: 0, .IsArtificial: 0 },
694 { .Name: 881, .SubRegs: 2316, .SuperRegs: 1668, .SubRegIndices: 8, .RegUnits: 13652020, .RegUnitLaneMasks: 25, .IsConstant: 0, .IsArtificial: 0 },
695 { .Name: 987, .SubRegs: 3326, .SuperRegs: 1703, .SubRegIndices: 6, .RegUnits: 13627446, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
696 { .Name: 1101, .SubRegs: 3326, .SuperRegs: 1573, .SubRegIndices: 6, .RegUnits: 13627447, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
697 { .Name: 55, .SubRegs: 3326, .SuperRegs: 1608, .SubRegIndices: 6, .RegUnits: 13627448, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
698 { .Name: 207, .SubRegs: 3326, .SuperRegs: 1503, .SubRegIndices: 6, .RegUnits: 13627449, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
699 { .Name: 335, .SubRegs: 3326, .SuperRegs: 1538, .SubRegIndices: 6, .RegUnits: 13627450, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
700 { .Name: 455, .SubRegs: 3326, .SuperRegs: 1433, .SubRegIndices: 6, .RegUnits: 13627451, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
701 { .Name: 574, .SubRegs: 3326, .SuperRegs: 1468, .SubRegIndices: 6, .RegUnits: 13627452, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
702 { .Name: 696, .SubRegs: 3326, .SuperRegs: 1363, .SubRegIndices: 6, .RegUnits: 13627453, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
703 { .Name: 803, .SubRegs: 3326, .SuperRegs: 1398, .SubRegIndices: 6, .RegUnits: 13627454, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
704 { .Name: 913, .SubRegs: 3326, .SuperRegs: 1292, .SubRegIndices: 6, .RegUnits: 13627455, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
705 { .Name: 1023, .SubRegs: 3326, .SuperRegs: 1330, .SubRegIndices: 6, .RegUnits: 13627456, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
706 { .Name: 1133, .SubRegs: 3326, .SuperRegs: 873, .SubRegIndices: 6, .RegUnits: 13627457, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
707 { .Name: 91, .SubRegs: 3326, .SuperRegs: 912, .SubRegIndices: 6, .RegUnits: 13627458, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
708 { .Name: 239, .SubRegs: 3326, .SuperRegs: 1263, .SubRegIndices: 6, .RegUnits: 13627459, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
709 { .Name: 254, .SubRegs: 3779, .SuperRegs: 3557, .SubRegIndices: 150, .RegUnits: 12673046, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
710 { .Name: 378, .SubRegs: 3759, .SuperRegs: 3117, .SubRegIndices: 150, .RegUnits: 12673050, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
711 { .Name: 500, .SubRegs: 3739, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673054, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
712 { .Name: 629, .SubRegs: 3719, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673058, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
713 { .Name: 744, .SubRegs: 3699, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673062, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
714 { .Name: 861, .SubRegs: 3679, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673066, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
715 { .Name: 964, .SubRegs: 3659, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673070, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
716 { .Name: 1081, .SubRegs: 3643, .SuperRegs: 3102, .SubRegIndices: 75, .RegUnits: 12681266, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
717 { .Name: 1184, .SubRegs: 3631, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689462, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
718 { .Name: 32, .SubRegs: 3619, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689464, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
719 { .Name: 167, .SubRegs: 3607, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689466, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
720 { .Name: 311, .SubRegs: 3595, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689468, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
721 { .Name: 435, .SubRegs: 3583, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689470, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
722 { .Name: 554, .SubRegs: 3571, .SuperRegs: 3114, .SubRegIndices: 64, .RegUnits: 12689472, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
723 { .Name: 676, .SubRegs: 3559, .SuperRegs: 3553, .SubRegIndices: 64, .RegUnits: 12689474, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
724 { .Name: 494, .SubRegs: 628, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640278, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
725 { .Name: 623, .SubRegs: 573, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640282, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
726 { .Name: 738, .SubRegs: 518, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640286, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
727 { .Name: 855, .SubRegs: 463, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640290, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
728 { .Name: 958, .SubRegs: 408, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640294, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
729 { .Name: 1075, .SubRegs: 357, .SuperRegs: 11, .SubRegIndices: 392, .RegUnits: 12648490, .RegUnitLaneMasks: 136, .IsConstant: 0, .IsArtificial: 0 },
730 { .Name: 1178, .SubRegs: 310, .SuperRegs: 11, .SubRegIndices: 346, .RegUnits: 12656686, .RegUnitLaneMasks: 150, .IsConstant: 0, .IsArtificial: 0 },
731 { .Name: 26, .SubRegs: 267, .SuperRegs: 11, .SubRegIndices: 304, .RegUnits: 12664882, .RegUnitLaneMasks: 162, .IsConstant: 0, .IsArtificial: 0 },
732 { .Name: 161, .SubRegs: 228, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673078, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
733 { .Name: 304, .SubRegs: 189, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673080, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
734 { .Name: 427, .SubRegs: 150, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673082, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
735 { .Name: 546, .SubRegs: 111, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673084, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
736 { .Name: 668, .SubRegs: 72, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673086, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
737 { .Name: 266, .SubRegs: 2875, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874955, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
738 { .Name: 506, .SubRegs: 2878, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874957, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
739 { .Name: 750, .SubRegs: 2881, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874959, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
740 { .Name: 970, .SubRegs: 2884, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874961, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
741 { .Name: 1190, .SubRegs: 2887, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874963, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
742 { .Name: 175, .SubRegs: 2890, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874965, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
743 { .Name: 1257, .SubRegs: 2551, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 14618642, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
744 { .Name: 369, .SubRegs: 3951, .SuperRegs: 3556, .SubRegIndices: 52, .RegUnits: 12681238, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
745 { .Name: 485, .SubRegs: 2641, .SuperRegs: 983, .SubRegIndices: 52, .RegUnits: 12681240, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
746 { .Name: 614, .SubRegs: 3938, .SuperRegs: 2870, .SubRegIndices: 52, .RegUnits: 12681242, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
747 { .Name: 729, .SubRegs: 2628, .SuperRegs: 2862, .SubRegIndices: 52, .RegUnits: 12681244, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
748 { .Name: 846, .SubRegs: 3925, .SuperRegs: 3080, .SubRegIndices: 52, .RegUnits: 12681246, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
749 { .Name: 949, .SubRegs: 2615, .SuperRegs: 2851, .SubRegIndices: 52, .RegUnits: 12681248, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
750 { .Name: 1066, .SubRegs: 3912, .SuperRegs: 3071, .SubRegIndices: 52, .RegUnits: 12681250, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
751 { .Name: 1169, .SubRegs: 2602, .SuperRegs: 2845, .SubRegIndices: 52, .RegUnits: 12681252, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
752 { .Name: 16, .SubRegs: 3899, .SuperRegs: 3065, .SubRegIndices: 52, .RegUnits: 12681254, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
753 { .Name: 137, .SubRegs: 2589, .SuperRegs: 2839, .SubRegIndices: 52, .RegUnits: 12681256, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
754 { .Name: 292, .SubRegs: 3886, .SuperRegs: 3059, .SubRegIndices: 52, .RegUnits: 12681258, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
755 { .Name: 415, .SubRegs: 2576, .SuperRegs: 2833, .SubRegIndices: 52, .RegUnits: 12681260, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
756 { .Name: 534, .SubRegs: 3873, .SuperRegs: 3053, .SubRegIndices: 52, .RegUnits: 12681262, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
757 { .Name: 656, .SubRegs: 2563, .SuperRegs: 2827, .SubRegIndices: 52, .RegUnits: 12681264, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
758 { .Name: 779, .SubRegs: 3862, .SuperRegs: 3047, .SubRegIndices: 42, .RegUnits: 12685362, .RegUnitLaneMasks: 30, .IsConstant: 0, .IsArtificial: 0 },
759 { .Name: 889, .SubRegs: 2554, .SuperRegs: 2821, .SubRegIndices: 34, .RegUnits: 12689460, .RegUnitLaneMasks: 35, .IsConstant: 0, .IsArtificial: 0 },
760 { .Name: 999, .SubRegs: 3855, .SuperRegs: 3041, .SubRegIndices: 28, .RegUnits: 11976758, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
761 { .Name: 1109, .SubRegs: 2544, .SuperRegs: 2815, .SubRegIndices: 28, .RegUnits: 11976759, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
762 { .Name: 67, .SubRegs: 3848, .SuperRegs: 3035, .SubRegIndices: 28, .RegUnits: 11976760, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
763 { .Name: 187, .SubRegs: 2537, .SuperRegs: 2809, .SubRegIndices: 28, .RegUnits: 11976761, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
764 { .Name: 347, .SubRegs: 3841, .SuperRegs: 3029, .SubRegIndices: 28, .RegUnits: 11976762, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
765 { .Name: 463, .SubRegs: 2530, .SuperRegs: 2803, .SubRegIndices: 28, .RegUnits: 11976763, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
766 { .Name: 586, .SubRegs: 3834, .SuperRegs: 3023, .SubRegIndices: 28, .RegUnits: 11976764, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
767 { .Name: 704, .SubRegs: 2523, .SuperRegs: 2797, .SubRegIndices: 28, .RegUnits: 11976765, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
768 { .Name: 815, .SubRegs: 3827, .SuperRegs: 3017, .SubRegIndices: 28, .RegUnits: 11976766, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
769 { .Name: 921, .SubRegs: 2516, .SuperRegs: 2791, .SubRegIndices: 28, .RegUnits: 11976767, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
770 { .Name: 1035, .SubRegs: 3820, .SuperRegs: 2857, .SubRegIndices: 28, .RegUnits: 11976768, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
771 { .Name: 1141, .SubRegs: 2509, .SuperRegs: 935, .SubRegIndices: 28, .RegUnits: 11976769, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
772 { .Name: 103, .SubRegs: 3813, .SuperRegs: 946, .SubRegIndices: 28, .RegUnits: 11976770, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
773 { .Name: 219, .SubRegs: 2502, .SuperRegs: 3552, .SubRegIndices: 28, .RegUnits: 11976771, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
774 { .Name: 602, .SubRegs: 3490, .SuperRegs: 2490, .SubRegIndices: 190, .RegUnits: 12730390, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
775 { .Name: 720, .SubRegs: 3478, .SuperRegs: 2430, .SubRegIndices: 190, .RegUnits: 12730392, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
776 { .Name: 834, .SubRegs: 3466, .SuperRegs: 2479, .SubRegIndices: 190, .RegUnits: 12730394, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
777 { .Name: 940, .SubRegs: 3454, .SuperRegs: 2386, .SubRegIndices: 190, .RegUnits: 12730396, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
778 { .Name: 1054, .SubRegs: 3442, .SuperRegs: 2386, .SubRegIndices: 190, .RegUnits: 12730398, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
779 { .Name: 1160, .SubRegs: 3430, .SuperRegs: 2275, .SubRegIndices: 190, .RegUnits: 12730400, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
780 { .Name: 3, .SubRegs: 3418, .SuperRegs: 2275, .SubRegIndices: 190, .RegUnits: 12730402, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
781 { .Name: 151, .SubRegs: 3406, .SuperRegs: 2154, .SubRegIndices: 190, .RegUnits: 12730404, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
782 { .Name: 278, .SubRegs: 3394, .SuperRegs: 2154, .SubRegIndices: 190, .RegUnits: 12730406, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
783 { .Name: 404, .SubRegs: 3382, .SuperRegs: 2034, .SubRegIndices: 190, .RegUnits: 12730408, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
784 { .Name: 518, .SubRegs: 3370, .SuperRegs: 2034, .SubRegIndices: 190, .RegUnits: 12730410, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
785 { .Name: 644, .SubRegs: 3358, .SuperRegs: 1914, .SubRegIndices: 190, .RegUnits: 12730412, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
786 { .Name: 763, .SubRegs: 3512, .SuperRegs: 1914, .SubRegIndices: 181, .RegUnits: 14524462, .RegUnitLaneMasks: 78, .IsConstant: 0, .IsArtificial: 0 },
787 { .Name: 877, .SubRegs: 3502, .SuperRegs: 1794, .SubRegIndices: 181, .RegUnits: 13643824, .RegUnitLaneMasks: 78, .IsConstant: 0, .IsArtificial: 0 },
788 { .Name: 983, .SubRegs: 3530, .SuperRegs: 1794, .SubRegIndices: 174, .RegUnits: 13738034, .RegUnitLaneMasks: 83, .IsConstant: 0, .IsArtificial: 0 },
789 { .Name: 1097, .SubRegs: 3522, .SuperRegs: 1698, .SubRegIndices: 174, .RegUnits: 13672500, .RegUnitLaneMasks: 83, .IsConstant: 0, .IsArtificial: 0 },
790 { .Name: 51, .SubRegs: 3538, .SuperRegs: 1698, .SubRegIndices: 169, .RegUnits: 13676598, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
791 { .Name: 203, .SubRegs: 3538, .SuperRegs: 1603, .SubRegIndices: 169, .RegUnits: 13676599, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
792 { .Name: 331, .SubRegs: 3538, .SuperRegs: 1603, .SubRegIndices: 169, .RegUnits: 13676600, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
793 { .Name: 451, .SubRegs: 3538, .SuperRegs: 1533, .SubRegIndices: 169, .RegUnits: 13676601, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
794 { .Name: 570, .SubRegs: 3538, .SuperRegs: 1533, .SubRegIndices: 169, .RegUnits: 13676602, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
795 { .Name: 692, .SubRegs: 3538, .SuperRegs: 1463, .SubRegIndices: 169, .RegUnits: 13676603, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
796 { .Name: 799, .SubRegs: 3538, .SuperRegs: 1463, .SubRegIndices: 169, .RegUnits: 13676604, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
797 { .Name: 909, .SubRegs: 3538, .SuperRegs: 1393, .SubRegIndices: 169, .RegUnits: 13676605, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
798 { .Name: 1019, .SubRegs: 3538, .SuperRegs: 1393, .SubRegIndices: 169, .RegUnits: 13676606, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
799 { .Name: 1129, .SubRegs: 3538, .SuperRegs: 1304, .SubRegIndices: 169, .RegUnits: 13676607, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
800 { .Name: 87, .SubRegs: 3538, .SuperRegs: 1327, .SubRegIndices: 169, .RegUnits: 13676608, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
801 { .Name: 235, .SubRegs: 3538, .SuperRegs: 1266, .SubRegIndices: 169, .RegUnits: 13676609, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
802 { .Name: 831, .SubRegs: 1149, .SuperRegs: 2491, .SubRegIndices: 249, .RegUnits: 12722198, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
803 { .Name: 937, .SubRegs: 1131, .SuperRegs: 2428, .SubRegIndices: 249, .RegUnits: 12722200, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
804 { .Name: 1051, .SubRegs: 1113, .SuperRegs: 2428, .SubRegIndices: 249, .RegUnits: 12722202, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
805 { .Name: 1157, .SubRegs: 1095, .SuperRegs: 2319, .SubRegIndices: 249, .RegUnits: 12722204, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
806 { .Name: 0, .SubRegs: 1077, .SuperRegs: 2319, .SubRegIndices: 249, .RegUnits: 12722206, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
807 { .Name: 148, .SubRegs: 1059, .SuperRegs: 2198, .SubRegIndices: 249, .RegUnits: 12722208, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
808 { .Name: 275, .SubRegs: 1041, .SuperRegs: 2198, .SubRegIndices: 249, .RegUnits: 12722210, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
809 { .Name: 401, .SubRegs: 1023, .SuperRegs: 2097, .SubRegIndices: 249, .RegUnits: 12722212, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
810 { .Name: 515, .SubRegs: 1005, .SuperRegs: 2097, .SubRegIndices: 249, .RegUnits: 12722214, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
811 { .Name: 641, .SubRegs: 987, .SuperRegs: 1977, .SubRegIndices: 249, .RegUnits: 12722216, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
812 { .Name: 759, .SubRegs: 1183, .SuperRegs: 1977, .SubRegIndices: 234, .RegUnits: 14516266, .RegUnitLaneMasks: 98, .IsConstant: 0, .IsArtificial: 0 },
813 { .Name: 873, .SubRegs: 1167, .SuperRegs: 1857, .SubRegIndices: 234, .RegUnits: 13635628, .RegUnitLaneMasks: 98, .IsConstant: 0, .IsArtificial: 0 },
814 { .Name: 979, .SubRegs: 1213, .SuperRegs: 1857, .SubRegIndices: 221, .RegUnits: 13729838, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
815 { .Name: 1093, .SubRegs: 1199, .SuperRegs: 1737, .SubRegIndices: 221, .RegUnits: 13664304, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
816 { .Name: 47, .SubRegs: 1239, .SuperRegs: 1737, .SubRegIndices: 210, .RegUnits: 13709362, .RegUnitLaneMasks: 111, .IsConstant: 0, .IsArtificial: 0 },
817 { .Name: 199, .SubRegs: 1227, .SuperRegs: 1642, .SubRegIndices: 210, .RegUnits: 13688884, .RegUnitLaneMasks: 111, .IsConstant: 0, .IsArtificial: 0 },
818 { .Name: 327, .SubRegs: 1251, .SuperRegs: 1642, .SubRegIndices: 201, .RegUnits: 13692982, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
819 { .Name: 447, .SubRegs: 1251, .SuperRegs: 1571, .SubRegIndices: 201, .RegUnits: 13692983, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
820 { .Name: 566, .SubRegs: 1251, .SuperRegs: 1571, .SubRegIndices: 201, .RegUnits: 13692984, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
821 { .Name: 688, .SubRegs: 1251, .SuperRegs: 1501, .SubRegIndices: 201, .RegUnits: 13692985, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
822 { .Name: 795, .SubRegs: 1251, .SuperRegs: 1501, .SubRegIndices: 201, .RegUnits: 13692986, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
823 { .Name: 905, .SubRegs: 1251, .SuperRegs: 1431, .SubRegIndices: 201, .RegUnits: 13692987, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
824 { .Name: 1015, .SubRegs: 1251, .SuperRegs: 1431, .SubRegIndices: 201, .RegUnits: 13692988, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
825 { .Name: 1125, .SubRegs: 1251, .SuperRegs: 1328, .SubRegIndices: 201, .RegUnits: 13692989, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
826 { .Name: 83, .SubRegs: 1251, .SuperRegs: 1328, .SubRegIndices: 201, .RegUnits: 13692990, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
827 { .Name: 231, .SubRegs: 1251, .SuperRegs: 1267, .SubRegIndices: 201, .RegUnits: 13692991, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
828 { .Name: 372, .SubRegs: 3130, .SuperRegs: 981, .SubRegIndices: 16, .RegUnits: 12689432, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
829 { .Name: 617, .SubRegs: 3158, .SuperRegs: 2675, .SubRegIndices: 16, .RegUnits: 12689436, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
830 { .Name: 849, .SubRegs: 3186, .SuperRegs: 2773, .SubRegIndices: 16, .RegUnits: 12689440, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
831 { .Name: 1069, .SubRegs: 3214, .SuperRegs: 2764, .SubRegIndices: 16, .RegUnits: 12689444, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
832 { .Name: 19, .SubRegs: 3242, .SuperRegs: 2755, .SubRegIndices: 16, .RegUnits: 12689448, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
833 { .Name: 296, .SubRegs: 3270, .SuperRegs: 2746, .SubRegIndices: 16, .RegUnits: 12689452, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
834 { .Name: 538, .SubRegs: 3298, .SuperRegs: 2737, .SubRegIndices: 16, .RegUnits: 12689456, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
835 { .Name: 783, .SubRegs: 2195, .SuperRegs: 2728, .SubRegIndices: 2, .RegUnits: 11976756, .RegUnitLaneMasks: 10, .IsConstant: 0, .IsArtificial: 0 },
836 { .Name: 1003, .SubRegs: 2654, .SuperRegs: 2719, .SubRegIndices: 0, .RegUnits: 10874935, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
837 { .Name: 71, .SubRegs: 2657, .SuperRegs: 2710, .SubRegIndices: 0, .RegUnits: 10874937, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
838 { .Name: 351, .SubRegs: 2660, .SuperRegs: 2701, .SubRegIndices: 0, .RegUnits: 10874939, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
839 { .Name: 590, .SubRegs: 2663, .SuperRegs: 2692, .SubRegIndices: 0, .RegUnits: 10874941, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
840 { .Name: 819, .SubRegs: 2666, .SuperRegs: 2683, .SubRegIndices: 0, .RegUnits: 10874943, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
841 { .Name: 1039, .SubRegs: 2669, .SuperRegs: 919, .SubRegIndices: 0, .RegUnits: 10874945, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
842 { .Name: 107, .SubRegs: 2672, .SuperRegs: 940, .SubRegIndices: 0, .RegUnits: 10874947, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
843 { .Name: 611, .SubRegs: 815, .SuperRegs: 960, .SubRegIndices: 131, .RegUnits: 12673048, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
844 { .Name: 843, .SubRegs: 795, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673052, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
845 { .Name: 1063, .SubRegs: 775, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673056, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
846 { .Name: 13, .SubRegs: 755, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673060, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
847 { .Name: 289, .SubRegs: 735, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673064, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
848 { .Name: 530, .SubRegs: 715, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673068, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
849 { .Name: 775, .SubRegs: 697, .SuperRegs: 2680, .SubRegIndices: 114, .RegUnits: 12677168, .RegUnitLaneMasks: 50, .IsConstant: 0, .IsArtificial: 0 },
850 { .Name: 995, .SubRegs: 683, .SuperRegs: 2680, .SubRegIndices: 101, .RegUnits: 12685364, .RegUnitLaneMasks: 63, .IsConstant: 0, .IsArtificial: 0 },
851 { .Name: 63, .SubRegs: 60, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689463, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
852 { .Name: 343, .SubRegs: 48, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689465, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
853 { .Name: 582, .SubRegs: 36, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689467, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
854 { .Name: 811, .SubRegs: 24, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689469, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
855 { .Name: 1031, .SubRegs: 12, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689471, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
856 { .Name: 99, .SubRegs: 0, .SuperRegs: 854, .SubRegIndices: 90, .RegUnits: 12689473, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
857};
858
859extern const MCPhysReg ARMRegUnitRoots[][2] = {
860 { ARM::APSR },
861 { ARM::APSR_NZCV },
862 { ARM::CPSR },
863 { ARM::FPCXTNS },
864 { ARM::FPCXTS },
865 { ARM::FPEXC },
866 { ARM::FPINST },
867 { ARM::FPSCR },
868 { ARM::FPSCR, ARM::FPSCR_NZCV },
869 { ARM::FPSCR, ARM::FPSCR_RM },
870 { ARM::FPSCR_NZCV },
871 { ARM::FPSCR_NZCVQC },
872 { ARM::FPSCR_RM },
873 { ARM::FPSID },
874 { ARM::ITSTATE },
875 { ARM::LR },
876 { ARM::PC },
877 { ARM::RA_AUTH_CODE },
878 { ARM::SP },
879 { ARM::SPSR },
880 { ARM::VPR },
881 { ARM::ZR },
882 { ARM::S0 },
883 { ARM::S1 },
884 { ARM::S2 },
885 { ARM::S3 },
886 { ARM::S4 },
887 { ARM::S5 },
888 { ARM::S6 },
889 { ARM::S7 },
890 { ARM::S8 },
891 { ARM::S9 },
892 { ARM::S10 },
893 { ARM::S11 },
894 { ARM::S12 },
895 { ARM::S13 },
896 { ARM::S14 },
897 { ARM::S15 },
898 { ARM::S16 },
899 { ARM::S17 },
900 { ARM::S18 },
901 { ARM::S19 },
902 { ARM::S20 },
903 { ARM::S21 },
904 { ARM::S22 },
905 { ARM::S23 },
906 { ARM::S24 },
907 { ARM::S25 },
908 { ARM::S26 },
909 { ARM::S27 },
910 { ARM::S28 },
911 { ARM::S29 },
912 { ARM::S30 },
913 { ARM::S31 },
914 { ARM::D16 },
915 { ARM::D17 },
916 { ARM::D18 },
917 { ARM::D19 },
918 { ARM::D20 },
919 { ARM::D21 },
920 { ARM::D22 },
921 { ARM::D23 },
922 { ARM::D24 },
923 { ARM::D25 },
924 { ARM::D26 },
925 { ARM::D27 },
926 { ARM::D28 },
927 { ARM::D29 },
928 { ARM::D30 },
929 { ARM::D31 },
930 { ARM::FPINST2 },
931 { ARM::MVFR0 },
932 { ARM::MVFR1 },
933 { ARM::MVFR2 },
934 { ARM::P0 },
935 { ARM::R0 },
936 { ARM::R1 },
937 { ARM::R2 },
938 { ARM::R3 },
939 { ARM::R4 },
940 { ARM::R5 },
941 { ARM::R6 },
942 { ARM::R7 },
943 { ARM::R8 },
944 { ARM::R9 },
945 { ARM::R10 },
946 { ARM::R11 },
947 { ARM::R12 },
948};
949
950namespace { // Register classes...
951 // HPR Register Class...
952 const MCPhysReg HPR[] = {
953 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31,
954 };
955
956 // HPR Bit set.
957 const uint8_t HPRBits[] = {
958 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
959 };
960
961 // FPWithVPR Register Class...
962 const MCPhysReg FPWithVPR[] = {
963 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::VPR,
964 };
965
966 // FPWithVPR Bit set.
967 const uint8_t FPWithVPRBits[] = {
968 0x00, 0x00, 0xe8, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
969 };
970
971 // SPR Register Class...
972 const MCPhysReg SPR[] = {
973 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31,
974 };
975
976 // SPR Bit set.
977 const uint8_t SPRBits[] = {
978 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
979 };
980
981 // FPWithVPR_with_ssub_0 Register Class...
982 const MCPhysReg FPWithVPR_with_ssub_0[] = {
983 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15,
984 };
985
986 // FPWithVPR_with_ssub_0 Bit set.
987 const uint8_t FPWithVPR_with_ssub_0Bits[] = {
988 0x00, 0x00, 0xe0, 0xff, 0x1f,
989 };
990
991 // GPR Register Class...
992 const MCPhysReg GPR[] = {
993 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
994 };
995
996 // GPR Bit set.
997 const uint8_t GPRBits[] = {
998 0x00, 0xc0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
999 };
1000
1001 // GPRwithAPSR Register Class...
1002 const MCPhysReg GPRwithAPSR[] = {
1003 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV,
1004 };
1005
1006 // GPRwithAPSR Bit set.
1007 const uint8_t GPRwithAPSRBits[] = {
1008 0x04, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1009 };
1010
1011 // GPRwithZR Register Class...
1012 const MCPhysReg GPRwithZR[] = {
1013 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::ZR,
1014 };
1015
1016 // GPRwithZR Bit set.
1017 const uint8_t GPRwithZRBits[] = {
1018 0x00, 0x40, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1019 };
1020
1021 // SPR_8 Register Class...
1022 const MCPhysReg SPR_8[] = {
1023 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1024 };
1025
1026 // SPR_8 Bit set.
1027 const uint8_t SPR_8Bits[] = {
1028 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1029 };
1030
1031 // GPRnopc Register Class...
1032 const MCPhysReg GPRnopc[] = {
1033 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
1034 };
1035
1036 // GPRnopc Bit set.
1037 const uint8_t GPRnopcBits[] = {
1038 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1039 };
1040
1041 // GPRnosp Register Class...
1042 const MCPhysReg GPRnosp[] = {
1043 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::PC,
1044 };
1045
1046 // GPRnosp Bit set.
1047 const uint8_t GPRnospBits[] = {
1048 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1049 };
1050
1051 // GPRwithAPSR_NZCVnosp Register Class...
1052 const MCPhysReg GPRwithAPSR_NZCVnosp[] = {
1053 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR_NZCV,
1054 };
1055
1056 // GPRwithAPSR_NZCVnosp Bit set.
1057 const uint8_t GPRwithAPSR_NZCVnospBits[] = {
1058 0x04, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1059 };
1060
1061 // GPRwithAPSRnosp Register Class...
1062 const MCPhysReg GPRwithAPSRnosp[] = {
1063 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR,
1064 };
1065
1066 // GPRwithAPSRnosp Bit set.
1067 const uint8_t GPRwithAPSRnospBits[] = {
1068 0x02, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1069 };
1070
1071 // GPRwithZRnosp Register Class...
1072 const MCPhysReg GPRwithZRnosp[] = {
1073 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::ZR,
1074 };
1075
1076 // GPRwithZRnosp Bit set.
1077 const uint8_t GPRwithZRnospBits[] = {
1078 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1079 };
1080
1081 // GPRnoip Register Class...
1082 const MCPhysReg GPRnoip[] = {
1083 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC,
1084 };
1085
1086 // GPRnoip Bit set.
1087 const uint8_t GPRnoipBits[] = {
1088 0x00, 0x80, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3f,
1089 };
1090
1091 // rGPR Register Class...
1092 const MCPhysReg rGPR[] = {
1093 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
1094 };
1095
1096 // rGPR Bit set.
1097 const uint8_t rGPRBits[] = {
1098 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1099 };
1100
1101 // GPRnoip_and_GPRnopc Register Class...
1102 const MCPhysReg GPRnoip_and_GPRnopc[] = {
1103 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP,
1104 };
1105
1106 // GPRnoip_and_GPRnopc Bit set.
1107 const uint8_t GPRnoip_and_GPRnopcBits[] = {
1108 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3f,
1109 };
1110
1111 // GPRnoip_and_GPRnosp Register Class...
1112 const MCPhysReg GPRnoip_and_GPRnosp[] = {
1113 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::PC,
1114 };
1115
1116 // GPRnoip_and_GPRnosp Bit set.
1117 const uint8_t GPRnoip_and_GPRnospBits[] = {
1118 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3f,
1119 };
1120
1121 // GPRnoip_and_GPRwithAPSR_NZCVnosp Register Class...
1122 const MCPhysReg GPRnoip_and_GPRwithAPSR_NZCVnosp[] = {
1123 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1124 };
1125
1126 // GPRnoip_and_GPRwithAPSR_NZCVnosp Bit set.
1127 const uint8_t GPRnoip_and_GPRwithAPSR_NZCVnospBits[] = {
1128 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3f,
1129 };
1130
1131 // tGPRwithpc Register Class...
1132 const MCPhysReg tGPRwithpc[] = {
1133 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC,
1134 };
1135
1136 // tGPRwithpc Bit set.
1137 const uint8_t tGPRwithpcBits[] = {
1138 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1139 };
1140
1141 // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Register Class...
1142 const MCPhysReg FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8[] = {
1143 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1144 };
1145
1146 // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Bit set.
1147 const uint8_t FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits[] = {
1148 0x00, 0x00, 0xe0, 0x1f,
1149 };
1150
1151 // hGPR Register Class...
1152 const MCPhysReg hGPR[] = {
1153 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
1154 };
1155
1156 // hGPR Bit set.
1157 const uint8_t hGPRBits[] = {
1158 0x00, 0xc0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1159 };
1160
1161 // tGPR Register Class...
1162 const MCPhysReg tGPR[] = {
1163 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1164 };
1165
1166 // tGPR Bit set.
1167 const uint8_t tGPRBits[] = {
1168 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1169 };
1170
1171 // tGPREven Register Class...
1172 const MCPhysReg tGPREven[] = {
1173 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, ARM::R12, ARM::LR,
1174 };
1175
1176 // tGPREven Bit set.
1177 const uint8_t tGPREvenBits[] = {
1178 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55,
1179 };
1180
1181 // GPRnopc_and_hGPR Register Class...
1182 const MCPhysReg GPRnopc_and_hGPR[] = {
1183 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
1184 };
1185
1186 // GPRnopc_and_hGPR Bit set.
1187 const uint8_t GPRnopc_and_hGPRBits[] = {
1188 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1189 };
1190
1191 // GPRnosp_and_hGPR Register Class...
1192 const MCPhysReg GPRnosp_and_hGPR[] = {
1193 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::PC,
1194 };
1195
1196 // GPRnosp_and_hGPR Bit set.
1197 const uint8_t GPRnosp_and_hGPRBits[] = {
1198 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1199 };
1200
1201 // GPRnoip_and_hGPR Register Class...
1202 const MCPhysReg GPRnoip_and_hGPR[] = {
1203 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC,
1204 };
1205
1206 // GPRnoip_and_hGPR Bit set.
1207 const uint8_t GPRnoip_and_hGPRBits[] = {
1208 0x00, 0x80, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1209 };
1210
1211 // GPRnoip_and_tGPREven Register Class...
1212 const MCPhysReg GPRnoip_and_tGPREven[] = {
1213 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
1214 };
1215
1216 // GPRnoip_and_tGPREven Bit set.
1217 const uint8_t GPRnoip_and_tGPREvenBits[] = {
1218 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x15,
1219 };
1220
1221 // GPRnosp_and_GPRnopc_and_hGPR Register Class...
1222 const MCPhysReg GPRnosp_and_GPRnopc_and_hGPR[] = {
1223 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
1224 };
1225
1226 // GPRnosp_and_GPRnopc_and_hGPR Bit set.
1227 const uint8_t GPRnosp_and_GPRnopc_and_hGPRBits[] = {
1228 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1229 };
1230
1231 // tGPROdd Register Class...
1232 const MCPhysReg tGPROdd[] = {
1233 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
1234 };
1235
1236 // tGPROdd Bit set.
1237 const uint8_t tGPROddBits[] = {
1238 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x2a,
1239 };
1240
1241 // GPRnopc_and_GPRnoip_and_hGPR Register Class...
1242 const MCPhysReg GPRnopc_and_GPRnoip_and_hGPR[] = {
1243 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP,
1244 };
1245
1246 // GPRnopc_and_GPRnoip_and_hGPR Bit set.
1247 const uint8_t GPRnopc_and_GPRnoip_and_hGPRBits[] = {
1248 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1249 };
1250
1251 // GPRnosp_and_GPRnoip_and_hGPR Register Class...
1252 const MCPhysReg GPRnosp_and_GPRnoip_and_hGPR[] = {
1253 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::PC,
1254 };
1255
1256 // GPRnosp_and_GPRnoip_and_hGPR Bit set.
1257 const uint8_t GPRnosp_and_GPRnoip_and_hGPRBits[] = {
1258 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1259 };
1260
1261 // tcGPR Register Class...
1262 const MCPhysReg tcGPR[] = {
1263 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12,
1264 };
1265
1266 // tcGPR Bit set.
1267 const uint8_t tcGPRBits[] = {
1268 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40,
1269 };
1270
1271 // GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR Register Class...
1272 const MCPhysReg GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR[] = {
1273 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1274 };
1275
1276 // GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR Bit set.
1277 const uint8_t GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits[] = {
1278 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1279 };
1280
1281 // hGPR_and_tGPREven Register Class...
1282 const MCPhysReg hGPR_and_tGPREven[] = {
1283 ARM::R8, ARM::R10, ARM::R12, ARM::LR,
1284 };
1285
1286 // hGPR_and_tGPREven Bit set.
1287 const uint8_t hGPR_and_tGPREvenBits[] = {
1288 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54,
1289 };
1290
1291 // tGPR_and_tGPREven Register Class...
1292 const MCPhysReg tGPR_and_tGPREven[] = {
1293 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
1294 };
1295
1296 // tGPR_and_tGPREven Bit set.
1297 const uint8_t tGPR_and_tGPREvenBits[] = {
1298 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x01,
1299 };
1300
1301 // tGPR_and_tGPROdd Register Class...
1302 const MCPhysReg tGPR_and_tGPROdd[] = {
1303 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
1304 };
1305
1306 // tGPR_and_tGPROdd Bit set.
1307 const uint8_t tGPR_and_tGPROddBits[] = {
1308 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x02,
1309 };
1310
1311 // tcGPRnotr12 Register Class...
1312 const MCPhysReg tcGPRnotr12[] = {
1313 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1314 };
1315
1316 // tcGPRnotr12 Bit set.
1317 const uint8_t tcGPRnotr12Bits[] = {
1318 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1319 };
1320
1321 // tGPREven_and_tcGPR Register Class...
1322 const MCPhysReg tGPREven_and_tcGPR[] = {
1323 ARM::R0, ARM::R2, ARM::R12,
1324 };
1325
1326 // tGPREven_and_tcGPR Bit set.
1327 const uint8_t tGPREven_and_tcGPRBits[] = {
1328 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x40,
1329 };
1330
1331 // FP_STATUS_REGS Register Class...
1332 const MCPhysReg FP_STATUS_REGS[] = {
1333 ARM::FPSCR, ARM::FPEXC,
1334 };
1335
1336 // FP_STATUS_REGS Bit set.
1337 const uint8_t FP_STATUS_REGSBits[] = {
1338 0x40, 0x01,
1339 };
1340
1341 // hGPR_and_GPRnoip_and_tGPREven Register Class...
1342 const MCPhysReg hGPR_and_GPRnoip_and_tGPREven[] = {
1343 ARM::R8, ARM::R10,
1344 };
1345
1346 // hGPR_and_GPRnoip_and_tGPREven Bit set.
1347 const uint8_t hGPR_and_GPRnoip_and_tGPREvenBits[] = {
1348 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14,
1349 };
1350
1351 // hGPR_and_tGPROdd Register Class...
1352 const MCPhysReg hGPR_and_tGPROdd[] = {
1353 ARM::R9, ARM::R11,
1354 };
1355
1356 // hGPR_and_tGPROdd Bit set.
1357 const uint8_t hGPR_and_tGPROddBits[] = {
1358 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28,
1359 };
1360
1361 // tGPREven_and_tcGPRnotr12 Register Class...
1362 const MCPhysReg tGPREven_and_tcGPRnotr12[] = {
1363 ARM::R0, ARM::R2,
1364 };
1365
1366 // tGPREven_and_tcGPRnotr12 Bit set.
1367 const uint8_t tGPREven_and_tcGPRnotr12Bits[] = {
1368 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14,
1369 };
1370
1371 // tGPROdd_and_tcGPR Register Class...
1372 const MCPhysReg tGPROdd_and_tcGPR[] = {
1373 ARM::R1, ARM::R3,
1374 };
1375
1376 // tGPROdd_and_tcGPR Bit set.
1377 const uint8_t tGPROdd_and_tcGPRBits[] = {
1378 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28,
1379 };
1380
1381 // CCR Register Class...
1382 const MCPhysReg CCR[] = {
1383 ARM::CPSR,
1384 };
1385
1386 // CCR Bit set.
1387 const uint8_t CCRBits[] = {
1388 0x08,
1389 };
1390
1391 // FPCXTRegs Register Class...
1392 const MCPhysReg FPCXTRegs[] = {
1393 ARM::FPCXTNS,
1394 };
1395
1396 // FPCXTRegs Bit set.
1397 const uint8_t FPCXTRegsBits[] = {
1398 0x10,
1399 };
1400
1401 // GPRlr Register Class...
1402 const MCPhysReg GPRlr[] = {
1403 ARM::LR,
1404 };
1405
1406 // GPRlr Bit set.
1407 const uint8_t GPRlrBits[] = {
1408 0x00, 0x40,
1409 };
1410
1411 // GPRsp Register Class...
1412 const MCPhysReg GPRsp[] = {
1413 ARM::SP,
1414 };
1415
1416 // GPRsp Bit set.
1417 const uint8_t GPRspBits[] = {
1418 0x00, 0x00, 0x02,
1419 };
1420
1421 // VCCR Register Class...
1422 const MCPhysReg VCCR[] = {
1423 ARM::VPR,
1424 };
1425
1426 // VCCR Bit set.
1427 const uint8_t VCCRBits[] = {
1428 0x00, 0x00, 0x08,
1429 };
1430
1431 // cl_FPSCR_NZCV Register Class...
1432 const MCPhysReg cl_FPSCR_NZCV[] = {
1433 ARM::FPSCR_NZCV,
1434 };
1435
1436 // cl_FPSCR_NZCV Bit set.
1437 const uint8_t cl_FPSCR_NZCVBits[] = {
1438 0x00, 0x02,
1439 };
1440
1441 // hGPR_and_tGPRwithpc Register Class...
1442 const MCPhysReg hGPR_and_tGPRwithpc[] = {
1443 ARM::PC,
1444 };
1445
1446 // hGPR_and_tGPRwithpc Bit set.
1447 const uint8_t hGPR_and_tGPRwithpcBits[] = {
1448 0x00, 0x80,
1449 };
1450
1451 // hGPR_and_tcGPR Register Class...
1452 const MCPhysReg hGPR_and_tcGPR[] = {
1453 ARM::R12,
1454 };
1455
1456 // hGPR_and_tcGPR Bit set.
1457 const uint8_t hGPR_and_tcGPRBits[] = {
1458 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
1459 };
1460
1461 // DPR Register Class...
1462 const MCPhysReg DPR[] = {
1463 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31,
1464 };
1465
1466 // DPR Bit set.
1467 const uint8_t DPRBits[] = {
1468 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
1469 };
1470
1471 // DPR_VFP2 Register Class...
1472 const MCPhysReg DPR_VFP2[] = {
1473 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1474 };
1475
1476 // DPR_VFP2 Bit set.
1477 const uint8_t DPR_VFP2Bits[] = {
1478 0x00, 0x00, 0xe0, 0xff, 0x1f,
1479 };
1480
1481 // DPR_8 Register Class...
1482 const MCPhysReg DPR_8[] = {
1483 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1484 };
1485
1486 // DPR_8 Bit set.
1487 const uint8_t DPR_8Bits[] = {
1488 0x00, 0x00, 0xe0, 0x1f,
1489 };
1490
1491 // GPRPair Register Class...
1492 const MCPhysReg GPRPair[] = {
1493 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, ARM::R12_SP,
1494 };
1495
1496 // GPRPair Bit set.
1497 const uint8_t GPRPairBits[] = {
1498 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1499 };
1500
1501 // GPRPairnosp Register Class...
1502 const MCPhysReg GPRPairnosp[] = {
1503 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11,
1504 };
1505
1506 // GPRPairnosp Bit set.
1507 const uint8_t GPRPairnospBits[] = {
1508 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e,
1509 };
1510
1511 // GPRPair_with_gsub_0_in_tGPR Register Class...
1512 const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
1513 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1514 };
1515
1516 // GPRPair_with_gsub_0_in_tGPR Bit set.
1517 const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
1518 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
1519 };
1520
1521 // GPRPair_with_gsub_0_in_hGPR Register Class...
1522 const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
1523 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP,
1524 };
1525
1526 // GPRPair_with_gsub_0_in_hGPR Bit set.
1527 const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
1528 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
1529 };
1530
1531 // GPRPair_with_gsub_0_in_tcGPR Register Class...
1532 const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
1533 ARM::R0_R1, ARM::R2_R3, ARM::R12_SP,
1534 };
1535
1536 // GPRPair_with_gsub_0_in_tcGPR Bit set.
1537 const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
1538 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86,
1539 };
1540
1541 // GPRPair_with_gsub_0_in_tcGPRnotr12 Register Class...
1542 const MCPhysReg GPRPair_with_gsub_0_in_tcGPRnotr12[] = {
1543 ARM::R0_R1, ARM::R2_R3,
1544 };
1545
1546 // GPRPair_with_gsub_0_in_tcGPRnotr12 Bit set.
1547 const uint8_t GPRPair_with_gsub_0_in_tcGPRnotr12Bits[] = {
1548 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,
1549 };
1550
1551 // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Register Class...
1552 const MCPhysReg GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR[] = {
1553 ARM::R8_R9, ARM::R10_R11,
1554 };
1555
1556 // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Bit set.
1557 const uint8_t GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits[] = {
1558 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
1559 };
1560
1561 // GPRPair_with_gsub_1_in_GPRsp Register Class...
1562 const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
1563 ARM::R12_SP,
1564 };
1565
1566 // GPRPair_with_gsub_1_in_GPRsp Bit set.
1567 const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
1568 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
1569 };
1570
1571 // DPairSpc Register Class...
1572 const MCPhysReg DPairSpc[] = {
1573 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D28_D30, ARM::D29_D31,
1574 };
1575
1576 // DPairSpc Bit set.
1577 const uint8_t DPairSpcBits[] = {
1578 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f,
1579 };
1580
1581 // DPairSpc_with_ssub_0 Register Class...
1582 const MCPhysReg DPairSpc_with_ssub_0[] = {
1583 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1584 };
1585
1586 // DPairSpc_with_ssub_0 Bit set.
1587 const uint8_t DPairSpc_with_ssub_0Bits[] = {
1588 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1589 };
1590
1591 // DPairSpc_with_ssub_4 Register Class...
1592 const MCPhysReg DPairSpc_with_ssub_4[] = {
1593 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15,
1594 };
1595
1596 // DPairSpc_with_ssub_4 Bit set.
1597 const uint8_t DPairSpc_with_ssub_4Bits[] = {
1598 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f,
1599 };
1600
1601 // DPairSpc_with_dsub_0_in_DPR_8 Register Class...
1602 const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
1603 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1604 };
1605
1606 // DPairSpc_with_dsub_0_in_DPR_8 Bit set.
1607 const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
1608 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1609 };
1610
1611 // DPairSpc_with_dsub_2_in_DPR_8 Register Class...
1612 const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
1613 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7,
1614 };
1615
1616 // DPairSpc_with_dsub_2_in_DPR_8 Bit set.
1617 const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
1618 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f,
1619 };
1620
1621 // DPair Register Class...
1622 const MCPhysReg DPair[] = {
1623 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q15,
1624 };
1625
1626 // DPair Bit set.
1627 const uint8_t DPairBits[] = {
1628 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
1629 };
1630
1631 // DPair_with_ssub_0 Register Class...
1632 const MCPhysReg DPair_with_ssub_0[] = {
1633 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16,
1634 };
1635
1636 // DPair_with_ssub_0 Bit set.
1637 const uint8_t DPair_with_ssub_0Bits[] = {
1638 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
1639 };
1640
1641 // QPR Register Class...
1642 const MCPhysReg QPR[] = {
1643 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15,
1644 };
1645
1646 // QPR Bit set.
1647 const uint8_t QPRBits[] = {
1648 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
1649 };
1650
1651 // DPair_with_ssub_2 Register Class...
1652 const MCPhysReg DPair_with_ssub_2[] = {
1653 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7,
1654 };
1655
1656 // DPair_with_ssub_2 Bit set.
1657 const uint8_t DPair_with_ssub_2Bits[] = {
1658 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
1659 };
1660
1661 // DPair_with_dsub_0_in_DPR_8 Register Class...
1662 const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
1663 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8,
1664 };
1665
1666 // DPair_with_dsub_0_in_DPR_8 Bit set.
1667 const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
1668 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
1669 };
1670
1671 // MQPR Register Class...
1672 const MCPhysReg MQPR[] = {
1673 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1674 };
1675
1676 // MQPR Bit set.
1677 const uint8_t MQPRBits[] = {
1678 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1679 };
1680
1681 // QPR_VFP2 Register Class...
1682 const MCPhysReg QPR_VFP2[] = {
1683 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1684 };
1685
1686 // QPR_VFP2 Bit set.
1687 const uint8_t QPR_VFP2Bits[] = {
1688 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1689 };
1690
1691 // DPair_with_dsub_1_in_DPR_8 Register Class...
1692 const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
1693 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3,
1694 };
1695
1696 // DPair_with_dsub_1_in_DPR_8 Bit set.
1697 const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
1698 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
1699 };
1700
1701 // QPR_8 Register Class...
1702 const MCPhysReg QPR_8[] = {
1703 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1704 };
1705
1706 // QPR_8 Bit set.
1707 const uint8_t QPR_8Bits[] = {
1708 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1709 };
1710
1711 // DTriple Register Class...
1712 const MCPhysReg DTriple[] = {
1713 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, ARM::D16_D17_D18, ARM::D17_D18_D19, ARM::D18_D19_D20, ARM::D19_D20_D21, ARM::D20_D21_D22, ARM::D21_D22_D23, ARM::D22_D23_D24, ARM::D23_D24_D25, ARM::D24_D25_D26, ARM::D25_D26_D27, ARM::D26_D27_D28, ARM::D27_D28_D29, ARM::D28_D29_D30, ARM::D29_D30_D31,
1714 };
1715
1716 // DTriple Bit set.
1717 const uint8_t DTripleBits[] = {
1718 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f,
1719 };
1720
1721 // DTripleSpc Register Class...
1722 const MCPhysReg DTripleSpc[] = {
1723 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31,
1724 };
1725
1726 // DTripleSpc Bit set.
1727 const uint8_t DTripleSpcBits[] = {
1728 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
1729 };
1730
1731 // DTripleSpc_with_ssub_0 Register Class...
1732 const MCPhysReg DTripleSpc_with_ssub_0[] = {
1733 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19,
1734 };
1735
1736 // DTripleSpc_with_ssub_0 Bit set.
1737 const uint8_t DTripleSpc_with_ssub_0Bits[] = {
1738 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1739 };
1740
1741 // DTriple_with_ssub_0 Register Class...
1742 const MCPhysReg DTriple_with_ssub_0[] = {
1743 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17,
1744 };
1745
1746 // DTriple_with_ssub_0 Bit set.
1747 const uint8_t DTriple_with_ssub_0Bits[] = {
1748 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
1749 };
1750
1751 // DTriple_with_qsub_0_in_QPR Register Class...
1752 const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
1753 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, ARM::D16_D17_D18, ARM::D18_D19_D20, ARM::D20_D21_D22, ARM::D22_D23_D24, ARM::D24_D25_D26, ARM::D26_D27_D28, ARM::D28_D29_D30,
1754 };
1755
1756 // DTriple_with_qsub_0_in_QPR Bit set.
1757 const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
1758 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15,
1759 };
1760
1761 // DTriple_with_ssub_2 Register Class...
1762 const MCPhysReg DTriple_with_ssub_2[] = {
1763 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16,
1764 };
1765
1766 // DTriple_with_ssub_2 Bit set.
1767 const uint8_t DTriple_with_ssub_2Bits[] = {
1768 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f,
1769 };
1770
1771 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1772 const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1773 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, ARM::D17_D18_D19, ARM::D19_D20_D21, ARM::D21_D22_D23, ARM::D23_D24_D25, ARM::D25_D26_D27, ARM::D27_D28_D29, ARM::D29_D30_D31,
1774 };
1775
1776 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1777 const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1778 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a,
1779 };
1780
1781 // DTripleSpc_with_ssub_4 Register Class...
1782 const MCPhysReg DTripleSpc_with_ssub_4[] = {
1783 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17,
1784 };
1785
1786 // DTripleSpc_with_ssub_4 Bit set.
1787 const uint8_t DTripleSpc_with_ssub_4Bits[] = {
1788 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
1789 };
1790
1791 // DTriple_with_ssub_4 Register Class...
1792 const MCPhysReg DTriple_with_ssub_4[] = {
1793 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15,
1794 };
1795
1796 // DTriple_with_ssub_4 Bit set.
1797 const uint8_t DTriple_with_ssub_4Bits[] = {
1798 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f,
1799 };
1800
1801 // DTripleSpc_with_ssub_8 Register Class...
1802 const MCPhysReg DTripleSpc_with_ssub_8[] = {
1803 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15,
1804 };
1805
1806 // DTripleSpc_with_ssub_8 Bit set.
1807 const uint8_t DTripleSpc_with_ssub_8Bits[] = {
1808 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
1809 };
1810
1811 // DTripleSpc_with_dsub_0_in_DPR_8 Register Class...
1812 const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
1813 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11,
1814 };
1815
1816 // DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
1817 const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
1818 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
1819 };
1820
1821 // DTriple_with_dsub_0_in_DPR_8 Register Class...
1822 const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
1823 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9,
1824 };
1825
1826 // DTriple_with_dsub_0_in_DPR_8 Bit set.
1827 const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
1828 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1829 };
1830
1831 // DTriple_with_qsub_0_in_MQPR Register Class...
1832 const MCPhysReg DTriple_with_qsub_0_in_MQPR[] = {
1833 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16,
1834 };
1835
1836 // DTriple_with_qsub_0_in_MQPR Bit set.
1837 const uint8_t DTriple_with_qsub_0_in_MQPRBits[] = {
1838 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
1839 };
1840
1841 // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1842 const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1843 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17,
1844 };
1845
1846 // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1847 const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1848 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa,
1849 };
1850
1851 // DTriple_with_dsub_1_in_DPR_8 Register Class...
1852 const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
1853 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8,
1854 };
1855
1856 // DTriple_with_dsub_1_in_DPR_8 Bit set.
1857 const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
1858 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1859 };
1860
1861 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
1862 const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
1863 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15,
1864 };
1865
1866 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
1867 const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
1868 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a,
1869 };
1870
1871 // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Register Class...
1872 const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR[] = {
1873 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14,
1874 };
1875
1876 // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Bit set.
1877 const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits[] = {
1878 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15,
1879 };
1880
1881 // DTripleSpc_with_dsub_2_in_DPR_8 Register Class...
1882 const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
1883 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9,
1884 };
1885
1886 // DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
1887 const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
1888 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1889 };
1890
1891 // DTriple_with_dsub_2_in_DPR_8 Register Class...
1892 const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
1893 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7,
1894 };
1895
1896 // DTriple_with_dsub_2_in_DPR_8 Bit set.
1897 const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
1898 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
1899 };
1900
1901 // DTripleSpc_with_dsub_4_in_DPR_8 Register Class...
1902 const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
1903 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7,
1904 };
1905
1906 // DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
1907 const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
1908 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
1909 };
1910
1911 // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
1912 const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
1913 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9,
1914 };
1915
1916 // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
1917 const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
1918 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa,
1919 };
1920
1921 // DTriple_with_qsub_0_in_QPR_8 Register Class...
1922 const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
1923 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8,
1924 };
1925
1926 // DTriple_with_qsub_0_in_QPR_8 Bit set.
1927 const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
1928 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55,
1929 };
1930
1931 // DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8 Register Class...
1932 const MCPhysReg DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8[] = {
1933 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6,
1934 };
1935
1936 // DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8 Bit set.
1937 const uint8_t DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8Bits[] = {
1938 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15,
1939 };
1940
1941 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
1942 const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
1943 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7,
1944 };
1945
1946 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
1947 const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
1948 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a,
1949 };
1950
1951 // DQuadSpc Register Class...
1952 const MCPhysReg DQuadSpc[] = {
1953 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31,
1954 };
1955
1956 // DQuadSpc Bit set.
1957 const uint8_t DQuadSpcBits[] = {
1958 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
1959 };
1960
1961 // DQuadSpc_with_ssub_0 Register Class...
1962 const MCPhysReg DQuadSpc_with_ssub_0[] = {
1963 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19,
1964 };
1965
1966 // DQuadSpc_with_ssub_0 Bit set.
1967 const uint8_t DQuadSpc_with_ssub_0Bits[] = {
1968 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1969 };
1970
1971 // DQuadSpc_with_ssub_4 Register Class...
1972 const MCPhysReg DQuadSpc_with_ssub_4[] = {
1973 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17,
1974 };
1975
1976 // DQuadSpc_with_ssub_4 Bit set.
1977 const uint8_t DQuadSpc_with_ssub_4Bits[] = {
1978 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
1979 };
1980
1981 // DQuadSpc_with_ssub_8 Register Class...
1982 const MCPhysReg DQuadSpc_with_ssub_8[] = {
1983 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15,
1984 };
1985
1986 // DQuadSpc_with_ssub_8 Bit set.
1987 const uint8_t DQuadSpc_with_ssub_8Bits[] = {
1988 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
1989 };
1990
1991 // DQuadSpc_with_dsub_0_in_DPR_8 Register Class...
1992 const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
1993 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11,
1994 };
1995
1996 // DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
1997 const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
1998 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
1999 };
2000
2001 // DQuadSpc_with_dsub_2_in_DPR_8 Register Class...
2002 const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
2003 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9,
2004 };
2005
2006 // DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
2007 const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
2008 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
2009 };
2010
2011 // DQuadSpc_with_dsub_4_in_DPR_8 Register Class...
2012 const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
2013 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7,
2014 };
2015
2016 // DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
2017 const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
2018 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
2019 };
2020
2021 // DQuad Register Class...
2022 const MCPhysReg DQuad[] = {
2023 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, ARM::Q8_Q9, ARM::D17_D18_D19_D20, ARM::Q9_Q10, ARM::D19_D20_D21_D22, ARM::Q10_Q11, ARM::D21_D22_D23_D24, ARM::Q11_Q12, ARM::D23_D24_D25_D26, ARM::Q12_Q13, ARM::D25_D26_D27_D28, ARM::Q13_Q14, ARM::D27_D28_D29_D30, ARM::Q14_Q15,
2024 };
2025
2026 // DQuad Bit set.
2027 const uint8_t DQuadBits[] = {
2028 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
2029 };
2030
2031 // DQuad_with_ssub_0 Register Class...
2032 const MCPhysReg DQuad_with_ssub_0[] = {
2033 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18,
2034 };
2035
2036 // DQuad_with_ssub_0 Bit set.
2037 const uint8_t DQuad_with_ssub_0Bits[] = {
2038 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2039 };
2040
2041 // DQuad_with_ssub_2 Register Class...
2042 const MCPhysReg DQuad_with_ssub_2[] = {
2043 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8,
2044 };
2045
2046 // DQuad_with_ssub_2 Bit set.
2047 const uint8_t DQuad_with_ssub_2Bits[] = {
2048 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
2049 };
2050
2051 // QQPR Register Class...
2052 const MCPhysReg QQPR[] = {
2053 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15,
2054 };
2055
2056 // QQPR Bit set.
2057 const uint8_t QQPRBits[] = {
2058 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2059 };
2060
2061 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2062 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2063 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, ARM::D17_D18_D19_D20, ARM::D19_D20_D21_D22, ARM::D21_D22_D23_D24, ARM::D23_D24_D25_D26, ARM::D25_D26_D27_D28, ARM::D27_D28_D29_D30,
2064 };
2065
2066 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2067 const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2068 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
2069 };
2070
2071 // DQuad_with_ssub_4 Register Class...
2072 const MCPhysReg DQuad_with_ssub_4[] = {
2073 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16,
2074 };
2075
2076 // DQuad_with_ssub_4 Bit set.
2077 const uint8_t DQuad_with_ssub_4Bits[] = {
2078 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
2079 };
2080
2081 // DQuad_with_ssub_6 Register Class...
2082 const MCPhysReg DQuad_with_ssub_6[] = {
2083 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7,
2084 };
2085
2086 // DQuad_with_ssub_6 Bit set.
2087 const uint8_t DQuad_with_ssub_6Bits[] = {
2088 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
2089 };
2090
2091 // DQuad_with_dsub_0_in_DPR_8 Register Class...
2092 const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
2093 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10,
2094 };
2095
2096 // DQuad_with_dsub_0_in_DPR_8 Bit set.
2097 const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
2098 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
2099 };
2100
2101 // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2102 const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2103 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18,
2104 };
2105
2106 // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2107 const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2108 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2109 };
2110
2111 // QQPR_with_ssub_0 Register Class...
2112 const MCPhysReg QQPR_with_ssub_0[] = {
2113 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8,
2114 };
2115
2116 // QQPR_with_ssub_0 Bit set.
2117 const uint8_t QQPR_with_ssub_0Bits[] = {
2118 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
2119 };
2120
2121 // DQuad_with_dsub_1_in_DPR_8 Register Class...
2122 const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
2123 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4,
2124 };
2125
2126 // DQuad_with_dsub_1_in_DPR_8 Bit set.
2127 const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
2128 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
2129 };
2130
2131 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
2132 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
2133 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16,
2134 };
2135
2136 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
2137 const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
2138 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
2139 };
2140
2141 // MQQPR Register Class...
2142 const MCPhysReg MQQPR[] = {
2143 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7,
2144 };
2145
2146 // MQQPR Bit set.
2147 const uint8_t MQQPRBits[] = {
2148 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
2149 };
2150
2151 // DQuad_with_dsub_2_in_DPR_8 Register Class...
2152 const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
2153 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8,
2154 };
2155
2156 // DQuad_with_dsub_2_in_DPR_8 Bit set.
2157 const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
2158 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
2159 };
2160
2161 // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
2162 const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
2163 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14,
2164 };
2165
2166 // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
2167 const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
2168 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
2169 };
2170
2171 // DQuad_with_dsub_3_in_DPR_8 Register Class...
2172 const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
2173 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3,
2174 };
2175
2176 // DQuad_with_dsub_3_in_DPR_8 Bit set.
2177 const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
2178 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2179 };
2180
2181 // DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
2182 const MCPhysReg DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
2183 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10,
2184 };
2185
2186 // DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
2187 const uint8_t DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
2188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
2189 };
2190
2191 // MQQPR_with_qsub_0_in_QPR_8 Register Class...
2192 const MCPhysReg MQQPR_with_qsub_0_in_QPR_8[] = {
2193 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
2194 };
2195
2196 // MQQPR_with_qsub_0_in_QPR_8 Bit set.
2197 const uint8_t MQQPR_with_qsub_0_in_QPR_8Bits[] = {
2198 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
2199 };
2200
2201 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
2202 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
2203 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8,
2204 };
2205
2206 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
2207 const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
2208 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
2209 };
2210
2211 // MQQPR_with_dsub_2_in_DPR_8 Register Class...
2212 const MCPhysReg MQQPR_with_dsub_2_in_DPR_8[] = {
2213 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3,
2214 };
2215
2216 // MQQPR_with_dsub_2_in_DPR_8 Bit set.
2217 const uint8_t MQQPR_with_dsub_2_in_DPR_8Bits[] = {
2218 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
2219 };
2220
2221 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8 Register Class...
2222 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8[] = {
2223 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6,
2224 };
2225
2226 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8 Bit set.
2227 const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8Bits[] = {
2228 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2229 };
2230
2231 // QQQQPR Register Class...
2232 const MCPhysReg QQQQPR[] = {
2233 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15,
2234 };
2235
2236 // QQQQPR Bit set.
2237 const uint8_t QQQQPRBits[] = {
2238 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
2239 };
2240
2241 // QQQQPR_with_ssub_0 Register Class...
2242 const MCPhysReg QQQQPR_with_ssub_0[] = {
2243 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10,
2244 };
2245
2246 // QQQQPR_with_ssub_0 Bit set.
2247 const uint8_t QQQQPR_with_ssub_0Bits[] = {
2248 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
2249 };
2250
2251 // QQQQPR_with_ssub_4 Register Class...
2252 const MCPhysReg QQQQPR_with_ssub_4[] = {
2253 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9,
2254 };
2255
2256 // QQQQPR_with_ssub_4 Bit set.
2257 const uint8_t QQQQPR_with_ssub_4Bits[] = {
2258 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
2259 };
2260
2261 // QQQQPR_with_ssub_8 Register Class...
2262 const MCPhysReg QQQQPR_with_ssub_8[] = {
2263 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8,
2264 };
2265
2266 // QQQQPR_with_ssub_8 Bit set.
2267 const uint8_t QQQQPR_with_ssub_8Bits[] = {
2268 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03,
2269 };
2270
2271 // MQQQQPR Register Class...
2272 const MCPhysReg MQQQQPR[] = {
2273 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7,
2274 };
2275
2276 // MQQQQPR Bit set.
2277 const uint8_t MQQQQPRBits[] = {
2278 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01,
2279 };
2280
2281 // MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8 Register Class...
2282 const MCPhysReg MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8[] = {
2283 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6,
2284 };
2285
2286 // MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8 Bit set.
2287 const uint8_t MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8Bits[] = {
2288 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
2289 };
2290
2291 // MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8 Register Class...
2292 const MCPhysReg MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8[] = {
2293 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
2294 };
2295
2296 // MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8 Bit set.
2297 const uint8_t MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8Bits[] = {
2298 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
2299 };
2300
2301 // MQQQQPR_with_qsub_2_in_QPR_8 Register Class...
2302 const MCPhysReg MQQQQPR_with_qsub_2_in_QPR_8[] = {
2303 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4,
2304 };
2305
2306 // MQQQQPR_with_qsub_2_in_QPR_8 Bit set.
2307 const uint8_t MQQQQPR_with_qsub_2_in_QPR_8Bits[] = {
2308 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
2309 };
2310
2311 // MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8 Register Class...
2312 const MCPhysReg MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8[] = {
2313 ARM::Q0_Q1_Q2_Q3,
2314 };
2315
2316 // MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8 Bit set.
2317 const uint8_t MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8Bits[] = {
2318 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2319 };
2320
2321} // end anonymous namespace
2322
2323
2324#ifdef __GNUC__
2325#pragma GCC diagnostic push
2326#pragma GCC diagnostic ignored "-Woverlength-strings"
2327#endif
2328extern const char ARMRegClassStrings[] = {
2329 /* 0 */ "QQQQPR_with_ssub_0\000"
2330 /* 19 */ "FPWithVPR_with_ssub_0\000"
2331 /* 41 */ "DQuadSpc_with_ssub_0\000"
2332 /* 62 */ "DTripleSpc_with_ssub_0\000"
2333 /* 85 */ "DPairSpc_with_ssub_0\000"
2334 /* 106 */ "DQuad_with_ssub_0\000"
2335 /* 124 */ "DTriple_with_ssub_0\000"
2336 /* 144 */ "DPair_with_ssub_0\000"
2337 /* 162 */ "tGPREven_and_tcGPRnotr12\000"
2338 /* 187 */ "GPRPair_with_gsub_0_in_tcGPRnotr12\000"
2339 /* 222 */ "DPR_VFP2\000"
2340 /* 231 */ "QPR_VFP2\000"
2341 /* 240 */ "DQuad_with_ssub_2\000"
2342 /* 258 */ "DTriple_with_ssub_2\000"
2343 /* 278 */ "DPair_with_ssub_2\000"
2344 /* 296 */ "QQQQPR_with_ssub_4\000"
2345 /* 315 */ "DQuadSpc_with_ssub_4\000"
2346 /* 336 */ "DTripleSpc_with_ssub_4\000"
2347 /* 359 */ "DPairSpc_with_ssub_4\000"
2348 /* 380 */ "DQuad_with_ssub_4\000"
2349 /* 398 */ "DTriple_with_ssub_4\000"
2350 /* 418 */ "DQuad_with_ssub_6\000"
2351 /* 436 */ "DQuadSpc_with_dsub_0_in_DPR_8\000"
2352 /* 466 */ "DTripleSpc_with_dsub_0_in_DPR_8\000"
2353 /* 498 */ "DPairSpc_with_dsub_0_in_DPR_8\000"
2354 /* 528 */ "DQuad_with_dsub_0_in_DPR_8\000"
2355 /* 555 */ "DTriple_with_dsub_0_in_DPR_8\000"
2356 /* 584 */ "DPair_with_dsub_0_in_DPR_8\000"
2357 /* 611 */ "DQuad_with_dsub_1_in_DPR_8\000"
2358 /* 638 */ "DTriple_with_dsub_1_in_DPR_8\000"
2359 /* 667 */ "DPair_with_dsub_1_in_DPR_8\000"
2360 /* 694 */ "MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8\000"
2361 /* 745 */ "MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8\000"
2362 /* 796 */ "DQuadSpc_with_dsub_2_in_DPR_8\000"
2363 /* 826 */ "DTripleSpc_with_dsub_2_in_DPR_8\000"
2364 /* 858 */ "DPairSpc_with_dsub_2_in_DPR_8\000"
2365 /* 888 */ "DQuad_with_dsub_2_in_DPR_8\000"
2366 /* 915 */ "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8\000"
2367 /* 1032 */ "DQuad_with_dsub_3_in_DPR_8\000"
2368 /* 1059 */ "DQuadSpc_with_dsub_4_in_DPR_8\000"
2369 /* 1089 */ "DTripleSpc_with_dsub_4_in_DPR_8\000"
2370 /* 1121 */ "MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8\000"
2371 /* 1172 */ "DTriple_with_qsub_0_in_QPR_8\000"
2372 /* 1201 */ "MQQQQPR_with_qsub_2_in_QPR_8\000"
2373 /* 1230 */ "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8\000"
2374 /* 1278 */ "DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8\000"
2375 /* 1328 */ "FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8\000"
2376 /* 1371 */ "QQQQPR_with_ssub_8\000"
2377 /* 1390 */ "DQuadSpc_with_ssub_8\000"
2378 /* 1411 */ "DTripleSpc_with_ssub_8\000"
2379 /* 1434 */ "VCCR\000"
2380 /* 1439 */ "DPR\000"
2381 /* 1443 */ "hGPR_and_tcGPR\000"
2382 /* 1458 */ "tGPROdd_and_tcGPR\000"
2383 /* 1476 */ "tGPREven_and_tcGPR\000"
2384 /* 1495 */ "GPRPair_with_gsub_0_in_tcGPR\000"
2385 /* 1524 */ "GPRnosp_and_GPRnopc_and_hGPR\000"
2386 /* 1553 */ "GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR\000"
2387 /* 1594 */ "GPRnosp_and_GPRnoip_and_hGPR\000"
2388 /* 1623 */ "GPRnosp_and_hGPR\000"
2389 /* 1640 */ "GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR\000"
2390 /* 1684 */ "rGPR\000"
2391 /* 1689 */ "GPRPair_with_gsub_0_in_tGPR\000"
2392 /* 1717 */ "HPR\000"
2393 /* 1721 */ "DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR\000"
2394 /* 1773 */ "DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR\000"
2395 /* 1842 */ "DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR\000"
2396 /* 1980 */ "MQQPR\000"
2397 /* 1986 */ "MQQQQPR\000"
2398 /* 1994 */ "DTriple_with_qsub_0_in_QPR\000"
2399 /* 2021 */ "DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR\000"
2400 /* 2089 */ "DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR\000"
2401 /* 2161 */ "SPR\000"
2402 /* 2165 */ "FPWithVPR\000"
2403 /* 2175 */ "GPRwithAPSR\000"
2404 /* 2187 */ "GPRwithZR\000"
2405 /* 2197 */ "FP_STATUS_REGS\000"
2406 /* 2212 */ "cl_FPSCR_NZCV\000"
2407 /* 2226 */ "DQuadSpc\000"
2408 /* 2235 */ "DTripleSpc\000"
2409 /* 2246 */ "DPairSpc\000"
2410 /* 2255 */ "hGPR_and_tGPRwithpc\000"
2411 /* 2275 */ "GPRnoip_and_GPRnopc\000"
2412 /* 2295 */ "DQuad\000"
2413 /* 2301 */ "hGPR_and_tGPROdd\000"
2414 /* 2318 */ "tGPR_and_tGPROdd\000"
2415 /* 2335 */ "DTriple\000"
2416 /* 2343 */ "hGPR_and_tGPREven\000"
2417 /* 2361 */ "tGPR_and_tGPREven\000"
2418 /* 2379 */ "hGPR_and_GPRnoip_and_tGPREven\000"
2419 /* 2409 */ "GPRnoip\000"
2420 /* 2417 */ "GPRPair_with_gsub_1_in_GPRsp\000"
2421 /* 2446 */ "GPRnoip_and_GPRnosp\000"
2422 /* 2466 */ "GPRwithAPSRnosp\000"
2423 /* 2482 */ "GPRwithZRnosp\000"
2424 /* 2496 */ "GPRnoip_and_GPRwithAPSR_NZCVnosp\000"
2425 /* 2529 */ "GPRPairnosp\000"
2426 /* 2541 */ "DPair\000"
2427 /* 2547 */ "GPRPair\000"
2428 /* 2555 */ "GPRlr\000"
2429 /* 2561 */ "FPCXTRegs\000"
2430};
2431#ifdef __GNUC__
2432#pragma GCC diagnostic pop
2433#endif
2434
2435extern const MCRegisterClass ARMMCRegisterClasses[] = {
2436 { .RegsBegin: HPR, .RegSet: HPRBits, .NameIdx: 1717, .RegsSize: 32, .RegSetSize: sizeof(HPRBits), .ID: ARM::HPRRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2437 { .RegsBegin: FPWithVPR, .RegSet: FPWithVPRBits, .NameIdx: 2165, .RegsSize: 65, .RegSetSize: sizeof(FPWithVPRBits), .ID: ARM::FPWithVPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2438 { .RegsBegin: SPR, .RegSet: SPRBits, .NameIdx: 2161, .RegsSize: 32, .RegSetSize: sizeof(SPRBits), .ID: ARM::SPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2439 { .RegsBegin: FPWithVPR_with_ssub_0, .RegSet: FPWithVPR_with_ssub_0Bits, .NameIdx: 19, .RegsSize: 16, .RegSetSize: sizeof(FPWithVPR_with_ssub_0Bits), .ID: ARM::FPWithVPR_with_ssub_0RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2440 { .RegsBegin: GPR, .RegSet: GPRBits, .NameIdx: 1454, .RegsSize: 16, .RegSetSize: sizeof(GPRBits), .ID: ARM::GPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2441 { .RegsBegin: GPRwithAPSR, .RegSet: GPRwithAPSRBits, .NameIdx: 2175, .RegsSize: 16, .RegSetSize: sizeof(GPRwithAPSRBits), .ID: ARM::GPRwithAPSRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2442 { .RegsBegin: GPRwithZR, .RegSet: GPRwithZRBits, .NameIdx: 2187, .RegsSize: 16, .RegSetSize: sizeof(GPRwithZRBits), .ID: ARM::GPRwithZRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2443 { .RegsBegin: SPR_8, .RegSet: SPR_8Bits, .NameIdx: 1365, .RegsSize: 16, .RegSetSize: sizeof(SPR_8Bits), .ID: ARM::SPR_8RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2444 { .RegsBegin: GPRnopc, .RegSet: GPRnopcBits, .NameIdx: 2287, .RegsSize: 15, .RegSetSize: sizeof(GPRnopcBits), .ID: ARM::GPRnopcRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2445 { .RegsBegin: GPRnosp, .RegSet: GPRnospBits, .NameIdx: 2458, .RegsSize: 15, .RegSetSize: sizeof(GPRnospBits), .ID: ARM::GPRnospRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2446 { .RegsBegin: GPRwithAPSR_NZCVnosp, .RegSet: GPRwithAPSR_NZCVnospBits, .NameIdx: 2508, .RegsSize: 15, .RegSetSize: sizeof(GPRwithAPSR_NZCVnospBits), .ID: ARM::GPRwithAPSR_NZCVnospRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2447 { .RegsBegin: GPRwithAPSRnosp, .RegSet: GPRwithAPSRnospBits, .NameIdx: 2466, .RegsSize: 15, .RegSetSize: sizeof(GPRwithAPSRnospBits), .ID: ARM::GPRwithAPSRnospRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2448 { .RegsBegin: GPRwithZRnosp, .RegSet: GPRwithZRnospBits, .NameIdx: 2482, .RegsSize: 15, .RegSetSize: sizeof(GPRwithZRnospBits), .ID: ARM::GPRwithZRnospRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2449 { .RegsBegin: GPRnoip, .RegSet: GPRnoipBits, .NameIdx: 2409, .RegsSize: 14, .RegSetSize: sizeof(GPRnoipBits), .ID: ARM::GPRnoipRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2450 { .RegsBegin: rGPR, .RegSet: rGPRBits, .NameIdx: 1684, .RegsSize: 14, .RegSetSize: sizeof(rGPRBits), .ID: ARM::rGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2451 { .RegsBegin: GPRnoip_and_GPRnopc, .RegSet: GPRnoip_and_GPRnopcBits, .NameIdx: 2275, .RegsSize: 13, .RegSetSize: sizeof(GPRnoip_and_GPRnopcBits), .ID: ARM::GPRnoip_and_GPRnopcRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2452 { .RegsBegin: GPRnoip_and_GPRnosp, .RegSet: GPRnoip_and_GPRnospBits, .NameIdx: 2446, .RegsSize: 13, .RegSetSize: sizeof(GPRnoip_and_GPRnospBits), .ID: ARM::GPRnoip_and_GPRnospRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2453 { .RegsBegin: GPRnoip_and_GPRwithAPSR_NZCVnosp, .RegSet: GPRnoip_and_GPRwithAPSR_NZCVnospBits, .NameIdx: 2496, .RegsSize: 12, .RegSetSize: sizeof(GPRnoip_and_GPRwithAPSR_NZCVnospBits), .ID: ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2454 { .RegsBegin: tGPRwithpc, .RegSet: tGPRwithpcBits, .NameIdx: 2264, .RegsSize: 9, .RegSetSize: sizeof(tGPRwithpcBits), .ID: ARM::tGPRwithpcRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2455 { .RegsBegin: FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8, .RegSet: FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits, .NameIdx: 1328, .RegsSize: 8, .RegSetSize: sizeof(FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits), .ID: ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2456 { .RegsBegin: hGPR, .RegSet: hGPRBits, .NameIdx: 1548, .RegsSize: 8, .RegSetSize: sizeof(hGPRBits), .ID: ARM::hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2457 { .RegsBegin: tGPR, .RegSet: tGPRBits, .NameIdx: 1712, .RegsSize: 8, .RegSetSize: sizeof(tGPRBits), .ID: ARM::tGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2458 { .RegsBegin: tGPREven, .RegSet: tGPREvenBits, .NameIdx: 2352, .RegsSize: 8, .RegSetSize: sizeof(tGPREvenBits), .ID: ARM::tGPREvenRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2459 { .RegsBegin: GPRnopc_and_hGPR, .RegSet: GPRnopc_and_hGPRBits, .NameIdx: 1536, .RegsSize: 7, .RegSetSize: sizeof(GPRnopc_and_hGPRBits), .ID: ARM::GPRnopc_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2460 { .RegsBegin: GPRnosp_and_hGPR, .RegSet: GPRnosp_and_hGPRBits, .NameIdx: 1623, .RegsSize: 7, .RegSetSize: sizeof(GPRnosp_and_hGPRBits), .ID: ARM::GPRnosp_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2461 { .RegsBegin: GPRnoip_and_hGPR, .RegSet: GPRnoip_and_hGPRBits, .NameIdx: 1577, .RegsSize: 6, .RegSetSize: sizeof(GPRnoip_and_hGPRBits), .ID: ARM::GPRnoip_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2462 { .RegsBegin: GPRnoip_and_tGPREven, .RegSet: GPRnoip_and_tGPREvenBits, .NameIdx: 2388, .RegsSize: 6, .RegSetSize: sizeof(GPRnoip_and_tGPREvenBits), .ID: ARM::GPRnoip_and_tGPREvenRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2463 { .RegsBegin: GPRnosp_and_GPRnopc_and_hGPR, .RegSet: GPRnosp_and_GPRnopc_and_hGPRBits, .NameIdx: 1524, .RegsSize: 6, .RegSetSize: sizeof(GPRnosp_and_GPRnopc_and_hGPRBits), .ID: ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2464 { .RegsBegin: tGPROdd, .RegSet: tGPROddBits, .NameIdx: 2310, .RegsSize: 6, .RegSetSize: sizeof(tGPROddBits), .ID: ARM::tGPROddRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2465 { .RegsBegin: GPRnopc_and_GPRnoip_and_hGPR, .RegSet: GPRnopc_and_GPRnoip_and_hGPRBits, .NameIdx: 1565, .RegsSize: 5, .RegSetSize: sizeof(GPRnopc_and_GPRnoip_and_hGPRBits), .ID: ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2466 { .RegsBegin: GPRnosp_and_GPRnoip_and_hGPR, .RegSet: GPRnosp_and_GPRnoip_and_hGPRBits, .NameIdx: 1594, .RegsSize: 5, .RegSetSize: sizeof(GPRnosp_and_GPRnoip_and_hGPRBits), .ID: ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2467 { .RegsBegin: tcGPR, .RegSet: tcGPRBits, .NameIdx: 1452, .RegsSize: 5, .RegSetSize: sizeof(tcGPRBits), .ID: ARM::tcGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2468 { .RegsBegin: GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR, .RegSet: GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits, .NameIdx: 1553, .RegsSize: 4, .RegSetSize: sizeof(GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits), .ID: ARM::GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2469 { .RegsBegin: hGPR_and_tGPREven, .RegSet: hGPR_and_tGPREvenBits, .NameIdx: 2343, .RegsSize: 4, .RegSetSize: sizeof(hGPR_and_tGPREvenBits), .ID: ARM::hGPR_and_tGPREvenRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2470 { .RegsBegin: tGPR_and_tGPREven, .RegSet: tGPR_and_tGPREvenBits, .NameIdx: 2361, .RegsSize: 4, .RegSetSize: sizeof(tGPR_and_tGPREvenBits), .ID: ARM::tGPR_and_tGPREvenRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2471 { .RegsBegin: tGPR_and_tGPROdd, .RegSet: tGPR_and_tGPROddBits, .NameIdx: 2318, .RegsSize: 4, .RegSetSize: sizeof(tGPR_and_tGPROddBits), .ID: ARM::tGPR_and_tGPROddRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2472 { .RegsBegin: tcGPRnotr12, .RegSet: tcGPRnotr12Bits, .NameIdx: 175, .RegsSize: 4, .RegSetSize: sizeof(tcGPRnotr12Bits), .ID: ARM::tcGPRnotr12RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2473 { .RegsBegin: tGPREven_and_tcGPR, .RegSet: tGPREven_and_tcGPRBits, .NameIdx: 1476, .RegsSize: 3, .RegSetSize: sizeof(tGPREven_and_tcGPRBits), .ID: ARM::tGPREven_and_tcGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2474 { .RegsBegin: FP_STATUS_REGS, .RegSet: FP_STATUS_REGSBits, .NameIdx: 2197, .RegsSize: 2, .RegSetSize: sizeof(FP_STATUS_REGSBits), .ID: ARM::FP_STATUS_REGSRegClassID, .RegSizeInBits: 32, .CopyCost: 255, .Allocatable: false, .BaseClass: false },
2475 { .RegsBegin: hGPR_and_GPRnoip_and_tGPREven, .RegSet: hGPR_and_GPRnoip_and_tGPREvenBits, .NameIdx: 2379, .RegsSize: 2, .RegSetSize: sizeof(hGPR_and_GPRnoip_and_tGPREvenBits), .ID: ARM::hGPR_and_GPRnoip_and_tGPREvenRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2476 { .RegsBegin: hGPR_and_tGPROdd, .RegSet: hGPR_and_tGPROddBits, .NameIdx: 2301, .RegsSize: 2, .RegSetSize: sizeof(hGPR_and_tGPROddBits), .ID: ARM::hGPR_and_tGPROddRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2477 { .RegsBegin: tGPREven_and_tcGPRnotr12, .RegSet: tGPREven_and_tcGPRnotr12Bits, .NameIdx: 162, .RegsSize: 2, .RegSetSize: sizeof(tGPREven_and_tcGPRnotr12Bits), .ID: ARM::tGPREven_and_tcGPRnotr12RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2478 { .RegsBegin: tGPROdd_and_tcGPR, .RegSet: tGPROdd_and_tcGPRBits, .NameIdx: 1458, .RegsSize: 2, .RegSetSize: sizeof(tGPROdd_and_tcGPRBits), .ID: ARM::tGPROdd_and_tcGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2479 { .RegsBegin: CCR, .RegSet: CCRBits, .NameIdx: 1435, .RegsSize: 1, .RegSetSize: sizeof(CCRBits), .ID: ARM::CCRRegClassID, .RegSizeInBits: 32, .CopyCost: 255, .Allocatable: false, .BaseClass: false },
2480 { .RegsBegin: FPCXTRegs, .RegSet: FPCXTRegsBits, .NameIdx: 2561, .RegsSize: 1, .RegSetSize: sizeof(FPCXTRegsBits), .ID: ARM::FPCXTRegsRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2481 { .RegsBegin: GPRlr, .RegSet: GPRlrBits, .NameIdx: 2555, .RegsSize: 1, .RegSetSize: sizeof(GPRlrBits), .ID: ARM::GPRlrRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2482 { .RegsBegin: GPRsp, .RegSet: GPRspBits, .NameIdx: 2440, .RegsSize: 1, .RegSetSize: sizeof(GPRspBits), .ID: ARM::GPRspRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2483 { .RegsBegin: VCCR, .RegSet: VCCRBits, .NameIdx: 1434, .RegsSize: 1, .RegSetSize: sizeof(VCCRBits), .ID: ARM::VCCRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2484 { .RegsBegin: cl_FPSCR_NZCV, .RegSet: cl_FPSCR_NZCVBits, .NameIdx: 2212, .RegsSize: 1, .RegSetSize: sizeof(cl_FPSCR_NZCVBits), .ID: ARM::cl_FPSCR_NZCVRegClassID, .RegSizeInBits: 32, .CopyCost: 255, .Allocatable: true, .BaseClass: false },
2485 { .RegsBegin: hGPR_and_tGPRwithpc, .RegSet: hGPR_and_tGPRwithpcBits, .NameIdx: 2255, .RegsSize: 1, .RegSetSize: sizeof(hGPR_and_tGPRwithpcBits), .ID: ARM::hGPR_and_tGPRwithpcRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2486 { .RegsBegin: hGPR_and_tcGPR, .RegSet: hGPR_and_tcGPRBits, .NameIdx: 1443, .RegsSize: 1, .RegSetSize: sizeof(hGPR_and_tcGPRBits), .ID: ARM::hGPR_and_tcGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2487 { .RegsBegin: DPR, .RegSet: DPRBits, .NameIdx: 1439, .RegsSize: 32, .RegSetSize: sizeof(DPRBits), .ID: ARM::DPRRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2488 { .RegsBegin: DPR_VFP2, .RegSet: DPR_VFP2Bits, .NameIdx: 222, .RegsSize: 16, .RegSetSize: sizeof(DPR_VFP2Bits), .ID: ARM::DPR_VFP2RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2489 { .RegsBegin: DPR_8, .RegSet: DPR_8Bits, .NameIdx: 460, .RegsSize: 8, .RegSetSize: sizeof(DPR_8Bits), .ID: ARM::DPR_8RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2490 { .RegsBegin: GPRPair, .RegSet: GPRPairBits, .NameIdx: 2547, .RegsSize: 7, .RegSetSize: sizeof(GPRPairBits), .ID: ARM::GPRPairRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2491 { .RegsBegin: GPRPairnosp, .RegSet: GPRPairnospBits, .NameIdx: 2529, .RegsSize: 6, .RegSetSize: sizeof(GPRPairnospBits), .ID: ARM::GPRPairnospRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2492 { .RegsBegin: GPRPair_with_gsub_0_in_tGPR, .RegSet: GPRPair_with_gsub_0_in_tGPRBits, .NameIdx: 1689, .RegsSize: 4, .RegSetSize: sizeof(GPRPair_with_gsub_0_in_tGPRBits), .ID: ARM::GPRPair_with_gsub_0_in_tGPRRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2493 { .RegsBegin: GPRPair_with_gsub_0_in_hGPR, .RegSet: GPRPair_with_gsub_0_in_hGPRBits, .NameIdx: 1656, .RegsSize: 3, .RegSetSize: sizeof(GPRPair_with_gsub_0_in_hGPRBits), .ID: ARM::GPRPair_with_gsub_0_in_hGPRRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2494 { .RegsBegin: GPRPair_with_gsub_0_in_tcGPR, .RegSet: GPRPair_with_gsub_0_in_tcGPRBits, .NameIdx: 1495, .RegsSize: 3, .RegSetSize: sizeof(GPRPair_with_gsub_0_in_tcGPRBits), .ID: ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2495 { .RegsBegin: GPRPair_with_gsub_0_in_tcGPRnotr12, .RegSet: GPRPair_with_gsub_0_in_tcGPRnotr12Bits, .NameIdx: 187, .RegsSize: 2, .RegSetSize: sizeof(GPRPair_with_gsub_0_in_tcGPRnotr12Bits), .ID: ARM::GPRPair_with_gsub_0_in_tcGPRnotr12RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2496 { .RegsBegin: GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR, .RegSet: GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits, .NameIdx: 1640, .RegsSize: 2, .RegSetSize: sizeof(GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits), .ID: ARM::GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2497 { .RegsBegin: GPRPair_with_gsub_1_in_GPRsp, .RegSet: GPRPair_with_gsub_1_in_GPRspBits, .NameIdx: 2417, .RegsSize: 1, .RegSetSize: sizeof(GPRPair_with_gsub_1_in_GPRspBits), .ID: ARM::GPRPair_with_gsub_1_in_GPRspRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2498 { .RegsBegin: DPairSpc, .RegSet: DPairSpcBits, .NameIdx: 2246, .RegsSize: 30, .RegSetSize: sizeof(DPairSpcBits), .ID: ARM::DPairSpcRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2499 { .RegsBegin: DPairSpc_with_ssub_0, .RegSet: DPairSpc_with_ssub_0Bits, .NameIdx: 85, .RegsSize: 16, .RegSetSize: sizeof(DPairSpc_with_ssub_0Bits), .ID: ARM::DPairSpc_with_ssub_0RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2500 { .RegsBegin: DPairSpc_with_ssub_4, .RegSet: DPairSpc_with_ssub_4Bits, .NameIdx: 359, .RegsSize: 14, .RegSetSize: sizeof(DPairSpc_with_ssub_4Bits), .ID: ARM::DPairSpc_with_ssub_4RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2501 { .RegsBegin: DPairSpc_with_dsub_0_in_DPR_8, .RegSet: DPairSpc_with_dsub_0_in_DPR_8Bits, .NameIdx: 498, .RegsSize: 8, .RegSetSize: sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), .ID: ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2502 { .RegsBegin: DPairSpc_with_dsub_2_in_DPR_8, .RegSet: DPairSpc_with_dsub_2_in_DPR_8Bits, .NameIdx: 858, .RegsSize: 6, .RegSetSize: sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), .ID: ARM::DPairSpc_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2503 { .RegsBegin: DPair, .RegSet: DPairBits, .NameIdx: 2541, .RegsSize: 31, .RegSetSize: sizeof(DPairBits), .ID: ARM::DPairRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2504 { .RegsBegin: DPair_with_ssub_0, .RegSet: DPair_with_ssub_0Bits, .NameIdx: 144, .RegsSize: 16, .RegSetSize: sizeof(DPair_with_ssub_0Bits), .ID: ARM::DPair_with_ssub_0RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2505 { .RegsBegin: QPR, .RegSet: QPRBits, .NameIdx: 1769, .RegsSize: 16, .RegSetSize: sizeof(QPRBits), .ID: ARM::QPRRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2506 { .RegsBegin: DPair_with_ssub_2, .RegSet: DPair_with_ssub_2Bits, .NameIdx: 278, .RegsSize: 15, .RegSetSize: sizeof(DPair_with_ssub_2Bits), .ID: ARM::DPair_with_ssub_2RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2507 { .RegsBegin: DPair_with_dsub_0_in_DPR_8, .RegSet: DPair_with_dsub_0_in_DPR_8Bits, .NameIdx: 584, .RegsSize: 8, .RegSetSize: sizeof(DPair_with_dsub_0_in_DPR_8Bits), .ID: ARM::DPair_with_dsub_0_in_DPR_8RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2508 { .RegsBegin: MQPR, .RegSet: MQPRBits, .NameIdx: 1768, .RegsSize: 8, .RegSetSize: sizeof(MQPRBits), .ID: ARM::MQPRRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2509 { .RegsBegin: QPR_VFP2, .RegSet: QPR_VFP2Bits, .NameIdx: 231, .RegsSize: 8, .RegSetSize: sizeof(QPR_VFP2Bits), .ID: ARM::QPR_VFP2RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2510 { .RegsBegin: DPair_with_dsub_1_in_DPR_8, .RegSet: DPair_with_dsub_1_in_DPR_8Bits, .NameIdx: 667, .RegsSize: 7, .RegSetSize: sizeof(DPair_with_dsub_1_in_DPR_8Bits), .ID: ARM::DPair_with_dsub_1_in_DPR_8RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2511 { .RegsBegin: QPR_8, .RegSet: QPR_8Bits, .NameIdx: 1166, .RegsSize: 4, .RegSetSize: sizeof(QPR_8Bits), .ID: ARM::QPR_8RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2512 { .RegsBegin: DTriple, .RegSet: DTripleBits, .NameIdx: 2335, .RegsSize: 30, .RegSetSize: sizeof(DTripleBits), .ID: ARM::DTripleRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2513 { .RegsBegin: DTripleSpc, .RegSet: DTripleSpcBits, .NameIdx: 2235, .RegsSize: 28, .RegSetSize: sizeof(DTripleSpcBits), .ID: ARM::DTripleSpcRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2514 { .RegsBegin: DTripleSpc_with_ssub_0, .RegSet: DTripleSpc_with_ssub_0Bits, .NameIdx: 62, .RegsSize: 16, .RegSetSize: sizeof(DTripleSpc_with_ssub_0Bits), .ID: ARM::DTripleSpc_with_ssub_0RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2515 { .RegsBegin: DTriple_with_ssub_0, .RegSet: DTriple_with_ssub_0Bits, .NameIdx: 124, .RegsSize: 16, .RegSetSize: sizeof(DTriple_with_ssub_0Bits), .ID: ARM::DTriple_with_ssub_0RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2516 { .RegsBegin: DTriple_with_qsub_0_in_QPR, .RegSet: DTriple_with_qsub_0_in_QPRBits, .NameIdx: 1994, .RegsSize: 15, .RegSetSize: sizeof(DTriple_with_qsub_0_in_QPRBits), .ID: ARM::DTriple_with_qsub_0_in_QPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2517 { .RegsBegin: DTriple_with_ssub_2, .RegSet: DTriple_with_ssub_2Bits, .NameIdx: 258, .RegsSize: 15, .RegSetSize: sizeof(DTriple_with_ssub_2Bits), .ID: ARM::DTriple_with_ssub_2RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2518 { .RegsBegin: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, .RegSet: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, .NameIdx: 2113, .RegsSize: 15, .RegSetSize: sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), .ID: ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2519 { .RegsBegin: DTripleSpc_with_ssub_4, .RegSet: DTripleSpc_with_ssub_4Bits, .NameIdx: 336, .RegsSize: 14, .RegSetSize: sizeof(DTripleSpc_with_ssub_4Bits), .ID: ARM::DTripleSpc_with_ssub_4RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2520 { .RegsBegin: DTriple_with_ssub_4, .RegSet: DTriple_with_ssub_4Bits, .NameIdx: 398, .RegsSize: 14, .RegSetSize: sizeof(DTriple_with_ssub_4Bits), .ID: ARM::DTriple_with_ssub_4RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2521 { .RegsBegin: DTripleSpc_with_ssub_8, .RegSet: DTripleSpc_with_ssub_8Bits, .NameIdx: 1411, .RegsSize: 12, .RegSetSize: sizeof(DTripleSpc_with_ssub_8Bits), .ID: ARM::DTripleSpc_with_ssub_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2522 { .RegsBegin: DTripleSpc_with_dsub_0_in_DPR_8, .RegSet: DTripleSpc_with_dsub_0_in_DPR_8Bits, .NameIdx: 466, .RegsSize: 8, .RegSetSize: sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), .ID: ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2523 { .RegsBegin: DTriple_with_dsub_0_in_DPR_8, .RegSet: DTriple_with_dsub_0_in_DPR_8Bits, .NameIdx: 555, .RegsSize: 8, .RegSetSize: sizeof(DTriple_with_dsub_0_in_DPR_8Bits), .ID: ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2524 { .RegsBegin: DTriple_with_qsub_0_in_MQPR, .RegSet: DTriple_with_qsub_0_in_MQPRBits, .NameIdx: 1745, .RegsSize: 8, .RegSetSize: sizeof(DTriple_with_qsub_0_in_MQPRBits), .ID: ARM::DTriple_with_qsub_0_in_MQPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2525 { .RegsBegin: DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, .RegSet: DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, .NameIdx: 2089, .RegsSize: 8, .RegSetSize: sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), .ID: ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2526 { .RegsBegin: DTriple_with_dsub_1_in_DPR_8, .RegSet: DTriple_with_dsub_1_in_DPR_8Bits, .NameIdx: 638, .RegsSize: 7, .RegSetSize: sizeof(DTriple_with_dsub_1_in_DPR_8Bits), .ID: ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2527 { .RegsBegin: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, .RegSet: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, .NameIdx: 1931, .RegsSize: 7, .RegSetSize: sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), .ID: ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2528 { .RegsBegin: DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR, .RegSet: DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits, .NameIdx: 1721, .RegsSize: 7, .RegSetSize: sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits), .ID: ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2529 { .RegsBegin: DTripleSpc_with_dsub_2_in_DPR_8, .RegSet: DTripleSpc_with_dsub_2_in_DPR_8Bits, .NameIdx: 826, .RegsSize: 6, .RegSetSize: sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), .ID: ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2530 { .RegsBegin: DTriple_with_dsub_2_in_DPR_8, .RegSet: DTriple_with_dsub_2_in_DPR_8Bits, .NameIdx: 1003, .RegsSize: 6, .RegSetSize: sizeof(DTriple_with_dsub_2_in_DPR_8Bits), .ID: ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2531 { .RegsBegin: DTripleSpc_with_dsub_4_in_DPR_8, .RegSet: DTripleSpc_with_dsub_4_in_DPR_8Bits, .NameIdx: 1089, .RegsSize: 4, .RegSetSize: sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), .ID: ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2532 { .RegsBegin: DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, .RegSet: DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, .NameIdx: 1898, .RegsSize: 4, .RegSetSize: sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), .ID: ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2533 { .RegsBegin: DTriple_with_qsub_0_in_QPR_8, .RegSet: DTriple_with_qsub_0_in_QPR_8Bits, .NameIdx: 1172, .RegsSize: 4, .RegSetSize: sizeof(DTriple_with_qsub_0_in_QPR_8Bits), .ID: ARM::DTriple_with_qsub_0_in_QPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2534 { .RegsBegin: DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8, .RegSet: DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8Bits, .NameIdx: 971, .RegsSize: 3, .RegSetSize: sizeof(DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8Bits), .ID: ARM::DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2535 { .RegsBegin: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, .RegSet: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, .NameIdx: 1278, .RegsSize: 3, .RegSetSize: sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), .ID: ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2536 { .RegsBegin: DQuadSpc, .RegSet: DQuadSpcBits, .NameIdx: 2226, .RegsSize: 28, .RegSetSize: sizeof(DQuadSpcBits), .ID: ARM::DQuadSpcRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2537 { .RegsBegin: DQuadSpc_with_ssub_0, .RegSet: DQuadSpc_with_ssub_0Bits, .NameIdx: 41, .RegsSize: 16, .RegSetSize: sizeof(DQuadSpc_with_ssub_0Bits), .ID: ARM::DQuadSpc_with_ssub_0RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2538 { .RegsBegin: DQuadSpc_with_ssub_4, .RegSet: DQuadSpc_with_ssub_4Bits, .NameIdx: 315, .RegsSize: 14, .RegSetSize: sizeof(DQuadSpc_with_ssub_4Bits), .ID: ARM::DQuadSpc_with_ssub_4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2539 { .RegsBegin: DQuadSpc_with_ssub_8, .RegSet: DQuadSpc_with_ssub_8Bits, .NameIdx: 1390, .RegsSize: 12, .RegSetSize: sizeof(DQuadSpc_with_ssub_8Bits), .ID: ARM::DQuadSpc_with_ssub_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2540 { .RegsBegin: DQuadSpc_with_dsub_0_in_DPR_8, .RegSet: DQuadSpc_with_dsub_0_in_DPR_8Bits, .NameIdx: 436, .RegsSize: 8, .RegSetSize: sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), .ID: ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2541 { .RegsBegin: DQuadSpc_with_dsub_2_in_DPR_8, .RegSet: DQuadSpc_with_dsub_2_in_DPR_8Bits, .NameIdx: 796, .RegsSize: 6, .RegSetSize: sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), .ID: ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2542 { .RegsBegin: DQuadSpc_with_dsub_4_in_DPR_8, .RegSet: DQuadSpc_with_dsub_4_in_DPR_8Bits, .NameIdx: 1059, .RegsSize: 4, .RegSetSize: sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), .ID: ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2543 { .RegsBegin: DQuad, .RegSet: DQuadBits, .NameIdx: 2295, .RegsSize: 29, .RegSetSize: sizeof(DQuadBits), .ID: ARM::DQuadRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2544 { .RegsBegin: DQuad_with_ssub_0, .RegSet: DQuad_with_ssub_0Bits, .NameIdx: 106, .RegsSize: 16, .RegSetSize: sizeof(DQuad_with_ssub_0Bits), .ID: ARM::DQuad_with_ssub_0RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2545 { .RegsBegin: DQuad_with_ssub_2, .RegSet: DQuad_with_ssub_2Bits, .NameIdx: 240, .RegsSize: 15, .RegSetSize: sizeof(DQuad_with_ssub_2Bits), .ID: ARM::DQuad_with_ssub_2RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2546 { .RegsBegin: QQPR, .RegSet: QQPRBits, .NameIdx: 1981, .RegsSize: 15, .RegSetSize: sizeof(QQPRBits), .ID: ARM::QQPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2547 { .RegsBegin: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, .RegSet: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, .NameIdx: 2043, .RegsSize: 14, .RegSetSize: sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2548 { .RegsBegin: DQuad_with_ssub_4, .RegSet: DQuad_with_ssub_4Bits, .NameIdx: 380, .RegsSize: 14, .RegSetSize: sizeof(DQuad_with_ssub_4Bits), .ID: ARM::DQuad_with_ssub_4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2549 { .RegsBegin: DQuad_with_ssub_6, .RegSet: DQuad_with_ssub_6Bits, .NameIdx: 418, .RegsSize: 13, .RegSetSize: sizeof(DQuad_with_ssub_6Bits), .ID: ARM::DQuad_with_ssub_6RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2550 { .RegsBegin: DQuad_with_dsub_0_in_DPR_8, .RegSet: DQuad_with_dsub_0_in_DPR_8Bits, .NameIdx: 528, .RegsSize: 8, .RegSetSize: sizeof(DQuad_with_dsub_0_in_DPR_8Bits), .ID: ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2551 { .RegsBegin: DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, .RegSet: DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, .NameIdx: 2021, .RegsSize: 8, .RegSetSize: sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), .ID: ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2552 { .RegsBegin: QQPR_with_ssub_0, .RegSet: QQPR_with_ssub_0Bits, .NameIdx: 2, .RegsSize: 8, .RegSetSize: sizeof(QQPR_with_ssub_0Bits), .ID: ARM::QQPR_with_ssub_0RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2553 { .RegsBegin: DQuad_with_dsub_1_in_DPR_8, .RegSet: DQuad_with_dsub_1_in_DPR_8Bits, .NameIdx: 611, .RegsSize: 7, .RegSetSize: sizeof(DQuad_with_dsub_1_in_DPR_8Bits), .ID: ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2554 { .RegsBegin: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, .RegSet: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, .NameIdx: 1795, .RegsSize: 7, .RegSetSize: sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2555 { .RegsBegin: MQQPR, .RegSet: MQQPRBits, .NameIdx: 1980, .RegsSize: 7, .RegSetSize: sizeof(MQQPRBits), .ID: ARM::MQQPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2556 { .RegsBegin: DQuad_with_dsub_2_in_DPR_8, .RegSet: DQuad_with_dsub_2_in_DPR_8Bits, .NameIdx: 888, .RegsSize: 6, .RegSetSize: sizeof(DQuad_with_dsub_2_in_DPR_8Bits), .ID: ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2557 { .RegsBegin: DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, .RegSet: DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, .NameIdx: 1773, .RegsSize: 6, .RegSetSize: sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), .ID: ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2558 { .RegsBegin: DQuad_with_dsub_3_in_DPR_8, .RegSet: DQuad_with_dsub_3_in_DPR_8Bits, .NameIdx: 1032, .RegsSize: 5, .RegSetSize: sizeof(DQuad_with_dsub_3_in_DPR_8Bits), .ID: ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2559 { .RegsBegin: DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, .RegSet: DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, .NameIdx: 1842, .RegsSize: 4, .RegSetSize: sizeof(DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), .ID: ARM::DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2560 { .RegsBegin: MQQPR_with_qsub_0_in_QPR_8, .RegSet: MQQPR_with_qsub_0_in_QPR_8Bits, .NameIdx: 1145, .RegsSize: 4, .RegSetSize: sizeof(MQQPR_with_qsub_0_in_QPR_8Bits), .ID: ARM::MQQPR_with_qsub_0_in_QPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2561 { .RegsBegin: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, .RegSet: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, .NameIdx: 1230, .RegsSize: 3, .RegSetSize: sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2562 { .RegsBegin: MQQPR_with_dsub_2_in_DPR_8, .RegSet: MQQPR_with_dsub_2_in_DPR_8Bits, .NameIdx: 718, .RegsSize: 3, .RegSetSize: sizeof(MQQPR_with_dsub_2_in_DPR_8Bits), .ID: ARM::MQQPR_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2563 { .RegsBegin: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8, .RegSet: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8Bits, .NameIdx: 915, .RegsSize: 2, .RegSetSize: sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8Bits), .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2564 { .RegsBegin: QQQQPR, .RegSet: QQQQPRBits, .NameIdx: 1987, .RegsSize: 13, .RegSetSize: sizeof(QQQQPRBits), .ID: ARM::QQQQPRRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2565 { .RegsBegin: QQQQPR_with_ssub_0, .RegSet: QQQQPR_with_ssub_0Bits, .NameIdx: 0, .RegsSize: 8, .RegSetSize: sizeof(QQQQPR_with_ssub_0Bits), .ID: ARM::QQQQPR_with_ssub_0RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2566 { .RegsBegin: QQQQPR_with_ssub_4, .RegSet: QQQQPR_with_ssub_4Bits, .NameIdx: 296, .RegsSize: 7, .RegSetSize: sizeof(QQQQPR_with_ssub_4Bits), .ID: ARM::QQQQPR_with_ssub_4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2567 { .RegsBegin: QQQQPR_with_ssub_8, .RegSet: QQQQPR_with_ssub_8Bits, .NameIdx: 1371, .RegsSize: 6, .RegSetSize: sizeof(QQQQPR_with_ssub_8Bits), .ID: ARM::QQQQPR_with_ssub_8RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2568 { .RegsBegin: MQQQQPR, .RegSet: MQQQQPRBits, .NameIdx: 1986, .RegsSize: 5, .RegSetSize: sizeof(MQQQQPRBits), .ID: ARM::MQQQQPRRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2569 { .RegsBegin: MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8, .RegSet: MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8Bits, .NameIdx: 1121, .RegsSize: 4, .RegSetSize: sizeof(MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8Bits), .ID: ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2570 { .RegsBegin: MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8, .RegSet: MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8Bits, .NameIdx: 694, .RegsSize: 3, .RegSetSize: sizeof(MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8Bits), .ID: ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2571 { .RegsBegin: MQQQQPR_with_qsub_2_in_QPR_8, .RegSet: MQQQQPR_with_qsub_2_in_QPR_8Bits, .NameIdx: 1201, .RegsSize: 2, .RegSetSize: sizeof(MQQQQPR_with_qsub_2_in_QPR_8Bits), .ID: ARM::MQQQQPR_with_qsub_2_in_QPR_8RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2572 { .RegsBegin: MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8, .RegSet: MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8Bits, .NameIdx: 745, .RegsSize: 1, .RegSetSize: sizeof(MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8Bits), .ID: ARM::MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2573};
2574
2575// ARM Dwarf<->LLVM register mappings.
2576extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = {
2577 { .FromReg: 0U, .ToReg: ARM::R0 },
2578 { .FromReg: 1U, .ToReg: ARM::R1 },
2579 { .FromReg: 2U, .ToReg: ARM::R2 },
2580 { .FromReg: 3U, .ToReg: ARM::R3 },
2581 { .FromReg: 4U, .ToReg: ARM::R4 },
2582 { .FromReg: 5U, .ToReg: ARM::R5 },
2583 { .FromReg: 6U, .ToReg: ARM::R6 },
2584 { .FromReg: 7U, .ToReg: ARM::R7 },
2585 { .FromReg: 8U, .ToReg: ARM::R8 },
2586 { .FromReg: 9U, .ToReg: ARM::R9 },
2587 { .FromReg: 10U, .ToReg: ARM::R10 },
2588 { .FromReg: 11U, .ToReg: ARM::R11 },
2589 { .FromReg: 12U, .ToReg: ARM::R12 },
2590 { .FromReg: 13U, .ToReg: ARM::SP },
2591 { .FromReg: 14U, .ToReg: ARM::LR },
2592 { .FromReg: 15U, .ToReg: ARM::ZR },
2593 { .FromReg: 143U, .ToReg: ARM::RA_AUTH_CODE },
2594 { .FromReg: 256U, .ToReg: ARM::D0 },
2595 { .FromReg: 257U, .ToReg: ARM::D1 },
2596 { .FromReg: 258U, .ToReg: ARM::D2 },
2597 { .FromReg: 259U, .ToReg: ARM::D3 },
2598 { .FromReg: 260U, .ToReg: ARM::D4 },
2599 { .FromReg: 261U, .ToReg: ARM::D5 },
2600 { .FromReg: 262U, .ToReg: ARM::D6 },
2601 { .FromReg: 263U, .ToReg: ARM::D7 },
2602 { .FromReg: 264U, .ToReg: ARM::D8 },
2603 { .FromReg: 265U, .ToReg: ARM::D9 },
2604 { .FromReg: 266U, .ToReg: ARM::D10 },
2605 { .FromReg: 267U, .ToReg: ARM::D11 },
2606 { .FromReg: 268U, .ToReg: ARM::D12 },
2607 { .FromReg: 269U, .ToReg: ARM::D13 },
2608 { .FromReg: 270U, .ToReg: ARM::D14 },
2609 { .FromReg: 271U, .ToReg: ARM::D15 },
2610 { .FromReg: 272U, .ToReg: ARM::D16 },
2611 { .FromReg: 273U, .ToReg: ARM::D17 },
2612 { .FromReg: 274U, .ToReg: ARM::D18 },
2613 { .FromReg: 275U, .ToReg: ARM::D19 },
2614 { .FromReg: 276U, .ToReg: ARM::D20 },
2615 { .FromReg: 277U, .ToReg: ARM::D21 },
2616 { .FromReg: 278U, .ToReg: ARM::D22 },
2617 { .FromReg: 279U, .ToReg: ARM::D23 },
2618 { .FromReg: 280U, .ToReg: ARM::D24 },
2619 { .FromReg: 281U, .ToReg: ARM::D25 },
2620 { .FromReg: 282U, .ToReg: ARM::D26 },
2621 { .FromReg: 283U, .ToReg: ARM::D27 },
2622 { .FromReg: 284U, .ToReg: ARM::D28 },
2623 { .FromReg: 285U, .ToReg: ARM::D29 },
2624 { .FromReg: 286U, .ToReg: ARM::D30 },
2625 { .FromReg: 287U, .ToReg: ARM::D31 },
2626};
2627extern const unsigned ARMDwarfFlavour0Dwarf2LSize = std::size(ARMDwarfFlavour0Dwarf2L);
2628
2629extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = {
2630 { .FromReg: 0U, .ToReg: ARM::R0 },
2631 { .FromReg: 1U, .ToReg: ARM::R1 },
2632 { .FromReg: 2U, .ToReg: ARM::R2 },
2633 { .FromReg: 3U, .ToReg: ARM::R3 },
2634 { .FromReg: 4U, .ToReg: ARM::R4 },
2635 { .FromReg: 5U, .ToReg: ARM::R5 },
2636 { .FromReg: 6U, .ToReg: ARM::R6 },
2637 { .FromReg: 7U, .ToReg: ARM::R7 },
2638 { .FromReg: 8U, .ToReg: ARM::R8 },
2639 { .FromReg: 9U, .ToReg: ARM::R9 },
2640 { .FromReg: 10U, .ToReg: ARM::R10 },
2641 { .FromReg: 11U, .ToReg: ARM::R11 },
2642 { .FromReg: 12U, .ToReg: ARM::R12 },
2643 { .FromReg: 13U, .ToReg: ARM::SP },
2644 { .FromReg: 14U, .ToReg: ARM::LR },
2645 { .FromReg: 15U, .ToReg: ARM::ZR },
2646 { .FromReg: 143U, .ToReg: ARM::RA_AUTH_CODE },
2647 { .FromReg: 256U, .ToReg: ARM::D0 },
2648 { .FromReg: 257U, .ToReg: ARM::D1 },
2649 { .FromReg: 258U, .ToReg: ARM::D2 },
2650 { .FromReg: 259U, .ToReg: ARM::D3 },
2651 { .FromReg: 260U, .ToReg: ARM::D4 },
2652 { .FromReg: 261U, .ToReg: ARM::D5 },
2653 { .FromReg: 262U, .ToReg: ARM::D6 },
2654 { .FromReg: 263U, .ToReg: ARM::D7 },
2655 { .FromReg: 264U, .ToReg: ARM::D8 },
2656 { .FromReg: 265U, .ToReg: ARM::D9 },
2657 { .FromReg: 266U, .ToReg: ARM::D10 },
2658 { .FromReg: 267U, .ToReg: ARM::D11 },
2659 { .FromReg: 268U, .ToReg: ARM::D12 },
2660 { .FromReg: 269U, .ToReg: ARM::D13 },
2661 { .FromReg: 270U, .ToReg: ARM::D14 },
2662 { .FromReg: 271U, .ToReg: ARM::D15 },
2663 { .FromReg: 272U, .ToReg: ARM::D16 },
2664 { .FromReg: 273U, .ToReg: ARM::D17 },
2665 { .FromReg: 274U, .ToReg: ARM::D18 },
2666 { .FromReg: 275U, .ToReg: ARM::D19 },
2667 { .FromReg: 276U, .ToReg: ARM::D20 },
2668 { .FromReg: 277U, .ToReg: ARM::D21 },
2669 { .FromReg: 278U, .ToReg: ARM::D22 },
2670 { .FromReg: 279U, .ToReg: ARM::D23 },
2671 { .FromReg: 280U, .ToReg: ARM::D24 },
2672 { .FromReg: 281U, .ToReg: ARM::D25 },
2673 { .FromReg: 282U, .ToReg: ARM::D26 },
2674 { .FromReg: 283U, .ToReg: ARM::D27 },
2675 { .FromReg: 284U, .ToReg: ARM::D28 },
2676 { .FromReg: 285U, .ToReg: ARM::D29 },
2677 { .FromReg: 286U, .ToReg: ARM::D30 },
2678 { .FromReg: 287U, .ToReg: ARM::D31 },
2679};
2680extern const unsigned ARMEHFlavour0Dwarf2LSize = std::size(ARMEHFlavour0Dwarf2L);
2681
2682extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = {
2683 { .FromReg: ARM::LR, .ToReg: 14U },
2684 { .FromReg: ARM::PC, .ToReg: 15U },
2685 { .FromReg: ARM::RA_AUTH_CODE, .ToReg: 143U },
2686 { .FromReg: ARM::SP, .ToReg: 13U },
2687 { .FromReg: ARM::ZR, .ToReg: 15U },
2688 { .FromReg: ARM::D0, .ToReg: 256U },
2689 { .FromReg: ARM::D1, .ToReg: 257U },
2690 { .FromReg: ARM::D2, .ToReg: 258U },
2691 { .FromReg: ARM::D3, .ToReg: 259U },
2692 { .FromReg: ARM::D4, .ToReg: 260U },
2693 { .FromReg: ARM::D5, .ToReg: 261U },
2694 { .FromReg: ARM::D6, .ToReg: 262U },
2695 { .FromReg: ARM::D7, .ToReg: 263U },
2696 { .FromReg: ARM::D8, .ToReg: 264U },
2697 { .FromReg: ARM::D9, .ToReg: 265U },
2698 { .FromReg: ARM::D10, .ToReg: 266U },
2699 { .FromReg: ARM::D11, .ToReg: 267U },
2700 { .FromReg: ARM::D12, .ToReg: 268U },
2701 { .FromReg: ARM::D13, .ToReg: 269U },
2702 { .FromReg: ARM::D14, .ToReg: 270U },
2703 { .FromReg: ARM::D15, .ToReg: 271U },
2704 { .FromReg: ARM::D16, .ToReg: 272U },
2705 { .FromReg: ARM::D17, .ToReg: 273U },
2706 { .FromReg: ARM::D18, .ToReg: 274U },
2707 { .FromReg: ARM::D19, .ToReg: 275U },
2708 { .FromReg: ARM::D20, .ToReg: 276U },
2709 { .FromReg: ARM::D21, .ToReg: 277U },
2710 { .FromReg: ARM::D22, .ToReg: 278U },
2711 { .FromReg: ARM::D23, .ToReg: 279U },
2712 { .FromReg: ARM::D24, .ToReg: 280U },
2713 { .FromReg: ARM::D25, .ToReg: 281U },
2714 { .FromReg: ARM::D26, .ToReg: 282U },
2715 { .FromReg: ARM::D27, .ToReg: 283U },
2716 { .FromReg: ARM::D28, .ToReg: 284U },
2717 { .FromReg: ARM::D29, .ToReg: 285U },
2718 { .FromReg: ARM::D30, .ToReg: 286U },
2719 { .FromReg: ARM::D31, .ToReg: 287U },
2720 { .FromReg: ARM::R0, .ToReg: 0U },
2721 { .FromReg: ARM::R1, .ToReg: 1U },
2722 { .FromReg: ARM::R2, .ToReg: 2U },
2723 { .FromReg: ARM::R3, .ToReg: 3U },
2724 { .FromReg: ARM::R4, .ToReg: 4U },
2725 { .FromReg: ARM::R5, .ToReg: 5U },
2726 { .FromReg: ARM::R6, .ToReg: 6U },
2727 { .FromReg: ARM::R7, .ToReg: 7U },
2728 { .FromReg: ARM::R8, .ToReg: 8U },
2729 { .FromReg: ARM::R9, .ToReg: 9U },
2730 { .FromReg: ARM::R10, .ToReg: 10U },
2731 { .FromReg: ARM::R11, .ToReg: 11U },
2732 { .FromReg: ARM::R12, .ToReg: 12U },
2733};
2734extern const unsigned ARMDwarfFlavour0L2DwarfSize = std::size(ARMDwarfFlavour0L2Dwarf);
2735
2736extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = {
2737 { .FromReg: ARM::LR, .ToReg: 14U },
2738 { .FromReg: ARM::PC, .ToReg: 15U },
2739 { .FromReg: ARM::RA_AUTH_CODE, .ToReg: 143U },
2740 { .FromReg: ARM::SP, .ToReg: 13U },
2741 { .FromReg: ARM::ZR, .ToReg: 15U },
2742 { .FromReg: ARM::D0, .ToReg: 256U },
2743 { .FromReg: ARM::D1, .ToReg: 257U },
2744 { .FromReg: ARM::D2, .ToReg: 258U },
2745 { .FromReg: ARM::D3, .ToReg: 259U },
2746 { .FromReg: ARM::D4, .ToReg: 260U },
2747 { .FromReg: ARM::D5, .ToReg: 261U },
2748 { .FromReg: ARM::D6, .ToReg: 262U },
2749 { .FromReg: ARM::D7, .ToReg: 263U },
2750 { .FromReg: ARM::D8, .ToReg: 264U },
2751 { .FromReg: ARM::D9, .ToReg: 265U },
2752 { .FromReg: ARM::D10, .ToReg: 266U },
2753 { .FromReg: ARM::D11, .ToReg: 267U },
2754 { .FromReg: ARM::D12, .ToReg: 268U },
2755 { .FromReg: ARM::D13, .ToReg: 269U },
2756 { .FromReg: ARM::D14, .ToReg: 270U },
2757 { .FromReg: ARM::D15, .ToReg: 271U },
2758 { .FromReg: ARM::D16, .ToReg: 272U },
2759 { .FromReg: ARM::D17, .ToReg: 273U },
2760 { .FromReg: ARM::D18, .ToReg: 274U },
2761 { .FromReg: ARM::D19, .ToReg: 275U },
2762 { .FromReg: ARM::D20, .ToReg: 276U },
2763 { .FromReg: ARM::D21, .ToReg: 277U },
2764 { .FromReg: ARM::D22, .ToReg: 278U },
2765 { .FromReg: ARM::D23, .ToReg: 279U },
2766 { .FromReg: ARM::D24, .ToReg: 280U },
2767 { .FromReg: ARM::D25, .ToReg: 281U },
2768 { .FromReg: ARM::D26, .ToReg: 282U },
2769 { .FromReg: ARM::D27, .ToReg: 283U },
2770 { .FromReg: ARM::D28, .ToReg: 284U },
2771 { .FromReg: ARM::D29, .ToReg: 285U },
2772 { .FromReg: ARM::D30, .ToReg: 286U },
2773 { .FromReg: ARM::D31, .ToReg: 287U },
2774 { .FromReg: ARM::R0, .ToReg: 0U },
2775 { .FromReg: ARM::R1, .ToReg: 1U },
2776 { .FromReg: ARM::R2, .ToReg: 2U },
2777 { .FromReg: ARM::R3, .ToReg: 3U },
2778 { .FromReg: ARM::R4, .ToReg: 4U },
2779 { .FromReg: ARM::R5, .ToReg: 5U },
2780 { .FromReg: ARM::R6, .ToReg: 6U },
2781 { .FromReg: ARM::R7, .ToReg: 7U },
2782 { .FromReg: ARM::R8, .ToReg: 8U },
2783 { .FromReg: ARM::R9, .ToReg: 9U },
2784 { .FromReg: ARM::R10, .ToReg: 10U },
2785 { .FromReg: ARM::R11, .ToReg: 11U },
2786 { .FromReg: ARM::R12, .ToReg: 12U },
2787};
2788extern const unsigned ARMEHFlavour0L2DwarfSize = std::size(ARMEHFlavour0L2Dwarf);
2789
2790extern const uint16_t ARMRegEncodingTable[] = {
2791 0,
2792 15,
2793 15,
2794 0,
2795 14,
2796 15,
2797 8,
2798 9,
2799 3,
2800 3,
2801 2,
2802 3,
2803 0,
2804 4,
2805 14,
2806 15,
2807 12,
2808 13,
2809 2,
2810 64,
2811 15,
2812 0,
2813 1,
2814 2,
2815 3,
2816 4,
2817 5,
2818 6,
2819 7,
2820 8,
2821 9,
2822 10,
2823 11,
2824 12,
2825 13,
2826 14,
2827 15,
2828 16,
2829 17,
2830 18,
2831 19,
2832 20,
2833 21,
2834 22,
2835 23,
2836 24,
2837 25,
2838 26,
2839 27,
2840 28,
2841 29,
2842 30,
2843 31,
2844 10,
2845 7,
2846 6,
2847 5,
2848 13,
2849 0,
2850 1,
2851 2,
2852 3,
2853 4,
2854 5,
2855 6,
2856 7,
2857 8,
2858 9,
2859 10,
2860 11,
2861 12,
2862 13,
2863 14,
2864 15,
2865 0,
2866 1,
2867 2,
2868 3,
2869 4,
2870 5,
2871 6,
2872 7,
2873 8,
2874 9,
2875 10,
2876 11,
2877 12,
2878 0,
2879 1,
2880 2,
2881 3,
2882 4,
2883 5,
2884 6,
2885 7,
2886 8,
2887 9,
2888 10,
2889 11,
2890 12,
2891 13,
2892 14,
2893 15,
2894 16,
2895 17,
2896 18,
2897 19,
2898 20,
2899 21,
2900 22,
2901 23,
2902 24,
2903 25,
2904 26,
2905 27,
2906 28,
2907 29,
2908 30,
2909 31,
2910 0,
2911 1,
2912 2,
2913 3,
2914 4,
2915 5,
2916 6,
2917 7,
2918 8,
2919 9,
2920 10,
2921 11,
2922 12,
2923 13,
2924 14,
2925 15,
2926 16,
2927 17,
2928 18,
2929 19,
2930 20,
2931 21,
2932 22,
2933 23,
2934 24,
2935 25,
2936 26,
2937 27,
2938 28,
2939 29,
2940 0,
2941 1,
2942 2,
2943 3,
2944 4,
2945 5,
2946 6,
2947 7,
2948 8,
2949 9,
2950 10,
2951 11,
2952 12,
2953 13,
2954 14,
2955 0,
2956 1,
2957 2,
2958 3,
2959 4,
2960 5,
2961 6,
2962 7,
2963 8,
2964 9,
2965 10,
2966 11,
2967 12,
2968 0,
2969 2,
2970 4,
2971 6,
2972 8,
2973 10,
2974 12,
2975 0,
2976 1,
2977 2,
2978 3,
2979 4,
2980 5,
2981 6,
2982 7,
2983 8,
2984 9,
2985 10,
2986 11,
2987 12,
2988 13,
2989 14,
2990 15,
2991 16,
2992 17,
2993 18,
2994 19,
2995 20,
2996 21,
2997 22,
2998 23,
2999 24,
3000 25,
3001 26,
3002 27,
3003 28,
3004 29,
3005 0,
3006 1,
3007 2,
3008 3,
3009 4,
3010 5,
3011 6,
3012 7,
3013 8,
3014 9,
3015 10,
3016 11,
3017 12,
3018 13,
3019 14,
3020 15,
3021 16,
3022 17,
3023 18,
3024 19,
3025 20,
3026 21,
3027 22,
3028 23,
3029 24,
3030 25,
3031 26,
3032 27,
3033 0,
3034 1,
3035 2,
3036 3,
3037 4,
3038 5,
3039 6,
3040 7,
3041 8,
3042 9,
3043 10,
3044 11,
3045 12,
3046 13,
3047 14,
3048 15,
3049 16,
3050 17,
3051 18,
3052 19,
3053 20,
3054 21,
3055 22,
3056 23,
3057 24,
3058 25,
3059 1,
3060 3,
3061 5,
3062 7,
3063 9,
3064 11,
3065 13,
3066 15,
3067 17,
3068 19,
3069 21,
3070 23,
3071 25,
3072 27,
3073 29,
3074 1,
3075 3,
3076 5,
3077 7,
3078 9,
3079 11,
3080 13,
3081 15,
3082 17,
3083 19,
3084 21,
3085 23,
3086 25,
3087 27,
3088};
3089static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3090 RI->InitMCRegisterInfo(D: ARMRegDesc, NR: 297, RA, PC, C: ARMMCRegisterClasses, NC: 137, RURoots: ARMRegUnitRoots, NRU: 88, DL: ARMRegDiffLists, RUMS: ARMLaneMaskLists, Strings: ARMRegStrings, ClassStrings: ARMRegClassStrings, SubIndices: ARMSubRegIdxLists, NumIndices: 57,
3091RET: ARMRegEncodingTable);
3092
3093 switch (DwarfFlavour) {
3094 default:
3095 llvm_unreachable("Unknown DWARF flavour");
3096 case 0:
3097 RI->mapDwarfRegsToLLVMRegs(Map: ARMDwarfFlavour0Dwarf2L, Size: ARMDwarfFlavour0Dwarf2LSize, isEH: false);
3098 break;
3099 }
3100 switch (EHFlavour) {
3101 default:
3102 llvm_unreachable("Unknown DWARF flavour");
3103 case 0:
3104 RI->mapDwarfRegsToLLVMRegs(Map: ARMEHFlavour0Dwarf2L, Size: ARMEHFlavour0Dwarf2LSize, isEH: true);
3105 break;
3106 }
3107 switch (DwarfFlavour) {
3108 default:
3109 llvm_unreachable("Unknown DWARF flavour");
3110 case 0:
3111 RI->mapLLVMRegsToDwarfRegs(Map: ARMDwarfFlavour0L2Dwarf, Size: ARMDwarfFlavour0L2DwarfSize, isEH: false);
3112 break;
3113 }
3114 switch (EHFlavour) {
3115 default:
3116 llvm_unreachable("Unknown DWARF flavour");
3117 case 0:
3118 RI->mapLLVMRegsToDwarfRegs(Map: ARMEHFlavour0L2Dwarf, Size: ARMEHFlavour0L2DwarfSize, isEH: true);
3119 break;
3120 }
3121}
3122
3123} // end namespace llvm
3124
3125