1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t ARMRegDiffLists[] = {
12 /* 0 */ -248, 1, 1, 1, 230, 1, -136, 65, -64, 65, -140, 0,
13 /* 12 */ -249, 1, 1, 1, 231, 1, -137, 65, -64, 65, -139, 0,
14 /* 24 */ -250, 1, 1, 1, 232, 1, -138, 65, -64, 65, -138, 0,
15 /* 36 */ -251, 1, 1, 1, 233, 1, -139, 65, -64, 65, -137, 0,
16 /* 48 */ -252, 1, 1, 1, 234, 1, -140, 65, -64, 65, -136, 0,
17 /* 60 */ -253, 1, 1, 1, 235, 1, -141, 65, -64, 65, -135, 0,
18 /* 72 */ -15, -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, -117, -91, -23, 1, 23, -22, 1, 95, 65, -64, 65, 69, -44, 28, -27, 28, 28, -150, 65, 30, -94, 65, 30, 40, 15, -134, 0,
19 /* 111 */ -15, -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, -117, -91, -24, 1, 24, -23, 1, 95, 65, -64, 65, 70, -45, 28, -27, 28, 29, -151, 65, 30, -94, 65, 30, 41, 15, -134, 0,
20 /* 150 */ -15, -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, -117, -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, -46, 28, -27, 28, 30, -152, 65, 30, -94, 65, 30, 42, 15, -134, 0,
21 /* 189 */ -15, -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, -117, -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, -47, 28, -27, 28, 31, -153, 65, 30, -94, 65, 30, 43, 15, -134, 0,
22 /* 228 */ -15, -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, -117, -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, -48, 28, -27, 28, 32, -154, 65, 30, -94, 65, 30, 44, 15, -134, 0,
23 /* 267 */ -15, -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, -117, -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, -49, 28, -27, 28, 33, -155, 65, 30, -94, 65, 30, 45, 15, -134, 0,
24 /* 310 */ -15, -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, -117, -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, -50, 28, -27, 28, 34, -156, 65, 30, -94, 65, 30, 46, 15, -134, 0,
25 /* 357 */ -15, -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, -117, -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, -51, 28, -27, 28, 35, -157, 65, 30, -94, 65, 30, 47, 15, -134, 0,
26 /* 408 */ -15, -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, -117, -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, -52, 28, -27, 28, 36, -158, 65, 30, -94, 65, 30, 48, 15, -134, 0,
27 /* 463 */ -15, -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, -117, -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, -53, 28, -27, 28, 37, -159, 65, 30, -94, 65, 30, 49, 15, -134, 0,
28 /* 518 */ -15, -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, -117, -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, -54, 28, -27, 28, 38, -160, 65, 30, -94, 65, 30, 50, 15, -134, 0,
29 /* 573 */ -15, -91, -36, 68, 1, -68, 69, 1, -34, -35, 70, 1, -70, 71, 1, 23, 65, -64, 65, 82, -117, -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, -55, 28, -27, 28, 39, -161, 65, 30, -94, 65, 30, 51, 15, -134, 0,
30 /* 628 */ -15, -91, -37, 66, 1, -66, 67, 1, -31, -36, 68, 1, -68, 69, 1, 25, 65, -64, 65, 83, -117, -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, -56, 28, -27, 28, 40, -162, 65, 30, -94, 65, 30, 52, 15, -134, 0,
31 /* 683 */ -254, 81, 1, -81, 1, 1, 236, 1, -142, 65, -64, 65, -134, 0,
32 /* 697 */ -255, 79, 1, -79, 80, 1, -80, 81, 1, -81, 237, 1, -143, 65, -64, 65, -133, 0,
33 /* 715 */ -256, 77, 1, -77, 78, 1, -78, 79, 1, -79, 80, 1, 157, 1, -144, 65, -64, 65, -132, 0,
34 /* 735 */ -257, 75, 1, -75, 76, 1, -76, 77, 1, -77, 78, 1, 160, 1, -145, 65, -64, 65, -131, 0,
35 /* 755 */ -258, 73, 1, -73, 74, 1, -74, 75, 1, -75, 76, 1, 163, 1, -146, 65, -64, 65, -130, 0,
36 /* 775 */ -259, 71, 1, -71, 72, 1, -72, 73, 1, -73, 74, 1, 166, 1, -147, 65, -64, 65, -129, 0,
37 /* 795 */ -260, 69, 1, -69, 70, 1, -70, 71, 1, -71, 72, 1, 169, 1, -148, 65, -64, 65, -128, 0,
38 /* 815 */ -261, 67, 1, -67, 68, 1, -68, 69, 1, -69, 70, 1, 172, 1, -149, 65, -64, 65, -127, 0,
39 /* 835 */ 23, 73, 2, 63, -48, 120, -71, 1, -49, 75, 26, -89, 65, 26, 30, -120, 66, 26, 29, -120, 0,
40 /* 856 */ 22, 74, 2, 63, -49, 120, -70, 1, -50, 76, 26, -90, 66, 26, 29, -120, 0,
41 /* 873 */ 65, -49, 77, 26, -90, 66, 26, 29, -120, 0,
42 /* 883 */ 23, 73, 2, 134, -71, 1, -49, 50, -49, 75, 26, 31, -120, 65, 26, 30, -120, 0,
43 /* 901 */ 22, 74, 135, -70, 1, -50, 77, 26, 30, -120, 0,
44 /* 912 */ 65, -49, 77, 26, 30, -120, 0,
45 /* 919 */ -71, 1, -49, 133, -120, 121, -120, 0,
46 /* 927 */ 139, -49, 50, -49, 12, 121, -120, 0,
47 /* 935 */ -49, 13, 121, -120, 0,
48 /* 940 */ -70, 1, -50, 133, -120, 0,
49 /* 946 */ -49, 133, -120, 0,
50 /* 950 */ -68, 36, 62, 148, -84, 1, -36, 66, 28, 40, -119, 0,
51 /* 962 */ -67, 36, 62, 148, -84, 1, -36, 66, 28, 40, -119, 0,
52 /* 974 */ 65, -36, 66, 28, 40, -119, 0,
53 /* 981 */ -84, 1, -36, 134, -119, 0,
54 /* 987 */ -221, 75, 1, -74, 77, 1, -76, 79, 1, -78, 81, 1, 10, 95, -93, 95, -93, 0,
55 /* 1005 */ -221, 74, 1, -73, 76, 1, -75, 78, 1, -77, 80, 1, 11, 95, -93, 95, -93, 0,
56 /* 1023 */ -221, 73, 1, -72, 75, 1, -74, 77, 1, -76, 79, 1, 12, 95, -93, 95, -93, 0,
57 /* 1041 */ -221, 72, 1, -71, 74, 1, -73, 76, 1, -75, 78, 1, 13, 95, -93, 95, -93, 0,
58 /* 1059 */ -221, 71, 1, -70, 73, 1, -72, 75, 1, -74, 77, 1, 14, 95, -93, 95, -93, 0,
59 /* 1077 */ -221, 70, 1, -69, 72, 1, -71, 74, 1, -73, 76, 1, 15, 95, -93, 95, -93, 0,
60 /* 1095 */ -221, 69, 1, -68, 71, 1, -70, 73, 1, -72, 75, 1, 16, 95, -93, 95, -93, 0,
61 /* 1113 */ -221, 68, 1, -67, 70, 1, -69, 72, 1, -71, 74, 1, 17, 95, -93, 95, -93, 0,
62 /* 1131 */ -221, 67, 1, -66, 69, 1, -68, 71, 1, -70, 73, 1, 18, 95, -93, 95, -93, 0,
63 /* 1149 */ -221, 66, 1, -65, 68, 1, -67, 70, 1, -69, 72, 1, 19, 95, -93, 95, -93, 0,
64 /* 1167 */ -221, 77, 1, -76, 79, 1, -78, 81, 1, -80, 92, 95, -93, 95, -93, 0,
65 /* 1183 */ -221, 76, 1, -75, 78, 1, -77, 80, 1, -79, 92, 95, -93, 95, -93, 0,
66 /* 1199 */ -221, 79, 1, -78, 81, 1, -80, 2, 92, 95, -93, 95, -93, 0,
67 /* 1213 */ -221, 78, 1, -77, 80, 1, -79, 2, 92, 95, -93, 95, -93, 0,
68 /* 1227 */ -221, 81, 1, -80, 2, 2, 92, 95, -93, 95, -93, 0,
69 /* 1239 */ -221, 80, 1, -79, 2, 2, 92, 95, -93, 95, -93, 0,
70 /* 1251 */ -221, 2, 2, 2, 92, 95, -93, 95, -93, 0,
71 /* 1261 */ 21, 75, 65, -50, 78, 26, -91, 0,
72 /* 1269 */ 24, 72, 2, 63, -47, 120, -72, 1, -48, 74, 26, -88, 64, 26, 31, -120, 65, 26, 30, -120, 92, -91, 0,
73 /* 1292 */ 65, -48, 76, 26, -89, 65, 26, 30, -120, 92, -91, 0,
74 /* 1304 */ 26, -90, 92, -91, 0,
75 /* 1309 */ 24, 72, 2, 135, -72, 1, -48, 49, -48, 74, 26, 32, -120, 64, 26, 31, -120, 65, 26, -90, 0,
76 /* 1330 */ 65, -48, 76, 26, 31, -120, 65, 26, -90, 0,
77 /* 1340 */ 25, 71, 2, 63, -46, 120, -73, 1, -47, 73, 26, -87, 63, 26, 32, -120, 64, 26, 31, -120, 91, -90, 0,
78 /* 1363 */ 65, -47, 75, 26, -88, 64, 26, 31, -120, 91, -90, 0,
79 /* 1375 */ 25, 71, 2, 136, -73, 1, -47, 48, -47, 73, 26, 33, -120, 63, 26, 32, -120, 64, 26, -89, 91, -90, 0,
80 /* 1398 */ 65, -47, 75, 26, 32, -120, 64, 26, -89, 91, -90, 0,
81 /* 1410 */ 26, 70, 2, 63, -45, 120, -74, 1, -46, 72, 26, -86, 62, 26, 33, -120, 63, 26, 32, -120, 90, -89, 0,
82 /* 1433 */ 65, -46, 74, 26, -87, 63, 26, 32, -120, 90, -89, 0,
83 /* 1445 */ 26, 70, 2, 137, -74, 1, -46, 47, -46, 72, 26, 34, -120, 62, 26, 33, -120, 63, 26, -88, 90, -89, 0,
84 /* 1468 */ 65, -46, 74, 26, 33, -120, 63, 26, -88, 90, -89, 0,
85 /* 1480 */ 27, 69, 2, 63, -44, 120, -75, 1, -45, 71, 26, -85, 61, 26, 34, -120, 62, 26, 33, -120, 89, -88, 0,
86 /* 1503 */ 65, -45, 73, 26, -86, 62, 26, 33, -120, 89, -88, 0,
87 /* 1515 */ 27, 69, 2, 138, -75, 1, -45, 46, -45, 71, 26, 35, -120, 61, 26, 34, -120, 62, 26, -87, 89, -88, 0,
88 /* 1538 */ 65, -45, 73, 26, 34, -120, 62, 26, -87, 89, -88, 0,
89 /* 1550 */ 28, 68, 2, 63, -43, 120, -76, 1, -44, 70, 26, -84, 60, 26, 35, -120, 61, 26, 34, -120, 88, -87, 0,
90 /* 1573 */ 65, -44, 72, 26, -85, 61, 26, 34, -120, 88, -87, 0,
91 /* 1585 */ 28, 68, 2, 139, -76, 1, -44, 45, -44, 70, 26, 36, -120, 60, 26, 35, -120, 61, 26, -86, 88, -87, 0,
92 /* 1608 */ 65, -44, 72, 26, 35, -120, 61, 26, -86, 88, -87, 0,
93 /* 1620 */ -82, 29, 67, 2, 63, -42, 120, -77, 1, -43, 69, 26, -83, 59, 26, 36, -120, 60, 26, 35, -120, 87, -86, 0,
94 /* 1644 */ -81, 29, 67, 2, 63, -42, 120, -77, 1, -43, 69, 26, -83, 59, 26, 36, -120, 60, 26, 35, -120, 87, -86, 0,
95 /* 1668 */ 65, -43, 71, 26, -84, 60, 26, 35, -120, 87, -86, 0,
96 /* 1680 */ 29, 67, 2, 140, -77, 1, -43, 44, -43, 69, 26, 37, -120, 59, 26, 36, -120, 60, 26, -85, 87, -86, 0,
97 /* 1703 */ 65, -43, 71, 26, 36, -120, 60, 26, -85, 87, -86, 0,
98 /* 1715 */ -80, 30, 66, 2, 63, -41, 120, -78, 1, -42, 68, 26, -82, 58, 26, 37, -120, 59, 26, 36, -120, 86, -85, 0,
99 /* 1739 */ -79, 30, 66, 2, 63, -41, 120, -78, 1, -42, 68, 26, -82, 58, 26, 37, -120, 59, 26, 36, -120, 86, -85, 0,
100 /* 1763 */ 65, -42, 70, 26, -83, 59, 26, 36, -120, 86, -85, 0,
101 /* 1775 */ -81, 30, 66, 2, 141, -78, 1, -42, 43, -42, 68, 26, 38, -120, 58, 26, 37, -120, 59, 26, -84, 86, -85, 0,
102 /* 1799 */ -80, 30, 66, 2, 141, -78, 1, -42, 43, -42, 68, 26, 38, -120, 58, 26, 37, -120, 59, 26, -84, 86, -85, 0,
103 /* 1823 */ 65, -42, 70, 26, 37, -120, 59, 26, -84, 86, -85, 0,
104 /* 1835 */ -78, 31, 65, 2, 63, -40, 120, -79, 1, -41, 67, 26, -81, 57, 26, 38, -120, 58, 26, 37, -120, 85, -84, 0,
105 /* 1859 */ -77, 31, 65, 2, 63, -40, 120, -79, 1, -41, 67, 26, -81, 57, 26, 38, -120, 58, 26, 37, -120, 85, -84, 0,
106 /* 1883 */ 65, -41, 69, 26, -82, 58, 26, 37, -120, 85, -84, 0,
107 /* 1895 */ -79, 31, 65, 2, 142, -79, 1, -41, 42, -41, 67, 26, 39, -120, 57, 26, 38, -120, 58, 26, -83, 85, -84, 0,
108 /* 1919 */ -78, 31, 65, 2, 142, -79, 1, -41, 42, -41, 67, 26, 39, -120, 57, 26, 38, -120, 58, 26, -83, 85, -84, 0,
109 /* 1943 */ 65, -41, 69, 26, 38, -120, 58, 26, -83, 85, -84, 0,
110 /* 1955 */ -76, 32, 64, 2, 63, -39, 120, -80, 1, -40, 66, 26, -80, 56, 26, 39, -120, 57, 26, 38, -120, 84, -83, 0,
111 /* 1979 */ -75, 32, 64, 2, 63, -39, 120, -80, 1, -40, 66, 26, -80, 56, 26, 39, -120, 57, 26, 38, -120, 84, -83, 0,
112 /* 2003 */ 65, -40, 68, 26, -81, 57, 26, 38, -120, 84, -83, 0,
113 /* 2015 */ -77, 32, 64, 2, 143, -80, 1, -40, 41, -40, 66, 26, 40, -120, 56, 26, 39, -120, 57, 26, -82, 84, -83, 0,
114 /* 2039 */ -76, 32, 64, 2, 143, -80, 1, -40, 41, -40, 66, 26, 40, -120, 56, 26, 39, -120, 57, 26, -82, 84, -83, 0,
115 /* 2063 */ 65, -40, 68, 26, 39, -120, 57, 26, -82, 84, -83, 0,
116 /* 2075 */ -74, 33, 63, 2, 63, -38, 120, -81, 1, -39, 65, 26, -79, 55, 26, 40, -120, 56, 26, 39, -120, 83, -82, 0,
117 /* 2099 */ -73, 33, 63, 2, 63, -38, 120, -81, 1, -39, 65, 26, -79, 55, 26, 40, -120, 56, 26, 39, -120, 83, -82, 0,
118 /* 2123 */ 65, -39, 67, 26, -80, 56, 26, 39, -120, 83, -82, 0,
119 /* 2135 */ -75, 33, 63, 2, 144, -81, 1, -39, 40, -39, 65, 26, 41, -120, 55, 26, 40, -120, 56, 26, -81, 83, -82, 0,
120 /* 2159 */ -74, 33, 63, 2, 144, -81, 1, -39, 40, -39, 65, 26, 41, -120, 55, 26, 40, -120, 56, 26, -81, 83, -82, 0,
121 /* 2183 */ 65, -39, 67, 26, 40, -120, 56, 26, -81, 83, -82, 0,
122 /* 2195 */ -239, 81, 1, -81, 0,
123 /* 2200 */ -72, 34, 62, 2, 63, -37, 120, -82, 1, -38, 64, 2, 26, 41, -120, 55, 26, 40, -120, 82, -81, 0,
124 /* 2222 */ -71, 34, 62, 2, 63, -37, 120, -82, 1, -38, 64, 2, 26, 41, -120, 55, 26, 40, -120, 82, -81, 0,
125 /* 2244 */ 65, -38, 66, 26, -79, 55, 26, 40, -120, 82, -81, 0,
126 /* 2256 */ -73, 34, 62, 2, 145, -82, 1, -38, 39, -38, 64, 26, 42, -120, 54, 26, 41, -120, 55, 26, -80, 82, -81, 0,
127 /* 2280 */ -72, 34, 62, 2, 145, -82, 1, -38, 39, -38, 64, 26, 42, -120, 54, 26, 41, -120, 55, 26, -80, 82, -81, 0,
128 /* 2304 */ 65, -38, 66, 26, 41, -120, 55, 26, -80, 82, -81, 0,
129 /* 2316 */ -98, 81, 1, -80, 0,
130 /* 2321 */ -70, 35, 61, 2, 63, -36, 120, -83, 1, -37, 65, 2, 26, 40, 1, -120, 81, -80, 0,
131 /* 2340 */ -69, 35, 61, 2, 63, -36, 120, -83, 1, -37, 65, 2, 26, 40, 1, -120, 81, -80, 0,
132 /* 2359 */ 65, -37, 65, 2, 26, 41, -120, 81, -80, 0,
133 /* 2369 */ -71, 35, 61, 2, 146, -83, 1, -37, 38, -37, 63, 2, 26, 41, 1, -120, 54, 26, -79, 81, -80, 0,
134 /* 2391 */ -70, 35, 61, 2, 146, -83, 1, -37, 38, -37, 63, 2, 26, 41, 1, -120, 54, 26, -79, 81, -80, 0,
135 /* 2413 */ 65, -37, 65, 26, 42, -120, 54, 26, -79, 81, -80, 0,
136 /* 2425 */ -98, 80, 1, -79, 0,
137 /* 2430 */ 28, -79, 0,
138 /* 2433 */ -69, 36, 60, 2, 147, -84, 1, -36, 37, -36, 64, 2, 26, 41, -119, 80, -79, 0,
139 /* 2451 */ -68, 36, 60, 2, 147, -84, 1, -36, 37, -36, 64, 2, 26, 41, -119, 80, -79, 0,
140 /* 2469 */ 65, -36, 64, 2, 26, 41, -119, 80, -79, 0,
141 /* 2479 */ 26, -78, 80, -79, 0,
142 /* 2484 */ -67, 37, 61, 65, -35, 65, 28, -78, 0,
143 /* 2493 */ -66, 37, 61, 65, -35, 65, 28, -78, 0,
144 /* 2502 */ -163, 1, 1, 230, -134, -75, 0,
145 /* 2509 */ -163, 1, 1, 231, -135, -74, 0,
146 /* 2516 */ -163, 1, 1, 232, -136, -73, 0,
147 /* 2523 */ -163, 1, 1, 233, -137, -72, 0,
148 /* 2530 */ -163, 1, 1, 234, -138, -71, 0,
149 /* 2537 */ -163, 1, 1, 235, -139, -70, 0,
150 /* 2544 */ -163, 1, 1, 236, -140, -69, 0,
151 /* 2551 */ -97, -69, 0,
152 /* 2554 */ -163, 81, 1, -81, 1, 237, -141, -68, 0,
153 /* 2563 */ -163, 79, 1, -79, 80, 1, -80, 81, 1, 156, -142, -67, 0,
154 /* 2576 */ -163, 77, 1, -77, 78, 1, -78, 79, 1, 159, -143, -66, 0,
155 /* 2589 */ -163, 75, 1, -75, 76, 1, -76, 77, 1, 162, -144, -65, 0,
156 /* 2602 */ -163, 73, 1, -73, 74, 1, -74, 75, 1, 165, -145, -64, 0,
157 /* 2615 */ -163, 71, 1, -71, 72, 1, -72, 73, 1, 168, -146, -63, 0,
158 /* 2628 */ -163, 69, 1, -69, 70, 1, -70, 71, 1, 171, -147, -62, 0,
159 /* 2641 */ -163, 67, 1, -67, 68, 1, -68, 69, 1, 174, -148, -61, 0,
160 /* 2654 */ -238, 1, 0,
161 /* 2657 */ -237, 1, 0,
162 /* 2660 */ -236, 1, 0,
163 /* 2663 */ -235, 1, 0,
164 /* 2666 */ -234, 1, 0,
165 /* 2669 */ -233, 1, 0,
166 /* 2672 */ -232, 1, 0,
167 /* 2675 */ -83, 1, -37, 133, 1, -120, 1, 0,
168 /* 2683 */ -72, 1, -48, 133, -120, 121, -120, 1, 0,
169 /* 2692 */ -73, 1, -47, 133, -120, 121, -120, 1, 0,
170 /* 2701 */ -74, 1, -46, 133, -120, 121, -120, 1, 0,
171 /* 2710 */ -75, 1, -45, 133, -120, 121, -120, 1, 0,
172 /* 2719 */ -76, 1, -44, 133, -120, 121, -120, 1, 0,
173 /* 2728 */ -77, 1, -43, 133, -120, 121, -120, 1, 0,
174 /* 2737 */ -78, 1, -42, 133, -120, 121, -120, 1, 0,
175 /* 2746 */ -79, 1, -41, 133, -120, 121, -120, 1, 0,
176 /* 2755 */ -80, 1, -40, 133, -120, 121, -120, 1, 0,
177 /* 2764 */ -81, 1, -39, 133, -120, 121, -120, 1, 0,
178 /* 2773 */ -82, 1, -38, 133, -120, 121, -120, 1, 0,
179 /* 2782 */ 138, -48, 49, -48, 12, 121, -120, 1, 0,
180 /* 2791 */ -48, 13, 121, -120, 1, 0,
181 /* 2797 */ -47, 13, 121, -120, 1, 0,
182 /* 2803 */ -46, 13, 121, -120, 1, 0,
183 /* 2809 */ -45, 13, 121, -120, 1, 0,
184 /* 2815 */ -44, 13, 121, -120, 1, 0,
185 /* 2821 */ -43, 13, 121, -120, 1, 0,
186 /* 2827 */ -42, 13, 121, -120, 1, 0,
187 /* 2833 */ -41, 13, 121, -120, 1, 0,
188 /* 2839 */ -40, 13, 121, -120, 1, 0,
189 /* 2845 */ -39, 13, 121, -120, 1, 0,
190 /* 2851 */ -38, 13, 121, -120, 1, 0,
191 /* 2857 */ -48, 133, -120, 1, 0,
192 /* 2862 */ -37, 134, -120, 1, 0,
193 /* 2867 */ 126, -36, 37, -36, 133, -119, 1, 0,
194 /* 2875 */ -103, 1, 0,
195 /* 2878 */ -102, 1, 0,
196 /* 2881 */ -101, 1, 0,
197 /* 2884 */ -100, 1, 0,
198 /* 2887 */ -99, 1, 0,
199 /* 2890 */ -98, 1, 0,
200 /* 2893 */ -29, 1, 0,
201 /* 2896 */ -28, 1, 0,
202 /* 2899 */ -27, 1, 0,
203 /* 2902 */ -26, 1, 0,
204 /* 2905 */ -25, 1, 0,
205 /* 2908 */ -24, 1, 0,
206 /* 2911 */ -23, 1, 0,
207 /* 2914 */ -22, 1, 0,
208 /* 2917 */ 137, -47, 48, -47, 12, 121, -120, 1, 1, 0,
209 /* 2927 */ 136, -46, 47, -46, 12, 121, -120, 1, 1, 0,
210 /* 2937 */ 135, -45, 46, -45, 12, 121, -120, 1, 1, 0,
211 /* 2947 */ 134, -44, 45, -44, 12, 121, -120, 1, 1, 0,
212 /* 2957 */ 133, -43, 44, -43, 12, 121, -120, 1, 1, 0,
213 /* 2967 */ 132, -42, 43, -42, 12, 121, -120, 1, 1, 0,
214 /* 2977 */ 131, -41, 42, -41, 12, 121, -120, 1, 1, 0,
215 /* 2987 */ 130, -40, 41, -40, 12, 121, -120, 1, 1, 0,
216 /* 2997 */ 129, -39, 40, -39, 12, 121, -120, 1, 1, 0,
217 /* 3007 */ 128, -38, 39, -38, 12, 121, -120, 1, 1, 0,
218 /* 3017 */ -47, 133, -120, 1, 1, 0,
219 /* 3023 */ -46, 133, -120, 1, 1, 0,
220 /* 3029 */ -45, 133, -120, 1, 1, 0,
221 /* 3035 */ -44, 133, -120, 1, 1, 0,
222 /* 3041 */ -43, 133, -120, 1, 1, 0,
223 /* 3047 */ -42, 133, -120, 1, 1, 0,
224 /* 3053 */ -41, 133, -120, 1, 1, 0,
225 /* 3059 */ -40, 133, -120, 1, 1, 0,
226 /* 3065 */ -39, 133, -120, 1, 1, 0,
227 /* 3071 */ -38, 133, -120, 1, 1, 0,
228 /* 3077 */ 127, -37, 38, -37, 133, -120, 1, 1, 0,
229 /* 3086 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
230 /* 3102 */ 13, 1, 1, 0,
231 /* 3106 */ 1, 3, 1, 3, 1, 3, 1, 0,
232 /* 3114 */ 13, 1, 0,
233 /* 3117 */ 14, 1, 0,
234 /* 3120 */ 66, 1, 0,
235 /* 3123 */ -37, 66, 1, -66, 67, 1, 0,
236 /* 3130 */ -246, 67, 1, -67, 68, 1, 0,
237 /* 3137 */ -98, 66, 1, -65, 68, 1, 0,
238 /* 3144 */ -36, 68, 1, -68, 69, 1, 0,
239 /* 3151 */ -98, 67, 1, -66, 69, 1, 0,
240 /* 3158 */ -245, 69, 1, -69, 70, 1, 0,
241 /* 3165 */ -98, 68, 1, -67, 70, 1, 0,
242 /* 3172 */ -35, 70, 1, -70, 71, 1, 0,
243 /* 3179 */ -98, 69, 1, -68, 71, 1, 0,
244 /* 3186 */ -244, 71, 1, -71, 72, 1, 0,
245 /* 3193 */ -98, 70, 1, -69, 72, 1, 0,
246 /* 3200 */ -34, 72, 1, -72, 73, 1, 0,
247 /* 3207 */ -98, 71, 1, -70, 73, 1, 0,
248 /* 3214 */ -243, 73, 1, -73, 74, 1, 0,
249 /* 3221 */ -98, 72, 1, -71, 74, 1, 0,
250 /* 3228 */ -33, 74, 1, -74, 75, 1, 0,
251 /* 3235 */ -98, 73, 1, -72, 75, 1, 0,
252 /* 3242 */ -242, 75, 1, -75, 76, 1, 0,
253 /* 3249 */ -98, 74, 1, -73, 76, 1, 0,
254 /* 3256 */ -32, 76, 1, -76, 77, 1, 0,
255 /* 3263 */ -98, 75, 1, -74, 77, 1, 0,
256 /* 3270 */ -241, 77, 1, -77, 78, 1, 0,
257 /* 3277 */ -98, 76, 1, -75, 78, 1, 0,
258 /* 3284 */ -31, 78, 1, -78, 79, 1, 0,
259 /* 3291 */ -98, 77, 1, -76, 79, 1, 0,
260 /* 3298 */ -240, 79, 1, -79, 80, 1, 0,
261 /* 3305 */ -98, 78, 1, -77, 80, 1, 0,
262 /* 3312 */ -30, 80, 1, -80, 81, 1, 0,
263 /* 3319 */ -98, 79, 1, -78, 81, 1, 0,
264 /* 3326 */ -98, 2, 0,
265 /* 3329 */ 1, 3, 1, 3, 1, 2, 0,
266 /* 3336 */ 1, 3, 1, 2, 2, 0,
267 /* 3342 */ 1, 2, 2, 2, 0,
268 /* 3347 */ 1, 3, 2, 2, 0,
269 /* 3352 */ 1, 3, 1, 3, 2, 0,
270 /* 3358 */ -193, 77, 1, -76, 79, 1, -78, 81, 1, 12, 2, 0,
271 /* 3370 */ -193, 76, 1, -75, 78, 1, -77, 80, 1, 13, 2, 0,
272 /* 3382 */ -193, 75, 1, -74, 77, 1, -76, 79, 1, 14, 2, 0,
273 /* 3394 */ -193, 74, 1, -73, 76, 1, -75, 78, 1, 15, 2, 0,
274 /* 3406 */ -193, 73, 1, -72, 75, 1, -74, 77, 1, 16, 2, 0,
275 /* 3418 */ -193, 72, 1, -71, 74, 1, -73, 76, 1, 17, 2, 0,
276 /* 3430 */ -193, 71, 1, -70, 73, 1, -72, 75, 1, 18, 2, 0,
277 /* 3442 */ -193, 70, 1, -69, 72, 1, -71, 74, 1, 19, 2, 0,
278 /* 3454 */ -193, 69, 1, -68, 71, 1, -70, 73, 1, 20, 2, 0,
279 /* 3466 */ -193, 68, 1, -67, 70, 1, -69, 72, 1, 21, 2, 0,
280 /* 3478 */ -193, 67, 1, -66, 69, 1, -68, 71, 1, 22, 2, 0,
281 /* 3490 */ -193, 66, 1, -65, 68, 1, -67, 70, 1, 23, 2, 0,
282 /* 3502 */ -193, 79, 1, -78, 81, 1, -80, 94, 2, 0,
283 /* 3512 */ -193, 78, 1, -77, 80, 1, -79, 94, 2, 0,
284 /* 3522 */ -193, 81, 1, -80, 2, 94, 2, 0,
285 /* 3530 */ -193, 80, 1, -79, 2, 94, 2, 0,
286 /* 3538 */ -193, 2, 2, 94, 2, 0,
287 /* 3544 */ 1, 3, 1, 3, 1, 3, 0,
288 /* 3551 */ 140, -50, 13, 0,
289 /* 3555 */ 126, -35, 15, 0,
290 /* 3559 */ -91, -23, 1, 23, -22, 1, 95, 65, -64, 65, 69, 0,
291 /* 3571 */ -91, -24, 1, 24, -23, 1, 95, 65, -64, 65, 70, 0,
292 /* 3583 */ -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, 0,
293 /* 3595 */ -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, 0,
294 /* 3607 */ -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, 0,
295 /* 3619 */ -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, 0,
296 /* 3631 */ -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, 0,
297 /* 3643 */ -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, 0,
298 /* 3659 */ -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, 0,
299 /* 3679 */ -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, 0,
300 /* 3699 */ -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, 0,
301 /* 3719 */ -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, 0,
302 /* 3739 */ -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, 0,
303 /* 3759 */ -91, -36, 68, 1, -68, 69, 1, -34, -35, 70, 1, -70, 71, 1, 23, 65, -64, 65, 82, 0,
304 /* 3779 */ -91, -37, 66, 1, -66, 67, 1, -31, -36, 68, 1, -68, 69, 1, 25, 65, -64, 65, 83, 0,
305 /* 3799 */ 97, 0,
306 /* 3801 */ 98, 0,
307 /* 3803 */ 99, 0,
308 /* 3805 */ 100, 0,
309 /* 3807 */ 101, 0,
310 /* 3809 */ 102, 0,
311 /* 3811 */ 103, 0,
312 /* 3813 */ -163, 1, 1, 21, 75, 135, 0,
313 /* 3820 */ -163, 1, 1, 22, 74, 136, 0,
314 /* 3827 */ -163, 1, 1, 23, 73, 137, 0,
315 /* 3834 */ -163, 1, 1, 24, 72, 138, 0,
316 /* 3841 */ -163, 1, 1, 25, 71, 139, 0,
317 /* 3848 */ -163, 1, 1, 26, 70, 140, 0,
318 /* 3855 */ -163, 1, 1, 27, 69, 141, 0,
319 /* 3862 */ -163, 80, 1, -80, 81, 1, -81, 28, 68, 142, 0,
320 /* 3873 */ -163, 78, 1, -78, 79, 1, -79, 80, 1, -52, 67, 143, 0,
321 /* 3886 */ -163, 76, 1, -76, 77, 1, -77, 78, 1, -49, 66, 144, 0,
322 /* 3899 */ -163, 74, 1, -74, 75, 1, -75, 76, 1, -46, 65, 145, 0,
323 /* 3912 */ -163, 72, 1, -72, 73, 1, -73, 74, 1, -43, 64, 146, 0,
324 /* 3925 */ -163, 70, 1, -70, 71, 1, -71, 72, 1, -40, 63, 147, 0,
325 /* 3938 */ -163, 68, 1, -68, 69, 1, -69, 70, 1, -37, 62, 148, 0,
326 /* 3951 */ -163, 66, 1, -66, 67, 1, -67, 68, 1, -34, 61, 149, 0,
327 /* 3964 */ 166, 0,
328};
329
330extern const LaneBitmask ARMLaneMaskLists[] = {
331 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
332 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002),
333 /* 4 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
334 /* 6 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020),
335 /* 10 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000030),
336 /* 13 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030),
337 /* 15 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080),
338 /* 19 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080),
339 /* 25 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x00000000000000C0),
340 /* 28 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x00000000000000C0),
341 /* 30 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x00000000000000C0),
342 /* 35 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0),
343 /* 39 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0),
344 /* 42 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200),
345 /* 50 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000300),
346 /* 57 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300),
347 /* 63 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300),
348 /* 68 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300),
349 /* 72 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800),
350 /* 78 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000C00),
351 /* 83 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00),
352 /* 87 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00),
353 /* 90 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000),
354 /* 98 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x000000000000C000),
355 /* 105 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000C00), LaneBitmask(0x000000000000C000),
356 /* 111 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00), LaneBitmask(0x000000000000C000),
357 /* 116 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00), LaneBitmask(0x000000000000C000),
358 /* 120 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000020000),
359 /* 136 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
360 /* 150 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000C00), LaneBitmask(0x0000000000003000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
361 /* 162 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300), LaneBitmask(0x0000000000000C00), LaneBitmask(0x0000000000003000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
362 /* 172 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300), LaneBitmask(0x0000000000000C00), LaneBitmask(0x0000000000003000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
363 /* 180 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF),
364};
365
366extern const uint16_t ARMSubRegIdxLists[] = {
367 /* 0 */ 1, 2,
368 /* 2 */ 1, 17, 18, 2,
369 /* 6 */ 1, 3,
370 /* 8 */ 1, 17, 18, 3,
371 /* 12 */ 9, 10,
372 /* 14 */ 17, 18,
373 /* 16 */ 1, 17, 18, 2, 19, 20,
374 /* 22 */ 1, 17, 18, 3, 21, 22,
375 /* 28 */ 1, 2, 3, 13, 33, 37,
376 /* 34 */ 1, 17, 18, 2, 3, 13, 33, 37,
377 /* 42 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37,
378 /* 52 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37,
379 /* 64 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37,
380 /* 75 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37,
381 /* 90 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37,
382 /* 101 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37,
383 /* 114 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37,
384 /* 131 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37,
385 /* 150 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37,
386 /* 169 */ 1, 3, 5, 33, 43,
387 /* 174 */ 1, 17, 18, 3, 5, 33, 43,
388 /* 181 */ 1, 17, 18, 3, 21, 22, 5, 33, 43,
389 /* 190 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43,
390 /* 201 */ 1, 3, 5, 7, 33, 38, 43, 45, 51,
391 /* 210 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51,
392 /* 221 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51,
393 /* 234 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51,
394 /* 249 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51,
395 /* 266 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
396 /* 304 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
397 /* 346 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
398 /* 392 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
399 /* 442 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
400};
401
402
403#ifdef __GNUC__
404#pragma GCC diagnostic push
405#pragma GCC diagnostic ignored "-Woverlength-strings"
406#endif
407extern const char ARMRegStrings[] = {
408 /* 0 */ "D4_D6_D8_D10\000"
409 /* 13 */ "D7_D8_D9_D10\000"
410 /* 26 */ "Q7_Q8_Q9_Q10\000"
411 /* 39 */ "R10\000"
412 /* 43 */ "S10\000"
413 /* 47 */ "D14_D16_D18_D20\000"
414 /* 63 */ "D17_D18_D19_D20\000"
415 /* 79 */ "S20\000"
416 /* 83 */ "D24_D26_D28_D30\000"
417 /* 99 */ "D27_D28_D29_D30\000"
418 /* 115 */ "S30\000"
419 /* 119 */ "D0\000"
420 /* 122 */ "P0\000"
421 /* 125 */ "Q0\000"
422 /* 128 */ "MVFR0\000"
423 /* 134 */ "S0\000"
424 /* 137 */ "D9_D10_D11\000"
425 /* 148 */ "D5_D7_D9_D11\000"
426 /* 161 */ "Q8_Q9_Q10_Q11\000"
427 /* 175 */ "R10_R11\000"
428 /* 183 */ "S11\000"
429 /* 187 */ "D19_D20_D21\000"
430 /* 199 */ "D15_D17_D19_D21\000"
431 /* 215 */ "S21\000"
432 /* 219 */ "D29_D30_D31\000"
433 /* 231 */ "D25_D27_D29_D31\000"
434 /* 247 */ "S31\000"
435 /* 251 */ "D1\000"
436 /* 254 */ "Q0_Q1\000"
437 /* 260 */ "MVFR1\000"
438 /* 266 */ "R0_R1\000"
439 /* 272 */ "S1\000"
440 /* 275 */ "D6_D8_D10_D12\000"
441 /* 289 */ "D9_D10_D11_D12\000"
442 /* 304 */ "Q9_Q10_Q11_Q12\000"
443 /* 319 */ "R12\000"
444 /* 323 */ "S12\000"
445 /* 327 */ "D16_D18_D20_D22\000"
446 /* 343 */ "D19_D20_D21_D22\000"
447 /* 359 */ "S22\000"
448 /* 363 */ "D0_D2\000"
449 /* 369 */ "D0_D1_D2\000"
450 /* 378 */ "Q1_Q2\000"
451 /* 384 */ "MVFR2\000"
452 /* 390 */ "S2\000"
453 /* 393 */ "FPINST2\000"
454 /* 401 */ "D7_D9_D11_D13\000"
455 /* 415 */ "D11_D12_D13\000"
456 /* 427 */ "Q10_Q11_Q12_Q13\000"
457 /* 443 */ "S13\000"
458 /* 447 */ "D17_D19_D21_D23\000"
459 /* 463 */ "D21_D22_D23\000"
460 /* 475 */ "S23\000"
461 /* 479 */ "D1_D3\000"
462 /* 485 */ "D1_D2_D3\000"
463 /* 494 */ "Q0_Q1_Q2_Q3\000"
464 /* 506 */ "R2_R3\000"
465 /* 512 */ "S3\000"
466 /* 515 */ "D8_D10_D12_D14\000"
467 /* 530 */ "D11_D12_D13_D14\000"
468 /* 546 */ "Q11_Q12_Q13_Q14\000"
469 /* 562 */ "S14\000"
470 /* 566 */ "D18_D20_D22_D24\000"
471 /* 582 */ "D21_D22_D23_D24\000"
472 /* 598 */ "S24\000"
473 /* 602 */ "D0_D2_D4\000"
474 /* 611 */ "D1_D2_D3_D4\000"
475 /* 623 */ "Q1_Q2_Q3_Q4\000"
476 /* 635 */ "R4\000"
477 /* 638 */ "S4\000"
478 /* 641 */ "D9_D11_D13_D15\000"
479 /* 656 */ "D13_D14_D15\000"
480 /* 668 */ "Q12_Q13_Q14_Q15\000"
481 /* 684 */ "S15\000"
482 /* 688 */ "D19_D21_D23_D25\000"
483 /* 704 */ "D23_D24_D25\000"
484 /* 716 */ "S25\000"
485 /* 720 */ "D1_D3_D5\000"
486 /* 729 */ "D3_D4_D5\000"
487 /* 738 */ "Q2_Q3_Q4_Q5\000"
488 /* 750 */ "R4_R5\000"
489 /* 756 */ "S5\000"
490 /* 759 */ "D10_D12_D14_D16\000"
491 /* 775 */ "D13_D14_D15_D16\000"
492 /* 791 */ "S16\000"
493 /* 795 */ "D20_D22_D24_D26\000"
494 /* 811 */ "D23_D24_D25_D26\000"
495 /* 827 */ "S26\000"
496 /* 831 */ "D0_D2_D4_D6\000"
497 /* 843 */ "D3_D4_D5_D6\000"
498 /* 855 */ "Q3_Q4_Q5_Q6\000"
499 /* 867 */ "R6\000"
500 /* 870 */ "S6\000"
501 /* 873 */ "D11_D13_D15_D17\000"
502 /* 889 */ "D15_D16_D17\000"
503 /* 901 */ "S17\000"
504 /* 905 */ "D21_D23_D25_D27\000"
505 /* 921 */ "D25_D26_D27\000"
506 /* 933 */ "S27\000"
507 /* 937 */ "D1_D3_D5_D7\000"
508 /* 949 */ "D5_D6_D7\000"
509 /* 958 */ "Q4_Q5_Q6_Q7\000"
510 /* 970 */ "R6_R7\000"
511 /* 976 */ "S7\000"
512 /* 979 */ "D12_D14_D16_D18\000"
513 /* 995 */ "D15_D16_D17_D18\000"
514 /* 1011 */ "S18\000"
515 /* 1015 */ "D22_D24_D26_D28\000"
516 /* 1031 */ "D25_D26_D27_D28\000"
517 /* 1047 */ "S28\000"
518 /* 1051 */ "D2_D4_D6_D8\000"
519 /* 1063 */ "D5_D6_D7_D8\000"
520 /* 1075 */ "Q5_Q6_Q7_Q8\000"
521 /* 1087 */ "R8\000"
522 /* 1090 */ "S8\000"
523 /* 1093 */ "D13_D15_D17_D19\000"
524 /* 1109 */ "D17_D18_D19\000"
525 /* 1121 */ "S19\000"
526 /* 1125 */ "D23_D25_D27_D29\000"
527 /* 1141 */ "D27_D28_D29\000"
528 /* 1153 */ "S29\000"
529 /* 1157 */ "D3_D5_D7_D9\000"
530 /* 1169 */ "D7_D8_D9\000"
531 /* 1178 */ "Q6_Q7_Q8_Q9\000"
532 /* 1190 */ "R8_R9\000"
533 /* 1196 */ "S9\000"
534 /* 1199 */ "PC\000"
535 /* 1202 */ "FPSCR_NZCVQC\000"
536 /* 1215 */ "FPEXC\000"
537 /* 1221 */ "FPSID\000"
538 /* 1227 */ "RA_AUTH_CODE\000"
539 /* 1240 */ "ITSTATE\000"
540 /* 1248 */ "FPSCR_RM\000"
541 /* 1257 */ "R12_SP\000"
542 /* 1264 */ "FPSCR\000"
543 /* 1270 */ "LR\000"
544 /* 1273 */ "VPR\000"
545 /* 1277 */ "APSR\000"
546 /* 1282 */ "CPSR\000"
547 /* 1287 */ "SPSR\000"
548 /* 1292 */ "ZR\000"
549 /* 1295 */ "FPCXTNS\000"
550 /* 1303 */ "FPCXTS\000"
551 /* 1310 */ "FPINST\000"
552 /* 1317 */ "FPSCR_NZCV\000"
553 /* 1328 */ "APSR_NZCV\000"
554};
555#ifdef __GNUC__
556#pragma GCC diagnostic pop
557#endif
558
559extern const MCRegisterDesc ARMRegDesc[] = { // Descriptors
560 { .Name: 12, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
561 { .Name: 1277, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45056, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
562 { .Name: 1328, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45057, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
563 { .Name: 1282, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45058, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
564 { .Name: 1295, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45059, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
565 { .Name: 1303, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45060, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
566 { .Name: 1215, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45061, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
567 { .Name: 1310, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45062, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
568 { .Name: 1264, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 11976711, .RegUnitLaneMasks: 180, .IsConstant: 0, .IsArtificial: 0 },
569 { .Name: 1317, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 13627400, .RegUnitLaneMasks: 181, .IsConstant: 0, .IsArtificial: 0 },
570 { .Name: 1202, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45067, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
571 { .Name: 1248, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 14536713, .RegUnitLaneMasks: 181, .IsConstant: 0, .IsArtificial: 0 },
572 { .Name: 1221, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45069, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
573 { .Name: 1240, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45070, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
574 { .Name: 1270, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45071, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
575 { .Name: 1199, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45072, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
576 { .Name: 1227, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45073, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
577 { .Name: 1261, .SubRegs: 11, .SuperRegs: 3964, .SubRegIndices: 2, .RegUnits: 45074, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
578 { .Name: 1287, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45075, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
579 { .Name: 1273, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45076, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
580 { .Name: 1292, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45077, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
581 { .Name: 119, .SubRegs: 3120, .SuperRegs: 2485, .SubRegIndices: 14, .RegUnits: 10874902, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
582 { .Name: 251, .SubRegs: 3127, .SuperRegs: 951, .SubRegIndices: 14, .RegUnits: 10874904, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
583 { .Name: 366, .SubRegs: 3134, .SuperRegs: 2434, .SubRegIndices: 14, .RegUnits: 10874906, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
584 { .Name: 482, .SubRegs: 3148, .SuperRegs: 2322, .SubRegIndices: 14, .RegUnits: 10874908, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
585 { .Name: 608, .SubRegs: 3162, .SuperRegs: 2370, .SubRegIndices: 14, .RegUnits: 10874910, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
586 { .Name: 726, .SubRegs: 3176, .SuperRegs: 2201, .SubRegIndices: 14, .RegUnits: 10874912, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
587 { .Name: 840, .SubRegs: 3190, .SuperRegs: 2257, .SubRegIndices: 14, .RegUnits: 10874914, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
588 { .Name: 946, .SubRegs: 3204, .SuperRegs: 2076, .SubRegIndices: 14, .RegUnits: 10874916, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
589 { .Name: 1060, .SubRegs: 3218, .SuperRegs: 2136, .SubRegIndices: 14, .RegUnits: 10874918, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
590 { .Name: 1166, .SubRegs: 3232, .SuperRegs: 1956, .SubRegIndices: 14, .RegUnits: 10874920, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
591 { .Name: 9, .SubRegs: 3246, .SuperRegs: 2016, .SubRegIndices: 14, .RegUnits: 10874922, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
592 { .Name: 144, .SubRegs: 3260, .SuperRegs: 1836, .SubRegIndices: 14, .RegUnits: 10874924, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
593 { .Name: 285, .SubRegs: 3274, .SuperRegs: 1896, .SubRegIndices: 14, .RegUnits: 10874926, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
594 { .Name: 411, .SubRegs: 3288, .SuperRegs: 1716, .SubRegIndices: 14, .RegUnits: 10874928, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
595 { .Name: 526, .SubRegs: 3302, .SuperRegs: 1776, .SubRegIndices: 14, .RegUnits: 10874930, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
596 { .Name: 652, .SubRegs: 3316, .SuperRegs: 1621, .SubRegIndices: 14, .RegUnits: 10874932, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
597 { .Name: 771, .SubRegs: 11, .SuperRegs: 1680, .SubRegIndices: 2, .RegUnits: 45110, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
598 { .Name: 885, .SubRegs: 11, .SuperRegs: 1550, .SubRegIndices: 2, .RegUnits: 45111, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
599 { .Name: 991, .SubRegs: 11, .SuperRegs: 1585, .SubRegIndices: 2, .RegUnits: 45112, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
600 { .Name: 1105, .SubRegs: 11, .SuperRegs: 1480, .SubRegIndices: 2, .RegUnits: 45113, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
601 { .Name: 59, .SubRegs: 11, .SuperRegs: 1515, .SubRegIndices: 2, .RegUnits: 45114, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
602 { .Name: 195, .SubRegs: 11, .SuperRegs: 1410, .SubRegIndices: 2, .RegUnits: 45115, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
603 { .Name: 339, .SubRegs: 11, .SuperRegs: 1445, .SubRegIndices: 2, .RegUnits: 45116, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
604 { .Name: 459, .SubRegs: 11, .SuperRegs: 1340, .SubRegIndices: 2, .RegUnits: 45117, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
605 { .Name: 578, .SubRegs: 11, .SuperRegs: 1375, .SubRegIndices: 2, .RegUnits: 45118, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
606 { .Name: 700, .SubRegs: 11, .SuperRegs: 1269, .SubRegIndices: 2, .RegUnits: 45119, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
607 { .Name: 807, .SubRegs: 11, .SuperRegs: 1309, .SubRegIndices: 2, .RegUnits: 45120, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
608 { .Name: 917, .SubRegs: 11, .SuperRegs: 835, .SubRegIndices: 2, .RegUnits: 45121, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
609 { .Name: 1027, .SubRegs: 11, .SuperRegs: 883, .SubRegIndices: 2, .RegUnits: 45122, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
610 { .Name: 1137, .SubRegs: 11, .SuperRegs: 856, .SubRegIndices: 2, .RegUnits: 45123, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
611 { .Name: 95, .SubRegs: 11, .SuperRegs: 901, .SubRegIndices: 2, .RegUnits: 45124, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
612 { .Name: 227, .SubRegs: 11, .SuperRegs: 1261, .SubRegIndices: 2, .RegUnits: 45125, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
613 { .Name: 393, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45126, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
614 { .Name: 128, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45127, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
615 { .Name: 260, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45128, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
616 { .Name: 384, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45129, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
617 { .Name: 122, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45130, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
618 { .Name: 125, .SubRegs: 3123, .SuperRegs: 3555, .SubRegIndices: 16, .RegUnits: 12689430, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
619 { .Name: 257, .SubRegs: 3144, .SuperRegs: 2867, .SubRegIndices: 16, .RegUnits: 12689434, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
620 { .Name: 381, .SubRegs: 3172, .SuperRegs: 3077, .SubRegIndices: 16, .RegUnits: 12689438, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
621 { .Name: 503, .SubRegs: 3200, .SuperRegs: 3007, .SubRegIndices: 16, .RegUnits: 12689442, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
622 { .Name: 632, .SubRegs: 3228, .SuperRegs: 2997, .SubRegIndices: 16, .RegUnits: 12689446, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
623 { .Name: 747, .SubRegs: 3256, .SuperRegs: 2987, .SubRegIndices: 16, .RegUnits: 12689450, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
624 { .Name: 864, .SubRegs: 3284, .SuperRegs: 2977, .SubRegIndices: 16, .RegUnits: 12689454, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
625 { .Name: 967, .SubRegs: 3312, .SuperRegs: 2967, .SubRegIndices: 16, .RegUnits: 12689458, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
626 { .Name: 1084, .SubRegs: 2893, .SuperRegs: 2957, .SubRegIndices: 0, .RegUnits: 10874934, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
627 { .Name: 1187, .SubRegs: 2896, .SuperRegs: 2947, .SubRegIndices: 0, .RegUnits: 10874936, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
628 { .Name: 35, .SubRegs: 2899, .SuperRegs: 2937, .SubRegIndices: 0, .RegUnits: 10874938, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
629 { .Name: 171, .SubRegs: 2902, .SuperRegs: 2927, .SubRegIndices: 0, .RegUnits: 10874940, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
630 { .Name: 315, .SubRegs: 2905, .SuperRegs: 2917, .SubRegIndices: 0, .RegUnits: 10874942, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
631 { .Name: 439, .SubRegs: 2908, .SuperRegs: 2782, .SubRegIndices: 0, .RegUnits: 10874944, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
632 { .Name: 558, .SubRegs: 2911, .SuperRegs: 927, .SubRegIndices: 0, .RegUnits: 10874946, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
633 { .Name: 680, .SubRegs: 2914, .SuperRegs: 3551, .SubRegIndices: 0, .RegUnits: 10874948, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
634 { .Name: 131, .SubRegs: 11, .SuperRegs: 3811, .SubRegIndices: 2, .RegUnits: 45131, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
635 { .Name: 263, .SubRegs: 11, .SuperRegs: 3809, .SubRegIndices: 2, .RegUnits: 45132, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
636 { .Name: 387, .SubRegs: 11, .SuperRegs: 3809, .SubRegIndices: 2, .RegUnits: 45133, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
637 { .Name: 509, .SubRegs: 11, .SuperRegs: 3807, .SubRegIndices: 2, .RegUnits: 45134, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
638 { .Name: 635, .SubRegs: 11, .SuperRegs: 3807, .SubRegIndices: 2, .RegUnits: 45135, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
639 { .Name: 753, .SubRegs: 11, .SuperRegs: 3805, .SubRegIndices: 2, .RegUnits: 45136, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
640 { .Name: 867, .SubRegs: 11, .SuperRegs: 3805, .SubRegIndices: 2, .RegUnits: 45137, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
641 { .Name: 973, .SubRegs: 11, .SuperRegs: 3803, .SubRegIndices: 2, .RegUnits: 45138, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
642 { .Name: 1087, .SubRegs: 11, .SuperRegs: 3803, .SubRegIndices: 2, .RegUnits: 45139, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
643 { .Name: 1193, .SubRegs: 11, .SuperRegs: 3801, .SubRegIndices: 2, .RegUnits: 45140, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
644 { .Name: 39, .SubRegs: 11, .SuperRegs: 3801, .SubRegIndices: 2, .RegUnits: 45141, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
645 { .Name: 179, .SubRegs: 11, .SuperRegs: 3799, .SubRegIndices: 2, .RegUnits: 45142, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
646 { .Name: 319, .SubRegs: 11, .SuperRegs: 3799, .SubRegIndices: 2, .RegUnits: 45143, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
647 { .Name: 134, .SubRegs: 11, .SuperRegs: 2493, .SubRegIndices: 2, .RegUnits: 45078, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
648 { .Name: 272, .SubRegs: 11, .SuperRegs: 2484, .SubRegIndices: 2, .RegUnits: 45079, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
649 { .Name: 390, .SubRegs: 11, .SuperRegs: 962, .SubRegIndices: 2, .RegUnits: 45080, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
650 { .Name: 512, .SubRegs: 11, .SuperRegs: 950, .SubRegIndices: 2, .RegUnits: 45081, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
651 { .Name: 638, .SubRegs: 11, .SuperRegs: 2451, .SubRegIndices: 2, .RegUnits: 45082, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
652 { .Name: 756, .SubRegs: 11, .SuperRegs: 2433, .SubRegIndices: 2, .RegUnits: 45083, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
653 { .Name: 870, .SubRegs: 11, .SuperRegs: 2340, .SubRegIndices: 2, .RegUnits: 45084, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
654 { .Name: 976, .SubRegs: 11, .SuperRegs: 2321, .SubRegIndices: 2, .RegUnits: 45085, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
655 { .Name: 1090, .SubRegs: 11, .SuperRegs: 2391, .SubRegIndices: 2, .RegUnits: 45086, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
656 { .Name: 1196, .SubRegs: 11, .SuperRegs: 2369, .SubRegIndices: 2, .RegUnits: 45087, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
657 { .Name: 43, .SubRegs: 11, .SuperRegs: 2222, .SubRegIndices: 2, .RegUnits: 45088, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
658 { .Name: 183, .SubRegs: 11, .SuperRegs: 2200, .SubRegIndices: 2, .RegUnits: 45089, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
659 { .Name: 323, .SubRegs: 11, .SuperRegs: 2280, .SubRegIndices: 2, .RegUnits: 45090, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
660 { .Name: 443, .SubRegs: 11, .SuperRegs: 2256, .SubRegIndices: 2, .RegUnits: 45091, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
661 { .Name: 562, .SubRegs: 11, .SuperRegs: 2099, .SubRegIndices: 2, .RegUnits: 45092, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
662 { .Name: 684, .SubRegs: 11, .SuperRegs: 2075, .SubRegIndices: 2, .RegUnits: 45093, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
663 { .Name: 791, .SubRegs: 11, .SuperRegs: 2159, .SubRegIndices: 2, .RegUnits: 45094, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
664 { .Name: 901, .SubRegs: 11, .SuperRegs: 2135, .SubRegIndices: 2, .RegUnits: 45095, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
665 { .Name: 1011, .SubRegs: 11, .SuperRegs: 1979, .SubRegIndices: 2, .RegUnits: 45096, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
666 { .Name: 1121, .SubRegs: 11, .SuperRegs: 1955, .SubRegIndices: 2, .RegUnits: 45097, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
667 { .Name: 79, .SubRegs: 11, .SuperRegs: 2039, .SubRegIndices: 2, .RegUnits: 45098, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
668 { .Name: 215, .SubRegs: 11, .SuperRegs: 2015, .SubRegIndices: 2, .RegUnits: 45099, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
669 { .Name: 359, .SubRegs: 11, .SuperRegs: 1859, .SubRegIndices: 2, .RegUnits: 45100, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
670 { .Name: 475, .SubRegs: 11, .SuperRegs: 1835, .SubRegIndices: 2, .RegUnits: 45101, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
671 { .Name: 598, .SubRegs: 11, .SuperRegs: 1919, .SubRegIndices: 2, .RegUnits: 45102, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
672 { .Name: 716, .SubRegs: 11, .SuperRegs: 1895, .SubRegIndices: 2, .RegUnits: 45103, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
673 { .Name: 827, .SubRegs: 11, .SuperRegs: 1739, .SubRegIndices: 2, .RegUnits: 45104, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
674 { .Name: 933, .SubRegs: 11, .SuperRegs: 1715, .SubRegIndices: 2, .RegUnits: 45105, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
675 { .Name: 1047, .SubRegs: 11, .SuperRegs: 1799, .SubRegIndices: 2, .RegUnits: 45106, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
676 { .Name: 1153, .SubRegs: 11, .SuperRegs: 1775, .SubRegIndices: 2, .RegUnits: 45107, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
677 { .Name: 115, .SubRegs: 11, .SuperRegs: 1644, .SubRegIndices: 2, .RegUnits: 45108, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
678 { .Name: 247, .SubRegs: 11, .SuperRegs: 1620, .SubRegIndices: 2, .RegUnits: 45109, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
679 { .Name: 363, .SubRegs: 3137, .SuperRegs: 2487, .SubRegIndices: 22, .RegUnits: 12738582, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
680 { .Name: 479, .SubRegs: 3151, .SuperRegs: 974, .SubRegIndices: 22, .RegUnits: 12738584, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
681 { .Name: 605, .SubRegs: 3165, .SuperRegs: 2469, .SubRegIndices: 22, .RegUnits: 12738586, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
682 { .Name: 723, .SubRegs: 3179, .SuperRegs: 2359, .SubRegIndices: 22, .RegUnits: 12738588, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
683 { .Name: 837, .SubRegs: 3193, .SuperRegs: 2413, .SubRegIndices: 22, .RegUnits: 12738590, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
684 { .Name: 943, .SubRegs: 3207, .SuperRegs: 2244, .SubRegIndices: 22, .RegUnits: 12738592, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
685 { .Name: 1057, .SubRegs: 3221, .SuperRegs: 2304, .SubRegIndices: 22, .RegUnits: 12738594, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
686 { .Name: 1163, .SubRegs: 3235, .SuperRegs: 2123, .SubRegIndices: 22, .RegUnits: 12738596, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
687 { .Name: 6, .SubRegs: 3249, .SuperRegs: 2183, .SubRegIndices: 22, .RegUnits: 12738598, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
688 { .Name: 154, .SubRegs: 3263, .SuperRegs: 2003, .SubRegIndices: 22, .RegUnits: 12738600, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
689 { .Name: 281, .SubRegs: 3277, .SuperRegs: 2063, .SubRegIndices: 22, .RegUnits: 12738602, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
690 { .Name: 407, .SubRegs: 3291, .SuperRegs: 1883, .SubRegIndices: 22, .RegUnits: 12738604, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
691 { .Name: 522, .SubRegs: 3305, .SuperRegs: 1943, .SubRegIndices: 22, .RegUnits: 12738606, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
692 { .Name: 648, .SubRegs: 3319, .SuperRegs: 1763, .SubRegIndices: 22, .RegUnits: 12738608, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
693 { .Name: 767, .SubRegs: 2425, .SuperRegs: 1823, .SubRegIndices: 8, .RegUnits: 14532658, .RegUnitLaneMasks: 25, .IsConstant: 0, .IsArtificial: 0 },
694 { .Name: 881, .SubRegs: 2316, .SuperRegs: 1668, .SubRegIndices: 8, .RegUnits: 13652020, .RegUnitLaneMasks: 25, .IsConstant: 0, .IsArtificial: 0 },
695 { .Name: 987, .SubRegs: 3326, .SuperRegs: 1703, .SubRegIndices: 6, .RegUnits: 13627446, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
696 { .Name: 1101, .SubRegs: 3326, .SuperRegs: 1573, .SubRegIndices: 6, .RegUnits: 13627447, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
697 { .Name: 55, .SubRegs: 3326, .SuperRegs: 1608, .SubRegIndices: 6, .RegUnits: 13627448, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
698 { .Name: 207, .SubRegs: 3326, .SuperRegs: 1503, .SubRegIndices: 6, .RegUnits: 13627449, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
699 { .Name: 335, .SubRegs: 3326, .SuperRegs: 1538, .SubRegIndices: 6, .RegUnits: 13627450, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
700 { .Name: 455, .SubRegs: 3326, .SuperRegs: 1433, .SubRegIndices: 6, .RegUnits: 13627451, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
701 { .Name: 574, .SubRegs: 3326, .SuperRegs: 1468, .SubRegIndices: 6, .RegUnits: 13627452, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
702 { .Name: 696, .SubRegs: 3326, .SuperRegs: 1363, .SubRegIndices: 6, .RegUnits: 13627453, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
703 { .Name: 803, .SubRegs: 3326, .SuperRegs: 1398, .SubRegIndices: 6, .RegUnits: 13627454, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
704 { .Name: 913, .SubRegs: 3326, .SuperRegs: 1292, .SubRegIndices: 6, .RegUnits: 13627455, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
705 { .Name: 1023, .SubRegs: 3326, .SuperRegs: 1330, .SubRegIndices: 6, .RegUnits: 13627456, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
706 { .Name: 1133, .SubRegs: 3326, .SuperRegs: 873, .SubRegIndices: 6, .RegUnits: 13627457, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
707 { .Name: 91, .SubRegs: 3326, .SuperRegs: 912, .SubRegIndices: 6, .RegUnits: 13627458, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
708 { .Name: 239, .SubRegs: 3326, .SuperRegs: 1263, .SubRegIndices: 6, .RegUnits: 13627459, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
709 { .Name: 254, .SubRegs: 3779, .SuperRegs: 3557, .SubRegIndices: 150, .RegUnits: 12673046, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
710 { .Name: 378, .SubRegs: 3759, .SuperRegs: 3117, .SubRegIndices: 150, .RegUnits: 12673050, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
711 { .Name: 500, .SubRegs: 3739, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673054, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
712 { .Name: 629, .SubRegs: 3719, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673058, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
713 { .Name: 744, .SubRegs: 3699, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673062, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
714 { .Name: 861, .SubRegs: 3679, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673066, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
715 { .Name: 964, .SubRegs: 3659, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673070, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
716 { .Name: 1081, .SubRegs: 3643, .SuperRegs: 3102, .SubRegIndices: 75, .RegUnits: 12681266, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
717 { .Name: 1184, .SubRegs: 3631, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689462, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
718 { .Name: 32, .SubRegs: 3619, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689464, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
719 { .Name: 167, .SubRegs: 3607, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689466, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
720 { .Name: 311, .SubRegs: 3595, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689468, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
721 { .Name: 435, .SubRegs: 3583, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689470, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
722 { .Name: 554, .SubRegs: 3571, .SuperRegs: 3114, .SubRegIndices: 64, .RegUnits: 12689472, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
723 { .Name: 676, .SubRegs: 3559, .SuperRegs: 3553, .SubRegIndices: 64, .RegUnits: 12689474, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
724 { .Name: 494, .SubRegs: 628, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640278, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
725 { .Name: 623, .SubRegs: 573, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640282, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
726 { .Name: 738, .SubRegs: 518, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640286, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
727 { .Name: 855, .SubRegs: 463, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640290, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
728 { .Name: 958, .SubRegs: 408, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640294, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
729 { .Name: 1075, .SubRegs: 357, .SuperRegs: 11, .SubRegIndices: 392, .RegUnits: 12648490, .RegUnitLaneMasks: 136, .IsConstant: 0, .IsArtificial: 0 },
730 { .Name: 1178, .SubRegs: 310, .SuperRegs: 11, .SubRegIndices: 346, .RegUnits: 12656686, .RegUnitLaneMasks: 150, .IsConstant: 0, .IsArtificial: 0 },
731 { .Name: 26, .SubRegs: 267, .SuperRegs: 11, .SubRegIndices: 304, .RegUnits: 12664882, .RegUnitLaneMasks: 162, .IsConstant: 0, .IsArtificial: 0 },
732 { .Name: 161, .SubRegs: 228, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673078, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
733 { .Name: 304, .SubRegs: 189, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673080, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
734 { .Name: 427, .SubRegs: 150, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673082, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
735 { .Name: 546, .SubRegs: 111, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673084, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
736 { .Name: 668, .SubRegs: 72, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673086, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
737 { .Name: 266, .SubRegs: 2875, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874955, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
738 { .Name: 506, .SubRegs: 2878, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874957, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
739 { .Name: 750, .SubRegs: 2881, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874959, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
740 { .Name: 970, .SubRegs: 2884, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874961, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
741 { .Name: 1190, .SubRegs: 2887, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874963, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
742 { .Name: 175, .SubRegs: 2890, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874965, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
743 { .Name: 1257, .SubRegs: 2551, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 14618642, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
744 { .Name: 369, .SubRegs: 3951, .SuperRegs: 3556, .SubRegIndices: 52, .RegUnits: 12681238, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
745 { .Name: 485, .SubRegs: 2641, .SuperRegs: 983, .SubRegIndices: 52, .RegUnits: 12681240, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
746 { .Name: 614, .SubRegs: 3938, .SuperRegs: 2870, .SubRegIndices: 52, .RegUnits: 12681242, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
747 { .Name: 729, .SubRegs: 2628, .SuperRegs: 2862, .SubRegIndices: 52, .RegUnits: 12681244, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
748 { .Name: 846, .SubRegs: 3925, .SuperRegs: 3080, .SubRegIndices: 52, .RegUnits: 12681246, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
749 { .Name: 949, .SubRegs: 2615, .SuperRegs: 2851, .SubRegIndices: 52, .RegUnits: 12681248, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
750 { .Name: 1066, .SubRegs: 3912, .SuperRegs: 3071, .SubRegIndices: 52, .RegUnits: 12681250, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
751 { .Name: 1169, .SubRegs: 2602, .SuperRegs: 2845, .SubRegIndices: 52, .RegUnits: 12681252, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
752 { .Name: 16, .SubRegs: 3899, .SuperRegs: 3065, .SubRegIndices: 52, .RegUnits: 12681254, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
753 { .Name: 137, .SubRegs: 2589, .SuperRegs: 2839, .SubRegIndices: 52, .RegUnits: 12681256, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
754 { .Name: 292, .SubRegs: 3886, .SuperRegs: 3059, .SubRegIndices: 52, .RegUnits: 12681258, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
755 { .Name: 415, .SubRegs: 2576, .SuperRegs: 2833, .SubRegIndices: 52, .RegUnits: 12681260, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
756 { .Name: 534, .SubRegs: 3873, .SuperRegs: 3053, .SubRegIndices: 52, .RegUnits: 12681262, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
757 { .Name: 656, .SubRegs: 2563, .SuperRegs: 2827, .SubRegIndices: 52, .RegUnits: 12681264, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
758 { .Name: 779, .SubRegs: 3862, .SuperRegs: 3047, .SubRegIndices: 42, .RegUnits: 12685362, .RegUnitLaneMasks: 30, .IsConstant: 0, .IsArtificial: 0 },
759 { .Name: 889, .SubRegs: 2554, .SuperRegs: 2821, .SubRegIndices: 34, .RegUnits: 12689460, .RegUnitLaneMasks: 35, .IsConstant: 0, .IsArtificial: 0 },
760 { .Name: 999, .SubRegs: 3855, .SuperRegs: 3041, .SubRegIndices: 28, .RegUnits: 11976758, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
761 { .Name: 1109, .SubRegs: 2544, .SuperRegs: 2815, .SubRegIndices: 28, .RegUnits: 11976759, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
762 { .Name: 67, .SubRegs: 3848, .SuperRegs: 3035, .SubRegIndices: 28, .RegUnits: 11976760, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
763 { .Name: 187, .SubRegs: 2537, .SuperRegs: 2809, .SubRegIndices: 28, .RegUnits: 11976761, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
764 { .Name: 347, .SubRegs: 3841, .SuperRegs: 3029, .SubRegIndices: 28, .RegUnits: 11976762, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
765 { .Name: 463, .SubRegs: 2530, .SuperRegs: 2803, .SubRegIndices: 28, .RegUnits: 11976763, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
766 { .Name: 586, .SubRegs: 3834, .SuperRegs: 3023, .SubRegIndices: 28, .RegUnits: 11976764, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
767 { .Name: 704, .SubRegs: 2523, .SuperRegs: 2797, .SubRegIndices: 28, .RegUnits: 11976765, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
768 { .Name: 815, .SubRegs: 3827, .SuperRegs: 3017, .SubRegIndices: 28, .RegUnits: 11976766, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
769 { .Name: 921, .SubRegs: 2516, .SuperRegs: 2791, .SubRegIndices: 28, .RegUnits: 11976767, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
770 { .Name: 1035, .SubRegs: 3820, .SuperRegs: 2857, .SubRegIndices: 28, .RegUnits: 11976768, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
771 { .Name: 1141, .SubRegs: 2509, .SuperRegs: 935, .SubRegIndices: 28, .RegUnits: 11976769, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
772 { .Name: 103, .SubRegs: 3813, .SuperRegs: 946, .SubRegIndices: 28, .RegUnits: 11976770, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
773 { .Name: 219, .SubRegs: 2502, .SuperRegs: 3552, .SubRegIndices: 28, .RegUnits: 11976771, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
774 { .Name: 602, .SubRegs: 3490, .SuperRegs: 2490, .SubRegIndices: 190, .RegUnits: 12730390, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
775 { .Name: 720, .SubRegs: 3478, .SuperRegs: 2430, .SubRegIndices: 190, .RegUnits: 12730392, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
776 { .Name: 834, .SubRegs: 3466, .SuperRegs: 2479, .SubRegIndices: 190, .RegUnits: 12730394, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
777 { .Name: 940, .SubRegs: 3454, .SuperRegs: 2386, .SubRegIndices: 190, .RegUnits: 12730396, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
778 { .Name: 1054, .SubRegs: 3442, .SuperRegs: 2386, .SubRegIndices: 190, .RegUnits: 12730398, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
779 { .Name: 1160, .SubRegs: 3430, .SuperRegs: 2275, .SubRegIndices: 190, .RegUnits: 12730400, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
780 { .Name: 3, .SubRegs: 3418, .SuperRegs: 2275, .SubRegIndices: 190, .RegUnits: 12730402, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
781 { .Name: 151, .SubRegs: 3406, .SuperRegs: 2154, .SubRegIndices: 190, .RegUnits: 12730404, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
782 { .Name: 278, .SubRegs: 3394, .SuperRegs: 2154, .SubRegIndices: 190, .RegUnits: 12730406, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
783 { .Name: 404, .SubRegs: 3382, .SuperRegs: 2034, .SubRegIndices: 190, .RegUnits: 12730408, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
784 { .Name: 518, .SubRegs: 3370, .SuperRegs: 2034, .SubRegIndices: 190, .RegUnits: 12730410, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
785 { .Name: 644, .SubRegs: 3358, .SuperRegs: 1914, .SubRegIndices: 190, .RegUnits: 12730412, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
786 { .Name: 763, .SubRegs: 3512, .SuperRegs: 1914, .SubRegIndices: 181, .RegUnits: 14524462, .RegUnitLaneMasks: 78, .IsConstant: 0, .IsArtificial: 0 },
787 { .Name: 877, .SubRegs: 3502, .SuperRegs: 1794, .SubRegIndices: 181, .RegUnits: 13643824, .RegUnitLaneMasks: 78, .IsConstant: 0, .IsArtificial: 0 },
788 { .Name: 983, .SubRegs: 3530, .SuperRegs: 1794, .SubRegIndices: 174, .RegUnits: 13738034, .RegUnitLaneMasks: 83, .IsConstant: 0, .IsArtificial: 0 },
789 { .Name: 1097, .SubRegs: 3522, .SuperRegs: 1698, .SubRegIndices: 174, .RegUnits: 13672500, .RegUnitLaneMasks: 83, .IsConstant: 0, .IsArtificial: 0 },
790 { .Name: 51, .SubRegs: 3538, .SuperRegs: 1698, .SubRegIndices: 169, .RegUnits: 13676598, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
791 { .Name: 203, .SubRegs: 3538, .SuperRegs: 1603, .SubRegIndices: 169, .RegUnits: 13676599, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
792 { .Name: 331, .SubRegs: 3538, .SuperRegs: 1603, .SubRegIndices: 169, .RegUnits: 13676600, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
793 { .Name: 451, .SubRegs: 3538, .SuperRegs: 1533, .SubRegIndices: 169, .RegUnits: 13676601, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
794 { .Name: 570, .SubRegs: 3538, .SuperRegs: 1533, .SubRegIndices: 169, .RegUnits: 13676602, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
795 { .Name: 692, .SubRegs: 3538, .SuperRegs: 1463, .SubRegIndices: 169, .RegUnits: 13676603, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
796 { .Name: 799, .SubRegs: 3538, .SuperRegs: 1463, .SubRegIndices: 169, .RegUnits: 13676604, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
797 { .Name: 909, .SubRegs: 3538, .SuperRegs: 1393, .SubRegIndices: 169, .RegUnits: 13676605, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
798 { .Name: 1019, .SubRegs: 3538, .SuperRegs: 1393, .SubRegIndices: 169, .RegUnits: 13676606, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
799 { .Name: 1129, .SubRegs: 3538, .SuperRegs: 1304, .SubRegIndices: 169, .RegUnits: 13676607, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
800 { .Name: 87, .SubRegs: 3538, .SuperRegs: 1327, .SubRegIndices: 169, .RegUnits: 13676608, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
801 { .Name: 235, .SubRegs: 3538, .SuperRegs: 1266, .SubRegIndices: 169, .RegUnits: 13676609, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
802 { .Name: 831, .SubRegs: 1149, .SuperRegs: 2491, .SubRegIndices: 249, .RegUnits: 12722198, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
803 { .Name: 937, .SubRegs: 1131, .SuperRegs: 2428, .SubRegIndices: 249, .RegUnits: 12722200, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
804 { .Name: 1051, .SubRegs: 1113, .SuperRegs: 2428, .SubRegIndices: 249, .RegUnits: 12722202, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
805 { .Name: 1157, .SubRegs: 1095, .SuperRegs: 2319, .SubRegIndices: 249, .RegUnits: 12722204, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
806 { .Name: 0, .SubRegs: 1077, .SuperRegs: 2319, .SubRegIndices: 249, .RegUnits: 12722206, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
807 { .Name: 148, .SubRegs: 1059, .SuperRegs: 2198, .SubRegIndices: 249, .RegUnits: 12722208, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
808 { .Name: 275, .SubRegs: 1041, .SuperRegs: 2198, .SubRegIndices: 249, .RegUnits: 12722210, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
809 { .Name: 401, .SubRegs: 1023, .SuperRegs: 2097, .SubRegIndices: 249, .RegUnits: 12722212, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
810 { .Name: 515, .SubRegs: 1005, .SuperRegs: 2097, .SubRegIndices: 249, .RegUnits: 12722214, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
811 { .Name: 641, .SubRegs: 987, .SuperRegs: 1977, .SubRegIndices: 249, .RegUnits: 12722216, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
812 { .Name: 759, .SubRegs: 1183, .SuperRegs: 1977, .SubRegIndices: 234, .RegUnits: 14516266, .RegUnitLaneMasks: 98, .IsConstant: 0, .IsArtificial: 0 },
813 { .Name: 873, .SubRegs: 1167, .SuperRegs: 1857, .SubRegIndices: 234, .RegUnits: 13635628, .RegUnitLaneMasks: 98, .IsConstant: 0, .IsArtificial: 0 },
814 { .Name: 979, .SubRegs: 1213, .SuperRegs: 1857, .SubRegIndices: 221, .RegUnits: 13729838, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
815 { .Name: 1093, .SubRegs: 1199, .SuperRegs: 1737, .SubRegIndices: 221, .RegUnits: 13664304, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
816 { .Name: 47, .SubRegs: 1239, .SuperRegs: 1737, .SubRegIndices: 210, .RegUnits: 13709362, .RegUnitLaneMasks: 111, .IsConstant: 0, .IsArtificial: 0 },
817 { .Name: 199, .SubRegs: 1227, .SuperRegs: 1642, .SubRegIndices: 210, .RegUnits: 13688884, .RegUnitLaneMasks: 111, .IsConstant: 0, .IsArtificial: 0 },
818 { .Name: 327, .SubRegs: 1251, .SuperRegs: 1642, .SubRegIndices: 201, .RegUnits: 13692982, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
819 { .Name: 447, .SubRegs: 1251, .SuperRegs: 1571, .SubRegIndices: 201, .RegUnits: 13692983, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
820 { .Name: 566, .SubRegs: 1251, .SuperRegs: 1571, .SubRegIndices: 201, .RegUnits: 13692984, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
821 { .Name: 688, .SubRegs: 1251, .SuperRegs: 1501, .SubRegIndices: 201, .RegUnits: 13692985, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
822 { .Name: 795, .SubRegs: 1251, .SuperRegs: 1501, .SubRegIndices: 201, .RegUnits: 13692986, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
823 { .Name: 905, .SubRegs: 1251, .SuperRegs: 1431, .SubRegIndices: 201, .RegUnits: 13692987, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
824 { .Name: 1015, .SubRegs: 1251, .SuperRegs: 1431, .SubRegIndices: 201, .RegUnits: 13692988, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
825 { .Name: 1125, .SubRegs: 1251, .SuperRegs: 1328, .SubRegIndices: 201, .RegUnits: 13692989, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
826 { .Name: 83, .SubRegs: 1251, .SuperRegs: 1328, .SubRegIndices: 201, .RegUnits: 13692990, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
827 { .Name: 231, .SubRegs: 1251, .SuperRegs: 1267, .SubRegIndices: 201, .RegUnits: 13692991, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
828 { .Name: 372, .SubRegs: 3130, .SuperRegs: 981, .SubRegIndices: 16, .RegUnits: 12689432, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
829 { .Name: 617, .SubRegs: 3158, .SuperRegs: 2675, .SubRegIndices: 16, .RegUnits: 12689436, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
830 { .Name: 849, .SubRegs: 3186, .SuperRegs: 2773, .SubRegIndices: 16, .RegUnits: 12689440, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
831 { .Name: 1069, .SubRegs: 3214, .SuperRegs: 2764, .SubRegIndices: 16, .RegUnits: 12689444, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
832 { .Name: 19, .SubRegs: 3242, .SuperRegs: 2755, .SubRegIndices: 16, .RegUnits: 12689448, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
833 { .Name: 296, .SubRegs: 3270, .SuperRegs: 2746, .SubRegIndices: 16, .RegUnits: 12689452, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
834 { .Name: 538, .SubRegs: 3298, .SuperRegs: 2737, .SubRegIndices: 16, .RegUnits: 12689456, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
835 { .Name: 783, .SubRegs: 2195, .SuperRegs: 2728, .SubRegIndices: 2, .RegUnits: 11976756, .RegUnitLaneMasks: 10, .IsConstant: 0, .IsArtificial: 0 },
836 { .Name: 1003, .SubRegs: 2654, .SuperRegs: 2719, .SubRegIndices: 0, .RegUnits: 10874935, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
837 { .Name: 71, .SubRegs: 2657, .SuperRegs: 2710, .SubRegIndices: 0, .RegUnits: 10874937, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
838 { .Name: 351, .SubRegs: 2660, .SuperRegs: 2701, .SubRegIndices: 0, .RegUnits: 10874939, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
839 { .Name: 590, .SubRegs: 2663, .SuperRegs: 2692, .SubRegIndices: 0, .RegUnits: 10874941, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
840 { .Name: 819, .SubRegs: 2666, .SuperRegs: 2683, .SubRegIndices: 0, .RegUnits: 10874943, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
841 { .Name: 1039, .SubRegs: 2669, .SuperRegs: 919, .SubRegIndices: 0, .RegUnits: 10874945, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
842 { .Name: 107, .SubRegs: 2672, .SuperRegs: 940, .SubRegIndices: 0, .RegUnits: 10874947, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
843 { .Name: 611, .SubRegs: 815, .SuperRegs: 960, .SubRegIndices: 131, .RegUnits: 12673048, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
844 { .Name: 843, .SubRegs: 795, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673052, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
845 { .Name: 1063, .SubRegs: 775, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673056, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
846 { .Name: 13, .SubRegs: 755, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673060, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
847 { .Name: 289, .SubRegs: 735, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673064, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
848 { .Name: 530, .SubRegs: 715, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673068, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
849 { .Name: 775, .SubRegs: 697, .SuperRegs: 2680, .SubRegIndices: 114, .RegUnits: 12677168, .RegUnitLaneMasks: 50, .IsConstant: 0, .IsArtificial: 0 },
850 { .Name: 995, .SubRegs: 683, .SuperRegs: 2680, .SubRegIndices: 101, .RegUnits: 12685364, .RegUnitLaneMasks: 63, .IsConstant: 0, .IsArtificial: 0 },
851 { .Name: 63, .SubRegs: 60, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689463, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
852 { .Name: 343, .SubRegs: 48, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689465, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
853 { .Name: 582, .SubRegs: 36, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689467, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
854 { .Name: 811, .SubRegs: 24, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689469, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
855 { .Name: 1031, .SubRegs: 12, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689471, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
856 { .Name: 99, .SubRegs: 0, .SuperRegs: 854, .SubRegIndices: 90, .RegUnits: 12689473, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
857};
858
859extern const MCPhysReg ARMRegUnitRoots[][2] = {
860 { ARM::APSR },
861 { ARM::APSR_NZCV },
862 { ARM::CPSR },
863 { ARM::FPCXTNS },
864 { ARM::FPCXTS },
865 { ARM::FPEXC },
866 { ARM::FPINST },
867 { ARM::FPSCR },
868 { ARM::FPSCR, ARM::FPSCR_NZCV },
869 { ARM::FPSCR, ARM::FPSCR_RM },
870 { ARM::FPSCR_NZCV },
871 { ARM::FPSCR_NZCVQC },
872 { ARM::FPSCR_RM },
873 { ARM::FPSID },
874 { ARM::ITSTATE },
875 { ARM::LR },
876 { ARM::PC },
877 { ARM::RA_AUTH_CODE },
878 { ARM::SP },
879 { ARM::SPSR },
880 { ARM::VPR },
881 { ARM::ZR },
882 { ARM::S0 },
883 { ARM::S1 },
884 { ARM::S2 },
885 { ARM::S3 },
886 { ARM::S4 },
887 { ARM::S5 },
888 { ARM::S6 },
889 { ARM::S7 },
890 { ARM::S8 },
891 { ARM::S9 },
892 { ARM::S10 },
893 { ARM::S11 },
894 { ARM::S12 },
895 { ARM::S13 },
896 { ARM::S14 },
897 { ARM::S15 },
898 { ARM::S16 },
899 { ARM::S17 },
900 { ARM::S18 },
901 { ARM::S19 },
902 { ARM::S20 },
903 { ARM::S21 },
904 { ARM::S22 },
905 { ARM::S23 },
906 { ARM::S24 },
907 { ARM::S25 },
908 { ARM::S26 },
909 { ARM::S27 },
910 { ARM::S28 },
911 { ARM::S29 },
912 { ARM::S30 },
913 { ARM::S31 },
914 { ARM::D16 },
915 { ARM::D17 },
916 { ARM::D18 },
917 { ARM::D19 },
918 { ARM::D20 },
919 { ARM::D21 },
920 { ARM::D22 },
921 { ARM::D23 },
922 { ARM::D24 },
923 { ARM::D25 },
924 { ARM::D26 },
925 { ARM::D27 },
926 { ARM::D28 },
927 { ARM::D29 },
928 { ARM::D30 },
929 { ARM::D31 },
930 { ARM::FPINST2 },
931 { ARM::MVFR0 },
932 { ARM::MVFR1 },
933 { ARM::MVFR2 },
934 { ARM::P0 },
935 { ARM::R0 },
936 { ARM::R1 },
937 { ARM::R2 },
938 { ARM::R3 },
939 { ARM::R4 },
940 { ARM::R5 },
941 { ARM::R6 },
942 { ARM::R7 },
943 { ARM::R8 },
944 { ARM::R9 },
945 { ARM::R10 },
946 { ARM::R11 },
947 { ARM::R12 },
948};
949
950// Register classes...
951
952#ifdef __GNUC__
953#pragma GCC diagnostic push
954#pragma GCC diagnostic ignored "-Woverlength-strings"
955#endif
956extern const char ARMRegClassStrings[] = {
957 /* 0 */ "QQQQPR_with_ssub_0\000"
958 /* 19 */ "FPWithVPR_with_ssub_0\000"
959 /* 41 */ "DQuadSpc_with_ssub_0\000"
960 /* 62 */ "DTripleSpc_with_ssub_0\000"
961 /* 85 */ "DPairSpc_with_ssub_0\000"
962 /* 106 */ "DQuad_with_ssub_0\000"
963 /* 124 */ "DTriple_with_ssub_0\000"
964 /* 144 */ "DPair_with_ssub_0\000"
965 /* 162 */ "tGPREven_and_tcGPRnotr12\000"
966 /* 187 */ "GPRPair_with_gsub_0_in_tcGPRnotr12\000"
967 /* 222 */ "DPR_VFP2\000"
968 /* 231 */ "QPR_VFP2\000"
969 /* 240 */ "DQuad_with_ssub_2\000"
970 /* 258 */ "DTriple_with_ssub_2\000"
971 /* 278 */ "DPair_with_ssub_2\000"
972 /* 296 */ "QQQQPR_with_ssub_4\000"
973 /* 315 */ "DQuadSpc_with_ssub_4\000"
974 /* 336 */ "DTripleSpc_with_ssub_4\000"
975 /* 359 */ "DPairSpc_with_ssub_4\000"
976 /* 380 */ "DQuad_with_ssub_4\000"
977 /* 398 */ "DTriple_with_ssub_4\000"
978 /* 418 */ "DQuad_with_ssub_6\000"
979 /* 436 */ "DQuadSpc_with_dsub_0_in_DPR_8\000"
980 /* 466 */ "DTripleSpc_with_dsub_0_in_DPR_8\000"
981 /* 498 */ "DPairSpc_with_dsub_0_in_DPR_8\000"
982 /* 528 */ "DQuad_with_dsub_0_in_DPR_8\000"
983 /* 555 */ "DTriple_with_dsub_0_in_DPR_8\000"
984 /* 584 */ "DPair_with_dsub_0_in_DPR_8\000"
985 /* 611 */ "DQuad_with_dsub_1_in_DPR_8\000"
986 /* 638 */ "DTriple_with_dsub_1_in_DPR_8\000"
987 /* 667 */ "DPair_with_dsub_1_in_DPR_8\000"
988 /* 694 */ "MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8\000"
989 /* 745 */ "MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8\000"
990 /* 796 */ "DQuadSpc_with_dsub_2_in_DPR_8\000"
991 /* 826 */ "DTripleSpc_with_dsub_2_in_DPR_8\000"
992 /* 858 */ "DPairSpc_with_dsub_2_in_DPR_8\000"
993 /* 888 */ "DQuad_with_dsub_2_in_DPR_8\000"
994 /* 915 */ "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8\000"
995 /* 1032 */ "DQuad_with_dsub_3_in_DPR_8\000"
996 /* 1059 */ "DQuadSpc_with_dsub_4_in_DPR_8\000"
997 /* 1089 */ "DTripleSpc_with_dsub_4_in_DPR_8\000"
998 /* 1121 */ "MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8\000"
999 /* 1172 */ "DTriple_with_qsub_0_in_QPR_8\000"
1000 /* 1201 */ "MQQQQPR_with_qsub_2_in_QPR_8\000"
1001 /* 1230 */ "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8\000"
1002 /* 1278 */ "DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8\000"
1003 /* 1328 */ "FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8\000"
1004 /* 1371 */ "QQQQPR_with_ssub_8\000"
1005 /* 1390 */ "DQuadSpc_with_ssub_8\000"
1006 /* 1411 */ "DTripleSpc_with_ssub_8\000"
1007 /* 1434 */ "VCCR\000"
1008 /* 1439 */ "DPR\000"
1009 /* 1443 */ "hGPR_and_tcGPR\000"
1010 /* 1458 */ "tGPROdd_and_tcGPR\000"
1011 /* 1476 */ "tGPREven_and_tcGPR\000"
1012 /* 1495 */ "GPRPair_with_gsub_0_in_tcGPR\000"
1013 /* 1524 */ "GPRnosp_and_GPRnopc_and_hGPR\000"
1014 /* 1553 */ "GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR\000"
1015 /* 1594 */ "GPRnosp_and_GPRnoip_and_hGPR\000"
1016 /* 1623 */ "GPRnosp_and_hGPR\000"
1017 /* 1640 */ "GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR\000"
1018 /* 1684 */ "rGPR\000"
1019 /* 1689 */ "GPRPair_with_gsub_0_in_tGPR\000"
1020 /* 1717 */ "HPR\000"
1021 /* 1721 */ "DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR\000"
1022 /* 1773 */ "DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR\000"
1023 /* 1842 */ "DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR\000"
1024 /* 1980 */ "MQQPR\000"
1025 /* 1986 */ "MQQQQPR\000"
1026 /* 1994 */ "DTriple_with_qsub_0_in_QPR\000"
1027 /* 2021 */ "DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR\000"
1028 /* 2089 */ "DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR\000"
1029 /* 2161 */ "SPR\000"
1030 /* 2165 */ "FPWithVPR\000"
1031 /* 2175 */ "GPRwithAPSR\000"
1032 /* 2187 */ "GPRwithZR\000"
1033 /* 2197 */ "FP_STATUS_REGS\000"
1034 /* 2212 */ "cl_FPSCR_NZCV\000"
1035 /* 2226 */ "DQuadSpc\000"
1036 /* 2235 */ "DTripleSpc\000"
1037 /* 2246 */ "DPairSpc\000"
1038 /* 2255 */ "hGPR_and_tGPRwithpc\000"
1039 /* 2275 */ "GPRnoip_and_GPRnopc\000"
1040 /* 2295 */ "DQuad\000"
1041 /* 2301 */ "hGPR_and_tGPROdd\000"
1042 /* 2318 */ "tGPR_and_tGPROdd\000"
1043 /* 2335 */ "DTriple\000"
1044 /* 2343 */ "hGPR_and_tGPREven\000"
1045 /* 2361 */ "tGPR_and_tGPREven\000"
1046 /* 2379 */ "hGPR_and_GPRnoip_and_tGPREven\000"
1047 /* 2409 */ "GPRnoip\000"
1048 /* 2417 */ "GPRPair_with_gsub_1_in_GPRsp\000"
1049 /* 2446 */ "GPRnoip_and_GPRnosp\000"
1050 /* 2466 */ "GPRwithAPSRnosp\000"
1051 /* 2482 */ "GPRwithZRnosp\000"
1052 /* 2496 */ "GPRnoip_and_GPRwithAPSR_NZCVnosp\000"
1053 /* 2529 */ "GPRPairnosp\000"
1054 /* 2541 */ "DPair\000"
1055 /* 2547 */ "GPRPair\000"
1056 /* 2555 */ "GPRlr\000"
1057 /* 2561 */ "FPCXTRegs\000"
1058};
1059#ifdef __GNUC__
1060#pragma GCC diagnostic pop
1061#endif
1062
1063using ARMRegisterClassStorage = MCRegisterClassStorage<137, 1345, 2692, 3020, 94, 755>;
1064extern const MCRegisterClassStorage<137, 1345, 2692, 3020, 94, 755> ARMMCRegisterClassStorage = {
1065 .Classes: {
1066 {
1067 offsetof(ARMRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
1068 offsetof(ARMRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
1069 .NameIdx: 1717,
1070 .RegSizeInBits: 16,
1071 .RegsSize: 32,
1072 .RegSetSize: 15,
1073 .ID: ARM::HPRRegClassID,
1074 .CopyCost: 1, /* CopyCost */
1075 .Allocatable: true, /* Allocatable */
1076 .BaseClass: false,
1077 offsetof(ARMRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
1078 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[22]) - 0 * sizeof(MCRegisterClass),
1079 .LaneMask: LaneBitmask(0x0000000000000001),
1080 .AllocationPriority: 0,
1081 .GlobalPriority: false,
1082 .TSFlags: 0x00, /* TSFlags */
1083 .SpillStackID: 0, /* SpillStackID */
1084 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1085 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1086 offsetof(ARMRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
1087 .SuperClassesSize: 0
1088 },
1089 {
1090 offsetof(ARMRegisterClassStorage, Regs[32]) - 1 * sizeof(MCRegisterClass),
1091 offsetof(ARMRegisterClassStorage, BitSets[15]) - 1 * sizeof(MCRegisterClass),
1092 .NameIdx: 2165,
1093 .RegSizeInBits: 32,
1094 .RegsSize: 65,
1095 .RegSetSize: 15,
1096 .ID: ARM::FPWithVPRRegClassID,
1097 .CopyCost: 1, /* CopyCost */
1098 .Allocatable: false, /* Allocatable */
1099 .BaseClass: false,
1100 offsetof(ARMRegisterClassStorage, SubClassMasks[85]) - 1 * sizeof(MCRegisterClass),
1101 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[14]) - 1 * sizeof(MCRegisterClass),
1102 .LaneMask: LaneBitmask(0x000000000000000C),
1103 .AllocationPriority: 0,
1104 .GlobalPriority: false,
1105 .TSFlags: 0x00, /* TSFlags */
1106 .SpillStackID: 0, /* SpillStackID */
1107 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1108 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1109 offsetof(ARMRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
1110 .SuperClassesSize: 0
1111 },
1112 {
1113 offsetof(ARMRegisterClassStorage, Regs[97]) - 2 * sizeof(MCRegisterClass),
1114 offsetof(ARMRegisterClassStorage, BitSets[30]) - 2 * sizeof(MCRegisterClass),
1115 .NameIdx: 2161,
1116 .RegSizeInBits: 32,
1117 .RegsSize: 32,
1118 .RegSetSize: 15,
1119 .ID: ARM::SPRRegClassID,
1120 .CopyCost: 1, /* CopyCost */
1121 .Allocatable: true, /* Allocatable */
1122 .BaseClass: false,
1123 offsetof(ARMRegisterClassStorage, SubClassMasks[210]) - 2 * sizeof(MCRegisterClass),
1124 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[22]) - 2 * sizeof(MCRegisterClass),
1125 .LaneMask: LaneBitmask(0x0000000000000001),
1126 .AllocationPriority: 0,
1127 .GlobalPriority: false,
1128 .TSFlags: 0x00, /* TSFlags */
1129 .SpillStackID: 0, /* SpillStackID */
1130 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1131 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1132 offsetof(ARMRegisterClassStorage, SuperClasses[0]) - 2 * sizeof(MCRegisterClass),
1133 .SuperClassesSize: 2
1134 },
1135 {
1136 offsetof(ARMRegisterClassStorage, Regs[129]) - 3 * sizeof(MCRegisterClass),
1137 offsetof(ARMRegisterClassStorage, BitSets[45]) - 3 * sizeof(MCRegisterClass),
1138 .NameIdx: 19,
1139 .RegSizeInBits: 32,
1140 .RegsSize: 16,
1141 .RegSetSize: 5,
1142 .ID: ARM::FPWithVPR_with_ssub_0RegClassID,
1143 .CopyCost: 1, /* CopyCost */
1144 .Allocatable: false, /* Allocatable */
1145 .BaseClass: false,
1146 offsetof(ARMRegisterClassStorage, SubClassMasks[295]) - 3 * sizeof(MCRegisterClass),
1147 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[0]) - 3 * sizeof(MCRegisterClass),
1148 .LaneMask: LaneBitmask(0x000000000000000C),
1149 .AllocationPriority: 0,
1150 .GlobalPriority: false,
1151 .TSFlags: 0x00, /* TSFlags */
1152 .SpillStackID: 0, /* SpillStackID */
1153 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1154 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1155 offsetof(ARMRegisterClassStorage, SuperClasses[2]) - 3 * sizeof(MCRegisterClass),
1156 .SuperClassesSize: 1
1157 },
1158 {
1159 offsetof(ARMRegisterClassStorage, Regs[145]) - 4 * sizeof(MCRegisterClass),
1160 offsetof(ARMRegisterClassStorage, BitSets[50]) - 4 * sizeof(MCRegisterClass),
1161 .NameIdx: 1454,
1162 .RegSizeInBits: 32,
1163 .RegsSize: 16,
1164 .RegSetSize: 11,
1165 .ID: ARM::GPRRegClassID,
1166 .CopyCost: 1, /* CopyCost */
1167 .Allocatable: true, /* Allocatable */
1168 .BaseClass: false,
1169 offsetof(ARMRegisterClassStorage, SubClassMasks[340]) - 4 * sizeof(MCRegisterClass),
1170 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 4 * sizeof(MCRegisterClass),
1171 .LaneMask: LaneBitmask(0x0000000000000001),
1172 .AllocationPriority: 0,
1173 .GlobalPriority: false,
1174 .TSFlags: 0x00, /* TSFlags */
1175 .SpillStackID: 0, /* SpillStackID */
1176 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1177 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1178 offsetof(ARMRegisterClassStorage, SuperClasses[3]) - 4 * sizeof(MCRegisterClass),
1179 .SuperClassesSize: 0
1180 },
1181 {
1182 offsetof(ARMRegisterClassStorage, Regs[161]) - 5 * sizeof(MCRegisterClass),
1183 offsetof(ARMRegisterClassStorage, BitSets[61]) - 5 * sizeof(MCRegisterClass),
1184 .NameIdx: 2175,
1185 .RegSizeInBits: 32,
1186 .RegsSize: 16,
1187 .RegSetSize: 11,
1188 .ID: ARM::GPRwithAPSRRegClassID,
1189 .CopyCost: 1, /* CopyCost */
1190 .Allocatable: true, /* Allocatable */
1191 .BaseClass: false,
1192 offsetof(ARMRegisterClassStorage, SubClassMasks[355]) - 5 * sizeof(MCRegisterClass),
1193 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 5 * sizeof(MCRegisterClass),
1194 .LaneMask: LaneBitmask(0x0000000000000001),
1195 .AllocationPriority: 0,
1196 .GlobalPriority: false,
1197 .TSFlags: 0x00, /* TSFlags */
1198 .SpillStackID: 0, /* SpillStackID */
1199 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1200 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1201 offsetof(ARMRegisterClassStorage, SuperClasses[3]) - 5 * sizeof(MCRegisterClass),
1202 .SuperClassesSize: 0
1203 },
1204 {
1205 offsetof(ARMRegisterClassStorage, Regs[177]) - 6 * sizeof(MCRegisterClass),
1206 offsetof(ARMRegisterClassStorage, BitSets[72]) - 6 * sizeof(MCRegisterClass),
1207 .NameIdx: 2187,
1208 .RegSizeInBits: 32,
1209 .RegsSize: 16,
1210 .RegSetSize: 11,
1211 .ID: ARM::GPRwithZRRegClassID,
1212 .CopyCost: 1, /* CopyCost */
1213 .Allocatable: true, /* Allocatable */
1214 .BaseClass: false,
1215 offsetof(ARMRegisterClassStorage, SubClassMasks[370]) - 6 * sizeof(MCRegisterClass),
1216 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 6 * sizeof(MCRegisterClass),
1217 .LaneMask: LaneBitmask(0x0000000000000001),
1218 .AllocationPriority: 0,
1219 .GlobalPriority: false,
1220 .TSFlags: 0x00, /* TSFlags */
1221 .SpillStackID: 0, /* SpillStackID */
1222 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1223 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1224 offsetof(ARMRegisterClassStorage, SuperClasses[3]) - 6 * sizeof(MCRegisterClass),
1225 .SuperClassesSize: 0
1226 },
1227 {
1228 offsetof(ARMRegisterClassStorage, Regs[193]) - 7 * sizeof(MCRegisterClass),
1229 offsetof(ARMRegisterClassStorage, BitSets[83]) - 7 * sizeof(MCRegisterClass),
1230 .NameIdx: 1365,
1231 .RegSizeInBits: 32,
1232 .RegsSize: 16,
1233 .RegSetSize: 13,
1234 .ID: ARM::SPR_8RegClassID,
1235 .CopyCost: 1, /* CopyCost */
1236 .Allocatable: true, /* Allocatable */
1237 .BaseClass: false,
1238 offsetof(ARMRegisterClassStorage, SubClassMasks[385]) - 7 * sizeof(MCRegisterClass),
1239 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[22]) - 7 * sizeof(MCRegisterClass),
1240 .LaneMask: LaneBitmask(0x0000000000000001),
1241 .AllocationPriority: 0,
1242 .GlobalPriority: false,
1243 .TSFlags: 0x00, /* TSFlags */
1244 .SpillStackID: 0, /* SpillStackID */
1245 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1246 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1247 offsetof(ARMRegisterClassStorage, SuperClasses[3]) - 7 * sizeof(MCRegisterClass),
1248 .SuperClassesSize: 3
1249 },
1250 {
1251 offsetof(ARMRegisterClassStorage, Regs[209]) - 8 * sizeof(MCRegisterClass),
1252 offsetof(ARMRegisterClassStorage, BitSets[96]) - 8 * sizeof(MCRegisterClass),
1253 .NameIdx: 2287,
1254 .RegSizeInBits: 32,
1255 .RegsSize: 15,
1256 .RegSetSize: 11,
1257 .ID: ARM::GPRnopcRegClassID,
1258 .CopyCost: 1, /* CopyCost */
1259 .Allocatable: true, /* Allocatable */
1260 .BaseClass: false,
1261 offsetof(ARMRegisterClassStorage, SubClassMasks[470]) - 8 * sizeof(MCRegisterClass),
1262 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 8 * sizeof(MCRegisterClass),
1263 .LaneMask: LaneBitmask(0x0000000000000001),
1264 .AllocationPriority: 0,
1265 .GlobalPriority: false,
1266 .TSFlags: 0x00, /* TSFlags */
1267 .SpillStackID: 0, /* SpillStackID */
1268 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1269 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1270 offsetof(ARMRegisterClassStorage, SuperClasses[6]) - 8 * sizeof(MCRegisterClass),
1271 .SuperClassesSize: 3
1272 },
1273 {
1274 offsetof(ARMRegisterClassStorage, Regs[224]) - 9 * sizeof(MCRegisterClass),
1275 offsetof(ARMRegisterClassStorage, BitSets[107]) - 9 * sizeof(MCRegisterClass),
1276 .NameIdx: 2458,
1277 .RegSizeInBits: 32,
1278 .RegsSize: 15,
1279 .RegSetSize: 11,
1280 .ID: ARM::GPRnospRegClassID,
1281 .CopyCost: 1, /* CopyCost */
1282 .Allocatable: true, /* Allocatable */
1283 .BaseClass: false,
1284 offsetof(ARMRegisterClassStorage, SubClassMasks[485]) - 9 * sizeof(MCRegisterClass),
1285 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 9 * sizeof(MCRegisterClass),
1286 .LaneMask: LaneBitmask(0x0000000000000001),
1287 .AllocationPriority: 0,
1288 .GlobalPriority: false,
1289 .TSFlags: 0x00, /* TSFlags */
1290 .SpillStackID: 0, /* SpillStackID */
1291 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1292 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1293 offsetof(ARMRegisterClassStorage, SuperClasses[9]) - 9 * sizeof(MCRegisterClass),
1294 .SuperClassesSize: 1
1295 },
1296 {
1297 offsetof(ARMRegisterClassStorage, Regs[239]) - 10 * sizeof(MCRegisterClass),
1298 offsetof(ARMRegisterClassStorage, BitSets[118]) - 10 * sizeof(MCRegisterClass),
1299 .NameIdx: 2508,
1300 .RegSizeInBits: 32,
1301 .RegsSize: 15,
1302 .RegSetSize: 11,
1303 .ID: ARM::GPRwithAPSR_NZCVnospRegClassID,
1304 .CopyCost: 1, /* CopyCost */
1305 .Allocatable: false, /* Allocatable */
1306 .BaseClass: false,
1307 offsetof(ARMRegisterClassStorage, SubClassMasks[500]) - 10 * sizeof(MCRegisterClass),
1308 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 10 * sizeof(MCRegisterClass),
1309 .LaneMask: LaneBitmask(0x0000000000000001),
1310 .AllocationPriority: 0,
1311 .GlobalPriority: false,
1312 .TSFlags: 0x00, /* TSFlags */
1313 .SpillStackID: 0, /* SpillStackID */
1314 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1315 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1316 offsetof(ARMRegisterClassStorage, SuperClasses[10]) - 10 * sizeof(MCRegisterClass),
1317 .SuperClassesSize: 1
1318 },
1319 {
1320 offsetof(ARMRegisterClassStorage, Regs[254]) - 11 * sizeof(MCRegisterClass),
1321 offsetof(ARMRegisterClassStorage, BitSets[129]) - 11 * sizeof(MCRegisterClass),
1322 .NameIdx: 2466,
1323 .RegSizeInBits: 32,
1324 .RegsSize: 15,
1325 .RegSetSize: 11,
1326 .ID: ARM::GPRwithAPSRnospRegClassID,
1327 .CopyCost: 1, /* CopyCost */
1328 .Allocatable: false, /* Allocatable */
1329 .BaseClass: false,
1330 offsetof(ARMRegisterClassStorage, SubClassMasks[515]) - 11 * sizeof(MCRegisterClass),
1331 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 11 * sizeof(MCRegisterClass),
1332 .LaneMask: LaneBitmask(0x0000000000000001),
1333 .AllocationPriority: 0,
1334 .GlobalPriority: false,
1335 .TSFlags: 0x00, /* TSFlags */
1336 .SpillStackID: 0, /* SpillStackID */
1337 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1338 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1339 offsetof(ARMRegisterClassStorage, SuperClasses[11]) - 11 * sizeof(MCRegisterClass),
1340 .SuperClassesSize: 0
1341 },
1342 {
1343 offsetof(ARMRegisterClassStorage, Regs[269]) - 12 * sizeof(MCRegisterClass),
1344 offsetof(ARMRegisterClassStorage, BitSets[140]) - 12 * sizeof(MCRegisterClass),
1345 .NameIdx: 2482,
1346 .RegSizeInBits: 32,
1347 .RegsSize: 15,
1348 .RegSetSize: 11,
1349 .ID: ARM::GPRwithZRnospRegClassID,
1350 .CopyCost: 1, /* CopyCost */
1351 .Allocatable: true, /* Allocatable */
1352 .BaseClass: false,
1353 offsetof(ARMRegisterClassStorage, SubClassMasks[530]) - 12 * sizeof(MCRegisterClass),
1354 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 12 * sizeof(MCRegisterClass),
1355 .LaneMask: LaneBitmask(0x0000000000000001),
1356 .AllocationPriority: 0,
1357 .GlobalPriority: false,
1358 .TSFlags: 0x00, /* TSFlags */
1359 .SpillStackID: 0, /* SpillStackID */
1360 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1361 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1362 offsetof(ARMRegisterClassStorage, SuperClasses[11]) - 12 * sizeof(MCRegisterClass),
1363 .SuperClassesSize: 1
1364 },
1365 {
1366 offsetof(ARMRegisterClassStorage, Regs[284]) - 13 * sizeof(MCRegisterClass),
1367 offsetof(ARMRegisterClassStorage, BitSets[151]) - 13 * sizeof(MCRegisterClass),
1368 .NameIdx: 2409,
1369 .RegSizeInBits: 32,
1370 .RegsSize: 14,
1371 .RegSetSize: 11,
1372 .ID: ARM::GPRnoipRegClassID,
1373 .CopyCost: 1, /* CopyCost */
1374 .Allocatable: true, /* Allocatable */
1375 .BaseClass: false,
1376 offsetof(ARMRegisterClassStorage, SubClassMasks[545]) - 13 * sizeof(MCRegisterClass),
1377 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 13 * sizeof(MCRegisterClass),
1378 .LaneMask: LaneBitmask(0x0000000000000001),
1379 .AllocationPriority: 0,
1380 .GlobalPriority: false,
1381 .TSFlags: 0x00, /* TSFlags */
1382 .SpillStackID: 0, /* SpillStackID */
1383 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1384 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1385 offsetof(ARMRegisterClassStorage, SuperClasses[12]) - 13 * sizeof(MCRegisterClass),
1386 .SuperClassesSize: 1
1387 },
1388 {
1389 offsetof(ARMRegisterClassStorage, Regs[298]) - 14 * sizeof(MCRegisterClass),
1390 offsetof(ARMRegisterClassStorage, BitSets[162]) - 14 * sizeof(MCRegisterClass),
1391 .NameIdx: 1684,
1392 .RegSizeInBits: 32,
1393 .RegsSize: 14,
1394 .RegSetSize: 11,
1395 .ID: ARM::rGPRRegClassID,
1396 .CopyCost: 1, /* CopyCost */
1397 .Allocatable: true, /* Allocatable */
1398 .BaseClass: false,
1399 offsetof(ARMRegisterClassStorage, SubClassMasks[560]) - 14 * sizeof(MCRegisterClass),
1400 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 14 * sizeof(MCRegisterClass),
1401 .LaneMask: LaneBitmask(0x0000000000000001),
1402 .AllocationPriority: 0,
1403 .GlobalPriority: false,
1404 .TSFlags: 0x00, /* TSFlags */
1405 .SpillStackID: 0, /* SpillStackID */
1406 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1407 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1408 offsetof(ARMRegisterClassStorage, SuperClasses[13]) - 14 * sizeof(MCRegisterClass),
1409 .SuperClassesSize: 8
1410 },
1411 {
1412 offsetof(ARMRegisterClassStorage, Regs[312]) - 15 * sizeof(MCRegisterClass),
1413 offsetof(ARMRegisterClassStorage, BitSets[173]) - 15 * sizeof(MCRegisterClass),
1414 .NameIdx: 2275,
1415 .RegSizeInBits: 32,
1416 .RegsSize: 13,
1417 .RegSetSize: 11,
1418 .ID: ARM::GPRnoip_and_GPRnopcRegClassID,
1419 .CopyCost: 1, /* CopyCost */
1420 .Allocatable: true, /* Allocatable */
1421 .BaseClass: false,
1422 offsetof(ARMRegisterClassStorage, SubClassMasks[575]) - 15 * sizeof(MCRegisterClass),
1423 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 15 * sizeof(MCRegisterClass),
1424 .LaneMask: LaneBitmask(0x0000000000000001),
1425 .AllocationPriority: 0,
1426 .GlobalPriority: false,
1427 .TSFlags: 0x00, /* TSFlags */
1428 .SpillStackID: 0, /* SpillStackID */
1429 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1430 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1431 offsetof(ARMRegisterClassStorage, SuperClasses[21]) - 15 * sizeof(MCRegisterClass),
1432 .SuperClassesSize: 5
1433 },
1434 {
1435 offsetof(ARMRegisterClassStorage, Regs[325]) - 16 * sizeof(MCRegisterClass),
1436 offsetof(ARMRegisterClassStorage, BitSets[184]) - 16 * sizeof(MCRegisterClass),
1437 .NameIdx: 2446,
1438 .RegSizeInBits: 32,
1439 .RegsSize: 13,
1440 .RegSetSize: 11,
1441 .ID: ARM::GPRnoip_and_GPRnospRegClassID,
1442 .CopyCost: 1, /* CopyCost */
1443 .Allocatable: true, /* Allocatable */
1444 .BaseClass: false,
1445 offsetof(ARMRegisterClassStorage, SubClassMasks[590]) - 16 * sizeof(MCRegisterClass),
1446 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 16 * sizeof(MCRegisterClass),
1447 .LaneMask: LaneBitmask(0x0000000000000001),
1448 .AllocationPriority: 0,
1449 .GlobalPriority: false,
1450 .TSFlags: 0x00, /* TSFlags */
1451 .SpillStackID: 0, /* SpillStackID */
1452 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1453 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1454 offsetof(ARMRegisterClassStorage, SuperClasses[26]) - 16 * sizeof(MCRegisterClass),
1455 .SuperClassesSize: 3
1456 },
1457 {
1458 offsetof(ARMRegisterClassStorage, Regs[338]) - 17 * sizeof(MCRegisterClass),
1459 offsetof(ARMRegisterClassStorage, BitSets[195]) - 17 * sizeof(MCRegisterClass),
1460 .NameIdx: 2496,
1461 .RegSizeInBits: 32,
1462 .RegsSize: 12,
1463 .RegSetSize: 11,
1464 .ID: ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID,
1465 .CopyCost: 1, /* CopyCost */
1466 .Allocatable: true, /* Allocatable */
1467 .BaseClass: false,
1468 offsetof(ARMRegisterClassStorage, SubClassMasks[605]) - 17 * sizeof(MCRegisterClass),
1469 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 17 * sizeof(MCRegisterClass),
1470 .LaneMask: LaneBitmask(0x0000000000000001),
1471 .AllocationPriority: 0,
1472 .GlobalPriority: false,
1473 .TSFlags: 0x00, /* TSFlags */
1474 .SpillStackID: 0, /* SpillStackID */
1475 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1476 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1477 offsetof(ARMRegisterClassStorage, SuperClasses[29]) - 17 * sizeof(MCRegisterClass),
1478 .SuperClassesSize: 12
1479 },
1480 {
1481 offsetof(ARMRegisterClassStorage, Regs[350]) - 18 * sizeof(MCRegisterClass),
1482 offsetof(ARMRegisterClassStorage, BitSets[206]) - 18 * sizeof(MCRegisterClass),
1483 .NameIdx: 2264,
1484 .RegSizeInBits: 32,
1485 .RegsSize: 9,
1486 .RegSetSize: 11,
1487 .ID: ARM::tGPRwithpcRegClassID,
1488 .CopyCost: 1, /* CopyCost */
1489 .Allocatable: true, /* Allocatable */
1490 .BaseClass: false,
1491 offsetof(ARMRegisterClassStorage, SubClassMasks[620]) - 18 * sizeof(MCRegisterClass),
1492 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 18 * sizeof(MCRegisterClass),
1493 .LaneMask: LaneBitmask(0x0000000000000001),
1494 .AllocationPriority: 0,
1495 .GlobalPriority: false,
1496 .TSFlags: 0x00, /* TSFlags */
1497 .SpillStackID: 0, /* SpillStackID */
1498 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1499 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1500 offsetof(ARMRegisterClassStorage, SuperClasses[41]) - 18 * sizeof(MCRegisterClass),
1501 .SuperClassesSize: 4
1502 },
1503 {
1504 offsetof(ARMRegisterClassStorage, Regs[359]) - 19 * sizeof(MCRegisterClass),
1505 offsetof(ARMRegisterClassStorage, BitSets[217]) - 19 * sizeof(MCRegisterClass),
1506 .NameIdx: 1328,
1507 .RegSizeInBits: 32,
1508 .RegsSize: 8,
1509 .RegSetSize: 4,
1510 .ID: ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID,
1511 .CopyCost: 1, /* CopyCost */
1512 .Allocatable: false, /* Allocatable */
1513 .BaseClass: false,
1514 offsetof(ARMRegisterClassStorage, SubClassMasks[635]) - 19 * sizeof(MCRegisterClass),
1515 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[0]) - 19 * sizeof(MCRegisterClass),
1516 .LaneMask: LaneBitmask(0x000000000000000C),
1517 .AllocationPriority: 0,
1518 .GlobalPriority: false,
1519 .TSFlags: 0x00, /* TSFlags */
1520 .SpillStackID: 0, /* SpillStackID */
1521 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1522 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1523 offsetof(ARMRegisterClassStorage, SuperClasses[45]) - 19 * sizeof(MCRegisterClass),
1524 .SuperClassesSize: 2
1525 },
1526 {
1527 offsetof(ARMRegisterClassStorage, Regs[367]) - 20 * sizeof(MCRegisterClass),
1528 offsetof(ARMRegisterClassStorage, BitSets[221]) - 20 * sizeof(MCRegisterClass),
1529 .NameIdx: 1548,
1530 .RegSizeInBits: 32,
1531 .RegsSize: 8,
1532 .RegSetSize: 11,
1533 .ID: ARM::hGPRRegClassID,
1534 .CopyCost: 1, /* CopyCost */
1535 .Allocatable: true, /* Allocatable */
1536 .BaseClass: false,
1537 offsetof(ARMRegisterClassStorage, SubClassMasks[680]) - 20 * sizeof(MCRegisterClass),
1538 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 20 * sizeof(MCRegisterClass),
1539 .LaneMask: LaneBitmask(0x0000000000000001),
1540 .AllocationPriority: 0,
1541 .GlobalPriority: false,
1542 .TSFlags: 0x00, /* TSFlags */
1543 .SpillStackID: 0, /* SpillStackID */
1544 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1545 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1546 offsetof(ARMRegisterClassStorage, SuperClasses[47]) - 20 * sizeof(MCRegisterClass),
1547 .SuperClassesSize: 1
1548 },
1549 {
1550 offsetof(ARMRegisterClassStorage, Regs[375]) - 21 * sizeof(MCRegisterClass),
1551 offsetof(ARMRegisterClassStorage, BitSets[232]) - 21 * sizeof(MCRegisterClass),
1552 .NameIdx: 1712,
1553 .RegSizeInBits: 32,
1554 .RegsSize: 8,
1555 .RegSetSize: 11,
1556 .ID: ARM::tGPRRegClassID,
1557 .CopyCost: 1, /* CopyCost */
1558 .Allocatable: true, /* Allocatable */
1559 .BaseClass: false,
1560 offsetof(ARMRegisterClassStorage, SubClassMasks[695]) - 21 * sizeof(MCRegisterClass),
1561 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 21 * sizeof(MCRegisterClass),
1562 .LaneMask: LaneBitmask(0x0000000000000001),
1563 .AllocationPriority: 0,
1564 .GlobalPriority: false,
1565 .TSFlags: 0x00, /* TSFlags */
1566 .SpillStackID: 0, /* SpillStackID */
1567 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1568 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1569 offsetof(ARMRegisterClassStorage, SuperClasses[48]) - 21 * sizeof(MCRegisterClass),
1570 .SuperClassesSize: 14
1571 },
1572 {
1573 offsetof(ARMRegisterClassStorage, Regs[383]) - 22 * sizeof(MCRegisterClass),
1574 offsetof(ARMRegisterClassStorage, BitSets[243]) - 22 * sizeof(MCRegisterClass),
1575 .NameIdx: 2352,
1576 .RegSizeInBits: 32,
1577 .RegsSize: 8,
1578 .RegSetSize: 11,
1579 .ID: ARM::tGPREvenRegClassID,
1580 .CopyCost: 1, /* CopyCost */
1581 .Allocatable: true, /* Allocatable */
1582 .BaseClass: false,
1583 offsetof(ARMRegisterClassStorage, SubClassMasks[710]) - 22 * sizeof(MCRegisterClass),
1584 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 22 * sizeof(MCRegisterClass),
1585 .LaneMask: LaneBitmask(0x0000000000000001),
1586 .AllocationPriority: 0,
1587 .GlobalPriority: false,
1588 .TSFlags: 0x00, /* TSFlags */
1589 .SpillStackID: 0, /* SpillStackID */
1590 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1591 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1592 offsetof(ARMRegisterClassStorage, SuperClasses[62]) - 22 * sizeof(MCRegisterClass),
1593 .SuperClassesSize: 9
1594 },
1595 {
1596 offsetof(ARMRegisterClassStorage, Regs[391]) - 23 * sizeof(MCRegisterClass),
1597 offsetof(ARMRegisterClassStorage, BitSets[254]) - 23 * sizeof(MCRegisterClass),
1598 .NameIdx: 1536,
1599 .RegSizeInBits: 32,
1600 .RegsSize: 7,
1601 .RegSetSize: 11,
1602 .ID: ARM::GPRnopc_and_hGPRRegClassID,
1603 .CopyCost: 1, /* CopyCost */
1604 .Allocatable: true, /* Allocatable */
1605 .BaseClass: false,
1606 offsetof(ARMRegisterClassStorage, SubClassMasks[720]) - 23 * sizeof(MCRegisterClass),
1607 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 23 * sizeof(MCRegisterClass),
1608 .LaneMask: LaneBitmask(0x0000000000000001),
1609 .AllocationPriority: 0,
1610 .GlobalPriority: false,
1611 .TSFlags: 0x00, /* TSFlags */
1612 .SpillStackID: 0, /* SpillStackID */
1613 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1614 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1615 offsetof(ARMRegisterClassStorage, SuperClasses[71]) - 23 * sizeof(MCRegisterClass),
1616 .SuperClassesSize: 5
1617 },
1618 {
1619 offsetof(ARMRegisterClassStorage, Regs[398]) - 24 * sizeof(MCRegisterClass),
1620 offsetof(ARMRegisterClassStorage, BitSets[265]) - 24 * sizeof(MCRegisterClass),
1621 .NameIdx: 1623,
1622 .RegSizeInBits: 32,
1623 .RegsSize: 7,
1624 .RegSetSize: 11,
1625 .ID: ARM::GPRnosp_and_hGPRRegClassID,
1626 .CopyCost: 1, /* CopyCost */
1627 .Allocatable: true, /* Allocatable */
1628 .BaseClass: false,
1629 offsetof(ARMRegisterClassStorage, SubClassMasks[735]) - 24 * sizeof(MCRegisterClass),
1630 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 24 * sizeof(MCRegisterClass),
1631 .LaneMask: LaneBitmask(0x0000000000000001),
1632 .AllocationPriority: 0,
1633 .GlobalPriority: false,
1634 .TSFlags: 0x00, /* TSFlags */
1635 .SpillStackID: 0, /* SpillStackID */
1636 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1637 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1638 offsetof(ARMRegisterClassStorage, SuperClasses[76]) - 24 * sizeof(MCRegisterClass),
1639 .SuperClassesSize: 3
1640 },
1641 {
1642 offsetof(ARMRegisterClassStorage, Regs[405]) - 25 * sizeof(MCRegisterClass),
1643 offsetof(ARMRegisterClassStorage, BitSets[276]) - 25 * sizeof(MCRegisterClass),
1644 .NameIdx: 1577,
1645 .RegSizeInBits: 32,
1646 .RegsSize: 6,
1647 .RegSetSize: 11,
1648 .ID: ARM::GPRnoip_and_hGPRRegClassID,
1649 .CopyCost: 1, /* CopyCost */
1650 .Allocatable: true, /* Allocatable */
1651 .BaseClass: false,
1652 offsetof(ARMRegisterClassStorage, SubClassMasks[750]) - 25 * sizeof(MCRegisterClass),
1653 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 25 * sizeof(MCRegisterClass),
1654 .LaneMask: LaneBitmask(0x0000000000000001),
1655 .AllocationPriority: 0,
1656 .GlobalPriority: false,
1657 .TSFlags: 0x00, /* TSFlags */
1658 .SpillStackID: 0, /* SpillStackID */
1659 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1660 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1661 offsetof(ARMRegisterClassStorage, SuperClasses[79]) - 25 * sizeof(MCRegisterClass),
1662 .SuperClassesSize: 3
1663 },
1664 {
1665 offsetof(ARMRegisterClassStorage, Regs[411]) - 26 * sizeof(MCRegisterClass),
1666 offsetof(ARMRegisterClassStorage, BitSets[287]) - 26 * sizeof(MCRegisterClass),
1667 .NameIdx: 2388,
1668 .RegSizeInBits: 32,
1669 .RegsSize: 6,
1670 .RegSetSize: 11,
1671 .ID: ARM::GPRnoip_and_tGPREvenRegClassID,
1672 .CopyCost: 1, /* CopyCost */
1673 .Allocatable: true, /* Allocatable */
1674 .BaseClass: false,
1675 offsetof(ARMRegisterClassStorage, SubClassMasks[765]) - 26 * sizeof(MCRegisterClass),
1676 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 26 * sizeof(MCRegisterClass),
1677 .LaneMask: LaneBitmask(0x0000000000000001),
1678 .AllocationPriority: 0,
1679 .GlobalPriority: false,
1680 .TSFlags: 0x00, /* TSFlags */
1681 .SpillStackID: 0, /* SpillStackID */
1682 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1683 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1684 offsetof(ARMRegisterClassStorage, SuperClasses[82]) - 26 * sizeof(MCRegisterClass),
1685 .SuperClassesSize: 14
1686 },
1687 {
1688 offsetof(ARMRegisterClassStorage, Regs[417]) - 27 * sizeof(MCRegisterClass),
1689 offsetof(ARMRegisterClassStorage, BitSets[298]) - 27 * sizeof(MCRegisterClass),
1690 .NameIdx: 1524,
1691 .RegSizeInBits: 32,
1692 .RegsSize: 6,
1693 .RegSetSize: 11,
1694 .ID: ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID,
1695 .CopyCost: 1, /* CopyCost */
1696 .Allocatable: true, /* Allocatable */
1697 .BaseClass: false,
1698 offsetof(ARMRegisterClassStorage, SubClassMasks[775]) - 27 * sizeof(MCRegisterClass),
1699 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 27 * sizeof(MCRegisterClass),
1700 .LaneMask: LaneBitmask(0x0000000000000001),
1701 .AllocationPriority: 0,
1702 .GlobalPriority: false,
1703 .TSFlags: 0x00, /* TSFlags */
1704 .SpillStackID: 0, /* SpillStackID */
1705 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1706 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1707 offsetof(ARMRegisterClassStorage, SuperClasses[96]) - 27 * sizeof(MCRegisterClass),
1708 .SuperClassesSize: 12
1709 },
1710 {
1711 offsetof(ARMRegisterClassStorage, Regs[423]) - 28 * sizeof(MCRegisterClass),
1712 offsetof(ARMRegisterClassStorage, BitSets[309]) - 28 * sizeof(MCRegisterClass),
1713 .NameIdx: 2310,
1714 .RegSizeInBits: 32,
1715 .RegsSize: 6,
1716 .RegSetSize: 11,
1717 .ID: ARM::tGPROddRegClassID,
1718 .CopyCost: 1, /* CopyCost */
1719 .Allocatable: true, /* Allocatable */
1720 .BaseClass: false,
1721 offsetof(ARMRegisterClassStorage, SubClassMasks[790]) - 28 * sizeof(MCRegisterClass),
1722 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[12]) - 28 * sizeof(MCRegisterClass),
1723 .LaneMask: LaneBitmask(0x0000000000000001),
1724 .AllocationPriority: 0,
1725 .GlobalPriority: false,
1726 .TSFlags: 0x00, /* TSFlags */
1727 .SpillStackID: 0, /* SpillStackID */
1728 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1729 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1730 offsetof(ARMRegisterClassStorage, SuperClasses[108]) - 28 * sizeof(MCRegisterClass),
1731 .SuperClassesSize: 13
1732 },
1733 {
1734 offsetof(ARMRegisterClassStorage, Regs[429]) - 29 * sizeof(MCRegisterClass),
1735 offsetof(ARMRegisterClassStorage, BitSets[320]) - 29 * sizeof(MCRegisterClass),
1736 .NameIdx: 1565,
1737 .RegSizeInBits: 32,
1738 .RegsSize: 5,
1739 .RegSetSize: 11,
1740 .ID: ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID,
1741 .CopyCost: 1, /* CopyCost */
1742 .Allocatable: true, /* Allocatable */
1743 .BaseClass: false,
1744 offsetof(ARMRegisterClassStorage, SubClassMasks[800]) - 29 * sizeof(MCRegisterClass),
1745 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 29 * sizeof(MCRegisterClass),
1746 .LaneMask: LaneBitmask(0x0000000000000001),
1747 .AllocationPriority: 0,
1748 .GlobalPriority: false,
1749 .TSFlags: 0x00, /* TSFlags */
1750 .SpillStackID: 0, /* SpillStackID */
1751 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1752 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1753 offsetof(ARMRegisterClassStorage, SuperClasses[121]) - 29 * sizeof(MCRegisterClass),
1754 .SuperClassesSize: 9
1755 },
1756 {
1757 offsetof(ARMRegisterClassStorage, Regs[434]) - 30 * sizeof(MCRegisterClass),
1758 offsetof(ARMRegisterClassStorage, BitSets[331]) - 30 * sizeof(MCRegisterClass),
1759 .NameIdx: 1594,
1760 .RegSizeInBits: 32,
1761 .RegsSize: 5,
1762 .RegSetSize: 11,
1763 .ID: ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID,
1764 .CopyCost: 1, /* CopyCost */
1765 .Allocatable: true, /* Allocatable */
1766 .BaseClass: false,
1767 offsetof(ARMRegisterClassStorage, SubClassMasks[815]) - 30 * sizeof(MCRegisterClass),
1768 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 30 * sizeof(MCRegisterClass),
1769 .LaneMask: LaneBitmask(0x0000000000000001),
1770 .AllocationPriority: 0,
1771 .GlobalPriority: false,
1772 .TSFlags: 0x00, /* TSFlags */
1773 .SpillStackID: 0, /* SpillStackID */
1774 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1775 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1776 offsetof(ARMRegisterClassStorage, SuperClasses[130]) - 30 * sizeof(MCRegisterClass),
1777 .SuperClassesSize: 7
1778 },
1779 {
1780 offsetof(ARMRegisterClassStorage, Regs[439]) - 31 * sizeof(MCRegisterClass),
1781 offsetof(ARMRegisterClassStorage, BitSets[342]) - 31 * sizeof(MCRegisterClass),
1782 .NameIdx: 1452,
1783 .RegSizeInBits: 32,
1784 .RegsSize: 5,
1785 .RegSetSize: 11,
1786 .ID: ARM::tcGPRRegClassID,
1787 .CopyCost: 1, /* CopyCost */
1788 .Allocatable: true, /* Allocatable */
1789 .BaseClass: false,
1790 offsetof(ARMRegisterClassStorage, SubClassMasks[830]) - 31 * sizeof(MCRegisterClass),
1791 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 31 * sizeof(MCRegisterClass),
1792 .LaneMask: LaneBitmask(0x0000000000000001),
1793 .AllocationPriority: 0,
1794 .GlobalPriority: false,
1795 .TSFlags: 0x00, /* TSFlags */
1796 .SpillStackID: 0, /* SpillStackID */
1797 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1798 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1799 offsetof(ARMRegisterClassStorage, SuperClasses[137]) - 31 * sizeof(MCRegisterClass),
1800 .SuperClassesSize: 9
1801 },
1802 {
1803 offsetof(ARMRegisterClassStorage, Regs[444]) - 32 * sizeof(MCRegisterClass),
1804 offsetof(ARMRegisterClassStorage, BitSets[353]) - 32 * sizeof(MCRegisterClass),
1805 .NameIdx: 1553,
1806 .RegSizeInBits: 32,
1807 .RegsSize: 4,
1808 .RegSetSize: 11,
1809 .ID: ARM::GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID,
1810 .CopyCost: 1, /* CopyCost */
1811 .Allocatable: true, /* Allocatable */
1812 .BaseClass: false,
1813 offsetof(ARMRegisterClassStorage, SubClassMasks[845]) - 32 * sizeof(MCRegisterClass),
1814 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 32 * sizeof(MCRegisterClass),
1815 .LaneMask: LaneBitmask(0x0000000000000001),
1816 .AllocationPriority: 0,
1817 .GlobalPriority: false,
1818 .TSFlags: 0x00, /* TSFlags */
1819 .SpillStackID: 0, /* SpillStackID */
1820 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1821 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1822 offsetof(ARMRegisterClassStorage, SuperClasses[146]) - 32 * sizeof(MCRegisterClass),
1823 .SuperClassesSize: 20
1824 },
1825 {
1826 offsetof(ARMRegisterClassStorage, Regs[448]) - 33 * sizeof(MCRegisterClass),
1827 offsetof(ARMRegisterClassStorage, BitSets[364]) - 33 * sizeof(MCRegisterClass),
1828 .NameIdx: 2343,
1829 .RegSizeInBits: 32,
1830 .RegsSize: 4,
1831 .RegSetSize: 11,
1832 .ID: ARM::hGPR_and_tGPREvenRegClassID,
1833 .CopyCost: 1, /* CopyCost */
1834 .Allocatable: true, /* Allocatable */
1835 .BaseClass: false,
1836 offsetof(ARMRegisterClassStorage, SubClassMasks[860]) - 33 * sizeof(MCRegisterClass),
1837 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 33 * sizeof(MCRegisterClass),
1838 .LaneMask: LaneBitmask(0x0000000000000001),
1839 .AllocationPriority: 0,
1840 .GlobalPriority: false,
1841 .TSFlags: 0x00, /* TSFlags */
1842 .SpillStackID: 0, /* SpillStackID */
1843 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1844 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1845 offsetof(ARMRegisterClassStorage, SuperClasses[166]) - 33 * sizeof(MCRegisterClass),
1846 .SuperClassesSize: 14
1847 },
1848 {
1849 offsetof(ARMRegisterClassStorage, Regs[452]) - 34 * sizeof(MCRegisterClass),
1850 offsetof(ARMRegisterClassStorage, BitSets[375]) - 34 * sizeof(MCRegisterClass),
1851 .NameIdx: 2361,
1852 .RegSizeInBits: 32,
1853 .RegsSize: 4,
1854 .RegSetSize: 11,
1855 .ID: ARM::tGPR_and_tGPREvenRegClassID,
1856 .CopyCost: 1, /* CopyCost */
1857 .Allocatable: true, /* Allocatable */
1858 .BaseClass: false,
1859 offsetof(ARMRegisterClassStorage, SubClassMasks[870]) - 34 * sizeof(MCRegisterClass),
1860 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 34 * sizeof(MCRegisterClass),
1861 .LaneMask: LaneBitmask(0x0000000000000001),
1862 .AllocationPriority: 0,
1863 .GlobalPriority: false,
1864 .TSFlags: 0x00, /* TSFlags */
1865 .SpillStackID: 0, /* SpillStackID */
1866 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1867 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1868 offsetof(ARMRegisterClassStorage, SuperClasses[180]) - 34 * sizeof(MCRegisterClass),
1869 .SuperClassesSize: 17
1870 },
1871 {
1872 offsetof(ARMRegisterClassStorage, Regs[456]) - 35 * sizeof(MCRegisterClass),
1873 offsetof(ARMRegisterClassStorage, BitSets[386]) - 35 * sizeof(MCRegisterClass),
1874 .NameIdx: 2318,
1875 .RegSizeInBits: 32,
1876 .RegsSize: 4,
1877 .RegSetSize: 11,
1878 .ID: ARM::tGPR_and_tGPROddRegClassID,
1879 .CopyCost: 1, /* CopyCost */
1880 .Allocatable: true, /* Allocatable */
1881 .BaseClass: false,
1882 offsetof(ARMRegisterClassStorage, SubClassMasks[880]) - 35 * sizeof(MCRegisterClass),
1883 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[12]) - 35 * sizeof(MCRegisterClass),
1884 .LaneMask: LaneBitmask(0x0000000000000001),
1885 .AllocationPriority: 0,
1886 .GlobalPriority: false,
1887 .TSFlags: 0x00, /* TSFlags */
1888 .SpillStackID: 0, /* SpillStackID */
1889 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1890 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1891 offsetof(ARMRegisterClassStorage, SuperClasses[197]) - 35 * sizeof(MCRegisterClass),
1892 .SuperClassesSize: 16
1893 },
1894 {
1895 offsetof(ARMRegisterClassStorage, Regs[460]) - 36 * sizeof(MCRegisterClass),
1896 offsetof(ARMRegisterClassStorage, BitSets[397]) - 36 * sizeof(MCRegisterClass),
1897 .NameIdx: 175,
1898 .RegSizeInBits: 32,
1899 .RegsSize: 4,
1900 .RegSetSize: 10,
1901 .ID: ARM::tcGPRnotr12RegClassID,
1902 .CopyCost: 1, /* CopyCost */
1903 .Allocatable: true, /* Allocatable */
1904 .BaseClass: false,
1905 offsetof(ARMRegisterClassStorage, SubClassMasks[890]) - 36 * sizeof(MCRegisterClass),
1906 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 36 * sizeof(MCRegisterClass),
1907 .LaneMask: LaneBitmask(0x0000000000000001),
1908 .AllocationPriority: 0,
1909 .GlobalPriority: false,
1910 .TSFlags: 0x00, /* TSFlags */
1911 .SpillStackID: 0, /* SpillStackID */
1912 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1913 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1914 offsetof(ARMRegisterClassStorage, SuperClasses[213]) - 36 * sizeof(MCRegisterClass),
1915 .SuperClassesSize: 16
1916 },
1917 {
1918 offsetof(ARMRegisterClassStorage, Regs[464]) - 37 * sizeof(MCRegisterClass),
1919 offsetof(ARMRegisterClassStorage, BitSets[407]) - 37 * sizeof(MCRegisterClass),
1920 .NameIdx: 1476,
1921 .RegSizeInBits: 32,
1922 .RegsSize: 3,
1923 .RegSetSize: 11,
1924 .ID: ARM::tGPREven_and_tcGPRRegClassID,
1925 .CopyCost: 1, /* CopyCost */
1926 .Allocatable: true, /* Allocatable */
1927 .BaseClass: false,
1928 offsetof(ARMRegisterClassStorage, SubClassMasks[905]) - 37 * sizeof(MCRegisterClass),
1929 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 37 * sizeof(MCRegisterClass),
1930 .LaneMask: LaneBitmask(0x0000000000000001),
1931 .AllocationPriority: 0,
1932 .GlobalPriority: false,
1933 .TSFlags: 0x00, /* TSFlags */
1934 .SpillStackID: 0, /* SpillStackID */
1935 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1936 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1937 offsetof(ARMRegisterClassStorage, SuperClasses[229]) - 37 * sizeof(MCRegisterClass),
1938 .SuperClassesSize: 11
1939 },
1940 {
1941 offsetof(ARMRegisterClassStorage, Regs[467]) - 38 * sizeof(MCRegisterClass),
1942 offsetof(ARMRegisterClassStorage, BitSets[418]) - 38 * sizeof(MCRegisterClass),
1943 .NameIdx: 2197,
1944 .RegSizeInBits: 32,
1945 .RegsSize: 2,
1946 .RegSetSize: 2,
1947 .ID: ARM::FP_STATUS_REGSRegClassID,
1948 .CopyCost: 255, /* CopyCost */
1949 .Allocatable: false, /* Allocatable */
1950 .BaseClass: false,
1951 offsetof(ARMRegisterClassStorage, SubClassMasks[915]) - 38 * sizeof(MCRegisterClass),
1952 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 38 * sizeof(MCRegisterClass),
1953 .LaneMask: LaneBitmask(0x0000000000000001),
1954 .AllocationPriority: 0,
1955 .GlobalPriority: false,
1956 .TSFlags: 0x00, /* TSFlags */
1957 .SpillStackID: 0, /* SpillStackID */
1958 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1959 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1960 offsetof(ARMRegisterClassStorage, SuperClasses[240]) - 38 * sizeof(MCRegisterClass),
1961 .SuperClassesSize: 0
1962 },
1963 {
1964 offsetof(ARMRegisterClassStorage, Regs[469]) - 39 * sizeof(MCRegisterClass),
1965 offsetof(ARMRegisterClassStorage, BitSets[420]) - 39 * sizeof(MCRegisterClass),
1966 .NameIdx: 2379,
1967 .RegSizeInBits: 32,
1968 .RegsSize: 2,
1969 .RegSetSize: 11,
1970 .ID: ARM::hGPR_and_GPRnoip_and_tGPREvenRegClassID,
1971 .CopyCost: 1, /* CopyCost */
1972 .Allocatable: true, /* Allocatable */
1973 .BaseClass: false,
1974 offsetof(ARMRegisterClassStorage, SubClassMasks[920]) - 39 * sizeof(MCRegisterClass),
1975 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 39 * sizeof(MCRegisterClass),
1976 .LaneMask: LaneBitmask(0x0000000000000001),
1977 .AllocationPriority: 0,
1978 .GlobalPriority: false,
1979 .TSFlags: 0x00, /* TSFlags */
1980 .SpillStackID: 0, /* SpillStackID */
1981 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1982 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1983 offsetof(ARMRegisterClassStorage, SuperClasses[240]) - 39 * sizeof(MCRegisterClass),
1984 .SuperClassesSize: 24
1985 },
1986 {
1987 offsetof(ARMRegisterClassStorage, Regs[471]) - 40 * sizeof(MCRegisterClass),
1988 offsetof(ARMRegisterClassStorage, BitSets[431]) - 40 * sizeof(MCRegisterClass),
1989 .NameIdx: 2301,
1990 .RegSizeInBits: 32,
1991 .RegsSize: 2,
1992 .RegSetSize: 11,
1993 .ID: ARM::hGPR_and_tGPROddRegClassID,
1994 .CopyCost: 1, /* CopyCost */
1995 .Allocatable: true, /* Allocatable */
1996 .BaseClass: false,
1997 offsetof(ARMRegisterClassStorage, SubClassMasks[930]) - 40 * sizeof(MCRegisterClass),
1998 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[12]) - 40 * sizeof(MCRegisterClass),
1999 .LaneMask: LaneBitmask(0x0000000000000001),
2000 .AllocationPriority: 0,
2001 .GlobalPriority: false,
2002 .TSFlags: 0x00, /* TSFlags */
2003 .SpillStackID: 0, /* SpillStackID */
2004 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2005 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2006 offsetof(ARMRegisterClassStorage, SuperClasses[264]) - 40 * sizeof(MCRegisterClass),
2007 .SuperClassesSize: 22
2008 },
2009 {
2010 offsetof(ARMRegisterClassStorage, Regs[473]) - 41 * sizeof(MCRegisterClass),
2011 offsetof(ARMRegisterClassStorage, BitSets[442]) - 41 * sizeof(MCRegisterClass),
2012 .NameIdx: 162,
2013 .RegSizeInBits: 32,
2014 .RegsSize: 2,
2015 .RegSetSize: 10,
2016 .ID: ARM::tGPREven_and_tcGPRnotr12RegClassID,
2017 .CopyCost: 1, /* CopyCost */
2018 .Allocatable: true, /* Allocatable */
2019 .BaseClass: false,
2020 offsetof(ARMRegisterClassStorage, SubClassMasks[940]) - 41 * sizeof(MCRegisterClass),
2021 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 41 * sizeof(MCRegisterClass),
2022 .LaneMask: LaneBitmask(0x0000000000000001),
2023 .AllocationPriority: 0,
2024 .GlobalPriority: false,
2025 .TSFlags: 0x00, /* TSFlags */
2026 .SpillStackID: 0, /* SpillStackID */
2027 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2028 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2029 offsetof(ARMRegisterClassStorage, SuperClasses[286]) - 41 * sizeof(MCRegisterClass),
2030 .SuperClassesSize: 21
2031 },
2032 {
2033 offsetof(ARMRegisterClassStorage, Regs[475]) - 42 * sizeof(MCRegisterClass),
2034 offsetof(ARMRegisterClassStorage, BitSets[452]) - 42 * sizeof(MCRegisterClass),
2035 .NameIdx: 1458,
2036 .RegSizeInBits: 32,
2037 .RegsSize: 2,
2038 .RegSetSize: 10,
2039 .ID: ARM::tGPROdd_and_tcGPRRegClassID,
2040 .CopyCost: 1, /* CopyCost */
2041 .Allocatable: true, /* Allocatable */
2042 .BaseClass: false,
2043 offsetof(ARMRegisterClassStorage, SubClassMasks[950]) - 42 * sizeof(MCRegisterClass),
2044 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[12]) - 42 * sizeof(MCRegisterClass),
2045 .LaneMask: LaneBitmask(0x0000000000000001),
2046 .AllocationPriority: 0,
2047 .GlobalPriority: false,
2048 .TSFlags: 0x00, /* TSFlags */
2049 .SpillStackID: 0, /* SpillStackID */
2050 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2051 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2052 offsetof(ARMRegisterClassStorage, SuperClasses[307]) - 42 * sizeof(MCRegisterClass),
2053 .SuperClassesSize: 19
2054 },
2055 {
2056 offsetof(ARMRegisterClassStorage, Regs[477]) - 43 * sizeof(MCRegisterClass),
2057 offsetof(ARMRegisterClassStorage, BitSets[462]) - 43 * sizeof(MCRegisterClass),
2058 .NameIdx: 1435,
2059 .RegSizeInBits: 32,
2060 .RegsSize: 1,
2061 .RegSetSize: 1,
2062 .ID: ARM::CCRRegClassID,
2063 .CopyCost: 255, /* CopyCost */
2064 .Allocatable: false, /* Allocatable */
2065 .BaseClass: false,
2066 offsetof(ARMRegisterClassStorage, SubClassMasks[960]) - 43 * sizeof(MCRegisterClass),
2067 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 43 * sizeof(MCRegisterClass),
2068 .LaneMask: LaneBitmask(0x0000000000000001),
2069 .AllocationPriority: 0,
2070 .GlobalPriority: false,
2071 .TSFlags: 0x00, /* TSFlags */
2072 .SpillStackID: 0, /* SpillStackID */
2073 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2074 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2075 offsetof(ARMRegisterClassStorage, SuperClasses[326]) - 43 * sizeof(MCRegisterClass),
2076 .SuperClassesSize: 0
2077 },
2078 {
2079 offsetof(ARMRegisterClassStorage, Regs[478]) - 44 * sizeof(MCRegisterClass),
2080 offsetof(ARMRegisterClassStorage, BitSets[463]) - 44 * sizeof(MCRegisterClass),
2081 .NameIdx: 2561,
2082 .RegSizeInBits: 32,
2083 .RegsSize: 1,
2084 .RegSetSize: 1,
2085 .ID: ARM::FPCXTRegsRegClassID,
2086 .CopyCost: 1, /* CopyCost */
2087 .Allocatable: true, /* Allocatable */
2088 .BaseClass: false,
2089 offsetof(ARMRegisterClassStorage, SubClassMasks[965]) - 44 * sizeof(MCRegisterClass),
2090 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 44 * sizeof(MCRegisterClass),
2091 .LaneMask: LaneBitmask(0x0000000000000001),
2092 .AllocationPriority: 0,
2093 .GlobalPriority: false,
2094 .TSFlags: 0x00, /* TSFlags */
2095 .SpillStackID: 0, /* SpillStackID */
2096 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2097 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2098 offsetof(ARMRegisterClassStorage, SuperClasses[326]) - 44 * sizeof(MCRegisterClass),
2099 .SuperClassesSize: 0
2100 },
2101 {
2102 offsetof(ARMRegisterClassStorage, Regs[479]) - 45 * sizeof(MCRegisterClass),
2103 offsetof(ARMRegisterClassStorage, BitSets[464]) - 45 * sizeof(MCRegisterClass),
2104 .NameIdx: 2555,
2105 .RegSizeInBits: 32,
2106 .RegsSize: 1,
2107 .RegSetSize: 2,
2108 .ID: ARM::GPRlrRegClassID,
2109 .CopyCost: 1, /* CopyCost */
2110 .Allocatable: true, /* Allocatable */
2111 .BaseClass: false,
2112 offsetof(ARMRegisterClassStorage, SubClassMasks[970]) - 45 * sizeof(MCRegisterClass),
2113 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 45 * sizeof(MCRegisterClass),
2114 .LaneMask: LaneBitmask(0x0000000000000001),
2115 .AllocationPriority: 0,
2116 .GlobalPriority: false,
2117 .TSFlags: 0x00, /* TSFlags */
2118 .SpillStackID: 0, /* SpillStackID */
2119 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2120 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2121 offsetof(ARMRegisterClassStorage, SuperClasses[326]) - 45 * sizeof(MCRegisterClass),
2122 .SuperClassesSize: 15
2123 },
2124 {
2125 offsetof(ARMRegisterClassStorage, Regs[480]) - 46 * sizeof(MCRegisterClass),
2126 offsetof(ARMRegisterClassStorage, BitSets[466]) - 46 * sizeof(MCRegisterClass),
2127 .NameIdx: 2440,
2128 .RegSizeInBits: 32,
2129 .RegsSize: 1,
2130 .RegSetSize: 3,
2131 .ID: ARM::GPRspRegClassID,
2132 .CopyCost: 1, /* CopyCost */
2133 .Allocatable: true, /* Allocatable */
2134 .BaseClass: false,
2135 offsetof(ARMRegisterClassStorage, SubClassMasks[975]) - 46 * sizeof(MCRegisterClass),
2136 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[12]) - 46 * sizeof(MCRegisterClass),
2137 .LaneMask: LaneBitmask(0x0000000000000001),
2138 .AllocationPriority: 0,
2139 .GlobalPriority: false,
2140 .TSFlags: 0x00, /* TSFlags */
2141 .SpillStackID: 0, /* SpillStackID */
2142 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2143 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2144 offsetof(ARMRegisterClassStorage, SuperClasses[341]) - 46 * sizeof(MCRegisterClass),
2145 .SuperClassesSize: 10
2146 },
2147 {
2148 offsetof(ARMRegisterClassStorage, Regs[481]) - 47 * sizeof(MCRegisterClass),
2149 offsetof(ARMRegisterClassStorage, BitSets[469]) - 47 * sizeof(MCRegisterClass),
2150 .NameIdx: 1434,
2151 .RegSizeInBits: 32,
2152 .RegsSize: 1,
2153 .RegSetSize: 3,
2154 .ID: ARM::VCCRRegClassID,
2155 .CopyCost: 1, /* CopyCost */
2156 .Allocatable: true, /* Allocatable */
2157 .BaseClass: false,
2158 offsetof(ARMRegisterClassStorage, SubClassMasks[985]) - 47 * sizeof(MCRegisterClass),
2159 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 47 * sizeof(MCRegisterClass),
2160 .LaneMask: LaneBitmask(0x0000000000000001),
2161 .AllocationPriority: 0,
2162 .GlobalPriority: false,
2163 .TSFlags: 0x00, /* TSFlags */
2164 .SpillStackID: 0, /* SpillStackID */
2165 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2166 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2167 offsetof(ARMRegisterClassStorage, SuperClasses[351]) - 47 * sizeof(MCRegisterClass),
2168 .SuperClassesSize: 1
2169 },
2170 {
2171 offsetof(ARMRegisterClassStorage, Regs[482]) - 48 * sizeof(MCRegisterClass),
2172 offsetof(ARMRegisterClassStorage, BitSets[472]) - 48 * sizeof(MCRegisterClass),
2173 .NameIdx: 2212,
2174 .RegSizeInBits: 32,
2175 .RegsSize: 1,
2176 .RegSetSize: 2,
2177 .ID: ARM::cl_FPSCR_NZCVRegClassID,
2178 .CopyCost: 255, /* CopyCost */
2179 .Allocatable: true, /* Allocatable */
2180 .BaseClass: false,
2181 offsetof(ARMRegisterClassStorage, SubClassMasks[990]) - 48 * sizeof(MCRegisterClass),
2182 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 48 * sizeof(MCRegisterClass),
2183 .LaneMask: LaneBitmask(0x0000000000000001),
2184 .AllocationPriority: 0,
2185 .GlobalPriority: false,
2186 .TSFlags: 0x00, /* TSFlags */
2187 .SpillStackID: 0, /* SpillStackID */
2188 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2189 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2190 offsetof(ARMRegisterClassStorage, SuperClasses[352]) - 48 * sizeof(MCRegisterClass),
2191 .SuperClassesSize: 0
2192 },
2193 {
2194 offsetof(ARMRegisterClassStorage, Regs[483]) - 49 * sizeof(MCRegisterClass),
2195 offsetof(ARMRegisterClassStorage, BitSets[474]) - 49 * sizeof(MCRegisterClass),
2196 .NameIdx: 2255,
2197 .RegSizeInBits: 32,
2198 .RegsSize: 1,
2199 .RegSetSize: 2,
2200 .ID: ARM::hGPR_and_tGPRwithpcRegClassID,
2201 .CopyCost: 1, /* CopyCost */
2202 .Allocatable: true, /* Allocatable */
2203 .BaseClass: false,
2204 offsetof(ARMRegisterClassStorage, SubClassMasks[995]) - 49 * sizeof(MCRegisterClass),
2205 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 49 * sizeof(MCRegisterClass),
2206 .LaneMask: LaneBitmask(0x0000000000000001),
2207 .AllocationPriority: 0,
2208 .GlobalPriority: false,
2209 .TSFlags: 0x00, /* TSFlags */
2210 .SpillStackID: 0, /* SpillStackID */
2211 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2212 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2213 offsetof(ARMRegisterClassStorage, SuperClasses[352]) - 49 * sizeof(MCRegisterClass),
2214 .SuperClassesSize: 9
2215 },
2216 {
2217 offsetof(ARMRegisterClassStorage, Regs[484]) - 50 * sizeof(MCRegisterClass),
2218 offsetof(ARMRegisterClassStorage, BitSets[476]) - 50 * sizeof(MCRegisterClass),
2219 .NameIdx: 1443,
2220 .RegSizeInBits: 32,
2221 .RegsSize: 1,
2222 .RegSetSize: 11,
2223 .ID: ARM::hGPR_and_tcGPRRegClassID,
2224 .CopyCost: 1, /* CopyCost */
2225 .Allocatable: true, /* Allocatable */
2226 .BaseClass: false,
2227 offsetof(ARMRegisterClassStorage, SubClassMasks[1000]) - 50 * sizeof(MCRegisterClass),
2228 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 50 * sizeof(MCRegisterClass),
2229 .LaneMask: LaneBitmask(0x0000000000000001),
2230 .AllocationPriority: 0,
2231 .GlobalPriority: false,
2232 .TSFlags: 0x00, /* TSFlags */
2233 .SpillStackID: 0, /* SpillStackID */
2234 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2235 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2236 offsetof(ARMRegisterClassStorage, SuperClasses[361]) - 50 * sizeof(MCRegisterClass),
2237 .SuperClassesSize: 17
2238 },
2239 {
2240 offsetof(ARMRegisterClassStorage, Regs[485]) - 51 * sizeof(MCRegisterClass),
2241 offsetof(ARMRegisterClassStorage, BitSets[487]) - 51 * sizeof(MCRegisterClass),
2242 .NameIdx: 1439,
2243 .RegSizeInBits: 64,
2244 .RegsSize: 32,
2245 .RegSetSize: 7,
2246 .ID: ARM::DPRRegClassID,
2247 .CopyCost: 1, /* CopyCost */
2248 .Allocatable: true, /* Allocatable */
2249 .BaseClass: false,
2250 offsetof(ARMRegisterClassStorage, SubClassMasks[1010]) - 51 * sizeof(MCRegisterClass),
2251 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[0]) - 51 * sizeof(MCRegisterClass),
2252 .LaneMask: LaneBitmask(0x000000000000000C),
2253 .AllocationPriority: 0,
2254 .GlobalPriority: false,
2255 .TSFlags: 0x00, /* TSFlags */
2256 .SpillStackID: 0, /* SpillStackID */
2257 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2258 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2259 offsetof(ARMRegisterClassStorage, SuperClasses[378]) - 51 * sizeof(MCRegisterClass),
2260 .SuperClassesSize: 1
2261 },
2262 {
2263 offsetof(ARMRegisterClassStorage, Regs[517]) - 52 * sizeof(MCRegisterClass),
2264 offsetof(ARMRegisterClassStorage, BitSets[494]) - 52 * sizeof(MCRegisterClass),
2265 .NameIdx: 222,
2266 .RegSizeInBits: 64,
2267 .RegsSize: 16,
2268 .RegSetSize: 5,
2269 .ID: ARM::DPR_VFP2RegClassID,
2270 .CopyCost: 1, /* CopyCost */
2271 .Allocatable: true, /* Allocatable */
2272 .BaseClass: false,
2273 offsetof(ARMRegisterClassStorage, SubClassMasks[1055]) - 52 * sizeof(MCRegisterClass),
2274 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[0]) - 52 * sizeof(MCRegisterClass),
2275 .LaneMask: LaneBitmask(0x000000000000000C),
2276 .AllocationPriority: 0,
2277 .GlobalPriority: false,
2278 .TSFlags: 0x00, /* TSFlags */
2279 .SpillStackID: 0, /* SpillStackID */
2280 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2281 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2282 offsetof(ARMRegisterClassStorage, SuperClasses[379]) - 52 * sizeof(MCRegisterClass),
2283 .SuperClassesSize: 3
2284 },
2285 {
2286 offsetof(ARMRegisterClassStorage, Regs[533]) - 53 * sizeof(MCRegisterClass),
2287 offsetof(ARMRegisterClassStorage, BitSets[499]) - 53 * sizeof(MCRegisterClass),
2288 .NameIdx: 460,
2289 .RegSizeInBits: 64,
2290 .RegsSize: 8,
2291 .RegSetSize: 4,
2292 .ID: ARM::DPR_8RegClassID,
2293 .CopyCost: 1, /* CopyCost */
2294 .Allocatable: true, /* Allocatable */
2295 .BaseClass: false,
2296 offsetof(ARMRegisterClassStorage, SubClassMasks[1100]) - 53 * sizeof(MCRegisterClass),
2297 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[0]) - 53 * sizeof(MCRegisterClass),
2298 .LaneMask: LaneBitmask(0x000000000000000C),
2299 .AllocationPriority: 0,
2300 .GlobalPriority: false,
2301 .TSFlags: 0x00, /* TSFlags */
2302 .SpillStackID: 0, /* SpillStackID */
2303 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2304 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2305 offsetof(ARMRegisterClassStorage, SuperClasses[382]) - 53 * sizeof(MCRegisterClass),
2306 .SuperClassesSize: 5
2307 },
2308 {
2309 offsetof(ARMRegisterClassStorage, Regs[541]) - 54 * sizeof(MCRegisterClass),
2310 offsetof(ARMRegisterClassStorage, BitSets[503]) - 54 * sizeof(MCRegisterClass),
2311 .NameIdx: 2547,
2312 .RegSizeInBits: 64,
2313 .RegsSize: 7,
2314 .RegSetSize: 23,
2315 .ID: ARM::GPRPairRegClassID,
2316 .CopyCost: 1, /* CopyCost */
2317 .Allocatable: true, /* Allocatable */
2318 .BaseClass: false,
2319 offsetof(ARMRegisterClassStorage, SubClassMasks[1145]) - 54 * sizeof(MCRegisterClass),
2320 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 54 * sizeof(MCRegisterClass),
2321 .LaneMask: LaneBitmask(0x0000000000000003),
2322 .AllocationPriority: 0,
2323 .GlobalPriority: false,
2324 .TSFlags: 0x00, /* TSFlags */
2325 .SpillStackID: 0, /* SpillStackID */
2326 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2327 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2328 offsetof(ARMRegisterClassStorage, SuperClasses[387]) - 54 * sizeof(MCRegisterClass),
2329 .SuperClassesSize: 0
2330 },
2331 {
2332 offsetof(ARMRegisterClassStorage, Regs[548]) - 55 * sizeof(MCRegisterClass),
2333 offsetof(ARMRegisterClassStorage, BitSets[526]) - 55 * sizeof(MCRegisterClass),
2334 .NameIdx: 2529,
2335 .RegSizeInBits: 64,
2336 .RegsSize: 6,
2337 .RegSetSize: 23,
2338 .ID: ARM::GPRPairnospRegClassID,
2339 .CopyCost: 1, /* CopyCost */
2340 .Allocatable: true, /* Allocatable */
2341 .BaseClass: false,
2342 offsetof(ARMRegisterClassStorage, SubClassMasks[1150]) - 55 * sizeof(MCRegisterClass),
2343 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 55 * sizeof(MCRegisterClass),
2344 .LaneMask: LaneBitmask(0x0000000000000003),
2345 .AllocationPriority: 0,
2346 .GlobalPriority: false,
2347 .TSFlags: 0x00, /* TSFlags */
2348 .SpillStackID: 0, /* SpillStackID */
2349 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2350 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2351 offsetof(ARMRegisterClassStorage, SuperClasses[387]) - 55 * sizeof(MCRegisterClass),
2352 .SuperClassesSize: 1
2353 },
2354 {
2355 offsetof(ARMRegisterClassStorage, Regs[554]) - 56 * sizeof(MCRegisterClass),
2356 offsetof(ARMRegisterClassStorage, BitSets[549]) - 56 * sizeof(MCRegisterClass),
2357 .NameIdx: 1689,
2358 .RegSizeInBits: 64,
2359 .RegsSize: 4,
2360 .RegSetSize: 23,
2361 .ID: ARM::GPRPair_with_gsub_0_in_tGPRRegClassID,
2362 .CopyCost: 1, /* CopyCost */
2363 .Allocatable: true, /* Allocatable */
2364 .BaseClass: false,
2365 offsetof(ARMRegisterClassStorage, SubClassMasks[1155]) - 56 * sizeof(MCRegisterClass),
2366 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 56 * sizeof(MCRegisterClass),
2367 .LaneMask: LaneBitmask(0x0000000000000003),
2368 .AllocationPriority: 0,
2369 .GlobalPriority: false,
2370 .TSFlags: 0x00, /* TSFlags */
2371 .SpillStackID: 0, /* SpillStackID */
2372 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2373 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2374 offsetof(ARMRegisterClassStorage, SuperClasses[388]) - 56 * sizeof(MCRegisterClass),
2375 .SuperClassesSize: 2
2376 },
2377 {
2378 offsetof(ARMRegisterClassStorage, Regs[558]) - 57 * sizeof(MCRegisterClass),
2379 offsetof(ARMRegisterClassStorage, BitSets[572]) - 57 * sizeof(MCRegisterClass),
2380 .NameIdx: 1656,
2381 .RegSizeInBits: 64,
2382 .RegsSize: 3,
2383 .RegSetSize: 23,
2384 .ID: ARM::GPRPair_with_gsub_0_in_hGPRRegClassID,
2385 .CopyCost: 1, /* CopyCost */
2386 .Allocatable: true, /* Allocatable */
2387 .BaseClass: false,
2388 offsetof(ARMRegisterClassStorage, SubClassMasks[1160]) - 57 * sizeof(MCRegisterClass),
2389 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 57 * sizeof(MCRegisterClass),
2390 .LaneMask: LaneBitmask(0x0000000000000003),
2391 .AllocationPriority: 0,
2392 .GlobalPriority: false,
2393 .TSFlags: 0x00, /* TSFlags */
2394 .SpillStackID: 0, /* SpillStackID */
2395 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2396 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2397 offsetof(ARMRegisterClassStorage, SuperClasses[390]) - 57 * sizeof(MCRegisterClass),
2398 .SuperClassesSize: 1
2399 },
2400 {
2401 offsetof(ARMRegisterClassStorage, Regs[561]) - 58 * sizeof(MCRegisterClass),
2402 offsetof(ARMRegisterClassStorage, BitSets[595]) - 58 * sizeof(MCRegisterClass),
2403 .NameIdx: 1495,
2404 .RegSizeInBits: 64,
2405 .RegsSize: 3,
2406 .RegSetSize: 23,
2407 .ID: ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID,
2408 .CopyCost: 1, /* CopyCost */
2409 .Allocatable: true, /* Allocatable */
2410 .BaseClass: false,
2411 offsetof(ARMRegisterClassStorage, SubClassMasks[1165]) - 58 * sizeof(MCRegisterClass),
2412 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 58 * sizeof(MCRegisterClass),
2413 .LaneMask: LaneBitmask(0x0000000000000003),
2414 .AllocationPriority: 0,
2415 .GlobalPriority: false,
2416 .TSFlags: 0x00, /* TSFlags */
2417 .SpillStackID: 0, /* SpillStackID */
2418 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2419 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2420 offsetof(ARMRegisterClassStorage, SuperClasses[391]) - 58 * sizeof(MCRegisterClass),
2421 .SuperClassesSize: 1
2422 },
2423 {
2424 offsetof(ARMRegisterClassStorage, Regs[564]) - 59 * sizeof(MCRegisterClass),
2425 offsetof(ARMRegisterClassStorage, BitSets[618]) - 59 * sizeof(MCRegisterClass),
2426 .NameIdx: 187,
2427 .RegSizeInBits: 64,
2428 .RegsSize: 2,
2429 .RegSetSize: 23,
2430 .ID: ARM::GPRPair_with_gsub_0_in_tcGPRnotr12RegClassID,
2431 .CopyCost: 1, /* CopyCost */
2432 .Allocatable: true, /* Allocatable */
2433 .BaseClass: false,
2434 offsetof(ARMRegisterClassStorage, SubClassMasks[1170]) - 59 * sizeof(MCRegisterClass),
2435 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 59 * sizeof(MCRegisterClass),
2436 .LaneMask: LaneBitmask(0x0000000000000003),
2437 .AllocationPriority: 0,
2438 .GlobalPriority: false,
2439 .TSFlags: 0x00, /* TSFlags */
2440 .SpillStackID: 0, /* SpillStackID */
2441 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2442 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2443 offsetof(ARMRegisterClassStorage, SuperClasses[392]) - 59 * sizeof(MCRegisterClass),
2444 .SuperClassesSize: 4
2445 },
2446 {
2447 offsetof(ARMRegisterClassStorage, Regs[566]) - 60 * sizeof(MCRegisterClass),
2448 offsetof(ARMRegisterClassStorage, BitSets[641]) - 60 * sizeof(MCRegisterClass),
2449 .NameIdx: 1640,
2450 .RegSizeInBits: 64,
2451 .RegsSize: 2,
2452 .RegSetSize: 23,
2453 .ID: ARM::GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID,
2454 .CopyCost: 1, /* CopyCost */
2455 .Allocatable: true, /* Allocatable */
2456 .BaseClass: false,
2457 offsetof(ARMRegisterClassStorage, SubClassMasks[1175]) - 60 * sizeof(MCRegisterClass),
2458 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 60 * sizeof(MCRegisterClass),
2459 .LaneMask: LaneBitmask(0x0000000000000003),
2460 .AllocationPriority: 0,
2461 .GlobalPriority: false,
2462 .TSFlags: 0x00, /* TSFlags */
2463 .SpillStackID: 0, /* SpillStackID */
2464 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2465 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2466 offsetof(ARMRegisterClassStorage, SuperClasses[396]) - 60 * sizeof(MCRegisterClass),
2467 .SuperClassesSize: 3
2468 },
2469 {
2470 offsetof(ARMRegisterClassStorage, Regs[568]) - 61 * sizeof(MCRegisterClass),
2471 offsetof(ARMRegisterClassStorage, BitSets[664]) - 61 * sizeof(MCRegisterClass),
2472 .NameIdx: 2417,
2473 .RegSizeInBits: 64,
2474 .RegsSize: 1,
2475 .RegSetSize: 23,
2476 .ID: ARM::GPRPair_with_gsub_1_in_GPRspRegClassID,
2477 .CopyCost: 1, /* CopyCost */
2478 .Allocatable: true, /* Allocatable */
2479 .BaseClass: false,
2480 offsetof(ARMRegisterClassStorage, SubClassMasks[1180]) - 61 * sizeof(MCRegisterClass),
2481 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 61 * sizeof(MCRegisterClass),
2482 .LaneMask: LaneBitmask(0x0000000000000003),
2483 .AllocationPriority: 0,
2484 .GlobalPriority: false,
2485 .TSFlags: 0x00, /* TSFlags */
2486 .SpillStackID: 0, /* SpillStackID */
2487 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2488 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2489 offsetof(ARMRegisterClassStorage, SuperClasses[399]) - 61 * sizeof(MCRegisterClass),
2490 .SuperClassesSize: 3
2491 },
2492 {
2493 offsetof(ARMRegisterClassStorage, Regs[569]) - 62 * sizeof(MCRegisterClass),
2494 offsetof(ARMRegisterClassStorage, BitSets[687]) - 62 * sizeof(MCRegisterClass),
2495 .NameIdx: 2246,
2496 .RegSizeInBits: 128,
2497 .RegsSize: 30,
2498 .RegSetSize: 19,
2499 .ID: ARM::DPairSpcRegClassID,
2500 .CopyCost: 1, /* CopyCost */
2501 .Allocatable: true, /* Allocatable */
2502 .BaseClass: false,
2503 offsetof(ARMRegisterClassStorage, SubClassMasks[1185]) - 62 * sizeof(MCRegisterClass),
2504 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[58]) - 62 * sizeof(MCRegisterClass),
2505 .LaneMask: LaneBitmask(0x00000000000000CC),
2506 .AllocationPriority: 0,
2507 .GlobalPriority: false,
2508 .TSFlags: 0x00, /* TSFlags */
2509 .SpillStackID: 0, /* SpillStackID */
2510 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2511 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2512 offsetof(ARMRegisterClassStorage, SuperClasses[402]) - 62 * sizeof(MCRegisterClass),
2513 .SuperClassesSize: 0
2514 },
2515 {
2516 offsetof(ARMRegisterClassStorage, Regs[599]) - 63 * sizeof(MCRegisterClass),
2517 offsetof(ARMRegisterClassStorage, BitSets[706]) - 63 * sizeof(MCRegisterClass),
2518 .NameIdx: 85,
2519 .RegSizeInBits: 128,
2520 .RegsSize: 16,
2521 .RegSetSize: 17,
2522 .ID: ARM::DPairSpc_with_ssub_0RegClassID,
2523 .CopyCost: 1, /* CopyCost */
2524 .Allocatable: true, /* Allocatable */
2525 .BaseClass: false,
2526 offsetof(ARMRegisterClassStorage, SubClassMasks[1215]) - 63 * sizeof(MCRegisterClass),
2527 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[58]) - 63 * sizeof(MCRegisterClass),
2528 .LaneMask: LaneBitmask(0x00000000000000CC),
2529 .AllocationPriority: 0,
2530 .GlobalPriority: false,
2531 .TSFlags: 0x00, /* TSFlags */
2532 .SpillStackID: 0, /* SpillStackID */
2533 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2534 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2535 offsetof(ARMRegisterClassStorage, SuperClasses[402]) - 63 * sizeof(MCRegisterClass),
2536 .SuperClassesSize: 1
2537 },
2538 {
2539 offsetof(ARMRegisterClassStorage, Regs[615]) - 64 * sizeof(MCRegisterClass),
2540 offsetof(ARMRegisterClassStorage, BitSets[723]) - 64 * sizeof(MCRegisterClass),
2541 .NameIdx: 359,
2542 .RegSizeInBits: 128,
2543 .RegsSize: 14,
2544 .RegSetSize: 17,
2545 .ID: ARM::DPairSpc_with_ssub_4RegClassID,
2546 .CopyCost: 1, /* CopyCost */
2547 .Allocatable: true, /* Allocatable */
2548 .BaseClass: false,
2549 offsetof(ARMRegisterClassStorage, SubClassMasks[1245]) - 64 * sizeof(MCRegisterClass),
2550 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[58]) - 64 * sizeof(MCRegisterClass),
2551 .LaneMask: LaneBitmask(0x00000000000000CC),
2552 .AllocationPriority: 0,
2553 .GlobalPriority: false,
2554 .TSFlags: 0x00, /* TSFlags */
2555 .SpillStackID: 0, /* SpillStackID */
2556 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2557 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2558 offsetof(ARMRegisterClassStorage, SuperClasses[403]) - 64 * sizeof(MCRegisterClass),
2559 .SuperClassesSize: 2
2560 },
2561 {
2562 offsetof(ARMRegisterClassStorage, Regs[629]) - 65 * sizeof(MCRegisterClass),
2563 offsetof(ARMRegisterClassStorage, BitSets[740]) - 65 * sizeof(MCRegisterClass),
2564 .NameIdx: 498,
2565 .RegSizeInBits: 128,
2566 .RegsSize: 8,
2567 .RegSetSize: 16,
2568 .ID: ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID,
2569 .CopyCost: 1, /* CopyCost */
2570 .Allocatable: true, /* Allocatable */
2571 .BaseClass: false,
2572 offsetof(ARMRegisterClassStorage, SubClassMasks[1275]) - 65 * sizeof(MCRegisterClass),
2573 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[58]) - 65 * sizeof(MCRegisterClass),
2574 .LaneMask: LaneBitmask(0x00000000000000CC),
2575 .AllocationPriority: 0,
2576 .GlobalPriority: false,
2577 .TSFlags: 0x00, /* TSFlags */
2578 .SpillStackID: 0, /* SpillStackID */
2579 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2580 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2581 offsetof(ARMRegisterClassStorage, SuperClasses[405]) - 65 * sizeof(MCRegisterClass),
2582 .SuperClassesSize: 3
2583 },
2584 {
2585 offsetof(ARMRegisterClassStorage, Regs[637]) - 66 * sizeof(MCRegisterClass),
2586 offsetof(ARMRegisterClassStorage, BitSets[756]) - 66 * sizeof(MCRegisterClass),
2587 .NameIdx: 858,
2588 .RegSizeInBits: 128,
2589 .RegsSize: 6,
2590 .RegSetSize: 16,
2591 .ID: ARM::DPairSpc_with_dsub_2_in_DPR_8RegClassID,
2592 .CopyCost: 1, /* CopyCost */
2593 .Allocatable: true, /* Allocatable */
2594 .BaseClass: false,
2595 offsetof(ARMRegisterClassStorage, SubClassMasks[1305]) - 66 * sizeof(MCRegisterClass),
2596 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[58]) - 66 * sizeof(MCRegisterClass),
2597 .LaneMask: LaneBitmask(0x00000000000000CC),
2598 .AllocationPriority: 0,
2599 .GlobalPriority: false,
2600 .TSFlags: 0x00, /* TSFlags */
2601 .SpillStackID: 0, /* SpillStackID */
2602 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2603 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2604 offsetof(ARMRegisterClassStorage, SuperClasses[408]) - 66 * sizeof(MCRegisterClass),
2605 .SuperClassesSize: 4
2606 },
2607 {
2608 offsetof(ARMRegisterClassStorage, Regs[643]) - 67 * sizeof(MCRegisterClass),
2609 offsetof(ARMRegisterClassStorage, BitSets[772]) - 67 * sizeof(MCRegisterClass),
2610 .NameIdx: 2541,
2611 .RegSizeInBits: 128,
2612 .RegsSize: 31,
2613 .RegSetSize: 36,
2614 .ID: ARM::DPairRegClassID,
2615 .CopyCost: 1, /* CopyCost */
2616 .Allocatable: true, /* Allocatable */
2617 .BaseClass: false,
2618 offsetof(ARMRegisterClassStorage, SubClassMasks[1335]) - 67 * sizeof(MCRegisterClass),
2619 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[76]) - 67 * sizeof(MCRegisterClass),
2620 .LaneMask: LaneBitmask(0x000000000000003C),
2621 .AllocationPriority: 0,
2622 .GlobalPriority: false,
2623 .TSFlags: 0x00, /* TSFlags */
2624 .SpillStackID: 0, /* SpillStackID */
2625 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2626 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2627 offsetof(ARMRegisterClassStorage, SuperClasses[412]) - 67 * sizeof(MCRegisterClass),
2628 .SuperClassesSize: 0
2629 },
2630 {
2631 offsetof(ARMRegisterClassStorage, Regs[674]) - 68 * sizeof(MCRegisterClass),
2632 offsetof(ARMRegisterClassStorage, BitSets[808]) - 68 * sizeof(MCRegisterClass),
2633 .NameIdx: 144,
2634 .RegSizeInBits: 128,
2635 .RegsSize: 16,
2636 .RegSetSize: 35,
2637 .ID: ARM::DPair_with_ssub_0RegClassID,
2638 .CopyCost: 1, /* CopyCost */
2639 .Allocatable: true, /* Allocatable */
2640 .BaseClass: false,
2641 offsetof(ARMRegisterClassStorage, SubClassMasks[1375]) - 68 * sizeof(MCRegisterClass),
2642 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[76]) - 68 * sizeof(MCRegisterClass),
2643 .LaneMask: LaneBitmask(0x000000000000003C),
2644 .AllocationPriority: 0,
2645 .GlobalPriority: false,
2646 .TSFlags: 0x00, /* TSFlags */
2647 .SpillStackID: 0, /* SpillStackID */
2648 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2649 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2650 offsetof(ARMRegisterClassStorage, SuperClasses[412]) - 68 * sizeof(MCRegisterClass),
2651 .SuperClassesSize: 1
2652 },
2653 {
2654 offsetof(ARMRegisterClassStorage, Regs[690]) - 69 * sizeof(MCRegisterClass),
2655 offsetof(ARMRegisterClassStorage, BitSets[843]) - 69 * sizeof(MCRegisterClass),
2656 .NameIdx: 1769,
2657 .RegSizeInBits: 128,
2658 .RegsSize: 16,
2659 .RegSetSize: 10,
2660 .ID: ARM::QPRRegClassID,
2661 .CopyCost: 1, /* CopyCost */
2662 .Allocatable: true, /* Allocatable */
2663 .BaseClass: false,
2664 offsetof(ARMRegisterClassStorage, SubClassMasks[1415]) - 69 * sizeof(MCRegisterClass),
2665 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[39]) - 69 * sizeof(MCRegisterClass),
2666 .LaneMask: LaneBitmask(0x000000000000003C),
2667 .AllocationPriority: 0,
2668 .GlobalPriority: false,
2669 .TSFlags: 0x00, /* TSFlags */
2670 .SpillStackID: 0, /* SpillStackID */
2671 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2672 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2673 offsetof(ARMRegisterClassStorage, SuperClasses[413]) - 69 * sizeof(MCRegisterClass),
2674 .SuperClassesSize: 1
2675 },
2676 {
2677 offsetof(ARMRegisterClassStorage, Regs[706]) - 70 * sizeof(MCRegisterClass),
2678 offsetof(ARMRegisterClassStorage, BitSets[853]) - 70 * sizeof(MCRegisterClass),
2679 .NameIdx: 278,
2680 .RegSizeInBits: 128,
2681 .RegsSize: 15,
2682 .RegSetSize: 35,
2683 .ID: ARM::DPair_with_ssub_2RegClassID,
2684 .CopyCost: 1, /* CopyCost */
2685 .Allocatable: true, /* Allocatable */
2686 .BaseClass: false,
2687 offsetof(ARMRegisterClassStorage, SubClassMasks[1445]) - 70 * sizeof(MCRegisterClass),
2688 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[76]) - 70 * sizeof(MCRegisterClass),
2689 .LaneMask: LaneBitmask(0x000000000000003C),
2690 .AllocationPriority: 0,
2691 .GlobalPriority: false,
2692 .TSFlags: 0x00, /* TSFlags */
2693 .SpillStackID: 0, /* SpillStackID */
2694 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2695 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2696 offsetof(ARMRegisterClassStorage, SuperClasses[414]) - 70 * sizeof(MCRegisterClass),
2697 .SuperClassesSize: 2
2698 },
2699 {
2700 offsetof(ARMRegisterClassStorage, Regs[721]) - 71 * sizeof(MCRegisterClass),
2701 offsetof(ARMRegisterClassStorage, BitSets[888]) - 71 * sizeof(MCRegisterClass),
2702 .NameIdx: 584,
2703 .RegSizeInBits: 128,
2704 .RegsSize: 8,
2705 .RegSetSize: 34,
2706 .ID: ARM::DPair_with_dsub_0_in_DPR_8RegClassID,
2707 .CopyCost: 1, /* CopyCost */
2708 .Allocatable: true, /* Allocatable */
2709 .BaseClass: false,
2710 offsetof(ARMRegisterClassStorage, SubClassMasks[1485]) - 71 * sizeof(MCRegisterClass),
2711 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[76]) - 71 * sizeof(MCRegisterClass),
2712 .LaneMask: LaneBitmask(0x000000000000003C),
2713 .AllocationPriority: 0,
2714 .GlobalPriority: false,
2715 .TSFlags: 0x00, /* TSFlags */
2716 .SpillStackID: 0, /* SpillStackID */
2717 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2718 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2719 offsetof(ARMRegisterClassStorage, SuperClasses[416]) - 71 * sizeof(MCRegisterClass),
2720 .SuperClassesSize: 3
2721 },
2722 {
2723 offsetof(ARMRegisterClassStorage, Regs[729]) - 72 * sizeof(MCRegisterClass),
2724 offsetof(ARMRegisterClassStorage, BitSets[922]) - 72 * sizeof(MCRegisterClass),
2725 .NameIdx: 1768,
2726 .RegSizeInBits: 128,
2727 .RegsSize: 8,
2728 .RegSetSize: 9,
2729 .ID: ARM::MQPRRegClassID,
2730 .CopyCost: 1, /* CopyCost */
2731 .Allocatable: true, /* Allocatable */
2732 .BaseClass: false,
2733 offsetof(ARMRegisterClassStorage, SubClassMasks[1525]) - 72 * sizeof(MCRegisterClass),
2734 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[39]) - 72 * sizeof(MCRegisterClass),
2735 .LaneMask: LaneBitmask(0x000000000000003C),
2736 .AllocationPriority: 0,
2737 .GlobalPriority: false,
2738 .TSFlags: 0x00, /* TSFlags */
2739 .SpillStackID: 0, /* SpillStackID */
2740 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2741 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2742 offsetof(ARMRegisterClassStorage, SuperClasses[419]) - 72 * sizeof(MCRegisterClass),
2743 .SuperClassesSize: 5
2744 },
2745 {
2746 offsetof(ARMRegisterClassStorage, Regs[737]) - 73 * sizeof(MCRegisterClass),
2747 offsetof(ARMRegisterClassStorage, BitSets[931]) - 73 * sizeof(MCRegisterClass),
2748 .NameIdx: 231,
2749 .RegSizeInBits: 128,
2750 .RegsSize: 8,
2751 .RegSetSize: 9,
2752 .ID: ARM::QPR_VFP2RegClassID,
2753 .CopyCost: 1, /* CopyCost */
2754 .Allocatable: true, /* Allocatable */
2755 .BaseClass: false,
2756 offsetof(ARMRegisterClassStorage, SubClassMasks[1555]) - 73 * sizeof(MCRegisterClass),
2757 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[39]) - 73 * sizeof(MCRegisterClass),
2758 .LaneMask: LaneBitmask(0x000000000000003C),
2759 .AllocationPriority: 0,
2760 .GlobalPriority: false,
2761 .TSFlags: 0x00, /* TSFlags */
2762 .SpillStackID: 0, /* SpillStackID */
2763 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2764 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2765 offsetof(ARMRegisterClassStorage, SuperClasses[424]) - 73 * sizeof(MCRegisterClass),
2766 .SuperClassesSize: 5
2767 },
2768 {
2769 offsetof(ARMRegisterClassStorage, Regs[745]) - 74 * sizeof(MCRegisterClass),
2770 offsetof(ARMRegisterClassStorage, BitSets[940]) - 74 * sizeof(MCRegisterClass),
2771 .NameIdx: 667,
2772 .RegSizeInBits: 128,
2773 .RegsSize: 7,
2774 .RegSetSize: 34,
2775 .ID: ARM::DPair_with_dsub_1_in_DPR_8RegClassID,
2776 .CopyCost: 1, /* CopyCost */
2777 .Allocatable: true, /* Allocatable */
2778 .BaseClass: false,
2779 offsetof(ARMRegisterClassStorage, SubClassMasks[1585]) - 74 * sizeof(MCRegisterClass),
2780 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[76]) - 74 * sizeof(MCRegisterClass),
2781 .LaneMask: LaneBitmask(0x000000000000003C),
2782 .AllocationPriority: 0,
2783 .GlobalPriority: false,
2784 .TSFlags: 0x00, /* TSFlags */
2785 .SpillStackID: 0, /* SpillStackID */
2786 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2787 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2788 offsetof(ARMRegisterClassStorage, SuperClasses[429]) - 74 * sizeof(MCRegisterClass),
2789 .SuperClassesSize: 4
2790 },
2791 {
2792 offsetof(ARMRegisterClassStorage, Regs[752]) - 75 * sizeof(MCRegisterClass),
2793 offsetof(ARMRegisterClassStorage, BitSets[974]) - 75 * sizeof(MCRegisterClass),
2794 .NameIdx: 1166,
2795 .RegSizeInBits: 128,
2796 .RegsSize: 4,
2797 .RegSetSize: 8,
2798 .ID: ARM::QPR_8RegClassID,
2799 .CopyCost: 1, /* CopyCost */
2800 .Allocatable: true, /* Allocatable */
2801 .BaseClass: false,
2802 offsetof(ARMRegisterClassStorage, SubClassMasks[1625]) - 75 * sizeof(MCRegisterClass),
2803 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[39]) - 75 * sizeof(MCRegisterClass),
2804 .LaneMask: LaneBitmask(0x000000000000003C),
2805 .AllocationPriority: 0,
2806 .GlobalPriority: false,
2807 .TSFlags: 0x00, /* TSFlags */
2808 .SpillStackID: 0, /* SpillStackID */
2809 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2810 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2811 offsetof(ARMRegisterClassStorage, SuperClasses[433]) - 75 * sizeof(MCRegisterClass),
2812 .SuperClassesSize: 8
2813 },
2814 {
2815 offsetof(ARMRegisterClassStorage, Regs[756]) - 76 * sizeof(MCRegisterClass),
2816 offsetof(ARMRegisterClassStorage, BitSets[982]) - 76 * sizeof(MCRegisterClass),
2817 .NameIdx: 2335,
2818 .RegSizeInBits: 192,
2819 .RegsSize: 30,
2820 .RegSetSize: 27,
2821 .ID: ARM::DTripleRegClassID,
2822 .CopyCost: 1, /* CopyCost */
2823 .Allocatable: true, /* Allocatable */
2824 .BaseClass: false,
2825 offsetof(ARMRegisterClassStorage, SubClassMasks[1655]) - 76 * sizeof(MCRegisterClass),
2826 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 76 * sizeof(MCRegisterClass),
2827 .LaneMask: LaneBitmask(0x00000000000000FC),
2828 .AllocationPriority: 0,
2829 .GlobalPriority: false,
2830 .TSFlags: 0x00, /* TSFlags */
2831 .SpillStackID: 0, /* SpillStackID */
2832 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2833 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2834 offsetof(ARMRegisterClassStorage, SuperClasses[441]) - 76 * sizeof(MCRegisterClass),
2835 .SuperClassesSize: 0
2836 },
2837 {
2838 offsetof(ARMRegisterClassStorage, Regs[786]) - 77 * sizeof(MCRegisterClass),
2839 offsetof(ARMRegisterClassStorage, BitSets[1009]) - 77 * sizeof(MCRegisterClass),
2840 .NameIdx: 2235,
2841 .RegSizeInBits: 192,
2842 .RegsSize: 28,
2843 .RegSetSize: 31,
2844 .ID: ARM::DTripleSpcRegClassID,
2845 .CopyCost: 1, /* CopyCost */
2846 .Allocatable: true, /* Allocatable */
2847 .BaseClass: false,
2848 offsetof(ARMRegisterClassStorage, SubClassMasks[1690]) - 77 * sizeof(MCRegisterClass),
2849 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 77 * sizeof(MCRegisterClass),
2850 .LaneMask: LaneBitmask(0x0000000000000CCC),
2851 .AllocationPriority: 0,
2852 .GlobalPriority: false,
2853 .TSFlags: 0x00, /* TSFlags */
2854 .SpillStackID: 0, /* SpillStackID */
2855 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2856 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2857 offsetof(ARMRegisterClassStorage, SuperClasses[441]) - 77 * sizeof(MCRegisterClass),
2858 .SuperClassesSize: 0
2859 },
2860 {
2861 offsetof(ARMRegisterClassStorage, Regs[814]) - 78 * sizeof(MCRegisterClass),
2862 offsetof(ARMRegisterClassStorage, BitSets[1040]) - 78 * sizeof(MCRegisterClass),
2863 .NameIdx: 62,
2864 .RegSizeInBits: 192,
2865 .RegsSize: 16,
2866 .RegSetSize: 29,
2867 .ID: ARM::DTripleSpc_with_ssub_0RegClassID,
2868 .CopyCost: 1, /* CopyCost */
2869 .Allocatable: true, /* Allocatable */
2870 .BaseClass: false,
2871 offsetof(ARMRegisterClassStorage, SubClassMasks[1715]) - 78 * sizeof(MCRegisterClass),
2872 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 78 * sizeof(MCRegisterClass),
2873 .LaneMask: LaneBitmask(0x0000000000000CCC),
2874 .AllocationPriority: 0,
2875 .GlobalPriority: false,
2876 .TSFlags: 0x00, /* TSFlags */
2877 .SpillStackID: 0, /* SpillStackID */
2878 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2879 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2880 offsetof(ARMRegisterClassStorage, SuperClasses[441]) - 78 * sizeof(MCRegisterClass),
2881 .SuperClassesSize: 1
2882 },
2883 {
2884 offsetof(ARMRegisterClassStorage, Regs[830]) - 79 * sizeof(MCRegisterClass),
2885 offsetof(ARMRegisterClassStorage, BitSets[1069]) - 79 * sizeof(MCRegisterClass),
2886 .NameIdx: 124,
2887 .RegSizeInBits: 192,
2888 .RegsSize: 16,
2889 .RegSetSize: 25,
2890 .ID: ARM::DTriple_with_ssub_0RegClassID,
2891 .CopyCost: 1, /* CopyCost */
2892 .Allocatable: true, /* Allocatable */
2893 .BaseClass: false,
2894 offsetof(ARMRegisterClassStorage, SubClassMasks[1740]) - 79 * sizeof(MCRegisterClass),
2895 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 79 * sizeof(MCRegisterClass),
2896 .LaneMask: LaneBitmask(0x00000000000000FC),
2897 .AllocationPriority: 0,
2898 .GlobalPriority: false,
2899 .TSFlags: 0x00, /* TSFlags */
2900 .SpillStackID: 0, /* SpillStackID */
2901 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2902 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2903 offsetof(ARMRegisterClassStorage, SuperClasses[442]) - 79 * sizeof(MCRegisterClass),
2904 .SuperClassesSize: 1
2905 },
2906 {
2907 offsetof(ARMRegisterClassStorage, Regs[846]) - 80 * sizeof(MCRegisterClass),
2908 offsetof(ARMRegisterClassStorage, BitSets[1094]) - 80 * sizeof(MCRegisterClass),
2909 .NameIdx: 1994,
2910 .RegSizeInBits: 192,
2911 .RegsSize: 15,
2912 .RegSetSize: 27,
2913 .ID: ARM::DTriple_with_qsub_0_in_QPRRegClassID,
2914 .CopyCost: 1, /* CopyCost */
2915 .Allocatable: true, /* Allocatable */
2916 .BaseClass: false,
2917 offsetof(ARMRegisterClassStorage, SubClassMasks[1775]) - 80 * sizeof(MCRegisterClass),
2918 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[53]) - 80 * sizeof(MCRegisterClass),
2919 .LaneMask: LaneBitmask(0x00000000000000FC),
2920 .AllocationPriority: 0,
2921 .GlobalPriority: false,
2922 .TSFlags: 0x00, /* TSFlags */
2923 .SpillStackID: 0, /* SpillStackID */
2924 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2925 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2926 offsetof(ARMRegisterClassStorage, SuperClasses[443]) - 80 * sizeof(MCRegisterClass),
2927 .SuperClassesSize: 1
2928 },
2929 {
2930 offsetof(ARMRegisterClassStorage, Regs[861]) - 81 * sizeof(MCRegisterClass),
2931 offsetof(ARMRegisterClassStorage, BitSets[1121]) - 81 * sizeof(MCRegisterClass),
2932 .NameIdx: 258,
2933 .RegSizeInBits: 192,
2934 .RegsSize: 15,
2935 .RegSetSize: 25,
2936 .ID: ARM::DTriple_with_ssub_2RegClassID,
2937 .CopyCost: 1, /* CopyCost */
2938 .Allocatable: true, /* Allocatable */
2939 .BaseClass: false,
2940 offsetof(ARMRegisterClassStorage, SubClassMasks[1800]) - 81 * sizeof(MCRegisterClass),
2941 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 81 * sizeof(MCRegisterClass),
2942 .LaneMask: LaneBitmask(0x00000000000000FC),
2943 .AllocationPriority: 0,
2944 .GlobalPriority: false,
2945 .TSFlags: 0x00, /* TSFlags */
2946 .SpillStackID: 0, /* SpillStackID */
2947 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2948 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2949 offsetof(ARMRegisterClassStorage, SuperClasses[444]) - 81 * sizeof(MCRegisterClass),
2950 .SuperClassesSize: 2
2951 },
2952 {
2953 offsetof(ARMRegisterClassStorage, Regs[876]) - 82 * sizeof(MCRegisterClass),
2954 offsetof(ARMRegisterClassStorage, BitSets[1146]) - 82 * sizeof(MCRegisterClass),
2955 .NameIdx: 2113,
2956 .RegSizeInBits: 192,
2957 .RegsSize: 15,
2958 .RegSetSize: 27,
2959 .ID: ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
2960 .CopyCost: 1, /* CopyCost */
2961 .Allocatable: true, /* Allocatable */
2962 .BaseClass: false,
2963 offsetof(ARMRegisterClassStorage, SubClassMasks[1835]) - 82 * sizeof(MCRegisterClass),
2964 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[64]) - 82 * sizeof(MCRegisterClass),
2965 .LaneMask: LaneBitmask(0x00000000000000FC),
2966 .AllocationPriority: 0,
2967 .GlobalPriority: false,
2968 .TSFlags: 0x00, /* TSFlags */
2969 .SpillStackID: 0, /* SpillStackID */
2970 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2971 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2972 offsetof(ARMRegisterClassStorage, SuperClasses[446]) - 82 * sizeof(MCRegisterClass),
2973 .SuperClassesSize: 1
2974 },
2975 {
2976 offsetof(ARMRegisterClassStorage, Regs[891]) - 83 * sizeof(MCRegisterClass),
2977 offsetof(ARMRegisterClassStorage, BitSets[1173]) - 83 * sizeof(MCRegisterClass),
2978 .NameIdx: 336,
2979 .RegSizeInBits: 192,
2980 .RegsSize: 14,
2981 .RegSetSize: 29,
2982 .ID: ARM::DTripleSpc_with_ssub_4RegClassID,
2983 .CopyCost: 1, /* CopyCost */
2984 .Allocatable: true, /* Allocatable */
2985 .BaseClass: false,
2986 offsetof(ARMRegisterClassStorage, SubClassMasks[1860]) - 83 * sizeof(MCRegisterClass),
2987 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 83 * sizeof(MCRegisterClass),
2988 .LaneMask: LaneBitmask(0x0000000000000CCC),
2989 .AllocationPriority: 0,
2990 .GlobalPriority: false,
2991 .TSFlags: 0x00, /* TSFlags */
2992 .SpillStackID: 0, /* SpillStackID */
2993 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2994 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2995 offsetof(ARMRegisterClassStorage, SuperClasses[447]) - 83 * sizeof(MCRegisterClass),
2996 .SuperClassesSize: 2
2997 },
2998 {
2999 offsetof(ARMRegisterClassStorage, Regs[905]) - 84 * sizeof(MCRegisterClass),
3000 offsetof(ARMRegisterClassStorage, BitSets[1202]) - 84 * sizeof(MCRegisterClass),
3001 .NameIdx: 398,
3002 .RegSizeInBits: 192,
3003 .RegsSize: 14,
3004 .RegSetSize: 25,
3005 .ID: ARM::DTriple_with_ssub_4RegClassID,
3006 .CopyCost: 1, /* CopyCost */
3007 .Allocatable: true, /* Allocatable */
3008 .BaseClass: false,
3009 offsetof(ARMRegisterClassStorage, SubClassMasks[1885]) - 84 * sizeof(MCRegisterClass),
3010 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 84 * sizeof(MCRegisterClass),
3011 .LaneMask: LaneBitmask(0x00000000000000FC),
3012 .AllocationPriority: 0,
3013 .GlobalPriority: false,
3014 .TSFlags: 0x00, /* TSFlags */
3015 .SpillStackID: 0, /* SpillStackID */
3016 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3017 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3018 offsetof(ARMRegisterClassStorage, SuperClasses[449]) - 84 * sizeof(MCRegisterClass),
3019 .SuperClassesSize: 3
3020 },
3021 {
3022 offsetof(ARMRegisterClassStorage, Regs[919]) - 85 * sizeof(MCRegisterClass),
3023 offsetof(ARMRegisterClassStorage, BitSets[1227]) - 85 * sizeof(MCRegisterClass),
3024 .NameIdx: 1411,
3025 .RegSizeInBits: 192,
3026 .RegsSize: 12,
3027 .RegSetSize: 29,
3028 .ID: ARM::DTripleSpc_with_ssub_8RegClassID,
3029 .CopyCost: 1, /* CopyCost */
3030 .Allocatable: true, /* Allocatable */
3031 .BaseClass: false,
3032 offsetof(ARMRegisterClassStorage, SubClassMasks[1920]) - 85 * sizeof(MCRegisterClass),
3033 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 85 * sizeof(MCRegisterClass),
3034 .LaneMask: LaneBitmask(0x0000000000000CCC),
3035 .AllocationPriority: 0,
3036 .GlobalPriority: false,
3037 .TSFlags: 0x00, /* TSFlags */
3038 .SpillStackID: 0, /* SpillStackID */
3039 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3040 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3041 offsetof(ARMRegisterClassStorage, SuperClasses[452]) - 85 * sizeof(MCRegisterClass),
3042 .SuperClassesSize: 3
3043 },
3044 {
3045 offsetof(ARMRegisterClassStorage, Regs[931]) - 86 * sizeof(MCRegisterClass),
3046 offsetof(ARMRegisterClassStorage, BitSets[1256]) - 86 * sizeof(MCRegisterClass),
3047 .NameIdx: 466,
3048 .RegSizeInBits: 192,
3049 .RegsSize: 8,
3050 .RegSetSize: 28,
3051 .ID: ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID,
3052 .CopyCost: 1, /* CopyCost */
3053 .Allocatable: true, /* Allocatable */
3054 .BaseClass: false,
3055 offsetof(ARMRegisterClassStorage, SubClassMasks[1945]) - 86 * sizeof(MCRegisterClass),
3056 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 86 * sizeof(MCRegisterClass),
3057 .LaneMask: LaneBitmask(0x0000000000000CCC),
3058 .AllocationPriority: 0,
3059 .GlobalPriority: false,
3060 .TSFlags: 0x00, /* TSFlags */
3061 .SpillStackID: 0, /* SpillStackID */
3062 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3063 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3064 offsetof(ARMRegisterClassStorage, SuperClasses[455]) - 86 * sizeof(MCRegisterClass),
3065 .SuperClassesSize: 4
3066 },
3067 {
3068 offsetof(ARMRegisterClassStorage, Regs[939]) - 87 * sizeof(MCRegisterClass),
3069 offsetof(ARMRegisterClassStorage, BitSets[1284]) - 87 * sizeof(MCRegisterClass),
3070 .NameIdx: 555,
3071 .RegSizeInBits: 192,
3072 .RegsSize: 8,
3073 .RegSetSize: 24,
3074 .ID: ARM::DTriple_with_dsub_0_in_DPR_8RegClassID,
3075 .CopyCost: 1, /* CopyCost */
3076 .Allocatable: true, /* Allocatable */
3077 .BaseClass: false,
3078 offsetof(ARMRegisterClassStorage, SubClassMasks[1970]) - 87 * sizeof(MCRegisterClass),
3079 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 87 * sizeof(MCRegisterClass),
3080 .LaneMask: LaneBitmask(0x00000000000000FC),
3081 .AllocationPriority: 0,
3082 .GlobalPriority: false,
3083 .TSFlags: 0x00, /* TSFlags */
3084 .SpillStackID: 0, /* SpillStackID */
3085 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3086 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3087 offsetof(ARMRegisterClassStorage, SuperClasses[459]) - 87 * sizeof(MCRegisterClass),
3088 .SuperClassesSize: 4
3089 },
3090 {
3091 offsetof(ARMRegisterClassStorage, Regs[947]) - 88 * sizeof(MCRegisterClass),
3092 offsetof(ARMRegisterClassStorage, BitSets[1308]) - 88 * sizeof(MCRegisterClass),
3093 .NameIdx: 1745,
3094 .RegSizeInBits: 192,
3095 .RegsSize: 8,
3096 .RegSetSize: 25,
3097 .ID: ARM::DTriple_with_qsub_0_in_MQPRRegClassID,
3098 .CopyCost: 1, /* CopyCost */
3099 .Allocatable: true, /* Allocatable */
3100 .BaseClass: false,
3101 offsetof(ARMRegisterClassStorage, SubClassMasks[2005]) - 88 * sizeof(MCRegisterClass),
3102 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[53]) - 88 * sizeof(MCRegisterClass),
3103 .LaneMask: LaneBitmask(0x00000000000000FC),
3104 .AllocationPriority: 0,
3105 .GlobalPriority: false,
3106 .TSFlags: 0x00, /* TSFlags */
3107 .SpillStackID: 0, /* SpillStackID */
3108 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3109 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3110 offsetof(ARMRegisterClassStorage, SuperClasses[463]) - 88 * sizeof(MCRegisterClass),
3111 .SuperClassesSize: 4
3112 },
3113 {
3114 offsetof(ARMRegisterClassStorage, Regs[955]) - 89 * sizeof(MCRegisterClass),
3115 offsetof(ARMRegisterClassStorage, BitSets[1333]) - 89 * sizeof(MCRegisterClass),
3116 .NameIdx: 2089,
3117 .RegSizeInBits: 192,
3118 .RegsSize: 8,
3119 .RegSetSize: 25,
3120 .ID: ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
3121 .CopyCost: 1, /* CopyCost */
3122 .Allocatable: true, /* Allocatable */
3123 .BaseClass: false,
3124 offsetof(ARMRegisterClassStorage, SubClassMasks[2030]) - 89 * sizeof(MCRegisterClass),
3125 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[64]) - 89 * sizeof(MCRegisterClass),
3126 .LaneMask: LaneBitmask(0x00000000000000FC),
3127 .AllocationPriority: 0,
3128 .GlobalPriority: false,
3129 .TSFlags: 0x00, /* TSFlags */
3130 .SpillStackID: 0, /* SpillStackID */
3131 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3132 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3133 offsetof(ARMRegisterClassStorage, SuperClasses[467]) - 89 * sizeof(MCRegisterClass),
3134 .SuperClassesSize: 3
3135 },
3136 {
3137 offsetof(ARMRegisterClassStorage, Regs[963]) - 90 * sizeof(MCRegisterClass),
3138 offsetof(ARMRegisterClassStorage, BitSets[1358]) - 90 * sizeof(MCRegisterClass),
3139 .NameIdx: 638,
3140 .RegSizeInBits: 192,
3141 .RegsSize: 7,
3142 .RegSetSize: 24,
3143 .ID: ARM::DTriple_with_dsub_1_in_DPR_8RegClassID,
3144 .CopyCost: 1, /* CopyCost */
3145 .Allocatable: true, /* Allocatable */
3146 .BaseClass: false,
3147 offsetof(ARMRegisterClassStorage, SubClassMasks[2055]) - 90 * sizeof(MCRegisterClass),
3148 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 90 * sizeof(MCRegisterClass),
3149 .LaneMask: LaneBitmask(0x00000000000000FC),
3150 .AllocationPriority: 0,
3151 .GlobalPriority: false,
3152 .TSFlags: 0x00, /* TSFlags */
3153 .SpillStackID: 0, /* SpillStackID */
3154 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3155 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3156 offsetof(ARMRegisterClassStorage, SuperClasses[470]) - 90 * sizeof(MCRegisterClass),
3157 .SuperClassesSize: 5
3158 },
3159 {
3160 offsetof(ARMRegisterClassStorage, Regs[970]) - 91 * sizeof(MCRegisterClass),
3161 offsetof(ARMRegisterClassStorage, BitSets[1382]) - 91 * sizeof(MCRegisterClass),
3162 .NameIdx: 1931,
3163 .RegSizeInBits: 192,
3164 .RegsSize: 7,
3165 .RegSetSize: 25,
3166 .ID: ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
3167 .CopyCost: 1, /* CopyCost */
3168 .Allocatable: true, /* Allocatable */
3169 .BaseClass: false,
3170 offsetof(ARMRegisterClassStorage, SubClassMasks[2090]) - 91 * sizeof(MCRegisterClass),
3171 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[64]) - 91 * sizeof(MCRegisterClass),
3172 .LaneMask: LaneBitmask(0x00000000000000FC),
3173 .AllocationPriority: 0,
3174 .GlobalPriority: false,
3175 .TSFlags: 0x00, /* TSFlags */
3176 .SpillStackID: 0, /* SpillStackID */
3177 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3178 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3179 offsetof(ARMRegisterClassStorage, SuperClasses[475]) - 91 * sizeof(MCRegisterClass),
3180 .SuperClassesSize: 6
3181 },
3182 {
3183 offsetof(ARMRegisterClassStorage, Regs[977]) - 92 * sizeof(MCRegisterClass),
3184 offsetof(ARMRegisterClassStorage, BitSets[1407]) - 92 * sizeof(MCRegisterClass),
3185 .NameIdx: 1721,
3186 .RegSizeInBits: 192,
3187 .RegsSize: 7,
3188 .RegSetSize: 25,
3189 .ID: ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID,
3190 .CopyCost: 1, /* CopyCost */
3191 .Allocatable: true, /* Allocatable */
3192 .BaseClass: false,
3193 offsetof(ARMRegisterClassStorage, SubClassMasks[2115]) - 92 * sizeof(MCRegisterClass),
3194 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[53]) - 92 * sizeof(MCRegisterClass),
3195 .LaneMask: LaneBitmask(0x00000000000000FC),
3196 .AllocationPriority: 0,
3197 .GlobalPriority: false,
3198 .TSFlags: 0x00, /* TSFlags */
3199 .SpillStackID: 0, /* SpillStackID */
3200 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3201 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3202 offsetof(ARMRegisterClassStorage, SuperClasses[481]) - 92 * sizeof(MCRegisterClass),
3203 .SuperClassesSize: 6
3204 },
3205 {
3206 offsetof(ARMRegisterClassStorage, Regs[984]) - 93 * sizeof(MCRegisterClass),
3207 offsetof(ARMRegisterClassStorage, BitSets[1432]) - 93 * sizeof(MCRegisterClass),
3208 .NameIdx: 826,
3209 .RegSizeInBits: 192,
3210 .RegsSize: 6,
3211 .RegSetSize: 28,
3212 .ID: ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID,
3213 .CopyCost: 1, /* CopyCost */
3214 .Allocatable: true, /* Allocatable */
3215 .BaseClass: false,
3216 offsetof(ARMRegisterClassStorage, SubClassMasks[2140]) - 93 * sizeof(MCRegisterClass),
3217 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 93 * sizeof(MCRegisterClass),
3218 .LaneMask: LaneBitmask(0x0000000000000CCC),
3219 .AllocationPriority: 0,
3220 .GlobalPriority: false,
3221 .TSFlags: 0x00, /* TSFlags */
3222 .SpillStackID: 0, /* SpillStackID */
3223 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3224 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3225 offsetof(ARMRegisterClassStorage, SuperClasses[487]) - 93 * sizeof(MCRegisterClass),
3226 .SuperClassesSize: 5
3227 },
3228 {
3229 offsetof(ARMRegisterClassStorage, Regs[990]) - 94 * sizeof(MCRegisterClass),
3230 offsetof(ARMRegisterClassStorage, BitSets[1460]) - 94 * sizeof(MCRegisterClass),
3231 .NameIdx: 1003,
3232 .RegSizeInBits: 192,
3233 .RegsSize: 6,
3234 .RegSetSize: 24,
3235 .ID: ARM::DTriple_with_dsub_2_in_DPR_8RegClassID,
3236 .CopyCost: 1, /* CopyCost */
3237 .Allocatable: true, /* Allocatable */
3238 .BaseClass: false,
3239 offsetof(ARMRegisterClassStorage, SubClassMasks[2165]) - 94 * sizeof(MCRegisterClass),
3240 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 94 * sizeof(MCRegisterClass),
3241 .LaneMask: LaneBitmask(0x00000000000000FC),
3242 .AllocationPriority: 0,
3243 .GlobalPriority: false,
3244 .TSFlags: 0x00, /* TSFlags */
3245 .SpillStackID: 0, /* SpillStackID */
3246 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3247 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3248 offsetof(ARMRegisterClassStorage, SuperClasses[492]) - 94 * sizeof(MCRegisterClass),
3249 .SuperClassesSize: 6
3250 },
3251 {
3252 offsetof(ARMRegisterClassStorage, Regs[996]) - 95 * sizeof(MCRegisterClass),
3253 offsetof(ARMRegisterClassStorage, BitSets[1484]) - 95 * sizeof(MCRegisterClass),
3254 .NameIdx: 1089,
3255 .RegSizeInBits: 192,
3256 .RegsSize: 4,
3257 .RegSetSize: 28,
3258 .ID: ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID,
3259 .CopyCost: 1, /* CopyCost */
3260 .Allocatable: true, /* Allocatable */
3261 .BaseClass: false,
3262 offsetof(ARMRegisterClassStorage, SubClassMasks[2200]) - 95 * sizeof(MCRegisterClass),
3263 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 95 * sizeof(MCRegisterClass),
3264 .LaneMask: LaneBitmask(0x0000000000000CCC),
3265 .AllocationPriority: 0,
3266 .GlobalPriority: false,
3267 .TSFlags: 0x00, /* TSFlags */
3268 .SpillStackID: 0, /* SpillStackID */
3269 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3270 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3271 offsetof(ARMRegisterClassStorage, SuperClasses[498]) - 95 * sizeof(MCRegisterClass),
3272 .SuperClassesSize: 6
3273 },
3274 {
3275 offsetof(ARMRegisterClassStorage, Regs[1000]) - 96 * sizeof(MCRegisterClass),
3276 offsetof(ARMRegisterClassStorage, BitSets[1512]) - 96 * sizeof(MCRegisterClass),
3277 .NameIdx: 1898,
3278 .RegSizeInBits: 192,
3279 .RegsSize: 4,
3280 .RegSetSize: 24,
3281 .ID: ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
3282 .CopyCost: 1, /* CopyCost */
3283 .Allocatable: true, /* Allocatable */
3284 .BaseClass: false,
3285 offsetof(ARMRegisterClassStorage, SubClassMasks[2225]) - 96 * sizeof(MCRegisterClass),
3286 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[64]) - 96 * sizeof(MCRegisterClass),
3287 .LaneMask: LaneBitmask(0x00000000000000FC),
3288 .AllocationPriority: 0,
3289 .GlobalPriority: false,
3290 .TSFlags: 0x00, /* TSFlags */
3291 .SpillStackID: 0, /* SpillStackID */
3292 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3293 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3294 offsetof(ARMRegisterClassStorage, SuperClasses[504]) - 96 * sizeof(MCRegisterClass),
3295 .SuperClassesSize: 8
3296 },
3297 {
3298 offsetof(ARMRegisterClassStorage, Regs[1004]) - 97 * sizeof(MCRegisterClass),
3299 offsetof(ARMRegisterClassStorage, BitSets[1536]) - 97 * sizeof(MCRegisterClass),
3300 .NameIdx: 1172,
3301 .RegSizeInBits: 192,
3302 .RegsSize: 4,
3303 .RegSetSize: 24,
3304 .ID: ARM::DTriple_with_qsub_0_in_QPR_8RegClassID,
3305 .CopyCost: 1, /* CopyCost */
3306 .Allocatable: true, /* Allocatable */
3307 .BaseClass: false,
3308 offsetof(ARMRegisterClassStorage, SubClassMasks[2250]) - 97 * sizeof(MCRegisterClass),
3309 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[53]) - 97 * sizeof(MCRegisterClass),
3310 .LaneMask: LaneBitmask(0x00000000000000FC),
3311 .AllocationPriority: 0,
3312 .GlobalPriority: false,
3313 .TSFlags: 0x00, /* TSFlags */
3314 .SpillStackID: 0, /* SpillStackID */
3315 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3316 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3317 offsetof(ARMRegisterClassStorage, SuperClasses[512]) - 97 * sizeof(MCRegisterClass),
3318 .SuperClassesSize: 9
3319 },
3320 {
3321 offsetof(ARMRegisterClassStorage, Regs[1008]) - 98 * sizeof(MCRegisterClass),
3322 offsetof(ARMRegisterClassStorage, BitSets[1560]) - 98 * sizeof(MCRegisterClass),
3323 .NameIdx: 971,
3324 .RegSizeInBits: 192,
3325 .RegsSize: 3,
3326 .RegSetSize: 24,
3327 .ID: ARM::DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID,
3328 .CopyCost: 1, /* CopyCost */
3329 .Allocatable: true, /* Allocatable */
3330 .BaseClass: false,
3331 offsetof(ARMRegisterClassStorage, SubClassMasks[2275]) - 98 * sizeof(MCRegisterClass),
3332 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[53]) - 98 * sizeof(MCRegisterClass),
3333 .LaneMask: LaneBitmask(0x00000000000000FC),
3334 .AllocationPriority: 0,
3335 .GlobalPriority: false,
3336 .TSFlags: 0x00, /* TSFlags */
3337 .SpillStackID: 0, /* SpillStackID */
3338 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3339 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3340 offsetof(ARMRegisterClassStorage, SuperClasses[521]) - 98 * sizeof(MCRegisterClass),
3341 .SuperClassesSize: 11
3342 },
3343 {
3344 offsetof(ARMRegisterClassStorage, Regs[1011]) - 99 * sizeof(MCRegisterClass),
3345 offsetof(ARMRegisterClassStorage, BitSets[1584]) - 99 * sizeof(MCRegisterClass),
3346 .NameIdx: 1278,
3347 .RegSizeInBits: 192,
3348 .RegsSize: 3,
3349 .RegSetSize: 24,
3350 .ID: ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID,
3351 .CopyCost: 1, /* CopyCost */
3352 .Allocatable: true, /* Allocatable */
3353 .BaseClass: false,
3354 offsetof(ARMRegisterClassStorage, SubClassMasks[2300]) - 99 * sizeof(MCRegisterClass),
3355 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[64]) - 99 * sizeof(MCRegisterClass),
3356 .LaneMask: LaneBitmask(0x00000000000000FC),
3357 .AllocationPriority: 0,
3358 .GlobalPriority: false,
3359 .TSFlags: 0x00, /* TSFlags */
3360 .SpillStackID: 0, /* SpillStackID */
3361 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3362 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3363 offsetof(ARMRegisterClassStorage, SuperClasses[532]) - 99 * sizeof(MCRegisterClass),
3364 .SuperClassesSize: 11
3365 },
3366 {
3367 offsetof(ARMRegisterClassStorage, Regs[1014]) - 100 * sizeof(MCRegisterClass),
3368 offsetof(ARMRegisterClassStorage, BitSets[1608]) - 100 * sizeof(MCRegisterClass),
3369 .NameIdx: 2226,
3370 .RegSizeInBits: 256,
3371 .RegsSize: 28,
3372 .RegSetSize: 31,
3373 .ID: ARM::DQuadSpcRegClassID,
3374 .CopyCost: 1, /* CopyCost */
3375 .Allocatable: true, /* Allocatable */
3376 .BaseClass: false,
3377 offsetof(ARMRegisterClassStorage, SubClassMasks[2325]) - 100 * sizeof(MCRegisterClass),
3378 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 100 * sizeof(MCRegisterClass),
3379 .LaneMask: LaneBitmask(0x0000000000000CCC),
3380 .AllocationPriority: 0,
3381 .GlobalPriority: false,
3382 .TSFlags: 0x00, /* TSFlags */
3383 .SpillStackID: 0, /* SpillStackID */
3384 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3385 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3386 offsetof(ARMRegisterClassStorage, SuperClasses[543]) - 100 * sizeof(MCRegisterClass),
3387 .SuperClassesSize: 1
3388 },
3389 {
3390 offsetof(ARMRegisterClassStorage, Regs[1042]) - 101 * sizeof(MCRegisterClass),
3391 offsetof(ARMRegisterClassStorage, BitSets[1639]) - 101 * sizeof(MCRegisterClass),
3392 .NameIdx: 41,
3393 .RegSizeInBits: 256,
3394 .RegsSize: 16,
3395 .RegSetSize: 29,
3396 .ID: ARM::DQuadSpc_with_ssub_0RegClassID,
3397 .CopyCost: 1, /* CopyCost */
3398 .Allocatable: true, /* Allocatable */
3399 .BaseClass: false,
3400 offsetof(ARMRegisterClassStorage, SubClassMasks[2350]) - 101 * sizeof(MCRegisterClass),
3401 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 101 * sizeof(MCRegisterClass),
3402 .LaneMask: LaneBitmask(0x0000000000000CCC),
3403 .AllocationPriority: 0,
3404 .GlobalPriority: false,
3405 .TSFlags: 0x00, /* TSFlags */
3406 .SpillStackID: 0, /* SpillStackID */
3407 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3408 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3409 offsetof(ARMRegisterClassStorage, SuperClasses[544]) - 101 * sizeof(MCRegisterClass),
3410 .SuperClassesSize: 3
3411 },
3412 {
3413 offsetof(ARMRegisterClassStorage, Regs[1058]) - 102 * sizeof(MCRegisterClass),
3414 offsetof(ARMRegisterClassStorage, BitSets[1668]) - 102 * sizeof(MCRegisterClass),
3415 .NameIdx: 315,
3416 .RegSizeInBits: 256,
3417 .RegsSize: 14,
3418 .RegSetSize: 29,
3419 .ID: ARM::DQuadSpc_with_ssub_4RegClassID,
3420 .CopyCost: 1, /* CopyCost */
3421 .Allocatable: true, /* Allocatable */
3422 .BaseClass: false,
3423 offsetof(ARMRegisterClassStorage, SubClassMasks[2375]) - 102 * sizeof(MCRegisterClass),
3424 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 102 * sizeof(MCRegisterClass),
3425 .LaneMask: LaneBitmask(0x0000000000000CCC),
3426 .AllocationPriority: 0,
3427 .GlobalPriority: false,
3428 .TSFlags: 0x00, /* TSFlags */
3429 .SpillStackID: 0, /* SpillStackID */
3430 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3431 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3432 offsetof(ARMRegisterClassStorage, SuperClasses[547]) - 102 * sizeof(MCRegisterClass),
3433 .SuperClassesSize: 5
3434 },
3435 {
3436 offsetof(ARMRegisterClassStorage, Regs[1072]) - 103 * sizeof(MCRegisterClass),
3437 offsetof(ARMRegisterClassStorage, BitSets[1697]) - 103 * sizeof(MCRegisterClass),
3438 .NameIdx: 1390,
3439 .RegSizeInBits: 256,
3440 .RegsSize: 12,
3441 .RegSetSize: 29,
3442 .ID: ARM::DQuadSpc_with_ssub_8RegClassID,
3443 .CopyCost: 1, /* CopyCost */
3444 .Allocatable: true, /* Allocatable */
3445 .BaseClass: false,
3446 offsetof(ARMRegisterClassStorage, SubClassMasks[2400]) - 103 * sizeof(MCRegisterClass),
3447 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 103 * sizeof(MCRegisterClass),
3448 .LaneMask: LaneBitmask(0x0000000000000CCC),
3449 .AllocationPriority: 0,
3450 .GlobalPriority: false,
3451 .TSFlags: 0x00, /* TSFlags */
3452 .SpillStackID: 0, /* SpillStackID */
3453 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3454 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3455 offsetof(ARMRegisterClassStorage, SuperClasses[552]) - 103 * sizeof(MCRegisterClass),
3456 .SuperClassesSize: 7
3457 },
3458 {
3459 offsetof(ARMRegisterClassStorage, Regs[1084]) - 104 * sizeof(MCRegisterClass),
3460 offsetof(ARMRegisterClassStorage, BitSets[1726]) - 104 * sizeof(MCRegisterClass),
3461 .NameIdx: 436,
3462 .RegSizeInBits: 256,
3463 .RegsSize: 8,
3464 .RegSetSize: 28,
3465 .ID: ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID,
3466 .CopyCost: 1, /* CopyCost */
3467 .Allocatable: true, /* Allocatable */
3468 .BaseClass: false,
3469 offsetof(ARMRegisterClassStorage, SubClassMasks[2425]) - 104 * sizeof(MCRegisterClass),
3470 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 104 * sizeof(MCRegisterClass),
3471 .LaneMask: LaneBitmask(0x0000000000000CCC),
3472 .AllocationPriority: 0,
3473 .GlobalPriority: false,
3474 .TSFlags: 0x00, /* TSFlags */
3475 .SpillStackID: 0, /* SpillStackID */
3476 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3477 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3478 offsetof(ARMRegisterClassStorage, SuperClasses[559]) - 104 * sizeof(MCRegisterClass),
3479 .SuperClassesSize: 9
3480 },
3481 {
3482 offsetof(ARMRegisterClassStorage, Regs[1092]) - 105 * sizeof(MCRegisterClass),
3483 offsetof(ARMRegisterClassStorage, BitSets[1754]) - 105 * sizeof(MCRegisterClass),
3484 .NameIdx: 796,
3485 .RegSizeInBits: 256,
3486 .RegsSize: 6,
3487 .RegSetSize: 28,
3488 .ID: ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID,
3489 .CopyCost: 1, /* CopyCost */
3490 .Allocatable: true, /* Allocatable */
3491 .BaseClass: false,
3492 offsetof(ARMRegisterClassStorage, SubClassMasks[2450]) - 105 * sizeof(MCRegisterClass),
3493 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 105 * sizeof(MCRegisterClass),
3494 .LaneMask: LaneBitmask(0x0000000000000CCC),
3495 .AllocationPriority: 0,
3496 .GlobalPriority: false,
3497 .TSFlags: 0x00, /* TSFlags */
3498 .SpillStackID: 0, /* SpillStackID */
3499 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3500 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3501 offsetof(ARMRegisterClassStorage, SuperClasses[568]) - 105 * sizeof(MCRegisterClass),
3502 .SuperClassesSize: 11
3503 },
3504 {
3505 offsetof(ARMRegisterClassStorage, Regs[1098]) - 106 * sizeof(MCRegisterClass),
3506 offsetof(ARMRegisterClassStorage, BitSets[1782]) - 106 * sizeof(MCRegisterClass),
3507 .NameIdx: 1059,
3508 .RegSizeInBits: 256,
3509 .RegsSize: 4,
3510 .RegSetSize: 28,
3511 .ID: ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID,
3512 .CopyCost: 1, /* CopyCost */
3513 .Allocatable: true, /* Allocatable */
3514 .BaseClass: false,
3515 offsetof(ARMRegisterClassStorage, SubClassMasks[2475]) - 106 * sizeof(MCRegisterClass),
3516 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 106 * sizeof(MCRegisterClass),
3517 .LaneMask: LaneBitmask(0x0000000000000CCC),
3518 .AllocationPriority: 0,
3519 .GlobalPriority: false,
3520 .TSFlags: 0x00, /* TSFlags */
3521 .SpillStackID: 0, /* SpillStackID */
3522 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3523 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3524 offsetof(ARMRegisterClassStorage, SuperClasses[579]) - 106 * sizeof(MCRegisterClass),
3525 .SuperClassesSize: 13
3526 },
3527 {
3528 offsetof(ARMRegisterClassStorage, Regs[1102]) - 107 * sizeof(MCRegisterClass),
3529 offsetof(ARMRegisterClassStorage, BitSets[1810]) - 107 * sizeof(MCRegisterClass),
3530 .NameIdx: 2295,
3531 .RegSizeInBits: 256,
3532 .RegsSize: 29,
3533 .RegSetSize: 38,
3534 .ID: ARM::DQuadRegClassID,
3535 .CopyCost: 1, /* CopyCost */
3536 .Allocatable: true, /* Allocatable */
3537 .BaseClass: false,
3538 offsetof(ARMRegisterClassStorage, SubClassMasks[2500]) - 107 * sizeof(MCRegisterClass),
3539 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 107 * sizeof(MCRegisterClass),
3540 .LaneMask: LaneBitmask(0x00000000000003FC),
3541 .AllocationPriority: 0,
3542 .GlobalPriority: false,
3543 .TSFlags: 0x00, /* TSFlags */
3544 .SpillStackID: 0, /* SpillStackID */
3545 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3546 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3547 offsetof(ARMRegisterClassStorage, SuperClasses[592]) - 107 * sizeof(MCRegisterClass),
3548 .SuperClassesSize: 0
3549 },
3550 {
3551 offsetof(ARMRegisterClassStorage, Regs[1131]) - 108 * sizeof(MCRegisterClass),
3552 offsetof(ARMRegisterClassStorage, BitSets[1848]) - 108 * sizeof(MCRegisterClass),
3553 .NameIdx: 106,
3554 .RegSizeInBits: 256,
3555 .RegsSize: 16,
3556 .RegSetSize: 37,
3557 .ID: ARM::DQuad_with_ssub_0RegClassID,
3558 .CopyCost: 1, /* CopyCost */
3559 .Allocatable: true, /* Allocatable */
3560 .BaseClass: false,
3561 offsetof(ARMRegisterClassStorage, SubClassMasks[2530]) - 108 * sizeof(MCRegisterClass),
3562 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 108 * sizeof(MCRegisterClass),
3563 .LaneMask: LaneBitmask(0x00000000000003FC),
3564 .AllocationPriority: 0,
3565 .GlobalPriority: false,
3566 .TSFlags: 0x00, /* TSFlags */
3567 .SpillStackID: 0, /* SpillStackID */
3568 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3569 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3570 offsetof(ARMRegisterClassStorage, SuperClasses[592]) - 108 * sizeof(MCRegisterClass),
3571 .SuperClassesSize: 1
3572 },
3573 {
3574 offsetof(ARMRegisterClassStorage, Regs[1147]) - 109 * sizeof(MCRegisterClass),
3575 offsetof(ARMRegisterClassStorage, BitSets[1885]) - 109 * sizeof(MCRegisterClass),
3576 .NameIdx: 240,
3577 .RegSizeInBits: 256,
3578 .RegsSize: 15,
3579 .RegSetSize: 37,
3580 .ID: ARM::DQuad_with_ssub_2RegClassID,
3581 .CopyCost: 1, /* CopyCost */
3582 .Allocatable: true, /* Allocatable */
3583 .BaseClass: false,
3584 offsetof(ARMRegisterClassStorage, SubClassMasks[2560]) - 109 * sizeof(MCRegisterClass),
3585 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 109 * sizeof(MCRegisterClass),
3586 .LaneMask: LaneBitmask(0x00000000000003FC),
3587 .AllocationPriority: 0,
3588 .GlobalPriority: false,
3589 .TSFlags: 0x00, /* TSFlags */
3590 .SpillStackID: 0, /* SpillStackID */
3591 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3592 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3593 offsetof(ARMRegisterClassStorage, SuperClasses[593]) - 109 * sizeof(MCRegisterClass),
3594 .SuperClassesSize: 2
3595 },
3596 {
3597 offsetof(ARMRegisterClassStorage, Regs[1162]) - 110 * sizeof(MCRegisterClass),
3598 offsetof(ARMRegisterClassStorage, BitSets[1922]) - 110 * sizeof(MCRegisterClass),
3599 .NameIdx: 1981,
3600 .RegSizeInBits: 256,
3601 .RegsSize: 15,
3602 .RegSetSize: 21,
3603 .ID: ARM::QQPRRegClassID,
3604 .CopyCost: 1, /* CopyCost */
3605 .Allocatable: true, /* Allocatable */
3606 .BaseClass: false,
3607 offsetof(ARMRegisterClassStorage, SubClassMasks[2590]) - 110 * sizeof(MCRegisterClass),
3608 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[84]) - 110 * sizeof(MCRegisterClass),
3609 .LaneMask: LaneBitmask(0x00000000000003FC),
3610 .AllocationPriority: 0,
3611 .GlobalPriority: false,
3612 .TSFlags: 0x00, /* TSFlags */
3613 .SpillStackID: 0, /* SpillStackID */
3614 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3615 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3616 offsetof(ARMRegisterClassStorage, SuperClasses[595]) - 110 * sizeof(MCRegisterClass),
3617 .SuperClassesSize: 1
3618 },
3619 {
3620 offsetof(ARMRegisterClassStorage, Regs[1177]) - 111 * sizeof(MCRegisterClass),
3621 offsetof(ARMRegisterClassStorage, BitSets[1943]) - 111 * sizeof(MCRegisterClass),
3622 .NameIdx: 2043,
3623 .RegSizeInBits: 256,
3624 .RegsSize: 14,
3625 .RegSetSize: 38,
3626 .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
3627 .CopyCost: 1, /* CopyCost */
3628 .Allocatable: true, /* Allocatable */
3629 .BaseClass: false,
3630 offsetof(ARMRegisterClassStorage, SubClassMasks[2610]) - 111 * sizeof(MCRegisterClass),
3631 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 111 * sizeof(MCRegisterClass),
3632 .LaneMask: LaneBitmask(0x00000000000003FC),
3633 .AllocationPriority: 0,
3634 .GlobalPriority: false,
3635 .TSFlags: 0x00, /* TSFlags */
3636 .SpillStackID: 0, /* SpillStackID */
3637 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3638 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3639 offsetof(ARMRegisterClassStorage, SuperClasses[596]) - 111 * sizeof(MCRegisterClass),
3640 .SuperClassesSize: 1
3641 },
3642 {
3643 offsetof(ARMRegisterClassStorage, Regs[1191]) - 112 * sizeof(MCRegisterClass),
3644 offsetof(ARMRegisterClassStorage, BitSets[1981]) - 112 * sizeof(MCRegisterClass),
3645 .NameIdx: 380,
3646 .RegSizeInBits: 256,
3647 .RegsSize: 14,
3648 .RegSetSize: 37,
3649 .ID: ARM::DQuad_with_ssub_4RegClassID,
3650 .CopyCost: 1, /* CopyCost */
3651 .Allocatable: true, /* Allocatable */
3652 .BaseClass: false,
3653 offsetof(ARMRegisterClassStorage, SubClassMasks[2625]) - 112 * sizeof(MCRegisterClass),
3654 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 112 * sizeof(MCRegisterClass),
3655 .LaneMask: LaneBitmask(0x00000000000003FC),
3656 .AllocationPriority: 0,
3657 .GlobalPriority: false,
3658 .TSFlags: 0x00, /* TSFlags */
3659 .SpillStackID: 0, /* SpillStackID */
3660 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3661 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3662 offsetof(ARMRegisterClassStorage, SuperClasses[597]) - 112 * sizeof(MCRegisterClass),
3663 .SuperClassesSize: 3
3664 },
3665 {
3666 offsetof(ARMRegisterClassStorage, Regs[1205]) - 113 * sizeof(MCRegisterClass),
3667 offsetof(ARMRegisterClassStorage, BitSets[2018]) - 113 * sizeof(MCRegisterClass),
3668 .NameIdx: 418,
3669 .RegSizeInBits: 256,
3670 .RegsSize: 13,
3671 .RegSetSize: 37,
3672 .ID: ARM::DQuad_with_ssub_6RegClassID,
3673 .CopyCost: 1, /* CopyCost */
3674 .Allocatable: true, /* Allocatable */
3675 .BaseClass: false,
3676 offsetof(ARMRegisterClassStorage, SubClassMasks[2655]) - 113 * sizeof(MCRegisterClass),
3677 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 113 * sizeof(MCRegisterClass),
3678 .LaneMask: LaneBitmask(0x00000000000003FC),
3679 .AllocationPriority: 0,
3680 .GlobalPriority: false,
3681 .TSFlags: 0x00, /* TSFlags */
3682 .SpillStackID: 0, /* SpillStackID */
3683 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3684 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3685 offsetof(ARMRegisterClassStorage, SuperClasses[600]) - 113 * sizeof(MCRegisterClass),
3686 .SuperClassesSize: 4
3687 },
3688 {
3689 offsetof(ARMRegisterClassStorage, Regs[1218]) - 114 * sizeof(MCRegisterClass),
3690 offsetof(ARMRegisterClassStorage, BitSets[2055]) - 114 * sizeof(MCRegisterClass),
3691 .NameIdx: 528,
3692 .RegSizeInBits: 256,
3693 .RegsSize: 8,
3694 .RegSetSize: 36,
3695 .ID: ARM::DQuad_with_dsub_0_in_DPR_8RegClassID,
3696 .CopyCost: 1, /* CopyCost */
3697 .Allocatable: true, /* Allocatable */
3698 .BaseClass: false,
3699 offsetof(ARMRegisterClassStorage, SubClassMasks[2685]) - 114 * sizeof(MCRegisterClass),
3700 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 114 * sizeof(MCRegisterClass),
3701 .LaneMask: LaneBitmask(0x00000000000003FC),
3702 .AllocationPriority: 0,
3703 .GlobalPriority: false,
3704 .TSFlags: 0x00, /* TSFlags */
3705 .SpillStackID: 0, /* SpillStackID */
3706 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3707 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3708 offsetof(ARMRegisterClassStorage, SuperClasses[604]) - 114 * sizeof(MCRegisterClass),
3709 .SuperClassesSize: 5
3710 },
3711 {
3712 offsetof(ARMRegisterClassStorage, Regs[1226]) - 115 * sizeof(MCRegisterClass),
3713 offsetof(ARMRegisterClassStorage, BitSets[2091]) - 115 * sizeof(MCRegisterClass),
3714 .NameIdx: 2021,
3715 .RegSizeInBits: 256,
3716 .RegsSize: 8,
3717 .RegSetSize: 37,
3718 .ID: ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
3719 .CopyCost: 1, /* CopyCost */
3720 .Allocatable: true, /* Allocatable */
3721 .BaseClass: false,
3722 offsetof(ARMRegisterClassStorage, SubClassMasks[2715]) - 115 * sizeof(MCRegisterClass),
3723 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 115 * sizeof(MCRegisterClass),
3724 .LaneMask: LaneBitmask(0x00000000000003FC),
3725 .AllocationPriority: 0,
3726 .GlobalPriority: false,
3727 .TSFlags: 0x00, /* TSFlags */
3728 .SpillStackID: 0, /* SpillStackID */
3729 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3730 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3731 offsetof(ARMRegisterClassStorage, SuperClasses[609]) - 115 * sizeof(MCRegisterClass),
3732 .SuperClassesSize: 3
3733 },
3734 {
3735 offsetof(ARMRegisterClassStorage, Regs[1234]) - 116 * sizeof(MCRegisterClass),
3736 offsetof(ARMRegisterClassStorage, BitSets[2128]) - 116 * sizeof(MCRegisterClass),
3737 .NameIdx: 2,
3738 .RegSizeInBits: 256,
3739 .RegsSize: 8,
3740 .RegSetSize: 20,
3741 .ID: ARM::QQPR_with_ssub_0RegClassID,
3742 .CopyCost: 1, /* CopyCost */
3743 .Allocatable: true, /* Allocatable */
3744 .BaseClass: false,
3745 offsetof(ARMRegisterClassStorage, SubClassMasks[2730]) - 116 * sizeof(MCRegisterClass),
3746 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[84]) - 116 * sizeof(MCRegisterClass),
3747 .LaneMask: LaneBitmask(0x00000000000003FC),
3748 .AllocationPriority: 0,
3749 .GlobalPriority: false,
3750 .TSFlags: 0x00, /* TSFlags */
3751 .SpillStackID: 0, /* SpillStackID */
3752 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3753 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3754 offsetof(ARMRegisterClassStorage, SuperClasses[612]) - 116 * sizeof(MCRegisterClass),
3755 .SuperClassesSize: 4
3756 },
3757 {
3758 offsetof(ARMRegisterClassStorage, Regs[1242]) - 117 * sizeof(MCRegisterClass),
3759 offsetof(ARMRegisterClassStorage, BitSets[2148]) - 117 * sizeof(MCRegisterClass),
3760 .NameIdx: 611,
3761 .RegSizeInBits: 256,
3762 .RegsSize: 7,
3763 .RegSetSize: 36,
3764 .ID: ARM::DQuad_with_dsub_1_in_DPR_8RegClassID,
3765 .CopyCost: 1, /* CopyCost */
3766 .Allocatable: true, /* Allocatable */
3767 .BaseClass: false,
3768 offsetof(ARMRegisterClassStorage, SubClassMasks[2750]) - 117 * sizeof(MCRegisterClass),
3769 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 117 * sizeof(MCRegisterClass),
3770 .LaneMask: LaneBitmask(0x00000000000003FC),
3771 .AllocationPriority: 0,
3772 .GlobalPriority: false,
3773 .TSFlags: 0x00, /* TSFlags */
3774 .SpillStackID: 0, /* SpillStackID */
3775 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3776 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3777 offsetof(ARMRegisterClassStorage, SuperClasses[616]) - 117 * sizeof(MCRegisterClass),
3778 .SuperClassesSize: 6
3779 },
3780 {
3781 offsetof(ARMRegisterClassStorage, Regs[1249]) - 118 * sizeof(MCRegisterClass),
3782 offsetof(ARMRegisterClassStorage, BitSets[2184]) - 118 * sizeof(MCRegisterClass),
3783 .NameIdx: 1795,
3784 .RegSizeInBits: 256,
3785 .RegsSize: 7,
3786 .RegSetSize: 37,
3787 .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
3788 .CopyCost: 1, /* CopyCost */
3789 .Allocatable: true, /* Allocatable */
3790 .BaseClass: false,
3791 offsetof(ARMRegisterClassStorage, SubClassMasks[2780]) - 118 * sizeof(MCRegisterClass),
3792 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 118 * sizeof(MCRegisterClass),
3793 .LaneMask: LaneBitmask(0x00000000000003FC),
3794 .AllocationPriority: 0,
3795 .GlobalPriority: false,
3796 .TSFlags: 0x00, /* TSFlags */
3797 .SpillStackID: 0, /* SpillStackID */
3798 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3799 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3800 offsetof(ARMRegisterClassStorage, SuperClasses[622]) - 118 * sizeof(MCRegisterClass),
3801 .SuperClassesSize: 6
3802 },
3803 {
3804 offsetof(ARMRegisterClassStorage, Regs[1256]) - 119 * sizeof(MCRegisterClass),
3805 offsetof(ARMRegisterClassStorage, BitSets[2221]) - 119 * sizeof(MCRegisterClass),
3806 .NameIdx: 1980,
3807 .RegSizeInBits: 256,
3808 .RegsSize: 7,
3809 .RegSetSize: 20,
3810 .ID: ARM::MQQPRRegClassID,
3811 .CopyCost: 1, /* CopyCost */
3812 .Allocatable: true, /* Allocatable */
3813 .BaseClass: false,
3814 offsetof(ARMRegisterClassStorage, SubClassMasks[2795]) - 119 * sizeof(MCRegisterClass),
3815 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[84]) - 119 * sizeof(MCRegisterClass),
3816 .LaneMask: LaneBitmask(0x00000000000003FC),
3817 .AllocationPriority: 0,
3818 .GlobalPriority: false,
3819 .TSFlags: 0x00, /* TSFlags */
3820 .SpillStackID: 0, /* SpillStackID */
3821 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3822 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3823 offsetof(ARMRegisterClassStorage, SuperClasses[628]) - 119 * sizeof(MCRegisterClass),
3824 .SuperClassesSize: 7
3825 },
3826 {
3827 offsetof(ARMRegisterClassStorage, Regs[1263]) - 120 * sizeof(MCRegisterClass),
3828 offsetof(ARMRegisterClassStorage, BitSets[2241]) - 120 * sizeof(MCRegisterClass),
3829 .NameIdx: 888,
3830 .RegSizeInBits: 256,
3831 .RegsSize: 6,
3832 .RegSetSize: 36,
3833 .ID: ARM::DQuad_with_dsub_2_in_DPR_8RegClassID,
3834 .CopyCost: 1, /* CopyCost */
3835 .Allocatable: true, /* Allocatable */
3836 .BaseClass: false,
3837 offsetof(ARMRegisterClassStorage, SubClassMasks[2815]) - 120 * sizeof(MCRegisterClass),
3838 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 120 * sizeof(MCRegisterClass),
3839 .LaneMask: LaneBitmask(0x00000000000003FC),
3840 .AllocationPriority: 0,
3841 .GlobalPriority: false,
3842 .TSFlags: 0x00, /* TSFlags */
3843 .SpillStackID: 0, /* SpillStackID */
3844 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3845 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3846 offsetof(ARMRegisterClassStorage, SuperClasses[635]) - 120 * sizeof(MCRegisterClass),
3847 .SuperClassesSize: 7
3848 },
3849 {
3850 offsetof(ARMRegisterClassStorage, Regs[1269]) - 121 * sizeof(MCRegisterClass),
3851 offsetof(ARMRegisterClassStorage, BitSets[2277]) - 121 * sizeof(MCRegisterClass),
3852 .NameIdx: 1773,
3853 .RegSizeInBits: 256,
3854 .RegsSize: 6,
3855 .RegSetSize: 37,
3856 .ID: ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
3857 .CopyCost: 1, /* CopyCost */
3858 .Allocatable: true, /* Allocatable */
3859 .BaseClass: false,
3860 offsetof(ARMRegisterClassStorage, SubClassMasks[2845]) - 121 * sizeof(MCRegisterClass),
3861 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 121 * sizeof(MCRegisterClass),
3862 .LaneMask: LaneBitmask(0x00000000000003FC),
3863 .AllocationPriority: 0,
3864 .GlobalPriority: false,
3865 .TSFlags: 0x00, /* TSFlags */
3866 .SpillStackID: 0, /* SpillStackID */
3867 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3868 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3869 offsetof(ARMRegisterClassStorage, SuperClasses[642]) - 121 * sizeof(MCRegisterClass),
3870 .SuperClassesSize: 8
3871 },
3872 {
3873 offsetof(ARMRegisterClassStorage, Regs[1275]) - 122 * sizeof(MCRegisterClass),
3874 offsetof(ARMRegisterClassStorage, BitSets[2314]) - 122 * sizeof(MCRegisterClass),
3875 .NameIdx: 1032,
3876 .RegSizeInBits: 256,
3877 .RegsSize: 5,
3878 .RegSetSize: 36,
3879 .ID: ARM::DQuad_with_dsub_3_in_DPR_8RegClassID,
3880 .CopyCost: 1, /* CopyCost */
3881 .Allocatable: true, /* Allocatable */
3882 .BaseClass: false,
3883 offsetof(ARMRegisterClassStorage, SubClassMasks[2860]) - 122 * sizeof(MCRegisterClass),
3884 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 122 * sizeof(MCRegisterClass),
3885 .LaneMask: LaneBitmask(0x00000000000003FC),
3886 .AllocationPriority: 0,
3887 .GlobalPriority: false,
3888 .TSFlags: 0x00, /* TSFlags */
3889 .SpillStackID: 0, /* SpillStackID */
3890 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3891 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3892 offsetof(ARMRegisterClassStorage, SuperClasses[650]) - 122 * sizeof(MCRegisterClass),
3893 .SuperClassesSize: 8
3894 },
3895 {
3896 offsetof(ARMRegisterClassStorage, Regs[1280]) - 123 * sizeof(MCRegisterClass),
3897 offsetof(ARMRegisterClassStorage, BitSets[2350]) - 123 * sizeof(MCRegisterClass),
3898 .NameIdx: 1842,
3899 .RegSizeInBits: 256,
3900 .RegsSize: 4,
3901 .RegSetSize: 36,
3902 .ID: ARM::DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
3903 .CopyCost: 1, /* CopyCost */
3904 .Allocatable: true, /* Allocatable */
3905 .BaseClass: false,
3906 offsetof(ARMRegisterClassStorage, SubClassMasks[2890]) - 123 * sizeof(MCRegisterClass),
3907 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 123 * sizeof(MCRegisterClass),
3908 .LaneMask: LaneBitmask(0x00000000000003FC),
3909 .AllocationPriority: 0,
3910 .GlobalPriority: false,
3911 .TSFlags: 0x00, /* TSFlags */
3912 .SpillStackID: 0, /* SpillStackID */
3913 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3914 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3915 offsetof(ARMRegisterClassStorage, SuperClasses[658]) - 123 * sizeof(MCRegisterClass),
3916 .SuperClassesSize: 10
3917 },
3918 {
3919 offsetof(ARMRegisterClassStorage, Regs[1284]) - 124 * sizeof(MCRegisterClass),
3920 offsetof(ARMRegisterClassStorage, BitSets[2386]) - 124 * sizeof(MCRegisterClass),
3921 .NameIdx: 1145,
3922 .RegSizeInBits: 256,
3923 .RegsSize: 4,
3924 .RegSetSize: 20,
3925 .ID: ARM::MQQPR_with_qsub_0_in_QPR_8RegClassID,
3926 .CopyCost: 1, /* CopyCost */
3927 .Allocatable: true, /* Allocatable */
3928 .BaseClass: false,
3929 offsetof(ARMRegisterClassStorage, SubClassMasks[2905]) - 124 * sizeof(MCRegisterClass),
3930 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[84]) - 124 * sizeof(MCRegisterClass),
3931 .LaneMask: LaneBitmask(0x00000000000003FC),
3932 .AllocationPriority: 0,
3933 .GlobalPriority: false,
3934 .TSFlags: 0x00, /* TSFlags */
3935 .SpillStackID: 0, /* SpillStackID */
3936 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3937 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3938 offsetof(ARMRegisterClassStorage, SuperClasses[668]) - 124 * sizeof(MCRegisterClass),
3939 .SuperClassesSize: 10
3940 },
3941 {
3942 offsetof(ARMRegisterClassStorage, Regs[1288]) - 125 * sizeof(MCRegisterClass),
3943 offsetof(ARMRegisterClassStorage, BitSets[2406]) - 125 * sizeof(MCRegisterClass),
3944 .NameIdx: 1230,
3945 .RegSizeInBits: 256,
3946 .RegsSize: 3,
3947 .RegSetSize: 36,
3948 .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID,
3949 .CopyCost: 1, /* CopyCost */
3950 .Allocatable: true, /* Allocatable */
3951 .BaseClass: false,
3952 offsetof(ARMRegisterClassStorage, SubClassMasks[2925]) - 125 * sizeof(MCRegisterClass),
3953 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 125 * sizeof(MCRegisterClass),
3954 .LaneMask: LaneBitmask(0x00000000000003FC),
3955 .AllocationPriority: 0,
3956 .GlobalPriority: false,
3957 .TSFlags: 0x00, /* TSFlags */
3958 .SpillStackID: 0, /* SpillStackID */
3959 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3960 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3961 offsetof(ARMRegisterClassStorage, SuperClasses[678]) - 125 * sizeof(MCRegisterClass),
3962 .SuperClassesSize: 13
3963 },
3964 {
3965 offsetof(ARMRegisterClassStorage, Regs[1291]) - 126 * sizeof(MCRegisterClass),
3966 offsetof(ARMRegisterClassStorage, BitSets[2442]) - 126 * sizeof(MCRegisterClass),
3967 .NameIdx: 718,
3968 .RegSizeInBits: 256,
3969 .RegsSize: 3,
3970 .RegSetSize: 19,
3971 .ID: ARM::MQQPR_with_dsub_2_in_DPR_8RegClassID,
3972 .CopyCost: 1, /* CopyCost */
3973 .Allocatable: true, /* Allocatable */
3974 .BaseClass: false,
3975 offsetof(ARMRegisterClassStorage, SubClassMasks[2940]) - 126 * sizeof(MCRegisterClass),
3976 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[84]) - 126 * sizeof(MCRegisterClass),
3977 .LaneMask: LaneBitmask(0x00000000000003FC),
3978 .AllocationPriority: 0,
3979 .GlobalPriority: false,
3980 .TSFlags: 0x00, /* TSFlags */
3981 .SpillStackID: 0, /* SpillStackID */
3982 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3983 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3984 offsetof(ARMRegisterClassStorage, SuperClasses[691]) - 126 * sizeof(MCRegisterClass),
3985 .SuperClassesSize: 13
3986 },
3987 {
3988 offsetof(ARMRegisterClassStorage, Regs[1294]) - 127 * sizeof(MCRegisterClass),
3989 offsetof(ARMRegisterClassStorage, BitSets[2461]) - 127 * sizeof(MCRegisterClass),
3990 .NameIdx: 915,
3991 .RegSizeInBits: 256,
3992 .RegsSize: 2,
3993 .RegSetSize: 36,
3994 .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID,
3995 .CopyCost: 1, /* CopyCost */
3996 .Allocatable: true, /* Allocatable */
3997 .BaseClass: false,
3998 offsetof(ARMRegisterClassStorage, SubClassMasks[2960]) - 127 * sizeof(MCRegisterClass),
3999 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 127 * sizeof(MCRegisterClass),
4000 .LaneMask: LaneBitmask(0x00000000000003FC),
4001 .AllocationPriority: 0,
4002 .GlobalPriority: false,
4003 .TSFlags: 0x00, /* TSFlags */
4004 .SpillStackID: 0, /* SpillStackID */
4005 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4006 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4007 offsetof(ARMRegisterClassStorage, SuperClasses[704]) - 127 * sizeof(MCRegisterClass),
4008 .SuperClassesSize: 15
4009 },
4010 {
4011 offsetof(ARMRegisterClassStorage, Regs[1296]) - 128 * sizeof(MCRegisterClass),
4012 offsetof(ARMRegisterClassStorage, BitSets[2497]) - 128 * sizeof(MCRegisterClass),
4013 .NameIdx: 1987,
4014 .RegSizeInBits: 512,
4015 .RegsSize: 13,
4016 .RegSetSize: 23,
4017 .ID: ARM::QQQQPRRegClassID,
4018 .CopyCost: 1, /* CopyCost */
4019 .Allocatable: true, /* Allocatable */
4020 .BaseClass: false,
4021 offsetof(ARMRegisterClassStorage, SubClassMasks[2975]) - 128 * sizeof(MCRegisterClass),
4022 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 128 * sizeof(MCRegisterClass),
4023 .LaneMask: LaneBitmask(0x000000000003FFFC),
4024 .AllocationPriority: 0,
4025 .GlobalPriority: false,
4026 .TSFlags: 0x00, /* TSFlags */
4027 .SpillStackID: 0, /* SpillStackID */
4028 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4029 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4030 offsetof(ARMRegisterClassStorage, SuperClasses[719]) - 128 * sizeof(MCRegisterClass),
4031 .SuperClassesSize: 0
4032 },
4033 {
4034 offsetof(ARMRegisterClassStorage, Regs[1309]) - 129 * sizeof(MCRegisterClass),
4035 offsetof(ARMRegisterClassStorage, BitSets[2520]) - 129 * sizeof(MCRegisterClass),
4036 .NameIdx: 0,
4037 .RegSizeInBits: 512,
4038 .RegsSize: 8,
4039 .RegSetSize: 22,
4040 .ID: ARM::QQQQPR_with_ssub_0RegClassID,
4041 .CopyCost: 1, /* CopyCost */
4042 .Allocatable: true, /* Allocatable */
4043 .BaseClass: false,
4044 offsetof(ARMRegisterClassStorage, SubClassMasks[2980]) - 129 * sizeof(MCRegisterClass),
4045 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 129 * sizeof(MCRegisterClass),
4046 .LaneMask: LaneBitmask(0x000000000003FFFC),
4047 .AllocationPriority: 0,
4048 .GlobalPriority: false,
4049 .TSFlags: 0x00, /* TSFlags */
4050 .SpillStackID: 0, /* SpillStackID */
4051 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4052 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4053 offsetof(ARMRegisterClassStorage, SuperClasses[719]) - 129 * sizeof(MCRegisterClass),
4054 .SuperClassesSize: 1
4055 },
4056 {
4057 offsetof(ARMRegisterClassStorage, Regs[1317]) - 130 * sizeof(MCRegisterClass),
4058 offsetof(ARMRegisterClassStorage, BitSets[2542]) - 130 * sizeof(MCRegisterClass),
4059 .NameIdx: 296,
4060 .RegSizeInBits: 512,
4061 .RegsSize: 7,
4062 .RegSetSize: 22,
4063 .ID: ARM::QQQQPR_with_ssub_4RegClassID,
4064 .CopyCost: 1, /* CopyCost */
4065 .Allocatable: true, /* Allocatable */
4066 .BaseClass: false,
4067 offsetof(ARMRegisterClassStorage, SubClassMasks[2985]) - 130 * sizeof(MCRegisterClass),
4068 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 130 * sizeof(MCRegisterClass),
4069 .LaneMask: LaneBitmask(0x000000000003FFFC),
4070 .AllocationPriority: 0,
4071 .GlobalPriority: false,
4072 .TSFlags: 0x00, /* TSFlags */
4073 .SpillStackID: 0, /* SpillStackID */
4074 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4075 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4076 offsetof(ARMRegisterClassStorage, SuperClasses[720]) - 130 * sizeof(MCRegisterClass),
4077 .SuperClassesSize: 2
4078 },
4079 {
4080 offsetof(ARMRegisterClassStorage, Regs[1324]) - 131 * sizeof(MCRegisterClass),
4081 offsetof(ARMRegisterClassStorage, BitSets[2564]) - 131 * sizeof(MCRegisterClass),
4082 .NameIdx: 1371,
4083 .RegSizeInBits: 512,
4084 .RegsSize: 6,
4085 .RegSetSize: 22,
4086 .ID: ARM::QQQQPR_with_ssub_8RegClassID,
4087 .CopyCost: 1, /* CopyCost */
4088 .Allocatable: true, /* Allocatable */
4089 .BaseClass: false,
4090 offsetof(ARMRegisterClassStorage, SubClassMasks[2990]) - 131 * sizeof(MCRegisterClass),
4091 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 131 * sizeof(MCRegisterClass),
4092 .LaneMask: LaneBitmask(0x000000000003FFFC),
4093 .AllocationPriority: 0,
4094 .GlobalPriority: false,
4095 .TSFlags: 0x00, /* TSFlags */
4096 .SpillStackID: 0, /* SpillStackID */
4097 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4098 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4099 offsetof(ARMRegisterClassStorage, SuperClasses[722]) - 131 * sizeof(MCRegisterClass),
4100 .SuperClassesSize: 3
4101 },
4102 {
4103 offsetof(ARMRegisterClassStorage, Regs[1330]) - 132 * sizeof(MCRegisterClass),
4104 offsetof(ARMRegisterClassStorage, BitSets[2586]) - 132 * sizeof(MCRegisterClass),
4105 .NameIdx: 1986,
4106 .RegSizeInBits: 512,
4107 .RegsSize: 5,
4108 .RegSetSize: 22,
4109 .ID: ARM::MQQQQPRRegClassID,
4110 .CopyCost: 1, /* CopyCost */
4111 .Allocatable: true, /* Allocatable */
4112 .BaseClass: false,
4113 offsetof(ARMRegisterClassStorage, SubClassMasks[2995]) - 132 * sizeof(MCRegisterClass),
4114 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 132 * sizeof(MCRegisterClass),
4115 .LaneMask: LaneBitmask(0x000000000003FFFC),
4116 .AllocationPriority: 0,
4117 .GlobalPriority: false,
4118 .TSFlags: 0x00, /* TSFlags */
4119 .SpillStackID: 0, /* SpillStackID */
4120 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4121 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4122 offsetof(ARMRegisterClassStorage, SuperClasses[725]) - 132 * sizeof(MCRegisterClass),
4123 .SuperClassesSize: 4
4124 },
4125 {
4126 offsetof(ARMRegisterClassStorage, Regs[1335]) - 133 * sizeof(MCRegisterClass),
4127 offsetof(ARMRegisterClassStorage, BitSets[2608]) - 133 * sizeof(MCRegisterClass),
4128 .NameIdx: 1121,
4129 .RegSizeInBits: 512,
4130 .RegsSize: 4,
4131 .RegSetSize: 21,
4132 .ID: ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID,
4133 .CopyCost: 1, /* CopyCost */
4134 .Allocatable: true, /* Allocatable */
4135 .BaseClass: false,
4136 offsetof(ARMRegisterClassStorage, SubClassMasks[3000]) - 133 * sizeof(MCRegisterClass),
4137 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 133 * sizeof(MCRegisterClass),
4138 .LaneMask: LaneBitmask(0x000000000003FFFC),
4139 .AllocationPriority: 0,
4140 .GlobalPriority: false,
4141 .TSFlags: 0x00, /* TSFlags */
4142 .SpillStackID: 0, /* SpillStackID */
4143 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4144 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4145 offsetof(ARMRegisterClassStorage, SuperClasses[729]) - 133 * sizeof(MCRegisterClass),
4146 .SuperClassesSize: 5
4147 },
4148 {
4149 offsetof(ARMRegisterClassStorage, Regs[1339]) - 134 * sizeof(MCRegisterClass),
4150 offsetof(ARMRegisterClassStorage, BitSets[2629]) - 134 * sizeof(MCRegisterClass),
4151 .NameIdx: 694,
4152 .RegSizeInBits: 512,
4153 .RegsSize: 3,
4154 .RegSetSize: 21,
4155 .ID: ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8RegClassID,
4156 .CopyCost: 1, /* CopyCost */
4157 .Allocatable: true, /* Allocatable */
4158 .BaseClass: false,
4159 offsetof(ARMRegisterClassStorage, SubClassMasks[3005]) - 134 * sizeof(MCRegisterClass),
4160 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 134 * sizeof(MCRegisterClass),
4161 .LaneMask: LaneBitmask(0x000000000003FFFC),
4162 .AllocationPriority: 0,
4163 .GlobalPriority: false,
4164 .TSFlags: 0x00, /* TSFlags */
4165 .SpillStackID: 0, /* SpillStackID */
4166 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4167 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4168 offsetof(ARMRegisterClassStorage, SuperClasses[734]) - 134 * sizeof(MCRegisterClass),
4169 .SuperClassesSize: 6
4170 },
4171 {
4172 offsetof(ARMRegisterClassStorage, Regs[1342]) - 135 * sizeof(MCRegisterClass),
4173 offsetof(ARMRegisterClassStorage, BitSets[2650]) - 135 * sizeof(MCRegisterClass),
4174 .NameIdx: 1201,
4175 .RegSizeInBits: 512,
4176 .RegsSize: 2,
4177 .RegSetSize: 21,
4178 .ID: ARM::MQQQQPR_with_qsub_2_in_QPR_8RegClassID,
4179 .CopyCost: 1, /* CopyCost */
4180 .Allocatable: true, /* Allocatable */
4181 .BaseClass: false,
4182 offsetof(ARMRegisterClassStorage, SubClassMasks[3010]) - 135 * sizeof(MCRegisterClass),
4183 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 135 * sizeof(MCRegisterClass),
4184 .LaneMask: LaneBitmask(0x000000000003FFFC),
4185 .AllocationPriority: 0,
4186 .GlobalPriority: false,
4187 .TSFlags: 0x00, /* TSFlags */
4188 .SpillStackID: 0, /* SpillStackID */
4189 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4190 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4191 offsetof(ARMRegisterClassStorage, SuperClasses[740]) - 135 * sizeof(MCRegisterClass),
4192 .SuperClassesSize: 7
4193 },
4194 {
4195 offsetof(ARMRegisterClassStorage, Regs[1344]) - 136 * sizeof(MCRegisterClass),
4196 offsetof(ARMRegisterClassStorage, BitSets[2671]) - 136 * sizeof(MCRegisterClass),
4197 .NameIdx: 745,
4198 .RegSizeInBits: 512,
4199 .RegsSize: 1,
4200 .RegSetSize: 21,
4201 .ID: ARM::MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8RegClassID,
4202 .CopyCost: 1, /* CopyCost */
4203 .Allocatable: true, /* Allocatable */
4204 .BaseClass: false,
4205 offsetof(ARMRegisterClassStorage, SubClassMasks[3015]) - 136 * sizeof(MCRegisterClass),
4206 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 136 * sizeof(MCRegisterClass),
4207 .LaneMask: LaneBitmask(0x000000000003FFFC),
4208 .AllocationPriority: 0,
4209 .GlobalPriority: false,
4210 .TSFlags: 0x00, /* TSFlags */
4211 .SpillStackID: 0, /* SpillStackID */
4212 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4213 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4214 offsetof(ARMRegisterClassStorage, SuperClasses[747]) - 136 * sizeof(MCRegisterClass),
4215 .SuperClassesSize: 8
4216 },
4217 },
4218 .Regs: {
4219 /* 0 */ ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31,
4220 /* 32 */ ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::VPR,
4221 /* 97 */ ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31,
4222 /* 129 */ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15,
4223 /* 145 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
4224 /* 161 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV,
4225 /* 177 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::ZR,
4226 /* 193 */ ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15,
4227 /* 209 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
4228 /* 224 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::PC,
4229 /* 239 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR_NZCV,
4230 /* 254 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR,
4231 /* 269 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::ZR,
4232 /* 284 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC,
4233 /* 298 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
4234 /* 312 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP,
4235 /* 325 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::PC,
4236 /* 338 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11,
4237 /* 350 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC,
4238 /* 359 */ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7,
4239 /* 367 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
4240 /* 375 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4241 /* 383 */ ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, ARM::R12, ARM::LR,
4242 /* 391 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
4243 /* 398 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::PC,
4244 /* 405 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC,
4245 /* 411 */ ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
4246 /* 417 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
4247 /* 423 */ ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
4248 /* 429 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP,
4249 /* 434 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::PC,
4250 /* 439 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12,
4251 /* 444 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11,
4252 /* 448 */ ARM::R8, ARM::R10, ARM::R12, ARM::LR,
4253 /* 452 */ ARM::R0, ARM::R2, ARM::R4, ARM::R6,
4254 /* 456 */ ARM::R1, ARM::R3, ARM::R5, ARM::R7,
4255 /* 460 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4256 /* 464 */ ARM::R0, ARM::R2, ARM::R12,
4257 /* 467 */ ARM::FPSCR, ARM::FPEXC,
4258 /* 469 */ ARM::R8, ARM::R10,
4259 /* 471 */ ARM::R9, ARM::R11,
4260 /* 473 */ ARM::R0, ARM::R2,
4261 /* 475 */ ARM::R1, ARM::R3,
4262 /* 477 */ ARM::CPSR,
4263 /* 478 */ ARM::FPCXTNS,
4264 /* 479 */ ARM::LR,
4265 /* 480 */ ARM::SP,
4266 /* 481 */ ARM::VPR,
4267 /* 482 */ ARM::FPSCR_NZCV,
4268 /* 483 */ ARM::PC,
4269 /* 484 */ ARM::R12,
4270 /* 485 */ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31,
4271 /* 517 */ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15,
4272 /* 533 */ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7,
4273 /* 541 */ ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, ARM::R12_SP,
4274 /* 548 */ ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11,
4275 /* 554 */ ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
4276 /* 558 */ ARM::R8_R9, ARM::R10_R11, ARM::R12_SP,
4277 /* 561 */ ARM::R0_R1, ARM::R2_R3, ARM::R12_SP,
4278 /* 564 */ ARM::R0_R1, ARM::R2_R3,
4279 /* 566 */ ARM::R8_R9, ARM::R10_R11,
4280 /* 568 */ ARM::R12_SP,
4281 /* 569 */ ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D28_D30, ARM::D29_D31,
4282 /* 599 */ ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
4283 /* 615 */ ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15,
4284 /* 629 */ ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
4285 /* 637 */ ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7,
4286 /* 643 */ ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q15,
4287 /* 674 */ ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16,
4288 /* 690 */ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15,
4289 /* 706 */ ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7,
4290 /* 721 */ ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8,
4291 /* 729 */ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
4292 /* 737 */ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
4293 /* 745 */ ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3,
4294 /* 752 */ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
4295 /* 756 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, ARM::D16_D17_D18, ARM::D17_D18_D19, ARM::D18_D19_D20, ARM::D19_D20_D21, ARM::D20_D21_D22, ARM::D21_D22_D23, ARM::D22_D23_D24, ARM::D23_D24_D25, ARM::D24_D25_D26, ARM::D25_D26_D27, ARM::D26_D27_D28, ARM::D27_D28_D29, ARM::D28_D29_D30, ARM::D29_D30_D31,
4296 /* 786 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31,
4297 /* 814 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19,
4298 /* 830 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17,
4299 /* 846 */ ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, ARM::D16_D17_D18, ARM::D18_D19_D20, ARM::D20_D21_D22, ARM::D22_D23_D24, ARM::D24_D25_D26, ARM::D26_D27_D28, ARM::D28_D29_D30,
4300 /* 861 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16,
4301 /* 876 */ ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, ARM::D17_D18_D19, ARM::D19_D20_D21, ARM::D21_D22_D23, ARM::D23_D24_D25, ARM::D25_D26_D27, ARM::D27_D28_D29, ARM::D29_D30_D31,
4302 /* 891 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17,
4303 /* 905 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15,
4304 /* 919 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15,
4305 /* 931 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11,
4306 /* 939 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9,
4307 /* 947 */ ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16,
4308 /* 955 */ ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17,
4309 /* 963 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8,
4310 /* 970 */ ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15,
4311 /* 977 */ ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14,
4312 /* 984 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9,
4313 /* 990 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7,
4314 /* 996 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7,
4315 /* 1000 */ ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9,
4316 /* 1004 */ ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8,
4317 /* 1008 */ ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6,
4318 /* 1011 */ ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7,
4319 /* 1014 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31,
4320 /* 1042 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19,
4321 /* 1058 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17,
4322 /* 1072 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15,
4323 /* 1084 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11,
4324 /* 1092 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9,
4325 /* 1098 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7,
4326 /* 1102 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, ARM::Q8_Q9, ARM::D17_D18_D19_D20, ARM::Q9_Q10, ARM::D19_D20_D21_D22, ARM::Q10_Q11, ARM::D21_D22_D23_D24, ARM::Q11_Q12, ARM::D23_D24_D25_D26, ARM::Q12_Q13, ARM::D25_D26_D27_D28, ARM::Q13_Q14, ARM::D27_D28_D29_D30, ARM::Q14_Q15,
4327 /* 1131 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18,
4328 /* 1147 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8,
4329 /* 1162 */ ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15,
4330 /* 1177 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, ARM::D17_D18_D19_D20, ARM::D19_D20_D21_D22, ARM::D21_D22_D23_D24, ARM::D23_D24_D25_D26, ARM::D25_D26_D27_D28, ARM::D27_D28_D29_D30,
4331 /* 1191 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16,
4332 /* 1205 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7,
4333 /* 1218 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10,
4334 /* 1226 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18,
4335 /* 1234 */ ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8,
4336 /* 1242 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4,
4337 /* 1249 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16,
4338 /* 1256 */ ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7,
4339 /* 1263 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8,
4340 /* 1269 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14,
4341 /* 1275 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3,
4342 /* 1280 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10,
4343 /* 1284 */ ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
4344 /* 1288 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8,
4345 /* 1291 */ ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3,
4346 /* 1294 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6,
4347 /* 1296 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15,
4348 /* 1309 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10,
4349 /* 1317 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9,
4350 /* 1324 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8,
4351 /* 1330 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7,
4352 /* 1335 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6,
4353 /* 1339 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
4354 /* 1342 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4,
4355 /* 1344 */ ARM::Q0_Q1_Q2_Q3,
4356 },
4357 .BitSets: {
4358 /* 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
4359 /* 15 */ 0x00, 0x00, 0xe8, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
4360 /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
4361 /* 45 */ 0x00, 0x00, 0xe0, 0xff, 0x1f,
4362 /* 50 */ 0x00, 0xc0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
4363 /* 61 */ 0x04, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
4364 /* 72 */ 0x00, 0x40, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
4365 /* 83 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4366 /* 96 */ 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
4367 /* 107 */ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
4368 /* 118 */ 0x04, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
4369 /* 129 */ 0x02, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
4370 /* 140 */ 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
4371 /* 151 */ 0x00, 0x80, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3f,
4372 /* 162 */ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
4373 /* 173 */ 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3f,
4374 /* 184 */ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3f,
4375 /* 195 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3f,
4376 /* 206 */ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
4377 /* 217 */ 0x00, 0x00, 0xe0, 0x1f,
4378 /* 221 */ 0x00, 0xc0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
4379 /* 232 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
4380 /* 243 */ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55,
4381 /* 254 */ 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
4382 /* 265 */ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
4383 /* 276 */ 0x00, 0x80, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
4384 /* 287 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x15,
4385 /* 298 */ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
4386 /* 309 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x2a,
4387 /* 320 */ 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
4388 /* 331 */ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
4389 /* 342 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40,
4390 /* 353 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
4391 /* 364 */ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54,
4392 /* 375 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x01,
4393 /* 386 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x02,
4394 /* 397 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
4395 /* 407 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x40,
4396 /* 418 */ 0x40, 0x01,
4397 /* 420 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14,
4398 /* 431 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28,
4399 /* 442 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14,
4400 /* 452 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28,
4401 /* 462 */ 0x08,
4402 /* 463 */ 0x10,
4403 /* 464 */ 0x00, 0x40,
4404 /* 466 */ 0x00, 0x00, 0x02,
4405 /* 469 */ 0x00, 0x00, 0x08,
4406 /* 472 */ 0x00, 0x02,
4407 /* 474 */ 0x00, 0x80,
4408 /* 476 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
4409 /* 487 */ 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
4410 /* 494 */ 0x00, 0x00, 0xe0, 0xff, 0x1f,
4411 /* 499 */ 0x00, 0x00, 0xe0, 0x1f,
4412 /* 503 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
4413 /* 526 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e,
4414 /* 549 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
4415 /* 572 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
4416 /* 595 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86,
4417 /* 618 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,
4418 /* 641 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
4419 /* 664 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
4420 /* 687 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f,
4421 /* 706 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4422 /* 723 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f,
4423 /* 740 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4424 /* 756 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f,
4425 /* 772 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
4426 /* 808 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
4427 /* 843 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
4428 /* 853 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
4429 /* 888 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
4430 /* 922 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
4431 /* 931 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
4432 /* 940 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
4433 /* 974 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
4434 /* 982 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f,
4435 /* 1009 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
4436 /* 1040 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
4437 /* 1069 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
4438 /* 1094 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15,
4439 /* 1121 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f,
4440 /* 1146 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a,
4441 /* 1173 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
4442 /* 1202 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f,
4443 /* 1227 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
4444 /* 1256 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
4445 /* 1284 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
4446 /* 1308 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
4447 /* 1333 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa,
4448 /* 1358 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
4449 /* 1382 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a,
4450 /* 1407 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15,
4451 /* 1432 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
4452 /* 1460 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
4453 /* 1484 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
4454 /* 1512 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa,
4455 /* 1536 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55,
4456 /* 1560 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15,
4457 /* 1584 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a,
4458 /* 1608 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
4459 /* 1639 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
4460 /* 1668 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
4461 /* 1697 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
4462 /* 1726 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
4463 /* 1754 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
4464 /* 1782 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
4465 /* 1810 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
4466 /* 1848 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
4467 /* 1885 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
4468 /* 1922 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
4469 /* 1943 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
4470 /* 1981 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
4471 /* 2018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
4472 /* 2055 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
4473 /* 2091 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
4474 /* 2128 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
4475 /* 2148 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
4476 /* 2184 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
4477 /* 2221 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
4478 /* 2241 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
4479 /* 2277 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
4480 /* 2314 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
4481 /* 2350 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
4482 /* 2386 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
4483 /* 2406 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
4484 /* 2442 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
4485 /* 2461 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
4486 /* 2497 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
4487 /* 2520 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
4488 /* 2542 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
4489 /* 2564 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03,
4490 /* 2586 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01,
4491 /* 2608 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
4492 /* 2629 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
4493 /* 2650 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
4494 /* 2671 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
4495 },
4496 .SubClassMasks: {
4497 // 0 HPR
4498 0x00000085, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4499 0x00080008, 0x80300000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // ssub_0
4500 0x00080008, 0x80300000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // ssub_1
4501 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // ssub_2
4502 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // ssub_3
4503 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // ssub_4
4504 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // ssub_5
4505 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_6
4506 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_7
4507 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_8
4508 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_9
4509 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_10
4510 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_11
4511 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_12
4512 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_13
4513 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_14
4514 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_15
4515 // 85 FPWithVPR
4516 0x0008008e, 0x00388000, 0x00000000, 0x00000000, 0x00000000,
4517 0x00000000, 0xc0000000, 0xffffffff, 0xffffffff, 0x000001ff, // dsub_0
4518 0x00000000, 0x00000000, 0x5f979ff8, 0xfffff80f, 0x000001ff, // dsub_1
4519 0x00000000, 0xc0000000, 0xfffff007, 0xffffffff, 0x000001ff, // dsub_2
4520 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x000001ff, // dsub_3
4521 0x00000000, 0x00000000, 0xa0686000, 0x000007f0, 0x000001ff, // dsub_4
4522 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_5
4523 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_6
4524 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_7
4525 0x00080008, 0x80300000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // ssub_0
4526 0x00080008, 0x80300000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // ssub_1
4527 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // ssub_2
4528 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // ssub_3
4529 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // ssub_4
4530 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // ssub_5
4531 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_6
4532 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_7
4533 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_8
4534 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_9
4535 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_10
4536 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_11
4537 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_12
4538 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_13
4539 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_14
4540 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_15
4541 // 210 SPR
4542 0x00000084, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4543 0x00080008, 0x80300000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // ssub_0
4544 0x00080008, 0x80300000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // ssub_1
4545 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // ssub_2
4546 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // ssub_3
4547 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // ssub_4
4548 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // ssub_5
4549 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_6
4550 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_7
4551 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_8
4552 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_9
4553 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_10
4554 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_11
4555 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_12
4556 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_13
4557 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_14
4558 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_15
4559 // 295 FPWithVPR_with_ssub_0
4560 0x00080008, 0x00300000, 0x00000000, 0x00000000, 0x00000000,
4561 0x00000000, 0x80000000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // dsub_0
4562 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // dsub_1
4563 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // dsub_2
4564 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // dsub_3
4565 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // dsub_4
4566 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // dsub_5
4567 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_6
4568 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_7
4569 // 340 GPR
4570 0xfff7e310, 0x000667bf, 0x00000000, 0x00000000, 0x00000000,
4571 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4572 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4573 // 355 GPRwithAPSR
4574 0xbce2c520, 0x000467bf, 0x00000000, 0x00000000, 0x00000000,
4575 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4576 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4577 // 370 GPRwithZR
4578 0xbce2d140, 0x000467bf, 0x00000000, 0x00000000, 0x00000000,
4579 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4580 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4581 // 385 SPR_8
4582 0x00000080, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4583 0x00080000, 0x00200000, 0xe4c00c86, 0xfd24070f, 0x000001e0, // ssub_0
4584 0x00080000, 0x00200000, 0xe4c00c86, 0xfd24070f, 0x000001e0, // ssub_1
4585 0x00000000, 0x00000000, 0x44000c00, 0xf520000e, 0x000001e0, // ssub_2
4586 0x00000000, 0x00000000, 0x44000c00, 0xf520000e, 0x000001e0, // ssub_3
4587 0x00000000, 0x00000000, 0xe0000004, 0xe500060c, 0x000001c0, // ssub_4
4588 0x00000000, 0x00000000, 0xe0000004, 0xe500060c, 0x000001c0, // ssub_5
4589 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // ssub_6
4590 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // ssub_7
4591 0x00000000, 0x00000000, 0x80000000, 0x00000400, 0x00000180, // ssub_8
4592 0x00000000, 0x00000000, 0x80000000, 0x00000400, 0x00000180, // ssub_9
4593 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_10
4594 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_11
4595 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_12
4596 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_13
4597 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_14
4598 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_15
4599 // 470 GPRnopc
4600 0xbce2c100, 0x000467bf, 0x00000000, 0x00000000, 0x00000000,
4601 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4602 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4603 // 485 GPRnosp
4604 0xdd674200, 0x000627bf, 0x00000000, 0x00000000, 0x00000000,
4605 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4606 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4607 // 500 GPRwithAPSR_NZCVnosp
4608 0x9c624400, 0x000427bf, 0x00000000, 0x00000000, 0x00000000,
4609 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4610 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4611 // 515 GPRwithAPSRnosp
4612 0x9c624800, 0x000427bf, 0x00000000, 0x00000000, 0x00000000,
4613 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4614 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4615 // 530 GPRwithZRnosp
4616 0x9c625000, 0x000427bf, 0x00000000, 0x00000000, 0x00000000,
4617 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4618 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4619 // 545 GPRnoip
4620 0x7627a000, 0x0002479d, 0x00000000, 0x00000000, 0x00000000,
4621 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4622 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4623 // 560 rGPR
4624 0x9c624000, 0x000427bf, 0x00000000, 0x00000000, 0x00000000,
4625 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4626 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4627 // 575 GPRnoip_and_GPRnopc
4628 0x34228000, 0x0000479d, 0x00000000, 0x00000000, 0x00000000,
4629 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4630 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4631 // 590 GPRnoip_and_GPRnosp
4632 0x54270000, 0x0002079d, 0x00000000, 0x00000000, 0x00000000,
4633 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4634 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4635 // 605 GPRnoip_and_GPRwithAPSR_NZCVnosp
4636 0x14220000, 0x0000079d, 0x00000000, 0x00000000, 0x00000000,
4637 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4638 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4639 // 620 tGPRwithpc
4640 0x00240000, 0x0002061c, 0x00000000, 0x00000000, 0x00000000,
4641 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4642 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4643 // 635 FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8
4644 0x00080000, 0x00200000, 0x00000000, 0x00000000, 0x00000000,
4645 0x00000000, 0x00000000, 0xe4c00c86, 0xfd24070f, 0x000001e0, // dsub_0
4646 0x00000000, 0x00000000, 0x44000c00, 0xf520000e, 0x000001e0, // dsub_1
4647 0x00000000, 0x00000000, 0xe0000004, 0xe500060c, 0x000001c0, // dsub_2
4648 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // dsub_3
4649 0x00000000, 0x00000000, 0x80000000, 0x00000400, 0x00000180, // dsub_4
4650 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // dsub_5
4651 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_6
4652 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_7
4653 // 680 hGPR
4654 0x6b900000, 0x00066183, 0x00000000, 0x00000000, 0x00000000,
4655 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4656 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4657 // 695 tGPR
4658 0x00200000, 0x0000061c, 0x00000000, 0x00000000, 0x00000000,
4659 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4660 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4661 // 710 tGPREven
4662 0x04400000, 0x000422a6, 0x00000000, 0x00000000, 0x00000000,
4663 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4664 // 720 GPRnopc_and_hGPR
4665 0x28800000, 0x00046183, 0x00000000, 0x00000000, 0x00000000,
4666 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4667 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4668 // 735 GPRnosp_and_hGPR
4669 0x49000000, 0x00062183, 0x00000000, 0x00000000, 0x00000000,
4670 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4671 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4672 // 750 GPRnoip_and_hGPR
4673 0x62000000, 0x00024181, 0x00000000, 0x00000000, 0x00000000,
4674 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4675 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4676 // 765 GPRnoip_and_tGPREven
4677 0x04000000, 0x00000284, 0x00000000, 0x00000000, 0x00000000,
4678 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4679 // 775 GPRnosp_and_GPRnopc_and_hGPR
4680 0x08000000, 0x00042183, 0x00000000, 0x00000000, 0x00000000,
4681 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4682 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4683 // 790 tGPROdd
4684 0x10000000, 0x00000508, 0x00000000, 0x00000000, 0x00000000,
4685 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4686 // 800 GPRnopc_and_GPRnoip_and_hGPR
4687 0x20000000, 0x00004181, 0x00000000, 0x00000000, 0x00000000,
4688 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4689 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4690 // 815 GPRnosp_and_GPRnoip_and_hGPR
4691 0x40000000, 0x00020181, 0x00000000, 0x00000000, 0x00000000,
4692 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4693 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4694 // 830 tcGPR
4695 0x80000000, 0x00040630, 0x00000000, 0x00000000, 0x00000000,
4696 0x00000000, 0x2c000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4697 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4698 // 845 GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR
4699 0x00000000, 0x00000181, 0x00000000, 0x00000000, 0x00000000,
4700 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4701 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4702 // 860 hGPR_and_tGPREven
4703 0x00000000, 0x00042082, 0x00000000, 0x00000000, 0x00000000,
4704 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4705 // 870 tGPR_and_tGPREven
4706 0x00000000, 0x00000204, 0x00000000, 0x00000000, 0x00000000,
4707 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4708 // 880 tGPR_and_tGPROdd
4709 0x00000000, 0x00000408, 0x00000000, 0x00000000, 0x00000000,
4710 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4711 // 890 tcGPRnotr12
4712 0x00000000, 0x00000610, 0x00000000, 0x00000000, 0x00000000,
4713 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4714 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4715 // 905 tGPREven_and_tcGPR
4716 0x00000000, 0x00040220, 0x00000000, 0x00000000, 0x00000000,
4717 0x00000000, 0x2c000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4718 // 915 FP_STATUS_REGS
4719 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00000000,
4720 // 920 hGPR_and_GPRnoip_and_tGPREven
4721 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
4722 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4723 // 930 hGPR_and_tGPROdd
4724 0x00000000, 0x00000100, 0x00000000, 0x00000000, 0x00000000,
4725 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4726 // 940 tGPREven_and_tcGPRnotr12
4727 0x00000000, 0x00000200, 0x00000000, 0x00000000, 0x00000000,
4728 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4729 // 950 tGPROdd_and_tcGPR
4730 0x00000000, 0x00000400, 0x00000000, 0x00000000, 0x00000000,
4731 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4732 // 960 CCR
4733 0x00000000, 0x00000800, 0x00000000, 0x00000000, 0x00000000,
4734 // 965 FPCXTRegs
4735 0x00000000, 0x00001000, 0x00000000, 0x00000000, 0x00000000,
4736 // 970 GPRlr
4737 0x00000000, 0x00002000, 0x00000000, 0x00000000, 0x00000000,
4738 // 975 GPRsp
4739 0x00000000, 0x00004000, 0x00000000, 0x00000000, 0x00000000,
4740 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4741 // 985 VCCR
4742 0x00000000, 0x00008000, 0x00000000, 0x00000000, 0x00000000,
4743 // 990 cl_FPSCR_NZCV
4744 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000,
4745 // 995 hGPR_and_tGPRwithpc
4746 0x00000000, 0x00020000, 0x00000000, 0x00000000, 0x00000000,
4747 // 1000 hGPR_and_tcGPR
4748 0x00000000, 0x00040000, 0x00000000, 0x00000000, 0x00000000,
4749 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4750 // 1010 DPR
4751 0x00000000, 0x00380000, 0x00000000, 0x00000000, 0x00000000,
4752 0x00000000, 0xc0000000, 0xffffffff, 0xffffffff, 0x000001ff, // dsub_0
4753 0x00000000, 0x00000000, 0x5f979ff8, 0xfffff80f, 0x000001ff, // dsub_1
4754 0x00000000, 0xc0000000, 0xfffff007, 0xffffffff, 0x000001ff, // dsub_2
4755 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x000001ff, // dsub_3
4756 0x00000000, 0x00000000, 0xa0686000, 0x000007f0, 0x000001ff, // dsub_4
4757 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_5
4758 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_6
4759 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_7
4760 // 1055 DPR_VFP2
4761 0x00000000, 0x00300000, 0x00000000, 0x00000000, 0x00000000,
4762 0x00000000, 0x80000000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // dsub_0
4763 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // dsub_1
4764 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // dsub_2
4765 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // dsub_3
4766 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // dsub_4
4767 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // dsub_5
4768 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_6
4769 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_7
4770 // 1100 DPR_8
4771 0x00000000, 0x00200000, 0x00000000, 0x00000000, 0x00000000,
4772 0x00000000, 0x00000000, 0xe4c00c86, 0xfd24070f, 0x000001e0, // dsub_0
4773 0x00000000, 0x00000000, 0x44000c00, 0xf520000e, 0x000001e0, // dsub_1
4774 0x00000000, 0x00000000, 0xe0000004, 0xe500060c, 0x000001c0, // dsub_2
4775 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // dsub_3
4776 0x00000000, 0x00000000, 0x80000000, 0x00000400, 0x00000180, // dsub_4
4777 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // dsub_5
4778 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_6
4779 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_7
4780 // 1145 GPRPair
4781 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000,
4782 // 1150 GPRPairnosp
4783 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000,
4784 // 1155 GPRPair_with_gsub_0_in_tGPR
4785 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000,
4786 // 1160 GPRPair_with_gsub_0_in_hGPR
4787 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000,
4788 // 1165 GPRPair_with_gsub_0_in_tcGPR
4789 0x00000000, 0x2c000000, 0x00000000, 0x00000000, 0x00000000,
4790 // 1170 GPRPair_with_gsub_0_in_tcGPRnotr12
4791 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000,
4792 // 1175 GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR
4793 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000,
4794 // 1180 GPRPair_with_gsub_1_in_GPRsp
4795 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000,
4796 // 1185 DPairSpc
4797 0x00000000, 0xc0000000, 0x00000007, 0x00000000, 0x00000000,
4798 0x00000000, 0x00000000, 0xfffff000, 0xffffffff, 0x000001ff, // ssub_0_ssub_1_ssub_4_ssub_5
4799 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x000001ff, // ssub_2_ssub_3_ssub_6_ssub_7
4800 0x00000000, 0x00000000, 0xa0686000, 0x000007f0, 0x000001ff, // ssub_4_ssub_5_ssub_8_ssub_9
4801 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_8_ssub_9_ssub_12_ssub_13
4802 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_5_dsub_7
4803 // 1215 DPairSpc_with_ssub_0
4804 0x00000000, 0x80000000, 0x00000007, 0x00000000, 0x00000000,
4805 0x00000000, 0x00000000, 0xfffac000, 0xffff37ef, 0x000001fe, // ssub_0_ssub_1_ssub_4_ssub_5
4806 0x00000000, 0x00000000, 0x00000000, 0xfff72000, 0x000001fe, // ssub_2_ssub_3_ssub_6_ssub_7
4807 0x00000000, 0x00000000, 0xa0680000, 0x000007c0, 0x000001fc, // ssub_4_ssub_5_ssub_8_ssub_9
4808 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_8_ssub_9_ssub_12_ssub_13
4809 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // dsub_5_dsub_7
4810 // 1245 DPairSpc_with_ssub_4
4811 0x00000000, 0x00000000, 0x00000007, 0x00000000, 0x00000000,
4812 0x00000000, 0x00000000, 0xfcf80000, 0xffe707cf, 0x000001fc, // ssub_0_ssub_1_ssub_4_ssub_5
4813 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_2_ssub_3_ssub_6_ssub_7
4814 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_4_ssub_5_ssub_8_ssub_9
4815 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_8_ssub_9_ssub_12_ssub_13
4816 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_5_dsub_7
4817 // 1275 DPairSpc_with_dsub_0_in_DPR_8
4818 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000,
4819 0x00000000, 0x00000000, 0xe4c00000, 0xfd24070f, 0x000001e0, // ssub_0_ssub_1_ssub_4_ssub_5
4820 0x00000000, 0x00000000, 0x00000000, 0xf5200000, 0x000001e0, // ssub_2_ssub_3_ssub_6_ssub_7
4821 0x00000000, 0x00000000, 0xa0000000, 0x00000600, 0x000001c0, // ssub_4_ssub_5_ssub_8_ssub_9
4822 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_8_ssub_9_ssub_12_ssub_13
4823 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // dsub_5_dsub_7
4824 // 1305 DPairSpc_with_dsub_2_in_DPR_8
4825 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000,
4826 0x00000000, 0x00000000, 0xe0000000, 0xe500060c, 0x000001c0, // ssub_0_ssub_1_ssub_4_ssub_5
4827 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // ssub_2_ssub_3_ssub_6_ssub_7
4828 0x00000000, 0x00000000, 0x80000000, 0x00000400, 0x00000180, // ssub_4_ssub_5_ssub_8_ssub_9
4829 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_8_ssub_9_ssub_12_ssub_13
4830 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_5_dsub_7
4831 // 1335 DPair
4832 0x00000000, 0x00000000, 0x00000ff8, 0x00000000, 0x00000000,
4833 0x00000000, 0x00000000, 0x5f979000, 0xfffff80f, 0x000001ff, // qsub_0
4834 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x000001ff, // qsub_1
4835 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qsub_2
4836 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qsub_3
4837 0x00000000, 0x00000000, 0x5f979000, 0xfffff80f, 0x000001ff, // ssub_2_ssub_3_ssub_4_ssub_5
4838 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_ssub_8_ssub_9
4839 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_5_ssub_12_ssub_13
4840 // 1375 DPair_with_ssub_0
4841 0x00000000, 0x00000000, 0x00000fd0, 0x00000000, 0x00000000,
4842 0x00000000, 0x00000000, 0x5f928000, 0xffff300f, 0x000001fe, // qsub_0
4843 0x00000000, 0x00000000, 0x00000000, 0xffe70000, 0x000001fc, // qsub_1
4844 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qsub_2
4845 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qsub_3
4846 0x00000000, 0x00000000, 0x5d920000, 0xfff7200f, 0x000001fe, // ssub_2_ssub_3_ssub_4_ssub_5
4847 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_ssub_8_ssub_9
4848 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // dsub_5_ssub_12_ssub_13
4849 // 1415 QPR
4850 0x00000000, 0x00000000, 0x00000b20, 0x00000000, 0x00000000,
4851 0x00000000, 0x00000000, 0x11010000, 0x50904006, 0x000001ff, // qsub_0
4852 0x00000000, 0x00000000, 0x00000000, 0x50904000, 0x000001ff, // qsub_1
4853 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qsub_2
4854 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qsub_3
4855 0x00000000, 0x00000000, 0x0a040000, 0xaa488009, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
4856 // 1445 DPair_with_ssub_2
4857 0x00000000, 0x00000000, 0x00000fc0, 0x00000000, 0x00000000,
4858 0x00000000, 0x00000000, 0x5d920000, 0xfff7200f, 0x000001fe, // qsub_0
4859 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // qsub_1
4860 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qsub_2
4861 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qsub_3
4862 0x00000000, 0x00000000, 0x5c900000, 0xffe7000f, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5
4863 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9
4864 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_5_ssub_12_ssub_13
4865 // 1485 DPair_with_dsub_0_in_DPR_8
4866 0x00000000, 0x00000000, 0x00000c80, 0x00000000, 0x00000000,
4867 0x00000000, 0x00000000, 0x44800000, 0xfd24000f, 0x000001e0, // qsub_0
4868 0x00000000, 0x00000000, 0x00000000, 0xe5000000, 0x000001c0, // qsub_1
4869 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // qsub_2
4870 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // qsub_3
4871 0x00000000, 0x00000000, 0x44000000, 0xf520000e, 0x000001e0, // ssub_2_ssub_3_ssub_4_ssub_5
4872 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_ssub_8_ssub_9
4873 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // dsub_5_ssub_12_ssub_13
4874 // 1525 MQPR
4875 0x00000000, 0x00000000, 0x00000b00, 0x00000000, 0x00000000,
4876 0x00000000, 0x00000000, 0x11000000, 0x50900006, 0x000001fe, // qsub_0
4877 0x00000000, 0x00000000, 0x00000000, 0x50800000, 0x000001fc, // qsub_1
4878 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qsub_2
4879 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qsub_3
4880 0x00000000, 0x00000000, 0x08000000, 0xaa400009, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
4881 // 1555 QPR_VFP2
4882 0x00000000, 0x00000000, 0x00000b00, 0x00000000, 0x00000000,
4883 0x00000000, 0x00000000, 0x11000000, 0x50900006, 0x000001fe, // qsub_0
4884 0x00000000, 0x00000000, 0x00000000, 0x50800000, 0x000001fc, // qsub_1
4885 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qsub_2
4886 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qsub_3
4887 0x00000000, 0x00000000, 0x08000000, 0xaa400009, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
4888 // 1585 DPair_with_dsub_1_in_DPR_8
4889 0x00000000, 0x00000000, 0x00000c00, 0x00000000, 0x00000000,
4890 0x00000000, 0x00000000, 0x44000000, 0xf520000e, 0x000001e0, // qsub_0
4891 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // qsub_1
4892 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // qsub_2
4893 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // qsub_3
4894 0x00000000, 0x00000000, 0x40000000, 0xe500000c, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5
4895 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9
4896 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_5_ssub_12_ssub_13
4897 // 1625 QPR_8
4898 0x00000000, 0x00000000, 0x00000800, 0x00000000, 0x00000000,
4899 0x00000000, 0x00000000, 0x00000000, 0x50000006, 0x000001e0, // qsub_0
4900 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x000001c0, // qsub_1
4901 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // qsub_2
4902 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // qsub_3
4903 0x00000000, 0x00000000, 0x00000000, 0xa0000008, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
4904 // 1655 DTriple
4905 0x00000000, 0x00000000, 0x5f979000, 0x0000000f, 0x00000000,
4906 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x000001ff, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4907 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x000001ff, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4908 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4909 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4910 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4911 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_5_ssub_12_ssub_13_dsub_7
4912 // 1690 DTripleSpc
4913 0x00000000, 0x00000000, 0xa0686000, 0x000007f0, 0x00000000,
4914 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4915 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4916 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4917 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_dsub_5_dsub_7
4918 // 1715 DTripleSpc_with_ssub_0
4919 0x00000000, 0x00000000, 0xa0684000, 0x000007e0, 0x00000000,
4920 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4921 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4922 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4923 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_dsub_5_dsub_7
4924 // 1740 DTriple_with_ssub_0
4925 0x00000000, 0x00000000, 0x5f928000, 0x0000000f, 0x00000000,
4926 0x00000000, 0x00000000, 0x00000000, 0xffff3000, 0x000001fe, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4927 0x00000000, 0x00000000, 0x00000000, 0xfff72000, 0x000001fe, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4928 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4929 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4930 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4931 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // dsub_5_ssub_12_ssub_13_dsub_7
4932 // 1775 DTriple_with_qsub_0_in_QPR
4933 0x00000000, 0x00000000, 0x11010000, 0x00000006, 0x00000000,
4934 0x00000000, 0x00000000, 0x00000000, 0x50904000, 0x000001ff, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4935 0x00000000, 0x00000000, 0x00000000, 0xaa488000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4936 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4937 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4938 // 1800 DTriple_with_ssub_2
4939 0x00000000, 0x00000000, 0x5d920000, 0x0000000f, 0x00000000,
4940 0x00000000, 0x00000000, 0x00000000, 0xfff72000, 0x000001fe, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4941 0x00000000, 0x00000000, 0x00000000, 0xffe70000, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4942 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4943 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4944 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4945 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_5_ssub_12_ssub_13_dsub_7
4946 // 1835 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
4947 0x00000000, 0x00000000, 0x0a040000, 0x00000009, 0x00000000,
4948 0x00000000, 0x00000000, 0x00000000, 0xaa488000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4949 0x00000000, 0x00000000, 0x00000000, 0x50904000, 0x000001ff, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4950 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4951 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_5_ssub_12_ssub_13_dsub_7
4952 // 1860 DTripleSpc_with_ssub_4
4953 0x00000000, 0x00000000, 0xa0680000, 0x000007c0, 0x00000000,
4954 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4955 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4956 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4957 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_dsub_5_dsub_7
4958 // 1885 DTriple_with_ssub_4
4959 0x00000000, 0x00000000, 0x5c900000, 0x0000000f, 0x00000000,
4960 0x00000000, 0x00000000, 0x00000000, 0xffe70000, 0x000001fc, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4961 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4962 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4963 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4964 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4965 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_5_ssub_12_ssub_13_dsub_7
4966 // 1920 DTripleSpc_with_ssub_8
4967 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x00000000,
4968 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4969 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4970 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4971 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_6_ssub_7_dsub_5_dsub_7
4972 // 1945 DTripleSpc_with_dsub_0_in_DPR_8
4973 0x00000000, 0x00000000, 0xa0400000, 0x00000700, 0x00000000,
4974 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4975 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4976 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4977 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_dsub_5_dsub_7
4978 // 1970 DTriple_with_dsub_0_in_DPR_8
4979 0x00000000, 0x00000000, 0x44800000, 0x0000000f, 0x00000000,
4980 0x00000000, 0x00000000, 0x00000000, 0xfd240000, 0x000001e0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4981 0x00000000, 0x00000000, 0x00000000, 0xf5200000, 0x000001e0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4982 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4983 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4984 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4985 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // dsub_5_ssub_12_ssub_13_dsub_7
4986 // 2005 DTriple_with_qsub_0_in_MQPR
4987 0x00000000, 0x00000000, 0x11000000, 0x00000006, 0x00000000,
4988 0x00000000, 0x00000000, 0x00000000, 0x50900000, 0x000001fe, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4989 0x00000000, 0x00000000, 0x00000000, 0xaa400000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4990 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4991 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4992 // 2030 DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
4993 0x00000000, 0x00000000, 0x0a000000, 0x00000009, 0x00000000,
4994 0x00000000, 0x00000000, 0x00000000, 0xaa480000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4995 0x00000000, 0x00000000, 0x00000000, 0x50900000, 0x000001fe, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4996 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4997 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // dsub_5_ssub_12_ssub_13_dsub_7
4998 // 2055 DTriple_with_dsub_1_in_DPR_8
4999 0x00000000, 0x00000000, 0x44000000, 0x0000000e, 0x00000000,
5000 0x00000000, 0x00000000, 0x00000000, 0xf5200000, 0x000001e0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5001 0x00000000, 0x00000000, 0x00000000, 0xe5000000, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5002 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5003 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5004 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5005 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_5_ssub_12_ssub_13_dsub_7
5006 // 2090 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
5007 0x00000000, 0x00000000, 0x08000000, 0x00000009, 0x00000000,
5008 0x00000000, 0x00000000, 0x00000000, 0xaa400000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5009 0x00000000, 0x00000000, 0x00000000, 0x50800000, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5010 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5011 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_5_ssub_12_ssub_13_dsub_7
5012 // 2115 DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR
5013 0x00000000, 0x00000000, 0x10000000, 0x00000006, 0x00000000,
5014 0x00000000, 0x00000000, 0x00000000, 0x50800000, 0x000001fc, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5015 0x00000000, 0x00000000, 0x00000000, 0xaa000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5016 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5017 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5018 // 2140 DTripleSpc_with_dsub_2_in_DPR_8
5019 0x00000000, 0x00000000, 0xa0000000, 0x00000600, 0x00000000,
5020 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5021 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5022 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5023 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_dsub_5_dsub_7
5024 // 2165 DTriple_with_dsub_2_in_DPR_8
5025 0x00000000, 0x00000000, 0x40000000, 0x0000000c, 0x00000000,
5026 0x00000000, 0x00000000, 0x00000000, 0xe5000000, 0x000001c0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5027 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5028 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5029 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5030 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5031 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_5_ssub_12_ssub_13_dsub_7
5032 // 2200 DTripleSpc_with_dsub_4_in_DPR_8
5033 0x00000000, 0x00000000, 0x80000000, 0x00000400, 0x00000000,
5034 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5035 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5036 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5037 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_6_ssub_7_dsub_5_dsub_7
5038 // 2225 DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
5039 0x00000000, 0x00000000, 0x00000000, 0x00000009, 0x00000000,
5040 0x00000000, 0x00000000, 0x00000000, 0xa8000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5041 0x00000000, 0x00000000, 0x00000000, 0x50000000, 0x000001e0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5042 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5043 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // dsub_5_ssub_12_ssub_13_dsub_7
5044 // 2250 DTriple_with_qsub_0_in_QPR_8
5045 0x00000000, 0x00000000, 0x00000000, 0x00000006, 0x00000000,
5046 0x00000000, 0x00000000, 0x00000000, 0x50000000, 0x000001e0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5047 0x00000000, 0x00000000, 0x00000000, 0xa0000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5048 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5049 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5050 // 2275 DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8
5051 0x00000000, 0x00000000, 0x00000000, 0x00000004, 0x00000000,
5052 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x000001c0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5053 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5054 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5055 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5056 // 2300 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
5057 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000,
5058 0x00000000, 0x00000000, 0x00000000, 0xa0000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5059 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5060 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5061 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_5_ssub_12_ssub_13_dsub_7
5062 // 2325 DQuadSpc
5063 0x00000000, 0x00000000, 0x00000000, 0x000007f0, 0x00000000,
5064 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5065 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5066 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5067 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_dsub_5_dsub_7
5068 // 2350 DQuadSpc_with_ssub_0
5069 0x00000000, 0x00000000, 0x00000000, 0x000007e0, 0x00000000,
5070 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5071 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5072 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5073 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_dsub_5_dsub_7
5074 // 2375 DQuadSpc_with_ssub_4
5075 0x00000000, 0x00000000, 0x00000000, 0x000007c0, 0x00000000,
5076 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5077 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5078 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5079 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_dsub_5_dsub_7
5080 // 2400 DQuadSpc_with_ssub_8
5081 0x00000000, 0x00000000, 0x00000000, 0x00000780, 0x00000000,
5082 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5083 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5084 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5085 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_6_ssub_7_dsub_5_dsub_7
5086 // 2425 DQuadSpc_with_dsub_0_in_DPR_8
5087 0x00000000, 0x00000000, 0x00000000, 0x00000700, 0x00000000,
5088 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5089 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5090 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5091 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_dsub_5_dsub_7
5092 // 2450 DQuadSpc_with_dsub_2_in_DPR_8
5093 0x00000000, 0x00000000, 0x00000000, 0x00000600, 0x00000000,
5094 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5095 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5096 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5097 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_dsub_5_dsub_7
5098 // 2475 DQuadSpc_with_dsub_4_in_DPR_8
5099 0x00000000, 0x00000000, 0x00000000, 0x00000400, 0x00000000,
5100 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5101 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5102 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5103 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_6_ssub_7_dsub_5_dsub_7
5104 // 2500 DQuad
5105 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x00000000,
5106 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qqsub_0
5107 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qqsub_1
5108 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5109 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5110 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5111 // 2530 DQuad_with_ssub_0
5112 0x00000000, 0x00000000, 0x00000000, 0xffff3000, 0x00000000,
5113 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // qqsub_0
5114 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qqsub_1
5115 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5116 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5117 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5118 // 2560 DQuad_with_ssub_2
5119 0x00000000, 0x00000000, 0x00000000, 0xfff72000, 0x00000000,
5120 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // qqsub_0
5121 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qqsub_1
5122 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5123 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5124 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5125 // 2590 QQPR
5126 0x00000000, 0x00000000, 0x00000000, 0x50904000, 0x00000000,
5127 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qqsub_0
5128 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qqsub_1
5129 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5130 // 2610 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
5131 0x00000000, 0x00000000, 0x00000000, 0xaa488000, 0x00000000,
5132 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5133 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5134 // 2625 DQuad_with_ssub_4
5135 0x00000000, 0x00000000, 0x00000000, 0xffe70000, 0x00000000,
5136 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // qqsub_0
5137 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qqsub_1
5138 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5139 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5140 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5141 // 2655 DQuad_with_ssub_6
5142 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x00000000,
5143 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // qqsub_0
5144 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qqsub_1
5145 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5146 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5147 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5148 // 2685 DQuad_with_dsub_0_in_DPR_8
5149 0x00000000, 0x00000000, 0x00000000, 0xfd240000, 0x00000000,
5150 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // qqsub_0
5151 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // qqsub_1
5152 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5153 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5154 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5155 // 2715 DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
5156 0x00000000, 0x00000000, 0x00000000, 0xaa480000, 0x00000000,
5157 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5158 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5159 // 2730 QQPR_with_ssub_0
5160 0x00000000, 0x00000000, 0x00000000, 0x50900000, 0x00000000,
5161 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // qqsub_0
5162 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qqsub_1
5163 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5164 // 2750 DQuad_with_dsub_1_in_DPR_8
5165 0x00000000, 0x00000000, 0x00000000, 0xf5200000, 0x00000000,
5166 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // qqsub_0
5167 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // qqsub_1
5168 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5169 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5170 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5171 // 2780 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
5172 0x00000000, 0x00000000, 0x00000000, 0xaa400000, 0x00000000,
5173 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5174 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5175 // 2795 MQQPR
5176 0x00000000, 0x00000000, 0x00000000, 0x50800000, 0x00000000,
5177 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // qqsub_0
5178 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qqsub_1
5179 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5180 // 2815 DQuad_with_dsub_2_in_DPR_8
5181 0x00000000, 0x00000000, 0x00000000, 0xe5000000, 0x00000000,
5182 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // qqsub_0
5183 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // qqsub_1
5184 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5185 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5186 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5187 // 2845 DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
5188 0x00000000, 0x00000000, 0x00000000, 0xaa000000, 0x00000000,
5189 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5190 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5191 // 2860 DQuad_with_dsub_3_in_DPR_8
5192 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x00000000,
5193 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // qqsub_0
5194 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // qqsub_1
5195 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5196 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5197 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5198 // 2890 DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
5199 0x00000000, 0x00000000, 0x00000000, 0xa8000000, 0x00000000,
5200 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5201 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5202 // 2905 MQQPR_with_qsub_0_in_QPR_8
5203 0x00000000, 0x00000000, 0x00000000, 0x50000000, 0x00000000,
5204 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // qqsub_0
5205 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // qqsub_1
5206 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5207 // 2925 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
5208 0x00000000, 0x00000000, 0x00000000, 0xa0000000, 0x00000000,
5209 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5210 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5211 // 2940 MQQPR_with_dsub_2_in_DPR_8
5212 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00000000,
5213 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // qqsub_0
5214 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // qqsub_1
5215 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5216 // 2960 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8
5217 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000000,
5218 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5219 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5220 // 2975 QQQQPR
5221 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff,
5222 // 2980 QQQQPR_with_ssub_0
5223 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe,
5224 // 2985 QQQQPR_with_ssub_4
5225 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc,
5226 // 2990 QQQQPR_with_ssub_8
5227 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8,
5228 // 2995 MQQQQPR
5229 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0,
5230 // 3000 MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8
5231 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0,
5232 // 3005 MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8
5233 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0,
5234 // 3010 MQQQQPR_with_qsub_2_in_QPR_8
5235 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180,
5236 // 3015 MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8
5237 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100,
5238 },
5239 .SuperRegIdxSeqs: {
5240 /* 0 */ 1, 2, 3, 4, 5, 6, 7, 8, 0,
5241 /* 9 */ 9, 0,
5242 /* 11 */ 9, 10, 0,
5243 /* 14 */ 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0,
5244 /* 39 */ 13, 14, 15, 16, 37, 0,
5245 /* 45 */ 38, 40, 45, 48, 0,
5246 /* 50 */ 42, 50, 0,
5247 /* 53 */ 34, 36, 44, 52, 0,
5248 /* 58 */ 33, 35, 43, 51, 53, 0,
5249 /* 64 */ 34, 36, 47, 54, 0,
5250 /* 69 */ 34, 36, 44, 47, 52, 54, 0,
5251 /* 76 */ 13, 14, 15, 16, 37, 49, 55, 0,
5252 /* 84 */ 11, 12, 56, 0,
5253 /* 88 */ 11, 12, 42, 50, 56, 0,
5254 },
5255 .SuperClasses: {
5256 /* 0 HPR */
5257 /* 0 FPWithVPR */
5258 /* 0 SPR */ ARM::HPRRegClassID, ARM::FPWithVPRRegClassID,
5259 /* 2 FPWithVPR_with_ssub_0 */ ARM::FPWithVPRRegClassID,
5260 /* 3 GPR */
5261 /* 3 GPRwithAPSR */
5262 /* 3 GPRwithZR */
5263 /* 3 SPR_8 */ ARM::HPRRegClassID, ARM::FPWithVPRRegClassID, ARM::SPRRegClassID,
5264 /* 6 GPRnopc */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID,
5265 /* 9 GPRnosp */ ARM::GPRRegClassID,
5266 /* 10 GPRwithAPSR_NZCVnosp */ ARM::GPRwithAPSRRegClassID,
5267 /* 11 GPRwithAPSRnosp */
5268 /* 11 GPRwithZRnosp */ ARM::GPRwithZRRegClassID,
5269 /* 12 GPRnoip */ ARM::GPRRegClassID,
5270 /* 13 rGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID,
5271 /* 21 GPRnoip_and_GPRnopc */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnoipRegClassID,
5272 /* 26 GPRnoip_and_GPRnosp */ ARM::GPRRegClassID, ARM::GPRnospRegClassID, ARM::GPRnoipRegClassID,
5273 /* 29 GPRnoip_and_GPRwithAPSR_NZCVnosp */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID,
5274 /* 41 tGPRwithpc */ ARM::GPRRegClassID, ARM::GPRnospRegClassID, ARM::GPRnoipRegClassID, ARM::GPRnoip_and_GPRnospRegClassID,
5275 /* 45 FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 */ ARM::FPWithVPRRegClassID, ARM::FPWithVPR_with_ssub_0RegClassID,
5276 /* 47 hGPR */ ARM::GPRRegClassID,
5277 /* 48 tGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPRwithpcRegClassID,
5278 /* 62 tGPREven */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID,
5279 /* 71 GPRnopc_and_hGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::hGPRRegClassID,
5280 /* 76 GPRnosp_and_hGPR */ ARM::GPRRegClassID, ARM::GPRnospRegClassID, ARM::hGPRRegClassID,
5281 /* 79 GPRnoip_and_hGPR */ ARM::GPRRegClassID, ARM::GPRnoipRegClassID, ARM::hGPRRegClassID,
5282 /* 82 GPRnoip_and_tGPREven */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPREvenRegClassID,
5283 /* 96 GPRnosp_and_GPRnopc_and_hGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID, ARM::hGPRRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID,
5284 /* 108 tGPROdd */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID,
5285 /* 121 GPRnopc_and_GPRnoip_and_hGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnoipRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::hGPRRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID,
5286 /* 130 GPRnosp_and_GPRnoip_and_hGPR */ ARM::GPRRegClassID, ARM::GPRnospRegClassID, ARM::GPRnoipRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID,
5287 /* 137 tcGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID,
5288 /* 146 GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::hGPRRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID, ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID,
5289 /* 166 hGPR_and_tGPREven */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID, ARM::hGPRRegClassID, ARM::tGPREvenRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID,
5290 /* 180 tGPR_and_tGPREven */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPRwithpcRegClassID, ARM::tGPRRegClassID, ARM::tGPREvenRegClassID, ARM::GPRnoip_and_tGPREvenRegClassID,
5291 /* 197 tGPR_and_tGPROdd */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPRwithpcRegClassID, ARM::tGPRRegClassID, ARM::tGPROddRegClassID,
5292 /* 213 tcGPRnotr12 */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPRwithpcRegClassID, ARM::tGPRRegClassID, ARM::tcGPRRegClassID,
5293 /* 229 tGPREven_and_tcGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID, ARM::tGPREvenRegClassID, ARM::tcGPRRegClassID,
5294 /* 240 FP_STATUS_REGS */
5295 /* 240 hGPR_and_GPRnoip_and_tGPREven */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::hGPRRegClassID, ARM::tGPREvenRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID, ARM::GPRnoip_and_tGPREvenRegClassID, ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID, ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID, ARM::hGPR_and_tGPREvenRegClassID,
5296 /* 264 hGPR_and_tGPROdd */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::hGPRRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID, ARM::tGPROddRegClassID, ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID,
5297 /* 286 tGPREven_and_tcGPRnotr12 */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPRwithpcRegClassID, ARM::tGPRRegClassID, ARM::tGPREvenRegClassID, ARM::GPRnoip_and_tGPREvenRegClassID, ARM::tcGPRRegClassID, ARM::tGPR_and_tGPREvenRegClassID, ARM::tcGPRnotr12RegClassID, ARM::tGPREven_and_tcGPRRegClassID,
5298 /* 307 tGPROdd_and_tcGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPRwithpcRegClassID, ARM::tGPRRegClassID, ARM::tGPROddRegClassID, ARM::tcGPRRegClassID, ARM::tGPR_and_tGPROddRegClassID, ARM::tcGPRnotr12RegClassID,
5299 /* 326 CCR */
5300 /* 326 FPCXTRegs */
5301 /* 326 GPRlr */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID, ARM::hGPRRegClassID, ARM::tGPREvenRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID, ARM::hGPR_and_tGPREvenRegClassID,
5302 /* 341 GPRsp */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnoipRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::hGPRRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID, ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID,
5303 /* 351 VCCR */ ARM::FPWithVPRRegClassID,
5304 /* 352 cl_FPSCR_NZCV */
5305 /* 352 hGPR_and_tGPRwithpc */ ARM::GPRRegClassID, ARM::GPRnospRegClassID, ARM::GPRnoipRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::tGPRwithpcRegClassID, ARM::hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID,
5306 /* 361 hGPR_and_tcGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID, ARM::hGPRRegClassID, ARM::tGPREvenRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID, ARM::tcGPRRegClassID, ARM::hGPR_and_tGPREvenRegClassID, ARM::tGPREven_and_tcGPRRegClassID,
5307 /* 378 DPR */ ARM::FPWithVPRRegClassID,
5308 /* 379 DPR_VFP2 */ ARM::FPWithVPRRegClassID, ARM::FPWithVPR_with_ssub_0RegClassID, ARM::DPRRegClassID,
5309 /* 382 DPR_8 */ ARM::FPWithVPRRegClassID, ARM::FPWithVPR_with_ssub_0RegClassID, ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID, ARM::DPRRegClassID, ARM::DPR_VFP2RegClassID,
5310 /* 387 GPRPair */
5311 /* 387 GPRPairnosp */ ARM::GPRPairRegClassID,
5312 /* 388 GPRPair_with_gsub_0_in_tGPR */ ARM::GPRPairRegClassID, ARM::GPRPairnospRegClassID,
5313 /* 390 GPRPair_with_gsub_0_in_hGPR */ ARM::GPRPairRegClassID,
5314 /* 391 GPRPair_with_gsub_0_in_tcGPR */ ARM::GPRPairRegClassID,
5315 /* 392 GPRPair_with_gsub_0_in_tcGPRnotr12 */ ARM::GPRPairRegClassID, ARM::GPRPairnospRegClassID, ARM::GPRPair_with_gsub_0_in_tGPRRegClassID, ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID,
5316 /* 396 GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR */ ARM::GPRPairRegClassID, ARM::GPRPairnospRegClassID, ARM::GPRPair_with_gsub_0_in_hGPRRegClassID,
5317 /* 399 GPRPair_with_gsub_1_in_GPRsp */ ARM::GPRPairRegClassID, ARM::GPRPair_with_gsub_0_in_hGPRRegClassID, ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID,
5318 /* 402 DPairSpc */
5319 /* 402 DPairSpc_with_ssub_0 */ ARM::DPairSpcRegClassID,
5320 /* 403 DPairSpc_with_ssub_4 */ ARM::DPairSpcRegClassID, ARM::DPairSpc_with_ssub_0RegClassID,
5321 /* 405 DPairSpc_with_dsub_0_in_DPR_8 */ ARM::DPairSpcRegClassID, ARM::DPairSpc_with_ssub_0RegClassID, ARM::DPairSpc_with_ssub_4RegClassID,
5322 /* 408 DPairSpc_with_dsub_2_in_DPR_8 */ ARM::DPairSpcRegClassID, ARM::DPairSpc_with_ssub_0RegClassID, ARM::DPairSpc_with_ssub_4RegClassID, ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID,
5323 /* 412 DPair */
5324 /* 412 DPair_with_ssub_0 */ ARM::DPairRegClassID,
5325 /* 413 QPR */ ARM::DPairRegClassID,
5326 /* 414 DPair_with_ssub_2 */ ARM::DPairRegClassID, ARM::DPair_with_ssub_0RegClassID,
5327 /* 416 DPair_with_dsub_0_in_DPR_8 */ ARM::DPairRegClassID, ARM::DPair_with_ssub_0RegClassID, ARM::DPair_with_ssub_2RegClassID,
5328 /* 419 MQPR */ ARM::DPairRegClassID, ARM::DPair_with_ssub_0RegClassID, ARM::QPRRegClassID, ARM::DPair_with_ssub_2RegClassID, ARM::QPR_VFP2RegClassID,
5329 /* 424 QPR_VFP2 */ ARM::DPairRegClassID, ARM::DPair_with_ssub_0RegClassID, ARM::QPRRegClassID, ARM::DPair_with_ssub_2RegClassID, ARM::MQPRRegClassID,
5330 /* 429 DPair_with_dsub_1_in_DPR_8 */ ARM::DPairRegClassID, ARM::DPair_with_ssub_0RegClassID, ARM::DPair_with_ssub_2RegClassID, ARM::DPair_with_dsub_0_in_DPR_8RegClassID,
5331 /* 433 QPR_8 */ ARM::DPairRegClassID, ARM::DPair_with_ssub_0RegClassID, ARM::QPRRegClassID, ARM::DPair_with_ssub_2RegClassID, ARM::DPair_with_dsub_0_in_DPR_8RegClassID, ARM::MQPRRegClassID, ARM::QPR_VFP2RegClassID, ARM::DPair_with_dsub_1_in_DPR_8RegClassID,
5332 /* 441 DTriple */
5333 /* 441 DTripleSpc */
5334 /* 441 DTripleSpc_with_ssub_0 */ ARM::DTripleSpcRegClassID,
5335 /* 442 DTriple_with_ssub_0 */ ARM::DTripleRegClassID,
5336 /* 443 DTriple_with_qsub_0_in_QPR */ ARM::DTripleRegClassID,
5337 /* 444 DTriple_with_ssub_2 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID,
5338 /* 446 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR */ ARM::DTripleRegClassID,
5339 /* 447 DTripleSpc_with_ssub_4 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID,
5340 /* 449 DTriple_with_ssub_4 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID,
5341 /* 452 DTripleSpc_with_ssub_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID,
5342 /* 455 DTripleSpc_with_dsub_0_in_DPR_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID,
5343 /* 459 DTriple_with_dsub_0_in_DPR_8 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_4RegClassID,
5344 /* 463 DTriple_with_qsub_0_in_MQPR */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_qsub_0_in_QPRRegClassID, ARM::DTriple_with_ssub_2RegClassID,
5345 /* 467 DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
5346 /* 470 DTriple_with_dsub_1_in_DPR_8 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8RegClassID,
5347 /* 475 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
5348 /* 481 DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_qsub_0_in_QPRRegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_qsub_0_in_MQPRRegClassID,
5349 /* 487 DTripleSpc_with_dsub_2_in_DPR_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID, ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID,
5350 /* 492 DTriple_with_dsub_2_in_DPR_8 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, ARM::DTriple_with_dsub_1_in_DPR_8RegClassID,
5351 /* 498 DTripleSpc_with_dsub_4_in_DPR_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID, ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID,
5352 /* 504 DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
5353 /* 512 DTriple_with_qsub_0_in_QPR_8 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_qsub_0_in_QPRRegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, ARM::DTriple_with_qsub_0_in_MQPRRegClassID, ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID,
5354 /* 521 DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_qsub_0_in_QPRRegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, ARM::DTriple_with_qsub_0_in_MQPRRegClassID, ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID, ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, ARM::DTriple_with_qsub_0_in_QPR_8RegClassID,
5355 /* 532 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
5356 /* 543 DQuadSpc */ ARM::DTripleSpcRegClassID,
5357 /* 544 DQuadSpc_with_ssub_0 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DQuadSpcRegClassID,
5358 /* 547 DQuadSpc_with_ssub_4 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DQuadSpcRegClassID, ARM::DQuadSpc_with_ssub_0RegClassID,
5359 /* 552 DQuadSpc_with_ssub_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID, ARM::DQuadSpcRegClassID, ARM::DQuadSpc_with_ssub_0RegClassID, ARM::DQuadSpc_with_ssub_4RegClassID,
5360 /* 559 DQuadSpc_with_dsub_0_in_DPR_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID, ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, ARM::DQuadSpcRegClassID, ARM::DQuadSpc_with_ssub_0RegClassID, ARM::DQuadSpc_with_ssub_4RegClassID, ARM::DQuadSpc_with_ssub_8RegClassID,
5361 /* 568 DQuadSpc_with_dsub_2_in_DPR_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID, ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, ARM::DQuadSpcRegClassID, ARM::DQuadSpc_with_ssub_0RegClassID, ARM::DQuadSpc_with_ssub_4RegClassID, ARM::DQuadSpc_with_ssub_8RegClassID, ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID,
5362 /* 579 DQuadSpc_with_dsub_4_in_DPR_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID, ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID, ARM::DQuadSpcRegClassID, ARM::DQuadSpc_with_ssub_0RegClassID, ARM::DQuadSpc_with_ssub_4RegClassID, ARM::DQuadSpc_with_ssub_8RegClassID, ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID, ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID,
5363 /* 592 DQuad */
5364 /* 592 DQuad_with_ssub_0 */ ARM::DQuadRegClassID,
5365 /* 593 DQuad_with_ssub_2 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID,
5366 /* 595 QQPR */ ARM::DQuadRegClassID,
5367 /* 596 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR */ ARM::DQuadRegClassID,
5368 /* 597 DQuad_with_ssub_4 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID,
5369 /* 600 DQuad_with_ssub_6 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_4RegClassID,
5370 /* 604 DQuad_with_dsub_0_in_DPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID,
5371 /* 609 DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
5372 /* 612 QQPR_with_ssub_0 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::QQPRRegClassID,
5373 /* 616 DQuad_with_dsub_1_in_DPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID,
5374 /* 622 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
5375 /* 628 MQQPR */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::QQPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::QQPR_with_ssub_0RegClassID,
5376 /* 635 DQuad_with_dsub_2_in_DPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::DQuad_with_dsub_1_in_DPR_8RegClassID,
5377 /* 642 DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
5378 /* 650 DQuad_with_dsub_3_in_DPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, ARM::DQuad_with_dsub_2_in_DPR_8RegClassID,
5379 /* 658 DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
5380 /* 668 MQQPR_with_qsub_0_in_QPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::QQPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::QQPR_with_ssub_0RegClassID, ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, ARM::MQQPRRegClassID,
5381 /* 678 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
5382 /* 691 MQQPR_with_dsub_2_in_DPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::QQPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::QQPR_with_ssub_0RegClassID, ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, ARM::MQQPRRegClassID, ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, ARM::MQQPR_with_qsub_0_in_QPR_8RegClassID,
5383 /* 704 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, ARM::DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID,
5384 /* 719 QQQQPR */
5385 /* 719 QQQQPR_with_ssub_0 */ ARM::QQQQPRRegClassID,
5386 /* 720 QQQQPR_with_ssub_4 */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID,
5387 /* 722 QQQQPR_with_ssub_8 */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID, ARM::QQQQPR_with_ssub_4RegClassID,
5388 /* 725 MQQQQPR */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID, ARM::QQQQPR_with_ssub_4RegClassID, ARM::QQQQPR_with_ssub_8RegClassID,
5389 /* 729 MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8 */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID, ARM::QQQQPR_with_ssub_4RegClassID, ARM::QQQQPR_with_ssub_8RegClassID, ARM::MQQQQPRRegClassID,
5390 /* 734 MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8 */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID, ARM::QQQQPR_with_ssub_4RegClassID, ARM::QQQQPR_with_ssub_8RegClassID, ARM::MQQQQPRRegClassID, ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID,
5391 /* 740 MQQQQPR_with_qsub_2_in_QPR_8 */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID, ARM::QQQQPR_with_ssub_4RegClassID, ARM::QQQQPR_with_ssub_8RegClassID, ARM::MQQQQPRRegClassID, ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID, ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8RegClassID,
5392 /* 747 MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8 */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID, ARM::QQQQPR_with_ssub_4RegClassID, ARM::QQQQPR_with_ssub_8RegClassID, ARM::MQQQQPRRegClassID, ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID, ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8RegClassID, ARM::MQQQQPR_with_qsub_2_in_QPR_8RegClassID,
5393 }
5394};
5395
5396const MCRegisterClass &getARMMCRegisterClass(unsigned RC) {
5397 return ARMMCRegisterClassStorage.Classes[RC];
5398}
5399
5400// ARM Dwarf<->LLVM register mappings.
5401extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = {
5402 { .FromReg: 0U, .ToReg: ARM::R0 },
5403 { .FromReg: 1U, .ToReg: ARM::R1 },
5404 { .FromReg: 2U, .ToReg: ARM::R2 },
5405 { .FromReg: 3U, .ToReg: ARM::R3 },
5406 { .FromReg: 4U, .ToReg: ARM::R4 },
5407 { .FromReg: 5U, .ToReg: ARM::R5 },
5408 { .FromReg: 6U, .ToReg: ARM::R6 },
5409 { .FromReg: 7U, .ToReg: ARM::R7 },
5410 { .FromReg: 8U, .ToReg: ARM::R8 },
5411 { .FromReg: 9U, .ToReg: ARM::R9 },
5412 { .FromReg: 10U, .ToReg: ARM::R10 },
5413 { .FromReg: 11U, .ToReg: ARM::R11 },
5414 { .FromReg: 12U, .ToReg: ARM::R12 },
5415 { .FromReg: 13U, .ToReg: ARM::SP },
5416 { .FromReg: 14U, .ToReg: ARM::LR },
5417 { .FromReg: 15U, .ToReg: ARM::ZR },
5418 { .FromReg: 143U, .ToReg: ARM::RA_AUTH_CODE },
5419 { .FromReg: 256U, .ToReg: ARM::D0 },
5420 { .FromReg: 257U, .ToReg: ARM::D1 },
5421 { .FromReg: 258U, .ToReg: ARM::D2 },
5422 { .FromReg: 259U, .ToReg: ARM::D3 },
5423 { .FromReg: 260U, .ToReg: ARM::D4 },
5424 { .FromReg: 261U, .ToReg: ARM::D5 },
5425 { .FromReg: 262U, .ToReg: ARM::D6 },
5426 { .FromReg: 263U, .ToReg: ARM::D7 },
5427 { .FromReg: 264U, .ToReg: ARM::D8 },
5428 { .FromReg: 265U, .ToReg: ARM::D9 },
5429 { .FromReg: 266U, .ToReg: ARM::D10 },
5430 { .FromReg: 267U, .ToReg: ARM::D11 },
5431 { .FromReg: 268U, .ToReg: ARM::D12 },
5432 { .FromReg: 269U, .ToReg: ARM::D13 },
5433 { .FromReg: 270U, .ToReg: ARM::D14 },
5434 { .FromReg: 271U, .ToReg: ARM::D15 },
5435 { .FromReg: 272U, .ToReg: ARM::D16 },
5436 { .FromReg: 273U, .ToReg: ARM::D17 },
5437 { .FromReg: 274U, .ToReg: ARM::D18 },
5438 { .FromReg: 275U, .ToReg: ARM::D19 },
5439 { .FromReg: 276U, .ToReg: ARM::D20 },
5440 { .FromReg: 277U, .ToReg: ARM::D21 },
5441 { .FromReg: 278U, .ToReg: ARM::D22 },
5442 { .FromReg: 279U, .ToReg: ARM::D23 },
5443 { .FromReg: 280U, .ToReg: ARM::D24 },
5444 { .FromReg: 281U, .ToReg: ARM::D25 },
5445 { .FromReg: 282U, .ToReg: ARM::D26 },
5446 { .FromReg: 283U, .ToReg: ARM::D27 },
5447 { .FromReg: 284U, .ToReg: ARM::D28 },
5448 { .FromReg: 285U, .ToReg: ARM::D29 },
5449 { .FromReg: 286U, .ToReg: ARM::D30 },
5450 { .FromReg: 287U, .ToReg: ARM::D31 },
5451};
5452extern const unsigned ARMDwarfFlavour0Dwarf2LSize = std::size(ARMDwarfFlavour0Dwarf2L);
5453
5454extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = {
5455 { .FromReg: 0U, .ToReg: ARM::R0 },
5456 { .FromReg: 1U, .ToReg: ARM::R1 },
5457 { .FromReg: 2U, .ToReg: ARM::R2 },
5458 { .FromReg: 3U, .ToReg: ARM::R3 },
5459 { .FromReg: 4U, .ToReg: ARM::R4 },
5460 { .FromReg: 5U, .ToReg: ARM::R5 },
5461 { .FromReg: 6U, .ToReg: ARM::R6 },
5462 { .FromReg: 7U, .ToReg: ARM::R7 },
5463 { .FromReg: 8U, .ToReg: ARM::R8 },
5464 { .FromReg: 9U, .ToReg: ARM::R9 },
5465 { .FromReg: 10U, .ToReg: ARM::R10 },
5466 { .FromReg: 11U, .ToReg: ARM::R11 },
5467 { .FromReg: 12U, .ToReg: ARM::R12 },
5468 { .FromReg: 13U, .ToReg: ARM::SP },
5469 { .FromReg: 14U, .ToReg: ARM::LR },
5470 { .FromReg: 15U, .ToReg: ARM::ZR },
5471 { .FromReg: 143U, .ToReg: ARM::RA_AUTH_CODE },
5472 { .FromReg: 256U, .ToReg: ARM::D0 },
5473 { .FromReg: 257U, .ToReg: ARM::D1 },
5474 { .FromReg: 258U, .ToReg: ARM::D2 },
5475 { .FromReg: 259U, .ToReg: ARM::D3 },
5476 { .FromReg: 260U, .ToReg: ARM::D4 },
5477 { .FromReg: 261U, .ToReg: ARM::D5 },
5478 { .FromReg: 262U, .ToReg: ARM::D6 },
5479 { .FromReg: 263U, .ToReg: ARM::D7 },
5480 { .FromReg: 264U, .ToReg: ARM::D8 },
5481 { .FromReg: 265U, .ToReg: ARM::D9 },
5482 { .FromReg: 266U, .ToReg: ARM::D10 },
5483 { .FromReg: 267U, .ToReg: ARM::D11 },
5484 { .FromReg: 268U, .ToReg: ARM::D12 },
5485 { .FromReg: 269U, .ToReg: ARM::D13 },
5486 { .FromReg: 270U, .ToReg: ARM::D14 },
5487 { .FromReg: 271U, .ToReg: ARM::D15 },
5488 { .FromReg: 272U, .ToReg: ARM::D16 },
5489 { .FromReg: 273U, .ToReg: ARM::D17 },
5490 { .FromReg: 274U, .ToReg: ARM::D18 },
5491 { .FromReg: 275U, .ToReg: ARM::D19 },
5492 { .FromReg: 276U, .ToReg: ARM::D20 },
5493 { .FromReg: 277U, .ToReg: ARM::D21 },
5494 { .FromReg: 278U, .ToReg: ARM::D22 },
5495 { .FromReg: 279U, .ToReg: ARM::D23 },
5496 { .FromReg: 280U, .ToReg: ARM::D24 },
5497 { .FromReg: 281U, .ToReg: ARM::D25 },
5498 { .FromReg: 282U, .ToReg: ARM::D26 },
5499 { .FromReg: 283U, .ToReg: ARM::D27 },
5500 { .FromReg: 284U, .ToReg: ARM::D28 },
5501 { .FromReg: 285U, .ToReg: ARM::D29 },
5502 { .FromReg: 286U, .ToReg: ARM::D30 },
5503 { .FromReg: 287U, .ToReg: ARM::D31 },
5504};
5505extern const unsigned ARMEHFlavour0Dwarf2LSize = std::size(ARMEHFlavour0Dwarf2L);
5506
5507extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = {
5508 { .FromReg: ARM::LR, .ToReg: 14U },
5509 { .FromReg: ARM::PC, .ToReg: 15U },
5510 { .FromReg: ARM::RA_AUTH_CODE, .ToReg: 143U },
5511 { .FromReg: ARM::SP, .ToReg: 13U },
5512 { .FromReg: ARM::ZR, .ToReg: 15U },
5513 { .FromReg: ARM::D0, .ToReg: 256U },
5514 { .FromReg: ARM::D1, .ToReg: 257U },
5515 { .FromReg: ARM::D2, .ToReg: 258U },
5516 { .FromReg: ARM::D3, .ToReg: 259U },
5517 { .FromReg: ARM::D4, .ToReg: 260U },
5518 { .FromReg: ARM::D5, .ToReg: 261U },
5519 { .FromReg: ARM::D6, .ToReg: 262U },
5520 { .FromReg: ARM::D7, .ToReg: 263U },
5521 { .FromReg: ARM::D8, .ToReg: 264U },
5522 { .FromReg: ARM::D9, .ToReg: 265U },
5523 { .FromReg: ARM::D10, .ToReg: 266U },
5524 { .FromReg: ARM::D11, .ToReg: 267U },
5525 { .FromReg: ARM::D12, .ToReg: 268U },
5526 { .FromReg: ARM::D13, .ToReg: 269U },
5527 { .FromReg: ARM::D14, .ToReg: 270U },
5528 { .FromReg: ARM::D15, .ToReg: 271U },
5529 { .FromReg: ARM::D16, .ToReg: 272U },
5530 { .FromReg: ARM::D17, .ToReg: 273U },
5531 { .FromReg: ARM::D18, .ToReg: 274U },
5532 { .FromReg: ARM::D19, .ToReg: 275U },
5533 { .FromReg: ARM::D20, .ToReg: 276U },
5534 { .FromReg: ARM::D21, .ToReg: 277U },
5535 { .FromReg: ARM::D22, .ToReg: 278U },
5536 { .FromReg: ARM::D23, .ToReg: 279U },
5537 { .FromReg: ARM::D24, .ToReg: 280U },
5538 { .FromReg: ARM::D25, .ToReg: 281U },
5539 { .FromReg: ARM::D26, .ToReg: 282U },
5540 { .FromReg: ARM::D27, .ToReg: 283U },
5541 { .FromReg: ARM::D28, .ToReg: 284U },
5542 { .FromReg: ARM::D29, .ToReg: 285U },
5543 { .FromReg: ARM::D30, .ToReg: 286U },
5544 { .FromReg: ARM::D31, .ToReg: 287U },
5545 { .FromReg: ARM::R0, .ToReg: 0U },
5546 { .FromReg: ARM::R1, .ToReg: 1U },
5547 { .FromReg: ARM::R2, .ToReg: 2U },
5548 { .FromReg: ARM::R3, .ToReg: 3U },
5549 { .FromReg: ARM::R4, .ToReg: 4U },
5550 { .FromReg: ARM::R5, .ToReg: 5U },
5551 { .FromReg: ARM::R6, .ToReg: 6U },
5552 { .FromReg: ARM::R7, .ToReg: 7U },
5553 { .FromReg: ARM::R8, .ToReg: 8U },
5554 { .FromReg: ARM::R9, .ToReg: 9U },
5555 { .FromReg: ARM::R10, .ToReg: 10U },
5556 { .FromReg: ARM::R11, .ToReg: 11U },
5557 { .FromReg: ARM::R12, .ToReg: 12U },
5558};
5559extern const unsigned ARMDwarfFlavour0L2DwarfSize = std::size(ARMDwarfFlavour0L2Dwarf);
5560
5561extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = {
5562 { .FromReg: ARM::LR, .ToReg: 14U },
5563 { .FromReg: ARM::PC, .ToReg: 15U },
5564 { .FromReg: ARM::RA_AUTH_CODE, .ToReg: 143U },
5565 { .FromReg: ARM::SP, .ToReg: 13U },
5566 { .FromReg: ARM::ZR, .ToReg: 15U },
5567 { .FromReg: ARM::D0, .ToReg: 256U },
5568 { .FromReg: ARM::D1, .ToReg: 257U },
5569 { .FromReg: ARM::D2, .ToReg: 258U },
5570 { .FromReg: ARM::D3, .ToReg: 259U },
5571 { .FromReg: ARM::D4, .ToReg: 260U },
5572 { .FromReg: ARM::D5, .ToReg: 261U },
5573 { .FromReg: ARM::D6, .ToReg: 262U },
5574 { .FromReg: ARM::D7, .ToReg: 263U },
5575 { .FromReg: ARM::D8, .ToReg: 264U },
5576 { .FromReg: ARM::D9, .ToReg: 265U },
5577 { .FromReg: ARM::D10, .ToReg: 266U },
5578 { .FromReg: ARM::D11, .ToReg: 267U },
5579 { .FromReg: ARM::D12, .ToReg: 268U },
5580 { .FromReg: ARM::D13, .ToReg: 269U },
5581 { .FromReg: ARM::D14, .ToReg: 270U },
5582 { .FromReg: ARM::D15, .ToReg: 271U },
5583 { .FromReg: ARM::D16, .ToReg: 272U },
5584 { .FromReg: ARM::D17, .ToReg: 273U },
5585 { .FromReg: ARM::D18, .ToReg: 274U },
5586 { .FromReg: ARM::D19, .ToReg: 275U },
5587 { .FromReg: ARM::D20, .ToReg: 276U },
5588 { .FromReg: ARM::D21, .ToReg: 277U },
5589 { .FromReg: ARM::D22, .ToReg: 278U },
5590 { .FromReg: ARM::D23, .ToReg: 279U },
5591 { .FromReg: ARM::D24, .ToReg: 280U },
5592 { .FromReg: ARM::D25, .ToReg: 281U },
5593 { .FromReg: ARM::D26, .ToReg: 282U },
5594 { .FromReg: ARM::D27, .ToReg: 283U },
5595 { .FromReg: ARM::D28, .ToReg: 284U },
5596 { .FromReg: ARM::D29, .ToReg: 285U },
5597 { .FromReg: ARM::D30, .ToReg: 286U },
5598 { .FromReg: ARM::D31, .ToReg: 287U },
5599 { .FromReg: ARM::R0, .ToReg: 0U },
5600 { .FromReg: ARM::R1, .ToReg: 1U },
5601 { .FromReg: ARM::R2, .ToReg: 2U },
5602 { .FromReg: ARM::R3, .ToReg: 3U },
5603 { .FromReg: ARM::R4, .ToReg: 4U },
5604 { .FromReg: ARM::R5, .ToReg: 5U },
5605 { .FromReg: ARM::R6, .ToReg: 6U },
5606 { .FromReg: ARM::R7, .ToReg: 7U },
5607 { .FromReg: ARM::R8, .ToReg: 8U },
5608 { .FromReg: ARM::R9, .ToReg: 9U },
5609 { .FromReg: ARM::R10, .ToReg: 10U },
5610 { .FromReg: ARM::R11, .ToReg: 11U },
5611 { .FromReg: ARM::R12, .ToReg: 12U },
5612};
5613extern const unsigned ARMEHFlavour0L2DwarfSize = std::size(ARMEHFlavour0L2Dwarf);
5614
5615extern const uint16_t ARMRegEncodingTable[] = {
5616 0,
5617 15,
5618 15,
5619 0,
5620 14,
5621 15,
5622 8,
5623 9,
5624 3,
5625 3,
5626 2,
5627 3,
5628 0,
5629 4,
5630 14,
5631 15,
5632 12,
5633 13,
5634 2,
5635 64,
5636 15,
5637 0,
5638 1,
5639 2,
5640 3,
5641 4,
5642 5,
5643 6,
5644 7,
5645 8,
5646 9,
5647 10,
5648 11,
5649 12,
5650 13,
5651 14,
5652 15,
5653 16,
5654 17,
5655 18,
5656 19,
5657 20,
5658 21,
5659 22,
5660 23,
5661 24,
5662 25,
5663 26,
5664 27,
5665 28,
5666 29,
5667 30,
5668 31,
5669 10,
5670 7,
5671 6,
5672 5,
5673 13,
5674 0,
5675 1,
5676 2,
5677 3,
5678 4,
5679 5,
5680 6,
5681 7,
5682 8,
5683 9,
5684 10,
5685 11,
5686 12,
5687 13,
5688 14,
5689 15,
5690 0,
5691 1,
5692 2,
5693 3,
5694 4,
5695 5,
5696 6,
5697 7,
5698 8,
5699 9,
5700 10,
5701 11,
5702 12,
5703 0,
5704 1,
5705 2,
5706 3,
5707 4,
5708 5,
5709 6,
5710 7,
5711 8,
5712 9,
5713 10,
5714 11,
5715 12,
5716 13,
5717 14,
5718 15,
5719 16,
5720 17,
5721 18,
5722 19,
5723 20,
5724 21,
5725 22,
5726 23,
5727 24,
5728 25,
5729 26,
5730 27,
5731 28,
5732 29,
5733 30,
5734 31,
5735 0,
5736 1,
5737 2,
5738 3,
5739 4,
5740 5,
5741 6,
5742 7,
5743 8,
5744 9,
5745 10,
5746 11,
5747 12,
5748 13,
5749 14,
5750 15,
5751 16,
5752 17,
5753 18,
5754 19,
5755 20,
5756 21,
5757 22,
5758 23,
5759 24,
5760 25,
5761 26,
5762 27,
5763 28,
5764 29,
5765 0,
5766 1,
5767 2,
5768 3,
5769 4,
5770 5,
5771 6,
5772 7,
5773 8,
5774 9,
5775 10,
5776 11,
5777 12,
5778 13,
5779 14,
5780 0,
5781 1,
5782 2,
5783 3,
5784 4,
5785 5,
5786 6,
5787 7,
5788 8,
5789 9,
5790 10,
5791 11,
5792 12,
5793 0,
5794 2,
5795 4,
5796 6,
5797 8,
5798 10,
5799 12,
5800 0,
5801 1,
5802 2,
5803 3,
5804 4,
5805 5,
5806 6,
5807 7,
5808 8,
5809 9,
5810 10,
5811 11,
5812 12,
5813 13,
5814 14,
5815 15,
5816 16,
5817 17,
5818 18,
5819 19,
5820 20,
5821 21,
5822 22,
5823 23,
5824 24,
5825 25,
5826 26,
5827 27,
5828 28,
5829 29,
5830 0,
5831 1,
5832 2,
5833 3,
5834 4,
5835 5,
5836 6,
5837 7,
5838 8,
5839 9,
5840 10,
5841 11,
5842 12,
5843 13,
5844 14,
5845 15,
5846 16,
5847 17,
5848 18,
5849 19,
5850 20,
5851 21,
5852 22,
5853 23,
5854 24,
5855 25,
5856 26,
5857 27,
5858 0,
5859 1,
5860 2,
5861 3,
5862 4,
5863 5,
5864 6,
5865 7,
5866 8,
5867 9,
5868 10,
5869 11,
5870 12,
5871 13,
5872 14,
5873 15,
5874 16,
5875 17,
5876 18,
5877 19,
5878 20,
5879 21,
5880 22,
5881 23,
5882 24,
5883 25,
5884 1,
5885 3,
5886 5,
5887 7,
5888 9,
5889 11,
5890 13,
5891 15,
5892 17,
5893 19,
5894 21,
5895 23,
5896 25,
5897 27,
5898 29,
5899 1,
5900 3,
5901 5,
5902 7,
5903 9,
5904 11,
5905 13,
5906 15,
5907 17,
5908 19,
5909 21,
5910 23,
5911 25,
5912 27,
5913};
5914static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
5915 RI->InitMCRegisterInfo(D: ARMRegDesc, NR: 297, RA, PC, C: ARMMCRegisterClassStorage.Classes, NC: 137, RURoots: ARMRegUnitRoots, NRU: 88, DL: ARMRegDiffLists, RUMS: ARMLaneMaskLists, Strings: ARMRegStrings, ClassStrings: ARMRegClassStrings, SubIndices: ARMSubRegIdxLists, NumIndices: 57,
5916RET: ARMRegEncodingTable, RUI: nullptr);
5917
5918 switch (DwarfFlavour) {
5919 default:
5920 llvm_unreachable("Unknown DWARF flavour");
5921 case 0:
5922 RI->mapDwarfRegsToLLVMRegs(Map: ARMDwarfFlavour0Dwarf2L, Size: ARMDwarfFlavour0Dwarf2LSize, isEH: false);
5923 break;
5924 }
5925 switch (EHFlavour) {
5926 default:
5927 llvm_unreachable("Unknown DWARF flavour");
5928 case 0:
5929 RI->mapDwarfRegsToLLVMRegs(Map: ARMEHFlavour0Dwarf2L, Size: ARMEHFlavour0Dwarf2LSize, isEH: true);
5930 break;
5931 }
5932 switch (DwarfFlavour) {
5933 default:
5934 llvm_unreachable("Unknown DWARF flavour");
5935 case 0:
5936 RI->mapLLVMRegsToDwarfRegs(Map: ARMDwarfFlavour0L2Dwarf, Size: ARMDwarfFlavour0L2DwarfSize, isEH: false);
5937 break;
5938 }
5939 switch (EHFlavour) {
5940 default:
5941 llvm_unreachable("Unknown DWARF flavour");
5942 case 0:
5943 RI->mapLLVMRegsToDwarfRegs(Map: ARMEHFlavour0L2Dwarf, Size: ARMEHFlavour0L2DwarfSize, isEH: true);
5944 break;
5945 }
5946}
5947
5948
5949} // namespace llvm
5950