1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t ARMRegDiffLists[] = {
12 /* 0 */ -248, 1, 1, 1, 230, 1, -136, 65, -64, 65, -140, 0,
13 /* 12 */ -249, 1, 1, 1, 231, 1, -137, 65, -64, 65, -139, 0,
14 /* 24 */ -250, 1, 1, 1, 232, 1, -138, 65, -64, 65, -138, 0,
15 /* 36 */ -251, 1, 1, 1, 233, 1, -139, 65, -64, 65, -137, 0,
16 /* 48 */ -252, 1, 1, 1, 234, 1, -140, 65, -64, 65, -136, 0,
17 /* 60 */ -253, 1, 1, 1, 235, 1, -141, 65, -64, 65, -135, 0,
18 /* 72 */ -15, -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, -117, -91, -23, 1, 23, -22, 1, 95, 65, -64, 65, 69, -44, 28, -27, 28, 28, -150, 65, 30, -94, 65, 30, 40, 15, -134, 0,
19 /* 111 */ -15, -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, -117, -91, -24, 1, 24, -23, 1, 95, 65, -64, 65, 70, -45, 28, -27, 28, 29, -151, 65, 30, -94, 65, 30, 41, 15, -134, 0,
20 /* 150 */ -15, -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, -117, -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, -46, 28, -27, 28, 30, -152, 65, 30, -94, 65, 30, 42, 15, -134, 0,
21 /* 189 */ -15, -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, -117, -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, -47, 28, -27, 28, 31, -153, 65, 30, -94, 65, 30, 43, 15, -134, 0,
22 /* 228 */ -15, -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, -117, -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, -48, 28, -27, 28, 32, -154, 65, 30, -94, 65, 30, 44, 15, -134, 0,
23 /* 267 */ -15, -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, -117, -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, -49, 28, -27, 28, 33, -155, 65, 30, -94, 65, 30, 45, 15, -134, 0,
24 /* 310 */ -15, -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, -117, -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, -50, 28, -27, 28, 34, -156, 65, 30, -94, 65, 30, 46, 15, -134, 0,
25 /* 357 */ -15, -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, -117, -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, -51, 28, -27, 28, 35, -157, 65, 30, -94, 65, 30, 47, 15, -134, 0,
26 /* 408 */ -15, -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, -117, -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, -52, 28, -27, 28, 36, -158, 65, 30, -94, 65, 30, 48, 15, -134, 0,
27 /* 463 */ -15, -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, -117, -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, -53, 28, -27, 28, 37, -159, 65, 30, -94, 65, 30, 49, 15, -134, 0,
28 /* 518 */ -15, -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, -117, -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, -54, 28, -27, 28, 38, -160, 65, 30, -94, 65, 30, 50, 15, -134, 0,
29 /* 573 */ -15, -91, -36, 68, 1, -68, 69, 1, -34, -35, 70, 1, -70, 71, 1, 23, 65, -64, 65, 82, -117, -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, -55, 28, -27, 28, 39, -161, 65, 30, -94, 65, 30, 51, 15, -134, 0,
30 /* 628 */ -15, -91, -37, 66, 1, -66, 67, 1, -31, -36, 68, 1, -68, 69, 1, 25, 65, -64, 65, 83, -117, -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, -56, 28, -27, 28, 40, -162, 65, 30, -94, 65, 30, 52, 15, -134, 0,
31 /* 683 */ -254, 81, 1, -81, 1, 1, 236, 1, -142, 65, -64, 65, -134, 0,
32 /* 697 */ -255, 79, 1, -79, 80, 1, -80, 81, 1, -81, 237, 1, -143, 65, -64, 65, -133, 0,
33 /* 715 */ -256, 77, 1, -77, 78, 1, -78, 79, 1, -79, 80, 1, 157, 1, -144, 65, -64, 65, -132, 0,
34 /* 735 */ -257, 75, 1, -75, 76, 1, -76, 77, 1, -77, 78, 1, 160, 1, -145, 65, -64, 65, -131, 0,
35 /* 755 */ -258, 73, 1, -73, 74, 1, -74, 75, 1, -75, 76, 1, 163, 1, -146, 65, -64, 65, -130, 0,
36 /* 775 */ -259, 71, 1, -71, 72, 1, -72, 73, 1, -73, 74, 1, 166, 1, -147, 65, -64, 65, -129, 0,
37 /* 795 */ -260, 69, 1, -69, 70, 1, -70, 71, 1, -71, 72, 1, 169, 1, -148, 65, -64, 65, -128, 0,
38 /* 815 */ -261, 67, 1, -67, 68, 1, -68, 69, 1, -69, 70, 1, 172, 1, -149, 65, -64, 65, -127, 0,
39 /* 835 */ 23, 73, 2, 63, -48, 120, -71, 1, -49, 75, 26, -89, 65, 26, 30, -120, 66, 26, 29, -120, 0,
40 /* 856 */ 22, 74, 2, 63, -49, 120, -70, 1, -50, 76, 26, -90, 66, 26, 29, -120, 0,
41 /* 873 */ 65, -49, 77, 26, -90, 66, 26, 29, -120, 0,
42 /* 883 */ 23, 73, 2, 134, -71, 1, -49, 50, -49, 75, 26, 31, -120, 65, 26, 30, -120, 0,
43 /* 901 */ 22, 74, 135, -70, 1, -50, 77, 26, 30, -120, 0,
44 /* 912 */ 65, -49, 77, 26, 30, -120, 0,
45 /* 919 */ -71, 1, -49, 133, -120, 121, -120, 0,
46 /* 927 */ 139, -49, 50, -49, 12, 121, -120, 0,
47 /* 935 */ -49, 13, 121, -120, 0,
48 /* 940 */ -70, 1, -50, 133, -120, 0,
49 /* 946 */ -49, 133, -120, 0,
50 /* 950 */ -68, 36, 62, 148, -84, 1, -36, 66, 28, 40, -119, 0,
51 /* 962 */ -67, 36, 62, 148, -84, 1, -36, 66, 28, 40, -119, 0,
52 /* 974 */ 65, -36, 66, 28, 40, -119, 0,
53 /* 981 */ -84, 1, -36, 134, -119, 0,
54 /* 987 */ -221, 75, 1, -74, 77, 1, -76, 79, 1, -78, 81, 1, 10, 95, -93, 95, -93, 0,
55 /* 1005 */ -221, 74, 1, -73, 76, 1, -75, 78, 1, -77, 80, 1, 11, 95, -93, 95, -93, 0,
56 /* 1023 */ -221, 73, 1, -72, 75, 1, -74, 77, 1, -76, 79, 1, 12, 95, -93, 95, -93, 0,
57 /* 1041 */ -221, 72, 1, -71, 74, 1, -73, 76, 1, -75, 78, 1, 13, 95, -93, 95, -93, 0,
58 /* 1059 */ -221, 71, 1, -70, 73, 1, -72, 75, 1, -74, 77, 1, 14, 95, -93, 95, -93, 0,
59 /* 1077 */ -221, 70, 1, -69, 72, 1, -71, 74, 1, -73, 76, 1, 15, 95, -93, 95, -93, 0,
60 /* 1095 */ -221, 69, 1, -68, 71, 1, -70, 73, 1, -72, 75, 1, 16, 95, -93, 95, -93, 0,
61 /* 1113 */ -221, 68, 1, -67, 70, 1, -69, 72, 1, -71, 74, 1, 17, 95, -93, 95, -93, 0,
62 /* 1131 */ -221, 67, 1, -66, 69, 1, -68, 71, 1, -70, 73, 1, 18, 95, -93, 95, -93, 0,
63 /* 1149 */ -221, 66, 1, -65, 68, 1, -67, 70, 1, -69, 72, 1, 19, 95, -93, 95, -93, 0,
64 /* 1167 */ -221, 77, 1, -76, 79, 1, -78, 81, 1, -80, 92, 95, -93, 95, -93, 0,
65 /* 1183 */ -221, 76, 1, -75, 78, 1, -77, 80, 1, -79, 92, 95, -93, 95, -93, 0,
66 /* 1199 */ -221, 79, 1, -78, 81, 1, -80, 2, 92, 95, -93, 95, -93, 0,
67 /* 1213 */ -221, 78, 1, -77, 80, 1, -79, 2, 92, 95, -93, 95, -93, 0,
68 /* 1227 */ -221, 81, 1, -80, 2, 2, 92, 95, -93, 95, -93, 0,
69 /* 1239 */ -221, 80, 1, -79, 2, 2, 92, 95, -93, 95, -93, 0,
70 /* 1251 */ -221, 2, 2, 2, 92, 95, -93, 95, -93, 0,
71 /* 1261 */ 21, 75, 65, -50, 78, 26, -91, 0,
72 /* 1269 */ 24, 72, 2, 63, -47, 120, -72, 1, -48, 74, 26, -88, 64, 26, 31, -120, 65, 26, 30, -120, 92, -91, 0,
73 /* 1292 */ 65, -48, 76, 26, -89, 65, 26, 30, -120, 92, -91, 0,
74 /* 1304 */ 26, -90, 92, -91, 0,
75 /* 1309 */ 24, 72, 2, 135, -72, 1, -48, 49, -48, 74, 26, 32, -120, 64, 26, 31, -120, 65, 26, -90, 0,
76 /* 1330 */ 65, -48, 76, 26, 31, -120, 65, 26, -90, 0,
77 /* 1340 */ 25, 71, 2, 63, -46, 120, -73, 1, -47, 73, 26, -87, 63, 26, 32, -120, 64, 26, 31, -120, 91, -90, 0,
78 /* 1363 */ 65, -47, 75, 26, -88, 64, 26, 31, -120, 91, -90, 0,
79 /* 1375 */ 25, 71, 2, 136, -73, 1, -47, 48, -47, 73, 26, 33, -120, 63, 26, 32, -120, 64, 26, -89, 91, -90, 0,
80 /* 1398 */ 65, -47, 75, 26, 32, -120, 64, 26, -89, 91, -90, 0,
81 /* 1410 */ 26, 70, 2, 63, -45, 120, -74, 1, -46, 72, 26, -86, 62, 26, 33, -120, 63, 26, 32, -120, 90, -89, 0,
82 /* 1433 */ 65, -46, 74, 26, -87, 63, 26, 32, -120, 90, -89, 0,
83 /* 1445 */ 26, 70, 2, 137, -74, 1, -46, 47, -46, 72, 26, 34, -120, 62, 26, 33, -120, 63, 26, -88, 90, -89, 0,
84 /* 1468 */ 65, -46, 74, 26, 33, -120, 63, 26, -88, 90, -89, 0,
85 /* 1480 */ 27, 69, 2, 63, -44, 120, -75, 1, -45, 71, 26, -85, 61, 26, 34, -120, 62, 26, 33, -120, 89, -88, 0,
86 /* 1503 */ 65, -45, 73, 26, -86, 62, 26, 33, -120, 89, -88, 0,
87 /* 1515 */ 27, 69, 2, 138, -75, 1, -45, 46, -45, 71, 26, 35, -120, 61, 26, 34, -120, 62, 26, -87, 89, -88, 0,
88 /* 1538 */ 65, -45, 73, 26, 34, -120, 62, 26, -87, 89, -88, 0,
89 /* 1550 */ 28, 68, 2, 63, -43, 120, -76, 1, -44, 70, 26, -84, 60, 26, 35, -120, 61, 26, 34, -120, 88, -87, 0,
90 /* 1573 */ 65, -44, 72, 26, -85, 61, 26, 34, -120, 88, -87, 0,
91 /* 1585 */ 28, 68, 2, 139, -76, 1, -44, 45, -44, 70, 26, 36, -120, 60, 26, 35, -120, 61, 26, -86, 88, -87, 0,
92 /* 1608 */ 65, -44, 72, 26, 35, -120, 61, 26, -86, 88, -87, 0,
93 /* 1620 */ -82, 29, 67, 2, 63, -42, 120, -77, 1, -43, 69, 26, -83, 59, 26, 36, -120, 60, 26, 35, -120, 87, -86, 0,
94 /* 1644 */ -81, 29, 67, 2, 63, -42, 120, -77, 1, -43, 69, 26, -83, 59, 26, 36, -120, 60, 26, 35, -120, 87, -86, 0,
95 /* 1668 */ 65, -43, 71, 26, -84, 60, 26, 35, -120, 87, -86, 0,
96 /* 1680 */ 29, 67, 2, 140, -77, 1, -43, 44, -43, 69, 26, 37, -120, 59, 26, 36, -120, 60, 26, -85, 87, -86, 0,
97 /* 1703 */ 65, -43, 71, 26, 36, -120, 60, 26, -85, 87, -86, 0,
98 /* 1715 */ -80, 30, 66, 2, 63, -41, 120, -78, 1, -42, 68, 26, -82, 58, 26, 37, -120, 59, 26, 36, -120, 86, -85, 0,
99 /* 1739 */ -79, 30, 66, 2, 63, -41, 120, -78, 1, -42, 68, 26, -82, 58, 26, 37, -120, 59, 26, 36, -120, 86, -85, 0,
100 /* 1763 */ 65, -42, 70, 26, -83, 59, 26, 36, -120, 86, -85, 0,
101 /* 1775 */ -81, 30, 66, 2, 141, -78, 1, -42, 43, -42, 68, 26, 38, -120, 58, 26, 37, -120, 59, 26, -84, 86, -85, 0,
102 /* 1799 */ -80, 30, 66, 2, 141, -78, 1, -42, 43, -42, 68, 26, 38, -120, 58, 26, 37, -120, 59, 26, -84, 86, -85, 0,
103 /* 1823 */ 65, -42, 70, 26, 37, -120, 59, 26, -84, 86, -85, 0,
104 /* 1835 */ -78, 31, 65, 2, 63, -40, 120, -79, 1, -41, 67, 26, -81, 57, 26, 38, -120, 58, 26, 37, -120, 85, -84, 0,
105 /* 1859 */ -77, 31, 65, 2, 63, -40, 120, -79, 1, -41, 67, 26, -81, 57, 26, 38, -120, 58, 26, 37, -120, 85, -84, 0,
106 /* 1883 */ 65, -41, 69, 26, -82, 58, 26, 37, -120, 85, -84, 0,
107 /* 1895 */ -79, 31, 65, 2, 142, -79, 1, -41, 42, -41, 67, 26, 39, -120, 57, 26, 38, -120, 58, 26, -83, 85, -84, 0,
108 /* 1919 */ -78, 31, 65, 2, 142, -79, 1, -41, 42, -41, 67, 26, 39, -120, 57, 26, 38, -120, 58, 26, -83, 85, -84, 0,
109 /* 1943 */ 65, -41, 69, 26, 38, -120, 58, 26, -83, 85, -84, 0,
110 /* 1955 */ -76, 32, 64, 2, 63, -39, 120, -80, 1, -40, 66, 26, -80, 56, 26, 39, -120, 57, 26, 38, -120, 84, -83, 0,
111 /* 1979 */ -75, 32, 64, 2, 63, -39, 120, -80, 1, -40, 66, 26, -80, 56, 26, 39, -120, 57, 26, 38, -120, 84, -83, 0,
112 /* 2003 */ 65, -40, 68, 26, -81, 57, 26, 38, -120, 84, -83, 0,
113 /* 2015 */ -77, 32, 64, 2, 143, -80, 1, -40, 41, -40, 66, 26, 40, -120, 56, 26, 39, -120, 57, 26, -82, 84, -83, 0,
114 /* 2039 */ -76, 32, 64, 2, 143, -80, 1, -40, 41, -40, 66, 26, 40, -120, 56, 26, 39, -120, 57, 26, -82, 84, -83, 0,
115 /* 2063 */ 65, -40, 68, 26, 39, -120, 57, 26, -82, 84, -83, 0,
116 /* 2075 */ -74, 33, 63, 2, 63, -38, 120, -81, 1, -39, 65, 26, -79, 55, 26, 40, -120, 56, 26, 39, -120, 83, -82, 0,
117 /* 2099 */ -73, 33, 63, 2, 63, -38, 120, -81, 1, -39, 65, 26, -79, 55, 26, 40, -120, 56, 26, 39, -120, 83, -82, 0,
118 /* 2123 */ 65, -39, 67, 26, -80, 56, 26, 39, -120, 83, -82, 0,
119 /* 2135 */ -75, 33, 63, 2, 144, -81, 1, -39, 40, -39, 65, 26, 41, -120, 55, 26, 40, -120, 56, 26, -81, 83, -82, 0,
120 /* 2159 */ -74, 33, 63, 2, 144, -81, 1, -39, 40, -39, 65, 26, 41, -120, 55, 26, 40, -120, 56, 26, -81, 83, -82, 0,
121 /* 2183 */ 65, -39, 67, 26, 40, -120, 56, 26, -81, 83, -82, 0,
122 /* 2195 */ -239, 81, 1, -81, 0,
123 /* 2200 */ -72, 34, 62, 2, 63, -37, 120, -82, 1, -38, 64, 2, 26, 41, -120, 55, 26, 40, -120, 82, -81, 0,
124 /* 2222 */ -71, 34, 62, 2, 63, -37, 120, -82, 1, -38, 64, 2, 26, 41, -120, 55, 26, 40, -120, 82, -81, 0,
125 /* 2244 */ 65, -38, 66, 26, -79, 55, 26, 40, -120, 82, -81, 0,
126 /* 2256 */ -73, 34, 62, 2, 145, -82, 1, -38, 39, -38, 64, 26, 42, -120, 54, 26, 41, -120, 55, 26, -80, 82, -81, 0,
127 /* 2280 */ -72, 34, 62, 2, 145, -82, 1, -38, 39, -38, 64, 26, 42, -120, 54, 26, 41, -120, 55, 26, -80, 82, -81, 0,
128 /* 2304 */ 65, -38, 66, 26, 41, -120, 55, 26, -80, 82, -81, 0,
129 /* 2316 */ -98, 81, 1, -80, 0,
130 /* 2321 */ -70, 35, 61, 2, 63, -36, 120, -83, 1, -37, 65, 2, 26, 40, 1, -120, 81, -80, 0,
131 /* 2340 */ -69, 35, 61, 2, 63, -36, 120, -83, 1, -37, 65, 2, 26, 40, 1, -120, 81, -80, 0,
132 /* 2359 */ 65, -37, 65, 2, 26, 41, -120, 81, -80, 0,
133 /* 2369 */ -71, 35, 61, 2, 146, -83, 1, -37, 38, -37, 63, 2, 26, 41, 1, -120, 54, 26, -79, 81, -80, 0,
134 /* 2391 */ -70, 35, 61, 2, 146, -83, 1, -37, 38, -37, 63, 2, 26, 41, 1, -120, 54, 26, -79, 81, -80, 0,
135 /* 2413 */ 65, -37, 65, 26, 42, -120, 54, 26, -79, 81, -80, 0,
136 /* 2425 */ -98, 80, 1, -79, 0,
137 /* 2430 */ 28, -79, 0,
138 /* 2433 */ -69, 36, 60, 2, 147, -84, 1, -36, 37, -36, 64, 2, 26, 41, -119, 80, -79, 0,
139 /* 2451 */ -68, 36, 60, 2, 147, -84, 1, -36, 37, -36, 64, 2, 26, 41, -119, 80, -79, 0,
140 /* 2469 */ 65, -36, 64, 2, 26, 41, -119, 80, -79, 0,
141 /* 2479 */ 26, -78, 80, -79, 0,
142 /* 2484 */ -67, 37, 61, 65, -35, 65, 28, -78, 0,
143 /* 2493 */ -66, 37, 61, 65, -35, 65, 28, -78, 0,
144 /* 2502 */ -163, 1, 1, 230, -134, -75, 0,
145 /* 2509 */ -163, 1, 1, 231, -135, -74, 0,
146 /* 2516 */ -163, 1, 1, 232, -136, -73, 0,
147 /* 2523 */ -163, 1, 1, 233, -137, -72, 0,
148 /* 2530 */ -163, 1, 1, 234, -138, -71, 0,
149 /* 2537 */ -163, 1, 1, 235, -139, -70, 0,
150 /* 2544 */ -163, 1, 1, 236, -140, -69, 0,
151 /* 2551 */ -97, -69, 0,
152 /* 2554 */ -163, 81, 1, -81, 1, 237, -141, -68, 0,
153 /* 2563 */ -163, 79, 1, -79, 80, 1, -80, 81, 1, 156, -142, -67, 0,
154 /* 2576 */ -163, 77, 1, -77, 78, 1, -78, 79, 1, 159, -143, -66, 0,
155 /* 2589 */ -163, 75, 1, -75, 76, 1, -76, 77, 1, 162, -144, -65, 0,
156 /* 2602 */ -163, 73, 1, -73, 74, 1, -74, 75, 1, 165, -145, -64, 0,
157 /* 2615 */ -163, 71, 1, -71, 72, 1, -72, 73, 1, 168, -146, -63, 0,
158 /* 2628 */ -163, 69, 1, -69, 70, 1, -70, 71, 1, 171, -147, -62, 0,
159 /* 2641 */ -163, 67, 1, -67, 68, 1, -68, 69, 1, 174, -148, -61, 0,
160 /* 2654 */ -238, 1, 0,
161 /* 2657 */ -237, 1, 0,
162 /* 2660 */ -236, 1, 0,
163 /* 2663 */ -235, 1, 0,
164 /* 2666 */ -234, 1, 0,
165 /* 2669 */ -233, 1, 0,
166 /* 2672 */ -232, 1, 0,
167 /* 2675 */ -83, 1, -37, 133, 1, -120, 1, 0,
168 /* 2683 */ -72, 1, -48, 133, -120, 121, -120, 1, 0,
169 /* 2692 */ -73, 1, -47, 133, -120, 121, -120, 1, 0,
170 /* 2701 */ -74, 1, -46, 133, -120, 121, -120, 1, 0,
171 /* 2710 */ -75, 1, -45, 133, -120, 121, -120, 1, 0,
172 /* 2719 */ -76, 1, -44, 133, -120, 121, -120, 1, 0,
173 /* 2728 */ -77, 1, -43, 133, -120, 121, -120, 1, 0,
174 /* 2737 */ -78, 1, -42, 133, -120, 121, -120, 1, 0,
175 /* 2746 */ -79, 1, -41, 133, -120, 121, -120, 1, 0,
176 /* 2755 */ -80, 1, -40, 133, -120, 121, -120, 1, 0,
177 /* 2764 */ -81, 1, -39, 133, -120, 121, -120, 1, 0,
178 /* 2773 */ -82, 1, -38, 133, -120, 121, -120, 1, 0,
179 /* 2782 */ 138, -48, 49, -48, 12, 121, -120, 1, 0,
180 /* 2791 */ -48, 13, 121, -120, 1, 0,
181 /* 2797 */ -47, 13, 121, -120, 1, 0,
182 /* 2803 */ -46, 13, 121, -120, 1, 0,
183 /* 2809 */ -45, 13, 121, -120, 1, 0,
184 /* 2815 */ -44, 13, 121, -120, 1, 0,
185 /* 2821 */ -43, 13, 121, -120, 1, 0,
186 /* 2827 */ -42, 13, 121, -120, 1, 0,
187 /* 2833 */ -41, 13, 121, -120, 1, 0,
188 /* 2839 */ -40, 13, 121, -120, 1, 0,
189 /* 2845 */ -39, 13, 121, -120, 1, 0,
190 /* 2851 */ -38, 13, 121, -120, 1, 0,
191 /* 2857 */ -48, 133, -120, 1, 0,
192 /* 2862 */ -37, 134, -120, 1, 0,
193 /* 2867 */ 126, -36, 37, -36, 133, -119, 1, 0,
194 /* 2875 */ -103, 1, 0,
195 /* 2878 */ -102, 1, 0,
196 /* 2881 */ -101, 1, 0,
197 /* 2884 */ -100, 1, 0,
198 /* 2887 */ -99, 1, 0,
199 /* 2890 */ -98, 1, 0,
200 /* 2893 */ -29, 1, 0,
201 /* 2896 */ -28, 1, 0,
202 /* 2899 */ -27, 1, 0,
203 /* 2902 */ -26, 1, 0,
204 /* 2905 */ -25, 1, 0,
205 /* 2908 */ -24, 1, 0,
206 /* 2911 */ -23, 1, 0,
207 /* 2914 */ -22, 1, 0,
208 /* 2917 */ 137, -47, 48, -47, 12, 121, -120, 1, 1, 0,
209 /* 2927 */ 136, -46, 47, -46, 12, 121, -120, 1, 1, 0,
210 /* 2937 */ 135, -45, 46, -45, 12, 121, -120, 1, 1, 0,
211 /* 2947 */ 134, -44, 45, -44, 12, 121, -120, 1, 1, 0,
212 /* 2957 */ 133, -43, 44, -43, 12, 121, -120, 1, 1, 0,
213 /* 2967 */ 132, -42, 43, -42, 12, 121, -120, 1, 1, 0,
214 /* 2977 */ 131, -41, 42, -41, 12, 121, -120, 1, 1, 0,
215 /* 2987 */ 130, -40, 41, -40, 12, 121, -120, 1, 1, 0,
216 /* 2997 */ 129, -39, 40, -39, 12, 121, -120, 1, 1, 0,
217 /* 3007 */ 128, -38, 39, -38, 12, 121, -120, 1, 1, 0,
218 /* 3017 */ -47, 133, -120, 1, 1, 0,
219 /* 3023 */ -46, 133, -120, 1, 1, 0,
220 /* 3029 */ -45, 133, -120, 1, 1, 0,
221 /* 3035 */ -44, 133, -120, 1, 1, 0,
222 /* 3041 */ -43, 133, -120, 1, 1, 0,
223 /* 3047 */ -42, 133, -120, 1, 1, 0,
224 /* 3053 */ -41, 133, -120, 1, 1, 0,
225 /* 3059 */ -40, 133, -120, 1, 1, 0,
226 /* 3065 */ -39, 133, -120, 1, 1, 0,
227 /* 3071 */ -38, 133, -120, 1, 1, 0,
228 /* 3077 */ 127, -37, 38, -37, 133, -120, 1, 1, 0,
229 /* 3086 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
230 /* 3102 */ 13, 1, 1, 0,
231 /* 3106 */ 1, 3, 1, 3, 1, 3, 1, 0,
232 /* 3114 */ 13, 1, 0,
233 /* 3117 */ 14, 1, 0,
234 /* 3120 */ 66, 1, 0,
235 /* 3123 */ -37, 66, 1, -66, 67, 1, 0,
236 /* 3130 */ -246, 67, 1, -67, 68, 1, 0,
237 /* 3137 */ -98, 66, 1, -65, 68, 1, 0,
238 /* 3144 */ -36, 68, 1, -68, 69, 1, 0,
239 /* 3151 */ -98, 67, 1, -66, 69, 1, 0,
240 /* 3158 */ -245, 69, 1, -69, 70, 1, 0,
241 /* 3165 */ -98, 68, 1, -67, 70, 1, 0,
242 /* 3172 */ -35, 70, 1, -70, 71, 1, 0,
243 /* 3179 */ -98, 69, 1, -68, 71, 1, 0,
244 /* 3186 */ -244, 71, 1, -71, 72, 1, 0,
245 /* 3193 */ -98, 70, 1, -69, 72, 1, 0,
246 /* 3200 */ -34, 72, 1, -72, 73, 1, 0,
247 /* 3207 */ -98, 71, 1, -70, 73, 1, 0,
248 /* 3214 */ -243, 73, 1, -73, 74, 1, 0,
249 /* 3221 */ -98, 72, 1, -71, 74, 1, 0,
250 /* 3228 */ -33, 74, 1, -74, 75, 1, 0,
251 /* 3235 */ -98, 73, 1, -72, 75, 1, 0,
252 /* 3242 */ -242, 75, 1, -75, 76, 1, 0,
253 /* 3249 */ -98, 74, 1, -73, 76, 1, 0,
254 /* 3256 */ -32, 76, 1, -76, 77, 1, 0,
255 /* 3263 */ -98, 75, 1, -74, 77, 1, 0,
256 /* 3270 */ -241, 77, 1, -77, 78, 1, 0,
257 /* 3277 */ -98, 76, 1, -75, 78, 1, 0,
258 /* 3284 */ -31, 78, 1, -78, 79, 1, 0,
259 /* 3291 */ -98, 77, 1, -76, 79, 1, 0,
260 /* 3298 */ -240, 79, 1, -79, 80, 1, 0,
261 /* 3305 */ -98, 78, 1, -77, 80, 1, 0,
262 /* 3312 */ -30, 80, 1, -80, 81, 1, 0,
263 /* 3319 */ -98, 79, 1, -78, 81, 1, 0,
264 /* 3326 */ -98, 2, 0,
265 /* 3329 */ 1, 3, 1, 3, 1, 2, 0,
266 /* 3336 */ 1, 3, 1, 2, 2, 0,
267 /* 3342 */ 1, 2, 2, 2, 0,
268 /* 3347 */ 1, 3, 2, 2, 0,
269 /* 3352 */ 1, 3, 1, 3, 2, 0,
270 /* 3358 */ -193, 77, 1, -76, 79, 1, -78, 81, 1, 12, 2, 0,
271 /* 3370 */ -193, 76, 1, -75, 78, 1, -77, 80, 1, 13, 2, 0,
272 /* 3382 */ -193, 75, 1, -74, 77, 1, -76, 79, 1, 14, 2, 0,
273 /* 3394 */ -193, 74, 1, -73, 76, 1, -75, 78, 1, 15, 2, 0,
274 /* 3406 */ -193, 73, 1, -72, 75, 1, -74, 77, 1, 16, 2, 0,
275 /* 3418 */ -193, 72, 1, -71, 74, 1, -73, 76, 1, 17, 2, 0,
276 /* 3430 */ -193, 71, 1, -70, 73, 1, -72, 75, 1, 18, 2, 0,
277 /* 3442 */ -193, 70, 1, -69, 72, 1, -71, 74, 1, 19, 2, 0,
278 /* 3454 */ -193, 69, 1, -68, 71, 1, -70, 73, 1, 20, 2, 0,
279 /* 3466 */ -193, 68, 1, -67, 70, 1, -69, 72, 1, 21, 2, 0,
280 /* 3478 */ -193, 67, 1, -66, 69, 1, -68, 71, 1, 22, 2, 0,
281 /* 3490 */ -193, 66, 1, -65, 68, 1, -67, 70, 1, 23, 2, 0,
282 /* 3502 */ -193, 79, 1, -78, 81, 1, -80, 94, 2, 0,
283 /* 3512 */ -193, 78, 1, -77, 80, 1, -79, 94, 2, 0,
284 /* 3522 */ -193, 81, 1, -80, 2, 94, 2, 0,
285 /* 3530 */ -193, 80, 1, -79, 2, 94, 2, 0,
286 /* 3538 */ -193, 2, 2, 94, 2, 0,
287 /* 3544 */ 1, 3, 1, 3, 1, 3, 0,
288 /* 3551 */ 140, -50, 13, 0,
289 /* 3555 */ 126, -35, 15, 0,
290 /* 3559 */ -91, -23, 1, 23, -22, 1, 95, 65, -64, 65, 69, 0,
291 /* 3571 */ -91, -24, 1, 24, -23, 1, 95, 65, -64, 65, 70, 0,
292 /* 3583 */ -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, 0,
293 /* 3595 */ -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, 0,
294 /* 3607 */ -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, 0,
295 /* 3619 */ -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, 0,
296 /* 3631 */ -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, 0,
297 /* 3643 */ -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, 0,
298 /* 3659 */ -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, 0,
299 /* 3679 */ -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, 0,
300 /* 3699 */ -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, 0,
301 /* 3719 */ -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, 0,
302 /* 3739 */ -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, 0,
303 /* 3759 */ -91, -36, 68, 1, -68, 69, 1, -34, -35, 70, 1, -70, 71, 1, 23, 65, -64, 65, 82, 0,
304 /* 3779 */ -91, -37, 66, 1, -66, 67, 1, -31, -36, 68, 1, -68, 69, 1, 25, 65, -64, 65, 83, 0,
305 /* 3799 */ 97, 0,
306 /* 3801 */ 98, 0,
307 /* 3803 */ 99, 0,
308 /* 3805 */ 100, 0,
309 /* 3807 */ 101, 0,
310 /* 3809 */ 102, 0,
311 /* 3811 */ 103, 0,
312 /* 3813 */ -163, 1, 1, 21, 75, 135, 0,
313 /* 3820 */ -163, 1, 1, 22, 74, 136, 0,
314 /* 3827 */ -163, 1, 1, 23, 73, 137, 0,
315 /* 3834 */ -163, 1, 1, 24, 72, 138, 0,
316 /* 3841 */ -163, 1, 1, 25, 71, 139, 0,
317 /* 3848 */ -163, 1, 1, 26, 70, 140, 0,
318 /* 3855 */ -163, 1, 1, 27, 69, 141, 0,
319 /* 3862 */ -163, 80, 1, -80, 81, 1, -81, 28, 68, 142, 0,
320 /* 3873 */ -163, 78, 1, -78, 79, 1, -79, 80, 1, -52, 67, 143, 0,
321 /* 3886 */ -163, 76, 1, -76, 77, 1, -77, 78, 1, -49, 66, 144, 0,
322 /* 3899 */ -163, 74, 1, -74, 75, 1, -75, 76, 1, -46, 65, 145, 0,
323 /* 3912 */ -163, 72, 1, -72, 73, 1, -73, 74, 1, -43, 64, 146, 0,
324 /* 3925 */ -163, 70, 1, -70, 71, 1, -71, 72, 1, -40, 63, 147, 0,
325 /* 3938 */ -163, 68, 1, -68, 69, 1, -69, 70, 1, -37, 62, 148, 0,
326 /* 3951 */ -163, 66, 1, -66, 67, 1, -67, 68, 1, -34, 61, 149, 0,
327 /* 3964 */ 166, 0,
328};
329
330extern const LaneBitmask ARMLaneMaskLists[] = {
331 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
332 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002),
333 /* 4 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
334 /* 6 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020),
335 /* 10 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000030),
336 /* 13 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030),
337 /* 15 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080),
338 /* 19 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080),
339 /* 25 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x00000000000000C0),
340 /* 28 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x00000000000000C0),
341 /* 30 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x00000000000000C0),
342 /* 35 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0),
343 /* 39 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0),
344 /* 42 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200),
345 /* 50 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000300),
346 /* 57 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300),
347 /* 63 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300),
348 /* 68 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300),
349 /* 72 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800),
350 /* 78 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000C00),
351 /* 83 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00),
352 /* 87 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00),
353 /* 90 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000),
354 /* 98 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x000000000000C000),
355 /* 105 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000C00), LaneBitmask(0x000000000000C000),
356 /* 111 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00), LaneBitmask(0x000000000000C000),
357 /* 116 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00), LaneBitmask(0x000000000000C000),
358 /* 120 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000020000),
359 /* 136 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
360 /* 150 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000C00), LaneBitmask(0x0000000000003000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
361 /* 162 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300), LaneBitmask(0x0000000000000C00), LaneBitmask(0x0000000000003000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
362 /* 172 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300), LaneBitmask(0x0000000000000C00), LaneBitmask(0x0000000000003000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
363 /* 180 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF),
364};
365
366extern const uint16_t ARMSubRegIdxLists[] = {
367 /* 0 */ 1, 2,
368 /* 2 */ 1, 17, 18, 2,
369 /* 6 */ 1, 3,
370 /* 8 */ 1, 17, 18, 3,
371 /* 12 */ 9, 10,
372 /* 14 */ 17, 18,
373 /* 16 */ 1, 17, 18, 2, 19, 20,
374 /* 22 */ 1, 17, 18, 3, 21, 22,
375 /* 28 */ 1, 2, 3, 13, 33, 37,
376 /* 34 */ 1, 17, 18, 2, 3, 13, 33, 37,
377 /* 42 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37,
378 /* 52 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37,
379 /* 64 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37,
380 /* 75 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37,
381 /* 90 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37,
382 /* 101 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37,
383 /* 114 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37,
384 /* 131 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37,
385 /* 150 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37,
386 /* 169 */ 1, 3, 5, 33, 43,
387 /* 174 */ 1, 17, 18, 3, 5, 33, 43,
388 /* 181 */ 1, 17, 18, 3, 21, 22, 5, 33, 43,
389 /* 190 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43,
390 /* 201 */ 1, 3, 5, 7, 33, 38, 43, 45, 51,
391 /* 210 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51,
392 /* 221 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51,
393 /* 234 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51,
394 /* 249 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51,
395 /* 266 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
396 /* 304 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
397 /* 346 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
398 /* 392 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
399 /* 442 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
400};
401
402
403#ifdef __GNUC__
404#pragma GCC diagnostic push
405#pragma GCC diagnostic ignored "-Woverlength-strings"
406#endif
407extern const char ARMRegStrings[] = {
408 /* 0 */ "D4_D6_D8_D10\000"
409 /* 13 */ "D7_D8_D9_D10\000"
410 /* 26 */ "Q7_Q8_Q9_Q10\000"
411 /* 39 */ "R10\000"
412 /* 43 */ "S10\000"
413 /* 47 */ "D14_D16_D18_D20\000"
414 /* 63 */ "D17_D18_D19_D20\000"
415 /* 79 */ "S20\000"
416 /* 83 */ "D24_D26_D28_D30\000"
417 /* 99 */ "D27_D28_D29_D30\000"
418 /* 115 */ "S30\000"
419 /* 119 */ "D0\000"
420 /* 122 */ "P0\000"
421 /* 125 */ "Q0\000"
422 /* 128 */ "MVFR0\000"
423 /* 134 */ "S0\000"
424 /* 137 */ "D9_D10_D11\000"
425 /* 148 */ "D5_D7_D9_D11\000"
426 /* 161 */ "Q8_Q9_Q10_Q11\000"
427 /* 175 */ "R10_R11\000"
428 /* 183 */ "S11\000"
429 /* 187 */ "D19_D20_D21\000"
430 /* 199 */ "D15_D17_D19_D21\000"
431 /* 215 */ "S21\000"
432 /* 219 */ "D29_D30_D31\000"
433 /* 231 */ "D25_D27_D29_D31\000"
434 /* 247 */ "S31\000"
435 /* 251 */ "D1\000"
436 /* 254 */ "Q0_Q1\000"
437 /* 260 */ "MVFR1\000"
438 /* 266 */ "R0_R1\000"
439 /* 272 */ "S1\000"
440 /* 275 */ "D6_D8_D10_D12\000"
441 /* 289 */ "D9_D10_D11_D12\000"
442 /* 304 */ "Q9_Q10_Q11_Q12\000"
443 /* 319 */ "R12\000"
444 /* 323 */ "S12\000"
445 /* 327 */ "D16_D18_D20_D22\000"
446 /* 343 */ "D19_D20_D21_D22\000"
447 /* 359 */ "S22\000"
448 /* 363 */ "D0_D2\000"
449 /* 369 */ "D0_D1_D2\000"
450 /* 378 */ "Q1_Q2\000"
451 /* 384 */ "MVFR2\000"
452 /* 390 */ "S2\000"
453 /* 393 */ "FPINST2\000"
454 /* 401 */ "D7_D9_D11_D13\000"
455 /* 415 */ "D11_D12_D13\000"
456 /* 427 */ "Q10_Q11_Q12_Q13\000"
457 /* 443 */ "S13\000"
458 /* 447 */ "D17_D19_D21_D23\000"
459 /* 463 */ "D21_D22_D23\000"
460 /* 475 */ "S23\000"
461 /* 479 */ "D1_D3\000"
462 /* 485 */ "D1_D2_D3\000"
463 /* 494 */ "Q0_Q1_Q2_Q3\000"
464 /* 506 */ "R2_R3\000"
465 /* 512 */ "S3\000"
466 /* 515 */ "D8_D10_D12_D14\000"
467 /* 530 */ "D11_D12_D13_D14\000"
468 /* 546 */ "Q11_Q12_Q13_Q14\000"
469 /* 562 */ "S14\000"
470 /* 566 */ "D18_D20_D22_D24\000"
471 /* 582 */ "D21_D22_D23_D24\000"
472 /* 598 */ "S24\000"
473 /* 602 */ "D0_D2_D4\000"
474 /* 611 */ "D1_D2_D3_D4\000"
475 /* 623 */ "Q1_Q2_Q3_Q4\000"
476 /* 635 */ "R4\000"
477 /* 638 */ "S4\000"
478 /* 641 */ "D9_D11_D13_D15\000"
479 /* 656 */ "D13_D14_D15\000"
480 /* 668 */ "Q12_Q13_Q14_Q15\000"
481 /* 684 */ "S15\000"
482 /* 688 */ "D19_D21_D23_D25\000"
483 /* 704 */ "D23_D24_D25\000"
484 /* 716 */ "S25\000"
485 /* 720 */ "D1_D3_D5\000"
486 /* 729 */ "D3_D4_D5\000"
487 /* 738 */ "Q2_Q3_Q4_Q5\000"
488 /* 750 */ "R4_R5\000"
489 /* 756 */ "S5\000"
490 /* 759 */ "D10_D12_D14_D16\000"
491 /* 775 */ "D13_D14_D15_D16\000"
492 /* 791 */ "S16\000"
493 /* 795 */ "D20_D22_D24_D26\000"
494 /* 811 */ "D23_D24_D25_D26\000"
495 /* 827 */ "S26\000"
496 /* 831 */ "D0_D2_D4_D6\000"
497 /* 843 */ "D3_D4_D5_D6\000"
498 /* 855 */ "Q3_Q4_Q5_Q6\000"
499 /* 867 */ "R6\000"
500 /* 870 */ "S6\000"
501 /* 873 */ "D11_D13_D15_D17\000"
502 /* 889 */ "D15_D16_D17\000"
503 /* 901 */ "S17\000"
504 /* 905 */ "D21_D23_D25_D27\000"
505 /* 921 */ "D25_D26_D27\000"
506 /* 933 */ "S27\000"
507 /* 937 */ "D1_D3_D5_D7\000"
508 /* 949 */ "D5_D6_D7\000"
509 /* 958 */ "Q4_Q5_Q6_Q7\000"
510 /* 970 */ "R6_R7\000"
511 /* 976 */ "S7\000"
512 /* 979 */ "D12_D14_D16_D18\000"
513 /* 995 */ "D15_D16_D17_D18\000"
514 /* 1011 */ "S18\000"
515 /* 1015 */ "D22_D24_D26_D28\000"
516 /* 1031 */ "D25_D26_D27_D28\000"
517 /* 1047 */ "S28\000"
518 /* 1051 */ "D2_D4_D6_D8\000"
519 /* 1063 */ "D5_D6_D7_D8\000"
520 /* 1075 */ "Q5_Q6_Q7_Q8\000"
521 /* 1087 */ "R8\000"
522 /* 1090 */ "S8\000"
523 /* 1093 */ "D13_D15_D17_D19\000"
524 /* 1109 */ "D17_D18_D19\000"
525 /* 1121 */ "S19\000"
526 /* 1125 */ "D23_D25_D27_D29\000"
527 /* 1141 */ "D27_D28_D29\000"
528 /* 1153 */ "S29\000"
529 /* 1157 */ "D3_D5_D7_D9\000"
530 /* 1169 */ "D7_D8_D9\000"
531 /* 1178 */ "Q6_Q7_Q8_Q9\000"
532 /* 1190 */ "R8_R9\000"
533 /* 1196 */ "S9\000"
534 /* 1199 */ "PC\000"
535 /* 1202 */ "FPSCR_NZCVQC\000"
536 /* 1215 */ "FPEXC\000"
537 /* 1221 */ "FPSID\000"
538 /* 1227 */ "RA_AUTH_CODE\000"
539 /* 1240 */ "ITSTATE\000"
540 /* 1248 */ "FPSCR_RM\000"
541 /* 1257 */ "R12_SP\000"
542 /* 1264 */ "FPSCR\000"
543 /* 1270 */ "LR\000"
544 /* 1273 */ "VPR\000"
545 /* 1277 */ "APSR\000"
546 /* 1282 */ "CPSR\000"
547 /* 1287 */ "SPSR\000"
548 /* 1292 */ "ZR\000"
549 /* 1295 */ "FPCXTNS\000"
550 /* 1303 */ "FPCXTS\000"
551 /* 1310 */ "FPINST\000"
552 /* 1317 */ "FPSCR_NZCV\000"
553 /* 1328 */ "APSR_NZCV\000"
554};
555#ifdef __GNUC__
556#pragma GCC diagnostic pop
557#endif
558
559extern const MCRegisterDesc ARMRegDesc[] = { // Descriptors
560 { .Name: 12, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
561 { .Name: 1277, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45056, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
562 { .Name: 1328, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45057, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
563 { .Name: 1282, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45058, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
564 { .Name: 1295, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45059, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
565 { .Name: 1303, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45060, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
566 { .Name: 1215, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45061, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
567 { .Name: 1310, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45062, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
568 { .Name: 1264, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 11976711, .RegUnitLaneMasks: 180, .IsConstant: 0, .IsArtificial: 0 },
569 { .Name: 1317, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 13627400, .RegUnitLaneMasks: 181, .IsConstant: 0, .IsArtificial: 0 },
570 { .Name: 1202, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45067, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
571 { .Name: 1248, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 14536713, .RegUnitLaneMasks: 181, .IsConstant: 0, .IsArtificial: 0 },
572 { .Name: 1221, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45069, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
573 { .Name: 1240, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45070, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
574 { .Name: 1270, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45071, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
575 { .Name: 1199, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45072, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
576 { .Name: 1227, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45073, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
577 { .Name: 1261, .SubRegs: 11, .SuperRegs: 3964, .SubRegIndices: 2, .RegUnits: 45074, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
578 { .Name: 1287, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45075, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
579 { .Name: 1273, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45076, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
580 { .Name: 1292, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45077, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
581 { .Name: 119, .SubRegs: 3120, .SuperRegs: 2485, .SubRegIndices: 14, .RegUnits: 10874902, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
582 { .Name: 251, .SubRegs: 3127, .SuperRegs: 951, .SubRegIndices: 14, .RegUnits: 10874904, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
583 { .Name: 366, .SubRegs: 3134, .SuperRegs: 2434, .SubRegIndices: 14, .RegUnits: 10874906, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
584 { .Name: 482, .SubRegs: 3148, .SuperRegs: 2322, .SubRegIndices: 14, .RegUnits: 10874908, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
585 { .Name: 608, .SubRegs: 3162, .SuperRegs: 2370, .SubRegIndices: 14, .RegUnits: 10874910, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
586 { .Name: 726, .SubRegs: 3176, .SuperRegs: 2201, .SubRegIndices: 14, .RegUnits: 10874912, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
587 { .Name: 840, .SubRegs: 3190, .SuperRegs: 2257, .SubRegIndices: 14, .RegUnits: 10874914, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
588 { .Name: 946, .SubRegs: 3204, .SuperRegs: 2076, .SubRegIndices: 14, .RegUnits: 10874916, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
589 { .Name: 1060, .SubRegs: 3218, .SuperRegs: 2136, .SubRegIndices: 14, .RegUnits: 10874918, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
590 { .Name: 1166, .SubRegs: 3232, .SuperRegs: 1956, .SubRegIndices: 14, .RegUnits: 10874920, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
591 { .Name: 9, .SubRegs: 3246, .SuperRegs: 2016, .SubRegIndices: 14, .RegUnits: 10874922, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
592 { .Name: 144, .SubRegs: 3260, .SuperRegs: 1836, .SubRegIndices: 14, .RegUnits: 10874924, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
593 { .Name: 285, .SubRegs: 3274, .SuperRegs: 1896, .SubRegIndices: 14, .RegUnits: 10874926, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
594 { .Name: 411, .SubRegs: 3288, .SuperRegs: 1716, .SubRegIndices: 14, .RegUnits: 10874928, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
595 { .Name: 526, .SubRegs: 3302, .SuperRegs: 1776, .SubRegIndices: 14, .RegUnits: 10874930, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
596 { .Name: 652, .SubRegs: 3316, .SuperRegs: 1621, .SubRegIndices: 14, .RegUnits: 10874932, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
597 { .Name: 771, .SubRegs: 11, .SuperRegs: 1680, .SubRegIndices: 2, .RegUnits: 45110, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
598 { .Name: 885, .SubRegs: 11, .SuperRegs: 1550, .SubRegIndices: 2, .RegUnits: 45111, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
599 { .Name: 991, .SubRegs: 11, .SuperRegs: 1585, .SubRegIndices: 2, .RegUnits: 45112, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
600 { .Name: 1105, .SubRegs: 11, .SuperRegs: 1480, .SubRegIndices: 2, .RegUnits: 45113, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
601 { .Name: 59, .SubRegs: 11, .SuperRegs: 1515, .SubRegIndices: 2, .RegUnits: 45114, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
602 { .Name: 195, .SubRegs: 11, .SuperRegs: 1410, .SubRegIndices: 2, .RegUnits: 45115, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
603 { .Name: 339, .SubRegs: 11, .SuperRegs: 1445, .SubRegIndices: 2, .RegUnits: 45116, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
604 { .Name: 459, .SubRegs: 11, .SuperRegs: 1340, .SubRegIndices: 2, .RegUnits: 45117, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
605 { .Name: 578, .SubRegs: 11, .SuperRegs: 1375, .SubRegIndices: 2, .RegUnits: 45118, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
606 { .Name: 700, .SubRegs: 11, .SuperRegs: 1269, .SubRegIndices: 2, .RegUnits: 45119, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
607 { .Name: 807, .SubRegs: 11, .SuperRegs: 1309, .SubRegIndices: 2, .RegUnits: 45120, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
608 { .Name: 917, .SubRegs: 11, .SuperRegs: 835, .SubRegIndices: 2, .RegUnits: 45121, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
609 { .Name: 1027, .SubRegs: 11, .SuperRegs: 883, .SubRegIndices: 2, .RegUnits: 45122, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
610 { .Name: 1137, .SubRegs: 11, .SuperRegs: 856, .SubRegIndices: 2, .RegUnits: 45123, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
611 { .Name: 95, .SubRegs: 11, .SuperRegs: 901, .SubRegIndices: 2, .RegUnits: 45124, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
612 { .Name: 227, .SubRegs: 11, .SuperRegs: 1261, .SubRegIndices: 2, .RegUnits: 45125, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
613 { .Name: 393, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45126, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
614 { .Name: 128, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45127, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
615 { .Name: 260, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45128, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
616 { .Name: 384, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45129, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
617 { .Name: 122, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45130, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
618 { .Name: 125, .SubRegs: 3123, .SuperRegs: 3555, .SubRegIndices: 16, .RegUnits: 12689430, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
619 { .Name: 257, .SubRegs: 3144, .SuperRegs: 2867, .SubRegIndices: 16, .RegUnits: 12689434, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
620 { .Name: 381, .SubRegs: 3172, .SuperRegs: 3077, .SubRegIndices: 16, .RegUnits: 12689438, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
621 { .Name: 503, .SubRegs: 3200, .SuperRegs: 3007, .SubRegIndices: 16, .RegUnits: 12689442, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
622 { .Name: 632, .SubRegs: 3228, .SuperRegs: 2997, .SubRegIndices: 16, .RegUnits: 12689446, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
623 { .Name: 747, .SubRegs: 3256, .SuperRegs: 2987, .SubRegIndices: 16, .RegUnits: 12689450, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
624 { .Name: 864, .SubRegs: 3284, .SuperRegs: 2977, .SubRegIndices: 16, .RegUnits: 12689454, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
625 { .Name: 967, .SubRegs: 3312, .SuperRegs: 2967, .SubRegIndices: 16, .RegUnits: 12689458, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
626 { .Name: 1084, .SubRegs: 2893, .SuperRegs: 2957, .SubRegIndices: 0, .RegUnits: 10874934, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
627 { .Name: 1187, .SubRegs: 2896, .SuperRegs: 2947, .SubRegIndices: 0, .RegUnits: 10874936, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
628 { .Name: 35, .SubRegs: 2899, .SuperRegs: 2937, .SubRegIndices: 0, .RegUnits: 10874938, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
629 { .Name: 171, .SubRegs: 2902, .SuperRegs: 2927, .SubRegIndices: 0, .RegUnits: 10874940, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
630 { .Name: 315, .SubRegs: 2905, .SuperRegs: 2917, .SubRegIndices: 0, .RegUnits: 10874942, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
631 { .Name: 439, .SubRegs: 2908, .SuperRegs: 2782, .SubRegIndices: 0, .RegUnits: 10874944, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
632 { .Name: 558, .SubRegs: 2911, .SuperRegs: 927, .SubRegIndices: 0, .RegUnits: 10874946, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
633 { .Name: 680, .SubRegs: 2914, .SuperRegs: 3551, .SubRegIndices: 0, .RegUnits: 10874948, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
634 { .Name: 131, .SubRegs: 11, .SuperRegs: 3811, .SubRegIndices: 2, .RegUnits: 45131, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
635 { .Name: 263, .SubRegs: 11, .SuperRegs: 3809, .SubRegIndices: 2, .RegUnits: 45132, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
636 { .Name: 387, .SubRegs: 11, .SuperRegs: 3809, .SubRegIndices: 2, .RegUnits: 45133, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
637 { .Name: 509, .SubRegs: 11, .SuperRegs: 3807, .SubRegIndices: 2, .RegUnits: 45134, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
638 { .Name: 635, .SubRegs: 11, .SuperRegs: 3807, .SubRegIndices: 2, .RegUnits: 45135, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
639 { .Name: 753, .SubRegs: 11, .SuperRegs: 3805, .SubRegIndices: 2, .RegUnits: 45136, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
640 { .Name: 867, .SubRegs: 11, .SuperRegs: 3805, .SubRegIndices: 2, .RegUnits: 45137, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
641 { .Name: 973, .SubRegs: 11, .SuperRegs: 3803, .SubRegIndices: 2, .RegUnits: 45138, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
642 { .Name: 1087, .SubRegs: 11, .SuperRegs: 3803, .SubRegIndices: 2, .RegUnits: 45139, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
643 { .Name: 1193, .SubRegs: 11, .SuperRegs: 3801, .SubRegIndices: 2, .RegUnits: 45140, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
644 { .Name: 39, .SubRegs: 11, .SuperRegs: 3801, .SubRegIndices: 2, .RegUnits: 45141, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
645 { .Name: 179, .SubRegs: 11, .SuperRegs: 3799, .SubRegIndices: 2, .RegUnits: 45142, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
646 { .Name: 319, .SubRegs: 11, .SuperRegs: 3799, .SubRegIndices: 2, .RegUnits: 45143, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
647 { .Name: 134, .SubRegs: 11, .SuperRegs: 2493, .SubRegIndices: 2, .RegUnits: 45078, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
648 { .Name: 272, .SubRegs: 11, .SuperRegs: 2484, .SubRegIndices: 2, .RegUnits: 45079, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
649 { .Name: 390, .SubRegs: 11, .SuperRegs: 962, .SubRegIndices: 2, .RegUnits: 45080, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
650 { .Name: 512, .SubRegs: 11, .SuperRegs: 950, .SubRegIndices: 2, .RegUnits: 45081, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
651 { .Name: 638, .SubRegs: 11, .SuperRegs: 2451, .SubRegIndices: 2, .RegUnits: 45082, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
652 { .Name: 756, .SubRegs: 11, .SuperRegs: 2433, .SubRegIndices: 2, .RegUnits: 45083, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
653 { .Name: 870, .SubRegs: 11, .SuperRegs: 2340, .SubRegIndices: 2, .RegUnits: 45084, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
654 { .Name: 976, .SubRegs: 11, .SuperRegs: 2321, .SubRegIndices: 2, .RegUnits: 45085, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
655 { .Name: 1090, .SubRegs: 11, .SuperRegs: 2391, .SubRegIndices: 2, .RegUnits: 45086, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
656 { .Name: 1196, .SubRegs: 11, .SuperRegs: 2369, .SubRegIndices: 2, .RegUnits: 45087, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
657 { .Name: 43, .SubRegs: 11, .SuperRegs: 2222, .SubRegIndices: 2, .RegUnits: 45088, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
658 { .Name: 183, .SubRegs: 11, .SuperRegs: 2200, .SubRegIndices: 2, .RegUnits: 45089, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
659 { .Name: 323, .SubRegs: 11, .SuperRegs: 2280, .SubRegIndices: 2, .RegUnits: 45090, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
660 { .Name: 443, .SubRegs: 11, .SuperRegs: 2256, .SubRegIndices: 2, .RegUnits: 45091, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
661 { .Name: 562, .SubRegs: 11, .SuperRegs: 2099, .SubRegIndices: 2, .RegUnits: 45092, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
662 { .Name: 684, .SubRegs: 11, .SuperRegs: 2075, .SubRegIndices: 2, .RegUnits: 45093, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
663 { .Name: 791, .SubRegs: 11, .SuperRegs: 2159, .SubRegIndices: 2, .RegUnits: 45094, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
664 { .Name: 901, .SubRegs: 11, .SuperRegs: 2135, .SubRegIndices: 2, .RegUnits: 45095, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
665 { .Name: 1011, .SubRegs: 11, .SuperRegs: 1979, .SubRegIndices: 2, .RegUnits: 45096, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
666 { .Name: 1121, .SubRegs: 11, .SuperRegs: 1955, .SubRegIndices: 2, .RegUnits: 45097, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
667 { .Name: 79, .SubRegs: 11, .SuperRegs: 2039, .SubRegIndices: 2, .RegUnits: 45098, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
668 { .Name: 215, .SubRegs: 11, .SuperRegs: 2015, .SubRegIndices: 2, .RegUnits: 45099, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
669 { .Name: 359, .SubRegs: 11, .SuperRegs: 1859, .SubRegIndices: 2, .RegUnits: 45100, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
670 { .Name: 475, .SubRegs: 11, .SuperRegs: 1835, .SubRegIndices: 2, .RegUnits: 45101, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
671 { .Name: 598, .SubRegs: 11, .SuperRegs: 1919, .SubRegIndices: 2, .RegUnits: 45102, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
672 { .Name: 716, .SubRegs: 11, .SuperRegs: 1895, .SubRegIndices: 2, .RegUnits: 45103, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
673 { .Name: 827, .SubRegs: 11, .SuperRegs: 1739, .SubRegIndices: 2, .RegUnits: 45104, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
674 { .Name: 933, .SubRegs: 11, .SuperRegs: 1715, .SubRegIndices: 2, .RegUnits: 45105, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
675 { .Name: 1047, .SubRegs: 11, .SuperRegs: 1799, .SubRegIndices: 2, .RegUnits: 45106, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
676 { .Name: 1153, .SubRegs: 11, .SuperRegs: 1775, .SubRegIndices: 2, .RegUnits: 45107, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
677 { .Name: 115, .SubRegs: 11, .SuperRegs: 1644, .SubRegIndices: 2, .RegUnits: 45108, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
678 { .Name: 247, .SubRegs: 11, .SuperRegs: 1620, .SubRegIndices: 2, .RegUnits: 45109, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
679 { .Name: 363, .SubRegs: 3137, .SuperRegs: 2487, .SubRegIndices: 22, .RegUnits: 12738582, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
680 { .Name: 479, .SubRegs: 3151, .SuperRegs: 974, .SubRegIndices: 22, .RegUnits: 12738584, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
681 { .Name: 605, .SubRegs: 3165, .SuperRegs: 2469, .SubRegIndices: 22, .RegUnits: 12738586, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
682 { .Name: 723, .SubRegs: 3179, .SuperRegs: 2359, .SubRegIndices: 22, .RegUnits: 12738588, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
683 { .Name: 837, .SubRegs: 3193, .SuperRegs: 2413, .SubRegIndices: 22, .RegUnits: 12738590, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
684 { .Name: 943, .SubRegs: 3207, .SuperRegs: 2244, .SubRegIndices: 22, .RegUnits: 12738592, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
685 { .Name: 1057, .SubRegs: 3221, .SuperRegs: 2304, .SubRegIndices: 22, .RegUnits: 12738594, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
686 { .Name: 1163, .SubRegs: 3235, .SuperRegs: 2123, .SubRegIndices: 22, .RegUnits: 12738596, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
687 { .Name: 6, .SubRegs: 3249, .SuperRegs: 2183, .SubRegIndices: 22, .RegUnits: 12738598, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
688 { .Name: 154, .SubRegs: 3263, .SuperRegs: 2003, .SubRegIndices: 22, .RegUnits: 12738600, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
689 { .Name: 281, .SubRegs: 3277, .SuperRegs: 2063, .SubRegIndices: 22, .RegUnits: 12738602, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
690 { .Name: 407, .SubRegs: 3291, .SuperRegs: 1883, .SubRegIndices: 22, .RegUnits: 12738604, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
691 { .Name: 522, .SubRegs: 3305, .SuperRegs: 1943, .SubRegIndices: 22, .RegUnits: 12738606, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
692 { .Name: 648, .SubRegs: 3319, .SuperRegs: 1763, .SubRegIndices: 22, .RegUnits: 12738608, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
693 { .Name: 767, .SubRegs: 2425, .SuperRegs: 1823, .SubRegIndices: 8, .RegUnits: 14532658, .RegUnitLaneMasks: 25, .IsConstant: 0, .IsArtificial: 0 },
694 { .Name: 881, .SubRegs: 2316, .SuperRegs: 1668, .SubRegIndices: 8, .RegUnits: 13652020, .RegUnitLaneMasks: 25, .IsConstant: 0, .IsArtificial: 0 },
695 { .Name: 987, .SubRegs: 3326, .SuperRegs: 1703, .SubRegIndices: 6, .RegUnits: 13627446, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
696 { .Name: 1101, .SubRegs: 3326, .SuperRegs: 1573, .SubRegIndices: 6, .RegUnits: 13627447, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
697 { .Name: 55, .SubRegs: 3326, .SuperRegs: 1608, .SubRegIndices: 6, .RegUnits: 13627448, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
698 { .Name: 207, .SubRegs: 3326, .SuperRegs: 1503, .SubRegIndices: 6, .RegUnits: 13627449, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
699 { .Name: 335, .SubRegs: 3326, .SuperRegs: 1538, .SubRegIndices: 6, .RegUnits: 13627450, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
700 { .Name: 455, .SubRegs: 3326, .SuperRegs: 1433, .SubRegIndices: 6, .RegUnits: 13627451, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
701 { .Name: 574, .SubRegs: 3326, .SuperRegs: 1468, .SubRegIndices: 6, .RegUnits: 13627452, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
702 { .Name: 696, .SubRegs: 3326, .SuperRegs: 1363, .SubRegIndices: 6, .RegUnits: 13627453, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
703 { .Name: 803, .SubRegs: 3326, .SuperRegs: 1398, .SubRegIndices: 6, .RegUnits: 13627454, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
704 { .Name: 913, .SubRegs: 3326, .SuperRegs: 1292, .SubRegIndices: 6, .RegUnits: 13627455, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
705 { .Name: 1023, .SubRegs: 3326, .SuperRegs: 1330, .SubRegIndices: 6, .RegUnits: 13627456, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
706 { .Name: 1133, .SubRegs: 3326, .SuperRegs: 873, .SubRegIndices: 6, .RegUnits: 13627457, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
707 { .Name: 91, .SubRegs: 3326, .SuperRegs: 912, .SubRegIndices: 6, .RegUnits: 13627458, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
708 { .Name: 239, .SubRegs: 3326, .SuperRegs: 1263, .SubRegIndices: 6, .RegUnits: 13627459, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
709 { .Name: 254, .SubRegs: 3779, .SuperRegs: 3557, .SubRegIndices: 150, .RegUnits: 12673046, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
710 { .Name: 378, .SubRegs: 3759, .SuperRegs: 3117, .SubRegIndices: 150, .RegUnits: 12673050, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
711 { .Name: 500, .SubRegs: 3739, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673054, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
712 { .Name: 629, .SubRegs: 3719, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673058, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
713 { .Name: 744, .SubRegs: 3699, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673062, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
714 { .Name: 861, .SubRegs: 3679, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673066, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
715 { .Name: 964, .SubRegs: 3659, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673070, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
716 { .Name: 1081, .SubRegs: 3643, .SuperRegs: 3102, .SubRegIndices: 75, .RegUnits: 12681266, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
717 { .Name: 1184, .SubRegs: 3631, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689462, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
718 { .Name: 32, .SubRegs: 3619, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689464, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
719 { .Name: 167, .SubRegs: 3607, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689466, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
720 { .Name: 311, .SubRegs: 3595, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689468, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
721 { .Name: 435, .SubRegs: 3583, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689470, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
722 { .Name: 554, .SubRegs: 3571, .SuperRegs: 3114, .SubRegIndices: 64, .RegUnits: 12689472, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
723 { .Name: 676, .SubRegs: 3559, .SuperRegs: 3553, .SubRegIndices: 64, .RegUnits: 12689474, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
724 { .Name: 494, .SubRegs: 628, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640278, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
725 { .Name: 623, .SubRegs: 573, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640282, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
726 { .Name: 738, .SubRegs: 518, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640286, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
727 { .Name: 855, .SubRegs: 463, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640290, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
728 { .Name: 958, .SubRegs: 408, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640294, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
729 { .Name: 1075, .SubRegs: 357, .SuperRegs: 11, .SubRegIndices: 392, .RegUnits: 12648490, .RegUnitLaneMasks: 136, .IsConstant: 0, .IsArtificial: 0 },
730 { .Name: 1178, .SubRegs: 310, .SuperRegs: 11, .SubRegIndices: 346, .RegUnits: 12656686, .RegUnitLaneMasks: 150, .IsConstant: 0, .IsArtificial: 0 },
731 { .Name: 26, .SubRegs: 267, .SuperRegs: 11, .SubRegIndices: 304, .RegUnits: 12664882, .RegUnitLaneMasks: 162, .IsConstant: 0, .IsArtificial: 0 },
732 { .Name: 161, .SubRegs: 228, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673078, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
733 { .Name: 304, .SubRegs: 189, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673080, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
734 { .Name: 427, .SubRegs: 150, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673082, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
735 { .Name: 546, .SubRegs: 111, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673084, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
736 { .Name: 668, .SubRegs: 72, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673086, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
737 { .Name: 266, .SubRegs: 2875, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874955, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
738 { .Name: 506, .SubRegs: 2878, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874957, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
739 { .Name: 750, .SubRegs: 2881, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874959, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
740 { .Name: 970, .SubRegs: 2884, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874961, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
741 { .Name: 1190, .SubRegs: 2887, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874963, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
742 { .Name: 175, .SubRegs: 2890, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874965, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
743 { .Name: 1257, .SubRegs: 2551, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 14618642, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
744 { .Name: 369, .SubRegs: 3951, .SuperRegs: 3556, .SubRegIndices: 52, .RegUnits: 12681238, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
745 { .Name: 485, .SubRegs: 2641, .SuperRegs: 983, .SubRegIndices: 52, .RegUnits: 12681240, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
746 { .Name: 614, .SubRegs: 3938, .SuperRegs: 2870, .SubRegIndices: 52, .RegUnits: 12681242, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
747 { .Name: 729, .SubRegs: 2628, .SuperRegs: 2862, .SubRegIndices: 52, .RegUnits: 12681244, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
748 { .Name: 846, .SubRegs: 3925, .SuperRegs: 3080, .SubRegIndices: 52, .RegUnits: 12681246, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
749 { .Name: 949, .SubRegs: 2615, .SuperRegs: 2851, .SubRegIndices: 52, .RegUnits: 12681248, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
750 { .Name: 1066, .SubRegs: 3912, .SuperRegs: 3071, .SubRegIndices: 52, .RegUnits: 12681250, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
751 { .Name: 1169, .SubRegs: 2602, .SuperRegs: 2845, .SubRegIndices: 52, .RegUnits: 12681252, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
752 { .Name: 16, .SubRegs: 3899, .SuperRegs: 3065, .SubRegIndices: 52, .RegUnits: 12681254, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
753 { .Name: 137, .SubRegs: 2589, .SuperRegs: 2839, .SubRegIndices: 52, .RegUnits: 12681256, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
754 { .Name: 292, .SubRegs: 3886, .SuperRegs: 3059, .SubRegIndices: 52, .RegUnits: 12681258, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
755 { .Name: 415, .SubRegs: 2576, .SuperRegs: 2833, .SubRegIndices: 52, .RegUnits: 12681260, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
756 { .Name: 534, .SubRegs: 3873, .SuperRegs: 3053, .SubRegIndices: 52, .RegUnits: 12681262, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
757 { .Name: 656, .SubRegs: 2563, .SuperRegs: 2827, .SubRegIndices: 52, .RegUnits: 12681264, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
758 { .Name: 779, .SubRegs: 3862, .SuperRegs: 3047, .SubRegIndices: 42, .RegUnits: 12685362, .RegUnitLaneMasks: 30, .IsConstant: 0, .IsArtificial: 0 },
759 { .Name: 889, .SubRegs: 2554, .SuperRegs: 2821, .SubRegIndices: 34, .RegUnits: 12689460, .RegUnitLaneMasks: 35, .IsConstant: 0, .IsArtificial: 0 },
760 { .Name: 999, .SubRegs: 3855, .SuperRegs: 3041, .SubRegIndices: 28, .RegUnits: 11976758, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
761 { .Name: 1109, .SubRegs: 2544, .SuperRegs: 2815, .SubRegIndices: 28, .RegUnits: 11976759, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
762 { .Name: 67, .SubRegs: 3848, .SuperRegs: 3035, .SubRegIndices: 28, .RegUnits: 11976760, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
763 { .Name: 187, .SubRegs: 2537, .SuperRegs: 2809, .SubRegIndices: 28, .RegUnits: 11976761, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
764 { .Name: 347, .SubRegs: 3841, .SuperRegs: 3029, .SubRegIndices: 28, .RegUnits: 11976762, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
765 { .Name: 463, .SubRegs: 2530, .SuperRegs: 2803, .SubRegIndices: 28, .RegUnits: 11976763, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
766 { .Name: 586, .SubRegs: 3834, .SuperRegs: 3023, .SubRegIndices: 28, .RegUnits: 11976764, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
767 { .Name: 704, .SubRegs: 2523, .SuperRegs: 2797, .SubRegIndices: 28, .RegUnits: 11976765, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
768 { .Name: 815, .SubRegs: 3827, .SuperRegs: 3017, .SubRegIndices: 28, .RegUnits: 11976766, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
769 { .Name: 921, .SubRegs: 2516, .SuperRegs: 2791, .SubRegIndices: 28, .RegUnits: 11976767, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
770 { .Name: 1035, .SubRegs: 3820, .SuperRegs: 2857, .SubRegIndices: 28, .RegUnits: 11976768, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
771 { .Name: 1141, .SubRegs: 2509, .SuperRegs: 935, .SubRegIndices: 28, .RegUnits: 11976769, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
772 { .Name: 103, .SubRegs: 3813, .SuperRegs: 946, .SubRegIndices: 28, .RegUnits: 11976770, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
773 { .Name: 219, .SubRegs: 2502, .SuperRegs: 3552, .SubRegIndices: 28, .RegUnits: 11976771, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
774 { .Name: 602, .SubRegs: 3490, .SuperRegs: 2490, .SubRegIndices: 190, .RegUnits: 12730390, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
775 { .Name: 720, .SubRegs: 3478, .SuperRegs: 2430, .SubRegIndices: 190, .RegUnits: 12730392, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
776 { .Name: 834, .SubRegs: 3466, .SuperRegs: 2479, .SubRegIndices: 190, .RegUnits: 12730394, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
777 { .Name: 940, .SubRegs: 3454, .SuperRegs: 2386, .SubRegIndices: 190, .RegUnits: 12730396, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
778 { .Name: 1054, .SubRegs: 3442, .SuperRegs: 2386, .SubRegIndices: 190, .RegUnits: 12730398, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
779 { .Name: 1160, .SubRegs: 3430, .SuperRegs: 2275, .SubRegIndices: 190, .RegUnits: 12730400, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
780 { .Name: 3, .SubRegs: 3418, .SuperRegs: 2275, .SubRegIndices: 190, .RegUnits: 12730402, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
781 { .Name: 151, .SubRegs: 3406, .SuperRegs: 2154, .SubRegIndices: 190, .RegUnits: 12730404, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
782 { .Name: 278, .SubRegs: 3394, .SuperRegs: 2154, .SubRegIndices: 190, .RegUnits: 12730406, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
783 { .Name: 404, .SubRegs: 3382, .SuperRegs: 2034, .SubRegIndices: 190, .RegUnits: 12730408, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
784 { .Name: 518, .SubRegs: 3370, .SuperRegs: 2034, .SubRegIndices: 190, .RegUnits: 12730410, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
785 { .Name: 644, .SubRegs: 3358, .SuperRegs: 1914, .SubRegIndices: 190, .RegUnits: 12730412, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
786 { .Name: 763, .SubRegs: 3512, .SuperRegs: 1914, .SubRegIndices: 181, .RegUnits: 14524462, .RegUnitLaneMasks: 78, .IsConstant: 0, .IsArtificial: 0 },
787 { .Name: 877, .SubRegs: 3502, .SuperRegs: 1794, .SubRegIndices: 181, .RegUnits: 13643824, .RegUnitLaneMasks: 78, .IsConstant: 0, .IsArtificial: 0 },
788 { .Name: 983, .SubRegs: 3530, .SuperRegs: 1794, .SubRegIndices: 174, .RegUnits: 13738034, .RegUnitLaneMasks: 83, .IsConstant: 0, .IsArtificial: 0 },
789 { .Name: 1097, .SubRegs: 3522, .SuperRegs: 1698, .SubRegIndices: 174, .RegUnits: 13672500, .RegUnitLaneMasks: 83, .IsConstant: 0, .IsArtificial: 0 },
790 { .Name: 51, .SubRegs: 3538, .SuperRegs: 1698, .SubRegIndices: 169, .RegUnits: 13676598, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
791 { .Name: 203, .SubRegs: 3538, .SuperRegs: 1603, .SubRegIndices: 169, .RegUnits: 13676599, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
792 { .Name: 331, .SubRegs: 3538, .SuperRegs: 1603, .SubRegIndices: 169, .RegUnits: 13676600, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
793 { .Name: 451, .SubRegs: 3538, .SuperRegs: 1533, .SubRegIndices: 169, .RegUnits: 13676601, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
794 { .Name: 570, .SubRegs: 3538, .SuperRegs: 1533, .SubRegIndices: 169, .RegUnits: 13676602, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
795 { .Name: 692, .SubRegs: 3538, .SuperRegs: 1463, .SubRegIndices: 169, .RegUnits: 13676603, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
796 { .Name: 799, .SubRegs: 3538, .SuperRegs: 1463, .SubRegIndices: 169, .RegUnits: 13676604, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
797 { .Name: 909, .SubRegs: 3538, .SuperRegs: 1393, .SubRegIndices: 169, .RegUnits: 13676605, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
798 { .Name: 1019, .SubRegs: 3538, .SuperRegs: 1393, .SubRegIndices: 169, .RegUnits: 13676606, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
799 { .Name: 1129, .SubRegs: 3538, .SuperRegs: 1304, .SubRegIndices: 169, .RegUnits: 13676607, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
800 { .Name: 87, .SubRegs: 3538, .SuperRegs: 1327, .SubRegIndices: 169, .RegUnits: 13676608, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
801 { .Name: 235, .SubRegs: 3538, .SuperRegs: 1266, .SubRegIndices: 169, .RegUnits: 13676609, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
802 { .Name: 831, .SubRegs: 1149, .SuperRegs: 2491, .SubRegIndices: 249, .RegUnits: 12722198, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
803 { .Name: 937, .SubRegs: 1131, .SuperRegs: 2428, .SubRegIndices: 249, .RegUnits: 12722200, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
804 { .Name: 1051, .SubRegs: 1113, .SuperRegs: 2428, .SubRegIndices: 249, .RegUnits: 12722202, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
805 { .Name: 1157, .SubRegs: 1095, .SuperRegs: 2319, .SubRegIndices: 249, .RegUnits: 12722204, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
806 { .Name: 0, .SubRegs: 1077, .SuperRegs: 2319, .SubRegIndices: 249, .RegUnits: 12722206, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
807 { .Name: 148, .SubRegs: 1059, .SuperRegs: 2198, .SubRegIndices: 249, .RegUnits: 12722208, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
808 { .Name: 275, .SubRegs: 1041, .SuperRegs: 2198, .SubRegIndices: 249, .RegUnits: 12722210, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
809 { .Name: 401, .SubRegs: 1023, .SuperRegs: 2097, .SubRegIndices: 249, .RegUnits: 12722212, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
810 { .Name: 515, .SubRegs: 1005, .SuperRegs: 2097, .SubRegIndices: 249, .RegUnits: 12722214, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
811 { .Name: 641, .SubRegs: 987, .SuperRegs: 1977, .SubRegIndices: 249, .RegUnits: 12722216, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
812 { .Name: 759, .SubRegs: 1183, .SuperRegs: 1977, .SubRegIndices: 234, .RegUnits: 14516266, .RegUnitLaneMasks: 98, .IsConstant: 0, .IsArtificial: 0 },
813 { .Name: 873, .SubRegs: 1167, .SuperRegs: 1857, .SubRegIndices: 234, .RegUnits: 13635628, .RegUnitLaneMasks: 98, .IsConstant: 0, .IsArtificial: 0 },
814 { .Name: 979, .SubRegs: 1213, .SuperRegs: 1857, .SubRegIndices: 221, .RegUnits: 13729838, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
815 { .Name: 1093, .SubRegs: 1199, .SuperRegs: 1737, .SubRegIndices: 221, .RegUnits: 13664304, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
816 { .Name: 47, .SubRegs: 1239, .SuperRegs: 1737, .SubRegIndices: 210, .RegUnits: 13709362, .RegUnitLaneMasks: 111, .IsConstant: 0, .IsArtificial: 0 },
817 { .Name: 199, .SubRegs: 1227, .SuperRegs: 1642, .SubRegIndices: 210, .RegUnits: 13688884, .RegUnitLaneMasks: 111, .IsConstant: 0, .IsArtificial: 0 },
818 { .Name: 327, .SubRegs: 1251, .SuperRegs: 1642, .SubRegIndices: 201, .RegUnits: 13692982, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
819 { .Name: 447, .SubRegs: 1251, .SuperRegs: 1571, .SubRegIndices: 201, .RegUnits: 13692983, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
820 { .Name: 566, .SubRegs: 1251, .SuperRegs: 1571, .SubRegIndices: 201, .RegUnits: 13692984, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
821 { .Name: 688, .SubRegs: 1251, .SuperRegs: 1501, .SubRegIndices: 201, .RegUnits: 13692985, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
822 { .Name: 795, .SubRegs: 1251, .SuperRegs: 1501, .SubRegIndices: 201, .RegUnits: 13692986, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
823 { .Name: 905, .SubRegs: 1251, .SuperRegs: 1431, .SubRegIndices: 201, .RegUnits: 13692987, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
824 { .Name: 1015, .SubRegs: 1251, .SuperRegs: 1431, .SubRegIndices: 201, .RegUnits: 13692988, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
825 { .Name: 1125, .SubRegs: 1251, .SuperRegs: 1328, .SubRegIndices: 201, .RegUnits: 13692989, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
826 { .Name: 83, .SubRegs: 1251, .SuperRegs: 1328, .SubRegIndices: 201, .RegUnits: 13692990, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
827 { .Name: 231, .SubRegs: 1251, .SuperRegs: 1267, .SubRegIndices: 201, .RegUnits: 13692991, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
828 { .Name: 372, .SubRegs: 3130, .SuperRegs: 981, .SubRegIndices: 16, .RegUnits: 12689432, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
829 { .Name: 617, .SubRegs: 3158, .SuperRegs: 2675, .SubRegIndices: 16, .RegUnits: 12689436, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
830 { .Name: 849, .SubRegs: 3186, .SuperRegs: 2773, .SubRegIndices: 16, .RegUnits: 12689440, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
831 { .Name: 1069, .SubRegs: 3214, .SuperRegs: 2764, .SubRegIndices: 16, .RegUnits: 12689444, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
832 { .Name: 19, .SubRegs: 3242, .SuperRegs: 2755, .SubRegIndices: 16, .RegUnits: 12689448, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
833 { .Name: 296, .SubRegs: 3270, .SuperRegs: 2746, .SubRegIndices: 16, .RegUnits: 12689452, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
834 { .Name: 538, .SubRegs: 3298, .SuperRegs: 2737, .SubRegIndices: 16, .RegUnits: 12689456, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
835 { .Name: 783, .SubRegs: 2195, .SuperRegs: 2728, .SubRegIndices: 2, .RegUnits: 11976756, .RegUnitLaneMasks: 10, .IsConstant: 0, .IsArtificial: 0 },
836 { .Name: 1003, .SubRegs: 2654, .SuperRegs: 2719, .SubRegIndices: 0, .RegUnits: 10874935, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
837 { .Name: 71, .SubRegs: 2657, .SuperRegs: 2710, .SubRegIndices: 0, .RegUnits: 10874937, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
838 { .Name: 351, .SubRegs: 2660, .SuperRegs: 2701, .SubRegIndices: 0, .RegUnits: 10874939, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
839 { .Name: 590, .SubRegs: 2663, .SuperRegs: 2692, .SubRegIndices: 0, .RegUnits: 10874941, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
840 { .Name: 819, .SubRegs: 2666, .SuperRegs: 2683, .SubRegIndices: 0, .RegUnits: 10874943, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
841 { .Name: 1039, .SubRegs: 2669, .SuperRegs: 919, .SubRegIndices: 0, .RegUnits: 10874945, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
842 { .Name: 107, .SubRegs: 2672, .SuperRegs: 940, .SubRegIndices: 0, .RegUnits: 10874947, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
843 { .Name: 611, .SubRegs: 815, .SuperRegs: 960, .SubRegIndices: 131, .RegUnits: 12673048, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
844 { .Name: 843, .SubRegs: 795, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673052, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
845 { .Name: 1063, .SubRegs: 775, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673056, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
846 { .Name: 13, .SubRegs: 755, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673060, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
847 { .Name: 289, .SubRegs: 735, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673064, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
848 { .Name: 530, .SubRegs: 715, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673068, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
849 { .Name: 775, .SubRegs: 697, .SuperRegs: 2680, .SubRegIndices: 114, .RegUnits: 12677168, .RegUnitLaneMasks: 50, .IsConstant: 0, .IsArtificial: 0 },
850 { .Name: 995, .SubRegs: 683, .SuperRegs: 2680, .SubRegIndices: 101, .RegUnits: 12685364, .RegUnitLaneMasks: 63, .IsConstant: 0, .IsArtificial: 0 },
851 { .Name: 63, .SubRegs: 60, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689463, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
852 { .Name: 343, .SubRegs: 48, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689465, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
853 { .Name: 582, .SubRegs: 36, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689467, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
854 { .Name: 811, .SubRegs: 24, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689469, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
855 { .Name: 1031, .SubRegs: 12, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689471, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
856 { .Name: 99, .SubRegs: 0, .SuperRegs: 854, .SubRegIndices: 90, .RegUnits: 12689473, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
857};
858
859extern const MCPhysReg ARMRegUnitRoots[][2] = {
860 { ARM::APSR },
861 { ARM::APSR_NZCV },
862 { ARM::CPSR },
863 { ARM::FPCXTNS },
864 { ARM::FPCXTS },
865 { ARM::FPEXC },
866 { ARM::FPINST },
867 { ARM::FPSCR },
868 { ARM::FPSCR, ARM::FPSCR_NZCV },
869 { ARM::FPSCR, ARM::FPSCR_RM },
870 { ARM::FPSCR_NZCV },
871 { ARM::FPSCR_NZCVQC },
872 { ARM::FPSCR_RM },
873 { ARM::FPSID },
874 { ARM::ITSTATE },
875 { ARM::LR },
876 { ARM::PC },
877 { ARM::RA_AUTH_CODE },
878 { ARM::SP },
879 { ARM::SPSR },
880 { ARM::VPR },
881 { ARM::ZR },
882 { ARM::S0 },
883 { ARM::S1 },
884 { ARM::S2 },
885 { ARM::S3 },
886 { ARM::S4 },
887 { ARM::S5 },
888 { ARM::S6 },
889 { ARM::S7 },
890 { ARM::S8 },
891 { ARM::S9 },
892 { ARM::S10 },
893 { ARM::S11 },
894 { ARM::S12 },
895 { ARM::S13 },
896 { ARM::S14 },
897 { ARM::S15 },
898 { ARM::S16 },
899 { ARM::S17 },
900 { ARM::S18 },
901 { ARM::S19 },
902 { ARM::S20 },
903 { ARM::S21 },
904 { ARM::S22 },
905 { ARM::S23 },
906 { ARM::S24 },
907 { ARM::S25 },
908 { ARM::S26 },
909 { ARM::S27 },
910 { ARM::S28 },
911 { ARM::S29 },
912 { ARM::S30 },
913 { ARM::S31 },
914 { ARM::D16 },
915 { ARM::D17 },
916 { ARM::D18 },
917 { ARM::D19 },
918 { ARM::D20 },
919 { ARM::D21 },
920 { ARM::D22 },
921 { ARM::D23 },
922 { ARM::D24 },
923 { ARM::D25 },
924 { ARM::D26 },
925 { ARM::D27 },
926 { ARM::D28 },
927 { ARM::D29 },
928 { ARM::D30 },
929 { ARM::D31 },
930 { ARM::FPINST2 },
931 { ARM::MVFR0 },
932 { ARM::MVFR1 },
933 { ARM::MVFR2 },
934 { ARM::P0 },
935 { ARM::R0 },
936 { ARM::R1 },
937 { ARM::R2 },
938 { ARM::R3 },
939 { ARM::R4 },
940 { ARM::R5 },
941 { ARM::R6 },
942 { ARM::R7 },
943 { ARM::R8 },
944 { ARM::R9 },
945 { ARM::R10 },
946 { ARM::R11 },
947 { ARM::R12 },
948};
949
950// Register classes...
951
952#ifdef __GNUC__
953#pragma GCC diagnostic push
954#pragma GCC diagnostic ignored "-Woverlength-strings"
955#endif
956extern const char ARMRegClassStrings[] = {
957 /* 0 */ "QQQQPR_with_ssub_0\000"
958 /* 19 */ "FPWithVPR_with_ssub_0\000"
959 /* 41 */ "DQuadSpc_with_ssub_0\000"
960 /* 62 */ "DTripleSpc_with_ssub_0\000"
961 /* 85 */ "DPairSpc_with_ssub_0\000"
962 /* 106 */ "DQuad_with_ssub_0\000"
963 /* 124 */ "DTriple_with_ssub_0\000"
964 /* 144 */ "DPair_with_ssub_0\000"
965 /* 162 */ "tGPREven_and_tcGPRnotr12\000"
966 /* 187 */ "GPRPair_with_gsub_0_in_tcGPRnotr12\000"
967 /* 222 */ "DPR_VFP2\000"
968 /* 231 */ "QPR_VFP2\000"
969 /* 240 */ "DQuad_with_ssub_2\000"
970 /* 258 */ "DTriple_with_ssub_2\000"
971 /* 278 */ "DPair_with_ssub_2\000"
972 /* 296 */ "QQQQPR_with_ssub_4\000"
973 /* 315 */ "DQuadSpc_with_ssub_4\000"
974 /* 336 */ "DTripleSpc_with_ssub_4\000"
975 /* 359 */ "DPairSpc_with_ssub_4\000"
976 /* 380 */ "DQuad_with_ssub_4\000"
977 /* 398 */ "DTriple_with_ssub_4\000"
978 /* 418 */ "DQuad_with_ssub_6\000"
979 /* 436 */ "DQuadSpc_with_dsub_0_in_DPR_8\000"
980 /* 466 */ "DTripleSpc_with_dsub_0_in_DPR_8\000"
981 /* 498 */ "DPairSpc_with_dsub_0_in_DPR_8\000"
982 /* 528 */ "DQuad_with_dsub_0_in_DPR_8\000"
983 /* 555 */ "DTriple_with_dsub_0_in_DPR_8\000"
984 /* 584 */ "DPair_with_dsub_0_in_DPR_8\000"
985 /* 611 */ "DQuad_with_dsub_1_in_DPR_8\000"
986 /* 638 */ "DTriple_with_dsub_1_in_DPR_8\000"
987 /* 667 */ "DPair_with_dsub_1_in_DPR_8\000"
988 /* 694 */ "MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8\000"
989 /* 745 */ "MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8\000"
990 /* 796 */ "DQuadSpc_with_dsub_2_in_DPR_8\000"
991 /* 826 */ "DTripleSpc_with_dsub_2_in_DPR_8\000"
992 /* 858 */ "DPairSpc_with_dsub_2_in_DPR_8\000"
993 /* 888 */ "DQuad_with_dsub_2_in_DPR_8\000"
994 /* 915 */ "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8\000"
995 /* 1032 */ "DQuad_with_dsub_3_in_DPR_8\000"
996 /* 1059 */ "DQuadSpc_with_dsub_4_in_DPR_8\000"
997 /* 1089 */ "DTripleSpc_with_dsub_4_in_DPR_8\000"
998 /* 1121 */ "MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8\000"
999 /* 1172 */ "DTriple_with_qsub_0_in_QPR_8\000"
1000 /* 1201 */ "MQQQQPR_with_qsub_2_in_QPR_8\000"
1001 /* 1230 */ "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8\000"
1002 /* 1278 */ "DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8\000"
1003 /* 1328 */ "FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8\000"
1004 /* 1371 */ "QQQQPR_with_ssub_8\000"
1005 /* 1390 */ "DQuadSpc_with_ssub_8\000"
1006 /* 1411 */ "DTripleSpc_with_ssub_8\000"
1007 /* 1434 */ "VCCR\000"
1008 /* 1439 */ "DPR\000"
1009 /* 1443 */ "hGPR_and_tcGPR\000"
1010 /* 1458 */ "tGPROdd_and_tcGPR\000"
1011 /* 1476 */ "tGPREven_and_tcGPR\000"
1012 /* 1495 */ "GPRPair_with_gsub_0_in_tcGPR\000"
1013 /* 1524 */ "GPRnosp_and_GPRnopc_and_hGPR\000"
1014 /* 1553 */ "GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR\000"
1015 /* 1594 */ "GPRnosp_and_GPRnoip_and_hGPR\000"
1016 /* 1623 */ "GPRnosp_and_hGPR\000"
1017 /* 1640 */ "GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR\000"
1018 /* 1684 */ "rGPR\000"
1019 /* 1689 */ "GPRPair_with_gsub_0_in_tGPR\000"
1020 /* 1717 */ "HPR\000"
1021 /* 1721 */ "DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR\000"
1022 /* 1773 */ "DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR\000"
1023 /* 1842 */ "DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR\000"
1024 /* 1980 */ "MQQPR\000"
1025 /* 1986 */ "MQQQQPR\000"
1026 /* 1994 */ "DTriple_with_qsub_0_in_QPR\000"
1027 /* 2021 */ "DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR\000"
1028 /* 2089 */ "DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR\000"
1029 /* 2161 */ "SPR\000"
1030 /* 2165 */ "FPWithVPR\000"
1031 /* 2175 */ "GPRwithAPSR\000"
1032 /* 2187 */ "GPRwithZR\000"
1033 /* 2197 */ "FP_STATUS_REGS\000"
1034 /* 2212 */ "cl_FPSCR_NZCV\000"
1035 /* 2226 */ "DQuadSpc\000"
1036 /* 2235 */ "DTripleSpc\000"
1037 /* 2246 */ "DPairSpc\000"
1038 /* 2255 */ "hGPR_and_tGPRwithpc\000"
1039 /* 2275 */ "GPRnoip_and_GPRnopc\000"
1040 /* 2295 */ "DQuad\000"
1041 /* 2301 */ "hGPR_and_tGPROdd\000"
1042 /* 2318 */ "tGPR_and_tGPROdd\000"
1043 /* 2335 */ "DTriple\000"
1044 /* 2343 */ "hGPR_and_tGPREven\000"
1045 /* 2361 */ "tGPR_and_tGPREven\000"
1046 /* 2379 */ "hGPR_and_GPRnoip_and_tGPREven\000"
1047 /* 2409 */ "GPRnoip\000"
1048 /* 2417 */ "GPRPair_with_gsub_1_in_GPRsp\000"
1049 /* 2446 */ "GPRnoip_and_GPRnosp\000"
1050 /* 2466 */ "GPRwithAPSRnosp\000"
1051 /* 2482 */ "GPRwithZRnosp\000"
1052 /* 2496 */ "GPRnoip_and_GPRwithAPSR_NZCVnosp\000"
1053 /* 2529 */ "GPRPairnosp\000"
1054 /* 2541 */ "DPair\000"
1055 /* 2547 */ "GPRPair\000"
1056 /* 2555 */ "GPRlr\000"
1057 /* 2561 */ "FPCXTRegs\000"
1058};
1059#ifdef __GNUC__
1060#pragma GCC diagnostic pop
1061#endif
1062
1063using ARMRegisterClassStorage = MCRegisterClassStorage<137, 1345, 684, 3020, 94, 755>;
1064extern const MCRegisterClassStorage<137, 1345, 684, 3020, 94, 755> ARMMCRegisterClassStorage = {
1065 .Classes: {
1066 {
1067 offsetof(ARMRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
1068 offsetof(ARMRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
1069 .NameIdx: 1717,
1070 .RegSizeInBits: 16,
1071 .RegsSize: 32,
1072 .RegSetBegin: 87, /* MinRegVal */
1073 .RegSetSize: 32, /* RegSetSize */
1074 .ID: ARM::HPRRegClassID,
1075 .CopyCost: 1, /* CopyCost */
1076 .Allocatable: true, /* Allocatable */
1077 .BaseClass: false,
1078 offsetof(ARMRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
1079 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[22]) - 0 * sizeof(MCRegisterClass),
1080 .LaneMask: LaneBitmask(0x0000000000000001),
1081 .AllocationPriority: 0,
1082 .GlobalPriority: false,
1083 .TSFlags: 0x00, /* TSFlags */
1084 .SpillStackID: 0, /* SpillStackID */
1085 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1086 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1087 offsetof(ARMRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
1088 .SuperClassesSize: 0
1089 },
1090 {
1091 offsetof(ARMRegisterClassStorage, Regs[32]) - 1 * sizeof(MCRegisterClass),
1092 offsetof(ARMRegisterClassStorage, BitSets[4]) - 1 * sizeof(MCRegisterClass),
1093 .NameIdx: 2165,
1094 .RegSizeInBits: 32,
1095 .RegsSize: 65,
1096 .RegSetBegin: 19, /* MinRegVal */
1097 .RegSetSize: 100, /* RegSetSize */
1098 .ID: ARM::FPWithVPRRegClassID,
1099 .CopyCost: 1, /* CopyCost */
1100 .Allocatable: false, /* Allocatable */
1101 .BaseClass: false,
1102 offsetof(ARMRegisterClassStorage, SubClassMasks[85]) - 1 * sizeof(MCRegisterClass),
1103 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[14]) - 1 * sizeof(MCRegisterClass),
1104 .LaneMask: LaneBitmask(0x000000000000000C),
1105 .AllocationPriority: 0,
1106 .GlobalPriority: false,
1107 .TSFlags: 0x00, /* TSFlags */
1108 .SpillStackID: 0, /* SpillStackID */
1109 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1110 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1111 offsetof(ARMRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
1112 .SuperClassesSize: 0
1113 },
1114 {
1115 offsetof(ARMRegisterClassStorage, Regs[97]) - 2 * sizeof(MCRegisterClass),
1116 offsetof(ARMRegisterClassStorage, BitSets[17]) - 2 * sizeof(MCRegisterClass),
1117 .NameIdx: 2161,
1118 .RegSizeInBits: 32,
1119 .RegsSize: 32,
1120 .RegSetBegin: 87, /* MinRegVal */
1121 .RegSetSize: 32, /* RegSetSize */
1122 .ID: ARM::SPRRegClassID,
1123 .CopyCost: 1, /* CopyCost */
1124 .Allocatable: true, /* Allocatable */
1125 .BaseClass: false,
1126 offsetof(ARMRegisterClassStorage, SubClassMasks[210]) - 2 * sizeof(MCRegisterClass),
1127 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[22]) - 2 * sizeof(MCRegisterClass),
1128 .LaneMask: LaneBitmask(0x0000000000000001),
1129 .AllocationPriority: 0,
1130 .GlobalPriority: false,
1131 .TSFlags: 0x00, /* TSFlags */
1132 .SpillStackID: 0, /* SpillStackID */
1133 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1134 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1135 offsetof(ARMRegisterClassStorage, SuperClasses[0]) - 2 * sizeof(MCRegisterClass),
1136 .SuperClassesSize: 2
1137 },
1138 {
1139 offsetof(ARMRegisterClassStorage, Regs[129]) - 3 * sizeof(MCRegisterClass),
1140 offsetof(ARMRegisterClassStorage, BitSets[21]) - 3 * sizeof(MCRegisterClass),
1141 .NameIdx: 19,
1142 .RegSizeInBits: 32,
1143 .RegsSize: 16,
1144 .RegSetBegin: 21, /* MinRegVal */
1145 .RegSetSize: 16, /* RegSetSize */
1146 .ID: ARM::FPWithVPR_with_ssub_0RegClassID,
1147 .CopyCost: 1, /* CopyCost */
1148 .Allocatable: false, /* Allocatable */
1149 .BaseClass: false,
1150 offsetof(ARMRegisterClassStorage, SubClassMasks[295]) - 3 * sizeof(MCRegisterClass),
1151 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[0]) - 3 * sizeof(MCRegisterClass),
1152 .LaneMask: LaneBitmask(0x000000000000000C),
1153 .AllocationPriority: 0,
1154 .GlobalPriority: false,
1155 .TSFlags: 0x00, /* TSFlags */
1156 .SpillStackID: 0, /* SpillStackID */
1157 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1158 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1159 offsetof(ARMRegisterClassStorage, SuperClasses[2]) - 3 * sizeof(MCRegisterClass),
1160 .SuperClassesSize: 1
1161 },
1162 {
1163 offsetof(ARMRegisterClassStorage, Regs[145]) - 4 * sizeof(MCRegisterClass),
1164 offsetof(ARMRegisterClassStorage, BitSets[23]) - 4 * sizeof(MCRegisterClass),
1165 .NameIdx: 1454,
1166 .RegSizeInBits: 32,
1167 .RegsSize: 16,
1168 .RegSetBegin: 14, /* MinRegVal */
1169 .RegSetSize: 73, /* RegSetSize */
1170 .ID: ARM::GPRRegClassID,
1171 .CopyCost: 1, /* CopyCost */
1172 .Allocatable: true, /* Allocatable */
1173 .BaseClass: false,
1174 offsetof(ARMRegisterClassStorage, SubClassMasks[340]) - 4 * sizeof(MCRegisterClass),
1175 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 4 * sizeof(MCRegisterClass),
1176 .LaneMask: LaneBitmask(0x0000000000000001),
1177 .AllocationPriority: 0,
1178 .GlobalPriority: false,
1179 .TSFlags: 0x00, /* TSFlags */
1180 .SpillStackID: 0, /* SpillStackID */
1181 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1182 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1183 offsetof(ARMRegisterClassStorage, SuperClasses[3]) - 4 * sizeof(MCRegisterClass),
1184 .SuperClassesSize: 0
1185 },
1186 {
1187 offsetof(ARMRegisterClassStorage, Regs[161]) - 5 * sizeof(MCRegisterClass),
1188 offsetof(ARMRegisterClassStorage, BitSets[33]) - 5 * sizeof(MCRegisterClass),
1189 .NameIdx: 2175,
1190 .RegSizeInBits: 32,
1191 .RegsSize: 16,
1192 .RegSetBegin: 2, /* MinRegVal */
1193 .RegSetSize: 85, /* RegSetSize */
1194 .ID: ARM::GPRwithAPSRRegClassID,
1195 .CopyCost: 1, /* CopyCost */
1196 .Allocatable: true, /* Allocatable */
1197 .BaseClass: false,
1198 offsetof(ARMRegisterClassStorage, SubClassMasks[355]) - 5 * sizeof(MCRegisterClass),
1199 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 5 * sizeof(MCRegisterClass),
1200 .LaneMask: LaneBitmask(0x0000000000000001),
1201 .AllocationPriority: 0,
1202 .GlobalPriority: false,
1203 .TSFlags: 0x00, /* TSFlags */
1204 .SpillStackID: 0, /* SpillStackID */
1205 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1206 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1207 offsetof(ARMRegisterClassStorage, SuperClasses[3]) - 5 * sizeof(MCRegisterClass),
1208 .SuperClassesSize: 0
1209 },
1210 {
1211 offsetof(ARMRegisterClassStorage, Regs[177]) - 6 * sizeof(MCRegisterClass),
1212 offsetof(ARMRegisterClassStorage, BitSets[44]) - 6 * sizeof(MCRegisterClass),
1213 .NameIdx: 2187,
1214 .RegSizeInBits: 32,
1215 .RegsSize: 16,
1216 .RegSetBegin: 14, /* MinRegVal */
1217 .RegSetSize: 73, /* RegSetSize */
1218 .ID: ARM::GPRwithZRRegClassID,
1219 .CopyCost: 1, /* CopyCost */
1220 .Allocatable: true, /* Allocatable */
1221 .BaseClass: false,
1222 offsetof(ARMRegisterClassStorage, SubClassMasks[370]) - 6 * sizeof(MCRegisterClass),
1223 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 6 * sizeof(MCRegisterClass),
1224 .LaneMask: LaneBitmask(0x0000000000000001),
1225 .AllocationPriority: 0,
1226 .GlobalPriority: false,
1227 .TSFlags: 0x00, /* TSFlags */
1228 .SpillStackID: 0, /* SpillStackID */
1229 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1230 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1231 offsetof(ARMRegisterClassStorage, SuperClasses[3]) - 6 * sizeof(MCRegisterClass),
1232 .SuperClassesSize: 0
1233 },
1234 {
1235 offsetof(ARMRegisterClassStorage, Regs[193]) - 7 * sizeof(MCRegisterClass),
1236 offsetof(ARMRegisterClassStorage, BitSets[54]) - 7 * sizeof(MCRegisterClass),
1237 .NameIdx: 1365,
1238 .RegSizeInBits: 32,
1239 .RegsSize: 16,
1240 .RegSetBegin: 87, /* MinRegVal */
1241 .RegSetSize: 16, /* RegSetSize */
1242 .ID: ARM::SPR_8RegClassID,
1243 .CopyCost: 1, /* CopyCost */
1244 .Allocatable: true, /* Allocatable */
1245 .BaseClass: false,
1246 offsetof(ARMRegisterClassStorage, SubClassMasks[385]) - 7 * sizeof(MCRegisterClass),
1247 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[22]) - 7 * sizeof(MCRegisterClass),
1248 .LaneMask: LaneBitmask(0x0000000000000001),
1249 .AllocationPriority: 0,
1250 .GlobalPriority: false,
1251 .TSFlags: 0x00, /* TSFlags */
1252 .SpillStackID: 0, /* SpillStackID */
1253 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1254 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1255 offsetof(ARMRegisterClassStorage, SuperClasses[3]) - 7 * sizeof(MCRegisterClass),
1256 .SuperClassesSize: 3
1257 },
1258 {
1259 offsetof(ARMRegisterClassStorage, Regs[209]) - 8 * sizeof(MCRegisterClass),
1260 offsetof(ARMRegisterClassStorage, BitSets[56]) - 8 * sizeof(MCRegisterClass),
1261 .NameIdx: 2287,
1262 .RegSizeInBits: 32,
1263 .RegsSize: 15,
1264 .RegSetBegin: 14, /* MinRegVal */
1265 .RegSetSize: 73, /* RegSetSize */
1266 .ID: ARM::GPRnopcRegClassID,
1267 .CopyCost: 1, /* CopyCost */
1268 .Allocatable: true, /* Allocatable */
1269 .BaseClass: false,
1270 offsetof(ARMRegisterClassStorage, SubClassMasks[470]) - 8 * sizeof(MCRegisterClass),
1271 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 8 * sizeof(MCRegisterClass),
1272 .LaneMask: LaneBitmask(0x0000000000000001),
1273 .AllocationPriority: 0,
1274 .GlobalPriority: false,
1275 .TSFlags: 0x00, /* TSFlags */
1276 .SpillStackID: 0, /* SpillStackID */
1277 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1278 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1279 offsetof(ARMRegisterClassStorage, SuperClasses[6]) - 8 * sizeof(MCRegisterClass),
1280 .SuperClassesSize: 3
1281 },
1282 {
1283 offsetof(ARMRegisterClassStorage, Regs[224]) - 9 * sizeof(MCRegisterClass),
1284 offsetof(ARMRegisterClassStorage, BitSets[66]) - 9 * sizeof(MCRegisterClass),
1285 .NameIdx: 2458,
1286 .RegSizeInBits: 32,
1287 .RegsSize: 15,
1288 .RegSetBegin: 14, /* MinRegVal */
1289 .RegSetSize: 73, /* RegSetSize */
1290 .ID: ARM::GPRnospRegClassID,
1291 .CopyCost: 1, /* CopyCost */
1292 .Allocatable: true, /* Allocatable */
1293 .BaseClass: false,
1294 offsetof(ARMRegisterClassStorage, SubClassMasks[485]) - 9 * sizeof(MCRegisterClass),
1295 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 9 * sizeof(MCRegisterClass),
1296 .LaneMask: LaneBitmask(0x0000000000000001),
1297 .AllocationPriority: 0,
1298 .GlobalPriority: false,
1299 .TSFlags: 0x00, /* TSFlags */
1300 .SpillStackID: 0, /* SpillStackID */
1301 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1302 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1303 offsetof(ARMRegisterClassStorage, SuperClasses[9]) - 9 * sizeof(MCRegisterClass),
1304 .SuperClassesSize: 1
1305 },
1306 {
1307 offsetof(ARMRegisterClassStorage, Regs[239]) - 10 * sizeof(MCRegisterClass),
1308 offsetof(ARMRegisterClassStorage, BitSets[76]) - 10 * sizeof(MCRegisterClass),
1309 .NameIdx: 2508,
1310 .RegSizeInBits: 32,
1311 .RegsSize: 15,
1312 .RegSetBegin: 2, /* MinRegVal */
1313 .RegSetSize: 85, /* RegSetSize */
1314 .ID: ARM::GPRwithAPSR_NZCVnospRegClassID,
1315 .CopyCost: 1, /* CopyCost */
1316 .Allocatable: false, /* Allocatable */
1317 .BaseClass: false,
1318 offsetof(ARMRegisterClassStorage, SubClassMasks[500]) - 10 * sizeof(MCRegisterClass),
1319 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 10 * sizeof(MCRegisterClass),
1320 .LaneMask: LaneBitmask(0x0000000000000001),
1321 .AllocationPriority: 0,
1322 .GlobalPriority: false,
1323 .TSFlags: 0x00, /* TSFlags */
1324 .SpillStackID: 0, /* SpillStackID */
1325 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1326 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1327 offsetof(ARMRegisterClassStorage, SuperClasses[10]) - 10 * sizeof(MCRegisterClass),
1328 .SuperClassesSize: 1
1329 },
1330 {
1331 offsetof(ARMRegisterClassStorage, Regs[254]) - 11 * sizeof(MCRegisterClass),
1332 offsetof(ARMRegisterClassStorage, BitSets[87]) - 11 * sizeof(MCRegisterClass),
1333 .NameIdx: 2466,
1334 .RegSizeInBits: 32,
1335 .RegsSize: 15,
1336 .RegSetBegin: 1, /* MinRegVal */
1337 .RegSetSize: 86, /* RegSetSize */
1338 .ID: ARM::GPRwithAPSRnospRegClassID,
1339 .CopyCost: 1, /* CopyCost */
1340 .Allocatable: false, /* Allocatable */
1341 .BaseClass: false,
1342 offsetof(ARMRegisterClassStorage, SubClassMasks[515]) - 11 * sizeof(MCRegisterClass),
1343 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 11 * sizeof(MCRegisterClass),
1344 .LaneMask: LaneBitmask(0x0000000000000001),
1345 .AllocationPriority: 0,
1346 .GlobalPriority: false,
1347 .TSFlags: 0x00, /* TSFlags */
1348 .SpillStackID: 0, /* SpillStackID */
1349 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1350 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1351 offsetof(ARMRegisterClassStorage, SuperClasses[11]) - 11 * sizeof(MCRegisterClass),
1352 .SuperClassesSize: 0
1353 },
1354 {
1355 offsetof(ARMRegisterClassStorage, Regs[269]) - 12 * sizeof(MCRegisterClass),
1356 offsetof(ARMRegisterClassStorage, BitSets[98]) - 12 * sizeof(MCRegisterClass),
1357 .NameIdx: 2482,
1358 .RegSizeInBits: 32,
1359 .RegsSize: 15,
1360 .RegSetBegin: 14, /* MinRegVal */
1361 .RegSetSize: 73, /* RegSetSize */
1362 .ID: ARM::GPRwithZRnospRegClassID,
1363 .CopyCost: 1, /* CopyCost */
1364 .Allocatable: true, /* Allocatable */
1365 .BaseClass: false,
1366 offsetof(ARMRegisterClassStorage, SubClassMasks[530]) - 12 * sizeof(MCRegisterClass),
1367 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 12 * sizeof(MCRegisterClass),
1368 .LaneMask: LaneBitmask(0x0000000000000001),
1369 .AllocationPriority: 0,
1370 .GlobalPriority: false,
1371 .TSFlags: 0x00, /* TSFlags */
1372 .SpillStackID: 0, /* SpillStackID */
1373 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1374 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1375 offsetof(ARMRegisterClassStorage, SuperClasses[11]) - 12 * sizeof(MCRegisterClass),
1376 .SuperClassesSize: 1
1377 },
1378 {
1379 offsetof(ARMRegisterClassStorage, Regs[284]) - 13 * sizeof(MCRegisterClass),
1380 offsetof(ARMRegisterClassStorage, BitSets[108]) - 13 * sizeof(MCRegisterClass),
1381 .NameIdx: 2409,
1382 .RegSizeInBits: 32,
1383 .RegsSize: 14,
1384 .RegSetBegin: 15, /* MinRegVal */
1385 .RegSetSize: 71, /* RegSetSize */
1386 .ID: ARM::GPRnoipRegClassID,
1387 .CopyCost: 1, /* CopyCost */
1388 .Allocatable: true, /* Allocatable */
1389 .BaseClass: false,
1390 offsetof(ARMRegisterClassStorage, SubClassMasks[545]) - 13 * sizeof(MCRegisterClass),
1391 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 13 * sizeof(MCRegisterClass),
1392 .LaneMask: LaneBitmask(0x0000000000000001),
1393 .AllocationPriority: 0,
1394 .GlobalPriority: false,
1395 .TSFlags: 0x00, /* TSFlags */
1396 .SpillStackID: 0, /* SpillStackID */
1397 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1398 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1399 offsetof(ARMRegisterClassStorage, SuperClasses[12]) - 13 * sizeof(MCRegisterClass),
1400 .SuperClassesSize: 1
1401 },
1402 {
1403 offsetof(ARMRegisterClassStorage, Regs[298]) - 14 * sizeof(MCRegisterClass),
1404 offsetof(ARMRegisterClassStorage, BitSets[117]) - 14 * sizeof(MCRegisterClass),
1405 .NameIdx: 1684,
1406 .RegSizeInBits: 32,
1407 .RegsSize: 14,
1408 .RegSetBegin: 14, /* MinRegVal */
1409 .RegSetSize: 73, /* RegSetSize */
1410 .ID: ARM::rGPRRegClassID,
1411 .CopyCost: 1, /* CopyCost */
1412 .Allocatable: true, /* Allocatable */
1413 .BaseClass: false,
1414 offsetof(ARMRegisterClassStorage, SubClassMasks[560]) - 14 * sizeof(MCRegisterClass),
1415 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 14 * sizeof(MCRegisterClass),
1416 .LaneMask: LaneBitmask(0x0000000000000001),
1417 .AllocationPriority: 0,
1418 .GlobalPriority: false,
1419 .TSFlags: 0x00, /* TSFlags */
1420 .SpillStackID: 0, /* SpillStackID */
1421 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1422 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1423 offsetof(ARMRegisterClassStorage, SuperClasses[13]) - 14 * sizeof(MCRegisterClass),
1424 .SuperClassesSize: 8
1425 },
1426 {
1427 offsetof(ARMRegisterClassStorage, Regs[312]) - 15 * sizeof(MCRegisterClass),
1428 offsetof(ARMRegisterClassStorage, BitSets[127]) - 15 * sizeof(MCRegisterClass),
1429 .NameIdx: 2275,
1430 .RegSizeInBits: 32,
1431 .RegsSize: 13,
1432 .RegSetBegin: 17, /* MinRegVal */
1433 .RegSetSize: 69, /* RegSetSize */
1434 .ID: ARM::GPRnoip_and_GPRnopcRegClassID,
1435 .CopyCost: 1, /* CopyCost */
1436 .Allocatable: true, /* Allocatable */
1437 .BaseClass: false,
1438 offsetof(ARMRegisterClassStorage, SubClassMasks[575]) - 15 * sizeof(MCRegisterClass),
1439 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 15 * sizeof(MCRegisterClass),
1440 .LaneMask: LaneBitmask(0x0000000000000001),
1441 .AllocationPriority: 0,
1442 .GlobalPriority: false,
1443 .TSFlags: 0x00, /* TSFlags */
1444 .SpillStackID: 0, /* SpillStackID */
1445 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1446 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1447 offsetof(ARMRegisterClassStorage, SuperClasses[21]) - 15 * sizeof(MCRegisterClass),
1448 .SuperClassesSize: 5
1449 },
1450 {
1451 offsetof(ARMRegisterClassStorage, Regs[325]) - 16 * sizeof(MCRegisterClass),
1452 offsetof(ARMRegisterClassStorage, BitSets[136]) - 16 * sizeof(MCRegisterClass),
1453 .NameIdx: 2446,
1454 .RegSizeInBits: 32,
1455 .RegsSize: 13,
1456 .RegSetBegin: 15, /* MinRegVal */
1457 .RegSetSize: 71, /* RegSetSize */
1458 .ID: ARM::GPRnoip_and_GPRnospRegClassID,
1459 .CopyCost: 1, /* CopyCost */
1460 .Allocatable: true, /* Allocatable */
1461 .BaseClass: false,
1462 offsetof(ARMRegisterClassStorage, SubClassMasks[590]) - 16 * sizeof(MCRegisterClass),
1463 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 16 * sizeof(MCRegisterClass),
1464 .LaneMask: LaneBitmask(0x0000000000000001),
1465 .AllocationPriority: 0,
1466 .GlobalPriority: false,
1467 .TSFlags: 0x00, /* TSFlags */
1468 .SpillStackID: 0, /* SpillStackID */
1469 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1470 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1471 offsetof(ARMRegisterClassStorage, SuperClasses[26]) - 16 * sizeof(MCRegisterClass),
1472 .SuperClassesSize: 3
1473 },
1474 {
1475 offsetof(ARMRegisterClassStorage, Regs[338]) - 17 * sizeof(MCRegisterClass),
1476 offsetof(ARMRegisterClassStorage, BitSets[145]) - 17 * sizeof(MCRegisterClass),
1477 .NameIdx: 2496,
1478 .RegSizeInBits: 32,
1479 .RegsSize: 12,
1480 .RegSetBegin: 74, /* MinRegVal */
1481 .RegSetSize: 12, /* RegSetSize */
1482 .ID: ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID,
1483 .CopyCost: 1, /* CopyCost */
1484 .Allocatable: true, /* Allocatable */
1485 .BaseClass: false,
1486 offsetof(ARMRegisterClassStorage, SubClassMasks[605]) - 17 * sizeof(MCRegisterClass),
1487 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 17 * sizeof(MCRegisterClass),
1488 .LaneMask: LaneBitmask(0x0000000000000001),
1489 .AllocationPriority: 0,
1490 .GlobalPriority: false,
1491 .TSFlags: 0x00, /* TSFlags */
1492 .SpillStackID: 0, /* SpillStackID */
1493 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1494 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1495 offsetof(ARMRegisterClassStorage, SuperClasses[29]) - 17 * sizeof(MCRegisterClass),
1496 .SuperClassesSize: 12
1497 },
1498 {
1499 offsetof(ARMRegisterClassStorage, Regs[350]) - 18 * sizeof(MCRegisterClass),
1500 offsetof(ARMRegisterClassStorage, BitSets[147]) - 18 * sizeof(MCRegisterClass),
1501 .NameIdx: 2264,
1502 .RegSizeInBits: 32,
1503 .RegsSize: 9,
1504 .RegSetBegin: 15, /* MinRegVal */
1505 .RegSetSize: 67, /* RegSetSize */
1506 .ID: ARM::tGPRwithpcRegClassID,
1507 .CopyCost: 1, /* CopyCost */
1508 .Allocatable: true, /* Allocatable */
1509 .BaseClass: false,
1510 offsetof(ARMRegisterClassStorage, SubClassMasks[620]) - 18 * sizeof(MCRegisterClass),
1511 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 18 * sizeof(MCRegisterClass),
1512 .LaneMask: LaneBitmask(0x0000000000000001),
1513 .AllocationPriority: 0,
1514 .GlobalPriority: false,
1515 .TSFlags: 0x00, /* TSFlags */
1516 .SpillStackID: 0, /* SpillStackID */
1517 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1518 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1519 offsetof(ARMRegisterClassStorage, SuperClasses[41]) - 18 * sizeof(MCRegisterClass),
1520 .SuperClassesSize: 4
1521 },
1522 {
1523 offsetof(ARMRegisterClassStorage, Regs[359]) - 19 * sizeof(MCRegisterClass),
1524 offsetof(ARMRegisterClassStorage, BitSets[156]) - 19 * sizeof(MCRegisterClass),
1525 .NameIdx: 1328,
1526 .RegSizeInBits: 32,
1527 .RegsSize: 8,
1528 .RegSetBegin: 21, /* MinRegVal */
1529 .RegSetSize: 8, /* RegSetSize */
1530 .ID: ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID,
1531 .CopyCost: 1, /* CopyCost */
1532 .Allocatable: false, /* Allocatable */
1533 .BaseClass: false,
1534 offsetof(ARMRegisterClassStorage, SubClassMasks[635]) - 19 * sizeof(MCRegisterClass),
1535 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[0]) - 19 * sizeof(MCRegisterClass),
1536 .LaneMask: LaneBitmask(0x000000000000000C),
1537 .AllocationPriority: 0,
1538 .GlobalPriority: false,
1539 .TSFlags: 0x00, /* TSFlags */
1540 .SpillStackID: 0, /* SpillStackID */
1541 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1542 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1543 offsetof(ARMRegisterClassStorage, SuperClasses[45]) - 19 * sizeof(MCRegisterClass),
1544 .SuperClassesSize: 2
1545 },
1546 {
1547 offsetof(ARMRegisterClassStorage, Regs[367]) - 20 * sizeof(MCRegisterClass),
1548 offsetof(ARMRegisterClassStorage, BitSets[157]) - 20 * sizeof(MCRegisterClass),
1549 .NameIdx: 1548,
1550 .RegSizeInBits: 32,
1551 .RegsSize: 8,
1552 .RegSetBegin: 14, /* MinRegVal */
1553 .RegSetSize: 73, /* RegSetSize */
1554 .ID: ARM::hGPRRegClassID,
1555 .CopyCost: 1, /* CopyCost */
1556 .Allocatable: true, /* Allocatable */
1557 .BaseClass: false,
1558 offsetof(ARMRegisterClassStorage, SubClassMasks[680]) - 20 * sizeof(MCRegisterClass),
1559 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 20 * sizeof(MCRegisterClass),
1560 .LaneMask: LaneBitmask(0x0000000000000001),
1561 .AllocationPriority: 0,
1562 .GlobalPriority: false,
1563 .TSFlags: 0x00, /* TSFlags */
1564 .SpillStackID: 0, /* SpillStackID */
1565 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1566 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1567 offsetof(ARMRegisterClassStorage, SuperClasses[47]) - 20 * sizeof(MCRegisterClass),
1568 .SuperClassesSize: 1
1569 },
1570 {
1571 offsetof(ARMRegisterClassStorage, Regs[375]) - 21 * sizeof(MCRegisterClass),
1572 offsetof(ARMRegisterClassStorage, BitSets[167]) - 21 * sizeof(MCRegisterClass),
1573 .NameIdx: 1712,
1574 .RegSizeInBits: 32,
1575 .RegsSize: 8,
1576 .RegSetBegin: 74, /* MinRegVal */
1577 .RegSetSize: 8, /* RegSetSize */
1578 .ID: ARM::tGPRRegClassID,
1579 .CopyCost: 1, /* CopyCost */
1580 .Allocatable: true, /* Allocatable */
1581 .BaseClass: false,
1582 offsetof(ARMRegisterClassStorage, SubClassMasks[695]) - 21 * sizeof(MCRegisterClass),
1583 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 21 * sizeof(MCRegisterClass),
1584 .LaneMask: LaneBitmask(0x0000000000000001),
1585 .AllocationPriority: 0,
1586 .GlobalPriority: false,
1587 .TSFlags: 0x00, /* TSFlags */
1588 .SpillStackID: 0, /* SpillStackID */
1589 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1590 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1591 offsetof(ARMRegisterClassStorage, SuperClasses[48]) - 21 * sizeof(MCRegisterClass),
1592 .SuperClassesSize: 14
1593 },
1594 {
1595 offsetof(ARMRegisterClassStorage, Regs[383]) - 22 * sizeof(MCRegisterClass),
1596 offsetof(ARMRegisterClassStorage, BitSets[168]) - 22 * sizeof(MCRegisterClass),
1597 .NameIdx: 2352,
1598 .RegSizeInBits: 32,
1599 .RegsSize: 8,
1600 .RegSetBegin: 14, /* MinRegVal */
1601 .RegSetSize: 73, /* RegSetSize */
1602 .ID: ARM::tGPREvenRegClassID,
1603 .CopyCost: 1, /* CopyCost */
1604 .Allocatable: true, /* Allocatable */
1605 .BaseClass: false,
1606 offsetof(ARMRegisterClassStorage, SubClassMasks[710]) - 22 * sizeof(MCRegisterClass),
1607 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 22 * sizeof(MCRegisterClass),
1608 .LaneMask: LaneBitmask(0x0000000000000001),
1609 .AllocationPriority: 0,
1610 .GlobalPriority: false,
1611 .TSFlags: 0x00, /* TSFlags */
1612 .SpillStackID: 0, /* SpillStackID */
1613 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1614 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1615 offsetof(ARMRegisterClassStorage, SuperClasses[62]) - 22 * sizeof(MCRegisterClass),
1616 .SuperClassesSize: 9
1617 },
1618 {
1619 offsetof(ARMRegisterClassStorage, Regs[391]) - 23 * sizeof(MCRegisterClass),
1620 offsetof(ARMRegisterClassStorage, BitSets[178]) - 23 * sizeof(MCRegisterClass),
1621 .NameIdx: 1536,
1622 .RegSizeInBits: 32,
1623 .RegsSize: 7,
1624 .RegSetBegin: 14, /* MinRegVal */
1625 .RegSetSize: 73, /* RegSetSize */
1626 .ID: ARM::GPRnopc_and_hGPRRegClassID,
1627 .CopyCost: 1, /* CopyCost */
1628 .Allocatable: true, /* Allocatable */
1629 .BaseClass: false,
1630 offsetof(ARMRegisterClassStorage, SubClassMasks[720]) - 23 * sizeof(MCRegisterClass),
1631 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 23 * sizeof(MCRegisterClass),
1632 .LaneMask: LaneBitmask(0x0000000000000001),
1633 .AllocationPriority: 0,
1634 .GlobalPriority: false,
1635 .TSFlags: 0x00, /* TSFlags */
1636 .SpillStackID: 0, /* SpillStackID */
1637 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1638 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1639 offsetof(ARMRegisterClassStorage, SuperClasses[71]) - 23 * sizeof(MCRegisterClass),
1640 .SuperClassesSize: 5
1641 },
1642 {
1643 offsetof(ARMRegisterClassStorage, Regs[398]) - 24 * sizeof(MCRegisterClass),
1644 offsetof(ARMRegisterClassStorage, BitSets[188]) - 24 * sizeof(MCRegisterClass),
1645 .NameIdx: 1623,
1646 .RegSizeInBits: 32,
1647 .RegsSize: 7,
1648 .RegSetBegin: 14, /* MinRegVal */
1649 .RegSetSize: 73, /* RegSetSize */
1650 .ID: ARM::GPRnosp_and_hGPRRegClassID,
1651 .CopyCost: 1, /* CopyCost */
1652 .Allocatable: true, /* Allocatable */
1653 .BaseClass: false,
1654 offsetof(ARMRegisterClassStorage, SubClassMasks[735]) - 24 * sizeof(MCRegisterClass),
1655 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 24 * sizeof(MCRegisterClass),
1656 .LaneMask: LaneBitmask(0x0000000000000001),
1657 .AllocationPriority: 0,
1658 .GlobalPriority: false,
1659 .TSFlags: 0x00, /* TSFlags */
1660 .SpillStackID: 0, /* SpillStackID */
1661 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1662 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1663 offsetof(ARMRegisterClassStorage, SuperClasses[76]) - 24 * sizeof(MCRegisterClass),
1664 .SuperClassesSize: 3
1665 },
1666 {
1667 offsetof(ARMRegisterClassStorage, Regs[405]) - 25 * sizeof(MCRegisterClass),
1668 offsetof(ARMRegisterClassStorage, BitSets[198]) - 25 * sizeof(MCRegisterClass),
1669 .NameIdx: 1577,
1670 .RegSizeInBits: 32,
1671 .RegsSize: 6,
1672 .RegSetBegin: 15, /* MinRegVal */
1673 .RegSetSize: 71, /* RegSetSize */
1674 .ID: ARM::GPRnoip_and_hGPRRegClassID,
1675 .CopyCost: 1, /* CopyCost */
1676 .Allocatable: true, /* Allocatable */
1677 .BaseClass: false,
1678 offsetof(ARMRegisterClassStorage, SubClassMasks[750]) - 25 * sizeof(MCRegisterClass),
1679 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 25 * sizeof(MCRegisterClass),
1680 .LaneMask: LaneBitmask(0x0000000000000001),
1681 .AllocationPriority: 0,
1682 .GlobalPriority: false,
1683 .TSFlags: 0x00, /* TSFlags */
1684 .SpillStackID: 0, /* SpillStackID */
1685 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1686 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1687 offsetof(ARMRegisterClassStorage, SuperClasses[79]) - 25 * sizeof(MCRegisterClass),
1688 .SuperClassesSize: 3
1689 },
1690 {
1691 offsetof(ARMRegisterClassStorage, Regs[411]) - 26 * sizeof(MCRegisterClass),
1692 offsetof(ARMRegisterClassStorage, BitSets[207]) - 26 * sizeof(MCRegisterClass),
1693 .NameIdx: 2388,
1694 .RegSizeInBits: 32,
1695 .RegsSize: 6,
1696 .RegSetBegin: 74, /* MinRegVal */
1697 .RegSetSize: 11, /* RegSetSize */
1698 .ID: ARM::GPRnoip_and_tGPREvenRegClassID,
1699 .CopyCost: 1, /* CopyCost */
1700 .Allocatable: true, /* Allocatable */
1701 .BaseClass: false,
1702 offsetof(ARMRegisterClassStorage, SubClassMasks[765]) - 26 * sizeof(MCRegisterClass),
1703 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 26 * sizeof(MCRegisterClass),
1704 .LaneMask: LaneBitmask(0x0000000000000001),
1705 .AllocationPriority: 0,
1706 .GlobalPriority: false,
1707 .TSFlags: 0x00, /* TSFlags */
1708 .SpillStackID: 0, /* SpillStackID */
1709 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1710 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1711 offsetof(ARMRegisterClassStorage, SuperClasses[82]) - 26 * sizeof(MCRegisterClass),
1712 .SuperClassesSize: 14
1713 },
1714 {
1715 offsetof(ARMRegisterClassStorage, Regs[417]) - 27 * sizeof(MCRegisterClass),
1716 offsetof(ARMRegisterClassStorage, BitSets[209]) - 27 * sizeof(MCRegisterClass),
1717 .NameIdx: 1524,
1718 .RegSizeInBits: 32,
1719 .RegsSize: 6,
1720 .RegSetBegin: 14, /* MinRegVal */
1721 .RegSetSize: 73, /* RegSetSize */
1722 .ID: ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID,
1723 .CopyCost: 1, /* CopyCost */
1724 .Allocatable: true, /* Allocatable */
1725 .BaseClass: false,
1726 offsetof(ARMRegisterClassStorage, SubClassMasks[775]) - 27 * sizeof(MCRegisterClass),
1727 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 27 * sizeof(MCRegisterClass),
1728 .LaneMask: LaneBitmask(0x0000000000000001),
1729 .AllocationPriority: 0,
1730 .GlobalPriority: false,
1731 .TSFlags: 0x00, /* TSFlags */
1732 .SpillStackID: 0, /* SpillStackID */
1733 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1734 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1735 offsetof(ARMRegisterClassStorage, SuperClasses[96]) - 27 * sizeof(MCRegisterClass),
1736 .SuperClassesSize: 12
1737 },
1738 {
1739 offsetof(ARMRegisterClassStorage, Regs[423]) - 28 * sizeof(MCRegisterClass),
1740 offsetof(ARMRegisterClassStorage, BitSets[219]) - 28 * sizeof(MCRegisterClass),
1741 .NameIdx: 2310,
1742 .RegSizeInBits: 32,
1743 .RegsSize: 6,
1744 .RegSetBegin: 75, /* MinRegVal */
1745 .RegSetSize: 11, /* RegSetSize */
1746 .ID: ARM::tGPROddRegClassID,
1747 .CopyCost: 1, /* CopyCost */
1748 .Allocatable: true, /* Allocatable */
1749 .BaseClass: false,
1750 offsetof(ARMRegisterClassStorage, SubClassMasks[790]) - 28 * sizeof(MCRegisterClass),
1751 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[12]) - 28 * sizeof(MCRegisterClass),
1752 .LaneMask: LaneBitmask(0x0000000000000001),
1753 .AllocationPriority: 0,
1754 .GlobalPriority: false,
1755 .TSFlags: 0x00, /* TSFlags */
1756 .SpillStackID: 0, /* SpillStackID */
1757 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1758 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1759 offsetof(ARMRegisterClassStorage, SuperClasses[108]) - 28 * sizeof(MCRegisterClass),
1760 .SuperClassesSize: 13
1761 },
1762 {
1763 offsetof(ARMRegisterClassStorage, Regs[429]) - 29 * sizeof(MCRegisterClass),
1764 offsetof(ARMRegisterClassStorage, BitSets[221]) - 29 * sizeof(MCRegisterClass),
1765 .NameIdx: 1565,
1766 .RegSizeInBits: 32,
1767 .RegsSize: 5,
1768 .RegSetBegin: 17, /* MinRegVal */
1769 .RegSetSize: 69, /* RegSetSize */
1770 .ID: ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID,
1771 .CopyCost: 1, /* CopyCost */
1772 .Allocatable: true, /* Allocatable */
1773 .BaseClass: false,
1774 offsetof(ARMRegisterClassStorage, SubClassMasks[800]) - 29 * sizeof(MCRegisterClass),
1775 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 29 * sizeof(MCRegisterClass),
1776 .LaneMask: LaneBitmask(0x0000000000000001),
1777 .AllocationPriority: 0,
1778 .GlobalPriority: false,
1779 .TSFlags: 0x00, /* TSFlags */
1780 .SpillStackID: 0, /* SpillStackID */
1781 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1782 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1783 offsetof(ARMRegisterClassStorage, SuperClasses[121]) - 29 * sizeof(MCRegisterClass),
1784 .SuperClassesSize: 9
1785 },
1786 {
1787 offsetof(ARMRegisterClassStorage, Regs[434]) - 30 * sizeof(MCRegisterClass),
1788 offsetof(ARMRegisterClassStorage, BitSets[230]) - 30 * sizeof(MCRegisterClass),
1789 .NameIdx: 1594,
1790 .RegSizeInBits: 32,
1791 .RegsSize: 5,
1792 .RegSetBegin: 15, /* MinRegVal */
1793 .RegSetSize: 71, /* RegSetSize */
1794 .ID: ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID,
1795 .CopyCost: 1, /* CopyCost */
1796 .Allocatable: true, /* Allocatable */
1797 .BaseClass: false,
1798 offsetof(ARMRegisterClassStorage, SubClassMasks[815]) - 30 * sizeof(MCRegisterClass),
1799 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 30 * sizeof(MCRegisterClass),
1800 .LaneMask: LaneBitmask(0x0000000000000001),
1801 .AllocationPriority: 0,
1802 .GlobalPriority: false,
1803 .TSFlags: 0x00, /* TSFlags */
1804 .SpillStackID: 0, /* SpillStackID */
1805 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1806 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1807 offsetof(ARMRegisterClassStorage, SuperClasses[130]) - 30 * sizeof(MCRegisterClass),
1808 .SuperClassesSize: 7
1809 },
1810 {
1811 offsetof(ARMRegisterClassStorage, Regs[439]) - 31 * sizeof(MCRegisterClass),
1812 offsetof(ARMRegisterClassStorage, BitSets[239]) - 31 * sizeof(MCRegisterClass),
1813 .NameIdx: 1452,
1814 .RegSizeInBits: 32,
1815 .RegsSize: 5,
1816 .RegSetBegin: 74, /* MinRegVal */
1817 .RegSetSize: 13, /* RegSetSize */
1818 .ID: ARM::tcGPRRegClassID,
1819 .CopyCost: 1, /* CopyCost */
1820 .Allocatable: true, /* Allocatable */
1821 .BaseClass: false,
1822 offsetof(ARMRegisterClassStorage, SubClassMasks[830]) - 31 * sizeof(MCRegisterClass),
1823 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 31 * sizeof(MCRegisterClass),
1824 .LaneMask: LaneBitmask(0x0000000000000001),
1825 .AllocationPriority: 0,
1826 .GlobalPriority: false,
1827 .TSFlags: 0x00, /* TSFlags */
1828 .SpillStackID: 0, /* SpillStackID */
1829 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1830 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1831 offsetof(ARMRegisterClassStorage, SuperClasses[137]) - 31 * sizeof(MCRegisterClass),
1832 .SuperClassesSize: 9
1833 },
1834 {
1835 offsetof(ARMRegisterClassStorage, Regs[444]) - 32 * sizeof(MCRegisterClass),
1836 offsetof(ARMRegisterClassStorage, BitSets[241]) - 32 * sizeof(MCRegisterClass),
1837 .NameIdx: 1553,
1838 .RegSizeInBits: 32,
1839 .RegsSize: 4,
1840 .RegSetBegin: 82, /* MinRegVal */
1841 .RegSetSize: 4, /* RegSetSize */
1842 .ID: ARM::GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID,
1843 .CopyCost: 1, /* CopyCost */
1844 .Allocatable: true, /* Allocatable */
1845 .BaseClass: false,
1846 offsetof(ARMRegisterClassStorage, SubClassMasks[845]) - 32 * sizeof(MCRegisterClass),
1847 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 32 * sizeof(MCRegisterClass),
1848 .LaneMask: LaneBitmask(0x0000000000000001),
1849 .AllocationPriority: 0,
1850 .GlobalPriority: false,
1851 .TSFlags: 0x00, /* TSFlags */
1852 .SpillStackID: 0, /* SpillStackID */
1853 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1854 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1855 offsetof(ARMRegisterClassStorage, SuperClasses[146]) - 32 * sizeof(MCRegisterClass),
1856 .SuperClassesSize: 20
1857 },
1858 {
1859 offsetof(ARMRegisterClassStorage, Regs[448]) - 33 * sizeof(MCRegisterClass),
1860 offsetof(ARMRegisterClassStorage, BitSets[242]) - 33 * sizeof(MCRegisterClass),
1861 .NameIdx: 2343,
1862 .RegSizeInBits: 32,
1863 .RegsSize: 4,
1864 .RegSetBegin: 14, /* MinRegVal */
1865 .RegSetSize: 73, /* RegSetSize */
1866 .ID: ARM::hGPR_and_tGPREvenRegClassID,
1867 .CopyCost: 1, /* CopyCost */
1868 .Allocatable: true, /* Allocatable */
1869 .BaseClass: false,
1870 offsetof(ARMRegisterClassStorage, SubClassMasks[860]) - 33 * sizeof(MCRegisterClass),
1871 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 33 * sizeof(MCRegisterClass),
1872 .LaneMask: LaneBitmask(0x0000000000000001),
1873 .AllocationPriority: 0,
1874 .GlobalPriority: false,
1875 .TSFlags: 0x00, /* TSFlags */
1876 .SpillStackID: 0, /* SpillStackID */
1877 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1878 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1879 offsetof(ARMRegisterClassStorage, SuperClasses[166]) - 33 * sizeof(MCRegisterClass),
1880 .SuperClassesSize: 14
1881 },
1882 {
1883 offsetof(ARMRegisterClassStorage, Regs[452]) - 34 * sizeof(MCRegisterClass),
1884 offsetof(ARMRegisterClassStorage, BitSets[252]) - 34 * sizeof(MCRegisterClass),
1885 .NameIdx: 2361,
1886 .RegSizeInBits: 32,
1887 .RegsSize: 4,
1888 .RegSetBegin: 74, /* MinRegVal */
1889 .RegSetSize: 7, /* RegSetSize */
1890 .ID: ARM::tGPR_and_tGPREvenRegClassID,
1891 .CopyCost: 1, /* CopyCost */
1892 .Allocatable: true, /* Allocatable */
1893 .BaseClass: false,
1894 offsetof(ARMRegisterClassStorage, SubClassMasks[870]) - 34 * sizeof(MCRegisterClass),
1895 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 34 * sizeof(MCRegisterClass),
1896 .LaneMask: LaneBitmask(0x0000000000000001),
1897 .AllocationPriority: 0,
1898 .GlobalPriority: false,
1899 .TSFlags: 0x00, /* TSFlags */
1900 .SpillStackID: 0, /* SpillStackID */
1901 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1902 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1903 offsetof(ARMRegisterClassStorage, SuperClasses[180]) - 34 * sizeof(MCRegisterClass),
1904 .SuperClassesSize: 17
1905 },
1906 {
1907 offsetof(ARMRegisterClassStorage, Regs[456]) - 35 * sizeof(MCRegisterClass),
1908 offsetof(ARMRegisterClassStorage, BitSets[253]) - 35 * sizeof(MCRegisterClass),
1909 .NameIdx: 2318,
1910 .RegSizeInBits: 32,
1911 .RegsSize: 4,
1912 .RegSetBegin: 75, /* MinRegVal */
1913 .RegSetSize: 7, /* RegSetSize */
1914 .ID: ARM::tGPR_and_tGPROddRegClassID,
1915 .CopyCost: 1, /* CopyCost */
1916 .Allocatable: true, /* Allocatable */
1917 .BaseClass: false,
1918 offsetof(ARMRegisterClassStorage, SubClassMasks[880]) - 35 * sizeof(MCRegisterClass),
1919 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[12]) - 35 * sizeof(MCRegisterClass),
1920 .LaneMask: LaneBitmask(0x0000000000000001),
1921 .AllocationPriority: 0,
1922 .GlobalPriority: false,
1923 .TSFlags: 0x00, /* TSFlags */
1924 .SpillStackID: 0, /* SpillStackID */
1925 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1926 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1927 offsetof(ARMRegisterClassStorage, SuperClasses[197]) - 35 * sizeof(MCRegisterClass),
1928 .SuperClassesSize: 16
1929 },
1930 {
1931 offsetof(ARMRegisterClassStorage, Regs[460]) - 36 * sizeof(MCRegisterClass),
1932 offsetof(ARMRegisterClassStorage, BitSets[254]) - 36 * sizeof(MCRegisterClass),
1933 .NameIdx: 175,
1934 .RegSizeInBits: 32,
1935 .RegsSize: 4,
1936 .RegSetBegin: 74, /* MinRegVal */
1937 .RegSetSize: 4, /* RegSetSize */
1938 .ID: ARM::tcGPRnotr12RegClassID,
1939 .CopyCost: 1, /* CopyCost */
1940 .Allocatable: true, /* Allocatable */
1941 .BaseClass: false,
1942 offsetof(ARMRegisterClassStorage, SubClassMasks[890]) - 36 * sizeof(MCRegisterClass),
1943 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[11]) - 36 * sizeof(MCRegisterClass),
1944 .LaneMask: LaneBitmask(0x0000000000000001),
1945 .AllocationPriority: 0,
1946 .GlobalPriority: false,
1947 .TSFlags: 0x00, /* TSFlags */
1948 .SpillStackID: 0, /* SpillStackID */
1949 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1950 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1951 offsetof(ARMRegisterClassStorage, SuperClasses[213]) - 36 * sizeof(MCRegisterClass),
1952 .SuperClassesSize: 16
1953 },
1954 {
1955 offsetof(ARMRegisterClassStorage, Regs[464]) - 37 * sizeof(MCRegisterClass),
1956 offsetof(ARMRegisterClassStorage, BitSets[255]) - 37 * sizeof(MCRegisterClass),
1957 .NameIdx: 1476,
1958 .RegSizeInBits: 32,
1959 .RegsSize: 3,
1960 .RegSetBegin: 74, /* MinRegVal */
1961 .RegSetSize: 13, /* RegSetSize */
1962 .ID: ARM::tGPREven_and_tcGPRRegClassID,
1963 .CopyCost: 1, /* CopyCost */
1964 .Allocatable: true, /* Allocatable */
1965 .BaseClass: false,
1966 offsetof(ARMRegisterClassStorage, SubClassMasks[905]) - 37 * sizeof(MCRegisterClass),
1967 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 37 * sizeof(MCRegisterClass),
1968 .LaneMask: LaneBitmask(0x0000000000000001),
1969 .AllocationPriority: 0,
1970 .GlobalPriority: false,
1971 .TSFlags: 0x00, /* TSFlags */
1972 .SpillStackID: 0, /* SpillStackID */
1973 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1974 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1975 offsetof(ARMRegisterClassStorage, SuperClasses[229]) - 37 * sizeof(MCRegisterClass),
1976 .SuperClassesSize: 11
1977 },
1978 {
1979 offsetof(ARMRegisterClassStorage, Regs[467]) - 38 * sizeof(MCRegisterClass),
1980 offsetof(ARMRegisterClassStorage, BitSets[257]) - 38 * sizeof(MCRegisterClass),
1981 .NameIdx: 2197,
1982 .RegSizeInBits: 32,
1983 .RegsSize: 2,
1984 .RegSetBegin: 6, /* MinRegVal */
1985 .RegSetSize: 3, /* RegSetSize */
1986 .ID: ARM::FP_STATUS_REGSRegClassID,
1987 .CopyCost: 255, /* CopyCost */
1988 .Allocatable: false, /* Allocatable */
1989 .BaseClass: false,
1990 offsetof(ARMRegisterClassStorage, SubClassMasks[915]) - 38 * sizeof(MCRegisterClass),
1991 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 38 * sizeof(MCRegisterClass),
1992 .LaneMask: LaneBitmask(0x0000000000000001),
1993 .AllocationPriority: 0,
1994 .GlobalPriority: false,
1995 .TSFlags: 0x00, /* TSFlags */
1996 .SpillStackID: 0, /* SpillStackID */
1997 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1998 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1999 offsetof(ARMRegisterClassStorage, SuperClasses[240]) - 38 * sizeof(MCRegisterClass),
2000 .SuperClassesSize: 0
2001 },
2002 {
2003 offsetof(ARMRegisterClassStorage, Regs[469]) - 39 * sizeof(MCRegisterClass),
2004 offsetof(ARMRegisterClassStorage, BitSets[258]) - 39 * sizeof(MCRegisterClass),
2005 .NameIdx: 2379,
2006 .RegSizeInBits: 32,
2007 .RegsSize: 2,
2008 .RegSetBegin: 82, /* MinRegVal */
2009 .RegSetSize: 3, /* RegSetSize */
2010 .ID: ARM::hGPR_and_GPRnoip_and_tGPREvenRegClassID,
2011 .CopyCost: 1, /* CopyCost */
2012 .Allocatable: true, /* Allocatable */
2013 .BaseClass: false,
2014 offsetof(ARMRegisterClassStorage, SubClassMasks[920]) - 39 * sizeof(MCRegisterClass),
2015 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 39 * sizeof(MCRegisterClass),
2016 .LaneMask: LaneBitmask(0x0000000000000001),
2017 .AllocationPriority: 0,
2018 .GlobalPriority: false,
2019 .TSFlags: 0x00, /* TSFlags */
2020 .SpillStackID: 0, /* SpillStackID */
2021 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2022 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2023 offsetof(ARMRegisterClassStorage, SuperClasses[240]) - 39 * sizeof(MCRegisterClass),
2024 .SuperClassesSize: 24
2025 },
2026 {
2027 offsetof(ARMRegisterClassStorage, Regs[471]) - 40 * sizeof(MCRegisterClass),
2028 offsetof(ARMRegisterClassStorage, BitSets[259]) - 40 * sizeof(MCRegisterClass),
2029 .NameIdx: 2301,
2030 .RegSizeInBits: 32,
2031 .RegsSize: 2,
2032 .RegSetBegin: 83, /* MinRegVal */
2033 .RegSetSize: 3, /* RegSetSize */
2034 .ID: ARM::hGPR_and_tGPROddRegClassID,
2035 .CopyCost: 1, /* CopyCost */
2036 .Allocatable: true, /* Allocatable */
2037 .BaseClass: false,
2038 offsetof(ARMRegisterClassStorage, SubClassMasks[930]) - 40 * sizeof(MCRegisterClass),
2039 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[12]) - 40 * sizeof(MCRegisterClass),
2040 .LaneMask: LaneBitmask(0x0000000000000001),
2041 .AllocationPriority: 0,
2042 .GlobalPriority: false,
2043 .TSFlags: 0x00, /* TSFlags */
2044 .SpillStackID: 0, /* SpillStackID */
2045 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2046 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2047 offsetof(ARMRegisterClassStorage, SuperClasses[264]) - 40 * sizeof(MCRegisterClass),
2048 .SuperClassesSize: 22
2049 },
2050 {
2051 offsetof(ARMRegisterClassStorage, Regs[473]) - 41 * sizeof(MCRegisterClass),
2052 offsetof(ARMRegisterClassStorage, BitSets[260]) - 41 * sizeof(MCRegisterClass),
2053 .NameIdx: 162,
2054 .RegSizeInBits: 32,
2055 .RegsSize: 2,
2056 .RegSetBegin: 74, /* MinRegVal */
2057 .RegSetSize: 3, /* RegSetSize */
2058 .ID: ARM::tGPREven_and_tcGPRnotr12RegClassID,
2059 .CopyCost: 1, /* CopyCost */
2060 .Allocatable: true, /* Allocatable */
2061 .BaseClass: false,
2062 offsetof(ARMRegisterClassStorage, SubClassMasks[940]) - 41 * sizeof(MCRegisterClass),
2063 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 41 * sizeof(MCRegisterClass),
2064 .LaneMask: LaneBitmask(0x0000000000000001),
2065 .AllocationPriority: 0,
2066 .GlobalPriority: false,
2067 .TSFlags: 0x00, /* TSFlags */
2068 .SpillStackID: 0, /* SpillStackID */
2069 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2070 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2071 offsetof(ARMRegisterClassStorage, SuperClasses[286]) - 41 * sizeof(MCRegisterClass),
2072 .SuperClassesSize: 21
2073 },
2074 {
2075 offsetof(ARMRegisterClassStorage, Regs[475]) - 42 * sizeof(MCRegisterClass),
2076 offsetof(ARMRegisterClassStorage, BitSets[261]) - 42 * sizeof(MCRegisterClass),
2077 .NameIdx: 1458,
2078 .RegSizeInBits: 32,
2079 .RegsSize: 2,
2080 .RegSetBegin: 75, /* MinRegVal */
2081 .RegSetSize: 3, /* RegSetSize */
2082 .ID: ARM::tGPROdd_and_tcGPRRegClassID,
2083 .CopyCost: 1, /* CopyCost */
2084 .Allocatable: true, /* Allocatable */
2085 .BaseClass: false,
2086 offsetof(ARMRegisterClassStorage, SubClassMasks[950]) - 42 * sizeof(MCRegisterClass),
2087 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[12]) - 42 * sizeof(MCRegisterClass),
2088 .LaneMask: LaneBitmask(0x0000000000000001),
2089 .AllocationPriority: 0,
2090 .GlobalPriority: false,
2091 .TSFlags: 0x00, /* TSFlags */
2092 .SpillStackID: 0, /* SpillStackID */
2093 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2094 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2095 offsetof(ARMRegisterClassStorage, SuperClasses[307]) - 42 * sizeof(MCRegisterClass),
2096 .SuperClassesSize: 19
2097 },
2098 {
2099 offsetof(ARMRegisterClassStorage, Regs[477]) - 43 * sizeof(MCRegisterClass),
2100 offsetof(ARMRegisterClassStorage, BitSets[262]) - 43 * sizeof(MCRegisterClass),
2101 .NameIdx: 1435,
2102 .RegSizeInBits: 32,
2103 .RegsSize: 1,
2104 .RegSetBegin: 3, /* MinRegVal */
2105 .RegSetSize: 1, /* RegSetSize */
2106 .ID: ARM::CCRRegClassID,
2107 .CopyCost: 255, /* CopyCost */
2108 .Allocatable: false, /* Allocatable */
2109 .BaseClass: false,
2110 offsetof(ARMRegisterClassStorage, SubClassMasks[960]) - 43 * sizeof(MCRegisterClass),
2111 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 43 * sizeof(MCRegisterClass),
2112 .LaneMask: LaneBitmask(0x0000000000000001),
2113 .AllocationPriority: 0,
2114 .GlobalPriority: false,
2115 .TSFlags: 0x00, /* TSFlags */
2116 .SpillStackID: 0, /* SpillStackID */
2117 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2118 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2119 offsetof(ARMRegisterClassStorage, SuperClasses[326]) - 43 * sizeof(MCRegisterClass),
2120 .SuperClassesSize: 0
2121 },
2122 {
2123 offsetof(ARMRegisterClassStorage, Regs[478]) - 44 * sizeof(MCRegisterClass),
2124 offsetof(ARMRegisterClassStorage, BitSets[263]) - 44 * sizeof(MCRegisterClass),
2125 .NameIdx: 2561,
2126 .RegSizeInBits: 32,
2127 .RegsSize: 1,
2128 .RegSetBegin: 4, /* MinRegVal */
2129 .RegSetSize: 1, /* RegSetSize */
2130 .ID: ARM::FPCXTRegsRegClassID,
2131 .CopyCost: 1, /* CopyCost */
2132 .Allocatable: true, /* Allocatable */
2133 .BaseClass: false,
2134 offsetof(ARMRegisterClassStorage, SubClassMasks[965]) - 44 * sizeof(MCRegisterClass),
2135 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 44 * sizeof(MCRegisterClass),
2136 .LaneMask: LaneBitmask(0x0000000000000001),
2137 .AllocationPriority: 0,
2138 .GlobalPriority: false,
2139 .TSFlags: 0x00, /* TSFlags */
2140 .SpillStackID: 0, /* SpillStackID */
2141 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2142 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2143 offsetof(ARMRegisterClassStorage, SuperClasses[326]) - 44 * sizeof(MCRegisterClass),
2144 .SuperClassesSize: 0
2145 },
2146 {
2147 offsetof(ARMRegisterClassStorage, Regs[479]) - 45 * sizeof(MCRegisterClass),
2148 offsetof(ARMRegisterClassStorage, BitSets[264]) - 45 * sizeof(MCRegisterClass),
2149 .NameIdx: 2555,
2150 .RegSizeInBits: 32,
2151 .RegsSize: 1,
2152 .RegSetBegin: 14, /* MinRegVal */
2153 .RegSetSize: 1, /* RegSetSize */
2154 .ID: ARM::GPRlrRegClassID,
2155 .CopyCost: 1, /* CopyCost */
2156 .Allocatable: true, /* Allocatable */
2157 .BaseClass: false,
2158 offsetof(ARMRegisterClassStorage, SubClassMasks[970]) - 45 * sizeof(MCRegisterClass),
2159 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 45 * sizeof(MCRegisterClass),
2160 .LaneMask: LaneBitmask(0x0000000000000001),
2161 .AllocationPriority: 0,
2162 .GlobalPriority: false,
2163 .TSFlags: 0x00, /* TSFlags */
2164 .SpillStackID: 0, /* SpillStackID */
2165 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2166 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2167 offsetof(ARMRegisterClassStorage, SuperClasses[326]) - 45 * sizeof(MCRegisterClass),
2168 .SuperClassesSize: 15
2169 },
2170 {
2171 offsetof(ARMRegisterClassStorage, Regs[480]) - 46 * sizeof(MCRegisterClass),
2172 offsetof(ARMRegisterClassStorage, BitSets[265]) - 46 * sizeof(MCRegisterClass),
2173 .NameIdx: 2440,
2174 .RegSizeInBits: 32,
2175 .RegsSize: 1,
2176 .RegSetBegin: 17, /* MinRegVal */
2177 .RegSetSize: 1, /* RegSetSize */
2178 .ID: ARM::GPRspRegClassID,
2179 .CopyCost: 1, /* CopyCost */
2180 .Allocatable: true, /* Allocatable */
2181 .BaseClass: false,
2182 offsetof(ARMRegisterClassStorage, SubClassMasks[975]) - 46 * sizeof(MCRegisterClass),
2183 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[12]) - 46 * sizeof(MCRegisterClass),
2184 .LaneMask: LaneBitmask(0x0000000000000001),
2185 .AllocationPriority: 0,
2186 .GlobalPriority: false,
2187 .TSFlags: 0x00, /* TSFlags */
2188 .SpillStackID: 0, /* SpillStackID */
2189 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2190 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2191 offsetof(ARMRegisterClassStorage, SuperClasses[341]) - 46 * sizeof(MCRegisterClass),
2192 .SuperClassesSize: 10
2193 },
2194 {
2195 offsetof(ARMRegisterClassStorage, Regs[481]) - 47 * sizeof(MCRegisterClass),
2196 offsetof(ARMRegisterClassStorage, BitSets[266]) - 47 * sizeof(MCRegisterClass),
2197 .NameIdx: 1434,
2198 .RegSizeInBits: 32,
2199 .RegsSize: 1,
2200 .RegSetBegin: 19, /* MinRegVal */
2201 .RegSetSize: 1, /* RegSetSize */
2202 .ID: ARM::VCCRRegClassID,
2203 .CopyCost: 1, /* CopyCost */
2204 .Allocatable: true, /* Allocatable */
2205 .BaseClass: false,
2206 offsetof(ARMRegisterClassStorage, SubClassMasks[985]) - 47 * sizeof(MCRegisterClass),
2207 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 47 * sizeof(MCRegisterClass),
2208 .LaneMask: LaneBitmask(0x0000000000000001),
2209 .AllocationPriority: 0,
2210 .GlobalPriority: false,
2211 .TSFlags: 0x00, /* TSFlags */
2212 .SpillStackID: 0, /* SpillStackID */
2213 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2214 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2215 offsetof(ARMRegisterClassStorage, SuperClasses[351]) - 47 * sizeof(MCRegisterClass),
2216 .SuperClassesSize: 1
2217 },
2218 {
2219 offsetof(ARMRegisterClassStorage, Regs[482]) - 48 * sizeof(MCRegisterClass),
2220 offsetof(ARMRegisterClassStorage, BitSets[267]) - 48 * sizeof(MCRegisterClass),
2221 .NameIdx: 2212,
2222 .RegSizeInBits: 32,
2223 .RegsSize: 1,
2224 .RegSetBegin: 9, /* MinRegVal */
2225 .RegSetSize: 1, /* RegSetSize */
2226 .ID: ARM::cl_FPSCR_NZCVRegClassID,
2227 .CopyCost: 255, /* CopyCost */
2228 .Allocatable: true, /* Allocatable */
2229 .BaseClass: false,
2230 offsetof(ARMRegisterClassStorage, SubClassMasks[990]) - 48 * sizeof(MCRegisterClass),
2231 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 48 * sizeof(MCRegisterClass),
2232 .LaneMask: LaneBitmask(0x0000000000000001),
2233 .AllocationPriority: 0,
2234 .GlobalPriority: false,
2235 .TSFlags: 0x00, /* TSFlags */
2236 .SpillStackID: 0, /* SpillStackID */
2237 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2238 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2239 offsetof(ARMRegisterClassStorage, SuperClasses[352]) - 48 * sizeof(MCRegisterClass),
2240 .SuperClassesSize: 0
2241 },
2242 {
2243 offsetof(ARMRegisterClassStorage, Regs[483]) - 49 * sizeof(MCRegisterClass),
2244 offsetof(ARMRegisterClassStorage, BitSets[268]) - 49 * sizeof(MCRegisterClass),
2245 .NameIdx: 2255,
2246 .RegSizeInBits: 32,
2247 .RegsSize: 1,
2248 .RegSetBegin: 15, /* MinRegVal */
2249 .RegSetSize: 1, /* RegSetSize */
2250 .ID: ARM::hGPR_and_tGPRwithpcRegClassID,
2251 .CopyCost: 1, /* CopyCost */
2252 .Allocatable: true, /* Allocatable */
2253 .BaseClass: false,
2254 offsetof(ARMRegisterClassStorage, SubClassMasks[995]) - 49 * sizeof(MCRegisterClass),
2255 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 49 * sizeof(MCRegisterClass),
2256 .LaneMask: LaneBitmask(0x0000000000000001),
2257 .AllocationPriority: 0,
2258 .GlobalPriority: false,
2259 .TSFlags: 0x00, /* TSFlags */
2260 .SpillStackID: 0, /* SpillStackID */
2261 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2262 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2263 offsetof(ARMRegisterClassStorage, SuperClasses[352]) - 49 * sizeof(MCRegisterClass),
2264 .SuperClassesSize: 9
2265 },
2266 {
2267 offsetof(ARMRegisterClassStorage, Regs[484]) - 50 * sizeof(MCRegisterClass),
2268 offsetof(ARMRegisterClassStorage, BitSets[269]) - 50 * sizeof(MCRegisterClass),
2269 .NameIdx: 1443,
2270 .RegSizeInBits: 32,
2271 .RegsSize: 1,
2272 .RegSetBegin: 86, /* MinRegVal */
2273 .RegSetSize: 1, /* RegSetSize */
2274 .ID: ARM::hGPR_and_tcGPRRegClassID,
2275 .CopyCost: 1, /* CopyCost */
2276 .Allocatable: true, /* Allocatable */
2277 .BaseClass: false,
2278 offsetof(ARMRegisterClassStorage, SubClassMasks[1000]) - 50 * sizeof(MCRegisterClass),
2279 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[9]) - 50 * sizeof(MCRegisterClass),
2280 .LaneMask: LaneBitmask(0x0000000000000001),
2281 .AllocationPriority: 0,
2282 .GlobalPriority: false,
2283 .TSFlags: 0x00, /* TSFlags */
2284 .SpillStackID: 0, /* SpillStackID */
2285 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2286 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2287 offsetof(ARMRegisterClassStorage, SuperClasses[361]) - 50 * sizeof(MCRegisterClass),
2288 .SuperClassesSize: 17
2289 },
2290 {
2291 offsetof(ARMRegisterClassStorage, Regs[485]) - 51 * sizeof(MCRegisterClass),
2292 offsetof(ARMRegisterClassStorage, BitSets[270]) - 51 * sizeof(MCRegisterClass),
2293 .NameIdx: 1439,
2294 .RegSizeInBits: 64,
2295 .RegsSize: 32,
2296 .RegSetBegin: 21, /* MinRegVal */
2297 .RegSetSize: 32, /* RegSetSize */
2298 .ID: ARM::DPRRegClassID,
2299 .CopyCost: 1, /* CopyCost */
2300 .Allocatable: true, /* Allocatable */
2301 .BaseClass: false,
2302 offsetof(ARMRegisterClassStorage, SubClassMasks[1010]) - 51 * sizeof(MCRegisterClass),
2303 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[0]) - 51 * sizeof(MCRegisterClass),
2304 .LaneMask: LaneBitmask(0x000000000000000C),
2305 .AllocationPriority: 0,
2306 .GlobalPriority: false,
2307 .TSFlags: 0x00, /* TSFlags */
2308 .SpillStackID: 0, /* SpillStackID */
2309 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2310 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2311 offsetof(ARMRegisterClassStorage, SuperClasses[378]) - 51 * sizeof(MCRegisterClass),
2312 .SuperClassesSize: 1
2313 },
2314 {
2315 offsetof(ARMRegisterClassStorage, Regs[517]) - 52 * sizeof(MCRegisterClass),
2316 offsetof(ARMRegisterClassStorage, BitSets[274]) - 52 * sizeof(MCRegisterClass),
2317 .NameIdx: 222,
2318 .RegSizeInBits: 64,
2319 .RegsSize: 16,
2320 .RegSetBegin: 21, /* MinRegVal */
2321 .RegSetSize: 16, /* RegSetSize */
2322 .ID: ARM::DPR_VFP2RegClassID,
2323 .CopyCost: 1, /* CopyCost */
2324 .Allocatable: true, /* Allocatable */
2325 .BaseClass: false,
2326 offsetof(ARMRegisterClassStorage, SubClassMasks[1055]) - 52 * sizeof(MCRegisterClass),
2327 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[0]) - 52 * sizeof(MCRegisterClass),
2328 .LaneMask: LaneBitmask(0x000000000000000C),
2329 .AllocationPriority: 0,
2330 .GlobalPriority: false,
2331 .TSFlags: 0x00, /* TSFlags */
2332 .SpillStackID: 0, /* SpillStackID */
2333 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2334 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2335 offsetof(ARMRegisterClassStorage, SuperClasses[379]) - 52 * sizeof(MCRegisterClass),
2336 .SuperClassesSize: 3
2337 },
2338 {
2339 offsetof(ARMRegisterClassStorage, Regs[533]) - 53 * sizeof(MCRegisterClass),
2340 offsetof(ARMRegisterClassStorage, BitSets[276]) - 53 * sizeof(MCRegisterClass),
2341 .NameIdx: 460,
2342 .RegSizeInBits: 64,
2343 .RegsSize: 8,
2344 .RegSetBegin: 21, /* MinRegVal */
2345 .RegSetSize: 8, /* RegSetSize */
2346 .ID: ARM::DPR_8RegClassID,
2347 .CopyCost: 1, /* CopyCost */
2348 .Allocatable: true, /* Allocatable */
2349 .BaseClass: false,
2350 offsetof(ARMRegisterClassStorage, SubClassMasks[1100]) - 53 * sizeof(MCRegisterClass),
2351 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[0]) - 53 * sizeof(MCRegisterClass),
2352 .LaneMask: LaneBitmask(0x000000000000000C),
2353 .AllocationPriority: 0,
2354 .GlobalPriority: false,
2355 .TSFlags: 0x00, /* TSFlags */
2356 .SpillStackID: 0, /* SpillStackID */
2357 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2358 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2359 offsetof(ARMRegisterClassStorage, SuperClasses[382]) - 53 * sizeof(MCRegisterClass),
2360 .SuperClassesSize: 5
2361 },
2362 {
2363 offsetof(ARMRegisterClassStorage, Regs[541]) - 54 * sizeof(MCRegisterClass),
2364 offsetof(ARMRegisterClassStorage, BitSets[277]) - 54 * sizeof(MCRegisterClass),
2365 .NameIdx: 2547,
2366 .RegSizeInBits: 64,
2367 .RegsSize: 7,
2368 .RegSetBegin: 177, /* MinRegVal */
2369 .RegSetSize: 7, /* RegSetSize */
2370 .ID: ARM::GPRPairRegClassID,
2371 .CopyCost: 1, /* CopyCost */
2372 .Allocatable: true, /* Allocatable */
2373 .BaseClass: false,
2374 offsetof(ARMRegisterClassStorage, SubClassMasks[1145]) - 54 * sizeof(MCRegisterClass),
2375 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 54 * sizeof(MCRegisterClass),
2376 .LaneMask: LaneBitmask(0x0000000000000003),
2377 .AllocationPriority: 0,
2378 .GlobalPriority: false,
2379 .TSFlags: 0x00, /* TSFlags */
2380 .SpillStackID: 0, /* SpillStackID */
2381 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2382 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2383 offsetof(ARMRegisterClassStorage, SuperClasses[387]) - 54 * sizeof(MCRegisterClass),
2384 .SuperClassesSize: 0
2385 },
2386 {
2387 offsetof(ARMRegisterClassStorage, Regs[548]) - 55 * sizeof(MCRegisterClass),
2388 offsetof(ARMRegisterClassStorage, BitSets[278]) - 55 * sizeof(MCRegisterClass),
2389 .NameIdx: 2529,
2390 .RegSizeInBits: 64,
2391 .RegsSize: 6,
2392 .RegSetBegin: 177, /* MinRegVal */
2393 .RegSetSize: 6, /* RegSetSize */
2394 .ID: ARM::GPRPairnospRegClassID,
2395 .CopyCost: 1, /* CopyCost */
2396 .Allocatable: true, /* Allocatable */
2397 .BaseClass: false,
2398 offsetof(ARMRegisterClassStorage, SubClassMasks[1150]) - 55 * sizeof(MCRegisterClass),
2399 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 55 * sizeof(MCRegisterClass),
2400 .LaneMask: LaneBitmask(0x0000000000000003),
2401 .AllocationPriority: 0,
2402 .GlobalPriority: false,
2403 .TSFlags: 0x00, /* TSFlags */
2404 .SpillStackID: 0, /* SpillStackID */
2405 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2406 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2407 offsetof(ARMRegisterClassStorage, SuperClasses[387]) - 55 * sizeof(MCRegisterClass),
2408 .SuperClassesSize: 1
2409 },
2410 {
2411 offsetof(ARMRegisterClassStorage, Regs[554]) - 56 * sizeof(MCRegisterClass),
2412 offsetof(ARMRegisterClassStorage, BitSets[279]) - 56 * sizeof(MCRegisterClass),
2413 .NameIdx: 1689,
2414 .RegSizeInBits: 64,
2415 .RegsSize: 4,
2416 .RegSetBegin: 177, /* MinRegVal */
2417 .RegSetSize: 4, /* RegSetSize */
2418 .ID: ARM::GPRPair_with_gsub_0_in_tGPRRegClassID,
2419 .CopyCost: 1, /* CopyCost */
2420 .Allocatable: true, /* Allocatable */
2421 .BaseClass: false,
2422 offsetof(ARMRegisterClassStorage, SubClassMasks[1155]) - 56 * sizeof(MCRegisterClass),
2423 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 56 * sizeof(MCRegisterClass),
2424 .LaneMask: LaneBitmask(0x0000000000000003),
2425 .AllocationPriority: 0,
2426 .GlobalPriority: false,
2427 .TSFlags: 0x00, /* TSFlags */
2428 .SpillStackID: 0, /* SpillStackID */
2429 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2430 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2431 offsetof(ARMRegisterClassStorage, SuperClasses[388]) - 56 * sizeof(MCRegisterClass),
2432 .SuperClassesSize: 2
2433 },
2434 {
2435 offsetof(ARMRegisterClassStorage, Regs[558]) - 57 * sizeof(MCRegisterClass),
2436 offsetof(ARMRegisterClassStorage, BitSets[280]) - 57 * sizeof(MCRegisterClass),
2437 .NameIdx: 1656,
2438 .RegSizeInBits: 64,
2439 .RegsSize: 3,
2440 .RegSetBegin: 181, /* MinRegVal */
2441 .RegSetSize: 3, /* RegSetSize */
2442 .ID: ARM::GPRPair_with_gsub_0_in_hGPRRegClassID,
2443 .CopyCost: 1, /* CopyCost */
2444 .Allocatable: true, /* Allocatable */
2445 .BaseClass: false,
2446 offsetof(ARMRegisterClassStorage, SubClassMasks[1160]) - 57 * sizeof(MCRegisterClass),
2447 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 57 * sizeof(MCRegisterClass),
2448 .LaneMask: LaneBitmask(0x0000000000000003),
2449 .AllocationPriority: 0,
2450 .GlobalPriority: false,
2451 .TSFlags: 0x00, /* TSFlags */
2452 .SpillStackID: 0, /* SpillStackID */
2453 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2454 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2455 offsetof(ARMRegisterClassStorage, SuperClasses[390]) - 57 * sizeof(MCRegisterClass),
2456 .SuperClassesSize: 1
2457 },
2458 {
2459 offsetof(ARMRegisterClassStorage, Regs[561]) - 58 * sizeof(MCRegisterClass),
2460 offsetof(ARMRegisterClassStorage, BitSets[281]) - 58 * sizeof(MCRegisterClass),
2461 .NameIdx: 1495,
2462 .RegSizeInBits: 64,
2463 .RegsSize: 3,
2464 .RegSetBegin: 177, /* MinRegVal */
2465 .RegSetSize: 7, /* RegSetSize */
2466 .ID: ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID,
2467 .CopyCost: 1, /* CopyCost */
2468 .Allocatable: true, /* Allocatable */
2469 .BaseClass: false,
2470 offsetof(ARMRegisterClassStorage, SubClassMasks[1165]) - 58 * sizeof(MCRegisterClass),
2471 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 58 * sizeof(MCRegisterClass),
2472 .LaneMask: LaneBitmask(0x0000000000000003),
2473 .AllocationPriority: 0,
2474 .GlobalPriority: false,
2475 .TSFlags: 0x00, /* TSFlags */
2476 .SpillStackID: 0, /* SpillStackID */
2477 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2478 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2479 offsetof(ARMRegisterClassStorage, SuperClasses[391]) - 58 * sizeof(MCRegisterClass),
2480 .SuperClassesSize: 1
2481 },
2482 {
2483 offsetof(ARMRegisterClassStorage, Regs[564]) - 59 * sizeof(MCRegisterClass),
2484 offsetof(ARMRegisterClassStorage, BitSets[282]) - 59 * sizeof(MCRegisterClass),
2485 .NameIdx: 187,
2486 .RegSizeInBits: 64,
2487 .RegsSize: 2,
2488 .RegSetBegin: 177, /* MinRegVal */
2489 .RegSetSize: 2, /* RegSetSize */
2490 .ID: ARM::GPRPair_with_gsub_0_in_tcGPRnotr12RegClassID,
2491 .CopyCost: 1, /* CopyCost */
2492 .Allocatable: true, /* Allocatable */
2493 .BaseClass: false,
2494 offsetof(ARMRegisterClassStorage, SubClassMasks[1170]) - 59 * sizeof(MCRegisterClass),
2495 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 59 * sizeof(MCRegisterClass),
2496 .LaneMask: LaneBitmask(0x0000000000000003),
2497 .AllocationPriority: 0,
2498 .GlobalPriority: false,
2499 .TSFlags: 0x00, /* TSFlags */
2500 .SpillStackID: 0, /* SpillStackID */
2501 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2502 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2503 offsetof(ARMRegisterClassStorage, SuperClasses[392]) - 59 * sizeof(MCRegisterClass),
2504 .SuperClassesSize: 4
2505 },
2506 {
2507 offsetof(ARMRegisterClassStorage, Regs[566]) - 60 * sizeof(MCRegisterClass),
2508 offsetof(ARMRegisterClassStorage, BitSets[283]) - 60 * sizeof(MCRegisterClass),
2509 .NameIdx: 1640,
2510 .RegSizeInBits: 64,
2511 .RegsSize: 2,
2512 .RegSetBegin: 181, /* MinRegVal */
2513 .RegSetSize: 2, /* RegSetSize */
2514 .ID: ARM::GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID,
2515 .CopyCost: 1, /* CopyCost */
2516 .Allocatable: true, /* Allocatable */
2517 .BaseClass: false,
2518 offsetof(ARMRegisterClassStorage, SubClassMasks[1175]) - 60 * sizeof(MCRegisterClass),
2519 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 60 * sizeof(MCRegisterClass),
2520 .LaneMask: LaneBitmask(0x0000000000000003),
2521 .AllocationPriority: 0,
2522 .GlobalPriority: false,
2523 .TSFlags: 0x00, /* TSFlags */
2524 .SpillStackID: 0, /* SpillStackID */
2525 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2526 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2527 offsetof(ARMRegisterClassStorage, SuperClasses[396]) - 60 * sizeof(MCRegisterClass),
2528 .SuperClassesSize: 3
2529 },
2530 {
2531 offsetof(ARMRegisterClassStorage, Regs[568]) - 61 * sizeof(MCRegisterClass),
2532 offsetof(ARMRegisterClassStorage, BitSets[284]) - 61 * sizeof(MCRegisterClass),
2533 .NameIdx: 2417,
2534 .RegSizeInBits: 64,
2535 .RegsSize: 1,
2536 .RegSetBegin: 183, /* MinRegVal */
2537 .RegSetSize: 1, /* RegSetSize */
2538 .ID: ARM::GPRPair_with_gsub_1_in_GPRspRegClassID,
2539 .CopyCost: 1, /* CopyCost */
2540 .Allocatable: true, /* Allocatable */
2541 .BaseClass: false,
2542 offsetof(ARMRegisterClassStorage, SubClassMasks[1180]) - 61 * sizeof(MCRegisterClass),
2543 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 61 * sizeof(MCRegisterClass),
2544 .LaneMask: LaneBitmask(0x0000000000000003),
2545 .AllocationPriority: 0,
2546 .GlobalPriority: false,
2547 .TSFlags: 0x00, /* TSFlags */
2548 .SpillStackID: 0, /* SpillStackID */
2549 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2550 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2551 offsetof(ARMRegisterClassStorage, SuperClasses[399]) - 61 * sizeof(MCRegisterClass),
2552 .SuperClassesSize: 3
2553 },
2554 {
2555 offsetof(ARMRegisterClassStorage, Regs[569]) - 62 * sizeof(MCRegisterClass),
2556 offsetof(ARMRegisterClassStorage, BitSets[285]) - 62 * sizeof(MCRegisterClass),
2557 .NameIdx: 2246,
2558 .RegSizeInBits: 128,
2559 .RegsSize: 30,
2560 .RegSetBegin: 119, /* MinRegVal */
2561 .RegSetSize: 30, /* RegSetSize */
2562 .ID: ARM::DPairSpcRegClassID,
2563 .CopyCost: 1, /* CopyCost */
2564 .Allocatable: true, /* Allocatable */
2565 .BaseClass: false,
2566 offsetof(ARMRegisterClassStorage, SubClassMasks[1185]) - 62 * sizeof(MCRegisterClass),
2567 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[58]) - 62 * sizeof(MCRegisterClass),
2568 .LaneMask: LaneBitmask(0x00000000000000CC),
2569 .AllocationPriority: 0,
2570 .GlobalPriority: false,
2571 .TSFlags: 0x00, /* TSFlags */
2572 .SpillStackID: 0, /* SpillStackID */
2573 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2574 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2575 offsetof(ARMRegisterClassStorage, SuperClasses[402]) - 62 * sizeof(MCRegisterClass),
2576 .SuperClassesSize: 0
2577 },
2578 {
2579 offsetof(ARMRegisterClassStorage, Regs[599]) - 63 * sizeof(MCRegisterClass),
2580 offsetof(ARMRegisterClassStorage, BitSets[289]) - 63 * sizeof(MCRegisterClass),
2581 .NameIdx: 85,
2582 .RegSizeInBits: 128,
2583 .RegsSize: 16,
2584 .RegSetBegin: 119, /* MinRegVal */
2585 .RegSetSize: 16, /* RegSetSize */
2586 .ID: ARM::DPairSpc_with_ssub_0RegClassID,
2587 .CopyCost: 1, /* CopyCost */
2588 .Allocatable: true, /* Allocatable */
2589 .BaseClass: false,
2590 offsetof(ARMRegisterClassStorage, SubClassMasks[1215]) - 63 * sizeof(MCRegisterClass),
2591 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[58]) - 63 * sizeof(MCRegisterClass),
2592 .LaneMask: LaneBitmask(0x00000000000000CC),
2593 .AllocationPriority: 0,
2594 .GlobalPriority: false,
2595 .TSFlags: 0x00, /* TSFlags */
2596 .SpillStackID: 0, /* SpillStackID */
2597 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2598 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2599 offsetof(ARMRegisterClassStorage, SuperClasses[402]) - 63 * sizeof(MCRegisterClass),
2600 .SuperClassesSize: 1
2601 },
2602 {
2603 offsetof(ARMRegisterClassStorage, Regs[615]) - 64 * sizeof(MCRegisterClass),
2604 offsetof(ARMRegisterClassStorage, BitSets[291]) - 64 * sizeof(MCRegisterClass),
2605 .NameIdx: 359,
2606 .RegSizeInBits: 128,
2607 .RegsSize: 14,
2608 .RegSetBegin: 119, /* MinRegVal */
2609 .RegSetSize: 14, /* RegSetSize */
2610 .ID: ARM::DPairSpc_with_ssub_4RegClassID,
2611 .CopyCost: 1, /* CopyCost */
2612 .Allocatable: true, /* Allocatable */
2613 .BaseClass: false,
2614 offsetof(ARMRegisterClassStorage, SubClassMasks[1245]) - 64 * sizeof(MCRegisterClass),
2615 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[58]) - 64 * sizeof(MCRegisterClass),
2616 .LaneMask: LaneBitmask(0x00000000000000CC),
2617 .AllocationPriority: 0,
2618 .GlobalPriority: false,
2619 .TSFlags: 0x00, /* TSFlags */
2620 .SpillStackID: 0, /* SpillStackID */
2621 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2622 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2623 offsetof(ARMRegisterClassStorage, SuperClasses[403]) - 64 * sizeof(MCRegisterClass),
2624 .SuperClassesSize: 2
2625 },
2626 {
2627 offsetof(ARMRegisterClassStorage, Regs[629]) - 65 * sizeof(MCRegisterClass),
2628 offsetof(ARMRegisterClassStorage, BitSets[293]) - 65 * sizeof(MCRegisterClass),
2629 .NameIdx: 498,
2630 .RegSizeInBits: 128,
2631 .RegsSize: 8,
2632 .RegSetBegin: 119, /* MinRegVal */
2633 .RegSetSize: 8, /* RegSetSize */
2634 .ID: ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID,
2635 .CopyCost: 1, /* CopyCost */
2636 .Allocatable: true, /* Allocatable */
2637 .BaseClass: false,
2638 offsetof(ARMRegisterClassStorage, SubClassMasks[1275]) - 65 * sizeof(MCRegisterClass),
2639 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[58]) - 65 * sizeof(MCRegisterClass),
2640 .LaneMask: LaneBitmask(0x00000000000000CC),
2641 .AllocationPriority: 0,
2642 .GlobalPriority: false,
2643 .TSFlags: 0x00, /* TSFlags */
2644 .SpillStackID: 0, /* SpillStackID */
2645 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2646 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2647 offsetof(ARMRegisterClassStorage, SuperClasses[405]) - 65 * sizeof(MCRegisterClass),
2648 .SuperClassesSize: 3
2649 },
2650 {
2651 offsetof(ARMRegisterClassStorage, Regs[637]) - 66 * sizeof(MCRegisterClass),
2652 offsetof(ARMRegisterClassStorage, BitSets[294]) - 66 * sizeof(MCRegisterClass),
2653 .NameIdx: 858,
2654 .RegSizeInBits: 128,
2655 .RegsSize: 6,
2656 .RegSetBegin: 119, /* MinRegVal */
2657 .RegSetSize: 6, /* RegSetSize */
2658 .ID: ARM::DPairSpc_with_dsub_2_in_DPR_8RegClassID,
2659 .CopyCost: 1, /* CopyCost */
2660 .Allocatable: true, /* Allocatable */
2661 .BaseClass: false,
2662 offsetof(ARMRegisterClassStorage, SubClassMasks[1305]) - 66 * sizeof(MCRegisterClass),
2663 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[58]) - 66 * sizeof(MCRegisterClass),
2664 .LaneMask: LaneBitmask(0x00000000000000CC),
2665 .AllocationPriority: 0,
2666 .GlobalPriority: false,
2667 .TSFlags: 0x00, /* TSFlags */
2668 .SpillStackID: 0, /* SpillStackID */
2669 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2670 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2671 offsetof(ARMRegisterClassStorage, SuperClasses[408]) - 66 * sizeof(MCRegisterClass),
2672 .SuperClassesSize: 4
2673 },
2674 {
2675 offsetof(ARMRegisterClassStorage, Regs[643]) - 67 * sizeof(MCRegisterClass),
2676 offsetof(ARMRegisterClassStorage, BitSets[295]) - 67 * sizeof(MCRegisterClass),
2677 .NameIdx: 2541,
2678 .RegSizeInBits: 128,
2679 .RegsSize: 31,
2680 .RegSetBegin: 58, /* MinRegVal */
2681 .RegSetSize: 225, /* RegSetSize */
2682 .ID: ARM::DPairRegClassID,
2683 .CopyCost: 1, /* CopyCost */
2684 .Allocatable: true, /* Allocatable */
2685 .BaseClass: false,
2686 offsetof(ARMRegisterClassStorage, SubClassMasks[1335]) - 67 * sizeof(MCRegisterClass),
2687 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[76]) - 67 * sizeof(MCRegisterClass),
2688 .LaneMask: LaneBitmask(0x000000000000003C),
2689 .AllocationPriority: 0,
2690 .GlobalPriority: false,
2691 .TSFlags: 0x00, /* TSFlags */
2692 .SpillStackID: 0, /* SpillStackID */
2693 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2694 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2695 offsetof(ARMRegisterClassStorage, SuperClasses[412]) - 67 * sizeof(MCRegisterClass),
2696 .SuperClassesSize: 0
2697 },
2698 {
2699 offsetof(ARMRegisterClassStorage, Regs[674]) - 68 * sizeof(MCRegisterClass),
2700 offsetof(ARMRegisterClassStorage, BitSets[324]) - 68 * sizeof(MCRegisterClass),
2701 .NameIdx: 144,
2702 .RegSizeInBits: 128,
2703 .RegsSize: 16,
2704 .RegSetBegin: 58, /* MinRegVal */
2705 .RegSetSize: 218, /* RegSetSize */
2706 .ID: ARM::DPair_with_ssub_0RegClassID,
2707 .CopyCost: 1, /* CopyCost */
2708 .Allocatable: true, /* Allocatable */
2709 .BaseClass: false,
2710 offsetof(ARMRegisterClassStorage, SubClassMasks[1375]) - 68 * sizeof(MCRegisterClass),
2711 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[76]) - 68 * sizeof(MCRegisterClass),
2712 .LaneMask: LaneBitmask(0x000000000000003C),
2713 .AllocationPriority: 0,
2714 .GlobalPriority: false,
2715 .TSFlags: 0x00, /* TSFlags */
2716 .SpillStackID: 0, /* SpillStackID */
2717 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2718 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2719 offsetof(ARMRegisterClassStorage, SuperClasses[412]) - 68 * sizeof(MCRegisterClass),
2720 .SuperClassesSize: 1
2721 },
2722 {
2723 offsetof(ARMRegisterClassStorage, Regs[690]) - 69 * sizeof(MCRegisterClass),
2724 offsetof(ARMRegisterClassStorage, BitSets[352]) - 69 * sizeof(MCRegisterClass),
2725 .NameIdx: 1769,
2726 .RegSizeInBits: 128,
2727 .RegsSize: 16,
2728 .RegSetBegin: 58, /* MinRegVal */
2729 .RegSetSize: 16, /* RegSetSize */
2730 .ID: ARM::QPRRegClassID,
2731 .CopyCost: 1, /* CopyCost */
2732 .Allocatable: true, /* Allocatable */
2733 .BaseClass: false,
2734 offsetof(ARMRegisterClassStorage, SubClassMasks[1415]) - 69 * sizeof(MCRegisterClass),
2735 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[39]) - 69 * sizeof(MCRegisterClass),
2736 .LaneMask: LaneBitmask(0x000000000000003C),
2737 .AllocationPriority: 0,
2738 .GlobalPriority: false,
2739 .TSFlags: 0x00, /* TSFlags */
2740 .SpillStackID: 0, /* SpillStackID */
2741 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2742 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2743 offsetof(ARMRegisterClassStorage, SuperClasses[413]) - 69 * sizeof(MCRegisterClass),
2744 .SuperClassesSize: 1
2745 },
2746 {
2747 offsetof(ARMRegisterClassStorage, Regs[706]) - 70 * sizeof(MCRegisterClass),
2748 offsetof(ARMRegisterClassStorage, BitSets[354]) - 70 * sizeof(MCRegisterClass),
2749 .NameIdx: 278,
2750 .RegSizeInBits: 128,
2751 .RegsSize: 15,
2752 .RegSetBegin: 58, /* MinRegVal */
2753 .RegSetSize: 217, /* RegSetSize */
2754 .ID: ARM::DPair_with_ssub_2RegClassID,
2755 .CopyCost: 1, /* CopyCost */
2756 .Allocatable: true, /* Allocatable */
2757 .BaseClass: false,
2758 offsetof(ARMRegisterClassStorage, SubClassMasks[1445]) - 70 * sizeof(MCRegisterClass),
2759 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[76]) - 70 * sizeof(MCRegisterClass),
2760 .LaneMask: LaneBitmask(0x000000000000003C),
2761 .AllocationPriority: 0,
2762 .GlobalPriority: false,
2763 .TSFlags: 0x00, /* TSFlags */
2764 .SpillStackID: 0, /* SpillStackID */
2765 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2766 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2767 offsetof(ARMRegisterClassStorage, SuperClasses[414]) - 70 * sizeof(MCRegisterClass),
2768 .SuperClassesSize: 2
2769 },
2770 {
2771 offsetof(ARMRegisterClassStorage, Regs[721]) - 71 * sizeof(MCRegisterClass),
2772 offsetof(ARMRegisterClassStorage, BitSets[382]) - 71 * sizeof(MCRegisterClass),
2773 .NameIdx: 584,
2774 .RegSizeInBits: 128,
2775 .RegsSize: 8,
2776 .RegSetBegin: 58, /* MinRegVal */
2777 .RegSetSize: 214, /* RegSetSize */
2778 .ID: ARM::DPair_with_dsub_0_in_DPR_8RegClassID,
2779 .CopyCost: 1, /* CopyCost */
2780 .Allocatable: true, /* Allocatable */
2781 .BaseClass: false,
2782 offsetof(ARMRegisterClassStorage, SubClassMasks[1485]) - 71 * sizeof(MCRegisterClass),
2783 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[76]) - 71 * sizeof(MCRegisterClass),
2784 .LaneMask: LaneBitmask(0x000000000000003C),
2785 .AllocationPriority: 0,
2786 .GlobalPriority: false,
2787 .TSFlags: 0x00, /* TSFlags */
2788 .SpillStackID: 0, /* SpillStackID */
2789 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2790 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2791 offsetof(ARMRegisterClassStorage, SuperClasses[416]) - 71 * sizeof(MCRegisterClass),
2792 .SuperClassesSize: 3
2793 },
2794 {
2795 offsetof(ARMRegisterClassStorage, Regs[729]) - 72 * sizeof(MCRegisterClass),
2796 offsetof(ARMRegisterClassStorage, BitSets[409]) - 72 * sizeof(MCRegisterClass),
2797 .NameIdx: 1768,
2798 .RegSizeInBits: 128,
2799 .RegsSize: 8,
2800 .RegSetBegin: 58, /* MinRegVal */
2801 .RegSetSize: 8, /* RegSetSize */
2802 .ID: ARM::MQPRRegClassID,
2803 .CopyCost: 1, /* CopyCost */
2804 .Allocatable: true, /* Allocatable */
2805 .BaseClass: false,
2806 offsetof(ARMRegisterClassStorage, SubClassMasks[1525]) - 72 * sizeof(MCRegisterClass),
2807 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[39]) - 72 * sizeof(MCRegisterClass),
2808 .LaneMask: LaneBitmask(0x000000000000003C),
2809 .AllocationPriority: 0,
2810 .GlobalPriority: false,
2811 .TSFlags: 0x00, /* TSFlags */
2812 .SpillStackID: 0, /* SpillStackID */
2813 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2814 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2815 offsetof(ARMRegisterClassStorage, SuperClasses[419]) - 72 * sizeof(MCRegisterClass),
2816 .SuperClassesSize: 5
2817 },
2818 {
2819 offsetof(ARMRegisterClassStorage, Regs[737]) - 73 * sizeof(MCRegisterClass),
2820 offsetof(ARMRegisterClassStorage, BitSets[410]) - 73 * sizeof(MCRegisterClass),
2821 .NameIdx: 231,
2822 .RegSizeInBits: 128,
2823 .RegsSize: 8,
2824 .RegSetBegin: 58, /* MinRegVal */
2825 .RegSetSize: 8, /* RegSetSize */
2826 .ID: ARM::QPR_VFP2RegClassID,
2827 .CopyCost: 1, /* CopyCost */
2828 .Allocatable: true, /* Allocatable */
2829 .BaseClass: false,
2830 offsetof(ARMRegisterClassStorage, SubClassMasks[1555]) - 73 * sizeof(MCRegisterClass),
2831 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[39]) - 73 * sizeof(MCRegisterClass),
2832 .LaneMask: LaneBitmask(0x000000000000003C),
2833 .AllocationPriority: 0,
2834 .GlobalPriority: false,
2835 .TSFlags: 0x00, /* TSFlags */
2836 .SpillStackID: 0, /* SpillStackID */
2837 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2838 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2839 offsetof(ARMRegisterClassStorage, SuperClasses[424]) - 73 * sizeof(MCRegisterClass),
2840 .SuperClassesSize: 5
2841 },
2842 {
2843 offsetof(ARMRegisterClassStorage, Regs[745]) - 74 * sizeof(MCRegisterClass),
2844 offsetof(ARMRegisterClassStorage, BitSets[411]) - 74 * sizeof(MCRegisterClass),
2845 .NameIdx: 667,
2846 .RegSizeInBits: 128,
2847 .RegsSize: 7,
2848 .RegSetBegin: 58, /* MinRegVal */
2849 .RegSetSize: 213, /* RegSetSize */
2850 .ID: ARM::DPair_with_dsub_1_in_DPR_8RegClassID,
2851 .CopyCost: 1, /* CopyCost */
2852 .Allocatable: true, /* Allocatable */
2853 .BaseClass: false,
2854 offsetof(ARMRegisterClassStorage, SubClassMasks[1585]) - 74 * sizeof(MCRegisterClass),
2855 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[76]) - 74 * sizeof(MCRegisterClass),
2856 .LaneMask: LaneBitmask(0x000000000000003C),
2857 .AllocationPriority: 0,
2858 .GlobalPriority: false,
2859 .TSFlags: 0x00, /* TSFlags */
2860 .SpillStackID: 0, /* SpillStackID */
2861 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2862 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2863 offsetof(ARMRegisterClassStorage, SuperClasses[429]) - 74 * sizeof(MCRegisterClass),
2864 .SuperClassesSize: 4
2865 },
2866 {
2867 offsetof(ARMRegisterClassStorage, Regs[752]) - 75 * sizeof(MCRegisterClass),
2868 offsetof(ARMRegisterClassStorage, BitSets[438]) - 75 * sizeof(MCRegisterClass),
2869 .NameIdx: 1166,
2870 .RegSizeInBits: 128,
2871 .RegsSize: 4,
2872 .RegSetBegin: 58, /* MinRegVal */
2873 .RegSetSize: 4, /* RegSetSize */
2874 .ID: ARM::QPR_8RegClassID,
2875 .CopyCost: 1, /* CopyCost */
2876 .Allocatable: true, /* Allocatable */
2877 .BaseClass: false,
2878 offsetof(ARMRegisterClassStorage, SubClassMasks[1625]) - 75 * sizeof(MCRegisterClass),
2879 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[39]) - 75 * sizeof(MCRegisterClass),
2880 .LaneMask: LaneBitmask(0x000000000000003C),
2881 .AllocationPriority: 0,
2882 .GlobalPriority: false,
2883 .TSFlags: 0x00, /* TSFlags */
2884 .SpillStackID: 0, /* SpillStackID */
2885 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2886 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2887 offsetof(ARMRegisterClassStorage, SuperClasses[433]) - 75 * sizeof(MCRegisterClass),
2888 .SuperClassesSize: 8
2889 },
2890 {
2891 offsetof(ARMRegisterClassStorage, Regs[756]) - 76 * sizeof(MCRegisterClass),
2892 offsetof(ARMRegisterClassStorage, BitSets[439]) - 76 * sizeof(MCRegisterClass),
2893 .NameIdx: 2335,
2894 .RegSizeInBits: 192,
2895 .RegsSize: 30,
2896 .RegSetBegin: 184, /* MinRegVal */
2897 .RegSetSize: 30, /* RegSetSize */
2898 .ID: ARM::DTripleRegClassID,
2899 .CopyCost: 1, /* CopyCost */
2900 .Allocatable: true, /* Allocatable */
2901 .BaseClass: false,
2902 offsetof(ARMRegisterClassStorage, SubClassMasks[1655]) - 76 * sizeof(MCRegisterClass),
2903 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 76 * sizeof(MCRegisterClass),
2904 .LaneMask: LaneBitmask(0x00000000000000FC),
2905 .AllocationPriority: 0,
2906 .GlobalPriority: false,
2907 .TSFlags: 0x00, /* TSFlags */
2908 .SpillStackID: 0, /* SpillStackID */
2909 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2910 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2911 offsetof(ARMRegisterClassStorage, SuperClasses[441]) - 76 * sizeof(MCRegisterClass),
2912 .SuperClassesSize: 0
2913 },
2914 {
2915 offsetof(ARMRegisterClassStorage, Regs[786]) - 77 * sizeof(MCRegisterClass),
2916 offsetof(ARMRegisterClassStorage, BitSets[443]) - 77 * sizeof(MCRegisterClass),
2917 .NameIdx: 2235,
2918 .RegSizeInBits: 192,
2919 .RegsSize: 28,
2920 .RegSetBegin: 214, /* MinRegVal */
2921 .RegSetSize: 28, /* RegSetSize */
2922 .ID: ARM::DTripleSpcRegClassID,
2923 .CopyCost: 1, /* CopyCost */
2924 .Allocatable: true, /* Allocatable */
2925 .BaseClass: false,
2926 offsetof(ARMRegisterClassStorage, SubClassMasks[1690]) - 77 * sizeof(MCRegisterClass),
2927 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 77 * sizeof(MCRegisterClass),
2928 .LaneMask: LaneBitmask(0x0000000000000CCC),
2929 .AllocationPriority: 0,
2930 .GlobalPriority: false,
2931 .TSFlags: 0x00, /* TSFlags */
2932 .SpillStackID: 0, /* SpillStackID */
2933 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2934 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2935 offsetof(ARMRegisterClassStorage, SuperClasses[441]) - 77 * sizeof(MCRegisterClass),
2936 .SuperClassesSize: 0
2937 },
2938 {
2939 offsetof(ARMRegisterClassStorage, Regs[814]) - 78 * sizeof(MCRegisterClass),
2940 offsetof(ARMRegisterClassStorage, BitSets[447]) - 78 * sizeof(MCRegisterClass),
2941 .NameIdx: 62,
2942 .RegSizeInBits: 192,
2943 .RegsSize: 16,
2944 .RegSetBegin: 214, /* MinRegVal */
2945 .RegSetSize: 16, /* RegSetSize */
2946 .ID: ARM::DTripleSpc_with_ssub_0RegClassID,
2947 .CopyCost: 1, /* CopyCost */
2948 .Allocatable: true, /* Allocatable */
2949 .BaseClass: false,
2950 offsetof(ARMRegisterClassStorage, SubClassMasks[1715]) - 78 * sizeof(MCRegisterClass),
2951 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 78 * sizeof(MCRegisterClass),
2952 .LaneMask: LaneBitmask(0x0000000000000CCC),
2953 .AllocationPriority: 0,
2954 .GlobalPriority: false,
2955 .TSFlags: 0x00, /* TSFlags */
2956 .SpillStackID: 0, /* SpillStackID */
2957 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2958 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2959 offsetof(ARMRegisterClassStorage, SuperClasses[441]) - 78 * sizeof(MCRegisterClass),
2960 .SuperClassesSize: 1
2961 },
2962 {
2963 offsetof(ARMRegisterClassStorage, Regs[830]) - 79 * sizeof(MCRegisterClass),
2964 offsetof(ARMRegisterClassStorage, BitSets[449]) - 79 * sizeof(MCRegisterClass),
2965 .NameIdx: 124,
2966 .RegSizeInBits: 192,
2967 .RegsSize: 16,
2968 .RegSetBegin: 184, /* MinRegVal */
2969 .RegSetSize: 16, /* RegSetSize */
2970 .ID: ARM::DTriple_with_ssub_0RegClassID,
2971 .CopyCost: 1, /* CopyCost */
2972 .Allocatable: true, /* Allocatable */
2973 .BaseClass: false,
2974 offsetof(ARMRegisterClassStorage, SubClassMasks[1740]) - 79 * sizeof(MCRegisterClass),
2975 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 79 * sizeof(MCRegisterClass),
2976 .LaneMask: LaneBitmask(0x00000000000000FC),
2977 .AllocationPriority: 0,
2978 .GlobalPriority: false,
2979 .TSFlags: 0x00, /* TSFlags */
2980 .SpillStackID: 0, /* SpillStackID */
2981 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2982 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2983 offsetof(ARMRegisterClassStorage, SuperClasses[442]) - 79 * sizeof(MCRegisterClass),
2984 .SuperClassesSize: 1
2985 },
2986 {
2987 offsetof(ARMRegisterClassStorage, Regs[846]) - 80 * sizeof(MCRegisterClass),
2988 offsetof(ARMRegisterClassStorage, BitSets[451]) - 80 * sizeof(MCRegisterClass),
2989 .NameIdx: 1994,
2990 .RegSizeInBits: 192,
2991 .RegsSize: 15,
2992 .RegSetBegin: 184, /* MinRegVal */
2993 .RegSetSize: 29, /* RegSetSize */
2994 .ID: ARM::DTriple_with_qsub_0_in_QPRRegClassID,
2995 .CopyCost: 1, /* CopyCost */
2996 .Allocatable: true, /* Allocatable */
2997 .BaseClass: false,
2998 offsetof(ARMRegisterClassStorage, SubClassMasks[1775]) - 80 * sizeof(MCRegisterClass),
2999 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[53]) - 80 * sizeof(MCRegisterClass),
3000 .LaneMask: LaneBitmask(0x00000000000000FC),
3001 .AllocationPriority: 0,
3002 .GlobalPriority: false,
3003 .TSFlags: 0x00, /* TSFlags */
3004 .SpillStackID: 0, /* SpillStackID */
3005 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3006 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3007 offsetof(ARMRegisterClassStorage, SuperClasses[443]) - 80 * sizeof(MCRegisterClass),
3008 .SuperClassesSize: 1
3009 },
3010 {
3011 offsetof(ARMRegisterClassStorage, Regs[861]) - 81 * sizeof(MCRegisterClass),
3012 offsetof(ARMRegisterClassStorage, BitSets[455]) - 81 * sizeof(MCRegisterClass),
3013 .NameIdx: 258,
3014 .RegSizeInBits: 192,
3015 .RegsSize: 15,
3016 .RegSetBegin: 184, /* MinRegVal */
3017 .RegSetSize: 15, /* RegSetSize */
3018 .ID: ARM::DTriple_with_ssub_2RegClassID,
3019 .CopyCost: 1, /* CopyCost */
3020 .Allocatable: true, /* Allocatable */
3021 .BaseClass: false,
3022 offsetof(ARMRegisterClassStorage, SubClassMasks[1800]) - 81 * sizeof(MCRegisterClass),
3023 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 81 * sizeof(MCRegisterClass),
3024 .LaneMask: LaneBitmask(0x00000000000000FC),
3025 .AllocationPriority: 0,
3026 .GlobalPriority: false,
3027 .TSFlags: 0x00, /* TSFlags */
3028 .SpillStackID: 0, /* SpillStackID */
3029 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3030 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3031 offsetof(ARMRegisterClassStorage, SuperClasses[444]) - 81 * sizeof(MCRegisterClass),
3032 .SuperClassesSize: 2
3033 },
3034 {
3035 offsetof(ARMRegisterClassStorage, Regs[876]) - 82 * sizeof(MCRegisterClass),
3036 offsetof(ARMRegisterClassStorage, BitSets[457]) - 82 * sizeof(MCRegisterClass),
3037 .NameIdx: 2113,
3038 .RegSizeInBits: 192,
3039 .RegsSize: 15,
3040 .RegSetBegin: 185, /* MinRegVal */
3041 .RegSetSize: 29, /* RegSetSize */
3042 .ID: ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
3043 .CopyCost: 1, /* CopyCost */
3044 .Allocatable: true, /* Allocatable */
3045 .BaseClass: false,
3046 offsetof(ARMRegisterClassStorage, SubClassMasks[1835]) - 82 * sizeof(MCRegisterClass),
3047 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[64]) - 82 * sizeof(MCRegisterClass),
3048 .LaneMask: LaneBitmask(0x00000000000000FC),
3049 .AllocationPriority: 0,
3050 .GlobalPriority: false,
3051 .TSFlags: 0x00, /* TSFlags */
3052 .SpillStackID: 0, /* SpillStackID */
3053 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3054 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3055 offsetof(ARMRegisterClassStorage, SuperClasses[446]) - 82 * sizeof(MCRegisterClass),
3056 .SuperClassesSize: 1
3057 },
3058 {
3059 offsetof(ARMRegisterClassStorage, Regs[891]) - 83 * sizeof(MCRegisterClass),
3060 offsetof(ARMRegisterClassStorage, BitSets[461]) - 83 * sizeof(MCRegisterClass),
3061 .NameIdx: 336,
3062 .RegSizeInBits: 192,
3063 .RegsSize: 14,
3064 .RegSetBegin: 214, /* MinRegVal */
3065 .RegSetSize: 14, /* RegSetSize */
3066 .ID: ARM::DTripleSpc_with_ssub_4RegClassID,
3067 .CopyCost: 1, /* CopyCost */
3068 .Allocatable: true, /* Allocatable */
3069 .BaseClass: false,
3070 offsetof(ARMRegisterClassStorage, SubClassMasks[1860]) - 83 * sizeof(MCRegisterClass),
3071 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 83 * sizeof(MCRegisterClass),
3072 .LaneMask: LaneBitmask(0x0000000000000CCC),
3073 .AllocationPriority: 0,
3074 .GlobalPriority: false,
3075 .TSFlags: 0x00, /* TSFlags */
3076 .SpillStackID: 0, /* SpillStackID */
3077 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3078 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3079 offsetof(ARMRegisterClassStorage, SuperClasses[447]) - 83 * sizeof(MCRegisterClass),
3080 .SuperClassesSize: 2
3081 },
3082 {
3083 offsetof(ARMRegisterClassStorage, Regs[905]) - 84 * sizeof(MCRegisterClass),
3084 offsetof(ARMRegisterClassStorage, BitSets[463]) - 84 * sizeof(MCRegisterClass),
3085 .NameIdx: 398,
3086 .RegSizeInBits: 192,
3087 .RegsSize: 14,
3088 .RegSetBegin: 184, /* MinRegVal */
3089 .RegSetSize: 14, /* RegSetSize */
3090 .ID: ARM::DTriple_with_ssub_4RegClassID,
3091 .CopyCost: 1, /* CopyCost */
3092 .Allocatable: true, /* Allocatable */
3093 .BaseClass: false,
3094 offsetof(ARMRegisterClassStorage, SubClassMasks[1885]) - 84 * sizeof(MCRegisterClass),
3095 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 84 * sizeof(MCRegisterClass),
3096 .LaneMask: LaneBitmask(0x00000000000000FC),
3097 .AllocationPriority: 0,
3098 .GlobalPriority: false,
3099 .TSFlags: 0x00, /* TSFlags */
3100 .SpillStackID: 0, /* SpillStackID */
3101 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3102 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3103 offsetof(ARMRegisterClassStorage, SuperClasses[449]) - 84 * sizeof(MCRegisterClass),
3104 .SuperClassesSize: 3
3105 },
3106 {
3107 offsetof(ARMRegisterClassStorage, Regs[919]) - 85 * sizeof(MCRegisterClass),
3108 offsetof(ARMRegisterClassStorage, BitSets[465]) - 85 * sizeof(MCRegisterClass),
3109 .NameIdx: 1411,
3110 .RegSizeInBits: 192,
3111 .RegsSize: 12,
3112 .RegSetBegin: 214, /* MinRegVal */
3113 .RegSetSize: 12, /* RegSetSize */
3114 .ID: ARM::DTripleSpc_with_ssub_8RegClassID,
3115 .CopyCost: 1, /* CopyCost */
3116 .Allocatable: true, /* Allocatable */
3117 .BaseClass: false,
3118 offsetof(ARMRegisterClassStorage, SubClassMasks[1920]) - 85 * sizeof(MCRegisterClass),
3119 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 85 * sizeof(MCRegisterClass),
3120 .LaneMask: LaneBitmask(0x0000000000000CCC),
3121 .AllocationPriority: 0,
3122 .GlobalPriority: false,
3123 .TSFlags: 0x00, /* TSFlags */
3124 .SpillStackID: 0, /* SpillStackID */
3125 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3126 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3127 offsetof(ARMRegisterClassStorage, SuperClasses[452]) - 85 * sizeof(MCRegisterClass),
3128 .SuperClassesSize: 3
3129 },
3130 {
3131 offsetof(ARMRegisterClassStorage, Regs[931]) - 86 * sizeof(MCRegisterClass),
3132 offsetof(ARMRegisterClassStorage, BitSets[467]) - 86 * sizeof(MCRegisterClass),
3133 .NameIdx: 466,
3134 .RegSizeInBits: 192,
3135 .RegsSize: 8,
3136 .RegSetBegin: 214, /* MinRegVal */
3137 .RegSetSize: 8, /* RegSetSize */
3138 .ID: ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID,
3139 .CopyCost: 1, /* CopyCost */
3140 .Allocatable: true, /* Allocatable */
3141 .BaseClass: false,
3142 offsetof(ARMRegisterClassStorage, SubClassMasks[1945]) - 86 * sizeof(MCRegisterClass),
3143 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 86 * sizeof(MCRegisterClass),
3144 .LaneMask: LaneBitmask(0x0000000000000CCC),
3145 .AllocationPriority: 0,
3146 .GlobalPriority: false,
3147 .TSFlags: 0x00, /* TSFlags */
3148 .SpillStackID: 0, /* SpillStackID */
3149 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3150 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3151 offsetof(ARMRegisterClassStorage, SuperClasses[455]) - 86 * sizeof(MCRegisterClass),
3152 .SuperClassesSize: 4
3153 },
3154 {
3155 offsetof(ARMRegisterClassStorage, Regs[939]) - 87 * sizeof(MCRegisterClass),
3156 offsetof(ARMRegisterClassStorage, BitSets[468]) - 87 * sizeof(MCRegisterClass),
3157 .NameIdx: 555,
3158 .RegSizeInBits: 192,
3159 .RegsSize: 8,
3160 .RegSetBegin: 184, /* MinRegVal */
3161 .RegSetSize: 8, /* RegSetSize */
3162 .ID: ARM::DTriple_with_dsub_0_in_DPR_8RegClassID,
3163 .CopyCost: 1, /* CopyCost */
3164 .Allocatable: true, /* Allocatable */
3165 .BaseClass: false,
3166 offsetof(ARMRegisterClassStorage, SubClassMasks[1970]) - 87 * sizeof(MCRegisterClass),
3167 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 87 * sizeof(MCRegisterClass),
3168 .LaneMask: LaneBitmask(0x00000000000000FC),
3169 .AllocationPriority: 0,
3170 .GlobalPriority: false,
3171 .TSFlags: 0x00, /* TSFlags */
3172 .SpillStackID: 0, /* SpillStackID */
3173 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3174 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3175 offsetof(ARMRegisterClassStorage, SuperClasses[459]) - 87 * sizeof(MCRegisterClass),
3176 .SuperClassesSize: 4
3177 },
3178 {
3179 offsetof(ARMRegisterClassStorage, Regs[947]) - 88 * sizeof(MCRegisterClass),
3180 offsetof(ARMRegisterClassStorage, BitSets[469]) - 88 * sizeof(MCRegisterClass),
3181 .NameIdx: 1745,
3182 .RegSizeInBits: 192,
3183 .RegsSize: 8,
3184 .RegSetBegin: 184, /* MinRegVal */
3185 .RegSetSize: 15, /* RegSetSize */
3186 .ID: ARM::DTriple_with_qsub_0_in_MQPRRegClassID,
3187 .CopyCost: 1, /* CopyCost */
3188 .Allocatable: true, /* Allocatable */
3189 .BaseClass: false,
3190 offsetof(ARMRegisterClassStorage, SubClassMasks[2005]) - 88 * sizeof(MCRegisterClass),
3191 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[53]) - 88 * sizeof(MCRegisterClass),
3192 .LaneMask: LaneBitmask(0x00000000000000FC),
3193 .AllocationPriority: 0,
3194 .GlobalPriority: false,
3195 .TSFlags: 0x00, /* TSFlags */
3196 .SpillStackID: 0, /* SpillStackID */
3197 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3198 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3199 offsetof(ARMRegisterClassStorage, SuperClasses[463]) - 88 * sizeof(MCRegisterClass),
3200 .SuperClassesSize: 4
3201 },
3202 {
3203 offsetof(ARMRegisterClassStorage, Regs[955]) - 89 * sizeof(MCRegisterClass),
3204 offsetof(ARMRegisterClassStorage, BitSets[471]) - 89 * sizeof(MCRegisterClass),
3205 .NameIdx: 2089,
3206 .RegSizeInBits: 192,
3207 .RegsSize: 8,
3208 .RegSetBegin: 185, /* MinRegVal */
3209 .RegSetSize: 15, /* RegSetSize */
3210 .ID: ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
3211 .CopyCost: 1, /* CopyCost */
3212 .Allocatable: true, /* Allocatable */
3213 .BaseClass: false,
3214 offsetof(ARMRegisterClassStorage, SubClassMasks[2030]) - 89 * sizeof(MCRegisterClass),
3215 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[64]) - 89 * sizeof(MCRegisterClass),
3216 .LaneMask: LaneBitmask(0x00000000000000FC),
3217 .AllocationPriority: 0,
3218 .GlobalPriority: false,
3219 .TSFlags: 0x00, /* TSFlags */
3220 .SpillStackID: 0, /* SpillStackID */
3221 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3222 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3223 offsetof(ARMRegisterClassStorage, SuperClasses[467]) - 89 * sizeof(MCRegisterClass),
3224 .SuperClassesSize: 3
3225 },
3226 {
3227 offsetof(ARMRegisterClassStorage, Regs[963]) - 90 * sizeof(MCRegisterClass),
3228 offsetof(ARMRegisterClassStorage, BitSets[473]) - 90 * sizeof(MCRegisterClass),
3229 .NameIdx: 638,
3230 .RegSizeInBits: 192,
3231 .RegsSize: 7,
3232 .RegSetBegin: 184, /* MinRegVal */
3233 .RegSetSize: 7, /* RegSetSize */
3234 .ID: ARM::DTriple_with_dsub_1_in_DPR_8RegClassID,
3235 .CopyCost: 1, /* CopyCost */
3236 .Allocatable: true, /* Allocatable */
3237 .BaseClass: false,
3238 offsetof(ARMRegisterClassStorage, SubClassMasks[2055]) - 90 * sizeof(MCRegisterClass),
3239 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 90 * sizeof(MCRegisterClass),
3240 .LaneMask: LaneBitmask(0x00000000000000FC),
3241 .AllocationPriority: 0,
3242 .GlobalPriority: false,
3243 .TSFlags: 0x00, /* TSFlags */
3244 .SpillStackID: 0, /* SpillStackID */
3245 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3246 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3247 offsetof(ARMRegisterClassStorage, SuperClasses[470]) - 90 * sizeof(MCRegisterClass),
3248 .SuperClassesSize: 5
3249 },
3250 {
3251 offsetof(ARMRegisterClassStorage, Regs[970]) - 91 * sizeof(MCRegisterClass),
3252 offsetof(ARMRegisterClassStorage, BitSets[474]) - 91 * sizeof(MCRegisterClass),
3253 .NameIdx: 1931,
3254 .RegSizeInBits: 192,
3255 .RegsSize: 7,
3256 .RegSetBegin: 185, /* MinRegVal */
3257 .RegSetSize: 13, /* RegSetSize */
3258 .ID: ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
3259 .CopyCost: 1, /* CopyCost */
3260 .Allocatable: true, /* Allocatable */
3261 .BaseClass: false,
3262 offsetof(ARMRegisterClassStorage, SubClassMasks[2090]) - 91 * sizeof(MCRegisterClass),
3263 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[64]) - 91 * sizeof(MCRegisterClass),
3264 .LaneMask: LaneBitmask(0x00000000000000FC),
3265 .AllocationPriority: 0,
3266 .GlobalPriority: false,
3267 .TSFlags: 0x00, /* TSFlags */
3268 .SpillStackID: 0, /* SpillStackID */
3269 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3270 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3271 offsetof(ARMRegisterClassStorage, SuperClasses[475]) - 91 * sizeof(MCRegisterClass),
3272 .SuperClassesSize: 6
3273 },
3274 {
3275 offsetof(ARMRegisterClassStorage, Regs[977]) - 92 * sizeof(MCRegisterClass),
3276 offsetof(ARMRegisterClassStorage, BitSets[476]) - 92 * sizeof(MCRegisterClass),
3277 .NameIdx: 1721,
3278 .RegSizeInBits: 192,
3279 .RegsSize: 7,
3280 .RegSetBegin: 184, /* MinRegVal */
3281 .RegSetSize: 13, /* RegSetSize */
3282 .ID: ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID,
3283 .CopyCost: 1, /* CopyCost */
3284 .Allocatable: true, /* Allocatable */
3285 .BaseClass: false,
3286 offsetof(ARMRegisterClassStorage, SubClassMasks[2115]) - 92 * sizeof(MCRegisterClass),
3287 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[53]) - 92 * sizeof(MCRegisterClass),
3288 .LaneMask: LaneBitmask(0x00000000000000FC),
3289 .AllocationPriority: 0,
3290 .GlobalPriority: false,
3291 .TSFlags: 0x00, /* TSFlags */
3292 .SpillStackID: 0, /* SpillStackID */
3293 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3294 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3295 offsetof(ARMRegisterClassStorage, SuperClasses[481]) - 92 * sizeof(MCRegisterClass),
3296 .SuperClassesSize: 6
3297 },
3298 {
3299 offsetof(ARMRegisterClassStorage, Regs[984]) - 93 * sizeof(MCRegisterClass),
3300 offsetof(ARMRegisterClassStorage, BitSets[478]) - 93 * sizeof(MCRegisterClass),
3301 .NameIdx: 826,
3302 .RegSizeInBits: 192,
3303 .RegsSize: 6,
3304 .RegSetBegin: 214, /* MinRegVal */
3305 .RegSetSize: 6, /* RegSetSize */
3306 .ID: ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID,
3307 .CopyCost: 1, /* CopyCost */
3308 .Allocatable: true, /* Allocatable */
3309 .BaseClass: false,
3310 offsetof(ARMRegisterClassStorage, SubClassMasks[2140]) - 93 * sizeof(MCRegisterClass),
3311 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 93 * sizeof(MCRegisterClass),
3312 .LaneMask: LaneBitmask(0x0000000000000CCC),
3313 .AllocationPriority: 0,
3314 .GlobalPriority: false,
3315 .TSFlags: 0x00, /* TSFlags */
3316 .SpillStackID: 0, /* SpillStackID */
3317 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3318 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3319 offsetof(ARMRegisterClassStorage, SuperClasses[487]) - 93 * sizeof(MCRegisterClass),
3320 .SuperClassesSize: 5
3321 },
3322 {
3323 offsetof(ARMRegisterClassStorage, Regs[990]) - 94 * sizeof(MCRegisterClass),
3324 offsetof(ARMRegisterClassStorage, BitSets[479]) - 94 * sizeof(MCRegisterClass),
3325 .NameIdx: 1003,
3326 .RegSizeInBits: 192,
3327 .RegsSize: 6,
3328 .RegSetBegin: 184, /* MinRegVal */
3329 .RegSetSize: 6, /* RegSetSize */
3330 .ID: ARM::DTriple_with_dsub_2_in_DPR_8RegClassID,
3331 .CopyCost: 1, /* CopyCost */
3332 .Allocatable: true, /* Allocatable */
3333 .BaseClass: false,
3334 offsetof(ARMRegisterClassStorage, SubClassMasks[2165]) - 94 * sizeof(MCRegisterClass),
3335 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[69]) - 94 * sizeof(MCRegisterClass),
3336 .LaneMask: LaneBitmask(0x00000000000000FC),
3337 .AllocationPriority: 0,
3338 .GlobalPriority: false,
3339 .TSFlags: 0x00, /* TSFlags */
3340 .SpillStackID: 0, /* SpillStackID */
3341 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3342 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3343 offsetof(ARMRegisterClassStorage, SuperClasses[492]) - 94 * sizeof(MCRegisterClass),
3344 .SuperClassesSize: 6
3345 },
3346 {
3347 offsetof(ARMRegisterClassStorage, Regs[996]) - 95 * sizeof(MCRegisterClass),
3348 offsetof(ARMRegisterClassStorage, BitSets[480]) - 95 * sizeof(MCRegisterClass),
3349 .NameIdx: 1089,
3350 .RegSizeInBits: 192,
3351 .RegsSize: 4,
3352 .RegSetBegin: 214, /* MinRegVal */
3353 .RegSetSize: 4, /* RegSetSize */
3354 .ID: ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID,
3355 .CopyCost: 1, /* CopyCost */
3356 .Allocatable: true, /* Allocatable */
3357 .BaseClass: false,
3358 offsetof(ARMRegisterClassStorage, SubClassMasks[2200]) - 95 * sizeof(MCRegisterClass),
3359 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 95 * sizeof(MCRegisterClass),
3360 .LaneMask: LaneBitmask(0x0000000000000CCC),
3361 .AllocationPriority: 0,
3362 .GlobalPriority: false,
3363 .TSFlags: 0x00, /* TSFlags */
3364 .SpillStackID: 0, /* SpillStackID */
3365 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3366 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3367 offsetof(ARMRegisterClassStorage, SuperClasses[498]) - 95 * sizeof(MCRegisterClass),
3368 .SuperClassesSize: 6
3369 },
3370 {
3371 offsetof(ARMRegisterClassStorage, Regs[1000]) - 96 * sizeof(MCRegisterClass),
3372 offsetof(ARMRegisterClassStorage, BitSets[481]) - 96 * sizeof(MCRegisterClass),
3373 .NameIdx: 1898,
3374 .RegSizeInBits: 192,
3375 .RegsSize: 4,
3376 .RegSetBegin: 185, /* MinRegVal */
3377 .RegSetSize: 7, /* RegSetSize */
3378 .ID: ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
3379 .CopyCost: 1, /* CopyCost */
3380 .Allocatable: true, /* Allocatable */
3381 .BaseClass: false,
3382 offsetof(ARMRegisterClassStorage, SubClassMasks[2225]) - 96 * sizeof(MCRegisterClass),
3383 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[64]) - 96 * sizeof(MCRegisterClass),
3384 .LaneMask: LaneBitmask(0x00000000000000FC),
3385 .AllocationPriority: 0,
3386 .GlobalPriority: false,
3387 .TSFlags: 0x00, /* TSFlags */
3388 .SpillStackID: 0, /* SpillStackID */
3389 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3390 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3391 offsetof(ARMRegisterClassStorage, SuperClasses[504]) - 96 * sizeof(MCRegisterClass),
3392 .SuperClassesSize: 8
3393 },
3394 {
3395 offsetof(ARMRegisterClassStorage, Regs[1004]) - 97 * sizeof(MCRegisterClass),
3396 offsetof(ARMRegisterClassStorage, BitSets[482]) - 97 * sizeof(MCRegisterClass),
3397 .NameIdx: 1172,
3398 .RegSizeInBits: 192,
3399 .RegsSize: 4,
3400 .RegSetBegin: 184, /* MinRegVal */
3401 .RegSetSize: 7, /* RegSetSize */
3402 .ID: ARM::DTriple_with_qsub_0_in_QPR_8RegClassID,
3403 .CopyCost: 1, /* CopyCost */
3404 .Allocatable: true, /* Allocatable */
3405 .BaseClass: false,
3406 offsetof(ARMRegisterClassStorage, SubClassMasks[2250]) - 97 * sizeof(MCRegisterClass),
3407 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[53]) - 97 * sizeof(MCRegisterClass),
3408 .LaneMask: LaneBitmask(0x00000000000000FC),
3409 .AllocationPriority: 0,
3410 .GlobalPriority: false,
3411 .TSFlags: 0x00, /* TSFlags */
3412 .SpillStackID: 0, /* SpillStackID */
3413 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3414 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3415 offsetof(ARMRegisterClassStorage, SuperClasses[512]) - 97 * sizeof(MCRegisterClass),
3416 .SuperClassesSize: 9
3417 },
3418 {
3419 offsetof(ARMRegisterClassStorage, Regs[1008]) - 98 * sizeof(MCRegisterClass),
3420 offsetof(ARMRegisterClassStorage, BitSets[483]) - 98 * sizeof(MCRegisterClass),
3421 .NameIdx: 971,
3422 .RegSizeInBits: 192,
3423 .RegsSize: 3,
3424 .RegSetBegin: 184, /* MinRegVal */
3425 .RegSetSize: 5, /* RegSetSize */
3426 .ID: ARM::DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID,
3427 .CopyCost: 1, /* CopyCost */
3428 .Allocatable: true, /* Allocatable */
3429 .BaseClass: false,
3430 offsetof(ARMRegisterClassStorage, SubClassMasks[2275]) - 98 * sizeof(MCRegisterClass),
3431 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[53]) - 98 * sizeof(MCRegisterClass),
3432 .LaneMask: LaneBitmask(0x00000000000000FC),
3433 .AllocationPriority: 0,
3434 .GlobalPriority: false,
3435 .TSFlags: 0x00, /* TSFlags */
3436 .SpillStackID: 0, /* SpillStackID */
3437 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3438 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3439 offsetof(ARMRegisterClassStorage, SuperClasses[521]) - 98 * sizeof(MCRegisterClass),
3440 .SuperClassesSize: 11
3441 },
3442 {
3443 offsetof(ARMRegisterClassStorage, Regs[1011]) - 99 * sizeof(MCRegisterClass),
3444 offsetof(ARMRegisterClassStorage, BitSets[484]) - 99 * sizeof(MCRegisterClass),
3445 .NameIdx: 1278,
3446 .RegSizeInBits: 192,
3447 .RegsSize: 3,
3448 .RegSetBegin: 185, /* MinRegVal */
3449 .RegSetSize: 5, /* RegSetSize */
3450 .ID: ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID,
3451 .CopyCost: 1, /* CopyCost */
3452 .Allocatable: true, /* Allocatable */
3453 .BaseClass: false,
3454 offsetof(ARMRegisterClassStorage, SubClassMasks[2300]) - 99 * sizeof(MCRegisterClass),
3455 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[64]) - 99 * sizeof(MCRegisterClass),
3456 .LaneMask: LaneBitmask(0x00000000000000FC),
3457 .AllocationPriority: 0,
3458 .GlobalPriority: false,
3459 .TSFlags: 0x00, /* TSFlags */
3460 .SpillStackID: 0, /* SpillStackID */
3461 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3462 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3463 offsetof(ARMRegisterClassStorage, SuperClasses[532]) - 99 * sizeof(MCRegisterClass),
3464 .SuperClassesSize: 11
3465 },
3466 {
3467 offsetof(ARMRegisterClassStorage, Regs[1014]) - 100 * sizeof(MCRegisterClass),
3468 offsetof(ARMRegisterClassStorage, BitSets[485]) - 100 * sizeof(MCRegisterClass),
3469 .NameIdx: 2226,
3470 .RegSizeInBits: 256,
3471 .RegsSize: 28,
3472 .RegSetBegin: 214, /* MinRegVal */
3473 .RegSetSize: 28, /* RegSetSize */
3474 .ID: ARM::DQuadSpcRegClassID,
3475 .CopyCost: 1, /* CopyCost */
3476 .Allocatable: true, /* Allocatable */
3477 .BaseClass: false,
3478 offsetof(ARMRegisterClassStorage, SubClassMasks[2325]) - 100 * sizeof(MCRegisterClass),
3479 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 100 * sizeof(MCRegisterClass),
3480 .LaneMask: LaneBitmask(0x0000000000000CCC),
3481 .AllocationPriority: 0,
3482 .GlobalPriority: false,
3483 .TSFlags: 0x00, /* TSFlags */
3484 .SpillStackID: 0, /* SpillStackID */
3485 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3486 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3487 offsetof(ARMRegisterClassStorage, SuperClasses[543]) - 100 * sizeof(MCRegisterClass),
3488 .SuperClassesSize: 1
3489 },
3490 {
3491 offsetof(ARMRegisterClassStorage, Regs[1042]) - 101 * sizeof(MCRegisterClass),
3492 offsetof(ARMRegisterClassStorage, BitSets[489]) - 101 * sizeof(MCRegisterClass),
3493 .NameIdx: 41,
3494 .RegSizeInBits: 256,
3495 .RegsSize: 16,
3496 .RegSetBegin: 214, /* MinRegVal */
3497 .RegSetSize: 16, /* RegSetSize */
3498 .ID: ARM::DQuadSpc_with_ssub_0RegClassID,
3499 .CopyCost: 1, /* CopyCost */
3500 .Allocatable: true, /* Allocatable */
3501 .BaseClass: false,
3502 offsetof(ARMRegisterClassStorage, SubClassMasks[2350]) - 101 * sizeof(MCRegisterClass),
3503 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 101 * sizeof(MCRegisterClass),
3504 .LaneMask: LaneBitmask(0x0000000000000CCC),
3505 .AllocationPriority: 0,
3506 .GlobalPriority: false,
3507 .TSFlags: 0x00, /* TSFlags */
3508 .SpillStackID: 0, /* SpillStackID */
3509 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3510 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3511 offsetof(ARMRegisterClassStorage, SuperClasses[544]) - 101 * sizeof(MCRegisterClass),
3512 .SuperClassesSize: 3
3513 },
3514 {
3515 offsetof(ARMRegisterClassStorage, Regs[1058]) - 102 * sizeof(MCRegisterClass),
3516 offsetof(ARMRegisterClassStorage, BitSets[491]) - 102 * sizeof(MCRegisterClass),
3517 .NameIdx: 315,
3518 .RegSizeInBits: 256,
3519 .RegsSize: 14,
3520 .RegSetBegin: 214, /* MinRegVal */
3521 .RegSetSize: 14, /* RegSetSize */
3522 .ID: ARM::DQuadSpc_with_ssub_4RegClassID,
3523 .CopyCost: 1, /* CopyCost */
3524 .Allocatable: true, /* Allocatable */
3525 .BaseClass: false,
3526 offsetof(ARMRegisterClassStorage, SubClassMasks[2375]) - 102 * sizeof(MCRegisterClass),
3527 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 102 * sizeof(MCRegisterClass),
3528 .LaneMask: LaneBitmask(0x0000000000000CCC),
3529 .AllocationPriority: 0,
3530 .GlobalPriority: false,
3531 .TSFlags: 0x00, /* TSFlags */
3532 .SpillStackID: 0, /* SpillStackID */
3533 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3534 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3535 offsetof(ARMRegisterClassStorage, SuperClasses[547]) - 102 * sizeof(MCRegisterClass),
3536 .SuperClassesSize: 5
3537 },
3538 {
3539 offsetof(ARMRegisterClassStorage, Regs[1072]) - 103 * sizeof(MCRegisterClass),
3540 offsetof(ARMRegisterClassStorage, BitSets[493]) - 103 * sizeof(MCRegisterClass),
3541 .NameIdx: 1390,
3542 .RegSizeInBits: 256,
3543 .RegsSize: 12,
3544 .RegSetBegin: 214, /* MinRegVal */
3545 .RegSetSize: 12, /* RegSetSize */
3546 .ID: ARM::DQuadSpc_with_ssub_8RegClassID,
3547 .CopyCost: 1, /* CopyCost */
3548 .Allocatable: true, /* Allocatable */
3549 .BaseClass: false,
3550 offsetof(ARMRegisterClassStorage, SubClassMasks[2400]) - 103 * sizeof(MCRegisterClass),
3551 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 103 * sizeof(MCRegisterClass),
3552 .LaneMask: LaneBitmask(0x0000000000000CCC),
3553 .AllocationPriority: 0,
3554 .GlobalPriority: false,
3555 .TSFlags: 0x00, /* TSFlags */
3556 .SpillStackID: 0, /* SpillStackID */
3557 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3558 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3559 offsetof(ARMRegisterClassStorage, SuperClasses[552]) - 103 * sizeof(MCRegisterClass),
3560 .SuperClassesSize: 7
3561 },
3562 {
3563 offsetof(ARMRegisterClassStorage, Regs[1084]) - 104 * sizeof(MCRegisterClass),
3564 offsetof(ARMRegisterClassStorage, BitSets[495]) - 104 * sizeof(MCRegisterClass),
3565 .NameIdx: 436,
3566 .RegSizeInBits: 256,
3567 .RegsSize: 8,
3568 .RegSetBegin: 214, /* MinRegVal */
3569 .RegSetSize: 8, /* RegSetSize */
3570 .ID: ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID,
3571 .CopyCost: 1, /* CopyCost */
3572 .Allocatable: true, /* Allocatable */
3573 .BaseClass: false,
3574 offsetof(ARMRegisterClassStorage, SubClassMasks[2425]) - 104 * sizeof(MCRegisterClass),
3575 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 104 * sizeof(MCRegisterClass),
3576 .LaneMask: LaneBitmask(0x0000000000000CCC),
3577 .AllocationPriority: 0,
3578 .GlobalPriority: false,
3579 .TSFlags: 0x00, /* TSFlags */
3580 .SpillStackID: 0, /* SpillStackID */
3581 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3582 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3583 offsetof(ARMRegisterClassStorage, SuperClasses[559]) - 104 * sizeof(MCRegisterClass),
3584 .SuperClassesSize: 9
3585 },
3586 {
3587 offsetof(ARMRegisterClassStorage, Regs[1092]) - 105 * sizeof(MCRegisterClass),
3588 offsetof(ARMRegisterClassStorage, BitSets[496]) - 105 * sizeof(MCRegisterClass),
3589 .NameIdx: 796,
3590 .RegSizeInBits: 256,
3591 .RegsSize: 6,
3592 .RegSetBegin: 214, /* MinRegVal */
3593 .RegSetSize: 6, /* RegSetSize */
3594 .ID: ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID,
3595 .CopyCost: 1, /* CopyCost */
3596 .Allocatable: true, /* Allocatable */
3597 .BaseClass: false,
3598 offsetof(ARMRegisterClassStorage, SubClassMasks[2450]) - 105 * sizeof(MCRegisterClass),
3599 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 105 * sizeof(MCRegisterClass),
3600 .LaneMask: LaneBitmask(0x0000000000000CCC),
3601 .AllocationPriority: 0,
3602 .GlobalPriority: false,
3603 .TSFlags: 0x00, /* TSFlags */
3604 .SpillStackID: 0, /* SpillStackID */
3605 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3606 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3607 offsetof(ARMRegisterClassStorage, SuperClasses[568]) - 105 * sizeof(MCRegisterClass),
3608 .SuperClassesSize: 11
3609 },
3610 {
3611 offsetof(ARMRegisterClassStorage, Regs[1098]) - 106 * sizeof(MCRegisterClass),
3612 offsetof(ARMRegisterClassStorage, BitSets[497]) - 106 * sizeof(MCRegisterClass),
3613 .NameIdx: 1059,
3614 .RegSizeInBits: 256,
3615 .RegsSize: 4,
3616 .RegSetBegin: 214, /* MinRegVal */
3617 .RegSetSize: 4, /* RegSetSize */
3618 .ID: ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID,
3619 .CopyCost: 1, /* CopyCost */
3620 .Allocatable: true, /* Allocatable */
3621 .BaseClass: false,
3622 offsetof(ARMRegisterClassStorage, SubClassMasks[2475]) - 106 * sizeof(MCRegisterClass),
3623 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[45]) - 106 * sizeof(MCRegisterClass),
3624 .LaneMask: LaneBitmask(0x0000000000000CCC),
3625 .AllocationPriority: 0,
3626 .GlobalPriority: false,
3627 .TSFlags: 0x00, /* TSFlags */
3628 .SpillStackID: 0, /* SpillStackID */
3629 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3630 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3631 offsetof(ARMRegisterClassStorage, SuperClasses[579]) - 106 * sizeof(MCRegisterClass),
3632 .SuperClassesSize: 13
3633 },
3634 {
3635 offsetof(ARMRegisterClassStorage, Regs[1102]) - 107 * sizeof(MCRegisterClass),
3636 offsetof(ARMRegisterClassStorage, BitSets[498]) - 107 * sizeof(MCRegisterClass),
3637 .NameIdx: 2295,
3638 .RegSizeInBits: 256,
3639 .RegsSize: 29,
3640 .RegSetBegin: 149, /* MinRegVal */
3641 .RegSetSize: 148, /* RegSetSize */
3642 .ID: ARM::DQuadRegClassID,
3643 .CopyCost: 1, /* CopyCost */
3644 .Allocatable: true, /* Allocatable */
3645 .BaseClass: false,
3646 offsetof(ARMRegisterClassStorage, SubClassMasks[2500]) - 107 * sizeof(MCRegisterClass),
3647 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 107 * sizeof(MCRegisterClass),
3648 .LaneMask: LaneBitmask(0x00000000000003FC),
3649 .AllocationPriority: 0,
3650 .GlobalPriority: false,
3651 .TSFlags: 0x00, /* TSFlags */
3652 .SpillStackID: 0, /* SpillStackID */
3653 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3654 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3655 offsetof(ARMRegisterClassStorage, SuperClasses[592]) - 107 * sizeof(MCRegisterClass),
3656 .SuperClassesSize: 0
3657 },
3658 {
3659 offsetof(ARMRegisterClassStorage, Regs[1131]) - 108 * sizeof(MCRegisterClass),
3660 offsetof(ARMRegisterClassStorage, BitSets[517]) - 108 * sizeof(MCRegisterClass),
3661 .NameIdx: 106,
3662 .RegSizeInBits: 256,
3663 .RegsSize: 16,
3664 .RegSetBegin: 149, /* MinRegVal */
3665 .RegSetSize: 142, /* RegSetSize */
3666 .ID: ARM::DQuad_with_ssub_0RegClassID,
3667 .CopyCost: 1, /* CopyCost */
3668 .Allocatable: true, /* Allocatable */
3669 .BaseClass: false,
3670 offsetof(ARMRegisterClassStorage, SubClassMasks[2530]) - 108 * sizeof(MCRegisterClass),
3671 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 108 * sizeof(MCRegisterClass),
3672 .LaneMask: LaneBitmask(0x00000000000003FC),
3673 .AllocationPriority: 0,
3674 .GlobalPriority: false,
3675 .TSFlags: 0x00, /* TSFlags */
3676 .SpillStackID: 0, /* SpillStackID */
3677 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3678 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3679 offsetof(ARMRegisterClassStorage, SuperClasses[592]) - 108 * sizeof(MCRegisterClass),
3680 .SuperClassesSize: 1
3681 },
3682 {
3683 offsetof(ARMRegisterClassStorage, Regs[1147]) - 109 * sizeof(MCRegisterClass),
3684 offsetof(ARMRegisterClassStorage, BitSets[535]) - 109 * sizeof(MCRegisterClass),
3685 .NameIdx: 240,
3686 .RegSizeInBits: 256,
3687 .RegsSize: 15,
3688 .RegSetBegin: 149, /* MinRegVal */
3689 .RegSetSize: 141, /* RegSetSize */
3690 .ID: ARM::DQuad_with_ssub_2RegClassID,
3691 .CopyCost: 1, /* CopyCost */
3692 .Allocatable: true, /* Allocatable */
3693 .BaseClass: false,
3694 offsetof(ARMRegisterClassStorage, SubClassMasks[2560]) - 109 * sizeof(MCRegisterClass),
3695 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 109 * sizeof(MCRegisterClass),
3696 .LaneMask: LaneBitmask(0x00000000000003FC),
3697 .AllocationPriority: 0,
3698 .GlobalPriority: false,
3699 .TSFlags: 0x00, /* TSFlags */
3700 .SpillStackID: 0, /* SpillStackID */
3701 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3702 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3703 offsetof(ARMRegisterClassStorage, SuperClasses[593]) - 109 * sizeof(MCRegisterClass),
3704 .SuperClassesSize: 2
3705 },
3706 {
3707 offsetof(ARMRegisterClassStorage, Regs[1162]) - 110 * sizeof(MCRegisterClass),
3708 offsetof(ARMRegisterClassStorage, BitSets[553]) - 110 * sizeof(MCRegisterClass),
3709 .NameIdx: 1981,
3710 .RegSizeInBits: 256,
3711 .RegsSize: 15,
3712 .RegSetBegin: 149, /* MinRegVal */
3713 .RegSetSize: 15, /* RegSetSize */
3714 .ID: ARM::QQPRRegClassID,
3715 .CopyCost: 1, /* CopyCost */
3716 .Allocatable: true, /* Allocatable */
3717 .BaseClass: false,
3718 offsetof(ARMRegisterClassStorage, SubClassMasks[2590]) - 110 * sizeof(MCRegisterClass),
3719 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[84]) - 110 * sizeof(MCRegisterClass),
3720 .LaneMask: LaneBitmask(0x00000000000003FC),
3721 .AllocationPriority: 0,
3722 .GlobalPriority: false,
3723 .TSFlags: 0x00, /* TSFlags */
3724 .SpillStackID: 0, /* SpillStackID */
3725 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3726 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3727 offsetof(ARMRegisterClassStorage, SuperClasses[595]) - 110 * sizeof(MCRegisterClass),
3728 .SuperClassesSize: 1
3729 },
3730 {
3731 offsetof(ARMRegisterClassStorage, Regs[1177]) - 111 * sizeof(MCRegisterClass),
3732 offsetof(ARMRegisterClassStorage, BitSets[555]) - 111 * sizeof(MCRegisterClass),
3733 .NameIdx: 2043,
3734 .RegSizeInBits: 256,
3735 .RegsSize: 14,
3736 .RegSetBegin: 283, /* MinRegVal */
3737 .RegSetSize: 14, /* RegSetSize */
3738 .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
3739 .CopyCost: 1, /* CopyCost */
3740 .Allocatable: true, /* Allocatable */
3741 .BaseClass: false,
3742 offsetof(ARMRegisterClassStorage, SubClassMasks[2610]) - 111 * sizeof(MCRegisterClass),
3743 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 111 * sizeof(MCRegisterClass),
3744 .LaneMask: LaneBitmask(0x00000000000003FC),
3745 .AllocationPriority: 0,
3746 .GlobalPriority: false,
3747 .TSFlags: 0x00, /* TSFlags */
3748 .SpillStackID: 0, /* SpillStackID */
3749 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3750 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3751 offsetof(ARMRegisterClassStorage, SuperClasses[596]) - 111 * sizeof(MCRegisterClass),
3752 .SuperClassesSize: 1
3753 },
3754 {
3755 offsetof(ARMRegisterClassStorage, Regs[1191]) - 112 * sizeof(MCRegisterClass),
3756 offsetof(ARMRegisterClassStorage, BitSets[557]) - 112 * sizeof(MCRegisterClass),
3757 .NameIdx: 380,
3758 .RegSizeInBits: 256,
3759 .RegsSize: 14,
3760 .RegSetBegin: 149, /* MinRegVal */
3761 .RegSetSize: 141, /* RegSetSize */
3762 .ID: ARM::DQuad_with_ssub_4RegClassID,
3763 .CopyCost: 1, /* CopyCost */
3764 .Allocatable: true, /* Allocatable */
3765 .BaseClass: false,
3766 offsetof(ARMRegisterClassStorage, SubClassMasks[2625]) - 112 * sizeof(MCRegisterClass),
3767 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 112 * sizeof(MCRegisterClass),
3768 .LaneMask: LaneBitmask(0x00000000000003FC),
3769 .AllocationPriority: 0,
3770 .GlobalPriority: false,
3771 .TSFlags: 0x00, /* TSFlags */
3772 .SpillStackID: 0, /* SpillStackID */
3773 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3774 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3775 offsetof(ARMRegisterClassStorage, SuperClasses[597]) - 112 * sizeof(MCRegisterClass),
3776 .SuperClassesSize: 3
3777 },
3778 {
3779 offsetof(ARMRegisterClassStorage, Regs[1205]) - 113 * sizeof(MCRegisterClass),
3780 offsetof(ARMRegisterClassStorage, BitSets[575]) - 113 * sizeof(MCRegisterClass),
3781 .NameIdx: 418,
3782 .RegSizeInBits: 256,
3783 .RegsSize: 13,
3784 .RegSetBegin: 149, /* MinRegVal */
3785 .RegSetSize: 140, /* RegSetSize */
3786 .ID: ARM::DQuad_with_ssub_6RegClassID,
3787 .CopyCost: 1, /* CopyCost */
3788 .Allocatable: true, /* Allocatable */
3789 .BaseClass: false,
3790 offsetof(ARMRegisterClassStorage, SubClassMasks[2655]) - 113 * sizeof(MCRegisterClass),
3791 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 113 * sizeof(MCRegisterClass),
3792 .LaneMask: LaneBitmask(0x00000000000003FC),
3793 .AllocationPriority: 0,
3794 .GlobalPriority: false,
3795 .TSFlags: 0x00, /* TSFlags */
3796 .SpillStackID: 0, /* SpillStackID */
3797 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3798 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3799 offsetof(ARMRegisterClassStorage, SuperClasses[600]) - 113 * sizeof(MCRegisterClass),
3800 .SuperClassesSize: 4
3801 },
3802 {
3803 offsetof(ARMRegisterClassStorage, Regs[1218]) - 114 * sizeof(MCRegisterClass),
3804 offsetof(ARMRegisterClassStorage, BitSets[593]) - 114 * sizeof(MCRegisterClass),
3805 .NameIdx: 528,
3806 .RegSizeInBits: 256,
3807 .RegsSize: 8,
3808 .RegSetBegin: 149, /* MinRegVal */
3809 .RegSetSize: 138, /* RegSetSize */
3810 .ID: ARM::DQuad_with_dsub_0_in_DPR_8RegClassID,
3811 .CopyCost: 1, /* CopyCost */
3812 .Allocatable: true, /* Allocatable */
3813 .BaseClass: false,
3814 offsetof(ARMRegisterClassStorage, SubClassMasks[2685]) - 114 * sizeof(MCRegisterClass),
3815 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 114 * sizeof(MCRegisterClass),
3816 .LaneMask: LaneBitmask(0x00000000000003FC),
3817 .AllocationPriority: 0,
3818 .GlobalPriority: false,
3819 .TSFlags: 0x00, /* TSFlags */
3820 .SpillStackID: 0, /* SpillStackID */
3821 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3822 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3823 offsetof(ARMRegisterClassStorage, SuperClasses[604]) - 114 * sizeof(MCRegisterClass),
3824 .SuperClassesSize: 5
3825 },
3826 {
3827 offsetof(ARMRegisterClassStorage, Regs[1226]) - 115 * sizeof(MCRegisterClass),
3828 offsetof(ARMRegisterClassStorage, BitSets[611]) - 115 * sizeof(MCRegisterClass),
3829 .NameIdx: 2021,
3830 .RegSizeInBits: 256,
3831 .RegsSize: 8,
3832 .RegSetBegin: 283, /* MinRegVal */
3833 .RegSetSize: 8, /* RegSetSize */
3834 .ID: ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
3835 .CopyCost: 1, /* CopyCost */
3836 .Allocatable: true, /* Allocatable */
3837 .BaseClass: false,
3838 offsetof(ARMRegisterClassStorage, SubClassMasks[2715]) - 115 * sizeof(MCRegisterClass),
3839 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 115 * sizeof(MCRegisterClass),
3840 .LaneMask: LaneBitmask(0x00000000000003FC),
3841 .AllocationPriority: 0,
3842 .GlobalPriority: false,
3843 .TSFlags: 0x00, /* TSFlags */
3844 .SpillStackID: 0, /* SpillStackID */
3845 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3846 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3847 offsetof(ARMRegisterClassStorage, SuperClasses[609]) - 115 * sizeof(MCRegisterClass),
3848 .SuperClassesSize: 3
3849 },
3850 {
3851 offsetof(ARMRegisterClassStorage, Regs[1234]) - 116 * sizeof(MCRegisterClass),
3852 offsetof(ARMRegisterClassStorage, BitSets[612]) - 116 * sizeof(MCRegisterClass),
3853 .NameIdx: 2,
3854 .RegSizeInBits: 256,
3855 .RegsSize: 8,
3856 .RegSetBegin: 149, /* MinRegVal */
3857 .RegSetSize: 8, /* RegSetSize */
3858 .ID: ARM::QQPR_with_ssub_0RegClassID,
3859 .CopyCost: 1, /* CopyCost */
3860 .Allocatable: true, /* Allocatable */
3861 .BaseClass: false,
3862 offsetof(ARMRegisterClassStorage, SubClassMasks[2730]) - 116 * sizeof(MCRegisterClass),
3863 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[84]) - 116 * sizeof(MCRegisterClass),
3864 .LaneMask: LaneBitmask(0x00000000000003FC),
3865 .AllocationPriority: 0,
3866 .GlobalPriority: false,
3867 .TSFlags: 0x00, /* TSFlags */
3868 .SpillStackID: 0, /* SpillStackID */
3869 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3870 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3871 offsetof(ARMRegisterClassStorage, SuperClasses[612]) - 116 * sizeof(MCRegisterClass),
3872 .SuperClassesSize: 4
3873 },
3874 {
3875 offsetof(ARMRegisterClassStorage, Regs[1242]) - 117 * sizeof(MCRegisterClass),
3876 offsetof(ARMRegisterClassStorage, BitSets[613]) - 117 * sizeof(MCRegisterClass),
3877 .NameIdx: 611,
3878 .RegSizeInBits: 256,
3879 .RegsSize: 7,
3880 .RegSetBegin: 149, /* MinRegVal */
3881 .RegSetSize: 137, /* RegSetSize */
3882 .ID: ARM::DQuad_with_dsub_1_in_DPR_8RegClassID,
3883 .CopyCost: 1, /* CopyCost */
3884 .Allocatable: true, /* Allocatable */
3885 .BaseClass: false,
3886 offsetof(ARMRegisterClassStorage, SubClassMasks[2750]) - 117 * sizeof(MCRegisterClass),
3887 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 117 * sizeof(MCRegisterClass),
3888 .LaneMask: LaneBitmask(0x00000000000003FC),
3889 .AllocationPriority: 0,
3890 .GlobalPriority: false,
3891 .TSFlags: 0x00, /* TSFlags */
3892 .SpillStackID: 0, /* SpillStackID */
3893 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3894 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3895 offsetof(ARMRegisterClassStorage, SuperClasses[616]) - 117 * sizeof(MCRegisterClass),
3896 .SuperClassesSize: 6
3897 },
3898 {
3899 offsetof(ARMRegisterClassStorage, Regs[1249]) - 118 * sizeof(MCRegisterClass),
3900 offsetof(ARMRegisterClassStorage, BitSets[631]) - 118 * sizeof(MCRegisterClass),
3901 .NameIdx: 1795,
3902 .RegSizeInBits: 256,
3903 .RegsSize: 7,
3904 .RegSetBegin: 283, /* MinRegVal */
3905 .RegSetSize: 7, /* RegSetSize */
3906 .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
3907 .CopyCost: 1, /* CopyCost */
3908 .Allocatable: true, /* Allocatable */
3909 .BaseClass: false,
3910 offsetof(ARMRegisterClassStorage, SubClassMasks[2780]) - 118 * sizeof(MCRegisterClass),
3911 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 118 * sizeof(MCRegisterClass),
3912 .LaneMask: LaneBitmask(0x00000000000003FC),
3913 .AllocationPriority: 0,
3914 .GlobalPriority: false,
3915 .TSFlags: 0x00, /* TSFlags */
3916 .SpillStackID: 0, /* SpillStackID */
3917 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3918 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3919 offsetof(ARMRegisterClassStorage, SuperClasses[622]) - 118 * sizeof(MCRegisterClass),
3920 .SuperClassesSize: 6
3921 },
3922 {
3923 offsetof(ARMRegisterClassStorage, Regs[1256]) - 119 * sizeof(MCRegisterClass),
3924 offsetof(ARMRegisterClassStorage, BitSets[632]) - 119 * sizeof(MCRegisterClass),
3925 .NameIdx: 1980,
3926 .RegSizeInBits: 256,
3927 .RegsSize: 7,
3928 .RegSetBegin: 149, /* MinRegVal */
3929 .RegSetSize: 7, /* RegSetSize */
3930 .ID: ARM::MQQPRRegClassID,
3931 .CopyCost: 1, /* CopyCost */
3932 .Allocatable: true, /* Allocatable */
3933 .BaseClass: false,
3934 offsetof(ARMRegisterClassStorage, SubClassMasks[2795]) - 119 * sizeof(MCRegisterClass),
3935 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[84]) - 119 * sizeof(MCRegisterClass),
3936 .LaneMask: LaneBitmask(0x00000000000003FC),
3937 .AllocationPriority: 0,
3938 .GlobalPriority: false,
3939 .TSFlags: 0x00, /* TSFlags */
3940 .SpillStackID: 0, /* SpillStackID */
3941 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3942 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3943 offsetof(ARMRegisterClassStorage, SuperClasses[628]) - 119 * sizeof(MCRegisterClass),
3944 .SuperClassesSize: 7
3945 },
3946 {
3947 offsetof(ARMRegisterClassStorage, Regs[1263]) - 120 * sizeof(MCRegisterClass),
3948 offsetof(ARMRegisterClassStorage, BitSets[633]) - 120 * sizeof(MCRegisterClass),
3949 .NameIdx: 888,
3950 .RegSizeInBits: 256,
3951 .RegsSize: 6,
3952 .RegSetBegin: 149, /* MinRegVal */
3953 .RegSetSize: 137, /* RegSetSize */
3954 .ID: ARM::DQuad_with_dsub_2_in_DPR_8RegClassID,
3955 .CopyCost: 1, /* CopyCost */
3956 .Allocatable: true, /* Allocatable */
3957 .BaseClass: false,
3958 offsetof(ARMRegisterClassStorage, SubClassMasks[2815]) - 120 * sizeof(MCRegisterClass),
3959 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 120 * sizeof(MCRegisterClass),
3960 .LaneMask: LaneBitmask(0x00000000000003FC),
3961 .AllocationPriority: 0,
3962 .GlobalPriority: false,
3963 .TSFlags: 0x00, /* TSFlags */
3964 .SpillStackID: 0, /* SpillStackID */
3965 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3966 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3967 offsetof(ARMRegisterClassStorage, SuperClasses[635]) - 120 * sizeof(MCRegisterClass),
3968 .SuperClassesSize: 7
3969 },
3970 {
3971 offsetof(ARMRegisterClassStorage, Regs[1269]) - 121 * sizeof(MCRegisterClass),
3972 offsetof(ARMRegisterClassStorage, BitSets[651]) - 121 * sizeof(MCRegisterClass),
3973 .NameIdx: 1773,
3974 .RegSizeInBits: 256,
3975 .RegsSize: 6,
3976 .RegSetBegin: 283, /* MinRegVal */
3977 .RegSetSize: 6, /* RegSetSize */
3978 .ID: ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
3979 .CopyCost: 1, /* CopyCost */
3980 .Allocatable: true, /* Allocatable */
3981 .BaseClass: false,
3982 offsetof(ARMRegisterClassStorage, SubClassMasks[2845]) - 121 * sizeof(MCRegisterClass),
3983 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 121 * sizeof(MCRegisterClass),
3984 .LaneMask: LaneBitmask(0x00000000000003FC),
3985 .AllocationPriority: 0,
3986 .GlobalPriority: false,
3987 .TSFlags: 0x00, /* TSFlags */
3988 .SpillStackID: 0, /* SpillStackID */
3989 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3990 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3991 offsetof(ARMRegisterClassStorage, SuperClasses[642]) - 121 * sizeof(MCRegisterClass),
3992 .SuperClassesSize: 8
3993 },
3994 {
3995 offsetof(ARMRegisterClassStorage, Regs[1275]) - 122 * sizeof(MCRegisterClass),
3996 offsetof(ARMRegisterClassStorage, BitSets[652]) - 122 * sizeof(MCRegisterClass),
3997 .NameIdx: 1032,
3998 .RegSizeInBits: 256,
3999 .RegsSize: 5,
4000 .RegSetBegin: 149, /* MinRegVal */
4001 .RegSetSize: 136, /* RegSetSize */
4002 .ID: ARM::DQuad_with_dsub_3_in_DPR_8RegClassID,
4003 .CopyCost: 1, /* CopyCost */
4004 .Allocatable: true, /* Allocatable */
4005 .BaseClass: false,
4006 offsetof(ARMRegisterClassStorage, SubClassMasks[2860]) - 122 * sizeof(MCRegisterClass),
4007 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[88]) - 122 * sizeof(MCRegisterClass),
4008 .LaneMask: LaneBitmask(0x00000000000003FC),
4009 .AllocationPriority: 0,
4010 .GlobalPriority: false,
4011 .TSFlags: 0x00, /* TSFlags */
4012 .SpillStackID: 0, /* SpillStackID */
4013 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4014 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4015 offsetof(ARMRegisterClassStorage, SuperClasses[650]) - 122 * sizeof(MCRegisterClass),
4016 .SuperClassesSize: 8
4017 },
4018 {
4019 offsetof(ARMRegisterClassStorage, Regs[1280]) - 123 * sizeof(MCRegisterClass),
4020 offsetof(ARMRegisterClassStorage, BitSets[669]) - 123 * sizeof(MCRegisterClass),
4021 .NameIdx: 1842,
4022 .RegSizeInBits: 256,
4023 .RegsSize: 4,
4024 .RegSetBegin: 283, /* MinRegVal */
4025 .RegSetSize: 4, /* RegSetSize */
4026 .ID: ARM::DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
4027 .CopyCost: 1, /* CopyCost */
4028 .Allocatable: true, /* Allocatable */
4029 .BaseClass: false,
4030 offsetof(ARMRegisterClassStorage, SubClassMasks[2890]) - 123 * sizeof(MCRegisterClass),
4031 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 123 * sizeof(MCRegisterClass),
4032 .LaneMask: LaneBitmask(0x00000000000003FC),
4033 .AllocationPriority: 0,
4034 .GlobalPriority: false,
4035 .TSFlags: 0x00, /* TSFlags */
4036 .SpillStackID: 0, /* SpillStackID */
4037 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4038 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4039 offsetof(ARMRegisterClassStorage, SuperClasses[658]) - 123 * sizeof(MCRegisterClass),
4040 .SuperClassesSize: 10
4041 },
4042 {
4043 offsetof(ARMRegisterClassStorage, Regs[1284]) - 124 * sizeof(MCRegisterClass),
4044 offsetof(ARMRegisterClassStorage, BitSets[670]) - 124 * sizeof(MCRegisterClass),
4045 .NameIdx: 1145,
4046 .RegSizeInBits: 256,
4047 .RegsSize: 4,
4048 .RegSetBegin: 149, /* MinRegVal */
4049 .RegSetSize: 4, /* RegSetSize */
4050 .ID: ARM::MQQPR_with_qsub_0_in_QPR_8RegClassID,
4051 .CopyCost: 1, /* CopyCost */
4052 .Allocatable: true, /* Allocatable */
4053 .BaseClass: false,
4054 offsetof(ARMRegisterClassStorage, SubClassMasks[2905]) - 124 * sizeof(MCRegisterClass),
4055 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[84]) - 124 * sizeof(MCRegisterClass),
4056 .LaneMask: LaneBitmask(0x00000000000003FC),
4057 .AllocationPriority: 0,
4058 .GlobalPriority: false,
4059 .TSFlags: 0x00, /* TSFlags */
4060 .SpillStackID: 0, /* SpillStackID */
4061 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4062 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4063 offsetof(ARMRegisterClassStorage, SuperClasses[668]) - 124 * sizeof(MCRegisterClass),
4064 .SuperClassesSize: 10
4065 },
4066 {
4067 offsetof(ARMRegisterClassStorage, Regs[1288]) - 125 * sizeof(MCRegisterClass),
4068 offsetof(ARMRegisterClassStorage, BitSets[671]) - 125 * sizeof(MCRegisterClass),
4069 .NameIdx: 1230,
4070 .RegSizeInBits: 256,
4071 .RegsSize: 3,
4072 .RegSetBegin: 283, /* MinRegVal */
4073 .RegSetSize: 3, /* RegSetSize */
4074 .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID,
4075 .CopyCost: 1, /* CopyCost */
4076 .Allocatable: true, /* Allocatable */
4077 .BaseClass: false,
4078 offsetof(ARMRegisterClassStorage, SubClassMasks[2925]) - 125 * sizeof(MCRegisterClass),
4079 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 125 * sizeof(MCRegisterClass),
4080 .LaneMask: LaneBitmask(0x00000000000003FC),
4081 .AllocationPriority: 0,
4082 .GlobalPriority: false,
4083 .TSFlags: 0x00, /* TSFlags */
4084 .SpillStackID: 0, /* SpillStackID */
4085 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4086 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4087 offsetof(ARMRegisterClassStorage, SuperClasses[678]) - 125 * sizeof(MCRegisterClass),
4088 .SuperClassesSize: 13
4089 },
4090 {
4091 offsetof(ARMRegisterClassStorage, Regs[1291]) - 126 * sizeof(MCRegisterClass),
4092 offsetof(ARMRegisterClassStorage, BitSets[672]) - 126 * sizeof(MCRegisterClass),
4093 .NameIdx: 718,
4094 .RegSizeInBits: 256,
4095 .RegsSize: 3,
4096 .RegSetBegin: 149, /* MinRegVal */
4097 .RegSetSize: 3, /* RegSetSize */
4098 .ID: ARM::MQQPR_with_dsub_2_in_DPR_8RegClassID,
4099 .CopyCost: 1, /* CopyCost */
4100 .Allocatable: true, /* Allocatable */
4101 .BaseClass: false,
4102 offsetof(ARMRegisterClassStorage, SubClassMasks[2940]) - 126 * sizeof(MCRegisterClass),
4103 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[84]) - 126 * sizeof(MCRegisterClass),
4104 .LaneMask: LaneBitmask(0x00000000000003FC),
4105 .AllocationPriority: 0,
4106 .GlobalPriority: false,
4107 .TSFlags: 0x00, /* TSFlags */
4108 .SpillStackID: 0, /* SpillStackID */
4109 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4110 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4111 offsetof(ARMRegisterClassStorage, SuperClasses[691]) - 126 * sizeof(MCRegisterClass),
4112 .SuperClassesSize: 13
4113 },
4114 {
4115 offsetof(ARMRegisterClassStorage, Regs[1294]) - 127 * sizeof(MCRegisterClass),
4116 offsetof(ARMRegisterClassStorage, BitSets[673]) - 127 * sizeof(MCRegisterClass),
4117 .NameIdx: 915,
4118 .RegSizeInBits: 256,
4119 .RegsSize: 2,
4120 .RegSetBegin: 283, /* MinRegVal */
4121 .RegSetSize: 2, /* RegSetSize */
4122 .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID,
4123 .CopyCost: 1, /* CopyCost */
4124 .Allocatable: true, /* Allocatable */
4125 .BaseClass: false,
4126 offsetof(ARMRegisterClassStorage, SubClassMasks[2960]) - 127 * sizeof(MCRegisterClass),
4127 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[50]) - 127 * sizeof(MCRegisterClass),
4128 .LaneMask: LaneBitmask(0x00000000000003FC),
4129 .AllocationPriority: 0,
4130 .GlobalPriority: false,
4131 .TSFlags: 0x00, /* TSFlags */
4132 .SpillStackID: 0, /* SpillStackID */
4133 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4134 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4135 offsetof(ARMRegisterClassStorage, SuperClasses[704]) - 127 * sizeof(MCRegisterClass),
4136 .SuperClassesSize: 15
4137 },
4138 {
4139 offsetof(ARMRegisterClassStorage, Regs[1296]) - 128 * sizeof(MCRegisterClass),
4140 offsetof(ARMRegisterClassStorage, BitSets[674]) - 128 * sizeof(MCRegisterClass),
4141 .NameIdx: 1987,
4142 .RegSizeInBits: 512,
4143 .RegsSize: 13,
4144 .RegSetBegin: 164, /* MinRegVal */
4145 .RegSetSize: 13, /* RegSetSize */
4146 .ID: ARM::QQQQPRRegClassID,
4147 .CopyCost: 1, /* CopyCost */
4148 .Allocatable: true, /* Allocatable */
4149 .BaseClass: false,
4150 offsetof(ARMRegisterClassStorage, SubClassMasks[2975]) - 128 * sizeof(MCRegisterClass),
4151 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 128 * sizeof(MCRegisterClass),
4152 .LaneMask: LaneBitmask(0x000000000003FFFC),
4153 .AllocationPriority: 0,
4154 .GlobalPriority: false,
4155 .TSFlags: 0x00, /* TSFlags */
4156 .SpillStackID: 0, /* SpillStackID */
4157 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4158 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4159 offsetof(ARMRegisterClassStorage, SuperClasses[719]) - 128 * sizeof(MCRegisterClass),
4160 .SuperClassesSize: 0
4161 },
4162 {
4163 offsetof(ARMRegisterClassStorage, Regs[1309]) - 129 * sizeof(MCRegisterClass),
4164 offsetof(ARMRegisterClassStorage, BitSets[676]) - 129 * sizeof(MCRegisterClass),
4165 .NameIdx: 0,
4166 .RegSizeInBits: 512,
4167 .RegsSize: 8,
4168 .RegSetBegin: 164, /* MinRegVal */
4169 .RegSetSize: 8, /* RegSetSize */
4170 .ID: ARM::QQQQPR_with_ssub_0RegClassID,
4171 .CopyCost: 1, /* CopyCost */
4172 .Allocatable: true, /* Allocatable */
4173 .BaseClass: false,
4174 offsetof(ARMRegisterClassStorage, SubClassMasks[2980]) - 129 * sizeof(MCRegisterClass),
4175 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 129 * sizeof(MCRegisterClass),
4176 .LaneMask: LaneBitmask(0x000000000003FFFC),
4177 .AllocationPriority: 0,
4178 .GlobalPriority: false,
4179 .TSFlags: 0x00, /* TSFlags */
4180 .SpillStackID: 0, /* SpillStackID */
4181 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4182 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4183 offsetof(ARMRegisterClassStorage, SuperClasses[719]) - 129 * sizeof(MCRegisterClass),
4184 .SuperClassesSize: 1
4185 },
4186 {
4187 offsetof(ARMRegisterClassStorage, Regs[1317]) - 130 * sizeof(MCRegisterClass),
4188 offsetof(ARMRegisterClassStorage, BitSets[677]) - 130 * sizeof(MCRegisterClass),
4189 .NameIdx: 296,
4190 .RegSizeInBits: 512,
4191 .RegsSize: 7,
4192 .RegSetBegin: 164, /* MinRegVal */
4193 .RegSetSize: 7, /* RegSetSize */
4194 .ID: ARM::QQQQPR_with_ssub_4RegClassID,
4195 .CopyCost: 1, /* CopyCost */
4196 .Allocatable: true, /* Allocatable */
4197 .BaseClass: false,
4198 offsetof(ARMRegisterClassStorage, SubClassMasks[2985]) - 130 * sizeof(MCRegisterClass),
4199 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 130 * sizeof(MCRegisterClass),
4200 .LaneMask: LaneBitmask(0x000000000003FFFC),
4201 .AllocationPriority: 0,
4202 .GlobalPriority: false,
4203 .TSFlags: 0x00, /* TSFlags */
4204 .SpillStackID: 0, /* SpillStackID */
4205 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4206 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4207 offsetof(ARMRegisterClassStorage, SuperClasses[720]) - 130 * sizeof(MCRegisterClass),
4208 .SuperClassesSize: 2
4209 },
4210 {
4211 offsetof(ARMRegisterClassStorage, Regs[1324]) - 131 * sizeof(MCRegisterClass),
4212 offsetof(ARMRegisterClassStorage, BitSets[678]) - 131 * sizeof(MCRegisterClass),
4213 .NameIdx: 1371,
4214 .RegSizeInBits: 512,
4215 .RegsSize: 6,
4216 .RegSetBegin: 164, /* MinRegVal */
4217 .RegSetSize: 6, /* RegSetSize */
4218 .ID: ARM::QQQQPR_with_ssub_8RegClassID,
4219 .CopyCost: 1, /* CopyCost */
4220 .Allocatable: true, /* Allocatable */
4221 .BaseClass: false,
4222 offsetof(ARMRegisterClassStorage, SubClassMasks[2990]) - 131 * sizeof(MCRegisterClass),
4223 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 131 * sizeof(MCRegisterClass),
4224 .LaneMask: LaneBitmask(0x000000000003FFFC),
4225 .AllocationPriority: 0,
4226 .GlobalPriority: false,
4227 .TSFlags: 0x00, /* TSFlags */
4228 .SpillStackID: 0, /* SpillStackID */
4229 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4230 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4231 offsetof(ARMRegisterClassStorage, SuperClasses[722]) - 131 * sizeof(MCRegisterClass),
4232 .SuperClassesSize: 3
4233 },
4234 {
4235 offsetof(ARMRegisterClassStorage, Regs[1330]) - 132 * sizeof(MCRegisterClass),
4236 offsetof(ARMRegisterClassStorage, BitSets[679]) - 132 * sizeof(MCRegisterClass),
4237 .NameIdx: 1986,
4238 .RegSizeInBits: 512,
4239 .RegsSize: 5,
4240 .RegSetBegin: 164, /* MinRegVal */
4241 .RegSetSize: 5, /* RegSetSize */
4242 .ID: ARM::MQQQQPRRegClassID,
4243 .CopyCost: 1, /* CopyCost */
4244 .Allocatable: true, /* Allocatable */
4245 .BaseClass: false,
4246 offsetof(ARMRegisterClassStorage, SubClassMasks[2995]) - 132 * sizeof(MCRegisterClass),
4247 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 132 * sizeof(MCRegisterClass),
4248 .LaneMask: LaneBitmask(0x000000000003FFFC),
4249 .AllocationPriority: 0,
4250 .GlobalPriority: false,
4251 .TSFlags: 0x00, /* TSFlags */
4252 .SpillStackID: 0, /* SpillStackID */
4253 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4254 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4255 offsetof(ARMRegisterClassStorage, SuperClasses[725]) - 132 * sizeof(MCRegisterClass),
4256 .SuperClassesSize: 4
4257 },
4258 {
4259 offsetof(ARMRegisterClassStorage, Regs[1335]) - 133 * sizeof(MCRegisterClass),
4260 offsetof(ARMRegisterClassStorage, BitSets[680]) - 133 * sizeof(MCRegisterClass),
4261 .NameIdx: 1121,
4262 .RegSizeInBits: 512,
4263 .RegsSize: 4,
4264 .RegSetBegin: 164, /* MinRegVal */
4265 .RegSetSize: 4, /* RegSetSize */
4266 .ID: ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID,
4267 .CopyCost: 1, /* CopyCost */
4268 .Allocatable: true, /* Allocatable */
4269 .BaseClass: false,
4270 offsetof(ARMRegisterClassStorage, SubClassMasks[3000]) - 133 * sizeof(MCRegisterClass),
4271 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 133 * sizeof(MCRegisterClass),
4272 .LaneMask: LaneBitmask(0x000000000003FFFC),
4273 .AllocationPriority: 0,
4274 .GlobalPriority: false,
4275 .TSFlags: 0x00, /* TSFlags */
4276 .SpillStackID: 0, /* SpillStackID */
4277 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4278 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4279 offsetof(ARMRegisterClassStorage, SuperClasses[729]) - 133 * sizeof(MCRegisterClass),
4280 .SuperClassesSize: 5
4281 },
4282 {
4283 offsetof(ARMRegisterClassStorage, Regs[1339]) - 134 * sizeof(MCRegisterClass),
4284 offsetof(ARMRegisterClassStorage, BitSets[681]) - 134 * sizeof(MCRegisterClass),
4285 .NameIdx: 694,
4286 .RegSizeInBits: 512,
4287 .RegsSize: 3,
4288 .RegSetBegin: 164, /* MinRegVal */
4289 .RegSetSize: 3, /* RegSetSize */
4290 .ID: ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8RegClassID,
4291 .CopyCost: 1, /* CopyCost */
4292 .Allocatable: true, /* Allocatable */
4293 .BaseClass: false,
4294 offsetof(ARMRegisterClassStorage, SubClassMasks[3005]) - 134 * sizeof(MCRegisterClass),
4295 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 134 * sizeof(MCRegisterClass),
4296 .LaneMask: LaneBitmask(0x000000000003FFFC),
4297 .AllocationPriority: 0,
4298 .GlobalPriority: false,
4299 .TSFlags: 0x00, /* TSFlags */
4300 .SpillStackID: 0, /* SpillStackID */
4301 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4302 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4303 offsetof(ARMRegisterClassStorage, SuperClasses[734]) - 134 * sizeof(MCRegisterClass),
4304 .SuperClassesSize: 6
4305 },
4306 {
4307 offsetof(ARMRegisterClassStorage, Regs[1342]) - 135 * sizeof(MCRegisterClass),
4308 offsetof(ARMRegisterClassStorage, BitSets[682]) - 135 * sizeof(MCRegisterClass),
4309 .NameIdx: 1201,
4310 .RegSizeInBits: 512,
4311 .RegsSize: 2,
4312 .RegSetBegin: 164, /* MinRegVal */
4313 .RegSetSize: 2, /* RegSetSize */
4314 .ID: ARM::MQQQQPR_with_qsub_2_in_QPR_8RegClassID,
4315 .CopyCost: 1, /* CopyCost */
4316 .Allocatable: true, /* Allocatable */
4317 .BaseClass: false,
4318 offsetof(ARMRegisterClassStorage, SubClassMasks[3010]) - 135 * sizeof(MCRegisterClass),
4319 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 135 * sizeof(MCRegisterClass),
4320 .LaneMask: LaneBitmask(0x000000000003FFFC),
4321 .AllocationPriority: 0,
4322 .GlobalPriority: false,
4323 .TSFlags: 0x00, /* TSFlags */
4324 .SpillStackID: 0, /* SpillStackID */
4325 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4326 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4327 offsetof(ARMRegisterClassStorage, SuperClasses[740]) - 135 * sizeof(MCRegisterClass),
4328 .SuperClassesSize: 7
4329 },
4330 {
4331 offsetof(ARMRegisterClassStorage, Regs[1344]) - 136 * sizeof(MCRegisterClass),
4332 offsetof(ARMRegisterClassStorage, BitSets[683]) - 136 * sizeof(MCRegisterClass),
4333 .NameIdx: 745,
4334 .RegSizeInBits: 512,
4335 .RegsSize: 1,
4336 .RegSetBegin: 164, /* MinRegVal */
4337 .RegSetSize: 1, /* RegSetSize */
4338 .ID: ARM::MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8RegClassID,
4339 .CopyCost: 1, /* CopyCost */
4340 .Allocatable: true, /* Allocatable */
4341 .BaseClass: false,
4342 offsetof(ARMRegisterClassStorage, SubClassMasks[3015]) - 136 * sizeof(MCRegisterClass),
4343 offsetof(ARMRegisterClassStorage, SuperRegIdxSeqs[8]) - 136 * sizeof(MCRegisterClass),
4344 .LaneMask: LaneBitmask(0x000000000003FFFC),
4345 .AllocationPriority: 0,
4346 .GlobalPriority: false,
4347 .TSFlags: 0x00, /* TSFlags */
4348 .SpillStackID: 0, /* SpillStackID */
4349 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4350 .CoveredBySubRegs: true, /* CoveredBySubRegs */
4351 offsetof(ARMRegisterClassStorage, SuperClasses[747]) - 136 * sizeof(MCRegisterClass),
4352 .SuperClassesSize: 8
4353 },
4354 },
4355 .Regs: {
4356 /* 0 */ ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31,
4357 /* 32 */ ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::VPR,
4358 /* 97 */ ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31,
4359 /* 129 */ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15,
4360 /* 145 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
4361 /* 161 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV,
4362 /* 177 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::ZR,
4363 /* 193 */ ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15,
4364 /* 209 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
4365 /* 224 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::PC,
4366 /* 239 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR_NZCV,
4367 /* 254 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR,
4368 /* 269 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::ZR,
4369 /* 284 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC,
4370 /* 298 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
4371 /* 312 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP,
4372 /* 325 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::PC,
4373 /* 338 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11,
4374 /* 350 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC,
4375 /* 359 */ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7,
4376 /* 367 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
4377 /* 375 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4378 /* 383 */ ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, ARM::R12, ARM::LR,
4379 /* 391 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
4380 /* 398 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::PC,
4381 /* 405 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC,
4382 /* 411 */ ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
4383 /* 417 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
4384 /* 423 */ ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
4385 /* 429 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP,
4386 /* 434 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::PC,
4387 /* 439 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12,
4388 /* 444 */ ARM::R8, ARM::R9, ARM::R10, ARM::R11,
4389 /* 448 */ ARM::R8, ARM::R10, ARM::R12, ARM::LR,
4390 /* 452 */ ARM::R0, ARM::R2, ARM::R4, ARM::R6,
4391 /* 456 */ ARM::R1, ARM::R3, ARM::R5, ARM::R7,
4392 /* 460 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4393 /* 464 */ ARM::R0, ARM::R2, ARM::R12,
4394 /* 467 */ ARM::FPSCR, ARM::FPEXC,
4395 /* 469 */ ARM::R8, ARM::R10,
4396 /* 471 */ ARM::R9, ARM::R11,
4397 /* 473 */ ARM::R0, ARM::R2,
4398 /* 475 */ ARM::R1, ARM::R3,
4399 /* 477 */ ARM::CPSR,
4400 /* 478 */ ARM::FPCXTNS,
4401 /* 479 */ ARM::LR,
4402 /* 480 */ ARM::SP,
4403 /* 481 */ ARM::VPR,
4404 /* 482 */ ARM::FPSCR_NZCV,
4405 /* 483 */ ARM::PC,
4406 /* 484 */ ARM::R12,
4407 /* 485 */ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31,
4408 /* 517 */ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15,
4409 /* 533 */ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7,
4410 /* 541 */ ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, ARM::R12_SP,
4411 /* 548 */ ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11,
4412 /* 554 */ ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
4413 /* 558 */ ARM::R8_R9, ARM::R10_R11, ARM::R12_SP,
4414 /* 561 */ ARM::R0_R1, ARM::R2_R3, ARM::R12_SP,
4415 /* 564 */ ARM::R0_R1, ARM::R2_R3,
4416 /* 566 */ ARM::R8_R9, ARM::R10_R11,
4417 /* 568 */ ARM::R12_SP,
4418 /* 569 */ ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D28_D30, ARM::D29_D31,
4419 /* 599 */ ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
4420 /* 615 */ ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15,
4421 /* 629 */ ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
4422 /* 637 */ ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7,
4423 /* 643 */ ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q15,
4424 /* 674 */ ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16,
4425 /* 690 */ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15,
4426 /* 706 */ ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7,
4427 /* 721 */ ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8,
4428 /* 729 */ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
4429 /* 737 */ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
4430 /* 745 */ ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3,
4431 /* 752 */ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
4432 /* 756 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, ARM::D16_D17_D18, ARM::D17_D18_D19, ARM::D18_D19_D20, ARM::D19_D20_D21, ARM::D20_D21_D22, ARM::D21_D22_D23, ARM::D22_D23_D24, ARM::D23_D24_D25, ARM::D24_D25_D26, ARM::D25_D26_D27, ARM::D26_D27_D28, ARM::D27_D28_D29, ARM::D28_D29_D30, ARM::D29_D30_D31,
4433 /* 786 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31,
4434 /* 814 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19,
4435 /* 830 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17,
4436 /* 846 */ ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, ARM::D16_D17_D18, ARM::D18_D19_D20, ARM::D20_D21_D22, ARM::D22_D23_D24, ARM::D24_D25_D26, ARM::D26_D27_D28, ARM::D28_D29_D30,
4437 /* 861 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16,
4438 /* 876 */ ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, ARM::D17_D18_D19, ARM::D19_D20_D21, ARM::D21_D22_D23, ARM::D23_D24_D25, ARM::D25_D26_D27, ARM::D27_D28_D29, ARM::D29_D30_D31,
4439 /* 891 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17,
4440 /* 905 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15,
4441 /* 919 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15,
4442 /* 931 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11,
4443 /* 939 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9,
4444 /* 947 */ ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16,
4445 /* 955 */ ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17,
4446 /* 963 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8,
4447 /* 970 */ ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15,
4448 /* 977 */ ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14,
4449 /* 984 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9,
4450 /* 990 */ ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7,
4451 /* 996 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7,
4452 /* 1000 */ ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9,
4453 /* 1004 */ ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8,
4454 /* 1008 */ ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6,
4455 /* 1011 */ ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7,
4456 /* 1014 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31,
4457 /* 1042 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19,
4458 /* 1058 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17,
4459 /* 1072 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15,
4460 /* 1084 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11,
4461 /* 1092 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9,
4462 /* 1098 */ ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7,
4463 /* 1102 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, ARM::Q8_Q9, ARM::D17_D18_D19_D20, ARM::Q9_Q10, ARM::D19_D20_D21_D22, ARM::Q10_Q11, ARM::D21_D22_D23_D24, ARM::Q11_Q12, ARM::D23_D24_D25_D26, ARM::Q12_Q13, ARM::D25_D26_D27_D28, ARM::Q13_Q14, ARM::D27_D28_D29_D30, ARM::Q14_Q15,
4464 /* 1131 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18,
4465 /* 1147 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8,
4466 /* 1162 */ ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15,
4467 /* 1177 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, ARM::D17_D18_D19_D20, ARM::D19_D20_D21_D22, ARM::D21_D22_D23_D24, ARM::D23_D24_D25_D26, ARM::D25_D26_D27_D28, ARM::D27_D28_D29_D30,
4468 /* 1191 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16,
4469 /* 1205 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7,
4470 /* 1218 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10,
4471 /* 1226 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18,
4472 /* 1234 */ ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8,
4473 /* 1242 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4,
4474 /* 1249 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16,
4475 /* 1256 */ ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7,
4476 /* 1263 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8,
4477 /* 1269 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14,
4478 /* 1275 */ ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3,
4479 /* 1280 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10,
4480 /* 1284 */ ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
4481 /* 1288 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8,
4482 /* 1291 */ ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3,
4483 /* 1294 */ ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6,
4484 /* 1296 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15,
4485 /* 1309 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10,
4486 /* 1317 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9,
4487 /* 1324 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8,
4488 /* 1330 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7,
4489 /* 1335 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6,
4490 /* 1339 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
4491 /* 1342 */ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4,
4492 /* 1344 */ ARM::Q0_Q1_Q2_Q3,
4493 },
4494 .BitSets: {
4495 /* 0 */ 0xff, 0xff, 0xff, 0xff,
4496 /* 4 */ 0xfd, 0xff, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
4497 /* 17 */ 0xff, 0xff, 0xff, 0xff,
4498 /* 21 */ 0xff, 0xff,
4499 /* 23 */ 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
4500 /* 33 */ 0x01, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f,
4501 /* 44 */ 0x49, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
4502 /* 54 */ 0xff, 0xff,
4503 /* 56 */ 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
4504 /* 66 */ 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
4505 /* 76 */ 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f,
4506 /* 87 */ 0x01, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
4507 /* 98 */ 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
4508 /* 108 */ 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x7f,
4509 /* 117 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
4510 /* 127 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f,
4511 /* 136 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x7f,
4512 /* 145 */ 0xff, 0x0f,
4513 /* 147 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
4514 /* 156 */ 0xff,
4515 /* 157 */ 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01,
4516 /* 167 */ 0xff,
4517 /* 168 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x01,
4518 /* 178 */ 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01,
4519 /* 188 */ 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01,
4520 /* 198 */ 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
4521 /* 207 */ 0x55, 0x05,
4522 /* 209 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01,
4523 /* 219 */ 0x55, 0x05,
4524 /* 221 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
4525 /* 230 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
4526 /* 239 */ 0x0f, 0x10,
4527 /* 241 */ 0x0f,
4528 /* 242 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x01,
4529 /* 252 */ 0x55,
4530 /* 253 */ 0x55,
4531 /* 254 */ 0x0f,
4532 /* 255 */ 0x05, 0x10,
4533 /* 257 */ 0x05,
4534 /* 258 */ 0x05,
4535 /* 259 */ 0x05,
4536 /* 260 */ 0x05,
4537 /* 261 */ 0x05,
4538 /* 262 */ 0x01,
4539 /* 263 */ 0x01,
4540 /* 264 */ 0x01,
4541 /* 265 */ 0x01,
4542 /* 266 */ 0x01,
4543 /* 267 */ 0x01,
4544 /* 268 */ 0x01,
4545 /* 269 */ 0x01,
4546 /* 270 */ 0xff, 0xff, 0xff, 0xff,
4547 /* 274 */ 0xff, 0xff,
4548 /* 276 */ 0xff,
4549 /* 277 */ 0x7f,
4550 /* 278 */ 0x3f,
4551 /* 279 */ 0x0f,
4552 /* 280 */ 0x07,
4553 /* 281 */ 0x43,
4554 /* 282 */ 0x03,
4555 /* 283 */ 0x03,
4556 /* 284 */ 0x01,
4557 /* 285 */ 0xff, 0xff, 0xff, 0x3f,
4558 /* 289 */ 0xff, 0xff,
4559 /* 291 */ 0xff, 0x3f,
4560 /* 293 */ 0xff,
4561 /* 294 */ 0x3f,
4562 /* 295 */ 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01,
4563 /* 324 */ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
4564 /* 352 */ 0xff, 0xff,
4565 /* 354 */ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01,
4566 /* 382 */ 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
4567 /* 409 */ 0xff,
4568 /* 410 */ 0xff,
4569 /* 411 */ 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
4570 /* 438 */ 0x0f,
4571 /* 439 */ 0xff, 0xff, 0xff, 0x3f,
4572 /* 443 */ 0xff, 0xff, 0xff, 0x0f,
4573 /* 447 */ 0xff, 0xff,
4574 /* 449 */ 0xff, 0xff,
4575 /* 451 */ 0x55, 0x55, 0x55, 0x15,
4576 /* 455 */ 0xff, 0x7f,
4577 /* 457 */ 0x55, 0x55, 0x55, 0x15,
4578 /* 461 */ 0xff, 0x3f,
4579 /* 463 */ 0xff, 0x3f,
4580 /* 465 */ 0xff, 0x0f,
4581 /* 467 */ 0xff,
4582 /* 468 */ 0xff,
4583 /* 469 */ 0x55, 0x55,
4584 /* 471 */ 0x55, 0x55,
4585 /* 473 */ 0x7f,
4586 /* 474 */ 0x55, 0x15,
4587 /* 476 */ 0x55, 0x15,
4588 /* 478 */ 0x3f,
4589 /* 479 */ 0x3f,
4590 /* 480 */ 0x0f,
4591 /* 481 */ 0x55,
4592 /* 482 */ 0x55,
4593 /* 483 */ 0x15,
4594 /* 484 */ 0x15,
4595 /* 485 */ 0xff, 0xff, 0xff, 0x0f,
4596 /* 489 */ 0xff, 0xff,
4597 /* 491 */ 0xff, 0x3f,
4598 /* 493 */ 0xff, 0x0f,
4599 /* 495 */ 0xff,
4600 /* 496 */ 0x3f,
4601 /* 497 */ 0x0f,
4602 /* 498 */ 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
4603 /* 517 */ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
4604 /* 535 */ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f,
4605 /* 553 */ 0xff, 0x7f,
4606 /* 555 */ 0xff, 0x3f,
4607 /* 557 */ 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f,
4608 /* 575 */ 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
4609 /* 593 */ 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
4610 /* 611 */ 0xff,
4611 /* 612 */ 0xff,
4612 /* 613 */ 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x01,
4613 /* 631 */ 0x7f,
4614 /* 632 */ 0x7f,
4615 /* 633 */ 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x01,
4616 /* 651 */ 0x3f,
4617 /* 652 */ 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
4618 /* 669 */ 0x0f,
4619 /* 670 */ 0x0f,
4620 /* 671 */ 0x07,
4621 /* 672 */ 0x07,
4622 /* 673 */ 0x03,
4623 /* 674 */ 0xff, 0x1f,
4624 /* 676 */ 0xff,
4625 /* 677 */ 0x7f,
4626 /* 678 */ 0x3f,
4627 /* 679 */ 0x1f,
4628 /* 680 */ 0x0f,
4629 /* 681 */ 0x07,
4630 /* 682 */ 0x03,
4631 /* 683 */ 0x01,
4632 },
4633 .SubClassMasks: {
4634 // 0 HPR
4635 0x00000085, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4636 0x00080008, 0x80300000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // ssub_0
4637 0x00080008, 0x80300000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // ssub_1
4638 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // ssub_2
4639 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // ssub_3
4640 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // ssub_4
4641 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // ssub_5
4642 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_6
4643 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_7
4644 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_8
4645 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_9
4646 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_10
4647 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_11
4648 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_12
4649 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_13
4650 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_14
4651 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_15
4652 // 85 FPWithVPR
4653 0x0008008e, 0x00388000, 0x00000000, 0x00000000, 0x00000000,
4654 0x00000000, 0xc0000000, 0xffffffff, 0xffffffff, 0x000001ff, // dsub_0
4655 0x00000000, 0x00000000, 0x5f979ff8, 0xfffff80f, 0x000001ff, // dsub_1
4656 0x00000000, 0xc0000000, 0xfffff007, 0xffffffff, 0x000001ff, // dsub_2
4657 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x000001ff, // dsub_3
4658 0x00000000, 0x00000000, 0xa0686000, 0x000007f0, 0x000001ff, // dsub_4
4659 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_5
4660 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_6
4661 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_7
4662 0x00080008, 0x80300000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // ssub_0
4663 0x00080008, 0x80300000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // ssub_1
4664 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // ssub_2
4665 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // ssub_3
4666 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // ssub_4
4667 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // ssub_5
4668 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_6
4669 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_7
4670 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_8
4671 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_9
4672 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_10
4673 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_11
4674 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_12
4675 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_13
4676 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_14
4677 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_15
4678 // 210 SPR
4679 0x00000084, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4680 0x00080008, 0x80300000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // ssub_0
4681 0x00080008, 0x80300000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // ssub_1
4682 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // ssub_2
4683 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // ssub_3
4684 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // ssub_4
4685 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // ssub_5
4686 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_6
4687 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_7
4688 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_8
4689 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_9
4690 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_10
4691 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_11
4692 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_12
4693 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_13
4694 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_14
4695 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_15
4696 // 295 FPWithVPR_with_ssub_0
4697 0x00080008, 0x00300000, 0x00000000, 0x00000000, 0x00000000,
4698 0x00000000, 0x80000000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // dsub_0
4699 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // dsub_1
4700 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // dsub_2
4701 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // dsub_3
4702 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // dsub_4
4703 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // dsub_5
4704 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_6
4705 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_7
4706 // 340 GPR
4707 0xfff7e310, 0x000667bf, 0x00000000, 0x00000000, 0x00000000,
4708 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4709 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4710 // 355 GPRwithAPSR
4711 0xbce2c520, 0x000467bf, 0x00000000, 0x00000000, 0x00000000,
4712 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4713 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4714 // 370 GPRwithZR
4715 0xbce2d140, 0x000467bf, 0x00000000, 0x00000000, 0x00000000,
4716 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4717 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4718 // 385 SPR_8
4719 0x00000080, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4720 0x00080000, 0x00200000, 0xe4c00c86, 0xfd24070f, 0x000001e0, // ssub_0
4721 0x00080000, 0x00200000, 0xe4c00c86, 0xfd24070f, 0x000001e0, // ssub_1
4722 0x00000000, 0x00000000, 0x44000c00, 0xf520000e, 0x000001e0, // ssub_2
4723 0x00000000, 0x00000000, 0x44000c00, 0xf520000e, 0x000001e0, // ssub_3
4724 0x00000000, 0x00000000, 0xe0000004, 0xe500060c, 0x000001c0, // ssub_4
4725 0x00000000, 0x00000000, 0xe0000004, 0xe500060c, 0x000001c0, // ssub_5
4726 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // ssub_6
4727 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // ssub_7
4728 0x00000000, 0x00000000, 0x80000000, 0x00000400, 0x00000180, // ssub_8
4729 0x00000000, 0x00000000, 0x80000000, 0x00000400, 0x00000180, // ssub_9
4730 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_10
4731 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_11
4732 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_12
4733 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_13
4734 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_14
4735 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_15
4736 // 470 GPRnopc
4737 0xbce2c100, 0x000467bf, 0x00000000, 0x00000000, 0x00000000,
4738 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4739 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4740 // 485 GPRnosp
4741 0xdd674200, 0x000627bf, 0x00000000, 0x00000000, 0x00000000,
4742 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4743 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4744 // 500 GPRwithAPSR_NZCVnosp
4745 0x9c624400, 0x000427bf, 0x00000000, 0x00000000, 0x00000000,
4746 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4747 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4748 // 515 GPRwithAPSRnosp
4749 0x9c624800, 0x000427bf, 0x00000000, 0x00000000, 0x00000000,
4750 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4751 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4752 // 530 GPRwithZRnosp
4753 0x9c625000, 0x000427bf, 0x00000000, 0x00000000, 0x00000000,
4754 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4755 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4756 // 545 GPRnoip
4757 0x7627a000, 0x0002479d, 0x00000000, 0x00000000, 0x00000000,
4758 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4759 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4760 // 560 rGPR
4761 0x9c624000, 0x000427bf, 0x00000000, 0x00000000, 0x00000000,
4762 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4763 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4764 // 575 GPRnoip_and_GPRnopc
4765 0x34228000, 0x0000479d, 0x00000000, 0x00000000, 0x00000000,
4766 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4767 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4768 // 590 GPRnoip_and_GPRnosp
4769 0x54270000, 0x0002079d, 0x00000000, 0x00000000, 0x00000000,
4770 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4771 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4772 // 605 GPRnoip_and_GPRwithAPSR_NZCVnosp
4773 0x14220000, 0x0000079d, 0x00000000, 0x00000000, 0x00000000,
4774 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4775 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4776 // 620 tGPRwithpc
4777 0x00240000, 0x0002061c, 0x00000000, 0x00000000, 0x00000000,
4778 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4779 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4780 // 635 FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8
4781 0x00080000, 0x00200000, 0x00000000, 0x00000000, 0x00000000,
4782 0x00000000, 0x00000000, 0xe4c00c86, 0xfd24070f, 0x000001e0, // dsub_0
4783 0x00000000, 0x00000000, 0x44000c00, 0xf520000e, 0x000001e0, // dsub_1
4784 0x00000000, 0x00000000, 0xe0000004, 0xe500060c, 0x000001c0, // dsub_2
4785 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // dsub_3
4786 0x00000000, 0x00000000, 0x80000000, 0x00000400, 0x00000180, // dsub_4
4787 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // dsub_5
4788 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_6
4789 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_7
4790 // 680 hGPR
4791 0x6b900000, 0x00066183, 0x00000000, 0x00000000, 0x00000000,
4792 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4793 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4794 // 695 tGPR
4795 0x00200000, 0x0000061c, 0x00000000, 0x00000000, 0x00000000,
4796 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4797 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4798 // 710 tGPREven
4799 0x04400000, 0x000422a6, 0x00000000, 0x00000000, 0x00000000,
4800 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4801 // 720 GPRnopc_and_hGPR
4802 0x28800000, 0x00046183, 0x00000000, 0x00000000, 0x00000000,
4803 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4804 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4805 // 735 GPRnosp_and_hGPR
4806 0x49000000, 0x00062183, 0x00000000, 0x00000000, 0x00000000,
4807 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4808 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4809 // 750 GPRnoip_and_hGPR
4810 0x62000000, 0x00024181, 0x00000000, 0x00000000, 0x00000000,
4811 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4812 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4813 // 765 GPRnoip_and_tGPREven
4814 0x04000000, 0x00000284, 0x00000000, 0x00000000, 0x00000000,
4815 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4816 // 775 GPRnosp_and_GPRnopc_and_hGPR
4817 0x08000000, 0x00042183, 0x00000000, 0x00000000, 0x00000000,
4818 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4819 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4820 // 790 tGPROdd
4821 0x10000000, 0x00000508, 0x00000000, 0x00000000, 0x00000000,
4822 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4823 // 800 GPRnopc_and_GPRnoip_and_hGPR
4824 0x20000000, 0x00004181, 0x00000000, 0x00000000, 0x00000000,
4825 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4826 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4827 // 815 GPRnosp_and_GPRnoip_and_hGPR
4828 0x40000000, 0x00020181, 0x00000000, 0x00000000, 0x00000000,
4829 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4830 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4831 // 830 tcGPR
4832 0x80000000, 0x00040630, 0x00000000, 0x00000000, 0x00000000,
4833 0x00000000, 0x2c000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4834 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4835 // 845 GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR
4836 0x00000000, 0x00000181, 0x00000000, 0x00000000, 0x00000000,
4837 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4838 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4839 // 860 hGPR_and_tGPREven
4840 0x00000000, 0x00042082, 0x00000000, 0x00000000, 0x00000000,
4841 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4842 // 870 tGPR_and_tGPREven
4843 0x00000000, 0x00000204, 0x00000000, 0x00000000, 0x00000000,
4844 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4845 // 880 tGPR_and_tGPROdd
4846 0x00000000, 0x00000408, 0x00000000, 0x00000000, 0x00000000,
4847 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4848 // 890 tcGPRnotr12
4849 0x00000000, 0x00000610, 0x00000000, 0x00000000, 0x00000000,
4850 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4851 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4852 // 905 tGPREven_and_tcGPR
4853 0x00000000, 0x00040220, 0x00000000, 0x00000000, 0x00000000,
4854 0x00000000, 0x2c000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4855 // 915 FP_STATUS_REGS
4856 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00000000,
4857 // 920 hGPR_and_GPRnoip_and_tGPREven
4858 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
4859 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4860 // 930 hGPR_and_tGPROdd
4861 0x00000000, 0x00000100, 0x00000000, 0x00000000, 0x00000000,
4862 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4863 // 940 tGPREven_and_tcGPRnotr12
4864 0x00000000, 0x00000200, 0x00000000, 0x00000000, 0x00000000,
4865 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4866 // 950 tGPROdd_and_tcGPR
4867 0x00000000, 0x00000400, 0x00000000, 0x00000000, 0x00000000,
4868 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4869 // 960 CCR
4870 0x00000000, 0x00000800, 0x00000000, 0x00000000, 0x00000000,
4871 // 965 FPCXTRegs
4872 0x00000000, 0x00001000, 0x00000000, 0x00000000, 0x00000000,
4873 // 970 GPRlr
4874 0x00000000, 0x00002000, 0x00000000, 0x00000000, 0x00000000,
4875 // 975 GPRsp
4876 0x00000000, 0x00004000, 0x00000000, 0x00000000, 0x00000000,
4877 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
4878 // 985 VCCR
4879 0x00000000, 0x00008000, 0x00000000, 0x00000000, 0x00000000,
4880 // 990 cl_FPSCR_NZCV
4881 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000,
4882 // 995 hGPR_and_tGPRwithpc
4883 0x00000000, 0x00020000, 0x00000000, 0x00000000, 0x00000000,
4884 // 1000 hGPR_and_tcGPR
4885 0x00000000, 0x00040000, 0x00000000, 0x00000000, 0x00000000,
4886 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
4887 // 1010 DPR
4888 0x00000000, 0x00380000, 0x00000000, 0x00000000, 0x00000000,
4889 0x00000000, 0xc0000000, 0xffffffff, 0xffffffff, 0x000001ff, // dsub_0
4890 0x00000000, 0x00000000, 0x5f979ff8, 0xfffff80f, 0x000001ff, // dsub_1
4891 0x00000000, 0xc0000000, 0xfffff007, 0xffffffff, 0x000001ff, // dsub_2
4892 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x000001ff, // dsub_3
4893 0x00000000, 0x00000000, 0xa0686000, 0x000007f0, 0x000001ff, // dsub_4
4894 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_5
4895 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_6
4896 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_7
4897 // 1055 DPR_VFP2
4898 0x00000000, 0x00300000, 0x00000000, 0x00000000, 0x00000000,
4899 0x00000000, 0x80000000, 0xfffacfd7, 0xffff37ef, 0x000001fe, // dsub_0
4900 0x00000000, 0x00000000, 0x5d920fc0, 0xfff7200f, 0x000001fe, // dsub_1
4901 0x00000000, 0x00000000, 0xfcf80007, 0xffe707cf, 0x000001fc, // dsub_2
4902 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // dsub_3
4903 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // dsub_4
4904 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // dsub_5
4905 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_6
4906 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_7
4907 // 1100 DPR_8
4908 0x00000000, 0x00200000, 0x00000000, 0x00000000, 0x00000000,
4909 0x00000000, 0x00000000, 0xe4c00c86, 0xfd24070f, 0x000001e0, // dsub_0
4910 0x00000000, 0x00000000, 0x44000c00, 0xf520000e, 0x000001e0, // dsub_1
4911 0x00000000, 0x00000000, 0xe0000004, 0xe500060c, 0x000001c0, // dsub_2
4912 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // dsub_3
4913 0x00000000, 0x00000000, 0x80000000, 0x00000400, 0x00000180, // dsub_4
4914 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // dsub_5
4915 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_6
4916 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_7
4917 // 1145 GPRPair
4918 0x00000000, 0x3fc00000, 0x00000000, 0x00000000, 0x00000000,
4919 // 1150 GPRPairnosp
4920 0x00000000, 0x19800000, 0x00000000, 0x00000000, 0x00000000,
4921 // 1155 GPRPair_with_gsub_0_in_tGPR
4922 0x00000000, 0x09000000, 0x00000000, 0x00000000, 0x00000000,
4923 // 1160 GPRPair_with_gsub_0_in_hGPR
4924 0x00000000, 0x32000000, 0x00000000, 0x00000000, 0x00000000,
4925 // 1165 GPRPair_with_gsub_0_in_tcGPR
4926 0x00000000, 0x2c000000, 0x00000000, 0x00000000, 0x00000000,
4927 // 1170 GPRPair_with_gsub_0_in_tcGPRnotr12
4928 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000,
4929 // 1175 GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR
4930 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000,
4931 // 1180 GPRPair_with_gsub_1_in_GPRsp
4932 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000,
4933 // 1185 DPairSpc
4934 0x00000000, 0xc0000000, 0x00000007, 0x00000000, 0x00000000,
4935 0x00000000, 0x00000000, 0xfffff000, 0xffffffff, 0x000001ff, // ssub_0_ssub_1_ssub_4_ssub_5
4936 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x000001ff, // ssub_2_ssub_3_ssub_6_ssub_7
4937 0x00000000, 0x00000000, 0xa0686000, 0x000007f0, 0x000001ff, // ssub_4_ssub_5_ssub_8_ssub_9
4938 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_8_ssub_9_ssub_12_ssub_13
4939 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_5_dsub_7
4940 // 1215 DPairSpc_with_ssub_0
4941 0x00000000, 0x80000000, 0x00000007, 0x00000000, 0x00000000,
4942 0x00000000, 0x00000000, 0xfffac000, 0xffff37ef, 0x000001fe, // ssub_0_ssub_1_ssub_4_ssub_5
4943 0x00000000, 0x00000000, 0x00000000, 0xfff72000, 0x000001fe, // ssub_2_ssub_3_ssub_6_ssub_7
4944 0x00000000, 0x00000000, 0xa0680000, 0x000007c0, 0x000001fc, // ssub_4_ssub_5_ssub_8_ssub_9
4945 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_8_ssub_9_ssub_12_ssub_13
4946 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // dsub_5_dsub_7
4947 // 1245 DPairSpc_with_ssub_4
4948 0x00000000, 0x00000000, 0x00000007, 0x00000000, 0x00000000,
4949 0x00000000, 0x00000000, 0xfcf80000, 0xffe707cf, 0x000001fc, // ssub_0_ssub_1_ssub_4_ssub_5
4950 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_2_ssub_3_ssub_6_ssub_7
4951 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x000001f8, // ssub_4_ssub_5_ssub_8_ssub_9
4952 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_8_ssub_9_ssub_12_ssub_13
4953 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_5_dsub_7
4954 // 1275 DPairSpc_with_dsub_0_in_DPR_8
4955 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000,
4956 0x00000000, 0x00000000, 0xe4c00000, 0xfd24070f, 0x000001e0, // ssub_0_ssub_1_ssub_4_ssub_5
4957 0x00000000, 0x00000000, 0x00000000, 0xf5200000, 0x000001e0, // ssub_2_ssub_3_ssub_6_ssub_7
4958 0x00000000, 0x00000000, 0xa0000000, 0x00000600, 0x000001c0, // ssub_4_ssub_5_ssub_8_ssub_9
4959 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_8_ssub_9_ssub_12_ssub_13
4960 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // dsub_5_dsub_7
4961 // 1305 DPairSpc_with_dsub_2_in_DPR_8
4962 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000,
4963 0x00000000, 0x00000000, 0xe0000000, 0xe500060c, 0x000001c0, // ssub_0_ssub_1_ssub_4_ssub_5
4964 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // ssub_2_ssub_3_ssub_6_ssub_7
4965 0x00000000, 0x00000000, 0x80000000, 0x00000400, 0x00000180, // ssub_4_ssub_5_ssub_8_ssub_9
4966 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_8_ssub_9_ssub_12_ssub_13
4967 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_5_dsub_7
4968 // 1335 DPair
4969 0x00000000, 0x00000000, 0x00000ff8, 0x00000000, 0x00000000,
4970 0x00000000, 0x00000000, 0x5f979000, 0xfffff80f, 0x000001ff, // qsub_0
4971 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x000001ff, // qsub_1
4972 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qsub_2
4973 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qsub_3
4974 0x00000000, 0x00000000, 0x5f979000, 0xfffff80f, 0x000001ff, // ssub_2_ssub_3_ssub_4_ssub_5
4975 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_ssub_8_ssub_9
4976 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_5_ssub_12_ssub_13
4977 // 1375 DPair_with_ssub_0
4978 0x00000000, 0x00000000, 0x00000fd0, 0x00000000, 0x00000000,
4979 0x00000000, 0x00000000, 0x5f928000, 0xffff300f, 0x000001fe, // qsub_0
4980 0x00000000, 0x00000000, 0x00000000, 0xffe70000, 0x000001fc, // qsub_1
4981 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qsub_2
4982 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qsub_3
4983 0x00000000, 0x00000000, 0x5d920000, 0xfff7200f, 0x000001fe, // ssub_2_ssub_3_ssub_4_ssub_5
4984 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_ssub_8_ssub_9
4985 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // dsub_5_ssub_12_ssub_13
4986 // 1415 QPR
4987 0x00000000, 0x00000000, 0x00000b20, 0x00000000, 0x00000000,
4988 0x00000000, 0x00000000, 0x11010000, 0x50904006, 0x000001ff, // qsub_0
4989 0x00000000, 0x00000000, 0x00000000, 0x50904000, 0x000001ff, // qsub_1
4990 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qsub_2
4991 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qsub_3
4992 0x00000000, 0x00000000, 0x0a040000, 0xaa488009, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
4993 // 1445 DPair_with_ssub_2
4994 0x00000000, 0x00000000, 0x00000fc0, 0x00000000, 0x00000000,
4995 0x00000000, 0x00000000, 0x5d920000, 0xfff7200f, 0x000001fe, // qsub_0
4996 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // qsub_1
4997 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qsub_2
4998 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qsub_3
4999 0x00000000, 0x00000000, 0x5c900000, 0xffe7000f, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5
5000 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9
5001 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_5_ssub_12_ssub_13
5002 // 1485 DPair_with_dsub_0_in_DPR_8
5003 0x00000000, 0x00000000, 0x00000c80, 0x00000000, 0x00000000,
5004 0x00000000, 0x00000000, 0x44800000, 0xfd24000f, 0x000001e0, // qsub_0
5005 0x00000000, 0x00000000, 0x00000000, 0xe5000000, 0x000001c0, // qsub_1
5006 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // qsub_2
5007 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // qsub_3
5008 0x00000000, 0x00000000, 0x44000000, 0xf520000e, 0x000001e0, // ssub_2_ssub_3_ssub_4_ssub_5
5009 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_ssub_8_ssub_9
5010 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // dsub_5_ssub_12_ssub_13
5011 // 1525 MQPR
5012 0x00000000, 0x00000000, 0x00000b00, 0x00000000, 0x00000000,
5013 0x00000000, 0x00000000, 0x11000000, 0x50900006, 0x000001fe, // qsub_0
5014 0x00000000, 0x00000000, 0x00000000, 0x50800000, 0x000001fc, // qsub_1
5015 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qsub_2
5016 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qsub_3
5017 0x00000000, 0x00000000, 0x08000000, 0xaa400009, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
5018 // 1555 QPR_VFP2
5019 0x00000000, 0x00000000, 0x00000b00, 0x00000000, 0x00000000,
5020 0x00000000, 0x00000000, 0x11000000, 0x50900006, 0x000001fe, // qsub_0
5021 0x00000000, 0x00000000, 0x00000000, 0x50800000, 0x000001fc, // qsub_1
5022 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qsub_2
5023 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qsub_3
5024 0x00000000, 0x00000000, 0x08000000, 0xaa400009, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
5025 // 1585 DPair_with_dsub_1_in_DPR_8
5026 0x00000000, 0x00000000, 0x00000c00, 0x00000000, 0x00000000,
5027 0x00000000, 0x00000000, 0x44000000, 0xf520000e, 0x000001e0, // qsub_0
5028 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // qsub_1
5029 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // qsub_2
5030 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // qsub_3
5031 0x00000000, 0x00000000, 0x40000000, 0xe500000c, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5
5032 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9
5033 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_5_ssub_12_ssub_13
5034 // 1625 QPR_8
5035 0x00000000, 0x00000000, 0x00000800, 0x00000000, 0x00000000,
5036 0x00000000, 0x00000000, 0x00000000, 0x50000006, 0x000001e0, // qsub_0
5037 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x000001c0, // qsub_1
5038 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // qsub_2
5039 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // qsub_3
5040 0x00000000, 0x00000000, 0x00000000, 0xa0000008, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
5041 // 1655 DTriple
5042 0x00000000, 0x00000000, 0x5f979000, 0x0000000f, 0x00000000,
5043 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x000001ff, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5044 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x000001ff, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5045 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5046 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5047 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5048 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_5_ssub_12_ssub_13_dsub_7
5049 // 1690 DTripleSpc
5050 0x00000000, 0x00000000, 0xa0686000, 0x000007f0, 0x00000000,
5051 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5052 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5053 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5054 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_dsub_5_dsub_7
5055 // 1715 DTripleSpc_with_ssub_0
5056 0x00000000, 0x00000000, 0xa0684000, 0x000007e0, 0x00000000,
5057 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5058 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5059 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5060 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_dsub_5_dsub_7
5061 // 1740 DTriple_with_ssub_0
5062 0x00000000, 0x00000000, 0x5f928000, 0x0000000f, 0x00000000,
5063 0x00000000, 0x00000000, 0x00000000, 0xffff3000, 0x000001fe, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5064 0x00000000, 0x00000000, 0x00000000, 0xfff72000, 0x000001fe, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5065 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5066 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5067 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5068 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // dsub_5_ssub_12_ssub_13_dsub_7
5069 // 1775 DTriple_with_qsub_0_in_QPR
5070 0x00000000, 0x00000000, 0x11010000, 0x00000006, 0x00000000,
5071 0x00000000, 0x00000000, 0x00000000, 0x50904000, 0x000001ff, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5072 0x00000000, 0x00000000, 0x00000000, 0xaa488000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5073 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5074 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5075 // 1800 DTriple_with_ssub_2
5076 0x00000000, 0x00000000, 0x5d920000, 0x0000000f, 0x00000000,
5077 0x00000000, 0x00000000, 0x00000000, 0xfff72000, 0x000001fe, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5078 0x00000000, 0x00000000, 0x00000000, 0xffe70000, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5079 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5080 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5081 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5082 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_5_ssub_12_ssub_13_dsub_7
5083 // 1835 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
5084 0x00000000, 0x00000000, 0x0a040000, 0x00000009, 0x00000000,
5085 0x00000000, 0x00000000, 0x00000000, 0xaa488000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5086 0x00000000, 0x00000000, 0x00000000, 0x50904000, 0x000001ff, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5087 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5088 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // dsub_5_ssub_12_ssub_13_dsub_7
5089 // 1860 DTripleSpc_with_ssub_4
5090 0x00000000, 0x00000000, 0xa0680000, 0x000007c0, 0x00000000,
5091 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5092 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5093 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5094 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_dsub_5_dsub_7
5095 // 1885 DTriple_with_ssub_4
5096 0x00000000, 0x00000000, 0x5c900000, 0x0000000f, 0x00000000,
5097 0x00000000, 0x00000000, 0x00000000, 0xffe70000, 0x000001fc, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5098 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5099 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5100 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5101 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5102 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_5_ssub_12_ssub_13_dsub_7
5103 // 1920 DTripleSpc_with_ssub_8
5104 0x00000000, 0x00000000, 0xa0600000, 0x00000780, 0x00000000,
5105 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5106 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5107 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5108 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_6_ssub_7_dsub_5_dsub_7
5109 // 1945 DTripleSpc_with_dsub_0_in_DPR_8
5110 0x00000000, 0x00000000, 0xa0400000, 0x00000700, 0x00000000,
5111 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5112 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5113 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5114 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_dsub_5_dsub_7
5115 // 1970 DTriple_with_dsub_0_in_DPR_8
5116 0x00000000, 0x00000000, 0x44800000, 0x0000000f, 0x00000000,
5117 0x00000000, 0x00000000, 0x00000000, 0xfd240000, 0x000001e0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5118 0x00000000, 0x00000000, 0x00000000, 0xf5200000, 0x000001e0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5119 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5120 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5121 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5122 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // dsub_5_ssub_12_ssub_13_dsub_7
5123 // 2005 DTriple_with_qsub_0_in_MQPR
5124 0x00000000, 0x00000000, 0x11000000, 0x00000006, 0x00000000,
5125 0x00000000, 0x00000000, 0x00000000, 0x50900000, 0x000001fe, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5126 0x00000000, 0x00000000, 0x00000000, 0xaa400000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5127 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5128 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5129 // 2030 DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
5130 0x00000000, 0x00000000, 0x0a000000, 0x00000009, 0x00000000,
5131 0x00000000, 0x00000000, 0x00000000, 0xaa480000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5132 0x00000000, 0x00000000, 0x00000000, 0x50900000, 0x000001fe, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5133 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5134 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // dsub_5_ssub_12_ssub_13_dsub_7
5135 // 2055 DTriple_with_dsub_1_in_DPR_8
5136 0x00000000, 0x00000000, 0x44000000, 0x0000000e, 0x00000000,
5137 0x00000000, 0x00000000, 0x00000000, 0xf5200000, 0x000001e0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5138 0x00000000, 0x00000000, 0x00000000, 0xe5000000, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5139 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5140 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5141 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5142 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_5_ssub_12_ssub_13_dsub_7
5143 // 2090 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
5144 0x00000000, 0x00000000, 0x08000000, 0x00000009, 0x00000000,
5145 0x00000000, 0x00000000, 0x00000000, 0xaa400000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5146 0x00000000, 0x00000000, 0x00000000, 0x50800000, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5147 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5148 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // dsub_5_ssub_12_ssub_13_dsub_7
5149 // 2115 DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR
5150 0x00000000, 0x00000000, 0x10000000, 0x00000006, 0x00000000,
5151 0x00000000, 0x00000000, 0x00000000, 0x50800000, 0x000001fc, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5152 0x00000000, 0x00000000, 0x00000000, 0xaa000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5153 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5154 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5155 // 2140 DTripleSpc_with_dsub_2_in_DPR_8
5156 0x00000000, 0x00000000, 0xa0000000, 0x00000600, 0x00000000,
5157 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5158 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5159 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5160 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_dsub_5_dsub_7
5161 // 2165 DTriple_with_dsub_2_in_DPR_8
5162 0x00000000, 0x00000000, 0x40000000, 0x0000000c, 0x00000000,
5163 0x00000000, 0x00000000, 0x00000000, 0xe5000000, 0x000001c0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5164 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5165 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5166 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5167 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5168 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_5_ssub_12_ssub_13_dsub_7
5169 // 2200 DTripleSpc_with_dsub_4_in_DPR_8
5170 0x00000000, 0x00000000, 0x80000000, 0x00000400, 0x00000000,
5171 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5172 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5173 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5174 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_6_ssub_7_dsub_5_dsub_7
5175 // 2225 DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
5176 0x00000000, 0x00000000, 0x00000000, 0x00000009, 0x00000000,
5177 0x00000000, 0x00000000, 0x00000000, 0xa8000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5178 0x00000000, 0x00000000, 0x00000000, 0x50000000, 0x000001e0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5179 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5180 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // dsub_5_ssub_12_ssub_13_dsub_7
5181 // 2250 DTriple_with_qsub_0_in_QPR_8
5182 0x00000000, 0x00000000, 0x00000000, 0x00000006, 0x00000000,
5183 0x00000000, 0x00000000, 0x00000000, 0x50000000, 0x000001e0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5184 0x00000000, 0x00000000, 0x00000000, 0xa0000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5185 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5186 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5187 // 2275 DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8
5188 0x00000000, 0x00000000, 0x00000000, 0x00000004, 0x00000000,
5189 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x000001c0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5190 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5191 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5192 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5193 // 2300 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
5194 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000,
5195 0x00000000, 0x00000000, 0x00000000, 0xa0000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
5196 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
5197 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
5198 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // dsub_5_ssub_12_ssub_13_dsub_7
5199 // 2325 DQuadSpc
5200 0x00000000, 0x00000000, 0x00000000, 0x000007f0, 0x00000000,
5201 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5202 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5203 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5204 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_dsub_5_dsub_7
5205 // 2350 DQuadSpc_with_ssub_0
5206 0x00000000, 0x00000000, 0x00000000, 0x000007e0, 0x00000000,
5207 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5208 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5209 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5210 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_dsub_5_dsub_7
5211 // 2375 DQuadSpc_with_ssub_4
5212 0x00000000, 0x00000000, 0x00000000, 0x000007c0, 0x00000000,
5213 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5214 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5215 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5216 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_dsub_5_dsub_7
5217 // 2400 DQuadSpc_with_ssub_8
5218 0x00000000, 0x00000000, 0x00000000, 0x00000780, 0x00000000,
5219 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5220 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5221 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5222 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_6_ssub_7_dsub_5_dsub_7
5223 // 2425 DQuadSpc_with_dsub_0_in_DPR_8
5224 0x00000000, 0x00000000, 0x00000000, 0x00000700, 0x00000000,
5225 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5226 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5227 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5228 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_dsub_5_dsub_7
5229 // 2450 DQuadSpc_with_dsub_2_in_DPR_8
5230 0x00000000, 0x00000000, 0x00000000, 0x00000600, 0x00000000,
5231 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5232 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5233 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5234 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_dsub_5_dsub_7
5235 // 2475 DQuadSpc_with_dsub_4_in_DPR_8
5236 0x00000000, 0x00000000, 0x00000000, 0x00000400, 0x00000000,
5237 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
5238 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
5239 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
5240 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_6_ssub_7_dsub_5_dsub_7
5241 // 2500 DQuad
5242 0x00000000, 0x00000000, 0x00000000, 0xfffff800, 0x00000000,
5243 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qqsub_0
5244 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qqsub_1
5245 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5246 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5247 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5248 // 2530 DQuad_with_ssub_0
5249 0x00000000, 0x00000000, 0x00000000, 0xffff3000, 0x00000000,
5250 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // qqsub_0
5251 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qqsub_1
5252 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5253 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5254 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5255 // 2560 DQuad_with_ssub_2
5256 0x00000000, 0x00000000, 0x00000000, 0xfff72000, 0x00000000,
5257 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // qqsub_0
5258 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qqsub_1
5259 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5260 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5261 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5262 // 2590 QQPR
5263 0x00000000, 0x00000000, 0x00000000, 0x50904000, 0x00000000,
5264 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qqsub_0
5265 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // qqsub_1
5266 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5267 // 2610 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
5268 0x00000000, 0x00000000, 0x00000000, 0xaa488000, 0x00000000,
5269 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5270 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5271 // 2625 DQuad_with_ssub_4
5272 0x00000000, 0x00000000, 0x00000000, 0xffe70000, 0x00000000,
5273 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // qqsub_0
5274 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qqsub_1
5275 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5276 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5277 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5278 // 2655 DQuad_with_ssub_6
5279 0x00000000, 0x00000000, 0x00000000, 0xffa60000, 0x00000000,
5280 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // qqsub_0
5281 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qqsub_1
5282 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5283 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5284 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5285 // 2685 DQuad_with_dsub_0_in_DPR_8
5286 0x00000000, 0x00000000, 0x00000000, 0xfd240000, 0x00000000,
5287 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // qqsub_0
5288 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // qqsub_1
5289 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5290 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5291 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5292 // 2715 DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
5293 0x00000000, 0x00000000, 0x00000000, 0xaa480000, 0x00000000,
5294 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5295 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5296 // 2730 QQPR_with_ssub_0
5297 0x00000000, 0x00000000, 0x00000000, 0x50900000, 0x00000000,
5298 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe, // qqsub_0
5299 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // qqsub_1
5300 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5301 // 2750 DQuad_with_dsub_1_in_DPR_8
5302 0x00000000, 0x00000000, 0x00000000, 0xf5200000, 0x00000000,
5303 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // qqsub_0
5304 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // qqsub_1
5305 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5306 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5307 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5308 // 2780 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
5309 0x00000000, 0x00000000, 0x00000000, 0xaa400000, 0x00000000,
5310 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5311 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5312 // 2795 MQQPR
5313 0x00000000, 0x00000000, 0x00000000, 0x50800000, 0x00000000,
5314 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc, // qqsub_0
5315 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // qqsub_1
5316 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5317 // 2815 DQuad_with_dsub_2_in_DPR_8
5318 0x00000000, 0x00000000, 0x00000000, 0xe5000000, 0x00000000,
5319 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // qqsub_0
5320 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // qqsub_1
5321 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5322 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5323 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5324 // 2845 DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
5325 0x00000000, 0x00000000, 0x00000000, 0xaa000000, 0x00000000,
5326 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5327 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5328 // 2860 DQuad_with_dsub_3_in_DPR_8
5329 0x00000000, 0x00000000, 0x00000000, 0xc4000000, 0x00000000,
5330 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // qqsub_0
5331 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // qqsub_1
5332 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5333 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5334 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5335 // 2890 DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
5336 0x00000000, 0x00000000, 0x00000000, 0xa8000000, 0x00000000,
5337 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5338 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5339 // 2905 MQQPR_with_qsub_0_in_QPR_8
5340 0x00000000, 0x00000000, 0x00000000, 0x50000000, 0x00000000,
5341 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0, // qqsub_0
5342 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // qqsub_1
5343 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5344 // 2925 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
5345 0x00000000, 0x00000000, 0x00000000, 0xa0000000, 0x00000000,
5346 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5347 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5348 // 2940 MQQPR_with_dsub_2_in_DPR_8
5349 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00000000,
5350 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0, // qqsub_0
5351 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // qqsub_1
5352 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
5353 // 2960 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8
5354 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000000,
5355 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
5356 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
5357 // 2975 QQQQPR
5358 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001ff,
5359 // 2980 QQQQPR_with_ssub_0
5360 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fe,
5361 // 2985 QQQQPR_with_ssub_4
5362 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001fc,
5363 // 2990 QQQQPR_with_ssub_8
5364 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f8,
5365 // 2995 MQQQQPR
5366 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001f0,
5367 // 3000 MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8
5368 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001e0,
5369 // 3005 MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8
5370 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000001c0,
5371 // 3010 MQQQQPR_with_qsub_2_in_QPR_8
5372 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000180,
5373 // 3015 MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8
5374 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100,
5375 },
5376 .SuperRegIdxSeqs: {
5377 /* 0 */ 1, 2, 3, 4, 5, 6, 7, 8, 0,
5378 /* 9 */ 9, 0,
5379 /* 11 */ 9, 10, 0,
5380 /* 14 */ 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0,
5381 /* 39 */ 13, 14, 15, 16, 37, 0,
5382 /* 45 */ 38, 40, 45, 48, 0,
5383 /* 50 */ 42, 50, 0,
5384 /* 53 */ 34, 36, 44, 52, 0,
5385 /* 58 */ 33, 35, 43, 51, 53, 0,
5386 /* 64 */ 34, 36, 47, 54, 0,
5387 /* 69 */ 34, 36, 44, 47, 52, 54, 0,
5388 /* 76 */ 13, 14, 15, 16, 37, 49, 55, 0,
5389 /* 84 */ 11, 12, 56, 0,
5390 /* 88 */ 11, 12, 42, 50, 56, 0,
5391 },
5392 .SuperClasses: {
5393 /* 0 HPR */
5394 /* 0 FPWithVPR */
5395 /* 0 SPR */ ARM::HPRRegClassID, ARM::FPWithVPRRegClassID,
5396 /* 2 FPWithVPR_with_ssub_0 */ ARM::FPWithVPRRegClassID,
5397 /* 3 GPR */
5398 /* 3 GPRwithAPSR */
5399 /* 3 GPRwithZR */
5400 /* 3 SPR_8 */ ARM::HPRRegClassID, ARM::FPWithVPRRegClassID, ARM::SPRRegClassID,
5401 /* 6 GPRnopc */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID,
5402 /* 9 GPRnosp */ ARM::GPRRegClassID,
5403 /* 10 GPRwithAPSR_NZCVnosp */ ARM::GPRwithAPSRRegClassID,
5404 /* 11 GPRwithAPSRnosp */
5405 /* 11 GPRwithZRnosp */ ARM::GPRwithZRRegClassID,
5406 /* 12 GPRnoip */ ARM::GPRRegClassID,
5407 /* 13 rGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID,
5408 /* 21 GPRnoip_and_GPRnopc */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnoipRegClassID,
5409 /* 26 GPRnoip_and_GPRnosp */ ARM::GPRRegClassID, ARM::GPRnospRegClassID, ARM::GPRnoipRegClassID,
5410 /* 29 GPRnoip_and_GPRwithAPSR_NZCVnosp */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID,
5411 /* 41 tGPRwithpc */ ARM::GPRRegClassID, ARM::GPRnospRegClassID, ARM::GPRnoipRegClassID, ARM::GPRnoip_and_GPRnospRegClassID,
5412 /* 45 FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 */ ARM::FPWithVPRRegClassID, ARM::FPWithVPR_with_ssub_0RegClassID,
5413 /* 47 hGPR */ ARM::GPRRegClassID,
5414 /* 48 tGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPRwithpcRegClassID,
5415 /* 62 tGPREven */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID,
5416 /* 71 GPRnopc_and_hGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::hGPRRegClassID,
5417 /* 76 GPRnosp_and_hGPR */ ARM::GPRRegClassID, ARM::GPRnospRegClassID, ARM::hGPRRegClassID,
5418 /* 79 GPRnoip_and_hGPR */ ARM::GPRRegClassID, ARM::GPRnoipRegClassID, ARM::hGPRRegClassID,
5419 /* 82 GPRnoip_and_tGPREven */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPREvenRegClassID,
5420 /* 96 GPRnosp_and_GPRnopc_and_hGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID, ARM::hGPRRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID,
5421 /* 108 tGPROdd */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID,
5422 /* 121 GPRnopc_and_GPRnoip_and_hGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnoipRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::hGPRRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID,
5423 /* 130 GPRnosp_and_GPRnoip_and_hGPR */ ARM::GPRRegClassID, ARM::GPRnospRegClassID, ARM::GPRnoipRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID,
5424 /* 137 tcGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID,
5425 /* 146 GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::hGPRRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID, ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID,
5426 /* 166 hGPR_and_tGPREven */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID, ARM::hGPRRegClassID, ARM::tGPREvenRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID,
5427 /* 180 tGPR_and_tGPREven */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPRwithpcRegClassID, ARM::tGPRRegClassID, ARM::tGPREvenRegClassID, ARM::GPRnoip_and_tGPREvenRegClassID,
5428 /* 197 tGPR_and_tGPROdd */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPRwithpcRegClassID, ARM::tGPRRegClassID, ARM::tGPROddRegClassID,
5429 /* 213 tcGPRnotr12 */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPRwithpcRegClassID, ARM::tGPRRegClassID, ARM::tcGPRRegClassID,
5430 /* 229 tGPREven_and_tcGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID, ARM::tGPREvenRegClassID, ARM::tcGPRRegClassID,
5431 /* 240 FP_STATUS_REGS */
5432 /* 240 hGPR_and_GPRnoip_and_tGPREven */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::hGPRRegClassID, ARM::tGPREvenRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID, ARM::GPRnoip_and_tGPREvenRegClassID, ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID, ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID, ARM::hGPR_and_tGPREvenRegClassID,
5433 /* 264 hGPR_and_tGPROdd */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::hGPRRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID, ARM::tGPROddRegClassID, ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID,
5434 /* 286 tGPREven_and_tcGPRnotr12 */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPRwithpcRegClassID, ARM::tGPRRegClassID, ARM::tGPREvenRegClassID, ARM::GPRnoip_and_tGPREvenRegClassID, ARM::tcGPRRegClassID, ARM::tGPR_and_tGPREvenRegClassID, ARM::tcGPRnotr12RegClassID, ARM::tGPREven_and_tcGPRRegClassID,
5435 /* 307 tGPROdd_and_tcGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::GPRnoipRegClassID, ARM::rGPRRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, ARM::tGPRwithpcRegClassID, ARM::tGPRRegClassID, ARM::tGPROddRegClassID, ARM::tcGPRRegClassID, ARM::tGPR_and_tGPROddRegClassID, ARM::tcGPRnotr12RegClassID,
5436 /* 326 CCR */
5437 /* 326 FPCXTRegs */
5438 /* 326 GPRlr */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID, ARM::hGPRRegClassID, ARM::tGPREvenRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID, ARM::hGPR_and_tGPREvenRegClassID,
5439 /* 341 GPRsp */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnoipRegClassID, ARM::GPRnoip_and_GPRnopcRegClassID, ARM::hGPRRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID, ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID,
5440 /* 351 VCCR */ ARM::FPWithVPRRegClassID,
5441 /* 352 cl_FPSCR_NZCV */
5442 /* 352 hGPR_and_tGPRwithpc */ ARM::GPRRegClassID, ARM::GPRnospRegClassID, ARM::GPRnoipRegClassID, ARM::GPRnoip_and_GPRnospRegClassID, ARM::tGPRwithpcRegClassID, ARM::hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnoip_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID,
5443 /* 361 hGPR_and_tcGPR */ ARM::GPRRegClassID, ARM::GPRwithAPSRRegClassID, ARM::GPRwithZRRegClassID, ARM::GPRnopcRegClassID, ARM::GPRnospRegClassID, ARM::GPRwithAPSR_NZCVnospRegClassID, ARM::GPRwithAPSRnospRegClassID, ARM::GPRwithZRnospRegClassID, ARM::rGPRRegClassID, ARM::hGPRRegClassID, ARM::tGPREvenRegClassID, ARM::GPRnopc_and_hGPRRegClassID, ARM::GPRnosp_and_hGPRRegClassID, ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID, ARM::tcGPRRegClassID, ARM::hGPR_and_tGPREvenRegClassID, ARM::tGPREven_and_tcGPRRegClassID,
5444 /* 378 DPR */ ARM::FPWithVPRRegClassID,
5445 /* 379 DPR_VFP2 */ ARM::FPWithVPRRegClassID, ARM::FPWithVPR_with_ssub_0RegClassID, ARM::DPRRegClassID,
5446 /* 382 DPR_8 */ ARM::FPWithVPRRegClassID, ARM::FPWithVPR_with_ssub_0RegClassID, ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID, ARM::DPRRegClassID, ARM::DPR_VFP2RegClassID,
5447 /* 387 GPRPair */
5448 /* 387 GPRPairnosp */ ARM::GPRPairRegClassID,
5449 /* 388 GPRPair_with_gsub_0_in_tGPR */ ARM::GPRPairRegClassID, ARM::GPRPairnospRegClassID,
5450 /* 390 GPRPair_with_gsub_0_in_hGPR */ ARM::GPRPairRegClassID,
5451 /* 391 GPRPair_with_gsub_0_in_tcGPR */ ARM::GPRPairRegClassID,
5452 /* 392 GPRPair_with_gsub_0_in_tcGPRnotr12 */ ARM::GPRPairRegClassID, ARM::GPRPairnospRegClassID, ARM::GPRPair_with_gsub_0_in_tGPRRegClassID, ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID,
5453 /* 396 GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR */ ARM::GPRPairRegClassID, ARM::GPRPairnospRegClassID, ARM::GPRPair_with_gsub_0_in_hGPRRegClassID,
5454 /* 399 GPRPair_with_gsub_1_in_GPRsp */ ARM::GPRPairRegClassID, ARM::GPRPair_with_gsub_0_in_hGPRRegClassID, ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID,
5455 /* 402 DPairSpc */
5456 /* 402 DPairSpc_with_ssub_0 */ ARM::DPairSpcRegClassID,
5457 /* 403 DPairSpc_with_ssub_4 */ ARM::DPairSpcRegClassID, ARM::DPairSpc_with_ssub_0RegClassID,
5458 /* 405 DPairSpc_with_dsub_0_in_DPR_8 */ ARM::DPairSpcRegClassID, ARM::DPairSpc_with_ssub_0RegClassID, ARM::DPairSpc_with_ssub_4RegClassID,
5459 /* 408 DPairSpc_with_dsub_2_in_DPR_8 */ ARM::DPairSpcRegClassID, ARM::DPairSpc_with_ssub_0RegClassID, ARM::DPairSpc_with_ssub_4RegClassID, ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID,
5460 /* 412 DPair */
5461 /* 412 DPair_with_ssub_0 */ ARM::DPairRegClassID,
5462 /* 413 QPR */ ARM::DPairRegClassID,
5463 /* 414 DPair_with_ssub_2 */ ARM::DPairRegClassID, ARM::DPair_with_ssub_0RegClassID,
5464 /* 416 DPair_with_dsub_0_in_DPR_8 */ ARM::DPairRegClassID, ARM::DPair_with_ssub_0RegClassID, ARM::DPair_with_ssub_2RegClassID,
5465 /* 419 MQPR */ ARM::DPairRegClassID, ARM::DPair_with_ssub_0RegClassID, ARM::QPRRegClassID, ARM::DPair_with_ssub_2RegClassID, ARM::QPR_VFP2RegClassID,
5466 /* 424 QPR_VFP2 */ ARM::DPairRegClassID, ARM::DPair_with_ssub_0RegClassID, ARM::QPRRegClassID, ARM::DPair_with_ssub_2RegClassID, ARM::MQPRRegClassID,
5467 /* 429 DPair_with_dsub_1_in_DPR_8 */ ARM::DPairRegClassID, ARM::DPair_with_ssub_0RegClassID, ARM::DPair_with_ssub_2RegClassID, ARM::DPair_with_dsub_0_in_DPR_8RegClassID,
5468 /* 433 QPR_8 */ ARM::DPairRegClassID, ARM::DPair_with_ssub_0RegClassID, ARM::QPRRegClassID, ARM::DPair_with_ssub_2RegClassID, ARM::DPair_with_dsub_0_in_DPR_8RegClassID, ARM::MQPRRegClassID, ARM::QPR_VFP2RegClassID, ARM::DPair_with_dsub_1_in_DPR_8RegClassID,
5469 /* 441 DTriple */
5470 /* 441 DTripleSpc */
5471 /* 441 DTripleSpc_with_ssub_0 */ ARM::DTripleSpcRegClassID,
5472 /* 442 DTriple_with_ssub_0 */ ARM::DTripleRegClassID,
5473 /* 443 DTriple_with_qsub_0_in_QPR */ ARM::DTripleRegClassID,
5474 /* 444 DTriple_with_ssub_2 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID,
5475 /* 446 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR */ ARM::DTripleRegClassID,
5476 /* 447 DTripleSpc_with_ssub_4 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID,
5477 /* 449 DTriple_with_ssub_4 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID,
5478 /* 452 DTripleSpc_with_ssub_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID,
5479 /* 455 DTripleSpc_with_dsub_0_in_DPR_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID,
5480 /* 459 DTriple_with_dsub_0_in_DPR_8 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_4RegClassID,
5481 /* 463 DTriple_with_qsub_0_in_MQPR */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_qsub_0_in_QPRRegClassID, ARM::DTriple_with_ssub_2RegClassID,
5482 /* 467 DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
5483 /* 470 DTriple_with_dsub_1_in_DPR_8 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8RegClassID,
5484 /* 475 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
5485 /* 481 DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_qsub_0_in_QPRRegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_qsub_0_in_MQPRRegClassID,
5486 /* 487 DTripleSpc_with_dsub_2_in_DPR_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID, ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID,
5487 /* 492 DTriple_with_dsub_2_in_DPR_8 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, ARM::DTriple_with_dsub_1_in_DPR_8RegClassID,
5488 /* 498 DTripleSpc_with_dsub_4_in_DPR_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID, ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID,
5489 /* 504 DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
5490 /* 512 DTriple_with_qsub_0_in_QPR_8 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_qsub_0_in_QPRRegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, ARM::DTriple_with_qsub_0_in_MQPRRegClassID, ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID,
5491 /* 521 DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_qsub_0_in_QPRRegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, ARM::DTriple_with_qsub_0_in_MQPRRegClassID, ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID, ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, ARM::DTriple_with_qsub_0_in_QPR_8RegClassID,
5492 /* 532 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 */ ARM::DTripleRegClassID, ARM::DTriple_with_ssub_0RegClassID, ARM::DTriple_with_ssub_2RegClassID, ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DTriple_with_ssub_4RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
5493 /* 543 DQuadSpc */ ARM::DTripleSpcRegClassID,
5494 /* 544 DQuadSpc_with_ssub_0 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DQuadSpcRegClassID,
5495 /* 547 DQuadSpc_with_ssub_4 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DQuadSpcRegClassID, ARM::DQuadSpc_with_ssub_0RegClassID,
5496 /* 552 DQuadSpc_with_ssub_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID, ARM::DQuadSpcRegClassID, ARM::DQuadSpc_with_ssub_0RegClassID, ARM::DQuadSpc_with_ssub_4RegClassID,
5497 /* 559 DQuadSpc_with_dsub_0_in_DPR_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID, ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, ARM::DQuadSpcRegClassID, ARM::DQuadSpc_with_ssub_0RegClassID, ARM::DQuadSpc_with_ssub_4RegClassID, ARM::DQuadSpc_with_ssub_8RegClassID,
5498 /* 568 DQuadSpc_with_dsub_2_in_DPR_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID, ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, ARM::DQuadSpcRegClassID, ARM::DQuadSpc_with_ssub_0RegClassID, ARM::DQuadSpc_with_ssub_4RegClassID, ARM::DQuadSpc_with_ssub_8RegClassID, ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID,
5499 /* 579 DQuadSpc_with_dsub_4_in_DPR_8 */ ARM::DTripleSpcRegClassID, ARM::DTripleSpc_with_ssub_0RegClassID, ARM::DTripleSpc_with_ssub_4RegClassID, ARM::DTripleSpc_with_ssub_8RegClassID, ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID, ARM::DQuadSpcRegClassID, ARM::DQuadSpc_with_ssub_0RegClassID, ARM::DQuadSpc_with_ssub_4RegClassID, ARM::DQuadSpc_with_ssub_8RegClassID, ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID, ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID,
5500 /* 592 DQuad */
5501 /* 592 DQuad_with_ssub_0 */ ARM::DQuadRegClassID,
5502 /* 593 DQuad_with_ssub_2 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID,
5503 /* 595 QQPR */ ARM::DQuadRegClassID,
5504 /* 596 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR */ ARM::DQuadRegClassID,
5505 /* 597 DQuad_with_ssub_4 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID,
5506 /* 600 DQuad_with_ssub_6 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_4RegClassID,
5507 /* 604 DQuad_with_dsub_0_in_DPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID,
5508 /* 609 DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
5509 /* 612 QQPR_with_ssub_0 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::QQPRRegClassID,
5510 /* 616 DQuad_with_dsub_1_in_DPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID,
5511 /* 622 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID,
5512 /* 628 MQQPR */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::QQPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::QQPR_with_ssub_0RegClassID,
5513 /* 635 DQuad_with_dsub_2_in_DPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::DQuad_with_dsub_1_in_DPR_8RegClassID,
5514 /* 642 DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
5515 /* 650 DQuad_with_dsub_3_in_DPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, ARM::DQuad_with_dsub_2_in_DPR_8RegClassID,
5516 /* 658 DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
5517 /* 668 MQQPR_with_qsub_0_in_QPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::QQPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::QQPR_with_ssub_0RegClassID, ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, ARM::MQQPRRegClassID,
5518 /* 678 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID,
5519 /* 691 MQQPR_with_dsub_2_in_DPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::QQPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::QQPR_with_ssub_0RegClassID, ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, ARM::MQQPRRegClassID, ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, ARM::MQQPR_with_qsub_0_in_QPR_8RegClassID,
5520 /* 704 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8 */ ARM::DQuadRegClassID, ARM::DQuad_with_ssub_0RegClassID, ARM::DQuad_with_ssub_2RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_ssub_4RegClassID, ARM::DQuad_with_ssub_6RegClassID, ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, ARM::DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID,
5521 /* 719 QQQQPR */
5522 /* 719 QQQQPR_with_ssub_0 */ ARM::QQQQPRRegClassID,
5523 /* 720 QQQQPR_with_ssub_4 */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID,
5524 /* 722 QQQQPR_with_ssub_8 */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID, ARM::QQQQPR_with_ssub_4RegClassID,
5525 /* 725 MQQQQPR */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID, ARM::QQQQPR_with_ssub_4RegClassID, ARM::QQQQPR_with_ssub_8RegClassID,
5526 /* 729 MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8 */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID, ARM::QQQQPR_with_ssub_4RegClassID, ARM::QQQQPR_with_ssub_8RegClassID, ARM::MQQQQPRRegClassID,
5527 /* 734 MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8 */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID, ARM::QQQQPR_with_ssub_4RegClassID, ARM::QQQQPR_with_ssub_8RegClassID, ARM::MQQQQPRRegClassID, ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID,
5528 /* 740 MQQQQPR_with_qsub_2_in_QPR_8 */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID, ARM::QQQQPR_with_ssub_4RegClassID, ARM::QQQQPR_with_ssub_8RegClassID, ARM::MQQQQPRRegClassID, ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID, ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8RegClassID,
5529 /* 747 MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8 */ ARM::QQQQPRRegClassID, ARM::QQQQPR_with_ssub_0RegClassID, ARM::QQQQPR_with_ssub_4RegClassID, ARM::QQQQPR_with_ssub_8RegClassID, ARM::MQQQQPRRegClassID, ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID, ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8RegClassID, ARM::MQQQQPR_with_qsub_2_in_QPR_8RegClassID,
5530 }
5531};
5532
5533const MCRegisterClass &getARMMCRegisterClass(unsigned RC) {
5534 return ARMMCRegisterClassStorage.Classes[RC];
5535}
5536
5537// ARM Dwarf<->LLVM register mappings.
5538extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = {
5539 { .FromReg: 0U, .ToReg: ARM::R0 },
5540 { .FromReg: 1U, .ToReg: ARM::R1 },
5541 { .FromReg: 2U, .ToReg: ARM::R2 },
5542 { .FromReg: 3U, .ToReg: ARM::R3 },
5543 { .FromReg: 4U, .ToReg: ARM::R4 },
5544 { .FromReg: 5U, .ToReg: ARM::R5 },
5545 { .FromReg: 6U, .ToReg: ARM::R6 },
5546 { .FromReg: 7U, .ToReg: ARM::R7 },
5547 { .FromReg: 8U, .ToReg: ARM::R8 },
5548 { .FromReg: 9U, .ToReg: ARM::R9 },
5549 { .FromReg: 10U, .ToReg: ARM::R10 },
5550 { .FromReg: 11U, .ToReg: ARM::R11 },
5551 { .FromReg: 12U, .ToReg: ARM::R12 },
5552 { .FromReg: 13U, .ToReg: ARM::SP },
5553 { .FromReg: 14U, .ToReg: ARM::LR },
5554 { .FromReg: 15U, .ToReg: ARM::ZR },
5555 { .FromReg: 143U, .ToReg: ARM::RA_AUTH_CODE },
5556 { .FromReg: 256U, .ToReg: ARM::D0 },
5557 { .FromReg: 257U, .ToReg: ARM::D1 },
5558 { .FromReg: 258U, .ToReg: ARM::D2 },
5559 { .FromReg: 259U, .ToReg: ARM::D3 },
5560 { .FromReg: 260U, .ToReg: ARM::D4 },
5561 { .FromReg: 261U, .ToReg: ARM::D5 },
5562 { .FromReg: 262U, .ToReg: ARM::D6 },
5563 { .FromReg: 263U, .ToReg: ARM::D7 },
5564 { .FromReg: 264U, .ToReg: ARM::D8 },
5565 { .FromReg: 265U, .ToReg: ARM::D9 },
5566 { .FromReg: 266U, .ToReg: ARM::D10 },
5567 { .FromReg: 267U, .ToReg: ARM::D11 },
5568 { .FromReg: 268U, .ToReg: ARM::D12 },
5569 { .FromReg: 269U, .ToReg: ARM::D13 },
5570 { .FromReg: 270U, .ToReg: ARM::D14 },
5571 { .FromReg: 271U, .ToReg: ARM::D15 },
5572 { .FromReg: 272U, .ToReg: ARM::D16 },
5573 { .FromReg: 273U, .ToReg: ARM::D17 },
5574 { .FromReg: 274U, .ToReg: ARM::D18 },
5575 { .FromReg: 275U, .ToReg: ARM::D19 },
5576 { .FromReg: 276U, .ToReg: ARM::D20 },
5577 { .FromReg: 277U, .ToReg: ARM::D21 },
5578 { .FromReg: 278U, .ToReg: ARM::D22 },
5579 { .FromReg: 279U, .ToReg: ARM::D23 },
5580 { .FromReg: 280U, .ToReg: ARM::D24 },
5581 { .FromReg: 281U, .ToReg: ARM::D25 },
5582 { .FromReg: 282U, .ToReg: ARM::D26 },
5583 { .FromReg: 283U, .ToReg: ARM::D27 },
5584 { .FromReg: 284U, .ToReg: ARM::D28 },
5585 { .FromReg: 285U, .ToReg: ARM::D29 },
5586 { .FromReg: 286U, .ToReg: ARM::D30 },
5587 { .FromReg: 287U, .ToReg: ARM::D31 },
5588};
5589extern const unsigned ARMDwarfFlavour0Dwarf2LSize = std::size(ARMDwarfFlavour0Dwarf2L);
5590
5591extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = {
5592 { .FromReg: 0U, .ToReg: ARM::R0 },
5593 { .FromReg: 1U, .ToReg: ARM::R1 },
5594 { .FromReg: 2U, .ToReg: ARM::R2 },
5595 { .FromReg: 3U, .ToReg: ARM::R3 },
5596 { .FromReg: 4U, .ToReg: ARM::R4 },
5597 { .FromReg: 5U, .ToReg: ARM::R5 },
5598 { .FromReg: 6U, .ToReg: ARM::R6 },
5599 { .FromReg: 7U, .ToReg: ARM::R7 },
5600 { .FromReg: 8U, .ToReg: ARM::R8 },
5601 { .FromReg: 9U, .ToReg: ARM::R9 },
5602 { .FromReg: 10U, .ToReg: ARM::R10 },
5603 { .FromReg: 11U, .ToReg: ARM::R11 },
5604 { .FromReg: 12U, .ToReg: ARM::R12 },
5605 { .FromReg: 13U, .ToReg: ARM::SP },
5606 { .FromReg: 14U, .ToReg: ARM::LR },
5607 { .FromReg: 15U, .ToReg: ARM::ZR },
5608 { .FromReg: 143U, .ToReg: ARM::RA_AUTH_CODE },
5609 { .FromReg: 256U, .ToReg: ARM::D0 },
5610 { .FromReg: 257U, .ToReg: ARM::D1 },
5611 { .FromReg: 258U, .ToReg: ARM::D2 },
5612 { .FromReg: 259U, .ToReg: ARM::D3 },
5613 { .FromReg: 260U, .ToReg: ARM::D4 },
5614 { .FromReg: 261U, .ToReg: ARM::D5 },
5615 { .FromReg: 262U, .ToReg: ARM::D6 },
5616 { .FromReg: 263U, .ToReg: ARM::D7 },
5617 { .FromReg: 264U, .ToReg: ARM::D8 },
5618 { .FromReg: 265U, .ToReg: ARM::D9 },
5619 { .FromReg: 266U, .ToReg: ARM::D10 },
5620 { .FromReg: 267U, .ToReg: ARM::D11 },
5621 { .FromReg: 268U, .ToReg: ARM::D12 },
5622 { .FromReg: 269U, .ToReg: ARM::D13 },
5623 { .FromReg: 270U, .ToReg: ARM::D14 },
5624 { .FromReg: 271U, .ToReg: ARM::D15 },
5625 { .FromReg: 272U, .ToReg: ARM::D16 },
5626 { .FromReg: 273U, .ToReg: ARM::D17 },
5627 { .FromReg: 274U, .ToReg: ARM::D18 },
5628 { .FromReg: 275U, .ToReg: ARM::D19 },
5629 { .FromReg: 276U, .ToReg: ARM::D20 },
5630 { .FromReg: 277U, .ToReg: ARM::D21 },
5631 { .FromReg: 278U, .ToReg: ARM::D22 },
5632 { .FromReg: 279U, .ToReg: ARM::D23 },
5633 { .FromReg: 280U, .ToReg: ARM::D24 },
5634 { .FromReg: 281U, .ToReg: ARM::D25 },
5635 { .FromReg: 282U, .ToReg: ARM::D26 },
5636 { .FromReg: 283U, .ToReg: ARM::D27 },
5637 { .FromReg: 284U, .ToReg: ARM::D28 },
5638 { .FromReg: 285U, .ToReg: ARM::D29 },
5639 { .FromReg: 286U, .ToReg: ARM::D30 },
5640 { .FromReg: 287U, .ToReg: ARM::D31 },
5641};
5642extern const unsigned ARMEHFlavour0Dwarf2LSize = std::size(ARMEHFlavour0Dwarf2L);
5643
5644extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = {
5645 { .FromReg: ARM::LR, .ToReg: 14U },
5646 { .FromReg: ARM::PC, .ToReg: 15U },
5647 { .FromReg: ARM::RA_AUTH_CODE, .ToReg: 143U },
5648 { .FromReg: ARM::SP, .ToReg: 13U },
5649 { .FromReg: ARM::ZR, .ToReg: 15U },
5650 { .FromReg: ARM::D0, .ToReg: 256U },
5651 { .FromReg: ARM::D1, .ToReg: 257U },
5652 { .FromReg: ARM::D2, .ToReg: 258U },
5653 { .FromReg: ARM::D3, .ToReg: 259U },
5654 { .FromReg: ARM::D4, .ToReg: 260U },
5655 { .FromReg: ARM::D5, .ToReg: 261U },
5656 { .FromReg: ARM::D6, .ToReg: 262U },
5657 { .FromReg: ARM::D7, .ToReg: 263U },
5658 { .FromReg: ARM::D8, .ToReg: 264U },
5659 { .FromReg: ARM::D9, .ToReg: 265U },
5660 { .FromReg: ARM::D10, .ToReg: 266U },
5661 { .FromReg: ARM::D11, .ToReg: 267U },
5662 { .FromReg: ARM::D12, .ToReg: 268U },
5663 { .FromReg: ARM::D13, .ToReg: 269U },
5664 { .FromReg: ARM::D14, .ToReg: 270U },
5665 { .FromReg: ARM::D15, .ToReg: 271U },
5666 { .FromReg: ARM::D16, .ToReg: 272U },
5667 { .FromReg: ARM::D17, .ToReg: 273U },
5668 { .FromReg: ARM::D18, .ToReg: 274U },
5669 { .FromReg: ARM::D19, .ToReg: 275U },
5670 { .FromReg: ARM::D20, .ToReg: 276U },
5671 { .FromReg: ARM::D21, .ToReg: 277U },
5672 { .FromReg: ARM::D22, .ToReg: 278U },
5673 { .FromReg: ARM::D23, .ToReg: 279U },
5674 { .FromReg: ARM::D24, .ToReg: 280U },
5675 { .FromReg: ARM::D25, .ToReg: 281U },
5676 { .FromReg: ARM::D26, .ToReg: 282U },
5677 { .FromReg: ARM::D27, .ToReg: 283U },
5678 { .FromReg: ARM::D28, .ToReg: 284U },
5679 { .FromReg: ARM::D29, .ToReg: 285U },
5680 { .FromReg: ARM::D30, .ToReg: 286U },
5681 { .FromReg: ARM::D31, .ToReg: 287U },
5682 { .FromReg: ARM::R0, .ToReg: 0U },
5683 { .FromReg: ARM::R1, .ToReg: 1U },
5684 { .FromReg: ARM::R2, .ToReg: 2U },
5685 { .FromReg: ARM::R3, .ToReg: 3U },
5686 { .FromReg: ARM::R4, .ToReg: 4U },
5687 { .FromReg: ARM::R5, .ToReg: 5U },
5688 { .FromReg: ARM::R6, .ToReg: 6U },
5689 { .FromReg: ARM::R7, .ToReg: 7U },
5690 { .FromReg: ARM::R8, .ToReg: 8U },
5691 { .FromReg: ARM::R9, .ToReg: 9U },
5692 { .FromReg: ARM::R10, .ToReg: 10U },
5693 { .FromReg: ARM::R11, .ToReg: 11U },
5694 { .FromReg: ARM::R12, .ToReg: 12U },
5695};
5696extern const unsigned ARMDwarfFlavour0L2DwarfSize = std::size(ARMDwarfFlavour0L2Dwarf);
5697
5698extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = {
5699 { .FromReg: ARM::LR, .ToReg: 14U },
5700 { .FromReg: ARM::PC, .ToReg: 15U },
5701 { .FromReg: ARM::RA_AUTH_CODE, .ToReg: 143U },
5702 { .FromReg: ARM::SP, .ToReg: 13U },
5703 { .FromReg: ARM::ZR, .ToReg: 15U },
5704 { .FromReg: ARM::D0, .ToReg: 256U },
5705 { .FromReg: ARM::D1, .ToReg: 257U },
5706 { .FromReg: ARM::D2, .ToReg: 258U },
5707 { .FromReg: ARM::D3, .ToReg: 259U },
5708 { .FromReg: ARM::D4, .ToReg: 260U },
5709 { .FromReg: ARM::D5, .ToReg: 261U },
5710 { .FromReg: ARM::D6, .ToReg: 262U },
5711 { .FromReg: ARM::D7, .ToReg: 263U },
5712 { .FromReg: ARM::D8, .ToReg: 264U },
5713 { .FromReg: ARM::D9, .ToReg: 265U },
5714 { .FromReg: ARM::D10, .ToReg: 266U },
5715 { .FromReg: ARM::D11, .ToReg: 267U },
5716 { .FromReg: ARM::D12, .ToReg: 268U },
5717 { .FromReg: ARM::D13, .ToReg: 269U },
5718 { .FromReg: ARM::D14, .ToReg: 270U },
5719 { .FromReg: ARM::D15, .ToReg: 271U },
5720 { .FromReg: ARM::D16, .ToReg: 272U },
5721 { .FromReg: ARM::D17, .ToReg: 273U },
5722 { .FromReg: ARM::D18, .ToReg: 274U },
5723 { .FromReg: ARM::D19, .ToReg: 275U },
5724 { .FromReg: ARM::D20, .ToReg: 276U },
5725 { .FromReg: ARM::D21, .ToReg: 277U },
5726 { .FromReg: ARM::D22, .ToReg: 278U },
5727 { .FromReg: ARM::D23, .ToReg: 279U },
5728 { .FromReg: ARM::D24, .ToReg: 280U },
5729 { .FromReg: ARM::D25, .ToReg: 281U },
5730 { .FromReg: ARM::D26, .ToReg: 282U },
5731 { .FromReg: ARM::D27, .ToReg: 283U },
5732 { .FromReg: ARM::D28, .ToReg: 284U },
5733 { .FromReg: ARM::D29, .ToReg: 285U },
5734 { .FromReg: ARM::D30, .ToReg: 286U },
5735 { .FromReg: ARM::D31, .ToReg: 287U },
5736 { .FromReg: ARM::R0, .ToReg: 0U },
5737 { .FromReg: ARM::R1, .ToReg: 1U },
5738 { .FromReg: ARM::R2, .ToReg: 2U },
5739 { .FromReg: ARM::R3, .ToReg: 3U },
5740 { .FromReg: ARM::R4, .ToReg: 4U },
5741 { .FromReg: ARM::R5, .ToReg: 5U },
5742 { .FromReg: ARM::R6, .ToReg: 6U },
5743 { .FromReg: ARM::R7, .ToReg: 7U },
5744 { .FromReg: ARM::R8, .ToReg: 8U },
5745 { .FromReg: ARM::R9, .ToReg: 9U },
5746 { .FromReg: ARM::R10, .ToReg: 10U },
5747 { .FromReg: ARM::R11, .ToReg: 11U },
5748 { .FromReg: ARM::R12, .ToReg: 12U },
5749};
5750extern const unsigned ARMEHFlavour0L2DwarfSize = std::size(ARMEHFlavour0L2Dwarf);
5751
5752extern const uint16_t ARMRegEncodingTable[] = {
5753 0,
5754 15,
5755 15,
5756 0,
5757 14,
5758 15,
5759 8,
5760 9,
5761 3,
5762 3,
5763 2,
5764 3,
5765 0,
5766 4,
5767 14,
5768 15,
5769 12,
5770 13,
5771 2,
5772 64,
5773 15,
5774 0,
5775 1,
5776 2,
5777 3,
5778 4,
5779 5,
5780 6,
5781 7,
5782 8,
5783 9,
5784 10,
5785 11,
5786 12,
5787 13,
5788 14,
5789 15,
5790 16,
5791 17,
5792 18,
5793 19,
5794 20,
5795 21,
5796 22,
5797 23,
5798 24,
5799 25,
5800 26,
5801 27,
5802 28,
5803 29,
5804 30,
5805 31,
5806 10,
5807 7,
5808 6,
5809 5,
5810 13,
5811 0,
5812 1,
5813 2,
5814 3,
5815 4,
5816 5,
5817 6,
5818 7,
5819 8,
5820 9,
5821 10,
5822 11,
5823 12,
5824 13,
5825 14,
5826 15,
5827 0,
5828 1,
5829 2,
5830 3,
5831 4,
5832 5,
5833 6,
5834 7,
5835 8,
5836 9,
5837 10,
5838 11,
5839 12,
5840 0,
5841 1,
5842 2,
5843 3,
5844 4,
5845 5,
5846 6,
5847 7,
5848 8,
5849 9,
5850 10,
5851 11,
5852 12,
5853 13,
5854 14,
5855 15,
5856 16,
5857 17,
5858 18,
5859 19,
5860 20,
5861 21,
5862 22,
5863 23,
5864 24,
5865 25,
5866 26,
5867 27,
5868 28,
5869 29,
5870 30,
5871 31,
5872 0,
5873 1,
5874 2,
5875 3,
5876 4,
5877 5,
5878 6,
5879 7,
5880 8,
5881 9,
5882 10,
5883 11,
5884 12,
5885 13,
5886 14,
5887 15,
5888 16,
5889 17,
5890 18,
5891 19,
5892 20,
5893 21,
5894 22,
5895 23,
5896 24,
5897 25,
5898 26,
5899 27,
5900 28,
5901 29,
5902 0,
5903 1,
5904 2,
5905 3,
5906 4,
5907 5,
5908 6,
5909 7,
5910 8,
5911 9,
5912 10,
5913 11,
5914 12,
5915 13,
5916 14,
5917 0,
5918 1,
5919 2,
5920 3,
5921 4,
5922 5,
5923 6,
5924 7,
5925 8,
5926 9,
5927 10,
5928 11,
5929 12,
5930 0,
5931 2,
5932 4,
5933 6,
5934 8,
5935 10,
5936 12,
5937 0,
5938 1,
5939 2,
5940 3,
5941 4,
5942 5,
5943 6,
5944 7,
5945 8,
5946 9,
5947 10,
5948 11,
5949 12,
5950 13,
5951 14,
5952 15,
5953 16,
5954 17,
5955 18,
5956 19,
5957 20,
5958 21,
5959 22,
5960 23,
5961 24,
5962 25,
5963 26,
5964 27,
5965 28,
5966 29,
5967 0,
5968 1,
5969 2,
5970 3,
5971 4,
5972 5,
5973 6,
5974 7,
5975 8,
5976 9,
5977 10,
5978 11,
5979 12,
5980 13,
5981 14,
5982 15,
5983 16,
5984 17,
5985 18,
5986 19,
5987 20,
5988 21,
5989 22,
5990 23,
5991 24,
5992 25,
5993 26,
5994 27,
5995 0,
5996 1,
5997 2,
5998 3,
5999 4,
6000 5,
6001 6,
6002 7,
6003 8,
6004 9,
6005 10,
6006 11,
6007 12,
6008 13,
6009 14,
6010 15,
6011 16,
6012 17,
6013 18,
6014 19,
6015 20,
6016 21,
6017 22,
6018 23,
6019 24,
6020 25,
6021 1,
6022 3,
6023 5,
6024 7,
6025 9,
6026 11,
6027 13,
6028 15,
6029 17,
6030 19,
6031 21,
6032 23,
6033 25,
6034 27,
6035 29,
6036 1,
6037 3,
6038 5,
6039 7,
6040 9,
6041 11,
6042 13,
6043 15,
6044 17,
6045 19,
6046 21,
6047 23,
6048 25,
6049 27,
6050};
6051static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
6052 RI->InitMCRegisterInfo(D: ARMRegDesc, NR: 297, RA, PC, C: ARMMCRegisterClassStorage.Classes, NC: 137, RURoots: ARMRegUnitRoots, NRU: 88, DL: ARMRegDiffLists, RUMS: ARMLaneMaskLists, Strings: ARMRegStrings, ClassStrings: ARMRegClassStrings, SubIndices: ARMSubRegIdxLists, NumIndices: 57,
6053RET: ARMRegEncodingTable, RUI: nullptr);
6054
6055 switch (DwarfFlavour) {
6056 default:
6057 llvm_unreachable("Unknown DWARF flavour");
6058 case 0:
6059 RI->mapDwarfRegsToLLVMRegs(Map: ARMDwarfFlavour0Dwarf2L, Size: ARMDwarfFlavour0Dwarf2LSize, isEH: false);
6060 break;
6061 }
6062 switch (EHFlavour) {
6063 default:
6064 llvm_unreachable("Unknown DWARF flavour");
6065 case 0:
6066 RI->mapDwarfRegsToLLVMRegs(Map: ARMEHFlavour0Dwarf2L, Size: ARMEHFlavour0Dwarf2LSize, isEH: true);
6067 break;
6068 }
6069 switch (DwarfFlavour) {
6070 default:
6071 llvm_unreachable("Unknown DWARF flavour");
6072 case 0:
6073 RI->mapLLVMRegsToDwarfRegs(Map: ARMDwarfFlavour0L2Dwarf, Size: ARMDwarfFlavour0L2DwarfSize, isEH: false);
6074 break;
6075 }
6076 switch (EHFlavour) {
6077 default:
6078 llvm_unreachable("Unknown DWARF flavour");
6079 case 0:
6080 RI->mapLLVMRegsToDwarfRegs(Map: ARMEHFlavour0L2Dwarf, Size: ARMEHFlavour0L2DwarfSize, isEH: true);
6081 break;
6082 }
6083}
6084
6085
6086} // namespace llvm
6087