1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t ARMRegDiffLists[] = {
12 /* 0 */ -248, 1, 1, 1, 230, 1, -136, 65, -64, 65, -140, 0,
13 /* 12 */ -249, 1, 1, 1, 231, 1, -137, 65, -64, 65, -139, 0,
14 /* 24 */ -250, 1, 1, 1, 232, 1, -138, 65, -64, 65, -138, 0,
15 /* 36 */ -251, 1, 1, 1, 233, 1, -139, 65, -64, 65, -137, 0,
16 /* 48 */ -252, 1, 1, 1, 234, 1, -140, 65, -64, 65, -136, 0,
17 /* 60 */ -253, 1, 1, 1, 235, 1, -141, 65, -64, 65, -135, 0,
18 /* 72 */ -15, -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, -117, -91, -23, 1, 23, -22, 1, 95, 65, -64, 65, 69, -44, 28, -27, 28, 28, -150, 65, 30, -94, 65, 30, 40, 15, -134, 0,
19 /* 111 */ -15, -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, -117, -91, -24, 1, 24, -23, 1, 95, 65, -64, 65, 70, -45, 28, -27, 28, 29, -151, 65, 30, -94, 65, 30, 41, 15, -134, 0,
20 /* 150 */ -15, -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, -117, -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, -46, 28, -27, 28, 30, -152, 65, 30, -94, 65, 30, 42, 15, -134, 0,
21 /* 189 */ -15, -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, -117, -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, -47, 28, -27, 28, 31, -153, 65, 30, -94, 65, 30, 43, 15, -134, 0,
22 /* 228 */ -15, -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, -117, -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, -48, 28, -27, 28, 32, -154, 65, 30, -94, 65, 30, 44, 15, -134, 0,
23 /* 267 */ -15, -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, -117, -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, -49, 28, -27, 28, 33, -155, 65, 30, -94, 65, 30, 45, 15, -134, 0,
24 /* 310 */ -15, -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, -117, -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, -50, 28, -27, 28, 34, -156, 65, 30, -94, 65, 30, 46, 15, -134, 0,
25 /* 357 */ -15, -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, -117, -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, -51, 28, -27, 28, 35, -157, 65, 30, -94, 65, 30, 47, 15, -134, 0,
26 /* 408 */ -15, -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, -117, -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, -52, 28, -27, 28, 36, -158, 65, 30, -94, 65, 30, 48, 15, -134, 0,
27 /* 463 */ -15, -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, -117, -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, -53, 28, -27, 28, 37, -159, 65, 30, -94, 65, 30, 49, 15, -134, 0,
28 /* 518 */ -15, -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, -117, -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, -54, 28, -27, 28, 38, -160, 65, 30, -94, 65, 30, 50, 15, -134, 0,
29 /* 573 */ -15, -91, -36, 68, 1, -68, 69, 1, -34, -35, 70, 1, -70, 71, 1, 23, 65, -64, 65, 82, -117, -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, -55, 28, -27, 28, 39, -161, 65, 30, -94, 65, 30, 51, 15, -134, 0,
30 /* 628 */ -15, -91, -37, 66, 1, -66, 67, 1, -31, -36, 68, 1, -68, 69, 1, 25, 65, -64, 65, 83, -117, -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, -56, 28, -27, 28, 40, -162, 65, 30, -94, 65, 30, 52, 15, -134, 0,
31 /* 683 */ -254, 81, 1, -81, 1, 1, 236, 1, -142, 65, -64, 65, -134, 0,
32 /* 697 */ -255, 79, 1, -79, 80, 1, -80, 81, 1, -81, 237, 1, -143, 65, -64, 65, -133, 0,
33 /* 715 */ -256, 77, 1, -77, 78, 1, -78, 79, 1, -79, 80, 1, 157, 1, -144, 65, -64, 65, -132, 0,
34 /* 735 */ -257, 75, 1, -75, 76, 1, -76, 77, 1, -77, 78, 1, 160, 1, -145, 65, -64, 65, -131, 0,
35 /* 755 */ -258, 73, 1, -73, 74, 1, -74, 75, 1, -75, 76, 1, 163, 1, -146, 65, -64, 65, -130, 0,
36 /* 775 */ -259, 71, 1, -71, 72, 1, -72, 73, 1, -73, 74, 1, 166, 1, -147, 65, -64, 65, -129, 0,
37 /* 795 */ -260, 69, 1, -69, 70, 1, -70, 71, 1, -71, 72, 1, 169, 1, -148, 65, -64, 65, -128, 0,
38 /* 815 */ -261, 67, 1, -67, 68, 1, -68, 69, 1, -69, 70, 1, 172, 1, -149, 65, -64, 65, -127, 0,
39 /* 835 */ 23, 73, 2, 63, -48, 120, -71, 1, -49, 75, 26, -89, 65, 26, 30, -120, 66, 26, 29, -120, 0,
40 /* 856 */ 22, 74, 2, 63, -49, 120, -70, 1, -50, 76, 26, -90, 66, 26, 29, -120, 0,
41 /* 873 */ 65, -49, 77, 26, -90, 66, 26, 29, -120, 0,
42 /* 883 */ 23, 73, 2, 134, -71, 1, -49, 50, -49, 75, 26, 31, -120, 65, 26, 30, -120, 0,
43 /* 901 */ 22, 74, 135, -70, 1, -50, 77, 26, 30, -120, 0,
44 /* 912 */ 65, -49, 77, 26, 30, -120, 0,
45 /* 919 */ -71, 1, -49, 133, -120, 121, -120, 0,
46 /* 927 */ 139, -49, 50, -49, 12, 121, -120, 0,
47 /* 935 */ -49, 13, 121, -120, 0,
48 /* 940 */ -70, 1, -50, 133, -120, 0,
49 /* 946 */ -49, 133, -120, 0,
50 /* 950 */ -68, 36, 62, 148, -84, 1, -36, 66, 28, 40, -119, 0,
51 /* 962 */ -67, 36, 62, 148, -84, 1, -36, 66, 28, 40, -119, 0,
52 /* 974 */ 65, -36, 66, 28, 40, -119, 0,
53 /* 981 */ -84, 1, -36, 134, -119, 0,
54 /* 987 */ -221, 75, 1, -74, 77, 1, -76, 79, 1, -78, 81, 1, 10, 95, -93, 95, -93, 0,
55 /* 1005 */ -221, 74, 1, -73, 76, 1, -75, 78, 1, -77, 80, 1, 11, 95, -93, 95, -93, 0,
56 /* 1023 */ -221, 73, 1, -72, 75, 1, -74, 77, 1, -76, 79, 1, 12, 95, -93, 95, -93, 0,
57 /* 1041 */ -221, 72, 1, -71, 74, 1, -73, 76, 1, -75, 78, 1, 13, 95, -93, 95, -93, 0,
58 /* 1059 */ -221, 71, 1, -70, 73, 1, -72, 75, 1, -74, 77, 1, 14, 95, -93, 95, -93, 0,
59 /* 1077 */ -221, 70, 1, -69, 72, 1, -71, 74, 1, -73, 76, 1, 15, 95, -93, 95, -93, 0,
60 /* 1095 */ -221, 69, 1, -68, 71, 1, -70, 73, 1, -72, 75, 1, 16, 95, -93, 95, -93, 0,
61 /* 1113 */ -221, 68, 1, -67, 70, 1, -69, 72, 1, -71, 74, 1, 17, 95, -93, 95, -93, 0,
62 /* 1131 */ -221, 67, 1, -66, 69, 1, -68, 71, 1, -70, 73, 1, 18, 95, -93, 95, -93, 0,
63 /* 1149 */ -221, 66, 1, -65, 68, 1, -67, 70, 1, -69, 72, 1, 19, 95, -93, 95, -93, 0,
64 /* 1167 */ -221, 77, 1, -76, 79, 1, -78, 81, 1, -80, 92, 95, -93, 95, -93, 0,
65 /* 1183 */ -221, 76, 1, -75, 78, 1, -77, 80, 1, -79, 92, 95, -93, 95, -93, 0,
66 /* 1199 */ -221, 79, 1, -78, 81, 1, -80, 2, 92, 95, -93, 95, -93, 0,
67 /* 1213 */ -221, 78, 1, -77, 80, 1, -79, 2, 92, 95, -93, 95, -93, 0,
68 /* 1227 */ -221, 81, 1, -80, 2, 2, 92, 95, -93, 95, -93, 0,
69 /* 1239 */ -221, 80, 1, -79, 2, 2, 92, 95, -93, 95, -93, 0,
70 /* 1251 */ -221, 2, 2, 2, 92, 95, -93, 95, -93, 0,
71 /* 1261 */ 21, 75, 65, -50, 78, 26, -91, 0,
72 /* 1269 */ 24, 72, 2, 63, -47, 120, -72, 1, -48, 74, 26, -88, 64, 26, 31, -120, 65, 26, 30, -120, 92, -91, 0,
73 /* 1292 */ 65, -48, 76, 26, -89, 65, 26, 30, -120, 92, -91, 0,
74 /* 1304 */ 26, -90, 92, -91, 0,
75 /* 1309 */ 24, 72, 2, 135, -72, 1, -48, 49, -48, 74, 26, 32, -120, 64, 26, 31, -120, 65, 26, -90, 0,
76 /* 1330 */ 65, -48, 76, 26, 31, -120, 65, 26, -90, 0,
77 /* 1340 */ 25, 71, 2, 63, -46, 120, -73, 1, -47, 73, 26, -87, 63, 26, 32, -120, 64, 26, 31, -120, 91, -90, 0,
78 /* 1363 */ 65, -47, 75, 26, -88, 64, 26, 31, -120, 91, -90, 0,
79 /* 1375 */ 25, 71, 2, 136, -73, 1, -47, 48, -47, 73, 26, 33, -120, 63, 26, 32, -120, 64, 26, -89, 91, -90, 0,
80 /* 1398 */ 65, -47, 75, 26, 32, -120, 64, 26, -89, 91, -90, 0,
81 /* 1410 */ 26, 70, 2, 63, -45, 120, -74, 1, -46, 72, 26, -86, 62, 26, 33, -120, 63, 26, 32, -120, 90, -89, 0,
82 /* 1433 */ 65, -46, 74, 26, -87, 63, 26, 32, -120, 90, -89, 0,
83 /* 1445 */ 26, 70, 2, 137, -74, 1, -46, 47, -46, 72, 26, 34, -120, 62, 26, 33, -120, 63, 26, -88, 90, -89, 0,
84 /* 1468 */ 65, -46, 74, 26, 33, -120, 63, 26, -88, 90, -89, 0,
85 /* 1480 */ 27, 69, 2, 63, -44, 120, -75, 1, -45, 71, 26, -85, 61, 26, 34, -120, 62, 26, 33, -120, 89, -88, 0,
86 /* 1503 */ 65, -45, 73, 26, -86, 62, 26, 33, -120, 89, -88, 0,
87 /* 1515 */ 27, 69, 2, 138, -75, 1, -45, 46, -45, 71, 26, 35, -120, 61, 26, 34, -120, 62, 26, -87, 89, -88, 0,
88 /* 1538 */ 65, -45, 73, 26, 34, -120, 62, 26, -87, 89, -88, 0,
89 /* 1550 */ 28, 68, 2, 63, -43, 120, -76, 1, -44, 70, 26, -84, 60, 26, 35, -120, 61, 26, 34, -120, 88, -87, 0,
90 /* 1573 */ 65, -44, 72, 26, -85, 61, 26, 34, -120, 88, -87, 0,
91 /* 1585 */ 28, 68, 2, 139, -76, 1, -44, 45, -44, 70, 26, 36, -120, 60, 26, 35, -120, 61, 26, -86, 88, -87, 0,
92 /* 1608 */ 65, -44, 72, 26, 35, -120, 61, 26, -86, 88, -87, 0,
93 /* 1620 */ -82, 29, 67, 2, 63, -42, 120, -77, 1, -43, 69, 26, -83, 59, 26, 36, -120, 60, 26, 35, -120, 87, -86, 0,
94 /* 1644 */ -81, 29, 67, 2, 63, -42, 120, -77, 1, -43, 69, 26, -83, 59, 26, 36, -120, 60, 26, 35, -120, 87, -86, 0,
95 /* 1668 */ 65, -43, 71, 26, -84, 60, 26, 35, -120, 87, -86, 0,
96 /* 1680 */ 29, 67, 2, 140, -77, 1, -43, 44, -43, 69, 26, 37, -120, 59, 26, 36, -120, 60, 26, -85, 87, -86, 0,
97 /* 1703 */ 65, -43, 71, 26, 36, -120, 60, 26, -85, 87, -86, 0,
98 /* 1715 */ -80, 30, 66, 2, 63, -41, 120, -78, 1, -42, 68, 26, -82, 58, 26, 37, -120, 59, 26, 36, -120, 86, -85, 0,
99 /* 1739 */ -79, 30, 66, 2, 63, -41, 120, -78, 1, -42, 68, 26, -82, 58, 26, 37, -120, 59, 26, 36, -120, 86, -85, 0,
100 /* 1763 */ 65, -42, 70, 26, -83, 59, 26, 36, -120, 86, -85, 0,
101 /* 1775 */ -81, 30, 66, 2, 141, -78, 1, -42, 43, -42, 68, 26, 38, -120, 58, 26, 37, -120, 59, 26, -84, 86, -85, 0,
102 /* 1799 */ -80, 30, 66, 2, 141, -78, 1, -42, 43, -42, 68, 26, 38, -120, 58, 26, 37, -120, 59, 26, -84, 86, -85, 0,
103 /* 1823 */ 65, -42, 70, 26, 37, -120, 59, 26, -84, 86, -85, 0,
104 /* 1835 */ -78, 31, 65, 2, 63, -40, 120, -79, 1, -41, 67, 26, -81, 57, 26, 38, -120, 58, 26, 37, -120, 85, -84, 0,
105 /* 1859 */ -77, 31, 65, 2, 63, -40, 120, -79, 1, -41, 67, 26, -81, 57, 26, 38, -120, 58, 26, 37, -120, 85, -84, 0,
106 /* 1883 */ 65, -41, 69, 26, -82, 58, 26, 37, -120, 85, -84, 0,
107 /* 1895 */ -79, 31, 65, 2, 142, -79, 1, -41, 42, -41, 67, 26, 39, -120, 57, 26, 38, -120, 58, 26, -83, 85, -84, 0,
108 /* 1919 */ -78, 31, 65, 2, 142, -79, 1, -41, 42, -41, 67, 26, 39, -120, 57, 26, 38, -120, 58, 26, -83, 85, -84, 0,
109 /* 1943 */ 65, -41, 69, 26, 38, -120, 58, 26, -83, 85, -84, 0,
110 /* 1955 */ -76, 32, 64, 2, 63, -39, 120, -80, 1, -40, 66, 26, -80, 56, 26, 39, -120, 57, 26, 38, -120, 84, -83, 0,
111 /* 1979 */ -75, 32, 64, 2, 63, -39, 120, -80, 1, -40, 66, 26, -80, 56, 26, 39, -120, 57, 26, 38, -120, 84, -83, 0,
112 /* 2003 */ 65, -40, 68, 26, -81, 57, 26, 38, -120, 84, -83, 0,
113 /* 2015 */ -77, 32, 64, 2, 143, -80, 1, -40, 41, -40, 66, 26, 40, -120, 56, 26, 39, -120, 57, 26, -82, 84, -83, 0,
114 /* 2039 */ -76, 32, 64, 2, 143, -80, 1, -40, 41, -40, 66, 26, 40, -120, 56, 26, 39, -120, 57, 26, -82, 84, -83, 0,
115 /* 2063 */ 65, -40, 68, 26, 39, -120, 57, 26, -82, 84, -83, 0,
116 /* 2075 */ -74, 33, 63, 2, 63, -38, 120, -81, 1, -39, 65, 26, -79, 55, 26, 40, -120, 56, 26, 39, -120, 83, -82, 0,
117 /* 2099 */ -73, 33, 63, 2, 63, -38, 120, -81, 1, -39, 65, 26, -79, 55, 26, 40, -120, 56, 26, 39, -120, 83, -82, 0,
118 /* 2123 */ 65, -39, 67, 26, -80, 56, 26, 39, -120, 83, -82, 0,
119 /* 2135 */ -75, 33, 63, 2, 144, -81, 1, -39, 40, -39, 65, 26, 41, -120, 55, 26, 40, -120, 56, 26, -81, 83, -82, 0,
120 /* 2159 */ -74, 33, 63, 2, 144, -81, 1, -39, 40, -39, 65, 26, 41, -120, 55, 26, 40, -120, 56, 26, -81, 83, -82, 0,
121 /* 2183 */ 65, -39, 67, 26, 40, -120, 56, 26, -81, 83, -82, 0,
122 /* 2195 */ -239, 81, 1, -81, 0,
123 /* 2200 */ -72, 34, 62, 2, 63, -37, 120, -82, 1, -38, 64, 2, 26, 41, -120, 55, 26, 40, -120, 82, -81, 0,
124 /* 2222 */ -71, 34, 62, 2, 63, -37, 120, -82, 1, -38, 64, 2, 26, 41, -120, 55, 26, 40, -120, 82, -81, 0,
125 /* 2244 */ 65, -38, 66, 26, -79, 55, 26, 40, -120, 82, -81, 0,
126 /* 2256 */ -73, 34, 62, 2, 145, -82, 1, -38, 39, -38, 64, 26, 42, -120, 54, 26, 41, -120, 55, 26, -80, 82, -81, 0,
127 /* 2280 */ -72, 34, 62, 2, 145, -82, 1, -38, 39, -38, 64, 26, 42, -120, 54, 26, 41, -120, 55, 26, -80, 82, -81, 0,
128 /* 2304 */ 65, -38, 66, 26, 41, -120, 55, 26, -80, 82, -81, 0,
129 /* 2316 */ -98, 81, 1, -80, 0,
130 /* 2321 */ -70, 35, 61, 2, 63, -36, 120, -83, 1, -37, 65, 2, 26, 40, 1, -120, 81, -80, 0,
131 /* 2340 */ -69, 35, 61, 2, 63, -36, 120, -83, 1, -37, 65, 2, 26, 40, 1, -120, 81, -80, 0,
132 /* 2359 */ 65, -37, 65, 2, 26, 41, -120, 81, -80, 0,
133 /* 2369 */ -71, 35, 61, 2, 146, -83, 1, -37, 38, -37, 63, 2, 26, 41, 1, -120, 54, 26, -79, 81, -80, 0,
134 /* 2391 */ -70, 35, 61, 2, 146, -83, 1, -37, 38, -37, 63, 2, 26, 41, 1, -120, 54, 26, -79, 81, -80, 0,
135 /* 2413 */ 65, -37, 65, 26, 42, -120, 54, 26, -79, 81, -80, 0,
136 /* 2425 */ -98, 80, 1, -79, 0,
137 /* 2430 */ 28, -79, 0,
138 /* 2433 */ -69, 36, 60, 2, 147, -84, 1, -36, 37, -36, 64, 2, 26, 41, -119, 80, -79, 0,
139 /* 2451 */ -68, 36, 60, 2, 147, -84, 1, -36, 37, -36, 64, 2, 26, 41, -119, 80, -79, 0,
140 /* 2469 */ 65, -36, 64, 2, 26, 41, -119, 80, -79, 0,
141 /* 2479 */ 26, -78, 80, -79, 0,
142 /* 2484 */ -67, 37, 61, 65, -35, 65, 28, -78, 0,
143 /* 2493 */ -66, 37, 61, 65, -35, 65, 28, -78, 0,
144 /* 2502 */ -163, 1, 1, 230, -134, -75, 0,
145 /* 2509 */ -163, 1, 1, 231, -135, -74, 0,
146 /* 2516 */ -163, 1, 1, 232, -136, -73, 0,
147 /* 2523 */ -163, 1, 1, 233, -137, -72, 0,
148 /* 2530 */ -163, 1, 1, 234, -138, -71, 0,
149 /* 2537 */ -163, 1, 1, 235, -139, -70, 0,
150 /* 2544 */ -163, 1, 1, 236, -140, -69, 0,
151 /* 2551 */ -97, -69, 0,
152 /* 2554 */ -163, 81, 1, -81, 1, 237, -141, -68, 0,
153 /* 2563 */ -163, 79, 1, -79, 80, 1, -80, 81, 1, 156, -142, -67, 0,
154 /* 2576 */ -163, 77, 1, -77, 78, 1, -78, 79, 1, 159, -143, -66, 0,
155 /* 2589 */ -163, 75, 1, -75, 76, 1, -76, 77, 1, 162, -144, -65, 0,
156 /* 2602 */ -163, 73, 1, -73, 74, 1, -74, 75, 1, 165, -145, -64, 0,
157 /* 2615 */ -163, 71, 1, -71, 72, 1, -72, 73, 1, 168, -146, -63, 0,
158 /* 2628 */ -163, 69, 1, -69, 70, 1, -70, 71, 1, 171, -147, -62, 0,
159 /* 2641 */ -163, 67, 1, -67, 68, 1, -68, 69, 1, 174, -148, -61, 0,
160 /* 2654 */ -238, 1, 0,
161 /* 2657 */ -237, 1, 0,
162 /* 2660 */ -236, 1, 0,
163 /* 2663 */ -235, 1, 0,
164 /* 2666 */ -234, 1, 0,
165 /* 2669 */ -233, 1, 0,
166 /* 2672 */ -232, 1, 0,
167 /* 2675 */ -83, 1, -37, 133, 1, -120, 1, 0,
168 /* 2683 */ -72, 1, -48, 133, -120, 121, -120, 1, 0,
169 /* 2692 */ -73, 1, -47, 133, -120, 121, -120, 1, 0,
170 /* 2701 */ -74, 1, -46, 133, -120, 121, -120, 1, 0,
171 /* 2710 */ -75, 1, -45, 133, -120, 121, -120, 1, 0,
172 /* 2719 */ -76, 1, -44, 133, -120, 121, -120, 1, 0,
173 /* 2728 */ -77, 1, -43, 133, -120, 121, -120, 1, 0,
174 /* 2737 */ -78, 1, -42, 133, -120, 121, -120, 1, 0,
175 /* 2746 */ -79, 1, -41, 133, -120, 121, -120, 1, 0,
176 /* 2755 */ -80, 1, -40, 133, -120, 121, -120, 1, 0,
177 /* 2764 */ -81, 1, -39, 133, -120, 121, -120, 1, 0,
178 /* 2773 */ -82, 1, -38, 133, -120, 121, -120, 1, 0,
179 /* 2782 */ 138, -48, 49, -48, 12, 121, -120, 1, 0,
180 /* 2791 */ -48, 13, 121, -120, 1, 0,
181 /* 2797 */ -47, 13, 121, -120, 1, 0,
182 /* 2803 */ -46, 13, 121, -120, 1, 0,
183 /* 2809 */ -45, 13, 121, -120, 1, 0,
184 /* 2815 */ -44, 13, 121, -120, 1, 0,
185 /* 2821 */ -43, 13, 121, -120, 1, 0,
186 /* 2827 */ -42, 13, 121, -120, 1, 0,
187 /* 2833 */ -41, 13, 121, -120, 1, 0,
188 /* 2839 */ -40, 13, 121, -120, 1, 0,
189 /* 2845 */ -39, 13, 121, -120, 1, 0,
190 /* 2851 */ -38, 13, 121, -120, 1, 0,
191 /* 2857 */ -48, 133, -120, 1, 0,
192 /* 2862 */ -37, 134, -120, 1, 0,
193 /* 2867 */ 126, -36, 37, -36, 133, -119, 1, 0,
194 /* 2875 */ -103, 1, 0,
195 /* 2878 */ -102, 1, 0,
196 /* 2881 */ -101, 1, 0,
197 /* 2884 */ -100, 1, 0,
198 /* 2887 */ -99, 1, 0,
199 /* 2890 */ -98, 1, 0,
200 /* 2893 */ -29, 1, 0,
201 /* 2896 */ -28, 1, 0,
202 /* 2899 */ -27, 1, 0,
203 /* 2902 */ -26, 1, 0,
204 /* 2905 */ -25, 1, 0,
205 /* 2908 */ -24, 1, 0,
206 /* 2911 */ -23, 1, 0,
207 /* 2914 */ -22, 1, 0,
208 /* 2917 */ 137, -47, 48, -47, 12, 121, -120, 1, 1, 0,
209 /* 2927 */ 136, -46, 47, -46, 12, 121, -120, 1, 1, 0,
210 /* 2937 */ 135, -45, 46, -45, 12, 121, -120, 1, 1, 0,
211 /* 2947 */ 134, -44, 45, -44, 12, 121, -120, 1, 1, 0,
212 /* 2957 */ 133, -43, 44, -43, 12, 121, -120, 1, 1, 0,
213 /* 2967 */ 132, -42, 43, -42, 12, 121, -120, 1, 1, 0,
214 /* 2977 */ 131, -41, 42, -41, 12, 121, -120, 1, 1, 0,
215 /* 2987 */ 130, -40, 41, -40, 12, 121, -120, 1, 1, 0,
216 /* 2997 */ 129, -39, 40, -39, 12, 121, -120, 1, 1, 0,
217 /* 3007 */ 128, -38, 39, -38, 12, 121, -120, 1, 1, 0,
218 /* 3017 */ -47, 133, -120, 1, 1, 0,
219 /* 3023 */ -46, 133, -120, 1, 1, 0,
220 /* 3029 */ -45, 133, -120, 1, 1, 0,
221 /* 3035 */ -44, 133, -120, 1, 1, 0,
222 /* 3041 */ -43, 133, -120, 1, 1, 0,
223 /* 3047 */ -42, 133, -120, 1, 1, 0,
224 /* 3053 */ -41, 133, -120, 1, 1, 0,
225 /* 3059 */ -40, 133, -120, 1, 1, 0,
226 /* 3065 */ -39, 133, -120, 1, 1, 0,
227 /* 3071 */ -38, 133, -120, 1, 1, 0,
228 /* 3077 */ 127, -37, 38, -37, 133, -120, 1, 1, 0,
229 /* 3086 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
230 /* 3102 */ 13, 1, 1, 0,
231 /* 3106 */ 1, 3, 1, 3, 1, 3, 1, 0,
232 /* 3114 */ 13, 1, 0,
233 /* 3117 */ 14, 1, 0,
234 /* 3120 */ 66, 1, 0,
235 /* 3123 */ -37, 66, 1, -66, 67, 1, 0,
236 /* 3130 */ -246, 67, 1, -67, 68, 1, 0,
237 /* 3137 */ -98, 66, 1, -65, 68, 1, 0,
238 /* 3144 */ -36, 68, 1, -68, 69, 1, 0,
239 /* 3151 */ -98, 67, 1, -66, 69, 1, 0,
240 /* 3158 */ -245, 69, 1, -69, 70, 1, 0,
241 /* 3165 */ -98, 68, 1, -67, 70, 1, 0,
242 /* 3172 */ -35, 70, 1, -70, 71, 1, 0,
243 /* 3179 */ -98, 69, 1, -68, 71, 1, 0,
244 /* 3186 */ -244, 71, 1, -71, 72, 1, 0,
245 /* 3193 */ -98, 70, 1, -69, 72, 1, 0,
246 /* 3200 */ -34, 72, 1, -72, 73, 1, 0,
247 /* 3207 */ -98, 71, 1, -70, 73, 1, 0,
248 /* 3214 */ -243, 73, 1, -73, 74, 1, 0,
249 /* 3221 */ -98, 72, 1, -71, 74, 1, 0,
250 /* 3228 */ -33, 74, 1, -74, 75, 1, 0,
251 /* 3235 */ -98, 73, 1, -72, 75, 1, 0,
252 /* 3242 */ -242, 75, 1, -75, 76, 1, 0,
253 /* 3249 */ -98, 74, 1, -73, 76, 1, 0,
254 /* 3256 */ -32, 76, 1, -76, 77, 1, 0,
255 /* 3263 */ -98, 75, 1, -74, 77, 1, 0,
256 /* 3270 */ -241, 77, 1, -77, 78, 1, 0,
257 /* 3277 */ -98, 76, 1, -75, 78, 1, 0,
258 /* 3284 */ -31, 78, 1, -78, 79, 1, 0,
259 /* 3291 */ -98, 77, 1, -76, 79, 1, 0,
260 /* 3298 */ -240, 79, 1, -79, 80, 1, 0,
261 /* 3305 */ -98, 78, 1, -77, 80, 1, 0,
262 /* 3312 */ -30, 80, 1, -80, 81, 1, 0,
263 /* 3319 */ -98, 79, 1, -78, 81, 1, 0,
264 /* 3326 */ -98, 2, 0,
265 /* 3329 */ 1, 3, 1, 3, 1, 2, 0,
266 /* 3336 */ 1, 3, 1, 2, 2, 0,
267 /* 3342 */ 1, 2, 2, 2, 0,
268 /* 3347 */ 1, 3, 2, 2, 0,
269 /* 3352 */ 1, 3, 1, 3, 2, 0,
270 /* 3358 */ -193, 77, 1, -76, 79, 1, -78, 81, 1, 12, 2, 0,
271 /* 3370 */ -193, 76, 1, -75, 78, 1, -77, 80, 1, 13, 2, 0,
272 /* 3382 */ -193, 75, 1, -74, 77, 1, -76, 79, 1, 14, 2, 0,
273 /* 3394 */ -193, 74, 1, -73, 76, 1, -75, 78, 1, 15, 2, 0,
274 /* 3406 */ -193, 73, 1, -72, 75, 1, -74, 77, 1, 16, 2, 0,
275 /* 3418 */ -193, 72, 1, -71, 74, 1, -73, 76, 1, 17, 2, 0,
276 /* 3430 */ -193, 71, 1, -70, 73, 1, -72, 75, 1, 18, 2, 0,
277 /* 3442 */ -193, 70, 1, -69, 72, 1, -71, 74, 1, 19, 2, 0,
278 /* 3454 */ -193, 69, 1, -68, 71, 1, -70, 73, 1, 20, 2, 0,
279 /* 3466 */ -193, 68, 1, -67, 70, 1, -69, 72, 1, 21, 2, 0,
280 /* 3478 */ -193, 67, 1, -66, 69, 1, -68, 71, 1, 22, 2, 0,
281 /* 3490 */ -193, 66, 1, -65, 68, 1, -67, 70, 1, 23, 2, 0,
282 /* 3502 */ -193, 79, 1, -78, 81, 1, -80, 94, 2, 0,
283 /* 3512 */ -193, 78, 1, -77, 80, 1, -79, 94, 2, 0,
284 /* 3522 */ -193, 81, 1, -80, 2, 94, 2, 0,
285 /* 3530 */ -193, 80, 1, -79, 2, 94, 2, 0,
286 /* 3538 */ -193, 2, 2, 94, 2, 0,
287 /* 3544 */ 1, 3, 1, 3, 1, 3, 0,
288 /* 3551 */ 140, -50, 13, 0,
289 /* 3555 */ 126, -35, 15, 0,
290 /* 3559 */ -91, -23, 1, 23, -22, 1, 95, 65, -64, 65, 69, 0,
291 /* 3571 */ -91, -24, 1, 24, -23, 1, 95, 65, -64, 65, 70, 0,
292 /* 3583 */ -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, 0,
293 /* 3595 */ -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, 0,
294 /* 3607 */ -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, 0,
295 /* 3619 */ -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, 0,
296 /* 3631 */ -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, 0,
297 /* 3643 */ -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, 0,
298 /* 3659 */ -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, 0,
299 /* 3679 */ -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, 0,
300 /* 3699 */ -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, 0,
301 /* 3719 */ -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, 0,
302 /* 3739 */ -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, 0,
303 /* 3759 */ -91, -36, 68, 1, -68, 69, 1, -34, -35, 70, 1, -70, 71, 1, 23, 65, -64, 65, 82, 0,
304 /* 3779 */ -91, -37, 66, 1, -66, 67, 1, -31, -36, 68, 1, -68, 69, 1, 25, 65, -64, 65, 83, 0,
305 /* 3799 */ 97, 0,
306 /* 3801 */ 98, 0,
307 /* 3803 */ 99, 0,
308 /* 3805 */ 100, 0,
309 /* 3807 */ 101, 0,
310 /* 3809 */ 102, 0,
311 /* 3811 */ 103, 0,
312 /* 3813 */ -163, 1, 1, 21, 75, 135, 0,
313 /* 3820 */ -163, 1, 1, 22, 74, 136, 0,
314 /* 3827 */ -163, 1, 1, 23, 73, 137, 0,
315 /* 3834 */ -163, 1, 1, 24, 72, 138, 0,
316 /* 3841 */ -163, 1, 1, 25, 71, 139, 0,
317 /* 3848 */ -163, 1, 1, 26, 70, 140, 0,
318 /* 3855 */ -163, 1, 1, 27, 69, 141, 0,
319 /* 3862 */ -163, 80, 1, -80, 81, 1, -81, 28, 68, 142, 0,
320 /* 3873 */ -163, 78, 1, -78, 79, 1, -79, 80, 1, -52, 67, 143, 0,
321 /* 3886 */ -163, 76, 1, -76, 77, 1, -77, 78, 1, -49, 66, 144, 0,
322 /* 3899 */ -163, 74, 1, -74, 75, 1, -75, 76, 1, -46, 65, 145, 0,
323 /* 3912 */ -163, 72, 1, -72, 73, 1, -73, 74, 1, -43, 64, 146, 0,
324 /* 3925 */ -163, 70, 1, -70, 71, 1, -71, 72, 1, -40, 63, 147, 0,
325 /* 3938 */ -163, 68, 1, -68, 69, 1, -69, 70, 1, -37, 62, 148, 0,
326 /* 3951 */ -163, 66, 1, -66, 67, 1, -67, 68, 1, -34, 61, 149, 0,
327 /* 3964 */ 166, 0,
328};
329
330extern const LaneBitmask ARMLaneMaskLists[] = {
331 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
332 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002),
333 /* 4 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
334 /* 6 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020),
335 /* 10 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000030),
336 /* 13 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030),
337 /* 15 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080),
338 /* 19 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080),
339 /* 25 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x00000000000000C0),
340 /* 28 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x00000000000000C0),
341 /* 30 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x00000000000000C0),
342 /* 35 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0),
343 /* 39 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0),
344 /* 42 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200),
345 /* 50 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000300),
346 /* 57 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300),
347 /* 63 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300),
348 /* 68 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300),
349 /* 72 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800),
350 /* 78 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000C00),
351 /* 83 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00),
352 /* 87 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00),
353 /* 90 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000),
354 /* 98 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x000000000000C000),
355 /* 105 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000C00), LaneBitmask(0x000000000000C000),
356 /* 111 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00), LaneBitmask(0x000000000000C000),
357 /* 116 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000C00), LaneBitmask(0x000000000000C000),
358 /* 120 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000020000),
359 /* 136 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
360 /* 150 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000C00), LaneBitmask(0x0000000000003000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
361 /* 162 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300), LaneBitmask(0x0000000000000C00), LaneBitmask(0x0000000000003000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
362 /* 172 */ LaneBitmask(0x000000000000000C), LaneBitmask(0x0000000000000030), LaneBitmask(0x00000000000000C0), LaneBitmask(0x0000000000000300), LaneBitmask(0x0000000000000C00), LaneBitmask(0x0000000000003000), LaneBitmask(0x000000000000C000), LaneBitmask(0x0000000000030000),
363 /* 180 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF),
364};
365
366extern const uint16_t ARMSubRegIdxLists[] = {
367 /* 0 */ 1, 2,
368 /* 2 */ 1, 17, 18, 2,
369 /* 6 */ 1, 3,
370 /* 8 */ 1, 17, 18, 3,
371 /* 12 */ 9, 10,
372 /* 14 */ 17, 18,
373 /* 16 */ 1, 17, 18, 2, 19, 20,
374 /* 22 */ 1, 17, 18, 3, 21, 22,
375 /* 28 */ 1, 2, 3, 13, 33, 37,
376 /* 34 */ 1, 17, 18, 2, 3, 13, 33, 37,
377 /* 42 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37,
378 /* 52 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37,
379 /* 64 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37,
380 /* 75 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37,
381 /* 90 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37,
382 /* 101 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37,
383 /* 114 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37,
384 /* 131 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37,
385 /* 150 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37,
386 /* 169 */ 1, 3, 5, 33, 43,
387 /* 174 */ 1, 17, 18, 3, 5, 33, 43,
388 /* 181 */ 1, 17, 18, 3, 21, 22, 5, 33, 43,
389 /* 190 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43,
390 /* 201 */ 1, 3, 5, 7, 33, 38, 43, 45, 51,
391 /* 210 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51,
392 /* 221 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51,
393 /* 234 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51,
394 /* 249 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51,
395 /* 266 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
396 /* 304 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
397 /* 346 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
398 /* 392 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
399 /* 442 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56,
400};
401
402
403#ifdef __GNUC__
404#pragma GCC diagnostic push
405#pragma GCC diagnostic ignored "-Woverlength-strings"
406#endif
407extern const char ARMRegStrings[] = {
408 /* 0 */ "D4_D6_D8_D10\000"
409 /* 13 */ "D7_D8_D9_D10\000"
410 /* 26 */ "Q7_Q8_Q9_Q10\000"
411 /* 39 */ "R10\000"
412 /* 43 */ "S10\000"
413 /* 47 */ "D14_D16_D18_D20\000"
414 /* 63 */ "D17_D18_D19_D20\000"
415 /* 79 */ "S20\000"
416 /* 83 */ "D24_D26_D28_D30\000"
417 /* 99 */ "D27_D28_D29_D30\000"
418 /* 115 */ "S30\000"
419 /* 119 */ "D0\000"
420 /* 122 */ "P0\000"
421 /* 125 */ "Q0\000"
422 /* 128 */ "MVFR0\000"
423 /* 134 */ "S0\000"
424 /* 137 */ "D9_D10_D11\000"
425 /* 148 */ "D5_D7_D9_D11\000"
426 /* 161 */ "Q8_Q9_Q10_Q11\000"
427 /* 175 */ "R10_R11\000"
428 /* 183 */ "S11\000"
429 /* 187 */ "D19_D20_D21\000"
430 /* 199 */ "D15_D17_D19_D21\000"
431 /* 215 */ "S21\000"
432 /* 219 */ "D29_D30_D31\000"
433 /* 231 */ "D25_D27_D29_D31\000"
434 /* 247 */ "S31\000"
435 /* 251 */ "D1\000"
436 /* 254 */ "Q0_Q1\000"
437 /* 260 */ "MVFR1\000"
438 /* 266 */ "R0_R1\000"
439 /* 272 */ "S1\000"
440 /* 275 */ "D6_D8_D10_D12\000"
441 /* 289 */ "D9_D10_D11_D12\000"
442 /* 304 */ "Q9_Q10_Q11_Q12\000"
443 /* 319 */ "R12\000"
444 /* 323 */ "S12\000"
445 /* 327 */ "D16_D18_D20_D22\000"
446 /* 343 */ "D19_D20_D21_D22\000"
447 /* 359 */ "S22\000"
448 /* 363 */ "D0_D2\000"
449 /* 369 */ "D0_D1_D2\000"
450 /* 378 */ "Q1_Q2\000"
451 /* 384 */ "MVFR2\000"
452 /* 390 */ "S2\000"
453 /* 393 */ "FPINST2\000"
454 /* 401 */ "D7_D9_D11_D13\000"
455 /* 415 */ "D11_D12_D13\000"
456 /* 427 */ "Q10_Q11_Q12_Q13\000"
457 /* 443 */ "S13\000"
458 /* 447 */ "D17_D19_D21_D23\000"
459 /* 463 */ "D21_D22_D23\000"
460 /* 475 */ "S23\000"
461 /* 479 */ "D1_D3\000"
462 /* 485 */ "D1_D2_D3\000"
463 /* 494 */ "Q0_Q1_Q2_Q3\000"
464 /* 506 */ "R2_R3\000"
465 /* 512 */ "S3\000"
466 /* 515 */ "D8_D10_D12_D14\000"
467 /* 530 */ "D11_D12_D13_D14\000"
468 /* 546 */ "Q11_Q12_Q13_Q14\000"
469 /* 562 */ "S14\000"
470 /* 566 */ "D18_D20_D22_D24\000"
471 /* 582 */ "D21_D22_D23_D24\000"
472 /* 598 */ "S24\000"
473 /* 602 */ "D0_D2_D4\000"
474 /* 611 */ "D1_D2_D3_D4\000"
475 /* 623 */ "Q1_Q2_Q3_Q4\000"
476 /* 635 */ "R4\000"
477 /* 638 */ "S4\000"
478 /* 641 */ "D9_D11_D13_D15\000"
479 /* 656 */ "D13_D14_D15\000"
480 /* 668 */ "Q12_Q13_Q14_Q15\000"
481 /* 684 */ "S15\000"
482 /* 688 */ "D19_D21_D23_D25\000"
483 /* 704 */ "D23_D24_D25\000"
484 /* 716 */ "S25\000"
485 /* 720 */ "D1_D3_D5\000"
486 /* 729 */ "D3_D4_D5\000"
487 /* 738 */ "Q2_Q3_Q4_Q5\000"
488 /* 750 */ "R4_R5\000"
489 /* 756 */ "S5\000"
490 /* 759 */ "D10_D12_D14_D16\000"
491 /* 775 */ "D13_D14_D15_D16\000"
492 /* 791 */ "S16\000"
493 /* 795 */ "D20_D22_D24_D26\000"
494 /* 811 */ "D23_D24_D25_D26\000"
495 /* 827 */ "S26\000"
496 /* 831 */ "D0_D2_D4_D6\000"
497 /* 843 */ "D3_D4_D5_D6\000"
498 /* 855 */ "Q3_Q4_Q5_Q6\000"
499 /* 867 */ "R6\000"
500 /* 870 */ "S6\000"
501 /* 873 */ "D11_D13_D15_D17\000"
502 /* 889 */ "D15_D16_D17\000"
503 /* 901 */ "S17\000"
504 /* 905 */ "D21_D23_D25_D27\000"
505 /* 921 */ "D25_D26_D27\000"
506 /* 933 */ "S27\000"
507 /* 937 */ "D1_D3_D5_D7\000"
508 /* 949 */ "D5_D6_D7\000"
509 /* 958 */ "Q4_Q5_Q6_Q7\000"
510 /* 970 */ "R6_R7\000"
511 /* 976 */ "S7\000"
512 /* 979 */ "D12_D14_D16_D18\000"
513 /* 995 */ "D15_D16_D17_D18\000"
514 /* 1011 */ "S18\000"
515 /* 1015 */ "D22_D24_D26_D28\000"
516 /* 1031 */ "D25_D26_D27_D28\000"
517 /* 1047 */ "S28\000"
518 /* 1051 */ "D2_D4_D6_D8\000"
519 /* 1063 */ "D5_D6_D7_D8\000"
520 /* 1075 */ "Q5_Q6_Q7_Q8\000"
521 /* 1087 */ "R8\000"
522 /* 1090 */ "S8\000"
523 /* 1093 */ "D13_D15_D17_D19\000"
524 /* 1109 */ "D17_D18_D19\000"
525 /* 1121 */ "S19\000"
526 /* 1125 */ "D23_D25_D27_D29\000"
527 /* 1141 */ "D27_D28_D29\000"
528 /* 1153 */ "S29\000"
529 /* 1157 */ "D3_D5_D7_D9\000"
530 /* 1169 */ "D7_D8_D9\000"
531 /* 1178 */ "Q6_Q7_Q8_Q9\000"
532 /* 1190 */ "R8_R9\000"
533 /* 1196 */ "S9\000"
534 /* 1199 */ "PC\000"
535 /* 1202 */ "FPSCR_NZCVQC\000"
536 /* 1215 */ "FPEXC\000"
537 /* 1221 */ "FPSID\000"
538 /* 1227 */ "RA_AUTH_CODE\000"
539 /* 1240 */ "ITSTATE\000"
540 /* 1248 */ "FPSCR_RM\000"
541 /* 1257 */ "R12_SP\000"
542 /* 1264 */ "FPSCR\000"
543 /* 1270 */ "LR\000"
544 /* 1273 */ "VPR\000"
545 /* 1277 */ "APSR\000"
546 /* 1282 */ "CPSR\000"
547 /* 1287 */ "SPSR\000"
548 /* 1292 */ "ZR\000"
549 /* 1295 */ "FPCXTNS\000"
550 /* 1303 */ "FPCXTS\000"
551 /* 1310 */ "FPINST\000"
552 /* 1317 */ "FPSCR_NZCV\000"
553 /* 1328 */ "APSR_NZCV\000"
554};
555#ifdef __GNUC__
556#pragma GCC diagnostic pop
557#endif
558
559extern const MCRegisterDesc ARMRegDesc[] = { // Descriptors
560 { .Name: 12, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
561 { .Name: 1277, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45056, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
562 { .Name: 1328, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45057, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
563 { .Name: 1282, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45058, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
564 { .Name: 1295, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45059, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
565 { .Name: 1303, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45060, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
566 { .Name: 1215, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45061, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
567 { .Name: 1310, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45062, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
568 { .Name: 1264, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 11976711, .RegUnitLaneMasks: 180, .IsConstant: 0, .IsArtificial: 0 },
569 { .Name: 1317, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 13627400, .RegUnitLaneMasks: 181, .IsConstant: 0, .IsArtificial: 0 },
570 { .Name: 1202, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45067, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
571 { .Name: 1248, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 14536713, .RegUnitLaneMasks: 181, .IsConstant: 0, .IsArtificial: 0 },
572 { .Name: 1221, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45069, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
573 { .Name: 1240, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45070, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
574 { .Name: 1270, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45071, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
575 { .Name: 1199, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45072, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
576 { .Name: 1227, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45073, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
577 { .Name: 1261, .SubRegs: 11, .SuperRegs: 3964, .SubRegIndices: 2, .RegUnits: 45074, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
578 { .Name: 1287, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45075, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
579 { .Name: 1273, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45076, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
580 { .Name: 1292, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45077, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
581 { .Name: 119, .SubRegs: 3120, .SuperRegs: 2485, .SubRegIndices: 14, .RegUnits: 10874902, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
582 { .Name: 251, .SubRegs: 3127, .SuperRegs: 951, .SubRegIndices: 14, .RegUnits: 10874904, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
583 { .Name: 366, .SubRegs: 3134, .SuperRegs: 2434, .SubRegIndices: 14, .RegUnits: 10874906, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
584 { .Name: 482, .SubRegs: 3148, .SuperRegs: 2322, .SubRegIndices: 14, .RegUnits: 10874908, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
585 { .Name: 608, .SubRegs: 3162, .SuperRegs: 2370, .SubRegIndices: 14, .RegUnits: 10874910, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
586 { .Name: 726, .SubRegs: 3176, .SuperRegs: 2201, .SubRegIndices: 14, .RegUnits: 10874912, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
587 { .Name: 840, .SubRegs: 3190, .SuperRegs: 2257, .SubRegIndices: 14, .RegUnits: 10874914, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
588 { .Name: 946, .SubRegs: 3204, .SuperRegs: 2076, .SubRegIndices: 14, .RegUnits: 10874916, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
589 { .Name: 1060, .SubRegs: 3218, .SuperRegs: 2136, .SubRegIndices: 14, .RegUnits: 10874918, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
590 { .Name: 1166, .SubRegs: 3232, .SuperRegs: 1956, .SubRegIndices: 14, .RegUnits: 10874920, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
591 { .Name: 9, .SubRegs: 3246, .SuperRegs: 2016, .SubRegIndices: 14, .RegUnits: 10874922, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
592 { .Name: 144, .SubRegs: 3260, .SuperRegs: 1836, .SubRegIndices: 14, .RegUnits: 10874924, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
593 { .Name: 285, .SubRegs: 3274, .SuperRegs: 1896, .SubRegIndices: 14, .RegUnits: 10874926, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
594 { .Name: 411, .SubRegs: 3288, .SuperRegs: 1716, .SubRegIndices: 14, .RegUnits: 10874928, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
595 { .Name: 526, .SubRegs: 3302, .SuperRegs: 1776, .SubRegIndices: 14, .RegUnits: 10874930, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
596 { .Name: 652, .SubRegs: 3316, .SuperRegs: 1621, .SubRegIndices: 14, .RegUnits: 10874932, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
597 { .Name: 771, .SubRegs: 11, .SuperRegs: 1680, .SubRegIndices: 2, .RegUnits: 45110, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
598 { .Name: 885, .SubRegs: 11, .SuperRegs: 1550, .SubRegIndices: 2, .RegUnits: 45111, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
599 { .Name: 991, .SubRegs: 11, .SuperRegs: 1585, .SubRegIndices: 2, .RegUnits: 45112, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
600 { .Name: 1105, .SubRegs: 11, .SuperRegs: 1480, .SubRegIndices: 2, .RegUnits: 45113, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
601 { .Name: 59, .SubRegs: 11, .SuperRegs: 1515, .SubRegIndices: 2, .RegUnits: 45114, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
602 { .Name: 195, .SubRegs: 11, .SuperRegs: 1410, .SubRegIndices: 2, .RegUnits: 45115, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
603 { .Name: 339, .SubRegs: 11, .SuperRegs: 1445, .SubRegIndices: 2, .RegUnits: 45116, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
604 { .Name: 459, .SubRegs: 11, .SuperRegs: 1340, .SubRegIndices: 2, .RegUnits: 45117, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
605 { .Name: 578, .SubRegs: 11, .SuperRegs: 1375, .SubRegIndices: 2, .RegUnits: 45118, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
606 { .Name: 700, .SubRegs: 11, .SuperRegs: 1269, .SubRegIndices: 2, .RegUnits: 45119, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
607 { .Name: 807, .SubRegs: 11, .SuperRegs: 1309, .SubRegIndices: 2, .RegUnits: 45120, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
608 { .Name: 917, .SubRegs: 11, .SuperRegs: 835, .SubRegIndices: 2, .RegUnits: 45121, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
609 { .Name: 1027, .SubRegs: 11, .SuperRegs: 883, .SubRegIndices: 2, .RegUnits: 45122, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
610 { .Name: 1137, .SubRegs: 11, .SuperRegs: 856, .SubRegIndices: 2, .RegUnits: 45123, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
611 { .Name: 95, .SubRegs: 11, .SuperRegs: 901, .SubRegIndices: 2, .RegUnits: 45124, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
612 { .Name: 227, .SubRegs: 11, .SuperRegs: 1261, .SubRegIndices: 2, .RegUnits: 45125, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
613 { .Name: 393, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45126, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
614 { .Name: 128, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45127, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
615 { .Name: 260, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45128, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
616 { .Name: 384, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45129, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
617 { .Name: 122, .SubRegs: 11, .SuperRegs: 11, .SubRegIndices: 2, .RegUnits: 45130, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
618 { .Name: 125, .SubRegs: 3123, .SuperRegs: 3555, .SubRegIndices: 16, .RegUnits: 12689430, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
619 { .Name: 257, .SubRegs: 3144, .SuperRegs: 2867, .SubRegIndices: 16, .RegUnits: 12689434, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
620 { .Name: 381, .SubRegs: 3172, .SuperRegs: 3077, .SubRegIndices: 16, .RegUnits: 12689438, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
621 { .Name: 503, .SubRegs: 3200, .SuperRegs: 3007, .SubRegIndices: 16, .RegUnits: 12689442, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
622 { .Name: 632, .SubRegs: 3228, .SuperRegs: 2997, .SubRegIndices: 16, .RegUnits: 12689446, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
623 { .Name: 747, .SubRegs: 3256, .SuperRegs: 2987, .SubRegIndices: 16, .RegUnits: 12689450, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
624 { .Name: 864, .SubRegs: 3284, .SuperRegs: 2977, .SubRegIndices: 16, .RegUnits: 12689454, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
625 { .Name: 967, .SubRegs: 3312, .SuperRegs: 2967, .SubRegIndices: 16, .RegUnits: 12689458, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
626 { .Name: 1084, .SubRegs: 2893, .SuperRegs: 2957, .SubRegIndices: 0, .RegUnits: 10874934, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
627 { .Name: 1187, .SubRegs: 2896, .SuperRegs: 2947, .SubRegIndices: 0, .RegUnits: 10874936, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
628 { .Name: 35, .SubRegs: 2899, .SuperRegs: 2937, .SubRegIndices: 0, .RegUnits: 10874938, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
629 { .Name: 171, .SubRegs: 2902, .SuperRegs: 2927, .SubRegIndices: 0, .RegUnits: 10874940, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
630 { .Name: 315, .SubRegs: 2905, .SuperRegs: 2917, .SubRegIndices: 0, .RegUnits: 10874942, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
631 { .Name: 439, .SubRegs: 2908, .SuperRegs: 2782, .SubRegIndices: 0, .RegUnits: 10874944, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
632 { .Name: 558, .SubRegs: 2911, .SuperRegs: 927, .SubRegIndices: 0, .RegUnits: 10874946, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
633 { .Name: 680, .SubRegs: 2914, .SuperRegs: 3551, .SubRegIndices: 0, .RegUnits: 10874948, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
634 { .Name: 131, .SubRegs: 11, .SuperRegs: 3811, .SubRegIndices: 2, .RegUnits: 45131, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
635 { .Name: 263, .SubRegs: 11, .SuperRegs: 3809, .SubRegIndices: 2, .RegUnits: 45132, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
636 { .Name: 387, .SubRegs: 11, .SuperRegs: 3809, .SubRegIndices: 2, .RegUnits: 45133, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
637 { .Name: 509, .SubRegs: 11, .SuperRegs: 3807, .SubRegIndices: 2, .RegUnits: 45134, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
638 { .Name: 635, .SubRegs: 11, .SuperRegs: 3807, .SubRegIndices: 2, .RegUnits: 45135, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
639 { .Name: 753, .SubRegs: 11, .SuperRegs: 3805, .SubRegIndices: 2, .RegUnits: 45136, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
640 { .Name: 867, .SubRegs: 11, .SuperRegs: 3805, .SubRegIndices: 2, .RegUnits: 45137, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
641 { .Name: 973, .SubRegs: 11, .SuperRegs: 3803, .SubRegIndices: 2, .RegUnits: 45138, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
642 { .Name: 1087, .SubRegs: 11, .SuperRegs: 3803, .SubRegIndices: 2, .RegUnits: 45139, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
643 { .Name: 1193, .SubRegs: 11, .SuperRegs: 3801, .SubRegIndices: 2, .RegUnits: 45140, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
644 { .Name: 39, .SubRegs: 11, .SuperRegs: 3801, .SubRegIndices: 2, .RegUnits: 45141, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
645 { .Name: 179, .SubRegs: 11, .SuperRegs: 3799, .SubRegIndices: 2, .RegUnits: 45142, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
646 { .Name: 319, .SubRegs: 11, .SuperRegs: 3799, .SubRegIndices: 2, .RegUnits: 45143, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
647 { .Name: 134, .SubRegs: 11, .SuperRegs: 2493, .SubRegIndices: 2, .RegUnits: 45078, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
648 { .Name: 272, .SubRegs: 11, .SuperRegs: 2484, .SubRegIndices: 2, .RegUnits: 45079, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
649 { .Name: 390, .SubRegs: 11, .SuperRegs: 962, .SubRegIndices: 2, .RegUnits: 45080, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
650 { .Name: 512, .SubRegs: 11, .SuperRegs: 950, .SubRegIndices: 2, .RegUnits: 45081, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
651 { .Name: 638, .SubRegs: 11, .SuperRegs: 2451, .SubRegIndices: 2, .RegUnits: 45082, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
652 { .Name: 756, .SubRegs: 11, .SuperRegs: 2433, .SubRegIndices: 2, .RegUnits: 45083, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
653 { .Name: 870, .SubRegs: 11, .SuperRegs: 2340, .SubRegIndices: 2, .RegUnits: 45084, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
654 { .Name: 976, .SubRegs: 11, .SuperRegs: 2321, .SubRegIndices: 2, .RegUnits: 45085, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
655 { .Name: 1090, .SubRegs: 11, .SuperRegs: 2391, .SubRegIndices: 2, .RegUnits: 45086, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
656 { .Name: 1196, .SubRegs: 11, .SuperRegs: 2369, .SubRegIndices: 2, .RegUnits: 45087, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
657 { .Name: 43, .SubRegs: 11, .SuperRegs: 2222, .SubRegIndices: 2, .RegUnits: 45088, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
658 { .Name: 183, .SubRegs: 11, .SuperRegs: 2200, .SubRegIndices: 2, .RegUnits: 45089, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
659 { .Name: 323, .SubRegs: 11, .SuperRegs: 2280, .SubRegIndices: 2, .RegUnits: 45090, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
660 { .Name: 443, .SubRegs: 11, .SuperRegs: 2256, .SubRegIndices: 2, .RegUnits: 45091, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
661 { .Name: 562, .SubRegs: 11, .SuperRegs: 2099, .SubRegIndices: 2, .RegUnits: 45092, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
662 { .Name: 684, .SubRegs: 11, .SuperRegs: 2075, .SubRegIndices: 2, .RegUnits: 45093, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
663 { .Name: 791, .SubRegs: 11, .SuperRegs: 2159, .SubRegIndices: 2, .RegUnits: 45094, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
664 { .Name: 901, .SubRegs: 11, .SuperRegs: 2135, .SubRegIndices: 2, .RegUnits: 45095, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
665 { .Name: 1011, .SubRegs: 11, .SuperRegs: 1979, .SubRegIndices: 2, .RegUnits: 45096, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
666 { .Name: 1121, .SubRegs: 11, .SuperRegs: 1955, .SubRegIndices: 2, .RegUnits: 45097, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
667 { .Name: 79, .SubRegs: 11, .SuperRegs: 2039, .SubRegIndices: 2, .RegUnits: 45098, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
668 { .Name: 215, .SubRegs: 11, .SuperRegs: 2015, .SubRegIndices: 2, .RegUnits: 45099, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
669 { .Name: 359, .SubRegs: 11, .SuperRegs: 1859, .SubRegIndices: 2, .RegUnits: 45100, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
670 { .Name: 475, .SubRegs: 11, .SuperRegs: 1835, .SubRegIndices: 2, .RegUnits: 45101, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
671 { .Name: 598, .SubRegs: 11, .SuperRegs: 1919, .SubRegIndices: 2, .RegUnits: 45102, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
672 { .Name: 716, .SubRegs: 11, .SuperRegs: 1895, .SubRegIndices: 2, .RegUnits: 45103, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
673 { .Name: 827, .SubRegs: 11, .SuperRegs: 1739, .SubRegIndices: 2, .RegUnits: 45104, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
674 { .Name: 933, .SubRegs: 11, .SuperRegs: 1715, .SubRegIndices: 2, .RegUnits: 45105, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
675 { .Name: 1047, .SubRegs: 11, .SuperRegs: 1799, .SubRegIndices: 2, .RegUnits: 45106, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
676 { .Name: 1153, .SubRegs: 11, .SuperRegs: 1775, .SubRegIndices: 2, .RegUnits: 45107, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
677 { .Name: 115, .SubRegs: 11, .SuperRegs: 1644, .SubRegIndices: 2, .RegUnits: 45108, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
678 { .Name: 247, .SubRegs: 11, .SuperRegs: 1620, .SubRegIndices: 2, .RegUnits: 45109, .RegUnitLaneMasks: 182, .IsConstant: 0, .IsArtificial: 0 },
679 { .Name: 363, .SubRegs: 3137, .SuperRegs: 2487, .SubRegIndices: 22, .RegUnits: 12738582, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
680 { .Name: 479, .SubRegs: 3151, .SuperRegs: 974, .SubRegIndices: 22, .RegUnits: 12738584, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
681 { .Name: 605, .SubRegs: 3165, .SuperRegs: 2469, .SubRegIndices: 22, .RegUnits: 12738586, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
682 { .Name: 723, .SubRegs: 3179, .SuperRegs: 2359, .SubRegIndices: 22, .RegUnits: 12738588, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
683 { .Name: 837, .SubRegs: 3193, .SuperRegs: 2413, .SubRegIndices: 22, .RegUnits: 12738590, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
684 { .Name: 943, .SubRegs: 3207, .SuperRegs: 2244, .SubRegIndices: 22, .RegUnits: 12738592, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
685 { .Name: 1057, .SubRegs: 3221, .SuperRegs: 2304, .SubRegIndices: 22, .RegUnits: 12738594, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
686 { .Name: 1163, .SubRegs: 3235, .SuperRegs: 2123, .SubRegIndices: 22, .RegUnits: 12738596, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
687 { .Name: 6, .SubRegs: 3249, .SuperRegs: 2183, .SubRegIndices: 22, .RegUnits: 12738598, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
688 { .Name: 154, .SubRegs: 3263, .SuperRegs: 2003, .SubRegIndices: 22, .RegUnits: 12738600, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
689 { .Name: 281, .SubRegs: 3277, .SuperRegs: 2063, .SubRegIndices: 22, .RegUnits: 12738602, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
690 { .Name: 407, .SubRegs: 3291, .SuperRegs: 1883, .SubRegIndices: 22, .RegUnits: 12738604, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
691 { .Name: 522, .SubRegs: 3305, .SuperRegs: 1943, .SubRegIndices: 22, .RegUnits: 12738606, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
692 { .Name: 648, .SubRegs: 3319, .SuperRegs: 1763, .SubRegIndices: 22, .RegUnits: 12738608, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
693 { .Name: 767, .SubRegs: 2425, .SuperRegs: 1823, .SubRegIndices: 8, .RegUnits: 14532658, .RegUnitLaneMasks: 25, .IsConstant: 0, .IsArtificial: 0 },
694 { .Name: 881, .SubRegs: 2316, .SuperRegs: 1668, .SubRegIndices: 8, .RegUnits: 13652020, .RegUnitLaneMasks: 25, .IsConstant: 0, .IsArtificial: 0 },
695 { .Name: 987, .SubRegs: 3326, .SuperRegs: 1703, .SubRegIndices: 6, .RegUnits: 13627446, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
696 { .Name: 1101, .SubRegs: 3326, .SuperRegs: 1573, .SubRegIndices: 6, .RegUnits: 13627447, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
697 { .Name: 55, .SubRegs: 3326, .SuperRegs: 1608, .SubRegIndices: 6, .RegUnits: 13627448, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
698 { .Name: 207, .SubRegs: 3326, .SuperRegs: 1503, .SubRegIndices: 6, .RegUnits: 13627449, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
699 { .Name: 335, .SubRegs: 3326, .SuperRegs: 1538, .SubRegIndices: 6, .RegUnits: 13627450, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
700 { .Name: 455, .SubRegs: 3326, .SuperRegs: 1433, .SubRegIndices: 6, .RegUnits: 13627451, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
701 { .Name: 574, .SubRegs: 3326, .SuperRegs: 1468, .SubRegIndices: 6, .RegUnits: 13627452, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
702 { .Name: 696, .SubRegs: 3326, .SuperRegs: 1363, .SubRegIndices: 6, .RegUnits: 13627453, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
703 { .Name: 803, .SubRegs: 3326, .SuperRegs: 1398, .SubRegIndices: 6, .RegUnits: 13627454, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
704 { .Name: 913, .SubRegs: 3326, .SuperRegs: 1292, .SubRegIndices: 6, .RegUnits: 13627455, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
705 { .Name: 1023, .SubRegs: 3326, .SuperRegs: 1330, .SubRegIndices: 6, .RegUnits: 13627456, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
706 { .Name: 1133, .SubRegs: 3326, .SuperRegs: 873, .SubRegIndices: 6, .RegUnits: 13627457, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
707 { .Name: 91, .SubRegs: 3326, .SuperRegs: 912, .SubRegIndices: 6, .RegUnits: 13627458, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
708 { .Name: 239, .SubRegs: 3326, .SuperRegs: 1263, .SubRegIndices: 6, .RegUnits: 13627459, .RegUnitLaneMasks: 28, .IsConstant: 0, .IsArtificial: 0 },
709 { .Name: 254, .SubRegs: 3779, .SuperRegs: 3557, .SubRegIndices: 150, .RegUnits: 12673046, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
710 { .Name: 378, .SubRegs: 3759, .SuperRegs: 3117, .SubRegIndices: 150, .RegUnits: 12673050, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
711 { .Name: 500, .SubRegs: 3739, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673054, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
712 { .Name: 629, .SubRegs: 3719, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673058, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
713 { .Name: 744, .SubRegs: 3699, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673062, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
714 { .Name: 861, .SubRegs: 3679, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673066, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
715 { .Name: 964, .SubRegs: 3659, .SuperRegs: 3102, .SubRegIndices: 150, .RegUnits: 12673070, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
716 { .Name: 1081, .SubRegs: 3643, .SuperRegs: 3102, .SubRegIndices: 75, .RegUnits: 12681266, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
717 { .Name: 1184, .SubRegs: 3631, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689462, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
718 { .Name: 32, .SubRegs: 3619, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689464, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
719 { .Name: 167, .SubRegs: 3607, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689466, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
720 { .Name: 311, .SubRegs: 3595, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689468, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
721 { .Name: 435, .SubRegs: 3583, .SuperRegs: 3102, .SubRegIndices: 64, .RegUnits: 12689470, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
722 { .Name: 554, .SubRegs: 3571, .SuperRegs: 3114, .SubRegIndices: 64, .RegUnits: 12689472, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
723 { .Name: 676, .SubRegs: 3559, .SuperRegs: 3553, .SubRegIndices: 64, .RegUnits: 12689474, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
724 { .Name: 494, .SubRegs: 628, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640278, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
725 { .Name: 623, .SubRegs: 573, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640282, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
726 { .Name: 738, .SubRegs: 518, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640286, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
727 { .Name: 855, .SubRegs: 463, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640290, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
728 { .Name: 958, .SubRegs: 408, .SuperRegs: 11, .SubRegIndices: 442, .RegUnits: 12640294, .RegUnitLaneMasks: 120, .IsConstant: 0, .IsArtificial: 0 },
729 { .Name: 1075, .SubRegs: 357, .SuperRegs: 11, .SubRegIndices: 392, .RegUnits: 12648490, .RegUnitLaneMasks: 136, .IsConstant: 0, .IsArtificial: 0 },
730 { .Name: 1178, .SubRegs: 310, .SuperRegs: 11, .SubRegIndices: 346, .RegUnits: 12656686, .RegUnitLaneMasks: 150, .IsConstant: 0, .IsArtificial: 0 },
731 { .Name: 26, .SubRegs: 267, .SuperRegs: 11, .SubRegIndices: 304, .RegUnits: 12664882, .RegUnitLaneMasks: 162, .IsConstant: 0, .IsArtificial: 0 },
732 { .Name: 161, .SubRegs: 228, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673078, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
733 { .Name: 304, .SubRegs: 189, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673080, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
734 { .Name: 427, .SubRegs: 150, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673082, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
735 { .Name: 546, .SubRegs: 111, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673084, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
736 { .Name: 668, .SubRegs: 72, .SuperRegs: 11, .SubRegIndices: 266, .RegUnits: 12673086, .RegUnitLaneMasks: 172, .IsConstant: 0, .IsArtificial: 0 },
737 { .Name: 266, .SubRegs: 2875, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874955, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
738 { .Name: 506, .SubRegs: 2878, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874957, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
739 { .Name: 750, .SubRegs: 2881, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874959, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
740 { .Name: 970, .SubRegs: 2884, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874961, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
741 { .Name: 1190, .SubRegs: 2887, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874963, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
742 { .Name: 175, .SubRegs: 2890, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 10874965, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
743 { .Name: 1257, .SubRegs: 2551, .SuperRegs: 11, .SubRegIndices: 12, .RegUnits: 14618642, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
744 { .Name: 369, .SubRegs: 3951, .SuperRegs: 3556, .SubRegIndices: 52, .RegUnits: 12681238, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
745 { .Name: 485, .SubRegs: 2641, .SuperRegs: 983, .SubRegIndices: 52, .RegUnits: 12681240, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
746 { .Name: 614, .SubRegs: 3938, .SuperRegs: 2870, .SubRegIndices: 52, .RegUnits: 12681242, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
747 { .Name: 729, .SubRegs: 2628, .SuperRegs: 2862, .SubRegIndices: 52, .RegUnits: 12681244, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
748 { .Name: 846, .SubRegs: 3925, .SuperRegs: 3080, .SubRegIndices: 52, .RegUnits: 12681246, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
749 { .Name: 949, .SubRegs: 2615, .SuperRegs: 2851, .SubRegIndices: 52, .RegUnits: 12681248, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
750 { .Name: 1066, .SubRegs: 3912, .SuperRegs: 3071, .SubRegIndices: 52, .RegUnits: 12681250, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
751 { .Name: 1169, .SubRegs: 2602, .SuperRegs: 2845, .SubRegIndices: 52, .RegUnits: 12681252, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
752 { .Name: 16, .SubRegs: 3899, .SuperRegs: 3065, .SubRegIndices: 52, .RegUnits: 12681254, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
753 { .Name: 137, .SubRegs: 2589, .SuperRegs: 2839, .SubRegIndices: 52, .RegUnits: 12681256, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
754 { .Name: 292, .SubRegs: 3886, .SuperRegs: 3059, .SubRegIndices: 52, .RegUnits: 12681258, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
755 { .Name: 415, .SubRegs: 2576, .SuperRegs: 2833, .SubRegIndices: 52, .RegUnits: 12681260, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
756 { .Name: 534, .SubRegs: 3873, .SuperRegs: 3053, .SubRegIndices: 52, .RegUnits: 12681262, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
757 { .Name: 656, .SubRegs: 2563, .SuperRegs: 2827, .SubRegIndices: 52, .RegUnits: 12681264, .RegUnitLaneMasks: 19, .IsConstant: 0, .IsArtificial: 0 },
758 { .Name: 779, .SubRegs: 3862, .SuperRegs: 3047, .SubRegIndices: 42, .RegUnits: 12685362, .RegUnitLaneMasks: 30, .IsConstant: 0, .IsArtificial: 0 },
759 { .Name: 889, .SubRegs: 2554, .SuperRegs: 2821, .SubRegIndices: 34, .RegUnits: 12689460, .RegUnitLaneMasks: 35, .IsConstant: 0, .IsArtificial: 0 },
760 { .Name: 999, .SubRegs: 3855, .SuperRegs: 3041, .SubRegIndices: 28, .RegUnits: 11976758, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
761 { .Name: 1109, .SubRegs: 2544, .SuperRegs: 2815, .SubRegIndices: 28, .RegUnits: 11976759, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
762 { .Name: 67, .SubRegs: 3848, .SuperRegs: 3035, .SubRegIndices: 28, .RegUnits: 11976760, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
763 { .Name: 187, .SubRegs: 2537, .SuperRegs: 2809, .SubRegIndices: 28, .RegUnits: 11976761, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
764 { .Name: 347, .SubRegs: 3841, .SuperRegs: 3029, .SubRegIndices: 28, .RegUnits: 11976762, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
765 { .Name: 463, .SubRegs: 2530, .SuperRegs: 2803, .SubRegIndices: 28, .RegUnits: 11976763, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
766 { .Name: 586, .SubRegs: 3834, .SuperRegs: 3023, .SubRegIndices: 28, .RegUnits: 11976764, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
767 { .Name: 704, .SubRegs: 2523, .SuperRegs: 2797, .SubRegIndices: 28, .RegUnits: 11976765, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
768 { .Name: 815, .SubRegs: 3827, .SuperRegs: 3017, .SubRegIndices: 28, .RegUnits: 11976766, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
769 { .Name: 921, .SubRegs: 2516, .SuperRegs: 2791, .SubRegIndices: 28, .RegUnits: 11976767, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
770 { .Name: 1035, .SubRegs: 3820, .SuperRegs: 2857, .SubRegIndices: 28, .RegUnits: 11976768, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
771 { .Name: 1141, .SubRegs: 2509, .SuperRegs: 935, .SubRegIndices: 28, .RegUnits: 11976769, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
772 { .Name: 103, .SubRegs: 3813, .SuperRegs: 946, .SubRegIndices: 28, .RegUnits: 11976770, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
773 { .Name: 219, .SubRegs: 2502, .SuperRegs: 3552, .SubRegIndices: 28, .RegUnits: 11976771, .RegUnitLaneMasks: 39, .IsConstant: 0, .IsArtificial: 0 },
774 { .Name: 602, .SubRegs: 3490, .SuperRegs: 2490, .SubRegIndices: 190, .RegUnits: 12730390, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
775 { .Name: 720, .SubRegs: 3478, .SuperRegs: 2430, .SubRegIndices: 190, .RegUnits: 12730392, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
776 { .Name: 834, .SubRegs: 3466, .SuperRegs: 2479, .SubRegIndices: 190, .RegUnits: 12730394, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
777 { .Name: 940, .SubRegs: 3454, .SuperRegs: 2386, .SubRegIndices: 190, .RegUnits: 12730396, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
778 { .Name: 1054, .SubRegs: 3442, .SuperRegs: 2386, .SubRegIndices: 190, .RegUnits: 12730398, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
779 { .Name: 1160, .SubRegs: 3430, .SuperRegs: 2275, .SubRegIndices: 190, .RegUnits: 12730400, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
780 { .Name: 3, .SubRegs: 3418, .SuperRegs: 2275, .SubRegIndices: 190, .RegUnits: 12730402, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
781 { .Name: 151, .SubRegs: 3406, .SuperRegs: 2154, .SubRegIndices: 190, .RegUnits: 12730404, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
782 { .Name: 278, .SubRegs: 3394, .SuperRegs: 2154, .SubRegIndices: 190, .RegUnits: 12730406, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
783 { .Name: 404, .SubRegs: 3382, .SuperRegs: 2034, .SubRegIndices: 190, .RegUnits: 12730408, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
784 { .Name: 518, .SubRegs: 3370, .SuperRegs: 2034, .SubRegIndices: 190, .RegUnits: 12730410, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
785 { .Name: 644, .SubRegs: 3358, .SuperRegs: 1914, .SubRegIndices: 190, .RegUnits: 12730412, .RegUnitLaneMasks: 72, .IsConstant: 0, .IsArtificial: 0 },
786 { .Name: 763, .SubRegs: 3512, .SuperRegs: 1914, .SubRegIndices: 181, .RegUnits: 14524462, .RegUnitLaneMasks: 78, .IsConstant: 0, .IsArtificial: 0 },
787 { .Name: 877, .SubRegs: 3502, .SuperRegs: 1794, .SubRegIndices: 181, .RegUnits: 13643824, .RegUnitLaneMasks: 78, .IsConstant: 0, .IsArtificial: 0 },
788 { .Name: 983, .SubRegs: 3530, .SuperRegs: 1794, .SubRegIndices: 174, .RegUnits: 13738034, .RegUnitLaneMasks: 83, .IsConstant: 0, .IsArtificial: 0 },
789 { .Name: 1097, .SubRegs: 3522, .SuperRegs: 1698, .SubRegIndices: 174, .RegUnits: 13672500, .RegUnitLaneMasks: 83, .IsConstant: 0, .IsArtificial: 0 },
790 { .Name: 51, .SubRegs: 3538, .SuperRegs: 1698, .SubRegIndices: 169, .RegUnits: 13676598, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
791 { .Name: 203, .SubRegs: 3538, .SuperRegs: 1603, .SubRegIndices: 169, .RegUnits: 13676599, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
792 { .Name: 331, .SubRegs: 3538, .SuperRegs: 1603, .SubRegIndices: 169, .RegUnits: 13676600, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
793 { .Name: 451, .SubRegs: 3538, .SuperRegs: 1533, .SubRegIndices: 169, .RegUnits: 13676601, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
794 { .Name: 570, .SubRegs: 3538, .SuperRegs: 1533, .SubRegIndices: 169, .RegUnits: 13676602, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
795 { .Name: 692, .SubRegs: 3538, .SuperRegs: 1463, .SubRegIndices: 169, .RegUnits: 13676603, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
796 { .Name: 799, .SubRegs: 3538, .SuperRegs: 1463, .SubRegIndices: 169, .RegUnits: 13676604, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
797 { .Name: 909, .SubRegs: 3538, .SuperRegs: 1393, .SubRegIndices: 169, .RegUnits: 13676605, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
798 { .Name: 1019, .SubRegs: 3538, .SuperRegs: 1393, .SubRegIndices: 169, .RegUnits: 13676606, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
799 { .Name: 1129, .SubRegs: 3538, .SuperRegs: 1304, .SubRegIndices: 169, .RegUnits: 13676607, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
800 { .Name: 87, .SubRegs: 3538, .SuperRegs: 1327, .SubRegIndices: 169, .RegUnits: 13676608, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
801 { .Name: 235, .SubRegs: 3538, .SuperRegs: 1266, .SubRegIndices: 169, .RegUnits: 13676609, .RegUnitLaneMasks: 87, .IsConstant: 0, .IsArtificial: 0 },
802 { .Name: 831, .SubRegs: 1149, .SuperRegs: 2491, .SubRegIndices: 249, .RegUnits: 12722198, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
803 { .Name: 937, .SubRegs: 1131, .SuperRegs: 2428, .SubRegIndices: 249, .RegUnits: 12722200, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
804 { .Name: 1051, .SubRegs: 1113, .SuperRegs: 2428, .SubRegIndices: 249, .RegUnits: 12722202, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
805 { .Name: 1157, .SubRegs: 1095, .SuperRegs: 2319, .SubRegIndices: 249, .RegUnits: 12722204, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
806 { .Name: 0, .SubRegs: 1077, .SuperRegs: 2319, .SubRegIndices: 249, .RegUnits: 12722206, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
807 { .Name: 148, .SubRegs: 1059, .SuperRegs: 2198, .SubRegIndices: 249, .RegUnits: 12722208, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
808 { .Name: 275, .SubRegs: 1041, .SuperRegs: 2198, .SubRegIndices: 249, .RegUnits: 12722210, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
809 { .Name: 401, .SubRegs: 1023, .SuperRegs: 2097, .SubRegIndices: 249, .RegUnits: 12722212, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
810 { .Name: 515, .SubRegs: 1005, .SuperRegs: 2097, .SubRegIndices: 249, .RegUnits: 12722214, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
811 { .Name: 641, .SubRegs: 987, .SuperRegs: 1977, .SubRegIndices: 249, .RegUnits: 12722216, .RegUnitLaneMasks: 90, .IsConstant: 0, .IsArtificial: 0 },
812 { .Name: 759, .SubRegs: 1183, .SuperRegs: 1977, .SubRegIndices: 234, .RegUnits: 14516266, .RegUnitLaneMasks: 98, .IsConstant: 0, .IsArtificial: 0 },
813 { .Name: 873, .SubRegs: 1167, .SuperRegs: 1857, .SubRegIndices: 234, .RegUnits: 13635628, .RegUnitLaneMasks: 98, .IsConstant: 0, .IsArtificial: 0 },
814 { .Name: 979, .SubRegs: 1213, .SuperRegs: 1857, .SubRegIndices: 221, .RegUnits: 13729838, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
815 { .Name: 1093, .SubRegs: 1199, .SuperRegs: 1737, .SubRegIndices: 221, .RegUnits: 13664304, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
816 { .Name: 47, .SubRegs: 1239, .SuperRegs: 1737, .SubRegIndices: 210, .RegUnits: 13709362, .RegUnitLaneMasks: 111, .IsConstant: 0, .IsArtificial: 0 },
817 { .Name: 199, .SubRegs: 1227, .SuperRegs: 1642, .SubRegIndices: 210, .RegUnits: 13688884, .RegUnitLaneMasks: 111, .IsConstant: 0, .IsArtificial: 0 },
818 { .Name: 327, .SubRegs: 1251, .SuperRegs: 1642, .SubRegIndices: 201, .RegUnits: 13692982, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
819 { .Name: 447, .SubRegs: 1251, .SuperRegs: 1571, .SubRegIndices: 201, .RegUnits: 13692983, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
820 { .Name: 566, .SubRegs: 1251, .SuperRegs: 1571, .SubRegIndices: 201, .RegUnits: 13692984, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
821 { .Name: 688, .SubRegs: 1251, .SuperRegs: 1501, .SubRegIndices: 201, .RegUnits: 13692985, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
822 { .Name: 795, .SubRegs: 1251, .SuperRegs: 1501, .SubRegIndices: 201, .RegUnits: 13692986, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
823 { .Name: 905, .SubRegs: 1251, .SuperRegs: 1431, .SubRegIndices: 201, .RegUnits: 13692987, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
824 { .Name: 1015, .SubRegs: 1251, .SuperRegs: 1431, .SubRegIndices: 201, .RegUnits: 13692988, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
825 { .Name: 1125, .SubRegs: 1251, .SuperRegs: 1328, .SubRegIndices: 201, .RegUnits: 13692989, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
826 { .Name: 83, .SubRegs: 1251, .SuperRegs: 1328, .SubRegIndices: 201, .RegUnits: 13692990, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
827 { .Name: 231, .SubRegs: 1251, .SuperRegs: 1267, .SubRegIndices: 201, .RegUnits: 13692991, .RegUnitLaneMasks: 116, .IsConstant: 0, .IsArtificial: 0 },
828 { .Name: 372, .SubRegs: 3130, .SuperRegs: 981, .SubRegIndices: 16, .RegUnits: 12689432, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
829 { .Name: 617, .SubRegs: 3158, .SuperRegs: 2675, .SubRegIndices: 16, .RegUnits: 12689436, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
830 { .Name: 849, .SubRegs: 3186, .SuperRegs: 2773, .SubRegIndices: 16, .RegUnits: 12689440, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
831 { .Name: 1069, .SubRegs: 3214, .SuperRegs: 2764, .SubRegIndices: 16, .RegUnits: 12689444, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
832 { .Name: 19, .SubRegs: 3242, .SuperRegs: 2755, .SubRegIndices: 16, .RegUnits: 12689448, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
833 { .Name: 296, .SubRegs: 3270, .SuperRegs: 2746, .SubRegIndices: 16, .RegUnits: 12689452, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
834 { .Name: 538, .SubRegs: 3298, .SuperRegs: 2737, .SubRegIndices: 16, .RegUnits: 12689456, .RegUnitLaneMasks: 6, .IsConstant: 0, .IsArtificial: 0 },
835 { .Name: 783, .SubRegs: 2195, .SuperRegs: 2728, .SubRegIndices: 2, .RegUnits: 11976756, .RegUnitLaneMasks: 10, .IsConstant: 0, .IsArtificial: 0 },
836 { .Name: 1003, .SubRegs: 2654, .SuperRegs: 2719, .SubRegIndices: 0, .RegUnits: 10874935, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
837 { .Name: 71, .SubRegs: 2657, .SuperRegs: 2710, .SubRegIndices: 0, .RegUnits: 10874937, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
838 { .Name: 351, .SubRegs: 2660, .SuperRegs: 2701, .SubRegIndices: 0, .RegUnits: 10874939, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
839 { .Name: 590, .SubRegs: 2663, .SuperRegs: 2692, .SubRegIndices: 0, .RegUnits: 10874941, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
840 { .Name: 819, .SubRegs: 2666, .SuperRegs: 2683, .SubRegIndices: 0, .RegUnits: 10874943, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
841 { .Name: 1039, .SubRegs: 2669, .SuperRegs: 919, .SubRegIndices: 0, .RegUnits: 10874945, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
842 { .Name: 107, .SubRegs: 2672, .SuperRegs: 940, .SubRegIndices: 0, .RegUnits: 10874947, .RegUnitLaneMasks: 13, .IsConstant: 0, .IsArtificial: 0 },
843 { .Name: 611, .SubRegs: 815, .SuperRegs: 960, .SubRegIndices: 131, .RegUnits: 12673048, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
844 { .Name: 843, .SubRegs: 795, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673052, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
845 { .Name: 1063, .SubRegs: 775, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673056, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
846 { .Name: 13, .SubRegs: 755, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673060, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
847 { .Name: 289, .SubRegs: 735, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673064, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
848 { .Name: 530, .SubRegs: 715, .SuperRegs: 2680, .SubRegIndices: 131, .RegUnits: 12673068, .RegUnitLaneMasks: 42, .IsConstant: 0, .IsArtificial: 0 },
849 { .Name: 775, .SubRegs: 697, .SuperRegs: 2680, .SubRegIndices: 114, .RegUnits: 12677168, .RegUnitLaneMasks: 50, .IsConstant: 0, .IsArtificial: 0 },
850 { .Name: 995, .SubRegs: 683, .SuperRegs: 2680, .SubRegIndices: 101, .RegUnits: 12685364, .RegUnitLaneMasks: 63, .IsConstant: 0, .IsArtificial: 0 },
851 { .Name: 63, .SubRegs: 60, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689463, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
852 { .Name: 343, .SubRegs: 48, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689465, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
853 { .Name: 582, .SubRegs: 36, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689467, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
854 { .Name: 811, .SubRegs: 24, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689469, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
855 { .Name: 1031, .SubRegs: 12, .SuperRegs: 2680, .SubRegIndices: 90, .RegUnits: 12689471, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
856 { .Name: 99, .SubRegs: 0, .SuperRegs: 854, .SubRegIndices: 90, .RegUnits: 12689473, .RegUnitLaneMasks: 68, .IsConstant: 0, .IsArtificial: 0 },
857};
858
859extern const MCPhysReg ARMRegUnitRoots[][2] = {
860 { ARM::APSR },
861 { ARM::APSR_NZCV },
862 { ARM::CPSR },
863 { ARM::FPCXTNS },
864 { ARM::FPCXTS },
865 { ARM::FPEXC },
866 { ARM::FPINST },
867 { ARM::FPSCR },
868 { ARM::FPSCR, ARM::FPSCR_NZCV },
869 { ARM::FPSCR, ARM::FPSCR_RM },
870 { ARM::FPSCR_NZCV },
871 { ARM::FPSCR_NZCVQC },
872 { ARM::FPSCR_RM },
873 { ARM::FPSID },
874 { ARM::ITSTATE },
875 { ARM::LR },
876 { ARM::PC },
877 { ARM::RA_AUTH_CODE },
878 { ARM::SP },
879 { ARM::SPSR },
880 { ARM::VPR },
881 { ARM::ZR },
882 { ARM::S0 },
883 { ARM::S1 },
884 { ARM::S2 },
885 { ARM::S3 },
886 { ARM::S4 },
887 { ARM::S5 },
888 { ARM::S6 },
889 { ARM::S7 },
890 { ARM::S8 },
891 { ARM::S9 },
892 { ARM::S10 },
893 { ARM::S11 },
894 { ARM::S12 },
895 { ARM::S13 },
896 { ARM::S14 },
897 { ARM::S15 },
898 { ARM::S16 },
899 { ARM::S17 },
900 { ARM::S18 },
901 { ARM::S19 },
902 { ARM::S20 },
903 { ARM::S21 },
904 { ARM::S22 },
905 { ARM::S23 },
906 { ARM::S24 },
907 { ARM::S25 },
908 { ARM::S26 },
909 { ARM::S27 },
910 { ARM::S28 },
911 { ARM::S29 },
912 { ARM::S30 },
913 { ARM::S31 },
914 { ARM::D16 },
915 { ARM::D17 },
916 { ARM::D18 },
917 { ARM::D19 },
918 { ARM::D20 },
919 { ARM::D21 },
920 { ARM::D22 },
921 { ARM::D23 },
922 { ARM::D24 },
923 { ARM::D25 },
924 { ARM::D26 },
925 { ARM::D27 },
926 { ARM::D28 },
927 { ARM::D29 },
928 { ARM::D30 },
929 { ARM::D31 },
930 { ARM::FPINST2 },
931 { ARM::MVFR0 },
932 { ARM::MVFR1 },
933 { ARM::MVFR2 },
934 { ARM::P0 },
935 { ARM::R0 },
936 { ARM::R1 },
937 { ARM::R2 },
938 { ARM::R3 },
939 { ARM::R4 },
940 { ARM::R5 },
941 { ARM::R6 },
942 { ARM::R7 },
943 { ARM::R8 },
944 { ARM::R9 },
945 { ARM::R10 },
946 { ARM::R11 },
947 { ARM::R12 },
948};
949
950namespace {
951
952// Register classes...
953 // HPR Register Class...
954 const MCPhysReg HPR[] = {
955 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31,
956 };
957
958 // HPR Bit set.
959 const uint8_t HPRBits[] = {
960 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
961 };
962
963 // FPWithVPR Register Class...
964 const MCPhysReg FPWithVPR[] = {
965 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::VPR,
966 };
967
968 // FPWithVPR Bit set.
969 const uint8_t FPWithVPRBits[] = {
970 0x00, 0x00, 0xe8, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
971 };
972
973 // SPR Register Class...
974 const MCPhysReg SPR[] = {
975 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31,
976 };
977
978 // SPR Bit set.
979 const uint8_t SPRBits[] = {
980 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
981 };
982
983 // FPWithVPR_with_ssub_0 Register Class...
984 const MCPhysReg FPWithVPR_with_ssub_0[] = {
985 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15,
986 };
987
988 // FPWithVPR_with_ssub_0 Bit set.
989 const uint8_t FPWithVPR_with_ssub_0Bits[] = {
990 0x00, 0x00, 0xe0, 0xff, 0x1f,
991 };
992
993 // GPR Register Class...
994 const MCPhysReg GPR[] = {
995 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
996 };
997
998 // GPR Bit set.
999 const uint8_t GPRBits[] = {
1000 0x00, 0xc0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1001 };
1002
1003 // GPRwithAPSR Register Class...
1004 const MCPhysReg GPRwithAPSR[] = {
1005 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV,
1006 };
1007
1008 // GPRwithAPSR Bit set.
1009 const uint8_t GPRwithAPSRBits[] = {
1010 0x04, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1011 };
1012
1013 // GPRwithZR Register Class...
1014 const MCPhysReg GPRwithZR[] = {
1015 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::ZR,
1016 };
1017
1018 // GPRwithZR Bit set.
1019 const uint8_t GPRwithZRBits[] = {
1020 0x00, 0x40, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1021 };
1022
1023 // SPR_8 Register Class...
1024 const MCPhysReg SPR_8[] = {
1025 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1026 };
1027
1028 // SPR_8 Bit set.
1029 const uint8_t SPR_8Bits[] = {
1030 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1031 };
1032
1033 // GPRnopc Register Class...
1034 const MCPhysReg GPRnopc[] = {
1035 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
1036 };
1037
1038 // GPRnopc Bit set.
1039 const uint8_t GPRnopcBits[] = {
1040 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1041 };
1042
1043 // GPRnosp Register Class...
1044 const MCPhysReg GPRnosp[] = {
1045 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::PC,
1046 };
1047
1048 // GPRnosp Bit set.
1049 const uint8_t GPRnospBits[] = {
1050 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1051 };
1052
1053 // GPRwithAPSR_NZCVnosp Register Class...
1054 const MCPhysReg GPRwithAPSR_NZCVnosp[] = {
1055 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR_NZCV,
1056 };
1057
1058 // GPRwithAPSR_NZCVnosp Bit set.
1059 const uint8_t GPRwithAPSR_NZCVnospBits[] = {
1060 0x04, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1061 };
1062
1063 // GPRwithAPSRnosp Register Class...
1064 const MCPhysReg GPRwithAPSRnosp[] = {
1065 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR,
1066 };
1067
1068 // GPRwithAPSRnosp Bit set.
1069 const uint8_t GPRwithAPSRnospBits[] = {
1070 0x02, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1071 };
1072
1073 // GPRwithZRnosp Register Class...
1074 const MCPhysReg GPRwithZRnosp[] = {
1075 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::ZR,
1076 };
1077
1078 // GPRwithZRnosp Bit set.
1079 const uint8_t GPRwithZRnospBits[] = {
1080 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1081 };
1082
1083 // GPRnoip Register Class...
1084 const MCPhysReg GPRnoip[] = {
1085 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC,
1086 };
1087
1088 // GPRnoip Bit set.
1089 const uint8_t GPRnoipBits[] = {
1090 0x00, 0x80, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3f,
1091 };
1092
1093 // rGPR Register Class...
1094 const MCPhysReg rGPR[] = {
1095 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
1096 };
1097
1098 // rGPR Bit set.
1099 const uint8_t rGPRBits[] = {
1100 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1101 };
1102
1103 // GPRnoip_and_GPRnopc Register Class...
1104 const MCPhysReg GPRnoip_and_GPRnopc[] = {
1105 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP,
1106 };
1107
1108 // GPRnoip_and_GPRnopc Bit set.
1109 const uint8_t GPRnoip_and_GPRnopcBits[] = {
1110 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3f,
1111 };
1112
1113 // GPRnoip_and_GPRnosp Register Class...
1114 const MCPhysReg GPRnoip_and_GPRnosp[] = {
1115 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::PC,
1116 };
1117
1118 // GPRnoip_and_GPRnosp Bit set.
1119 const uint8_t GPRnoip_and_GPRnospBits[] = {
1120 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3f,
1121 };
1122
1123 // GPRnoip_and_GPRwithAPSR_NZCVnosp Register Class...
1124 const MCPhysReg GPRnoip_and_GPRwithAPSR_NZCVnosp[] = {
1125 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1126 };
1127
1128 // GPRnoip_and_GPRwithAPSR_NZCVnosp Bit set.
1129 const uint8_t GPRnoip_and_GPRwithAPSR_NZCVnospBits[] = {
1130 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3f,
1131 };
1132
1133 // tGPRwithpc Register Class...
1134 const MCPhysReg tGPRwithpc[] = {
1135 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC,
1136 };
1137
1138 // tGPRwithpc Bit set.
1139 const uint8_t tGPRwithpcBits[] = {
1140 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1141 };
1142
1143 // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Register Class...
1144 const MCPhysReg FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8[] = {
1145 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1146 };
1147
1148 // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Bit set.
1149 const uint8_t FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits[] = {
1150 0x00, 0x00, 0xe0, 0x1f,
1151 };
1152
1153 // hGPR Register Class...
1154 const MCPhysReg hGPR[] = {
1155 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
1156 };
1157
1158 // hGPR Bit set.
1159 const uint8_t hGPRBits[] = {
1160 0x00, 0xc0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1161 };
1162
1163 // tGPR Register Class...
1164 const MCPhysReg tGPR[] = {
1165 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1166 };
1167
1168 // tGPR Bit set.
1169 const uint8_t tGPRBits[] = {
1170 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1171 };
1172
1173 // tGPREven Register Class...
1174 const MCPhysReg tGPREven[] = {
1175 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, ARM::R12, ARM::LR,
1176 };
1177
1178 // tGPREven Bit set.
1179 const uint8_t tGPREvenBits[] = {
1180 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55,
1181 };
1182
1183 // GPRnopc_and_hGPR Register Class...
1184 const MCPhysReg GPRnopc_and_hGPR[] = {
1185 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
1186 };
1187
1188 // GPRnopc_and_hGPR Bit set.
1189 const uint8_t GPRnopc_and_hGPRBits[] = {
1190 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1191 };
1192
1193 // GPRnosp_and_hGPR Register Class...
1194 const MCPhysReg GPRnosp_and_hGPR[] = {
1195 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::PC,
1196 };
1197
1198 // GPRnosp_and_hGPR Bit set.
1199 const uint8_t GPRnosp_and_hGPRBits[] = {
1200 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1201 };
1202
1203 // GPRnoip_and_hGPR Register Class...
1204 const MCPhysReg GPRnoip_and_hGPR[] = {
1205 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC,
1206 };
1207
1208 // GPRnoip_and_hGPR Bit set.
1209 const uint8_t GPRnoip_and_hGPRBits[] = {
1210 0x00, 0x80, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1211 };
1212
1213 // GPRnoip_and_tGPREven Register Class...
1214 const MCPhysReg GPRnoip_and_tGPREven[] = {
1215 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
1216 };
1217
1218 // GPRnoip_and_tGPREven Bit set.
1219 const uint8_t GPRnoip_and_tGPREvenBits[] = {
1220 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x15,
1221 };
1222
1223 // GPRnosp_and_GPRnopc_and_hGPR Register Class...
1224 const MCPhysReg GPRnosp_and_GPRnopc_and_hGPR[] = {
1225 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
1226 };
1227
1228 // GPRnosp_and_GPRnopc_and_hGPR Bit set.
1229 const uint8_t GPRnosp_and_GPRnopc_and_hGPRBits[] = {
1230 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1231 };
1232
1233 // tGPROdd Register Class...
1234 const MCPhysReg tGPROdd[] = {
1235 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
1236 };
1237
1238 // tGPROdd Bit set.
1239 const uint8_t tGPROddBits[] = {
1240 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x2a,
1241 };
1242
1243 // GPRnopc_and_GPRnoip_and_hGPR Register Class...
1244 const MCPhysReg GPRnopc_and_GPRnoip_and_hGPR[] = {
1245 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP,
1246 };
1247
1248 // GPRnopc_and_GPRnoip_and_hGPR Bit set.
1249 const uint8_t GPRnopc_and_GPRnoip_and_hGPRBits[] = {
1250 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1251 };
1252
1253 // GPRnosp_and_GPRnoip_and_hGPR Register Class...
1254 const MCPhysReg GPRnosp_and_GPRnoip_and_hGPR[] = {
1255 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::PC,
1256 };
1257
1258 // GPRnosp_and_GPRnoip_and_hGPR Bit set.
1259 const uint8_t GPRnosp_and_GPRnoip_and_hGPRBits[] = {
1260 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1261 };
1262
1263 // tcGPR Register Class...
1264 const MCPhysReg tcGPR[] = {
1265 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12,
1266 };
1267
1268 // tcGPR Bit set.
1269 const uint8_t tcGPRBits[] = {
1270 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40,
1271 };
1272
1273 // GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR Register Class...
1274 const MCPhysReg GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR[] = {
1275 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1276 };
1277
1278 // GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR Bit set.
1279 const uint8_t GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits[] = {
1280 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1281 };
1282
1283 // hGPR_and_tGPREven Register Class...
1284 const MCPhysReg hGPR_and_tGPREven[] = {
1285 ARM::R8, ARM::R10, ARM::R12, ARM::LR,
1286 };
1287
1288 // hGPR_and_tGPREven Bit set.
1289 const uint8_t hGPR_and_tGPREvenBits[] = {
1290 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54,
1291 };
1292
1293 // tGPR_and_tGPREven Register Class...
1294 const MCPhysReg tGPR_and_tGPREven[] = {
1295 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
1296 };
1297
1298 // tGPR_and_tGPREven Bit set.
1299 const uint8_t tGPR_and_tGPREvenBits[] = {
1300 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x01,
1301 };
1302
1303 // tGPR_and_tGPROdd Register Class...
1304 const MCPhysReg tGPR_and_tGPROdd[] = {
1305 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
1306 };
1307
1308 // tGPR_and_tGPROdd Bit set.
1309 const uint8_t tGPR_and_tGPROddBits[] = {
1310 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x02,
1311 };
1312
1313 // tcGPRnotr12 Register Class...
1314 const MCPhysReg tcGPRnotr12[] = {
1315 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1316 };
1317
1318 // tcGPRnotr12 Bit set.
1319 const uint8_t tcGPRnotr12Bits[] = {
1320 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1321 };
1322
1323 // tGPREven_and_tcGPR Register Class...
1324 const MCPhysReg tGPREven_and_tcGPR[] = {
1325 ARM::R0, ARM::R2, ARM::R12,
1326 };
1327
1328 // tGPREven_and_tcGPR Bit set.
1329 const uint8_t tGPREven_and_tcGPRBits[] = {
1330 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x40,
1331 };
1332
1333 // FP_STATUS_REGS Register Class...
1334 const MCPhysReg FP_STATUS_REGS[] = {
1335 ARM::FPSCR, ARM::FPEXC,
1336 };
1337
1338 // FP_STATUS_REGS Bit set.
1339 const uint8_t FP_STATUS_REGSBits[] = {
1340 0x40, 0x01,
1341 };
1342
1343 // hGPR_and_GPRnoip_and_tGPREven Register Class...
1344 const MCPhysReg hGPR_and_GPRnoip_and_tGPREven[] = {
1345 ARM::R8, ARM::R10,
1346 };
1347
1348 // hGPR_and_GPRnoip_and_tGPREven Bit set.
1349 const uint8_t hGPR_and_GPRnoip_and_tGPREvenBits[] = {
1350 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14,
1351 };
1352
1353 // hGPR_and_tGPROdd Register Class...
1354 const MCPhysReg hGPR_and_tGPROdd[] = {
1355 ARM::R9, ARM::R11,
1356 };
1357
1358 // hGPR_and_tGPROdd Bit set.
1359 const uint8_t hGPR_and_tGPROddBits[] = {
1360 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28,
1361 };
1362
1363 // tGPREven_and_tcGPRnotr12 Register Class...
1364 const MCPhysReg tGPREven_and_tcGPRnotr12[] = {
1365 ARM::R0, ARM::R2,
1366 };
1367
1368 // tGPREven_and_tcGPRnotr12 Bit set.
1369 const uint8_t tGPREven_and_tcGPRnotr12Bits[] = {
1370 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14,
1371 };
1372
1373 // tGPROdd_and_tcGPR Register Class...
1374 const MCPhysReg tGPROdd_and_tcGPR[] = {
1375 ARM::R1, ARM::R3,
1376 };
1377
1378 // tGPROdd_and_tcGPR Bit set.
1379 const uint8_t tGPROdd_and_tcGPRBits[] = {
1380 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28,
1381 };
1382
1383 // CCR Register Class...
1384 const MCPhysReg CCR[] = {
1385 ARM::CPSR,
1386 };
1387
1388 // CCR Bit set.
1389 const uint8_t CCRBits[] = {
1390 0x08,
1391 };
1392
1393 // FPCXTRegs Register Class...
1394 const MCPhysReg FPCXTRegs[] = {
1395 ARM::FPCXTNS,
1396 };
1397
1398 // FPCXTRegs Bit set.
1399 const uint8_t FPCXTRegsBits[] = {
1400 0x10,
1401 };
1402
1403 // GPRlr Register Class...
1404 const MCPhysReg GPRlr[] = {
1405 ARM::LR,
1406 };
1407
1408 // GPRlr Bit set.
1409 const uint8_t GPRlrBits[] = {
1410 0x00, 0x40,
1411 };
1412
1413 // GPRsp Register Class...
1414 const MCPhysReg GPRsp[] = {
1415 ARM::SP,
1416 };
1417
1418 // GPRsp Bit set.
1419 const uint8_t GPRspBits[] = {
1420 0x00, 0x00, 0x02,
1421 };
1422
1423 // VCCR Register Class...
1424 const MCPhysReg VCCR[] = {
1425 ARM::VPR,
1426 };
1427
1428 // VCCR Bit set.
1429 const uint8_t VCCRBits[] = {
1430 0x00, 0x00, 0x08,
1431 };
1432
1433 // cl_FPSCR_NZCV Register Class...
1434 const MCPhysReg cl_FPSCR_NZCV[] = {
1435 ARM::FPSCR_NZCV,
1436 };
1437
1438 // cl_FPSCR_NZCV Bit set.
1439 const uint8_t cl_FPSCR_NZCVBits[] = {
1440 0x00, 0x02,
1441 };
1442
1443 // hGPR_and_tGPRwithpc Register Class...
1444 const MCPhysReg hGPR_and_tGPRwithpc[] = {
1445 ARM::PC,
1446 };
1447
1448 // hGPR_and_tGPRwithpc Bit set.
1449 const uint8_t hGPR_and_tGPRwithpcBits[] = {
1450 0x00, 0x80,
1451 };
1452
1453 // hGPR_and_tcGPR Register Class...
1454 const MCPhysReg hGPR_and_tcGPR[] = {
1455 ARM::R12,
1456 };
1457
1458 // hGPR_and_tcGPR Bit set.
1459 const uint8_t hGPR_and_tcGPRBits[] = {
1460 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
1461 };
1462
1463 // DPR Register Class...
1464 const MCPhysReg DPR[] = {
1465 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31,
1466 };
1467
1468 // DPR Bit set.
1469 const uint8_t DPRBits[] = {
1470 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
1471 };
1472
1473 // DPR_VFP2 Register Class...
1474 const MCPhysReg DPR_VFP2[] = {
1475 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1476 };
1477
1478 // DPR_VFP2 Bit set.
1479 const uint8_t DPR_VFP2Bits[] = {
1480 0x00, 0x00, 0xe0, 0xff, 0x1f,
1481 };
1482
1483 // DPR_8 Register Class...
1484 const MCPhysReg DPR_8[] = {
1485 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1486 };
1487
1488 // DPR_8 Bit set.
1489 const uint8_t DPR_8Bits[] = {
1490 0x00, 0x00, 0xe0, 0x1f,
1491 };
1492
1493 // GPRPair Register Class...
1494 const MCPhysReg GPRPair[] = {
1495 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, ARM::R12_SP,
1496 };
1497
1498 // GPRPair Bit set.
1499 const uint8_t GPRPairBits[] = {
1500 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1501 };
1502
1503 // GPRPairnosp Register Class...
1504 const MCPhysReg GPRPairnosp[] = {
1505 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11,
1506 };
1507
1508 // GPRPairnosp Bit set.
1509 const uint8_t GPRPairnospBits[] = {
1510 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e,
1511 };
1512
1513 // GPRPair_with_gsub_0_in_tGPR Register Class...
1514 const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
1515 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1516 };
1517
1518 // GPRPair_with_gsub_0_in_tGPR Bit set.
1519 const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
1520 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
1521 };
1522
1523 // GPRPair_with_gsub_0_in_hGPR Register Class...
1524 const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
1525 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP,
1526 };
1527
1528 // GPRPair_with_gsub_0_in_hGPR Bit set.
1529 const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
1530 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
1531 };
1532
1533 // GPRPair_with_gsub_0_in_tcGPR Register Class...
1534 const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
1535 ARM::R0_R1, ARM::R2_R3, ARM::R12_SP,
1536 };
1537
1538 // GPRPair_with_gsub_0_in_tcGPR Bit set.
1539 const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
1540 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86,
1541 };
1542
1543 // GPRPair_with_gsub_0_in_tcGPRnotr12 Register Class...
1544 const MCPhysReg GPRPair_with_gsub_0_in_tcGPRnotr12[] = {
1545 ARM::R0_R1, ARM::R2_R3,
1546 };
1547
1548 // GPRPair_with_gsub_0_in_tcGPRnotr12 Bit set.
1549 const uint8_t GPRPair_with_gsub_0_in_tcGPRnotr12Bits[] = {
1550 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,
1551 };
1552
1553 // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Register Class...
1554 const MCPhysReg GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR[] = {
1555 ARM::R8_R9, ARM::R10_R11,
1556 };
1557
1558 // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Bit set.
1559 const uint8_t GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits[] = {
1560 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
1561 };
1562
1563 // GPRPair_with_gsub_1_in_GPRsp Register Class...
1564 const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
1565 ARM::R12_SP,
1566 };
1567
1568 // GPRPair_with_gsub_1_in_GPRsp Bit set.
1569 const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
1570 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
1571 };
1572
1573 // DPairSpc Register Class...
1574 const MCPhysReg DPairSpc[] = {
1575 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D28_D30, ARM::D29_D31,
1576 };
1577
1578 // DPairSpc Bit set.
1579 const uint8_t DPairSpcBits[] = {
1580 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f,
1581 };
1582
1583 // DPairSpc_with_ssub_0 Register Class...
1584 const MCPhysReg DPairSpc_with_ssub_0[] = {
1585 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1586 };
1587
1588 // DPairSpc_with_ssub_0 Bit set.
1589 const uint8_t DPairSpc_with_ssub_0Bits[] = {
1590 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1591 };
1592
1593 // DPairSpc_with_ssub_4 Register Class...
1594 const MCPhysReg DPairSpc_with_ssub_4[] = {
1595 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15,
1596 };
1597
1598 // DPairSpc_with_ssub_4 Bit set.
1599 const uint8_t DPairSpc_with_ssub_4Bits[] = {
1600 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f,
1601 };
1602
1603 // DPairSpc_with_dsub_0_in_DPR_8 Register Class...
1604 const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
1605 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1606 };
1607
1608 // DPairSpc_with_dsub_0_in_DPR_8 Bit set.
1609 const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
1610 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1611 };
1612
1613 // DPairSpc_with_dsub_2_in_DPR_8 Register Class...
1614 const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
1615 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7,
1616 };
1617
1618 // DPairSpc_with_dsub_2_in_DPR_8 Bit set.
1619 const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
1620 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f,
1621 };
1622
1623 // DPair Register Class...
1624 const MCPhysReg DPair[] = {
1625 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q15,
1626 };
1627
1628 // DPair Bit set.
1629 const uint8_t DPairBits[] = {
1630 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
1631 };
1632
1633 // DPair_with_ssub_0 Register Class...
1634 const MCPhysReg DPair_with_ssub_0[] = {
1635 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16,
1636 };
1637
1638 // DPair_with_ssub_0 Bit set.
1639 const uint8_t DPair_with_ssub_0Bits[] = {
1640 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
1641 };
1642
1643 // QPR Register Class...
1644 const MCPhysReg QPR[] = {
1645 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15,
1646 };
1647
1648 // QPR Bit set.
1649 const uint8_t QPRBits[] = {
1650 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
1651 };
1652
1653 // DPair_with_ssub_2 Register Class...
1654 const MCPhysReg DPair_with_ssub_2[] = {
1655 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7,
1656 };
1657
1658 // DPair_with_ssub_2 Bit set.
1659 const uint8_t DPair_with_ssub_2Bits[] = {
1660 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
1661 };
1662
1663 // DPair_with_dsub_0_in_DPR_8 Register Class...
1664 const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
1665 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8,
1666 };
1667
1668 // DPair_with_dsub_0_in_DPR_8 Bit set.
1669 const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
1670 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
1671 };
1672
1673 // MQPR Register Class...
1674 const MCPhysReg MQPR[] = {
1675 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1676 };
1677
1678 // MQPR Bit set.
1679 const uint8_t MQPRBits[] = {
1680 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1681 };
1682
1683 // QPR_VFP2 Register Class...
1684 const MCPhysReg QPR_VFP2[] = {
1685 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1686 };
1687
1688 // QPR_VFP2 Bit set.
1689 const uint8_t QPR_VFP2Bits[] = {
1690 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1691 };
1692
1693 // DPair_with_dsub_1_in_DPR_8 Register Class...
1694 const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
1695 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3,
1696 };
1697
1698 // DPair_with_dsub_1_in_DPR_8 Bit set.
1699 const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
1700 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
1701 };
1702
1703 // QPR_8 Register Class...
1704 const MCPhysReg QPR_8[] = {
1705 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1706 };
1707
1708 // QPR_8 Bit set.
1709 const uint8_t QPR_8Bits[] = {
1710 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1711 };
1712
1713 // DTriple Register Class...
1714 const MCPhysReg DTriple[] = {
1715 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, ARM::D16_D17_D18, ARM::D17_D18_D19, ARM::D18_D19_D20, ARM::D19_D20_D21, ARM::D20_D21_D22, ARM::D21_D22_D23, ARM::D22_D23_D24, ARM::D23_D24_D25, ARM::D24_D25_D26, ARM::D25_D26_D27, ARM::D26_D27_D28, ARM::D27_D28_D29, ARM::D28_D29_D30, ARM::D29_D30_D31,
1716 };
1717
1718 // DTriple Bit set.
1719 const uint8_t DTripleBits[] = {
1720 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f,
1721 };
1722
1723 // DTripleSpc Register Class...
1724 const MCPhysReg DTripleSpc[] = {
1725 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31,
1726 };
1727
1728 // DTripleSpc Bit set.
1729 const uint8_t DTripleSpcBits[] = {
1730 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
1731 };
1732
1733 // DTripleSpc_with_ssub_0 Register Class...
1734 const MCPhysReg DTripleSpc_with_ssub_0[] = {
1735 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19,
1736 };
1737
1738 // DTripleSpc_with_ssub_0 Bit set.
1739 const uint8_t DTripleSpc_with_ssub_0Bits[] = {
1740 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1741 };
1742
1743 // DTriple_with_ssub_0 Register Class...
1744 const MCPhysReg DTriple_with_ssub_0[] = {
1745 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17,
1746 };
1747
1748 // DTriple_with_ssub_0 Bit set.
1749 const uint8_t DTriple_with_ssub_0Bits[] = {
1750 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
1751 };
1752
1753 // DTriple_with_qsub_0_in_QPR Register Class...
1754 const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
1755 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, ARM::D16_D17_D18, ARM::D18_D19_D20, ARM::D20_D21_D22, ARM::D22_D23_D24, ARM::D24_D25_D26, ARM::D26_D27_D28, ARM::D28_D29_D30,
1756 };
1757
1758 // DTriple_with_qsub_0_in_QPR Bit set.
1759 const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
1760 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15,
1761 };
1762
1763 // DTriple_with_ssub_2 Register Class...
1764 const MCPhysReg DTriple_with_ssub_2[] = {
1765 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16,
1766 };
1767
1768 // DTriple_with_ssub_2 Bit set.
1769 const uint8_t DTriple_with_ssub_2Bits[] = {
1770 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f,
1771 };
1772
1773 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1774 const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1775 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, ARM::D17_D18_D19, ARM::D19_D20_D21, ARM::D21_D22_D23, ARM::D23_D24_D25, ARM::D25_D26_D27, ARM::D27_D28_D29, ARM::D29_D30_D31,
1776 };
1777
1778 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1779 const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1780 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a,
1781 };
1782
1783 // DTripleSpc_with_ssub_4 Register Class...
1784 const MCPhysReg DTripleSpc_with_ssub_4[] = {
1785 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17,
1786 };
1787
1788 // DTripleSpc_with_ssub_4 Bit set.
1789 const uint8_t DTripleSpc_with_ssub_4Bits[] = {
1790 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
1791 };
1792
1793 // DTriple_with_ssub_4 Register Class...
1794 const MCPhysReg DTriple_with_ssub_4[] = {
1795 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15,
1796 };
1797
1798 // DTriple_with_ssub_4 Bit set.
1799 const uint8_t DTriple_with_ssub_4Bits[] = {
1800 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f,
1801 };
1802
1803 // DTripleSpc_with_ssub_8 Register Class...
1804 const MCPhysReg DTripleSpc_with_ssub_8[] = {
1805 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15,
1806 };
1807
1808 // DTripleSpc_with_ssub_8 Bit set.
1809 const uint8_t DTripleSpc_with_ssub_8Bits[] = {
1810 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
1811 };
1812
1813 // DTripleSpc_with_dsub_0_in_DPR_8 Register Class...
1814 const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
1815 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11,
1816 };
1817
1818 // DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
1819 const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
1820 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
1821 };
1822
1823 // DTriple_with_dsub_0_in_DPR_8 Register Class...
1824 const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
1825 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9,
1826 };
1827
1828 // DTriple_with_dsub_0_in_DPR_8 Bit set.
1829 const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
1830 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1831 };
1832
1833 // DTriple_with_qsub_0_in_MQPR Register Class...
1834 const MCPhysReg DTriple_with_qsub_0_in_MQPR[] = {
1835 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16,
1836 };
1837
1838 // DTriple_with_qsub_0_in_MQPR Bit set.
1839 const uint8_t DTriple_with_qsub_0_in_MQPRBits[] = {
1840 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
1841 };
1842
1843 // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1844 const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1845 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17,
1846 };
1847
1848 // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1849 const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1850 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa,
1851 };
1852
1853 // DTriple_with_dsub_1_in_DPR_8 Register Class...
1854 const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
1855 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8,
1856 };
1857
1858 // DTriple_with_dsub_1_in_DPR_8 Bit set.
1859 const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
1860 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1861 };
1862
1863 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
1864 const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
1865 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15,
1866 };
1867
1868 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
1869 const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
1870 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a,
1871 };
1872
1873 // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Register Class...
1874 const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR[] = {
1875 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14,
1876 };
1877
1878 // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Bit set.
1879 const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits[] = {
1880 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15,
1881 };
1882
1883 // DTripleSpc_with_dsub_2_in_DPR_8 Register Class...
1884 const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
1885 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9,
1886 };
1887
1888 // DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
1889 const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
1890 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1891 };
1892
1893 // DTriple_with_dsub_2_in_DPR_8 Register Class...
1894 const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
1895 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7,
1896 };
1897
1898 // DTriple_with_dsub_2_in_DPR_8 Bit set.
1899 const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
1900 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
1901 };
1902
1903 // DTripleSpc_with_dsub_4_in_DPR_8 Register Class...
1904 const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
1905 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7,
1906 };
1907
1908 // DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
1909 const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
1910 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
1911 };
1912
1913 // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
1914 const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
1915 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9,
1916 };
1917
1918 // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
1919 const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
1920 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa,
1921 };
1922
1923 // DTriple_with_qsub_0_in_QPR_8 Register Class...
1924 const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
1925 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8,
1926 };
1927
1928 // DTriple_with_qsub_0_in_QPR_8 Bit set.
1929 const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
1930 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55,
1931 };
1932
1933 // DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8 Register Class...
1934 const MCPhysReg DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8[] = {
1935 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6,
1936 };
1937
1938 // DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8 Bit set.
1939 const uint8_t DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8Bits[] = {
1940 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15,
1941 };
1942
1943 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
1944 const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
1945 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7,
1946 };
1947
1948 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
1949 const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
1950 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a,
1951 };
1952
1953 // DQuadSpc Register Class...
1954 const MCPhysReg DQuadSpc[] = {
1955 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31,
1956 };
1957
1958 // DQuadSpc Bit set.
1959 const uint8_t DQuadSpcBits[] = {
1960 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
1961 };
1962
1963 // DQuadSpc_with_ssub_0 Register Class...
1964 const MCPhysReg DQuadSpc_with_ssub_0[] = {
1965 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19,
1966 };
1967
1968 // DQuadSpc_with_ssub_0 Bit set.
1969 const uint8_t DQuadSpc_with_ssub_0Bits[] = {
1970 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1971 };
1972
1973 // DQuadSpc_with_ssub_4 Register Class...
1974 const MCPhysReg DQuadSpc_with_ssub_4[] = {
1975 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17,
1976 };
1977
1978 // DQuadSpc_with_ssub_4 Bit set.
1979 const uint8_t DQuadSpc_with_ssub_4Bits[] = {
1980 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
1981 };
1982
1983 // DQuadSpc_with_ssub_8 Register Class...
1984 const MCPhysReg DQuadSpc_with_ssub_8[] = {
1985 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15,
1986 };
1987
1988 // DQuadSpc_with_ssub_8 Bit set.
1989 const uint8_t DQuadSpc_with_ssub_8Bits[] = {
1990 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
1991 };
1992
1993 // DQuadSpc_with_dsub_0_in_DPR_8 Register Class...
1994 const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
1995 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11,
1996 };
1997
1998 // DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
1999 const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
2000 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
2001 };
2002
2003 // DQuadSpc_with_dsub_2_in_DPR_8 Register Class...
2004 const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
2005 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9,
2006 };
2007
2008 // DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
2009 const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
2010 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
2011 };
2012
2013 // DQuadSpc_with_dsub_4_in_DPR_8 Register Class...
2014 const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
2015 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7,
2016 };
2017
2018 // DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
2019 const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
2020 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
2021 };
2022
2023 // DQuad Register Class...
2024 const MCPhysReg DQuad[] = {
2025 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, ARM::Q8_Q9, ARM::D17_D18_D19_D20, ARM::Q9_Q10, ARM::D19_D20_D21_D22, ARM::Q10_Q11, ARM::D21_D22_D23_D24, ARM::Q11_Q12, ARM::D23_D24_D25_D26, ARM::Q12_Q13, ARM::D25_D26_D27_D28, ARM::Q13_Q14, ARM::D27_D28_D29_D30, ARM::Q14_Q15,
2026 };
2027
2028 // DQuad Bit set.
2029 const uint8_t DQuadBits[] = {
2030 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
2031 };
2032
2033 // DQuad_with_ssub_0 Register Class...
2034 const MCPhysReg DQuad_with_ssub_0[] = {
2035 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18,
2036 };
2037
2038 // DQuad_with_ssub_0 Bit set.
2039 const uint8_t DQuad_with_ssub_0Bits[] = {
2040 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2041 };
2042
2043 // DQuad_with_ssub_2 Register Class...
2044 const MCPhysReg DQuad_with_ssub_2[] = {
2045 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8,
2046 };
2047
2048 // DQuad_with_ssub_2 Bit set.
2049 const uint8_t DQuad_with_ssub_2Bits[] = {
2050 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
2051 };
2052
2053 // QQPR Register Class...
2054 const MCPhysReg QQPR[] = {
2055 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15,
2056 };
2057
2058 // QQPR Bit set.
2059 const uint8_t QQPRBits[] = {
2060 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2061 };
2062
2063 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2064 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2065 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, ARM::D17_D18_D19_D20, ARM::D19_D20_D21_D22, ARM::D21_D22_D23_D24, ARM::D23_D24_D25_D26, ARM::D25_D26_D27_D28, ARM::D27_D28_D29_D30,
2066 };
2067
2068 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2069 const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2070 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
2071 };
2072
2073 // DQuad_with_ssub_4 Register Class...
2074 const MCPhysReg DQuad_with_ssub_4[] = {
2075 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16,
2076 };
2077
2078 // DQuad_with_ssub_4 Bit set.
2079 const uint8_t DQuad_with_ssub_4Bits[] = {
2080 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
2081 };
2082
2083 // DQuad_with_ssub_6 Register Class...
2084 const MCPhysReg DQuad_with_ssub_6[] = {
2085 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7,
2086 };
2087
2088 // DQuad_with_ssub_6 Bit set.
2089 const uint8_t DQuad_with_ssub_6Bits[] = {
2090 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
2091 };
2092
2093 // DQuad_with_dsub_0_in_DPR_8 Register Class...
2094 const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
2095 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10,
2096 };
2097
2098 // DQuad_with_dsub_0_in_DPR_8 Bit set.
2099 const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
2100 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
2101 };
2102
2103 // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2104 const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2105 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18,
2106 };
2107
2108 // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2109 const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2110 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2111 };
2112
2113 // QQPR_with_ssub_0 Register Class...
2114 const MCPhysReg QQPR_with_ssub_0[] = {
2115 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8,
2116 };
2117
2118 // QQPR_with_ssub_0 Bit set.
2119 const uint8_t QQPR_with_ssub_0Bits[] = {
2120 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
2121 };
2122
2123 // DQuad_with_dsub_1_in_DPR_8 Register Class...
2124 const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
2125 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4,
2126 };
2127
2128 // DQuad_with_dsub_1_in_DPR_8 Bit set.
2129 const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
2130 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
2131 };
2132
2133 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
2134 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
2135 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16,
2136 };
2137
2138 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
2139 const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
2140 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
2141 };
2142
2143 // MQQPR Register Class...
2144 const MCPhysReg MQQPR[] = {
2145 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7,
2146 };
2147
2148 // MQQPR Bit set.
2149 const uint8_t MQQPRBits[] = {
2150 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
2151 };
2152
2153 // DQuad_with_dsub_2_in_DPR_8 Register Class...
2154 const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
2155 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8,
2156 };
2157
2158 // DQuad_with_dsub_2_in_DPR_8 Bit set.
2159 const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
2160 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
2161 };
2162
2163 // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
2164 const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
2165 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14,
2166 };
2167
2168 // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
2169 const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
2170 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
2171 };
2172
2173 // DQuad_with_dsub_3_in_DPR_8 Register Class...
2174 const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
2175 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3,
2176 };
2177
2178 // DQuad_with_dsub_3_in_DPR_8 Bit set.
2179 const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
2180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2181 };
2182
2183 // DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
2184 const MCPhysReg DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
2185 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10,
2186 };
2187
2188 // DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
2189 const uint8_t DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
2190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
2191 };
2192
2193 // MQQPR_with_qsub_0_in_QPR_8 Register Class...
2194 const MCPhysReg MQQPR_with_qsub_0_in_QPR_8[] = {
2195 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
2196 };
2197
2198 // MQQPR_with_qsub_0_in_QPR_8 Bit set.
2199 const uint8_t MQQPR_with_qsub_0_in_QPR_8Bits[] = {
2200 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
2201 };
2202
2203 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
2204 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
2205 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8,
2206 };
2207
2208 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
2209 const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
2210 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
2211 };
2212
2213 // MQQPR_with_dsub_2_in_DPR_8 Register Class...
2214 const MCPhysReg MQQPR_with_dsub_2_in_DPR_8[] = {
2215 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3,
2216 };
2217
2218 // MQQPR_with_dsub_2_in_DPR_8 Bit set.
2219 const uint8_t MQQPR_with_dsub_2_in_DPR_8Bits[] = {
2220 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
2221 };
2222
2223 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8 Register Class...
2224 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8[] = {
2225 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6,
2226 };
2227
2228 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8 Bit set.
2229 const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8Bits[] = {
2230 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2231 };
2232
2233 // QQQQPR Register Class...
2234 const MCPhysReg QQQQPR[] = {
2235 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15,
2236 };
2237
2238 // QQQQPR Bit set.
2239 const uint8_t QQQQPRBits[] = {
2240 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
2241 };
2242
2243 // QQQQPR_with_ssub_0 Register Class...
2244 const MCPhysReg QQQQPR_with_ssub_0[] = {
2245 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10,
2246 };
2247
2248 // QQQQPR_with_ssub_0 Bit set.
2249 const uint8_t QQQQPR_with_ssub_0Bits[] = {
2250 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
2251 };
2252
2253 // QQQQPR_with_ssub_4 Register Class...
2254 const MCPhysReg QQQQPR_with_ssub_4[] = {
2255 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9,
2256 };
2257
2258 // QQQQPR_with_ssub_4 Bit set.
2259 const uint8_t QQQQPR_with_ssub_4Bits[] = {
2260 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
2261 };
2262
2263 // QQQQPR_with_ssub_8 Register Class...
2264 const MCPhysReg QQQQPR_with_ssub_8[] = {
2265 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8,
2266 };
2267
2268 // QQQQPR_with_ssub_8 Bit set.
2269 const uint8_t QQQQPR_with_ssub_8Bits[] = {
2270 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03,
2271 };
2272
2273 // MQQQQPR Register Class...
2274 const MCPhysReg MQQQQPR[] = {
2275 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7,
2276 };
2277
2278 // MQQQQPR Bit set.
2279 const uint8_t MQQQQPRBits[] = {
2280 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01,
2281 };
2282
2283 // MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8 Register Class...
2284 const MCPhysReg MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8[] = {
2285 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6,
2286 };
2287
2288 // MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8 Bit set.
2289 const uint8_t MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8Bits[] = {
2290 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
2291 };
2292
2293 // MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8 Register Class...
2294 const MCPhysReg MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8[] = {
2295 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
2296 };
2297
2298 // MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8 Bit set.
2299 const uint8_t MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8Bits[] = {
2300 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
2301 };
2302
2303 // MQQQQPR_with_qsub_2_in_QPR_8 Register Class...
2304 const MCPhysReg MQQQQPR_with_qsub_2_in_QPR_8[] = {
2305 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4,
2306 };
2307
2308 // MQQQQPR_with_qsub_2_in_QPR_8 Bit set.
2309 const uint8_t MQQQQPR_with_qsub_2_in_QPR_8Bits[] = {
2310 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
2311 };
2312
2313 // MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8 Register Class...
2314 const MCPhysReg MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8[] = {
2315 ARM::Q0_Q1_Q2_Q3,
2316 };
2317
2318 // MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8 Bit set.
2319 const uint8_t MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8Bits[] = {
2320 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2321 };
2322
2323} // namespace
2324
2325#ifdef __GNUC__
2326#pragma GCC diagnostic push
2327#pragma GCC diagnostic ignored "-Woverlength-strings"
2328#endif
2329extern const char ARMRegClassStrings[] = {
2330 /* 0 */ "QQQQPR_with_ssub_0\000"
2331 /* 19 */ "FPWithVPR_with_ssub_0\000"
2332 /* 41 */ "DQuadSpc_with_ssub_0\000"
2333 /* 62 */ "DTripleSpc_with_ssub_0\000"
2334 /* 85 */ "DPairSpc_with_ssub_0\000"
2335 /* 106 */ "DQuad_with_ssub_0\000"
2336 /* 124 */ "DTriple_with_ssub_0\000"
2337 /* 144 */ "DPair_with_ssub_0\000"
2338 /* 162 */ "tGPREven_and_tcGPRnotr12\000"
2339 /* 187 */ "GPRPair_with_gsub_0_in_tcGPRnotr12\000"
2340 /* 222 */ "DPR_VFP2\000"
2341 /* 231 */ "QPR_VFP2\000"
2342 /* 240 */ "DQuad_with_ssub_2\000"
2343 /* 258 */ "DTriple_with_ssub_2\000"
2344 /* 278 */ "DPair_with_ssub_2\000"
2345 /* 296 */ "QQQQPR_with_ssub_4\000"
2346 /* 315 */ "DQuadSpc_with_ssub_4\000"
2347 /* 336 */ "DTripleSpc_with_ssub_4\000"
2348 /* 359 */ "DPairSpc_with_ssub_4\000"
2349 /* 380 */ "DQuad_with_ssub_4\000"
2350 /* 398 */ "DTriple_with_ssub_4\000"
2351 /* 418 */ "DQuad_with_ssub_6\000"
2352 /* 436 */ "DQuadSpc_with_dsub_0_in_DPR_8\000"
2353 /* 466 */ "DTripleSpc_with_dsub_0_in_DPR_8\000"
2354 /* 498 */ "DPairSpc_with_dsub_0_in_DPR_8\000"
2355 /* 528 */ "DQuad_with_dsub_0_in_DPR_8\000"
2356 /* 555 */ "DTriple_with_dsub_0_in_DPR_8\000"
2357 /* 584 */ "DPair_with_dsub_0_in_DPR_8\000"
2358 /* 611 */ "DQuad_with_dsub_1_in_DPR_8\000"
2359 /* 638 */ "DTriple_with_dsub_1_in_DPR_8\000"
2360 /* 667 */ "DPair_with_dsub_1_in_DPR_8\000"
2361 /* 694 */ "MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8\000"
2362 /* 745 */ "MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8\000"
2363 /* 796 */ "DQuadSpc_with_dsub_2_in_DPR_8\000"
2364 /* 826 */ "DTripleSpc_with_dsub_2_in_DPR_8\000"
2365 /* 858 */ "DPairSpc_with_dsub_2_in_DPR_8\000"
2366 /* 888 */ "DQuad_with_dsub_2_in_DPR_8\000"
2367 /* 915 */ "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8\000"
2368 /* 1032 */ "DQuad_with_dsub_3_in_DPR_8\000"
2369 /* 1059 */ "DQuadSpc_with_dsub_4_in_DPR_8\000"
2370 /* 1089 */ "DTripleSpc_with_dsub_4_in_DPR_8\000"
2371 /* 1121 */ "MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8\000"
2372 /* 1172 */ "DTriple_with_qsub_0_in_QPR_8\000"
2373 /* 1201 */ "MQQQQPR_with_qsub_2_in_QPR_8\000"
2374 /* 1230 */ "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8\000"
2375 /* 1278 */ "DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8\000"
2376 /* 1328 */ "FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8\000"
2377 /* 1371 */ "QQQQPR_with_ssub_8\000"
2378 /* 1390 */ "DQuadSpc_with_ssub_8\000"
2379 /* 1411 */ "DTripleSpc_with_ssub_8\000"
2380 /* 1434 */ "VCCR\000"
2381 /* 1439 */ "DPR\000"
2382 /* 1443 */ "hGPR_and_tcGPR\000"
2383 /* 1458 */ "tGPROdd_and_tcGPR\000"
2384 /* 1476 */ "tGPREven_and_tcGPR\000"
2385 /* 1495 */ "GPRPair_with_gsub_0_in_tcGPR\000"
2386 /* 1524 */ "GPRnosp_and_GPRnopc_and_hGPR\000"
2387 /* 1553 */ "GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR\000"
2388 /* 1594 */ "GPRnosp_and_GPRnoip_and_hGPR\000"
2389 /* 1623 */ "GPRnosp_and_hGPR\000"
2390 /* 1640 */ "GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR\000"
2391 /* 1684 */ "rGPR\000"
2392 /* 1689 */ "GPRPair_with_gsub_0_in_tGPR\000"
2393 /* 1717 */ "HPR\000"
2394 /* 1721 */ "DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR\000"
2395 /* 1773 */ "DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR\000"
2396 /* 1842 */ "DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR\000"
2397 /* 1980 */ "MQQPR\000"
2398 /* 1986 */ "MQQQQPR\000"
2399 /* 1994 */ "DTriple_with_qsub_0_in_QPR\000"
2400 /* 2021 */ "DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR\000"
2401 /* 2089 */ "DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR\000"
2402 /* 2161 */ "SPR\000"
2403 /* 2165 */ "FPWithVPR\000"
2404 /* 2175 */ "GPRwithAPSR\000"
2405 /* 2187 */ "GPRwithZR\000"
2406 /* 2197 */ "FP_STATUS_REGS\000"
2407 /* 2212 */ "cl_FPSCR_NZCV\000"
2408 /* 2226 */ "DQuadSpc\000"
2409 /* 2235 */ "DTripleSpc\000"
2410 /* 2246 */ "DPairSpc\000"
2411 /* 2255 */ "hGPR_and_tGPRwithpc\000"
2412 /* 2275 */ "GPRnoip_and_GPRnopc\000"
2413 /* 2295 */ "DQuad\000"
2414 /* 2301 */ "hGPR_and_tGPROdd\000"
2415 /* 2318 */ "tGPR_and_tGPROdd\000"
2416 /* 2335 */ "DTriple\000"
2417 /* 2343 */ "hGPR_and_tGPREven\000"
2418 /* 2361 */ "tGPR_and_tGPREven\000"
2419 /* 2379 */ "hGPR_and_GPRnoip_and_tGPREven\000"
2420 /* 2409 */ "GPRnoip\000"
2421 /* 2417 */ "GPRPair_with_gsub_1_in_GPRsp\000"
2422 /* 2446 */ "GPRnoip_and_GPRnosp\000"
2423 /* 2466 */ "GPRwithAPSRnosp\000"
2424 /* 2482 */ "GPRwithZRnosp\000"
2425 /* 2496 */ "GPRnoip_and_GPRwithAPSR_NZCVnosp\000"
2426 /* 2529 */ "GPRPairnosp\000"
2427 /* 2541 */ "DPair\000"
2428 /* 2547 */ "GPRPair\000"
2429 /* 2555 */ "GPRlr\000"
2430 /* 2561 */ "FPCXTRegs\000"
2431};
2432#ifdef __GNUC__
2433#pragma GCC diagnostic pop
2434#endif
2435
2436extern const MCRegisterClass ARMMCRegisterClasses[] = {
2437 { .RegsBegin: HPR, .RegSet: HPRBits, .NameIdx: 1717, .RegsSize: 32, .RegSetSize: sizeof(HPRBits), .ID: ARM::HPRRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2438 { .RegsBegin: FPWithVPR, .RegSet: FPWithVPRBits, .NameIdx: 2165, .RegsSize: 65, .RegSetSize: sizeof(FPWithVPRBits), .ID: ARM::FPWithVPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2439 { .RegsBegin: SPR, .RegSet: SPRBits, .NameIdx: 2161, .RegsSize: 32, .RegSetSize: sizeof(SPRBits), .ID: ARM::SPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2440 { .RegsBegin: FPWithVPR_with_ssub_0, .RegSet: FPWithVPR_with_ssub_0Bits, .NameIdx: 19, .RegsSize: 16, .RegSetSize: sizeof(FPWithVPR_with_ssub_0Bits), .ID: ARM::FPWithVPR_with_ssub_0RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2441 { .RegsBegin: GPR, .RegSet: GPRBits, .NameIdx: 1454, .RegsSize: 16, .RegSetSize: sizeof(GPRBits), .ID: ARM::GPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2442 { .RegsBegin: GPRwithAPSR, .RegSet: GPRwithAPSRBits, .NameIdx: 2175, .RegsSize: 16, .RegSetSize: sizeof(GPRwithAPSRBits), .ID: ARM::GPRwithAPSRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2443 { .RegsBegin: GPRwithZR, .RegSet: GPRwithZRBits, .NameIdx: 2187, .RegsSize: 16, .RegSetSize: sizeof(GPRwithZRBits), .ID: ARM::GPRwithZRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2444 { .RegsBegin: SPR_8, .RegSet: SPR_8Bits, .NameIdx: 1365, .RegsSize: 16, .RegSetSize: sizeof(SPR_8Bits), .ID: ARM::SPR_8RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2445 { .RegsBegin: GPRnopc, .RegSet: GPRnopcBits, .NameIdx: 2287, .RegsSize: 15, .RegSetSize: sizeof(GPRnopcBits), .ID: ARM::GPRnopcRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2446 { .RegsBegin: GPRnosp, .RegSet: GPRnospBits, .NameIdx: 2458, .RegsSize: 15, .RegSetSize: sizeof(GPRnospBits), .ID: ARM::GPRnospRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2447 { .RegsBegin: GPRwithAPSR_NZCVnosp, .RegSet: GPRwithAPSR_NZCVnospBits, .NameIdx: 2508, .RegsSize: 15, .RegSetSize: sizeof(GPRwithAPSR_NZCVnospBits), .ID: ARM::GPRwithAPSR_NZCVnospRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2448 { .RegsBegin: GPRwithAPSRnosp, .RegSet: GPRwithAPSRnospBits, .NameIdx: 2466, .RegsSize: 15, .RegSetSize: sizeof(GPRwithAPSRnospBits), .ID: ARM::GPRwithAPSRnospRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2449 { .RegsBegin: GPRwithZRnosp, .RegSet: GPRwithZRnospBits, .NameIdx: 2482, .RegsSize: 15, .RegSetSize: sizeof(GPRwithZRnospBits), .ID: ARM::GPRwithZRnospRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2450 { .RegsBegin: GPRnoip, .RegSet: GPRnoipBits, .NameIdx: 2409, .RegsSize: 14, .RegSetSize: sizeof(GPRnoipBits), .ID: ARM::GPRnoipRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2451 { .RegsBegin: rGPR, .RegSet: rGPRBits, .NameIdx: 1684, .RegsSize: 14, .RegSetSize: sizeof(rGPRBits), .ID: ARM::rGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2452 { .RegsBegin: GPRnoip_and_GPRnopc, .RegSet: GPRnoip_and_GPRnopcBits, .NameIdx: 2275, .RegsSize: 13, .RegSetSize: sizeof(GPRnoip_and_GPRnopcBits), .ID: ARM::GPRnoip_and_GPRnopcRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2453 { .RegsBegin: GPRnoip_and_GPRnosp, .RegSet: GPRnoip_and_GPRnospBits, .NameIdx: 2446, .RegsSize: 13, .RegSetSize: sizeof(GPRnoip_and_GPRnospBits), .ID: ARM::GPRnoip_and_GPRnospRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2454 { .RegsBegin: GPRnoip_and_GPRwithAPSR_NZCVnosp, .RegSet: GPRnoip_and_GPRwithAPSR_NZCVnospBits, .NameIdx: 2496, .RegsSize: 12, .RegSetSize: sizeof(GPRnoip_and_GPRwithAPSR_NZCVnospBits), .ID: ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2455 { .RegsBegin: tGPRwithpc, .RegSet: tGPRwithpcBits, .NameIdx: 2264, .RegsSize: 9, .RegSetSize: sizeof(tGPRwithpcBits), .ID: ARM::tGPRwithpcRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2456 { .RegsBegin: FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8, .RegSet: FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits, .NameIdx: 1328, .RegsSize: 8, .RegSetSize: sizeof(FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits), .ID: ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2457 { .RegsBegin: hGPR, .RegSet: hGPRBits, .NameIdx: 1548, .RegsSize: 8, .RegSetSize: sizeof(hGPRBits), .ID: ARM::hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2458 { .RegsBegin: tGPR, .RegSet: tGPRBits, .NameIdx: 1712, .RegsSize: 8, .RegSetSize: sizeof(tGPRBits), .ID: ARM::tGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2459 { .RegsBegin: tGPREven, .RegSet: tGPREvenBits, .NameIdx: 2352, .RegsSize: 8, .RegSetSize: sizeof(tGPREvenBits), .ID: ARM::tGPREvenRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2460 { .RegsBegin: GPRnopc_and_hGPR, .RegSet: GPRnopc_and_hGPRBits, .NameIdx: 1536, .RegsSize: 7, .RegSetSize: sizeof(GPRnopc_and_hGPRBits), .ID: ARM::GPRnopc_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2461 { .RegsBegin: GPRnosp_and_hGPR, .RegSet: GPRnosp_and_hGPRBits, .NameIdx: 1623, .RegsSize: 7, .RegSetSize: sizeof(GPRnosp_and_hGPRBits), .ID: ARM::GPRnosp_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2462 { .RegsBegin: GPRnoip_and_hGPR, .RegSet: GPRnoip_and_hGPRBits, .NameIdx: 1577, .RegsSize: 6, .RegSetSize: sizeof(GPRnoip_and_hGPRBits), .ID: ARM::GPRnoip_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2463 { .RegsBegin: GPRnoip_and_tGPREven, .RegSet: GPRnoip_and_tGPREvenBits, .NameIdx: 2388, .RegsSize: 6, .RegSetSize: sizeof(GPRnoip_and_tGPREvenBits), .ID: ARM::GPRnoip_and_tGPREvenRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2464 { .RegsBegin: GPRnosp_and_GPRnopc_and_hGPR, .RegSet: GPRnosp_and_GPRnopc_and_hGPRBits, .NameIdx: 1524, .RegsSize: 6, .RegSetSize: sizeof(GPRnosp_and_GPRnopc_and_hGPRBits), .ID: ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2465 { .RegsBegin: tGPROdd, .RegSet: tGPROddBits, .NameIdx: 2310, .RegsSize: 6, .RegSetSize: sizeof(tGPROddBits), .ID: ARM::tGPROddRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2466 { .RegsBegin: GPRnopc_and_GPRnoip_and_hGPR, .RegSet: GPRnopc_and_GPRnoip_and_hGPRBits, .NameIdx: 1565, .RegsSize: 5, .RegSetSize: sizeof(GPRnopc_and_GPRnoip_and_hGPRBits), .ID: ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2467 { .RegsBegin: GPRnosp_and_GPRnoip_and_hGPR, .RegSet: GPRnosp_and_GPRnoip_and_hGPRBits, .NameIdx: 1594, .RegsSize: 5, .RegSetSize: sizeof(GPRnosp_and_GPRnoip_and_hGPRBits), .ID: ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2468 { .RegsBegin: tcGPR, .RegSet: tcGPRBits, .NameIdx: 1452, .RegsSize: 5, .RegSetSize: sizeof(tcGPRBits), .ID: ARM::tcGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2469 { .RegsBegin: GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR, .RegSet: GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits, .NameIdx: 1553, .RegsSize: 4, .RegSetSize: sizeof(GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits), .ID: ARM::GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2470 { .RegsBegin: hGPR_and_tGPREven, .RegSet: hGPR_and_tGPREvenBits, .NameIdx: 2343, .RegsSize: 4, .RegSetSize: sizeof(hGPR_and_tGPREvenBits), .ID: ARM::hGPR_and_tGPREvenRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2471 { .RegsBegin: tGPR_and_tGPREven, .RegSet: tGPR_and_tGPREvenBits, .NameIdx: 2361, .RegsSize: 4, .RegSetSize: sizeof(tGPR_and_tGPREvenBits), .ID: ARM::tGPR_and_tGPREvenRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2472 { .RegsBegin: tGPR_and_tGPROdd, .RegSet: tGPR_and_tGPROddBits, .NameIdx: 2318, .RegsSize: 4, .RegSetSize: sizeof(tGPR_and_tGPROddBits), .ID: ARM::tGPR_and_tGPROddRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2473 { .RegsBegin: tcGPRnotr12, .RegSet: tcGPRnotr12Bits, .NameIdx: 175, .RegsSize: 4, .RegSetSize: sizeof(tcGPRnotr12Bits), .ID: ARM::tcGPRnotr12RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2474 { .RegsBegin: tGPREven_and_tcGPR, .RegSet: tGPREven_and_tcGPRBits, .NameIdx: 1476, .RegsSize: 3, .RegSetSize: sizeof(tGPREven_and_tcGPRBits), .ID: ARM::tGPREven_and_tcGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2475 { .RegsBegin: FP_STATUS_REGS, .RegSet: FP_STATUS_REGSBits, .NameIdx: 2197, .RegsSize: 2, .RegSetSize: sizeof(FP_STATUS_REGSBits), .ID: ARM::FP_STATUS_REGSRegClassID, .RegSizeInBits: 32, .CopyCost: 255, .Allocatable: false, .BaseClass: false },
2476 { .RegsBegin: hGPR_and_GPRnoip_and_tGPREven, .RegSet: hGPR_and_GPRnoip_and_tGPREvenBits, .NameIdx: 2379, .RegsSize: 2, .RegSetSize: sizeof(hGPR_and_GPRnoip_and_tGPREvenBits), .ID: ARM::hGPR_and_GPRnoip_and_tGPREvenRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2477 { .RegsBegin: hGPR_and_tGPROdd, .RegSet: hGPR_and_tGPROddBits, .NameIdx: 2301, .RegsSize: 2, .RegSetSize: sizeof(hGPR_and_tGPROddBits), .ID: ARM::hGPR_and_tGPROddRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2478 { .RegsBegin: tGPREven_and_tcGPRnotr12, .RegSet: tGPREven_and_tcGPRnotr12Bits, .NameIdx: 162, .RegsSize: 2, .RegSetSize: sizeof(tGPREven_and_tcGPRnotr12Bits), .ID: ARM::tGPREven_and_tcGPRnotr12RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2479 { .RegsBegin: tGPROdd_and_tcGPR, .RegSet: tGPROdd_and_tcGPRBits, .NameIdx: 1458, .RegsSize: 2, .RegSetSize: sizeof(tGPROdd_and_tcGPRBits), .ID: ARM::tGPROdd_and_tcGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2480 { .RegsBegin: CCR, .RegSet: CCRBits, .NameIdx: 1435, .RegsSize: 1, .RegSetSize: sizeof(CCRBits), .ID: ARM::CCRRegClassID, .RegSizeInBits: 32, .CopyCost: 255, .Allocatable: false, .BaseClass: false },
2481 { .RegsBegin: FPCXTRegs, .RegSet: FPCXTRegsBits, .NameIdx: 2561, .RegsSize: 1, .RegSetSize: sizeof(FPCXTRegsBits), .ID: ARM::FPCXTRegsRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2482 { .RegsBegin: GPRlr, .RegSet: GPRlrBits, .NameIdx: 2555, .RegsSize: 1, .RegSetSize: sizeof(GPRlrBits), .ID: ARM::GPRlrRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2483 { .RegsBegin: GPRsp, .RegSet: GPRspBits, .NameIdx: 2440, .RegsSize: 1, .RegSetSize: sizeof(GPRspBits), .ID: ARM::GPRspRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2484 { .RegsBegin: VCCR, .RegSet: VCCRBits, .NameIdx: 1434, .RegsSize: 1, .RegSetSize: sizeof(VCCRBits), .ID: ARM::VCCRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2485 { .RegsBegin: cl_FPSCR_NZCV, .RegSet: cl_FPSCR_NZCVBits, .NameIdx: 2212, .RegsSize: 1, .RegSetSize: sizeof(cl_FPSCR_NZCVBits), .ID: ARM::cl_FPSCR_NZCVRegClassID, .RegSizeInBits: 32, .CopyCost: 255, .Allocatable: true, .BaseClass: false },
2486 { .RegsBegin: hGPR_and_tGPRwithpc, .RegSet: hGPR_and_tGPRwithpcBits, .NameIdx: 2255, .RegsSize: 1, .RegSetSize: sizeof(hGPR_and_tGPRwithpcBits), .ID: ARM::hGPR_and_tGPRwithpcRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2487 { .RegsBegin: hGPR_and_tcGPR, .RegSet: hGPR_and_tcGPRBits, .NameIdx: 1443, .RegsSize: 1, .RegSetSize: sizeof(hGPR_and_tcGPRBits), .ID: ARM::hGPR_and_tcGPRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2488 { .RegsBegin: DPR, .RegSet: DPRBits, .NameIdx: 1439, .RegsSize: 32, .RegSetSize: sizeof(DPRBits), .ID: ARM::DPRRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2489 { .RegsBegin: DPR_VFP2, .RegSet: DPR_VFP2Bits, .NameIdx: 222, .RegsSize: 16, .RegSetSize: sizeof(DPR_VFP2Bits), .ID: ARM::DPR_VFP2RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2490 { .RegsBegin: DPR_8, .RegSet: DPR_8Bits, .NameIdx: 460, .RegsSize: 8, .RegSetSize: sizeof(DPR_8Bits), .ID: ARM::DPR_8RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2491 { .RegsBegin: GPRPair, .RegSet: GPRPairBits, .NameIdx: 2547, .RegsSize: 7, .RegSetSize: sizeof(GPRPairBits), .ID: ARM::GPRPairRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2492 { .RegsBegin: GPRPairnosp, .RegSet: GPRPairnospBits, .NameIdx: 2529, .RegsSize: 6, .RegSetSize: sizeof(GPRPairnospBits), .ID: ARM::GPRPairnospRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2493 { .RegsBegin: GPRPair_with_gsub_0_in_tGPR, .RegSet: GPRPair_with_gsub_0_in_tGPRBits, .NameIdx: 1689, .RegsSize: 4, .RegSetSize: sizeof(GPRPair_with_gsub_0_in_tGPRBits), .ID: ARM::GPRPair_with_gsub_0_in_tGPRRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2494 { .RegsBegin: GPRPair_with_gsub_0_in_hGPR, .RegSet: GPRPair_with_gsub_0_in_hGPRBits, .NameIdx: 1656, .RegsSize: 3, .RegSetSize: sizeof(GPRPair_with_gsub_0_in_hGPRBits), .ID: ARM::GPRPair_with_gsub_0_in_hGPRRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2495 { .RegsBegin: GPRPair_with_gsub_0_in_tcGPR, .RegSet: GPRPair_with_gsub_0_in_tcGPRBits, .NameIdx: 1495, .RegsSize: 3, .RegSetSize: sizeof(GPRPair_with_gsub_0_in_tcGPRBits), .ID: ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2496 { .RegsBegin: GPRPair_with_gsub_0_in_tcGPRnotr12, .RegSet: GPRPair_with_gsub_0_in_tcGPRnotr12Bits, .NameIdx: 187, .RegsSize: 2, .RegSetSize: sizeof(GPRPair_with_gsub_0_in_tcGPRnotr12Bits), .ID: ARM::GPRPair_with_gsub_0_in_tcGPRnotr12RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2497 { .RegsBegin: GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR, .RegSet: GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits, .NameIdx: 1640, .RegsSize: 2, .RegSetSize: sizeof(GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits), .ID: ARM::GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2498 { .RegsBegin: GPRPair_with_gsub_1_in_GPRsp, .RegSet: GPRPair_with_gsub_1_in_GPRspBits, .NameIdx: 2417, .RegsSize: 1, .RegSetSize: sizeof(GPRPair_with_gsub_1_in_GPRspBits), .ID: ARM::GPRPair_with_gsub_1_in_GPRspRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2499 { .RegsBegin: DPairSpc, .RegSet: DPairSpcBits, .NameIdx: 2246, .RegsSize: 30, .RegSetSize: sizeof(DPairSpcBits), .ID: ARM::DPairSpcRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2500 { .RegsBegin: DPairSpc_with_ssub_0, .RegSet: DPairSpc_with_ssub_0Bits, .NameIdx: 85, .RegsSize: 16, .RegSetSize: sizeof(DPairSpc_with_ssub_0Bits), .ID: ARM::DPairSpc_with_ssub_0RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2501 { .RegsBegin: DPairSpc_with_ssub_4, .RegSet: DPairSpc_with_ssub_4Bits, .NameIdx: 359, .RegsSize: 14, .RegSetSize: sizeof(DPairSpc_with_ssub_4Bits), .ID: ARM::DPairSpc_with_ssub_4RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2502 { .RegsBegin: DPairSpc_with_dsub_0_in_DPR_8, .RegSet: DPairSpc_with_dsub_0_in_DPR_8Bits, .NameIdx: 498, .RegsSize: 8, .RegSetSize: sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), .ID: ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2503 { .RegsBegin: DPairSpc_with_dsub_2_in_DPR_8, .RegSet: DPairSpc_with_dsub_2_in_DPR_8Bits, .NameIdx: 858, .RegsSize: 6, .RegSetSize: sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), .ID: ARM::DPairSpc_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2504 { .RegsBegin: DPair, .RegSet: DPairBits, .NameIdx: 2541, .RegsSize: 31, .RegSetSize: sizeof(DPairBits), .ID: ARM::DPairRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2505 { .RegsBegin: DPair_with_ssub_0, .RegSet: DPair_with_ssub_0Bits, .NameIdx: 144, .RegsSize: 16, .RegSetSize: sizeof(DPair_with_ssub_0Bits), .ID: ARM::DPair_with_ssub_0RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2506 { .RegsBegin: QPR, .RegSet: QPRBits, .NameIdx: 1769, .RegsSize: 16, .RegSetSize: sizeof(QPRBits), .ID: ARM::QPRRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2507 { .RegsBegin: DPair_with_ssub_2, .RegSet: DPair_with_ssub_2Bits, .NameIdx: 278, .RegsSize: 15, .RegSetSize: sizeof(DPair_with_ssub_2Bits), .ID: ARM::DPair_with_ssub_2RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2508 { .RegsBegin: DPair_with_dsub_0_in_DPR_8, .RegSet: DPair_with_dsub_0_in_DPR_8Bits, .NameIdx: 584, .RegsSize: 8, .RegSetSize: sizeof(DPair_with_dsub_0_in_DPR_8Bits), .ID: ARM::DPair_with_dsub_0_in_DPR_8RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2509 { .RegsBegin: MQPR, .RegSet: MQPRBits, .NameIdx: 1768, .RegsSize: 8, .RegSetSize: sizeof(MQPRBits), .ID: ARM::MQPRRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2510 { .RegsBegin: QPR_VFP2, .RegSet: QPR_VFP2Bits, .NameIdx: 231, .RegsSize: 8, .RegSetSize: sizeof(QPR_VFP2Bits), .ID: ARM::QPR_VFP2RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2511 { .RegsBegin: DPair_with_dsub_1_in_DPR_8, .RegSet: DPair_with_dsub_1_in_DPR_8Bits, .NameIdx: 667, .RegsSize: 7, .RegSetSize: sizeof(DPair_with_dsub_1_in_DPR_8Bits), .ID: ARM::DPair_with_dsub_1_in_DPR_8RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2512 { .RegsBegin: QPR_8, .RegSet: QPR_8Bits, .NameIdx: 1166, .RegsSize: 4, .RegSetSize: sizeof(QPR_8Bits), .ID: ARM::QPR_8RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2513 { .RegsBegin: DTriple, .RegSet: DTripleBits, .NameIdx: 2335, .RegsSize: 30, .RegSetSize: sizeof(DTripleBits), .ID: ARM::DTripleRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2514 { .RegsBegin: DTripleSpc, .RegSet: DTripleSpcBits, .NameIdx: 2235, .RegsSize: 28, .RegSetSize: sizeof(DTripleSpcBits), .ID: ARM::DTripleSpcRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2515 { .RegsBegin: DTripleSpc_with_ssub_0, .RegSet: DTripleSpc_with_ssub_0Bits, .NameIdx: 62, .RegsSize: 16, .RegSetSize: sizeof(DTripleSpc_with_ssub_0Bits), .ID: ARM::DTripleSpc_with_ssub_0RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2516 { .RegsBegin: DTriple_with_ssub_0, .RegSet: DTriple_with_ssub_0Bits, .NameIdx: 124, .RegsSize: 16, .RegSetSize: sizeof(DTriple_with_ssub_0Bits), .ID: ARM::DTriple_with_ssub_0RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2517 { .RegsBegin: DTriple_with_qsub_0_in_QPR, .RegSet: DTriple_with_qsub_0_in_QPRBits, .NameIdx: 1994, .RegsSize: 15, .RegSetSize: sizeof(DTriple_with_qsub_0_in_QPRBits), .ID: ARM::DTriple_with_qsub_0_in_QPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2518 { .RegsBegin: DTriple_with_ssub_2, .RegSet: DTriple_with_ssub_2Bits, .NameIdx: 258, .RegsSize: 15, .RegSetSize: sizeof(DTriple_with_ssub_2Bits), .ID: ARM::DTriple_with_ssub_2RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2519 { .RegsBegin: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, .RegSet: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, .NameIdx: 2113, .RegsSize: 15, .RegSetSize: sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), .ID: ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2520 { .RegsBegin: DTripleSpc_with_ssub_4, .RegSet: DTripleSpc_with_ssub_4Bits, .NameIdx: 336, .RegsSize: 14, .RegSetSize: sizeof(DTripleSpc_with_ssub_4Bits), .ID: ARM::DTripleSpc_with_ssub_4RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2521 { .RegsBegin: DTriple_with_ssub_4, .RegSet: DTriple_with_ssub_4Bits, .NameIdx: 398, .RegsSize: 14, .RegSetSize: sizeof(DTriple_with_ssub_4Bits), .ID: ARM::DTriple_with_ssub_4RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2522 { .RegsBegin: DTripleSpc_with_ssub_8, .RegSet: DTripleSpc_with_ssub_8Bits, .NameIdx: 1411, .RegsSize: 12, .RegSetSize: sizeof(DTripleSpc_with_ssub_8Bits), .ID: ARM::DTripleSpc_with_ssub_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2523 { .RegsBegin: DTripleSpc_with_dsub_0_in_DPR_8, .RegSet: DTripleSpc_with_dsub_0_in_DPR_8Bits, .NameIdx: 466, .RegsSize: 8, .RegSetSize: sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), .ID: ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2524 { .RegsBegin: DTriple_with_dsub_0_in_DPR_8, .RegSet: DTriple_with_dsub_0_in_DPR_8Bits, .NameIdx: 555, .RegsSize: 8, .RegSetSize: sizeof(DTriple_with_dsub_0_in_DPR_8Bits), .ID: ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2525 { .RegsBegin: DTriple_with_qsub_0_in_MQPR, .RegSet: DTriple_with_qsub_0_in_MQPRBits, .NameIdx: 1745, .RegsSize: 8, .RegSetSize: sizeof(DTriple_with_qsub_0_in_MQPRBits), .ID: ARM::DTriple_with_qsub_0_in_MQPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2526 { .RegsBegin: DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, .RegSet: DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, .NameIdx: 2089, .RegsSize: 8, .RegSetSize: sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), .ID: ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2527 { .RegsBegin: DTriple_with_dsub_1_in_DPR_8, .RegSet: DTriple_with_dsub_1_in_DPR_8Bits, .NameIdx: 638, .RegsSize: 7, .RegSetSize: sizeof(DTriple_with_dsub_1_in_DPR_8Bits), .ID: ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2528 { .RegsBegin: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, .RegSet: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, .NameIdx: 1931, .RegsSize: 7, .RegSetSize: sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), .ID: ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2529 { .RegsBegin: DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR, .RegSet: DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits, .NameIdx: 1721, .RegsSize: 7, .RegSetSize: sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits), .ID: ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2530 { .RegsBegin: DTripleSpc_with_dsub_2_in_DPR_8, .RegSet: DTripleSpc_with_dsub_2_in_DPR_8Bits, .NameIdx: 826, .RegsSize: 6, .RegSetSize: sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), .ID: ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2531 { .RegsBegin: DTriple_with_dsub_2_in_DPR_8, .RegSet: DTriple_with_dsub_2_in_DPR_8Bits, .NameIdx: 1003, .RegsSize: 6, .RegSetSize: sizeof(DTriple_with_dsub_2_in_DPR_8Bits), .ID: ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2532 { .RegsBegin: DTripleSpc_with_dsub_4_in_DPR_8, .RegSet: DTripleSpc_with_dsub_4_in_DPR_8Bits, .NameIdx: 1089, .RegsSize: 4, .RegSetSize: sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), .ID: ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2533 { .RegsBegin: DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, .RegSet: DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, .NameIdx: 1898, .RegsSize: 4, .RegSetSize: sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), .ID: ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2534 { .RegsBegin: DTriple_with_qsub_0_in_QPR_8, .RegSet: DTriple_with_qsub_0_in_QPR_8Bits, .NameIdx: 1172, .RegsSize: 4, .RegSetSize: sizeof(DTriple_with_qsub_0_in_QPR_8Bits), .ID: ARM::DTriple_with_qsub_0_in_QPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2535 { .RegsBegin: DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8, .RegSet: DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8Bits, .NameIdx: 971, .RegsSize: 3, .RegSetSize: sizeof(DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8Bits), .ID: ARM::DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2536 { .RegsBegin: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, .RegSet: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, .NameIdx: 1278, .RegsSize: 3, .RegSetSize: sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), .ID: ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2537 { .RegsBegin: DQuadSpc, .RegSet: DQuadSpcBits, .NameIdx: 2226, .RegsSize: 28, .RegSetSize: sizeof(DQuadSpcBits), .ID: ARM::DQuadSpcRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2538 { .RegsBegin: DQuadSpc_with_ssub_0, .RegSet: DQuadSpc_with_ssub_0Bits, .NameIdx: 41, .RegsSize: 16, .RegSetSize: sizeof(DQuadSpc_with_ssub_0Bits), .ID: ARM::DQuadSpc_with_ssub_0RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2539 { .RegsBegin: DQuadSpc_with_ssub_4, .RegSet: DQuadSpc_with_ssub_4Bits, .NameIdx: 315, .RegsSize: 14, .RegSetSize: sizeof(DQuadSpc_with_ssub_4Bits), .ID: ARM::DQuadSpc_with_ssub_4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2540 { .RegsBegin: DQuadSpc_with_ssub_8, .RegSet: DQuadSpc_with_ssub_8Bits, .NameIdx: 1390, .RegsSize: 12, .RegSetSize: sizeof(DQuadSpc_with_ssub_8Bits), .ID: ARM::DQuadSpc_with_ssub_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2541 { .RegsBegin: DQuadSpc_with_dsub_0_in_DPR_8, .RegSet: DQuadSpc_with_dsub_0_in_DPR_8Bits, .NameIdx: 436, .RegsSize: 8, .RegSetSize: sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), .ID: ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2542 { .RegsBegin: DQuadSpc_with_dsub_2_in_DPR_8, .RegSet: DQuadSpc_with_dsub_2_in_DPR_8Bits, .NameIdx: 796, .RegsSize: 6, .RegSetSize: sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), .ID: ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2543 { .RegsBegin: DQuadSpc_with_dsub_4_in_DPR_8, .RegSet: DQuadSpc_with_dsub_4_in_DPR_8Bits, .NameIdx: 1059, .RegsSize: 4, .RegSetSize: sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), .ID: ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2544 { .RegsBegin: DQuad, .RegSet: DQuadBits, .NameIdx: 2295, .RegsSize: 29, .RegSetSize: sizeof(DQuadBits), .ID: ARM::DQuadRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2545 { .RegsBegin: DQuad_with_ssub_0, .RegSet: DQuad_with_ssub_0Bits, .NameIdx: 106, .RegsSize: 16, .RegSetSize: sizeof(DQuad_with_ssub_0Bits), .ID: ARM::DQuad_with_ssub_0RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2546 { .RegsBegin: DQuad_with_ssub_2, .RegSet: DQuad_with_ssub_2Bits, .NameIdx: 240, .RegsSize: 15, .RegSetSize: sizeof(DQuad_with_ssub_2Bits), .ID: ARM::DQuad_with_ssub_2RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2547 { .RegsBegin: QQPR, .RegSet: QQPRBits, .NameIdx: 1981, .RegsSize: 15, .RegSetSize: sizeof(QQPRBits), .ID: ARM::QQPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2548 { .RegsBegin: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, .RegSet: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, .NameIdx: 2043, .RegsSize: 14, .RegSetSize: sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2549 { .RegsBegin: DQuad_with_ssub_4, .RegSet: DQuad_with_ssub_4Bits, .NameIdx: 380, .RegsSize: 14, .RegSetSize: sizeof(DQuad_with_ssub_4Bits), .ID: ARM::DQuad_with_ssub_4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2550 { .RegsBegin: DQuad_with_ssub_6, .RegSet: DQuad_with_ssub_6Bits, .NameIdx: 418, .RegsSize: 13, .RegSetSize: sizeof(DQuad_with_ssub_6Bits), .ID: ARM::DQuad_with_ssub_6RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2551 { .RegsBegin: DQuad_with_dsub_0_in_DPR_8, .RegSet: DQuad_with_dsub_0_in_DPR_8Bits, .NameIdx: 528, .RegsSize: 8, .RegSetSize: sizeof(DQuad_with_dsub_0_in_DPR_8Bits), .ID: ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2552 { .RegsBegin: DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, .RegSet: DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, .NameIdx: 2021, .RegsSize: 8, .RegSetSize: sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), .ID: ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2553 { .RegsBegin: QQPR_with_ssub_0, .RegSet: QQPR_with_ssub_0Bits, .NameIdx: 2, .RegsSize: 8, .RegSetSize: sizeof(QQPR_with_ssub_0Bits), .ID: ARM::QQPR_with_ssub_0RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2554 { .RegsBegin: DQuad_with_dsub_1_in_DPR_8, .RegSet: DQuad_with_dsub_1_in_DPR_8Bits, .NameIdx: 611, .RegsSize: 7, .RegSetSize: sizeof(DQuad_with_dsub_1_in_DPR_8Bits), .ID: ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2555 { .RegsBegin: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, .RegSet: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, .NameIdx: 1795, .RegsSize: 7, .RegSetSize: sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2556 { .RegsBegin: MQQPR, .RegSet: MQQPRBits, .NameIdx: 1980, .RegsSize: 7, .RegSetSize: sizeof(MQQPRBits), .ID: ARM::MQQPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2557 { .RegsBegin: DQuad_with_dsub_2_in_DPR_8, .RegSet: DQuad_with_dsub_2_in_DPR_8Bits, .NameIdx: 888, .RegsSize: 6, .RegSetSize: sizeof(DQuad_with_dsub_2_in_DPR_8Bits), .ID: ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2558 { .RegsBegin: DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, .RegSet: DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, .NameIdx: 1773, .RegsSize: 6, .RegSetSize: sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), .ID: ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2559 { .RegsBegin: DQuad_with_dsub_3_in_DPR_8, .RegSet: DQuad_with_dsub_3_in_DPR_8Bits, .NameIdx: 1032, .RegsSize: 5, .RegSetSize: sizeof(DQuad_with_dsub_3_in_DPR_8Bits), .ID: ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2560 { .RegsBegin: DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, .RegSet: DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, .NameIdx: 1842, .RegsSize: 4, .RegSetSize: sizeof(DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), .ID: ARM::DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2561 { .RegsBegin: MQQPR_with_qsub_0_in_QPR_8, .RegSet: MQQPR_with_qsub_0_in_QPR_8Bits, .NameIdx: 1145, .RegsSize: 4, .RegSetSize: sizeof(MQQPR_with_qsub_0_in_QPR_8Bits), .ID: ARM::MQQPR_with_qsub_0_in_QPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2562 { .RegsBegin: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, .RegSet: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, .NameIdx: 1230, .RegsSize: 3, .RegSetSize: sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2563 { .RegsBegin: MQQPR_with_dsub_2_in_DPR_8, .RegSet: MQQPR_with_dsub_2_in_DPR_8Bits, .NameIdx: 718, .RegsSize: 3, .RegSetSize: sizeof(MQQPR_with_dsub_2_in_DPR_8Bits), .ID: ARM::MQQPR_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2564 { .RegsBegin: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8, .RegSet: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8Bits, .NameIdx: 915, .RegsSize: 2, .RegSetSize: sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8Bits), .ID: ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2565 { .RegsBegin: QQQQPR, .RegSet: QQQQPRBits, .NameIdx: 1987, .RegsSize: 13, .RegSetSize: sizeof(QQQQPRBits), .ID: ARM::QQQQPRRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2566 { .RegsBegin: QQQQPR_with_ssub_0, .RegSet: QQQQPR_with_ssub_0Bits, .NameIdx: 0, .RegsSize: 8, .RegSetSize: sizeof(QQQQPR_with_ssub_0Bits), .ID: ARM::QQQQPR_with_ssub_0RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2567 { .RegsBegin: QQQQPR_with_ssub_4, .RegSet: QQQQPR_with_ssub_4Bits, .NameIdx: 296, .RegsSize: 7, .RegSetSize: sizeof(QQQQPR_with_ssub_4Bits), .ID: ARM::QQQQPR_with_ssub_4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2568 { .RegsBegin: QQQQPR_with_ssub_8, .RegSet: QQQQPR_with_ssub_8Bits, .NameIdx: 1371, .RegsSize: 6, .RegSetSize: sizeof(QQQQPR_with_ssub_8Bits), .ID: ARM::QQQQPR_with_ssub_8RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2569 { .RegsBegin: MQQQQPR, .RegSet: MQQQQPRBits, .NameIdx: 1986, .RegsSize: 5, .RegSetSize: sizeof(MQQQQPRBits), .ID: ARM::MQQQQPRRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2570 { .RegsBegin: MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8, .RegSet: MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8Bits, .NameIdx: 1121, .RegsSize: 4, .RegSetSize: sizeof(MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8Bits), .ID: ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2571 { .RegsBegin: MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8, .RegSet: MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8Bits, .NameIdx: 694, .RegsSize: 3, .RegSetSize: sizeof(MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8Bits), .ID: ARM::MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2572 { .RegsBegin: MQQQQPR_with_qsub_2_in_QPR_8, .RegSet: MQQQQPR_with_qsub_2_in_QPR_8Bits, .NameIdx: 1201, .RegsSize: 2, .RegSetSize: sizeof(MQQQQPR_with_qsub_2_in_QPR_8Bits), .ID: ARM::MQQQQPR_with_qsub_2_in_QPR_8RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2573 { .RegsBegin: MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8, .RegSet: MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8Bits, .NameIdx: 745, .RegsSize: 1, .RegSetSize: sizeof(MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8Bits), .ID: ARM::MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2574};
2575
2576// ARM Dwarf<->LLVM register mappings.
2577extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = {
2578 { .FromReg: 0U, .ToReg: ARM::R0 },
2579 { .FromReg: 1U, .ToReg: ARM::R1 },
2580 { .FromReg: 2U, .ToReg: ARM::R2 },
2581 { .FromReg: 3U, .ToReg: ARM::R3 },
2582 { .FromReg: 4U, .ToReg: ARM::R4 },
2583 { .FromReg: 5U, .ToReg: ARM::R5 },
2584 { .FromReg: 6U, .ToReg: ARM::R6 },
2585 { .FromReg: 7U, .ToReg: ARM::R7 },
2586 { .FromReg: 8U, .ToReg: ARM::R8 },
2587 { .FromReg: 9U, .ToReg: ARM::R9 },
2588 { .FromReg: 10U, .ToReg: ARM::R10 },
2589 { .FromReg: 11U, .ToReg: ARM::R11 },
2590 { .FromReg: 12U, .ToReg: ARM::R12 },
2591 { .FromReg: 13U, .ToReg: ARM::SP },
2592 { .FromReg: 14U, .ToReg: ARM::LR },
2593 { .FromReg: 15U, .ToReg: ARM::ZR },
2594 { .FromReg: 143U, .ToReg: ARM::RA_AUTH_CODE },
2595 { .FromReg: 256U, .ToReg: ARM::D0 },
2596 { .FromReg: 257U, .ToReg: ARM::D1 },
2597 { .FromReg: 258U, .ToReg: ARM::D2 },
2598 { .FromReg: 259U, .ToReg: ARM::D3 },
2599 { .FromReg: 260U, .ToReg: ARM::D4 },
2600 { .FromReg: 261U, .ToReg: ARM::D5 },
2601 { .FromReg: 262U, .ToReg: ARM::D6 },
2602 { .FromReg: 263U, .ToReg: ARM::D7 },
2603 { .FromReg: 264U, .ToReg: ARM::D8 },
2604 { .FromReg: 265U, .ToReg: ARM::D9 },
2605 { .FromReg: 266U, .ToReg: ARM::D10 },
2606 { .FromReg: 267U, .ToReg: ARM::D11 },
2607 { .FromReg: 268U, .ToReg: ARM::D12 },
2608 { .FromReg: 269U, .ToReg: ARM::D13 },
2609 { .FromReg: 270U, .ToReg: ARM::D14 },
2610 { .FromReg: 271U, .ToReg: ARM::D15 },
2611 { .FromReg: 272U, .ToReg: ARM::D16 },
2612 { .FromReg: 273U, .ToReg: ARM::D17 },
2613 { .FromReg: 274U, .ToReg: ARM::D18 },
2614 { .FromReg: 275U, .ToReg: ARM::D19 },
2615 { .FromReg: 276U, .ToReg: ARM::D20 },
2616 { .FromReg: 277U, .ToReg: ARM::D21 },
2617 { .FromReg: 278U, .ToReg: ARM::D22 },
2618 { .FromReg: 279U, .ToReg: ARM::D23 },
2619 { .FromReg: 280U, .ToReg: ARM::D24 },
2620 { .FromReg: 281U, .ToReg: ARM::D25 },
2621 { .FromReg: 282U, .ToReg: ARM::D26 },
2622 { .FromReg: 283U, .ToReg: ARM::D27 },
2623 { .FromReg: 284U, .ToReg: ARM::D28 },
2624 { .FromReg: 285U, .ToReg: ARM::D29 },
2625 { .FromReg: 286U, .ToReg: ARM::D30 },
2626 { .FromReg: 287U, .ToReg: ARM::D31 },
2627};
2628extern const unsigned ARMDwarfFlavour0Dwarf2LSize = std::size(ARMDwarfFlavour0Dwarf2L);
2629
2630extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = {
2631 { .FromReg: 0U, .ToReg: ARM::R0 },
2632 { .FromReg: 1U, .ToReg: ARM::R1 },
2633 { .FromReg: 2U, .ToReg: ARM::R2 },
2634 { .FromReg: 3U, .ToReg: ARM::R3 },
2635 { .FromReg: 4U, .ToReg: ARM::R4 },
2636 { .FromReg: 5U, .ToReg: ARM::R5 },
2637 { .FromReg: 6U, .ToReg: ARM::R6 },
2638 { .FromReg: 7U, .ToReg: ARM::R7 },
2639 { .FromReg: 8U, .ToReg: ARM::R8 },
2640 { .FromReg: 9U, .ToReg: ARM::R9 },
2641 { .FromReg: 10U, .ToReg: ARM::R10 },
2642 { .FromReg: 11U, .ToReg: ARM::R11 },
2643 { .FromReg: 12U, .ToReg: ARM::R12 },
2644 { .FromReg: 13U, .ToReg: ARM::SP },
2645 { .FromReg: 14U, .ToReg: ARM::LR },
2646 { .FromReg: 15U, .ToReg: ARM::ZR },
2647 { .FromReg: 143U, .ToReg: ARM::RA_AUTH_CODE },
2648 { .FromReg: 256U, .ToReg: ARM::D0 },
2649 { .FromReg: 257U, .ToReg: ARM::D1 },
2650 { .FromReg: 258U, .ToReg: ARM::D2 },
2651 { .FromReg: 259U, .ToReg: ARM::D3 },
2652 { .FromReg: 260U, .ToReg: ARM::D4 },
2653 { .FromReg: 261U, .ToReg: ARM::D5 },
2654 { .FromReg: 262U, .ToReg: ARM::D6 },
2655 { .FromReg: 263U, .ToReg: ARM::D7 },
2656 { .FromReg: 264U, .ToReg: ARM::D8 },
2657 { .FromReg: 265U, .ToReg: ARM::D9 },
2658 { .FromReg: 266U, .ToReg: ARM::D10 },
2659 { .FromReg: 267U, .ToReg: ARM::D11 },
2660 { .FromReg: 268U, .ToReg: ARM::D12 },
2661 { .FromReg: 269U, .ToReg: ARM::D13 },
2662 { .FromReg: 270U, .ToReg: ARM::D14 },
2663 { .FromReg: 271U, .ToReg: ARM::D15 },
2664 { .FromReg: 272U, .ToReg: ARM::D16 },
2665 { .FromReg: 273U, .ToReg: ARM::D17 },
2666 { .FromReg: 274U, .ToReg: ARM::D18 },
2667 { .FromReg: 275U, .ToReg: ARM::D19 },
2668 { .FromReg: 276U, .ToReg: ARM::D20 },
2669 { .FromReg: 277U, .ToReg: ARM::D21 },
2670 { .FromReg: 278U, .ToReg: ARM::D22 },
2671 { .FromReg: 279U, .ToReg: ARM::D23 },
2672 { .FromReg: 280U, .ToReg: ARM::D24 },
2673 { .FromReg: 281U, .ToReg: ARM::D25 },
2674 { .FromReg: 282U, .ToReg: ARM::D26 },
2675 { .FromReg: 283U, .ToReg: ARM::D27 },
2676 { .FromReg: 284U, .ToReg: ARM::D28 },
2677 { .FromReg: 285U, .ToReg: ARM::D29 },
2678 { .FromReg: 286U, .ToReg: ARM::D30 },
2679 { .FromReg: 287U, .ToReg: ARM::D31 },
2680};
2681extern const unsigned ARMEHFlavour0Dwarf2LSize = std::size(ARMEHFlavour0Dwarf2L);
2682
2683extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = {
2684 { .FromReg: ARM::LR, .ToReg: 14U },
2685 { .FromReg: ARM::PC, .ToReg: 15U },
2686 { .FromReg: ARM::RA_AUTH_CODE, .ToReg: 143U },
2687 { .FromReg: ARM::SP, .ToReg: 13U },
2688 { .FromReg: ARM::ZR, .ToReg: 15U },
2689 { .FromReg: ARM::D0, .ToReg: 256U },
2690 { .FromReg: ARM::D1, .ToReg: 257U },
2691 { .FromReg: ARM::D2, .ToReg: 258U },
2692 { .FromReg: ARM::D3, .ToReg: 259U },
2693 { .FromReg: ARM::D4, .ToReg: 260U },
2694 { .FromReg: ARM::D5, .ToReg: 261U },
2695 { .FromReg: ARM::D6, .ToReg: 262U },
2696 { .FromReg: ARM::D7, .ToReg: 263U },
2697 { .FromReg: ARM::D8, .ToReg: 264U },
2698 { .FromReg: ARM::D9, .ToReg: 265U },
2699 { .FromReg: ARM::D10, .ToReg: 266U },
2700 { .FromReg: ARM::D11, .ToReg: 267U },
2701 { .FromReg: ARM::D12, .ToReg: 268U },
2702 { .FromReg: ARM::D13, .ToReg: 269U },
2703 { .FromReg: ARM::D14, .ToReg: 270U },
2704 { .FromReg: ARM::D15, .ToReg: 271U },
2705 { .FromReg: ARM::D16, .ToReg: 272U },
2706 { .FromReg: ARM::D17, .ToReg: 273U },
2707 { .FromReg: ARM::D18, .ToReg: 274U },
2708 { .FromReg: ARM::D19, .ToReg: 275U },
2709 { .FromReg: ARM::D20, .ToReg: 276U },
2710 { .FromReg: ARM::D21, .ToReg: 277U },
2711 { .FromReg: ARM::D22, .ToReg: 278U },
2712 { .FromReg: ARM::D23, .ToReg: 279U },
2713 { .FromReg: ARM::D24, .ToReg: 280U },
2714 { .FromReg: ARM::D25, .ToReg: 281U },
2715 { .FromReg: ARM::D26, .ToReg: 282U },
2716 { .FromReg: ARM::D27, .ToReg: 283U },
2717 { .FromReg: ARM::D28, .ToReg: 284U },
2718 { .FromReg: ARM::D29, .ToReg: 285U },
2719 { .FromReg: ARM::D30, .ToReg: 286U },
2720 { .FromReg: ARM::D31, .ToReg: 287U },
2721 { .FromReg: ARM::R0, .ToReg: 0U },
2722 { .FromReg: ARM::R1, .ToReg: 1U },
2723 { .FromReg: ARM::R2, .ToReg: 2U },
2724 { .FromReg: ARM::R3, .ToReg: 3U },
2725 { .FromReg: ARM::R4, .ToReg: 4U },
2726 { .FromReg: ARM::R5, .ToReg: 5U },
2727 { .FromReg: ARM::R6, .ToReg: 6U },
2728 { .FromReg: ARM::R7, .ToReg: 7U },
2729 { .FromReg: ARM::R8, .ToReg: 8U },
2730 { .FromReg: ARM::R9, .ToReg: 9U },
2731 { .FromReg: ARM::R10, .ToReg: 10U },
2732 { .FromReg: ARM::R11, .ToReg: 11U },
2733 { .FromReg: ARM::R12, .ToReg: 12U },
2734};
2735extern const unsigned ARMDwarfFlavour0L2DwarfSize = std::size(ARMDwarfFlavour0L2Dwarf);
2736
2737extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = {
2738 { .FromReg: ARM::LR, .ToReg: 14U },
2739 { .FromReg: ARM::PC, .ToReg: 15U },
2740 { .FromReg: ARM::RA_AUTH_CODE, .ToReg: 143U },
2741 { .FromReg: ARM::SP, .ToReg: 13U },
2742 { .FromReg: ARM::ZR, .ToReg: 15U },
2743 { .FromReg: ARM::D0, .ToReg: 256U },
2744 { .FromReg: ARM::D1, .ToReg: 257U },
2745 { .FromReg: ARM::D2, .ToReg: 258U },
2746 { .FromReg: ARM::D3, .ToReg: 259U },
2747 { .FromReg: ARM::D4, .ToReg: 260U },
2748 { .FromReg: ARM::D5, .ToReg: 261U },
2749 { .FromReg: ARM::D6, .ToReg: 262U },
2750 { .FromReg: ARM::D7, .ToReg: 263U },
2751 { .FromReg: ARM::D8, .ToReg: 264U },
2752 { .FromReg: ARM::D9, .ToReg: 265U },
2753 { .FromReg: ARM::D10, .ToReg: 266U },
2754 { .FromReg: ARM::D11, .ToReg: 267U },
2755 { .FromReg: ARM::D12, .ToReg: 268U },
2756 { .FromReg: ARM::D13, .ToReg: 269U },
2757 { .FromReg: ARM::D14, .ToReg: 270U },
2758 { .FromReg: ARM::D15, .ToReg: 271U },
2759 { .FromReg: ARM::D16, .ToReg: 272U },
2760 { .FromReg: ARM::D17, .ToReg: 273U },
2761 { .FromReg: ARM::D18, .ToReg: 274U },
2762 { .FromReg: ARM::D19, .ToReg: 275U },
2763 { .FromReg: ARM::D20, .ToReg: 276U },
2764 { .FromReg: ARM::D21, .ToReg: 277U },
2765 { .FromReg: ARM::D22, .ToReg: 278U },
2766 { .FromReg: ARM::D23, .ToReg: 279U },
2767 { .FromReg: ARM::D24, .ToReg: 280U },
2768 { .FromReg: ARM::D25, .ToReg: 281U },
2769 { .FromReg: ARM::D26, .ToReg: 282U },
2770 { .FromReg: ARM::D27, .ToReg: 283U },
2771 { .FromReg: ARM::D28, .ToReg: 284U },
2772 { .FromReg: ARM::D29, .ToReg: 285U },
2773 { .FromReg: ARM::D30, .ToReg: 286U },
2774 { .FromReg: ARM::D31, .ToReg: 287U },
2775 { .FromReg: ARM::R0, .ToReg: 0U },
2776 { .FromReg: ARM::R1, .ToReg: 1U },
2777 { .FromReg: ARM::R2, .ToReg: 2U },
2778 { .FromReg: ARM::R3, .ToReg: 3U },
2779 { .FromReg: ARM::R4, .ToReg: 4U },
2780 { .FromReg: ARM::R5, .ToReg: 5U },
2781 { .FromReg: ARM::R6, .ToReg: 6U },
2782 { .FromReg: ARM::R7, .ToReg: 7U },
2783 { .FromReg: ARM::R8, .ToReg: 8U },
2784 { .FromReg: ARM::R9, .ToReg: 9U },
2785 { .FromReg: ARM::R10, .ToReg: 10U },
2786 { .FromReg: ARM::R11, .ToReg: 11U },
2787 { .FromReg: ARM::R12, .ToReg: 12U },
2788};
2789extern const unsigned ARMEHFlavour0L2DwarfSize = std::size(ARMEHFlavour0L2Dwarf);
2790
2791extern const uint16_t ARMRegEncodingTable[] = {
2792 0,
2793 15,
2794 15,
2795 0,
2796 14,
2797 15,
2798 8,
2799 9,
2800 3,
2801 3,
2802 2,
2803 3,
2804 0,
2805 4,
2806 14,
2807 15,
2808 12,
2809 13,
2810 2,
2811 64,
2812 15,
2813 0,
2814 1,
2815 2,
2816 3,
2817 4,
2818 5,
2819 6,
2820 7,
2821 8,
2822 9,
2823 10,
2824 11,
2825 12,
2826 13,
2827 14,
2828 15,
2829 16,
2830 17,
2831 18,
2832 19,
2833 20,
2834 21,
2835 22,
2836 23,
2837 24,
2838 25,
2839 26,
2840 27,
2841 28,
2842 29,
2843 30,
2844 31,
2845 10,
2846 7,
2847 6,
2848 5,
2849 13,
2850 0,
2851 1,
2852 2,
2853 3,
2854 4,
2855 5,
2856 6,
2857 7,
2858 8,
2859 9,
2860 10,
2861 11,
2862 12,
2863 13,
2864 14,
2865 15,
2866 0,
2867 1,
2868 2,
2869 3,
2870 4,
2871 5,
2872 6,
2873 7,
2874 8,
2875 9,
2876 10,
2877 11,
2878 12,
2879 0,
2880 1,
2881 2,
2882 3,
2883 4,
2884 5,
2885 6,
2886 7,
2887 8,
2888 9,
2889 10,
2890 11,
2891 12,
2892 13,
2893 14,
2894 15,
2895 16,
2896 17,
2897 18,
2898 19,
2899 20,
2900 21,
2901 22,
2902 23,
2903 24,
2904 25,
2905 26,
2906 27,
2907 28,
2908 29,
2909 30,
2910 31,
2911 0,
2912 1,
2913 2,
2914 3,
2915 4,
2916 5,
2917 6,
2918 7,
2919 8,
2920 9,
2921 10,
2922 11,
2923 12,
2924 13,
2925 14,
2926 15,
2927 16,
2928 17,
2929 18,
2930 19,
2931 20,
2932 21,
2933 22,
2934 23,
2935 24,
2936 25,
2937 26,
2938 27,
2939 28,
2940 29,
2941 0,
2942 1,
2943 2,
2944 3,
2945 4,
2946 5,
2947 6,
2948 7,
2949 8,
2950 9,
2951 10,
2952 11,
2953 12,
2954 13,
2955 14,
2956 0,
2957 1,
2958 2,
2959 3,
2960 4,
2961 5,
2962 6,
2963 7,
2964 8,
2965 9,
2966 10,
2967 11,
2968 12,
2969 0,
2970 2,
2971 4,
2972 6,
2973 8,
2974 10,
2975 12,
2976 0,
2977 1,
2978 2,
2979 3,
2980 4,
2981 5,
2982 6,
2983 7,
2984 8,
2985 9,
2986 10,
2987 11,
2988 12,
2989 13,
2990 14,
2991 15,
2992 16,
2993 17,
2994 18,
2995 19,
2996 20,
2997 21,
2998 22,
2999 23,
3000 24,
3001 25,
3002 26,
3003 27,
3004 28,
3005 29,
3006 0,
3007 1,
3008 2,
3009 3,
3010 4,
3011 5,
3012 6,
3013 7,
3014 8,
3015 9,
3016 10,
3017 11,
3018 12,
3019 13,
3020 14,
3021 15,
3022 16,
3023 17,
3024 18,
3025 19,
3026 20,
3027 21,
3028 22,
3029 23,
3030 24,
3031 25,
3032 26,
3033 27,
3034 0,
3035 1,
3036 2,
3037 3,
3038 4,
3039 5,
3040 6,
3041 7,
3042 8,
3043 9,
3044 10,
3045 11,
3046 12,
3047 13,
3048 14,
3049 15,
3050 16,
3051 17,
3052 18,
3053 19,
3054 20,
3055 21,
3056 22,
3057 23,
3058 24,
3059 25,
3060 1,
3061 3,
3062 5,
3063 7,
3064 9,
3065 11,
3066 13,
3067 15,
3068 17,
3069 19,
3070 21,
3071 23,
3072 25,
3073 27,
3074 29,
3075 1,
3076 3,
3077 5,
3078 7,
3079 9,
3080 11,
3081 13,
3082 15,
3083 17,
3084 19,
3085 21,
3086 23,
3087 25,
3088 27,
3089};
3090static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3091 RI->InitMCRegisterInfo(D: ARMRegDesc, NR: 297, RA, PC, C: ARMMCRegisterClasses, NC: 137, RURoots: ARMRegUnitRoots, NRU: 88, DL: ARMRegDiffLists, RUMS: ARMLaneMaskLists, Strings: ARMRegStrings, ClassStrings: ARMRegClassStrings, SubIndices: ARMSubRegIdxLists, NumIndices: 57,
3092RET: ARMRegEncodingTable, RUI: nullptr);
3093
3094 switch (DwarfFlavour) {
3095 default:
3096 llvm_unreachable("Unknown DWARF flavour");
3097 case 0:
3098 RI->mapDwarfRegsToLLVMRegs(Map: ARMDwarfFlavour0Dwarf2L, Size: ARMDwarfFlavour0Dwarf2LSize, isEH: false);
3099 break;
3100 }
3101 switch (EHFlavour) {
3102 default:
3103 llvm_unreachable("Unknown DWARF flavour");
3104 case 0:
3105 RI->mapDwarfRegsToLLVMRegs(Map: ARMEHFlavour0Dwarf2L, Size: ARMEHFlavour0Dwarf2LSize, isEH: true);
3106 break;
3107 }
3108 switch (DwarfFlavour) {
3109 default:
3110 llvm_unreachable("Unknown DWARF flavour");
3111 case 0:
3112 RI->mapLLVMRegsToDwarfRegs(Map: ARMDwarfFlavour0L2Dwarf, Size: ARMDwarfFlavour0L2DwarfSize, isEH: false);
3113 break;
3114 }
3115 switch (EHFlavour) {
3116 default:
3117 llvm_unreachable("Unknown DWARF flavour");
3118 case 0:
3119 RI->mapLLVMRegsToDwarfRegs(Map: ARMEHFlavour0L2Dwarf, Size: ARMEHFlavour0L2DwarfSize, isEH: true);
3120 break;
3121 }
3122}
3123
3124
3125} // namespace llvm
3126