1//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides ARM specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "ARMMCTargetDesc.h"
14#include "ARMAddressingModes.h"
15#include "ARMBaseInfo.h"
16#include "ARMInstPrinter.h"
17#include "ARMMCAsmInfo.h"
18#include "TargetInfo/ARMTargetInfo.h"
19#include "llvm/DebugInfo/CodeView/CodeView.h"
20#include "llvm/MC/MCAsmBackend.h"
21#include "llvm/MC/MCCodeEmitter.h"
22#include "llvm/MC/MCELFStreamer.h"
23#include "llvm/MC/MCInstrAnalysis.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCObjectWriter.h"
26#include "llvm/MC/MCRegisterInfo.h"
27#include "llvm/MC/MCStreamer.h"
28#include "llvm/MC/MCSubtargetInfo.h"
29#include "llvm/MC/TargetRegistry.h"
30#include "llvm/Support/Compiler.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/TargetParser/Triple.h"
33
34using namespace llvm;
35
36#define GET_REGINFO_MC_DESC
37#include "ARMGenRegisterInfo.inc"
38
39static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
40 std::string &Info) {
41 if (STI.hasFeature(Feature: llvm::ARM::HasV7Ops) &&
42 (MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 15) &&
43 (MI.getOperand(i: 1).isImm() && MI.getOperand(i: 1).getImm() == 0) &&
44 // Checks for the deprecated CP15ISB encoding:
45 // mcr p15, #0, rX, c7, c5, #4
46 (MI.getOperand(i: 3).isImm() && MI.getOperand(i: 3).getImm() == 7)) {
47 if ((MI.getOperand(i: 5).isImm() && MI.getOperand(i: 5).getImm() == 4)) {
48 if (MI.getOperand(i: 4).isImm() && MI.getOperand(i: 4).getImm() == 5) {
49 Info = "deprecated since v7, use 'isb'";
50 return true;
51 }
52
53 // Checks for the deprecated CP15DSB encoding:
54 // mcr p15, #0, rX, c7, c10, #4
55 if (MI.getOperand(i: 4).isImm() && MI.getOperand(i: 4).getImm() == 10) {
56 Info = "deprecated since v7, use 'dsb'";
57 return true;
58 }
59 }
60 // Checks for the deprecated CP15DMB encoding:
61 // mcr p15, #0, rX, c7, c10, #5
62 if (MI.getOperand(i: 4).isImm() && MI.getOperand(i: 4).getImm() == 10 &&
63 (MI.getOperand(i: 5).isImm() && MI.getOperand(i: 5).getImm() == 5)) {
64 Info = "deprecated since v7, use 'dmb'";
65 return true;
66 }
67 }
68 if (STI.hasFeature(Feature: llvm::ARM::HasV7Ops) &&
69 ((MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 10) ||
70 (MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 11))) {
71 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
72 "point instructions";
73 return true;
74 }
75 return false;
76}
77
78static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
79 std::string &Info) {
80 if (STI.hasFeature(Feature: llvm::ARM::HasV7Ops) &&
81 ((MI.getOperand(i: 1).isImm() && MI.getOperand(i: 1).getImm() == 10) ||
82 (MI.getOperand(i: 1).isImm() && MI.getOperand(i: 1).getImm() == 11))) {
83 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
84 "point instructions";
85 return true;
86 }
87 return false;
88}
89
90static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
91 std::string &Info) {
92 assert(!STI.hasFeature(llvm::ARM::ModeThumb) &&
93 "cannot predicate thumb instructions");
94
95 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
96 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
97 assert(MI.getOperand(OI).isReg() && "expected register");
98 if (MI.getOperand(i: OI).getReg() == ARM::PC) {
99 Info = "use of PC in the list is deprecated";
100 return true;
101 }
102 }
103 return false;
104}
105
106static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
107 std::string &Info) {
108 assert(!STI.hasFeature(llvm::ARM::ModeThumb) &&
109 "cannot predicate thumb instructions");
110
111 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
112 bool ListContainsPC = false, ListContainsLR = false;
113 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
114 assert(MI.getOperand(OI).isReg() && "expected register");
115 switch (MI.getOperand(i: OI).getReg().id()) {
116 default:
117 break;
118 case ARM::LR:
119 ListContainsLR = true;
120 break;
121 case ARM::PC:
122 ListContainsPC = true;
123 break;
124 }
125 }
126
127 if (ListContainsPC && ListContainsLR) {
128 Info = "use of LR and PC simultaneously in the list is deprecated";
129 return true;
130 }
131
132 return false;
133}
134
135#define GET_INSTRINFO_MC_DESC
136#define ENABLE_INSTR_PREDICATE_VERIFIER
137#include "ARMGenInstrInfo.inc"
138
139#define GET_SUBTARGETINFO_MC_DESC
140#include "ARMGenSubtargetInfo.inc"
141
142std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
143 std::string ARMArchFeature;
144
145 ARM::ArchKind ArchID = ARM::parseArch(Arch: TT.getArchName());
146 if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))
147 ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(AK: ArchID)).str();
148
149 if (TT.isThumb()) {
150 if (!ARMArchFeature.empty())
151 ARMArchFeature += ",";
152 ARMArchFeature += "+thumb-mode,+v4t";
153 }
154
155 if (TT.isOSWindows()) {
156 if (!ARMArchFeature.empty())
157 ARMArchFeature += ",";
158 ARMArchFeature += "+noarm";
159 }
160
161 return ARMArchFeature;
162}
163
164bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
165 const MCInstrDesc &Desc = MCII->get(Opcode: MI.getOpcode());
166 int PredOpIdx = Desc.findFirstPredOperandIdx();
167 return PredOpIdx != -1 && MI.getOperand(i: PredOpIdx).getImm() != ARMCC::AL;
168}
169
170bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
171 const MCInstrDesc &Desc = MCII->get(Opcode: MI.getOpcode());
172 for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
173 const MCOperand &MO = MI.getOperand(i: I);
174 if (MO.isReg() && MO.getReg() == ARM::CPSR &&
175 Desc.operands()[I].isOptionalDef())
176 return true;
177 }
178 return false;
179}
180
181uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc,
182 uint64_t Addr, int64_t Imm) {
183 // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
184 // is 4 bytes.
185 uint64_t Offset =
186 ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8;
187
188 // A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code
189 // which is 32-bit aligned. The target address for the case is calculated as
190 // targetAddress = Align(PC,4) + imm32;
191 // where
192 // Align(x, y) = y * (x DIV y);
193 if (InstDesc.getOpcode() == ARM::tBLXi)
194 Addr &= ~0x3;
195
196 return Addr + Imm + Offset;
197}
198
199MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
200 StringRef CPU, StringRef FS) {
201 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
202 if (!FS.empty()) {
203 if (!ArchFS.empty())
204 ArchFS = (Twine(ArchFS) + "," + FS).str();
205 else
206 ArchFS = std::string(FS);
207 }
208
209 return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS: ArchFS);
210}
211
212static MCInstrInfo *createARMMCInstrInfo() {
213 MCInstrInfo *X = new MCInstrInfo();
214 InitARMMCInstrInfo(II: X);
215 return X;
216}
217
218void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
219 // Mapping from CodeView to MC register id.
220 static const struct {
221 codeview::RegisterId CVReg;
222 MCPhysReg Reg;
223 } RegMap[] = {
224 {.CVReg: codeview::RegisterId::ARM_R0, .Reg: ARM::R0},
225 {.CVReg: codeview::RegisterId::ARM_R1, .Reg: ARM::R1},
226 {.CVReg: codeview::RegisterId::ARM_R2, .Reg: ARM::R2},
227 {.CVReg: codeview::RegisterId::ARM_R3, .Reg: ARM::R3},
228 {.CVReg: codeview::RegisterId::ARM_R4, .Reg: ARM::R4},
229 {.CVReg: codeview::RegisterId::ARM_R5, .Reg: ARM::R5},
230 {.CVReg: codeview::RegisterId::ARM_R6, .Reg: ARM::R6},
231 {.CVReg: codeview::RegisterId::ARM_R7, .Reg: ARM::R7},
232 {.CVReg: codeview::RegisterId::ARM_R8, .Reg: ARM::R8},
233 {.CVReg: codeview::RegisterId::ARM_R9, .Reg: ARM::R9},
234 {.CVReg: codeview::RegisterId::ARM_R10, .Reg: ARM::R10},
235 {.CVReg: codeview::RegisterId::ARM_R11, .Reg: ARM::R11},
236 {.CVReg: codeview::RegisterId::ARM_R12, .Reg: ARM::R12},
237 {.CVReg: codeview::RegisterId::ARM_SP, .Reg: ARM::SP},
238 {.CVReg: codeview::RegisterId::ARM_LR, .Reg: ARM::LR},
239 {.CVReg: codeview::RegisterId::ARM_PC, .Reg: ARM::PC},
240 {.CVReg: codeview::RegisterId::ARM_CPSR, .Reg: ARM::CPSR},
241 {.CVReg: codeview::RegisterId::ARM_FPSCR, .Reg: ARM::FPSCR},
242 {.CVReg: codeview::RegisterId::ARM_FPEXC, .Reg: ARM::FPEXC},
243 {.CVReg: codeview::RegisterId::ARM_FS0, .Reg: ARM::S0},
244 {.CVReg: codeview::RegisterId::ARM_FS1, .Reg: ARM::S1},
245 {.CVReg: codeview::RegisterId::ARM_FS2, .Reg: ARM::S2},
246 {.CVReg: codeview::RegisterId::ARM_FS3, .Reg: ARM::S3},
247 {.CVReg: codeview::RegisterId::ARM_FS4, .Reg: ARM::S4},
248 {.CVReg: codeview::RegisterId::ARM_FS5, .Reg: ARM::S5},
249 {.CVReg: codeview::RegisterId::ARM_FS6, .Reg: ARM::S6},
250 {.CVReg: codeview::RegisterId::ARM_FS7, .Reg: ARM::S7},
251 {.CVReg: codeview::RegisterId::ARM_FS8, .Reg: ARM::S8},
252 {.CVReg: codeview::RegisterId::ARM_FS9, .Reg: ARM::S9},
253 {.CVReg: codeview::RegisterId::ARM_FS10, .Reg: ARM::S10},
254 {.CVReg: codeview::RegisterId::ARM_FS11, .Reg: ARM::S11},
255 {.CVReg: codeview::RegisterId::ARM_FS12, .Reg: ARM::S12},
256 {.CVReg: codeview::RegisterId::ARM_FS13, .Reg: ARM::S13},
257 {.CVReg: codeview::RegisterId::ARM_FS14, .Reg: ARM::S14},
258 {.CVReg: codeview::RegisterId::ARM_FS15, .Reg: ARM::S15},
259 {.CVReg: codeview::RegisterId::ARM_FS16, .Reg: ARM::S16},
260 {.CVReg: codeview::RegisterId::ARM_FS17, .Reg: ARM::S17},
261 {.CVReg: codeview::RegisterId::ARM_FS18, .Reg: ARM::S18},
262 {.CVReg: codeview::RegisterId::ARM_FS19, .Reg: ARM::S19},
263 {.CVReg: codeview::RegisterId::ARM_FS20, .Reg: ARM::S20},
264 {.CVReg: codeview::RegisterId::ARM_FS21, .Reg: ARM::S21},
265 {.CVReg: codeview::RegisterId::ARM_FS22, .Reg: ARM::S22},
266 {.CVReg: codeview::RegisterId::ARM_FS23, .Reg: ARM::S23},
267 {.CVReg: codeview::RegisterId::ARM_FS24, .Reg: ARM::S24},
268 {.CVReg: codeview::RegisterId::ARM_FS25, .Reg: ARM::S25},
269 {.CVReg: codeview::RegisterId::ARM_FS26, .Reg: ARM::S26},
270 {.CVReg: codeview::RegisterId::ARM_FS27, .Reg: ARM::S27},
271 {.CVReg: codeview::RegisterId::ARM_FS28, .Reg: ARM::S28},
272 {.CVReg: codeview::RegisterId::ARM_FS29, .Reg: ARM::S29},
273 {.CVReg: codeview::RegisterId::ARM_FS30, .Reg: ARM::S30},
274 {.CVReg: codeview::RegisterId::ARM_FS31, .Reg: ARM::S31},
275 {.CVReg: codeview::RegisterId::ARM_ND0, .Reg: ARM::D0},
276 {.CVReg: codeview::RegisterId::ARM_ND1, .Reg: ARM::D1},
277 {.CVReg: codeview::RegisterId::ARM_ND2, .Reg: ARM::D2},
278 {.CVReg: codeview::RegisterId::ARM_ND3, .Reg: ARM::D3},
279 {.CVReg: codeview::RegisterId::ARM_ND4, .Reg: ARM::D4},
280 {.CVReg: codeview::RegisterId::ARM_ND5, .Reg: ARM::D5},
281 {.CVReg: codeview::RegisterId::ARM_ND6, .Reg: ARM::D6},
282 {.CVReg: codeview::RegisterId::ARM_ND7, .Reg: ARM::D7},
283 {.CVReg: codeview::RegisterId::ARM_ND8, .Reg: ARM::D8},
284 {.CVReg: codeview::RegisterId::ARM_ND9, .Reg: ARM::D9},
285 {.CVReg: codeview::RegisterId::ARM_ND10, .Reg: ARM::D10},
286 {.CVReg: codeview::RegisterId::ARM_ND11, .Reg: ARM::D11},
287 {.CVReg: codeview::RegisterId::ARM_ND12, .Reg: ARM::D12},
288 {.CVReg: codeview::RegisterId::ARM_ND13, .Reg: ARM::D13},
289 {.CVReg: codeview::RegisterId::ARM_ND14, .Reg: ARM::D14},
290 {.CVReg: codeview::RegisterId::ARM_ND15, .Reg: ARM::D15},
291 {.CVReg: codeview::RegisterId::ARM_ND16, .Reg: ARM::D16},
292 {.CVReg: codeview::RegisterId::ARM_ND17, .Reg: ARM::D17},
293 {.CVReg: codeview::RegisterId::ARM_ND18, .Reg: ARM::D18},
294 {.CVReg: codeview::RegisterId::ARM_ND19, .Reg: ARM::D19},
295 {.CVReg: codeview::RegisterId::ARM_ND20, .Reg: ARM::D20},
296 {.CVReg: codeview::RegisterId::ARM_ND21, .Reg: ARM::D21},
297 {.CVReg: codeview::RegisterId::ARM_ND22, .Reg: ARM::D22},
298 {.CVReg: codeview::RegisterId::ARM_ND23, .Reg: ARM::D23},
299 {.CVReg: codeview::RegisterId::ARM_ND24, .Reg: ARM::D24},
300 {.CVReg: codeview::RegisterId::ARM_ND25, .Reg: ARM::D25},
301 {.CVReg: codeview::RegisterId::ARM_ND26, .Reg: ARM::D26},
302 {.CVReg: codeview::RegisterId::ARM_ND27, .Reg: ARM::D27},
303 {.CVReg: codeview::RegisterId::ARM_ND28, .Reg: ARM::D28},
304 {.CVReg: codeview::RegisterId::ARM_ND29, .Reg: ARM::D29},
305 {.CVReg: codeview::RegisterId::ARM_ND30, .Reg: ARM::D30},
306 {.CVReg: codeview::RegisterId::ARM_ND31, .Reg: ARM::D31},
307 {.CVReg: codeview::RegisterId::ARM_NQ0, .Reg: ARM::Q0},
308 {.CVReg: codeview::RegisterId::ARM_NQ1, .Reg: ARM::Q1},
309 {.CVReg: codeview::RegisterId::ARM_NQ2, .Reg: ARM::Q2},
310 {.CVReg: codeview::RegisterId::ARM_NQ3, .Reg: ARM::Q3},
311 {.CVReg: codeview::RegisterId::ARM_NQ4, .Reg: ARM::Q4},
312 {.CVReg: codeview::RegisterId::ARM_NQ5, .Reg: ARM::Q5},
313 {.CVReg: codeview::RegisterId::ARM_NQ6, .Reg: ARM::Q6},
314 {.CVReg: codeview::RegisterId::ARM_NQ7, .Reg: ARM::Q7},
315 {.CVReg: codeview::RegisterId::ARM_NQ8, .Reg: ARM::Q8},
316 {.CVReg: codeview::RegisterId::ARM_NQ9, .Reg: ARM::Q9},
317 {.CVReg: codeview::RegisterId::ARM_NQ10, .Reg: ARM::Q10},
318 {.CVReg: codeview::RegisterId::ARM_NQ11, .Reg: ARM::Q11},
319 {.CVReg: codeview::RegisterId::ARM_NQ12, .Reg: ARM::Q12},
320 {.CVReg: codeview::RegisterId::ARM_NQ13, .Reg: ARM::Q13},
321 {.CVReg: codeview::RegisterId::ARM_NQ14, .Reg: ARM::Q14},
322 {.CVReg: codeview::RegisterId::ARM_NQ15, .Reg: ARM::Q15},
323 };
324 for (const auto &I : RegMap)
325 MRI->mapLLVMRegToCVReg(LLVMReg: I.Reg, CVReg: static_cast<int>(I.CVReg));
326}
327
328static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
329 MCRegisterInfo *X = new MCRegisterInfo();
330 InitARMMCRegisterInfo(RI: X, RA: ARM::LR, DwarfFlavour: 0, EHFlavour: 0, PC: ARM::PC);
331 ARM_MC::initLLVMToCVRegMapping(MRI: X);
332 return X;
333}
334
335static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
336 const Triple &TheTriple,
337 const MCTargetOptions &Options) {
338 MCAsmInfo *MAI;
339 if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
340 MAI = new ARMMCAsmInfoDarwin(TheTriple, Options);
341 else if (TheTriple.isWindowsMSVCEnvironment())
342 MAI = new ARMCOFFMCAsmInfoMicrosoft(Options);
343 else if (TheTriple.isOSWindows())
344 MAI = new ARMCOFFMCAsmInfoGNU(Options);
345 else
346 MAI = new ARMELFMCAsmInfo(TheTriple, Options);
347
348 unsigned Reg = MRI.getDwarfRegNum(Reg: ARM::SP, isEH: true);
349 MAI->addInitialFrameState(Inst: MCCFIInstruction::cfiDefCfa(L: nullptr, Register: Reg, Offset: 0));
350
351 return MAI;
352}
353
354static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
355 std::unique_ptr<MCAsmBackend> &&MAB,
356 std::unique_ptr<MCObjectWriter> &&OW,
357 std::unique_ptr<MCCodeEmitter> &&Emitter) {
358 return createARMELFStreamer(Context&: Ctx, TAB: std::move(MAB), OW: std::move(OW),
359 Emitter: std::move(Emitter), IsThumb: T.isThumb(), IsAndroid: T.isAndroid());
360}
361
362static MCStreamer *
363createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
364 std::unique_ptr<MCObjectWriter> &&OW,
365 std::unique_ptr<MCCodeEmitter> &&Emitter) {
366 return createMachOStreamer(Ctx, TAB: std::move(MAB), OW: std::move(OW),
367 CE: std::move(Emitter), DWARFMustBeAtTheEnd: false);
368}
369
370static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
371 unsigned SyntaxVariant,
372 const MCAsmInfo &MAI,
373 const MCInstrInfo &MII,
374 const MCRegisterInfo &MRI) {
375 if (SyntaxVariant == 0)
376 return new ARMInstPrinter(MAI, MII, MRI);
377 return nullptr;
378}
379
380static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
381 MCContext &Ctx) {
382 if (TT.isOSBinFormatMachO())
383 return createARMMachORelocationInfo(Ctx);
384 // Default to the stock relocation info.
385 return llvm::createMCRelocationInfo(TT, Ctx);
386}
387
388namespace {
389
390class ARMMCInstrAnalysis : public MCInstrAnalysis {
391public:
392 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
393
394 bool isUnconditionalBranch(const MCInst &Inst) const override {
395 // BCCs with the "always" predicate are unconditional branches.
396 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(i: 1).getImm()==ARMCC::AL)
397 return true;
398 return MCInstrAnalysis::isUnconditionalBranch(Inst);
399 }
400
401 bool isConditionalBranch(const MCInst &Inst) const override {
402 // BCCs with the "always" predicate are unconditional branches.
403 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(i: 1).getImm()==ARMCC::AL)
404 return false;
405 return MCInstrAnalysis::isConditionalBranch(Inst);
406 }
407
408 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
409 uint64_t &Target) const override {
410 const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode());
411
412 // Find the PC-relative immediate operand in the instruction.
413 for (unsigned OpNum = 0; OpNum < Desc.getNumOperands(); ++OpNum) {
414 if (Inst.getOperand(i: OpNum).isImm() &&
415 Desc.operands()[OpNum].OperandType == MCOI::OPERAND_PCREL) {
416 int64_t Imm = Inst.getOperand(i: OpNum).getImm();
417 Target = ARM_MC::evaluateBranchTarget(InstDesc: Desc, Addr, Imm);
418 return true;
419 }
420 }
421 return false;
422 }
423
424 std::optional<uint64_t>
425 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,
426 uint64_t Addr, uint64_t Size) const override;
427
428 std::vector<std::pair<uint64_t, uint64_t>>
429 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
430 const MCSubtargetInfo &STI) const override;
431};
432
433} // namespace
434
435static std::optional<uint64_t>
436// NOLINTNEXTLINE(readability-identifier-naming)
437evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc,
438 unsigned MemOpIndex, uint64_t Addr) {
439 if (MemOpIndex + 1 >= Desc.getNumOperands())
440 return std::nullopt;
441
442 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
443 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
444 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
445 return std::nullopt;
446
447 int32_t OffImm = (int32_t)MO2.getImm();
448 // Special value for #-0. All others are normal.
449 if (OffImm == INT32_MIN)
450 OffImm = 0;
451 return Addr + OffImm;
452}
453
454static std::optional<uint64_t>
455evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc,
456 unsigned MemOpIndex, uint64_t Addr) {
457 if (MemOpIndex + 2 >= Desc.getNumOperands())
458 return std::nullopt;
459
460 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
461 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
462 const MCOperand &MO3 = Inst.getOperand(i: MemOpIndex + 2);
463 if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm())
464 return std::nullopt;
465
466 unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc: MO3.getImm());
467 ARM_AM::AddrOpc Op = ARM_AM::getAM3Op(AM3Opc: MO3.getImm());
468
469 if (Op == ARM_AM::sub)
470 return Addr - ImmOffs;
471 return Addr + ImmOffs;
472}
473
474static std::optional<uint64_t>
475evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc,
476 unsigned MemOpIndex, uint64_t Addr) {
477 if (MemOpIndex + 1 >= Desc.getNumOperands())
478 return std::nullopt;
479
480 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
481 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
482 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
483 return std::nullopt;
484
485 unsigned ImmOffs = ARM_AM::getAM5Offset(AM5Opc: MO2.getImm());
486 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(AM5Opc: MO2.getImm());
487
488 if (Op == ARM_AM::sub)
489 return Addr - ImmOffs * 4;
490 return Addr + ImmOffs * 4;
491}
492
493static std::optional<uint64_t>
494evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc,
495 unsigned MemOpIndex, uint64_t Addr) {
496 if (MemOpIndex + 1 >= Desc.getNumOperands())
497 return std::nullopt;
498
499 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
500 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
501 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
502 return std::nullopt;
503
504 unsigned ImmOffs = ARM_AM::getAM5FP16Offset(AM5Opc: MO2.getImm());
505 ARM_AM::AddrOpc Op = ARM_AM::getAM5FP16Op(AM5Opc: MO2.getImm());
506
507 if (Op == ARM_AM::sub)
508 return Addr - ImmOffs * 2;
509 return Addr + ImmOffs * 2;
510}
511
512static std::optional<uint64_t>
513// NOLINTNEXTLINE(readability-identifier-naming)
514evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc,
515 unsigned MemOpIndex, uint64_t Addr) {
516 if (MemOpIndex + 1 >= Desc.getNumOperands())
517 return std::nullopt;
518
519 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
520 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
521 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
522 return std::nullopt;
523
524 int32_t OffImm = (int32_t)MO2.getImm();
525 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
526
527 // Special value for #-0. All others are normal.
528 if (OffImm == INT32_MIN)
529 OffImm = 0;
530 return Addr + OffImm;
531}
532
533static std::optional<uint64_t>
534// NOLINTNEXTLINE(readability-identifier-naming)
535evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc,
536 unsigned MemOpIndex, uint64_t Addr) {
537 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
538 if (!MO1.isImm())
539 return std::nullopt;
540
541 int32_t OffImm = (int32_t)MO1.getImm();
542
543 // Special value for #-0. All others are normal.
544 if (OffImm == INT32_MIN)
545 OffImm = 0;
546 return Addr + OffImm;
547}
548
549static std::optional<uint64_t>
550// NOLINTNEXTLINE(readability-identifier-naming)
551evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc,
552 unsigned MemOpIndex, uint64_t Addr) {
553 return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex, Addr);
554}
555
556std::optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
557 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
558 uint64_t Size) const {
559 const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode());
560
561 // Only load instructions can have PC-relative memory addressing.
562 if (!Desc.mayLoad())
563 return std::nullopt;
564
565 // PC-relative addressing does not update the base register.
566 uint64_t TSFlags = Desc.TSFlags;
567 unsigned IndexMode =
568 (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
569 if (IndexMode != ARMII::IndexModeNone)
570 return std::nullopt;
571
572 // Find the memory addressing operand in the instruction.
573 unsigned OpIndex = Desc.NumDefs;
574 while (OpIndex < Desc.getNumOperands() &&
575 Desc.operands()[OpIndex].OperandType != MCOI::OPERAND_MEMORY)
576 ++OpIndex;
577 if (OpIndex == Desc.getNumOperands())
578 return std::nullopt;
579
580 // Base address for PC-relative addressing is always 32-bit aligned.
581 Addr &= ~0x3;
582
583 // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
584 // is 4 bytes.
585 switch (Desc.TSFlags & ARMII::FormMask) {
586 default:
587 Addr += 8;
588 break;
589 case ARMII::ThumbFrm:
590 Addr += 4;
591 break;
592 // VLDR* instructions share the same opcode (and thus the same form) for Arm
593 // and Thumb. Use a bit longer route through STI in that case.
594 case ARMII::VFPLdStFrm:
595 Addr += STI->hasFeature(Feature: ARM::ModeThumb) ? 4 : 8;
596 break;
597 }
598
599 // Evaluate the address depending on the addressing mode
600 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
601 switch (AddrMode) {
602 default:
603 return std::nullopt;
604 case ARMII::AddrMode_i12:
605 return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, MemOpIndex: OpIndex, Addr);
606 case ARMII::AddrMode3:
607 return evaluateMemOpAddrForAddrMode3(Inst, Desc, MemOpIndex: OpIndex, Addr);
608 case ARMII::AddrMode5:
609 return evaluateMemOpAddrForAddrMode5(Inst, Desc, MemOpIndex: OpIndex, Addr);
610 case ARMII::AddrMode5FP16:
611 return evaluateMemOpAddrForAddrMode5FP16(Inst, Desc, MemOpIndex: OpIndex, Addr);
612 case ARMII::AddrModeT2_i8s4:
613 return evaluateMemOpAddrForAddrModeT2_i8s4(Inst, Desc, MemOpIndex: OpIndex, Addr);
614 case ARMII::AddrModeT2_pc:
615 return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex: OpIndex, Addr);
616 case ARMII::AddrModeT1_s:
617 return evaluateMemOpAddrForAddrModeT1_s(Inst, Desc, MemOpIndex: OpIndex, Addr);
618 }
619}
620
621template <typename T, size_t N>
622static bool instructionsMatch(const T (&Insns)[N], const uint8_t *Buf,
623 llvm::endianness E) {
624 for (size_t I = 0; I < N; ++I) {
625 T Val = support::endian::read<T>(Buf + I * sizeof(T), E);
626 if (Val != Insns[I])
627 return false;
628 }
629 return true;
630}
631
632std::vector<std::pair<uint64_t, uint64_t>>
633ARMMCInstrAnalysis::findPltEntries(uint64_t PltSectionVA,
634 ArrayRef<uint8_t> PltContents,
635 const MCSubtargetInfo &STI) const {
636 llvm::endianness DataEndianness = STI.getTargetTriple().isLittleEndian()
637 ? endianness::little
638 : endianness::big;
639 llvm::endianness InstrEndianness =
640 STI.checkFeatures(FS: "+big-endian-instructions") ? endianness::big
641 : endianness::little;
642
643 // Do a lightweight parsing of PLT entries.
644 std::vector<std::pair<uint64_t, uint64_t>> Result;
645 if (STI.checkFeatures(FS: "+thumb-mode")) {
646 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 12 < End;
647 Byte += 16) {
648 // Expected instruction sequence:
649 //
650 // movw ip, #lower16
651 // movt ip, #upper16
652 // add ip, pc
653 // ldr.w pc, [ip]
654 // b . -4
655
656 uint32_t MovwPart1 =
657 support::endian::read16(P: PltContents.data() + Byte, E: InstrEndianness);
658 if ((MovwPart1 & 0xffb0) != 0xf200)
659 continue;
660
661 uint32_t MovwPart2 = support::endian::read16(
662 P: PltContents.data() + Byte + 2, E: InstrEndianness);
663 if ((MovwPart2 & 0x8f00) != 0xc00)
664 continue;
665
666 uint64_t OffsetLower = (MovwPart2 & 0xff) + ((MovwPart2 & 0x7000) >> 4) +
667 ((MovwPart1 & 0x400) << 1) +
668 ((MovwPart1 & 0xf) << 12);
669
670 uint32_t MovtPart1 = support::endian::read16(
671 P: PltContents.data() + Byte + 4, E: InstrEndianness);
672 if ((MovtPart1 & 0xfbf0) != 0xf2c0)
673 continue;
674
675 uint32_t MovtPart2 = support::endian::read16(
676 P: PltContents.data() + Byte + 6, E: InstrEndianness);
677 if ((MovtPart2 & 0x8f00) != 0xc00)
678 continue;
679
680 uint64_t OffsetHigher =
681 ((MovtPart2 & 0xff) << 16) + ((MovtPart2 & 0x7000) << 12) +
682 ((MovtPart1 & 0x400) << 17) + ((MovtPart1 & 0xf) << 28);
683
684 const uint16_t Insns[] = {
685 0x44fc, // add ip, pc
686 0xf8dc, 0xf000, // ldr.w pc, [ip]
687 0xe7fc, // b . -4
688 };
689
690 if (!instructionsMatch(Insns, Buf: PltContents.data() + Byte + 8,
691 E: InstrEndianness))
692 continue;
693
694 // add ip, pc at Byte + 8 + thumb-pc-bias = 12
695 uint64_t Offset = (PltSectionVA + Byte + 12) + OffsetLower + OffsetHigher;
696 Result.emplace_back(args: PltSectionVA + Byte, args&: Offset);
697 }
698 } else {
699 const uint32_t LongEntryInsns[] = {
700 0xe59fc004, // ldr ip, L2
701 0xe08cc00f, // L1: add ip, ip, pc
702 0xe59cf000, // ldr pc, [ip]
703 };
704
705 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 12 < End;
706 Byte += 4) {
707 // Is it a long entry?
708 if (instructionsMatch(Insns: LongEntryInsns, Buf: PltContents.data() + Byte,
709 E: InstrEndianness)) {
710 // Expected instruction sequence:
711 //
712 // ldr ip, L2
713 // L1: add ip, ip, pc
714 // ldr pc, [ip]
715 // L2: .word Offset(&(.got.plt) - L1 - 8
716
717 uint64_t Offset = (PltSectionVA + Byte + 12) +
718 support::endian::read32(
719 P: PltContents.data() + Byte + 12, E: DataEndianness);
720 Result.emplace_back(args: PltSectionVA + Byte, args&: Offset);
721 Byte += 12;
722 } else {
723 // Expected instruction sequence:
724 //
725 // L1: add ip, pc, #0x0NN00000 Offset(&(.got.plt) - L1 - 8
726 // add ip, ip, #0x000NN000 Offset(&(.got.plt) - L1 - 8
727 // ldr pc, [ip, #0x00000NNN] Offset(&(.got.plt) - L1 - 8
728
729 uint32_t Add1 =
730 support::endian::read32(P: PltContents.data() + Byte, E: InstrEndianness);
731 if ((Add1 & 0xe28fc600) != 0xe28fc600)
732 continue;
733 uint32_t Add2 = support::endian::read32(P: PltContents.data() + Byte + 4,
734 E: InstrEndianness);
735 if ((Add2 & 0xe28cca00) != 0xe28cca00)
736 continue;
737 uint32_t Ldr = support::endian::read32(P: PltContents.data() + Byte + 8,
738 E: InstrEndianness);
739 if ((Ldr & 0xe5bcf000) != 0xe5bcf000)
740 continue;
741
742 // add ip, pc, #offset at Byte + 0 + arm-pc-bias = 8
743 uint64_t Offset = (PltSectionVA + Byte + 8) + ((Add1 & 0xff) << 20) +
744 ((Add2 & 0xff) << 12) + (Ldr & 0xfff);
745 Result.emplace_back(args: PltSectionVA + Byte, args&: Offset);
746 Byte += 8;
747 }
748 }
749 }
750 return Result;
751}
752
753static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
754 return new ARMMCInstrAnalysis(Info);
755}
756
757bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) {
758 // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
759 // to rely on feature bits.
760 if (Coproc >= 8)
761 return false;
762 return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc];
763}
764
765// Force static initialization.
766extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC() {
767 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
768 &getTheThumbLETarget(), &getTheThumbBETarget()}) {
769 // Register the MC asm info.
770 RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
771
772 // Register the MC instruction info.
773 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createARMMCInstrInfo);
774
775 // Register the MC register info.
776 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createARMMCRegisterInfo);
777
778 // Register the MC subtarget info.
779 TargetRegistry::RegisterMCSubtargetInfo(T&: *T,
780 Fn: ARM_MC::createARMMCSubtargetInfo);
781
782 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createELFStreamer);
783 TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createARMWinCOFFStreamer);
784 TargetRegistry::RegisterMachOStreamer(T&: *T, Fn: createARMMachOStreamer);
785
786 // Register the obj target streamer.
787 TargetRegistry::RegisterObjectTargetStreamer(T&: *T,
788 Fn: createARMObjectTargetStreamer);
789
790 // Register the asm streamer.
791 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createARMTargetAsmStreamer);
792
793 // Register the null TargetStreamer.
794 TargetRegistry::RegisterNullTargetStreamer(T&: *T, Fn: createARMNullTargetStreamer);
795
796 // Register the MCInstPrinter.
797 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createARMMCInstPrinter);
798
799 // Register the MC relocation info.
800 TargetRegistry::RegisterMCRelocationInfo(T&: *T, Fn: createARMMCRelocationInfo);
801 }
802
803 // Register the MC instruction analyzer.
804 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
805 &getTheThumbLETarget(), &getTheThumbBETarget()})
806 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createARMMCInstrAnalysis);
807
808 for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) {
809 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createARMLEMCCodeEmitter);
810 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createARMLEAsmBackend);
811 }
812 for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) {
813 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createARMBEMCCodeEmitter);
814 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createARMBEAsmBackend);
815 }
816}
817