1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t LoongArchRegDiffLists[] = {
12 /* 0 */ -32, 64, -144, 0,
13 /* 4 */ 144, -64, 32, 0,
14};
15
16extern const LaneBitmask LoongArchLaneMaskLists[] = {
17 /* 0 */ LaneBitmask(0x0000000000000001),
18 /* 1 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
19};
20
21extern const uint16_t LoongArchSubRegIdxLists[] = {
22 /* 0 */ 3, 2, 1,
23};
24
25
26#ifdef __GNUC__
27#pragma GCC diagnostic push
28#pragma GCC diagnostic ignored "-Woverlength-strings"
29#endif
30extern const char LoongArchRegStrings[] = {
31 /* 0 */ "F10\000"
32 /* 4 */ "VR10\000"
33 /* 9 */ "XR10\000"
34 /* 14 */ "F20\000"
35 /* 18 */ "VR20\000"
36 /* 23 */ "XR20\000"
37 /* 28 */ "F30\000"
38 /* 32 */ "VR30\000"
39 /* 37 */ "XR30\000"
40 /* 42 */ "FCC0\000"
41 /* 47 */ "F0\000"
42 /* 50 */ "SCR0\000"
43 /* 55 */ "FCSR0\000"
44 /* 61 */ "VR0\000"
45 /* 65 */ "XR0\000"
46 /* 69 */ "F11\000"
47 /* 73 */ "VR11\000"
48 /* 78 */ "XR11\000"
49 /* 83 */ "F21\000"
50 /* 87 */ "VR21\000"
51 /* 92 */ "XR21\000"
52 /* 97 */ "F31\000"
53 /* 101 */ "VR31\000"
54 /* 106 */ "XR31\000"
55 /* 111 */ "FCC1\000"
56 /* 116 */ "F1\000"
57 /* 119 */ "SCR1\000"
58 /* 124 */ "FCSR1\000"
59 /* 130 */ "VR1\000"
60 /* 134 */ "XR1\000"
61 /* 138 */ "F12\000"
62 /* 142 */ "VR12\000"
63 /* 147 */ "XR12\000"
64 /* 152 */ "F22\000"
65 /* 156 */ "VR22\000"
66 /* 161 */ "XR22\000"
67 /* 166 */ "FCC2\000"
68 /* 171 */ "F2\000"
69 /* 174 */ "SCR2\000"
70 /* 179 */ "FCSR2\000"
71 /* 185 */ "VR2\000"
72 /* 189 */ "XR2\000"
73 /* 193 */ "F13\000"
74 /* 197 */ "VR13\000"
75 /* 202 */ "XR13\000"
76 /* 207 */ "F23\000"
77 /* 211 */ "VR23\000"
78 /* 216 */ "XR23\000"
79 /* 221 */ "FCC3\000"
80 /* 226 */ "F3\000"
81 /* 229 */ "SCR3\000"
82 /* 234 */ "FCSR3\000"
83 /* 240 */ "VR3\000"
84 /* 244 */ "XR3\000"
85 /* 248 */ "F14\000"
86 /* 252 */ "VR14\000"
87 /* 257 */ "XR14\000"
88 /* 262 */ "F24\000"
89 /* 266 */ "VR24\000"
90 /* 271 */ "XR24\000"
91 /* 276 */ "F10_64\000"
92 /* 283 */ "F20_64\000"
93 /* 290 */ "F30_64\000"
94 /* 297 */ "F0_64\000"
95 /* 303 */ "F11_64\000"
96 /* 310 */ "F21_64\000"
97 /* 317 */ "F31_64\000"
98 /* 324 */ "F1_64\000"
99 /* 330 */ "F12_64\000"
100 /* 337 */ "F22_64\000"
101 /* 344 */ "F2_64\000"
102 /* 350 */ "F13_64\000"
103 /* 357 */ "F23_64\000"
104 /* 364 */ "F3_64\000"
105 /* 370 */ "F14_64\000"
106 /* 377 */ "F24_64\000"
107 /* 384 */ "F4_64\000"
108 /* 390 */ "F15_64\000"
109 /* 397 */ "F25_64\000"
110 /* 404 */ "F5_64\000"
111 /* 410 */ "F16_64\000"
112 /* 417 */ "F26_64\000"
113 /* 424 */ "F6_64\000"
114 /* 430 */ "F17_64\000"
115 /* 437 */ "F27_64\000"
116 /* 444 */ "F7_64\000"
117 /* 450 */ "F18_64\000"
118 /* 457 */ "F28_64\000"
119 /* 464 */ "F8_64\000"
120 /* 470 */ "F19_64\000"
121 /* 477 */ "F29_64\000"
122 /* 484 */ "F9_64\000"
123 /* 490 */ "FCC4\000"
124 /* 495 */ "F4\000"
125 /* 498 */ "VR4\000"
126 /* 502 */ "XR4\000"
127 /* 506 */ "F15\000"
128 /* 510 */ "VR15\000"
129 /* 515 */ "XR15\000"
130 /* 520 */ "F25\000"
131 /* 524 */ "VR25\000"
132 /* 529 */ "XR25\000"
133 /* 534 */ "FCC5\000"
134 /* 539 */ "F5\000"
135 /* 542 */ "VR5\000"
136 /* 546 */ "XR5\000"
137 /* 550 */ "F16\000"
138 /* 554 */ "VR16\000"
139 /* 559 */ "XR16\000"
140 /* 564 */ "F26\000"
141 /* 568 */ "VR26\000"
142 /* 573 */ "XR26\000"
143 /* 578 */ "FCC6\000"
144 /* 583 */ "F6\000"
145 /* 586 */ "VR6\000"
146 /* 590 */ "XR6\000"
147 /* 594 */ "F17\000"
148 /* 598 */ "VR17\000"
149 /* 603 */ "XR17\000"
150 /* 608 */ "F27\000"
151 /* 612 */ "VR27\000"
152 /* 617 */ "XR27\000"
153 /* 622 */ "FCC7\000"
154 /* 627 */ "F7\000"
155 /* 630 */ "VR7\000"
156 /* 634 */ "XR7\000"
157 /* 638 */ "F18\000"
158 /* 642 */ "VR18\000"
159 /* 647 */ "XR18\000"
160 /* 652 */ "F28\000"
161 /* 656 */ "VR28\000"
162 /* 661 */ "XR28\000"
163 /* 666 */ "F8\000"
164 /* 669 */ "VR8\000"
165 /* 673 */ "XR8\000"
166 /* 677 */ "F19\000"
167 /* 681 */ "VR19\000"
168 /* 686 */ "XR19\000"
169 /* 691 */ "F29\000"
170 /* 695 */ "VR29\000"
171 /* 700 */ "XR29\000"
172 /* 705 */ "F9\000"
173 /* 708 */ "VR9\000"
174 /* 712 */ "XR9\000"
175};
176#ifdef __GNUC__
177#pragma GCC diagnostic pop
178#endif
179
180extern const MCRegisterDesc LoongArchRegDesc[] = { // Descriptors
181 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
182 { .Name: 47, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12288, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
183 { .Name: 116, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12289, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
184 { .Name: 171, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12290, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
185 { .Name: 226, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12291, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
186 { .Name: 495, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12292, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
187 { .Name: 539, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12293, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
188 { .Name: 583, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12294, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
189 { .Name: 627, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12295, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
190 { .Name: 666, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12296, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
191 { .Name: 705, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12297, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
192 { .Name: 0, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12298, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
193 { .Name: 69, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12299, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
194 { .Name: 138, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12300, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
195 { .Name: 193, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12301, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
196 { .Name: 248, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12302, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
197 { .Name: 506, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12303, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
198 { .Name: 550, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12304, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
199 { .Name: 594, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12305, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
200 { .Name: 638, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12306, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
201 { .Name: 677, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12307, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
202 { .Name: 14, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12308, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
203 { .Name: 83, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12309, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
204 { .Name: 152, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12310, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
205 { .Name: 207, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12311, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
206 { .Name: 262, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12312, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
207 { .Name: 520, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12313, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
208 { .Name: 564, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12314, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
209 { .Name: 608, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12315, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
210 { .Name: 652, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12316, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
211 { .Name: 691, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12317, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
212 { .Name: 28, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12318, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
213 { .Name: 97, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12319, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
214 { .Name: 42, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12320, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
215 { .Name: 111, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12321, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
216 { .Name: 166, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12322, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
217 { .Name: 221, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12323, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
218 { .Name: 490, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12324, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
219 { .Name: 534, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12325, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
220 { .Name: 578, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12326, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
221 { .Name: 622, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12327, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
222 { .Name: 55, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12328, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
223 { .Name: 124, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12329, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
224 { .Name: 179, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12330, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
225 { .Name: 234, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12331, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
226 { .Name: 52, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12332, .RegUnitLaneMasks: 1, .IsConstant: 1, .IsArtificial: 0 },
227 { .Name: 121, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12333, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
228 { .Name: 176, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12334, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
229 { .Name: 231, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12335, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
230 { .Name: 499, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12336, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
231 { .Name: 543, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12337, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
232 { .Name: 587, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12338, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
233 { .Name: 631, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12339, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
234 { .Name: 670, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12340, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
235 { .Name: 709, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12341, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
236 { .Name: 5, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12342, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
237 { .Name: 74, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12343, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
238 { .Name: 143, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12344, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
239 { .Name: 198, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12345, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
240 { .Name: 253, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12346, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
241 { .Name: 511, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12347, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
242 { .Name: 555, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12348, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
243 { .Name: 599, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12349, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
244 { .Name: 643, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12350, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
245 { .Name: 682, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12351, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
246 { .Name: 19, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12352, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
247 { .Name: 88, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12353, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
248 { .Name: 157, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12354, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
249 { .Name: 212, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12355, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
250 { .Name: 267, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12356, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
251 { .Name: 525, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12357, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
252 { .Name: 569, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12358, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
253 { .Name: 613, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12359, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
254 { .Name: 657, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12360, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
255 { .Name: 696, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12361, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
256 { .Name: 33, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12362, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
257 { .Name: 102, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12363, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
258 { .Name: 50, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12364, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
259 { .Name: 119, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12365, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
260 { .Name: 174, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12366, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
261 { .Name: 229, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12367, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
262 { .Name: 61, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12288, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
263 { .Name: 130, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12289, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
264 { .Name: 185, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12290, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
265 { .Name: 240, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12291, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
266 { .Name: 498, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12292, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
267 { .Name: 542, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12293, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
268 { .Name: 586, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12294, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
269 { .Name: 630, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12295, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
270 { .Name: 669, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12296, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
271 { .Name: 708, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12297, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
272 { .Name: 4, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12298, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
273 { .Name: 73, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12299, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
274 { .Name: 142, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12300, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
275 { .Name: 197, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12301, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
276 { .Name: 252, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12302, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
277 { .Name: 510, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12303, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
278 { .Name: 554, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12304, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
279 { .Name: 598, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12305, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
280 { .Name: 642, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12306, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
281 { .Name: 681, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12307, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
282 { .Name: 18, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12308, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
283 { .Name: 87, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12309, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
284 { .Name: 156, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12310, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
285 { .Name: 211, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12311, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
286 { .Name: 266, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12312, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
287 { .Name: 524, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12313, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
288 { .Name: 568, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12314, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
289 { .Name: 612, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12315, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
290 { .Name: 656, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12316, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
291 { .Name: 695, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12317, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
292 { .Name: 32, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12318, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
293 { .Name: 101, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12319, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
294 { .Name: 65, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12288, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
295 { .Name: 134, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12289, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
296 { .Name: 189, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12290, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
297 { .Name: 244, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12291, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
298 { .Name: 502, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12292, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
299 { .Name: 546, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12293, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
300 { .Name: 590, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12294, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
301 { .Name: 634, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12295, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
302 { .Name: 673, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12296, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
303 { .Name: 712, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12297, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
304 { .Name: 9, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12298, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
305 { .Name: 78, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12299, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
306 { .Name: 147, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12300, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
307 { .Name: 202, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12301, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
308 { .Name: 257, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12302, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
309 { .Name: 515, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12303, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
310 { .Name: 559, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12304, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
311 { .Name: 603, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12305, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
312 { .Name: 647, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12306, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
313 { .Name: 686, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12307, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
314 { .Name: 23, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12308, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
315 { .Name: 92, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12309, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
316 { .Name: 161, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12310, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
317 { .Name: 216, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12311, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
318 { .Name: 271, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12312, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
319 { .Name: 529, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12313, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
320 { .Name: 573, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12314, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
321 { .Name: 617, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12315, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
322 { .Name: 661, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12316, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
323 { .Name: 700, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12317, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
324 { .Name: 37, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12318, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
325 { .Name: 106, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12319, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
326 { .Name: 297, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12288, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
327 { .Name: 324, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12289, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
328 { .Name: 344, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12290, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
329 { .Name: 364, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12291, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
330 { .Name: 384, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12292, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
331 { .Name: 404, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12293, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
332 { .Name: 424, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12294, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
333 { .Name: 444, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12295, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
334 { .Name: 464, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12296, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
335 { .Name: 484, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12297, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
336 { .Name: 276, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12298, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
337 { .Name: 303, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12299, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
338 { .Name: 330, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12300, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
339 { .Name: 350, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12301, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
340 { .Name: 370, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12302, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
341 { .Name: 390, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12303, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
342 { .Name: 410, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12304, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
343 { .Name: 430, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12305, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
344 { .Name: 450, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12306, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
345 { .Name: 470, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12307, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
346 { .Name: 283, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12308, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
347 { .Name: 310, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12309, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
348 { .Name: 337, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12310, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
349 { .Name: 357, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12311, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
350 { .Name: 377, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12312, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
351 { .Name: 397, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12313, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
352 { .Name: 417, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12314, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
353 { .Name: 437, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12315, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
354 { .Name: 457, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12316, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
355 { .Name: 477, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12317, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
356 { .Name: 290, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12318, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
357 { .Name: 317, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12319, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
358};
359
360extern const MCPhysReg LoongArchRegUnitRoots[][2] = {
361 { LoongArch::F0 },
362 { LoongArch::F1 },
363 { LoongArch::F2 },
364 { LoongArch::F3 },
365 { LoongArch::F4 },
366 { LoongArch::F5 },
367 { LoongArch::F6 },
368 { LoongArch::F7 },
369 { LoongArch::F8 },
370 { LoongArch::F9 },
371 { LoongArch::F10 },
372 { LoongArch::F11 },
373 { LoongArch::F12 },
374 { LoongArch::F13 },
375 { LoongArch::F14 },
376 { LoongArch::F15 },
377 { LoongArch::F16 },
378 { LoongArch::F17 },
379 { LoongArch::F18 },
380 { LoongArch::F19 },
381 { LoongArch::F20 },
382 { LoongArch::F21 },
383 { LoongArch::F22 },
384 { LoongArch::F23 },
385 { LoongArch::F24 },
386 { LoongArch::F25 },
387 { LoongArch::F26 },
388 { LoongArch::F27 },
389 { LoongArch::F28 },
390 { LoongArch::F29 },
391 { LoongArch::F30 },
392 { LoongArch::F31 },
393 { LoongArch::FCC0 },
394 { LoongArch::FCC1 },
395 { LoongArch::FCC2 },
396 { LoongArch::FCC3 },
397 { LoongArch::FCC4 },
398 { LoongArch::FCC5 },
399 { LoongArch::FCC6 },
400 { LoongArch::FCC7 },
401 { LoongArch::FCSR0 },
402 { LoongArch::FCSR1 },
403 { LoongArch::FCSR2 },
404 { LoongArch::FCSR3 },
405 { LoongArch::R0 },
406 { LoongArch::R1 },
407 { LoongArch::R2 },
408 { LoongArch::R3 },
409 { LoongArch::R4 },
410 { LoongArch::R5 },
411 { LoongArch::R6 },
412 { LoongArch::R7 },
413 { LoongArch::R8 },
414 { LoongArch::R9 },
415 { LoongArch::R10 },
416 { LoongArch::R11 },
417 { LoongArch::R12 },
418 { LoongArch::R13 },
419 { LoongArch::R14 },
420 { LoongArch::R15 },
421 { LoongArch::R16 },
422 { LoongArch::R17 },
423 { LoongArch::R18 },
424 { LoongArch::R19 },
425 { LoongArch::R20 },
426 { LoongArch::R21 },
427 { LoongArch::R22 },
428 { LoongArch::R23 },
429 { LoongArch::R24 },
430 { LoongArch::R25 },
431 { LoongArch::R26 },
432 { LoongArch::R27 },
433 { LoongArch::R28 },
434 { LoongArch::R29 },
435 { LoongArch::R30 },
436 { LoongArch::R31 },
437 { LoongArch::SCR0 },
438 { LoongArch::SCR1 },
439 { LoongArch::SCR2 },
440 { LoongArch::SCR3 },
441};
442
443namespace { // Register classes...
444 // FPR32 Register Class...
445 const MCPhysReg FPR32[] = {
446 LoongArch::F0, LoongArch::F1, LoongArch::F2, LoongArch::F3, LoongArch::F4, LoongArch::F5, LoongArch::F6, LoongArch::F7, LoongArch::F8, LoongArch::F9, LoongArch::F10, LoongArch::F11, LoongArch::F12, LoongArch::F13, LoongArch::F14, LoongArch::F15, LoongArch::F16, LoongArch::F17, LoongArch::F18, LoongArch::F19, LoongArch::F20, LoongArch::F21, LoongArch::F22, LoongArch::F23, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31,
447 };
448
449 // FPR32 Bit set.
450 const uint8_t FPR32Bits[] = {
451 0xfe, 0xff, 0xff, 0xff, 0x01,
452 };
453
454 // GPR Register Class...
455 const MCPhysReg GPR[] = {
456 LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R0, LoongArch::R1, LoongArch::R2, LoongArch::R3, LoongArch::R21,
457 };
458
459 // GPR Bit set.
460 const uint8_t GPRBits[] = {
461 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
462 };
463
464 // GPRJR Register Class...
465 const MCPhysReg GPRJR[] = {
466 LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R0, LoongArch::R2, LoongArch::R3, LoongArch::R21,
467 };
468
469 // GPRJR Bit set.
470 const uint8_t GPRJRBits[] = {
471 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f,
472 };
473
474 // GPRNoR0R1 Register Class...
475 const MCPhysReg GPRNoR0R1[] = {
476 LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R2, LoongArch::R3, LoongArch::R21,
477 };
478
479 // GPRNoR0R1 Bit set.
480 const uint8_t GPRNoR0R1Bits[] = {
481 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f,
482 };
483
484 // GPRT Register Class...
485 const MCPhysReg GPRT[] = {
486 LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20,
487 };
488
489 // GPRT Bit set.
490 const uint8_t GPRTBits[] = {
491 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x03,
492 };
493
494 // CFR Register Class...
495 const MCPhysReg CFR[] = {
496 LoongArch::FCC0, LoongArch::FCC1, LoongArch::FCC2, LoongArch::FCC3, LoongArch::FCC4, LoongArch::FCC5, LoongArch::FCC6, LoongArch::FCC7,
497 };
498
499 // CFR Bit set.
500 const uint8_t CFRBits[] = {
501 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
502 };
503
504 // FCSR Register Class...
505 const MCPhysReg FCSR[] = {
506 LoongArch::FCSR0, LoongArch::FCSR1, LoongArch::FCSR2, LoongArch::FCSR3,
507 };
508
509 // FCSR Bit set.
510 const uint8_t FCSRBits[] = {
511 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
512 };
513
514 // SCR Register Class...
515 const MCPhysReg SCR[] = {
516 LoongArch::SCR0, LoongArch::SCR1, LoongArch::SCR2, LoongArch::SCR3,
517 };
518
519 // SCR Bit set.
520 const uint8_t SCRBits[] = {
521 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
522 };
523
524 // FPR64 Register Class...
525 const MCPhysReg FPR64[] = {
526 LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64, LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64, LoongArch::F8_64, LoongArch::F9_64, LoongArch::F10_64, LoongArch::F11_64, LoongArch::F12_64, LoongArch::F13_64, LoongArch::F14_64, LoongArch::F15_64, LoongArch::F16_64, LoongArch::F17_64, LoongArch::F18_64, LoongArch::F19_64, LoongArch::F20_64, LoongArch::F21_64, LoongArch::F22_64, LoongArch::F23_64, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64,
527 };
528
529 // FPR64 Bit set.
530 const uint8_t FPR64Bits[] = {
531 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
532 };
533
534 // LSX128 Register Class...
535 const MCPhysReg LSX128[] = {
536 LoongArch::VR0, LoongArch::VR1, LoongArch::VR2, LoongArch::VR3, LoongArch::VR4, LoongArch::VR5, LoongArch::VR6, LoongArch::VR7, LoongArch::VR8, LoongArch::VR9, LoongArch::VR10, LoongArch::VR11, LoongArch::VR12, LoongArch::VR13, LoongArch::VR14, LoongArch::VR15, LoongArch::VR16, LoongArch::VR17, LoongArch::VR18, LoongArch::VR19, LoongArch::VR20, LoongArch::VR21, LoongArch::VR22, LoongArch::VR23, LoongArch::VR24, LoongArch::VR25, LoongArch::VR26, LoongArch::VR27, LoongArch::VR28, LoongArch::VR29, LoongArch::VR30, LoongArch::VR31,
537 };
538
539 // LSX128 Bit set.
540 const uint8_t LSX128Bits[] = {
541 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
542 };
543
544 // LASX256 Register Class...
545 const MCPhysReg LASX256[] = {
546 LoongArch::XR0, LoongArch::XR1, LoongArch::XR2, LoongArch::XR3, LoongArch::XR4, LoongArch::XR5, LoongArch::XR6, LoongArch::XR7, LoongArch::XR8, LoongArch::XR9, LoongArch::XR10, LoongArch::XR11, LoongArch::XR12, LoongArch::XR13, LoongArch::XR14, LoongArch::XR15, LoongArch::XR16, LoongArch::XR17, LoongArch::XR18, LoongArch::XR19, LoongArch::XR20, LoongArch::XR21, LoongArch::XR22, LoongArch::XR23, LoongArch::XR24, LoongArch::XR25, LoongArch::XR26, LoongArch::XR27, LoongArch::XR28, LoongArch::XR29, LoongArch::XR30, LoongArch::XR31,
547 };
548
549 // LASX256 Bit set.
550 const uint8_t LASX256Bits[] = {
551 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
552 };
553
554} // end anonymous namespace
555
556
557#ifdef __GNUC__
558#pragma GCC diagnostic push
559#pragma GCC diagnostic ignored "-Woverlength-strings"
560#endif
561extern const char LoongArchRegClassStrings[] = {
562 /* 0 */ "GPRNoR0R1\000"
563 /* 10 */ "FPR32\000"
564 /* 16 */ "FPR64\000"
565 /* 22 */ "LASX256\000"
566 /* 30 */ "LSX128\000"
567 /* 37 */ "SCR\000"
568 /* 41 */ "CFR\000"
569 /* 45 */ "GPRJR\000"
570 /* 51 */ "GPR\000"
571 /* 55 */ "FCSR\000"
572 /* 60 */ "GPRT\000"
573};
574#ifdef __GNUC__
575#pragma GCC diagnostic pop
576#endif
577
578extern const MCRegisterClass LoongArchMCRegisterClasses[] = {
579 { .RegsBegin: FPR32, .RegSet: FPR32Bits, .NameIdx: 10, .RegsSize: 32, .RegSetSize: sizeof(FPR32Bits), .ID: LoongArch::FPR32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
580 { .RegsBegin: GPR, .RegSet: GPRBits, .NameIdx: 51, .RegsSize: 32, .RegSetSize: sizeof(GPRBits), .ID: LoongArch::GPRRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
581 { .RegsBegin: GPRJR, .RegSet: GPRJRBits, .NameIdx: 45, .RegsSize: 31, .RegSetSize: sizeof(GPRJRBits), .ID: LoongArch::GPRJRRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
582 { .RegsBegin: GPRNoR0R1, .RegSet: GPRNoR0R1Bits, .NameIdx: 0, .RegsSize: 30, .RegSetSize: sizeof(GPRNoR0R1Bits), .ID: LoongArch::GPRNoR0R1RegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
583 { .RegsBegin: GPRT, .RegSet: GPRTBits, .NameIdx: 60, .RegsSize: 17, .RegSetSize: sizeof(GPRTBits), .ID: LoongArch::GPRTRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
584 { .RegsBegin: CFR, .RegSet: CFRBits, .NameIdx: 41, .RegsSize: 8, .RegSetSize: sizeof(CFRBits), .ID: LoongArch::CFRRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
585 { .RegsBegin: FCSR, .RegSet: FCSRBits, .NameIdx: 55, .RegsSize: 4, .RegSetSize: sizeof(FCSRBits), .ID: LoongArch::FCSRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
586 { .RegsBegin: SCR, .RegSet: SCRBits, .NameIdx: 37, .RegsSize: 4, .RegSetSize: sizeof(SCRBits), .ID: LoongArch::SCRRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
587 { .RegsBegin: FPR64, .RegSet: FPR64Bits, .NameIdx: 16, .RegsSize: 32, .RegSetSize: sizeof(FPR64Bits), .ID: LoongArch::FPR64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
588 { .RegsBegin: LSX128, .RegSet: LSX128Bits, .NameIdx: 30, .RegsSize: 32, .RegSetSize: sizeof(LSX128Bits), .ID: LoongArch::LSX128RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
589 { .RegsBegin: LASX256, .RegSet: LASX256Bits, .NameIdx: 22, .RegsSize: 32, .RegSetSize: sizeof(LASX256Bits), .ID: LoongArch::LASX256RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
590};
591
592// LoongArch Dwarf<->LLVM register mappings.
593extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[] = {
594 { .FromReg: 0U, .ToReg: LoongArch::R0 },
595 { .FromReg: 1U, .ToReg: LoongArch::R1 },
596 { .FromReg: 2U, .ToReg: LoongArch::R2 },
597 { .FromReg: 3U, .ToReg: LoongArch::R3 },
598 { .FromReg: 4U, .ToReg: LoongArch::R4 },
599 { .FromReg: 5U, .ToReg: LoongArch::R5 },
600 { .FromReg: 6U, .ToReg: LoongArch::R6 },
601 { .FromReg: 7U, .ToReg: LoongArch::R7 },
602 { .FromReg: 8U, .ToReg: LoongArch::R8 },
603 { .FromReg: 9U, .ToReg: LoongArch::R9 },
604 { .FromReg: 10U, .ToReg: LoongArch::R10 },
605 { .FromReg: 11U, .ToReg: LoongArch::R11 },
606 { .FromReg: 12U, .ToReg: LoongArch::R12 },
607 { .FromReg: 13U, .ToReg: LoongArch::R13 },
608 { .FromReg: 14U, .ToReg: LoongArch::R14 },
609 { .FromReg: 15U, .ToReg: LoongArch::R15 },
610 { .FromReg: 16U, .ToReg: LoongArch::R16 },
611 { .FromReg: 17U, .ToReg: LoongArch::R17 },
612 { .FromReg: 18U, .ToReg: LoongArch::R18 },
613 { .FromReg: 19U, .ToReg: LoongArch::R19 },
614 { .FromReg: 20U, .ToReg: LoongArch::R20 },
615 { .FromReg: 21U, .ToReg: LoongArch::R21 },
616 { .FromReg: 22U, .ToReg: LoongArch::R22 },
617 { .FromReg: 23U, .ToReg: LoongArch::R23 },
618 { .FromReg: 24U, .ToReg: LoongArch::R24 },
619 { .FromReg: 25U, .ToReg: LoongArch::R25 },
620 { .FromReg: 26U, .ToReg: LoongArch::R26 },
621 { .FromReg: 27U, .ToReg: LoongArch::R27 },
622 { .FromReg: 28U, .ToReg: LoongArch::R28 },
623 { .FromReg: 29U, .ToReg: LoongArch::R29 },
624 { .FromReg: 30U, .ToReg: LoongArch::R30 },
625 { .FromReg: 31U, .ToReg: LoongArch::R31 },
626 { .FromReg: 32U, .ToReg: LoongArch::F0_64 },
627 { .FromReg: 33U, .ToReg: LoongArch::F1_64 },
628 { .FromReg: 34U, .ToReg: LoongArch::F2_64 },
629 { .FromReg: 35U, .ToReg: LoongArch::F3_64 },
630 { .FromReg: 36U, .ToReg: LoongArch::F4_64 },
631 { .FromReg: 37U, .ToReg: LoongArch::F5_64 },
632 { .FromReg: 38U, .ToReg: LoongArch::F6_64 },
633 { .FromReg: 39U, .ToReg: LoongArch::F7_64 },
634 { .FromReg: 40U, .ToReg: LoongArch::F8_64 },
635 { .FromReg: 41U, .ToReg: LoongArch::F9_64 },
636 { .FromReg: 42U, .ToReg: LoongArch::F10_64 },
637 { .FromReg: 43U, .ToReg: LoongArch::F11_64 },
638 { .FromReg: 44U, .ToReg: LoongArch::F12_64 },
639 { .FromReg: 45U, .ToReg: LoongArch::F13_64 },
640 { .FromReg: 46U, .ToReg: LoongArch::F14_64 },
641 { .FromReg: 47U, .ToReg: LoongArch::F15_64 },
642 { .FromReg: 48U, .ToReg: LoongArch::F16_64 },
643 { .FromReg: 49U, .ToReg: LoongArch::F17_64 },
644 { .FromReg: 50U, .ToReg: LoongArch::F18_64 },
645 { .FromReg: 51U, .ToReg: LoongArch::F19_64 },
646 { .FromReg: 52U, .ToReg: LoongArch::F20_64 },
647 { .FromReg: 53U, .ToReg: LoongArch::F21_64 },
648 { .FromReg: 54U, .ToReg: LoongArch::F22_64 },
649 { .FromReg: 55U, .ToReg: LoongArch::F23_64 },
650 { .FromReg: 56U, .ToReg: LoongArch::F24_64 },
651 { .FromReg: 57U, .ToReg: LoongArch::F25_64 },
652 { .FromReg: 58U, .ToReg: LoongArch::F26_64 },
653 { .FromReg: 59U, .ToReg: LoongArch::F27_64 },
654 { .FromReg: 60U, .ToReg: LoongArch::F28_64 },
655 { .FromReg: 61U, .ToReg: LoongArch::F29_64 },
656 { .FromReg: 62U, .ToReg: LoongArch::F30_64 },
657 { .FromReg: 63U, .ToReg: LoongArch::F31_64 },
658};
659extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize = std::size(LoongArchDwarfFlavour0Dwarf2L);
660
661extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[] = {
662 { .FromReg: 0U, .ToReg: LoongArch::R0 },
663 { .FromReg: 1U, .ToReg: LoongArch::R1 },
664 { .FromReg: 2U, .ToReg: LoongArch::R2 },
665 { .FromReg: 3U, .ToReg: LoongArch::R3 },
666 { .FromReg: 4U, .ToReg: LoongArch::R4 },
667 { .FromReg: 5U, .ToReg: LoongArch::R5 },
668 { .FromReg: 6U, .ToReg: LoongArch::R6 },
669 { .FromReg: 7U, .ToReg: LoongArch::R7 },
670 { .FromReg: 8U, .ToReg: LoongArch::R8 },
671 { .FromReg: 9U, .ToReg: LoongArch::R9 },
672 { .FromReg: 10U, .ToReg: LoongArch::R10 },
673 { .FromReg: 11U, .ToReg: LoongArch::R11 },
674 { .FromReg: 12U, .ToReg: LoongArch::R12 },
675 { .FromReg: 13U, .ToReg: LoongArch::R13 },
676 { .FromReg: 14U, .ToReg: LoongArch::R14 },
677 { .FromReg: 15U, .ToReg: LoongArch::R15 },
678 { .FromReg: 16U, .ToReg: LoongArch::R16 },
679 { .FromReg: 17U, .ToReg: LoongArch::R17 },
680 { .FromReg: 18U, .ToReg: LoongArch::R18 },
681 { .FromReg: 19U, .ToReg: LoongArch::R19 },
682 { .FromReg: 20U, .ToReg: LoongArch::R20 },
683 { .FromReg: 21U, .ToReg: LoongArch::R21 },
684 { .FromReg: 22U, .ToReg: LoongArch::R22 },
685 { .FromReg: 23U, .ToReg: LoongArch::R23 },
686 { .FromReg: 24U, .ToReg: LoongArch::R24 },
687 { .FromReg: 25U, .ToReg: LoongArch::R25 },
688 { .FromReg: 26U, .ToReg: LoongArch::R26 },
689 { .FromReg: 27U, .ToReg: LoongArch::R27 },
690 { .FromReg: 28U, .ToReg: LoongArch::R28 },
691 { .FromReg: 29U, .ToReg: LoongArch::R29 },
692 { .FromReg: 30U, .ToReg: LoongArch::R30 },
693 { .FromReg: 31U, .ToReg: LoongArch::R31 },
694 { .FromReg: 32U, .ToReg: LoongArch::F0_64 },
695 { .FromReg: 33U, .ToReg: LoongArch::F1_64 },
696 { .FromReg: 34U, .ToReg: LoongArch::F2_64 },
697 { .FromReg: 35U, .ToReg: LoongArch::F3_64 },
698 { .FromReg: 36U, .ToReg: LoongArch::F4_64 },
699 { .FromReg: 37U, .ToReg: LoongArch::F5_64 },
700 { .FromReg: 38U, .ToReg: LoongArch::F6_64 },
701 { .FromReg: 39U, .ToReg: LoongArch::F7_64 },
702 { .FromReg: 40U, .ToReg: LoongArch::F8_64 },
703 { .FromReg: 41U, .ToReg: LoongArch::F9_64 },
704 { .FromReg: 42U, .ToReg: LoongArch::F10_64 },
705 { .FromReg: 43U, .ToReg: LoongArch::F11_64 },
706 { .FromReg: 44U, .ToReg: LoongArch::F12_64 },
707 { .FromReg: 45U, .ToReg: LoongArch::F13_64 },
708 { .FromReg: 46U, .ToReg: LoongArch::F14_64 },
709 { .FromReg: 47U, .ToReg: LoongArch::F15_64 },
710 { .FromReg: 48U, .ToReg: LoongArch::F16_64 },
711 { .FromReg: 49U, .ToReg: LoongArch::F17_64 },
712 { .FromReg: 50U, .ToReg: LoongArch::F18_64 },
713 { .FromReg: 51U, .ToReg: LoongArch::F19_64 },
714 { .FromReg: 52U, .ToReg: LoongArch::F20_64 },
715 { .FromReg: 53U, .ToReg: LoongArch::F21_64 },
716 { .FromReg: 54U, .ToReg: LoongArch::F22_64 },
717 { .FromReg: 55U, .ToReg: LoongArch::F23_64 },
718 { .FromReg: 56U, .ToReg: LoongArch::F24_64 },
719 { .FromReg: 57U, .ToReg: LoongArch::F25_64 },
720 { .FromReg: 58U, .ToReg: LoongArch::F26_64 },
721 { .FromReg: 59U, .ToReg: LoongArch::F27_64 },
722 { .FromReg: 60U, .ToReg: LoongArch::F28_64 },
723 { .FromReg: 61U, .ToReg: LoongArch::F29_64 },
724 { .FromReg: 62U, .ToReg: LoongArch::F30_64 },
725 { .FromReg: 63U, .ToReg: LoongArch::F31_64 },
726};
727extern const unsigned LoongArchEHFlavour0Dwarf2LSize = std::size(LoongArchEHFlavour0Dwarf2L);
728
729extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[] = {
730 { .FromReg: LoongArch::F0, .ToReg: 32U },
731 { .FromReg: LoongArch::F1, .ToReg: 33U },
732 { .FromReg: LoongArch::F2, .ToReg: 34U },
733 { .FromReg: LoongArch::F3, .ToReg: 35U },
734 { .FromReg: LoongArch::F4, .ToReg: 36U },
735 { .FromReg: LoongArch::F5, .ToReg: 37U },
736 { .FromReg: LoongArch::F6, .ToReg: 38U },
737 { .FromReg: LoongArch::F7, .ToReg: 39U },
738 { .FromReg: LoongArch::F8, .ToReg: 40U },
739 { .FromReg: LoongArch::F9, .ToReg: 41U },
740 { .FromReg: LoongArch::F10, .ToReg: 42U },
741 { .FromReg: LoongArch::F11, .ToReg: 43U },
742 { .FromReg: LoongArch::F12, .ToReg: 44U },
743 { .FromReg: LoongArch::F13, .ToReg: 45U },
744 { .FromReg: LoongArch::F14, .ToReg: 46U },
745 { .FromReg: LoongArch::F15, .ToReg: 47U },
746 { .FromReg: LoongArch::F16, .ToReg: 48U },
747 { .FromReg: LoongArch::F17, .ToReg: 49U },
748 { .FromReg: LoongArch::F18, .ToReg: 50U },
749 { .FromReg: LoongArch::F19, .ToReg: 51U },
750 { .FromReg: LoongArch::F20, .ToReg: 52U },
751 { .FromReg: LoongArch::F21, .ToReg: 53U },
752 { .FromReg: LoongArch::F22, .ToReg: 54U },
753 { .FromReg: LoongArch::F23, .ToReg: 55U },
754 { .FromReg: LoongArch::F24, .ToReg: 56U },
755 { .FromReg: LoongArch::F25, .ToReg: 57U },
756 { .FromReg: LoongArch::F26, .ToReg: 58U },
757 { .FromReg: LoongArch::F27, .ToReg: 59U },
758 { .FromReg: LoongArch::F28, .ToReg: 60U },
759 { .FromReg: LoongArch::F29, .ToReg: 61U },
760 { .FromReg: LoongArch::F30, .ToReg: 62U },
761 { .FromReg: LoongArch::F31, .ToReg: 63U },
762 { .FromReg: LoongArch::R0, .ToReg: 0U },
763 { .FromReg: LoongArch::R1, .ToReg: 1U },
764 { .FromReg: LoongArch::R2, .ToReg: 2U },
765 { .FromReg: LoongArch::R3, .ToReg: 3U },
766 { .FromReg: LoongArch::R4, .ToReg: 4U },
767 { .FromReg: LoongArch::R5, .ToReg: 5U },
768 { .FromReg: LoongArch::R6, .ToReg: 6U },
769 { .FromReg: LoongArch::R7, .ToReg: 7U },
770 { .FromReg: LoongArch::R8, .ToReg: 8U },
771 { .FromReg: LoongArch::R9, .ToReg: 9U },
772 { .FromReg: LoongArch::R10, .ToReg: 10U },
773 { .FromReg: LoongArch::R11, .ToReg: 11U },
774 { .FromReg: LoongArch::R12, .ToReg: 12U },
775 { .FromReg: LoongArch::R13, .ToReg: 13U },
776 { .FromReg: LoongArch::R14, .ToReg: 14U },
777 { .FromReg: LoongArch::R15, .ToReg: 15U },
778 { .FromReg: LoongArch::R16, .ToReg: 16U },
779 { .FromReg: LoongArch::R17, .ToReg: 17U },
780 { .FromReg: LoongArch::R18, .ToReg: 18U },
781 { .FromReg: LoongArch::R19, .ToReg: 19U },
782 { .FromReg: LoongArch::R20, .ToReg: 20U },
783 { .FromReg: LoongArch::R21, .ToReg: 21U },
784 { .FromReg: LoongArch::R22, .ToReg: 22U },
785 { .FromReg: LoongArch::R23, .ToReg: 23U },
786 { .FromReg: LoongArch::R24, .ToReg: 24U },
787 { .FromReg: LoongArch::R25, .ToReg: 25U },
788 { .FromReg: LoongArch::R26, .ToReg: 26U },
789 { .FromReg: LoongArch::R27, .ToReg: 27U },
790 { .FromReg: LoongArch::R28, .ToReg: 28U },
791 { .FromReg: LoongArch::R29, .ToReg: 29U },
792 { .FromReg: LoongArch::R30, .ToReg: 30U },
793 { .FromReg: LoongArch::R31, .ToReg: 31U },
794 { .FromReg: LoongArch::VR0, .ToReg: 32U },
795 { .FromReg: LoongArch::VR1, .ToReg: 33U },
796 { .FromReg: LoongArch::VR2, .ToReg: 34U },
797 { .FromReg: LoongArch::VR3, .ToReg: 35U },
798 { .FromReg: LoongArch::VR4, .ToReg: 36U },
799 { .FromReg: LoongArch::VR5, .ToReg: 37U },
800 { .FromReg: LoongArch::VR6, .ToReg: 38U },
801 { .FromReg: LoongArch::VR7, .ToReg: 39U },
802 { .FromReg: LoongArch::VR8, .ToReg: 40U },
803 { .FromReg: LoongArch::VR9, .ToReg: 41U },
804 { .FromReg: LoongArch::VR10, .ToReg: 42U },
805 { .FromReg: LoongArch::VR11, .ToReg: 43U },
806 { .FromReg: LoongArch::VR12, .ToReg: 44U },
807 { .FromReg: LoongArch::VR13, .ToReg: 45U },
808 { .FromReg: LoongArch::VR14, .ToReg: 46U },
809 { .FromReg: LoongArch::VR15, .ToReg: 47U },
810 { .FromReg: LoongArch::VR16, .ToReg: 48U },
811 { .FromReg: LoongArch::VR17, .ToReg: 49U },
812 { .FromReg: LoongArch::VR18, .ToReg: 50U },
813 { .FromReg: LoongArch::VR19, .ToReg: 51U },
814 { .FromReg: LoongArch::VR20, .ToReg: 52U },
815 { .FromReg: LoongArch::VR21, .ToReg: 53U },
816 { .FromReg: LoongArch::VR22, .ToReg: 54U },
817 { .FromReg: LoongArch::VR23, .ToReg: 55U },
818 { .FromReg: LoongArch::VR24, .ToReg: 56U },
819 { .FromReg: LoongArch::VR25, .ToReg: 57U },
820 { .FromReg: LoongArch::VR26, .ToReg: 58U },
821 { .FromReg: LoongArch::VR27, .ToReg: 59U },
822 { .FromReg: LoongArch::VR28, .ToReg: 60U },
823 { .FromReg: LoongArch::VR29, .ToReg: 61U },
824 { .FromReg: LoongArch::VR30, .ToReg: 62U },
825 { .FromReg: LoongArch::VR31, .ToReg: 63U },
826 { .FromReg: LoongArch::XR0, .ToReg: 32U },
827 { .FromReg: LoongArch::XR1, .ToReg: 33U },
828 { .FromReg: LoongArch::XR2, .ToReg: 34U },
829 { .FromReg: LoongArch::XR3, .ToReg: 35U },
830 { .FromReg: LoongArch::XR4, .ToReg: 36U },
831 { .FromReg: LoongArch::XR5, .ToReg: 37U },
832 { .FromReg: LoongArch::XR6, .ToReg: 38U },
833 { .FromReg: LoongArch::XR7, .ToReg: 39U },
834 { .FromReg: LoongArch::XR8, .ToReg: 40U },
835 { .FromReg: LoongArch::XR9, .ToReg: 41U },
836 { .FromReg: LoongArch::XR10, .ToReg: 42U },
837 { .FromReg: LoongArch::XR11, .ToReg: 43U },
838 { .FromReg: LoongArch::XR12, .ToReg: 44U },
839 { .FromReg: LoongArch::XR13, .ToReg: 45U },
840 { .FromReg: LoongArch::XR14, .ToReg: 46U },
841 { .FromReg: LoongArch::XR15, .ToReg: 47U },
842 { .FromReg: LoongArch::XR16, .ToReg: 48U },
843 { .FromReg: LoongArch::XR17, .ToReg: 49U },
844 { .FromReg: LoongArch::XR18, .ToReg: 50U },
845 { .FromReg: LoongArch::XR19, .ToReg: 51U },
846 { .FromReg: LoongArch::XR20, .ToReg: 52U },
847 { .FromReg: LoongArch::XR21, .ToReg: 53U },
848 { .FromReg: LoongArch::XR22, .ToReg: 54U },
849 { .FromReg: LoongArch::XR23, .ToReg: 55U },
850 { .FromReg: LoongArch::XR24, .ToReg: 56U },
851 { .FromReg: LoongArch::XR25, .ToReg: 57U },
852 { .FromReg: LoongArch::XR26, .ToReg: 58U },
853 { .FromReg: LoongArch::XR27, .ToReg: 59U },
854 { .FromReg: LoongArch::XR28, .ToReg: 60U },
855 { .FromReg: LoongArch::XR29, .ToReg: 61U },
856 { .FromReg: LoongArch::XR30, .ToReg: 62U },
857 { .FromReg: LoongArch::XR31, .ToReg: 63U },
858 { .FromReg: LoongArch::F0_64, .ToReg: 32U },
859 { .FromReg: LoongArch::F1_64, .ToReg: 33U },
860 { .FromReg: LoongArch::F2_64, .ToReg: 34U },
861 { .FromReg: LoongArch::F3_64, .ToReg: 35U },
862 { .FromReg: LoongArch::F4_64, .ToReg: 36U },
863 { .FromReg: LoongArch::F5_64, .ToReg: 37U },
864 { .FromReg: LoongArch::F6_64, .ToReg: 38U },
865 { .FromReg: LoongArch::F7_64, .ToReg: 39U },
866 { .FromReg: LoongArch::F8_64, .ToReg: 40U },
867 { .FromReg: LoongArch::F9_64, .ToReg: 41U },
868 { .FromReg: LoongArch::F10_64, .ToReg: 42U },
869 { .FromReg: LoongArch::F11_64, .ToReg: 43U },
870 { .FromReg: LoongArch::F12_64, .ToReg: 44U },
871 { .FromReg: LoongArch::F13_64, .ToReg: 45U },
872 { .FromReg: LoongArch::F14_64, .ToReg: 46U },
873 { .FromReg: LoongArch::F15_64, .ToReg: 47U },
874 { .FromReg: LoongArch::F16_64, .ToReg: 48U },
875 { .FromReg: LoongArch::F17_64, .ToReg: 49U },
876 { .FromReg: LoongArch::F18_64, .ToReg: 50U },
877 { .FromReg: LoongArch::F19_64, .ToReg: 51U },
878 { .FromReg: LoongArch::F20_64, .ToReg: 52U },
879 { .FromReg: LoongArch::F21_64, .ToReg: 53U },
880 { .FromReg: LoongArch::F22_64, .ToReg: 54U },
881 { .FromReg: LoongArch::F23_64, .ToReg: 55U },
882 { .FromReg: LoongArch::F24_64, .ToReg: 56U },
883 { .FromReg: LoongArch::F25_64, .ToReg: 57U },
884 { .FromReg: LoongArch::F26_64, .ToReg: 58U },
885 { .FromReg: LoongArch::F27_64, .ToReg: 59U },
886 { .FromReg: LoongArch::F28_64, .ToReg: 60U },
887 { .FromReg: LoongArch::F29_64, .ToReg: 61U },
888 { .FromReg: LoongArch::F30_64, .ToReg: 62U },
889 { .FromReg: LoongArch::F31_64, .ToReg: 63U },
890};
891extern const unsigned LoongArchDwarfFlavour0L2DwarfSize = std::size(LoongArchDwarfFlavour0L2Dwarf);
892
893extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[] = {
894 { .FromReg: LoongArch::F0, .ToReg: 32U },
895 { .FromReg: LoongArch::F1, .ToReg: 33U },
896 { .FromReg: LoongArch::F2, .ToReg: 34U },
897 { .FromReg: LoongArch::F3, .ToReg: 35U },
898 { .FromReg: LoongArch::F4, .ToReg: 36U },
899 { .FromReg: LoongArch::F5, .ToReg: 37U },
900 { .FromReg: LoongArch::F6, .ToReg: 38U },
901 { .FromReg: LoongArch::F7, .ToReg: 39U },
902 { .FromReg: LoongArch::F8, .ToReg: 40U },
903 { .FromReg: LoongArch::F9, .ToReg: 41U },
904 { .FromReg: LoongArch::F10, .ToReg: 42U },
905 { .FromReg: LoongArch::F11, .ToReg: 43U },
906 { .FromReg: LoongArch::F12, .ToReg: 44U },
907 { .FromReg: LoongArch::F13, .ToReg: 45U },
908 { .FromReg: LoongArch::F14, .ToReg: 46U },
909 { .FromReg: LoongArch::F15, .ToReg: 47U },
910 { .FromReg: LoongArch::F16, .ToReg: 48U },
911 { .FromReg: LoongArch::F17, .ToReg: 49U },
912 { .FromReg: LoongArch::F18, .ToReg: 50U },
913 { .FromReg: LoongArch::F19, .ToReg: 51U },
914 { .FromReg: LoongArch::F20, .ToReg: 52U },
915 { .FromReg: LoongArch::F21, .ToReg: 53U },
916 { .FromReg: LoongArch::F22, .ToReg: 54U },
917 { .FromReg: LoongArch::F23, .ToReg: 55U },
918 { .FromReg: LoongArch::F24, .ToReg: 56U },
919 { .FromReg: LoongArch::F25, .ToReg: 57U },
920 { .FromReg: LoongArch::F26, .ToReg: 58U },
921 { .FromReg: LoongArch::F27, .ToReg: 59U },
922 { .FromReg: LoongArch::F28, .ToReg: 60U },
923 { .FromReg: LoongArch::F29, .ToReg: 61U },
924 { .FromReg: LoongArch::F30, .ToReg: 62U },
925 { .FromReg: LoongArch::F31, .ToReg: 63U },
926 { .FromReg: LoongArch::R0, .ToReg: 0U },
927 { .FromReg: LoongArch::R1, .ToReg: 1U },
928 { .FromReg: LoongArch::R2, .ToReg: 2U },
929 { .FromReg: LoongArch::R3, .ToReg: 3U },
930 { .FromReg: LoongArch::R4, .ToReg: 4U },
931 { .FromReg: LoongArch::R5, .ToReg: 5U },
932 { .FromReg: LoongArch::R6, .ToReg: 6U },
933 { .FromReg: LoongArch::R7, .ToReg: 7U },
934 { .FromReg: LoongArch::R8, .ToReg: 8U },
935 { .FromReg: LoongArch::R9, .ToReg: 9U },
936 { .FromReg: LoongArch::R10, .ToReg: 10U },
937 { .FromReg: LoongArch::R11, .ToReg: 11U },
938 { .FromReg: LoongArch::R12, .ToReg: 12U },
939 { .FromReg: LoongArch::R13, .ToReg: 13U },
940 { .FromReg: LoongArch::R14, .ToReg: 14U },
941 { .FromReg: LoongArch::R15, .ToReg: 15U },
942 { .FromReg: LoongArch::R16, .ToReg: 16U },
943 { .FromReg: LoongArch::R17, .ToReg: 17U },
944 { .FromReg: LoongArch::R18, .ToReg: 18U },
945 { .FromReg: LoongArch::R19, .ToReg: 19U },
946 { .FromReg: LoongArch::R20, .ToReg: 20U },
947 { .FromReg: LoongArch::R21, .ToReg: 21U },
948 { .FromReg: LoongArch::R22, .ToReg: 22U },
949 { .FromReg: LoongArch::R23, .ToReg: 23U },
950 { .FromReg: LoongArch::R24, .ToReg: 24U },
951 { .FromReg: LoongArch::R25, .ToReg: 25U },
952 { .FromReg: LoongArch::R26, .ToReg: 26U },
953 { .FromReg: LoongArch::R27, .ToReg: 27U },
954 { .FromReg: LoongArch::R28, .ToReg: 28U },
955 { .FromReg: LoongArch::R29, .ToReg: 29U },
956 { .FromReg: LoongArch::R30, .ToReg: 30U },
957 { .FromReg: LoongArch::R31, .ToReg: 31U },
958 { .FromReg: LoongArch::VR0, .ToReg: 32U },
959 { .FromReg: LoongArch::VR1, .ToReg: 33U },
960 { .FromReg: LoongArch::VR2, .ToReg: 34U },
961 { .FromReg: LoongArch::VR3, .ToReg: 35U },
962 { .FromReg: LoongArch::VR4, .ToReg: 36U },
963 { .FromReg: LoongArch::VR5, .ToReg: 37U },
964 { .FromReg: LoongArch::VR6, .ToReg: 38U },
965 { .FromReg: LoongArch::VR7, .ToReg: 39U },
966 { .FromReg: LoongArch::VR8, .ToReg: 40U },
967 { .FromReg: LoongArch::VR9, .ToReg: 41U },
968 { .FromReg: LoongArch::VR10, .ToReg: 42U },
969 { .FromReg: LoongArch::VR11, .ToReg: 43U },
970 { .FromReg: LoongArch::VR12, .ToReg: 44U },
971 { .FromReg: LoongArch::VR13, .ToReg: 45U },
972 { .FromReg: LoongArch::VR14, .ToReg: 46U },
973 { .FromReg: LoongArch::VR15, .ToReg: 47U },
974 { .FromReg: LoongArch::VR16, .ToReg: 48U },
975 { .FromReg: LoongArch::VR17, .ToReg: 49U },
976 { .FromReg: LoongArch::VR18, .ToReg: 50U },
977 { .FromReg: LoongArch::VR19, .ToReg: 51U },
978 { .FromReg: LoongArch::VR20, .ToReg: 52U },
979 { .FromReg: LoongArch::VR21, .ToReg: 53U },
980 { .FromReg: LoongArch::VR22, .ToReg: 54U },
981 { .FromReg: LoongArch::VR23, .ToReg: 55U },
982 { .FromReg: LoongArch::VR24, .ToReg: 56U },
983 { .FromReg: LoongArch::VR25, .ToReg: 57U },
984 { .FromReg: LoongArch::VR26, .ToReg: 58U },
985 { .FromReg: LoongArch::VR27, .ToReg: 59U },
986 { .FromReg: LoongArch::VR28, .ToReg: 60U },
987 { .FromReg: LoongArch::VR29, .ToReg: 61U },
988 { .FromReg: LoongArch::VR30, .ToReg: 62U },
989 { .FromReg: LoongArch::VR31, .ToReg: 63U },
990 { .FromReg: LoongArch::XR0, .ToReg: 32U },
991 { .FromReg: LoongArch::XR1, .ToReg: 33U },
992 { .FromReg: LoongArch::XR2, .ToReg: 34U },
993 { .FromReg: LoongArch::XR3, .ToReg: 35U },
994 { .FromReg: LoongArch::XR4, .ToReg: 36U },
995 { .FromReg: LoongArch::XR5, .ToReg: 37U },
996 { .FromReg: LoongArch::XR6, .ToReg: 38U },
997 { .FromReg: LoongArch::XR7, .ToReg: 39U },
998 { .FromReg: LoongArch::XR8, .ToReg: 40U },
999 { .FromReg: LoongArch::XR9, .ToReg: 41U },
1000 { .FromReg: LoongArch::XR10, .ToReg: 42U },
1001 { .FromReg: LoongArch::XR11, .ToReg: 43U },
1002 { .FromReg: LoongArch::XR12, .ToReg: 44U },
1003 { .FromReg: LoongArch::XR13, .ToReg: 45U },
1004 { .FromReg: LoongArch::XR14, .ToReg: 46U },
1005 { .FromReg: LoongArch::XR15, .ToReg: 47U },
1006 { .FromReg: LoongArch::XR16, .ToReg: 48U },
1007 { .FromReg: LoongArch::XR17, .ToReg: 49U },
1008 { .FromReg: LoongArch::XR18, .ToReg: 50U },
1009 { .FromReg: LoongArch::XR19, .ToReg: 51U },
1010 { .FromReg: LoongArch::XR20, .ToReg: 52U },
1011 { .FromReg: LoongArch::XR21, .ToReg: 53U },
1012 { .FromReg: LoongArch::XR22, .ToReg: 54U },
1013 { .FromReg: LoongArch::XR23, .ToReg: 55U },
1014 { .FromReg: LoongArch::XR24, .ToReg: 56U },
1015 { .FromReg: LoongArch::XR25, .ToReg: 57U },
1016 { .FromReg: LoongArch::XR26, .ToReg: 58U },
1017 { .FromReg: LoongArch::XR27, .ToReg: 59U },
1018 { .FromReg: LoongArch::XR28, .ToReg: 60U },
1019 { .FromReg: LoongArch::XR29, .ToReg: 61U },
1020 { .FromReg: LoongArch::XR30, .ToReg: 62U },
1021 { .FromReg: LoongArch::XR31, .ToReg: 63U },
1022 { .FromReg: LoongArch::F0_64, .ToReg: 32U },
1023 { .FromReg: LoongArch::F1_64, .ToReg: 33U },
1024 { .FromReg: LoongArch::F2_64, .ToReg: 34U },
1025 { .FromReg: LoongArch::F3_64, .ToReg: 35U },
1026 { .FromReg: LoongArch::F4_64, .ToReg: 36U },
1027 { .FromReg: LoongArch::F5_64, .ToReg: 37U },
1028 { .FromReg: LoongArch::F6_64, .ToReg: 38U },
1029 { .FromReg: LoongArch::F7_64, .ToReg: 39U },
1030 { .FromReg: LoongArch::F8_64, .ToReg: 40U },
1031 { .FromReg: LoongArch::F9_64, .ToReg: 41U },
1032 { .FromReg: LoongArch::F10_64, .ToReg: 42U },
1033 { .FromReg: LoongArch::F11_64, .ToReg: 43U },
1034 { .FromReg: LoongArch::F12_64, .ToReg: 44U },
1035 { .FromReg: LoongArch::F13_64, .ToReg: 45U },
1036 { .FromReg: LoongArch::F14_64, .ToReg: 46U },
1037 { .FromReg: LoongArch::F15_64, .ToReg: 47U },
1038 { .FromReg: LoongArch::F16_64, .ToReg: 48U },
1039 { .FromReg: LoongArch::F17_64, .ToReg: 49U },
1040 { .FromReg: LoongArch::F18_64, .ToReg: 50U },
1041 { .FromReg: LoongArch::F19_64, .ToReg: 51U },
1042 { .FromReg: LoongArch::F20_64, .ToReg: 52U },
1043 { .FromReg: LoongArch::F21_64, .ToReg: 53U },
1044 { .FromReg: LoongArch::F22_64, .ToReg: 54U },
1045 { .FromReg: LoongArch::F23_64, .ToReg: 55U },
1046 { .FromReg: LoongArch::F24_64, .ToReg: 56U },
1047 { .FromReg: LoongArch::F25_64, .ToReg: 57U },
1048 { .FromReg: LoongArch::F26_64, .ToReg: 58U },
1049 { .FromReg: LoongArch::F27_64, .ToReg: 59U },
1050 { .FromReg: LoongArch::F28_64, .ToReg: 60U },
1051 { .FromReg: LoongArch::F29_64, .ToReg: 61U },
1052 { .FromReg: LoongArch::F30_64, .ToReg: 62U },
1053 { .FromReg: LoongArch::F31_64, .ToReg: 63U },
1054};
1055extern const unsigned LoongArchEHFlavour0L2DwarfSize = std::size(LoongArchEHFlavour0L2Dwarf);
1056
1057extern const uint16_t LoongArchRegEncodingTable[] = {
1058 0,
1059 0,
1060 1,
1061 2,
1062 3,
1063 4,
1064 5,
1065 6,
1066 7,
1067 8,
1068 9,
1069 10,
1070 11,
1071 12,
1072 13,
1073 14,
1074 15,
1075 16,
1076 17,
1077 18,
1078 19,
1079 20,
1080 21,
1081 22,
1082 23,
1083 24,
1084 25,
1085 26,
1086 27,
1087 28,
1088 29,
1089 30,
1090 31,
1091 0,
1092 1,
1093 2,
1094 3,
1095 4,
1096 5,
1097 6,
1098 7,
1099 0,
1100 1,
1101 2,
1102 3,
1103 0,
1104 1,
1105 2,
1106 3,
1107 4,
1108 5,
1109 6,
1110 7,
1111 8,
1112 9,
1113 10,
1114 11,
1115 12,
1116 13,
1117 14,
1118 15,
1119 16,
1120 17,
1121 18,
1122 19,
1123 20,
1124 21,
1125 22,
1126 23,
1127 24,
1128 25,
1129 26,
1130 27,
1131 28,
1132 29,
1133 30,
1134 31,
1135 0,
1136 1,
1137 2,
1138 3,
1139 0,
1140 1,
1141 2,
1142 3,
1143 4,
1144 5,
1145 6,
1146 7,
1147 8,
1148 9,
1149 10,
1150 11,
1151 12,
1152 13,
1153 14,
1154 15,
1155 16,
1156 17,
1157 18,
1158 19,
1159 20,
1160 21,
1161 22,
1162 23,
1163 24,
1164 25,
1165 26,
1166 27,
1167 28,
1168 29,
1169 30,
1170 31,
1171 0,
1172 1,
1173 2,
1174 3,
1175 4,
1176 5,
1177 6,
1178 7,
1179 8,
1180 9,
1181 10,
1182 11,
1183 12,
1184 13,
1185 14,
1186 15,
1187 16,
1188 17,
1189 18,
1190 19,
1191 20,
1192 21,
1193 22,
1194 23,
1195 24,
1196 25,
1197 26,
1198 27,
1199 28,
1200 29,
1201 30,
1202 31,
1203 0,
1204 1,
1205 2,
1206 3,
1207 4,
1208 5,
1209 6,
1210 7,
1211 8,
1212 9,
1213 10,
1214 11,
1215 12,
1216 13,
1217 14,
1218 15,
1219 16,
1220 17,
1221 18,
1222 19,
1223 20,
1224 21,
1225 22,
1226 23,
1227 24,
1228 25,
1229 26,
1230 27,
1231 28,
1232 29,
1233 30,
1234 31,
1235};
1236static inline void InitLoongArchMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1237 RI->InitMCRegisterInfo(D: LoongArchRegDesc, NR: 177, RA, PC, C: LoongArchMCRegisterClasses, NC: 11, RURoots: LoongArchRegUnitRoots, NRU: 80, DL: LoongArchRegDiffLists, RUMS: LoongArchLaneMaskLists, Strings: LoongArchRegStrings, ClassStrings: LoongArchRegClassStrings, SubIndices: LoongArchSubRegIdxLists, NumIndices: 4,
1238RET: LoongArchRegEncodingTable);
1239
1240 switch (DwarfFlavour) {
1241 default:
1242 llvm_unreachable("Unknown DWARF flavour");
1243 case 0:
1244 RI->mapDwarfRegsToLLVMRegs(Map: LoongArchDwarfFlavour0Dwarf2L, Size: LoongArchDwarfFlavour0Dwarf2LSize, isEH: false);
1245 break;
1246 }
1247 switch (EHFlavour) {
1248 default:
1249 llvm_unreachable("Unknown DWARF flavour");
1250 case 0:
1251 RI->mapDwarfRegsToLLVMRegs(Map: LoongArchEHFlavour0Dwarf2L, Size: LoongArchEHFlavour0Dwarf2LSize, isEH: true);
1252 break;
1253 }
1254 switch (DwarfFlavour) {
1255 default:
1256 llvm_unreachable("Unknown DWARF flavour");
1257 case 0:
1258 RI->mapLLVMRegsToDwarfRegs(Map: LoongArchDwarfFlavour0L2Dwarf, Size: LoongArchDwarfFlavour0L2DwarfSize, isEH: false);
1259 break;
1260 }
1261 switch (EHFlavour) {
1262 default:
1263 llvm_unreachable("Unknown DWARF flavour");
1264 case 0:
1265 RI->mapLLVMRegsToDwarfRegs(Map: LoongArchEHFlavour0L2Dwarf, Size: LoongArchEHFlavour0L2DwarfSize, isEH: true);
1266 break;
1267 }
1268}
1269
1270} // end namespace llvm
1271
1272