1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t LoongArchRegDiffLists[] = {
12 /* 0 */ -32, 64, -144, 0,
13 /* 4 */ 144, -64, 32, 0,
14};
15
16extern const LaneBitmask LoongArchLaneMaskLists[] = {
17 /* 0 */ LaneBitmask(0x0000000000000001),
18 /* 1 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
19};
20
21extern const uint16_t LoongArchSubRegIdxLists[] = {
22 /* 0 */ 3, 2, 1,
23};
24
25
26#ifdef __GNUC__
27#pragma GCC diagnostic push
28#pragma GCC diagnostic ignored "-Woverlength-strings"
29#endif
30extern const char LoongArchRegStrings[] = {
31 /* 0 */ "F10\000"
32 /* 4 */ "VR10\000"
33 /* 9 */ "XR10\000"
34 /* 14 */ "F20\000"
35 /* 18 */ "VR20\000"
36 /* 23 */ "XR20\000"
37 /* 28 */ "F30\000"
38 /* 32 */ "VR30\000"
39 /* 37 */ "XR30\000"
40 /* 42 */ "FCC0\000"
41 /* 47 */ "F0\000"
42 /* 50 */ "SCR0\000"
43 /* 55 */ "FCSR0\000"
44 /* 61 */ "VR0\000"
45 /* 65 */ "XR0\000"
46 /* 69 */ "F11\000"
47 /* 73 */ "VR11\000"
48 /* 78 */ "XR11\000"
49 /* 83 */ "F21\000"
50 /* 87 */ "VR21\000"
51 /* 92 */ "XR21\000"
52 /* 97 */ "F31\000"
53 /* 101 */ "VR31\000"
54 /* 106 */ "XR31\000"
55 /* 111 */ "FCC1\000"
56 /* 116 */ "F1\000"
57 /* 119 */ "SCR1\000"
58 /* 124 */ "FCSR1\000"
59 /* 130 */ "VR1\000"
60 /* 134 */ "XR1\000"
61 /* 138 */ "F12\000"
62 /* 142 */ "VR12\000"
63 /* 147 */ "XR12\000"
64 /* 152 */ "F22\000"
65 /* 156 */ "VR22\000"
66 /* 161 */ "XR22\000"
67 /* 166 */ "FCC2\000"
68 /* 171 */ "F2\000"
69 /* 174 */ "SCR2\000"
70 /* 179 */ "FCSR2\000"
71 /* 185 */ "VR2\000"
72 /* 189 */ "XR2\000"
73 /* 193 */ "F13\000"
74 /* 197 */ "VR13\000"
75 /* 202 */ "XR13\000"
76 /* 207 */ "F23\000"
77 /* 211 */ "VR23\000"
78 /* 216 */ "XR23\000"
79 /* 221 */ "FCC3\000"
80 /* 226 */ "F3\000"
81 /* 229 */ "SCR3\000"
82 /* 234 */ "FCSR3\000"
83 /* 240 */ "VR3\000"
84 /* 244 */ "XR3\000"
85 /* 248 */ "F14\000"
86 /* 252 */ "VR14\000"
87 /* 257 */ "XR14\000"
88 /* 262 */ "F24\000"
89 /* 266 */ "VR24\000"
90 /* 271 */ "XR24\000"
91 /* 276 */ "F10_64\000"
92 /* 283 */ "F20_64\000"
93 /* 290 */ "F30_64\000"
94 /* 297 */ "F0_64\000"
95 /* 303 */ "F11_64\000"
96 /* 310 */ "F21_64\000"
97 /* 317 */ "F31_64\000"
98 /* 324 */ "F1_64\000"
99 /* 330 */ "F12_64\000"
100 /* 337 */ "F22_64\000"
101 /* 344 */ "F2_64\000"
102 /* 350 */ "F13_64\000"
103 /* 357 */ "F23_64\000"
104 /* 364 */ "F3_64\000"
105 /* 370 */ "F14_64\000"
106 /* 377 */ "F24_64\000"
107 /* 384 */ "F4_64\000"
108 /* 390 */ "F15_64\000"
109 /* 397 */ "F25_64\000"
110 /* 404 */ "F5_64\000"
111 /* 410 */ "F16_64\000"
112 /* 417 */ "F26_64\000"
113 /* 424 */ "F6_64\000"
114 /* 430 */ "F17_64\000"
115 /* 437 */ "F27_64\000"
116 /* 444 */ "F7_64\000"
117 /* 450 */ "F18_64\000"
118 /* 457 */ "F28_64\000"
119 /* 464 */ "F8_64\000"
120 /* 470 */ "F19_64\000"
121 /* 477 */ "F29_64\000"
122 /* 484 */ "F9_64\000"
123 /* 490 */ "FCC4\000"
124 /* 495 */ "F4\000"
125 /* 498 */ "VR4\000"
126 /* 502 */ "XR4\000"
127 /* 506 */ "F15\000"
128 /* 510 */ "VR15\000"
129 /* 515 */ "XR15\000"
130 /* 520 */ "F25\000"
131 /* 524 */ "VR25\000"
132 /* 529 */ "XR25\000"
133 /* 534 */ "FCC5\000"
134 /* 539 */ "F5\000"
135 /* 542 */ "VR5\000"
136 /* 546 */ "XR5\000"
137 /* 550 */ "F16\000"
138 /* 554 */ "VR16\000"
139 /* 559 */ "XR16\000"
140 /* 564 */ "F26\000"
141 /* 568 */ "VR26\000"
142 /* 573 */ "XR26\000"
143 /* 578 */ "FCC6\000"
144 /* 583 */ "F6\000"
145 /* 586 */ "VR6\000"
146 /* 590 */ "XR6\000"
147 /* 594 */ "F17\000"
148 /* 598 */ "VR17\000"
149 /* 603 */ "XR17\000"
150 /* 608 */ "F27\000"
151 /* 612 */ "VR27\000"
152 /* 617 */ "XR27\000"
153 /* 622 */ "FCC7\000"
154 /* 627 */ "F7\000"
155 /* 630 */ "VR7\000"
156 /* 634 */ "XR7\000"
157 /* 638 */ "F18\000"
158 /* 642 */ "VR18\000"
159 /* 647 */ "XR18\000"
160 /* 652 */ "F28\000"
161 /* 656 */ "VR28\000"
162 /* 661 */ "XR28\000"
163 /* 666 */ "F8\000"
164 /* 669 */ "VR8\000"
165 /* 673 */ "XR8\000"
166 /* 677 */ "F19\000"
167 /* 681 */ "VR19\000"
168 /* 686 */ "XR19\000"
169 /* 691 */ "F29\000"
170 /* 695 */ "VR29\000"
171 /* 700 */ "XR29\000"
172 /* 705 */ "F9\000"
173 /* 708 */ "VR9\000"
174 /* 712 */ "XR9\000"
175};
176#ifdef __GNUC__
177#pragma GCC diagnostic pop
178#endif
179
180extern const MCRegisterDesc LoongArchRegDesc[] = { // Descriptors
181 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
182 { .Name: 47, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12288, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
183 { .Name: 116, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12289, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
184 { .Name: 171, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12290, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
185 { .Name: 226, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12291, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
186 { .Name: 495, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12292, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
187 { .Name: 539, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12293, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
188 { .Name: 583, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12294, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
189 { .Name: 627, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12295, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
190 { .Name: 666, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12296, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
191 { .Name: 705, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12297, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
192 { .Name: 0, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12298, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
193 { .Name: 69, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12299, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
194 { .Name: 138, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12300, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
195 { .Name: 193, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12301, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
196 { .Name: 248, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12302, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
197 { .Name: 506, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12303, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
198 { .Name: 550, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12304, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
199 { .Name: 594, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12305, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
200 { .Name: 638, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12306, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
201 { .Name: 677, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12307, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
202 { .Name: 14, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12308, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
203 { .Name: 83, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12309, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
204 { .Name: 152, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12310, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
205 { .Name: 207, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12311, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
206 { .Name: 262, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12312, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
207 { .Name: 520, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12313, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
208 { .Name: 564, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12314, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
209 { .Name: 608, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12315, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
210 { .Name: 652, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12316, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
211 { .Name: 691, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12317, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
212 { .Name: 28, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12318, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
213 { .Name: 97, .SubRegs: 3, .SuperRegs: 4, .SubRegIndices: 3, .RegUnits: 12319, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
214 { .Name: 42, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12320, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
215 { .Name: 111, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12321, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
216 { .Name: 166, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12322, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
217 { .Name: 221, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12323, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
218 { .Name: 490, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12324, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
219 { .Name: 534, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12325, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
220 { .Name: 578, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12326, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
221 { .Name: 622, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12327, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
222 { .Name: 55, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12328, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
223 { .Name: 124, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12329, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
224 { .Name: 179, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12330, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
225 { .Name: 234, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12331, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
226 { .Name: 52, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12332, .RegUnitLaneMasks: 1, .IsConstant: 1, .IsArtificial: 0 },
227 { .Name: 121, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12333, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
228 { .Name: 176, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12334, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
229 { .Name: 231, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12335, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
230 { .Name: 499, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12336, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
231 { .Name: 543, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12337, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
232 { .Name: 587, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12338, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
233 { .Name: 631, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12339, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
234 { .Name: 670, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12340, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
235 { .Name: 709, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12341, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
236 { .Name: 5, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12342, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
237 { .Name: 74, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12343, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
238 { .Name: 143, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12344, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
239 { .Name: 198, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12345, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
240 { .Name: 253, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12346, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
241 { .Name: 511, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12347, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
242 { .Name: 555, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12348, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
243 { .Name: 599, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12349, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
244 { .Name: 643, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12350, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
245 { .Name: 682, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12351, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
246 { .Name: 19, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12352, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
247 { .Name: 88, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12353, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
248 { .Name: 157, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12354, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
249 { .Name: 212, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12355, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
250 { .Name: 267, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12356, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
251 { .Name: 525, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12357, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
252 { .Name: 569, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12358, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
253 { .Name: 613, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12359, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
254 { .Name: 657, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12360, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
255 { .Name: 696, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12361, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
256 { .Name: 33, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12362, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
257 { .Name: 102, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12363, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
258 { .Name: 50, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12364, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
259 { .Name: 119, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12365, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
260 { .Name: 174, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12366, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
261 { .Name: 229, .SubRegs: 3, .SuperRegs: 3, .SubRegIndices: 3, .RegUnits: 12367, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
262 { .Name: 61, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12288, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
263 { .Name: 130, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12289, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
264 { .Name: 185, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12290, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
265 { .Name: 240, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12291, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
266 { .Name: 498, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12292, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
267 { .Name: 542, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12293, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
268 { .Name: 586, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12294, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
269 { .Name: 630, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12295, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
270 { .Name: 669, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12296, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
271 { .Name: 708, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12297, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
272 { .Name: 4, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12298, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
273 { .Name: 73, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12299, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
274 { .Name: 142, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12300, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
275 { .Name: 197, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12301, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
276 { .Name: 252, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12302, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
277 { .Name: 510, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12303, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
278 { .Name: 554, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12304, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
279 { .Name: 598, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12305, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
280 { .Name: 642, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12306, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
281 { .Name: 681, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12307, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
282 { .Name: 18, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12308, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
283 { .Name: 87, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12309, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
284 { .Name: 156, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12310, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
285 { .Name: 211, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12311, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
286 { .Name: 266, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12312, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
287 { .Name: 524, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12313, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
288 { .Name: 568, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12314, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
289 { .Name: 612, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12315, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
290 { .Name: 656, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12316, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
291 { .Name: 695, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12317, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
292 { .Name: 32, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12318, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
293 { .Name: 101, .SubRegs: 1, .SuperRegs: 6, .SubRegIndices: 1, .RegUnits: 12319, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
294 { .Name: 65, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12288, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
295 { .Name: 134, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12289, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
296 { .Name: 189, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12290, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
297 { .Name: 244, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12291, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
298 { .Name: 502, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12292, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
299 { .Name: 546, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12293, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
300 { .Name: 590, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12294, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
301 { .Name: 634, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12295, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
302 { .Name: 673, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12296, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
303 { .Name: 712, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12297, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
304 { .Name: 9, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12298, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
305 { .Name: 78, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12299, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
306 { .Name: 147, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12300, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
307 { .Name: 202, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12301, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
308 { .Name: 257, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12302, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
309 { .Name: 515, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12303, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
310 { .Name: 559, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12304, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
311 { .Name: 603, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12305, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
312 { .Name: 647, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12306, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
313 { .Name: 686, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12307, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
314 { .Name: 23, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12308, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
315 { .Name: 92, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12309, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
316 { .Name: 161, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12310, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
317 { .Name: 216, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12311, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
318 { .Name: 271, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12312, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
319 { .Name: 529, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12313, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
320 { .Name: 573, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12314, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
321 { .Name: 617, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12315, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
322 { .Name: 661, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12316, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
323 { .Name: 700, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12317, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
324 { .Name: 37, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12318, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
325 { .Name: 106, .SubRegs: 0, .SuperRegs: 3, .SubRegIndices: 0, .RegUnits: 12319, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
326 { .Name: 297, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12288, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
327 { .Name: 324, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12289, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
328 { .Name: 344, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12290, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
329 { .Name: 364, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12291, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
330 { .Name: 384, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12292, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
331 { .Name: 404, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12293, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
332 { .Name: 424, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12294, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
333 { .Name: 444, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12295, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
334 { .Name: 464, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12296, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
335 { .Name: 484, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12297, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
336 { .Name: 276, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12298, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
337 { .Name: 303, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12299, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
338 { .Name: 330, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12300, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
339 { .Name: 350, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12301, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
340 { .Name: 370, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12302, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
341 { .Name: 390, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12303, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
342 { .Name: 410, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12304, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
343 { .Name: 430, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12305, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
344 { .Name: 450, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12306, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
345 { .Name: 470, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12307, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
346 { .Name: 283, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12308, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
347 { .Name: 310, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12309, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
348 { .Name: 337, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12310, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
349 { .Name: 357, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12311, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
350 { .Name: 377, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12312, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
351 { .Name: 397, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12313, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
352 { .Name: 417, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12314, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
353 { .Name: 437, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12315, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
354 { .Name: 457, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12316, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
355 { .Name: 477, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12317, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
356 { .Name: 290, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12318, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
357 { .Name: 317, .SubRegs: 2, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 12319, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
358};
359
360extern const MCPhysReg LoongArchRegUnitRoots[][2] = {
361 { LoongArch::F0 },
362 { LoongArch::F1 },
363 { LoongArch::F2 },
364 { LoongArch::F3 },
365 { LoongArch::F4 },
366 { LoongArch::F5 },
367 { LoongArch::F6 },
368 { LoongArch::F7 },
369 { LoongArch::F8 },
370 { LoongArch::F9 },
371 { LoongArch::F10 },
372 { LoongArch::F11 },
373 { LoongArch::F12 },
374 { LoongArch::F13 },
375 { LoongArch::F14 },
376 { LoongArch::F15 },
377 { LoongArch::F16 },
378 { LoongArch::F17 },
379 { LoongArch::F18 },
380 { LoongArch::F19 },
381 { LoongArch::F20 },
382 { LoongArch::F21 },
383 { LoongArch::F22 },
384 { LoongArch::F23 },
385 { LoongArch::F24 },
386 { LoongArch::F25 },
387 { LoongArch::F26 },
388 { LoongArch::F27 },
389 { LoongArch::F28 },
390 { LoongArch::F29 },
391 { LoongArch::F30 },
392 { LoongArch::F31 },
393 { LoongArch::FCC0 },
394 { LoongArch::FCC1 },
395 { LoongArch::FCC2 },
396 { LoongArch::FCC3 },
397 { LoongArch::FCC4 },
398 { LoongArch::FCC5 },
399 { LoongArch::FCC6 },
400 { LoongArch::FCC7 },
401 { LoongArch::FCSR0 },
402 { LoongArch::FCSR1 },
403 { LoongArch::FCSR2 },
404 { LoongArch::FCSR3 },
405 { LoongArch::R0 },
406 { LoongArch::R1 },
407 { LoongArch::R2 },
408 { LoongArch::R3 },
409 { LoongArch::R4 },
410 { LoongArch::R5 },
411 { LoongArch::R6 },
412 { LoongArch::R7 },
413 { LoongArch::R8 },
414 { LoongArch::R9 },
415 { LoongArch::R10 },
416 { LoongArch::R11 },
417 { LoongArch::R12 },
418 { LoongArch::R13 },
419 { LoongArch::R14 },
420 { LoongArch::R15 },
421 { LoongArch::R16 },
422 { LoongArch::R17 },
423 { LoongArch::R18 },
424 { LoongArch::R19 },
425 { LoongArch::R20 },
426 { LoongArch::R21 },
427 { LoongArch::R22 },
428 { LoongArch::R23 },
429 { LoongArch::R24 },
430 { LoongArch::R25 },
431 { LoongArch::R26 },
432 { LoongArch::R27 },
433 { LoongArch::R28 },
434 { LoongArch::R29 },
435 { LoongArch::R30 },
436 { LoongArch::R31 },
437 { LoongArch::SCR0 },
438 { LoongArch::SCR1 },
439 { LoongArch::SCR2 },
440 { LoongArch::SCR3 },
441};
442
443// Register classes...
444
445#ifdef __GNUC__
446#pragma GCC diagnostic push
447#pragma GCC diagnostic ignored "-Woverlength-strings"
448#endif
449extern const char LoongArchRegClassStrings[] = {
450 /* 0 */ "GPRNoR0R1\000"
451 /* 10 */ "FPR32\000"
452 /* 16 */ "FPR64\000"
453 /* 22 */ "LASX256\000"
454 /* 30 */ "LSX128\000"
455 /* 37 */ "SCR\000"
456 /* 41 */ "CFR\000"
457 /* 45 */ "GPRJR\000"
458 /* 51 */ "GPR\000"
459 /* 55 */ "FCSR\000"
460 /* 60 */ "GPRT\000"
461};
462#ifdef __GNUC__
463#pragma GCC diagnostic pop
464#endif
465
466using LoongArchRegisterClassStorage = MCRegisterClassStorage<11, 254, 34, 14, 6, 6>;
467extern const MCRegisterClassStorage<11, 254, 34, 14, 6, 6> LoongArchMCRegisterClassStorage = {
468 .Classes: {
469 {
470 offsetof(LoongArchRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
471 offsetof(LoongArchRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
472 .NameIdx: 10,
473 .RegSizeInBits: 32,
474 .RegsSize: 32,
475 .RegSetBegin: 1, /* MinRegVal */
476 .RegSetSize: 32, /* RegSetSize */
477 .ID: LoongArch::FPR32RegClassID,
478 .CopyCost: 1, /* CopyCost */
479 .Allocatable: true, /* Allocatable */
480 .BaseClass: false,
481 offsetof(LoongArchRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
482 offsetof(LoongArchRegisterClassStorage, SuperRegIdxSeqs[0]) - 0 * sizeof(MCRegisterClass),
483 .LaneMask: LaneBitmask(0x0000000000000001),
484 .AllocationPriority: 0,
485 .GlobalPriority: false,
486 .TSFlags: 0x00, /* TSFlags */
487 .SpillStackID: 0, /* SpillStackID */
488 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
489 .CoveredBySubRegs: false, /* CoveredBySubRegs */
490 offsetof(LoongArchRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
491 .SuperClassesSize: 0
492 },
493 {
494 offsetof(LoongArchRegisterClassStorage, Regs[32]) - 1 * sizeof(MCRegisterClass),
495 offsetof(LoongArchRegisterClassStorage, BitSets[4]) - 1 * sizeof(MCRegisterClass),
496 .NameIdx: 51,
497 .RegSizeInBits: 0,
498 .RegsSize: 32,
499 .RegSetBegin: 45, /* MinRegVal */
500 .RegSetSize: 32, /* RegSetSize */
501 .ID: LoongArch::GPRRegClassID,
502 .CopyCost: 1, /* CopyCost */
503 .Allocatable: true, /* Allocatable */
504 .BaseClass: false,
505 offsetof(LoongArchRegisterClassStorage, SubClassMasks[2]) - 1 * sizeof(MCRegisterClass),
506 offsetof(LoongArchRegisterClassStorage, SuperRegIdxSeqs[1]) - 1 * sizeof(MCRegisterClass),
507 .LaneMask: LaneBitmask(0x0000000000000001),
508 .AllocationPriority: 0,
509 .GlobalPriority: false,
510 .TSFlags: 0x00, /* TSFlags */
511 .SpillStackID: 0, /* SpillStackID */
512 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
513 .CoveredBySubRegs: false, /* CoveredBySubRegs */
514 offsetof(LoongArchRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
515 .SuperClassesSize: 0
516 },
517 {
518 offsetof(LoongArchRegisterClassStorage, Regs[64]) - 2 * sizeof(MCRegisterClass),
519 offsetof(LoongArchRegisterClassStorage, BitSets[8]) - 2 * sizeof(MCRegisterClass),
520 .NameIdx: 45,
521 .RegSizeInBits: 0,
522 .RegsSize: 31,
523 .RegSetBegin: 45, /* MinRegVal */
524 .RegSetSize: 32, /* RegSetSize */
525 .ID: LoongArch::GPRJRRegClassID,
526 .CopyCost: 1, /* CopyCost */
527 .Allocatable: true, /* Allocatable */
528 .BaseClass: false,
529 offsetof(LoongArchRegisterClassStorage, SubClassMasks[3]) - 2 * sizeof(MCRegisterClass),
530 offsetof(LoongArchRegisterClassStorage, SuperRegIdxSeqs[1]) - 2 * sizeof(MCRegisterClass),
531 .LaneMask: LaneBitmask(0x0000000000000001),
532 .AllocationPriority: 0,
533 .GlobalPriority: false,
534 .TSFlags: 0x00, /* TSFlags */
535 .SpillStackID: 0, /* SpillStackID */
536 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
537 .CoveredBySubRegs: false, /* CoveredBySubRegs */
538 offsetof(LoongArchRegisterClassStorage, SuperClasses[0]) - 2 * sizeof(MCRegisterClass),
539 .SuperClassesSize: 1
540 },
541 {
542 offsetof(LoongArchRegisterClassStorage, Regs[95]) - 3 * sizeof(MCRegisterClass),
543 offsetof(LoongArchRegisterClassStorage, BitSets[12]) - 3 * sizeof(MCRegisterClass),
544 .NameIdx: 0,
545 .RegSizeInBits: 0,
546 .RegsSize: 30,
547 .RegSetBegin: 47, /* MinRegVal */
548 .RegSetSize: 30, /* RegSetSize */
549 .ID: LoongArch::GPRNoR0R1RegClassID,
550 .CopyCost: 1, /* CopyCost */
551 .Allocatable: true, /* Allocatable */
552 .BaseClass: false,
553 offsetof(LoongArchRegisterClassStorage, SubClassMasks[4]) - 3 * sizeof(MCRegisterClass),
554 offsetof(LoongArchRegisterClassStorage, SuperRegIdxSeqs[1]) - 3 * sizeof(MCRegisterClass),
555 .LaneMask: LaneBitmask(0x0000000000000001),
556 .AllocationPriority: 0,
557 .GlobalPriority: false,
558 .TSFlags: 0x00, /* TSFlags */
559 .SpillStackID: 0, /* SpillStackID */
560 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
561 .CoveredBySubRegs: false, /* CoveredBySubRegs */
562 offsetof(LoongArchRegisterClassStorage, SuperClasses[1]) - 3 * sizeof(MCRegisterClass),
563 .SuperClassesSize: 2
564 },
565 {
566 offsetof(LoongArchRegisterClassStorage, Regs[125]) - 4 * sizeof(MCRegisterClass),
567 offsetof(LoongArchRegisterClassStorage, BitSets[16]) - 4 * sizeof(MCRegisterClass),
568 .NameIdx: 60,
569 .RegSizeInBits: 0,
570 .RegsSize: 17,
571 .RegSetBegin: 49, /* MinRegVal */
572 .RegSetSize: 17, /* RegSetSize */
573 .ID: LoongArch::GPRTRegClassID,
574 .CopyCost: 1, /* CopyCost */
575 .Allocatable: true, /* Allocatable */
576 .BaseClass: false,
577 offsetof(LoongArchRegisterClassStorage, SubClassMasks[5]) - 4 * sizeof(MCRegisterClass),
578 offsetof(LoongArchRegisterClassStorage, SuperRegIdxSeqs[1]) - 4 * sizeof(MCRegisterClass),
579 .LaneMask: LaneBitmask(0x0000000000000001),
580 .AllocationPriority: 0,
581 .GlobalPriority: false,
582 .TSFlags: 0x00, /* TSFlags */
583 .SpillStackID: 0, /* SpillStackID */
584 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
585 .CoveredBySubRegs: false, /* CoveredBySubRegs */
586 offsetof(LoongArchRegisterClassStorage, SuperClasses[3]) - 4 * sizeof(MCRegisterClass),
587 .SuperClassesSize: 3
588 },
589 {
590 offsetof(LoongArchRegisterClassStorage, Regs[142]) - 5 * sizeof(MCRegisterClass),
591 offsetof(LoongArchRegisterClassStorage, BitSets[19]) - 5 * sizeof(MCRegisterClass),
592 .NameIdx: 41,
593 .RegSizeInBits: 0,
594 .RegsSize: 8,
595 .RegSetBegin: 33, /* MinRegVal */
596 .RegSetSize: 8, /* RegSetSize */
597 .ID: LoongArch::CFRRegClassID,
598 .CopyCost: 1, /* CopyCost */
599 .Allocatable: true, /* Allocatable */
600 .BaseClass: false,
601 offsetof(LoongArchRegisterClassStorage, SubClassMasks[6]) - 5 * sizeof(MCRegisterClass),
602 offsetof(LoongArchRegisterClassStorage, SuperRegIdxSeqs[1]) - 5 * sizeof(MCRegisterClass),
603 .LaneMask: LaneBitmask(0x0000000000000001),
604 .AllocationPriority: 0,
605 .GlobalPriority: false,
606 .TSFlags: 0x00, /* TSFlags */
607 .SpillStackID: 0, /* SpillStackID */
608 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
609 .CoveredBySubRegs: false, /* CoveredBySubRegs */
610 offsetof(LoongArchRegisterClassStorage, SuperClasses[6]) - 5 * sizeof(MCRegisterClass),
611 .SuperClassesSize: 0
612 },
613 {
614 offsetof(LoongArchRegisterClassStorage, Regs[150]) - 6 * sizeof(MCRegisterClass),
615 offsetof(LoongArchRegisterClassStorage, BitSets[20]) - 6 * sizeof(MCRegisterClass),
616 .NameIdx: 55,
617 .RegSizeInBits: 32,
618 .RegsSize: 4,
619 .RegSetBegin: 41, /* MinRegVal */
620 .RegSetSize: 4, /* RegSetSize */
621 .ID: LoongArch::FCSRRegClassID,
622 .CopyCost: 1, /* CopyCost */
623 .Allocatable: false, /* Allocatable */
624 .BaseClass: false,
625 offsetof(LoongArchRegisterClassStorage, SubClassMasks[7]) - 6 * sizeof(MCRegisterClass),
626 offsetof(LoongArchRegisterClassStorage, SuperRegIdxSeqs[1]) - 6 * sizeof(MCRegisterClass),
627 .LaneMask: LaneBitmask(0x0000000000000001),
628 .AllocationPriority: 0,
629 .GlobalPriority: false,
630 .TSFlags: 0x00, /* TSFlags */
631 .SpillStackID: 0, /* SpillStackID */
632 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
633 .CoveredBySubRegs: false, /* CoveredBySubRegs */
634 offsetof(LoongArchRegisterClassStorage, SuperClasses[6]) - 6 * sizeof(MCRegisterClass),
635 .SuperClassesSize: 0
636 },
637 {
638 offsetof(LoongArchRegisterClassStorage, Regs[154]) - 7 * sizeof(MCRegisterClass),
639 offsetof(LoongArchRegisterClassStorage, BitSets[21]) - 7 * sizeof(MCRegisterClass),
640 .NameIdx: 37,
641 .RegSizeInBits: 0,
642 .RegsSize: 4,
643 .RegSetBegin: 77, /* MinRegVal */
644 .RegSetSize: 4, /* RegSetSize */
645 .ID: LoongArch::SCRRegClassID,
646 .CopyCost: 1, /* CopyCost */
647 .Allocatable: false, /* Allocatable */
648 .BaseClass: false,
649 offsetof(LoongArchRegisterClassStorage, SubClassMasks[8]) - 7 * sizeof(MCRegisterClass),
650 offsetof(LoongArchRegisterClassStorage, SuperRegIdxSeqs[1]) - 7 * sizeof(MCRegisterClass),
651 .LaneMask: LaneBitmask(0x0000000000000001),
652 .AllocationPriority: 0,
653 .GlobalPriority: false,
654 .TSFlags: 0x00, /* TSFlags */
655 .SpillStackID: 0, /* SpillStackID */
656 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
657 .CoveredBySubRegs: false, /* CoveredBySubRegs */
658 offsetof(LoongArchRegisterClassStorage, SuperClasses[6]) - 7 * sizeof(MCRegisterClass),
659 .SuperClassesSize: 0
660 },
661 {
662 offsetof(LoongArchRegisterClassStorage, Regs[158]) - 8 * sizeof(MCRegisterClass),
663 offsetof(LoongArchRegisterClassStorage, BitSets[22]) - 8 * sizeof(MCRegisterClass),
664 .NameIdx: 16,
665 .RegSizeInBits: 64,
666 .RegsSize: 32,
667 .RegSetBegin: 145, /* MinRegVal */
668 .RegSetSize: 32, /* RegSetSize */
669 .ID: LoongArch::FPR64RegClassID,
670 .CopyCost: 1, /* CopyCost */
671 .Allocatable: true, /* Allocatable */
672 .BaseClass: false,
673 offsetof(LoongArchRegisterClassStorage, SubClassMasks[9]) - 8 * sizeof(MCRegisterClass),
674 offsetof(LoongArchRegisterClassStorage, SuperRegIdxSeqs[2]) - 8 * sizeof(MCRegisterClass),
675 .LaneMask: LaneBitmask(0x0000000000000001),
676 .AllocationPriority: 0,
677 .GlobalPriority: false,
678 .TSFlags: 0x00, /* TSFlags */
679 .SpillStackID: 0, /* SpillStackID */
680 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
681 .CoveredBySubRegs: false, /* CoveredBySubRegs */
682 offsetof(LoongArchRegisterClassStorage, SuperClasses[6]) - 8 * sizeof(MCRegisterClass),
683 .SuperClassesSize: 0
684 },
685 {
686 offsetof(LoongArchRegisterClassStorage, Regs[190]) - 9 * sizeof(MCRegisterClass),
687 offsetof(LoongArchRegisterClassStorage, BitSets[26]) - 9 * sizeof(MCRegisterClass),
688 .NameIdx: 30,
689 .RegSizeInBits: 128,
690 .RegsSize: 32,
691 .RegSetBegin: 81, /* MinRegVal */
692 .RegSetSize: 32, /* RegSetSize */
693 .ID: LoongArch::LSX128RegClassID,
694 .CopyCost: 1, /* CopyCost */
695 .Allocatable: true, /* Allocatable */
696 .BaseClass: false,
697 offsetof(LoongArchRegisterClassStorage, SubClassMasks[11]) - 9 * sizeof(MCRegisterClass),
698 offsetof(LoongArchRegisterClassStorage, SuperRegIdxSeqs[4]) - 9 * sizeof(MCRegisterClass),
699 .LaneMask: LaneBitmask(0x0000000000000001),
700 .AllocationPriority: 0,
701 .GlobalPriority: false,
702 .TSFlags: 0x00, /* TSFlags */
703 .SpillStackID: 0, /* SpillStackID */
704 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
705 .CoveredBySubRegs: false, /* CoveredBySubRegs */
706 offsetof(LoongArchRegisterClassStorage, SuperClasses[6]) - 9 * sizeof(MCRegisterClass),
707 .SuperClassesSize: 0
708 },
709 {
710 offsetof(LoongArchRegisterClassStorage, Regs[222]) - 10 * sizeof(MCRegisterClass),
711 offsetof(LoongArchRegisterClassStorage, BitSets[30]) - 10 * sizeof(MCRegisterClass),
712 .NameIdx: 22,
713 .RegSizeInBits: 256,
714 .RegsSize: 32,
715 .RegSetBegin: 113, /* MinRegVal */
716 .RegSetSize: 32, /* RegSetSize */
717 .ID: LoongArch::LASX256RegClassID,
718 .CopyCost: 1, /* CopyCost */
719 .Allocatable: true, /* Allocatable */
720 .BaseClass: false,
721 offsetof(LoongArchRegisterClassStorage, SubClassMasks[13]) - 10 * sizeof(MCRegisterClass),
722 offsetof(LoongArchRegisterClassStorage, SuperRegIdxSeqs[1]) - 10 * sizeof(MCRegisterClass),
723 .LaneMask: LaneBitmask(0x0000000000000001),
724 .AllocationPriority: 0,
725 .GlobalPriority: false,
726 .TSFlags: 0x00, /* TSFlags */
727 .SpillStackID: 0, /* SpillStackID */
728 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
729 .CoveredBySubRegs: false, /* CoveredBySubRegs */
730 offsetof(LoongArchRegisterClassStorage, SuperClasses[6]) - 10 * sizeof(MCRegisterClass),
731 .SuperClassesSize: 0
732 },
733 },
734 .Regs: {
735 /* 0 */ LoongArch::F0, LoongArch::F1, LoongArch::F2, LoongArch::F3, LoongArch::F4, LoongArch::F5, LoongArch::F6, LoongArch::F7, LoongArch::F8, LoongArch::F9, LoongArch::F10, LoongArch::F11, LoongArch::F12, LoongArch::F13, LoongArch::F14, LoongArch::F15, LoongArch::F16, LoongArch::F17, LoongArch::F18, LoongArch::F19, LoongArch::F20, LoongArch::F21, LoongArch::F22, LoongArch::F23, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31,
736 /* 32 */ LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R0, LoongArch::R1, LoongArch::R2, LoongArch::R3, LoongArch::R21,
737 /* 64 */ LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R0, LoongArch::R2, LoongArch::R3, LoongArch::R21,
738 /* 95 */ LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R2, LoongArch::R3, LoongArch::R21,
739 /* 125 */ LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20,
740 /* 142 */ LoongArch::FCC0, LoongArch::FCC1, LoongArch::FCC2, LoongArch::FCC3, LoongArch::FCC4, LoongArch::FCC5, LoongArch::FCC6, LoongArch::FCC7,
741 /* 150 */ LoongArch::FCSR0, LoongArch::FCSR1, LoongArch::FCSR2, LoongArch::FCSR3,
742 /* 154 */ LoongArch::SCR0, LoongArch::SCR1, LoongArch::SCR2, LoongArch::SCR3,
743 /* 158 */ LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64, LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64, LoongArch::F8_64, LoongArch::F9_64, LoongArch::F10_64, LoongArch::F11_64, LoongArch::F12_64, LoongArch::F13_64, LoongArch::F14_64, LoongArch::F15_64, LoongArch::F16_64, LoongArch::F17_64, LoongArch::F18_64, LoongArch::F19_64, LoongArch::F20_64, LoongArch::F21_64, LoongArch::F22_64, LoongArch::F23_64, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64,
744 /* 190 */ LoongArch::VR0, LoongArch::VR1, LoongArch::VR2, LoongArch::VR3, LoongArch::VR4, LoongArch::VR5, LoongArch::VR6, LoongArch::VR7, LoongArch::VR8, LoongArch::VR9, LoongArch::VR10, LoongArch::VR11, LoongArch::VR12, LoongArch::VR13, LoongArch::VR14, LoongArch::VR15, LoongArch::VR16, LoongArch::VR17, LoongArch::VR18, LoongArch::VR19, LoongArch::VR20, LoongArch::VR21, LoongArch::VR22, LoongArch::VR23, LoongArch::VR24, LoongArch::VR25, LoongArch::VR26, LoongArch::VR27, LoongArch::VR28, LoongArch::VR29, LoongArch::VR30, LoongArch::VR31,
745 /* 222 */ LoongArch::XR0, LoongArch::XR1, LoongArch::XR2, LoongArch::XR3, LoongArch::XR4, LoongArch::XR5, LoongArch::XR6, LoongArch::XR7, LoongArch::XR8, LoongArch::XR9, LoongArch::XR10, LoongArch::XR11, LoongArch::XR12, LoongArch::XR13, LoongArch::XR14, LoongArch::XR15, LoongArch::XR16, LoongArch::XR17, LoongArch::XR18, LoongArch::XR19, LoongArch::XR20, LoongArch::XR21, LoongArch::XR22, LoongArch::XR23, LoongArch::XR24, LoongArch::XR25, LoongArch::XR26, LoongArch::XR27, LoongArch::XR28, LoongArch::XR29, LoongArch::XR30, LoongArch::XR31,
746 },
747 .BitSets: {
748 /* 0 */ 0xff, 0xff, 0xff, 0xff,
749 /* 4 */ 0xff, 0xff, 0xff, 0xff,
750 /* 8 */ 0xfd, 0xff, 0xff, 0xff,
751 /* 12 */ 0xff, 0xff, 0xff, 0x3f,
752 /* 16 */ 0xff, 0xff, 0x01,
753 /* 19 */ 0xff,
754 /* 20 */ 0x0f,
755 /* 21 */ 0x0f,
756 /* 22 */ 0xff, 0xff, 0xff, 0xff,
757 /* 26 */ 0xff, 0xff, 0xff, 0xff,
758 /* 30 */ 0xff, 0xff, 0xff, 0xff,
759 },
760 .SubClassMasks: {
761 // 0 FPR32
762 0x00000001,
763 0x00000700, // sub_32
764 // 2 GPR
765 0x0000001e,
766 // 3 GPRJR
767 0x0000001c,
768 // 4 GPRNoR0R1
769 0x00000018,
770 // 5 GPRT
771 0x00000010,
772 // 6 CFR
773 0x00000020,
774 // 7 FCSR
775 0x00000040,
776 // 8 SCR
777 0x00000080,
778 // 9 FPR64
779 0x00000100,
780 0x00000600, // sub_64
781 // 11 LSX128
782 0x00000200,
783 0x00000400, // sub_128
784 // 13 LASX256
785 0x00000400,
786 },
787 .SuperRegIdxSeqs: {
788 /* 0 */ 1, 0,
789 /* 2 */ 2, 0,
790 /* 4 */ 3, 0,
791 },
792 .SuperClasses: {
793 /* 0 FPR32 */
794 /* 0 GPR */
795 /* 0 GPRJR */ LoongArch::GPRRegClassID,
796 /* 1 GPRNoR0R1 */ LoongArch::GPRRegClassID, LoongArch::GPRJRRegClassID,
797 /* 3 GPRT */ LoongArch::GPRRegClassID, LoongArch::GPRJRRegClassID, LoongArch::GPRNoR0R1RegClassID,
798 /* 6 CFR */
799 /* 6 FCSR */
800 /* 6 SCR */
801 /* 6 FPR64 */
802 /* 6 LSX128 */
803 /* 6 LASX256 */
804 }
805};
806
807const MCRegisterClass &getLoongArchMCRegisterClass(unsigned RC) {
808 return LoongArchMCRegisterClassStorage.Classes[RC];
809}
810
811// LoongArch Dwarf<->LLVM register mappings.
812extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[] = {
813 { .FromReg: 0U, .ToReg: LoongArch::R0 },
814 { .FromReg: 1U, .ToReg: LoongArch::R1 },
815 { .FromReg: 2U, .ToReg: LoongArch::R2 },
816 { .FromReg: 3U, .ToReg: LoongArch::R3 },
817 { .FromReg: 4U, .ToReg: LoongArch::R4 },
818 { .FromReg: 5U, .ToReg: LoongArch::R5 },
819 { .FromReg: 6U, .ToReg: LoongArch::R6 },
820 { .FromReg: 7U, .ToReg: LoongArch::R7 },
821 { .FromReg: 8U, .ToReg: LoongArch::R8 },
822 { .FromReg: 9U, .ToReg: LoongArch::R9 },
823 { .FromReg: 10U, .ToReg: LoongArch::R10 },
824 { .FromReg: 11U, .ToReg: LoongArch::R11 },
825 { .FromReg: 12U, .ToReg: LoongArch::R12 },
826 { .FromReg: 13U, .ToReg: LoongArch::R13 },
827 { .FromReg: 14U, .ToReg: LoongArch::R14 },
828 { .FromReg: 15U, .ToReg: LoongArch::R15 },
829 { .FromReg: 16U, .ToReg: LoongArch::R16 },
830 { .FromReg: 17U, .ToReg: LoongArch::R17 },
831 { .FromReg: 18U, .ToReg: LoongArch::R18 },
832 { .FromReg: 19U, .ToReg: LoongArch::R19 },
833 { .FromReg: 20U, .ToReg: LoongArch::R20 },
834 { .FromReg: 21U, .ToReg: LoongArch::R21 },
835 { .FromReg: 22U, .ToReg: LoongArch::R22 },
836 { .FromReg: 23U, .ToReg: LoongArch::R23 },
837 { .FromReg: 24U, .ToReg: LoongArch::R24 },
838 { .FromReg: 25U, .ToReg: LoongArch::R25 },
839 { .FromReg: 26U, .ToReg: LoongArch::R26 },
840 { .FromReg: 27U, .ToReg: LoongArch::R27 },
841 { .FromReg: 28U, .ToReg: LoongArch::R28 },
842 { .FromReg: 29U, .ToReg: LoongArch::R29 },
843 { .FromReg: 30U, .ToReg: LoongArch::R30 },
844 { .FromReg: 31U, .ToReg: LoongArch::R31 },
845 { .FromReg: 32U, .ToReg: LoongArch::F0_64 },
846 { .FromReg: 33U, .ToReg: LoongArch::F1_64 },
847 { .FromReg: 34U, .ToReg: LoongArch::F2_64 },
848 { .FromReg: 35U, .ToReg: LoongArch::F3_64 },
849 { .FromReg: 36U, .ToReg: LoongArch::F4_64 },
850 { .FromReg: 37U, .ToReg: LoongArch::F5_64 },
851 { .FromReg: 38U, .ToReg: LoongArch::F6_64 },
852 { .FromReg: 39U, .ToReg: LoongArch::F7_64 },
853 { .FromReg: 40U, .ToReg: LoongArch::F8_64 },
854 { .FromReg: 41U, .ToReg: LoongArch::F9_64 },
855 { .FromReg: 42U, .ToReg: LoongArch::F10_64 },
856 { .FromReg: 43U, .ToReg: LoongArch::F11_64 },
857 { .FromReg: 44U, .ToReg: LoongArch::F12_64 },
858 { .FromReg: 45U, .ToReg: LoongArch::F13_64 },
859 { .FromReg: 46U, .ToReg: LoongArch::F14_64 },
860 { .FromReg: 47U, .ToReg: LoongArch::F15_64 },
861 { .FromReg: 48U, .ToReg: LoongArch::F16_64 },
862 { .FromReg: 49U, .ToReg: LoongArch::F17_64 },
863 { .FromReg: 50U, .ToReg: LoongArch::F18_64 },
864 { .FromReg: 51U, .ToReg: LoongArch::F19_64 },
865 { .FromReg: 52U, .ToReg: LoongArch::F20_64 },
866 { .FromReg: 53U, .ToReg: LoongArch::F21_64 },
867 { .FromReg: 54U, .ToReg: LoongArch::F22_64 },
868 { .FromReg: 55U, .ToReg: LoongArch::F23_64 },
869 { .FromReg: 56U, .ToReg: LoongArch::F24_64 },
870 { .FromReg: 57U, .ToReg: LoongArch::F25_64 },
871 { .FromReg: 58U, .ToReg: LoongArch::F26_64 },
872 { .FromReg: 59U, .ToReg: LoongArch::F27_64 },
873 { .FromReg: 60U, .ToReg: LoongArch::F28_64 },
874 { .FromReg: 61U, .ToReg: LoongArch::F29_64 },
875 { .FromReg: 62U, .ToReg: LoongArch::F30_64 },
876 { .FromReg: 63U, .ToReg: LoongArch::F31_64 },
877};
878extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize = std::size(LoongArchDwarfFlavour0Dwarf2L);
879
880extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[] = {
881 { .FromReg: 0U, .ToReg: LoongArch::R0 },
882 { .FromReg: 1U, .ToReg: LoongArch::R1 },
883 { .FromReg: 2U, .ToReg: LoongArch::R2 },
884 { .FromReg: 3U, .ToReg: LoongArch::R3 },
885 { .FromReg: 4U, .ToReg: LoongArch::R4 },
886 { .FromReg: 5U, .ToReg: LoongArch::R5 },
887 { .FromReg: 6U, .ToReg: LoongArch::R6 },
888 { .FromReg: 7U, .ToReg: LoongArch::R7 },
889 { .FromReg: 8U, .ToReg: LoongArch::R8 },
890 { .FromReg: 9U, .ToReg: LoongArch::R9 },
891 { .FromReg: 10U, .ToReg: LoongArch::R10 },
892 { .FromReg: 11U, .ToReg: LoongArch::R11 },
893 { .FromReg: 12U, .ToReg: LoongArch::R12 },
894 { .FromReg: 13U, .ToReg: LoongArch::R13 },
895 { .FromReg: 14U, .ToReg: LoongArch::R14 },
896 { .FromReg: 15U, .ToReg: LoongArch::R15 },
897 { .FromReg: 16U, .ToReg: LoongArch::R16 },
898 { .FromReg: 17U, .ToReg: LoongArch::R17 },
899 { .FromReg: 18U, .ToReg: LoongArch::R18 },
900 { .FromReg: 19U, .ToReg: LoongArch::R19 },
901 { .FromReg: 20U, .ToReg: LoongArch::R20 },
902 { .FromReg: 21U, .ToReg: LoongArch::R21 },
903 { .FromReg: 22U, .ToReg: LoongArch::R22 },
904 { .FromReg: 23U, .ToReg: LoongArch::R23 },
905 { .FromReg: 24U, .ToReg: LoongArch::R24 },
906 { .FromReg: 25U, .ToReg: LoongArch::R25 },
907 { .FromReg: 26U, .ToReg: LoongArch::R26 },
908 { .FromReg: 27U, .ToReg: LoongArch::R27 },
909 { .FromReg: 28U, .ToReg: LoongArch::R28 },
910 { .FromReg: 29U, .ToReg: LoongArch::R29 },
911 { .FromReg: 30U, .ToReg: LoongArch::R30 },
912 { .FromReg: 31U, .ToReg: LoongArch::R31 },
913 { .FromReg: 32U, .ToReg: LoongArch::F0_64 },
914 { .FromReg: 33U, .ToReg: LoongArch::F1_64 },
915 { .FromReg: 34U, .ToReg: LoongArch::F2_64 },
916 { .FromReg: 35U, .ToReg: LoongArch::F3_64 },
917 { .FromReg: 36U, .ToReg: LoongArch::F4_64 },
918 { .FromReg: 37U, .ToReg: LoongArch::F5_64 },
919 { .FromReg: 38U, .ToReg: LoongArch::F6_64 },
920 { .FromReg: 39U, .ToReg: LoongArch::F7_64 },
921 { .FromReg: 40U, .ToReg: LoongArch::F8_64 },
922 { .FromReg: 41U, .ToReg: LoongArch::F9_64 },
923 { .FromReg: 42U, .ToReg: LoongArch::F10_64 },
924 { .FromReg: 43U, .ToReg: LoongArch::F11_64 },
925 { .FromReg: 44U, .ToReg: LoongArch::F12_64 },
926 { .FromReg: 45U, .ToReg: LoongArch::F13_64 },
927 { .FromReg: 46U, .ToReg: LoongArch::F14_64 },
928 { .FromReg: 47U, .ToReg: LoongArch::F15_64 },
929 { .FromReg: 48U, .ToReg: LoongArch::F16_64 },
930 { .FromReg: 49U, .ToReg: LoongArch::F17_64 },
931 { .FromReg: 50U, .ToReg: LoongArch::F18_64 },
932 { .FromReg: 51U, .ToReg: LoongArch::F19_64 },
933 { .FromReg: 52U, .ToReg: LoongArch::F20_64 },
934 { .FromReg: 53U, .ToReg: LoongArch::F21_64 },
935 { .FromReg: 54U, .ToReg: LoongArch::F22_64 },
936 { .FromReg: 55U, .ToReg: LoongArch::F23_64 },
937 { .FromReg: 56U, .ToReg: LoongArch::F24_64 },
938 { .FromReg: 57U, .ToReg: LoongArch::F25_64 },
939 { .FromReg: 58U, .ToReg: LoongArch::F26_64 },
940 { .FromReg: 59U, .ToReg: LoongArch::F27_64 },
941 { .FromReg: 60U, .ToReg: LoongArch::F28_64 },
942 { .FromReg: 61U, .ToReg: LoongArch::F29_64 },
943 { .FromReg: 62U, .ToReg: LoongArch::F30_64 },
944 { .FromReg: 63U, .ToReg: LoongArch::F31_64 },
945};
946extern const unsigned LoongArchEHFlavour0Dwarf2LSize = std::size(LoongArchEHFlavour0Dwarf2L);
947
948extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[] = {
949 { .FromReg: LoongArch::F0, .ToReg: 32U },
950 { .FromReg: LoongArch::F1, .ToReg: 33U },
951 { .FromReg: LoongArch::F2, .ToReg: 34U },
952 { .FromReg: LoongArch::F3, .ToReg: 35U },
953 { .FromReg: LoongArch::F4, .ToReg: 36U },
954 { .FromReg: LoongArch::F5, .ToReg: 37U },
955 { .FromReg: LoongArch::F6, .ToReg: 38U },
956 { .FromReg: LoongArch::F7, .ToReg: 39U },
957 { .FromReg: LoongArch::F8, .ToReg: 40U },
958 { .FromReg: LoongArch::F9, .ToReg: 41U },
959 { .FromReg: LoongArch::F10, .ToReg: 42U },
960 { .FromReg: LoongArch::F11, .ToReg: 43U },
961 { .FromReg: LoongArch::F12, .ToReg: 44U },
962 { .FromReg: LoongArch::F13, .ToReg: 45U },
963 { .FromReg: LoongArch::F14, .ToReg: 46U },
964 { .FromReg: LoongArch::F15, .ToReg: 47U },
965 { .FromReg: LoongArch::F16, .ToReg: 48U },
966 { .FromReg: LoongArch::F17, .ToReg: 49U },
967 { .FromReg: LoongArch::F18, .ToReg: 50U },
968 { .FromReg: LoongArch::F19, .ToReg: 51U },
969 { .FromReg: LoongArch::F20, .ToReg: 52U },
970 { .FromReg: LoongArch::F21, .ToReg: 53U },
971 { .FromReg: LoongArch::F22, .ToReg: 54U },
972 { .FromReg: LoongArch::F23, .ToReg: 55U },
973 { .FromReg: LoongArch::F24, .ToReg: 56U },
974 { .FromReg: LoongArch::F25, .ToReg: 57U },
975 { .FromReg: LoongArch::F26, .ToReg: 58U },
976 { .FromReg: LoongArch::F27, .ToReg: 59U },
977 { .FromReg: LoongArch::F28, .ToReg: 60U },
978 { .FromReg: LoongArch::F29, .ToReg: 61U },
979 { .FromReg: LoongArch::F30, .ToReg: 62U },
980 { .FromReg: LoongArch::F31, .ToReg: 63U },
981 { .FromReg: LoongArch::R0, .ToReg: 0U },
982 { .FromReg: LoongArch::R1, .ToReg: 1U },
983 { .FromReg: LoongArch::R2, .ToReg: 2U },
984 { .FromReg: LoongArch::R3, .ToReg: 3U },
985 { .FromReg: LoongArch::R4, .ToReg: 4U },
986 { .FromReg: LoongArch::R5, .ToReg: 5U },
987 { .FromReg: LoongArch::R6, .ToReg: 6U },
988 { .FromReg: LoongArch::R7, .ToReg: 7U },
989 { .FromReg: LoongArch::R8, .ToReg: 8U },
990 { .FromReg: LoongArch::R9, .ToReg: 9U },
991 { .FromReg: LoongArch::R10, .ToReg: 10U },
992 { .FromReg: LoongArch::R11, .ToReg: 11U },
993 { .FromReg: LoongArch::R12, .ToReg: 12U },
994 { .FromReg: LoongArch::R13, .ToReg: 13U },
995 { .FromReg: LoongArch::R14, .ToReg: 14U },
996 { .FromReg: LoongArch::R15, .ToReg: 15U },
997 { .FromReg: LoongArch::R16, .ToReg: 16U },
998 { .FromReg: LoongArch::R17, .ToReg: 17U },
999 { .FromReg: LoongArch::R18, .ToReg: 18U },
1000 { .FromReg: LoongArch::R19, .ToReg: 19U },
1001 { .FromReg: LoongArch::R20, .ToReg: 20U },
1002 { .FromReg: LoongArch::R21, .ToReg: 21U },
1003 { .FromReg: LoongArch::R22, .ToReg: 22U },
1004 { .FromReg: LoongArch::R23, .ToReg: 23U },
1005 { .FromReg: LoongArch::R24, .ToReg: 24U },
1006 { .FromReg: LoongArch::R25, .ToReg: 25U },
1007 { .FromReg: LoongArch::R26, .ToReg: 26U },
1008 { .FromReg: LoongArch::R27, .ToReg: 27U },
1009 { .FromReg: LoongArch::R28, .ToReg: 28U },
1010 { .FromReg: LoongArch::R29, .ToReg: 29U },
1011 { .FromReg: LoongArch::R30, .ToReg: 30U },
1012 { .FromReg: LoongArch::R31, .ToReg: 31U },
1013 { .FromReg: LoongArch::VR0, .ToReg: 32U },
1014 { .FromReg: LoongArch::VR1, .ToReg: 33U },
1015 { .FromReg: LoongArch::VR2, .ToReg: 34U },
1016 { .FromReg: LoongArch::VR3, .ToReg: 35U },
1017 { .FromReg: LoongArch::VR4, .ToReg: 36U },
1018 { .FromReg: LoongArch::VR5, .ToReg: 37U },
1019 { .FromReg: LoongArch::VR6, .ToReg: 38U },
1020 { .FromReg: LoongArch::VR7, .ToReg: 39U },
1021 { .FromReg: LoongArch::VR8, .ToReg: 40U },
1022 { .FromReg: LoongArch::VR9, .ToReg: 41U },
1023 { .FromReg: LoongArch::VR10, .ToReg: 42U },
1024 { .FromReg: LoongArch::VR11, .ToReg: 43U },
1025 { .FromReg: LoongArch::VR12, .ToReg: 44U },
1026 { .FromReg: LoongArch::VR13, .ToReg: 45U },
1027 { .FromReg: LoongArch::VR14, .ToReg: 46U },
1028 { .FromReg: LoongArch::VR15, .ToReg: 47U },
1029 { .FromReg: LoongArch::VR16, .ToReg: 48U },
1030 { .FromReg: LoongArch::VR17, .ToReg: 49U },
1031 { .FromReg: LoongArch::VR18, .ToReg: 50U },
1032 { .FromReg: LoongArch::VR19, .ToReg: 51U },
1033 { .FromReg: LoongArch::VR20, .ToReg: 52U },
1034 { .FromReg: LoongArch::VR21, .ToReg: 53U },
1035 { .FromReg: LoongArch::VR22, .ToReg: 54U },
1036 { .FromReg: LoongArch::VR23, .ToReg: 55U },
1037 { .FromReg: LoongArch::VR24, .ToReg: 56U },
1038 { .FromReg: LoongArch::VR25, .ToReg: 57U },
1039 { .FromReg: LoongArch::VR26, .ToReg: 58U },
1040 { .FromReg: LoongArch::VR27, .ToReg: 59U },
1041 { .FromReg: LoongArch::VR28, .ToReg: 60U },
1042 { .FromReg: LoongArch::VR29, .ToReg: 61U },
1043 { .FromReg: LoongArch::VR30, .ToReg: 62U },
1044 { .FromReg: LoongArch::VR31, .ToReg: 63U },
1045 { .FromReg: LoongArch::XR0, .ToReg: 32U },
1046 { .FromReg: LoongArch::XR1, .ToReg: 33U },
1047 { .FromReg: LoongArch::XR2, .ToReg: 34U },
1048 { .FromReg: LoongArch::XR3, .ToReg: 35U },
1049 { .FromReg: LoongArch::XR4, .ToReg: 36U },
1050 { .FromReg: LoongArch::XR5, .ToReg: 37U },
1051 { .FromReg: LoongArch::XR6, .ToReg: 38U },
1052 { .FromReg: LoongArch::XR7, .ToReg: 39U },
1053 { .FromReg: LoongArch::XR8, .ToReg: 40U },
1054 { .FromReg: LoongArch::XR9, .ToReg: 41U },
1055 { .FromReg: LoongArch::XR10, .ToReg: 42U },
1056 { .FromReg: LoongArch::XR11, .ToReg: 43U },
1057 { .FromReg: LoongArch::XR12, .ToReg: 44U },
1058 { .FromReg: LoongArch::XR13, .ToReg: 45U },
1059 { .FromReg: LoongArch::XR14, .ToReg: 46U },
1060 { .FromReg: LoongArch::XR15, .ToReg: 47U },
1061 { .FromReg: LoongArch::XR16, .ToReg: 48U },
1062 { .FromReg: LoongArch::XR17, .ToReg: 49U },
1063 { .FromReg: LoongArch::XR18, .ToReg: 50U },
1064 { .FromReg: LoongArch::XR19, .ToReg: 51U },
1065 { .FromReg: LoongArch::XR20, .ToReg: 52U },
1066 { .FromReg: LoongArch::XR21, .ToReg: 53U },
1067 { .FromReg: LoongArch::XR22, .ToReg: 54U },
1068 { .FromReg: LoongArch::XR23, .ToReg: 55U },
1069 { .FromReg: LoongArch::XR24, .ToReg: 56U },
1070 { .FromReg: LoongArch::XR25, .ToReg: 57U },
1071 { .FromReg: LoongArch::XR26, .ToReg: 58U },
1072 { .FromReg: LoongArch::XR27, .ToReg: 59U },
1073 { .FromReg: LoongArch::XR28, .ToReg: 60U },
1074 { .FromReg: LoongArch::XR29, .ToReg: 61U },
1075 { .FromReg: LoongArch::XR30, .ToReg: 62U },
1076 { .FromReg: LoongArch::XR31, .ToReg: 63U },
1077 { .FromReg: LoongArch::F0_64, .ToReg: 32U },
1078 { .FromReg: LoongArch::F1_64, .ToReg: 33U },
1079 { .FromReg: LoongArch::F2_64, .ToReg: 34U },
1080 { .FromReg: LoongArch::F3_64, .ToReg: 35U },
1081 { .FromReg: LoongArch::F4_64, .ToReg: 36U },
1082 { .FromReg: LoongArch::F5_64, .ToReg: 37U },
1083 { .FromReg: LoongArch::F6_64, .ToReg: 38U },
1084 { .FromReg: LoongArch::F7_64, .ToReg: 39U },
1085 { .FromReg: LoongArch::F8_64, .ToReg: 40U },
1086 { .FromReg: LoongArch::F9_64, .ToReg: 41U },
1087 { .FromReg: LoongArch::F10_64, .ToReg: 42U },
1088 { .FromReg: LoongArch::F11_64, .ToReg: 43U },
1089 { .FromReg: LoongArch::F12_64, .ToReg: 44U },
1090 { .FromReg: LoongArch::F13_64, .ToReg: 45U },
1091 { .FromReg: LoongArch::F14_64, .ToReg: 46U },
1092 { .FromReg: LoongArch::F15_64, .ToReg: 47U },
1093 { .FromReg: LoongArch::F16_64, .ToReg: 48U },
1094 { .FromReg: LoongArch::F17_64, .ToReg: 49U },
1095 { .FromReg: LoongArch::F18_64, .ToReg: 50U },
1096 { .FromReg: LoongArch::F19_64, .ToReg: 51U },
1097 { .FromReg: LoongArch::F20_64, .ToReg: 52U },
1098 { .FromReg: LoongArch::F21_64, .ToReg: 53U },
1099 { .FromReg: LoongArch::F22_64, .ToReg: 54U },
1100 { .FromReg: LoongArch::F23_64, .ToReg: 55U },
1101 { .FromReg: LoongArch::F24_64, .ToReg: 56U },
1102 { .FromReg: LoongArch::F25_64, .ToReg: 57U },
1103 { .FromReg: LoongArch::F26_64, .ToReg: 58U },
1104 { .FromReg: LoongArch::F27_64, .ToReg: 59U },
1105 { .FromReg: LoongArch::F28_64, .ToReg: 60U },
1106 { .FromReg: LoongArch::F29_64, .ToReg: 61U },
1107 { .FromReg: LoongArch::F30_64, .ToReg: 62U },
1108 { .FromReg: LoongArch::F31_64, .ToReg: 63U },
1109};
1110extern const unsigned LoongArchDwarfFlavour0L2DwarfSize = std::size(LoongArchDwarfFlavour0L2Dwarf);
1111
1112extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[] = {
1113 { .FromReg: LoongArch::F0, .ToReg: 32U },
1114 { .FromReg: LoongArch::F1, .ToReg: 33U },
1115 { .FromReg: LoongArch::F2, .ToReg: 34U },
1116 { .FromReg: LoongArch::F3, .ToReg: 35U },
1117 { .FromReg: LoongArch::F4, .ToReg: 36U },
1118 { .FromReg: LoongArch::F5, .ToReg: 37U },
1119 { .FromReg: LoongArch::F6, .ToReg: 38U },
1120 { .FromReg: LoongArch::F7, .ToReg: 39U },
1121 { .FromReg: LoongArch::F8, .ToReg: 40U },
1122 { .FromReg: LoongArch::F9, .ToReg: 41U },
1123 { .FromReg: LoongArch::F10, .ToReg: 42U },
1124 { .FromReg: LoongArch::F11, .ToReg: 43U },
1125 { .FromReg: LoongArch::F12, .ToReg: 44U },
1126 { .FromReg: LoongArch::F13, .ToReg: 45U },
1127 { .FromReg: LoongArch::F14, .ToReg: 46U },
1128 { .FromReg: LoongArch::F15, .ToReg: 47U },
1129 { .FromReg: LoongArch::F16, .ToReg: 48U },
1130 { .FromReg: LoongArch::F17, .ToReg: 49U },
1131 { .FromReg: LoongArch::F18, .ToReg: 50U },
1132 { .FromReg: LoongArch::F19, .ToReg: 51U },
1133 { .FromReg: LoongArch::F20, .ToReg: 52U },
1134 { .FromReg: LoongArch::F21, .ToReg: 53U },
1135 { .FromReg: LoongArch::F22, .ToReg: 54U },
1136 { .FromReg: LoongArch::F23, .ToReg: 55U },
1137 { .FromReg: LoongArch::F24, .ToReg: 56U },
1138 { .FromReg: LoongArch::F25, .ToReg: 57U },
1139 { .FromReg: LoongArch::F26, .ToReg: 58U },
1140 { .FromReg: LoongArch::F27, .ToReg: 59U },
1141 { .FromReg: LoongArch::F28, .ToReg: 60U },
1142 { .FromReg: LoongArch::F29, .ToReg: 61U },
1143 { .FromReg: LoongArch::F30, .ToReg: 62U },
1144 { .FromReg: LoongArch::F31, .ToReg: 63U },
1145 { .FromReg: LoongArch::R0, .ToReg: 0U },
1146 { .FromReg: LoongArch::R1, .ToReg: 1U },
1147 { .FromReg: LoongArch::R2, .ToReg: 2U },
1148 { .FromReg: LoongArch::R3, .ToReg: 3U },
1149 { .FromReg: LoongArch::R4, .ToReg: 4U },
1150 { .FromReg: LoongArch::R5, .ToReg: 5U },
1151 { .FromReg: LoongArch::R6, .ToReg: 6U },
1152 { .FromReg: LoongArch::R7, .ToReg: 7U },
1153 { .FromReg: LoongArch::R8, .ToReg: 8U },
1154 { .FromReg: LoongArch::R9, .ToReg: 9U },
1155 { .FromReg: LoongArch::R10, .ToReg: 10U },
1156 { .FromReg: LoongArch::R11, .ToReg: 11U },
1157 { .FromReg: LoongArch::R12, .ToReg: 12U },
1158 { .FromReg: LoongArch::R13, .ToReg: 13U },
1159 { .FromReg: LoongArch::R14, .ToReg: 14U },
1160 { .FromReg: LoongArch::R15, .ToReg: 15U },
1161 { .FromReg: LoongArch::R16, .ToReg: 16U },
1162 { .FromReg: LoongArch::R17, .ToReg: 17U },
1163 { .FromReg: LoongArch::R18, .ToReg: 18U },
1164 { .FromReg: LoongArch::R19, .ToReg: 19U },
1165 { .FromReg: LoongArch::R20, .ToReg: 20U },
1166 { .FromReg: LoongArch::R21, .ToReg: 21U },
1167 { .FromReg: LoongArch::R22, .ToReg: 22U },
1168 { .FromReg: LoongArch::R23, .ToReg: 23U },
1169 { .FromReg: LoongArch::R24, .ToReg: 24U },
1170 { .FromReg: LoongArch::R25, .ToReg: 25U },
1171 { .FromReg: LoongArch::R26, .ToReg: 26U },
1172 { .FromReg: LoongArch::R27, .ToReg: 27U },
1173 { .FromReg: LoongArch::R28, .ToReg: 28U },
1174 { .FromReg: LoongArch::R29, .ToReg: 29U },
1175 { .FromReg: LoongArch::R30, .ToReg: 30U },
1176 { .FromReg: LoongArch::R31, .ToReg: 31U },
1177 { .FromReg: LoongArch::VR0, .ToReg: 32U },
1178 { .FromReg: LoongArch::VR1, .ToReg: 33U },
1179 { .FromReg: LoongArch::VR2, .ToReg: 34U },
1180 { .FromReg: LoongArch::VR3, .ToReg: 35U },
1181 { .FromReg: LoongArch::VR4, .ToReg: 36U },
1182 { .FromReg: LoongArch::VR5, .ToReg: 37U },
1183 { .FromReg: LoongArch::VR6, .ToReg: 38U },
1184 { .FromReg: LoongArch::VR7, .ToReg: 39U },
1185 { .FromReg: LoongArch::VR8, .ToReg: 40U },
1186 { .FromReg: LoongArch::VR9, .ToReg: 41U },
1187 { .FromReg: LoongArch::VR10, .ToReg: 42U },
1188 { .FromReg: LoongArch::VR11, .ToReg: 43U },
1189 { .FromReg: LoongArch::VR12, .ToReg: 44U },
1190 { .FromReg: LoongArch::VR13, .ToReg: 45U },
1191 { .FromReg: LoongArch::VR14, .ToReg: 46U },
1192 { .FromReg: LoongArch::VR15, .ToReg: 47U },
1193 { .FromReg: LoongArch::VR16, .ToReg: 48U },
1194 { .FromReg: LoongArch::VR17, .ToReg: 49U },
1195 { .FromReg: LoongArch::VR18, .ToReg: 50U },
1196 { .FromReg: LoongArch::VR19, .ToReg: 51U },
1197 { .FromReg: LoongArch::VR20, .ToReg: 52U },
1198 { .FromReg: LoongArch::VR21, .ToReg: 53U },
1199 { .FromReg: LoongArch::VR22, .ToReg: 54U },
1200 { .FromReg: LoongArch::VR23, .ToReg: 55U },
1201 { .FromReg: LoongArch::VR24, .ToReg: 56U },
1202 { .FromReg: LoongArch::VR25, .ToReg: 57U },
1203 { .FromReg: LoongArch::VR26, .ToReg: 58U },
1204 { .FromReg: LoongArch::VR27, .ToReg: 59U },
1205 { .FromReg: LoongArch::VR28, .ToReg: 60U },
1206 { .FromReg: LoongArch::VR29, .ToReg: 61U },
1207 { .FromReg: LoongArch::VR30, .ToReg: 62U },
1208 { .FromReg: LoongArch::VR31, .ToReg: 63U },
1209 { .FromReg: LoongArch::XR0, .ToReg: 32U },
1210 { .FromReg: LoongArch::XR1, .ToReg: 33U },
1211 { .FromReg: LoongArch::XR2, .ToReg: 34U },
1212 { .FromReg: LoongArch::XR3, .ToReg: 35U },
1213 { .FromReg: LoongArch::XR4, .ToReg: 36U },
1214 { .FromReg: LoongArch::XR5, .ToReg: 37U },
1215 { .FromReg: LoongArch::XR6, .ToReg: 38U },
1216 { .FromReg: LoongArch::XR7, .ToReg: 39U },
1217 { .FromReg: LoongArch::XR8, .ToReg: 40U },
1218 { .FromReg: LoongArch::XR9, .ToReg: 41U },
1219 { .FromReg: LoongArch::XR10, .ToReg: 42U },
1220 { .FromReg: LoongArch::XR11, .ToReg: 43U },
1221 { .FromReg: LoongArch::XR12, .ToReg: 44U },
1222 { .FromReg: LoongArch::XR13, .ToReg: 45U },
1223 { .FromReg: LoongArch::XR14, .ToReg: 46U },
1224 { .FromReg: LoongArch::XR15, .ToReg: 47U },
1225 { .FromReg: LoongArch::XR16, .ToReg: 48U },
1226 { .FromReg: LoongArch::XR17, .ToReg: 49U },
1227 { .FromReg: LoongArch::XR18, .ToReg: 50U },
1228 { .FromReg: LoongArch::XR19, .ToReg: 51U },
1229 { .FromReg: LoongArch::XR20, .ToReg: 52U },
1230 { .FromReg: LoongArch::XR21, .ToReg: 53U },
1231 { .FromReg: LoongArch::XR22, .ToReg: 54U },
1232 { .FromReg: LoongArch::XR23, .ToReg: 55U },
1233 { .FromReg: LoongArch::XR24, .ToReg: 56U },
1234 { .FromReg: LoongArch::XR25, .ToReg: 57U },
1235 { .FromReg: LoongArch::XR26, .ToReg: 58U },
1236 { .FromReg: LoongArch::XR27, .ToReg: 59U },
1237 { .FromReg: LoongArch::XR28, .ToReg: 60U },
1238 { .FromReg: LoongArch::XR29, .ToReg: 61U },
1239 { .FromReg: LoongArch::XR30, .ToReg: 62U },
1240 { .FromReg: LoongArch::XR31, .ToReg: 63U },
1241 { .FromReg: LoongArch::F0_64, .ToReg: 32U },
1242 { .FromReg: LoongArch::F1_64, .ToReg: 33U },
1243 { .FromReg: LoongArch::F2_64, .ToReg: 34U },
1244 { .FromReg: LoongArch::F3_64, .ToReg: 35U },
1245 { .FromReg: LoongArch::F4_64, .ToReg: 36U },
1246 { .FromReg: LoongArch::F5_64, .ToReg: 37U },
1247 { .FromReg: LoongArch::F6_64, .ToReg: 38U },
1248 { .FromReg: LoongArch::F7_64, .ToReg: 39U },
1249 { .FromReg: LoongArch::F8_64, .ToReg: 40U },
1250 { .FromReg: LoongArch::F9_64, .ToReg: 41U },
1251 { .FromReg: LoongArch::F10_64, .ToReg: 42U },
1252 { .FromReg: LoongArch::F11_64, .ToReg: 43U },
1253 { .FromReg: LoongArch::F12_64, .ToReg: 44U },
1254 { .FromReg: LoongArch::F13_64, .ToReg: 45U },
1255 { .FromReg: LoongArch::F14_64, .ToReg: 46U },
1256 { .FromReg: LoongArch::F15_64, .ToReg: 47U },
1257 { .FromReg: LoongArch::F16_64, .ToReg: 48U },
1258 { .FromReg: LoongArch::F17_64, .ToReg: 49U },
1259 { .FromReg: LoongArch::F18_64, .ToReg: 50U },
1260 { .FromReg: LoongArch::F19_64, .ToReg: 51U },
1261 { .FromReg: LoongArch::F20_64, .ToReg: 52U },
1262 { .FromReg: LoongArch::F21_64, .ToReg: 53U },
1263 { .FromReg: LoongArch::F22_64, .ToReg: 54U },
1264 { .FromReg: LoongArch::F23_64, .ToReg: 55U },
1265 { .FromReg: LoongArch::F24_64, .ToReg: 56U },
1266 { .FromReg: LoongArch::F25_64, .ToReg: 57U },
1267 { .FromReg: LoongArch::F26_64, .ToReg: 58U },
1268 { .FromReg: LoongArch::F27_64, .ToReg: 59U },
1269 { .FromReg: LoongArch::F28_64, .ToReg: 60U },
1270 { .FromReg: LoongArch::F29_64, .ToReg: 61U },
1271 { .FromReg: LoongArch::F30_64, .ToReg: 62U },
1272 { .FromReg: LoongArch::F31_64, .ToReg: 63U },
1273};
1274extern const unsigned LoongArchEHFlavour0L2DwarfSize = std::size(LoongArchEHFlavour0L2Dwarf);
1275
1276extern const uint16_t LoongArchRegEncodingTable[] = {
1277 0,
1278 0,
1279 1,
1280 2,
1281 3,
1282 4,
1283 5,
1284 6,
1285 7,
1286 8,
1287 9,
1288 10,
1289 11,
1290 12,
1291 13,
1292 14,
1293 15,
1294 16,
1295 17,
1296 18,
1297 19,
1298 20,
1299 21,
1300 22,
1301 23,
1302 24,
1303 25,
1304 26,
1305 27,
1306 28,
1307 29,
1308 30,
1309 31,
1310 0,
1311 1,
1312 2,
1313 3,
1314 4,
1315 5,
1316 6,
1317 7,
1318 0,
1319 1,
1320 2,
1321 3,
1322 0,
1323 1,
1324 2,
1325 3,
1326 4,
1327 5,
1328 6,
1329 7,
1330 8,
1331 9,
1332 10,
1333 11,
1334 12,
1335 13,
1336 14,
1337 15,
1338 16,
1339 17,
1340 18,
1341 19,
1342 20,
1343 21,
1344 22,
1345 23,
1346 24,
1347 25,
1348 26,
1349 27,
1350 28,
1351 29,
1352 30,
1353 31,
1354 0,
1355 1,
1356 2,
1357 3,
1358 0,
1359 1,
1360 2,
1361 3,
1362 4,
1363 5,
1364 6,
1365 7,
1366 8,
1367 9,
1368 10,
1369 11,
1370 12,
1371 13,
1372 14,
1373 15,
1374 16,
1375 17,
1376 18,
1377 19,
1378 20,
1379 21,
1380 22,
1381 23,
1382 24,
1383 25,
1384 26,
1385 27,
1386 28,
1387 29,
1388 30,
1389 31,
1390 0,
1391 1,
1392 2,
1393 3,
1394 4,
1395 5,
1396 6,
1397 7,
1398 8,
1399 9,
1400 10,
1401 11,
1402 12,
1403 13,
1404 14,
1405 15,
1406 16,
1407 17,
1408 18,
1409 19,
1410 20,
1411 21,
1412 22,
1413 23,
1414 24,
1415 25,
1416 26,
1417 27,
1418 28,
1419 29,
1420 30,
1421 31,
1422 0,
1423 1,
1424 2,
1425 3,
1426 4,
1427 5,
1428 6,
1429 7,
1430 8,
1431 9,
1432 10,
1433 11,
1434 12,
1435 13,
1436 14,
1437 15,
1438 16,
1439 17,
1440 18,
1441 19,
1442 20,
1443 21,
1444 22,
1445 23,
1446 24,
1447 25,
1448 26,
1449 27,
1450 28,
1451 29,
1452 30,
1453 31,
1454};
1455static inline void InitLoongArchMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1456 RI->InitMCRegisterInfo(D: LoongArchRegDesc, NR: 177, RA, PC, C: LoongArchMCRegisterClassStorage.Classes, NC: 11, RURoots: LoongArchRegUnitRoots, NRU: 80, DL: LoongArchRegDiffLists, RUMS: LoongArchLaneMaskLists, Strings: LoongArchRegStrings, ClassStrings: LoongArchRegClassStrings, SubIndices: LoongArchSubRegIdxLists, NumIndices: 4,
1457RET: LoongArchRegEncodingTable, RUI: nullptr);
1458
1459 switch (DwarfFlavour) {
1460 default:
1461 llvm_unreachable("Unknown DWARF flavour");
1462 case 0:
1463 RI->mapDwarfRegsToLLVMRegs(Map: LoongArchDwarfFlavour0Dwarf2L, Size: LoongArchDwarfFlavour0Dwarf2LSize, isEH: false);
1464 break;
1465 }
1466 switch (EHFlavour) {
1467 default:
1468 llvm_unreachable("Unknown DWARF flavour");
1469 case 0:
1470 RI->mapDwarfRegsToLLVMRegs(Map: LoongArchEHFlavour0Dwarf2L, Size: LoongArchEHFlavour0Dwarf2LSize, isEH: true);
1471 break;
1472 }
1473 switch (DwarfFlavour) {
1474 default:
1475 llvm_unreachable("Unknown DWARF flavour");
1476 case 0:
1477 RI->mapLLVMRegsToDwarfRegs(Map: LoongArchDwarfFlavour0L2Dwarf, Size: LoongArchDwarfFlavour0L2DwarfSize, isEH: false);
1478 break;
1479 }
1480 switch (EHFlavour) {
1481 default:
1482 llvm_unreachable("Unknown DWARF flavour");
1483 case 0:
1484 RI->mapLLVMRegsToDwarfRegs(Map: LoongArchEHFlavour0L2Dwarf, Size: LoongArchEHFlavour0L2DwarfSize, isEH: true);
1485 break;
1486 }
1487}
1488
1489
1490} // namespace llvm
1491