1//===-- LoongArchMCTargetDesc.cpp - LoongArch Target Descriptions ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides LoongArch specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "LoongArchMCTargetDesc.h"
14#include "LoongArchELFStreamer.h"
15#include "LoongArchInstPrinter.h"
16#include "LoongArchMCAsmInfo.h"
17#include "TargetInfo/LoongArchTargetInfo.h"
18#include "llvm/MC/MCAsmBackend.h"
19#include "llvm/MC/MCAsmInfo.h"
20#include "llvm/MC/MCCodeEmitter.h"
21#include "llvm/MC/MCDwarf.h"
22#include "llvm/MC/MCInstrAnalysis.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCObjectWriter.h"
25#include "llvm/MC/MCRegisterInfo.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/MC/TargetRegistry.h"
28#include "llvm/Support/Compiler.h"
29#include <bitset>
30
31#define GET_INSTRINFO_MC_DESC
32#define ENABLE_INSTR_PREDICATE_VERIFIER
33#include "LoongArchGenInstrInfo.inc"
34
35#define GET_REGINFO_MC_DESC
36#include "LoongArchGenRegisterInfo.inc"
37
38#define GET_SUBTARGETINFO_MC_DESC
39#include "LoongArchGenSubtargetInfo.inc"
40
41using namespace llvm;
42
43static MCRegisterInfo *createLoongArchMCRegisterInfo(const Triple &TT) {
44 MCRegisterInfo *X = new MCRegisterInfo();
45 InitLoongArchMCRegisterInfo(RI: X, RA: LoongArch::R1);
46 return X;
47}
48
49static MCInstrInfo *createLoongArchMCInstrInfo() {
50 MCInstrInfo *X = new MCInstrInfo();
51 InitLoongArchMCInstrInfo(II: X);
52 return X;
53}
54
55static MCSubtargetInfo *
56createLoongArchMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
57 if (CPU.empty() || CPU == "generic")
58 CPU = TT.isArch64Bit() ? "generic-la64" : "generic-la32";
59 return createLoongArchMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
60}
61
62static MCAsmInfo *createLoongArchMCAsmInfo(const MCRegisterInfo &MRI,
63 const Triple &TT,
64 const MCTargetOptions &Options) {
65 MCAsmInfo *MAI = new LoongArchMCAsmInfo(TT);
66
67 // Initial state of the frame pointer is sp(r3).
68 unsigned SP = MRI.getDwarfRegNum(Reg: LoongArch::R3, isEH: true);
69 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(L: nullptr, Register: SP, Offset: 0);
70 MAI->addInitialFrameState(Inst);
71
72 return MAI;
73}
74
75static MCInstPrinter *createLoongArchMCInstPrinter(const Triple &T,
76 unsigned SyntaxVariant,
77 const MCAsmInfo &MAI,
78 const MCInstrInfo &MII,
79 const MCRegisterInfo &MRI) {
80 return new LoongArchInstPrinter(MAI, MII, MRI);
81}
82
83static MCTargetStreamer *
84createLoongArchObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
85 return STI.getTargetTriple().isOSBinFormatELF()
86 ? new LoongArchTargetELFStreamer(S, STI)
87 : nullptr;
88}
89
90static MCTargetStreamer *
91createLoongArchAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
92 MCInstPrinter *InstPrint) {
93 return new LoongArchTargetAsmStreamer(S, OS);
94}
95
96namespace {
97
98class LoongArchMCInstrAnalysis : public MCInstrAnalysis {
99 int64_t GPRState[31] = {};
100 std::bitset<31> GPRValidMask;
101
102 static bool isGPR(MCRegister Reg) {
103 return Reg >= LoongArch::R0 && Reg <= LoongArch::R31;
104 }
105
106 static unsigned getRegIndex(MCRegister Reg) {
107 assert(isGPR(Reg) && Reg != LoongArch::R0 && "Invalid GPR reg");
108 return Reg - LoongArch::R1;
109 }
110
111 void setGPRState(MCRegister Reg, std::optional<int64_t> Value) {
112 if (Reg == LoongArch::R0)
113 return;
114
115 auto Index = getRegIndex(Reg);
116
117 if (Value) {
118 GPRState[Index] = *Value;
119 GPRValidMask.set(position: Index);
120 } else {
121 GPRValidMask.reset(position: Index);
122 }
123 }
124
125 std::optional<int64_t> getGPRState(MCRegister Reg) const {
126 if (Reg == LoongArch::R0)
127 return 0;
128
129 auto Index = getRegIndex(Reg);
130
131 if (GPRValidMask.test(position: Index))
132 return GPRState[Index];
133 return std::nullopt;
134 }
135
136public:
137 explicit LoongArchMCInstrAnalysis(const MCInstrInfo *Info)
138 : MCInstrAnalysis(Info) {}
139
140 void resetState() override { GPRValidMask.reset(); }
141
142 void updateState(const MCInst &Inst, const MCSubtargetInfo *STI,
143 uint64_t Addr) override {
144 // Terminators mark the end of a basic block which means the sequentially
145 // next instruction will be the first of another basic block and the current
146 // state will typically not be valid anymore. For calls, we assume all
147 // registers may be clobbered by the callee (TODO: should we take the
148 // calling convention into account?).
149 if (isTerminator(Inst) || isCall(Inst)) {
150 resetState();
151 return;
152 }
153
154 switch (Inst.getOpcode()) {
155 default: {
156 // Clear the state of all defined registers for instructions that we don't
157 // explicitly support.
158 auto NumDefs = Info->get(Opcode: Inst.getOpcode()).getNumDefs();
159 for (unsigned I = 0; I < NumDefs; ++I) {
160 auto DefReg = Inst.getOperand(i: I).getReg();
161 if (isGPR(Reg: DefReg))
162 setGPRState(Reg: DefReg, Value: std::nullopt);
163 }
164 break;
165 }
166 case LoongArch::PCADDU18I:
167 setGPRState(
168 Reg: Inst.getOperand(i: 0).getReg(),
169 Value: Addr + SignExtend64<38>(
170 x: static_cast<uint64_t>(Inst.getOperand(i: 1).getImm()) << 18));
171 break;
172 }
173 }
174
175 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
176 uint64_t &Target) const override {
177 unsigned NumOps = Inst.getNumOperands();
178 if ((isBranch(Inst) && !isIndirectBranch(Inst)) ||
179 Inst.getOpcode() == LoongArch::BL) {
180 Target = Addr + Inst.getOperand(i: NumOps - 1).getImm();
181 return true;
182 }
183
184 if (Inst.getOpcode() == LoongArch::JIRL) {
185 if (auto TargetRegState = getGPRState(Reg: Inst.getOperand(i: 1).getReg())) {
186 Target = *TargetRegState + Inst.getOperand(i: 2).getImm();
187 return true;
188 }
189 return false;
190 }
191
192 return false;
193 }
194
195 bool isTerminator(const MCInst &Inst) const override {
196 if (MCInstrAnalysis::isTerminator(Inst))
197 return true;
198
199 switch (Inst.getOpcode()) {
200 default:
201 return false;
202 case LoongArch::JIRL:
203 return Inst.getOperand(i: 0).getReg() == LoongArch::R0;
204 }
205 }
206
207 bool isCall(const MCInst &Inst) const override {
208 if (MCInstrAnalysis::isCall(Inst))
209 return true;
210
211 switch (Inst.getOpcode()) {
212 default:
213 return false;
214 case LoongArch::JIRL:
215 return Inst.getOperand(i: 0).getReg() != LoongArch::R0;
216 }
217 }
218
219 bool isReturn(const MCInst &Inst) const override {
220 if (MCInstrAnalysis::isReturn(Inst))
221 return true;
222
223 switch (Inst.getOpcode()) {
224 default:
225 return false;
226 case LoongArch::JIRL:
227 return Inst.getOperand(i: 0).getReg() == LoongArch::R0 &&
228 Inst.getOperand(i: 1).getReg() == LoongArch::R1;
229 }
230 }
231
232 bool isBranch(const MCInst &Inst) const override {
233 if (MCInstrAnalysis::isBranch(Inst))
234 return true;
235
236 switch (Inst.getOpcode()) {
237 default:
238 return false;
239 case LoongArch::JIRL:
240 return Inst.getOperand(i: 0).getReg() == LoongArch::R0 &&
241 Inst.getOperand(i: 1).getReg() != LoongArch::R1;
242 }
243 }
244
245 bool isUnconditionalBranch(const MCInst &Inst) const override {
246 if (MCInstrAnalysis::isUnconditionalBranch(Inst))
247 return true;
248
249 switch (Inst.getOpcode()) {
250 default:
251 return false;
252 case LoongArch::JIRL:
253 return Inst.getOperand(i: 0).getReg() == LoongArch::R0 &&
254 Inst.getOperand(i: 1).getReg() != LoongArch::R1;
255 }
256 }
257
258 bool isIndirectBranch(const MCInst &Inst) const override {
259 if (MCInstrAnalysis::isIndirectBranch(Inst))
260 return true;
261
262 switch (Inst.getOpcode()) {
263 default:
264 return false;
265 case LoongArch::JIRL:
266 return Inst.getOperand(i: 0).getReg() == LoongArch::R0 &&
267 Inst.getOperand(i: 1).getReg() != LoongArch::R1;
268 }
269 }
270};
271
272} // end namespace
273
274static MCInstrAnalysis *createLoongArchInstrAnalysis(const MCInstrInfo *Info) {
275 return new LoongArchMCInstrAnalysis(Info);
276}
277
278namespace {
279MCStreamer *createLoongArchELFStreamer(const Triple &T, MCContext &Context,
280 std::unique_ptr<MCAsmBackend> &&MAB,
281 std::unique_ptr<MCObjectWriter> &&MOW,
282 std::unique_ptr<MCCodeEmitter> &&MCE) {
283 return createLoongArchELFStreamer(C&: Context, MAB: std::move(MAB), MOW: std::move(MOW),
284 MCE: std::move(MCE));
285}
286} // end namespace
287
288extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
289LLVMInitializeLoongArchTargetMC() {
290 for (Target *T : {&getTheLoongArch32Target(), &getTheLoongArch64Target()}) {
291 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createLoongArchMCRegisterInfo);
292 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createLoongArchMCInstrInfo);
293 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createLoongArchMCSubtargetInfo);
294 TargetRegistry::RegisterMCAsmInfo(T&: *T, Fn: createLoongArchMCAsmInfo);
295 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createLoongArchMCCodeEmitter);
296 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createLoongArchAsmBackend);
297 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createLoongArchMCInstPrinter);
298 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createLoongArchInstrAnalysis);
299 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createLoongArchELFStreamer);
300 TargetRegistry::RegisterObjectTargetStreamer(
301 T&: *T, Fn: createLoongArchObjectTargetStreamer);
302 TargetRegistry::RegisterAsmTargetStreamer(T&: *T,
303 Fn: createLoongArchAsmTargetStreamer);
304 }
305}
306