1//===-- LoongArchMCTargetDesc.cpp - LoongArch Target Descriptions ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides LoongArch specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "LoongArchMCTargetDesc.h"
14#include "LoongArchELFStreamer.h"
15#include "LoongArchInstPrinter.h"
16#include "LoongArchMCAsmInfo.h"
17#include "TargetInfo/LoongArchTargetInfo.h"
18#include "llvm/MC/MCAsmBackend.h"
19#include "llvm/MC/MCAsmInfo.h"
20#include "llvm/MC/MCCodeEmitter.h"
21#include "llvm/MC/MCDwarf.h"
22#include "llvm/MC/MCInstrAnalysis.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCObjectWriter.h"
25#include "llvm/MC/MCRegisterInfo.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/MC/TargetRegistry.h"
28#include "llvm/Support/Compiler.h"
29#include <bitset>
30
31#define GET_INSTRINFO_MC_DESC
32#define ENABLE_INSTR_PREDICATE_VERIFIER
33#include "LoongArchGenInstrInfo.inc"
34
35#define GET_REGINFO_MC_DESC
36#include "LoongArchGenRegisterInfo.inc"
37
38#define GET_SUBTARGETINFO_MC_DESC
39#include "LoongArchGenSubtargetInfo.inc"
40
41using namespace llvm;
42
43static MCRegisterInfo *createLoongArchMCRegisterInfo(const Triple &TT) {
44 MCRegisterInfo *X = new MCRegisterInfo();
45 InitLoongArchMCRegisterInfo(RI: X, RA: LoongArch::R1);
46 return X;
47}
48
49static MCInstrInfo *createLoongArchMCInstrInfo() {
50 MCInstrInfo *X = new MCInstrInfo();
51 InitLoongArchMCInstrInfo(II: X);
52 return X;
53}
54
55static MCSubtargetInfo *
56createLoongArchMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
57 if (CPU.empty() || CPU == "generic")
58 CPU = TT.isArch64Bit() ? "generic-la64" : "generic-la32";
59 return createLoongArchMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
60}
61
62static MCAsmInfo *createLoongArchMCAsmInfo(const MCRegisterInfo &MRI,
63 const Triple &TT,
64 const MCTargetOptions &Options) {
65 MCAsmInfo *MAI = new LoongArchMCAsmInfo(TT, Options);
66
67 // Initial state of the frame pointer is sp(r3).
68 unsigned SP = MRI.getDwarfRegNum(Reg: LoongArch::R3, isEH: true);
69 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(L: nullptr, Register: SP, Offset: 0);
70 MAI->addInitialFrameState(Inst);
71
72 return MAI;
73}
74
75static MCInstPrinter *createLoongArchMCInstPrinter(const Triple &T,
76 unsigned SyntaxVariant,
77 const MCAsmInfo &MAI,
78 const MCInstrInfo &MII,
79 const MCRegisterInfo &MRI) {
80 return new LoongArchInstPrinter(MAI, MII, MRI);
81}
82
83static MCTargetStreamer *
84createLoongArchObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
85 return STI.getTargetTriple().isOSBinFormatELF()
86 ? new LoongArchTargetELFStreamer(S, STI)
87 : nullptr;
88}
89
90static MCTargetStreamer *
91createLoongArchAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
92 MCInstPrinter *InstPrint) {
93 return new LoongArchTargetAsmStreamer(S, OS);
94}
95
96static MCTargetStreamer *createLoongArchNullTargetStreamer(MCStreamer &S) {
97 return new LoongArchTargetStreamer(S);
98}
99
100namespace {
101
102class LoongArchMCInstrAnalysis : public MCInstrAnalysis {
103 int64_t GPRState[31] = {};
104 std::bitset<31> GPRValidMask;
105
106 static bool isGPR(MCRegister Reg) {
107 return Reg >= LoongArch::R0 && Reg <= LoongArch::R31;
108 }
109
110 static unsigned getRegIndex(MCRegister Reg) {
111 assert(isGPR(Reg) && Reg != LoongArch::R0 && "Invalid GPR reg");
112 return Reg - LoongArch::R1;
113 }
114
115 void setGPRState(MCRegister Reg, std::optional<int64_t> Value) {
116 if (Reg == LoongArch::R0)
117 return;
118
119 auto Index = getRegIndex(Reg);
120
121 if (Value) {
122 GPRState[Index] = *Value;
123 GPRValidMask.set(position: Index);
124 } else {
125 GPRValidMask.reset(position: Index);
126 }
127 }
128
129 std::optional<int64_t> getGPRState(MCRegister Reg) const {
130 if (Reg == LoongArch::R0)
131 return 0;
132
133 auto Index = getRegIndex(Reg);
134
135 if (GPRValidMask.test(position: Index))
136 return GPRState[Index];
137 return std::nullopt;
138 }
139
140public:
141 explicit LoongArchMCInstrAnalysis(const MCInstrInfo *Info)
142 : MCInstrAnalysis(Info) {}
143
144 void resetState() override { GPRValidMask.reset(); }
145
146 void updateState(const MCInst &Inst, const MCSubtargetInfo *STI,
147 uint64_t Addr) override {
148 // Terminators mark the end of a basic block which means the sequentially
149 // next instruction will be the first of another basic block and the current
150 // state will typically not be valid anymore. For calls, we assume all
151 // registers may be clobbered by the callee (TODO: should we take the
152 // calling convention into account?).
153 if (isTerminator(Inst) || isCall(Inst)) {
154 resetState();
155 return;
156 }
157
158 switch (Inst.getOpcode()) {
159 default: {
160 // Clear the state of all defined registers for instructions that we don't
161 // explicitly support.
162 auto NumDefs = Info->get(Opcode: Inst.getOpcode()).getNumDefs();
163 for (unsigned I = 0; I < NumDefs; ++I) {
164 auto DefReg = Inst.getOperand(i: I).getReg();
165 if (isGPR(Reg: DefReg))
166 setGPRState(Reg: DefReg, Value: std::nullopt);
167 }
168 break;
169 }
170 case LoongArch::PCADDU18I:
171 setGPRState(
172 Reg: Inst.getOperand(i: 0).getReg(),
173 Value: Addr + SignExtend64<38>(
174 x: static_cast<uint64_t>(Inst.getOperand(i: 1).getImm()) << 18));
175 break;
176 }
177 }
178
179 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
180 uint64_t &Target) const override {
181 unsigned NumOps = Inst.getNumOperands();
182 if ((isBranch(Inst) && !isIndirectBranch(Inst)) ||
183 Inst.getOpcode() == LoongArch::BL) {
184 Target = Addr + Inst.getOperand(i: NumOps - 1).getImm();
185 return true;
186 }
187
188 if (Inst.getOpcode() == LoongArch::JIRL) {
189 if (auto TargetRegState = getGPRState(Reg: Inst.getOperand(i: 1).getReg())) {
190 Target = *TargetRegState + Inst.getOperand(i: 2).getImm();
191 return true;
192 }
193 return false;
194 }
195
196 return false;
197 }
198
199 bool isTerminator(const MCInst &Inst) const override {
200 if (MCInstrAnalysis::isTerminator(Inst))
201 return true;
202
203 switch (Inst.getOpcode()) {
204 default:
205 return false;
206 case LoongArch::JIRL:
207 return Inst.getOperand(i: 0).getReg() == LoongArch::R0;
208 }
209 }
210
211 bool isCall(const MCInst &Inst) const override {
212 if (MCInstrAnalysis::isCall(Inst))
213 return true;
214
215 switch (Inst.getOpcode()) {
216 default:
217 return false;
218 case LoongArch::JIRL:
219 return Inst.getOperand(i: 0).getReg() != LoongArch::R0;
220 }
221 }
222
223 bool isReturn(const MCInst &Inst) const override {
224 if (MCInstrAnalysis::isReturn(Inst))
225 return true;
226
227 switch (Inst.getOpcode()) {
228 default:
229 return false;
230 case LoongArch::JIRL:
231 return Inst.getOperand(i: 0).getReg() == LoongArch::R0 &&
232 Inst.getOperand(i: 1).getReg() == LoongArch::R1;
233 }
234 }
235
236 bool isBranch(const MCInst &Inst) const override {
237 if (MCInstrAnalysis::isBranch(Inst))
238 return true;
239
240 switch (Inst.getOpcode()) {
241 default:
242 return false;
243 case LoongArch::JIRL:
244 return Inst.getOperand(i: 0).getReg() == LoongArch::R0 &&
245 Inst.getOperand(i: 1).getReg() != LoongArch::R1;
246 }
247 }
248
249 bool isUnconditionalBranch(const MCInst &Inst) const override {
250 if (MCInstrAnalysis::isUnconditionalBranch(Inst))
251 return true;
252
253 switch (Inst.getOpcode()) {
254 default:
255 return false;
256 case LoongArch::JIRL:
257 return Inst.getOperand(i: 0).getReg() == LoongArch::R0 &&
258 Inst.getOperand(i: 1).getReg() != LoongArch::R1;
259 }
260 }
261
262 bool isIndirectBranch(const MCInst &Inst) const override {
263 if (MCInstrAnalysis::isIndirectBranch(Inst))
264 return true;
265
266 switch (Inst.getOpcode()) {
267 default:
268 return false;
269 case LoongArch::JIRL:
270 return Inst.getOperand(i: 0).getReg() == LoongArch::R0 &&
271 Inst.getOperand(i: 1).getReg() != LoongArch::R1;
272 }
273 }
274};
275
276} // end namespace
277
278static MCInstrAnalysis *createLoongArchInstrAnalysis(const MCInstrInfo *Info) {
279 return new LoongArchMCInstrAnalysis(Info);
280}
281
282namespace {
283MCStreamer *createLoongArchELFStreamer(const Triple &T, MCContext &Context,
284 std::unique_ptr<MCAsmBackend> &&MAB,
285 std::unique_ptr<MCObjectWriter> &&MOW,
286 std::unique_ptr<MCCodeEmitter> &&MCE) {
287 return createLoongArchELFStreamer(C&: Context, MAB: std::move(MAB), MOW: std::move(MOW),
288 MCE: std::move(MCE));
289}
290} // end namespace
291
292extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
293LLVMInitializeLoongArchTargetMC() {
294 for (Target *T : {&getTheLoongArch32Target(), &getTheLoongArch64Target()}) {
295 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createLoongArchMCRegisterInfo);
296 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createLoongArchMCInstrInfo);
297 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createLoongArchMCSubtargetInfo);
298 TargetRegistry::RegisterMCAsmInfo(T&: *T, Fn: createLoongArchMCAsmInfo);
299 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createLoongArchMCCodeEmitter);
300 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createLoongArchAsmBackend);
301 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createLoongArchMCInstPrinter);
302 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createLoongArchInstrAnalysis);
303 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createLoongArchELFStreamer);
304 TargetRegistry::RegisterObjectTargetStreamer(
305 T&: *T, Fn: createLoongArchObjectTargetStreamer);
306 TargetRegistry::RegisterAsmTargetStreamer(T&: *T,
307 Fn: createLoongArchAsmTargetStreamer);
308 TargetRegistry::RegisterNullTargetStreamer(
309 T&: *T, Fn: createLoongArchNullTargetStreamer);
310 }
311}
312