1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<2, 32, 7, 3, 2, 0> MSP430MCRegisterClassStorage;
12
13static const MVT::SimpleValueType MSP430VTLists[] = {
14 /* 0 */ MVT::i8, MVT::Other,
15 /* 2 */ MVT::i16, MVT::Other,
16};
17
18#ifdef __GNUC__
19#pragma GCC diagnostic push
20#pragma GCC diagnostic ignored "-Woverlength-strings"
21#endif
22static constexpr char MSP430SubRegIndexStrings[] = {
23 /* 0 */ "subreg_8bit\000"
24};
25#ifdef __GNUC__
26#pragma GCC diagnostic pop
27#endif
28
29
30static constexpr uint32_t MSP430SubRegIndexNameOffsets[] = {
31 0,
32};
33
34static const TargetRegisterInfo::SubRegCoveredBits MSP430SubRegIdxRangeTable[] = {
35 { .Offset: 4294967295, .Size: 4294967295 },
36 { .Offset: 0, .Size: 8 }, // subreg_8bit
37};
38
39
40static const LaneBitmask MSP430SubRegIndexLaneMaskTable[] = {
41 LaneBitmask::getAll(),
42 LaneBitmask(0x0000000000000001), // subreg_8bit
43 };
44
45
46
47static const TargetRegisterInfo::RegClassInfo MSP430RegClassInfos[] = {
48 // Mode = 0 (DefaultMode)
49 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*MSP430VTLists+*/.VTListOffset: 0 }, // GR8
50 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*MSP430VTLists+*/.VTListOffset: 2 }, // GR16
51};
52
53static const uint8_t MSP430CostPerUseTable[] = {
540, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
55
56
57static const bool MSP430InAllocatableClassTable[] = {
58false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
59
60
61static const TargetRegisterInfoDesc MSP430RegInfoDesc = { // Extra Descriptors
62.CostPerUse: MSP430CostPerUseTable, .NumCosts: 1, .InAllocatableClass: MSP430InAllocatableClassTable};
63
64unsigned MSP430GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
65 static const uint8_t Rows[1][1] = {
66 { 0, },
67 };
68
69 --IdxA; assert(IdxA < 1); (void) IdxA;
70 --IdxB; assert(IdxB < 1);
71 return Rows[0][IdxB];
72}
73
74unsigned MSP430GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
75 static const uint8_t Table[1][1] = {
76 { 0, },
77 };
78
79 --IdxA; assert(IdxA < 1);
80 --IdxB; assert(IdxB < 1);
81 return Table[IdxA][IdxB];
82 }
83
84 struct MaskRolOp {
85 LaneBitmask Mask;
86 uint8_t RotateLeft;
87 };
88 static const MaskRolOp LaneMaskComposeSequences[] = {
89 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
90 };
91 static const uint8_t CompositeSequences[] = {
92 0 // to subreg_8bit
93 };
94
95LaneBitmask MSP430GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
96 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
97 LaneBitmask Result;
98 for (const MaskRolOp *Ops =
99 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
100 Ops->Mask.any(); ++Ops) {
101 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
102 if (unsigned S = Ops->RotateLeft)
103 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
104 else
105 Result |= LaneBitmask(M);
106 }
107 return Result;
108}
109
110LaneBitmask MSP430GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
111 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
112 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
113 LaneBitmask Result;
114 for (const MaskRolOp *Ops =
115 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
116 Ops->Mask.any(); ++Ops) {
117 LaneBitmask::Type M = LaneMask.getAsInteger();
118 if (unsigned S = Ops->RotateLeft)
119 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
120 else
121 Result |= LaneBitmask(M);
122 }
123 return Result;
124}
125
126const TargetRegisterClass *MSP430GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
127 static constexpr uint8_t Table[2][1] = {
128 { // GR8
129 0, // subreg_8bit
130 },
131 { // GR16
132 2, // subreg_8bit -> GR16
133 },
134
135 };
136 assert(RC && "Missing regclass");
137 if (!Idx) return RC;
138 --Idx;
139 assert(Idx < 1 && "Bad subreg");
140 unsigned TV = Table[RC->getID()][Idx];
141 return TV ? getRegClass(i: TV - 1) : nullptr;
142}const TargetRegisterClass *MSP430GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
143 static constexpr uint8_t Table[2][1] = {
144 { // GR8
145 0, // GR8:subreg_8bit
146 },
147 { // GR16
148 1, // GR16:subreg_8bit -> GR8
149 },
150
151 };
152 assert(RC && "Missing regclass");
153 if (!Idx) return RC;
154 --Idx;
155 assert(Idx < 1 && "Bad subreg");
156 unsigned TV = Table[RC->getID()][Idx];
157 return TV ? getRegClass(i: TV - 1) : nullptr;
158}/// Get the weight in units of pressure for this register class.
159const RegClassWeight &MSP430GenRegisterInfo::
160getRegClassWeight(const TargetRegisterClass *RC) const {
161 static const RegClassWeight RCWeightTable[] = {
162 {.RegWeight: 1, .WeightLimit: 16}, // GR8
163 {.RegWeight: 1, .WeightLimit: 16}, // GR16
164 };
165 return RCWeightTable[RC->getID()];
166}
167
168/// Get the weight in units of pressure for this register unit.
169unsigned MSP430GenRegisterInfo::
170getRegUnitWeight(MCRegUnit RegUnit) const {
171 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
172 // All register units have unit weight.
173 return 1;
174}
175
176
177// Get the number of dimensions of register pressure.
178unsigned MSP430GenRegisterInfo::getNumRegPressureSets() const {
179 return 1;
180}
181
182// Get the name of this register unit pressure set.
183const char *MSP430GenRegisterInfo::
184getRegPressureSetName(unsigned Idx) const {
185 static const char *PressureNameTable[] = {
186 "GR8",
187 };
188 return PressureNameTable[Idx];
189}
190
191// Get the register unit pressure limit for this dimension.
192// This limit must be adjusted dynamically for reserved registers.
193unsigned MSP430GenRegisterInfo::
194getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
195 static const uint8_t PressureLimitTable[] = {
196 16, // 0: GR8
197 };
198 return PressureLimitTable[Idx];
199}
200
201/// Get the register class for this pressure set with the largest
202/// `RegClassWeight::WeightLimit`.
203const TargetRegisterClass *MSP430GenRegisterInfo::
204getLargestRegClassForRegPressureSet(unsigned Idx) const {
205 static const uint8_t PSetRegClassTable[] = {
206 MSP430::GR8RegClassID, // 0: GR8
207 };
208 return getRegClass(i: PSetRegClassTable[Idx]);
209}
210
211/// Table of pressure sets per register class or unit.
212static const int RCSetsTable[] = {
213 /* 0 */ 0, -1,
214};
215
216/// Get the dimensions of register pressure impacted by this register class.
217/// Returns a -1 terminated array of pressure set IDs
218const int *MSP430GenRegisterInfo::
219getRegClassPressureSets(const TargetRegisterClass *RC) const {
220 static const uint8_t RCSetStartTable[] = {
221 0,0,};
222 return &RCSetsTable[RCSetStartTable[RC->getID()]];
223}
224
225/// Get the dimensions of register pressure impacted by this register unit.
226/// Returns a -1 terminated array of pressure set IDs
227const int *MSP430GenRegisterInfo::
228getRegUnitPressureSets(MCRegUnit RegUnit) const {
229 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
230 static const uint8_t RUSetStartTable[] = {
231 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,};
232 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
233}
234
235
236// Register to minimal register class mapping
237
238const TargetRegisterClass *MSP430GenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
239 static const uint16_t InvalidRegClassID = UINT16_MAX;
240
241 static const uint16_t Mapping[33] = {
242 InvalidRegClassID, // NoRegister
243 MSP430::GR16RegClassID, // CG
244 MSP430::GR8RegClassID, // CGB
245 MSP430::GR16RegClassID, // PC
246 MSP430::GR8RegClassID, // PCB
247 MSP430::GR16RegClassID, // SP
248 MSP430::GR8RegClassID, // SPB
249 MSP430::GR16RegClassID, // SR
250 MSP430::GR8RegClassID, // SRB
251 MSP430::GR16RegClassID, // R4
252 MSP430::GR16RegClassID, // R5
253 MSP430::GR16RegClassID, // R6
254 MSP430::GR16RegClassID, // R7
255 MSP430::GR16RegClassID, // R8
256 MSP430::GR16RegClassID, // R9
257 MSP430::GR16RegClassID, // R10
258 MSP430::GR16RegClassID, // R11
259 MSP430::GR16RegClassID, // R12
260 MSP430::GR16RegClassID, // R13
261 MSP430::GR16RegClassID, // R14
262 MSP430::GR16RegClassID, // R15
263 MSP430::GR8RegClassID, // R4B
264 MSP430::GR8RegClassID, // R5B
265 MSP430::GR8RegClassID, // R6B
266 MSP430::GR8RegClassID, // R7B
267 MSP430::GR8RegClassID, // R8B
268 MSP430::GR8RegClassID, // R9B
269 MSP430::GR8RegClassID, // R10B
270 MSP430::GR8RegClassID, // R11B
271 MSP430::GR8RegClassID, // R12B
272 MSP430::GR8RegClassID, // R13B
273 MSP430::GR8RegClassID, // R14B
274 MSP430::GR8RegClassID, // R15B
275 };
276
277 assert(Reg < ArrayRef(Mapping).size());
278 unsigned RCID = Mapping[Reg.id()];
279 if (RCID == InvalidRegClassID)
280 return nullptr;
281 return &MSP430MCRegisterClassStorage.Classes[RCID];
282}
283extern const MCRegisterDesc MSP430RegDesc[];
284extern const int16_t MSP430RegDiffLists[];
285extern const LaneBitmask MSP430LaneMaskLists[];
286extern const char MSP430RegStrings[];
287extern const char MSP430RegClassStrings[];
288extern const MCPhysReg MSP430RegUnitRoots[][2];
289extern const uint16_t MSP430SubRegIdxLists[];
290extern const uint16_t MSP430RegEncodingTable[];
291// MSP430 Dwarf<->LLVM register mappings.
292extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0Dwarf2L[];
293extern const unsigned MSP430DwarfFlavour0Dwarf2LSize;
294
295extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0Dwarf2L[];
296extern const unsigned MSP430EHFlavour0Dwarf2LSize;
297
298extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0L2Dwarf[];
299extern const unsigned MSP430DwarfFlavour0L2DwarfSize;
300
301extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0L2Dwarf[];
302extern const unsigned MSP430EHFlavour0L2DwarfSize;
303
304
305MSP430GenRegisterInfo::
306MSP430GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
307 unsigned PC, unsigned HwMode)
308 : TargetRegisterInfo(&MSP430RegInfoDesc,
309 MSP430SubRegIndexStrings, MSP430SubRegIndexNameOffsets,
310 MSP430SubRegIdxRangeTable, MSP430SubRegIndexLaneMaskTable,
311
312 LaneBitmask(0xFFFFFFFFFFFFFFFE), MSP430RegClassInfos, MSP430VTLists, HwMode) {
313 InitMCRegisterInfo(D: MSP430RegDesc, NR: 33, RA, PC,
314 C: &getMSP430MCRegisterClass(RC: 0), NC: 2, RURoots: MSP430RegUnitRoots, NRU: 16, DL: MSP430RegDiffLists,
315 RUMS: MSP430LaneMaskLists, Strings: MSP430RegStrings, ClassStrings: MSP430RegClassStrings, SubIndices: MSP430SubRegIdxLists, NumIndices: 2,
316 RET: MSP430RegEncodingTable, RUI: nullptr);
317
318 switch (DwarfFlavour) {
319 default:
320 llvm_unreachable("Unknown DWARF flavour");
321 case 0:
322 mapDwarfRegsToLLVMRegs(Map: MSP430DwarfFlavour0Dwarf2L, Size: MSP430DwarfFlavour0Dwarf2LSize, isEH: false);
323 break;
324 }
325 switch (EHFlavour) {
326 default:
327 llvm_unreachable("Unknown DWARF flavour");
328 case 0:
329 mapDwarfRegsToLLVMRegs(Map: MSP430EHFlavour0Dwarf2L, Size: MSP430EHFlavour0Dwarf2LSize, isEH: true);
330 break;
331 }
332 switch (DwarfFlavour) {
333 default:
334 llvm_unreachable("Unknown DWARF flavour");
335 case 0:
336 mapLLVMRegsToDwarfRegs(Map: MSP430DwarfFlavour0L2Dwarf, Size: MSP430DwarfFlavour0L2DwarfSize, isEH: false);
337 break;
338 }
339 switch (EHFlavour) {
340 default:
341 llvm_unreachable("Unknown DWARF flavour");
342 case 0:
343 mapLLVMRegsToDwarfRegs(Map: MSP430EHFlavour0L2Dwarf, Size: MSP430EHFlavour0L2DwarfSize, isEH: true);
344 break;
345 }
346}
347
348
349
350ArrayRef<const uint32_t *> MSP430GenRegisterInfo::getRegMasks() const {
351 return {};
352}
353
354bool MSP430GenRegisterInfo::
355isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
356 return
357 false;
358}
359
360bool MSP430GenRegisterInfo::
361isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
362 return
363 false;
364}
365
366bool MSP430GenRegisterInfo::
367isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
368 return
369 false;
370}
371
372bool MSP430GenRegisterInfo::
373isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
374 return
375 false;
376}
377
378bool MSP430GenRegisterInfo::
379isConstantPhysReg(MCRegister PhysReg) const {
380 return
381 false;
382}
383
384ArrayRef<const char *> MSP430GenRegisterInfo::getRegMaskNames() const {
385 return {};
386}
387
388const MSP430FrameLowering *
389MSP430GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
390 return static_cast<const MSP430FrameLowering *>(
391 MF.getSubtarget().getFrameLowering());
392}
393
394
395} // namespace llvm
396