1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass MSP430MCRegisterClasses[];
12
13static const MVT::SimpleValueType MSP430VTLists[] = {
14 /* 0 */ MVT::i8, MVT::Other,
15 /* 2 */ MVT::i16, MVT::Other,
16};
17
18#ifdef __GNUC__
19#pragma GCC diagnostic push
20#pragma GCC diagnostic ignored "-Woverlength-strings"
21#endif
22static constexpr char MSP430SubRegIndexStrings[] = {
23 /* 0 */ "subreg_8bit\000"
24};
25#ifdef __GNUC__
26#pragma GCC diagnostic pop
27#endif
28
29
30static constexpr uint32_t MSP430SubRegIndexNameOffsets[] = {
31 0,
32};
33
34static const TargetRegisterInfo::SubRegCoveredBits MSP430SubRegIdxRangeTable[] = {
35 { .Offset: 65535, .Size: 65535 },
36 { .Offset: 0, .Size: 8 }, // subreg_8bit
37};
38
39
40static const LaneBitmask MSP430SubRegIndexLaneMaskTable[] = {
41 LaneBitmask::getAll(),
42 LaneBitmask(0x0000000000000001), // subreg_8bit
43 };
44
45
46
47static const TargetRegisterInfo::RegClassInfo MSP430RegClassInfos[] = {
48 // Mode = 0 (DefaultMode)
49 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*MSP430VTLists+*/.VTListOffset: 0 }, // GR8
50 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*MSP430VTLists+*/.VTListOffset: 2 }, // GR16
51};
52static const uint32_t GR8SubClassMask[] = {
53 0x00000001,
54 0x00000002, // subreg_8bit
55};
56
57static const uint32_t GR16SubClassMask[] = {
58 0x00000002,
59};
60
61static const uint16_t SuperRegIdxSeqs[] = {
62 /* 0 */ 1, 0,
63};
64
65namespace MSP430 {
66
67// Register class instances.
68 extern const TargetRegisterClass GR8RegClass = {
69 .MC: &MSP430MCRegisterClasses[GR8RegClassID],
70 .SubClassMask: GR8SubClassMask,
71 .SuperRegIndices: SuperRegIdxSeqs + 0,
72 .LaneMask: LaneBitmask(0x0000000000000001),
73 .AllocationPriority: 0,
74 .GlobalPriority: false,
75 .TSFlags: 0x00, /* TSFlags */
76 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
77 .CoveredBySubRegs: false, /* CoveredBySubRegs */
78 .SuperClasses: nullptr, .SuperClassesSize: 0,
79 .OrderFunc: nullptr
80 };
81
82 extern const TargetRegisterClass GR16RegClass = {
83 .MC: &MSP430MCRegisterClasses[GR16RegClassID],
84 .SubClassMask: GR16SubClassMask,
85 .SuperRegIndices: SuperRegIdxSeqs + 1,
86 .LaneMask: LaneBitmask(0x0000000000000001),
87 .AllocationPriority: 0,
88 .GlobalPriority: false,
89 .TSFlags: 0x00, /* TSFlags */
90 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
91 .CoveredBySubRegs: false, /* CoveredBySubRegs */
92 .SuperClasses: nullptr, .SuperClassesSize: 0,
93 .OrderFunc: nullptr
94 };
95
96
97} // namespace MSP430
98static const TargetRegisterClass *const MSP430RegisterClasses[] = {
99 &MSP430::GR8RegClass,
100 &MSP430::GR16RegClass,
101 };
102
103static const uint8_t MSP430CostPerUseTable[] = {
1040, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
105
106
107static const bool MSP430InAllocatableClassTable[] = {
108false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
109
110
111static const TargetRegisterInfoDesc MSP430RegInfoDesc = { // Extra Descriptors
112.CostPerUse: MSP430CostPerUseTable, .NumCosts: 1, .InAllocatableClass: MSP430InAllocatableClassTable};
113
114unsigned MSP430GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
115 static const uint8_t Rows[1][1] = {
116 { 0, },
117 };
118
119 --IdxA; assert(IdxA < 1); (void) IdxA;
120 --IdxB; assert(IdxB < 1);
121 return Rows[0][IdxB];
122}
123
124unsigned MSP430GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
125 static const uint8_t Table[1][1] = {
126 { 0, },
127 };
128
129 --IdxA; assert(IdxA < 1);
130 --IdxB; assert(IdxB < 1);
131 return Table[IdxA][IdxB];
132 }
133
134 struct MaskRolOp {
135 LaneBitmask Mask;
136 uint8_t RotateLeft;
137 };
138 static const MaskRolOp LaneMaskComposeSequences[] = {
139 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
140 };
141 static const uint8_t CompositeSequences[] = {
142 0 // to subreg_8bit
143 };
144
145LaneBitmask MSP430GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
146 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
147 LaneBitmask Result;
148 for (const MaskRolOp *Ops =
149 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
150 Ops->Mask.any(); ++Ops) {
151 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
152 if (unsigned S = Ops->RotateLeft)
153 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
154 else
155 Result |= LaneBitmask(M);
156 }
157 return Result;
158}
159
160LaneBitmask MSP430GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
161 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
162 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
163 LaneBitmask Result;
164 for (const MaskRolOp *Ops =
165 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
166 Ops->Mask.any(); ++Ops) {
167 LaneBitmask::Type M = LaneMask.getAsInteger();
168 if (unsigned S = Ops->RotateLeft)
169 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
170 else
171 Result |= LaneBitmask(M);
172 }
173 return Result;
174}
175
176const TargetRegisterClass *MSP430GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
177 static constexpr uint8_t Table[2][1] = {
178 { // GR8
179 0, // subreg_8bit
180 },
181 { // GR16
182 2, // subreg_8bit -> GR16
183 },
184
185 };
186 assert(RC && "Missing regclass");
187 if (!Idx) return RC;
188 --Idx;
189 assert(Idx < 1 && "Bad subreg");
190 unsigned TV = Table[RC->getID()][Idx];
191 return TV ? getRegClass(i: TV - 1) : nullptr;
192}const TargetRegisterClass *MSP430GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
193 static constexpr uint8_t Table[2][1] = {
194 { // GR8
195 0, // GR8:subreg_8bit
196 },
197 { // GR16
198 1, // GR16:subreg_8bit -> GR8
199 },
200
201 };
202 assert(RC && "Missing regclass");
203 if (!Idx) return RC;
204 --Idx;
205 assert(Idx < 1 && "Bad subreg");
206 unsigned TV = Table[RC->getID()][Idx];
207 return TV ? getRegClass(i: TV - 1) : nullptr;
208}/// Get the weight in units of pressure for this register class.
209const RegClassWeight &MSP430GenRegisterInfo::
210getRegClassWeight(const TargetRegisterClass *RC) const {
211 static const RegClassWeight RCWeightTable[] = {
212 {.RegWeight: 1, .WeightLimit: 16}, // GR8
213 {.RegWeight: 1, .WeightLimit: 16}, // GR16
214 };
215 return RCWeightTable[RC->getID()];
216}
217
218/// Get the weight in units of pressure for this register unit.
219unsigned MSP430GenRegisterInfo::
220getRegUnitWeight(MCRegUnit RegUnit) const {
221 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
222 // All register units have unit weight.
223 return 1;
224}
225
226
227// Get the number of dimensions of register pressure.
228unsigned MSP430GenRegisterInfo::getNumRegPressureSets() const {
229 return 1;
230}
231
232// Get the name of this register unit pressure set.
233const char *MSP430GenRegisterInfo::
234getRegPressureSetName(unsigned Idx) const {
235 static const char *PressureNameTable[] = {
236 "GR8",
237 };
238 return PressureNameTable[Idx];
239}
240
241// Get the register unit pressure limit for this dimension.
242// This limit must be adjusted dynamically for reserved registers.
243unsigned MSP430GenRegisterInfo::
244getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
245 static const uint8_t PressureLimitTable[] = {
246 16, // 0: GR8
247 };
248 return PressureLimitTable[Idx];
249}
250
251/// Table of pressure sets per register class or unit.
252static const int RCSetsTable[] = {
253 /* 0 */ 0, -1,
254};
255
256/// Get the dimensions of register pressure impacted by this register class.
257/// Returns a -1 terminated array of pressure set IDs
258const int *MSP430GenRegisterInfo::
259getRegClassPressureSets(const TargetRegisterClass *RC) const {
260 static const uint8_t RCSetStartTable[] = {
261 0,0,};
262 return &RCSetsTable[RCSetStartTable[RC->getID()]];
263}
264
265/// Get the dimensions of register pressure impacted by this register unit.
266/// Returns a -1 terminated array of pressure set IDs
267const int *MSP430GenRegisterInfo::
268getRegUnitPressureSets(MCRegUnit RegUnit) const {
269 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
270 static const uint8_t RUSetStartTable[] = {
271 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,};
272 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
273}
274
275extern const MCRegisterDesc MSP430RegDesc[];
276extern const int16_t MSP430RegDiffLists[];
277extern const LaneBitmask MSP430LaneMaskLists[];
278extern const char MSP430RegStrings[];
279extern const char MSP430RegClassStrings[];
280extern const MCPhysReg MSP430RegUnitRoots[][2];
281extern const uint16_t MSP430SubRegIdxLists[];
282extern const uint16_t MSP430RegEncodingTable[];
283// MSP430 Dwarf<->LLVM register mappings.
284extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0Dwarf2L[];
285extern const unsigned MSP430DwarfFlavour0Dwarf2LSize;
286
287extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0Dwarf2L[];
288extern const unsigned MSP430EHFlavour0Dwarf2LSize;
289
290extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0L2Dwarf[];
291extern const unsigned MSP430DwarfFlavour0L2DwarfSize;
292
293extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0L2Dwarf[];
294extern const unsigned MSP430EHFlavour0L2DwarfSize;
295
296
297MSP430GenRegisterInfo::
298MSP430GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
299 unsigned PC, unsigned HwMode)
300 : TargetRegisterInfo(&MSP430RegInfoDesc, MSP430RegisterClasses,
301 MSP430SubRegIndexStrings, MSP430SubRegIndexNameOffsets,
302 MSP430SubRegIdxRangeTable, MSP430SubRegIndexLaneMaskTable,
303
304 LaneBitmask(0xFFFFFFFFFFFFFFFE), MSP430RegClassInfos, MSP430VTLists, HwMode) {
305 InitMCRegisterInfo(D: MSP430RegDesc, NR: 33, RA, PC,
306 C: MSP430MCRegisterClasses, NC: 2, RURoots: MSP430RegUnitRoots, NRU: 16, DL: MSP430RegDiffLists,
307 RUMS: MSP430LaneMaskLists, Strings: MSP430RegStrings, ClassStrings: MSP430RegClassStrings, SubIndices: MSP430SubRegIdxLists, NumIndices: 2,
308 RET: MSP430RegEncodingTable, RUI: nullptr);
309
310 switch (DwarfFlavour) {
311 default:
312 llvm_unreachable("Unknown DWARF flavour");
313 case 0:
314 mapDwarfRegsToLLVMRegs(Map: MSP430DwarfFlavour0Dwarf2L, Size: MSP430DwarfFlavour0Dwarf2LSize, isEH: false);
315 break;
316 }
317 switch (EHFlavour) {
318 default:
319 llvm_unreachable("Unknown DWARF flavour");
320 case 0:
321 mapDwarfRegsToLLVMRegs(Map: MSP430EHFlavour0Dwarf2L, Size: MSP430EHFlavour0Dwarf2LSize, isEH: true);
322 break;
323 }
324 switch (DwarfFlavour) {
325 default:
326 llvm_unreachable("Unknown DWARF flavour");
327 case 0:
328 mapLLVMRegsToDwarfRegs(Map: MSP430DwarfFlavour0L2Dwarf, Size: MSP430DwarfFlavour0L2DwarfSize, isEH: false);
329 break;
330 }
331 switch (EHFlavour) {
332 default:
333 llvm_unreachable("Unknown DWARF flavour");
334 case 0:
335 mapLLVMRegsToDwarfRegs(Map: MSP430EHFlavour0L2Dwarf, Size: MSP430EHFlavour0L2DwarfSize, isEH: true);
336 break;
337 }
338}
339
340
341
342ArrayRef<const uint32_t *> MSP430GenRegisterInfo::getRegMasks() const {
343 return {};
344}
345
346bool MSP430GenRegisterInfo::
347isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
348 return
349 false;
350}
351
352bool MSP430GenRegisterInfo::
353isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
354 return
355 false;
356}
357
358bool MSP430GenRegisterInfo::
359isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
360 return
361 false;
362}
363
364bool MSP430GenRegisterInfo::
365isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
366 return
367 false;
368}
369
370bool MSP430GenRegisterInfo::
371isConstantPhysReg(MCRegister PhysReg) const {
372 return
373 false;
374}
375
376ArrayRef<const char *> MSP430GenRegisterInfo::getRegMaskNames() const {
377 return {};
378}
379
380const MSP430FrameLowering *
381MSP430GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
382 return static_cast<const MSP430FrameLowering *>(
383 MF.getSubtarget().getFrameLowering());
384}
385
386
387} // namespace llvm
388