1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass MSP430MCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i8, MVT::Other,
15 /* 2 */ MVT::i16, MVT::Other,
16};
17
18#ifdef __GNUC__
19#pragma GCC diagnostic push
20#pragma GCC diagnostic ignored "-Woverlength-strings"
21#endif
22static constexpr char MSP430SubRegIndexStrings[] = {
23 /* 0 */ "subreg_8bit\000"
24};
25#ifdef __GNUC__
26#pragma GCC diagnostic pop
27#endif
28
29
30static constexpr uint32_t MSP430SubRegIndexNameOffsets[] = {
31 0,
32};
33
34static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
35 { .Offset: 65535, .Size: 65535 },
36 { .Offset: 0, .Size: 8 }, // subreg_8bit
37};
38
39
40static const LaneBitmask SubRegIndexLaneMaskTable[] = {
41 LaneBitmask::getAll(),
42 LaneBitmask(0x0000000000000001), // subreg_8bit
43 };
44
45
46
47static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
48 // Mode = 0 (DefaultMode)
49 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8
50 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GR16
51};
52static const uint32_t GR8SubClassMask[] = {
53 0x00000001,
54 0x00000002, // subreg_8bit
55};
56
57static const uint32_t GR16SubClassMask[] = {
58 0x00000002,
59};
60
61static const uint16_t SuperRegIdxSeqs[] = {
62 /* 0 */ 1, 0,
63};
64
65namespace MSP430 {
66
67// Register class instances
68 extern const TargetRegisterClass GR8RegClass = {
69 .MC: &MSP430MCRegisterClasses[GR8RegClassID],
70 .SubClassMask: GR8SubClassMask,
71 .SuperRegIndices: SuperRegIdxSeqs + 0,
72 .LaneMask: LaneBitmask(0x0000000000000001),
73 .AllocationPriority: 0,
74 .GlobalPriority: false,
75 .TSFlags: 0x00, /* TSFlags */
76 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
77 .CoveredBySubRegs: false, /* CoveredBySubRegs */
78 .SuperClasses: nullptr, .SuperClassesSize: 0,
79 .OrderFunc: nullptr
80 };
81
82 extern const TargetRegisterClass GR16RegClass = {
83 .MC: &MSP430MCRegisterClasses[GR16RegClassID],
84 .SubClassMask: GR16SubClassMask,
85 .SuperRegIndices: SuperRegIdxSeqs + 1,
86 .LaneMask: LaneBitmask(0x0000000000000001),
87 .AllocationPriority: 0,
88 .GlobalPriority: false,
89 .TSFlags: 0x00, /* TSFlags */
90 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
91 .CoveredBySubRegs: false, /* CoveredBySubRegs */
92 .SuperClasses: nullptr, .SuperClassesSize: 0,
93 .OrderFunc: nullptr
94 };
95
96
97} // namespace MSP430
98namespace {
99
100 const TargetRegisterClass *const RegisterClasses[] = {
101 &MSP430::GR8RegClass,
102 &MSP430::GR16RegClass,
103 };
104} // namespace
105
106static const uint8_t CostPerUseTable[] = {
1070, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
108
109
110static const bool InAllocatableClassTable[] = {
111false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
112
113
114static const TargetRegisterInfoDesc MSP430RegInfoDesc = { // Extra Descriptors
115.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
116
117unsigned MSP430GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
118 static const uint8_t Rows[1][1] = {
119 { 0, },
120 };
121
122 --IdxA; assert(IdxA < 1); (void) IdxA;
123 --IdxB; assert(IdxB < 1);
124 return Rows[0][IdxB];
125}
126
127unsigned MSP430GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
128 static const uint8_t Table[1][1] = {
129 { 0, },
130 };
131
132 --IdxA; assert(IdxA < 1);
133 --IdxB; assert(IdxB < 1);
134 return Table[IdxA][IdxB];
135 }
136
137 struct MaskRolOp {
138 LaneBitmask Mask;
139 uint8_t RotateLeft;
140 };
141 static const MaskRolOp LaneMaskComposeSequences[] = {
142 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
143 };
144 static const uint8_t CompositeSequences[] = {
145 0 // to subreg_8bit
146 };
147
148LaneBitmask MSP430GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
149 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
150 LaneBitmask Result;
151 for (const MaskRolOp *Ops =
152 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
153 Ops->Mask.any(); ++Ops) {
154 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
155 if (unsigned S = Ops->RotateLeft)
156 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
157 else
158 Result |= LaneBitmask(M);
159 }
160 return Result;
161}
162
163LaneBitmask MSP430GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
164 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
165 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
166 LaneBitmask Result;
167 for (const MaskRolOp *Ops =
168 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
169 Ops->Mask.any(); ++Ops) {
170 LaneBitmask::Type M = LaneMask.getAsInteger();
171 if (unsigned S = Ops->RotateLeft)
172 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
173 else
174 Result |= LaneBitmask(M);
175 }
176 return Result;
177}
178
179const TargetRegisterClass *MSP430GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
180 static constexpr uint8_t Table[2][1] = {
181 { // GR8
182 0, // subreg_8bit
183 },
184 { // GR16
185 2, // subreg_8bit -> GR16
186 },
187
188 };
189 assert(RC && "Missing regclass");
190 if (!Idx) return RC;
191 --Idx;
192 assert(Idx < 1 && "Bad subreg");
193 unsigned TV = Table[RC->getID()][Idx];
194 return TV ? getRegClass(i: TV - 1) : nullptr;
195}const TargetRegisterClass *MSP430GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
196 static constexpr uint8_t Table[2][1] = {
197 { // GR8
198 0, // GR8:subreg_8bit
199 },
200 { // GR16
201 1, // GR16:subreg_8bit -> GR8
202 },
203
204 };
205 assert(RC && "Missing regclass");
206 if (!Idx) return RC;
207 --Idx;
208 assert(Idx < 1 && "Bad subreg");
209 unsigned TV = Table[RC->getID()][Idx];
210 return TV ? getRegClass(i: TV - 1) : nullptr;
211}/// Get the weight in units of pressure for this register class.
212const RegClassWeight &MSP430GenRegisterInfo::
213getRegClassWeight(const TargetRegisterClass *RC) const {
214 static const RegClassWeight RCWeightTable[] = {
215 {.RegWeight: 1, .WeightLimit: 16}, // GR8
216 {.RegWeight: 1, .WeightLimit: 16}, // GR16
217 };
218 return RCWeightTable[RC->getID()];
219}
220
221/// Get the weight in units of pressure for this register unit.
222unsigned MSP430GenRegisterInfo::
223getRegUnitWeight(MCRegUnit RegUnit) const {
224 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
225 // All register units have unit weight.
226 return 1;
227}
228
229
230// Get the number of dimensions of register pressure.
231unsigned MSP430GenRegisterInfo::getNumRegPressureSets() const {
232 return 1;
233}
234
235// Get the name of this register unit pressure set.
236const char *MSP430GenRegisterInfo::
237getRegPressureSetName(unsigned Idx) const {
238 static const char *PressureNameTable[] = {
239 "GR8",
240 };
241 return PressureNameTable[Idx];
242}
243
244// Get the register unit pressure limit for this dimension.
245// This limit must be adjusted dynamically for reserved registers.
246unsigned MSP430GenRegisterInfo::
247getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
248 static const uint8_t PressureLimitTable[] = {
249 16, // 0: GR8
250 };
251 return PressureLimitTable[Idx];
252}
253
254/// Table of pressure sets per register class or unit.
255static const int RCSetsTable[] = {
256 /* 0 */ 0, -1,
257};
258
259/// Get the dimensions of register pressure impacted by this register class.
260/// Returns a -1 terminated array of pressure set IDs
261const int *MSP430GenRegisterInfo::
262getRegClassPressureSets(const TargetRegisterClass *RC) const {
263 static const uint8_t RCSetStartTable[] = {
264 0,0,};
265 return &RCSetsTable[RCSetStartTable[RC->getID()]];
266}
267
268/// Get the dimensions of register pressure impacted by this register unit.
269/// Returns a -1 terminated array of pressure set IDs
270const int *MSP430GenRegisterInfo::
271getRegUnitPressureSets(MCRegUnit RegUnit) const {
272 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
273 static const uint8_t RUSetStartTable[] = {
274 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,};
275 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
276}
277
278extern const MCRegisterDesc MSP430RegDesc[];
279extern const int16_t MSP430RegDiffLists[];
280extern const LaneBitmask MSP430LaneMaskLists[];
281extern const char MSP430RegStrings[];
282extern const char MSP430RegClassStrings[];
283extern const MCPhysReg MSP430RegUnitRoots[][2];
284extern const uint16_t MSP430SubRegIdxLists[];
285extern const uint16_t MSP430RegEncodingTable[];
286// MSP430 Dwarf<->LLVM register mappings.
287extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0Dwarf2L[];
288extern const unsigned MSP430DwarfFlavour0Dwarf2LSize;
289
290extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0Dwarf2L[];
291extern const unsigned MSP430EHFlavour0Dwarf2LSize;
292
293extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0L2Dwarf[];
294extern const unsigned MSP430DwarfFlavour0L2DwarfSize;
295
296extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0L2Dwarf[];
297extern const unsigned MSP430EHFlavour0L2DwarfSize;
298
299
300MSP430GenRegisterInfo::
301MSP430GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
302 unsigned PC, unsigned HwMode)
303 : TargetRegisterInfo(&MSP430RegInfoDesc, RegisterClasses, RegisterClasses+2,
304 MSP430SubRegIndexStrings, MSP430SubRegIndexNameOffsets,
305 SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
306
307 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
308 InitMCRegisterInfo(D: MSP430RegDesc, NR: 33, RA, PC,
309 C: MSP430MCRegisterClasses, NC: 2,
310 RURoots: MSP430RegUnitRoots,
311 NRU: 16,
312 DL: MSP430RegDiffLists,
313 RUMS: MSP430LaneMaskLists,
314 Strings: MSP430RegStrings,
315 ClassStrings: MSP430RegClassStrings,
316 SubIndices: MSP430SubRegIdxLists,
317 NumIndices: 2,
318 RET: MSP430RegEncodingTable,
319 RUI: nullptr);
320
321 switch (DwarfFlavour) {
322 default:
323 llvm_unreachable("Unknown DWARF flavour");
324 case 0:
325 mapDwarfRegsToLLVMRegs(Map: MSP430DwarfFlavour0Dwarf2L, Size: MSP430DwarfFlavour0Dwarf2LSize, isEH: false);
326 break;
327 }
328 switch (EHFlavour) {
329 default:
330 llvm_unreachable("Unknown DWARF flavour");
331 case 0:
332 mapDwarfRegsToLLVMRegs(Map: MSP430EHFlavour0Dwarf2L, Size: MSP430EHFlavour0Dwarf2LSize, isEH: true);
333 break;
334 }
335 switch (DwarfFlavour) {
336 default:
337 llvm_unreachable("Unknown DWARF flavour");
338 case 0:
339 mapLLVMRegsToDwarfRegs(Map: MSP430DwarfFlavour0L2Dwarf, Size: MSP430DwarfFlavour0L2DwarfSize, isEH: false);
340 break;
341 }
342 switch (EHFlavour) {
343 default:
344 llvm_unreachable("Unknown DWARF flavour");
345 case 0:
346 mapLLVMRegsToDwarfRegs(Map: MSP430EHFlavour0L2Dwarf, Size: MSP430EHFlavour0L2DwarfSize, isEH: true);
347 break;
348 }
349}
350
351
352
353ArrayRef<const uint32_t *> MSP430GenRegisterInfo::getRegMasks() const {
354 return {};
355}
356
357bool MSP430GenRegisterInfo::
358isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
359 return
360 false;
361}
362
363bool MSP430GenRegisterInfo::
364isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
365 return
366 false;
367}
368
369bool MSP430GenRegisterInfo::
370isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
371 return
372 false;
373}
374
375bool MSP430GenRegisterInfo::
376isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
377 return
378 false;
379}
380
381bool MSP430GenRegisterInfo::
382isConstantPhysReg(MCRegister PhysReg) const {
383 return
384 false;
385}
386
387ArrayRef<const char *> MSP430GenRegisterInfo::getRegMaskNames() const {
388 return {};
389}
390
391const MSP430FrameLowering *
392MSP430GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
393 return static_cast<const MSP430FrameLowering *>(
394 MF.getSubtarget().getFrameLowering());
395}
396
397
398} // namespace llvm
399