1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass MSP430MCRegisterClasses[];
12
13static const MVT::SimpleValueType MSP430VTLists[] = {
14 /* 0 */ MVT::i8, MVT::Other,
15 /* 2 */ MVT::i16, MVT::Other,
16};
17
18#ifdef __GNUC__
19#pragma GCC diagnostic push
20#pragma GCC diagnostic ignored "-Woverlength-strings"
21#endif
22static constexpr char MSP430SubRegIndexStrings[] = {
23 /* 0 */ "subreg_8bit\000"
24};
25#ifdef __GNUC__
26#pragma GCC diagnostic pop
27#endif
28
29
30static constexpr uint32_t MSP430SubRegIndexNameOffsets[] = {
31 0,
32};
33
34static const TargetRegisterInfo::SubRegCoveredBits MSP430SubRegIdxRangeTable[] = {
35 { .Offset: 4294967295, .Size: 4294967295 },
36 { .Offset: 0, .Size: 8 }, // subreg_8bit
37};
38
39
40static const LaneBitmask MSP430SubRegIndexLaneMaskTable[] = {
41 LaneBitmask::getAll(),
42 LaneBitmask(0x0000000000000001), // subreg_8bit
43 };
44
45
46
47static const TargetRegisterInfo::RegClassInfo MSP430RegClassInfos[] = {
48 // Mode = 0 (DefaultMode)
49 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*MSP430VTLists+*/.VTListOffset: 0 }, // GR8
50 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*MSP430VTLists+*/.VTListOffset: 2 }, // GR16
51};
52static const uint32_t GR8SubClassMask[] = {
53 0x00000001,
54 0x00000002, // subreg_8bit
55};
56
57static const uint32_t GR16SubClassMask[] = {
58 0x00000002,
59};
60
61static const uint16_t SuperRegIdxSeqs[] = {
62 /* 0 */ 1, 0,
63};
64
65namespace MSP430 {
66
67// Register class instances.
68 extern const TargetRegisterClass GR8RegClass = {
69 .MC: &MSP430MCRegisterClasses[GR8RegClassID],
70 .SubClassMask: GR8SubClassMask,
71 .SuperRegIndices: SuperRegIdxSeqs + 0,
72 .LaneMask: LaneBitmask(0x0000000000000001),
73 .AllocationPriority: 0,
74 .GlobalPriority: false,
75 .TSFlags: 0x00, /* TSFlags */
76 .SpillStackID: 0, /* SpillStackID */
77 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
78 .CoveredBySubRegs: false, /* CoveredBySubRegs */
79 .SuperClasses: nullptr, .SuperClassesSize: 0,
80 .OrderFunc: nullptr
81 };
82
83 extern const TargetRegisterClass GR16RegClass = {
84 .MC: &MSP430MCRegisterClasses[GR16RegClassID],
85 .SubClassMask: GR16SubClassMask,
86 .SuperRegIndices: SuperRegIdxSeqs + 1,
87 .LaneMask: LaneBitmask(0x0000000000000001),
88 .AllocationPriority: 0,
89 .GlobalPriority: false,
90 .TSFlags: 0x00, /* TSFlags */
91 .SpillStackID: 0, /* SpillStackID */
92 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
93 .CoveredBySubRegs: false, /* CoveredBySubRegs */
94 .SuperClasses: nullptr, .SuperClassesSize: 0,
95 .OrderFunc: nullptr
96 };
97
98
99} // namespace MSP430
100static const TargetRegisterClass *const MSP430RegisterClasses[] = {
101 &MSP430::GR8RegClass,
102 &MSP430::GR16RegClass,
103 };
104
105static const uint8_t MSP430CostPerUseTable[] = {
1060, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
107
108
109static const bool MSP430InAllocatableClassTable[] = {
110false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
111
112
113static const TargetRegisterInfoDesc MSP430RegInfoDesc = { // Extra Descriptors
114.CostPerUse: MSP430CostPerUseTable, .NumCosts: 1, .InAllocatableClass: MSP430InAllocatableClassTable};
115
116unsigned MSP430GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
117 static const uint8_t Rows[1][1] = {
118 { 0, },
119 };
120
121 --IdxA; assert(IdxA < 1); (void) IdxA;
122 --IdxB; assert(IdxB < 1);
123 return Rows[0][IdxB];
124}
125
126unsigned MSP430GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
127 static const uint8_t Table[1][1] = {
128 { 0, },
129 };
130
131 --IdxA; assert(IdxA < 1);
132 --IdxB; assert(IdxB < 1);
133 return Table[IdxA][IdxB];
134 }
135
136 struct MaskRolOp {
137 LaneBitmask Mask;
138 uint8_t RotateLeft;
139 };
140 static const MaskRolOp LaneMaskComposeSequences[] = {
141 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
142 };
143 static const uint8_t CompositeSequences[] = {
144 0 // to subreg_8bit
145 };
146
147LaneBitmask MSP430GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
148 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
149 LaneBitmask Result;
150 for (const MaskRolOp *Ops =
151 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
152 Ops->Mask.any(); ++Ops) {
153 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
154 if (unsigned S = Ops->RotateLeft)
155 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
156 else
157 Result |= LaneBitmask(M);
158 }
159 return Result;
160}
161
162LaneBitmask MSP430GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
163 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
164 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
165 LaneBitmask Result;
166 for (const MaskRolOp *Ops =
167 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
168 Ops->Mask.any(); ++Ops) {
169 LaneBitmask::Type M = LaneMask.getAsInteger();
170 if (unsigned S = Ops->RotateLeft)
171 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
172 else
173 Result |= LaneBitmask(M);
174 }
175 return Result;
176}
177
178const TargetRegisterClass *MSP430GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
179 static constexpr uint8_t Table[2][1] = {
180 { // GR8
181 0, // subreg_8bit
182 },
183 { // GR16
184 2, // subreg_8bit -> GR16
185 },
186
187 };
188 assert(RC && "Missing regclass");
189 if (!Idx) return RC;
190 --Idx;
191 assert(Idx < 1 && "Bad subreg");
192 unsigned TV = Table[RC->getID()][Idx];
193 return TV ? getRegClass(i: TV - 1) : nullptr;
194}const TargetRegisterClass *MSP430GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
195 static constexpr uint8_t Table[2][1] = {
196 { // GR8
197 0, // GR8:subreg_8bit
198 },
199 { // GR16
200 1, // GR16:subreg_8bit -> GR8
201 },
202
203 };
204 assert(RC && "Missing regclass");
205 if (!Idx) return RC;
206 --Idx;
207 assert(Idx < 1 && "Bad subreg");
208 unsigned TV = Table[RC->getID()][Idx];
209 return TV ? getRegClass(i: TV - 1) : nullptr;
210}/// Get the weight in units of pressure for this register class.
211const RegClassWeight &MSP430GenRegisterInfo::
212getRegClassWeight(const TargetRegisterClass *RC) const {
213 static const RegClassWeight RCWeightTable[] = {
214 {.RegWeight: 1, .WeightLimit: 16}, // GR8
215 {.RegWeight: 1, .WeightLimit: 16}, // GR16
216 };
217 return RCWeightTable[RC->getID()];
218}
219
220/// Get the weight in units of pressure for this register unit.
221unsigned MSP430GenRegisterInfo::
222getRegUnitWeight(MCRegUnit RegUnit) const {
223 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
224 // All register units have unit weight.
225 return 1;
226}
227
228
229// Get the number of dimensions of register pressure.
230unsigned MSP430GenRegisterInfo::getNumRegPressureSets() const {
231 return 1;
232}
233
234// Get the name of this register unit pressure set.
235const char *MSP430GenRegisterInfo::
236getRegPressureSetName(unsigned Idx) const {
237 static const char *PressureNameTable[] = {
238 "GR8",
239 };
240 return PressureNameTable[Idx];
241}
242
243// Get the register unit pressure limit for this dimension.
244// This limit must be adjusted dynamically for reserved registers.
245unsigned MSP430GenRegisterInfo::
246getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
247 static const uint8_t PressureLimitTable[] = {
248 16, // 0: GR8
249 };
250 return PressureLimitTable[Idx];
251}
252
253/// Table of pressure sets per register class or unit.
254static const int RCSetsTable[] = {
255 /* 0 */ 0, -1,
256};
257
258/// Get the dimensions of register pressure impacted by this register class.
259/// Returns a -1 terminated array of pressure set IDs
260const int *MSP430GenRegisterInfo::
261getRegClassPressureSets(const TargetRegisterClass *RC) const {
262 static const uint8_t RCSetStartTable[] = {
263 0,0,};
264 return &RCSetsTable[RCSetStartTable[RC->getID()]];
265}
266
267/// Get the dimensions of register pressure impacted by this register unit.
268/// Returns a -1 terminated array of pressure set IDs
269const int *MSP430GenRegisterInfo::
270getRegUnitPressureSets(MCRegUnit RegUnit) const {
271 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
272 static const uint8_t RUSetStartTable[] = {
273 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,};
274 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
275}
276
277
278// Register to minimal register class mapping
279
280const TargetRegisterClass *MSP430GenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
281 static const uint16_t InvalidRegClassID = UINT16_MAX;
282
283 static const uint16_t Mapping[33] = {
284 InvalidRegClassID, // NoRegister
285 MSP430::GR16RegClassID, // CG
286 MSP430::GR8RegClassID, // CGB
287 MSP430::GR16RegClassID, // PC
288 MSP430::GR8RegClassID, // PCB
289 MSP430::GR16RegClassID, // SP
290 MSP430::GR8RegClassID, // SPB
291 MSP430::GR16RegClassID, // SR
292 MSP430::GR8RegClassID, // SRB
293 MSP430::GR16RegClassID, // R4
294 MSP430::GR16RegClassID, // R5
295 MSP430::GR16RegClassID, // R6
296 MSP430::GR16RegClassID, // R7
297 MSP430::GR16RegClassID, // R8
298 MSP430::GR16RegClassID, // R9
299 MSP430::GR16RegClassID, // R10
300 MSP430::GR16RegClassID, // R11
301 MSP430::GR16RegClassID, // R12
302 MSP430::GR16RegClassID, // R13
303 MSP430::GR16RegClassID, // R14
304 MSP430::GR16RegClassID, // R15
305 MSP430::GR8RegClassID, // R4B
306 MSP430::GR8RegClassID, // R5B
307 MSP430::GR8RegClassID, // R6B
308 MSP430::GR8RegClassID, // R7B
309 MSP430::GR8RegClassID, // R8B
310 MSP430::GR8RegClassID, // R9B
311 MSP430::GR8RegClassID, // R10B
312 MSP430::GR8RegClassID, // R11B
313 MSP430::GR8RegClassID, // R12B
314 MSP430::GR8RegClassID, // R13B
315 MSP430::GR8RegClassID, // R14B
316 MSP430::GR8RegClassID, // R15B
317 };
318
319 assert(Reg < ArrayRef(Mapping).size());
320 unsigned RCID = Mapping[Reg.id()];
321 if (RCID == InvalidRegClassID)
322 return nullptr;
323 return MSP430RegisterClasses[RCID];
324}
325extern const MCRegisterDesc MSP430RegDesc[];
326extern const int16_t MSP430RegDiffLists[];
327extern const LaneBitmask MSP430LaneMaskLists[];
328extern const char MSP430RegStrings[];
329extern const char MSP430RegClassStrings[];
330extern const MCPhysReg MSP430RegUnitRoots[][2];
331extern const uint16_t MSP430SubRegIdxLists[];
332extern const uint16_t MSP430RegEncodingTable[];
333// MSP430 Dwarf<->LLVM register mappings.
334extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0Dwarf2L[];
335extern const unsigned MSP430DwarfFlavour0Dwarf2LSize;
336
337extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0Dwarf2L[];
338extern const unsigned MSP430EHFlavour0Dwarf2LSize;
339
340extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0L2Dwarf[];
341extern const unsigned MSP430DwarfFlavour0L2DwarfSize;
342
343extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0L2Dwarf[];
344extern const unsigned MSP430EHFlavour0L2DwarfSize;
345
346
347MSP430GenRegisterInfo::
348MSP430GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
349 unsigned PC, unsigned HwMode)
350 : TargetRegisterInfo(&MSP430RegInfoDesc, MSP430RegisterClasses,
351 MSP430SubRegIndexStrings, MSP430SubRegIndexNameOffsets,
352 MSP430SubRegIdxRangeTable, MSP430SubRegIndexLaneMaskTable,
353
354 LaneBitmask(0xFFFFFFFFFFFFFFFE), MSP430RegClassInfos, MSP430VTLists, HwMode) {
355 InitMCRegisterInfo(D: MSP430RegDesc, NR: 33, RA, PC,
356 C: MSP430MCRegisterClasses, NC: 2, RURoots: MSP430RegUnitRoots, NRU: 16, DL: MSP430RegDiffLists,
357 RUMS: MSP430LaneMaskLists, Strings: MSP430RegStrings, ClassStrings: MSP430RegClassStrings, SubIndices: MSP430SubRegIdxLists, NumIndices: 2,
358 RET: MSP430RegEncodingTable, RUI: nullptr);
359
360 switch (DwarfFlavour) {
361 default:
362 llvm_unreachable("Unknown DWARF flavour");
363 case 0:
364 mapDwarfRegsToLLVMRegs(Map: MSP430DwarfFlavour0Dwarf2L, Size: MSP430DwarfFlavour0Dwarf2LSize, isEH: false);
365 break;
366 }
367 switch (EHFlavour) {
368 default:
369 llvm_unreachable("Unknown DWARF flavour");
370 case 0:
371 mapDwarfRegsToLLVMRegs(Map: MSP430EHFlavour0Dwarf2L, Size: MSP430EHFlavour0Dwarf2LSize, isEH: true);
372 break;
373 }
374 switch (DwarfFlavour) {
375 default:
376 llvm_unreachable("Unknown DWARF flavour");
377 case 0:
378 mapLLVMRegsToDwarfRegs(Map: MSP430DwarfFlavour0L2Dwarf, Size: MSP430DwarfFlavour0L2DwarfSize, isEH: false);
379 break;
380 }
381 switch (EHFlavour) {
382 default:
383 llvm_unreachable("Unknown DWARF flavour");
384 case 0:
385 mapLLVMRegsToDwarfRegs(Map: MSP430EHFlavour0L2Dwarf, Size: MSP430EHFlavour0L2DwarfSize, isEH: true);
386 break;
387 }
388}
389
390
391
392ArrayRef<const uint32_t *> MSP430GenRegisterInfo::getRegMasks() const {
393 return {};
394}
395
396bool MSP430GenRegisterInfo::
397isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
398 return
399 false;
400}
401
402bool MSP430GenRegisterInfo::
403isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
404 return
405 false;
406}
407
408bool MSP430GenRegisterInfo::
409isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
410 return
411 false;
412}
413
414bool MSP430GenRegisterInfo::
415isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
416 return
417 false;
418}
419
420bool MSP430GenRegisterInfo::
421isConstantPhysReg(MCRegister PhysReg) const {
422 return
423 false;
424}
425
426ArrayRef<const char *> MSP430GenRegisterInfo::getRegMaskNames() const {
427 return {};
428}
429
430const MSP430FrameLowering *
431MSP430GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
432 return static_cast<const MSP430FrameLowering *>(
433 MF.getSubtarget().getFrameLowering());
434}
435
436
437} // namespace llvm
438