1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<2, 32, 8, 3, 2, 0> MSP430MCRegisterClassStorage;
12
13static const MVT::SimpleValueType MSP430VTLists[] = {
14 /* 0 */ MVT::i8, MVT::Other,
15 /* 2 */ MVT::i16, MVT::Other,
16};
17
18#ifdef __GNUC__
19#pragma GCC diagnostic push
20#pragma GCC diagnostic ignored "-Woverlength-strings"
21#endif
22static constexpr char MSP430SubRegIndexStrings[] = {
23 /* 0 */ "subreg_8bit\000"
24};
25#ifdef __GNUC__
26#pragma GCC diagnostic pop
27#endif
28
29
30static constexpr uint32_t MSP430SubRegIndexNameOffsets[] = {
31 0,
32};
33
34static const TargetRegisterInfo::SubRegCoveredBits MSP430SubRegIdxRangeTable[] = {
35 { .Offset: 4294967295, .Size: 4294967295 },
36 { .Offset: 0, .Size: 8 }, // subreg_8bit
37};
38
39
40static const LaneBitmask MSP430SubRegIndexLaneMaskTable[] = {
41 LaneBitmask::getAll(),
42 LaneBitmask(0x0000000000000001), // subreg_8bit
43 };
44
45
46
47static const TargetRegisterInfo::RegClassInfo MSP430RegClassInfos[] = {
48 // Mode = 0 (DefaultMode)
49 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*MSP430VTLists+*/.VTListOffset: 0 }, // GR8
50 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*MSP430VTLists+*/.VTListOffset: 2 }, // GR16
51};
52
53static const uint8_t MSP430CostPerUseTable[] = {
540, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
55
56
57static const bool MSP430InAllocatableClassTable[] = {
58false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
59
60
61static const TargetRegisterInfoDesc MSP430RegInfoDesc = { // Extra Descriptors
62.CostPerUse: MSP430CostPerUseTable, .NumCosts: 1, .InAllocatableClass: MSP430InAllocatableClassTable};
63
64unsigned MSP430GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
65 static const uint8_t Rows[1][1] = {
66 { 0, },
67 };
68
69 --IdxA; assert(IdxA < 1); (void) IdxA;
70 --IdxB; assert(IdxB < 1);
71 return Rows[0][IdxB];
72}
73
74unsigned MSP430GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
75 static const uint8_t Table[1][1] = {
76 { 0, },
77 };
78
79 --IdxA; assert(IdxA < 1);
80 --IdxB; assert(IdxB < 1);
81 return Table[IdxA][IdxB];
82 }
83
84 struct MaskRolOp {
85 LaneBitmask Mask;
86 uint8_t RotateLeft;
87 };
88 static const MaskRolOp LaneMaskComposeSequences[] = {
89 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
90 };
91 static const uint8_t CompositeSequences[] = {
92 0 // to subreg_8bit
93 };
94
95LaneBitmask MSP430GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
96 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
97 LaneBitmask Result;
98 for (const MaskRolOp *Ops =
99 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
100 Ops->Mask.any(); ++Ops) {
101 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
102 if (unsigned S = Ops->RotateLeft)
103 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
104 else
105 Result |= LaneBitmask(M);
106 }
107 return Result;
108}
109
110LaneBitmask MSP430GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
111 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
112 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
113 LaneBitmask Result;
114 for (const MaskRolOp *Ops =
115 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
116 Ops->Mask.any(); ++Ops) {
117 LaneBitmask::Type M = LaneMask.getAsInteger();
118 if (unsigned S = Ops->RotateLeft)
119 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
120 else
121 Result |= LaneBitmask(M);
122 }
123 return Result;
124}
125
126const TargetRegisterClass *MSP430GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
127 static constexpr uint8_t Table[2][1] = {
128 { // GR8
129 0, // subreg_8bit
130 },
131 { // GR16
132 2, // subreg_8bit -> GR16
133 },
134
135 };
136 assert(RC && "Missing regclass");
137 if (!Idx) return RC;
138 --Idx;
139 assert(Idx < 1 && "Bad subreg");
140 unsigned TV = Table[RC->getID()][Idx];
141 return TV ? getRegClass(i: TV - 1) : nullptr;
142}const TargetRegisterClass *MSP430GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
143 static constexpr uint8_t Table[2][1] = {
144 { // GR8
145 0, // GR8:subreg_8bit
146 },
147 { // GR16
148 1, // GR16:subreg_8bit -> GR8
149 },
150
151 };
152 assert(RC && "Missing regclass");
153 if (!Idx) return RC;
154 --Idx;
155 assert(Idx < 1 && "Bad subreg");
156 unsigned TV = Table[RC->getID()][Idx];
157 return TV ? getRegClass(i: TV - 1) : nullptr;
158}/// Get the weight in units of pressure for this register class.
159const RegClassWeight &MSP430GenRegisterInfo::
160getRegClassWeight(const TargetRegisterClass *RC) const {
161 static const RegClassWeight RCWeightTable[] = {
162 {.RegWeight: 1, .WeightLimit: 16}, // GR8
163 {.RegWeight: 1, .WeightLimit: 16}, // GR16
164 };
165 return RCWeightTable[RC->getID()];
166}
167
168/// Get the weight in units of pressure for this register unit.
169unsigned MSP430GenRegisterInfo::
170getRegUnitWeight(MCRegUnit RegUnit) const {
171 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
172 // All register units have unit weight.
173 return 1;
174}
175
176
177// Get the number of dimensions of register pressure.
178unsigned MSP430GenRegisterInfo::getNumRegPressureSets() const {
179 return 1;
180}
181
182// Get the name of this register unit pressure set.
183const char *MSP430GenRegisterInfo::
184getRegPressureSetName(unsigned Idx) const {
185 static const char *PressureNameTable[] = {
186 "GR8",
187 };
188 return PressureNameTable[Idx];
189}
190
191// Get the register unit pressure limit for this dimension.
192// This limit must be adjusted dynamically for reserved registers.
193unsigned MSP430GenRegisterInfo::
194getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
195 static const uint8_t PressureLimitTable[] = {
196 16, // 0: GR8
197 };
198 return PressureLimitTable[Idx];
199}
200
201/// Table of pressure sets per register class or unit.
202static const int RCSetsTable[] = {
203 /* 0 */ 0, -1,
204};
205
206/// Get the dimensions of register pressure impacted by this register class.
207/// Returns a -1 terminated array of pressure set IDs
208const int *MSP430GenRegisterInfo::
209getRegClassPressureSets(const TargetRegisterClass *RC) const {
210 static const uint8_t RCSetStartTable[] = {
211 0,0,};
212 return &RCSetsTable[RCSetStartTable[RC->getID()]];
213}
214
215/// Get the dimensions of register pressure impacted by this register unit.
216/// Returns a -1 terminated array of pressure set IDs
217const int *MSP430GenRegisterInfo::
218getRegUnitPressureSets(MCRegUnit RegUnit) const {
219 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
220 static const uint8_t RUSetStartTable[] = {
221 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,};
222 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
223}
224
225
226// Register to minimal register class mapping
227
228const TargetRegisterClass *MSP430GenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
229 static const uint16_t InvalidRegClassID = UINT16_MAX;
230
231 static const uint16_t Mapping[33] = {
232 InvalidRegClassID, // NoRegister
233 MSP430::GR16RegClassID, // CG
234 MSP430::GR8RegClassID, // CGB
235 MSP430::GR16RegClassID, // PC
236 MSP430::GR8RegClassID, // PCB
237 MSP430::GR16RegClassID, // SP
238 MSP430::GR8RegClassID, // SPB
239 MSP430::GR16RegClassID, // SR
240 MSP430::GR8RegClassID, // SRB
241 MSP430::GR16RegClassID, // R4
242 MSP430::GR16RegClassID, // R5
243 MSP430::GR16RegClassID, // R6
244 MSP430::GR16RegClassID, // R7
245 MSP430::GR16RegClassID, // R8
246 MSP430::GR16RegClassID, // R9
247 MSP430::GR16RegClassID, // R10
248 MSP430::GR16RegClassID, // R11
249 MSP430::GR16RegClassID, // R12
250 MSP430::GR16RegClassID, // R13
251 MSP430::GR16RegClassID, // R14
252 MSP430::GR16RegClassID, // R15
253 MSP430::GR8RegClassID, // R4B
254 MSP430::GR8RegClassID, // R5B
255 MSP430::GR8RegClassID, // R6B
256 MSP430::GR8RegClassID, // R7B
257 MSP430::GR8RegClassID, // R8B
258 MSP430::GR8RegClassID, // R9B
259 MSP430::GR8RegClassID, // R10B
260 MSP430::GR8RegClassID, // R11B
261 MSP430::GR8RegClassID, // R12B
262 MSP430::GR8RegClassID, // R13B
263 MSP430::GR8RegClassID, // R14B
264 MSP430::GR8RegClassID, // R15B
265 };
266
267 assert(Reg < ArrayRef(Mapping).size());
268 unsigned RCID = Mapping[Reg.id()];
269 if (RCID == InvalidRegClassID)
270 return nullptr;
271 return &MSP430MCRegisterClassStorage.Classes[RCID];
272}
273extern const MCRegisterDesc MSP430RegDesc[];
274extern const int16_t MSP430RegDiffLists[];
275extern const LaneBitmask MSP430LaneMaskLists[];
276extern const char MSP430RegStrings[];
277extern const char MSP430RegClassStrings[];
278extern const MCPhysReg MSP430RegUnitRoots[][2];
279extern const uint16_t MSP430SubRegIdxLists[];
280extern const uint16_t MSP430RegEncodingTable[];
281// MSP430 Dwarf<->LLVM register mappings.
282extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0Dwarf2L[];
283extern const unsigned MSP430DwarfFlavour0Dwarf2LSize;
284
285extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0Dwarf2L[];
286extern const unsigned MSP430EHFlavour0Dwarf2LSize;
287
288extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0L2Dwarf[];
289extern const unsigned MSP430DwarfFlavour0L2DwarfSize;
290
291extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0L2Dwarf[];
292extern const unsigned MSP430EHFlavour0L2DwarfSize;
293
294
295MSP430GenRegisterInfo::
296MSP430GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
297 unsigned PC, unsigned HwMode)
298 : TargetRegisterInfo(&MSP430RegInfoDesc,
299 MSP430SubRegIndexStrings, MSP430SubRegIndexNameOffsets,
300 MSP430SubRegIdxRangeTable, MSP430SubRegIndexLaneMaskTable,
301
302 LaneBitmask(0xFFFFFFFFFFFFFFFE), MSP430RegClassInfos, MSP430VTLists, HwMode) {
303 InitMCRegisterInfo(D: MSP430RegDesc, NR: 33, RA, PC,
304 C: &getMSP430MCRegisterClass(RC: 0), NC: 2, RURoots: MSP430RegUnitRoots, NRU: 16, DL: MSP430RegDiffLists,
305 RUMS: MSP430LaneMaskLists, Strings: MSP430RegStrings, ClassStrings: MSP430RegClassStrings, SubIndices: MSP430SubRegIdxLists, NumIndices: 2,
306 RET: MSP430RegEncodingTable, RUI: nullptr);
307
308 switch (DwarfFlavour) {
309 default:
310 llvm_unreachable("Unknown DWARF flavour");
311 case 0:
312 mapDwarfRegsToLLVMRegs(Map: MSP430DwarfFlavour0Dwarf2L, Size: MSP430DwarfFlavour0Dwarf2LSize, isEH: false);
313 break;
314 }
315 switch (EHFlavour) {
316 default:
317 llvm_unreachable("Unknown DWARF flavour");
318 case 0:
319 mapDwarfRegsToLLVMRegs(Map: MSP430EHFlavour0Dwarf2L, Size: MSP430EHFlavour0Dwarf2LSize, isEH: true);
320 break;
321 }
322 switch (DwarfFlavour) {
323 default:
324 llvm_unreachable("Unknown DWARF flavour");
325 case 0:
326 mapLLVMRegsToDwarfRegs(Map: MSP430DwarfFlavour0L2Dwarf, Size: MSP430DwarfFlavour0L2DwarfSize, isEH: false);
327 break;
328 }
329 switch (EHFlavour) {
330 default:
331 llvm_unreachable("Unknown DWARF flavour");
332 case 0:
333 mapLLVMRegsToDwarfRegs(Map: MSP430EHFlavour0L2Dwarf, Size: MSP430EHFlavour0L2DwarfSize, isEH: true);
334 break;
335 }
336}
337
338
339
340ArrayRef<const uint32_t *> MSP430GenRegisterInfo::getRegMasks() const {
341 return {};
342}
343
344bool MSP430GenRegisterInfo::
345isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
346 return
347 false;
348}
349
350bool MSP430GenRegisterInfo::
351isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
352 return
353 false;
354}
355
356bool MSP430GenRegisterInfo::
357isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
358 return
359 false;
360}
361
362bool MSP430GenRegisterInfo::
363isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
364 return
365 false;
366}
367
368bool MSP430GenRegisterInfo::
369isConstantPhysReg(MCRegister PhysReg) const {
370 return
371 false;
372}
373
374ArrayRef<const char *> MSP430GenRegisterInfo::getRegMaskNames() const {
375 return {};
376}
377
378const MSP430FrameLowering *
379MSP430GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
380 return static_cast<const MSP430FrameLowering *>(
381 MF.getSubtarget().getFrameLowering());
382}
383
384
385} // namespace llvm
386