1//===-- MSP430RegisterInfo.cpp - MSP430 Register Information --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the MSP430 implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MSP430RegisterInfo.h"
14#include "MSP430TargetMachine.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/IR/Function.h"
20#include "llvm/Target/TargetMachine.h"
21#include "llvm/Target/TargetOptions.h"
22
23using namespace llvm;
24
25#define DEBUG_TYPE "msp430-reg-info"
26
27#define GET_REGINFO_TARGET_DESC
28#include "MSP430GenRegisterInfo.inc"
29
30// FIXME: Provide proper call frame setup / destroy opcodes.
31MSP430RegisterInfo::MSP430RegisterInfo()
32 : MSP430GenRegisterInfo(MSP430::PC) {}
33
34const MCPhysReg*
35MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
36 const MSP430FrameLowering *TFI = getFrameLowering(MF: *MF);
37 const Function* F = &MF->getFunction();
38 static const MCPhysReg CalleeSavedRegs[] = {
39 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7,
40 MSP430::R8, MSP430::R9, MSP430::R10,
41 0
42 };
43 static const MCPhysReg CalleeSavedRegsFP[] = {
44 MSP430::R5, MSP430::R6, MSP430::R7,
45 MSP430::R8, MSP430::R9, MSP430::R10,
46 0
47 };
48 static const MCPhysReg CalleeSavedRegsIntr[] = {
49 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7,
50 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
51 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
52 0
53 };
54 static const MCPhysReg CalleeSavedRegsIntrFP[] = {
55 MSP430::R5, MSP430::R6, MSP430::R7,
56 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
57 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
58 0
59 };
60
61 if (TFI->hasFP(MF: *MF))
62 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
63 CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
64 else
65 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
66 CalleeSavedRegsIntr : CalleeSavedRegs);
67
68}
69
70BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
71 BitVector Reserved(getNumRegs());
72 const MSP430FrameLowering *TFI = getFrameLowering(MF);
73
74 // Mark 4 special registers with subregisters as reserved.
75 Reserved.set(MSP430::PCB);
76 Reserved.set(MSP430::SPB);
77 Reserved.set(MSP430::SRB);
78 Reserved.set(MSP430::CGB);
79 Reserved.set(MSP430::PC);
80 Reserved.set(MSP430::SP);
81 Reserved.set(MSP430::SR);
82 Reserved.set(MSP430::CG);
83
84 // Mark frame pointer as reserved if needed.
85 if (TFI->hasFP(MF)) {
86 Reserved.set(MSP430::R4B);
87 Reserved.set(MSP430::R4);
88 }
89
90 return Reserved;
91}
92
93const TargetRegisterClass *
94MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
95 return &MSP430::GR16RegClass;
96}
97
98bool
99MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
100 int SPAdj, unsigned FIOperandNum,
101 RegScavenger *RS) const {
102 assert(SPAdj == 0 && "Unexpected");
103
104 MachineInstr &MI = *II;
105 MachineBasicBlock &MBB = *MI.getParent();
106 MachineFunction &MF = *MBB.getParent();
107 const MSP430FrameLowering *TFI = getFrameLowering(MF);
108 DebugLoc dl = MI.getDebugLoc();
109 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
110
111 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::R4 : MSP430::SP);
112 int Offset = MF.getFrameInfo().getObjectOffset(ObjectIdx: FrameIndex);
113
114 // Skip the saved PC
115 Offset += 2;
116
117 if (!TFI->hasFP(MF))
118 Offset += MF.getFrameInfo().getStackSize();
119 else
120 Offset += 2; // Skip the saved FP
121
122 // Fold imm into offset
123 Offset += MI.getOperand(i: FIOperandNum + 1).getImm();
124
125 if (MI.getOpcode() == MSP430::ADDframe) {
126 // This is actually "load effective address" of the stack slot
127 // instruction. We have only two-address instructions, thus we need to
128 // expand it into mov + add
129 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
130
131 MI.setDesc(TII.get(Opcode: MSP430::MOV16rr));
132 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: BasePtr, isDef: false);
133
134 // Remove the now unused Offset operand.
135 MI.removeOperand(OpNo: FIOperandNum + 1);
136
137 if (Offset == 0)
138 return false;
139
140 // We need to materialize the offset via add instruction.
141 Register DstReg = MI.getOperand(i: 0).getReg();
142 if (Offset < 0)
143 BuildMI(BB&: MBB, I: std::next(x: II), MIMD: dl, MCID: TII.get(Opcode: MSP430::SUB16ri), DestReg: DstReg)
144 .addReg(RegNo: DstReg).addImm(Val: -Offset);
145 else
146 BuildMI(BB&: MBB, I: std::next(x: II), MIMD: dl, MCID: TII.get(Opcode: MSP430::ADD16ri), DestReg: DstReg)
147 .addReg(RegNo: DstReg).addImm(Val: Offset);
148
149 return false;
150 }
151
152 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: BasePtr, isDef: false);
153 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset);
154 return false;
155}
156
157Register MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
158 const MSP430FrameLowering *TFI = getFrameLowering(MF);
159 return TFI->hasFP(MF) ? MSP430::R4 : MSP430::SP;
160}
161