1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the PPC target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_imm32SExt16(int64_t Imm) {
12
13 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
14 // sign extended field. Used by instructions like 'addi'.
15 return (int32_t)Imm == (short)Imm;
16
17}
18static bool Predicate_imm64SExt16(int64_t Imm) {
19
20 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
21 // sign extended field. Used by instructions like 'addi'.
22 return (int64_t)Imm == (short)Imm;
23
24}
25static bool Predicate_immSExt5NonZero(int64_t Imm) {
26 return Imm && isInt<5>(x: Imm);
27}
28static bool Predicate_i32immNonAllOneNonZero(int64_t Imm) {
29 return Imm && (Imm != -1);
30}
31
32
33// FastEmit functions for ISD::READCYCLECOUNTER.
34
35Register fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) {
36 if (RetVT.SimpleTy != MVT::i64)
37 return Register();
38 return fastEmitInst_(MachineInstOpcode: PPC::MFTB8, RC: &PPC::G8RCRegClass);
39}
40
41Register fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) {
42 switch (VT.SimpleTy) {
43 case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT);
44 default: return Register();
45 }
46}
47
48// FastEmit functions for PPCISD::GET_TPOINTER.
49
50Register fastEmit_PPCISD_GET_TPOINTER_MVT_i32_(MVT RetVT) {
51 if (RetVT.SimpleTy != MVT::i32)
52 return Register();
53 return fastEmitInst_(MachineInstOpcode: PPC::GETtlsTpointer32AIX, RC: &PPC::GPRCRegClass);
54}
55
56Register fastEmit_PPCISD_GET_TPOINTER_(MVT VT, MVT RetVT) {
57 switch (VT.SimpleTy) {
58 case MVT::i32: return fastEmit_PPCISD_GET_TPOINTER_MVT_i32_(RetVT);
59 default: return Register();
60 }
61}
62
63// FastEmit functions for PPCISD::MFFS.
64
65Register fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) {
66 if (RetVT.SimpleTy != MVT::f64)
67 return Register();
68 if ((Subtarget->hasFPU())) {
69 return fastEmitInst_(MachineInstOpcode: PPC::MFFS, RC: &PPC::F8RCRegClass);
70 }
71 return Register();
72}
73
74Register fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) {
75 switch (VT.SimpleTy) {
76 case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT);
77 default: return Register();
78 }
79}
80
81// FastEmit functions for PPCISD::PPC32_GOT.
82
83Register fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) {
84 if (RetVT.SimpleTy != MVT::i32)
85 return Register();
86 return fastEmitInst_(MachineInstOpcode: PPC::PPC32GOT, RC: &PPC::GPRCRegClass);
87}
88
89Register fastEmit_PPCISD_PPC32_GOT_(MVT VT, MVT RetVT) {
90 switch (VT.SimpleTy) {
91 case MVT::i32: return fastEmit_PPCISD_PPC32_GOT_MVT_i32_(RetVT);
92 default: return Register();
93 }
94}
95
96// Top-level FastEmit function.
97
98Register fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override {
99 switch (Opcode) {
100 case ISD::READCYCLECOUNTER: return fastEmit_ISD_READCYCLECOUNTER_(VT, RetVT);
101 case PPCISD::GET_TPOINTER: return fastEmit_PPCISD_GET_TPOINTER_(VT, RetVT);
102 case PPCISD::MFFS: return fastEmit_PPCISD_MFFS_(VT, RetVT);
103 case PPCISD::PPC32_GOT: return fastEmit_PPCISD_PPC32_GOT_(VT, RetVT);
104 default: return Register();
105 }
106}
107
108// FastEmit functions for ISD::ANY_EXTEND.
109
110Register fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(Register Op0) {
111 if ((Subtarget->isISA3_1())) {
112 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC, RC: &PPC::GPRCRegClass, Op0);
113 }
114 return Register();
115}
116
117Register fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(Register Op0) {
118 if ((Subtarget->isISA3_1())) {
119 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC8, RC: &PPC::G8RCRegClass, Op0);
120 }
121 return Register();
122}
123
124Register fastEmit_ISD_ANY_EXTEND_MVT_i1_r(MVT RetVT, Register Op0) {
125switch (RetVT.SimpleTy) {
126 case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(Op0);
127 case MVT::i64: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(Op0);
128 default: return Register();
129}
130}
131
132Register fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
133 switch (VT.SimpleTy) {
134 case MVT::i1: return fastEmit_ISD_ANY_EXTEND_MVT_i1_r(RetVT, Op0);
135 default: return Register();
136 }
137}
138
139// FastEmit functions for ISD::BITCAST.
140
141Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
142 if (RetVT.SimpleTy != MVT::f64)
143 return Register();
144 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
145 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRD, RC: &PPC::VSFRCRegClass, Op0);
146 }
147 return Register();
148}
149
150Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
151 if (RetVT.SimpleTy != MVT::i64)
152 return Register();
153 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
154 return fastEmitInst_r(MachineInstOpcode: PPC::MFVSRD, RC: &PPC::G8RCRegClass, Op0);
155 }
156 return Register();
157}
158
159Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
160 switch (VT.SimpleTy) {
161 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
162 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
163 default: return Register();
164 }
165}
166
167// FastEmit functions for ISD::BSWAP.
168
169Register fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, Register Op0) {
170 if (RetVT.SimpleTy != MVT::i32)
171 return Register();
172 if ((Subtarget->isISA3_1())) {
173 return fastEmitInst_r(MachineInstOpcode: PPC::BRW, RC: &PPC::GPRCRegClass, Op0);
174 }
175 return Register();
176}
177
178Register fastEmit_ISD_BSWAP_MVT_i64_r(MVT RetVT, Register Op0) {
179 if (RetVT.SimpleTy != MVT::i64)
180 return Register();
181 if ((Subtarget->isISA3_1())) {
182 return fastEmitInst_r(MachineInstOpcode: PPC::BRD, RC: &PPC::G8RCRegClass, Op0);
183 }
184 return Register();
185}
186
187Register fastEmit_ISD_BSWAP_MVT_v4i32_r(MVT RetVT, Register Op0) {
188 if (RetVT.SimpleTy != MVT::v4i32)
189 return Register();
190 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
191 return fastEmitInst_r(MachineInstOpcode: PPC::XXBRW, RC: &PPC::VSRCRegClass, Op0);
192 }
193 return Register();
194}
195
196Register fastEmit_ISD_BSWAP_MVT_v2i64_r(MVT RetVT, Register Op0) {
197 if (RetVT.SimpleTy != MVT::v2i64)
198 return Register();
199 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
200 return fastEmitInst_r(MachineInstOpcode: PPC::XXBRD, RC: &PPC::VSRCRegClass, Op0);
201 }
202 return Register();
203}
204
205Register fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, Register Op0) {
206 switch (VT.SimpleTy) {
207 case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0);
208 case MVT::i64: return fastEmit_ISD_BSWAP_MVT_i64_r(RetVT, Op0);
209 case MVT::v4i32: return fastEmit_ISD_BSWAP_MVT_v4i32_r(RetVT, Op0);
210 case MVT::v2i64: return fastEmit_ISD_BSWAP_MVT_v2i64_r(RetVT, Op0);
211 default: return Register();
212 }
213}
214
215// FastEmit functions for ISD::CTLZ.
216
217Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
218 if (RetVT.SimpleTy != MVT::i32)
219 return Register();
220 return fastEmitInst_r(MachineInstOpcode: PPC::CNTLZW, RC: &PPC::GPRCRegClass, Op0);
221}
222
223Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
224 if (RetVT.SimpleTy != MVT::i64)
225 return Register();
226 return fastEmitInst_r(MachineInstOpcode: PPC::CNTLZD, RC: &PPC::G8RCRegClass, Op0);
227}
228
229Register fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, Register Op0) {
230 if (RetVT.SimpleTy != MVT::v16i8)
231 return Register();
232 if ((Subtarget->hasP8Altivec())) {
233 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZB, RC: &PPC::VRRCRegClass, Op0);
234 }
235 return Register();
236}
237
238Register fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, Register Op0) {
239 if (RetVT.SimpleTy != MVT::v8i16)
240 return Register();
241 if ((Subtarget->hasP8Altivec())) {
242 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZH, RC: &PPC::VRRCRegClass, Op0);
243 }
244 return Register();
245}
246
247Register fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, Register Op0) {
248 if (RetVT.SimpleTy != MVT::v4i32)
249 return Register();
250 if ((Subtarget->hasP8Altivec())) {
251 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZW, RC: &PPC::VRRCRegClass, Op0);
252 }
253 return Register();
254}
255
256Register fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, Register Op0) {
257 if (RetVT.SimpleTy != MVT::v2i64)
258 return Register();
259 if ((Subtarget->hasP8Altivec())) {
260 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZD, RC: &PPC::VRRCRegClass, Op0);
261 }
262 return Register();
263}
264
265Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
266 switch (VT.SimpleTy) {
267 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
268 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
269 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0);
270 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0);
271 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0);
272 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0);
273 default: return Register();
274 }
275}
276
277// FastEmit functions for ISD::CTPOP.
278
279Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
280 if (RetVT.SimpleTy != MVT::i32)
281 return Register();
282 return fastEmitInst_r(MachineInstOpcode: PPC::POPCNTW, RC: &PPC::GPRCRegClass, Op0);
283}
284
285Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
286 if (RetVT.SimpleTy != MVT::i64)
287 return Register();
288 return fastEmitInst_r(MachineInstOpcode: PPC::POPCNTD, RC: &PPC::G8RCRegClass, Op0);
289}
290
291Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
292 if (RetVT.SimpleTy != MVT::v16i8)
293 return Register();
294 if ((Subtarget->hasP8Altivec())) {
295 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTB, RC: &PPC::VRRCRegClass, Op0);
296 }
297 return Register();
298}
299
300Register fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, Register Op0) {
301 if (RetVT.SimpleTy != MVT::v8i16)
302 return Register();
303 if ((Subtarget->hasP8Altivec())) {
304 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTH, RC: &PPC::VRRCRegClass, Op0);
305 }
306 return Register();
307}
308
309Register fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, Register Op0) {
310 if (RetVT.SimpleTy != MVT::v4i32)
311 return Register();
312 if ((Subtarget->hasP8Altivec())) {
313 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTW, RC: &PPC::VRRCRegClass, Op0);
314 }
315 return Register();
316}
317
318Register fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, Register Op0) {
319 if (RetVT.SimpleTy != MVT::v2i64)
320 return Register();
321 if ((Subtarget->hasP8Altivec())) {
322 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTD, RC: &PPC::VRRCRegClass, Op0);
323 }
324 return Register();
325}
326
327Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
328 switch (VT.SimpleTy) {
329 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
330 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
331 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
332 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0);
333 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0);
334 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0);
335 default: return Register();
336 }
337}
338
339// FastEmit functions for ISD::CTTZ.
340
341Register fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, Register Op0) {
342 if (RetVT.SimpleTy != MVT::i32)
343 return Register();
344 if ((Subtarget->isISA3_0())) {
345 return fastEmitInst_r(MachineInstOpcode: PPC::CNTTZW, RC: &PPC::GPRCRegClass, Op0);
346 }
347 return Register();
348}
349
350Register fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, Register Op0) {
351 if (RetVT.SimpleTy != MVT::i64)
352 return Register();
353 if ((Subtarget->isISA3_0())) {
354 return fastEmitInst_r(MachineInstOpcode: PPC::CNTTZD, RC: &PPC::G8RCRegClass, Op0);
355 }
356 return Register();
357}
358
359Register fastEmit_ISD_CTTZ_MVT_v16i8_r(MVT RetVT, Register Op0) {
360 if (RetVT.SimpleTy != MVT::v16i8)
361 return Register();
362 if ((Subtarget->hasP9Altivec())) {
363 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZB, RC: &PPC::VRRCRegClass, Op0);
364 }
365 return Register();
366}
367
368Register fastEmit_ISD_CTTZ_MVT_v8i16_r(MVT RetVT, Register Op0) {
369 if (RetVT.SimpleTy != MVT::v8i16)
370 return Register();
371 if ((Subtarget->hasP9Altivec())) {
372 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZH, RC: &PPC::VRRCRegClass, Op0);
373 }
374 return Register();
375}
376
377Register fastEmit_ISD_CTTZ_MVT_v4i32_r(MVT RetVT, Register Op0) {
378 if (RetVT.SimpleTy != MVT::v4i32)
379 return Register();
380 if ((Subtarget->hasP9Altivec())) {
381 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZW, RC: &PPC::VRRCRegClass, Op0);
382 }
383 return Register();
384}
385
386Register fastEmit_ISD_CTTZ_MVT_v2i64_r(MVT RetVT, Register Op0) {
387 if (RetVT.SimpleTy != MVT::v2i64)
388 return Register();
389 if ((Subtarget->hasP9Altivec())) {
390 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZD, RC: &PPC::VRRCRegClass, Op0);
391 }
392 return Register();
393}
394
395Register fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, Register Op0) {
396 switch (VT.SimpleTy) {
397 case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0);
398 case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0);
399 case MVT::v16i8: return fastEmit_ISD_CTTZ_MVT_v16i8_r(RetVT, Op0);
400 case MVT::v8i16: return fastEmit_ISD_CTTZ_MVT_v8i16_r(RetVT, Op0);
401 case MVT::v4i32: return fastEmit_ISD_CTTZ_MVT_v4i32_r(RetVT, Op0);
402 case MVT::v2i64: return fastEmit_ISD_CTTZ_MVT_v2i64_r(RetVT, Op0);
403 default: return Register();
404 }
405}
406
407// FastEmit functions for ISD::FABS.
408
409Register fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, Register Op0) {
410 if (RetVT.SimpleTy != MVT::f32)
411 return Register();
412 if ((Subtarget->hasSPE())) {
413 return fastEmitInst_r(MachineInstOpcode: PPC::EFSABS, RC: &PPC::GPRCRegClass, Op0);
414 }
415 if ((Subtarget->hasFPU())) {
416 return fastEmitInst_r(MachineInstOpcode: PPC::FABSS, RC: &PPC::F4RCRegClass, Op0);
417 }
418 return Register();
419}
420
421Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
422 if (RetVT.SimpleTy != MVT::f64)
423 return Register();
424 if ((Subtarget->hasVSX())) {
425 return fastEmitInst_r(MachineInstOpcode: PPC::XSABSDP, RC: &PPC::VSFRCRegClass, Op0);
426 }
427 if ((Subtarget->hasSPE())) {
428 return fastEmitInst_r(MachineInstOpcode: PPC::EFDABS, RC: &PPC::SPERCRegClass, Op0);
429 }
430 if ((Subtarget->hasFPU())) {
431 return fastEmitInst_r(MachineInstOpcode: PPC::FABSD, RC: &PPC::F8RCRegClass, Op0);
432 }
433 return Register();
434}
435
436Register fastEmit_ISD_FABS_MVT_f128_r(MVT RetVT, Register Op0) {
437 if (RetVT.SimpleTy != MVT::f128)
438 return Register();
439 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
440 return fastEmitInst_r(MachineInstOpcode: PPC::XSABSQP, RC: &PPC::VRRCRegClass, Op0);
441 }
442 return Register();
443}
444
445Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
446 if (RetVT.SimpleTy != MVT::v4f32)
447 return Register();
448 if ((Subtarget->hasVSX())) {
449 return fastEmitInst_r(MachineInstOpcode: PPC::XVABSSP, RC: &PPC::VSRCRegClass, Op0);
450 }
451 return Register();
452}
453
454Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
455 if (RetVT.SimpleTy != MVT::v2f64)
456 return Register();
457 if ((Subtarget->hasVSX())) {
458 return fastEmitInst_r(MachineInstOpcode: PPC::XVABSDP, RC: &PPC::VSRCRegClass, Op0);
459 }
460 return Register();
461}
462
463Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
464 switch (VT.SimpleTy) {
465 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
466 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
467 case MVT::f128: return fastEmit_ISD_FABS_MVT_f128_r(RetVT, Op0);
468 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
469 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
470 default: return Register();
471 }
472}
473
474// FastEmit functions for ISD::FCEIL.
475
476Register fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, Register Op0) {
477 if (RetVT.SimpleTy != MVT::f32)
478 return Register();
479 if ((Subtarget->hasFPU())) {
480 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPS, RC: &PPC::F4RCRegClass, Op0);
481 }
482 return Register();
483}
484
485Register fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, Register Op0) {
486 if (RetVT.SimpleTy != MVT::f64)
487 return Register();
488 if ((Subtarget->hasVSX())) {
489 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIP, RC: &PPC::VSFRCRegClass, Op0);
490 }
491 if ((Subtarget->hasFPU())) {
492 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPD, RC: &PPC::F8RCRegClass, Op0);
493 }
494 return Register();
495}
496
497Register fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, Register Op0) {
498 if (RetVT.SimpleTy != MVT::v4f32)
499 return Register();
500 if ((Subtarget->hasVSX())) {
501 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIP, RC: &PPC::VSRCRegClass, Op0);
502 }
503 if ((Subtarget->hasAltivec())) {
504 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIP, RC: &PPC::VRRCRegClass, Op0);
505 }
506 return Register();
507}
508
509Register fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, Register Op0) {
510 if (RetVT.SimpleTy != MVT::v2f64)
511 return Register();
512 if ((Subtarget->hasVSX())) {
513 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIP, RC: &PPC::VSRCRegClass, Op0);
514 }
515 return Register();
516}
517
518Register fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, Register Op0) {
519 switch (VT.SimpleTy) {
520 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0);
521 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0);
522 case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0);
523 case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0);
524 default: return Register();
525 }
526}
527
528// FastEmit functions for ISD::FFLOOR.
529
530Register fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, Register Op0) {
531 if (RetVT.SimpleTy != MVT::f32)
532 return Register();
533 if ((Subtarget->hasFPU())) {
534 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMS, RC: &PPC::F4RCRegClass, Op0);
535 }
536 return Register();
537}
538
539Register fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, Register Op0) {
540 if (RetVT.SimpleTy != MVT::f64)
541 return Register();
542 if ((Subtarget->hasVSX())) {
543 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIM, RC: &PPC::VSFRCRegClass, Op0);
544 }
545 if ((Subtarget->hasFPU())) {
546 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMD, RC: &PPC::F8RCRegClass, Op0);
547 }
548 return Register();
549}
550
551Register fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, Register Op0) {
552 if (RetVT.SimpleTy != MVT::v4f32)
553 return Register();
554 if ((Subtarget->hasVSX())) {
555 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIM, RC: &PPC::VSRCRegClass, Op0);
556 }
557 if ((Subtarget->hasAltivec())) {
558 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIM, RC: &PPC::VRRCRegClass, Op0);
559 }
560 return Register();
561}
562
563Register fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, Register Op0) {
564 if (RetVT.SimpleTy != MVT::v2f64)
565 return Register();
566 if ((Subtarget->hasVSX())) {
567 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIM, RC: &PPC::VSRCRegClass, Op0);
568 }
569 return Register();
570}
571
572Register fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, Register Op0) {
573 switch (VT.SimpleTy) {
574 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0);
575 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0);
576 case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0);
577 case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0);
578 default: return Register();
579 }
580}
581
582// FastEmit functions for ISD::FNEARBYINT.
583
584Register fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
585 if (RetVT.SimpleTy != MVT::v4f32)
586 return Register();
587 if ((Subtarget->hasAltivec())) {
588 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIN, RC: &PPC::VRRCRegClass, Op0);
589 }
590 return Register();
591}
592
593Register fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, Register Op0) {
594 switch (VT.SimpleTy) {
595 case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0);
596 default: return Register();
597 }
598}
599
600// FastEmit functions for ISD::FNEG.
601
602Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
603 if (RetVT.SimpleTy != MVT::f32)
604 return Register();
605 if ((Subtarget->hasSPE())) {
606 return fastEmitInst_r(MachineInstOpcode: PPC::EFSNEG, RC: &PPC::GPRCRegClass, Op0);
607 }
608 if ((Subtarget->hasFPU())) {
609 return fastEmitInst_r(MachineInstOpcode: PPC::FNEGS, RC: &PPC::F4RCRegClass, Op0);
610 }
611 return Register();
612}
613
614Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
615 if (RetVT.SimpleTy != MVT::f64)
616 return Register();
617 if ((Subtarget->hasVSX())) {
618 return fastEmitInst_r(MachineInstOpcode: PPC::XSNEGDP, RC: &PPC::VSFRCRegClass, Op0);
619 }
620 if ((Subtarget->hasSPE())) {
621 return fastEmitInst_r(MachineInstOpcode: PPC::EFDNEG, RC: &PPC::SPERCRegClass, Op0);
622 }
623 if ((Subtarget->hasFPU())) {
624 return fastEmitInst_r(MachineInstOpcode: PPC::FNEGD, RC: &PPC::F8RCRegClass, Op0);
625 }
626 return Register();
627}
628
629Register fastEmit_ISD_FNEG_MVT_f128_r(MVT RetVT, Register Op0) {
630 if (RetVT.SimpleTy != MVT::f128)
631 return Register();
632 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
633 return fastEmitInst_r(MachineInstOpcode: PPC::XSNEGQP, RC: &PPC::VRRCRegClass, Op0);
634 }
635 return Register();
636}
637
638Register fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, Register Op0) {
639 if (RetVT.SimpleTy != MVT::v4f32)
640 return Register();
641 if ((Subtarget->hasVSX())) {
642 return fastEmitInst_r(MachineInstOpcode: PPC::XVNEGSP, RC: &PPC::VSRCRegClass, Op0);
643 }
644 return Register();
645}
646
647Register fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, Register Op0) {
648 if (RetVT.SimpleTy != MVT::v2f64)
649 return Register();
650 if ((Subtarget->hasVSX())) {
651 return fastEmitInst_r(MachineInstOpcode: PPC::XVNEGDP, RC: &PPC::VSRCRegClass, Op0);
652 }
653 return Register();
654}
655
656Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
657 switch (VT.SimpleTy) {
658 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
659 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
660 case MVT::f128: return fastEmit_ISD_FNEG_MVT_f128_r(RetVT, Op0);
661 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0);
662 case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0);
663 default: return Register();
664 }
665}
666
667// FastEmit functions for ISD::FP_EXTEND.
668
669Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
670 if (RetVT.SimpleTy != MVT::f64)
671 return Register();
672 if ((Subtarget->hasSPE())) {
673 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFS, RC: &PPC::SPERCRegClass, Op0);
674 }
675 return Register();
676}
677
678Register fastEmit_ISD_FP_EXTEND_MVT_f64_r(MVT RetVT, Register Op0) {
679 if (RetVT.SimpleTy != MVT::f128)
680 return Register();
681 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
682 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPQP, RC: &PPC::VRRCRegClass, Op0);
683 }
684 return Register();
685}
686
687Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
688 switch (VT.SimpleTy) {
689 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
690 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f64_r(RetVT, Op0);
691 default: return Register();
692 }
693}
694
695// FastEmit functions for ISD::FP_ROUND.
696
697Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
698 if (RetVT.SimpleTy != MVT::f32)
699 return Register();
700 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
701 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSP, RC: &PPC::VSSRCRegClass, Op0);
702 }
703 if ((Subtarget->hasSPE())) {
704 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFD, RC: &PPC::GPRCRegClass, Op0);
705 }
706 if ((Subtarget->hasFPU())) {
707 return fastEmitInst_r(MachineInstOpcode: PPC::FRSP, RC: &PPC::F4RCRegClass, Op0);
708 }
709 return Register();
710}
711
712Register fastEmit_ISD_FP_ROUND_MVT_f128_r(MVT RetVT, Register Op0) {
713 if (RetVT.SimpleTy != MVT::f64)
714 return Register();
715 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
716 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPDP, RC: &PPC::VFRCRegClass, Op0);
717 }
718 return Register();
719}
720
721Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
722 switch (VT.SimpleTy) {
723 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
724 case MVT::f128: return fastEmit_ISD_FP_ROUND_MVT_f128_r(RetVT, Op0);
725 default: return Register();
726 }
727}
728
729// FastEmit functions for ISD::FP_TO_SINT.
730
731Register fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, Register Op0) {
732 if (RetVT.SimpleTy != MVT::i32)
733 return Register();
734 if ((Subtarget->hasSPE())) {
735 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTSIZ, RC: &PPC::GPRCRegClass, Op0);
736 }
737 return Register();
738}
739
740Register fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, Register Op0) {
741 if (RetVT.SimpleTy != MVT::i32)
742 return Register();
743 if ((Subtarget->hasSPE())) {
744 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTSIZ, RC: &PPC::GPRCRegClass, Op0);
745 }
746 return Register();
747}
748
749Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
750 if (RetVT.SimpleTy != MVT::v4i32)
751 return Register();
752 if ((Subtarget->hasVSX())) {
753 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPSXWS, RC: &PPC::VSRCRegClass, Op0);
754 }
755 if ((Subtarget->hasAltivec())) {
756 return fastEmitInst_r(MachineInstOpcode: PPC::VCTSXS_0, RC: &PPC::VRRCRegClass, Op0);
757 }
758 return Register();
759}
760
761Register fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
762 if (RetVT.SimpleTy != MVT::v2i64)
763 return Register();
764 if ((Subtarget->hasVSX())) {
765 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPSXDS, RC: &PPC::VSRCRegClass, Op0);
766 }
767 return Register();
768}
769
770Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
771 switch (VT.SimpleTy) {
772 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
773 case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
774 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
775 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
776 default: return Register();
777 }
778}
779
780// FastEmit functions for ISD::FP_TO_UINT.
781
782Register fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, Register Op0) {
783 if (RetVT.SimpleTy != MVT::i32)
784 return Register();
785 if ((Subtarget->hasSPE())) {
786 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTUIZ, RC: &PPC::GPRCRegClass, Op0);
787 }
788 return Register();
789}
790
791Register fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, Register Op0) {
792 if (RetVT.SimpleTy != MVT::i32)
793 return Register();
794 if ((Subtarget->hasSPE())) {
795 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTUIZ, RC: &PPC::GPRCRegClass, Op0);
796 }
797 return Register();
798}
799
800Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
801 if (RetVT.SimpleTy != MVT::v4i32)
802 return Register();
803 if ((Subtarget->hasVSX())) {
804 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPUXWS, RC: &PPC::VSRCRegClass, Op0);
805 }
806 if ((Subtarget->hasAltivec())) {
807 return fastEmitInst_r(MachineInstOpcode: PPC::VCTUXS_0, RC: &PPC::VRRCRegClass, Op0);
808 }
809 return Register();
810}
811
812Register fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
813 if (RetVT.SimpleTy != MVT::v2i64)
814 return Register();
815 if ((Subtarget->hasVSX())) {
816 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPUXDS, RC: &PPC::VSRCRegClass, Op0);
817 }
818 return Register();
819}
820
821Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
822 switch (VT.SimpleTy) {
823 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
824 case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
825 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
826 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
827 default: return Register();
828 }
829}
830
831// FastEmit functions for ISD::FRINT.
832
833Register fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, Register Op0) {
834 if (RetVT.SimpleTy != MVT::f64)
835 return Register();
836 if ((Subtarget->hasVSX())) {
837 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIC, RC: &PPC::VSFRCRegClass, Op0);
838 }
839 return Register();
840}
841
842Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
843 if (RetVT.SimpleTy != MVT::v4f32)
844 return Register();
845 if ((Subtarget->hasVSX())) {
846 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIC, RC: &PPC::VSRCRegClass, Op0);
847 }
848 return Register();
849}
850
851Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
852 if (RetVT.SimpleTy != MVT::v2f64)
853 return Register();
854 if ((Subtarget->hasVSX())) {
855 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIC, RC: &PPC::VSRCRegClass, Op0);
856 }
857 return Register();
858}
859
860Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
861 switch (VT.SimpleTy) {
862 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0);
863 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
864 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
865 default: return Register();
866 }
867}
868
869// FastEmit functions for ISD::FROUND.
870
871Register fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, Register Op0) {
872 if (RetVT.SimpleTy != MVT::f32)
873 return Register();
874 if ((Subtarget->hasFPU())) {
875 return fastEmitInst_r(MachineInstOpcode: PPC::FRINS, RC: &PPC::F4RCRegClass, Op0);
876 }
877 return Register();
878}
879
880Register fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, Register Op0) {
881 if (RetVT.SimpleTy != MVT::f64)
882 return Register();
883 if ((Subtarget->hasVSX())) {
884 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPI, RC: &PPC::VSFRCRegClass, Op0);
885 }
886 if ((Subtarget->hasFPU())) {
887 return fastEmitInst_r(MachineInstOpcode: PPC::FRIND, RC: &PPC::F8RCRegClass, Op0);
888 }
889 return Register();
890}
891
892Register fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, Register Op0) {
893 if (RetVT.SimpleTy != MVT::v4f32)
894 return Register();
895 if ((Subtarget->hasVSX())) {
896 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPI, RC: &PPC::VSRCRegClass, Op0);
897 }
898 return Register();
899}
900
901Register fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, Register Op0) {
902 if (RetVT.SimpleTy != MVT::v2f64)
903 return Register();
904 if ((Subtarget->hasVSX())) {
905 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPI, RC: &PPC::VSRCRegClass, Op0);
906 }
907 return Register();
908}
909
910Register fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, Register Op0) {
911 switch (VT.SimpleTy) {
912 case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0);
913 case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0);
914 case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0);
915 case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0);
916 default: return Register();
917 }
918}
919
920// FastEmit functions for ISD::FSQRT.
921
922Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
923 if (RetVT.SimpleTy != MVT::f32)
924 return Register();
925 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
926 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTSP, RC: &PPC::VSSRCRegClass, Op0);
927 }
928 if ((Subtarget->hasFPU())) {
929 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRTS, RC: &PPC::F4RCRegClass, Op0);
930 }
931 return Register();
932}
933
934Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
935 if (RetVT.SimpleTy != MVT::f64)
936 return Register();
937 if ((Subtarget->hasVSX())) {
938 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTDP, RC: &PPC::VSFRCRegClass, Op0);
939 }
940 if ((Subtarget->hasFPU())) {
941 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRT, RC: &PPC::F8RCRegClass, Op0);
942 }
943 return Register();
944}
945
946Register fastEmit_ISD_FSQRT_MVT_f128_r(MVT RetVT, Register Op0) {
947 if (RetVT.SimpleTy != MVT::f128)
948 return Register();
949 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
950 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTQP, RC: &PPC::VRRCRegClass, Op0);
951 }
952 return Register();
953}
954
955Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
956 if (RetVT.SimpleTy != MVT::v4f32)
957 return Register();
958 if ((Subtarget->hasVSX())) {
959 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTSP, RC: &PPC::VSRCRegClass, Op0);
960 }
961 return Register();
962}
963
964Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
965 if (RetVT.SimpleTy != MVT::v2f64)
966 return Register();
967 if ((Subtarget->hasVSX())) {
968 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTDP, RC: &PPC::VSRCRegClass, Op0);
969 }
970 return Register();
971}
972
973Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
974 switch (VT.SimpleTy) {
975 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
976 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
977 case MVT::f128: return fastEmit_ISD_FSQRT_MVT_f128_r(RetVT, Op0);
978 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
979 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
980 default: return Register();
981 }
982}
983
984// FastEmit functions for ISD::FTRUNC.
985
986Register fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, Register Op0) {
987 if (RetVT.SimpleTy != MVT::f32)
988 return Register();
989 if ((Subtarget->hasFPU())) {
990 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZS, RC: &PPC::F4RCRegClass, Op0);
991 }
992 return Register();
993}
994
995Register fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, Register Op0) {
996 if (RetVT.SimpleTy != MVT::f64)
997 return Register();
998 if ((Subtarget->hasVSX())) {
999 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIZ, RC: &PPC::VSFRCRegClass, Op0);
1000 }
1001 if ((Subtarget->hasFPU())) {
1002 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZD, RC: &PPC::F8RCRegClass, Op0);
1003 }
1004 return Register();
1005}
1006
1007Register fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, Register Op0) {
1008 if (RetVT.SimpleTy != MVT::v4f32)
1009 return Register();
1010 if ((Subtarget->hasVSX())) {
1011 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIZ, RC: &PPC::VSRCRegClass, Op0);
1012 }
1013 if ((Subtarget->hasAltivec())) {
1014 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIZ, RC: &PPC::VRRCRegClass, Op0);
1015 }
1016 return Register();
1017}
1018
1019Register fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, Register Op0) {
1020 if (RetVT.SimpleTy != MVT::v2f64)
1021 return Register();
1022 if ((Subtarget->hasVSX())) {
1023 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIZ, RC: &PPC::VSRCRegClass, Op0);
1024 }
1025 return Register();
1026}
1027
1028Register fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, Register Op0) {
1029 switch (VT.SimpleTy) {
1030 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0);
1031 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0);
1032 case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0);
1033 case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0);
1034 default: return Register();
1035 }
1036}
1037
1038// FastEmit functions for ISD::SCALAR_TO_VECTOR.
1039
1040Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, Register Op0) {
1041 if (RetVT.SimpleTy != MVT::v4i32)
1042 return Register();
1043 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1044 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRWS, RC: &PPC::VSRCRegClass, Op0);
1045 }
1046 return Register();
1047}
1048
1049Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, Register Op0) {
1050 if (RetVT.SimpleTy != MVT::v4f32)
1051 return Register();
1052 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) {
1053 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSPN, RC: &PPC::VSRCRegClass, Op0);
1054 }
1055 return Register();
1056}
1057
1058Register fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, Register Op0) {
1059 switch (VT.SimpleTy) {
1060 case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0);
1061 case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0);
1062 default: return Register();
1063 }
1064}
1065
1066// FastEmit functions for ISD::SIGN_EXTEND.
1067
1068Register fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(Register Op0) {
1069 if ((Subtarget->isISA3_1())) {
1070 return fastEmitInst_r(MachineInstOpcode: PPC::SETNBC, RC: &PPC::GPRCRegClass, Op0);
1071 }
1072 return Register();
1073}
1074
1075Register fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(Register Op0) {
1076 if ((Subtarget->isISA3_1())) {
1077 return fastEmitInst_r(MachineInstOpcode: PPC::SETNBC8, RC: &PPC::G8RCRegClass, Op0);
1078 }
1079 return Register();
1080}
1081
1082Register fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(MVT RetVT, Register Op0) {
1083switch (RetVT.SimpleTy) {
1084 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(Op0);
1085 case MVT::i64: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(Op0);
1086 default: return Register();
1087}
1088}
1089
1090Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
1091 if (RetVT.SimpleTy != MVT::i64)
1092 return Register();
1093 return fastEmitInst_r(MachineInstOpcode: PPC::EXTSW_32_64, RC: &PPC::G8RCRegClass, Op0);
1094}
1095
1096Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
1097 switch (VT.SimpleTy) {
1098 case MVT::i1: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(RetVT, Op0);
1099 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
1100 default: return Register();
1101 }
1102}
1103
1104// FastEmit functions for ISD::SINT_TO_FP.
1105
1106Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1107 if ((Subtarget->hasSPE())) {
1108 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFSI, RC: &PPC::GPRCRegClass, Op0);
1109 }
1110 return Register();
1111}
1112
1113Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1114 if ((Subtarget->hasSPE())) {
1115 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFSI, RC: &PPC::SPERCRegClass, Op0);
1116 }
1117 return Register();
1118}
1119
1120Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1121switch (RetVT.SimpleTy) {
1122 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1123 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1124 default: return Register();
1125}
1126}
1127
1128Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1129 if (RetVT.SimpleTy != MVT::v4f32)
1130 return Register();
1131 if ((Subtarget->hasVSX())) {
1132 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXWSP, RC: &PPC::VSRCRegClass, Op0);
1133 }
1134 if ((Subtarget->hasAltivec())) {
1135 return fastEmitInst_r(MachineInstOpcode: PPC::VCFSX_0, RC: &PPC::VRRCRegClass, Op0);
1136 }
1137 return Register();
1138}
1139
1140Register fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
1141 if (RetVT.SimpleTy != MVT::v2f64)
1142 return Register();
1143 if ((Subtarget->hasVSX())) {
1144 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXDDP, RC: &PPC::VSRCRegClass, Op0);
1145 }
1146 return Register();
1147}
1148
1149Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1150 switch (VT.SimpleTy) {
1151 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
1152 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1153 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1154 default: return Register();
1155 }
1156}
1157
1158// FastEmit functions for ISD::STRICT_FCEIL.
1159
1160Register fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(MVT RetVT, Register Op0) {
1161 if (RetVT.SimpleTy != MVT::f32)
1162 return Register();
1163 if ((Subtarget->hasFPU())) {
1164 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPS, RC: &PPC::F4RCRegClass, Op0);
1165 }
1166 return Register();
1167}
1168
1169Register fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(MVT RetVT, Register Op0) {
1170 if (RetVT.SimpleTy != MVT::f64)
1171 return Register();
1172 if ((Subtarget->hasVSX())) {
1173 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIP, RC: &PPC::VSFRCRegClass, Op0);
1174 }
1175 if ((Subtarget->hasFPU())) {
1176 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPD, RC: &PPC::F8RCRegClass, Op0);
1177 }
1178 return Register();
1179}
1180
1181Register fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(MVT RetVT, Register Op0) {
1182 if (RetVT.SimpleTy != MVT::v4f32)
1183 return Register();
1184 if ((Subtarget->hasVSX())) {
1185 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIP, RC: &PPC::VSRCRegClass, Op0);
1186 }
1187 return Register();
1188}
1189
1190Register fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(MVT RetVT, Register Op0) {
1191 if (RetVT.SimpleTy != MVT::v2f64)
1192 return Register();
1193 if ((Subtarget->hasVSX())) {
1194 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIP, RC: &PPC::VSRCRegClass, Op0);
1195 }
1196 return Register();
1197}
1198
1199Register fastEmit_ISD_STRICT_FCEIL_r(MVT VT, MVT RetVT, Register Op0) {
1200 switch (VT.SimpleTy) {
1201 case MVT::f32: return fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(RetVT, Op0);
1202 case MVT::f64: return fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(RetVT, Op0);
1203 case MVT::v4f32: return fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(RetVT, Op0);
1204 case MVT::v2f64: return fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(RetVT, Op0);
1205 default: return Register();
1206 }
1207}
1208
1209// FastEmit functions for ISD::STRICT_FFLOOR.
1210
1211Register fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(MVT RetVT, Register Op0) {
1212 if (RetVT.SimpleTy != MVT::f32)
1213 return Register();
1214 if ((Subtarget->hasFPU())) {
1215 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMS, RC: &PPC::F4RCRegClass, Op0);
1216 }
1217 return Register();
1218}
1219
1220Register fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(MVT RetVT, Register Op0) {
1221 if (RetVT.SimpleTy != MVT::f64)
1222 return Register();
1223 if ((Subtarget->hasVSX())) {
1224 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIM, RC: &PPC::VSFRCRegClass, Op0);
1225 }
1226 if ((Subtarget->hasFPU())) {
1227 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMD, RC: &PPC::F8RCRegClass, Op0);
1228 }
1229 return Register();
1230}
1231
1232Register fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(MVT RetVT, Register Op0) {
1233 if (RetVT.SimpleTy != MVT::v4f32)
1234 return Register();
1235 if ((Subtarget->hasVSX())) {
1236 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIM, RC: &PPC::VSRCRegClass, Op0);
1237 }
1238 return Register();
1239}
1240
1241Register fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(MVT RetVT, Register Op0) {
1242 if (RetVT.SimpleTy != MVT::v2f64)
1243 return Register();
1244 if ((Subtarget->hasVSX())) {
1245 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIM, RC: &PPC::VSRCRegClass, Op0);
1246 }
1247 return Register();
1248}
1249
1250Register fastEmit_ISD_STRICT_FFLOOR_r(MVT VT, MVT RetVT, Register Op0) {
1251 switch (VT.SimpleTy) {
1252 case MVT::f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(RetVT, Op0);
1253 case MVT::f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(RetVT, Op0);
1254 case MVT::v4f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(RetVT, Op0);
1255 case MVT::v2f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(RetVT, Op0);
1256 default: return Register();
1257 }
1258}
1259
1260// FastEmit functions for ISD::STRICT_FNEARBYINT.
1261
1262Register fastEmit_ISD_STRICT_FNEARBYINT_MVT_f64_r(MVT RetVT, Register Op0) {
1263 if (RetVT.SimpleTy != MVT::f64)
1264 return Register();
1265 if ((Subtarget->hasVSX())) {
1266 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIC, RC: &PPC::VSFRCRegClass, Op0);
1267 }
1268 return Register();
1269}
1270
1271Register fastEmit_ISD_STRICT_FNEARBYINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1272 if (RetVT.SimpleTy != MVT::v4f32)
1273 return Register();
1274 if ((Subtarget->hasVSX())) {
1275 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIC, RC: &PPC::VSRCRegClass, Op0);
1276 }
1277 return Register();
1278}
1279
1280Register fastEmit_ISD_STRICT_FNEARBYINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1281 if (RetVT.SimpleTy != MVT::v2f64)
1282 return Register();
1283 if ((Subtarget->hasVSX())) {
1284 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIC, RC: &PPC::VSRCRegClass, Op0);
1285 }
1286 return Register();
1287}
1288
1289Register fastEmit_ISD_STRICT_FNEARBYINT_r(MVT VT, MVT RetVT, Register Op0) {
1290 switch (VT.SimpleTy) {
1291 case MVT::f64: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_f64_r(RetVT, Op0);
1292 case MVT::v4f32: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_v4f32_r(RetVT, Op0);
1293 case MVT::v2f64: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_v2f64_r(RetVT, Op0);
1294 default: return Register();
1295 }
1296}
1297
1298// FastEmit functions for ISD::STRICT_FP_EXTEND.
1299
1300Register fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
1301 if (RetVT.SimpleTy != MVT::f64)
1302 return Register();
1303 if ((Subtarget->hasSPE())) {
1304 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFS, RC: &PPC::SPERCRegClass, Op0);
1305 }
1306 return Register();
1307}
1308
1309Register fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(MVT RetVT, Register Op0) {
1310 if (RetVT.SimpleTy != MVT::f128)
1311 return Register();
1312 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1313 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPQP, RC: &PPC::VRRCRegClass, Op0);
1314 }
1315 return Register();
1316}
1317
1318Register fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
1319 switch (VT.SimpleTy) {
1320 case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0);
1321 case MVT::f64: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(RetVT, Op0);
1322 default: return Register();
1323 }
1324}
1325
1326// FastEmit functions for ISD::STRICT_FP_ROUND.
1327
1328Register fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
1329 if (RetVT.SimpleTy != MVT::f32)
1330 return Register();
1331 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1332 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSP, RC: &PPC::VSSRCRegClass, Op0);
1333 }
1334 if ((Subtarget->hasSPE())) {
1335 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFD, RC: &PPC::GPRCRegClass, Op0);
1336 }
1337 if ((Subtarget->hasFPU())) {
1338 return fastEmitInst_r(MachineInstOpcode: PPC::FRSP, RC: &PPC::F4RCRegClass, Op0);
1339 }
1340 return Register();
1341}
1342
1343Register fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(MVT RetVT, Register Op0) {
1344 if (RetVT.SimpleTy != MVT::f64)
1345 return Register();
1346 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1347 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPDP, RC: &PPC::VFRCRegClass, Op0);
1348 }
1349 return Register();
1350}
1351
1352Register fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
1353 switch (VT.SimpleTy) {
1354 case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0);
1355 case MVT::f128: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(RetVT, Op0);
1356 default: return Register();
1357 }
1358}
1359
1360// FastEmit functions for ISD::STRICT_FP_TO_SINT.
1361
1362Register fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(MVT RetVT, Register Op0) {
1363 if (RetVT.SimpleTy != MVT::i32)
1364 return Register();
1365 if ((Subtarget->hasSPE())) {
1366 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTSIZ, RC: &PPC::GPRCRegClass, Op0);
1367 }
1368 return Register();
1369}
1370
1371Register fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(MVT RetVT, Register Op0) {
1372 if (RetVT.SimpleTy != MVT::i32)
1373 return Register();
1374 if ((Subtarget->hasSPE())) {
1375 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTSIZ, RC: &PPC::GPRCRegClass, Op0);
1376 }
1377 return Register();
1378}
1379
1380Register fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1381 if (RetVT.SimpleTy != MVT::v4i32)
1382 return Register();
1383 if ((Subtarget->hasVSX())) {
1384 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPSXWS, RC: &PPC::VSRCRegClass, Op0);
1385 }
1386 return Register();
1387}
1388
1389Register fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1390 if (RetVT.SimpleTy != MVT::v2i64)
1391 return Register();
1392 if ((Subtarget->hasVSX())) {
1393 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPSXDS, RC: &PPC::VSRCRegClass, Op0);
1394 }
1395 return Register();
1396}
1397
1398Register fastEmit_ISD_STRICT_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
1399 switch (VT.SimpleTy) {
1400 case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
1401 case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
1402 case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
1403 case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
1404 default: return Register();
1405 }
1406}
1407
1408// FastEmit functions for ISD::STRICT_FP_TO_UINT.
1409
1410Register fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(MVT RetVT, Register Op0) {
1411 if (RetVT.SimpleTy != MVT::i32)
1412 return Register();
1413 if ((Subtarget->hasSPE())) {
1414 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTUIZ, RC: &PPC::GPRCRegClass, Op0);
1415 }
1416 return Register();
1417}
1418
1419Register fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(MVT RetVT, Register Op0) {
1420 if (RetVT.SimpleTy != MVT::i32)
1421 return Register();
1422 if ((Subtarget->hasSPE())) {
1423 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTUIZ, RC: &PPC::GPRCRegClass, Op0);
1424 }
1425 return Register();
1426}
1427
1428Register fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1429 if (RetVT.SimpleTy != MVT::v4i32)
1430 return Register();
1431 if ((Subtarget->hasVSX())) {
1432 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPUXWS, RC: &PPC::VSRCRegClass, Op0);
1433 }
1434 return Register();
1435}
1436
1437Register fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1438 if (RetVT.SimpleTy != MVT::v2i64)
1439 return Register();
1440 if ((Subtarget->hasVSX())) {
1441 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPUXDS, RC: &PPC::VSRCRegClass, Op0);
1442 }
1443 return Register();
1444}
1445
1446Register fastEmit_ISD_STRICT_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
1447 switch (VT.SimpleTy) {
1448 case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
1449 case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
1450 case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
1451 case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
1452 default: return Register();
1453 }
1454}
1455
1456// FastEmit functions for ISD::STRICT_FRINT.
1457
1458Register fastEmit_ISD_STRICT_FRINT_MVT_f64_r(MVT RetVT, Register Op0) {
1459 if (RetVT.SimpleTy != MVT::f64)
1460 return Register();
1461 if ((Subtarget->hasVSX())) {
1462 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIC, RC: &PPC::VSFRCRegClass, Op0);
1463 }
1464 return Register();
1465}
1466
1467Register fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1468 if (RetVT.SimpleTy != MVT::v4f32)
1469 return Register();
1470 if ((Subtarget->hasVSX())) {
1471 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIC, RC: &PPC::VSRCRegClass, Op0);
1472 }
1473 return Register();
1474}
1475
1476Register fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1477 if (RetVT.SimpleTy != MVT::v2f64)
1478 return Register();
1479 if ((Subtarget->hasVSX())) {
1480 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIC, RC: &PPC::VSRCRegClass, Op0);
1481 }
1482 return Register();
1483}
1484
1485Register fastEmit_ISD_STRICT_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
1486 switch (VT.SimpleTy) {
1487 case MVT::f64: return fastEmit_ISD_STRICT_FRINT_MVT_f64_r(RetVT, Op0);
1488 case MVT::v4f32: return fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(RetVT, Op0);
1489 case MVT::v2f64: return fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(RetVT, Op0);
1490 default: return Register();
1491 }
1492}
1493
1494// FastEmit functions for ISD::STRICT_FROUND.
1495
1496Register fastEmit_ISD_STRICT_FROUND_MVT_f32_r(MVT RetVT, Register Op0) {
1497 if (RetVT.SimpleTy != MVT::f32)
1498 return Register();
1499 if ((Subtarget->hasFPU())) {
1500 return fastEmitInst_r(MachineInstOpcode: PPC::FRINS, RC: &PPC::F4RCRegClass, Op0);
1501 }
1502 return Register();
1503}
1504
1505Register fastEmit_ISD_STRICT_FROUND_MVT_f64_r(MVT RetVT, Register Op0) {
1506 if (RetVT.SimpleTy != MVT::f64)
1507 return Register();
1508 if ((Subtarget->hasVSX())) {
1509 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPI, RC: &PPC::VSFRCRegClass, Op0);
1510 }
1511 if ((Subtarget->hasFPU())) {
1512 return fastEmitInst_r(MachineInstOpcode: PPC::FRIND, RC: &PPC::F8RCRegClass, Op0);
1513 }
1514 return Register();
1515}
1516
1517Register fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(MVT RetVT, Register Op0) {
1518 if (RetVT.SimpleTy != MVT::v4f32)
1519 return Register();
1520 if ((Subtarget->hasVSX())) {
1521 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPI, RC: &PPC::VSRCRegClass, Op0);
1522 }
1523 return Register();
1524}
1525
1526Register fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(MVT RetVT, Register Op0) {
1527 if (RetVT.SimpleTy != MVT::v2f64)
1528 return Register();
1529 if ((Subtarget->hasVSX())) {
1530 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPI, RC: &PPC::VSRCRegClass, Op0);
1531 }
1532 return Register();
1533}
1534
1535Register fastEmit_ISD_STRICT_FROUND_r(MVT VT, MVT RetVT, Register Op0) {
1536 switch (VT.SimpleTy) {
1537 case MVT::f32: return fastEmit_ISD_STRICT_FROUND_MVT_f32_r(RetVT, Op0);
1538 case MVT::f64: return fastEmit_ISD_STRICT_FROUND_MVT_f64_r(RetVT, Op0);
1539 case MVT::v4f32: return fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(RetVT, Op0);
1540 case MVT::v2f64: return fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(RetVT, Op0);
1541 default: return Register();
1542 }
1543}
1544
1545// FastEmit functions for ISD::STRICT_FSQRT.
1546
1547Register fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
1548 if (RetVT.SimpleTy != MVT::f32)
1549 return Register();
1550 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1551 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTSP, RC: &PPC::VSSRCRegClass, Op0);
1552 }
1553 if ((Subtarget->hasFPU())) {
1554 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRTS, RC: &PPC::F4RCRegClass, Op0);
1555 }
1556 return Register();
1557}
1558
1559Register fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
1560 if (RetVT.SimpleTy != MVT::f64)
1561 return Register();
1562 if ((Subtarget->hasVSX())) {
1563 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTDP, RC: &PPC::VSFRCRegClass, Op0);
1564 }
1565 if ((Subtarget->hasFPU())) {
1566 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRT, RC: &PPC::F8RCRegClass, Op0);
1567 }
1568 return Register();
1569}
1570
1571Register fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(MVT RetVT, Register Op0) {
1572 if (RetVT.SimpleTy != MVT::f128)
1573 return Register();
1574 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1575 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTQP, RC: &PPC::VRRCRegClass, Op0);
1576 }
1577 return Register();
1578}
1579
1580Register fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1581 if (RetVT.SimpleTy != MVT::v4f32)
1582 return Register();
1583 if ((Subtarget->hasVSX())) {
1584 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTSP, RC: &PPC::VSRCRegClass, Op0);
1585 }
1586 return Register();
1587}
1588
1589Register fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1590 if (RetVT.SimpleTy != MVT::v2f64)
1591 return Register();
1592 if ((Subtarget->hasVSX())) {
1593 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTDP, RC: &PPC::VSRCRegClass, Op0);
1594 }
1595 return Register();
1596}
1597
1598Register fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
1599 switch (VT.SimpleTy) {
1600 case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0);
1601 case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0);
1602 case MVT::f128: return fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(RetVT, Op0);
1603 case MVT::v4f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(RetVT, Op0);
1604 case MVT::v2f64: return fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(RetVT, Op0);
1605 default: return Register();
1606 }
1607}
1608
1609// FastEmit functions for ISD::STRICT_FTRUNC.
1610
1611Register fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(MVT RetVT, Register Op0) {
1612 if (RetVT.SimpleTy != MVT::f32)
1613 return Register();
1614 if ((Subtarget->hasFPU())) {
1615 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZS, RC: &PPC::F4RCRegClass, Op0);
1616 }
1617 return Register();
1618}
1619
1620Register fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(MVT RetVT, Register Op0) {
1621 if (RetVT.SimpleTy != MVT::f64)
1622 return Register();
1623 if ((Subtarget->hasVSX())) {
1624 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIZ, RC: &PPC::VSFRCRegClass, Op0);
1625 }
1626 if ((Subtarget->hasFPU())) {
1627 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZD, RC: &PPC::F8RCRegClass, Op0);
1628 }
1629 return Register();
1630}
1631
1632Register fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(MVT RetVT, Register Op0) {
1633 if (RetVT.SimpleTy != MVT::v4f32)
1634 return Register();
1635 if ((Subtarget->hasVSX())) {
1636 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIZ, RC: &PPC::VSRCRegClass, Op0);
1637 }
1638 return Register();
1639}
1640
1641Register fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(MVT RetVT, Register Op0) {
1642 if (RetVT.SimpleTy != MVT::v2f64)
1643 return Register();
1644 if ((Subtarget->hasVSX())) {
1645 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIZ, RC: &PPC::VSRCRegClass, Op0);
1646 }
1647 return Register();
1648}
1649
1650Register fastEmit_ISD_STRICT_FTRUNC_r(MVT VT, MVT RetVT, Register Op0) {
1651 switch (VT.SimpleTy) {
1652 case MVT::f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(RetVT, Op0);
1653 case MVT::f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(RetVT, Op0);
1654 case MVT::v4f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(RetVT, Op0);
1655 case MVT::v2f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(RetVT, Op0);
1656 default: return Register();
1657 }
1658}
1659
1660// FastEmit functions for ISD::STRICT_SINT_TO_FP.
1661
1662Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1663 if ((Subtarget->hasSPE())) {
1664 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFSI, RC: &PPC::GPRCRegClass, Op0);
1665 }
1666 return Register();
1667}
1668
1669Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1670 if ((Subtarget->hasSPE())) {
1671 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFSI, RC: &PPC::SPERCRegClass, Op0);
1672 }
1673 return Register();
1674}
1675
1676Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1677switch (RetVT.SimpleTy) {
1678 case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1679 case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1680 default: return Register();
1681}
1682}
1683
1684Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1685 if (RetVT.SimpleTy != MVT::v4f32)
1686 return Register();
1687 if ((Subtarget->hasVSX())) {
1688 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXWSP, RC: &PPC::VSRCRegClass, Op0);
1689 }
1690 return Register();
1691}
1692
1693Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
1694 if (RetVT.SimpleTy != MVT::v2f64)
1695 return Register();
1696 if ((Subtarget->hasVSX())) {
1697 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXDDP, RC: &PPC::VSRCRegClass, Op0);
1698 }
1699 return Register();
1700}
1701
1702Register fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1703 switch (VT.SimpleTy) {
1704 case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
1705 case MVT::v4i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1706 case MVT::v2i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1707 default: return Register();
1708 }
1709}
1710
1711// FastEmit functions for ISD::STRICT_UINT_TO_FP.
1712
1713Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1714 if ((Subtarget->hasSPE())) {
1715 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFUI, RC: &PPC::GPRCRegClass, Op0);
1716 }
1717 return Register();
1718}
1719
1720Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1721 if ((Subtarget->hasSPE())) {
1722 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFUI, RC: &PPC::SPERCRegClass, Op0);
1723 }
1724 return Register();
1725}
1726
1727Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1728switch (RetVT.SimpleTy) {
1729 case MVT::f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1730 case MVT::f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1731 default: return Register();
1732}
1733}
1734
1735Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1736 if (RetVT.SimpleTy != MVT::v4f32)
1737 return Register();
1738 if ((Subtarget->hasVSX())) {
1739 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXWSP, RC: &PPC::VSRCRegClass, Op0);
1740 }
1741 return Register();
1742}
1743
1744Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
1745 if (RetVT.SimpleTy != MVT::v2f64)
1746 return Register();
1747 if ((Subtarget->hasVSX())) {
1748 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXDDP, RC: &PPC::VSRCRegClass, Op0);
1749 }
1750 return Register();
1751}
1752
1753Register fastEmit_ISD_STRICT_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1754 switch (VT.SimpleTy) {
1755 case MVT::i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1756 case MVT::v4i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1757 case MVT::v2i64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1758 default: return Register();
1759 }
1760}
1761
1762// FastEmit functions for ISD::TRUNCATE.
1763
1764Register fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, Register Op0) {
1765 if (RetVT.SimpleTy != MVT::i1)
1766 return Register();
1767 return fastEmitInst_r(MachineInstOpcode: PPC::ANDI_rec_1_GT_BIT, RC: &PPC::CRBITRCRegClass, Op0);
1768}
1769
1770Register fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, Register Op0) {
1771 if (RetVT.SimpleTy != MVT::i1)
1772 return Register();
1773 return fastEmitInst_r(MachineInstOpcode: PPC::ANDI_rec_1_GT_BIT8, RC: &PPC::CRBITRCRegClass, Op0);
1774}
1775
1776Register fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, Register Op0) {
1777 switch (VT.SimpleTy) {
1778 case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0);
1779 case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0);
1780 default: return Register();
1781 }
1782}
1783
1784// FastEmit functions for ISD::UINT_TO_FP.
1785
1786Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1787 if ((Subtarget->hasSPE())) {
1788 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFUI, RC: &PPC::GPRCRegClass, Op0);
1789 }
1790 return Register();
1791}
1792
1793Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1794 if ((Subtarget->hasSPE())) {
1795 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFUI, RC: &PPC::SPERCRegClass, Op0);
1796 }
1797 return Register();
1798}
1799
1800Register fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1801switch (RetVT.SimpleTy) {
1802 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1803 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1804 default: return Register();
1805}
1806}
1807
1808Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1809 if (RetVT.SimpleTy != MVT::v4f32)
1810 return Register();
1811 if ((Subtarget->hasVSX())) {
1812 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXWSP, RC: &PPC::VSRCRegClass, Op0);
1813 }
1814 if ((Subtarget->hasAltivec())) {
1815 return fastEmitInst_r(MachineInstOpcode: PPC::VCFUX_0, RC: &PPC::VRRCRegClass, Op0);
1816 }
1817 return Register();
1818}
1819
1820Register fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
1821 if (RetVT.SimpleTy != MVT::v2f64)
1822 return Register();
1823 if ((Subtarget->hasVSX())) {
1824 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXDDP, RC: &PPC::VSRCRegClass, Op0);
1825 }
1826 return Register();
1827}
1828
1829Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1830 switch (VT.SimpleTy) {
1831 case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1832 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1833 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1834 default: return Register();
1835 }
1836}
1837
1838// FastEmit functions for ISD::ZERO_EXTEND.
1839
1840Register fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(Register Op0) {
1841 if ((Subtarget->isISA3_1())) {
1842 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC, RC: &PPC::GPRCRegClass, Op0);
1843 }
1844 return Register();
1845}
1846
1847Register fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(Register Op0) {
1848 if ((Subtarget->isISA3_1())) {
1849 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC8, RC: &PPC::G8RCRegClass, Op0);
1850 }
1851 return Register();
1852}
1853
1854Register fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(MVT RetVT, Register Op0) {
1855switch (RetVT.SimpleTy) {
1856 case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(Op0);
1857 case MVT::i64: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(Op0);
1858 default: return Register();
1859}
1860}
1861
1862Register fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
1863 switch (VT.SimpleTy) {
1864 case MVT::i1: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(RetVT, Op0);
1865 default: return Register();
1866 }
1867}
1868
1869// FastEmit functions for PPCISD::FCFID.
1870
1871Register fastEmit_PPCISD_FCFID_MVT_f64_r(MVT RetVT, Register Op0) {
1872 if (RetVT.SimpleTy != MVT::f64)
1873 return Register();
1874 if ((Subtarget->hasVSX())) {
1875 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDDP, RC: &PPC::VSFRCRegClass, Op0);
1876 }
1877 return fastEmitInst_r(MachineInstOpcode: PPC::FCFID, RC: &PPC::F8RCRegClass, Op0);
1878}
1879
1880Register fastEmit_PPCISD_FCFID_r(MVT VT, MVT RetVT, Register Op0) {
1881 switch (VT.SimpleTy) {
1882 case MVT::f64: return fastEmit_PPCISD_FCFID_MVT_f64_r(RetVT, Op0);
1883 default: return Register();
1884 }
1885}
1886
1887// FastEmit functions for PPCISD::FCFIDS.
1888
1889Register fastEmit_PPCISD_FCFIDS_MVT_f64_r(MVT RetVT, Register Op0) {
1890 if (RetVT.SimpleTy != MVT::f32)
1891 return Register();
1892 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1893 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDSP, RC: &PPC::VSSRCRegClass, Op0);
1894 }
1895 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDS, RC: &PPC::F4RCRegClass, Op0);
1896}
1897
1898Register fastEmit_PPCISD_FCFIDS_r(MVT VT, MVT RetVT, Register Op0) {
1899 switch (VT.SimpleTy) {
1900 case MVT::f64: return fastEmit_PPCISD_FCFIDS_MVT_f64_r(RetVT, Op0);
1901 default: return Register();
1902 }
1903}
1904
1905// FastEmit functions for PPCISD::FCFIDU.
1906
1907Register fastEmit_PPCISD_FCFIDU_MVT_f64_r(MVT RetVT, Register Op0) {
1908 if (RetVT.SimpleTy != MVT::f64)
1909 return Register();
1910 if ((Subtarget->hasVSX())) {
1911 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDDP, RC: &PPC::VSFRCRegClass, Op0);
1912 }
1913 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDU, RC: &PPC::F8RCRegClass, Op0);
1914}
1915
1916Register fastEmit_PPCISD_FCFIDU_r(MVT VT, MVT RetVT, Register Op0) {
1917 switch (VT.SimpleTy) {
1918 case MVT::f64: return fastEmit_PPCISD_FCFIDU_MVT_f64_r(RetVT, Op0);
1919 default: return Register();
1920 }
1921}
1922
1923// FastEmit functions for PPCISD::FCFIDUS.
1924
1925Register fastEmit_PPCISD_FCFIDUS_MVT_f64_r(MVT RetVT, Register Op0) {
1926 if (RetVT.SimpleTy != MVT::f32)
1927 return Register();
1928 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1929 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDSP, RC: &PPC::VSSRCRegClass, Op0);
1930 }
1931 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDUS, RC: &PPC::F4RCRegClass, Op0);
1932}
1933
1934Register fastEmit_PPCISD_FCFIDUS_r(MVT VT, MVT RetVT, Register Op0) {
1935 switch (VT.SimpleTy) {
1936 case MVT::f64: return fastEmit_PPCISD_FCFIDUS_MVT_f64_r(RetVT, Op0);
1937 default: return Register();
1938 }
1939}
1940
1941// FastEmit functions for PPCISD::FCTIDUZ.
1942
1943Register fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(MVT RetVT, Register Op0) {
1944 if (RetVT.SimpleTy != MVT::f32)
1945 return Register();
1946 if ((Subtarget->hasVSX())) {
1947 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDSs, RC: &PPC::VSSRCRegClass, Op0);
1948 }
1949 return Register();
1950}
1951
1952Register fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(MVT RetVT, Register Op0) {
1953 if (RetVT.SimpleTy != MVT::f64)
1954 return Register();
1955 if ((Subtarget->hasVSX())) {
1956 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDS, RC: &PPC::VSFRCRegClass, Op0);
1957 }
1958 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDUZ, RC: &PPC::F8RCRegClass, Op0);
1959}
1960
1961Register fastEmit_PPCISD_FCTIDUZ_MVT_f128_r(MVT RetVT, Register Op0) {
1962 if (RetVT.SimpleTy != MVT::f128)
1963 return Register();
1964 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1965 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUDZ, RC: &PPC::VRRCRegClass, Op0);
1966 }
1967 return Register();
1968}
1969
1970Register fastEmit_PPCISD_FCTIDUZ_r(MVT VT, MVT RetVT, Register Op0) {
1971 switch (VT.SimpleTy) {
1972 case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0);
1973 case MVT::f64: return fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(RetVT, Op0);
1974 case MVT::f128: return fastEmit_PPCISD_FCTIDUZ_MVT_f128_r(RetVT, Op0);
1975 default: return Register();
1976 }
1977}
1978
1979// FastEmit functions for PPCISD::FCTIDZ.
1980
1981Register fastEmit_PPCISD_FCTIDZ_MVT_f32_r(MVT RetVT, Register Op0) {
1982 if (RetVT.SimpleTy != MVT::f32)
1983 return Register();
1984 if ((Subtarget->hasVSX())) {
1985 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDSs, RC: &PPC::VSSRCRegClass, Op0);
1986 }
1987 return Register();
1988}
1989
1990Register fastEmit_PPCISD_FCTIDZ_MVT_f64_r(MVT RetVT, Register Op0) {
1991 if (RetVT.SimpleTy != MVT::f64)
1992 return Register();
1993 if ((Subtarget->hasVSX())) {
1994 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDS, RC: &PPC::VSFRCRegClass, Op0);
1995 }
1996 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDZ, RC: &PPC::F8RCRegClass, Op0);
1997}
1998
1999Register fastEmit_PPCISD_FCTIDZ_MVT_f128_r(MVT RetVT, Register Op0) {
2000 if (RetVT.SimpleTy != MVT::f128)
2001 return Register();
2002 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2003 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSDZ, RC: &PPC::VRRCRegClass, Op0);
2004 }
2005 return Register();
2006}
2007
2008Register fastEmit_PPCISD_FCTIDZ_r(MVT VT, MVT RetVT, Register Op0) {
2009 switch (VT.SimpleTy) {
2010 case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0);
2011 case MVT::f64: return fastEmit_PPCISD_FCTIDZ_MVT_f64_r(RetVT, Op0);
2012 case MVT::f128: return fastEmit_PPCISD_FCTIDZ_MVT_f128_r(RetVT, Op0);
2013 default: return Register();
2014 }
2015}
2016
2017// FastEmit functions for PPCISD::FCTIWUZ.
2018
2019Register fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(MVT RetVT, Register Op0) {
2020 if (RetVT.SimpleTy != MVT::f32)
2021 return Register();
2022 if ((Subtarget->hasVSX())) {
2023 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWSs, RC: &PPC::VSSRCRegClass, Op0);
2024 }
2025 return Register();
2026}
2027
2028Register fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(MVT RetVT, Register Op0) {
2029 if (RetVT.SimpleTy != MVT::f64)
2030 return Register();
2031 if ((Subtarget->hasVSX())) {
2032 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWS, RC: &PPC::VSFRCRegClass, Op0);
2033 }
2034 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWUZ, RC: &PPC::F8RCRegClass, Op0);
2035}
2036
2037Register fastEmit_PPCISD_FCTIWUZ_MVT_f128_r(MVT RetVT, Register Op0) {
2038 if (RetVT.SimpleTy != MVT::f128)
2039 return Register();
2040 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2041 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUWZ, RC: &PPC::VRRCRegClass, Op0);
2042 }
2043 return Register();
2044}
2045
2046Register fastEmit_PPCISD_FCTIWUZ_r(MVT VT, MVT RetVT, Register Op0) {
2047 switch (VT.SimpleTy) {
2048 case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0);
2049 case MVT::f64: return fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(RetVT, Op0);
2050 case MVT::f128: return fastEmit_PPCISD_FCTIWUZ_MVT_f128_r(RetVT, Op0);
2051 default: return Register();
2052 }
2053}
2054
2055// FastEmit functions for PPCISD::FCTIWZ.
2056
2057Register fastEmit_PPCISD_FCTIWZ_MVT_f32_r(MVT RetVT, Register Op0) {
2058 if (RetVT.SimpleTy != MVT::f32)
2059 return Register();
2060 if ((Subtarget->hasVSX())) {
2061 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWSs, RC: &PPC::VSSRCRegClass, Op0);
2062 }
2063 return Register();
2064}
2065
2066Register fastEmit_PPCISD_FCTIWZ_MVT_f64_r(MVT RetVT, Register Op0) {
2067 if (RetVT.SimpleTy != MVT::f64)
2068 return Register();
2069 if ((Subtarget->hasVSX())) {
2070 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWS, RC: &PPC::VSFRCRegClass, Op0);
2071 }
2072 if ((Subtarget->hasFPU())) {
2073 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWZ, RC: &PPC::F8RCRegClass, Op0);
2074 }
2075 return Register();
2076}
2077
2078Register fastEmit_PPCISD_FCTIWZ_MVT_f128_r(MVT RetVT, Register Op0) {
2079 if (RetVT.SimpleTy != MVT::f128)
2080 return Register();
2081 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2082 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSWZ, RC: &PPC::VRRCRegClass, Op0);
2083 }
2084 return Register();
2085}
2086
2087Register fastEmit_PPCISD_FCTIWZ_r(MVT VT, MVT RetVT, Register Op0) {
2088 switch (VT.SimpleTy) {
2089 case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0);
2090 case MVT::f64: return fastEmit_PPCISD_FCTIWZ_MVT_f64_r(RetVT, Op0);
2091 case MVT::f128: return fastEmit_PPCISD_FCTIWZ_MVT_f128_r(RetVT, Op0);
2092 default: return Register();
2093 }
2094}
2095
2096// FastEmit functions for PPCISD::FRE.
2097
2098Register fastEmit_PPCISD_FRE_MVT_f32_r(MVT RetVT, Register Op0) {
2099 if (RetVT.SimpleTy != MVT::f32)
2100 return Register();
2101 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2102 return fastEmitInst_r(MachineInstOpcode: PPC::XSRESP, RC: &PPC::VSSRCRegClass, Op0);
2103 }
2104 if ((Subtarget->hasFPU())) {
2105 return fastEmitInst_r(MachineInstOpcode: PPC::FRES, RC: &PPC::F4RCRegClass, Op0);
2106 }
2107 return Register();
2108}
2109
2110Register fastEmit_PPCISD_FRE_MVT_f64_r(MVT RetVT, Register Op0) {
2111 if (RetVT.SimpleTy != MVT::f64)
2112 return Register();
2113 if ((Subtarget->hasVSX())) {
2114 return fastEmitInst_r(MachineInstOpcode: PPC::XSREDP, RC: &PPC::VSFRCRegClass, Op0);
2115 }
2116 if ((Subtarget->hasFPU())) {
2117 return fastEmitInst_r(MachineInstOpcode: PPC::FRE, RC: &PPC::F8RCRegClass, Op0);
2118 }
2119 return Register();
2120}
2121
2122Register fastEmit_PPCISD_FRE_MVT_v4f32_r(MVT RetVT, Register Op0) {
2123 if (RetVT.SimpleTy != MVT::v4f32)
2124 return Register();
2125 if ((Subtarget->hasVSX())) {
2126 return fastEmitInst_r(MachineInstOpcode: PPC::XVRESP, RC: &PPC::VSRCRegClass, Op0);
2127 }
2128 if ((Subtarget->hasAltivec())) {
2129 return fastEmitInst_r(MachineInstOpcode: PPC::VREFP, RC: &PPC::VRRCRegClass, Op0);
2130 }
2131 return Register();
2132}
2133
2134Register fastEmit_PPCISD_FRE_MVT_v2f64_r(MVT RetVT, Register Op0) {
2135 if (RetVT.SimpleTy != MVT::v2f64)
2136 return Register();
2137 if ((Subtarget->hasVSX())) {
2138 return fastEmitInst_r(MachineInstOpcode: PPC::XVREDP, RC: &PPC::VSRCRegClass, Op0);
2139 }
2140 return Register();
2141}
2142
2143Register fastEmit_PPCISD_FRE_r(MVT VT, MVT RetVT, Register Op0) {
2144 switch (VT.SimpleTy) {
2145 case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0);
2146 case MVT::f64: return fastEmit_PPCISD_FRE_MVT_f64_r(RetVT, Op0);
2147 case MVT::v4f32: return fastEmit_PPCISD_FRE_MVT_v4f32_r(RetVT, Op0);
2148 case MVT::v2f64: return fastEmit_PPCISD_FRE_MVT_v2f64_r(RetVT, Op0);
2149 default: return Register();
2150 }
2151}
2152
2153// FastEmit functions for PPCISD::FRSQRTE.
2154
2155Register fastEmit_PPCISD_FRSQRTE_MVT_f32_r(MVT RetVT, Register Op0) {
2156 if (RetVT.SimpleTy != MVT::f32)
2157 return Register();
2158 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2159 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSQRTESP, RC: &PPC::VSSRCRegClass, Op0);
2160 }
2161 if ((Subtarget->hasFPU())) {
2162 return fastEmitInst_r(MachineInstOpcode: PPC::FRSQRTES, RC: &PPC::F4RCRegClass, Op0);
2163 }
2164 return Register();
2165}
2166
2167Register fastEmit_PPCISD_FRSQRTE_MVT_f64_r(MVT RetVT, Register Op0) {
2168 if (RetVT.SimpleTy != MVT::f64)
2169 return Register();
2170 if ((Subtarget->hasVSX())) {
2171 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSQRTEDP, RC: &PPC::VSFRCRegClass, Op0);
2172 }
2173 if ((Subtarget->hasFPU())) {
2174 return fastEmitInst_r(MachineInstOpcode: PPC::FRSQRTE, RC: &PPC::F8RCRegClass, Op0);
2175 }
2176 return Register();
2177}
2178
2179Register fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, Register Op0) {
2180 if (RetVT.SimpleTy != MVT::v4f32)
2181 return Register();
2182 if ((Subtarget->hasVSX())) {
2183 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSQRTESP, RC: &PPC::VSRCRegClass, Op0);
2184 }
2185 if ((Subtarget->hasAltivec())) {
2186 return fastEmitInst_r(MachineInstOpcode: PPC::VRSQRTEFP, RC: &PPC::VRRCRegClass, Op0);
2187 }
2188 return Register();
2189}
2190
2191Register fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, Register Op0) {
2192 if (RetVT.SimpleTy != MVT::v2f64)
2193 return Register();
2194 if ((Subtarget->hasVSX())) {
2195 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSQRTEDP, RC: &PPC::VSRCRegClass, Op0);
2196 }
2197 return Register();
2198}
2199
2200Register fastEmit_PPCISD_FRSQRTE_r(MVT VT, MVT RetVT, Register Op0) {
2201 switch (VT.SimpleTy) {
2202 case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0);
2203 case MVT::f64: return fastEmit_PPCISD_FRSQRTE_MVT_f64_r(RetVT, Op0);
2204 case MVT::v4f32: return fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0);
2205 case MVT::v2f64: return fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0);
2206 default: return Register();
2207 }
2208}
2209
2210// FastEmit functions for PPCISD::FSQRT.
2211
2212Register fastEmit_PPCISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
2213 if (RetVT.SimpleTy != MVT::f64)
2214 return Register();
2215 if ((Subtarget->hasVSX())) {
2216 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTDP, RC: &PPC::VSFRCRegClass, Op0);
2217 }
2218 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRT, RC: &PPC::F8RCRegClass, Op0);
2219}
2220
2221Register fastEmit_PPCISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
2222 if (RetVT.SimpleTy != MVT::v4f32)
2223 return Register();
2224 if ((Subtarget->hasVSX())) {
2225 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTSP, RC: &PPC::VSRCRegClass, Op0);
2226 }
2227 return Register();
2228}
2229
2230Register fastEmit_PPCISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
2231 if (RetVT.SimpleTy != MVT::v2f64)
2232 return Register();
2233 if ((Subtarget->hasVSX())) {
2234 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTDP, RC: &PPC::VSRCRegClass, Op0);
2235 }
2236 return Register();
2237}
2238
2239Register fastEmit_PPCISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
2240 switch (VT.SimpleTy) {
2241 case MVT::f64: return fastEmit_PPCISD_FSQRT_MVT_f64_r(RetVT, Op0);
2242 case MVT::v4f32: return fastEmit_PPCISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
2243 case MVT::v2f64: return fastEmit_PPCISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
2244 default: return Register();
2245 }
2246}
2247
2248// FastEmit functions for PPCISD::FTSQRT.
2249
2250Register fastEmit_PPCISD_FTSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
2251 if (RetVT.SimpleTy != MVT::i32)
2252 return Register();
2253 if ((Subtarget->hasVSX())) {
2254 return fastEmitInst_r(MachineInstOpcode: PPC::XSTSQRTDP, RC: &PPC::CRRCRegClass, Op0);
2255 }
2256 if ((Subtarget->hasFPU())) {
2257 return fastEmitInst_r(MachineInstOpcode: PPC::FTSQRT, RC: &PPC::CRRCRegClass, Op0);
2258 }
2259 return Register();
2260}
2261
2262Register fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
2263 if (RetVT.SimpleTy != MVT::i32)
2264 return Register();
2265 if ((Subtarget->hasVSX())) {
2266 return fastEmitInst_r(MachineInstOpcode: PPC::XVTSQRTSP, RC: &PPC::CRRCRegClass, Op0);
2267 }
2268 return Register();
2269}
2270
2271Register fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
2272 if (RetVT.SimpleTy != MVT::i32)
2273 return Register();
2274 if ((Subtarget->hasVSX())) {
2275 return fastEmitInst_r(MachineInstOpcode: PPC::XVTSQRTDP, RC: &PPC::CRRCRegClass, Op0);
2276 }
2277 return Register();
2278}
2279
2280Register fastEmit_PPCISD_FTSQRT_r(MVT VT, MVT RetVT, Register Op0) {
2281 switch (VT.SimpleTy) {
2282 case MVT::f64: return fastEmit_PPCISD_FTSQRT_MVT_f64_r(RetVT, Op0);
2283 case MVT::v4f32: return fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(RetVT, Op0);
2284 case MVT::v2f64: return fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(RetVT, Op0);
2285 default: return Register();
2286 }
2287}
2288
2289// FastEmit functions for PPCISD::GET_TLS_MOD_AIX.
2290
2291Register fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i32_r(MVT RetVT, Register Op0) {
2292 if (RetVT.SimpleTy != MVT::i32)
2293 return Register();
2294 return fastEmitInst_r(MachineInstOpcode: PPC::GETtlsMOD32AIX, RC: &PPC::GPRCRegClass, Op0);
2295}
2296
2297Register fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i64_r(MVT RetVT, Register Op0) {
2298 if (RetVT.SimpleTy != MVT::i64)
2299 return Register();
2300 return fastEmitInst_r(MachineInstOpcode: PPC::GETtlsMOD64AIX, RC: &PPC::G8RCRegClass, Op0);
2301}
2302
2303Register fastEmit_PPCISD_GET_TLS_MOD_AIX_r(MVT VT, MVT RetVT, Register Op0) {
2304 switch (VT.SimpleTy) {
2305 case MVT::i32: return fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i32_r(RetVT, Op0);
2306 case MVT::i64: return fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i64_r(RetVT, Op0);
2307 default: return Register();
2308 }
2309}
2310
2311// FastEmit functions for PPCISD::MFVSR.
2312
2313Register fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Register Op0) {
2314 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2315 return fastEmitInst_r(MachineInstOpcode: PPC::MFVSRWZ, RC: &PPC::GPRCRegClass, Op0);
2316 }
2317 return Register();
2318}
2319
2320Register fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Register Op0) {
2321 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2322 return fastEmitInst_r(MachineInstOpcode: PPC::MFVSRD, RC: &PPC::G8RCRegClass, Op0);
2323 }
2324 return Register();
2325}
2326
2327Register fastEmit_PPCISD_MFVSR_MVT_f64_r(MVT RetVT, Register Op0) {
2328switch (RetVT.SimpleTy) {
2329 case MVT::i32: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Op0);
2330 case MVT::i64: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Op0);
2331 default: return Register();
2332}
2333}
2334
2335Register fastEmit_PPCISD_MFVSR_r(MVT VT, MVT RetVT, Register Op0) {
2336 switch (VT.SimpleTy) {
2337 case MVT::f64: return fastEmit_PPCISD_MFVSR_MVT_f64_r(RetVT, Op0);
2338 default: return Register();
2339 }
2340}
2341
2342// FastEmit functions for PPCISD::MTVSRA.
2343
2344Register fastEmit_PPCISD_MTVSRA_MVT_i32_r(MVT RetVT, Register Op0) {
2345 if (RetVT.SimpleTy != MVT::f64)
2346 return Register();
2347 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2348 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRWA, RC: &PPC::VSFRCRegClass, Op0);
2349 }
2350 return Register();
2351}
2352
2353Register fastEmit_PPCISD_MTVSRA_MVT_i64_r(MVT RetVT, Register Op0) {
2354 if (RetVT.SimpleTy != MVT::f64)
2355 return Register();
2356 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2357 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRD, RC: &PPC::VSFRCRegClass, Op0);
2358 }
2359 return Register();
2360}
2361
2362Register fastEmit_PPCISD_MTVSRA_r(MVT VT, MVT RetVT, Register Op0) {
2363 switch (VT.SimpleTy) {
2364 case MVT::i32: return fastEmit_PPCISD_MTVSRA_MVT_i32_r(RetVT, Op0);
2365 case MVT::i64: return fastEmit_PPCISD_MTVSRA_MVT_i64_r(RetVT, Op0);
2366 default: return Register();
2367 }
2368}
2369
2370// FastEmit functions for PPCISD::MTVSRZ.
2371
2372Register fastEmit_PPCISD_MTVSRZ_MVT_i32_r(MVT RetVT, Register Op0) {
2373 if (RetVT.SimpleTy != MVT::f64)
2374 return Register();
2375 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2376 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRWZ, RC: &PPC::VSFRCRegClass, Op0);
2377 }
2378 return Register();
2379}
2380
2381Register fastEmit_PPCISD_MTVSRZ_r(MVT VT, MVT RetVT, Register Op0) {
2382 switch (VT.SimpleTy) {
2383 case MVT::i32: return fastEmit_PPCISD_MTVSRZ_MVT_i32_r(RetVT, Op0);
2384 default: return Register();
2385 }
2386}
2387
2388// FastEmit functions for PPCISD::SCALAR_TO_VECTOR_PERMUTED.
2389
2390Register fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(MVT RetVT, Register Op0) {
2391 if (RetVT.SimpleTy != MVT::v4f32)
2392 return Register();
2393 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (Subtarget->isLittleEndian())) {
2394 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSPN, RC: &PPC::VSRCRegClass, Op0);
2395 }
2396 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) {
2397 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSPN, RC: &PPC::VSRCRegClass, Op0);
2398 }
2399 return Register();
2400}
2401
2402Register fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_r(MVT VT, MVT RetVT, Register Op0) {
2403 switch (VT.SimpleTy) {
2404 case MVT::f32: return fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(RetVT, Op0);
2405 default: return Register();
2406 }
2407}
2408
2409// FastEmit functions for PPCISD::SETBC.
2410
2411Register fastEmit_PPCISD_SETBC_MVT_i1_r(MVT RetVT, Register Op0) {
2412 if (RetVT.SimpleTy != MVT::i32)
2413 return Register();
2414 if ((Subtarget->isISA3_1())) {
2415 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC, RC: &PPC::GPRCRegClass, Op0);
2416 }
2417 return Register();
2418}
2419
2420Register fastEmit_PPCISD_SETBC_r(MVT VT, MVT RetVT, Register Op0) {
2421 switch (VT.SimpleTy) {
2422 case MVT::i1: return fastEmit_PPCISD_SETBC_MVT_i1_r(RetVT, Op0);
2423 default: return Register();
2424 }
2425}
2426
2427// FastEmit functions for PPCISD::SETBCR.
2428
2429Register fastEmit_PPCISD_SETBCR_MVT_i1_r(MVT RetVT, Register Op0) {
2430 if (RetVT.SimpleTy != MVT::i32)
2431 return Register();
2432 if ((Subtarget->isISA3_1())) {
2433 return fastEmitInst_r(MachineInstOpcode: PPC::SETBCR, RC: &PPC::GPRCRegClass, Op0);
2434 }
2435 return Register();
2436}
2437
2438Register fastEmit_PPCISD_SETBCR_r(MVT VT, MVT RetVT, Register Op0) {
2439 switch (VT.SimpleTy) {
2440 case MVT::i1: return fastEmit_PPCISD_SETBCR_MVT_i1_r(RetVT, Op0);
2441 default: return Register();
2442 }
2443}
2444
2445// FastEmit functions for PPCISD::STRICT_FCFID.
2446
2447Register fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(MVT RetVT, Register Op0) {
2448 if (RetVT.SimpleTy != MVT::f64)
2449 return Register();
2450 if ((Subtarget->hasVSX())) {
2451 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDDP, RC: &PPC::VSFRCRegClass, Op0);
2452 }
2453 return fastEmitInst_r(MachineInstOpcode: PPC::FCFID, RC: &PPC::F8RCRegClass, Op0);
2454}
2455
2456Register fastEmit_PPCISD_STRICT_FCFID_r(MVT VT, MVT RetVT, Register Op0) {
2457 switch (VT.SimpleTy) {
2458 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(RetVT, Op0);
2459 default: return Register();
2460 }
2461}
2462
2463// FastEmit functions for PPCISD::STRICT_FCFIDS.
2464
2465Register fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(MVT RetVT, Register Op0) {
2466 if (RetVT.SimpleTy != MVT::f32)
2467 return Register();
2468 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2469 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDSP, RC: &PPC::VSSRCRegClass, Op0);
2470 }
2471 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDS, RC: &PPC::F4RCRegClass, Op0);
2472}
2473
2474Register fastEmit_PPCISD_STRICT_FCFIDS_r(MVT VT, MVT RetVT, Register Op0) {
2475 switch (VT.SimpleTy) {
2476 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(RetVT, Op0);
2477 default: return Register();
2478 }
2479}
2480
2481// FastEmit functions for PPCISD::STRICT_FCFIDU.
2482
2483Register fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(MVT RetVT, Register Op0) {
2484 if (RetVT.SimpleTy != MVT::f64)
2485 return Register();
2486 if ((Subtarget->hasVSX())) {
2487 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDDP, RC: &PPC::VSFRCRegClass, Op0);
2488 }
2489 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDU, RC: &PPC::F8RCRegClass, Op0);
2490}
2491
2492Register fastEmit_PPCISD_STRICT_FCFIDU_r(MVT VT, MVT RetVT, Register Op0) {
2493 switch (VT.SimpleTy) {
2494 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(RetVT, Op0);
2495 default: return Register();
2496 }
2497}
2498
2499// FastEmit functions for PPCISD::STRICT_FCFIDUS.
2500
2501Register fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(MVT RetVT, Register Op0) {
2502 if (RetVT.SimpleTy != MVT::f32)
2503 return Register();
2504 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2505 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDSP, RC: &PPC::VSSRCRegClass, Op0);
2506 }
2507 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDUS, RC: &PPC::F4RCRegClass, Op0);
2508}
2509
2510Register fastEmit_PPCISD_STRICT_FCFIDUS_r(MVT VT, MVT RetVT, Register Op0) {
2511 switch (VT.SimpleTy) {
2512 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(RetVT, Op0);
2513 default: return Register();
2514 }
2515}
2516
2517// FastEmit functions for PPCISD::STRICT_FCTIDUZ.
2518
2519Register fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(MVT RetVT, Register Op0) {
2520 if (RetVT.SimpleTy != MVT::f32)
2521 return Register();
2522 if ((Subtarget->hasVSX())) {
2523 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDSs, RC: &PPC::VSSRCRegClass, Op0);
2524 }
2525 return Register();
2526}
2527
2528Register fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(MVT RetVT, Register Op0) {
2529 if (RetVT.SimpleTy != MVT::f64)
2530 return Register();
2531 if ((Subtarget->hasVSX())) {
2532 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDS, RC: &PPC::VSFRCRegClass, Op0);
2533 }
2534 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDUZ, RC: &PPC::F8RCRegClass, Op0);
2535}
2536
2537Register fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f128_r(MVT RetVT, Register Op0) {
2538 if (RetVT.SimpleTy != MVT::f128)
2539 return Register();
2540 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2541 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUDZ, RC: &PPC::VRRCRegClass, Op0);
2542 }
2543 return Register();
2544}
2545
2546Register fastEmit_PPCISD_STRICT_FCTIDUZ_r(MVT VT, MVT RetVT, Register Op0) {
2547 switch (VT.SimpleTy) {
2548 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(RetVT, Op0);
2549 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(RetVT, Op0);
2550 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f128_r(RetVT, Op0);
2551 default: return Register();
2552 }
2553}
2554
2555// FastEmit functions for PPCISD::STRICT_FCTIDZ.
2556
2557Register fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(MVT RetVT, Register Op0) {
2558 if (RetVT.SimpleTy != MVT::f32)
2559 return Register();
2560 if ((Subtarget->hasVSX())) {
2561 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDSs, RC: &PPC::VSSRCRegClass, Op0);
2562 }
2563 return Register();
2564}
2565
2566Register fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(MVT RetVT, Register Op0) {
2567 if (RetVT.SimpleTy != MVT::f64)
2568 return Register();
2569 if ((Subtarget->hasVSX())) {
2570 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDS, RC: &PPC::VSFRCRegClass, Op0);
2571 }
2572 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDZ, RC: &PPC::F8RCRegClass, Op0);
2573}
2574
2575Register fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f128_r(MVT RetVT, Register Op0) {
2576 if (RetVT.SimpleTy != MVT::f128)
2577 return Register();
2578 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2579 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSDZ, RC: &PPC::VRRCRegClass, Op0);
2580 }
2581 return Register();
2582}
2583
2584Register fastEmit_PPCISD_STRICT_FCTIDZ_r(MVT VT, MVT RetVT, Register Op0) {
2585 switch (VT.SimpleTy) {
2586 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(RetVT, Op0);
2587 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(RetVT, Op0);
2588 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f128_r(RetVT, Op0);
2589 default: return Register();
2590 }
2591}
2592
2593// FastEmit functions for PPCISD::STRICT_FCTIWUZ.
2594
2595Register fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(MVT RetVT, Register Op0) {
2596 if (RetVT.SimpleTy != MVT::f32)
2597 return Register();
2598 if ((Subtarget->hasVSX())) {
2599 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWSs, RC: &PPC::VSSRCRegClass, Op0);
2600 }
2601 return Register();
2602}
2603
2604Register fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(MVT RetVT, Register Op0) {
2605 if (RetVT.SimpleTy != MVT::f64)
2606 return Register();
2607 if ((Subtarget->hasVSX())) {
2608 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWS, RC: &PPC::VSFRCRegClass, Op0);
2609 }
2610 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWUZ, RC: &PPC::F8RCRegClass, Op0);
2611}
2612
2613Register fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f128_r(MVT RetVT, Register Op0) {
2614 if (RetVT.SimpleTy != MVT::f128)
2615 return Register();
2616 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2617 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUWZ, RC: &PPC::VRRCRegClass, Op0);
2618 }
2619 return Register();
2620}
2621
2622Register fastEmit_PPCISD_STRICT_FCTIWUZ_r(MVT VT, MVT RetVT, Register Op0) {
2623 switch (VT.SimpleTy) {
2624 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(RetVT, Op0);
2625 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(RetVT, Op0);
2626 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f128_r(RetVT, Op0);
2627 default: return Register();
2628 }
2629}
2630
2631// FastEmit functions for PPCISD::STRICT_FCTIWZ.
2632
2633Register fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(MVT RetVT, Register Op0) {
2634 if (RetVT.SimpleTy != MVT::f32)
2635 return Register();
2636 if ((Subtarget->hasVSX())) {
2637 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWSs, RC: &PPC::VSSRCRegClass, Op0);
2638 }
2639 return Register();
2640}
2641
2642Register fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(MVT RetVT, Register Op0) {
2643 if (RetVT.SimpleTy != MVT::f64)
2644 return Register();
2645 if ((Subtarget->hasVSX())) {
2646 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWS, RC: &PPC::VSFRCRegClass, Op0);
2647 }
2648 if ((Subtarget->hasFPU())) {
2649 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWZ, RC: &PPC::F8RCRegClass, Op0);
2650 }
2651 return Register();
2652}
2653
2654Register fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f128_r(MVT RetVT, Register Op0) {
2655 if (RetVT.SimpleTy != MVT::f128)
2656 return Register();
2657 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2658 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSWZ, RC: &PPC::VRRCRegClass, Op0);
2659 }
2660 return Register();
2661}
2662
2663Register fastEmit_PPCISD_STRICT_FCTIWZ_r(MVT VT, MVT RetVT, Register Op0) {
2664 switch (VT.SimpleTy) {
2665 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(RetVT, Op0);
2666 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(RetVT, Op0);
2667 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f128_r(RetVT, Op0);
2668 default: return Register();
2669 }
2670}
2671
2672// FastEmit functions for PPCISD::TLSLD_AIX.
2673
2674Register fastEmit_PPCISD_TLSLD_AIX_MVT_i32_r(MVT RetVT, Register Op0) {
2675 if (RetVT.SimpleTy != MVT::i32)
2676 return Register();
2677 return fastEmitInst_r(MachineInstOpcode: PPC::TLSLDAIX, RC: &PPC::GPRCRegClass, Op0);
2678}
2679
2680Register fastEmit_PPCISD_TLSLD_AIX_MVT_i64_r(MVT RetVT, Register Op0) {
2681 if (RetVT.SimpleTy != MVT::i64)
2682 return Register();
2683 return fastEmitInst_r(MachineInstOpcode: PPC::TLSLDAIX8, RC: &PPC::G8RCRegClass, Op0);
2684}
2685
2686Register fastEmit_PPCISD_TLSLD_AIX_r(MVT VT, MVT RetVT, Register Op0) {
2687 switch (VT.SimpleTy) {
2688 case MVT::i32: return fastEmit_PPCISD_TLSLD_AIX_MVT_i32_r(RetVT, Op0);
2689 case MVT::i64: return fastEmit_PPCISD_TLSLD_AIX_MVT_i64_r(RetVT, Op0);
2690 default: return Register();
2691 }
2692}
2693
2694// FastEmit functions for PPCISD::XXMFACC.
2695
2696Register fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(MVT RetVT, Register Op0) {
2697 if (RetVT.SimpleTy != MVT::v512i1)
2698 return Register();
2699 if ((!Subtarget->isISAFuture()) && (Subtarget->hasMMA())) {
2700 return fastEmitInst_r(MachineInstOpcode: PPC::XXMFACC, RC: &PPC::ACCRCRegClass, Op0);
2701 }
2702 return Register();
2703}
2704
2705Register fastEmit_PPCISD_XXMFACC_r(MVT VT, MVT RetVT, Register Op0) {
2706 switch (VT.SimpleTy) {
2707 case MVT::v512i1: return fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(RetVT, Op0);
2708 default: return Register();
2709 }
2710}
2711
2712// FastEmit functions for PPCISD::XXSPLTI_SP_TO_DP.
2713
2714Register fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(MVT RetVT, Register Op0) {
2715 if (RetVT.SimpleTy != MVT::v2f64)
2716 return Register();
2717 if ((Subtarget->hasPrefixInstrs())) {
2718 return fastEmitInst_r(MachineInstOpcode: PPC::XXSPLTIDP, RC: &PPC::VSRCRegClass, Op0);
2719 }
2720 return Register();
2721}
2722
2723Register fastEmit_PPCISD_XXSPLTI_SP_TO_DP_r(MVT VT, MVT RetVT, Register Op0) {
2724 switch (VT.SimpleTy) {
2725 case MVT::i32: return fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(RetVT, Op0);
2726 default: return Register();
2727 }
2728}
2729
2730// Top-level FastEmit function.
2731
2732Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
2733 switch (Opcode) {
2734 case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0);
2735 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
2736 case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0);
2737 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
2738 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
2739 case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0);
2740 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
2741 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0);
2742 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0);
2743 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0);
2744 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
2745 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
2746 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
2747 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
2748 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
2749 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
2750 case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0);
2751 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
2752 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0);
2753 case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0);
2754 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
2755 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
2756 case ISD::STRICT_FCEIL: return fastEmit_ISD_STRICT_FCEIL_r(VT, RetVT, Op0);
2757 case ISD::STRICT_FFLOOR: return fastEmit_ISD_STRICT_FFLOOR_r(VT, RetVT, Op0);
2758 case ISD::STRICT_FNEARBYINT: return fastEmit_ISD_STRICT_FNEARBYINT_r(VT, RetVT, Op0);
2759 case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0);
2760 case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0);
2761 case ISD::STRICT_FP_TO_SINT: return fastEmit_ISD_STRICT_FP_TO_SINT_r(VT, RetVT, Op0);
2762 case ISD::STRICT_FP_TO_UINT: return fastEmit_ISD_STRICT_FP_TO_UINT_r(VT, RetVT, Op0);
2763 case ISD::STRICT_FRINT: return fastEmit_ISD_STRICT_FRINT_r(VT, RetVT, Op0);
2764 case ISD::STRICT_FROUND: return fastEmit_ISD_STRICT_FROUND_r(VT, RetVT, Op0);
2765 case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0);
2766 case ISD::STRICT_FTRUNC: return fastEmit_ISD_STRICT_FTRUNC_r(VT, RetVT, Op0);
2767 case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0);
2768 case ISD::STRICT_UINT_TO_FP: return fastEmit_ISD_STRICT_UINT_TO_FP_r(VT, RetVT, Op0);
2769 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0);
2770 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
2771 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0);
2772 case PPCISD::FCFID: return fastEmit_PPCISD_FCFID_r(VT, RetVT, Op0);
2773 case PPCISD::FCFIDS: return fastEmit_PPCISD_FCFIDS_r(VT, RetVT, Op0);
2774 case PPCISD::FCFIDU: return fastEmit_PPCISD_FCFIDU_r(VT, RetVT, Op0);
2775 case PPCISD::FCFIDUS: return fastEmit_PPCISD_FCFIDUS_r(VT, RetVT, Op0);
2776 case PPCISD::FCTIDUZ: return fastEmit_PPCISD_FCTIDUZ_r(VT, RetVT, Op0);
2777 case PPCISD::FCTIDZ: return fastEmit_PPCISD_FCTIDZ_r(VT, RetVT, Op0);
2778 case PPCISD::FCTIWUZ: return fastEmit_PPCISD_FCTIWUZ_r(VT, RetVT, Op0);
2779 case PPCISD::FCTIWZ: return fastEmit_PPCISD_FCTIWZ_r(VT, RetVT, Op0);
2780 case PPCISD::FRE: return fastEmit_PPCISD_FRE_r(VT, RetVT, Op0);
2781 case PPCISD::FRSQRTE: return fastEmit_PPCISD_FRSQRTE_r(VT, RetVT, Op0);
2782 case PPCISD::FSQRT: return fastEmit_PPCISD_FSQRT_r(VT, RetVT, Op0);
2783 case PPCISD::FTSQRT: return fastEmit_PPCISD_FTSQRT_r(VT, RetVT, Op0);
2784 case PPCISD::GET_TLS_MOD_AIX: return fastEmit_PPCISD_GET_TLS_MOD_AIX_r(VT, RetVT, Op0);
2785 case PPCISD::MFVSR: return fastEmit_PPCISD_MFVSR_r(VT, RetVT, Op0);
2786 case PPCISD::MTVSRA: return fastEmit_PPCISD_MTVSRA_r(VT, RetVT, Op0);
2787 case PPCISD::MTVSRZ: return fastEmit_PPCISD_MTVSRZ_r(VT, RetVT, Op0);
2788 case PPCISD::SCALAR_TO_VECTOR_PERMUTED: return fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_r(VT, RetVT, Op0);
2789 case PPCISD::SETBC: return fastEmit_PPCISD_SETBC_r(VT, RetVT, Op0);
2790 case PPCISD::SETBCR: return fastEmit_PPCISD_SETBCR_r(VT, RetVT, Op0);
2791 case PPCISD::STRICT_FCFID: return fastEmit_PPCISD_STRICT_FCFID_r(VT, RetVT, Op0);
2792 case PPCISD::STRICT_FCFIDS: return fastEmit_PPCISD_STRICT_FCFIDS_r(VT, RetVT, Op0);
2793 case PPCISD::STRICT_FCFIDU: return fastEmit_PPCISD_STRICT_FCFIDU_r(VT, RetVT, Op0);
2794 case PPCISD::STRICT_FCFIDUS: return fastEmit_PPCISD_STRICT_FCFIDUS_r(VT, RetVT, Op0);
2795 case PPCISD::STRICT_FCTIDUZ: return fastEmit_PPCISD_STRICT_FCTIDUZ_r(VT, RetVT, Op0);
2796 case PPCISD::STRICT_FCTIDZ: return fastEmit_PPCISD_STRICT_FCTIDZ_r(VT, RetVT, Op0);
2797 case PPCISD::STRICT_FCTIWUZ: return fastEmit_PPCISD_STRICT_FCTIWUZ_r(VT, RetVT, Op0);
2798 case PPCISD::STRICT_FCTIWZ: return fastEmit_PPCISD_STRICT_FCTIWZ_r(VT, RetVT, Op0);
2799 case PPCISD::TLSLD_AIX: return fastEmit_PPCISD_TLSLD_AIX_r(VT, RetVT, Op0);
2800 case PPCISD::XXMFACC: return fastEmit_PPCISD_XXMFACC_r(VT, RetVT, Op0);
2801 case PPCISD::XXSPLTI_SP_TO_DP: return fastEmit_PPCISD_XXSPLTI_SP_TO_DP_r(VT, RetVT, Op0);
2802 default: return Register();
2803 }
2804}
2805
2806// FastEmit functions for ISD::ABDU.
2807
2808Register fastEmit_ISD_ABDU_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2809 if (RetVT.SimpleTy != MVT::v16i8)
2810 return Register();
2811 if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) {
2812 return fastEmitInst_rr(MachineInstOpcode: PPC::VABSDUB, RC: &PPC::VRRCRegClass, Op0, Op1);
2813 }
2814 return Register();
2815}
2816
2817Register fastEmit_ISD_ABDU_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2818 if (RetVT.SimpleTy != MVT::v8i16)
2819 return Register();
2820 if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) {
2821 return fastEmitInst_rr(MachineInstOpcode: PPC::VABSDUH, RC: &PPC::VRRCRegClass, Op0, Op1);
2822 }
2823 return Register();
2824}
2825
2826Register fastEmit_ISD_ABDU_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2827 if (RetVT.SimpleTy != MVT::v4i32)
2828 return Register();
2829 if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) {
2830 return fastEmitInst_rr(MachineInstOpcode: PPC::VABSDUW, RC: &PPC::VRRCRegClass, Op0, Op1);
2831 }
2832 return Register();
2833}
2834
2835Register fastEmit_ISD_ABDU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2836 switch (VT.SimpleTy) {
2837 case MVT::v16i8: return fastEmit_ISD_ABDU_MVT_v16i8_rr(RetVT, Op0, Op1);
2838 case MVT::v8i16: return fastEmit_ISD_ABDU_MVT_v8i16_rr(RetVT, Op0, Op1);
2839 case MVT::v4i32: return fastEmit_ISD_ABDU_MVT_v4i32_rr(RetVT, Op0, Op1);
2840 default: return Register();
2841 }
2842}
2843
2844// FastEmit functions for ISD::ADD.
2845
2846Register fastEmit_ISD_ADD_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
2847 if (RetVT.SimpleTy != MVT::i1)
2848 return Register();
2849 return fastEmitInst_rr(MachineInstOpcode: PPC::CRXOR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
2850}
2851
2852Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2853 if (RetVT.SimpleTy != MVT::i32)
2854 return Register();
2855 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD4, RC: &PPC::GPRCRegClass, Op0, Op1);
2856}
2857
2858Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2859 if (RetVT.SimpleTy != MVT::i64)
2860 return Register();
2861 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD8, RC: &PPC::G8RCRegClass, Op0, Op1);
2862}
2863
2864Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2865 if (RetVT.SimpleTy != MVT::v16i8)
2866 return Register();
2867 if ((Subtarget->hasAltivec())) {
2868 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUBM, RC: &PPC::VRRCRegClass, Op0, Op1);
2869 }
2870 return Register();
2871}
2872
2873Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2874 if (RetVT.SimpleTy != MVT::v8i16)
2875 return Register();
2876 if ((Subtarget->hasAltivec())) {
2877 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUHM, RC: &PPC::VRRCRegClass, Op0, Op1);
2878 }
2879 return Register();
2880}
2881
2882Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2883 if (RetVT.SimpleTy != MVT::v4i32)
2884 return Register();
2885 if ((Subtarget->hasFutureVector())) {
2886 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDUWM, RC: &PPC::VSRCRegClass, Op0, Op1);
2887 }
2888 if ((Subtarget->hasAltivec())) {
2889 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUWM, RC: &PPC::VRRCRegClass, Op0, Op1);
2890 }
2891 return Register();
2892}
2893
2894Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2895 if (RetVT.SimpleTy != MVT::v2i64)
2896 return Register();
2897 if ((Subtarget->hasP8Altivec())) {
2898 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUDM, RC: &PPC::VRRCRegClass, Op0, Op1);
2899 }
2900 return Register();
2901}
2902
2903Register fastEmit_ISD_ADD_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
2904 if (RetVT.SimpleTy != MVT::v1i128)
2905 return Register();
2906 if ((Subtarget->hasP8Altivec())) {
2907 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUQM, RC: &PPC::VRRCRegClass, Op0, Op1);
2908 }
2909 return Register();
2910}
2911
2912Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2913 switch (VT.SimpleTy) {
2914 case MVT::i1: return fastEmit_ISD_ADD_MVT_i1_rr(RetVT, Op0, Op1);
2915 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
2916 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
2917 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
2918 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
2919 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
2920 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
2921 case MVT::v1i128: return fastEmit_ISD_ADD_MVT_v1i128_rr(RetVT, Op0, Op1);
2922 default: return Register();
2923 }
2924}
2925
2926// FastEmit functions for ISD::AND.
2927
2928Register fastEmit_ISD_AND_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
2929 if (RetVT.SimpleTy != MVT::i1)
2930 return Register();
2931 return fastEmitInst_rr(MachineInstOpcode: PPC::CRAND, RC: &PPC::CRBITRCRegClass, Op0, Op1);
2932}
2933
2934Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2935 if (RetVT.SimpleTy != MVT::i32)
2936 return Register();
2937 return fastEmitInst_rr(MachineInstOpcode: PPC::AND, RC: &PPC::GPRCRegClass, Op0, Op1);
2938}
2939
2940Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2941 if (RetVT.SimpleTy != MVT::i64)
2942 return Register();
2943 return fastEmitInst_rr(MachineInstOpcode: PPC::AND8, RC: &PPC::G8RCRegClass, Op0, Op1);
2944}
2945
2946Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2947 if (RetVT.SimpleTy != MVT::v4i32)
2948 return Register();
2949 if ((Subtarget->hasVSX())) {
2950 return fastEmitInst_rr(MachineInstOpcode: PPC::XXLAND, RC: &PPC::VSRCRegClass, Op0, Op1);
2951 }
2952 if ((Subtarget->hasAltivec())) {
2953 return fastEmitInst_rr(MachineInstOpcode: PPC::VAND, RC: &PPC::VRRCRegClass, Op0, Op1);
2954 }
2955 return Register();
2956}
2957
2958Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2959 switch (VT.SimpleTy) {
2960 case MVT::i1: return fastEmit_ISD_AND_MVT_i1_rr(RetVT, Op0, Op1);
2961 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
2962 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
2963 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
2964 default: return Register();
2965 }
2966}
2967
2968// FastEmit functions for ISD::AVGCEILS.
2969
2970Register fastEmit_ISD_AVGCEILS_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2971 if (RetVT.SimpleTy != MVT::v16i8)
2972 return Register();
2973 if ((Subtarget->hasAltivec())) {
2974 return fastEmitInst_rr(MachineInstOpcode: PPC::VAVGSB, RC: &PPC::VRRCRegClass, Op0, Op1);
2975 }
2976 return Register();
2977}
2978
2979Register fastEmit_ISD_AVGCEILS_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2980 if (RetVT.SimpleTy != MVT::v8i16)
2981 return Register();
2982 if ((Subtarget->hasAltivec())) {
2983 return fastEmitInst_rr(MachineInstOpcode: PPC::VAVGSH, RC: &PPC::VRRCRegClass, Op0, Op1);
2984 }
2985 return Register();
2986}
2987
2988Register fastEmit_ISD_AVGCEILS_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2989 if (RetVT.SimpleTy != MVT::v4i32)
2990 return Register();
2991 if ((Subtarget->hasAltivec())) {
2992 return fastEmitInst_rr(MachineInstOpcode: PPC::VAVGSW, RC: &PPC::VRRCRegClass, Op0, Op1);
2993 }
2994 return Register();
2995}
2996
2997Register fastEmit_ISD_AVGCEILS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2998 switch (VT.SimpleTy) {
2999 case MVT::v16i8: return fastEmit_ISD_AVGCEILS_MVT_v16i8_rr(RetVT, Op0, Op1);
3000 case MVT::v8i16: return fastEmit_ISD_AVGCEILS_MVT_v8i16_rr(RetVT, Op0, Op1);
3001 case MVT::v4i32: return fastEmit_ISD_AVGCEILS_MVT_v4i32_rr(RetVT, Op0, Op1);
3002 default: return Register();
3003 }
3004}
3005
3006// FastEmit functions for ISD::AVGCEILU.
3007
3008Register fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3009 if (RetVT.SimpleTy != MVT::v16i8)
3010 return Register();
3011 if ((Subtarget->hasAltivec())) {
3012 return fastEmitInst_rr(MachineInstOpcode: PPC::VAVGUB, RC: &PPC::VRRCRegClass, Op0, Op1);
3013 }
3014 return Register();
3015}
3016
3017Register fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3018 if (RetVT.SimpleTy != MVT::v8i16)
3019 return Register();
3020 if ((Subtarget->hasAltivec())) {
3021 return fastEmitInst_rr(MachineInstOpcode: PPC::VAVGUH, RC: &PPC::VRRCRegClass, Op0, Op1);
3022 }
3023 return Register();
3024}
3025
3026Register fastEmit_ISD_AVGCEILU_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3027 if (RetVT.SimpleTy != MVT::v4i32)
3028 return Register();
3029 if ((Subtarget->hasAltivec())) {
3030 return fastEmitInst_rr(MachineInstOpcode: PPC::VAVGUW, RC: &PPC::VRRCRegClass, Op0, Op1);
3031 }
3032 return Register();
3033}
3034
3035Register fastEmit_ISD_AVGCEILU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3036 switch (VT.SimpleTy) {
3037 case MVT::v16i8: return fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(RetVT, Op0, Op1);
3038 case MVT::v8i16: return fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(RetVT, Op0, Op1);
3039 case MVT::v4i32: return fastEmit_ISD_AVGCEILU_MVT_v4i32_rr(RetVT, Op0, Op1);
3040 default: return Register();
3041 }
3042}
3043
3044// FastEmit functions for ISD::BUILD_VECTOR.
3045
3046Register fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3047 if (RetVT.SimpleTy != MVT::v2i64)
3048 return Register();
3049 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian()) && (Subtarget->isISA3_0()) && (Subtarget->isPPC64())) {
3050 return fastEmitInst_rr(MachineInstOpcode: PPC::MTVSRDD, RC: &PPC::VSRCRegClass, Op0, Op1);
3051 }
3052 return Register();
3053}
3054
3055Register fastEmit_ISD_BUILD_VECTOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3056 switch (VT.SimpleTy) {
3057 case MVT::i64: return fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(RetVT, Op0, Op1);
3058 default: return Register();
3059 }
3060}
3061
3062// FastEmit functions for ISD::FADD.
3063
3064Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3065 if (RetVT.SimpleTy != MVT::f32)
3066 return Register();
3067 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3068 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3069 }
3070 if ((Subtarget->hasSPE())) {
3071 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSADD, RC: &PPC::GPRCRegClass, Op0, Op1);
3072 }
3073 if ((Subtarget->hasFPU())) {
3074 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDS, RC: &PPC::F4RCRegClass, Op0, Op1);
3075 }
3076 return Register();
3077}
3078
3079Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3080 if (RetVT.SimpleTy != MVT::f64)
3081 return Register();
3082 if ((Subtarget->hasVSX())) {
3083 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3084 }
3085 if ((Subtarget->hasSPE())) {
3086 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDADD, RC: &PPC::SPERCRegClass, Op0, Op1);
3087 }
3088 if ((Subtarget->hasFPU())) {
3089 return fastEmitInst_rr(MachineInstOpcode: PPC::FADD, RC: &PPC::F8RCRegClass, Op0, Op1);
3090 }
3091 return Register();
3092}
3093
3094Register fastEmit_ISD_FADD_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
3095 if (RetVT.SimpleTy != MVT::f128)
3096 return Register();
3097 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3098 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3099 }
3100 return Register();
3101}
3102
3103Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3104 if (RetVT.SimpleTy != MVT::v4f32)
3105 return Register();
3106 if ((Subtarget->hasVSX())) {
3107 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3108 }
3109 if ((Subtarget->hasAltivec())) {
3110 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDFP, RC: &PPC::VRRCRegClass, Op0, Op1);
3111 }
3112 return Register();
3113}
3114
3115Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3116 if (RetVT.SimpleTy != MVT::v2f64)
3117 return Register();
3118 if ((Subtarget->hasVSX())) {
3119 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3120 }
3121 return Register();
3122}
3123
3124Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3125 switch (VT.SimpleTy) {
3126 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
3127 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
3128 case MVT::f128: return fastEmit_ISD_FADD_MVT_f128_rr(RetVT, Op0, Op1);
3129 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
3130 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
3131 default: return Register();
3132 }
3133}
3134
3135// FastEmit functions for ISD::FDIV.
3136
3137Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3138 if (RetVT.SimpleTy != MVT::f32)
3139 return Register();
3140 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3141 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3142 }
3143 if ((Subtarget->hasSPE())) {
3144 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSDIV, RC: &PPC::GPRCRegClass, Op0, Op1);
3145 }
3146 if ((Subtarget->hasFPU())) {
3147 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIVS, RC: &PPC::F4RCRegClass, Op0, Op1);
3148 }
3149 return Register();
3150}
3151
3152Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3153 if (RetVT.SimpleTy != MVT::f64)
3154 return Register();
3155 if ((Subtarget->hasVSX())) {
3156 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3157 }
3158 if ((Subtarget->hasSPE())) {
3159 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDDIV, RC: &PPC::SPERCRegClass, Op0, Op1);
3160 }
3161 if ((Subtarget->hasFPU())) {
3162 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIV, RC: &PPC::F8RCRegClass, Op0, Op1);
3163 }
3164 return Register();
3165}
3166
3167Register fastEmit_ISD_FDIV_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
3168 if (RetVT.SimpleTy != MVT::f128)
3169 return Register();
3170 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3171 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3172 }
3173 return Register();
3174}
3175
3176Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3177 if (RetVT.SimpleTy != MVT::v4f32)
3178 return Register();
3179 if ((Subtarget->hasVSX())) {
3180 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3181 }
3182 return Register();
3183}
3184
3185Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3186 if (RetVT.SimpleTy != MVT::v2f64)
3187 return Register();
3188 if ((Subtarget->hasVSX())) {
3189 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3190 }
3191 return Register();
3192}
3193
3194Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3195 switch (VT.SimpleTy) {
3196 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
3197 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
3198 case MVT::f128: return fastEmit_ISD_FDIV_MVT_f128_rr(RetVT, Op0, Op1);
3199 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
3200 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
3201 default: return Register();
3202 }
3203}
3204
3205// FastEmit functions for ISD::FMAXNUM.
3206
3207Register fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3208 if (RetVT.SimpleTy != MVT::f64)
3209 return Register();
3210 if ((Subtarget->hasVSX())) {
3211 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3212 }
3213 return Register();
3214}
3215
3216Register fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3217 if (RetVT.SimpleTy != MVT::v4f32)
3218 return Register();
3219 if ((Subtarget->hasVSX())) {
3220 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3221 }
3222 return Register();
3223}
3224
3225Register fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3226 if (RetVT.SimpleTy != MVT::v2f64)
3227 return Register();
3228 if ((Subtarget->hasVSX())) {
3229 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3230 }
3231 return Register();
3232}
3233
3234Register fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3235 switch (VT.SimpleTy) {
3236 case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op1);
3237 case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
3238 case MVT::v2f64: return fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
3239 default: return Register();
3240 }
3241}
3242
3243// FastEmit functions for ISD::FMAXNUM_IEEE.
3244
3245Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3246 if (RetVT.SimpleTy != MVT::f64)
3247 return Register();
3248 if ((Subtarget->hasVSX())) {
3249 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3250 }
3251 return Register();
3252}
3253
3254Register fastEmit_ISD_FMAXNUM_IEEE_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3255 if (RetVT.SimpleTy != MVT::v4f32)
3256 return Register();
3257 if ((Subtarget->hasVSX())) {
3258 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3259 }
3260 return Register();
3261}
3262
3263Register fastEmit_ISD_FMAXNUM_IEEE_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3264 if (RetVT.SimpleTy != MVT::v2f64)
3265 return Register();
3266 if ((Subtarget->hasVSX())) {
3267 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3268 }
3269 return Register();
3270}
3271
3272Register fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3273 switch (VT.SimpleTy) {
3274 case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
3275 case MVT::v4f32: return fastEmit_ISD_FMAXNUM_IEEE_MVT_v4f32_rr(RetVT, Op0, Op1);
3276 case MVT::v2f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_v2f64_rr(RetVT, Op0, Op1);
3277 default: return Register();
3278 }
3279}
3280
3281// FastEmit functions for ISD::FMINNUM.
3282
3283Register fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3284 if (RetVT.SimpleTy != MVT::f64)
3285 return Register();
3286 if ((Subtarget->hasVSX())) {
3287 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3288 }
3289 return Register();
3290}
3291
3292Register fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3293 if (RetVT.SimpleTy != MVT::v4f32)
3294 return Register();
3295 if ((Subtarget->hasVSX())) {
3296 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3297 }
3298 return Register();
3299}
3300
3301Register fastEmit_ISD_FMINNUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3302 if (RetVT.SimpleTy != MVT::v2f64)
3303 return Register();
3304 if ((Subtarget->hasVSX())) {
3305 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3306 }
3307 return Register();
3308}
3309
3310Register fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3311 switch (VT.SimpleTy) {
3312 case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op1);
3313 case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
3314 case MVT::v2f64: return fastEmit_ISD_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
3315 default: return Register();
3316 }
3317}
3318
3319// FastEmit functions for ISD::FMINNUM_IEEE.
3320
3321Register fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3322 if (RetVT.SimpleTy != MVT::f64)
3323 return Register();
3324 if ((Subtarget->hasVSX())) {
3325 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3326 }
3327 return Register();
3328}
3329
3330Register fastEmit_ISD_FMINNUM_IEEE_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3331 if (RetVT.SimpleTy != MVT::v4f32)
3332 return Register();
3333 if ((Subtarget->hasVSX())) {
3334 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3335 }
3336 return Register();
3337}
3338
3339Register fastEmit_ISD_FMINNUM_IEEE_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3340 if (RetVT.SimpleTy != MVT::v2f64)
3341 return Register();
3342 if ((Subtarget->hasVSX())) {
3343 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3344 }
3345 return Register();
3346}
3347
3348Register fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3349 switch (VT.SimpleTy) {
3350 case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
3351 case MVT::v4f32: return fastEmit_ISD_FMINNUM_IEEE_MVT_v4f32_rr(RetVT, Op0, Op1);
3352 case MVT::v2f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_v2f64_rr(RetVT, Op0, Op1);
3353 default: return Register();
3354 }
3355}
3356
3357// FastEmit functions for ISD::FMUL.
3358
3359Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3360 if (RetVT.SimpleTy != MVT::f32)
3361 return Register();
3362 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3363 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3364 }
3365 if ((Subtarget->hasSPE())) {
3366 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSMUL, RC: &PPC::GPRCRegClass, Op0, Op1);
3367 }
3368 if ((Subtarget->hasFPU())) {
3369 return fastEmitInst_rr(MachineInstOpcode: PPC::FMULS, RC: &PPC::F4RCRegClass, Op0, Op1);
3370 }
3371 return Register();
3372}
3373
3374Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3375 if (RetVT.SimpleTy != MVT::f64)
3376 return Register();
3377 if ((Subtarget->hasVSX())) {
3378 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3379 }
3380 if ((Subtarget->hasSPE())) {
3381 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDMUL, RC: &PPC::SPERCRegClass, Op0, Op1);
3382 }
3383 if ((Subtarget->hasFPU())) {
3384 return fastEmitInst_rr(MachineInstOpcode: PPC::FMUL, RC: &PPC::F8RCRegClass, Op0, Op1);
3385 }
3386 return Register();
3387}
3388
3389Register fastEmit_ISD_FMUL_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
3390 if (RetVT.SimpleTy != MVT::f128)
3391 return Register();
3392 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3393 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3394 }
3395 return Register();
3396}
3397
3398Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3399 if (RetVT.SimpleTy != MVT::v4f32)
3400 return Register();
3401 if ((Subtarget->hasVSX())) {
3402 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3403 }
3404 return Register();
3405}
3406
3407Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3408 if (RetVT.SimpleTy != MVT::v2f64)
3409 return Register();
3410 if ((Subtarget->hasVSX())) {
3411 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3412 }
3413 return Register();
3414}
3415
3416Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3417 switch (VT.SimpleTy) {
3418 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
3419 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
3420 case MVT::f128: return fastEmit_ISD_FMUL_MVT_f128_rr(RetVT, Op0, Op1);
3421 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
3422 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
3423 default: return Register();
3424 }
3425}
3426
3427// FastEmit functions for ISD::FSUB.
3428
3429Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3430 if (RetVT.SimpleTy != MVT::f32)
3431 return Register();
3432 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3433 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3434 }
3435 if ((Subtarget->hasSPE())) {
3436 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSSUB, RC: &PPC::GPRCRegClass, Op0, Op1);
3437 }
3438 if ((Subtarget->hasFPU())) {
3439 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUBS, RC: &PPC::F4RCRegClass, Op0, Op1);
3440 }
3441 return Register();
3442}
3443
3444Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3445 if (RetVT.SimpleTy != MVT::f64)
3446 return Register();
3447 if ((Subtarget->hasVSX())) {
3448 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3449 }
3450 if ((Subtarget->hasSPE())) {
3451 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDSUB, RC: &PPC::SPERCRegClass, Op0, Op1);
3452 }
3453 if ((Subtarget->hasFPU())) {
3454 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUB, RC: &PPC::F8RCRegClass, Op0, Op1);
3455 }
3456 return Register();
3457}
3458
3459Register fastEmit_ISD_FSUB_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
3460 if (RetVT.SimpleTy != MVT::f128)
3461 return Register();
3462 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3463 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3464 }
3465 return Register();
3466}
3467
3468Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3469 if (RetVT.SimpleTy != MVT::v4f32)
3470 return Register();
3471 if ((Subtarget->hasVSX())) {
3472 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3473 }
3474 if ((Subtarget->hasAltivec())) {
3475 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBFP, RC: &PPC::VRRCRegClass, Op0, Op1);
3476 }
3477 return Register();
3478}
3479
3480Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3481 if (RetVT.SimpleTy != MVT::v2f64)
3482 return Register();
3483 if ((Subtarget->hasVSX())) {
3484 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3485 }
3486 return Register();
3487}
3488
3489Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3490 switch (VT.SimpleTy) {
3491 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
3492 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
3493 case MVT::f128: return fastEmit_ISD_FSUB_MVT_f128_rr(RetVT, Op0, Op1);
3494 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
3495 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
3496 default: return Register();
3497 }
3498}
3499
3500// FastEmit functions for ISD::MUL.
3501
3502Register fastEmit_ISD_MUL_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
3503 if (RetVT.SimpleTy != MVT::i1)
3504 return Register();
3505 return fastEmitInst_rr(MachineInstOpcode: PPC::CRAND, RC: &PPC::CRBITRCRegClass, Op0, Op1);
3506}
3507
3508Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3509 if (RetVT.SimpleTy != MVT::i32)
3510 return Register();
3511 return fastEmitInst_rr(MachineInstOpcode: PPC::MULLW, RC: &PPC::GPRCRegClass, Op0, Op1);
3512}
3513
3514Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3515 if (RetVT.SimpleTy != MVT::i64)
3516 return Register();
3517 return fastEmitInst_rr(MachineInstOpcode: PPC::MULLD, RC: &PPC::G8RCRegClass, Op0, Op1);
3518}
3519
3520Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3521 if (RetVT.SimpleTy != MVT::v4i32)
3522 return Register();
3523 if ((Subtarget->hasFutureVector())) {
3524 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULUWM, RC: &PPC::VSRCRegClass, Op0, Op1);
3525 }
3526 if ((Subtarget->hasP8Altivec())) {
3527 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULUWM, RC: &PPC::VRRCRegClass, Op0, Op1);
3528 }
3529 return Register();
3530}
3531
3532Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3533 if (RetVT.SimpleTy != MVT::v2i64)
3534 return Register();
3535 if ((Subtarget->isISA3_1())) {
3536 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULLD, RC: &PPC::VRRCRegClass, Op0, Op1);
3537 }
3538 return Register();
3539}
3540
3541Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3542 switch (VT.SimpleTy) {
3543 case MVT::i1: return fastEmit_ISD_MUL_MVT_i1_rr(RetVT, Op0, Op1);
3544 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
3545 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
3546 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
3547 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
3548 default: return Register();
3549 }
3550}
3551
3552// FastEmit functions for ISD::MULHS.
3553
3554Register fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3555 if (RetVT.SimpleTy != MVT::i32)
3556 return Register();
3557 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHW, RC: &PPC::GPRCRegClass, Op0, Op1);
3558}
3559
3560Register fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3561 if (RetVT.SimpleTy != MVT::i64)
3562 return Register();
3563 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHD, RC: &PPC::G8RCRegClass, Op0, Op1);
3564}
3565
3566Register fastEmit_ISD_MULHS_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3567 if (RetVT.SimpleTy != MVT::v4i32)
3568 return Register();
3569 if ((Subtarget->isISA3_1())) {
3570 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3571 }
3572 return Register();
3573}
3574
3575Register fastEmit_ISD_MULHS_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3576 if (RetVT.SimpleTy != MVT::v2i64)
3577 return Register();
3578 if ((Subtarget->isISA3_1())) {
3579 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHSD, RC: &PPC::VRRCRegClass, Op0, Op1);
3580 }
3581 return Register();
3582}
3583
3584Register fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3585 switch (VT.SimpleTy) {
3586 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1);
3587 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1);
3588 case MVT::v4i32: return fastEmit_ISD_MULHS_MVT_v4i32_rr(RetVT, Op0, Op1);
3589 case MVT::v2i64: return fastEmit_ISD_MULHS_MVT_v2i64_rr(RetVT, Op0, Op1);
3590 default: return Register();
3591 }
3592}
3593
3594// FastEmit functions for ISD::MULHU.
3595
3596Register fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3597 if (RetVT.SimpleTy != MVT::i32)
3598 return Register();
3599 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHWU, RC: &PPC::GPRCRegClass, Op0, Op1);
3600}
3601
3602Register fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3603 if (RetVT.SimpleTy != MVT::i64)
3604 return Register();
3605 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHDU, RC: &PPC::G8RCRegClass, Op0, Op1);
3606}
3607
3608Register fastEmit_ISD_MULHU_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3609 if (RetVT.SimpleTy != MVT::v4i32)
3610 return Register();
3611 if ((Subtarget->isISA3_1())) {
3612 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHUW, RC: &PPC::VRRCRegClass, Op0, Op1);
3613 }
3614 return Register();
3615}
3616
3617Register fastEmit_ISD_MULHU_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3618 if (RetVT.SimpleTy != MVT::v2i64)
3619 return Register();
3620 if ((Subtarget->isISA3_1())) {
3621 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHUD, RC: &PPC::VRRCRegClass, Op0, Op1);
3622 }
3623 return Register();
3624}
3625
3626Register fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3627 switch (VT.SimpleTy) {
3628 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1);
3629 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1);
3630 case MVT::v4i32: return fastEmit_ISD_MULHU_MVT_v4i32_rr(RetVT, Op0, Op1);
3631 case MVT::v2i64: return fastEmit_ISD_MULHU_MVT_v2i64_rr(RetVT, Op0, Op1);
3632 default: return Register();
3633 }
3634}
3635
3636// FastEmit functions for ISD::OR.
3637
3638Register fastEmit_ISD_OR_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
3639 if (RetVT.SimpleTy != MVT::i1)
3640 return Register();
3641 return fastEmitInst_rr(MachineInstOpcode: PPC::CROR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
3642}
3643
3644Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3645 if (RetVT.SimpleTy != MVT::i32)
3646 return Register();
3647 return fastEmitInst_rr(MachineInstOpcode: PPC::OR, RC: &PPC::GPRCRegClass, Op0, Op1);
3648}
3649
3650Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3651 if (RetVT.SimpleTy != MVT::i64)
3652 return Register();
3653 return fastEmitInst_rr(MachineInstOpcode: PPC::OR8, RC: &PPC::G8RCRegClass, Op0, Op1);
3654}
3655
3656Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3657 if (RetVT.SimpleTy != MVT::v4i32)
3658 return Register();
3659 if ((Subtarget->hasVSX())) {
3660 return fastEmitInst_rr(MachineInstOpcode: PPC::XXLOR, RC: &PPC::VSRCRegClass, Op0, Op1);
3661 }
3662 if ((Subtarget->hasAltivec())) {
3663 return fastEmitInst_rr(MachineInstOpcode: PPC::VOR, RC: &PPC::VRRCRegClass, Op0, Op1);
3664 }
3665 return Register();
3666}
3667
3668Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3669 switch (VT.SimpleTy) {
3670 case MVT::i1: return fastEmit_ISD_OR_MVT_i1_rr(RetVT, Op0, Op1);
3671 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
3672 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
3673 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
3674 default: return Register();
3675 }
3676}
3677
3678// FastEmit functions for ISD::ROTL.
3679
3680Register fastEmit_ISD_ROTL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3681 if (RetVT.SimpleTy != MVT::v16i8)
3682 return Register();
3683 if ((Subtarget->hasAltivec())) {
3684 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLB, RC: &PPC::VRRCRegClass, Op0, Op1);
3685 }
3686 return Register();
3687}
3688
3689Register fastEmit_ISD_ROTL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3690 if (RetVT.SimpleTy != MVT::v8i16)
3691 return Register();
3692 if ((Subtarget->hasAltivec())) {
3693 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLH, RC: &PPC::VRRCRegClass, Op0, Op1);
3694 }
3695 return Register();
3696}
3697
3698Register fastEmit_ISD_ROTL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3699 if (RetVT.SimpleTy != MVT::v4i32)
3700 return Register();
3701 if ((Subtarget->hasFutureVector())) {
3702 return fastEmitInst_rr(MachineInstOpcode: PPC::XVRLW, RC: &PPC::VSRCRegClass, Op0, Op1);
3703 }
3704 if ((!Subtarget->isISAFuture())) {
3705 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLW, RC: &PPC::VRRCRegClass, Op0, Op1);
3706 }
3707 return Register();
3708}
3709
3710Register fastEmit_ISD_ROTL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3711 if (RetVT.SimpleTy != MVT::v2i64)
3712 return Register();
3713 if ((Subtarget->hasP8Altivec())) {
3714 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLD, RC: &PPC::VRRCRegClass, Op0, Op1);
3715 }
3716 return Register();
3717}
3718
3719Register fastEmit_ISD_ROTL_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
3720 if (RetVT.SimpleTy != MVT::v1i128)
3721 return Register();
3722 if ((Subtarget->isISA3_1())) {
3723 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLQ, RC: &PPC::VRRCRegClass, Op0, Op1);
3724 }
3725 return Register();
3726}
3727
3728Register fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3729 switch (VT.SimpleTy) {
3730 case MVT::v16i8: return fastEmit_ISD_ROTL_MVT_v16i8_rr(RetVT, Op0, Op1);
3731 case MVT::v8i16: return fastEmit_ISD_ROTL_MVT_v8i16_rr(RetVT, Op0, Op1);
3732 case MVT::v4i32: return fastEmit_ISD_ROTL_MVT_v4i32_rr(RetVT, Op0, Op1);
3733 case MVT::v2i64: return fastEmit_ISD_ROTL_MVT_v2i64_rr(RetVT, Op0, Op1);
3734 case MVT::v1i128: return fastEmit_ISD_ROTL_MVT_v1i128_rr(RetVT, Op0, Op1);
3735 default: return Register();
3736 }
3737}
3738
3739// FastEmit functions for ISD::SADDSAT.
3740
3741Register fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3742 if (RetVT.SimpleTy != MVT::v16i8)
3743 return Register();
3744 if ((Subtarget->hasAltivec())) {
3745 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDSBS, RC: &PPC::VRRCRegClass, Op0, Op1);
3746 }
3747 return Register();
3748}
3749
3750Register fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3751 if (RetVT.SimpleTy != MVT::v8i16)
3752 return Register();
3753 if ((Subtarget->hasAltivec())) {
3754 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDSHS, RC: &PPC::VRRCRegClass, Op0, Op1);
3755 }
3756 return Register();
3757}
3758
3759Register fastEmit_ISD_SADDSAT_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3760 if (RetVT.SimpleTy != MVT::v4i32)
3761 return Register();
3762 if ((Subtarget->hasAltivec())) {
3763 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDSWS, RC: &PPC::VRRCRegClass, Op0, Op1);
3764 }
3765 return Register();
3766}
3767
3768Register fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3769 switch (VT.SimpleTy) {
3770 case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
3771 case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
3772 case MVT::v4i32: return fastEmit_ISD_SADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
3773 default: return Register();
3774 }
3775}
3776
3777// FastEmit functions for ISD::SDIV.
3778
3779Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3780 if (RetVT.SimpleTy != MVT::i32)
3781 return Register();
3782 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVW, RC: &PPC::GPRCRegClass, Op0, Op1);
3783}
3784
3785Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3786 if (RetVT.SimpleTy != MVT::i64)
3787 return Register();
3788 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVD, RC: &PPC::G8RCRegClass, Op0, Op1);
3789}
3790
3791Register fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3792 if (RetVT.SimpleTy != MVT::v4i32)
3793 return Register();
3794 if ((Subtarget->isISA3_1())) {
3795 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3796 }
3797 return Register();
3798}
3799
3800Register fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3801 if (RetVT.SimpleTy != MVT::v2i64)
3802 return Register();
3803 if ((Subtarget->isISA3_1())) {
3804 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVSD, RC: &PPC::VRRCRegClass, Op0, Op1);
3805 }
3806 return Register();
3807}
3808
3809Register fastEmit_ISD_SDIV_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
3810 if (RetVT.SimpleTy != MVT::v1i128)
3811 return Register();
3812 if ((Subtarget->isISA3_1())) {
3813 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVSQ, RC: &PPC::VRRCRegClass, Op0, Op1);
3814 }
3815 return Register();
3816}
3817
3818Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3819 switch (VT.SimpleTy) {
3820 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
3821 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
3822 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
3823 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
3824 case MVT::v1i128: return fastEmit_ISD_SDIV_MVT_v1i128_rr(RetVT, Op0, Op1);
3825 default: return Register();
3826 }
3827}
3828
3829// FastEmit functions for ISD::SHL.
3830
3831Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3832 if (RetVT.SimpleTy != MVT::i32)
3833 return Register();
3834 return fastEmitInst_rr(MachineInstOpcode: PPC::SLW, RC: &PPC::GPRCRegClass, Op0, Op1);
3835}
3836
3837Register fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3838 if (RetVT.SimpleTy != MVT::v16i8)
3839 return Register();
3840 if ((Subtarget->hasAltivec())) {
3841 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLB, RC: &PPC::VRRCRegClass, Op0, Op1);
3842 }
3843 return Register();
3844}
3845
3846Register fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3847 if (RetVT.SimpleTy != MVT::v8i16)
3848 return Register();
3849 if ((Subtarget->hasAltivec())) {
3850 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLH, RC: &PPC::VRRCRegClass, Op0, Op1);
3851 }
3852 return Register();
3853}
3854
3855Register fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3856 if (RetVT.SimpleTy != MVT::v4i32)
3857 return Register();
3858 if ((Subtarget->hasAltivec())) {
3859 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLW, RC: &PPC::VRRCRegClass, Op0, Op1);
3860 }
3861 return Register();
3862}
3863
3864Register fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3865 if (RetVT.SimpleTy != MVT::v2i64)
3866 return Register();
3867 if ((Subtarget->hasP8Altivec())) {
3868 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLD, RC: &PPC::VRRCRegClass, Op0, Op1);
3869 }
3870 return Register();
3871}
3872
3873Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3874 switch (VT.SimpleTy) {
3875 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
3876 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
3877 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
3878 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
3879 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
3880 default: return Register();
3881 }
3882}
3883
3884// FastEmit functions for ISD::SMAX.
3885
3886Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3887 if (RetVT.SimpleTy != MVT::v16i8)
3888 return Register();
3889 if ((Subtarget->hasAltivec())) {
3890 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXSB, RC: &PPC::VRRCRegClass, Op0, Op1);
3891 }
3892 return Register();
3893}
3894
3895Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3896 if (RetVT.SimpleTy != MVT::v8i16)
3897 return Register();
3898 if ((Subtarget->hasAltivec())) {
3899 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXSH, RC: &PPC::VRRCRegClass, Op0, Op1);
3900 }
3901 return Register();
3902}
3903
3904Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3905 if (RetVT.SimpleTy != MVT::v4i32)
3906 return Register();
3907 if ((Subtarget->hasAltivec())) {
3908 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3909 }
3910 return Register();
3911}
3912
3913Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3914 switch (VT.SimpleTy) {
3915 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
3916 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
3917 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
3918 default: return Register();
3919 }
3920}
3921
3922// FastEmit functions for ISD::SMIN.
3923
3924Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3925 if (RetVT.SimpleTy != MVT::v16i8)
3926 return Register();
3927 if ((Subtarget->hasAltivec())) {
3928 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINSB, RC: &PPC::VRRCRegClass, Op0, Op1);
3929 }
3930 return Register();
3931}
3932
3933Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3934 if (RetVT.SimpleTy != MVT::v8i16)
3935 return Register();
3936 if ((Subtarget->hasAltivec())) {
3937 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINSH, RC: &PPC::VRRCRegClass, Op0, Op1);
3938 }
3939 return Register();
3940}
3941
3942Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3943 if (RetVT.SimpleTy != MVT::v4i32)
3944 return Register();
3945 if ((Subtarget->hasAltivec())) {
3946 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3947 }
3948 return Register();
3949}
3950
3951Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3952 switch (VT.SimpleTy) {
3953 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
3954 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
3955 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
3956 default: return Register();
3957 }
3958}
3959
3960// FastEmit functions for ISD::SRA.
3961
3962Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3963 if (RetVT.SimpleTy != MVT::i32)
3964 return Register();
3965 return fastEmitInst_rr(MachineInstOpcode: PPC::SRAW, RC: &PPC::GPRCRegClass, Op0, Op1);
3966}
3967
3968Register fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3969 if (RetVT.SimpleTy != MVT::v16i8)
3970 return Register();
3971 if ((Subtarget->hasAltivec())) {
3972 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAB, RC: &PPC::VRRCRegClass, Op0, Op1);
3973 }
3974 return Register();
3975}
3976
3977Register fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3978 if (RetVT.SimpleTy != MVT::v8i16)
3979 return Register();
3980 if ((Subtarget->hasAltivec())) {
3981 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAH, RC: &PPC::VRRCRegClass, Op0, Op1);
3982 }
3983 return Register();
3984}
3985
3986Register fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3987 if (RetVT.SimpleTy != MVT::v4i32)
3988 return Register();
3989 if ((Subtarget->hasAltivec())) {
3990 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAW, RC: &PPC::VRRCRegClass, Op0, Op1);
3991 }
3992 return Register();
3993}
3994
3995Register fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3996 if (RetVT.SimpleTy != MVT::v2i64)
3997 return Register();
3998 if ((Subtarget->hasP8Altivec())) {
3999 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAD, RC: &PPC::VRRCRegClass, Op0, Op1);
4000 }
4001 return Register();
4002}
4003
4004Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4005 switch (VT.SimpleTy) {
4006 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
4007 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
4008 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
4009 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
4010 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
4011 default: return Register();
4012 }
4013}
4014
4015// FastEmit functions for ISD::SREM.
4016
4017Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4018 if (RetVT.SimpleTy != MVT::i32)
4019 return Register();
4020 if ((Subtarget->isISA3_0())) {
4021 return fastEmitInst_rr(MachineInstOpcode: PPC::MODSW, RC: &PPC::GPRCRegClass, Op0, Op1);
4022 }
4023 return Register();
4024}
4025
4026Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4027 if (RetVT.SimpleTy != MVT::i64)
4028 return Register();
4029 if ((Subtarget->isISA3_0())) {
4030 return fastEmitInst_rr(MachineInstOpcode: PPC::MODSD, RC: &PPC::G8RCRegClass, Op0, Op1);
4031 }
4032 return Register();
4033}
4034
4035Register fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4036 if (RetVT.SimpleTy != MVT::v4i32)
4037 return Register();
4038 if ((Subtarget->isISA3_1())) {
4039 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODSW, RC: &PPC::VRRCRegClass, Op0, Op1);
4040 }
4041 return Register();
4042}
4043
4044Register fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4045 if (RetVT.SimpleTy != MVT::v2i64)
4046 return Register();
4047 if ((Subtarget->isISA3_1())) {
4048 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODSD, RC: &PPC::VRRCRegClass, Op0, Op1);
4049 }
4050 return Register();
4051}
4052
4053Register fastEmit_ISD_SREM_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
4054 if (RetVT.SimpleTy != MVT::v1i128)
4055 return Register();
4056 if ((Subtarget->isISA3_1())) {
4057 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODSQ, RC: &PPC::VRRCRegClass, Op0, Op1);
4058 }
4059 return Register();
4060}
4061
4062Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4063 switch (VT.SimpleTy) {
4064 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
4065 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
4066 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1);
4067 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1);
4068 case MVT::v1i128: return fastEmit_ISD_SREM_MVT_v1i128_rr(RetVT, Op0, Op1);
4069 default: return Register();
4070 }
4071}
4072
4073// FastEmit functions for ISD::SRL.
4074
4075Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4076 if (RetVT.SimpleTy != MVT::i32)
4077 return Register();
4078 return fastEmitInst_rr(MachineInstOpcode: PPC::SRW, RC: &PPC::GPRCRegClass, Op0, Op1);
4079}
4080
4081Register fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4082 if (RetVT.SimpleTy != MVT::v16i8)
4083 return Register();
4084 if ((Subtarget->hasAltivec())) {
4085 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRB, RC: &PPC::VRRCRegClass, Op0, Op1);
4086 }
4087 return Register();
4088}
4089
4090Register fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4091 if (RetVT.SimpleTy != MVT::v8i16)
4092 return Register();
4093 if ((Subtarget->hasAltivec())) {
4094 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRH, RC: &PPC::VRRCRegClass, Op0, Op1);
4095 }
4096 return Register();
4097}
4098
4099Register fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4100 if (RetVT.SimpleTy != MVT::v4i32)
4101 return Register();
4102 if ((Subtarget->hasAltivec())) {
4103 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRW, RC: &PPC::VRRCRegClass, Op0, Op1);
4104 }
4105 return Register();
4106}
4107
4108Register fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4109 if (RetVT.SimpleTy != MVT::v2i64)
4110 return Register();
4111 if ((Subtarget->hasP8Altivec())) {
4112 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRD, RC: &PPC::VRRCRegClass, Op0, Op1);
4113 }
4114 return Register();
4115}
4116
4117Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4118 switch (VT.SimpleTy) {
4119 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
4120 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
4121 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
4122 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
4123 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
4124 default: return Register();
4125 }
4126}
4127
4128// FastEmit functions for ISD::SSUBSAT.
4129
4130Register fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4131 if (RetVT.SimpleTy != MVT::v16i8)
4132 return Register();
4133 if ((Subtarget->hasAltivec())) {
4134 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBSBS, RC: &PPC::VRRCRegClass, Op0, Op1);
4135 }
4136 return Register();
4137}
4138
4139Register fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4140 if (RetVT.SimpleTy != MVT::v8i16)
4141 return Register();
4142 if ((Subtarget->hasAltivec())) {
4143 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBSHS, RC: &PPC::VRRCRegClass, Op0, Op1);
4144 }
4145 return Register();
4146}
4147
4148Register fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4149 if (RetVT.SimpleTy != MVT::v4i32)
4150 return Register();
4151 if ((Subtarget->hasAltivec())) {
4152 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBSWS, RC: &PPC::VRRCRegClass, Op0, Op1);
4153 }
4154 return Register();
4155}
4156
4157Register fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4158 switch (VT.SimpleTy) {
4159 case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
4160 case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
4161 case MVT::v4i32: return fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
4162 default: return Register();
4163 }
4164}
4165
4166// FastEmit functions for ISD::STRICT_FADD.
4167
4168Register fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
4169 if (RetVT.SimpleTy != MVT::f32)
4170 return Register();
4171 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4172 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4173 }
4174 if ((Subtarget->hasSPE())) {
4175 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSADD, RC: &PPC::GPRCRegClass, Op0, Op1);
4176 }
4177 if ((Subtarget->hasFPU())) {
4178 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDS, RC: &PPC::F4RCRegClass, Op0, Op1);
4179 }
4180 return Register();
4181}
4182
4183Register fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4184 if (RetVT.SimpleTy != MVT::f64)
4185 return Register();
4186 if ((Subtarget->hasVSX())) {
4187 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4188 }
4189 if ((Subtarget->hasSPE())) {
4190 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDADD, RC: &PPC::SPERCRegClass, Op0, Op1);
4191 }
4192 if ((Subtarget->hasFPU())) {
4193 return fastEmitInst_rr(MachineInstOpcode: PPC::FADD, RC: &PPC::F8RCRegClass, Op0, Op1);
4194 }
4195 return Register();
4196}
4197
4198Register fastEmit_ISD_STRICT_FADD_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
4199 if (RetVT.SimpleTy != MVT::f128)
4200 return Register();
4201 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4202 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4203 }
4204 return Register();
4205}
4206
4207Register fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4208 if (RetVT.SimpleTy != MVT::v4f32)
4209 return Register();
4210 if ((Subtarget->hasVSX())) {
4211 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4212 }
4213 return Register();
4214}
4215
4216Register fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4217 if (RetVT.SimpleTy != MVT::v2f64)
4218 return Register();
4219 if ((Subtarget->hasVSX())) {
4220 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4221 }
4222 return Register();
4223}
4224
4225Register fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4226 switch (VT.SimpleTy) {
4227 case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1);
4228 case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1);
4229 case MVT::f128: return fastEmit_ISD_STRICT_FADD_MVT_f128_rr(RetVT, Op0, Op1);
4230 case MVT::v4f32: return fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
4231 case MVT::v2f64: return fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
4232 default: return Register();
4233 }
4234}
4235
4236// FastEmit functions for ISD::STRICT_FDIV.
4237
4238Register fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
4239 if (RetVT.SimpleTy != MVT::f32)
4240 return Register();
4241 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4242 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4243 }
4244 if ((Subtarget->hasSPE())) {
4245 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSDIV, RC: &PPC::GPRCRegClass, Op0, Op1);
4246 }
4247 if ((Subtarget->hasFPU())) {
4248 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIVS, RC: &PPC::F4RCRegClass, Op0, Op1);
4249 }
4250 return Register();
4251}
4252
4253Register fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4254 if (RetVT.SimpleTy != MVT::f64)
4255 return Register();
4256 if ((Subtarget->hasVSX())) {
4257 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4258 }
4259 if ((Subtarget->hasSPE())) {
4260 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDDIV, RC: &PPC::SPERCRegClass, Op0, Op1);
4261 }
4262 if ((Subtarget->hasFPU())) {
4263 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIV, RC: &PPC::F8RCRegClass, Op0, Op1);
4264 }
4265 return Register();
4266}
4267
4268Register fastEmit_ISD_STRICT_FDIV_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
4269 if (RetVT.SimpleTy != MVT::f128)
4270 return Register();
4271 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4272 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4273 }
4274 return Register();
4275}
4276
4277Register fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4278 if (RetVT.SimpleTy != MVT::v4f32)
4279 return Register();
4280 if ((Subtarget->hasVSX())) {
4281 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4282 }
4283 return Register();
4284}
4285
4286Register fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4287 if (RetVT.SimpleTy != MVT::v2f64)
4288 return Register();
4289 if ((Subtarget->hasVSX())) {
4290 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4291 }
4292 return Register();
4293}
4294
4295Register fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4296 switch (VT.SimpleTy) {
4297 case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
4298 case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
4299 case MVT::f128: return fastEmit_ISD_STRICT_FDIV_MVT_f128_rr(RetVT, Op0, Op1);
4300 case MVT::v4f32: return fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
4301 case MVT::v2f64: return fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
4302 default: return Register();
4303 }
4304}
4305
4306// FastEmit functions for ISD::STRICT_FMAXNUM.
4307
4308Register fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4309 if (RetVT.SimpleTy != MVT::v4f32)
4310 return Register();
4311 if ((Subtarget->hasVSX())) {
4312 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4313 }
4314 return Register();
4315}
4316
4317Register fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4318 if (RetVT.SimpleTy != MVT::v2f64)
4319 return Register();
4320 if ((Subtarget->hasVSX())) {
4321 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4322 }
4323 return Register();
4324}
4325
4326Register fastEmit_ISD_STRICT_FMAXNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4327 switch (VT.SimpleTy) {
4328 case MVT::v4f32: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
4329 case MVT::v2f64: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
4330 default: return Register();
4331 }
4332}
4333
4334// FastEmit functions for ISD::STRICT_FMINNUM.
4335
4336Register fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4337 if (RetVT.SimpleTy != MVT::v4f32)
4338 return Register();
4339 if ((Subtarget->hasVSX())) {
4340 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4341 }
4342 return Register();
4343}
4344
4345Register fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4346 if (RetVT.SimpleTy != MVT::v2f64)
4347 return Register();
4348 if ((Subtarget->hasVSX())) {
4349 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4350 }
4351 return Register();
4352}
4353
4354Register fastEmit_ISD_STRICT_FMINNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4355 switch (VT.SimpleTy) {
4356 case MVT::v4f32: return fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
4357 case MVT::v2f64: return fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
4358 default: return Register();
4359 }
4360}
4361
4362// FastEmit functions for ISD::STRICT_FMUL.
4363
4364Register fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
4365 if (RetVT.SimpleTy != MVT::f32)
4366 return Register();
4367 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4368 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4369 }
4370 if ((Subtarget->hasSPE())) {
4371 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSMUL, RC: &PPC::GPRCRegClass, Op0, Op1);
4372 }
4373 if ((Subtarget->hasFPU())) {
4374 return fastEmitInst_rr(MachineInstOpcode: PPC::FMULS, RC: &PPC::F4RCRegClass, Op0, Op1);
4375 }
4376 return Register();
4377}
4378
4379Register fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4380 if (RetVT.SimpleTy != MVT::f64)
4381 return Register();
4382 if ((Subtarget->hasVSX())) {
4383 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4384 }
4385 if ((Subtarget->hasSPE())) {
4386 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDMUL, RC: &PPC::SPERCRegClass, Op0, Op1);
4387 }
4388 if ((Subtarget->hasFPU())) {
4389 return fastEmitInst_rr(MachineInstOpcode: PPC::FMUL, RC: &PPC::F8RCRegClass, Op0, Op1);
4390 }
4391 return Register();
4392}
4393
4394Register fastEmit_ISD_STRICT_FMUL_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
4395 if (RetVT.SimpleTy != MVT::f128)
4396 return Register();
4397 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4398 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4399 }
4400 return Register();
4401}
4402
4403Register fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4404 if (RetVT.SimpleTy != MVT::v4f32)
4405 return Register();
4406 if ((Subtarget->hasVSX())) {
4407 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4408 }
4409 return Register();
4410}
4411
4412Register fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4413 if (RetVT.SimpleTy != MVT::v2f64)
4414 return Register();
4415 if ((Subtarget->hasVSX())) {
4416 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4417 }
4418 return Register();
4419}
4420
4421Register fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4422 switch (VT.SimpleTy) {
4423 case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
4424 case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
4425 case MVT::f128: return fastEmit_ISD_STRICT_FMUL_MVT_f128_rr(RetVT, Op0, Op1);
4426 case MVT::v4f32: return fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
4427 case MVT::v2f64: return fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
4428 default: return Register();
4429 }
4430}
4431
4432// FastEmit functions for ISD::STRICT_FSUB.
4433
4434Register fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
4435 if (RetVT.SimpleTy != MVT::f32)
4436 return Register();
4437 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4438 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4439 }
4440 if ((Subtarget->hasSPE())) {
4441 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSSUB, RC: &PPC::GPRCRegClass, Op0, Op1);
4442 }
4443 if ((Subtarget->hasFPU())) {
4444 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUBS, RC: &PPC::F4RCRegClass, Op0, Op1);
4445 }
4446 return Register();
4447}
4448
4449Register fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4450 if (RetVT.SimpleTy != MVT::f64)
4451 return Register();
4452 if ((Subtarget->hasVSX())) {
4453 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4454 }
4455 if ((Subtarget->hasSPE())) {
4456 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDSUB, RC: &PPC::SPERCRegClass, Op0, Op1);
4457 }
4458 if ((Subtarget->hasFPU())) {
4459 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUB, RC: &PPC::F8RCRegClass, Op0, Op1);
4460 }
4461 return Register();
4462}
4463
4464Register fastEmit_ISD_STRICT_FSUB_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
4465 if (RetVT.SimpleTy != MVT::f128)
4466 return Register();
4467 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4468 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4469 }
4470 return Register();
4471}
4472
4473Register fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4474 if (RetVT.SimpleTy != MVT::v4f32)
4475 return Register();
4476 if ((Subtarget->hasVSX())) {
4477 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4478 }
4479 return Register();
4480}
4481
4482Register fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4483 if (RetVT.SimpleTy != MVT::v2f64)
4484 return Register();
4485 if ((Subtarget->hasVSX())) {
4486 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4487 }
4488 return Register();
4489}
4490
4491Register fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4492 switch (VT.SimpleTy) {
4493 case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
4494 case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
4495 case MVT::f128: return fastEmit_ISD_STRICT_FSUB_MVT_f128_rr(RetVT, Op0, Op1);
4496 case MVT::v4f32: return fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
4497 case MVT::v2f64: return fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
4498 default: return Register();
4499 }
4500}
4501
4502// FastEmit functions for ISD::SUB.
4503
4504Register fastEmit_ISD_SUB_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
4505 if (RetVT.SimpleTy != MVT::i1)
4506 return Register();
4507 return fastEmitInst_rr(MachineInstOpcode: PPC::CRXOR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
4508}
4509
4510Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4511 if (RetVT.SimpleTy != MVT::v16i8)
4512 return Register();
4513 if ((Subtarget->hasAltivec())) {
4514 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUBM, RC: &PPC::VRRCRegClass, Op0, Op1);
4515 }
4516 return Register();
4517}
4518
4519Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4520 if (RetVT.SimpleTy != MVT::v8i16)
4521 return Register();
4522 if ((Subtarget->hasAltivec())) {
4523 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUHM, RC: &PPC::VRRCRegClass, Op0, Op1);
4524 }
4525 return Register();
4526}
4527
4528Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4529 if (RetVT.SimpleTy != MVT::v4i32)
4530 return Register();
4531 if ((Subtarget->hasFutureVector())) {
4532 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBUWM, RC: &PPC::VSRCRegClass, Op0, Op1);
4533 }
4534 if ((Subtarget->hasAltivec())) {
4535 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUWM, RC: &PPC::VRRCRegClass, Op0, Op1);
4536 }
4537 return Register();
4538}
4539
4540Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4541 if (RetVT.SimpleTy != MVT::v2i64)
4542 return Register();
4543 if ((Subtarget->hasP8Altivec())) {
4544 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUDM, RC: &PPC::VRRCRegClass, Op0, Op1);
4545 }
4546 return Register();
4547}
4548
4549Register fastEmit_ISD_SUB_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
4550 if (RetVT.SimpleTy != MVT::v1i128)
4551 return Register();
4552 if ((Subtarget->hasP8Altivec())) {
4553 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUQM, RC: &PPC::VRRCRegClass, Op0, Op1);
4554 }
4555 return Register();
4556}
4557
4558Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4559 switch (VT.SimpleTy) {
4560 case MVT::i1: return fastEmit_ISD_SUB_MVT_i1_rr(RetVT, Op0, Op1);
4561 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
4562 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
4563 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
4564 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
4565 case MVT::v1i128: return fastEmit_ISD_SUB_MVT_v1i128_rr(RetVT, Op0, Op1);
4566 default: return Register();
4567 }
4568}
4569
4570// FastEmit functions for ISD::UADDSAT.
4571
4572Register fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4573 if (RetVT.SimpleTy != MVT::v16i8)
4574 return Register();
4575 if ((Subtarget->hasAltivec())) {
4576 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUBS, RC: &PPC::VRRCRegClass, Op0, Op1);
4577 }
4578 return Register();
4579}
4580
4581Register fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4582 if (RetVT.SimpleTy != MVT::v8i16)
4583 return Register();
4584 if ((Subtarget->hasAltivec())) {
4585 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUHS, RC: &PPC::VRRCRegClass, Op0, Op1);
4586 }
4587 return Register();
4588}
4589
4590Register fastEmit_ISD_UADDSAT_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4591 if (RetVT.SimpleTy != MVT::v4i32)
4592 return Register();
4593 if ((Subtarget->hasAltivec())) {
4594 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUWS, RC: &PPC::VRRCRegClass, Op0, Op1);
4595 }
4596 return Register();
4597}
4598
4599Register fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4600 switch (VT.SimpleTy) {
4601 case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
4602 case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
4603 case MVT::v4i32: return fastEmit_ISD_UADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
4604 default: return Register();
4605 }
4606}
4607
4608// FastEmit functions for ISD::UDIV.
4609
4610Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4611 if (RetVT.SimpleTy != MVT::i32)
4612 return Register();
4613 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVWU, RC: &PPC::GPRCRegClass, Op0, Op1);
4614}
4615
4616Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4617 if (RetVT.SimpleTy != MVT::i64)
4618 return Register();
4619 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVDU, RC: &PPC::G8RCRegClass, Op0, Op1);
4620}
4621
4622Register fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4623 if (RetVT.SimpleTy != MVT::v4i32)
4624 return Register();
4625 if ((Subtarget->isISA3_1())) {
4626 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4627 }
4628 return Register();
4629}
4630
4631Register fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4632 if (RetVT.SimpleTy != MVT::v2i64)
4633 return Register();
4634 if ((Subtarget->isISA3_1())) {
4635 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVUD, RC: &PPC::VRRCRegClass, Op0, Op1);
4636 }
4637 return Register();
4638}
4639
4640Register fastEmit_ISD_UDIV_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
4641 if (RetVT.SimpleTy != MVT::v1i128)
4642 return Register();
4643 if ((Subtarget->isISA3_1())) {
4644 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVUQ, RC: &PPC::VRRCRegClass, Op0, Op1);
4645 }
4646 return Register();
4647}
4648
4649Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4650 switch (VT.SimpleTy) {
4651 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
4652 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
4653 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
4654 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
4655 case MVT::v1i128: return fastEmit_ISD_UDIV_MVT_v1i128_rr(RetVT, Op0, Op1);
4656 default: return Register();
4657 }
4658}
4659
4660// FastEmit functions for ISD::UMAX.
4661
4662Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4663 if (RetVT.SimpleTy != MVT::v16i8)
4664 return Register();
4665 if ((Subtarget->hasAltivec())) {
4666 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXUB, RC: &PPC::VRRCRegClass, Op0, Op1);
4667 }
4668 return Register();
4669}
4670
4671Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4672 if (RetVT.SimpleTy != MVT::v8i16)
4673 return Register();
4674 if ((Subtarget->hasAltivec())) {
4675 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXUH, RC: &PPC::VRRCRegClass, Op0, Op1);
4676 }
4677 return Register();
4678}
4679
4680Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4681 if (RetVT.SimpleTy != MVT::v4i32)
4682 return Register();
4683 if ((Subtarget->hasAltivec())) {
4684 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4685 }
4686 return Register();
4687}
4688
4689Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4690 switch (VT.SimpleTy) {
4691 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
4692 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
4693 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
4694 default: return Register();
4695 }
4696}
4697
4698// FastEmit functions for ISD::UMIN.
4699
4700Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4701 if (RetVT.SimpleTy != MVT::v16i8)
4702 return Register();
4703 if ((Subtarget->hasAltivec())) {
4704 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINUB, RC: &PPC::VRRCRegClass, Op0, Op1);
4705 }
4706 return Register();
4707}
4708
4709Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4710 if (RetVT.SimpleTy != MVT::v8i16)
4711 return Register();
4712 if ((Subtarget->hasAltivec())) {
4713 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINUH, RC: &PPC::VRRCRegClass, Op0, Op1);
4714 }
4715 return Register();
4716}
4717
4718Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4719 if (RetVT.SimpleTy != MVT::v4i32)
4720 return Register();
4721 if ((Subtarget->hasAltivec())) {
4722 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4723 }
4724 return Register();
4725}
4726
4727Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4728 switch (VT.SimpleTy) {
4729 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
4730 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
4731 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
4732 default: return Register();
4733 }
4734}
4735
4736// FastEmit functions for ISD::UREM.
4737
4738Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4739 if (RetVT.SimpleTy != MVT::i32)
4740 return Register();
4741 if ((Subtarget->isISA3_0())) {
4742 return fastEmitInst_rr(MachineInstOpcode: PPC::MODUW, RC: &PPC::GPRCRegClass, Op0, Op1);
4743 }
4744 return Register();
4745}
4746
4747Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4748 if (RetVT.SimpleTy != MVT::i64)
4749 return Register();
4750 if ((Subtarget->isISA3_0())) {
4751 return fastEmitInst_rr(MachineInstOpcode: PPC::MODUD, RC: &PPC::G8RCRegClass, Op0, Op1);
4752 }
4753 return Register();
4754}
4755
4756Register fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4757 if (RetVT.SimpleTy != MVT::v4i32)
4758 return Register();
4759 if ((Subtarget->isISA3_1())) {
4760 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4761 }
4762 return Register();
4763}
4764
4765Register fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4766 if (RetVT.SimpleTy != MVT::v2i64)
4767 return Register();
4768 if ((Subtarget->isISA3_1())) {
4769 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODUD, RC: &PPC::VRRCRegClass, Op0, Op1);
4770 }
4771 return Register();
4772}
4773
4774Register fastEmit_ISD_UREM_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
4775 if (RetVT.SimpleTy != MVT::v1i128)
4776 return Register();
4777 if ((Subtarget->isISA3_1())) {
4778 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODUQ, RC: &PPC::VRRCRegClass, Op0, Op1);
4779 }
4780 return Register();
4781}
4782
4783Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4784 switch (VT.SimpleTy) {
4785 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
4786 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
4787 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1);
4788 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1);
4789 case MVT::v1i128: return fastEmit_ISD_UREM_MVT_v1i128_rr(RetVT, Op0, Op1);
4790 default: return Register();
4791 }
4792}
4793
4794// FastEmit functions for ISD::USUBSAT.
4795
4796Register fastEmit_ISD_USUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4797 if (RetVT.SimpleTy != MVT::v16i8)
4798 return Register();
4799 if ((Subtarget->hasAltivec())) {
4800 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUBS, RC: &PPC::VRRCRegClass, Op0, Op1);
4801 }
4802 return Register();
4803}
4804
4805Register fastEmit_ISD_USUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4806 if (RetVT.SimpleTy != MVT::v8i16)
4807 return Register();
4808 if ((Subtarget->hasAltivec())) {
4809 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUHS, RC: &PPC::VRRCRegClass, Op0, Op1);
4810 }
4811 return Register();
4812}
4813
4814Register fastEmit_ISD_USUBSAT_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4815 if (RetVT.SimpleTy != MVT::v4i32)
4816 return Register();
4817 if ((Subtarget->hasAltivec())) {
4818 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUWS, RC: &PPC::VRRCRegClass, Op0, Op1);
4819 }
4820 return Register();
4821}
4822
4823Register fastEmit_ISD_USUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4824 switch (VT.SimpleTy) {
4825 case MVT::v16i8: return fastEmit_ISD_USUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
4826 case MVT::v8i16: return fastEmit_ISD_USUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
4827 case MVT::v4i32: return fastEmit_ISD_USUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
4828 default: return Register();
4829 }
4830}
4831
4832// FastEmit functions for ISD::XOR.
4833
4834Register fastEmit_ISD_XOR_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
4835 if (RetVT.SimpleTy != MVT::i1)
4836 return Register();
4837 return fastEmitInst_rr(MachineInstOpcode: PPC::CRXOR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
4838}
4839
4840Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4841 if (RetVT.SimpleTy != MVT::i32)
4842 return Register();
4843 return fastEmitInst_rr(MachineInstOpcode: PPC::XOR, RC: &PPC::GPRCRegClass, Op0, Op1);
4844}
4845
4846Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4847 if (RetVT.SimpleTy != MVT::i64)
4848 return Register();
4849 return fastEmitInst_rr(MachineInstOpcode: PPC::XOR8, RC: &PPC::G8RCRegClass, Op0, Op1);
4850}
4851
4852Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4853 if (RetVT.SimpleTy != MVT::v4i32)
4854 return Register();
4855 if ((Subtarget->hasVSX())) {
4856 return fastEmitInst_rr(MachineInstOpcode: PPC::XXLXOR, RC: &PPC::VSRCRegClass, Op0, Op1);
4857 }
4858 if ((Subtarget->hasAltivec())) {
4859 return fastEmitInst_rr(MachineInstOpcode: PPC::VXOR, RC: &PPC::VRRCRegClass, Op0, Op1);
4860 }
4861 return Register();
4862}
4863
4864Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4865 switch (VT.SimpleTy) {
4866 case MVT::i1: return fastEmit_ISD_XOR_MVT_i1_rr(RetVT, Op0, Op1);
4867 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
4868 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
4869 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
4870 default: return Register();
4871 }
4872}
4873
4874// FastEmit functions for PPCISD::ADD_TLS.
4875
4876Register fastEmit_PPCISD_ADD_TLS_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4877 if (RetVT.SimpleTy != MVT::i32)
4878 return Register();
4879 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD4TLS, RC: &PPC::GPRCRegClass, Op0, Op1);
4880}
4881
4882Register fastEmit_PPCISD_ADD_TLS_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4883 if (RetVT.SimpleTy != MVT::i64)
4884 return Register();
4885 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD8TLS, RC: &PPC::G8RCRegClass, Op0, Op1);
4886}
4887
4888Register fastEmit_PPCISD_ADD_TLS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4889 switch (VT.SimpleTy) {
4890 case MVT::i32: return fastEmit_PPCISD_ADD_TLS_MVT_i32_rr(RetVT, Op0, Op1);
4891 case MVT::i64: return fastEmit_PPCISD_ADD_TLS_MVT_i64_rr(RetVT, Op0, Op1);
4892 default: return Register();
4893 }
4894}
4895
4896// FastEmit functions for PPCISD::CMPB.
4897
4898Register fastEmit_PPCISD_CMPB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4899 if (RetVT.SimpleTy != MVT::i32)
4900 return Register();
4901 return fastEmitInst_rr(MachineInstOpcode: PPC::CMPB, RC: &PPC::GPRCRegClass, Op0, Op1);
4902}
4903
4904Register fastEmit_PPCISD_CMPB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4905 if (RetVT.SimpleTy != MVT::i64)
4906 return Register();
4907 return fastEmitInst_rr(MachineInstOpcode: PPC::CMPB8, RC: &PPC::G8RCRegClass, Op0, Op1);
4908}
4909
4910Register fastEmit_PPCISD_CMPB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4911 switch (VT.SimpleTy) {
4912 case MVT::i32: return fastEmit_PPCISD_CMPB_MVT_i32_rr(RetVT, Op0, Op1);
4913 case MVT::i64: return fastEmit_PPCISD_CMPB_MVT_i64_rr(RetVT, Op0, Op1);
4914 default: return Register();
4915 }
4916}
4917
4918// FastEmit functions for PPCISD::FADDRTZ.
4919
4920Register fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4921 if (RetVT.SimpleTy != MVT::f64)
4922 return Register();
4923 if ((Subtarget->hasFPU())) {
4924 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDrtz, RC: &PPC::F8RCRegClass, Op0, Op1);
4925 }
4926 return Register();
4927}
4928
4929Register fastEmit_PPCISD_FADDRTZ_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4930 switch (VT.SimpleTy) {
4931 case MVT::f64: return fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op1);
4932 default: return Register();
4933 }
4934}
4935
4936// FastEmit functions for PPCISD::GET_TLS_ADDR.
4937
4938Register fastEmit_PPCISD_GET_TLS_ADDR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4939 if (RetVT.SimpleTy != MVT::i32)
4940 return Register();
4941 return fastEmitInst_rr(MachineInstOpcode: PPC::GETtlsADDR32AIX, RC: &PPC::GPRCRegClass, Op0, Op1);
4942}
4943
4944Register fastEmit_PPCISD_GET_TLS_ADDR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4945 if (RetVT.SimpleTy != MVT::i64)
4946 return Register();
4947 return fastEmitInst_rr(MachineInstOpcode: PPC::GETtlsADDR64AIX, RC: &PPC::G8RCRegClass, Op0, Op1);
4948}
4949
4950Register fastEmit_PPCISD_GET_TLS_ADDR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4951 switch (VT.SimpleTy) {
4952 case MVT::i32: return fastEmit_PPCISD_GET_TLS_ADDR_MVT_i32_rr(RetVT, Op0, Op1);
4953 case MVT::i64: return fastEmit_PPCISD_GET_TLS_ADDR_MVT_i64_rr(RetVT, Op0, Op1);
4954 default: return Register();
4955 }
4956}
4957
4958// FastEmit functions for PPCISD::INST512.
4959
4960Register fastEmit_PPCISD_INST512_MVT_v256i1_rr(MVT RetVT, Register Op0, Register Op1) {
4961 if (RetVT.SimpleTy != MVT::v512i1)
4962 return Register();
4963 if ((Subtarget->isISAFuture()) && (Subtarget->hasMMA())) {
4964 return fastEmitInst_rr(MachineInstOpcode: PPC::DMXXINSTDMR512, RC: &PPC::WACCRCRegClass, Op0, Op1);
4965 }
4966 return Register();
4967}
4968
4969Register fastEmit_PPCISD_INST512_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4970 switch (VT.SimpleTy) {
4971 case MVT::v256i1: return fastEmit_PPCISD_INST512_MVT_v256i1_rr(RetVT, Op0, Op1);
4972 default: return Register();
4973 }
4974}
4975
4976// FastEmit functions for PPCISD::INST512HI.
4977
4978Register fastEmit_PPCISD_INST512HI_MVT_v256i1_rr(MVT RetVT, Register Op0, Register Op1) {
4979 if (RetVT.SimpleTy != MVT::v512i1)
4980 return Register();
4981 if ((Subtarget->isISAFuture()) && (Subtarget->hasMMA())) {
4982 return fastEmitInst_rr(MachineInstOpcode: PPC::DMXXINSTDMR512_HI, RC: &PPC::WACC_HIRCRegClass, Op0, Op1);
4983 }
4984 return Register();
4985}
4986
4987Register fastEmit_PPCISD_INST512HI_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4988 switch (VT.SimpleTy) {
4989 case MVT::v256i1: return fastEmit_PPCISD_INST512HI_MVT_v256i1_rr(RetVT, Op0, Op1);
4990 default: return Register();
4991 }
4992}
4993
4994// FastEmit functions for PPCISD::SHL.
4995
4996Register fastEmit_PPCISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4997 if (RetVT.SimpleTy != MVT::i32)
4998 return Register();
4999 return fastEmitInst_rr(MachineInstOpcode: PPC::SLW, RC: &PPC::GPRCRegClass, Op0, Op1);
5000}
5001
5002Register fastEmit_PPCISD_SHL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
5003 if (RetVT.SimpleTy != MVT::v16i8)
5004 return Register();
5005 if ((Subtarget->hasAltivec())) {
5006 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLB, RC: &PPC::VRRCRegClass, Op0, Op1);
5007 }
5008 return Register();
5009}
5010
5011Register fastEmit_PPCISD_SHL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
5012 if (RetVT.SimpleTy != MVT::v8i16)
5013 return Register();
5014 if ((Subtarget->hasAltivec())) {
5015 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLH, RC: &PPC::VRRCRegClass, Op0, Op1);
5016 }
5017 return Register();
5018}
5019
5020Register fastEmit_PPCISD_SHL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
5021 if (RetVT.SimpleTy != MVT::v4i32)
5022 return Register();
5023 if ((Subtarget->hasAltivec())) {
5024 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLW, RC: &PPC::VRRCRegClass, Op0, Op1);
5025 }
5026 return Register();
5027}
5028
5029Register fastEmit_PPCISD_SHL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
5030 if (RetVT.SimpleTy != MVT::v2i64)
5031 return Register();
5032 if ((Subtarget->hasP8Altivec())) {
5033 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLD, RC: &PPC::VRRCRegClass, Op0, Op1);
5034 }
5035 return Register();
5036}
5037
5038Register fastEmit_PPCISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5039 switch (VT.SimpleTy) {
5040 case MVT::i32: return fastEmit_PPCISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
5041 case MVT::v16i8: return fastEmit_PPCISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
5042 case MVT::v8i16: return fastEmit_PPCISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
5043 case MVT::v4i32: return fastEmit_PPCISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
5044 case MVT::v2i64: return fastEmit_PPCISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
5045 default: return Register();
5046 }
5047}
5048
5049// FastEmit functions for PPCISD::SRA.
5050
5051Register fastEmit_PPCISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
5052 if (RetVT.SimpleTy != MVT::i32)
5053 return Register();
5054 return fastEmitInst_rr(MachineInstOpcode: PPC::SRAW, RC: &PPC::GPRCRegClass, Op0, Op1);
5055}
5056
5057Register fastEmit_PPCISD_SRA_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
5058 if (RetVT.SimpleTy != MVT::v16i8)
5059 return Register();
5060 if ((Subtarget->hasAltivec())) {
5061 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAB, RC: &PPC::VRRCRegClass, Op0, Op1);
5062 }
5063 return Register();
5064}
5065
5066Register fastEmit_PPCISD_SRA_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
5067 if (RetVT.SimpleTy != MVT::v8i16)
5068 return Register();
5069 if ((Subtarget->hasAltivec())) {
5070 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAH, RC: &PPC::VRRCRegClass, Op0, Op1);
5071 }
5072 return Register();
5073}
5074
5075Register fastEmit_PPCISD_SRA_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
5076 if (RetVT.SimpleTy != MVT::v4i32)
5077 return Register();
5078 if ((Subtarget->hasAltivec())) {
5079 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAW, RC: &PPC::VRRCRegClass, Op0, Op1);
5080 }
5081 return Register();
5082}
5083
5084Register fastEmit_PPCISD_SRA_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
5085 if (RetVT.SimpleTy != MVT::v2i64)
5086 return Register();
5087 if ((Subtarget->hasP8Altivec())) {
5088 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAD, RC: &PPC::VRRCRegClass, Op0, Op1);
5089 }
5090 return Register();
5091}
5092
5093Register fastEmit_PPCISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5094 switch (VT.SimpleTy) {
5095 case MVT::i32: return fastEmit_PPCISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
5096 case MVT::v16i8: return fastEmit_PPCISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
5097 case MVT::v8i16: return fastEmit_PPCISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
5098 case MVT::v4i32: return fastEmit_PPCISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
5099 case MVT::v2i64: return fastEmit_PPCISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
5100 default: return Register();
5101 }
5102}
5103
5104// FastEmit functions for PPCISD::SRL.
5105
5106Register fastEmit_PPCISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
5107 if (RetVT.SimpleTy != MVT::i32)
5108 return Register();
5109 return fastEmitInst_rr(MachineInstOpcode: PPC::SRW, RC: &PPC::GPRCRegClass, Op0, Op1);
5110}
5111
5112Register fastEmit_PPCISD_SRL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
5113 if (RetVT.SimpleTy != MVT::v16i8)
5114 return Register();
5115 if ((Subtarget->hasAltivec())) {
5116 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRB, RC: &PPC::VRRCRegClass, Op0, Op1);
5117 }
5118 return Register();
5119}
5120
5121Register fastEmit_PPCISD_SRL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
5122 if (RetVT.SimpleTy != MVT::v8i16)
5123 return Register();
5124 if ((Subtarget->hasAltivec())) {
5125 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRH, RC: &PPC::VRRCRegClass, Op0, Op1);
5126 }
5127 return Register();
5128}
5129
5130Register fastEmit_PPCISD_SRL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
5131 if (RetVT.SimpleTy != MVT::v4i32)
5132 return Register();
5133 if ((Subtarget->hasAltivec())) {
5134 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRW, RC: &PPC::VRRCRegClass, Op0, Op1);
5135 }
5136 return Register();
5137}
5138
5139Register fastEmit_PPCISD_SRL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
5140 if (RetVT.SimpleTy != MVT::v2i64)
5141 return Register();
5142 if ((Subtarget->hasP8Altivec())) {
5143 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRD, RC: &PPC::VRRCRegClass, Op0, Op1);
5144 }
5145 return Register();
5146}
5147
5148Register fastEmit_PPCISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5149 switch (VT.SimpleTy) {
5150 case MVT::i32: return fastEmit_PPCISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
5151 case MVT::v16i8: return fastEmit_PPCISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
5152 case MVT::v8i16: return fastEmit_PPCISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
5153 case MVT::v4i32: return fastEmit_PPCISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
5154 case MVT::v2i64: return fastEmit_PPCISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
5155 default: return Register();
5156 }
5157}
5158
5159// FastEmit functions for PPCISD::STRICT_FADDRTZ.
5160
5161Register fastEmit_PPCISD_STRICT_FADDRTZ_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
5162 if (RetVT.SimpleTy != MVT::f64)
5163 return Register();
5164 if ((Subtarget->hasFPU())) {
5165 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDrtz, RC: &PPC::F8RCRegClass, Op0, Op1);
5166 }
5167 return Register();
5168}
5169
5170Register fastEmit_PPCISD_STRICT_FADDRTZ_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5171 switch (VT.SimpleTy) {
5172 case MVT::f64: return fastEmit_PPCISD_STRICT_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op1);
5173 default: return Register();
5174 }
5175}
5176
5177// FastEmit functions for PPCISD::TLSGD_AIX.
5178
5179Register fastEmit_PPCISD_TLSGD_AIX_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
5180 if (RetVT.SimpleTy != MVT::i32)
5181 return Register();
5182 return fastEmitInst_rr(MachineInstOpcode: PPC::TLSGDAIX, RC: &PPC::GPRCRegClass, Op0, Op1);
5183}
5184
5185Register fastEmit_PPCISD_TLSGD_AIX_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
5186 if (RetVT.SimpleTy != MVT::i64)
5187 return Register();
5188 return fastEmitInst_rr(MachineInstOpcode: PPC::TLSGDAIX8, RC: &PPC::G8RCRegClass, Op0, Op1);
5189}
5190
5191Register fastEmit_PPCISD_TLSGD_AIX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5192 switch (VT.SimpleTy) {
5193 case MVT::i32: return fastEmit_PPCISD_TLSGD_AIX_MVT_i32_rr(RetVT, Op0, Op1);
5194 case MVT::i64: return fastEmit_PPCISD_TLSGD_AIX_MVT_i64_rr(RetVT, Op0, Op1);
5195 default: return Register();
5196 }
5197}
5198
5199// FastEmit functions for PPCISD::VSRQ.
5200
5201Register fastEmit_PPCISD_VSRQ_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
5202 if (RetVT.SimpleTy != MVT::v4i32)
5203 return Register();
5204 if ((Subtarget->isISA3_1())) {
5205 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRQ, RC: &PPC::VRRCRegClass, Op0, Op1);
5206 }
5207 return Register();
5208}
5209
5210Register fastEmit_PPCISD_VSRQ_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5211 switch (VT.SimpleTy) {
5212 case MVT::v4i32: return fastEmit_PPCISD_VSRQ_MVT_v4i32_rr(RetVT, Op0, Op1);
5213 default: return Register();
5214 }
5215}
5216
5217// FastEmit functions for PPCISD::XSMAXC.
5218
5219Register fastEmit_PPCISD_XSMAXC_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
5220 if (RetVT.SimpleTy != MVT::f64)
5221 return Register();
5222 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
5223 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXCDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
5224 }
5225 return Register();
5226}
5227
5228Register fastEmit_PPCISD_XSMAXC_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
5229 if (RetVT.SimpleTy != MVT::f128)
5230 return Register();
5231 if ((Subtarget->hasVSX()) && (Subtarget->isISA3_1())) {
5232 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXCQP, RC: &PPC::VRRCRegClass, Op0, Op1);
5233 }
5234 return Register();
5235}
5236
5237Register fastEmit_PPCISD_XSMAXC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5238 switch (VT.SimpleTy) {
5239 case MVT::f64: return fastEmit_PPCISD_XSMAXC_MVT_f64_rr(RetVT, Op0, Op1);
5240 case MVT::f128: return fastEmit_PPCISD_XSMAXC_MVT_f128_rr(RetVT, Op0, Op1);
5241 default: return Register();
5242 }
5243}
5244
5245// FastEmit functions for PPCISD::XSMINC.
5246
5247Register fastEmit_PPCISD_XSMINC_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
5248 if (RetVT.SimpleTy != MVT::f64)
5249 return Register();
5250 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
5251 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINCDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
5252 }
5253 return Register();
5254}
5255
5256Register fastEmit_PPCISD_XSMINC_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
5257 if (RetVT.SimpleTy != MVT::f128)
5258 return Register();
5259 if ((Subtarget->hasVSX()) && (Subtarget->isISA3_1())) {
5260 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINCQP, RC: &PPC::VRRCRegClass, Op0, Op1);
5261 }
5262 return Register();
5263}
5264
5265Register fastEmit_PPCISD_XSMINC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5266 switch (VT.SimpleTy) {
5267 case MVT::f64: return fastEmit_PPCISD_XSMINC_MVT_f64_rr(RetVT, Op0, Op1);
5268 case MVT::f128: return fastEmit_PPCISD_XSMINC_MVT_f128_rr(RetVT, Op0, Op1);
5269 default: return Register();
5270 }
5271}
5272
5273// Top-level FastEmit function.
5274
5275Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
5276 switch (Opcode) {
5277 case ISD::ABDU: return fastEmit_ISD_ABDU_rr(VT, RetVT, Op0, Op1);
5278 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
5279 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
5280 case ISD::AVGCEILS: return fastEmit_ISD_AVGCEILS_rr(VT, RetVT, Op0, Op1);
5281 case ISD::AVGCEILU: return fastEmit_ISD_AVGCEILU_rr(VT, RetVT, Op0, Op1);
5282 case ISD::BUILD_VECTOR: return fastEmit_ISD_BUILD_VECTOR_rr(VT, RetVT, Op0, Op1);
5283 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
5284 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
5285 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1);
5286 case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1);
5287 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1);
5288 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1);
5289 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
5290 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
5291 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
5292 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1);
5293 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1);
5294 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
5295 case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op1);
5296 case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op1);
5297 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
5298 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
5299 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
5300 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
5301 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
5302 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
5303 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
5304 case ISD::SSUBSAT: return fastEmit_ISD_SSUBSAT_rr(VT, RetVT, Op0, Op1);
5305 case ISD::STRICT_FADD: return fastEmit_ISD_STRICT_FADD_rr(VT, RetVT, Op0, Op1);
5306 case ISD::STRICT_FDIV: return fastEmit_ISD_STRICT_FDIV_rr(VT, RetVT, Op0, Op1);
5307 case ISD::STRICT_FMAXNUM: return fastEmit_ISD_STRICT_FMAXNUM_rr(VT, RetVT, Op0, Op1);
5308 case ISD::STRICT_FMINNUM: return fastEmit_ISD_STRICT_FMINNUM_rr(VT, RetVT, Op0, Op1);
5309 case ISD::STRICT_FMUL: return fastEmit_ISD_STRICT_FMUL_rr(VT, RetVT, Op0, Op1);
5310 case ISD::STRICT_FSUB: return fastEmit_ISD_STRICT_FSUB_rr(VT, RetVT, Op0, Op1);
5311 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
5312 case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op1);
5313 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
5314 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
5315 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
5316 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
5317 case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op1);
5318 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
5319 case PPCISD::ADD_TLS: return fastEmit_PPCISD_ADD_TLS_rr(VT, RetVT, Op0, Op1);
5320 case PPCISD::CMPB: return fastEmit_PPCISD_CMPB_rr(VT, RetVT, Op0, Op1);
5321 case PPCISD::FADDRTZ: return fastEmit_PPCISD_FADDRTZ_rr(VT, RetVT, Op0, Op1);
5322 case PPCISD::GET_TLS_ADDR: return fastEmit_PPCISD_GET_TLS_ADDR_rr(VT, RetVT, Op0, Op1);
5323 case PPCISD::INST512: return fastEmit_PPCISD_INST512_rr(VT, RetVT, Op0, Op1);
5324 case PPCISD::INST512HI: return fastEmit_PPCISD_INST512HI_rr(VT, RetVT, Op0, Op1);
5325 case PPCISD::SHL: return fastEmit_PPCISD_SHL_rr(VT, RetVT, Op0, Op1);
5326 case PPCISD::SRA: return fastEmit_PPCISD_SRA_rr(VT, RetVT, Op0, Op1);
5327 case PPCISD::SRL: return fastEmit_PPCISD_SRL_rr(VT, RetVT, Op0, Op1);
5328 case PPCISD::STRICT_FADDRTZ: return fastEmit_PPCISD_STRICT_FADDRTZ_rr(VT, RetVT, Op0, Op1);
5329 case PPCISD::TLSGD_AIX: return fastEmit_PPCISD_TLSGD_AIX_rr(VT, RetVT, Op0, Op1);
5330 case PPCISD::VSRQ: return fastEmit_PPCISD_VSRQ_rr(VT, RetVT, Op0, Op1);
5331 case PPCISD::XSMAXC: return fastEmit_PPCISD_XSMAXC_rr(VT, RetVT, Op0, Op1);
5332 case PPCISD::XSMINC: return fastEmit_PPCISD_XSMINC_rr(VT, RetVT, Op0, Op1);
5333 default: return Register();
5334 }
5335}
5336
5337// FastEmit functions for ISD::SRA.
5338
5339Register fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, Register Op0, uint64_t imm1) {
5340 if (RetVT.SimpleTy != MVT::i32)
5341 return Register();
5342 return fastEmitInst_ri(MachineInstOpcode: PPC::SRAWI, RC: &PPC::GPRCRegClass, Op0, Imm: imm1);
5343}
5344
5345Register fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, Register Op0, uint64_t imm1) {
5346 if (RetVT.SimpleTy != MVT::i64)
5347 return Register();
5348 return fastEmitInst_ri(MachineInstOpcode: PPC::SRADI, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5349}
5350
5351Register fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5352 switch (VT.SimpleTy) {
5353 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, imm1);
5354 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, imm1);
5355 default: return Register();
5356 }
5357}
5358
5359// FastEmit functions for PPCISD::EXTSWSLI.
5360
5361Register fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(MVT RetVT, Register Op0, uint64_t imm1) {
5362 if (RetVT.SimpleTy != MVT::i64)
5363 return Register();
5364 if ((Subtarget->isISA3_0())) {
5365 return fastEmitInst_ri(MachineInstOpcode: PPC::EXTSWSLI_32_64, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5366 }
5367 return Register();
5368}
5369
5370Register fastEmit_PPCISD_EXTSWSLI_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5371 switch (VT.SimpleTy) {
5372 case MVT::i32: return fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(RetVT, Op0, imm1);
5373 default: return Register();
5374 }
5375}
5376
5377// Top-level FastEmit function.
5378
5379Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) override {
5380 if (VT == MVT::i32 && Predicate_imm32SExt16(Imm: imm1))
5381 if (Register Reg = fastEmit_ri_Predicate_imm32SExt16(VT, RetVT, Opcode, Op0, imm1))
5382 return Reg;
5383
5384 if (VT == MVT::i64 && Predicate_imm64SExt16(Imm: imm1))
5385 if (Register Reg = fastEmit_ri_Predicate_imm64SExt16(VT, RetVT, Opcode, Op0, imm1))
5386 return Reg;
5387
5388 switch (Opcode) {
5389 case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, imm1);
5390 case PPCISD::EXTSWSLI: return fastEmit_PPCISD_EXTSWSLI_ri(VT, RetVT, Op0, imm1);
5391 default: return Register();
5392 }
5393}
5394
5395// FastEmit functions for ISD::ADD.
5396
5397Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5398 if (RetVT.SimpleTy != MVT::i32)
5399 return Register();
5400 return fastEmitInst_ri(MachineInstOpcode: PPC::ADDI, RC: &PPC::GPRCRegClass, Op0, Imm: imm1);
5401}
5402
5403Register fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5404 switch (VT.SimpleTy) {
5405 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1);
5406 default: return Register();
5407 }
5408}
5409
5410// FastEmit functions for ISD::MUL.
5411
5412Register fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5413 if (RetVT.SimpleTy != MVT::i32)
5414 return Register();
5415 return fastEmitInst_ri(MachineInstOpcode: PPC::MULLI, RC: &PPC::GPRCRegClass, Op0, Imm: imm1);
5416}
5417
5418Register fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5419 switch (VT.SimpleTy) {
5420 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1);
5421 default: return Register();
5422 }
5423}
5424
5425// FastEmit functions for PPCISD::XXSPLT.
5426
5427Register fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5428 if (RetVT.SimpleTy != MVT::v4i32)
5429 return Register();
5430 if ((Subtarget->hasVSX())) {
5431 return fastEmitInst_ri(MachineInstOpcode: PPC::XXSPLTW, RC: &PPC::VSRCRegClass, Op0, Imm: imm1);
5432 }
5433 return Register();
5434}
5435
5436Register fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5437 switch (VT.SimpleTy) {
5438 case MVT::v4i32: return fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1);
5439 default: return Register();
5440 }
5441}
5442
5443// Top-level FastEmit function.
5444
5445Register fastEmit_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
5446 switch (Opcode) {
5447 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1);
5448 case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1);
5449 case PPCISD::XXSPLT: return fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1);
5450 default: return Register();
5451 }
5452}
5453
5454// FastEmit functions for ISD::ADD.
5455
5456Register fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5457 if (RetVT.SimpleTy != MVT::i64)
5458 return Register();
5459 return fastEmitInst_ri(MachineInstOpcode: PPC::ADDI8, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5460}
5461
5462Register fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5463 switch (VT.SimpleTy) {
5464 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1);
5465 default: return Register();
5466 }
5467}
5468
5469// FastEmit functions for ISD::MUL.
5470
5471Register fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5472 if (RetVT.SimpleTy != MVT::i64)
5473 return Register();
5474 return fastEmitInst_ri(MachineInstOpcode: PPC::MULLI8, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5475}
5476
5477Register fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5478 switch (VT.SimpleTy) {
5479 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1);
5480 default: return Register();
5481 }
5482}
5483
5484// Top-level FastEmit function.
5485
5486Register fastEmit_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
5487 switch (Opcode) {
5488 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1);
5489 case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1);
5490 default: return Register();
5491 }
5492}
5493
5494