1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the PPC target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_imm32SExt16(int64_t Imm) {
12
13 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
14 // sign extended field. Used by instructions like 'addi'.
15 return (int32_t)Imm == (short)Imm;
16
17}
18static bool Predicate_imm64SExt16(int64_t Imm) {
19
20 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
21 // sign extended field. Used by instructions like 'addi'.
22 return (int64_t)Imm == (short)Imm;
23
24}
25static bool Predicate_immSExt5NonZero(int64_t Imm) {
26 return Imm && isInt<5>(x: Imm);
27}
28static bool Predicate_i32immNonAllOneNonZero(int64_t Imm) {
29 return Imm && (Imm != -1);
30}
31
32
33// FastEmit functions for ISD::READCYCLECOUNTER.
34
35Register fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) {
36 if (RetVT.SimpleTy != MVT::i64)
37 return Register();
38 return fastEmitInst_(MachineInstOpcode: PPC::MFTB8, RC: &PPC::G8RCRegClass);
39}
40
41Register fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) {
42 switch (VT.SimpleTy) {
43 case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT);
44 default: return Register();
45 }
46}
47
48// FastEmit functions for PPCISD::GET_TPOINTER.
49
50Register fastEmit_PPCISD_GET_TPOINTER_MVT_i32_(MVT RetVT) {
51 if (RetVT.SimpleTy != MVT::i32)
52 return Register();
53 return fastEmitInst_(MachineInstOpcode: PPC::GETtlsTpointer32AIX, RC: &PPC::GPRCRegClass);
54}
55
56Register fastEmit_PPCISD_GET_TPOINTER_(MVT VT, MVT RetVT) {
57 switch (VT.SimpleTy) {
58 case MVT::i32: return fastEmit_PPCISD_GET_TPOINTER_MVT_i32_(RetVT);
59 default: return Register();
60 }
61}
62
63// FastEmit functions for PPCISD::MFFS.
64
65Register fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) {
66 if (RetVT.SimpleTy != MVT::f64)
67 return Register();
68 if ((Subtarget->hasFPU())) {
69 return fastEmitInst_(MachineInstOpcode: PPC::MFFS, RC: &PPC::F8RCRegClass);
70 }
71 return Register();
72}
73
74Register fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) {
75 switch (VT.SimpleTy) {
76 case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT);
77 default: return Register();
78 }
79}
80
81// FastEmit functions for PPCISD::PPC32_GOT.
82
83Register fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) {
84 if (RetVT.SimpleTy != MVT::i32)
85 return Register();
86 return fastEmitInst_(MachineInstOpcode: PPC::PPC32GOT, RC: &PPC::GPRCRegClass);
87}
88
89Register fastEmit_PPCISD_PPC32_GOT_(MVT VT, MVT RetVT) {
90 switch (VT.SimpleTy) {
91 case MVT::i32: return fastEmit_PPCISD_PPC32_GOT_MVT_i32_(RetVT);
92 default: return Register();
93 }
94}
95
96// Top-level FastEmit function.
97
98Register fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override {
99 switch (Opcode) {
100 case ISD::READCYCLECOUNTER: return fastEmit_ISD_READCYCLECOUNTER_(VT, RetVT);
101 case PPCISD::GET_TPOINTER: return fastEmit_PPCISD_GET_TPOINTER_(VT, RetVT);
102 case PPCISD::MFFS: return fastEmit_PPCISD_MFFS_(VT, RetVT);
103 case PPCISD::PPC32_GOT: return fastEmit_PPCISD_PPC32_GOT_(VT, RetVT);
104 default: return Register();
105 }
106}
107
108// FastEmit functions for ISD::ANY_EXTEND.
109
110Register fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(Register Op0) {
111 if ((Subtarget->isISA3_1())) {
112 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC, RC: &PPC::GPRCRegClass, Op0);
113 }
114 return Register();
115}
116
117Register fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(Register Op0) {
118 if ((Subtarget->isISA3_1())) {
119 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC8, RC: &PPC::G8RCRegClass, Op0);
120 }
121 return Register();
122}
123
124Register fastEmit_ISD_ANY_EXTEND_MVT_i1_r(MVT RetVT, Register Op0) {
125switch (RetVT.SimpleTy) {
126 case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(Op0);
127 case MVT::i64: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(Op0);
128 default: return Register();
129}
130}
131
132Register fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
133 switch (VT.SimpleTy) {
134 case MVT::i1: return fastEmit_ISD_ANY_EXTEND_MVT_i1_r(RetVT, Op0);
135 default: return Register();
136 }
137}
138
139// FastEmit functions for ISD::BITCAST.
140
141Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
142 if (RetVT.SimpleTy != MVT::f64)
143 return Register();
144 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
145 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRD, RC: &PPC::VSFRCRegClass, Op0);
146 }
147 return Register();
148}
149
150Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
151 if (RetVT.SimpleTy != MVT::i64)
152 return Register();
153 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
154 return fastEmitInst_r(MachineInstOpcode: PPC::MFVSRD, RC: &PPC::G8RCRegClass, Op0);
155 }
156 return Register();
157}
158
159Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
160 switch (VT.SimpleTy) {
161 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
162 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
163 default: return Register();
164 }
165}
166
167// FastEmit functions for ISD::BSWAP.
168
169Register fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, Register Op0) {
170 if (RetVT.SimpleTy != MVT::i32)
171 return Register();
172 if ((Subtarget->isISA3_1())) {
173 return fastEmitInst_r(MachineInstOpcode: PPC::BRW, RC: &PPC::GPRCRegClass, Op0);
174 }
175 return Register();
176}
177
178Register fastEmit_ISD_BSWAP_MVT_i64_r(MVT RetVT, Register Op0) {
179 if (RetVT.SimpleTy != MVT::i64)
180 return Register();
181 if ((Subtarget->isISA3_1())) {
182 return fastEmitInst_r(MachineInstOpcode: PPC::BRD, RC: &PPC::G8RCRegClass, Op0);
183 }
184 return Register();
185}
186
187Register fastEmit_ISD_BSWAP_MVT_v4i32_r(MVT RetVT, Register Op0) {
188 if (RetVT.SimpleTy != MVT::v4i32)
189 return Register();
190 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
191 return fastEmitInst_r(MachineInstOpcode: PPC::XXBRW, RC: &PPC::VSRCRegClass, Op0);
192 }
193 return Register();
194}
195
196Register fastEmit_ISD_BSWAP_MVT_v2i64_r(MVT RetVT, Register Op0) {
197 if (RetVT.SimpleTy != MVT::v2i64)
198 return Register();
199 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
200 return fastEmitInst_r(MachineInstOpcode: PPC::XXBRD, RC: &PPC::VSRCRegClass, Op0);
201 }
202 return Register();
203}
204
205Register fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, Register Op0) {
206 switch (VT.SimpleTy) {
207 case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0);
208 case MVT::i64: return fastEmit_ISD_BSWAP_MVT_i64_r(RetVT, Op0);
209 case MVT::v4i32: return fastEmit_ISD_BSWAP_MVT_v4i32_r(RetVT, Op0);
210 case MVT::v2i64: return fastEmit_ISD_BSWAP_MVT_v2i64_r(RetVT, Op0);
211 default: return Register();
212 }
213}
214
215// FastEmit functions for ISD::CTLZ.
216
217Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
218 if (RetVT.SimpleTy != MVT::i32)
219 return Register();
220 return fastEmitInst_r(MachineInstOpcode: PPC::CNTLZW, RC: &PPC::GPRCRegClass, Op0);
221}
222
223Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
224 if (RetVT.SimpleTy != MVT::i64)
225 return Register();
226 return fastEmitInst_r(MachineInstOpcode: PPC::CNTLZD, RC: &PPC::G8RCRegClass, Op0);
227}
228
229Register fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, Register Op0) {
230 if (RetVT.SimpleTy != MVT::v16i8)
231 return Register();
232 if ((Subtarget->hasP8Altivec())) {
233 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZB, RC: &PPC::VRRCRegClass, Op0);
234 }
235 return Register();
236}
237
238Register fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, Register Op0) {
239 if (RetVT.SimpleTy != MVT::v8i16)
240 return Register();
241 if ((Subtarget->hasP8Altivec())) {
242 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZH, RC: &PPC::VRRCRegClass, Op0);
243 }
244 return Register();
245}
246
247Register fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, Register Op0) {
248 if (RetVT.SimpleTy != MVT::v4i32)
249 return Register();
250 if ((Subtarget->hasP8Altivec())) {
251 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZW, RC: &PPC::VRRCRegClass, Op0);
252 }
253 return Register();
254}
255
256Register fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, Register Op0) {
257 if (RetVT.SimpleTy != MVT::v2i64)
258 return Register();
259 if ((Subtarget->hasP8Altivec())) {
260 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZD, RC: &PPC::VRRCRegClass, Op0);
261 }
262 return Register();
263}
264
265Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
266 switch (VT.SimpleTy) {
267 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
268 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
269 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0);
270 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0);
271 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0);
272 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0);
273 default: return Register();
274 }
275}
276
277// FastEmit functions for ISD::CTPOP.
278
279Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
280 if (RetVT.SimpleTy != MVT::i32)
281 return Register();
282 return fastEmitInst_r(MachineInstOpcode: PPC::POPCNTW, RC: &PPC::GPRCRegClass, Op0);
283}
284
285Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
286 if (RetVT.SimpleTy != MVT::i64)
287 return Register();
288 return fastEmitInst_r(MachineInstOpcode: PPC::POPCNTD, RC: &PPC::G8RCRegClass, Op0);
289}
290
291Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
292 if (RetVT.SimpleTy != MVT::v16i8)
293 return Register();
294 if ((Subtarget->hasP8Altivec())) {
295 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTB, RC: &PPC::VRRCRegClass, Op0);
296 }
297 return Register();
298}
299
300Register fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, Register Op0) {
301 if (RetVT.SimpleTy != MVT::v8i16)
302 return Register();
303 if ((Subtarget->hasP8Altivec())) {
304 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTH, RC: &PPC::VRRCRegClass, Op0);
305 }
306 return Register();
307}
308
309Register fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, Register Op0) {
310 if (RetVT.SimpleTy != MVT::v4i32)
311 return Register();
312 if ((Subtarget->hasP8Altivec())) {
313 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTW, RC: &PPC::VRRCRegClass, Op0);
314 }
315 return Register();
316}
317
318Register fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, Register Op0) {
319 if (RetVT.SimpleTy != MVT::v2i64)
320 return Register();
321 if ((Subtarget->hasP8Altivec())) {
322 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTD, RC: &PPC::VRRCRegClass, Op0);
323 }
324 return Register();
325}
326
327Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
328 switch (VT.SimpleTy) {
329 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
330 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
331 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
332 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0);
333 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0);
334 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0);
335 default: return Register();
336 }
337}
338
339// FastEmit functions for ISD::CTTZ.
340
341Register fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, Register Op0) {
342 if (RetVT.SimpleTy != MVT::i32)
343 return Register();
344 if ((Subtarget->isISA3_0())) {
345 return fastEmitInst_r(MachineInstOpcode: PPC::CNTTZW, RC: &PPC::GPRCRegClass, Op0);
346 }
347 return Register();
348}
349
350Register fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, Register Op0) {
351 if (RetVT.SimpleTy != MVT::i64)
352 return Register();
353 if ((Subtarget->isISA3_0())) {
354 return fastEmitInst_r(MachineInstOpcode: PPC::CNTTZD, RC: &PPC::G8RCRegClass, Op0);
355 }
356 return Register();
357}
358
359Register fastEmit_ISD_CTTZ_MVT_v16i8_r(MVT RetVT, Register Op0) {
360 if (RetVT.SimpleTy != MVT::v16i8)
361 return Register();
362 if ((Subtarget->hasP9Altivec())) {
363 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZB, RC: &PPC::VRRCRegClass, Op0);
364 }
365 return Register();
366}
367
368Register fastEmit_ISD_CTTZ_MVT_v8i16_r(MVT RetVT, Register Op0) {
369 if (RetVT.SimpleTy != MVT::v8i16)
370 return Register();
371 if ((Subtarget->hasP9Altivec())) {
372 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZH, RC: &PPC::VRRCRegClass, Op0);
373 }
374 return Register();
375}
376
377Register fastEmit_ISD_CTTZ_MVT_v4i32_r(MVT RetVT, Register Op0) {
378 if (RetVT.SimpleTy != MVT::v4i32)
379 return Register();
380 if ((Subtarget->hasP9Altivec())) {
381 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZW, RC: &PPC::VRRCRegClass, Op0);
382 }
383 return Register();
384}
385
386Register fastEmit_ISD_CTTZ_MVT_v2i64_r(MVT RetVT, Register Op0) {
387 if (RetVT.SimpleTy != MVT::v2i64)
388 return Register();
389 if ((Subtarget->hasP9Altivec())) {
390 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZD, RC: &PPC::VRRCRegClass, Op0);
391 }
392 return Register();
393}
394
395Register fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, Register Op0) {
396 switch (VT.SimpleTy) {
397 case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0);
398 case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0);
399 case MVT::v16i8: return fastEmit_ISD_CTTZ_MVT_v16i8_r(RetVT, Op0);
400 case MVT::v8i16: return fastEmit_ISD_CTTZ_MVT_v8i16_r(RetVT, Op0);
401 case MVT::v4i32: return fastEmit_ISD_CTTZ_MVT_v4i32_r(RetVT, Op0);
402 case MVT::v2i64: return fastEmit_ISD_CTTZ_MVT_v2i64_r(RetVT, Op0);
403 default: return Register();
404 }
405}
406
407// FastEmit functions for ISD::FABS.
408
409Register fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, Register Op0) {
410 if (RetVT.SimpleTy != MVT::f32)
411 return Register();
412 if ((Subtarget->hasSPE())) {
413 return fastEmitInst_r(MachineInstOpcode: PPC::EFSABS, RC: &PPC::GPRCRegClass, Op0);
414 }
415 if ((Subtarget->hasFPU())) {
416 return fastEmitInst_r(MachineInstOpcode: PPC::FABSS, RC: &PPC::F4RCRegClass, Op0);
417 }
418 return Register();
419}
420
421Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
422 if (RetVT.SimpleTy != MVT::f64)
423 return Register();
424 if ((Subtarget->hasVSX())) {
425 return fastEmitInst_r(MachineInstOpcode: PPC::XSABSDP, RC: &PPC::VSFRCRegClass, Op0);
426 }
427 if ((Subtarget->hasSPE())) {
428 return fastEmitInst_r(MachineInstOpcode: PPC::EFDABS, RC: &PPC::SPERCRegClass, Op0);
429 }
430 if ((Subtarget->hasFPU())) {
431 return fastEmitInst_r(MachineInstOpcode: PPC::FABSD, RC: &PPC::F8RCRegClass, Op0);
432 }
433 return Register();
434}
435
436Register fastEmit_ISD_FABS_MVT_f128_r(MVT RetVT, Register Op0) {
437 if (RetVT.SimpleTy != MVT::f128)
438 return Register();
439 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
440 return fastEmitInst_r(MachineInstOpcode: PPC::XSABSQP, RC: &PPC::VRRCRegClass, Op0);
441 }
442 return Register();
443}
444
445Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
446 if (RetVT.SimpleTy != MVT::v4f32)
447 return Register();
448 if ((Subtarget->hasVSX())) {
449 return fastEmitInst_r(MachineInstOpcode: PPC::XVABSSP, RC: &PPC::VSRCRegClass, Op0);
450 }
451 return Register();
452}
453
454Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
455 if (RetVT.SimpleTy != MVT::v2f64)
456 return Register();
457 if ((Subtarget->hasVSX())) {
458 return fastEmitInst_r(MachineInstOpcode: PPC::XVABSDP, RC: &PPC::VSRCRegClass, Op0);
459 }
460 return Register();
461}
462
463Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
464 switch (VT.SimpleTy) {
465 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
466 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
467 case MVT::f128: return fastEmit_ISD_FABS_MVT_f128_r(RetVT, Op0);
468 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
469 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
470 default: return Register();
471 }
472}
473
474// FastEmit functions for ISD::FCEIL.
475
476Register fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, Register Op0) {
477 if (RetVT.SimpleTy != MVT::f32)
478 return Register();
479 if ((Subtarget->hasFPU())) {
480 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPS, RC: &PPC::F4RCRegClass, Op0);
481 }
482 return Register();
483}
484
485Register fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, Register Op0) {
486 if (RetVT.SimpleTy != MVT::f64)
487 return Register();
488 if ((Subtarget->hasVSX())) {
489 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIP, RC: &PPC::VSFRCRegClass, Op0);
490 }
491 if ((Subtarget->hasFPU())) {
492 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPD, RC: &PPC::F8RCRegClass, Op0);
493 }
494 return Register();
495}
496
497Register fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, Register Op0) {
498 if (RetVT.SimpleTy != MVT::v4f32)
499 return Register();
500 if ((Subtarget->hasVSX())) {
501 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIP, RC: &PPC::VSRCRegClass, Op0);
502 }
503 if ((Subtarget->hasAltivec())) {
504 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIP, RC: &PPC::VRRCRegClass, Op0);
505 }
506 return Register();
507}
508
509Register fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, Register Op0) {
510 if (RetVT.SimpleTy != MVT::v2f64)
511 return Register();
512 if ((Subtarget->hasVSX())) {
513 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIP, RC: &PPC::VSRCRegClass, Op0);
514 }
515 return Register();
516}
517
518Register fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, Register Op0) {
519 switch (VT.SimpleTy) {
520 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0);
521 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0);
522 case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0);
523 case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0);
524 default: return Register();
525 }
526}
527
528// FastEmit functions for ISD::FFLOOR.
529
530Register fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, Register Op0) {
531 if (RetVT.SimpleTy != MVT::f32)
532 return Register();
533 if ((Subtarget->hasFPU())) {
534 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMS, RC: &PPC::F4RCRegClass, Op0);
535 }
536 return Register();
537}
538
539Register fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, Register Op0) {
540 if (RetVT.SimpleTy != MVT::f64)
541 return Register();
542 if ((Subtarget->hasVSX())) {
543 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIM, RC: &PPC::VSFRCRegClass, Op0);
544 }
545 if ((Subtarget->hasFPU())) {
546 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMD, RC: &PPC::F8RCRegClass, Op0);
547 }
548 return Register();
549}
550
551Register fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, Register Op0) {
552 if (RetVT.SimpleTy != MVT::v4f32)
553 return Register();
554 if ((Subtarget->hasVSX())) {
555 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIM, RC: &PPC::VSRCRegClass, Op0);
556 }
557 if ((Subtarget->hasAltivec())) {
558 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIM, RC: &PPC::VRRCRegClass, Op0);
559 }
560 return Register();
561}
562
563Register fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, Register Op0) {
564 if (RetVT.SimpleTy != MVT::v2f64)
565 return Register();
566 if ((Subtarget->hasVSX())) {
567 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIM, RC: &PPC::VSRCRegClass, Op0);
568 }
569 return Register();
570}
571
572Register fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, Register Op0) {
573 switch (VT.SimpleTy) {
574 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0);
575 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0);
576 case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0);
577 case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0);
578 default: return Register();
579 }
580}
581
582// FastEmit functions for ISD::FNEARBYINT.
583
584Register fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
585 if (RetVT.SimpleTy != MVT::v4f32)
586 return Register();
587 if ((Subtarget->hasAltivec())) {
588 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIN, RC: &PPC::VRRCRegClass, Op0);
589 }
590 return Register();
591}
592
593Register fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, Register Op0) {
594 switch (VT.SimpleTy) {
595 case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0);
596 default: return Register();
597 }
598}
599
600// FastEmit functions for ISD::FNEG.
601
602Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
603 if (RetVT.SimpleTy != MVT::f32)
604 return Register();
605 if ((Subtarget->hasSPE())) {
606 return fastEmitInst_r(MachineInstOpcode: PPC::EFSNEG, RC: &PPC::GPRCRegClass, Op0);
607 }
608 if ((Subtarget->hasFPU())) {
609 return fastEmitInst_r(MachineInstOpcode: PPC::FNEGS, RC: &PPC::F4RCRegClass, Op0);
610 }
611 return Register();
612}
613
614Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
615 if (RetVT.SimpleTy != MVT::f64)
616 return Register();
617 if ((Subtarget->hasVSX())) {
618 return fastEmitInst_r(MachineInstOpcode: PPC::XSNEGDP, RC: &PPC::VSFRCRegClass, Op0);
619 }
620 if ((Subtarget->hasSPE())) {
621 return fastEmitInst_r(MachineInstOpcode: PPC::EFDNEG, RC: &PPC::SPERCRegClass, Op0);
622 }
623 if ((Subtarget->hasFPU())) {
624 return fastEmitInst_r(MachineInstOpcode: PPC::FNEGD, RC: &PPC::F8RCRegClass, Op0);
625 }
626 return Register();
627}
628
629Register fastEmit_ISD_FNEG_MVT_f128_r(MVT RetVT, Register Op0) {
630 if (RetVT.SimpleTy != MVT::f128)
631 return Register();
632 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
633 return fastEmitInst_r(MachineInstOpcode: PPC::XSNEGQP, RC: &PPC::VRRCRegClass, Op0);
634 }
635 return Register();
636}
637
638Register fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, Register Op0) {
639 if (RetVT.SimpleTy != MVT::v4f32)
640 return Register();
641 if ((Subtarget->hasVSX())) {
642 return fastEmitInst_r(MachineInstOpcode: PPC::XVNEGSP, RC: &PPC::VSRCRegClass, Op0);
643 }
644 return Register();
645}
646
647Register fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, Register Op0) {
648 if (RetVT.SimpleTy != MVT::v2f64)
649 return Register();
650 if ((Subtarget->hasVSX())) {
651 return fastEmitInst_r(MachineInstOpcode: PPC::XVNEGDP, RC: &PPC::VSRCRegClass, Op0);
652 }
653 return Register();
654}
655
656Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
657 switch (VT.SimpleTy) {
658 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
659 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
660 case MVT::f128: return fastEmit_ISD_FNEG_MVT_f128_r(RetVT, Op0);
661 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0);
662 case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0);
663 default: return Register();
664 }
665}
666
667// FastEmit functions for ISD::FP_EXTEND.
668
669Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
670 if (RetVT.SimpleTy != MVT::f64)
671 return Register();
672 if ((Subtarget->hasSPE())) {
673 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFS, RC: &PPC::SPERCRegClass, Op0);
674 }
675 return Register();
676}
677
678Register fastEmit_ISD_FP_EXTEND_MVT_f64_r(MVT RetVT, Register Op0) {
679 if (RetVT.SimpleTy != MVT::f128)
680 return Register();
681 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
682 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPQP, RC: &PPC::VRRCRegClass, Op0);
683 }
684 return Register();
685}
686
687Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
688 switch (VT.SimpleTy) {
689 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
690 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f64_r(RetVT, Op0);
691 default: return Register();
692 }
693}
694
695// FastEmit functions for ISD::FP_ROUND.
696
697Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
698 if (RetVT.SimpleTy != MVT::f32)
699 return Register();
700 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
701 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSP, RC: &PPC::VSSRCRegClass, Op0);
702 }
703 if ((Subtarget->hasSPE())) {
704 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFD, RC: &PPC::GPRCRegClass, Op0);
705 }
706 if ((Subtarget->hasFPU())) {
707 return fastEmitInst_r(MachineInstOpcode: PPC::FRSP, RC: &PPC::F4RCRegClass, Op0);
708 }
709 return Register();
710}
711
712Register fastEmit_ISD_FP_ROUND_MVT_f128_r(MVT RetVT, Register Op0) {
713 if (RetVT.SimpleTy != MVT::f64)
714 return Register();
715 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
716 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPDP, RC: &PPC::VFRCRegClass, Op0);
717 }
718 return Register();
719}
720
721Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
722 switch (VT.SimpleTy) {
723 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
724 case MVT::f128: return fastEmit_ISD_FP_ROUND_MVT_f128_r(RetVT, Op0);
725 default: return Register();
726 }
727}
728
729// FastEmit functions for ISD::FP_TO_SINT.
730
731Register fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, Register Op0) {
732 if (RetVT.SimpleTy != MVT::i32)
733 return Register();
734 if ((Subtarget->hasSPE())) {
735 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTSIZ, RC: &PPC::GPRCRegClass, Op0);
736 }
737 return Register();
738}
739
740Register fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, Register Op0) {
741 if (RetVT.SimpleTy != MVT::i32)
742 return Register();
743 if ((Subtarget->hasSPE())) {
744 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTSIZ, RC: &PPC::GPRCRegClass, Op0);
745 }
746 return Register();
747}
748
749Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
750 if (RetVT.SimpleTy != MVT::v4i32)
751 return Register();
752 if ((Subtarget->hasVSX())) {
753 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPSXWS, RC: &PPC::VSRCRegClass, Op0);
754 }
755 if ((Subtarget->hasAltivec())) {
756 return fastEmitInst_r(MachineInstOpcode: PPC::VCTSXS_0, RC: &PPC::VRRCRegClass, Op0);
757 }
758 return Register();
759}
760
761Register fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
762 if (RetVT.SimpleTy != MVT::v2i64)
763 return Register();
764 if ((Subtarget->hasVSX())) {
765 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPSXDS, RC: &PPC::VSRCRegClass, Op0);
766 }
767 return Register();
768}
769
770Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
771 switch (VT.SimpleTy) {
772 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
773 case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
774 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
775 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
776 default: return Register();
777 }
778}
779
780// FastEmit functions for ISD::FP_TO_UINT.
781
782Register fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, Register Op0) {
783 if (RetVT.SimpleTy != MVT::i32)
784 return Register();
785 if ((Subtarget->hasSPE())) {
786 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTUIZ, RC: &PPC::GPRCRegClass, Op0);
787 }
788 return Register();
789}
790
791Register fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, Register Op0) {
792 if (RetVT.SimpleTy != MVT::i32)
793 return Register();
794 if ((Subtarget->hasSPE())) {
795 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTUIZ, RC: &PPC::GPRCRegClass, Op0);
796 }
797 return Register();
798}
799
800Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
801 if (RetVT.SimpleTy != MVT::v4i32)
802 return Register();
803 if ((Subtarget->hasVSX())) {
804 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPUXWS, RC: &PPC::VSRCRegClass, Op0);
805 }
806 if ((Subtarget->hasAltivec())) {
807 return fastEmitInst_r(MachineInstOpcode: PPC::VCTUXS_0, RC: &PPC::VRRCRegClass, Op0);
808 }
809 return Register();
810}
811
812Register fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
813 if (RetVT.SimpleTy != MVT::v2i64)
814 return Register();
815 if ((Subtarget->hasVSX())) {
816 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPUXDS, RC: &PPC::VSRCRegClass, Op0);
817 }
818 return Register();
819}
820
821Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
822 switch (VT.SimpleTy) {
823 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
824 case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
825 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
826 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
827 default: return Register();
828 }
829}
830
831// FastEmit functions for ISD::FRINT.
832
833Register fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, Register Op0) {
834 if (RetVT.SimpleTy != MVT::f64)
835 return Register();
836 if ((Subtarget->hasVSX())) {
837 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIC, RC: &PPC::VSFRCRegClass, Op0);
838 }
839 return Register();
840}
841
842Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
843 if (RetVT.SimpleTy != MVT::v4f32)
844 return Register();
845 if ((Subtarget->hasVSX())) {
846 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIC, RC: &PPC::VSRCRegClass, Op0);
847 }
848 return Register();
849}
850
851Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
852 if (RetVT.SimpleTy != MVT::v2f64)
853 return Register();
854 if ((Subtarget->hasVSX())) {
855 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIC, RC: &PPC::VSRCRegClass, Op0);
856 }
857 return Register();
858}
859
860Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
861 switch (VT.SimpleTy) {
862 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0);
863 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
864 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
865 default: return Register();
866 }
867}
868
869// FastEmit functions for ISD::FROUND.
870
871Register fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, Register Op0) {
872 if (RetVT.SimpleTy != MVT::f32)
873 return Register();
874 if ((Subtarget->hasFPU())) {
875 return fastEmitInst_r(MachineInstOpcode: PPC::FRINS, RC: &PPC::F4RCRegClass, Op0);
876 }
877 return Register();
878}
879
880Register fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, Register Op0) {
881 if (RetVT.SimpleTy != MVT::f64)
882 return Register();
883 if ((Subtarget->hasVSX())) {
884 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPI, RC: &PPC::VSFRCRegClass, Op0);
885 }
886 if ((Subtarget->hasFPU())) {
887 return fastEmitInst_r(MachineInstOpcode: PPC::FRIND, RC: &PPC::F8RCRegClass, Op0);
888 }
889 return Register();
890}
891
892Register fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, Register Op0) {
893 if (RetVT.SimpleTy != MVT::v4f32)
894 return Register();
895 if ((Subtarget->hasVSX())) {
896 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPI, RC: &PPC::VSRCRegClass, Op0);
897 }
898 return Register();
899}
900
901Register fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, Register Op0) {
902 if (RetVT.SimpleTy != MVT::v2f64)
903 return Register();
904 if ((Subtarget->hasVSX())) {
905 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPI, RC: &PPC::VSRCRegClass, Op0);
906 }
907 return Register();
908}
909
910Register fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, Register Op0) {
911 switch (VT.SimpleTy) {
912 case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0);
913 case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0);
914 case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0);
915 case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0);
916 default: return Register();
917 }
918}
919
920// FastEmit functions for ISD::FSQRT.
921
922Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
923 if (RetVT.SimpleTy != MVT::f32)
924 return Register();
925 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
926 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTSP, RC: &PPC::VSSRCRegClass, Op0);
927 }
928 if ((Subtarget->hasFPU())) {
929 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRTS, RC: &PPC::F4RCRegClass, Op0);
930 }
931 return Register();
932}
933
934Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
935 if (RetVT.SimpleTy != MVT::f64)
936 return Register();
937 if ((Subtarget->hasVSX())) {
938 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTDP, RC: &PPC::VSFRCRegClass, Op0);
939 }
940 if ((Subtarget->hasFPU())) {
941 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRT, RC: &PPC::F8RCRegClass, Op0);
942 }
943 return Register();
944}
945
946Register fastEmit_ISD_FSQRT_MVT_f128_r(MVT RetVT, Register Op0) {
947 if (RetVT.SimpleTy != MVT::f128)
948 return Register();
949 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
950 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTQP, RC: &PPC::VRRCRegClass, Op0);
951 }
952 return Register();
953}
954
955Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
956 if (RetVT.SimpleTy != MVT::v4f32)
957 return Register();
958 if ((Subtarget->hasVSX())) {
959 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTSP, RC: &PPC::VSRCRegClass, Op0);
960 }
961 return Register();
962}
963
964Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
965 if (RetVT.SimpleTy != MVT::v2f64)
966 return Register();
967 if ((Subtarget->hasVSX())) {
968 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTDP, RC: &PPC::VSRCRegClass, Op0);
969 }
970 return Register();
971}
972
973Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
974 switch (VT.SimpleTy) {
975 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
976 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
977 case MVT::f128: return fastEmit_ISD_FSQRT_MVT_f128_r(RetVT, Op0);
978 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
979 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
980 default: return Register();
981 }
982}
983
984// FastEmit functions for ISD::FTRUNC.
985
986Register fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, Register Op0) {
987 if (RetVT.SimpleTy != MVT::f32)
988 return Register();
989 if ((Subtarget->hasFPU())) {
990 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZS, RC: &PPC::F4RCRegClass, Op0);
991 }
992 return Register();
993}
994
995Register fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, Register Op0) {
996 if (RetVT.SimpleTy != MVT::f64)
997 return Register();
998 if ((Subtarget->hasVSX())) {
999 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIZ, RC: &PPC::VSFRCRegClass, Op0);
1000 }
1001 if ((Subtarget->hasFPU())) {
1002 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZD, RC: &PPC::F8RCRegClass, Op0);
1003 }
1004 return Register();
1005}
1006
1007Register fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, Register Op0) {
1008 if (RetVT.SimpleTy != MVT::v4f32)
1009 return Register();
1010 if ((Subtarget->hasVSX())) {
1011 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIZ, RC: &PPC::VSRCRegClass, Op0);
1012 }
1013 if ((Subtarget->hasAltivec())) {
1014 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIZ, RC: &PPC::VRRCRegClass, Op0);
1015 }
1016 return Register();
1017}
1018
1019Register fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, Register Op0) {
1020 if (RetVT.SimpleTy != MVT::v2f64)
1021 return Register();
1022 if ((Subtarget->hasVSX())) {
1023 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIZ, RC: &PPC::VSRCRegClass, Op0);
1024 }
1025 return Register();
1026}
1027
1028Register fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, Register Op0) {
1029 switch (VT.SimpleTy) {
1030 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0);
1031 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0);
1032 case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0);
1033 case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0);
1034 default: return Register();
1035 }
1036}
1037
1038// FastEmit functions for ISD::SCALAR_TO_VECTOR.
1039
1040Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, Register Op0) {
1041 if (RetVT.SimpleTy != MVT::v4i32)
1042 return Register();
1043 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1044 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRWS, RC: &PPC::VSRCRegClass, Op0);
1045 }
1046 return Register();
1047}
1048
1049Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, Register Op0) {
1050 if (RetVT.SimpleTy != MVT::v4f32)
1051 return Register();
1052 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) {
1053 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSPN, RC: &PPC::VSRCRegClass, Op0);
1054 }
1055 return Register();
1056}
1057
1058Register fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, Register Op0) {
1059 switch (VT.SimpleTy) {
1060 case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0);
1061 case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0);
1062 default: return Register();
1063 }
1064}
1065
1066// FastEmit functions for ISD::SIGN_EXTEND.
1067
1068Register fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(Register Op0) {
1069 if ((Subtarget->isISA3_1())) {
1070 return fastEmitInst_r(MachineInstOpcode: PPC::SETNBC, RC: &PPC::GPRCRegClass, Op0);
1071 }
1072 return Register();
1073}
1074
1075Register fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(Register Op0) {
1076 if ((Subtarget->isISA3_1())) {
1077 return fastEmitInst_r(MachineInstOpcode: PPC::SETNBC8, RC: &PPC::G8RCRegClass, Op0);
1078 }
1079 return Register();
1080}
1081
1082Register fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(MVT RetVT, Register Op0) {
1083switch (RetVT.SimpleTy) {
1084 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(Op0);
1085 case MVT::i64: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(Op0);
1086 default: return Register();
1087}
1088}
1089
1090Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
1091 if (RetVT.SimpleTy != MVT::i64)
1092 return Register();
1093 return fastEmitInst_r(MachineInstOpcode: PPC::EXTSW_32_64, RC: &PPC::G8RCRegClass, Op0);
1094}
1095
1096Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
1097 switch (VT.SimpleTy) {
1098 case MVT::i1: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(RetVT, Op0);
1099 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
1100 default: return Register();
1101 }
1102}
1103
1104// FastEmit functions for ISD::SINT_TO_FP.
1105
1106Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1107 if ((Subtarget->hasSPE())) {
1108 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFSI, RC: &PPC::GPRCRegClass, Op0);
1109 }
1110 return Register();
1111}
1112
1113Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1114 if ((Subtarget->hasSPE())) {
1115 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFSI, RC: &PPC::SPERCRegClass, Op0);
1116 }
1117 return Register();
1118}
1119
1120Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1121switch (RetVT.SimpleTy) {
1122 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1123 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1124 default: return Register();
1125}
1126}
1127
1128Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1129 if (RetVT.SimpleTy != MVT::v4f32)
1130 return Register();
1131 if ((Subtarget->hasVSX())) {
1132 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXWSP, RC: &PPC::VSRCRegClass, Op0);
1133 }
1134 if ((Subtarget->hasAltivec())) {
1135 return fastEmitInst_r(MachineInstOpcode: PPC::VCFSX_0, RC: &PPC::VRRCRegClass, Op0);
1136 }
1137 return Register();
1138}
1139
1140Register fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
1141 if (RetVT.SimpleTy != MVT::v2f64)
1142 return Register();
1143 if ((Subtarget->hasVSX())) {
1144 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXDDP, RC: &PPC::VSRCRegClass, Op0);
1145 }
1146 return Register();
1147}
1148
1149Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1150 switch (VT.SimpleTy) {
1151 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
1152 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1153 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1154 default: return Register();
1155 }
1156}
1157
1158// FastEmit functions for ISD::STRICT_FCEIL.
1159
1160Register fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(MVT RetVT, Register Op0) {
1161 if (RetVT.SimpleTy != MVT::f32)
1162 return Register();
1163 if ((Subtarget->hasFPU())) {
1164 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPS, RC: &PPC::F4RCRegClass, Op0);
1165 }
1166 return Register();
1167}
1168
1169Register fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(MVT RetVT, Register Op0) {
1170 if (RetVT.SimpleTy != MVT::f64)
1171 return Register();
1172 if ((Subtarget->hasVSX())) {
1173 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIP, RC: &PPC::VSFRCRegClass, Op0);
1174 }
1175 if ((Subtarget->hasFPU())) {
1176 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPD, RC: &PPC::F8RCRegClass, Op0);
1177 }
1178 return Register();
1179}
1180
1181Register fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(MVT RetVT, Register Op0) {
1182 if (RetVT.SimpleTy != MVT::v4f32)
1183 return Register();
1184 if ((Subtarget->hasVSX())) {
1185 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIP, RC: &PPC::VSRCRegClass, Op0);
1186 }
1187 return Register();
1188}
1189
1190Register fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(MVT RetVT, Register Op0) {
1191 if (RetVT.SimpleTy != MVT::v2f64)
1192 return Register();
1193 if ((Subtarget->hasVSX())) {
1194 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIP, RC: &PPC::VSRCRegClass, Op0);
1195 }
1196 return Register();
1197}
1198
1199Register fastEmit_ISD_STRICT_FCEIL_r(MVT VT, MVT RetVT, Register Op0) {
1200 switch (VT.SimpleTy) {
1201 case MVT::f32: return fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(RetVT, Op0);
1202 case MVT::f64: return fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(RetVT, Op0);
1203 case MVT::v4f32: return fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(RetVT, Op0);
1204 case MVT::v2f64: return fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(RetVT, Op0);
1205 default: return Register();
1206 }
1207}
1208
1209// FastEmit functions for ISD::STRICT_FFLOOR.
1210
1211Register fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(MVT RetVT, Register Op0) {
1212 if (RetVT.SimpleTy != MVT::f32)
1213 return Register();
1214 if ((Subtarget->hasFPU())) {
1215 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMS, RC: &PPC::F4RCRegClass, Op0);
1216 }
1217 return Register();
1218}
1219
1220Register fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(MVT RetVT, Register Op0) {
1221 if (RetVT.SimpleTy != MVT::f64)
1222 return Register();
1223 if ((Subtarget->hasVSX())) {
1224 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIM, RC: &PPC::VSFRCRegClass, Op0);
1225 }
1226 if ((Subtarget->hasFPU())) {
1227 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMD, RC: &PPC::F8RCRegClass, Op0);
1228 }
1229 return Register();
1230}
1231
1232Register fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(MVT RetVT, Register Op0) {
1233 if (RetVT.SimpleTy != MVT::v4f32)
1234 return Register();
1235 if ((Subtarget->hasVSX())) {
1236 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIM, RC: &PPC::VSRCRegClass, Op0);
1237 }
1238 return Register();
1239}
1240
1241Register fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(MVT RetVT, Register Op0) {
1242 if (RetVT.SimpleTy != MVT::v2f64)
1243 return Register();
1244 if ((Subtarget->hasVSX())) {
1245 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIM, RC: &PPC::VSRCRegClass, Op0);
1246 }
1247 return Register();
1248}
1249
1250Register fastEmit_ISD_STRICT_FFLOOR_r(MVT VT, MVT RetVT, Register Op0) {
1251 switch (VT.SimpleTy) {
1252 case MVT::f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(RetVT, Op0);
1253 case MVT::f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(RetVT, Op0);
1254 case MVT::v4f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(RetVT, Op0);
1255 case MVT::v2f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(RetVT, Op0);
1256 default: return Register();
1257 }
1258}
1259
1260// FastEmit functions for ISD::STRICT_FNEARBYINT.
1261
1262Register fastEmit_ISD_STRICT_FNEARBYINT_MVT_f64_r(MVT RetVT, Register Op0) {
1263 if (RetVT.SimpleTy != MVT::f64)
1264 return Register();
1265 if ((Subtarget->hasVSX())) {
1266 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIC, RC: &PPC::VSFRCRegClass, Op0);
1267 }
1268 return Register();
1269}
1270
1271Register fastEmit_ISD_STRICT_FNEARBYINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1272 if (RetVT.SimpleTy != MVT::v4f32)
1273 return Register();
1274 if ((Subtarget->hasVSX())) {
1275 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIC, RC: &PPC::VSRCRegClass, Op0);
1276 }
1277 return Register();
1278}
1279
1280Register fastEmit_ISD_STRICT_FNEARBYINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1281 if (RetVT.SimpleTy != MVT::v2f64)
1282 return Register();
1283 if ((Subtarget->hasVSX())) {
1284 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIC, RC: &PPC::VSRCRegClass, Op0);
1285 }
1286 return Register();
1287}
1288
1289Register fastEmit_ISD_STRICT_FNEARBYINT_r(MVT VT, MVT RetVT, Register Op0) {
1290 switch (VT.SimpleTy) {
1291 case MVT::f64: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_f64_r(RetVT, Op0);
1292 case MVT::v4f32: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_v4f32_r(RetVT, Op0);
1293 case MVT::v2f64: return fastEmit_ISD_STRICT_FNEARBYINT_MVT_v2f64_r(RetVT, Op0);
1294 default: return Register();
1295 }
1296}
1297
1298// FastEmit functions for ISD::STRICT_FP_EXTEND.
1299
1300Register fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
1301 if (RetVT.SimpleTy != MVT::f64)
1302 return Register();
1303 if ((Subtarget->hasSPE())) {
1304 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFS, RC: &PPC::SPERCRegClass, Op0);
1305 }
1306 return Register();
1307}
1308
1309Register fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(MVT RetVT, Register Op0) {
1310 if (RetVT.SimpleTy != MVT::f128)
1311 return Register();
1312 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1313 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPQP, RC: &PPC::VRRCRegClass, Op0);
1314 }
1315 return Register();
1316}
1317
1318Register fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
1319 switch (VT.SimpleTy) {
1320 case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0);
1321 case MVT::f64: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(RetVT, Op0);
1322 default: return Register();
1323 }
1324}
1325
1326// FastEmit functions for ISD::STRICT_FP_ROUND.
1327
1328Register fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
1329 if (RetVT.SimpleTy != MVT::f32)
1330 return Register();
1331 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1332 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSP, RC: &PPC::VSSRCRegClass, Op0);
1333 }
1334 if ((Subtarget->hasSPE())) {
1335 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFD, RC: &PPC::GPRCRegClass, Op0);
1336 }
1337 if ((Subtarget->hasFPU())) {
1338 return fastEmitInst_r(MachineInstOpcode: PPC::FRSP, RC: &PPC::F4RCRegClass, Op0);
1339 }
1340 return Register();
1341}
1342
1343Register fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(MVT RetVT, Register Op0) {
1344 if (RetVT.SimpleTy != MVT::f64)
1345 return Register();
1346 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1347 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPDP, RC: &PPC::VFRCRegClass, Op0);
1348 }
1349 return Register();
1350}
1351
1352Register fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
1353 switch (VT.SimpleTy) {
1354 case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0);
1355 case MVT::f128: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(RetVT, Op0);
1356 default: return Register();
1357 }
1358}
1359
1360// FastEmit functions for ISD::STRICT_FP_TO_SINT.
1361
1362Register fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(MVT RetVT, Register Op0) {
1363 if (RetVT.SimpleTy != MVT::i32)
1364 return Register();
1365 if ((Subtarget->hasSPE())) {
1366 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTSIZ, RC: &PPC::GPRCRegClass, Op0);
1367 }
1368 return Register();
1369}
1370
1371Register fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(MVT RetVT, Register Op0) {
1372 if (RetVT.SimpleTy != MVT::i32)
1373 return Register();
1374 if ((Subtarget->hasSPE())) {
1375 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTSIZ, RC: &PPC::GPRCRegClass, Op0);
1376 }
1377 return Register();
1378}
1379
1380Register fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1381 if (RetVT.SimpleTy != MVT::v4i32)
1382 return Register();
1383 if ((Subtarget->hasVSX())) {
1384 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPSXWS, RC: &PPC::VSRCRegClass, Op0);
1385 }
1386 return Register();
1387}
1388
1389Register fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1390 if (RetVT.SimpleTy != MVT::v2i64)
1391 return Register();
1392 if ((Subtarget->hasVSX())) {
1393 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPSXDS, RC: &PPC::VSRCRegClass, Op0);
1394 }
1395 return Register();
1396}
1397
1398Register fastEmit_ISD_STRICT_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
1399 switch (VT.SimpleTy) {
1400 case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
1401 case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
1402 case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
1403 case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
1404 default: return Register();
1405 }
1406}
1407
1408// FastEmit functions for ISD::STRICT_FP_TO_UINT.
1409
1410Register fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(MVT RetVT, Register Op0) {
1411 if (RetVT.SimpleTy != MVT::i32)
1412 return Register();
1413 if ((Subtarget->hasSPE())) {
1414 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTUIZ, RC: &PPC::GPRCRegClass, Op0);
1415 }
1416 return Register();
1417}
1418
1419Register fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(MVT RetVT, Register Op0) {
1420 if (RetVT.SimpleTy != MVT::i32)
1421 return Register();
1422 if ((Subtarget->hasSPE())) {
1423 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTUIZ, RC: &PPC::GPRCRegClass, Op0);
1424 }
1425 return Register();
1426}
1427
1428Register fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1429 if (RetVT.SimpleTy != MVT::v4i32)
1430 return Register();
1431 if ((Subtarget->hasVSX())) {
1432 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPUXWS, RC: &PPC::VSRCRegClass, Op0);
1433 }
1434 return Register();
1435}
1436
1437Register fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1438 if (RetVT.SimpleTy != MVT::v2i64)
1439 return Register();
1440 if ((Subtarget->hasVSX())) {
1441 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPUXDS, RC: &PPC::VSRCRegClass, Op0);
1442 }
1443 return Register();
1444}
1445
1446Register fastEmit_ISD_STRICT_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
1447 switch (VT.SimpleTy) {
1448 case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
1449 case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
1450 case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
1451 case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
1452 default: return Register();
1453 }
1454}
1455
1456// FastEmit functions for ISD::STRICT_FRINT.
1457
1458Register fastEmit_ISD_STRICT_FRINT_MVT_f64_r(MVT RetVT, Register Op0) {
1459 if (RetVT.SimpleTy != MVT::f64)
1460 return Register();
1461 if ((Subtarget->hasVSX())) {
1462 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIC, RC: &PPC::VSFRCRegClass, Op0);
1463 }
1464 return Register();
1465}
1466
1467Register fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1468 if (RetVT.SimpleTy != MVT::v4f32)
1469 return Register();
1470 if ((Subtarget->hasVSX())) {
1471 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIC, RC: &PPC::VSRCRegClass, Op0);
1472 }
1473 return Register();
1474}
1475
1476Register fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1477 if (RetVT.SimpleTy != MVT::v2f64)
1478 return Register();
1479 if ((Subtarget->hasVSX())) {
1480 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIC, RC: &PPC::VSRCRegClass, Op0);
1481 }
1482 return Register();
1483}
1484
1485Register fastEmit_ISD_STRICT_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
1486 switch (VT.SimpleTy) {
1487 case MVT::f64: return fastEmit_ISD_STRICT_FRINT_MVT_f64_r(RetVT, Op0);
1488 case MVT::v4f32: return fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(RetVT, Op0);
1489 case MVT::v2f64: return fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(RetVT, Op0);
1490 default: return Register();
1491 }
1492}
1493
1494// FastEmit functions for ISD::STRICT_FROUND.
1495
1496Register fastEmit_ISD_STRICT_FROUND_MVT_f32_r(MVT RetVT, Register Op0) {
1497 if (RetVT.SimpleTy != MVT::f32)
1498 return Register();
1499 if ((Subtarget->hasFPU())) {
1500 return fastEmitInst_r(MachineInstOpcode: PPC::FRINS, RC: &PPC::F4RCRegClass, Op0);
1501 }
1502 return Register();
1503}
1504
1505Register fastEmit_ISD_STRICT_FROUND_MVT_f64_r(MVT RetVT, Register Op0) {
1506 if (RetVT.SimpleTy != MVT::f64)
1507 return Register();
1508 if ((Subtarget->hasVSX())) {
1509 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPI, RC: &PPC::VSFRCRegClass, Op0);
1510 }
1511 if ((Subtarget->hasFPU())) {
1512 return fastEmitInst_r(MachineInstOpcode: PPC::FRIND, RC: &PPC::F8RCRegClass, Op0);
1513 }
1514 return Register();
1515}
1516
1517Register fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(MVT RetVT, Register Op0) {
1518 if (RetVT.SimpleTy != MVT::v4f32)
1519 return Register();
1520 if ((Subtarget->hasVSX())) {
1521 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPI, RC: &PPC::VSRCRegClass, Op0);
1522 }
1523 return Register();
1524}
1525
1526Register fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(MVT RetVT, Register Op0) {
1527 if (RetVT.SimpleTy != MVT::v2f64)
1528 return Register();
1529 if ((Subtarget->hasVSX())) {
1530 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPI, RC: &PPC::VSRCRegClass, Op0);
1531 }
1532 return Register();
1533}
1534
1535Register fastEmit_ISD_STRICT_FROUND_r(MVT VT, MVT RetVT, Register Op0) {
1536 switch (VT.SimpleTy) {
1537 case MVT::f32: return fastEmit_ISD_STRICT_FROUND_MVT_f32_r(RetVT, Op0);
1538 case MVT::f64: return fastEmit_ISD_STRICT_FROUND_MVT_f64_r(RetVT, Op0);
1539 case MVT::v4f32: return fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(RetVT, Op0);
1540 case MVT::v2f64: return fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(RetVT, Op0);
1541 default: return Register();
1542 }
1543}
1544
1545// FastEmit functions for ISD::STRICT_FSQRT.
1546
1547Register fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
1548 if (RetVT.SimpleTy != MVT::f32)
1549 return Register();
1550 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1551 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTSP, RC: &PPC::VSSRCRegClass, Op0);
1552 }
1553 if ((Subtarget->hasFPU())) {
1554 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRTS, RC: &PPC::F4RCRegClass, Op0);
1555 }
1556 return Register();
1557}
1558
1559Register fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
1560 if (RetVT.SimpleTy != MVT::f64)
1561 return Register();
1562 if ((Subtarget->hasVSX())) {
1563 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTDP, RC: &PPC::VSFRCRegClass, Op0);
1564 }
1565 if ((Subtarget->hasFPU())) {
1566 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRT, RC: &PPC::F8RCRegClass, Op0);
1567 }
1568 return Register();
1569}
1570
1571Register fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(MVT RetVT, Register Op0) {
1572 if (RetVT.SimpleTy != MVT::f128)
1573 return Register();
1574 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1575 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTQP, RC: &PPC::VRRCRegClass, Op0);
1576 }
1577 return Register();
1578}
1579
1580Register fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1581 if (RetVT.SimpleTy != MVT::v4f32)
1582 return Register();
1583 if ((Subtarget->hasVSX())) {
1584 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTSP, RC: &PPC::VSRCRegClass, Op0);
1585 }
1586 return Register();
1587}
1588
1589Register fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1590 if (RetVT.SimpleTy != MVT::v2f64)
1591 return Register();
1592 if ((Subtarget->hasVSX())) {
1593 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTDP, RC: &PPC::VSRCRegClass, Op0);
1594 }
1595 return Register();
1596}
1597
1598Register fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
1599 switch (VT.SimpleTy) {
1600 case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0);
1601 case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0);
1602 case MVT::f128: return fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(RetVT, Op0);
1603 case MVT::v4f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(RetVT, Op0);
1604 case MVT::v2f64: return fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(RetVT, Op0);
1605 default: return Register();
1606 }
1607}
1608
1609// FastEmit functions for ISD::STRICT_FTRUNC.
1610
1611Register fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(MVT RetVT, Register Op0) {
1612 if (RetVT.SimpleTy != MVT::f32)
1613 return Register();
1614 if ((Subtarget->hasFPU())) {
1615 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZS, RC: &PPC::F4RCRegClass, Op0);
1616 }
1617 return Register();
1618}
1619
1620Register fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(MVT RetVT, Register Op0) {
1621 if (RetVT.SimpleTy != MVT::f64)
1622 return Register();
1623 if ((Subtarget->hasVSX())) {
1624 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIZ, RC: &PPC::VSFRCRegClass, Op0);
1625 }
1626 if ((Subtarget->hasFPU())) {
1627 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZD, RC: &PPC::F8RCRegClass, Op0);
1628 }
1629 return Register();
1630}
1631
1632Register fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(MVT RetVT, Register Op0) {
1633 if (RetVT.SimpleTy != MVT::v4f32)
1634 return Register();
1635 if ((Subtarget->hasVSX())) {
1636 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIZ, RC: &PPC::VSRCRegClass, Op0);
1637 }
1638 return Register();
1639}
1640
1641Register fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(MVT RetVT, Register Op0) {
1642 if (RetVT.SimpleTy != MVT::v2f64)
1643 return Register();
1644 if ((Subtarget->hasVSX())) {
1645 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIZ, RC: &PPC::VSRCRegClass, Op0);
1646 }
1647 return Register();
1648}
1649
1650Register fastEmit_ISD_STRICT_FTRUNC_r(MVT VT, MVT RetVT, Register Op0) {
1651 switch (VT.SimpleTy) {
1652 case MVT::f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(RetVT, Op0);
1653 case MVT::f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(RetVT, Op0);
1654 case MVT::v4f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(RetVT, Op0);
1655 case MVT::v2f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(RetVT, Op0);
1656 default: return Register();
1657 }
1658}
1659
1660// FastEmit functions for ISD::STRICT_SINT_TO_FP.
1661
1662Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1663 if ((Subtarget->hasSPE())) {
1664 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFSI, RC: &PPC::GPRCRegClass, Op0);
1665 }
1666 return Register();
1667}
1668
1669Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1670 if ((Subtarget->hasSPE())) {
1671 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFSI, RC: &PPC::SPERCRegClass, Op0);
1672 }
1673 return Register();
1674}
1675
1676Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1677switch (RetVT.SimpleTy) {
1678 case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1679 case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1680 default: return Register();
1681}
1682}
1683
1684Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1685 if (RetVT.SimpleTy != MVT::v4f32)
1686 return Register();
1687 if ((Subtarget->hasVSX())) {
1688 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXWSP, RC: &PPC::VSRCRegClass, Op0);
1689 }
1690 return Register();
1691}
1692
1693Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
1694 if (RetVT.SimpleTy != MVT::v2f64)
1695 return Register();
1696 if ((Subtarget->hasVSX())) {
1697 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXDDP, RC: &PPC::VSRCRegClass, Op0);
1698 }
1699 return Register();
1700}
1701
1702Register fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1703 switch (VT.SimpleTy) {
1704 case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
1705 case MVT::v4i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1706 case MVT::v2i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1707 default: return Register();
1708 }
1709}
1710
1711// FastEmit functions for ISD::STRICT_UINT_TO_FP.
1712
1713Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1714 if ((Subtarget->hasSPE())) {
1715 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFUI, RC: &PPC::GPRCRegClass, Op0);
1716 }
1717 return Register();
1718}
1719
1720Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1721 if ((Subtarget->hasSPE())) {
1722 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFUI, RC: &PPC::SPERCRegClass, Op0);
1723 }
1724 return Register();
1725}
1726
1727Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1728switch (RetVT.SimpleTy) {
1729 case MVT::f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1730 case MVT::f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1731 default: return Register();
1732}
1733}
1734
1735Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1736 if (RetVT.SimpleTy != MVT::v4f32)
1737 return Register();
1738 if ((Subtarget->hasVSX())) {
1739 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXWSP, RC: &PPC::VSRCRegClass, Op0);
1740 }
1741 return Register();
1742}
1743
1744Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
1745 if (RetVT.SimpleTy != MVT::v2f64)
1746 return Register();
1747 if ((Subtarget->hasVSX())) {
1748 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXDDP, RC: &PPC::VSRCRegClass, Op0);
1749 }
1750 return Register();
1751}
1752
1753Register fastEmit_ISD_STRICT_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1754 switch (VT.SimpleTy) {
1755 case MVT::i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1756 case MVT::v4i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1757 case MVT::v2i64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1758 default: return Register();
1759 }
1760}
1761
1762// FastEmit functions for ISD::TRUNCATE.
1763
1764Register fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, Register Op0) {
1765 if (RetVT.SimpleTy != MVT::i1)
1766 return Register();
1767 return fastEmitInst_r(MachineInstOpcode: PPC::ANDI_rec_1_GT_BIT, RC: &PPC::CRBITRCRegClass, Op0);
1768}
1769
1770Register fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, Register Op0) {
1771 if (RetVT.SimpleTy != MVT::i1)
1772 return Register();
1773 return fastEmitInst_r(MachineInstOpcode: PPC::ANDI_rec_1_GT_BIT8, RC: &PPC::CRBITRCRegClass, Op0);
1774}
1775
1776Register fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, Register Op0) {
1777 switch (VT.SimpleTy) {
1778 case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0);
1779 case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0);
1780 default: return Register();
1781 }
1782}
1783
1784// FastEmit functions for ISD::UINT_TO_FP.
1785
1786Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1787 if ((Subtarget->hasSPE())) {
1788 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFUI, RC: &PPC::GPRCRegClass, Op0);
1789 }
1790 return Register();
1791}
1792
1793Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1794 if ((Subtarget->hasSPE())) {
1795 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFUI, RC: &PPC::SPERCRegClass, Op0);
1796 }
1797 return Register();
1798}
1799
1800Register fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1801switch (RetVT.SimpleTy) {
1802 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1803 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1804 default: return Register();
1805}
1806}
1807
1808Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1809 if (RetVT.SimpleTy != MVT::v4f32)
1810 return Register();
1811 if ((Subtarget->hasVSX())) {
1812 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXWSP, RC: &PPC::VSRCRegClass, Op0);
1813 }
1814 if ((Subtarget->hasAltivec())) {
1815 return fastEmitInst_r(MachineInstOpcode: PPC::VCFUX_0, RC: &PPC::VRRCRegClass, Op0);
1816 }
1817 return Register();
1818}
1819
1820Register fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
1821 if (RetVT.SimpleTy != MVT::v2f64)
1822 return Register();
1823 if ((Subtarget->hasVSX())) {
1824 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXDDP, RC: &PPC::VSRCRegClass, Op0);
1825 }
1826 return Register();
1827}
1828
1829Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1830 switch (VT.SimpleTy) {
1831 case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1832 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1833 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1834 default: return Register();
1835 }
1836}
1837
1838// FastEmit functions for ISD::ZERO_EXTEND.
1839
1840Register fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(Register Op0) {
1841 if ((Subtarget->isISA3_1())) {
1842 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC, RC: &PPC::GPRCRegClass, Op0);
1843 }
1844 return Register();
1845}
1846
1847Register fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(Register Op0) {
1848 if ((Subtarget->isISA3_1())) {
1849 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC8, RC: &PPC::G8RCRegClass, Op0);
1850 }
1851 return Register();
1852}
1853
1854Register fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(MVT RetVT, Register Op0) {
1855switch (RetVT.SimpleTy) {
1856 case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(Op0);
1857 case MVT::i64: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(Op0);
1858 default: return Register();
1859}
1860}
1861
1862Register fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
1863 switch (VT.SimpleTy) {
1864 case MVT::i1: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(RetVT, Op0);
1865 default: return Register();
1866 }
1867}
1868
1869// FastEmit functions for PPCISD::FCFID.
1870
1871Register fastEmit_PPCISD_FCFID_MVT_f64_r(MVT RetVT, Register Op0) {
1872 if (RetVT.SimpleTy != MVT::f64)
1873 return Register();
1874 if ((Subtarget->hasVSX())) {
1875 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDDP, RC: &PPC::VSFRCRegClass, Op0);
1876 }
1877 return fastEmitInst_r(MachineInstOpcode: PPC::FCFID, RC: &PPC::F8RCRegClass, Op0);
1878}
1879
1880Register fastEmit_PPCISD_FCFID_r(MVT VT, MVT RetVT, Register Op0) {
1881 switch (VT.SimpleTy) {
1882 case MVT::f64: return fastEmit_PPCISD_FCFID_MVT_f64_r(RetVT, Op0);
1883 default: return Register();
1884 }
1885}
1886
1887// FastEmit functions for PPCISD::FCFIDS.
1888
1889Register fastEmit_PPCISD_FCFIDS_MVT_f64_r(MVT RetVT, Register Op0) {
1890 if (RetVT.SimpleTy != MVT::f32)
1891 return Register();
1892 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1893 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDSP, RC: &PPC::VSSRCRegClass, Op0);
1894 }
1895 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDS, RC: &PPC::F4RCRegClass, Op0);
1896}
1897
1898Register fastEmit_PPCISD_FCFIDS_r(MVT VT, MVT RetVT, Register Op0) {
1899 switch (VT.SimpleTy) {
1900 case MVT::f64: return fastEmit_PPCISD_FCFIDS_MVT_f64_r(RetVT, Op0);
1901 default: return Register();
1902 }
1903}
1904
1905// FastEmit functions for PPCISD::FCFIDU.
1906
1907Register fastEmit_PPCISD_FCFIDU_MVT_f64_r(MVT RetVT, Register Op0) {
1908 if (RetVT.SimpleTy != MVT::f64)
1909 return Register();
1910 if ((Subtarget->hasVSX())) {
1911 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDDP, RC: &PPC::VSFRCRegClass, Op0);
1912 }
1913 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDU, RC: &PPC::F8RCRegClass, Op0);
1914}
1915
1916Register fastEmit_PPCISD_FCFIDU_r(MVT VT, MVT RetVT, Register Op0) {
1917 switch (VT.SimpleTy) {
1918 case MVT::f64: return fastEmit_PPCISD_FCFIDU_MVT_f64_r(RetVT, Op0);
1919 default: return Register();
1920 }
1921}
1922
1923// FastEmit functions for PPCISD::FCFIDUS.
1924
1925Register fastEmit_PPCISD_FCFIDUS_MVT_f64_r(MVT RetVT, Register Op0) {
1926 if (RetVT.SimpleTy != MVT::f32)
1927 return Register();
1928 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1929 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDSP, RC: &PPC::VSSRCRegClass, Op0);
1930 }
1931 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDUS, RC: &PPC::F4RCRegClass, Op0);
1932}
1933
1934Register fastEmit_PPCISD_FCFIDUS_r(MVT VT, MVT RetVT, Register Op0) {
1935 switch (VT.SimpleTy) {
1936 case MVT::f64: return fastEmit_PPCISD_FCFIDUS_MVT_f64_r(RetVT, Op0);
1937 default: return Register();
1938 }
1939}
1940
1941// FastEmit functions for PPCISD::FCTIDUZ.
1942
1943Register fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(MVT RetVT, Register Op0) {
1944 if (RetVT.SimpleTy != MVT::f32)
1945 return Register();
1946 if ((Subtarget->hasVSX())) {
1947 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDSs, RC: &PPC::VSSRCRegClass, Op0);
1948 }
1949 return Register();
1950}
1951
1952Register fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(MVT RetVT, Register Op0) {
1953 if (RetVT.SimpleTy != MVT::f64)
1954 return Register();
1955 if ((Subtarget->hasVSX())) {
1956 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDS, RC: &PPC::VSFRCRegClass, Op0);
1957 }
1958 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDUZ, RC: &PPC::F8RCRegClass, Op0);
1959}
1960
1961Register fastEmit_PPCISD_FCTIDUZ_MVT_f128_r(MVT RetVT, Register Op0) {
1962 if (RetVT.SimpleTy != MVT::f128)
1963 return Register();
1964 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1965 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUDZ, RC: &PPC::VRRCRegClass, Op0);
1966 }
1967 return Register();
1968}
1969
1970Register fastEmit_PPCISD_FCTIDUZ_r(MVT VT, MVT RetVT, Register Op0) {
1971 switch (VT.SimpleTy) {
1972 case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0);
1973 case MVT::f64: return fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(RetVT, Op0);
1974 case MVT::f128: return fastEmit_PPCISD_FCTIDUZ_MVT_f128_r(RetVT, Op0);
1975 default: return Register();
1976 }
1977}
1978
1979// FastEmit functions for PPCISD::FCTIDZ.
1980
1981Register fastEmit_PPCISD_FCTIDZ_MVT_f32_r(MVT RetVT, Register Op0) {
1982 if (RetVT.SimpleTy != MVT::f32)
1983 return Register();
1984 if ((Subtarget->hasVSX())) {
1985 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDSs, RC: &PPC::VSSRCRegClass, Op0);
1986 }
1987 return Register();
1988}
1989
1990Register fastEmit_PPCISD_FCTIDZ_MVT_f64_r(MVT RetVT, Register Op0) {
1991 if (RetVT.SimpleTy != MVT::f64)
1992 return Register();
1993 if ((Subtarget->hasVSX())) {
1994 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDS, RC: &PPC::VSFRCRegClass, Op0);
1995 }
1996 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDZ, RC: &PPC::F8RCRegClass, Op0);
1997}
1998
1999Register fastEmit_PPCISD_FCTIDZ_MVT_f128_r(MVT RetVT, Register Op0) {
2000 if (RetVT.SimpleTy != MVT::f128)
2001 return Register();
2002 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2003 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSDZ, RC: &PPC::VRRCRegClass, Op0);
2004 }
2005 return Register();
2006}
2007
2008Register fastEmit_PPCISD_FCTIDZ_r(MVT VT, MVT RetVT, Register Op0) {
2009 switch (VT.SimpleTy) {
2010 case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0);
2011 case MVT::f64: return fastEmit_PPCISD_FCTIDZ_MVT_f64_r(RetVT, Op0);
2012 case MVT::f128: return fastEmit_PPCISD_FCTIDZ_MVT_f128_r(RetVT, Op0);
2013 default: return Register();
2014 }
2015}
2016
2017// FastEmit functions for PPCISD::FCTIWUZ.
2018
2019Register fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(MVT RetVT, Register Op0) {
2020 if (RetVT.SimpleTy != MVT::f32)
2021 return Register();
2022 if ((Subtarget->hasVSX())) {
2023 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWSs, RC: &PPC::VSSRCRegClass, Op0);
2024 }
2025 return Register();
2026}
2027
2028Register fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(MVT RetVT, Register Op0) {
2029 if (RetVT.SimpleTy != MVT::f64)
2030 return Register();
2031 if ((Subtarget->hasVSX())) {
2032 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWS, RC: &PPC::VSFRCRegClass, Op0);
2033 }
2034 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWUZ, RC: &PPC::F8RCRegClass, Op0);
2035}
2036
2037Register fastEmit_PPCISD_FCTIWUZ_MVT_f128_r(MVT RetVT, Register Op0) {
2038 if (RetVT.SimpleTy != MVT::f128)
2039 return Register();
2040 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2041 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUWZ, RC: &PPC::VRRCRegClass, Op0);
2042 }
2043 return Register();
2044}
2045
2046Register fastEmit_PPCISD_FCTIWUZ_r(MVT VT, MVT RetVT, Register Op0) {
2047 switch (VT.SimpleTy) {
2048 case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0);
2049 case MVT::f64: return fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(RetVT, Op0);
2050 case MVT::f128: return fastEmit_PPCISD_FCTIWUZ_MVT_f128_r(RetVT, Op0);
2051 default: return Register();
2052 }
2053}
2054
2055// FastEmit functions for PPCISD::FCTIWZ.
2056
2057Register fastEmit_PPCISD_FCTIWZ_MVT_f32_r(MVT RetVT, Register Op0) {
2058 if (RetVT.SimpleTy != MVT::f32)
2059 return Register();
2060 if ((Subtarget->hasVSX())) {
2061 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWSs, RC: &PPC::VSSRCRegClass, Op0);
2062 }
2063 return Register();
2064}
2065
2066Register fastEmit_PPCISD_FCTIWZ_MVT_f64_r(MVT RetVT, Register Op0) {
2067 if (RetVT.SimpleTy != MVT::f64)
2068 return Register();
2069 if ((Subtarget->hasVSX())) {
2070 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWS, RC: &PPC::VSFRCRegClass, Op0);
2071 }
2072 if ((Subtarget->hasFPU())) {
2073 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWZ, RC: &PPC::F8RCRegClass, Op0);
2074 }
2075 return Register();
2076}
2077
2078Register fastEmit_PPCISD_FCTIWZ_MVT_f128_r(MVT RetVT, Register Op0) {
2079 if (RetVT.SimpleTy != MVT::f128)
2080 return Register();
2081 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2082 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSWZ, RC: &PPC::VRRCRegClass, Op0);
2083 }
2084 return Register();
2085}
2086
2087Register fastEmit_PPCISD_FCTIWZ_r(MVT VT, MVT RetVT, Register Op0) {
2088 switch (VT.SimpleTy) {
2089 case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0);
2090 case MVT::f64: return fastEmit_PPCISD_FCTIWZ_MVT_f64_r(RetVT, Op0);
2091 case MVT::f128: return fastEmit_PPCISD_FCTIWZ_MVT_f128_r(RetVT, Op0);
2092 default: return Register();
2093 }
2094}
2095
2096// FastEmit functions for PPCISD::FRE.
2097
2098Register fastEmit_PPCISD_FRE_MVT_f32_r(MVT RetVT, Register Op0) {
2099 if (RetVT.SimpleTy != MVT::f32)
2100 return Register();
2101 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2102 return fastEmitInst_r(MachineInstOpcode: PPC::XSRESP, RC: &PPC::VSSRCRegClass, Op0);
2103 }
2104 if ((Subtarget->hasFPU())) {
2105 return fastEmitInst_r(MachineInstOpcode: PPC::FRES, RC: &PPC::F4RCRegClass, Op0);
2106 }
2107 return Register();
2108}
2109
2110Register fastEmit_PPCISD_FRE_MVT_f64_r(MVT RetVT, Register Op0) {
2111 if (RetVT.SimpleTy != MVT::f64)
2112 return Register();
2113 if ((Subtarget->hasVSX())) {
2114 return fastEmitInst_r(MachineInstOpcode: PPC::XSREDP, RC: &PPC::VSFRCRegClass, Op0);
2115 }
2116 if ((Subtarget->hasFPU())) {
2117 return fastEmitInst_r(MachineInstOpcode: PPC::FRE, RC: &PPC::F8RCRegClass, Op0);
2118 }
2119 return Register();
2120}
2121
2122Register fastEmit_PPCISD_FRE_MVT_v4f32_r(MVT RetVT, Register Op0) {
2123 if (RetVT.SimpleTy != MVT::v4f32)
2124 return Register();
2125 if ((Subtarget->hasVSX())) {
2126 return fastEmitInst_r(MachineInstOpcode: PPC::XVRESP, RC: &PPC::VSRCRegClass, Op0);
2127 }
2128 if ((Subtarget->hasAltivec())) {
2129 return fastEmitInst_r(MachineInstOpcode: PPC::VREFP, RC: &PPC::VRRCRegClass, Op0);
2130 }
2131 return Register();
2132}
2133
2134Register fastEmit_PPCISD_FRE_MVT_v2f64_r(MVT RetVT, Register Op0) {
2135 if (RetVT.SimpleTy != MVT::v2f64)
2136 return Register();
2137 if ((Subtarget->hasVSX())) {
2138 return fastEmitInst_r(MachineInstOpcode: PPC::XVREDP, RC: &PPC::VSRCRegClass, Op0);
2139 }
2140 return Register();
2141}
2142
2143Register fastEmit_PPCISD_FRE_r(MVT VT, MVT RetVT, Register Op0) {
2144 switch (VT.SimpleTy) {
2145 case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0);
2146 case MVT::f64: return fastEmit_PPCISD_FRE_MVT_f64_r(RetVT, Op0);
2147 case MVT::v4f32: return fastEmit_PPCISD_FRE_MVT_v4f32_r(RetVT, Op0);
2148 case MVT::v2f64: return fastEmit_PPCISD_FRE_MVT_v2f64_r(RetVT, Op0);
2149 default: return Register();
2150 }
2151}
2152
2153// FastEmit functions for PPCISD::FRSQRTE.
2154
2155Register fastEmit_PPCISD_FRSQRTE_MVT_f32_r(MVT RetVT, Register Op0) {
2156 if (RetVT.SimpleTy != MVT::f32)
2157 return Register();
2158 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2159 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSQRTESP, RC: &PPC::VSSRCRegClass, Op0);
2160 }
2161 if ((Subtarget->hasFPU())) {
2162 return fastEmitInst_r(MachineInstOpcode: PPC::FRSQRTES, RC: &PPC::F4RCRegClass, Op0);
2163 }
2164 return Register();
2165}
2166
2167Register fastEmit_PPCISD_FRSQRTE_MVT_f64_r(MVT RetVT, Register Op0) {
2168 if (RetVT.SimpleTy != MVT::f64)
2169 return Register();
2170 if ((Subtarget->hasVSX())) {
2171 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSQRTEDP, RC: &PPC::VSFRCRegClass, Op0);
2172 }
2173 if ((Subtarget->hasFPU())) {
2174 return fastEmitInst_r(MachineInstOpcode: PPC::FRSQRTE, RC: &PPC::F8RCRegClass, Op0);
2175 }
2176 return Register();
2177}
2178
2179Register fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, Register Op0) {
2180 if (RetVT.SimpleTy != MVT::v4f32)
2181 return Register();
2182 if ((Subtarget->hasVSX())) {
2183 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSQRTESP, RC: &PPC::VSRCRegClass, Op0);
2184 }
2185 if ((Subtarget->hasAltivec())) {
2186 return fastEmitInst_r(MachineInstOpcode: PPC::VRSQRTEFP, RC: &PPC::VRRCRegClass, Op0);
2187 }
2188 return Register();
2189}
2190
2191Register fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, Register Op0) {
2192 if (RetVT.SimpleTy != MVT::v2f64)
2193 return Register();
2194 if ((Subtarget->hasVSX())) {
2195 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSQRTEDP, RC: &PPC::VSRCRegClass, Op0);
2196 }
2197 return Register();
2198}
2199
2200Register fastEmit_PPCISD_FRSQRTE_r(MVT VT, MVT RetVT, Register Op0) {
2201 switch (VT.SimpleTy) {
2202 case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0);
2203 case MVT::f64: return fastEmit_PPCISD_FRSQRTE_MVT_f64_r(RetVT, Op0);
2204 case MVT::v4f32: return fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0);
2205 case MVT::v2f64: return fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0);
2206 default: return Register();
2207 }
2208}
2209
2210// FastEmit functions for PPCISD::FSQRT.
2211
2212Register fastEmit_PPCISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
2213 if (RetVT.SimpleTy != MVT::f64)
2214 return Register();
2215 if ((Subtarget->hasVSX())) {
2216 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTDP, RC: &PPC::VSFRCRegClass, Op0);
2217 }
2218 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRT, RC: &PPC::F8RCRegClass, Op0);
2219}
2220
2221Register fastEmit_PPCISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
2222 if (RetVT.SimpleTy != MVT::v4f32)
2223 return Register();
2224 if ((Subtarget->hasVSX())) {
2225 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTSP, RC: &PPC::VSRCRegClass, Op0);
2226 }
2227 return Register();
2228}
2229
2230Register fastEmit_PPCISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
2231 if (RetVT.SimpleTy != MVT::v2f64)
2232 return Register();
2233 if ((Subtarget->hasVSX())) {
2234 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTDP, RC: &PPC::VSRCRegClass, Op0);
2235 }
2236 return Register();
2237}
2238
2239Register fastEmit_PPCISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
2240 switch (VT.SimpleTy) {
2241 case MVT::f64: return fastEmit_PPCISD_FSQRT_MVT_f64_r(RetVT, Op0);
2242 case MVT::v4f32: return fastEmit_PPCISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
2243 case MVT::v2f64: return fastEmit_PPCISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
2244 default: return Register();
2245 }
2246}
2247
2248// FastEmit functions for PPCISD::FTSQRT.
2249
2250Register fastEmit_PPCISD_FTSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
2251 if (RetVT.SimpleTy != MVT::i32)
2252 return Register();
2253 if ((Subtarget->hasVSX())) {
2254 return fastEmitInst_r(MachineInstOpcode: PPC::XSTSQRTDP, RC: &PPC::CRRCRegClass, Op0);
2255 }
2256 if ((Subtarget->hasFPU())) {
2257 return fastEmitInst_r(MachineInstOpcode: PPC::FTSQRT, RC: &PPC::CRRCRegClass, Op0);
2258 }
2259 return Register();
2260}
2261
2262Register fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
2263 if (RetVT.SimpleTy != MVT::i32)
2264 return Register();
2265 if ((Subtarget->hasVSX())) {
2266 return fastEmitInst_r(MachineInstOpcode: PPC::XVTSQRTSP, RC: &PPC::CRRCRegClass, Op0);
2267 }
2268 return Register();
2269}
2270
2271Register fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
2272 if (RetVT.SimpleTy != MVT::i32)
2273 return Register();
2274 if ((Subtarget->hasVSX())) {
2275 return fastEmitInst_r(MachineInstOpcode: PPC::XVTSQRTDP, RC: &PPC::CRRCRegClass, Op0);
2276 }
2277 return Register();
2278}
2279
2280Register fastEmit_PPCISD_FTSQRT_r(MVT VT, MVT RetVT, Register Op0) {
2281 switch (VT.SimpleTy) {
2282 case MVT::f64: return fastEmit_PPCISD_FTSQRT_MVT_f64_r(RetVT, Op0);
2283 case MVT::v4f32: return fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(RetVT, Op0);
2284 case MVT::v2f64: return fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(RetVT, Op0);
2285 default: return Register();
2286 }
2287}
2288
2289// FastEmit functions for PPCISD::GET_TLS_MOD_AIX.
2290
2291Register fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i32_r(MVT RetVT, Register Op0) {
2292 if (RetVT.SimpleTy != MVT::i32)
2293 return Register();
2294 return fastEmitInst_r(MachineInstOpcode: PPC::GETtlsMOD32AIX, RC: &PPC::GPRCRegClass, Op0);
2295}
2296
2297Register fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i64_r(MVT RetVT, Register Op0) {
2298 if (RetVT.SimpleTy != MVT::i64)
2299 return Register();
2300 return fastEmitInst_r(MachineInstOpcode: PPC::GETtlsMOD64AIX, RC: &PPC::G8RCRegClass, Op0);
2301}
2302
2303Register fastEmit_PPCISD_GET_TLS_MOD_AIX_r(MVT VT, MVT RetVT, Register Op0) {
2304 switch (VT.SimpleTy) {
2305 case MVT::i32: return fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i32_r(RetVT, Op0);
2306 case MVT::i64: return fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i64_r(RetVT, Op0);
2307 default: return Register();
2308 }
2309}
2310
2311// FastEmit functions for PPCISD::MFVSR.
2312
2313Register fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Register Op0) {
2314 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2315 return fastEmitInst_r(MachineInstOpcode: PPC::MFVSRWZ, RC: &PPC::GPRCRegClass, Op0);
2316 }
2317 return Register();
2318}
2319
2320Register fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Register Op0) {
2321 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2322 return fastEmitInst_r(MachineInstOpcode: PPC::MFVSRD, RC: &PPC::G8RCRegClass, Op0);
2323 }
2324 return Register();
2325}
2326
2327Register fastEmit_PPCISD_MFVSR_MVT_f64_r(MVT RetVT, Register Op0) {
2328switch (RetVT.SimpleTy) {
2329 case MVT::i32: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Op0);
2330 case MVT::i64: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Op0);
2331 default: return Register();
2332}
2333}
2334
2335Register fastEmit_PPCISD_MFVSR_r(MVT VT, MVT RetVT, Register Op0) {
2336 switch (VT.SimpleTy) {
2337 case MVT::f64: return fastEmit_PPCISD_MFVSR_MVT_f64_r(RetVT, Op0);
2338 default: return Register();
2339 }
2340}
2341
2342// FastEmit functions for PPCISD::MTCTR.
2343
2344Register fastEmit_PPCISD_MTCTR_MVT_i32_r(MVT RetVT, Register Op0) {
2345 if (RetVT.SimpleTy != MVT::isVoid)
2346 return Register();
2347 return fastEmitInst_r(MachineInstOpcode: PPC::MTCTR, RC: &PPC::GPRCRegClass, Op0);
2348}
2349
2350Register fastEmit_PPCISD_MTCTR_MVT_i64_r(MVT RetVT, Register Op0) {
2351 if (RetVT.SimpleTy != MVT::isVoid)
2352 return Register();
2353 return fastEmitInst_r(MachineInstOpcode: PPC::MTCTR8, RC: &PPC::G8RCRegClass, Op0);
2354}
2355
2356Register fastEmit_PPCISD_MTCTR_r(MVT VT, MVT RetVT, Register Op0) {
2357 switch (VT.SimpleTy) {
2358 case MVT::i32: return fastEmit_PPCISD_MTCTR_MVT_i32_r(RetVT, Op0);
2359 case MVT::i64: return fastEmit_PPCISD_MTCTR_MVT_i64_r(RetVT, Op0);
2360 default: return Register();
2361 }
2362}
2363
2364// FastEmit functions for PPCISD::MTVSRA.
2365
2366Register fastEmit_PPCISD_MTVSRA_MVT_i32_r(MVT RetVT, Register Op0) {
2367 if (RetVT.SimpleTy != MVT::f64)
2368 return Register();
2369 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2370 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRWA, RC: &PPC::VSFRCRegClass, Op0);
2371 }
2372 return Register();
2373}
2374
2375Register fastEmit_PPCISD_MTVSRA_MVT_i64_r(MVT RetVT, Register Op0) {
2376 if (RetVT.SimpleTy != MVT::f64)
2377 return Register();
2378 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2379 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRD, RC: &PPC::VSFRCRegClass, Op0);
2380 }
2381 return Register();
2382}
2383
2384Register fastEmit_PPCISD_MTVSRA_r(MVT VT, MVT RetVT, Register Op0) {
2385 switch (VT.SimpleTy) {
2386 case MVT::i32: return fastEmit_PPCISD_MTVSRA_MVT_i32_r(RetVT, Op0);
2387 case MVT::i64: return fastEmit_PPCISD_MTVSRA_MVT_i64_r(RetVT, Op0);
2388 default: return Register();
2389 }
2390}
2391
2392// FastEmit functions for PPCISD::MTVSRZ.
2393
2394Register fastEmit_PPCISD_MTVSRZ_MVT_i32_r(MVT RetVT, Register Op0) {
2395 if (RetVT.SimpleTy != MVT::f64)
2396 return Register();
2397 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2398 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRWZ, RC: &PPC::VSFRCRegClass, Op0);
2399 }
2400 return Register();
2401}
2402
2403Register fastEmit_PPCISD_MTVSRZ_r(MVT VT, MVT RetVT, Register Op0) {
2404 switch (VT.SimpleTy) {
2405 case MVT::i32: return fastEmit_PPCISD_MTVSRZ_MVT_i32_r(RetVT, Op0);
2406 default: return Register();
2407 }
2408}
2409
2410// FastEmit functions for PPCISD::SCALAR_TO_VECTOR_PERMUTED.
2411
2412Register fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(MVT RetVT, Register Op0) {
2413 if (RetVT.SimpleTy != MVT::v4f32)
2414 return Register();
2415 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (Subtarget->isLittleEndian())) {
2416 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSPN, RC: &PPC::VSRCRegClass, Op0);
2417 }
2418 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) {
2419 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSPN, RC: &PPC::VSRCRegClass, Op0);
2420 }
2421 return Register();
2422}
2423
2424Register fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_r(MVT VT, MVT RetVT, Register Op0) {
2425 switch (VT.SimpleTy) {
2426 case MVT::f32: return fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(RetVT, Op0);
2427 default: return Register();
2428 }
2429}
2430
2431// FastEmit functions for PPCISD::SETBC.
2432
2433Register fastEmit_PPCISD_SETBC_MVT_i1_r(MVT RetVT, Register Op0) {
2434 if (RetVT.SimpleTy != MVT::i32)
2435 return Register();
2436 if ((Subtarget->isISA3_1())) {
2437 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC, RC: &PPC::GPRCRegClass, Op0);
2438 }
2439 return Register();
2440}
2441
2442Register fastEmit_PPCISD_SETBC_r(MVT VT, MVT RetVT, Register Op0) {
2443 switch (VT.SimpleTy) {
2444 case MVT::i1: return fastEmit_PPCISD_SETBC_MVT_i1_r(RetVT, Op0);
2445 default: return Register();
2446 }
2447}
2448
2449// FastEmit functions for PPCISD::SETBCR.
2450
2451Register fastEmit_PPCISD_SETBCR_MVT_i1_r(MVT RetVT, Register Op0) {
2452 if (RetVT.SimpleTy != MVT::i32)
2453 return Register();
2454 if ((Subtarget->isISA3_1())) {
2455 return fastEmitInst_r(MachineInstOpcode: PPC::SETBCR, RC: &PPC::GPRCRegClass, Op0);
2456 }
2457 return Register();
2458}
2459
2460Register fastEmit_PPCISD_SETBCR_r(MVT VT, MVT RetVT, Register Op0) {
2461 switch (VT.SimpleTy) {
2462 case MVT::i1: return fastEmit_PPCISD_SETBCR_MVT_i1_r(RetVT, Op0);
2463 default: return Register();
2464 }
2465}
2466
2467// FastEmit functions for PPCISD::STRICT_FCFID.
2468
2469Register fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(MVT RetVT, Register Op0) {
2470 if (RetVT.SimpleTy != MVT::f64)
2471 return Register();
2472 if ((Subtarget->hasVSX())) {
2473 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDDP, RC: &PPC::VSFRCRegClass, Op0);
2474 }
2475 return fastEmitInst_r(MachineInstOpcode: PPC::FCFID, RC: &PPC::F8RCRegClass, Op0);
2476}
2477
2478Register fastEmit_PPCISD_STRICT_FCFID_r(MVT VT, MVT RetVT, Register Op0) {
2479 switch (VT.SimpleTy) {
2480 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(RetVT, Op0);
2481 default: return Register();
2482 }
2483}
2484
2485// FastEmit functions for PPCISD::STRICT_FCFIDS.
2486
2487Register fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(MVT RetVT, Register Op0) {
2488 if (RetVT.SimpleTy != MVT::f32)
2489 return Register();
2490 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2491 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDSP, RC: &PPC::VSSRCRegClass, Op0);
2492 }
2493 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDS, RC: &PPC::F4RCRegClass, Op0);
2494}
2495
2496Register fastEmit_PPCISD_STRICT_FCFIDS_r(MVT VT, MVT RetVT, Register Op0) {
2497 switch (VT.SimpleTy) {
2498 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(RetVT, Op0);
2499 default: return Register();
2500 }
2501}
2502
2503// FastEmit functions for PPCISD::STRICT_FCFIDU.
2504
2505Register fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(MVT RetVT, Register Op0) {
2506 if (RetVT.SimpleTy != MVT::f64)
2507 return Register();
2508 if ((Subtarget->hasVSX())) {
2509 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDDP, RC: &PPC::VSFRCRegClass, Op0);
2510 }
2511 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDU, RC: &PPC::F8RCRegClass, Op0);
2512}
2513
2514Register fastEmit_PPCISD_STRICT_FCFIDU_r(MVT VT, MVT RetVT, Register Op0) {
2515 switch (VT.SimpleTy) {
2516 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(RetVT, Op0);
2517 default: return Register();
2518 }
2519}
2520
2521// FastEmit functions for PPCISD::STRICT_FCFIDUS.
2522
2523Register fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(MVT RetVT, Register Op0) {
2524 if (RetVT.SimpleTy != MVT::f32)
2525 return Register();
2526 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2527 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDSP, RC: &PPC::VSSRCRegClass, Op0);
2528 }
2529 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDUS, RC: &PPC::F4RCRegClass, Op0);
2530}
2531
2532Register fastEmit_PPCISD_STRICT_FCFIDUS_r(MVT VT, MVT RetVT, Register Op0) {
2533 switch (VT.SimpleTy) {
2534 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(RetVT, Op0);
2535 default: return Register();
2536 }
2537}
2538
2539// FastEmit functions for PPCISD::STRICT_FCTIDUZ.
2540
2541Register fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(MVT RetVT, Register Op0) {
2542 if (RetVT.SimpleTy != MVT::f32)
2543 return Register();
2544 if ((Subtarget->hasVSX())) {
2545 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDSs, RC: &PPC::VSSRCRegClass, Op0);
2546 }
2547 return Register();
2548}
2549
2550Register fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(MVT RetVT, Register Op0) {
2551 if (RetVT.SimpleTy != MVT::f64)
2552 return Register();
2553 if ((Subtarget->hasVSX())) {
2554 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDS, RC: &PPC::VSFRCRegClass, Op0);
2555 }
2556 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDUZ, RC: &PPC::F8RCRegClass, Op0);
2557}
2558
2559Register fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f128_r(MVT RetVT, Register Op0) {
2560 if (RetVT.SimpleTy != MVT::f128)
2561 return Register();
2562 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2563 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUDZ, RC: &PPC::VRRCRegClass, Op0);
2564 }
2565 return Register();
2566}
2567
2568Register fastEmit_PPCISD_STRICT_FCTIDUZ_r(MVT VT, MVT RetVT, Register Op0) {
2569 switch (VT.SimpleTy) {
2570 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(RetVT, Op0);
2571 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(RetVT, Op0);
2572 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f128_r(RetVT, Op0);
2573 default: return Register();
2574 }
2575}
2576
2577// FastEmit functions for PPCISD::STRICT_FCTIDZ.
2578
2579Register fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(MVT RetVT, Register Op0) {
2580 if (RetVT.SimpleTy != MVT::f32)
2581 return Register();
2582 if ((Subtarget->hasVSX())) {
2583 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDSs, RC: &PPC::VSSRCRegClass, Op0);
2584 }
2585 return Register();
2586}
2587
2588Register fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(MVT RetVT, Register Op0) {
2589 if (RetVT.SimpleTy != MVT::f64)
2590 return Register();
2591 if ((Subtarget->hasVSX())) {
2592 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDS, RC: &PPC::VSFRCRegClass, Op0);
2593 }
2594 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDZ, RC: &PPC::F8RCRegClass, Op0);
2595}
2596
2597Register fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f128_r(MVT RetVT, Register Op0) {
2598 if (RetVT.SimpleTy != MVT::f128)
2599 return Register();
2600 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2601 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSDZ, RC: &PPC::VRRCRegClass, Op0);
2602 }
2603 return Register();
2604}
2605
2606Register fastEmit_PPCISD_STRICT_FCTIDZ_r(MVT VT, MVT RetVT, Register Op0) {
2607 switch (VT.SimpleTy) {
2608 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(RetVT, Op0);
2609 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(RetVT, Op0);
2610 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f128_r(RetVT, Op0);
2611 default: return Register();
2612 }
2613}
2614
2615// FastEmit functions for PPCISD::STRICT_FCTIWUZ.
2616
2617Register fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(MVT RetVT, Register Op0) {
2618 if (RetVT.SimpleTy != MVT::f32)
2619 return Register();
2620 if ((Subtarget->hasVSX())) {
2621 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWSs, RC: &PPC::VSSRCRegClass, Op0);
2622 }
2623 return Register();
2624}
2625
2626Register fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(MVT RetVT, Register Op0) {
2627 if (RetVT.SimpleTy != MVT::f64)
2628 return Register();
2629 if ((Subtarget->hasVSX())) {
2630 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWS, RC: &PPC::VSFRCRegClass, Op0);
2631 }
2632 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWUZ, RC: &PPC::F8RCRegClass, Op0);
2633}
2634
2635Register fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f128_r(MVT RetVT, Register Op0) {
2636 if (RetVT.SimpleTy != MVT::f128)
2637 return Register();
2638 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2639 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUWZ, RC: &PPC::VRRCRegClass, Op0);
2640 }
2641 return Register();
2642}
2643
2644Register fastEmit_PPCISD_STRICT_FCTIWUZ_r(MVT VT, MVT RetVT, Register Op0) {
2645 switch (VT.SimpleTy) {
2646 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(RetVT, Op0);
2647 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(RetVT, Op0);
2648 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f128_r(RetVT, Op0);
2649 default: return Register();
2650 }
2651}
2652
2653// FastEmit functions for PPCISD::STRICT_FCTIWZ.
2654
2655Register fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(MVT RetVT, Register Op0) {
2656 if (RetVT.SimpleTy != MVT::f32)
2657 return Register();
2658 if ((Subtarget->hasVSX())) {
2659 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWSs, RC: &PPC::VSSRCRegClass, Op0);
2660 }
2661 return Register();
2662}
2663
2664Register fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(MVT RetVT, Register Op0) {
2665 if (RetVT.SimpleTy != MVT::f64)
2666 return Register();
2667 if ((Subtarget->hasVSX())) {
2668 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWS, RC: &PPC::VSFRCRegClass, Op0);
2669 }
2670 if ((Subtarget->hasFPU())) {
2671 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWZ, RC: &PPC::F8RCRegClass, Op0);
2672 }
2673 return Register();
2674}
2675
2676Register fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f128_r(MVT RetVT, Register Op0) {
2677 if (RetVT.SimpleTy != MVT::f128)
2678 return Register();
2679 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2680 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSWZ, RC: &PPC::VRRCRegClass, Op0);
2681 }
2682 return Register();
2683}
2684
2685Register fastEmit_PPCISD_STRICT_FCTIWZ_r(MVT VT, MVT RetVT, Register Op0) {
2686 switch (VT.SimpleTy) {
2687 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(RetVT, Op0);
2688 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(RetVT, Op0);
2689 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f128_r(RetVT, Op0);
2690 default: return Register();
2691 }
2692}
2693
2694// FastEmit functions for PPCISD::TLSLD_AIX.
2695
2696Register fastEmit_PPCISD_TLSLD_AIX_MVT_i32_r(MVT RetVT, Register Op0) {
2697 if (RetVT.SimpleTy != MVT::i32)
2698 return Register();
2699 return fastEmitInst_r(MachineInstOpcode: PPC::TLSLDAIX, RC: &PPC::GPRCRegClass, Op0);
2700}
2701
2702Register fastEmit_PPCISD_TLSLD_AIX_MVT_i64_r(MVT RetVT, Register Op0) {
2703 if (RetVT.SimpleTy != MVT::i64)
2704 return Register();
2705 return fastEmitInst_r(MachineInstOpcode: PPC::TLSLDAIX8, RC: &PPC::G8RCRegClass, Op0);
2706}
2707
2708Register fastEmit_PPCISD_TLSLD_AIX_r(MVT VT, MVT RetVT, Register Op0) {
2709 switch (VT.SimpleTy) {
2710 case MVT::i32: return fastEmit_PPCISD_TLSLD_AIX_MVT_i32_r(RetVT, Op0);
2711 case MVT::i64: return fastEmit_PPCISD_TLSLD_AIX_MVT_i64_r(RetVT, Op0);
2712 default: return Register();
2713 }
2714}
2715
2716// FastEmit functions for PPCISD::XXMFACC.
2717
2718Register fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(MVT RetVT, Register Op0) {
2719 if (RetVT.SimpleTy != MVT::v512i1)
2720 return Register();
2721 if ((!Subtarget->isISAFuture()) && (Subtarget->hasMMA())) {
2722 return fastEmitInst_r(MachineInstOpcode: PPC::XXMFACC, RC: &PPC::ACCRCRegClass, Op0);
2723 }
2724 return Register();
2725}
2726
2727Register fastEmit_PPCISD_XXMFACC_r(MVT VT, MVT RetVT, Register Op0) {
2728 switch (VT.SimpleTy) {
2729 case MVT::v512i1: return fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(RetVT, Op0);
2730 default: return Register();
2731 }
2732}
2733
2734// FastEmit functions for PPCISD::XXSPLTI_SP_TO_DP.
2735
2736Register fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(MVT RetVT, Register Op0) {
2737 if (RetVT.SimpleTy != MVT::v2f64)
2738 return Register();
2739 if ((Subtarget->hasPrefixInstrs())) {
2740 return fastEmitInst_r(MachineInstOpcode: PPC::XXSPLTIDP, RC: &PPC::VSRCRegClass, Op0);
2741 }
2742 return Register();
2743}
2744
2745Register fastEmit_PPCISD_XXSPLTI_SP_TO_DP_r(MVT VT, MVT RetVT, Register Op0) {
2746 switch (VT.SimpleTy) {
2747 case MVT::i32: return fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(RetVT, Op0);
2748 default: return Register();
2749 }
2750}
2751
2752// Top-level FastEmit function.
2753
2754Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
2755 switch (Opcode) {
2756 case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0);
2757 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
2758 case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0);
2759 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
2760 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
2761 case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0);
2762 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
2763 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0);
2764 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0);
2765 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0);
2766 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
2767 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
2768 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
2769 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
2770 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
2771 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
2772 case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0);
2773 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
2774 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0);
2775 case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0);
2776 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
2777 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
2778 case ISD::STRICT_FCEIL: return fastEmit_ISD_STRICT_FCEIL_r(VT, RetVT, Op0);
2779 case ISD::STRICT_FFLOOR: return fastEmit_ISD_STRICT_FFLOOR_r(VT, RetVT, Op0);
2780 case ISD::STRICT_FNEARBYINT: return fastEmit_ISD_STRICT_FNEARBYINT_r(VT, RetVT, Op0);
2781 case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0);
2782 case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0);
2783 case ISD::STRICT_FP_TO_SINT: return fastEmit_ISD_STRICT_FP_TO_SINT_r(VT, RetVT, Op0);
2784 case ISD::STRICT_FP_TO_UINT: return fastEmit_ISD_STRICT_FP_TO_UINT_r(VT, RetVT, Op0);
2785 case ISD::STRICT_FRINT: return fastEmit_ISD_STRICT_FRINT_r(VT, RetVT, Op0);
2786 case ISD::STRICT_FROUND: return fastEmit_ISD_STRICT_FROUND_r(VT, RetVT, Op0);
2787 case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0);
2788 case ISD::STRICT_FTRUNC: return fastEmit_ISD_STRICT_FTRUNC_r(VT, RetVT, Op0);
2789 case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0);
2790 case ISD::STRICT_UINT_TO_FP: return fastEmit_ISD_STRICT_UINT_TO_FP_r(VT, RetVT, Op0);
2791 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0);
2792 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
2793 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0);
2794 case PPCISD::FCFID: return fastEmit_PPCISD_FCFID_r(VT, RetVT, Op0);
2795 case PPCISD::FCFIDS: return fastEmit_PPCISD_FCFIDS_r(VT, RetVT, Op0);
2796 case PPCISD::FCFIDU: return fastEmit_PPCISD_FCFIDU_r(VT, RetVT, Op0);
2797 case PPCISD::FCFIDUS: return fastEmit_PPCISD_FCFIDUS_r(VT, RetVT, Op0);
2798 case PPCISD::FCTIDUZ: return fastEmit_PPCISD_FCTIDUZ_r(VT, RetVT, Op0);
2799 case PPCISD::FCTIDZ: return fastEmit_PPCISD_FCTIDZ_r(VT, RetVT, Op0);
2800 case PPCISD::FCTIWUZ: return fastEmit_PPCISD_FCTIWUZ_r(VT, RetVT, Op0);
2801 case PPCISD::FCTIWZ: return fastEmit_PPCISD_FCTIWZ_r(VT, RetVT, Op0);
2802 case PPCISD::FRE: return fastEmit_PPCISD_FRE_r(VT, RetVT, Op0);
2803 case PPCISD::FRSQRTE: return fastEmit_PPCISD_FRSQRTE_r(VT, RetVT, Op0);
2804 case PPCISD::FSQRT: return fastEmit_PPCISD_FSQRT_r(VT, RetVT, Op0);
2805 case PPCISD::FTSQRT: return fastEmit_PPCISD_FTSQRT_r(VT, RetVT, Op0);
2806 case PPCISD::GET_TLS_MOD_AIX: return fastEmit_PPCISD_GET_TLS_MOD_AIX_r(VT, RetVT, Op0);
2807 case PPCISD::MFVSR: return fastEmit_PPCISD_MFVSR_r(VT, RetVT, Op0);
2808 case PPCISD::MTCTR: return fastEmit_PPCISD_MTCTR_r(VT, RetVT, Op0);
2809 case PPCISD::MTVSRA: return fastEmit_PPCISD_MTVSRA_r(VT, RetVT, Op0);
2810 case PPCISD::MTVSRZ: return fastEmit_PPCISD_MTVSRZ_r(VT, RetVT, Op0);
2811 case PPCISD::SCALAR_TO_VECTOR_PERMUTED: return fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_r(VT, RetVT, Op0);
2812 case PPCISD::SETBC: return fastEmit_PPCISD_SETBC_r(VT, RetVT, Op0);
2813 case PPCISD::SETBCR: return fastEmit_PPCISD_SETBCR_r(VT, RetVT, Op0);
2814 case PPCISD::STRICT_FCFID: return fastEmit_PPCISD_STRICT_FCFID_r(VT, RetVT, Op0);
2815 case PPCISD::STRICT_FCFIDS: return fastEmit_PPCISD_STRICT_FCFIDS_r(VT, RetVT, Op0);
2816 case PPCISD::STRICT_FCFIDU: return fastEmit_PPCISD_STRICT_FCFIDU_r(VT, RetVT, Op0);
2817 case PPCISD::STRICT_FCFIDUS: return fastEmit_PPCISD_STRICT_FCFIDUS_r(VT, RetVT, Op0);
2818 case PPCISD::STRICT_FCTIDUZ: return fastEmit_PPCISD_STRICT_FCTIDUZ_r(VT, RetVT, Op0);
2819 case PPCISD::STRICT_FCTIDZ: return fastEmit_PPCISD_STRICT_FCTIDZ_r(VT, RetVT, Op0);
2820 case PPCISD::STRICT_FCTIWUZ: return fastEmit_PPCISD_STRICT_FCTIWUZ_r(VT, RetVT, Op0);
2821 case PPCISD::STRICT_FCTIWZ: return fastEmit_PPCISD_STRICT_FCTIWZ_r(VT, RetVT, Op0);
2822 case PPCISD::TLSLD_AIX: return fastEmit_PPCISD_TLSLD_AIX_r(VT, RetVT, Op0);
2823 case PPCISD::XXMFACC: return fastEmit_PPCISD_XXMFACC_r(VT, RetVT, Op0);
2824 case PPCISD::XXSPLTI_SP_TO_DP: return fastEmit_PPCISD_XXSPLTI_SP_TO_DP_r(VT, RetVT, Op0);
2825 default: return Register();
2826 }
2827}
2828
2829// FastEmit functions for ISD::ABDU.
2830
2831Register fastEmit_ISD_ABDU_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2832 if (RetVT.SimpleTy != MVT::v16i8)
2833 return Register();
2834 if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) {
2835 return fastEmitInst_rr(MachineInstOpcode: PPC::VABSDUB, RC: &PPC::VRRCRegClass, Op0, Op1);
2836 }
2837 return Register();
2838}
2839
2840Register fastEmit_ISD_ABDU_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2841 if (RetVT.SimpleTy != MVT::v8i16)
2842 return Register();
2843 if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) {
2844 return fastEmitInst_rr(MachineInstOpcode: PPC::VABSDUH, RC: &PPC::VRRCRegClass, Op0, Op1);
2845 }
2846 return Register();
2847}
2848
2849Register fastEmit_ISD_ABDU_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2850 if (RetVT.SimpleTy != MVT::v4i32)
2851 return Register();
2852 if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) {
2853 return fastEmitInst_rr(MachineInstOpcode: PPC::VABSDUW, RC: &PPC::VRRCRegClass, Op0, Op1);
2854 }
2855 return Register();
2856}
2857
2858Register fastEmit_ISD_ABDU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2859 switch (VT.SimpleTy) {
2860 case MVT::v16i8: return fastEmit_ISD_ABDU_MVT_v16i8_rr(RetVT, Op0, Op1);
2861 case MVT::v8i16: return fastEmit_ISD_ABDU_MVT_v8i16_rr(RetVT, Op0, Op1);
2862 case MVT::v4i32: return fastEmit_ISD_ABDU_MVT_v4i32_rr(RetVT, Op0, Op1);
2863 default: return Register();
2864 }
2865}
2866
2867// FastEmit functions for ISD::ADD.
2868
2869Register fastEmit_ISD_ADD_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
2870 if (RetVT.SimpleTy != MVT::i1)
2871 return Register();
2872 return fastEmitInst_rr(MachineInstOpcode: PPC::CRXOR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
2873}
2874
2875Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2876 if (RetVT.SimpleTy != MVT::i32)
2877 return Register();
2878 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD4, RC: &PPC::GPRCRegClass, Op0, Op1);
2879}
2880
2881Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2882 if (RetVT.SimpleTy != MVT::i64)
2883 return Register();
2884 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD8, RC: &PPC::G8RCRegClass, Op0, Op1);
2885}
2886
2887Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2888 if (RetVT.SimpleTy != MVT::v16i8)
2889 return Register();
2890 if ((Subtarget->hasAltivec())) {
2891 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUBM, RC: &PPC::VRRCRegClass, Op0, Op1);
2892 }
2893 return Register();
2894}
2895
2896Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2897 if (RetVT.SimpleTy != MVT::v8i16)
2898 return Register();
2899 if ((Subtarget->hasAltivec())) {
2900 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUHM, RC: &PPC::VRRCRegClass, Op0, Op1);
2901 }
2902 return Register();
2903}
2904
2905Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2906 if (RetVT.SimpleTy != MVT::v4i32)
2907 return Register();
2908 if ((Subtarget->hasAltivec())) {
2909 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUWM, RC: &PPC::VRRCRegClass, Op0, Op1);
2910 }
2911 return Register();
2912}
2913
2914Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2915 if (RetVT.SimpleTy != MVT::v2i64)
2916 return Register();
2917 if ((Subtarget->hasP8Altivec())) {
2918 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUDM, RC: &PPC::VRRCRegClass, Op0, Op1);
2919 }
2920 return Register();
2921}
2922
2923Register fastEmit_ISD_ADD_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
2924 if (RetVT.SimpleTy != MVT::v1i128)
2925 return Register();
2926 if ((Subtarget->hasP8Altivec())) {
2927 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUQM, RC: &PPC::VRRCRegClass, Op0, Op1);
2928 }
2929 return Register();
2930}
2931
2932Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2933 switch (VT.SimpleTy) {
2934 case MVT::i1: return fastEmit_ISD_ADD_MVT_i1_rr(RetVT, Op0, Op1);
2935 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
2936 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
2937 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
2938 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
2939 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
2940 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
2941 case MVT::v1i128: return fastEmit_ISD_ADD_MVT_v1i128_rr(RetVT, Op0, Op1);
2942 default: return Register();
2943 }
2944}
2945
2946// FastEmit functions for ISD::AND.
2947
2948Register fastEmit_ISD_AND_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
2949 if (RetVT.SimpleTy != MVT::i1)
2950 return Register();
2951 return fastEmitInst_rr(MachineInstOpcode: PPC::CRAND, RC: &PPC::CRBITRCRegClass, Op0, Op1);
2952}
2953
2954Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2955 if (RetVT.SimpleTy != MVT::i32)
2956 return Register();
2957 return fastEmitInst_rr(MachineInstOpcode: PPC::AND, RC: &PPC::GPRCRegClass, Op0, Op1);
2958}
2959
2960Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2961 if (RetVT.SimpleTy != MVT::i64)
2962 return Register();
2963 return fastEmitInst_rr(MachineInstOpcode: PPC::AND8, RC: &PPC::G8RCRegClass, Op0, Op1);
2964}
2965
2966Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2967 if (RetVT.SimpleTy != MVT::v4i32)
2968 return Register();
2969 if ((Subtarget->hasVSX())) {
2970 return fastEmitInst_rr(MachineInstOpcode: PPC::XXLAND, RC: &PPC::VSRCRegClass, Op0, Op1);
2971 }
2972 if ((Subtarget->hasAltivec())) {
2973 return fastEmitInst_rr(MachineInstOpcode: PPC::VAND, RC: &PPC::VRRCRegClass, Op0, Op1);
2974 }
2975 return Register();
2976}
2977
2978Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2979 switch (VT.SimpleTy) {
2980 case MVT::i1: return fastEmit_ISD_AND_MVT_i1_rr(RetVT, Op0, Op1);
2981 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
2982 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
2983 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
2984 default: return Register();
2985 }
2986}
2987
2988// FastEmit functions for ISD::AVGCEILS.
2989
2990Register fastEmit_ISD_AVGCEILS_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2991 if (RetVT.SimpleTy != MVT::v16i8)
2992 return Register();
2993 if ((Subtarget->hasAltivec())) {
2994 return fastEmitInst_rr(MachineInstOpcode: PPC::VAVGSB, RC: &PPC::VRRCRegClass, Op0, Op1);
2995 }
2996 return Register();
2997}
2998
2999Register fastEmit_ISD_AVGCEILS_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3000 if (RetVT.SimpleTy != MVT::v8i16)
3001 return Register();
3002 if ((Subtarget->hasAltivec())) {
3003 return fastEmitInst_rr(MachineInstOpcode: PPC::VAVGSH, RC: &PPC::VRRCRegClass, Op0, Op1);
3004 }
3005 return Register();
3006}
3007
3008Register fastEmit_ISD_AVGCEILS_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3009 if (RetVT.SimpleTy != MVT::v4i32)
3010 return Register();
3011 if ((Subtarget->hasAltivec())) {
3012 return fastEmitInst_rr(MachineInstOpcode: PPC::VAVGSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3013 }
3014 return Register();
3015}
3016
3017Register fastEmit_ISD_AVGCEILS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3018 switch (VT.SimpleTy) {
3019 case MVT::v16i8: return fastEmit_ISD_AVGCEILS_MVT_v16i8_rr(RetVT, Op0, Op1);
3020 case MVT::v8i16: return fastEmit_ISD_AVGCEILS_MVT_v8i16_rr(RetVT, Op0, Op1);
3021 case MVT::v4i32: return fastEmit_ISD_AVGCEILS_MVT_v4i32_rr(RetVT, Op0, Op1);
3022 default: return Register();
3023 }
3024}
3025
3026// FastEmit functions for ISD::AVGCEILU.
3027
3028Register fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3029 if (RetVT.SimpleTy != MVT::v16i8)
3030 return Register();
3031 if ((Subtarget->hasAltivec())) {
3032 return fastEmitInst_rr(MachineInstOpcode: PPC::VAVGUB, RC: &PPC::VRRCRegClass, Op0, Op1);
3033 }
3034 return Register();
3035}
3036
3037Register fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3038 if (RetVT.SimpleTy != MVT::v8i16)
3039 return Register();
3040 if ((Subtarget->hasAltivec())) {
3041 return fastEmitInst_rr(MachineInstOpcode: PPC::VAVGUH, RC: &PPC::VRRCRegClass, Op0, Op1);
3042 }
3043 return Register();
3044}
3045
3046Register fastEmit_ISD_AVGCEILU_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3047 if (RetVT.SimpleTy != MVT::v4i32)
3048 return Register();
3049 if ((Subtarget->hasAltivec())) {
3050 return fastEmitInst_rr(MachineInstOpcode: PPC::VAVGUW, RC: &PPC::VRRCRegClass, Op0, Op1);
3051 }
3052 return Register();
3053}
3054
3055Register fastEmit_ISD_AVGCEILU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3056 switch (VT.SimpleTy) {
3057 case MVT::v16i8: return fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(RetVT, Op0, Op1);
3058 case MVT::v8i16: return fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(RetVT, Op0, Op1);
3059 case MVT::v4i32: return fastEmit_ISD_AVGCEILU_MVT_v4i32_rr(RetVT, Op0, Op1);
3060 default: return Register();
3061 }
3062}
3063
3064// FastEmit functions for ISD::BUILD_VECTOR.
3065
3066Register fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3067 if (RetVT.SimpleTy != MVT::v2i64)
3068 return Register();
3069 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian()) && (Subtarget->isISA3_0()) && (Subtarget->isPPC64())) {
3070 return fastEmitInst_rr(MachineInstOpcode: PPC::MTVSRDD, RC: &PPC::VSRCRegClass, Op0, Op1);
3071 }
3072 return Register();
3073}
3074
3075Register fastEmit_ISD_BUILD_VECTOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3076 switch (VT.SimpleTy) {
3077 case MVT::i64: return fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(RetVT, Op0, Op1);
3078 default: return Register();
3079 }
3080}
3081
3082// FastEmit functions for ISD::FADD.
3083
3084Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3085 if (RetVT.SimpleTy != MVT::f32)
3086 return Register();
3087 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3088 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3089 }
3090 if ((Subtarget->hasSPE())) {
3091 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSADD, RC: &PPC::GPRCRegClass, Op0, Op1);
3092 }
3093 if ((Subtarget->hasFPU())) {
3094 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDS, RC: &PPC::F4RCRegClass, Op0, Op1);
3095 }
3096 return Register();
3097}
3098
3099Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3100 if (RetVT.SimpleTy != MVT::f64)
3101 return Register();
3102 if ((Subtarget->hasVSX())) {
3103 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3104 }
3105 if ((Subtarget->hasSPE())) {
3106 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDADD, RC: &PPC::SPERCRegClass, Op0, Op1);
3107 }
3108 if ((Subtarget->hasFPU())) {
3109 return fastEmitInst_rr(MachineInstOpcode: PPC::FADD, RC: &PPC::F8RCRegClass, Op0, Op1);
3110 }
3111 return Register();
3112}
3113
3114Register fastEmit_ISD_FADD_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
3115 if (RetVT.SimpleTy != MVT::f128)
3116 return Register();
3117 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3118 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3119 }
3120 return Register();
3121}
3122
3123Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3124 if (RetVT.SimpleTy != MVT::v4f32)
3125 return Register();
3126 if ((Subtarget->hasVSX())) {
3127 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3128 }
3129 if ((Subtarget->hasAltivec())) {
3130 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDFP, RC: &PPC::VRRCRegClass, Op0, Op1);
3131 }
3132 return Register();
3133}
3134
3135Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3136 if (RetVT.SimpleTy != MVT::v2f64)
3137 return Register();
3138 if ((Subtarget->hasVSX())) {
3139 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3140 }
3141 return Register();
3142}
3143
3144Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3145 switch (VT.SimpleTy) {
3146 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
3147 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
3148 case MVT::f128: return fastEmit_ISD_FADD_MVT_f128_rr(RetVT, Op0, Op1);
3149 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
3150 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
3151 default: return Register();
3152 }
3153}
3154
3155// FastEmit functions for ISD::FDIV.
3156
3157Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3158 if (RetVT.SimpleTy != MVT::f32)
3159 return Register();
3160 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3161 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3162 }
3163 if ((Subtarget->hasSPE())) {
3164 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSDIV, RC: &PPC::GPRCRegClass, Op0, Op1);
3165 }
3166 if ((Subtarget->hasFPU())) {
3167 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIVS, RC: &PPC::F4RCRegClass, Op0, Op1);
3168 }
3169 return Register();
3170}
3171
3172Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3173 if (RetVT.SimpleTy != MVT::f64)
3174 return Register();
3175 if ((Subtarget->hasVSX())) {
3176 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3177 }
3178 if ((Subtarget->hasSPE())) {
3179 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDDIV, RC: &PPC::SPERCRegClass, Op0, Op1);
3180 }
3181 if ((Subtarget->hasFPU())) {
3182 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIV, RC: &PPC::F8RCRegClass, Op0, Op1);
3183 }
3184 return Register();
3185}
3186
3187Register fastEmit_ISD_FDIV_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
3188 if (RetVT.SimpleTy != MVT::f128)
3189 return Register();
3190 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3191 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3192 }
3193 return Register();
3194}
3195
3196Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3197 if (RetVT.SimpleTy != MVT::v4f32)
3198 return Register();
3199 if ((Subtarget->hasVSX())) {
3200 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3201 }
3202 return Register();
3203}
3204
3205Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3206 if (RetVT.SimpleTy != MVT::v2f64)
3207 return Register();
3208 if ((Subtarget->hasVSX())) {
3209 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3210 }
3211 return Register();
3212}
3213
3214Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3215 switch (VT.SimpleTy) {
3216 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
3217 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
3218 case MVT::f128: return fastEmit_ISD_FDIV_MVT_f128_rr(RetVT, Op0, Op1);
3219 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
3220 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
3221 default: return Register();
3222 }
3223}
3224
3225// FastEmit functions for ISD::FMAXNUM.
3226
3227Register fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3228 if (RetVT.SimpleTy != MVT::f64)
3229 return Register();
3230 if ((Subtarget->hasVSX())) {
3231 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3232 }
3233 return Register();
3234}
3235
3236Register fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3237 if (RetVT.SimpleTy != MVT::v4f32)
3238 return Register();
3239 if ((Subtarget->hasVSX())) {
3240 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3241 }
3242 return Register();
3243}
3244
3245Register fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3246 if (RetVT.SimpleTy != MVT::v2f64)
3247 return Register();
3248 if ((Subtarget->hasVSX())) {
3249 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3250 }
3251 return Register();
3252}
3253
3254Register fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3255 switch (VT.SimpleTy) {
3256 case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op1);
3257 case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
3258 case MVT::v2f64: return fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
3259 default: return Register();
3260 }
3261}
3262
3263// FastEmit functions for ISD::FMAXNUM_IEEE.
3264
3265Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3266 if (RetVT.SimpleTy != MVT::f64)
3267 return Register();
3268 if ((Subtarget->hasVSX())) {
3269 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3270 }
3271 return Register();
3272}
3273
3274Register fastEmit_ISD_FMAXNUM_IEEE_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3275 if (RetVT.SimpleTy != MVT::v4f32)
3276 return Register();
3277 if ((Subtarget->hasVSX())) {
3278 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3279 }
3280 return Register();
3281}
3282
3283Register fastEmit_ISD_FMAXNUM_IEEE_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3284 if (RetVT.SimpleTy != MVT::v2f64)
3285 return Register();
3286 if ((Subtarget->hasVSX())) {
3287 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3288 }
3289 return Register();
3290}
3291
3292Register fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3293 switch (VT.SimpleTy) {
3294 case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
3295 case MVT::v4f32: return fastEmit_ISD_FMAXNUM_IEEE_MVT_v4f32_rr(RetVT, Op0, Op1);
3296 case MVT::v2f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_v2f64_rr(RetVT, Op0, Op1);
3297 default: return Register();
3298 }
3299}
3300
3301// FastEmit functions for ISD::FMINNUM.
3302
3303Register fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3304 if (RetVT.SimpleTy != MVT::f64)
3305 return Register();
3306 if ((Subtarget->hasVSX())) {
3307 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3308 }
3309 return Register();
3310}
3311
3312Register fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3313 if (RetVT.SimpleTy != MVT::v4f32)
3314 return Register();
3315 if ((Subtarget->hasVSX())) {
3316 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3317 }
3318 return Register();
3319}
3320
3321Register fastEmit_ISD_FMINNUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3322 if (RetVT.SimpleTy != MVT::v2f64)
3323 return Register();
3324 if ((Subtarget->hasVSX())) {
3325 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3326 }
3327 return Register();
3328}
3329
3330Register fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3331 switch (VT.SimpleTy) {
3332 case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op1);
3333 case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
3334 case MVT::v2f64: return fastEmit_ISD_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
3335 default: return Register();
3336 }
3337}
3338
3339// FastEmit functions for ISD::FMINNUM_IEEE.
3340
3341Register fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3342 if (RetVT.SimpleTy != MVT::f64)
3343 return Register();
3344 if ((Subtarget->hasVSX())) {
3345 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3346 }
3347 return Register();
3348}
3349
3350Register fastEmit_ISD_FMINNUM_IEEE_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3351 if (RetVT.SimpleTy != MVT::v4f32)
3352 return Register();
3353 if ((Subtarget->hasVSX())) {
3354 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3355 }
3356 return Register();
3357}
3358
3359Register fastEmit_ISD_FMINNUM_IEEE_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3360 if (RetVT.SimpleTy != MVT::v2f64)
3361 return Register();
3362 if ((Subtarget->hasVSX())) {
3363 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3364 }
3365 return Register();
3366}
3367
3368Register fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3369 switch (VT.SimpleTy) {
3370 case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
3371 case MVT::v4f32: return fastEmit_ISD_FMINNUM_IEEE_MVT_v4f32_rr(RetVT, Op0, Op1);
3372 case MVT::v2f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_v2f64_rr(RetVT, Op0, Op1);
3373 default: return Register();
3374 }
3375}
3376
3377// FastEmit functions for ISD::FMUL.
3378
3379Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3380 if (RetVT.SimpleTy != MVT::f32)
3381 return Register();
3382 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3383 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3384 }
3385 if ((Subtarget->hasSPE())) {
3386 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSMUL, RC: &PPC::GPRCRegClass, Op0, Op1);
3387 }
3388 if ((Subtarget->hasFPU())) {
3389 return fastEmitInst_rr(MachineInstOpcode: PPC::FMULS, RC: &PPC::F4RCRegClass, Op0, Op1);
3390 }
3391 return Register();
3392}
3393
3394Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3395 if (RetVT.SimpleTy != MVT::f64)
3396 return Register();
3397 if ((Subtarget->hasVSX())) {
3398 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3399 }
3400 if ((Subtarget->hasSPE())) {
3401 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDMUL, RC: &PPC::SPERCRegClass, Op0, Op1);
3402 }
3403 if ((Subtarget->hasFPU())) {
3404 return fastEmitInst_rr(MachineInstOpcode: PPC::FMUL, RC: &PPC::F8RCRegClass, Op0, Op1);
3405 }
3406 return Register();
3407}
3408
3409Register fastEmit_ISD_FMUL_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
3410 if (RetVT.SimpleTy != MVT::f128)
3411 return Register();
3412 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3413 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3414 }
3415 return Register();
3416}
3417
3418Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3419 if (RetVT.SimpleTy != MVT::v4f32)
3420 return Register();
3421 if ((Subtarget->hasVSX())) {
3422 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3423 }
3424 return Register();
3425}
3426
3427Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3428 if (RetVT.SimpleTy != MVT::v2f64)
3429 return Register();
3430 if ((Subtarget->hasVSX())) {
3431 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3432 }
3433 return Register();
3434}
3435
3436Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3437 switch (VT.SimpleTy) {
3438 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
3439 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
3440 case MVT::f128: return fastEmit_ISD_FMUL_MVT_f128_rr(RetVT, Op0, Op1);
3441 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
3442 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
3443 default: return Register();
3444 }
3445}
3446
3447// FastEmit functions for ISD::FSUB.
3448
3449Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3450 if (RetVT.SimpleTy != MVT::f32)
3451 return Register();
3452 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3453 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3454 }
3455 if ((Subtarget->hasSPE())) {
3456 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSSUB, RC: &PPC::GPRCRegClass, Op0, Op1);
3457 }
3458 if ((Subtarget->hasFPU())) {
3459 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUBS, RC: &PPC::F4RCRegClass, Op0, Op1);
3460 }
3461 return Register();
3462}
3463
3464Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3465 if (RetVT.SimpleTy != MVT::f64)
3466 return Register();
3467 if ((Subtarget->hasVSX())) {
3468 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3469 }
3470 if ((Subtarget->hasSPE())) {
3471 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDSUB, RC: &PPC::SPERCRegClass, Op0, Op1);
3472 }
3473 if ((Subtarget->hasFPU())) {
3474 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUB, RC: &PPC::F8RCRegClass, Op0, Op1);
3475 }
3476 return Register();
3477}
3478
3479Register fastEmit_ISD_FSUB_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
3480 if (RetVT.SimpleTy != MVT::f128)
3481 return Register();
3482 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3483 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3484 }
3485 return Register();
3486}
3487
3488Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3489 if (RetVT.SimpleTy != MVT::v4f32)
3490 return Register();
3491 if ((Subtarget->hasVSX())) {
3492 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3493 }
3494 if ((Subtarget->hasAltivec())) {
3495 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBFP, RC: &PPC::VRRCRegClass, Op0, Op1);
3496 }
3497 return Register();
3498}
3499
3500Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3501 if (RetVT.SimpleTy != MVT::v2f64)
3502 return Register();
3503 if ((Subtarget->hasVSX())) {
3504 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3505 }
3506 return Register();
3507}
3508
3509Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3510 switch (VT.SimpleTy) {
3511 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
3512 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
3513 case MVT::f128: return fastEmit_ISD_FSUB_MVT_f128_rr(RetVT, Op0, Op1);
3514 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
3515 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
3516 default: return Register();
3517 }
3518}
3519
3520// FastEmit functions for ISD::MUL.
3521
3522Register fastEmit_ISD_MUL_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
3523 if (RetVT.SimpleTy != MVT::i1)
3524 return Register();
3525 return fastEmitInst_rr(MachineInstOpcode: PPC::CRAND, RC: &PPC::CRBITRCRegClass, Op0, Op1);
3526}
3527
3528Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3529 if (RetVT.SimpleTy != MVT::i32)
3530 return Register();
3531 return fastEmitInst_rr(MachineInstOpcode: PPC::MULLW, RC: &PPC::GPRCRegClass, Op0, Op1);
3532}
3533
3534Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3535 if (RetVT.SimpleTy != MVT::i64)
3536 return Register();
3537 return fastEmitInst_rr(MachineInstOpcode: PPC::MULLD, RC: &PPC::G8RCRegClass, Op0, Op1);
3538}
3539
3540Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3541 if (RetVT.SimpleTy != MVT::v4i32)
3542 return Register();
3543 if ((Subtarget->hasP8Altivec())) {
3544 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULUWM, RC: &PPC::VRRCRegClass, Op0, Op1);
3545 }
3546 return Register();
3547}
3548
3549Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3550 if (RetVT.SimpleTy != MVT::v2i64)
3551 return Register();
3552 if ((Subtarget->isISA3_1())) {
3553 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULLD, RC: &PPC::VRRCRegClass, Op0, Op1);
3554 }
3555 return Register();
3556}
3557
3558Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3559 switch (VT.SimpleTy) {
3560 case MVT::i1: return fastEmit_ISD_MUL_MVT_i1_rr(RetVT, Op0, Op1);
3561 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
3562 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
3563 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
3564 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
3565 default: return Register();
3566 }
3567}
3568
3569// FastEmit functions for ISD::MULHS.
3570
3571Register fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3572 if (RetVT.SimpleTy != MVT::i32)
3573 return Register();
3574 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHW, RC: &PPC::GPRCRegClass, Op0, Op1);
3575}
3576
3577Register fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3578 if (RetVT.SimpleTy != MVT::i64)
3579 return Register();
3580 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHD, RC: &PPC::G8RCRegClass, Op0, Op1);
3581}
3582
3583Register fastEmit_ISD_MULHS_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3584 if (RetVT.SimpleTy != MVT::v4i32)
3585 return Register();
3586 if ((Subtarget->isISA3_1())) {
3587 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3588 }
3589 return Register();
3590}
3591
3592Register fastEmit_ISD_MULHS_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3593 if (RetVT.SimpleTy != MVT::v2i64)
3594 return Register();
3595 if ((Subtarget->isISA3_1())) {
3596 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHSD, RC: &PPC::VRRCRegClass, Op0, Op1);
3597 }
3598 return Register();
3599}
3600
3601Register fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3602 switch (VT.SimpleTy) {
3603 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1);
3604 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1);
3605 case MVT::v4i32: return fastEmit_ISD_MULHS_MVT_v4i32_rr(RetVT, Op0, Op1);
3606 case MVT::v2i64: return fastEmit_ISD_MULHS_MVT_v2i64_rr(RetVT, Op0, Op1);
3607 default: return Register();
3608 }
3609}
3610
3611// FastEmit functions for ISD::MULHU.
3612
3613Register fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3614 if (RetVT.SimpleTy != MVT::i32)
3615 return Register();
3616 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHWU, RC: &PPC::GPRCRegClass, Op0, Op1);
3617}
3618
3619Register fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3620 if (RetVT.SimpleTy != MVT::i64)
3621 return Register();
3622 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHDU, RC: &PPC::G8RCRegClass, Op0, Op1);
3623}
3624
3625Register fastEmit_ISD_MULHU_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3626 if (RetVT.SimpleTy != MVT::v4i32)
3627 return Register();
3628 if ((Subtarget->isISA3_1())) {
3629 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHUW, RC: &PPC::VRRCRegClass, Op0, Op1);
3630 }
3631 return Register();
3632}
3633
3634Register fastEmit_ISD_MULHU_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3635 if (RetVT.SimpleTy != MVT::v2i64)
3636 return Register();
3637 if ((Subtarget->isISA3_1())) {
3638 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHUD, RC: &PPC::VRRCRegClass, Op0, Op1);
3639 }
3640 return Register();
3641}
3642
3643Register fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3644 switch (VT.SimpleTy) {
3645 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1);
3646 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1);
3647 case MVT::v4i32: return fastEmit_ISD_MULHU_MVT_v4i32_rr(RetVT, Op0, Op1);
3648 case MVT::v2i64: return fastEmit_ISD_MULHU_MVT_v2i64_rr(RetVT, Op0, Op1);
3649 default: return Register();
3650 }
3651}
3652
3653// FastEmit functions for ISD::OR.
3654
3655Register fastEmit_ISD_OR_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
3656 if (RetVT.SimpleTy != MVT::i1)
3657 return Register();
3658 return fastEmitInst_rr(MachineInstOpcode: PPC::CROR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
3659}
3660
3661Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3662 if (RetVT.SimpleTy != MVT::i32)
3663 return Register();
3664 return fastEmitInst_rr(MachineInstOpcode: PPC::OR, RC: &PPC::GPRCRegClass, Op0, Op1);
3665}
3666
3667Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3668 if (RetVT.SimpleTy != MVT::i64)
3669 return Register();
3670 return fastEmitInst_rr(MachineInstOpcode: PPC::OR8, RC: &PPC::G8RCRegClass, Op0, Op1);
3671}
3672
3673Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3674 if (RetVT.SimpleTy != MVT::v4i32)
3675 return Register();
3676 if ((Subtarget->hasVSX())) {
3677 return fastEmitInst_rr(MachineInstOpcode: PPC::XXLOR, RC: &PPC::VSRCRegClass, Op0, Op1);
3678 }
3679 if ((Subtarget->hasAltivec())) {
3680 return fastEmitInst_rr(MachineInstOpcode: PPC::VOR, RC: &PPC::VRRCRegClass, Op0, Op1);
3681 }
3682 return Register();
3683}
3684
3685Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3686 switch (VT.SimpleTy) {
3687 case MVT::i1: return fastEmit_ISD_OR_MVT_i1_rr(RetVT, Op0, Op1);
3688 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
3689 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
3690 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
3691 default: return Register();
3692 }
3693}
3694
3695// FastEmit functions for ISD::ROTL.
3696
3697Register fastEmit_ISD_ROTL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3698 if (RetVT.SimpleTy != MVT::v16i8)
3699 return Register();
3700 if ((Subtarget->hasAltivec())) {
3701 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLB, RC: &PPC::VRRCRegClass, Op0, Op1);
3702 }
3703 return Register();
3704}
3705
3706Register fastEmit_ISD_ROTL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3707 if (RetVT.SimpleTy != MVT::v8i16)
3708 return Register();
3709 if ((Subtarget->hasAltivec())) {
3710 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLH, RC: &PPC::VRRCRegClass, Op0, Op1);
3711 }
3712 return Register();
3713}
3714
3715Register fastEmit_ISD_ROTL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3716 if (RetVT.SimpleTy != MVT::v4i32)
3717 return Register();
3718 if ((Subtarget->hasVSX()) && (Subtarget->isISAFuture())) {
3719 return fastEmitInst_rr(MachineInstOpcode: PPC::XVRLW, RC: &PPC::VSRCRegClass, Op0, Op1);
3720 }
3721 if ((!Subtarget->isISAFuture())) {
3722 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLW, RC: &PPC::VRRCRegClass, Op0, Op1);
3723 }
3724 return Register();
3725}
3726
3727Register fastEmit_ISD_ROTL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3728 if (RetVT.SimpleTy != MVT::v2i64)
3729 return Register();
3730 if ((Subtarget->hasP8Altivec())) {
3731 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLD, RC: &PPC::VRRCRegClass, Op0, Op1);
3732 }
3733 return Register();
3734}
3735
3736Register fastEmit_ISD_ROTL_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
3737 if (RetVT.SimpleTy != MVT::v1i128)
3738 return Register();
3739 if ((Subtarget->isISA3_1())) {
3740 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLQ, RC: &PPC::VRRCRegClass, Op0, Op1);
3741 }
3742 return Register();
3743}
3744
3745Register fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3746 switch (VT.SimpleTy) {
3747 case MVT::v16i8: return fastEmit_ISD_ROTL_MVT_v16i8_rr(RetVT, Op0, Op1);
3748 case MVT::v8i16: return fastEmit_ISD_ROTL_MVT_v8i16_rr(RetVT, Op0, Op1);
3749 case MVT::v4i32: return fastEmit_ISD_ROTL_MVT_v4i32_rr(RetVT, Op0, Op1);
3750 case MVT::v2i64: return fastEmit_ISD_ROTL_MVT_v2i64_rr(RetVT, Op0, Op1);
3751 case MVT::v1i128: return fastEmit_ISD_ROTL_MVT_v1i128_rr(RetVT, Op0, Op1);
3752 default: return Register();
3753 }
3754}
3755
3756// FastEmit functions for ISD::SADDSAT.
3757
3758Register fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3759 if (RetVT.SimpleTy != MVT::v16i8)
3760 return Register();
3761 if ((Subtarget->hasAltivec())) {
3762 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDSBS, RC: &PPC::VRRCRegClass, Op0, Op1);
3763 }
3764 return Register();
3765}
3766
3767Register fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3768 if (RetVT.SimpleTy != MVT::v8i16)
3769 return Register();
3770 if ((Subtarget->hasAltivec())) {
3771 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDSHS, RC: &PPC::VRRCRegClass, Op0, Op1);
3772 }
3773 return Register();
3774}
3775
3776Register fastEmit_ISD_SADDSAT_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3777 if (RetVT.SimpleTy != MVT::v4i32)
3778 return Register();
3779 if ((Subtarget->hasAltivec())) {
3780 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDSWS, RC: &PPC::VRRCRegClass, Op0, Op1);
3781 }
3782 return Register();
3783}
3784
3785Register fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3786 switch (VT.SimpleTy) {
3787 case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
3788 case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
3789 case MVT::v4i32: return fastEmit_ISD_SADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
3790 default: return Register();
3791 }
3792}
3793
3794// FastEmit functions for ISD::SDIV.
3795
3796Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3797 if (RetVT.SimpleTy != MVT::i32)
3798 return Register();
3799 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVW, RC: &PPC::GPRCRegClass, Op0, Op1);
3800}
3801
3802Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3803 if (RetVT.SimpleTy != MVT::i64)
3804 return Register();
3805 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVD, RC: &PPC::G8RCRegClass, Op0, Op1);
3806}
3807
3808Register fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3809 if (RetVT.SimpleTy != MVT::v4i32)
3810 return Register();
3811 if ((Subtarget->isISA3_1())) {
3812 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3813 }
3814 return Register();
3815}
3816
3817Register fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3818 if (RetVT.SimpleTy != MVT::v2i64)
3819 return Register();
3820 if ((Subtarget->isISA3_1())) {
3821 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVSD, RC: &PPC::VRRCRegClass, Op0, Op1);
3822 }
3823 return Register();
3824}
3825
3826Register fastEmit_ISD_SDIV_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
3827 if (RetVT.SimpleTy != MVT::v1i128)
3828 return Register();
3829 if ((Subtarget->isISA3_1())) {
3830 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVSQ, RC: &PPC::VRRCRegClass, Op0, Op1);
3831 }
3832 return Register();
3833}
3834
3835Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3836 switch (VT.SimpleTy) {
3837 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
3838 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
3839 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
3840 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
3841 case MVT::v1i128: return fastEmit_ISD_SDIV_MVT_v1i128_rr(RetVT, Op0, Op1);
3842 default: return Register();
3843 }
3844}
3845
3846// FastEmit functions for ISD::SHL.
3847
3848Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3849 if (RetVT.SimpleTy != MVT::i32)
3850 return Register();
3851 return fastEmitInst_rr(MachineInstOpcode: PPC::SLW, RC: &PPC::GPRCRegClass, Op0, Op1);
3852}
3853
3854Register fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3855 if (RetVT.SimpleTy != MVT::v16i8)
3856 return Register();
3857 if ((Subtarget->hasAltivec())) {
3858 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLB, RC: &PPC::VRRCRegClass, Op0, Op1);
3859 }
3860 return Register();
3861}
3862
3863Register fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3864 if (RetVT.SimpleTy != MVT::v8i16)
3865 return Register();
3866 if ((Subtarget->hasAltivec())) {
3867 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLH, RC: &PPC::VRRCRegClass, Op0, Op1);
3868 }
3869 return Register();
3870}
3871
3872Register fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3873 if (RetVT.SimpleTy != MVT::v4i32)
3874 return Register();
3875 if ((Subtarget->hasAltivec())) {
3876 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLW, RC: &PPC::VRRCRegClass, Op0, Op1);
3877 }
3878 return Register();
3879}
3880
3881Register fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3882 if (RetVT.SimpleTy != MVT::v2i64)
3883 return Register();
3884 if ((Subtarget->hasP8Altivec())) {
3885 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLD, RC: &PPC::VRRCRegClass, Op0, Op1);
3886 }
3887 return Register();
3888}
3889
3890Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3891 switch (VT.SimpleTy) {
3892 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
3893 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
3894 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
3895 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
3896 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
3897 default: return Register();
3898 }
3899}
3900
3901// FastEmit functions for ISD::SMAX.
3902
3903Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3904 if (RetVT.SimpleTy != MVT::v16i8)
3905 return Register();
3906 if ((Subtarget->hasAltivec())) {
3907 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXSB, RC: &PPC::VRRCRegClass, Op0, Op1);
3908 }
3909 return Register();
3910}
3911
3912Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3913 if (RetVT.SimpleTy != MVT::v8i16)
3914 return Register();
3915 if ((Subtarget->hasAltivec())) {
3916 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXSH, RC: &PPC::VRRCRegClass, Op0, Op1);
3917 }
3918 return Register();
3919}
3920
3921Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3922 if (RetVT.SimpleTy != MVT::v4i32)
3923 return Register();
3924 if ((Subtarget->hasAltivec())) {
3925 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3926 }
3927 return Register();
3928}
3929
3930Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3931 switch (VT.SimpleTy) {
3932 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
3933 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
3934 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
3935 default: return Register();
3936 }
3937}
3938
3939// FastEmit functions for ISD::SMIN.
3940
3941Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3942 if (RetVT.SimpleTy != MVT::v16i8)
3943 return Register();
3944 if ((Subtarget->hasAltivec())) {
3945 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINSB, RC: &PPC::VRRCRegClass, Op0, Op1);
3946 }
3947 return Register();
3948}
3949
3950Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3951 if (RetVT.SimpleTy != MVT::v8i16)
3952 return Register();
3953 if ((Subtarget->hasAltivec())) {
3954 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINSH, RC: &PPC::VRRCRegClass, Op0, Op1);
3955 }
3956 return Register();
3957}
3958
3959Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3960 if (RetVT.SimpleTy != MVT::v4i32)
3961 return Register();
3962 if ((Subtarget->hasAltivec())) {
3963 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3964 }
3965 return Register();
3966}
3967
3968Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3969 switch (VT.SimpleTy) {
3970 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
3971 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
3972 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
3973 default: return Register();
3974 }
3975}
3976
3977// FastEmit functions for ISD::SRA.
3978
3979Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3980 if (RetVT.SimpleTy != MVT::i32)
3981 return Register();
3982 return fastEmitInst_rr(MachineInstOpcode: PPC::SRAW, RC: &PPC::GPRCRegClass, Op0, Op1);
3983}
3984
3985Register fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3986 if (RetVT.SimpleTy != MVT::v16i8)
3987 return Register();
3988 if ((Subtarget->hasAltivec())) {
3989 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAB, RC: &PPC::VRRCRegClass, Op0, Op1);
3990 }
3991 return Register();
3992}
3993
3994Register fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3995 if (RetVT.SimpleTy != MVT::v8i16)
3996 return Register();
3997 if ((Subtarget->hasAltivec())) {
3998 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAH, RC: &PPC::VRRCRegClass, Op0, Op1);
3999 }
4000 return Register();
4001}
4002
4003Register fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4004 if (RetVT.SimpleTy != MVT::v4i32)
4005 return Register();
4006 if ((Subtarget->hasAltivec())) {
4007 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAW, RC: &PPC::VRRCRegClass, Op0, Op1);
4008 }
4009 return Register();
4010}
4011
4012Register fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4013 if (RetVT.SimpleTy != MVT::v2i64)
4014 return Register();
4015 if ((Subtarget->hasP8Altivec())) {
4016 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAD, RC: &PPC::VRRCRegClass, Op0, Op1);
4017 }
4018 return Register();
4019}
4020
4021Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4022 switch (VT.SimpleTy) {
4023 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
4024 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
4025 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
4026 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
4027 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
4028 default: return Register();
4029 }
4030}
4031
4032// FastEmit functions for ISD::SREM.
4033
4034Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4035 if (RetVT.SimpleTy != MVT::i32)
4036 return Register();
4037 if ((Subtarget->isISA3_0())) {
4038 return fastEmitInst_rr(MachineInstOpcode: PPC::MODSW, RC: &PPC::GPRCRegClass, Op0, Op1);
4039 }
4040 return Register();
4041}
4042
4043Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4044 if (RetVT.SimpleTy != MVT::i64)
4045 return Register();
4046 if ((Subtarget->isISA3_0())) {
4047 return fastEmitInst_rr(MachineInstOpcode: PPC::MODSD, RC: &PPC::G8RCRegClass, Op0, Op1);
4048 }
4049 return Register();
4050}
4051
4052Register fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4053 if (RetVT.SimpleTy != MVT::v4i32)
4054 return Register();
4055 if ((Subtarget->isISA3_1())) {
4056 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODSW, RC: &PPC::VRRCRegClass, Op0, Op1);
4057 }
4058 return Register();
4059}
4060
4061Register fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4062 if (RetVT.SimpleTy != MVT::v2i64)
4063 return Register();
4064 if ((Subtarget->isISA3_1())) {
4065 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODSD, RC: &PPC::VRRCRegClass, Op0, Op1);
4066 }
4067 return Register();
4068}
4069
4070Register fastEmit_ISD_SREM_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
4071 if (RetVT.SimpleTy != MVT::v1i128)
4072 return Register();
4073 if ((Subtarget->isISA3_1())) {
4074 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODSQ, RC: &PPC::VRRCRegClass, Op0, Op1);
4075 }
4076 return Register();
4077}
4078
4079Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4080 switch (VT.SimpleTy) {
4081 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
4082 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
4083 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1);
4084 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1);
4085 case MVT::v1i128: return fastEmit_ISD_SREM_MVT_v1i128_rr(RetVT, Op0, Op1);
4086 default: return Register();
4087 }
4088}
4089
4090// FastEmit functions for ISD::SRL.
4091
4092Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4093 if (RetVT.SimpleTy != MVT::i32)
4094 return Register();
4095 return fastEmitInst_rr(MachineInstOpcode: PPC::SRW, RC: &PPC::GPRCRegClass, Op0, Op1);
4096}
4097
4098Register fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4099 if (RetVT.SimpleTy != MVT::v16i8)
4100 return Register();
4101 if ((Subtarget->hasAltivec())) {
4102 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRB, RC: &PPC::VRRCRegClass, Op0, Op1);
4103 }
4104 return Register();
4105}
4106
4107Register fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4108 if (RetVT.SimpleTy != MVT::v8i16)
4109 return Register();
4110 if ((Subtarget->hasAltivec())) {
4111 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRH, RC: &PPC::VRRCRegClass, Op0, Op1);
4112 }
4113 return Register();
4114}
4115
4116Register fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4117 if (RetVT.SimpleTy != MVT::v4i32)
4118 return Register();
4119 if ((Subtarget->hasAltivec())) {
4120 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRW, RC: &PPC::VRRCRegClass, Op0, Op1);
4121 }
4122 return Register();
4123}
4124
4125Register fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4126 if (RetVT.SimpleTy != MVT::v2i64)
4127 return Register();
4128 if ((Subtarget->hasP8Altivec())) {
4129 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRD, RC: &PPC::VRRCRegClass, Op0, Op1);
4130 }
4131 return Register();
4132}
4133
4134Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4135 switch (VT.SimpleTy) {
4136 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
4137 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
4138 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
4139 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
4140 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
4141 default: return Register();
4142 }
4143}
4144
4145// FastEmit functions for ISD::SSUBSAT.
4146
4147Register fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4148 if (RetVT.SimpleTy != MVT::v16i8)
4149 return Register();
4150 if ((Subtarget->hasAltivec())) {
4151 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBSBS, RC: &PPC::VRRCRegClass, Op0, Op1);
4152 }
4153 return Register();
4154}
4155
4156Register fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4157 if (RetVT.SimpleTy != MVT::v8i16)
4158 return Register();
4159 if ((Subtarget->hasAltivec())) {
4160 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBSHS, RC: &PPC::VRRCRegClass, Op0, Op1);
4161 }
4162 return Register();
4163}
4164
4165Register fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4166 if (RetVT.SimpleTy != MVT::v4i32)
4167 return Register();
4168 if ((Subtarget->hasAltivec())) {
4169 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBSWS, RC: &PPC::VRRCRegClass, Op0, Op1);
4170 }
4171 return Register();
4172}
4173
4174Register fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4175 switch (VT.SimpleTy) {
4176 case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
4177 case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
4178 case MVT::v4i32: return fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
4179 default: return Register();
4180 }
4181}
4182
4183// FastEmit functions for ISD::STRICT_FADD.
4184
4185Register fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
4186 if (RetVT.SimpleTy != MVT::f32)
4187 return Register();
4188 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4189 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4190 }
4191 if ((Subtarget->hasSPE())) {
4192 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSADD, RC: &PPC::GPRCRegClass, Op0, Op1);
4193 }
4194 if ((Subtarget->hasFPU())) {
4195 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDS, RC: &PPC::F4RCRegClass, Op0, Op1);
4196 }
4197 return Register();
4198}
4199
4200Register fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4201 if (RetVT.SimpleTy != MVT::f64)
4202 return Register();
4203 if ((Subtarget->hasVSX())) {
4204 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4205 }
4206 if ((Subtarget->hasSPE())) {
4207 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDADD, RC: &PPC::SPERCRegClass, Op0, Op1);
4208 }
4209 if ((Subtarget->hasFPU())) {
4210 return fastEmitInst_rr(MachineInstOpcode: PPC::FADD, RC: &PPC::F8RCRegClass, Op0, Op1);
4211 }
4212 return Register();
4213}
4214
4215Register fastEmit_ISD_STRICT_FADD_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
4216 if (RetVT.SimpleTy != MVT::f128)
4217 return Register();
4218 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4219 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4220 }
4221 return Register();
4222}
4223
4224Register fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4225 if (RetVT.SimpleTy != MVT::v4f32)
4226 return Register();
4227 if ((Subtarget->hasVSX())) {
4228 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4229 }
4230 return Register();
4231}
4232
4233Register fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4234 if (RetVT.SimpleTy != MVT::v2f64)
4235 return Register();
4236 if ((Subtarget->hasVSX())) {
4237 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4238 }
4239 return Register();
4240}
4241
4242Register fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4243 switch (VT.SimpleTy) {
4244 case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1);
4245 case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1);
4246 case MVT::f128: return fastEmit_ISD_STRICT_FADD_MVT_f128_rr(RetVT, Op0, Op1);
4247 case MVT::v4f32: return fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
4248 case MVT::v2f64: return fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
4249 default: return Register();
4250 }
4251}
4252
4253// FastEmit functions for ISD::STRICT_FDIV.
4254
4255Register fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
4256 if (RetVT.SimpleTy != MVT::f32)
4257 return Register();
4258 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4259 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4260 }
4261 if ((Subtarget->hasSPE())) {
4262 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSDIV, RC: &PPC::GPRCRegClass, Op0, Op1);
4263 }
4264 if ((Subtarget->hasFPU())) {
4265 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIVS, RC: &PPC::F4RCRegClass, Op0, Op1);
4266 }
4267 return Register();
4268}
4269
4270Register fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4271 if (RetVT.SimpleTy != MVT::f64)
4272 return Register();
4273 if ((Subtarget->hasVSX())) {
4274 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4275 }
4276 if ((Subtarget->hasSPE())) {
4277 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDDIV, RC: &PPC::SPERCRegClass, Op0, Op1);
4278 }
4279 if ((Subtarget->hasFPU())) {
4280 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIV, RC: &PPC::F8RCRegClass, Op0, Op1);
4281 }
4282 return Register();
4283}
4284
4285Register fastEmit_ISD_STRICT_FDIV_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
4286 if (RetVT.SimpleTy != MVT::f128)
4287 return Register();
4288 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4289 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4290 }
4291 return Register();
4292}
4293
4294Register fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4295 if (RetVT.SimpleTy != MVT::v4f32)
4296 return Register();
4297 if ((Subtarget->hasVSX())) {
4298 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4299 }
4300 return Register();
4301}
4302
4303Register fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4304 if (RetVT.SimpleTy != MVT::v2f64)
4305 return Register();
4306 if ((Subtarget->hasVSX())) {
4307 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4308 }
4309 return Register();
4310}
4311
4312Register fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4313 switch (VT.SimpleTy) {
4314 case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
4315 case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
4316 case MVT::f128: return fastEmit_ISD_STRICT_FDIV_MVT_f128_rr(RetVT, Op0, Op1);
4317 case MVT::v4f32: return fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
4318 case MVT::v2f64: return fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
4319 default: return Register();
4320 }
4321}
4322
4323// FastEmit functions for ISD::STRICT_FMAXNUM.
4324
4325Register fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4326 if (RetVT.SimpleTy != MVT::v4f32)
4327 return Register();
4328 if ((Subtarget->hasVSX())) {
4329 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4330 }
4331 return Register();
4332}
4333
4334Register fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4335 if (RetVT.SimpleTy != MVT::v2f64)
4336 return Register();
4337 if ((Subtarget->hasVSX())) {
4338 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4339 }
4340 return Register();
4341}
4342
4343Register fastEmit_ISD_STRICT_FMAXNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4344 switch (VT.SimpleTy) {
4345 case MVT::v4f32: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
4346 case MVT::v2f64: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
4347 default: return Register();
4348 }
4349}
4350
4351// FastEmit functions for ISD::STRICT_FMINNUM.
4352
4353Register fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4354 if (RetVT.SimpleTy != MVT::v4f32)
4355 return Register();
4356 if ((Subtarget->hasVSX())) {
4357 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4358 }
4359 return Register();
4360}
4361
4362Register fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4363 if (RetVT.SimpleTy != MVT::v2f64)
4364 return Register();
4365 if ((Subtarget->hasVSX())) {
4366 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4367 }
4368 return Register();
4369}
4370
4371Register fastEmit_ISD_STRICT_FMINNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4372 switch (VT.SimpleTy) {
4373 case MVT::v4f32: return fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
4374 case MVT::v2f64: return fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
4375 default: return Register();
4376 }
4377}
4378
4379// FastEmit functions for ISD::STRICT_FMUL.
4380
4381Register fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
4382 if (RetVT.SimpleTy != MVT::f32)
4383 return Register();
4384 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4385 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4386 }
4387 if ((Subtarget->hasSPE())) {
4388 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSMUL, RC: &PPC::GPRCRegClass, Op0, Op1);
4389 }
4390 if ((Subtarget->hasFPU())) {
4391 return fastEmitInst_rr(MachineInstOpcode: PPC::FMULS, RC: &PPC::F4RCRegClass, Op0, Op1);
4392 }
4393 return Register();
4394}
4395
4396Register fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4397 if (RetVT.SimpleTy != MVT::f64)
4398 return Register();
4399 if ((Subtarget->hasVSX())) {
4400 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4401 }
4402 if ((Subtarget->hasSPE())) {
4403 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDMUL, RC: &PPC::SPERCRegClass, Op0, Op1);
4404 }
4405 if ((Subtarget->hasFPU())) {
4406 return fastEmitInst_rr(MachineInstOpcode: PPC::FMUL, RC: &PPC::F8RCRegClass, Op0, Op1);
4407 }
4408 return Register();
4409}
4410
4411Register fastEmit_ISD_STRICT_FMUL_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
4412 if (RetVT.SimpleTy != MVT::f128)
4413 return Register();
4414 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4415 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4416 }
4417 return Register();
4418}
4419
4420Register fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4421 if (RetVT.SimpleTy != MVT::v4f32)
4422 return Register();
4423 if ((Subtarget->hasVSX())) {
4424 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4425 }
4426 return Register();
4427}
4428
4429Register fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4430 if (RetVT.SimpleTy != MVT::v2f64)
4431 return Register();
4432 if ((Subtarget->hasVSX())) {
4433 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4434 }
4435 return Register();
4436}
4437
4438Register fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4439 switch (VT.SimpleTy) {
4440 case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
4441 case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
4442 case MVT::f128: return fastEmit_ISD_STRICT_FMUL_MVT_f128_rr(RetVT, Op0, Op1);
4443 case MVT::v4f32: return fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
4444 case MVT::v2f64: return fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
4445 default: return Register();
4446 }
4447}
4448
4449// FastEmit functions for ISD::STRICT_FSUB.
4450
4451Register fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
4452 if (RetVT.SimpleTy != MVT::f32)
4453 return Register();
4454 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4455 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4456 }
4457 if ((Subtarget->hasSPE())) {
4458 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSSUB, RC: &PPC::GPRCRegClass, Op0, Op1);
4459 }
4460 if ((Subtarget->hasFPU())) {
4461 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUBS, RC: &PPC::F4RCRegClass, Op0, Op1);
4462 }
4463 return Register();
4464}
4465
4466Register fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4467 if (RetVT.SimpleTy != MVT::f64)
4468 return Register();
4469 if ((Subtarget->hasVSX())) {
4470 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4471 }
4472 if ((Subtarget->hasSPE())) {
4473 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDSUB, RC: &PPC::SPERCRegClass, Op0, Op1);
4474 }
4475 if ((Subtarget->hasFPU())) {
4476 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUB, RC: &PPC::F8RCRegClass, Op0, Op1);
4477 }
4478 return Register();
4479}
4480
4481Register fastEmit_ISD_STRICT_FSUB_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
4482 if (RetVT.SimpleTy != MVT::f128)
4483 return Register();
4484 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4485 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4486 }
4487 return Register();
4488}
4489
4490Register fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4491 if (RetVT.SimpleTy != MVT::v4f32)
4492 return Register();
4493 if ((Subtarget->hasVSX())) {
4494 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4495 }
4496 return Register();
4497}
4498
4499Register fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4500 if (RetVT.SimpleTy != MVT::v2f64)
4501 return Register();
4502 if ((Subtarget->hasVSX())) {
4503 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4504 }
4505 return Register();
4506}
4507
4508Register fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4509 switch (VT.SimpleTy) {
4510 case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
4511 case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
4512 case MVT::f128: return fastEmit_ISD_STRICT_FSUB_MVT_f128_rr(RetVT, Op0, Op1);
4513 case MVT::v4f32: return fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
4514 case MVT::v2f64: return fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
4515 default: return Register();
4516 }
4517}
4518
4519// FastEmit functions for ISD::SUB.
4520
4521Register fastEmit_ISD_SUB_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
4522 if (RetVT.SimpleTy != MVT::i1)
4523 return Register();
4524 return fastEmitInst_rr(MachineInstOpcode: PPC::CRXOR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
4525}
4526
4527Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4528 if (RetVT.SimpleTy != MVT::v16i8)
4529 return Register();
4530 if ((Subtarget->hasAltivec())) {
4531 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUBM, RC: &PPC::VRRCRegClass, Op0, Op1);
4532 }
4533 return Register();
4534}
4535
4536Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4537 if (RetVT.SimpleTy != MVT::v8i16)
4538 return Register();
4539 if ((Subtarget->hasAltivec())) {
4540 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUHM, RC: &PPC::VRRCRegClass, Op0, Op1);
4541 }
4542 return Register();
4543}
4544
4545Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4546 if (RetVT.SimpleTy != MVT::v4i32)
4547 return Register();
4548 if ((Subtarget->hasAltivec())) {
4549 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUWM, RC: &PPC::VRRCRegClass, Op0, Op1);
4550 }
4551 return Register();
4552}
4553
4554Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4555 if (RetVT.SimpleTy != MVT::v2i64)
4556 return Register();
4557 if ((Subtarget->hasP8Altivec())) {
4558 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUDM, RC: &PPC::VRRCRegClass, Op0, Op1);
4559 }
4560 return Register();
4561}
4562
4563Register fastEmit_ISD_SUB_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
4564 if (RetVT.SimpleTy != MVT::v1i128)
4565 return Register();
4566 if ((Subtarget->hasP8Altivec())) {
4567 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUQM, RC: &PPC::VRRCRegClass, Op0, Op1);
4568 }
4569 return Register();
4570}
4571
4572Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4573 switch (VT.SimpleTy) {
4574 case MVT::i1: return fastEmit_ISD_SUB_MVT_i1_rr(RetVT, Op0, Op1);
4575 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
4576 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
4577 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
4578 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
4579 case MVT::v1i128: return fastEmit_ISD_SUB_MVT_v1i128_rr(RetVT, Op0, Op1);
4580 default: return Register();
4581 }
4582}
4583
4584// FastEmit functions for ISD::UADDSAT.
4585
4586Register fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4587 if (RetVT.SimpleTy != MVT::v16i8)
4588 return Register();
4589 if ((Subtarget->hasAltivec())) {
4590 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUBS, RC: &PPC::VRRCRegClass, Op0, Op1);
4591 }
4592 return Register();
4593}
4594
4595Register fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4596 if (RetVT.SimpleTy != MVT::v8i16)
4597 return Register();
4598 if ((Subtarget->hasAltivec())) {
4599 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUHS, RC: &PPC::VRRCRegClass, Op0, Op1);
4600 }
4601 return Register();
4602}
4603
4604Register fastEmit_ISD_UADDSAT_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4605 if (RetVT.SimpleTy != MVT::v4i32)
4606 return Register();
4607 if ((Subtarget->hasAltivec())) {
4608 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUWS, RC: &PPC::VRRCRegClass, Op0, Op1);
4609 }
4610 return Register();
4611}
4612
4613Register fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4614 switch (VT.SimpleTy) {
4615 case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
4616 case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
4617 case MVT::v4i32: return fastEmit_ISD_UADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
4618 default: return Register();
4619 }
4620}
4621
4622// FastEmit functions for ISD::UDIV.
4623
4624Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4625 if (RetVT.SimpleTy != MVT::i32)
4626 return Register();
4627 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVWU, RC: &PPC::GPRCRegClass, Op0, Op1);
4628}
4629
4630Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4631 if (RetVT.SimpleTy != MVT::i64)
4632 return Register();
4633 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVDU, RC: &PPC::G8RCRegClass, Op0, Op1);
4634}
4635
4636Register fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4637 if (RetVT.SimpleTy != MVT::v4i32)
4638 return Register();
4639 if ((Subtarget->isISA3_1())) {
4640 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4641 }
4642 return Register();
4643}
4644
4645Register fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4646 if (RetVT.SimpleTy != MVT::v2i64)
4647 return Register();
4648 if ((Subtarget->isISA3_1())) {
4649 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVUD, RC: &PPC::VRRCRegClass, Op0, Op1);
4650 }
4651 return Register();
4652}
4653
4654Register fastEmit_ISD_UDIV_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
4655 if (RetVT.SimpleTy != MVT::v1i128)
4656 return Register();
4657 if ((Subtarget->isISA3_1())) {
4658 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVUQ, RC: &PPC::VRRCRegClass, Op0, Op1);
4659 }
4660 return Register();
4661}
4662
4663Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4664 switch (VT.SimpleTy) {
4665 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
4666 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
4667 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
4668 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
4669 case MVT::v1i128: return fastEmit_ISD_UDIV_MVT_v1i128_rr(RetVT, Op0, Op1);
4670 default: return Register();
4671 }
4672}
4673
4674// FastEmit functions for ISD::UMAX.
4675
4676Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4677 if (RetVT.SimpleTy != MVT::v16i8)
4678 return Register();
4679 if ((Subtarget->hasAltivec())) {
4680 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXUB, RC: &PPC::VRRCRegClass, Op0, Op1);
4681 }
4682 return Register();
4683}
4684
4685Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4686 if (RetVT.SimpleTy != MVT::v8i16)
4687 return Register();
4688 if ((Subtarget->hasAltivec())) {
4689 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXUH, RC: &PPC::VRRCRegClass, Op0, Op1);
4690 }
4691 return Register();
4692}
4693
4694Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4695 if (RetVT.SimpleTy != MVT::v4i32)
4696 return Register();
4697 if ((Subtarget->hasAltivec())) {
4698 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4699 }
4700 return Register();
4701}
4702
4703Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4704 switch (VT.SimpleTy) {
4705 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
4706 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
4707 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
4708 default: return Register();
4709 }
4710}
4711
4712// FastEmit functions for ISD::UMIN.
4713
4714Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4715 if (RetVT.SimpleTy != MVT::v16i8)
4716 return Register();
4717 if ((Subtarget->hasAltivec())) {
4718 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINUB, RC: &PPC::VRRCRegClass, Op0, Op1);
4719 }
4720 return Register();
4721}
4722
4723Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4724 if (RetVT.SimpleTy != MVT::v8i16)
4725 return Register();
4726 if ((Subtarget->hasAltivec())) {
4727 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINUH, RC: &PPC::VRRCRegClass, Op0, Op1);
4728 }
4729 return Register();
4730}
4731
4732Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4733 if (RetVT.SimpleTy != MVT::v4i32)
4734 return Register();
4735 if ((Subtarget->hasAltivec())) {
4736 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4737 }
4738 return Register();
4739}
4740
4741Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4742 switch (VT.SimpleTy) {
4743 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
4744 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
4745 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
4746 default: return Register();
4747 }
4748}
4749
4750// FastEmit functions for ISD::UREM.
4751
4752Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4753 if (RetVT.SimpleTy != MVT::i32)
4754 return Register();
4755 if ((Subtarget->isISA3_0())) {
4756 return fastEmitInst_rr(MachineInstOpcode: PPC::MODUW, RC: &PPC::GPRCRegClass, Op0, Op1);
4757 }
4758 return Register();
4759}
4760
4761Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4762 if (RetVT.SimpleTy != MVT::i64)
4763 return Register();
4764 if ((Subtarget->isISA3_0())) {
4765 return fastEmitInst_rr(MachineInstOpcode: PPC::MODUD, RC: &PPC::G8RCRegClass, Op0, Op1);
4766 }
4767 return Register();
4768}
4769
4770Register fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4771 if (RetVT.SimpleTy != MVT::v4i32)
4772 return Register();
4773 if ((Subtarget->isISA3_1())) {
4774 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4775 }
4776 return Register();
4777}
4778
4779Register fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4780 if (RetVT.SimpleTy != MVT::v2i64)
4781 return Register();
4782 if ((Subtarget->isISA3_1())) {
4783 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODUD, RC: &PPC::VRRCRegClass, Op0, Op1);
4784 }
4785 return Register();
4786}
4787
4788Register fastEmit_ISD_UREM_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
4789 if (RetVT.SimpleTy != MVT::v1i128)
4790 return Register();
4791 if ((Subtarget->isISA3_1())) {
4792 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODUQ, RC: &PPC::VRRCRegClass, Op0, Op1);
4793 }
4794 return Register();
4795}
4796
4797Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4798 switch (VT.SimpleTy) {
4799 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
4800 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
4801 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1);
4802 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1);
4803 case MVT::v1i128: return fastEmit_ISD_UREM_MVT_v1i128_rr(RetVT, Op0, Op1);
4804 default: return Register();
4805 }
4806}
4807
4808// FastEmit functions for ISD::USUBSAT.
4809
4810Register fastEmit_ISD_USUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4811 if (RetVT.SimpleTy != MVT::v16i8)
4812 return Register();
4813 if ((Subtarget->hasAltivec())) {
4814 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUBS, RC: &PPC::VRRCRegClass, Op0, Op1);
4815 }
4816 return Register();
4817}
4818
4819Register fastEmit_ISD_USUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4820 if (RetVT.SimpleTy != MVT::v8i16)
4821 return Register();
4822 if ((Subtarget->hasAltivec())) {
4823 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUHS, RC: &PPC::VRRCRegClass, Op0, Op1);
4824 }
4825 return Register();
4826}
4827
4828Register fastEmit_ISD_USUBSAT_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4829 if (RetVT.SimpleTy != MVT::v4i32)
4830 return Register();
4831 if ((Subtarget->hasAltivec())) {
4832 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUWS, RC: &PPC::VRRCRegClass, Op0, Op1);
4833 }
4834 return Register();
4835}
4836
4837Register fastEmit_ISD_USUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4838 switch (VT.SimpleTy) {
4839 case MVT::v16i8: return fastEmit_ISD_USUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
4840 case MVT::v8i16: return fastEmit_ISD_USUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
4841 case MVT::v4i32: return fastEmit_ISD_USUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
4842 default: return Register();
4843 }
4844}
4845
4846// FastEmit functions for ISD::XOR.
4847
4848Register fastEmit_ISD_XOR_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
4849 if (RetVT.SimpleTy != MVT::i1)
4850 return Register();
4851 return fastEmitInst_rr(MachineInstOpcode: PPC::CRXOR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
4852}
4853
4854Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4855 if (RetVT.SimpleTy != MVT::i32)
4856 return Register();
4857 return fastEmitInst_rr(MachineInstOpcode: PPC::XOR, RC: &PPC::GPRCRegClass, Op0, Op1);
4858}
4859
4860Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4861 if (RetVT.SimpleTy != MVT::i64)
4862 return Register();
4863 return fastEmitInst_rr(MachineInstOpcode: PPC::XOR8, RC: &PPC::G8RCRegClass, Op0, Op1);
4864}
4865
4866Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4867 if (RetVT.SimpleTy != MVT::v4i32)
4868 return Register();
4869 if ((Subtarget->hasVSX())) {
4870 return fastEmitInst_rr(MachineInstOpcode: PPC::XXLXOR, RC: &PPC::VSRCRegClass, Op0, Op1);
4871 }
4872 if ((Subtarget->hasAltivec())) {
4873 return fastEmitInst_rr(MachineInstOpcode: PPC::VXOR, RC: &PPC::VRRCRegClass, Op0, Op1);
4874 }
4875 return Register();
4876}
4877
4878Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4879 switch (VT.SimpleTy) {
4880 case MVT::i1: return fastEmit_ISD_XOR_MVT_i1_rr(RetVT, Op0, Op1);
4881 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
4882 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
4883 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
4884 default: return Register();
4885 }
4886}
4887
4888// FastEmit functions for PPCISD::ADD_TLS.
4889
4890Register fastEmit_PPCISD_ADD_TLS_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4891 if (RetVT.SimpleTy != MVT::i32)
4892 return Register();
4893 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD4TLS, RC: &PPC::GPRCRegClass, Op0, Op1);
4894}
4895
4896Register fastEmit_PPCISD_ADD_TLS_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4897 if (RetVT.SimpleTy != MVT::i64)
4898 return Register();
4899 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD8TLS, RC: &PPC::G8RCRegClass, Op0, Op1);
4900}
4901
4902Register fastEmit_PPCISD_ADD_TLS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4903 switch (VT.SimpleTy) {
4904 case MVT::i32: return fastEmit_PPCISD_ADD_TLS_MVT_i32_rr(RetVT, Op0, Op1);
4905 case MVT::i64: return fastEmit_PPCISD_ADD_TLS_MVT_i64_rr(RetVT, Op0, Op1);
4906 default: return Register();
4907 }
4908}
4909
4910// FastEmit functions for PPCISD::CMPB.
4911
4912Register fastEmit_PPCISD_CMPB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4913 if (RetVT.SimpleTy != MVT::i32)
4914 return Register();
4915 return fastEmitInst_rr(MachineInstOpcode: PPC::CMPB, RC: &PPC::GPRCRegClass, Op0, Op1);
4916}
4917
4918Register fastEmit_PPCISD_CMPB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4919 if (RetVT.SimpleTy != MVT::i64)
4920 return Register();
4921 return fastEmitInst_rr(MachineInstOpcode: PPC::CMPB8, RC: &PPC::G8RCRegClass, Op0, Op1);
4922}
4923
4924Register fastEmit_PPCISD_CMPB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4925 switch (VT.SimpleTy) {
4926 case MVT::i32: return fastEmit_PPCISD_CMPB_MVT_i32_rr(RetVT, Op0, Op1);
4927 case MVT::i64: return fastEmit_PPCISD_CMPB_MVT_i64_rr(RetVT, Op0, Op1);
4928 default: return Register();
4929 }
4930}
4931
4932// FastEmit functions for PPCISD::FADDRTZ.
4933
4934Register fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4935 if (RetVT.SimpleTy != MVT::f64)
4936 return Register();
4937 if ((Subtarget->hasFPU())) {
4938 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDrtz, RC: &PPC::F8RCRegClass, Op0, Op1);
4939 }
4940 return Register();
4941}
4942
4943Register fastEmit_PPCISD_FADDRTZ_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4944 switch (VT.SimpleTy) {
4945 case MVT::f64: return fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op1);
4946 default: return Register();
4947 }
4948}
4949
4950// FastEmit functions for PPCISD::GET_TLS_ADDR.
4951
4952Register fastEmit_PPCISD_GET_TLS_ADDR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4953 if (RetVT.SimpleTy != MVT::i32)
4954 return Register();
4955 return fastEmitInst_rr(MachineInstOpcode: PPC::GETtlsADDR32AIX, RC: &PPC::GPRCRegClass, Op0, Op1);
4956}
4957
4958Register fastEmit_PPCISD_GET_TLS_ADDR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4959 if (RetVT.SimpleTy != MVT::i64)
4960 return Register();
4961 return fastEmitInst_rr(MachineInstOpcode: PPC::GETtlsADDR64AIX, RC: &PPC::G8RCRegClass, Op0, Op1);
4962}
4963
4964Register fastEmit_PPCISD_GET_TLS_ADDR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4965 switch (VT.SimpleTy) {
4966 case MVT::i32: return fastEmit_PPCISD_GET_TLS_ADDR_MVT_i32_rr(RetVT, Op0, Op1);
4967 case MVT::i64: return fastEmit_PPCISD_GET_TLS_ADDR_MVT_i64_rr(RetVT, Op0, Op1);
4968 default: return Register();
4969 }
4970}
4971
4972// FastEmit functions for PPCISD::INST512.
4973
4974Register fastEmit_PPCISD_INST512_MVT_v256i1_rr(MVT RetVT, Register Op0, Register Op1) {
4975 if (RetVT.SimpleTy != MVT::v512i1)
4976 return Register();
4977 if ((Subtarget->isISAFuture()) && (Subtarget->hasMMA())) {
4978 return fastEmitInst_rr(MachineInstOpcode: PPC::DMXXINSTDMR512, RC: &PPC::WACCRCRegClass, Op0, Op1);
4979 }
4980 return Register();
4981}
4982
4983Register fastEmit_PPCISD_INST512_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4984 switch (VT.SimpleTy) {
4985 case MVT::v256i1: return fastEmit_PPCISD_INST512_MVT_v256i1_rr(RetVT, Op0, Op1);
4986 default: return Register();
4987 }
4988}
4989
4990// FastEmit functions for PPCISD::INST512HI.
4991
4992Register fastEmit_PPCISD_INST512HI_MVT_v256i1_rr(MVT RetVT, Register Op0, Register Op1) {
4993 if (RetVT.SimpleTy != MVT::v512i1)
4994 return Register();
4995 if ((Subtarget->isISAFuture()) && (Subtarget->hasMMA())) {
4996 return fastEmitInst_rr(MachineInstOpcode: PPC::DMXXINSTDMR512_HI, RC: &PPC::WACC_HIRCRegClass, Op0, Op1);
4997 }
4998 return Register();
4999}
5000
5001Register fastEmit_PPCISD_INST512HI_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5002 switch (VT.SimpleTy) {
5003 case MVT::v256i1: return fastEmit_PPCISD_INST512HI_MVT_v256i1_rr(RetVT, Op0, Op1);
5004 default: return Register();
5005 }
5006}
5007
5008// FastEmit functions for PPCISD::SHL.
5009
5010Register fastEmit_PPCISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
5011 if (RetVT.SimpleTy != MVT::i32)
5012 return Register();
5013 return fastEmitInst_rr(MachineInstOpcode: PPC::SLW, RC: &PPC::GPRCRegClass, Op0, Op1);
5014}
5015
5016Register fastEmit_PPCISD_SHL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
5017 if (RetVT.SimpleTy != MVT::v16i8)
5018 return Register();
5019 if ((Subtarget->hasAltivec())) {
5020 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLB, RC: &PPC::VRRCRegClass, Op0, Op1);
5021 }
5022 return Register();
5023}
5024
5025Register fastEmit_PPCISD_SHL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
5026 if (RetVT.SimpleTy != MVT::v8i16)
5027 return Register();
5028 if ((Subtarget->hasAltivec())) {
5029 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLH, RC: &PPC::VRRCRegClass, Op0, Op1);
5030 }
5031 return Register();
5032}
5033
5034Register fastEmit_PPCISD_SHL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
5035 if (RetVT.SimpleTy != MVT::v4i32)
5036 return Register();
5037 if ((Subtarget->hasAltivec())) {
5038 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLW, RC: &PPC::VRRCRegClass, Op0, Op1);
5039 }
5040 return Register();
5041}
5042
5043Register fastEmit_PPCISD_SHL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
5044 if (RetVT.SimpleTy != MVT::v2i64)
5045 return Register();
5046 if ((Subtarget->hasP8Altivec())) {
5047 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLD, RC: &PPC::VRRCRegClass, Op0, Op1);
5048 }
5049 return Register();
5050}
5051
5052Register fastEmit_PPCISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5053 switch (VT.SimpleTy) {
5054 case MVT::i32: return fastEmit_PPCISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
5055 case MVT::v16i8: return fastEmit_PPCISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
5056 case MVT::v8i16: return fastEmit_PPCISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
5057 case MVT::v4i32: return fastEmit_PPCISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
5058 case MVT::v2i64: return fastEmit_PPCISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
5059 default: return Register();
5060 }
5061}
5062
5063// FastEmit functions for PPCISD::SRA.
5064
5065Register fastEmit_PPCISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
5066 if (RetVT.SimpleTy != MVT::i32)
5067 return Register();
5068 return fastEmitInst_rr(MachineInstOpcode: PPC::SRAW, RC: &PPC::GPRCRegClass, Op0, Op1);
5069}
5070
5071Register fastEmit_PPCISD_SRA_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
5072 if (RetVT.SimpleTy != MVT::v16i8)
5073 return Register();
5074 if ((Subtarget->hasAltivec())) {
5075 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAB, RC: &PPC::VRRCRegClass, Op0, Op1);
5076 }
5077 return Register();
5078}
5079
5080Register fastEmit_PPCISD_SRA_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
5081 if (RetVT.SimpleTy != MVT::v8i16)
5082 return Register();
5083 if ((Subtarget->hasAltivec())) {
5084 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAH, RC: &PPC::VRRCRegClass, Op0, Op1);
5085 }
5086 return Register();
5087}
5088
5089Register fastEmit_PPCISD_SRA_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
5090 if (RetVT.SimpleTy != MVT::v4i32)
5091 return Register();
5092 if ((Subtarget->hasAltivec())) {
5093 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAW, RC: &PPC::VRRCRegClass, Op0, Op1);
5094 }
5095 return Register();
5096}
5097
5098Register fastEmit_PPCISD_SRA_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
5099 if (RetVT.SimpleTy != MVT::v2i64)
5100 return Register();
5101 if ((Subtarget->hasP8Altivec())) {
5102 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAD, RC: &PPC::VRRCRegClass, Op0, Op1);
5103 }
5104 return Register();
5105}
5106
5107Register fastEmit_PPCISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5108 switch (VT.SimpleTy) {
5109 case MVT::i32: return fastEmit_PPCISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
5110 case MVT::v16i8: return fastEmit_PPCISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
5111 case MVT::v8i16: return fastEmit_PPCISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
5112 case MVT::v4i32: return fastEmit_PPCISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
5113 case MVT::v2i64: return fastEmit_PPCISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
5114 default: return Register();
5115 }
5116}
5117
5118// FastEmit functions for PPCISD::SRL.
5119
5120Register fastEmit_PPCISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
5121 if (RetVT.SimpleTy != MVT::i32)
5122 return Register();
5123 return fastEmitInst_rr(MachineInstOpcode: PPC::SRW, RC: &PPC::GPRCRegClass, Op0, Op1);
5124}
5125
5126Register fastEmit_PPCISD_SRL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
5127 if (RetVT.SimpleTy != MVT::v16i8)
5128 return Register();
5129 if ((Subtarget->hasAltivec())) {
5130 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRB, RC: &PPC::VRRCRegClass, Op0, Op1);
5131 }
5132 return Register();
5133}
5134
5135Register fastEmit_PPCISD_SRL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
5136 if (RetVT.SimpleTy != MVT::v8i16)
5137 return Register();
5138 if ((Subtarget->hasAltivec())) {
5139 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRH, RC: &PPC::VRRCRegClass, Op0, Op1);
5140 }
5141 return Register();
5142}
5143
5144Register fastEmit_PPCISD_SRL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
5145 if (RetVT.SimpleTy != MVT::v4i32)
5146 return Register();
5147 if ((Subtarget->hasAltivec())) {
5148 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRW, RC: &PPC::VRRCRegClass, Op0, Op1);
5149 }
5150 return Register();
5151}
5152
5153Register fastEmit_PPCISD_SRL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
5154 if (RetVT.SimpleTy != MVT::v2i64)
5155 return Register();
5156 if ((Subtarget->hasP8Altivec())) {
5157 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRD, RC: &PPC::VRRCRegClass, Op0, Op1);
5158 }
5159 return Register();
5160}
5161
5162Register fastEmit_PPCISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5163 switch (VT.SimpleTy) {
5164 case MVT::i32: return fastEmit_PPCISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
5165 case MVT::v16i8: return fastEmit_PPCISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
5166 case MVT::v8i16: return fastEmit_PPCISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
5167 case MVT::v4i32: return fastEmit_PPCISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
5168 case MVT::v2i64: return fastEmit_PPCISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
5169 default: return Register();
5170 }
5171}
5172
5173// FastEmit functions for PPCISD::STRICT_FADDRTZ.
5174
5175Register fastEmit_PPCISD_STRICT_FADDRTZ_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
5176 if (RetVT.SimpleTy != MVT::f64)
5177 return Register();
5178 if ((Subtarget->hasFPU())) {
5179 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDrtz, RC: &PPC::F8RCRegClass, Op0, Op1);
5180 }
5181 return Register();
5182}
5183
5184Register fastEmit_PPCISD_STRICT_FADDRTZ_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5185 switch (VT.SimpleTy) {
5186 case MVT::f64: return fastEmit_PPCISD_STRICT_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op1);
5187 default: return Register();
5188 }
5189}
5190
5191// FastEmit functions for PPCISD::TLSGD_AIX.
5192
5193Register fastEmit_PPCISD_TLSGD_AIX_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
5194 if (RetVT.SimpleTy != MVT::i32)
5195 return Register();
5196 return fastEmitInst_rr(MachineInstOpcode: PPC::TLSGDAIX, RC: &PPC::GPRCRegClass, Op0, Op1);
5197}
5198
5199Register fastEmit_PPCISD_TLSGD_AIX_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
5200 if (RetVT.SimpleTy != MVT::i64)
5201 return Register();
5202 return fastEmitInst_rr(MachineInstOpcode: PPC::TLSGDAIX8, RC: &PPC::G8RCRegClass, Op0, Op1);
5203}
5204
5205Register fastEmit_PPCISD_TLSGD_AIX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5206 switch (VT.SimpleTy) {
5207 case MVT::i32: return fastEmit_PPCISD_TLSGD_AIX_MVT_i32_rr(RetVT, Op0, Op1);
5208 case MVT::i64: return fastEmit_PPCISD_TLSGD_AIX_MVT_i64_rr(RetVT, Op0, Op1);
5209 default: return Register();
5210 }
5211}
5212
5213// FastEmit functions for PPCISD::VSRQ.
5214
5215Register fastEmit_PPCISD_VSRQ_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
5216 if (RetVT.SimpleTy != MVT::v4i32)
5217 return Register();
5218 if ((Subtarget->isISA3_1())) {
5219 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRQ, RC: &PPC::VRRCRegClass, Op0, Op1);
5220 }
5221 return Register();
5222}
5223
5224Register fastEmit_PPCISD_VSRQ_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5225 switch (VT.SimpleTy) {
5226 case MVT::v4i32: return fastEmit_PPCISD_VSRQ_MVT_v4i32_rr(RetVT, Op0, Op1);
5227 default: return Register();
5228 }
5229}
5230
5231// FastEmit functions for PPCISD::XSMAXC.
5232
5233Register fastEmit_PPCISD_XSMAXC_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
5234 if (RetVT.SimpleTy != MVT::f64)
5235 return Register();
5236 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
5237 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXCDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
5238 }
5239 return Register();
5240}
5241
5242Register fastEmit_PPCISD_XSMAXC_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
5243 if (RetVT.SimpleTy != MVT::f128)
5244 return Register();
5245 if ((Subtarget->hasVSX()) && (Subtarget->isISA3_1())) {
5246 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXCQP, RC: &PPC::VRRCRegClass, Op0, Op1);
5247 }
5248 return Register();
5249}
5250
5251Register fastEmit_PPCISD_XSMAXC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5252 switch (VT.SimpleTy) {
5253 case MVT::f64: return fastEmit_PPCISD_XSMAXC_MVT_f64_rr(RetVT, Op0, Op1);
5254 case MVT::f128: return fastEmit_PPCISD_XSMAXC_MVT_f128_rr(RetVT, Op0, Op1);
5255 default: return Register();
5256 }
5257}
5258
5259// FastEmit functions for PPCISD::XSMINC.
5260
5261Register fastEmit_PPCISD_XSMINC_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
5262 if (RetVT.SimpleTy != MVT::f64)
5263 return Register();
5264 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
5265 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINCDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
5266 }
5267 return Register();
5268}
5269
5270Register fastEmit_PPCISD_XSMINC_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
5271 if (RetVT.SimpleTy != MVT::f128)
5272 return Register();
5273 if ((Subtarget->hasVSX()) && (Subtarget->isISA3_1())) {
5274 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINCQP, RC: &PPC::VRRCRegClass, Op0, Op1);
5275 }
5276 return Register();
5277}
5278
5279Register fastEmit_PPCISD_XSMINC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5280 switch (VT.SimpleTy) {
5281 case MVT::f64: return fastEmit_PPCISD_XSMINC_MVT_f64_rr(RetVT, Op0, Op1);
5282 case MVT::f128: return fastEmit_PPCISD_XSMINC_MVT_f128_rr(RetVT, Op0, Op1);
5283 default: return Register();
5284 }
5285}
5286
5287// Top-level FastEmit function.
5288
5289Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
5290 switch (Opcode) {
5291 case ISD::ABDU: return fastEmit_ISD_ABDU_rr(VT, RetVT, Op0, Op1);
5292 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
5293 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
5294 case ISD::AVGCEILS: return fastEmit_ISD_AVGCEILS_rr(VT, RetVT, Op0, Op1);
5295 case ISD::AVGCEILU: return fastEmit_ISD_AVGCEILU_rr(VT, RetVT, Op0, Op1);
5296 case ISD::BUILD_VECTOR: return fastEmit_ISD_BUILD_VECTOR_rr(VT, RetVT, Op0, Op1);
5297 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
5298 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
5299 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1);
5300 case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1);
5301 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1);
5302 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1);
5303 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
5304 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
5305 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
5306 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1);
5307 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1);
5308 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
5309 case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op1);
5310 case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op1);
5311 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
5312 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
5313 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
5314 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
5315 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
5316 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
5317 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
5318 case ISD::SSUBSAT: return fastEmit_ISD_SSUBSAT_rr(VT, RetVT, Op0, Op1);
5319 case ISD::STRICT_FADD: return fastEmit_ISD_STRICT_FADD_rr(VT, RetVT, Op0, Op1);
5320 case ISD::STRICT_FDIV: return fastEmit_ISD_STRICT_FDIV_rr(VT, RetVT, Op0, Op1);
5321 case ISD::STRICT_FMAXNUM: return fastEmit_ISD_STRICT_FMAXNUM_rr(VT, RetVT, Op0, Op1);
5322 case ISD::STRICT_FMINNUM: return fastEmit_ISD_STRICT_FMINNUM_rr(VT, RetVT, Op0, Op1);
5323 case ISD::STRICT_FMUL: return fastEmit_ISD_STRICT_FMUL_rr(VT, RetVT, Op0, Op1);
5324 case ISD::STRICT_FSUB: return fastEmit_ISD_STRICT_FSUB_rr(VT, RetVT, Op0, Op1);
5325 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
5326 case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op1);
5327 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
5328 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
5329 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
5330 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
5331 case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op1);
5332 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
5333 case PPCISD::ADD_TLS: return fastEmit_PPCISD_ADD_TLS_rr(VT, RetVT, Op0, Op1);
5334 case PPCISD::CMPB: return fastEmit_PPCISD_CMPB_rr(VT, RetVT, Op0, Op1);
5335 case PPCISD::FADDRTZ: return fastEmit_PPCISD_FADDRTZ_rr(VT, RetVT, Op0, Op1);
5336 case PPCISD::GET_TLS_ADDR: return fastEmit_PPCISD_GET_TLS_ADDR_rr(VT, RetVT, Op0, Op1);
5337 case PPCISD::INST512: return fastEmit_PPCISD_INST512_rr(VT, RetVT, Op0, Op1);
5338 case PPCISD::INST512HI: return fastEmit_PPCISD_INST512HI_rr(VT, RetVT, Op0, Op1);
5339 case PPCISD::SHL: return fastEmit_PPCISD_SHL_rr(VT, RetVT, Op0, Op1);
5340 case PPCISD::SRA: return fastEmit_PPCISD_SRA_rr(VT, RetVT, Op0, Op1);
5341 case PPCISD::SRL: return fastEmit_PPCISD_SRL_rr(VT, RetVT, Op0, Op1);
5342 case PPCISD::STRICT_FADDRTZ: return fastEmit_PPCISD_STRICT_FADDRTZ_rr(VT, RetVT, Op0, Op1);
5343 case PPCISD::TLSGD_AIX: return fastEmit_PPCISD_TLSGD_AIX_rr(VT, RetVT, Op0, Op1);
5344 case PPCISD::VSRQ: return fastEmit_PPCISD_VSRQ_rr(VT, RetVT, Op0, Op1);
5345 case PPCISD::XSMAXC: return fastEmit_PPCISD_XSMAXC_rr(VT, RetVT, Op0, Op1);
5346 case PPCISD::XSMINC: return fastEmit_PPCISD_XSMINC_rr(VT, RetVT, Op0, Op1);
5347 default: return Register();
5348 }
5349}
5350
5351// FastEmit functions for ISD::SRA.
5352
5353Register fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, Register Op0, uint64_t imm1) {
5354 if (RetVT.SimpleTy != MVT::i32)
5355 return Register();
5356 return fastEmitInst_ri(MachineInstOpcode: PPC::SRAWI, RC: &PPC::GPRCRegClass, Op0, Imm: imm1);
5357}
5358
5359Register fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, Register Op0, uint64_t imm1) {
5360 if (RetVT.SimpleTy != MVT::i64)
5361 return Register();
5362 return fastEmitInst_ri(MachineInstOpcode: PPC::SRADI, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5363}
5364
5365Register fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5366 switch (VT.SimpleTy) {
5367 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, imm1);
5368 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, imm1);
5369 default: return Register();
5370 }
5371}
5372
5373// FastEmit functions for PPCISD::EXTSWSLI.
5374
5375Register fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(MVT RetVT, Register Op0, uint64_t imm1) {
5376 if (RetVT.SimpleTy != MVT::i64)
5377 return Register();
5378 if ((Subtarget->isISA3_0())) {
5379 return fastEmitInst_ri(MachineInstOpcode: PPC::EXTSWSLI_32_64, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5380 }
5381 return Register();
5382}
5383
5384Register fastEmit_PPCISD_EXTSWSLI_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5385 switch (VT.SimpleTy) {
5386 case MVT::i32: return fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(RetVT, Op0, imm1);
5387 default: return Register();
5388 }
5389}
5390
5391// FastEmit functions for PPCISD::TC_RETURN.
5392
5393Register fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(MVT RetVT, Register Op0, uint64_t imm1) {
5394 if (RetVT.SimpleTy != MVT::isVoid)
5395 return Register();
5396 return fastEmitInst_ri(MachineInstOpcode: PPC::TCRETURNri, RC: &PPC::CTRRCRegClass, Op0, Imm: imm1);
5397}
5398
5399Register fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(MVT RetVT, Register Op0, uint64_t imm1) {
5400 if (RetVT.SimpleTy != MVT::isVoid)
5401 return Register();
5402 return fastEmitInst_ri(MachineInstOpcode: PPC::TCRETURNri8, RC: &PPC::CTRRC8RegClass, Op0, Imm: imm1);
5403}
5404
5405Register fastEmit_PPCISD_TC_RETURN_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5406 switch (VT.SimpleTy) {
5407 case MVT::i32: return fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(RetVT, Op0, imm1);
5408 case MVT::i64: return fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(RetVT, Op0, imm1);
5409 default: return Register();
5410 }
5411}
5412
5413// Top-level FastEmit function.
5414
5415Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) override {
5416 if (VT == MVT::i32 && Predicate_imm32SExt16(Imm: imm1))
5417 if (Register Reg = fastEmit_ri_Predicate_imm32SExt16(VT, RetVT, Opcode, Op0, imm1))
5418 return Reg;
5419
5420 if (VT == MVT::i64 && Predicate_imm64SExt16(Imm: imm1))
5421 if (Register Reg = fastEmit_ri_Predicate_imm64SExt16(VT, RetVT, Opcode, Op0, imm1))
5422 return Reg;
5423
5424 switch (Opcode) {
5425 case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, imm1);
5426 case PPCISD::EXTSWSLI: return fastEmit_PPCISD_EXTSWSLI_ri(VT, RetVT, Op0, imm1);
5427 case PPCISD::TC_RETURN: return fastEmit_PPCISD_TC_RETURN_ri(VT, RetVT, Op0, imm1);
5428 default: return Register();
5429 }
5430}
5431
5432// FastEmit functions for ISD::ADD.
5433
5434Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5435 if (RetVT.SimpleTy != MVT::i32)
5436 return Register();
5437 return fastEmitInst_ri(MachineInstOpcode: PPC::ADDI, RC: &PPC::GPRCRegClass, Op0, Imm: imm1);
5438}
5439
5440Register fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5441 switch (VT.SimpleTy) {
5442 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1);
5443 default: return Register();
5444 }
5445}
5446
5447// FastEmit functions for ISD::MUL.
5448
5449Register fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5450 if (RetVT.SimpleTy != MVT::i32)
5451 return Register();
5452 return fastEmitInst_ri(MachineInstOpcode: PPC::MULLI, RC: &PPC::GPRCRegClass, Op0, Imm: imm1);
5453}
5454
5455Register fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5456 switch (VT.SimpleTy) {
5457 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1);
5458 default: return Register();
5459 }
5460}
5461
5462// FastEmit functions for PPCISD::XXSPLT.
5463
5464Register fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5465 if (RetVT.SimpleTy != MVT::v4i32)
5466 return Register();
5467 if ((Subtarget->hasVSX())) {
5468 return fastEmitInst_ri(MachineInstOpcode: PPC::XXSPLTW, RC: &PPC::VSRCRegClass, Op0, Imm: imm1);
5469 }
5470 return Register();
5471}
5472
5473Register fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5474 switch (VT.SimpleTy) {
5475 case MVT::v4i32: return fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1);
5476 default: return Register();
5477 }
5478}
5479
5480// Top-level FastEmit function.
5481
5482Register fastEmit_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
5483 switch (Opcode) {
5484 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1);
5485 case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1);
5486 case PPCISD::XXSPLT: return fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1);
5487 default: return Register();
5488 }
5489}
5490
5491// FastEmit functions for ISD::ADD.
5492
5493Register fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5494 if (RetVT.SimpleTy != MVT::i64)
5495 return Register();
5496 return fastEmitInst_ri(MachineInstOpcode: PPC::ADDI8, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5497}
5498
5499Register fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5500 switch (VT.SimpleTy) {
5501 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1);
5502 default: return Register();
5503 }
5504}
5505
5506// FastEmit functions for ISD::MUL.
5507
5508Register fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5509 if (RetVT.SimpleTy != MVT::i64)
5510 return Register();
5511 return fastEmitInst_ri(MachineInstOpcode: PPC::MULLI8, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5512}
5513
5514Register fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5515 switch (VT.SimpleTy) {
5516 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1);
5517 default: return Register();
5518 }
5519}
5520
5521// Top-level FastEmit function.
5522
5523Register fastEmit_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
5524 switch (Opcode) {
5525 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1);
5526 case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1);
5527 default: return Register();
5528 }
5529}
5530
5531