1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#if !defined(GET_CC_REGISTER_LISTS)
10
11static bool CC_Sparc32(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
14static bool CC_Sparc64(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
17static bool RetCC_Sparc32(unsigned ValNo, MVT ValVT,
18 MVT LocVT, CCValAssign::LocInfo LocInfo,
19 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
20static bool RetCC_Sparc64(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
23
24
25static bool CC_Sparc32(unsigned ValNo, MVT ValVT,
26 MVT LocVT, CCValAssign::LocInfo LocInfo,
27 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
28
29 if (ArgFlags.isSRet()) {
30 if (CC_Sparc_Assign_SRet(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
31 return false;
32 }
33
34 if (LocVT == MVT::f128) {
35 LocVT = MVT::i32;
36 LocInfo = CCValAssign::Indirect;
37 }
38
39 if (LocVT == MVT::i32 ||
40 LocVT == MVT::f32) {
41 static const MCPhysReg RegList1[] = {
42 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
43 };
44 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
45 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
46 return false;
47 }
48 }
49
50 if (LocVT == MVT::f64) {
51 if (CC_Sparc_Assign_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
52 return false;
53 }
54
55 if (LocVT == MVT::v2i32) {
56 if (CC_Sparc_Assign_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
57 return false;
58 }
59
60 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
61 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
62 return false;
63
64 return true; // CC didn't match.
65}
66
67
68static bool CC_Sparc64(unsigned ValNo, MVT ValVT,
69 MVT LocVT, CCValAssign::LocInfo LocInfo,
70 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
71
72 if (ArgFlags.isInReg()) {
73 if (LocVT == MVT::i32 ||
74 LocVT == MVT::f32) {
75 if (CC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
76 return false;
77 }
78 }
79
80 if (LocVT == MVT::i32) {
81 LocVT = MVT::i64;
82 if (ArgFlags.isSExt())
83 LocInfo = CCValAssign::SExt;
84 else if (ArgFlags.isZExt())
85 LocInfo = CCValAssign::ZExt;
86 else
87 LocInfo = CCValAssign::AExt;
88 }
89
90 if (CC_Sparc64_Full(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
91 return false;
92
93 return true; // CC didn't match.
94}
95
96
97static bool RetCC_Sparc32(unsigned ValNo, MVT ValVT,
98 MVT LocVT, CCValAssign::LocInfo LocInfo,
99 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
100
101 if (LocVT == MVT::i32) {
102 static const MCPhysReg RegList1[] = {
103 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
104 };
105 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
106 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
107 return false;
108 }
109 }
110
111 if (LocVT == MVT::f32) {
112 static const MCPhysReg RegList2[] = {
113 SP::F0, SP::F1, SP::F2, SP::F3
114 };
115 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
116 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
117 return false;
118 }
119 }
120
121 if (LocVT == MVT::f64) {
122 static const MCPhysReg RegList3[] = {
123 SP::D0, SP::D1
124 };
125 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
126 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
127 return false;
128 }
129 }
130
131 if (LocVT == MVT::f128) {
132 if (ArgFlags.isInReg()) {
133 static const MCPhysReg RegList4[] = {
134 SP::Q0, SP::Q1
135 };
136 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
137 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
138 return false;
139 }
140 }
141 }
142
143 if (LocVT == MVT::v2i32) {
144 if (CC_Sparc_Assign_Ret_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
145 return false;
146 }
147
148 return true; // CC didn't match.
149}
150
151
152static bool RetCC_Sparc64(unsigned ValNo, MVT ValVT,
153 MVT LocVT, CCValAssign::LocInfo LocInfo,
154 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
155
156 if (LocVT == MVT::f32) {
157 if (RetCC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
158 return false;
159 }
160
161 if (ArgFlags.isInReg()) {
162 if (LocVT == MVT::i32 ||
163 LocVT == MVT::f32) {
164 if (RetCC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
165 return false;
166 }
167 }
168
169 if (LocVT == MVT::i32) {
170 LocVT = MVT::i64;
171 if (ArgFlags.isSExt())
172 LocInfo = CCValAssign::SExt;
173 else if (ArgFlags.isZExt())
174 LocInfo = CCValAssign::ZExt;
175 else
176 LocInfo = CCValAssign::AExt;
177 }
178
179 if (RetCC_Sparc64_Full(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
180 return false;
181
182 return true; // CC didn't match.
183}
184
185#else
186
187const MCRegister CC_Sparc32_ArgRegs[] = { SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 };
188const MCRegister CC_Sparc64_ArgRegs[] = { 0 };
189const MCRegister RetCC_Sparc32_ArgRegs[] = { SP::D0, SP::D1, SP::F0, SP::F1, SP::F2, SP::F3, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::Q0, SP::Q1 };
190const MCRegister RetCC_Sparc64_ArgRegs[] = { 0 };
191
192#endif // !defined(GET_CC_REGISTER_LISTS)
193
194