1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the interfaces that Sparc uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcISelLowering.h"
15#include "MCTargetDesc/SparcMCTargetDesc.h"
16#include "SparcMachineFunctionInfo.h"
17#include "SparcRegisterInfo.h"
18#include "SparcSelectionDAGInfo.h"
19#include "SparcTargetMachine.h"
20#include "SparcTargetObjectFile.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/ADT/StringSwitch.h"
23#include "llvm/BinaryFormat/ELF.h"
24#include "llvm/CodeGen/CallingConvLower.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/SelectionDAG.h"
30#include "llvm/CodeGen/SelectionDAGNodes.h"
31#include "llvm/CodeGen/TargetLowering.h"
32#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
33#include "llvm/IR/DerivedTypes.h"
34#include "llvm/IR/DiagnosticInfo.h"
35#include "llvm/IR/Function.h"
36#include "llvm/IR/IRBuilder.h"
37#include "llvm/IR/Module.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/KnownBits.h"
40using namespace llvm;
41
42
43//===----------------------------------------------------------------------===//
44// Calling Convention Implementation
45//===----------------------------------------------------------------------===//
46
47static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
48 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
49 ISD::ArgFlagsTy &ArgFlags, CCState &State)
50{
51 assert (ArgFlags.isSRet());
52
53 // Assign SRet argument.
54 State.addLoc(V: CCValAssign::getCustomMem(ValNo, ValVT,
55 Offset: 0,
56 LocVT, HTP: LocInfo));
57 return true;
58}
59
60static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT,
61 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
62 ISD::ArgFlagsTy &ArgFlags, CCState &State)
63{
64 static const MCPhysReg RegList[] = {
65 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
66 };
67 // Try to get first reg.
68 if (Register Reg = State.AllocateReg(Regs: RegList)) {
69 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
70 } else {
71 // Assign whole thing in stack.
72 State.addLoc(V: CCValAssign::getCustomMem(
73 ValNo, ValVT, Offset: State.AllocateStack(Size: 8, Alignment: Align(4)), LocVT, HTP: LocInfo));
74 return true;
75 }
76
77 // Try to get second reg.
78 if (Register Reg = State.AllocateReg(Regs: RegList))
79 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
80 else
81 State.addLoc(V: CCValAssign::getCustomMem(
82 ValNo, ValVT, Offset: State.AllocateStack(Size: 4, Alignment: Align(4)), LocVT, HTP: LocInfo));
83 return true;
84}
85
86static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT,
87 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
88 ISD::ArgFlagsTy &ArgFlags, CCState &State)
89{
90 static const MCPhysReg RegList[] = {
91 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
92 };
93
94 // Try to get first reg.
95 if (Register Reg = State.AllocateReg(Regs: RegList))
96 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
97 else
98 return false;
99
100 // Try to get second reg.
101 if (Register Reg = State.AllocateReg(Regs: RegList))
102 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
103 else
104 return false;
105
106 return true;
107}
108
109// Allocate a full-sized argument for the 64-bit ABI.
110static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT,
111 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
112 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
113 assert((LocVT == MVT::f32 || LocVT == MVT::f128
114 || LocVT.getSizeInBits() == 64) &&
115 "Can't handle non-64 bits locations");
116
117 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
118 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
119 Align alignment =
120 (LocVT == MVT::f128 || ArgFlags.isSplit()) ? Align(16) : Align(8);
121 unsigned Offset = State.AllocateStack(Size: size, Alignment: alignment);
122 unsigned Reg = 0;
123
124 if (LocVT == MVT::i64 && Offset < 6*8)
125 // Promote integers to %i0-%i5.
126 Reg = SP::I0 + Offset/8;
127 else if (LocVT == MVT::f64 && Offset < 16*8)
128 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
129 Reg = SP::D0 + Offset/8;
130 else if (LocVT == MVT::f32 && Offset < 16*8)
131 // Promote floats to %f1, %f3, ...
132 Reg = SP::F1 + Offset/4;
133 else if (LocVT == MVT::f128 && Offset < 16*8)
134 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
135 Reg = SP::Q0 + Offset/16;
136
137 // Promote to register when possible, otherwise use the stack slot.
138 if (Reg) {
139 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
140 return true;
141 }
142
143 // Bail out if this is a return CC and we run out of registers to place
144 // values into.
145 if (IsReturn)
146 return false;
147
148 // This argument goes on the stack in an 8-byte slot.
149 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
150 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
151 if (LocVT == MVT::f32)
152 Offset += 4;
153
154 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, HTP: LocInfo));
155 return true;
156}
157
158// Allocate a half-sized argument for the 64-bit ABI.
159//
160// This is used when passing { float, int } structs by value in registers.
161static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT,
162 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
163 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
164 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
165 unsigned Offset = State.AllocateStack(Size: 4, Alignment: Align(4));
166
167 if (LocVT == MVT::f32 && Offset < 16*8) {
168 // Promote floats to %f0-%f31.
169 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg: SP::F0 + Offset/4,
170 LocVT, HTP: LocInfo));
171 return true;
172 }
173
174 if (LocVT == MVT::i32 && Offset < 6*8) {
175 // Promote integers to %i0-%i5, using half the register.
176 unsigned Reg = SP::I0 + Offset/8;
177 LocVT = MVT::i64;
178 LocInfo = CCValAssign::AExt;
179
180 // Set the Custom bit if this i32 goes in the high bits of a register.
181 if (Offset % 8 == 0)
182 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg,
183 LocVT, HTP: LocInfo));
184 else
185 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
186 return true;
187 }
188
189 // Bail out if this is a return CC and we run out of registers to place
190 // values into.
191 if (IsReturn)
192 return false;
193
194 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, HTP: LocInfo));
195 return true;
196}
197
198static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
199 CCValAssign::LocInfo &LocInfo,
200 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
201 return Analyze_CC_Sparc64_Full(IsReturn: false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
202 State);
203}
204
205static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
206 CCValAssign::LocInfo &LocInfo,
207 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
208 return Analyze_CC_Sparc64_Half(IsReturn: false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
209 State);
210}
211
212static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
213 CCValAssign::LocInfo &LocInfo,
214 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
215 return Analyze_CC_Sparc64_Full(IsReturn: true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
216 State);
217}
218
219static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
220 CCValAssign::LocInfo &LocInfo,
221 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
222 return Analyze_CC_Sparc64_Half(IsReturn: true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
223 State);
224}
225
226#define GET_CALLING_CONV_IMPL
227#include "SparcGenCallingConv.inc"
228
229// The calling conventions in SparcCallingConv.td are described in terms of the
230// callee's register window. This function translates registers to the
231// corresponding caller window %o register.
232static unsigned toCallerWindow(unsigned Reg) {
233 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
234 "Unexpected enum");
235 if (Reg >= SP::I0 && Reg <= SP::I7)
236 return Reg - SP::I0 + SP::O0;
237 return Reg;
238}
239
240bool SparcTargetLowering::CanLowerReturn(
241 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
242 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
243 const Type *RetTy) const {
244 SmallVector<CCValAssign, 16> RVLocs;
245 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
246 return CCInfo.CheckReturn(Outs, Fn: Subtarget->is64Bit() ? RetCC_Sparc64
247 : RetCC_Sparc32);
248}
249
250SDValue
251SparcTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
252 bool IsVarArg,
253 const SmallVectorImpl<ISD::OutputArg> &Outs,
254 const SmallVectorImpl<SDValue> &OutVals,
255 const SDLoc &DL, SelectionDAG &DAG) const {
256 if (Subtarget->is64Bit())
257 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
258 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
259}
260
261SDValue
262SparcTargetLowering::LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
263 bool IsVarArg,
264 const SmallVectorImpl<ISD::OutputArg> &Outs,
265 const SmallVectorImpl<SDValue> &OutVals,
266 const SDLoc &DL, SelectionDAG &DAG) const {
267 MachineFunction &MF = DAG.getMachineFunction();
268
269 // CCValAssign - represent the assignment of the return value to locations.
270 SmallVector<CCValAssign, 16> RVLocs;
271
272 // CCState - Info about the registers and stack slot.
273 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
274 *DAG.getContext());
275
276 // Analyze return values.
277 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_Sparc32);
278
279 SDValue Glue;
280 SmallVector<SDValue, 4> RetOps(1, Chain);
281 // Make room for the return address offset.
282 RetOps.push_back(Elt: SDValue());
283
284 // Copy the result values into the output registers.
285 for (unsigned i = 0, realRVLocIdx = 0;
286 i != RVLocs.size();
287 ++i, ++realRVLocIdx) {
288 CCValAssign &VA = RVLocs[i];
289 assert(VA.isRegLoc() && "Can only return in registers!");
290
291 SDValue Arg = OutVals[realRVLocIdx];
292
293 if (VA.needsCustom()) {
294 assert(VA.getLocVT() == MVT::v2i32);
295 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
296 // happen by default if this wasn't a legal type)
297
298 SDValue Part0 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32,
299 N1: Arg,
300 N2: DAG.getConstant(Val: 0, DL, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
301 SDValue Part1 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32,
302 N1: Arg,
303 N2: DAG.getConstant(Val: 1, DL, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
304
305 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Part0, Glue);
306 Glue = Chain.getValue(R: 1);
307 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
308 VA = RVLocs[++i]; // skip ahead to next loc
309 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Part1,
310 Glue);
311 } else
312 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Arg, Glue);
313
314 // Guarantee that all emitted copies are stuck together with flags.
315 Glue = Chain.getValue(R: 1);
316 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
317 }
318
319 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
320 // If the function returns a struct, copy the SRetReturnReg to I0
321 if (MF.getFunction().hasStructRetAttr()) {
322 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
323 Register Reg = SFI->getSRetReturnReg();
324 if (!Reg)
325 llvm_unreachable("sret virtual register not created in the entry block");
326 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
327 SDValue Val = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: PtrVT);
328 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SP::I0, N: Val, Glue);
329 Glue = Chain.getValue(R: 1);
330 RetOps.push_back(Elt: DAG.getRegister(Reg: SP::I0, VT: PtrVT));
331 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
332 }
333
334 RetOps[0] = Chain; // Update chain.
335 RetOps[1] = DAG.getConstant(Val: RetAddrOffset, DL, VT: MVT::i32);
336
337 // Add the glue if we have it.
338 if (Glue.getNode())
339 RetOps.push_back(Elt: Glue);
340
341 return DAG.getNode(Opcode: SPISD::RET_GLUE, DL, VT: MVT::Other, Ops: RetOps);
342}
343
344// Lower return values for the 64-bit ABI.
345// Return values are passed the exactly the same way as function arguments.
346SDValue
347SparcTargetLowering::LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
348 bool IsVarArg,
349 const SmallVectorImpl<ISD::OutputArg> &Outs,
350 const SmallVectorImpl<SDValue> &OutVals,
351 const SDLoc &DL, SelectionDAG &DAG) const {
352 // CCValAssign - represent the assignment of the return value to locations.
353 SmallVector<CCValAssign, 16> RVLocs;
354
355 // CCState - Info about the registers and stack slot.
356 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
357 *DAG.getContext());
358
359 // Analyze return values.
360 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_Sparc64);
361
362 SDValue Glue;
363 SmallVector<SDValue, 4> RetOps(1, Chain);
364
365 // The second operand on the return instruction is the return address offset.
366 // The return address is always %i7+8 with the 64-bit ABI.
367 RetOps.push_back(Elt: DAG.getConstant(Val: 8, DL, VT: MVT::i32));
368
369 // Copy the result values into the output registers.
370 for (unsigned i = 0; i != RVLocs.size(); ++i) {
371 CCValAssign &VA = RVLocs[i];
372 assert(VA.isRegLoc() && "Can only return in registers!");
373 SDValue OutVal = OutVals[i];
374
375 // Integer return values must be sign or zero extended by the callee.
376 switch (VA.getLocInfo()) {
377 case CCValAssign::Full: break;
378 case CCValAssign::SExt:
379 OutVal = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
380 break;
381 case CCValAssign::ZExt:
382 OutVal = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
383 break;
384 case CCValAssign::AExt:
385 OutVal = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
386 break;
387 default:
388 llvm_unreachable("Unknown loc info!");
389 }
390
391 // The custom bit on an i32 return value indicates that it should be passed
392 // in the high bits of the register.
393 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
394 OutVal = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: OutVal,
395 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
396
397 // The next value may go in the low bits of the same register.
398 // Handle both at once.
399 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
400 SDValue NV = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i64, Operand: OutVals[i+1]);
401 OutVal = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i64, N1: OutVal, N2: NV);
402 // Skip the next value, it's already done.
403 ++i;
404 }
405 }
406
407 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: OutVal, Glue);
408
409 // Guarantee that all emitted copies are stuck together with flags.
410 Glue = Chain.getValue(R: 1);
411 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
412 }
413
414 RetOps[0] = Chain; // Update chain.
415
416 // Add the flag if we have it.
417 if (Glue.getNode())
418 RetOps.push_back(Elt: Glue);
419
420 return DAG.getNode(Opcode: SPISD::RET_GLUE, DL, VT: MVT::Other, Ops: RetOps);
421}
422
423SDValue SparcTargetLowering::LowerFormalArguments(
424 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
425 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
426 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
427 if (Subtarget->is64Bit())
428 return LowerFormalArguments_64(Chain, CallConv, isVarArg: IsVarArg, Ins,
429 dl: DL, DAG, InVals);
430 return LowerFormalArguments_32(Chain, CallConv, isVarArg: IsVarArg, Ins,
431 dl: DL, DAG, InVals);
432}
433
434/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
435/// passed in either one or two GPRs, including FP values. TODO: we should
436/// pass FP values in FP registers for fastcc functions.
437SDValue SparcTargetLowering::LowerFormalArguments_32(
438 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
439 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
440 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
441 MachineFunction &MF = DAG.getMachineFunction();
442 MachineRegisterInfo &RegInfo = MF.getRegInfo();
443 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
444 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
445
446 // Assign locations to all of the incoming arguments.
447 SmallVector<CCValAssign, 16> ArgLocs;
448 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
449 *DAG.getContext());
450 CCInfo.AnalyzeFormalArguments(Ins, Fn: CC_Sparc32);
451
452 const unsigned StackOffset = 92;
453 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
454
455 unsigned InIdx = 0;
456 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
457 CCValAssign &VA = ArgLocs[i];
458 EVT LocVT = VA.getLocVT();
459
460 if (Ins[InIdx].Flags.isSRet()) {
461 if (InIdx != 0)
462 report_fatal_error(reason: "sparc only supports sret on the first parameter");
463 // Get SRet from [%fp+64].
464 int FrameIdx = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: 64, IsImmutable: true);
465 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
466 SDValue Arg =
467 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
468 InVals.push_back(Elt: Arg);
469 continue;
470 }
471
472 SDValue Arg;
473 if (VA.isRegLoc()) {
474 if (VA.needsCustom()) {
475 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
476
477 Register VRegHi = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
478 MF.getRegInfo().addLiveIn(Reg: VA.getLocReg(), vreg: VRegHi);
479 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, Reg: VRegHi, VT: MVT::i32);
480
481 assert(i+1 < e);
482 CCValAssign &NextVA = ArgLocs[++i];
483
484 SDValue LoVal;
485 if (NextVA.isMemLoc()) {
486 int FrameIdx = MF.getFrameInfo().
487 CreateFixedObject(Size: 4, SPOffset: StackOffset+NextVA.getLocMemOffset(),IsImmutable: true);
488 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
489 LoVal = DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
490 } else {
491 Register loReg = MF.addLiveIn(PReg: NextVA.getLocReg(),
492 RC: &SP::IntRegsRegClass);
493 LoVal = DAG.getCopyFromReg(Chain, dl, Reg: loReg, VT: MVT::i32);
494 }
495
496 if (IsLittleEndian)
497 std::swap(a&: LoVal, b&: HiVal);
498
499 SDValue WholeValue =
500 DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: LoVal, N2: HiVal);
501 WholeValue = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getLocVT(), Operand: WholeValue);
502 InVals.push_back(Elt: WholeValue);
503 continue;
504 }
505 Register VReg = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
506 MF.getRegInfo().addLiveIn(Reg: VA.getLocReg(), vreg: VReg);
507 Arg = DAG.getCopyFromReg(Chain, dl, Reg: VReg, VT: MVT::i32);
508 if (VA.getLocInfo() != CCValAssign::Indirect) {
509 if (VA.getLocVT() == MVT::f32)
510 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::f32, Operand: Arg);
511 else if (VA.getLocVT() != MVT::i32) {
512 Arg = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: MVT::i32, N1: Arg,
513 N2: DAG.getValueType(VA.getLocVT()));
514 Arg = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getLocVT(), Operand: Arg);
515 }
516 InVals.push_back(Elt: Arg);
517 continue;
518 }
519 } else {
520 assert(VA.isMemLoc());
521
522 unsigned Offset = VA.getLocMemOffset() + StackOffset;
523
524 if (VA.needsCustom()) {
525 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
526 // If it is double-word aligned, just load.
527 if (Offset % 8 == 0) {
528 int FI = MF.getFrameInfo().CreateFixedObject(Size: 8, SPOffset: Offset, IsImmutable: true);
529 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
530 SDValue Load = DAG.getLoad(VT: VA.getValVT(), dl, Chain, Ptr: FIPtr,
531 PtrInfo: MachinePointerInfo());
532 InVals.push_back(Elt: Load);
533 continue;
534 }
535
536 int FI = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: Offset, IsImmutable: true);
537 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
538 SDValue HiVal =
539 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
540 int FI2 = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: Offset + 4, IsImmutable: true);
541 SDValue FIPtr2 = DAG.getFrameIndex(FI: FI2, VT: PtrVT);
542
543 SDValue LoVal =
544 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr2, PtrInfo: MachinePointerInfo());
545
546 if (IsLittleEndian)
547 std::swap(a&: LoVal, b&: HiVal);
548
549 SDValue WholeValue =
550 DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: LoVal, N2: HiVal);
551 WholeValue = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getValVT(), Operand: WholeValue);
552 InVals.push_back(Elt: WholeValue);
553 continue;
554 }
555
556 int FI = MF.getFrameInfo().CreateFixedObject(Size: LocVT.getSizeInBits() / 8,
557 SPOffset: Offset, IsImmutable: true);
558 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
559 SDValue Load = DAG.getLoad(VT: LocVT, dl, Chain, Ptr: FIPtr,
560 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI));
561 if (VA.getLocInfo() != CCValAssign::Indirect) {
562 InVals.push_back(Elt: Load);
563 continue;
564 }
565 Arg = Load;
566 }
567
568 assert(VA.getLocInfo() == CCValAssign::Indirect);
569
570 SDValue ArgValue =
571 DAG.getLoad(VT: VA.getValVT(), dl, Chain, Ptr: Arg, PtrInfo: MachinePointerInfo());
572 InVals.push_back(Elt: ArgValue);
573
574 unsigned ArgIndex = Ins[InIdx].OrigArgIndex;
575 assert(Ins[InIdx].PartOffset == 0);
576 while (i + 1 != e && Ins[InIdx + 1].OrigArgIndex == ArgIndex) {
577 CCValAssign &PartVA = ArgLocs[i + 1];
578 unsigned PartOffset = Ins[InIdx + 1].PartOffset;
579 SDValue Address = DAG.getMemBasePlusOffset(
580 Base: ArgValue, Offset: TypeSize::getFixed(ExactSize: PartOffset), DL: dl);
581 InVals.push_back(Elt: DAG.getLoad(VT: PartVA.getValVT(), dl, Chain, Ptr: Address,
582 PtrInfo: MachinePointerInfo()));
583 ++i;
584 ++InIdx;
585 }
586 }
587
588 if (MF.getFunction().hasStructRetAttr()) {
589 // Copy the SRet Argument to SRetReturnReg.
590 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
591 Register Reg = SFI->getSRetReturnReg();
592 if (!Reg) {
593 Reg = MF.getRegInfo().createVirtualRegister(RegClass: &SP::IntRegsRegClass);
594 SFI->setSRetReturnReg(Reg);
595 }
596 SDValue Copy = DAG.getCopyToReg(Chain: DAG.getEntryNode(), dl, Reg, N: InVals[0]);
597 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Copy, N2: Chain);
598 }
599
600 // Store remaining ArgRegs to the stack if this is a varargs function.
601 if (isVarArg) {
602 static const MCPhysReg ArgRegs[] = {
603 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
604 };
605 unsigned NumAllocated = CCInfo.getFirstUnallocated(Regs: ArgRegs);
606 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
607 unsigned ArgOffset = CCInfo.getStackSize();
608 if (NumAllocated == 6)
609 ArgOffset += StackOffset;
610 else {
611 assert(!ArgOffset);
612 ArgOffset = 68+4*NumAllocated;
613 }
614
615 // Remember the vararg offset for the va_start implementation.
616 FuncInfo->setVarArgsFrameOffset(ArgOffset);
617
618 std::vector<SDValue> OutChains;
619
620 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
621 Register VReg = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
622 MF.getRegInfo().addLiveIn(Reg: *CurArgReg, vreg: VReg);
623 SDValue Arg = DAG.getCopyFromReg(Chain: DAG.getRoot(), dl, Reg: VReg, VT: MVT::i32);
624
625 int FrameIdx = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: ArgOffset,
626 IsImmutable: true);
627 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
628
629 OutChains.push_back(
630 x: DAG.getStore(Chain: DAG.getRoot(), dl, Val: Arg, Ptr: FIPtr, PtrInfo: MachinePointerInfo()));
631 ArgOffset += 4;
632 }
633
634 if (!OutChains.empty()) {
635 OutChains.push_back(x: Chain);
636 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
637 }
638 }
639
640 return Chain;
641}
642
643// Lower formal arguments for the 64 bit ABI.
644SDValue SparcTargetLowering::LowerFormalArguments_64(
645 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
646 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
647 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
648 MachineFunction &MF = DAG.getMachineFunction();
649
650 // Analyze arguments according to CC_Sparc64.
651 SmallVector<CCValAssign, 16> ArgLocs;
652 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
653 *DAG.getContext());
654 CCInfo.AnalyzeFormalArguments(Ins, Fn: CC_Sparc64);
655
656 // The argument array begins at %fp+BIAS+128, after the register save area.
657 const unsigned ArgArea = 128;
658
659 for (const CCValAssign &VA : ArgLocs) {
660 if (VA.isRegLoc()) {
661 // This argument is passed in a register.
662 // All integer register arguments are promoted by the caller to i64.
663
664 // Create a virtual register for the promoted live-in value.
665 Register VReg = MF.addLiveIn(PReg: VA.getLocReg(),
666 RC: getRegClassFor(VT: VA.getLocVT()));
667 SDValue Arg = DAG.getCopyFromReg(Chain, dl: DL, Reg: VReg, VT: VA.getLocVT());
668
669 // Get the high bits for i32 struct elements.
670 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
671 Arg = DAG.getNode(Opcode: ISD::SRL, DL, VT: VA.getLocVT(), N1: Arg,
672 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
673
674 // The caller promoted the argument, so insert an Assert?ext SDNode so we
675 // won't promote the value again in this function.
676 switch (VA.getLocInfo()) {
677 case CCValAssign::SExt:
678 Arg = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: Arg,
679 N2: DAG.getValueType(VA.getValVT()));
680 break;
681 case CCValAssign::ZExt:
682 Arg = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: Arg,
683 N2: DAG.getValueType(VA.getValVT()));
684 break;
685 default:
686 break;
687 }
688
689 // Truncate the register down to the argument type.
690 if (VA.isExtInLoc())
691 Arg = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: Arg);
692
693 InVals.push_back(Elt: Arg);
694 continue;
695 }
696
697 // The registers are exhausted. This argument was passed on the stack.
698 assert(VA.isMemLoc());
699 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
700 // beginning of the arguments area at %fp+BIAS+128.
701 unsigned Offset = VA.getLocMemOffset() + ArgArea;
702 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
703 // Adjust offset for extended arguments, SPARC is big-endian.
704 // The caller will have written the full slot with extended bytes, but we
705 // prefer our own extending loads.
706 if (VA.isExtInLoc())
707 Offset += 8 - ValSize;
708 int FI = MF.getFrameInfo().CreateFixedObject(Size: ValSize, SPOffset: Offset, IsImmutable: true);
709 InVals.push_back(
710 Elt: DAG.getLoad(VT: VA.getValVT(), dl: DL, Chain,
711 Ptr: DAG.getFrameIndex(FI, VT: getPointerTy(DL: MF.getDataLayout())),
712 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
713 }
714
715 if (!IsVarArg)
716 return Chain;
717
718 // This function takes variable arguments, some of which may have been passed
719 // in registers %i0-%i5. Variable floating point arguments are never passed
720 // in floating point registers. They go on %i0-%i5 or on the stack like
721 // integer arguments.
722 //
723 // The va_start intrinsic needs to know the offset to the first variable
724 // argument.
725 unsigned ArgOffset = CCInfo.getStackSize();
726 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
727 // Skip the 128 bytes of register save area.
728 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
729 Subtarget->getStackPointerBias());
730
731 // Save the variable arguments that were passed in registers.
732 // The caller is required to reserve stack space for 6 arguments regardless
733 // of how many arguments were actually passed.
734 SmallVector<SDValue, 8> OutChains;
735 for (; ArgOffset < 6*8; ArgOffset += 8) {
736 Register VReg = MF.addLiveIn(PReg: SP::I0 + ArgOffset/8, RC: &SP::I64RegsRegClass);
737 SDValue VArg = DAG.getCopyFromReg(Chain, dl: DL, Reg: VReg, VT: MVT::i64);
738 int FI = MF.getFrameInfo().CreateFixedObject(Size: 8, SPOffset: ArgOffset + ArgArea, IsImmutable: true);
739 auto PtrVT = getPointerTy(DL: MF.getDataLayout());
740 OutChains.push_back(
741 Elt: DAG.getStore(Chain, dl: DL, Val: VArg, Ptr: DAG.getFrameIndex(FI, VT: PtrVT),
742 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
743 }
744
745 if (!OutChains.empty())
746 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: OutChains);
747
748 return Chain;
749}
750
751// Check whether any of the argument registers are reserved
752static bool isAnyArgRegReserved(const SparcRegisterInfo *TRI,
753 const MachineFunction &MF) {
754 // The register window design means that outgoing parameters at O*
755 // will appear in the callee as I*.
756 // Be conservative and check both sides of the register names.
757 bool Outgoing =
758 llvm::any_of(Range: SP::GPROutgoingArgRegClass, P: [TRI, &MF](MCPhysReg r) {
759 return TRI->isReservedReg(MF, Reg: r);
760 });
761 bool Incoming =
762 llvm::any_of(Range: SP::GPRIncomingArgRegClass, P: [TRI, &MF](MCPhysReg r) {
763 return TRI->isReservedReg(MF, Reg: r);
764 });
765 return Outgoing || Incoming;
766}
767
768static void emitReservedArgRegCallError(const MachineFunction &MF) {
769 const Function &F = MF.getFunction();
770 F.getContext().diagnose(DI: DiagnosticInfoUnsupported{
771 F, ("SPARC doesn't support"
772 " function calls if any of the argument registers is reserved.")});
773}
774
775SDValue
776SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
777 SmallVectorImpl<SDValue> &InVals) const {
778 if (Subtarget->is64Bit())
779 return LowerCall_64(CLI, InVals);
780 return LowerCall_32(CLI, InVals);
781}
782
783static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
784 const CallBase *Call) {
785 if (Call)
786 return Call->hasFnAttr(Kind: Attribute::ReturnsTwice);
787
788 const Function *CalleeFn = nullptr;
789 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
790 CalleeFn = dyn_cast<Function>(Val: G->getGlobal());
791 } else if (ExternalSymbolSDNode *E =
792 dyn_cast<ExternalSymbolSDNode>(Val&: Callee)) {
793 const Function &Fn = DAG.getMachineFunction().getFunction();
794 const Module *M = Fn.getParent();
795 const char *CalleeName = E->getSymbol();
796 CalleeFn = M->getFunction(Name: CalleeName);
797 }
798
799 if (!CalleeFn)
800 return false;
801 return CalleeFn->hasFnAttribute(Kind: Attribute::ReturnsTwice);
802}
803
804/// IsEligibleForTailCallOptimization - Check whether the call is eligible
805/// for tail call optimization.
806bool SparcTargetLowering::IsEligibleForTailCallOptimization(
807 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const {
808
809 auto &Outs = CLI.Outs;
810 auto &Caller = MF.getFunction();
811
812 // Do not tail call opt functions with "disable-tail-calls" attribute.
813 if (Caller.getFnAttribute(Kind: "disable-tail-calls").getValueAsString() == "true")
814 return false;
815
816 // Do not tail call opt if the stack is used to pass parameters.
817 // 64-bit targets have a slightly higher limit since the ABI requires
818 // to allocate some space even when all the parameters fit inside registers.
819 unsigned StackSizeLimit = Subtarget->is64Bit() ? 48 : 0;
820 if (CCInfo.getStackSize() > StackSizeLimit)
821 return false;
822
823 // Do not tail call opt if either the callee or caller returns
824 // a struct and the other does not.
825 if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
826 return false;
827
828 // Byval parameters hand the function a pointer directly into the stack area
829 // we want to reuse during a tail call.
830 for (auto &Arg : Outs)
831 if (Arg.Flags.isByVal())
832 return false;
833
834 return true;
835}
836
837// Lower a call for the 32-bit ABI.
838SDValue
839SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
840 SmallVectorImpl<SDValue> &InVals) const {
841 SelectionDAG &DAG = CLI.DAG;
842 SDLoc &dl = CLI.DL;
843 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
844 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
845 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
846 SDValue Chain = CLI.Chain;
847 SDValue Callee = CLI.Callee;
848 bool &isTailCall = CLI.IsTailCall;
849 CallingConv::ID CallConv = CLI.CallConv;
850 bool isVarArg = CLI.IsVarArg;
851 MachineFunction &MF = DAG.getMachineFunction();
852 LLVMContext &Ctx = *DAG.getContext();
853 EVT PtrVT = getPointerTy(DL: MF.getDataLayout());
854
855 // Analyze operands of the call, assigning locations to each operand.
856 SmallVector<CCValAssign, 16> ArgLocs;
857 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
858 *DAG.getContext());
859 CCInfo.AnalyzeCallOperands(Outs, Fn: CC_Sparc32);
860
861 isTailCall = isTailCall && IsEligibleForTailCallOptimization(
862 CCInfo, CLI, MF&: DAG.getMachineFunction());
863
864 // Get the size of the outgoing arguments stack space requirement.
865 unsigned ArgsSize = CCInfo.getStackSize();
866
867 // Keep stack frames 8-byte aligned.
868 ArgsSize = (ArgsSize+7) & ~7;
869
870 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
871
872 // Create local copies for byval args.
873 SmallVector<SDValue, 8> ByValArgs;
874 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
875 ISD::ArgFlagsTy Flags = Outs[i].Flags;
876 if (!Flags.isByVal())
877 continue;
878
879 SDValue Arg = OutVals[i];
880 unsigned Size = Flags.getByValSize();
881 Align Alignment = Flags.getNonZeroByValAlign();
882
883 if (Size > 0U) {
884 int FI = MFI.CreateStackObject(Size, Alignment, isSpillSlot: false);
885 SDValue FIPtr = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
886 SDValue SizeNode = DAG.getConstant(Val: Size, DL: dl, VT: MVT::i32);
887
888 Chain =
889 DAG.getMemcpy(Chain, dl, Dst: FIPtr, Src: Arg, Size: SizeNode, DstAlign: Alignment, SrcAlign: Alignment,
890 isVol: false, // isVolatile,
891 AlwaysInline: (Size <= 32), // AlwaysInline if size <= 32,
892 /*CI=*/nullptr, OverrideTailCall: std::nullopt, DstPtrInfo: MachinePointerInfo(),
893 SrcPtrInfo: MachinePointerInfo());
894 ByValArgs.push_back(Elt: FIPtr);
895 }
896 else {
897 SDValue nullVal;
898 ByValArgs.push_back(Elt: nullVal);
899 }
900 }
901
902 assert(!isTailCall || ArgsSize == 0);
903
904 if (!isTailCall)
905 Chain = DAG.getCALLSEQ_START(Chain, InSize: ArgsSize, OutSize: 0, DL: dl);
906
907 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
908 SmallVector<SDValue, 8> MemOpChains;
909
910 const unsigned StackOffset = 92;
911 bool hasStructRetAttr = false;
912 unsigned SRetArgSize = 0;
913 // Walk the register/memloc assignments, inserting copies/loads.
914 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
915 i != e;
916 ++i, ++realArgIdx) {
917 CCValAssign &VA = ArgLocs[i];
918 SDValue Arg = OutVals[realArgIdx];
919
920 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
921
922 // Use local copy if it is a byval arg.
923 if (Flags.isByVal()) {
924 Arg = ByValArgs[byvalArgIdx++];
925 if (!Arg) {
926 continue;
927 }
928 }
929
930 // Promote the value if needed.
931 switch (VA.getLocInfo()) {
932 default: llvm_unreachable("Unknown loc info!");
933 case CCValAssign::Full:
934 case CCValAssign::Indirect:
935 break;
936 case CCValAssign::SExt:
937 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
938 break;
939 case CCValAssign::ZExt:
940 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
941 break;
942 case CCValAssign::AExt:
943 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
944 break;
945 case CCValAssign::BCvt:
946 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getLocVT(), Operand: Arg);
947 break;
948 }
949
950 if (Flags.isSRet()) {
951 assert(VA.needsCustom());
952
953 if (isTailCall)
954 continue;
955
956 // store SRet argument in %sp+64
957 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
958 SDValue PtrOff = DAG.getIntPtrConstant(Val: 64, DL: dl);
959 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
960 MemOpChains.push_back(
961 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
962 hasStructRetAttr = true;
963 // sret only allowed on first argument
964 assert(Outs[realArgIdx].OrigArgIndex == 0);
965 SRetArgSize =
966 DAG.getDataLayout().getTypeAllocSize(Ty: CLI.getArgs()[0].IndirectType);
967 continue;
968 }
969
970 if (VA.needsCustom()) {
971 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
972
973 if (VA.isMemLoc()) {
974 unsigned Offset = VA.getLocMemOffset() + StackOffset;
975 // if it is double-word aligned, just store.
976 if (Offset % 8 == 0) {
977 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
978 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
979 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
980 MemOpChains.push_back(
981 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
982 continue;
983 }
984 }
985
986 if (VA.getLocVT() == MVT::f64) {
987 // Move from the float value from float registers into the
988 // integer registers.
989 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val&: Arg))
990 Arg = bitcastConstantFPToInt(C, DL: dl, DAG);
991 else
992 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::v2i32, Operand: Arg);
993 }
994
995 SDValue Part0 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: MVT::i32,
996 N1: Arg,
997 N2: DAG.getConstant(Val: 0, DL: dl, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
998 SDValue Part1 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: MVT::i32,
999 N1: Arg,
1000 N2: DAG.getConstant(Val: 1, DL: dl, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
1001
1002 if (VA.isRegLoc()) {
1003 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Part0));
1004 assert(i+1 != e);
1005 CCValAssign &NextVA = ArgLocs[++i];
1006 if (NextVA.isRegLoc()) {
1007 RegsToPass.push_back(Elt: std::make_pair(x: NextVA.getLocReg(), y&: Part1));
1008 } else {
1009 // Store the second part in stack.
1010 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
1011 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1012 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
1013 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1014 MemOpChains.push_back(
1015 Elt: DAG.getStore(Chain, dl, Val: Part1, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1016 }
1017 } else {
1018 unsigned Offset = VA.getLocMemOffset() + StackOffset;
1019 // Store the first part.
1020 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1021 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
1022 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1023 MemOpChains.push_back(
1024 Elt: DAG.getStore(Chain, dl, Val: Part0, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1025 // Store the second part.
1026 PtrOff = DAG.getIntPtrConstant(Val: Offset + 4, DL: dl);
1027 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1028 MemOpChains.push_back(
1029 Elt: DAG.getStore(Chain, dl, Val: Part1, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1030 }
1031 continue;
1032 }
1033
1034 if (VA.getLocInfo() == CCValAssign::Indirect) {
1035 // Store the argument in a stack slot and pass its address.
1036 unsigned ArgIndex = Outs[realArgIdx].OrigArgIndex;
1037 assert(Outs[realArgIdx].PartOffset == 0);
1038
1039 EVT SlotVT;
1040 if (i + 1 != e && Outs[realArgIdx + 1].OrigArgIndex == ArgIndex) {
1041 Type *OrigArgType = CLI.Args[ArgIndex].Ty;
1042 EVT OrigArgVT = getValueType(DL: MF.getDataLayout(), Ty: OrigArgType);
1043 MVT PartVT =
1044 getRegisterTypeForCallingConv(Context&: Ctx, CC: CLI.CallConv, VT: OrigArgVT);
1045 unsigned N =
1046 getNumRegistersForCallingConv(Context&: Ctx, CC: CLI.CallConv, VT: OrigArgVT);
1047 SlotVT = EVT::getIntegerVT(Context&: Ctx, BitWidth: PartVT.getSizeInBits() * N);
1048 } else {
1049 SlotVT = Outs[realArgIdx].VT;
1050 }
1051
1052 SDValue SpillSlot = DAG.CreateStackTemporary(VT: SlotVT);
1053 int FI = cast<FrameIndexSDNode>(Val&: SpillSlot)->getIndex();
1054 MemOpChains.push_back(
1055 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: SpillSlot,
1056 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
1057 // If the original argument was split (e.g. f128), we need
1058 // to store all parts of it here (and pass just one address).
1059 while (i + 1 != e && Outs[realArgIdx + 1].OrigArgIndex == ArgIndex) {
1060 SDValue PartValue = OutVals[realArgIdx + 1];
1061 unsigned PartOffset = Outs[realArgIdx + 1].PartOffset;
1062 SDValue Address = DAG.getMemBasePlusOffset(
1063 Base: DAG.getFrameIndex(FI, VT: PtrVT), Offset: TypeSize::getFixed(ExactSize: PartOffset), DL: dl);
1064 MemOpChains.push_back(
1065 Elt: DAG.getStore(Chain, dl, Val: PartValue, Ptr: Address,
1066 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
1067 assert((PartOffset + PartValue.getValueType().getStoreSize() <=
1068 SlotVT.getStoreSize()) &&
1069 "Not enough space for argument part!");
1070 ++i;
1071 ++realArgIdx;
1072 }
1073
1074 Arg = SpillSlot;
1075 }
1076
1077 // Arguments that can be passed on register must be kept at
1078 // RegsToPass vector
1079 if (VA.isRegLoc()) {
1080 if (VA.getLocVT() != MVT::f32) {
1081 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1082 continue;
1083 }
1084 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: Arg);
1085 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1086 continue;
1087 }
1088
1089 assert(VA.isMemLoc());
1090
1091 // Create a store off the stack pointer for this argument.
1092 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1093 SDValue PtrOff = DAG.getIntPtrConstant(Val: VA.getLocMemOffset() + StackOffset,
1094 DL: dl);
1095 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1096 MemOpChains.push_back(
1097 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1098 }
1099
1100
1101 // Emit all stores, make sure the occur before any copies into physregs.
1102 if (!MemOpChains.empty())
1103 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains);
1104
1105 // Build a sequence of copy-to-reg nodes chained together with token
1106 // chain and flag operands which copy the outgoing args into registers.
1107 // The InGlue in necessary since all emitted instructions must be
1108 // stuck together.
1109 SDValue InGlue;
1110 for (const auto &[OrigReg, N] : RegsToPass) {
1111 Register Reg = isTailCall ? OrigReg : toCallerWindow(Reg: OrigReg);
1112 Chain = DAG.getCopyToReg(Chain, dl, Reg, N, Glue: InGlue);
1113 InGlue = Chain.getValue(R: 1);
1114 }
1115
1116 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, Call: CLI.CB);
1117
1118 // If the callee is a GlobalAddress node (quite common, every direct call is)
1119 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1120 // Likewise ExternalSymbol -> TargetExternalSymbol.
1121 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
1122 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL: dl, VT: MVT::i32, offset: 0);
1123 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee))
1124 Callee = DAG.getTargetExternalSymbol(Sym: E->getSymbol(), VT: MVT::i32);
1125
1126 // Returns a chain & a flag for retval copy to use
1127 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1128 SmallVector<SDValue, 8> Ops;
1129 Ops.push_back(Elt: Chain);
1130 Ops.push_back(Elt: Callee);
1131 if (hasStructRetAttr)
1132 Ops.push_back(Elt: DAG.getTargetConstant(Val: SRetArgSize, DL: dl, VT: MVT::i32));
1133 for (const auto &[OrigReg, N] : RegsToPass) {
1134 Register Reg = isTailCall ? OrigReg : toCallerWindow(Reg: OrigReg);
1135 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
1136 }
1137
1138 // Add a register mask operand representing the call-preserved registers.
1139 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1140 const uint32_t *Mask =
1141 ((hasReturnsTwice)
1142 ? TRI->getRTCallPreservedMask(CC: CallConv)
1143 : TRI->getCallPreservedMask(MF: DAG.getMachineFunction(), CC: CallConv));
1144
1145 if (isAnyArgRegReserved(TRI, MF))
1146 emitReservedArgRegCallError(MF);
1147
1148 assert(Mask && "Missing call preserved mask for calling convention");
1149 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
1150
1151 if (InGlue.getNode())
1152 Ops.push_back(Elt: InGlue);
1153
1154 if (isTailCall) {
1155 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
1156 return DAG.getNode(Opcode: SPISD::TAIL_CALL, DL: dl, VT: MVT::Other, Ops);
1157 }
1158
1159 Chain = DAG.getNode(Opcode: SPISD::CALL, DL: dl, VTList: NodeTys, Ops);
1160 InGlue = Chain.getValue(R: 1);
1161
1162 Chain = DAG.getCALLSEQ_END(Chain, Size1: ArgsSize, Size2: 0, Glue: InGlue, DL: dl);
1163 InGlue = Chain.getValue(R: 1);
1164
1165 // Assign locations to each value returned by this call.
1166 SmallVector<CCValAssign, 16> RVLocs;
1167 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1168 *DAG.getContext());
1169
1170 RVInfo.AnalyzeCallResult(Ins, Fn: RetCC_Sparc32);
1171
1172 // Copy all of the result registers out of their specified physreg.
1173 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1174 assert(RVLocs[i].isRegLoc() && "Can only return in registers!");
1175 if (RVLocs[i].getLocVT() == MVT::v2i32) {
1176 SDValue Vec = DAG.getNode(Opcode: ISD::UNDEF, DL: dl, VT: MVT::v2i32);
1177 SDValue Lo = DAG.getCopyFromReg(
1178 Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i++].getLocReg()), VT: MVT::i32, Glue: InGlue);
1179 Chain = Lo.getValue(R: 1);
1180 InGlue = Lo.getValue(R: 2);
1181 Vec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: MVT::v2i32, N1: Vec, N2: Lo,
1182 N3: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
1183 SDValue Hi = DAG.getCopyFromReg(
1184 Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i].getLocReg()), VT: MVT::i32, Glue: InGlue);
1185 Chain = Hi.getValue(R: 1);
1186 InGlue = Hi.getValue(R: 2);
1187 Vec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: MVT::v2i32, N1: Vec, N2: Hi,
1188 N3: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i32));
1189 InVals.push_back(Elt: Vec);
1190 } else {
1191 Chain =
1192 DAG.getCopyFromReg(Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i].getLocReg()),
1193 VT: RVLocs[i].getValVT(), Glue: InGlue)
1194 .getValue(R: 1);
1195 InGlue = Chain.getValue(R: 2);
1196 InVals.push_back(Elt: Chain.getValue(R: 0));
1197 }
1198 }
1199
1200 return Chain;
1201}
1202
1203// FIXME? Maybe this could be a TableGen attribute on some registers and
1204// this table could be generated automatically from RegInfo.
1205Register SparcTargetLowering::getRegisterByName(const char* RegName, LLT VT,
1206 const MachineFunction &MF) const {
1207 Register Reg = StringSwitch<Register>(RegName)
1208 .Case(S: "i0", Value: SP::I0).Case(S: "i1", Value: SP::I1).Case(S: "i2", Value: SP::I2).Case(S: "i3", Value: SP::I3)
1209 .Case(S: "i4", Value: SP::I4).Case(S: "i5", Value: SP::I5).Case(S: "i6", Value: SP::I6).Case(S: "i7", Value: SP::I7)
1210 .Case(S: "o0", Value: SP::O0).Case(S: "o1", Value: SP::O1).Case(S: "o2", Value: SP::O2).Case(S: "o3", Value: SP::O3)
1211 .Case(S: "o4", Value: SP::O4).Case(S: "o5", Value: SP::O5).Case(S: "o6", Value: SP::O6).Case(S: "o7", Value: SP::O7)
1212 .Case(S: "l0", Value: SP::L0).Case(S: "l1", Value: SP::L1).Case(S: "l2", Value: SP::L2).Case(S: "l3", Value: SP::L3)
1213 .Case(S: "l4", Value: SP::L4).Case(S: "l5", Value: SP::L5).Case(S: "l6", Value: SP::L6).Case(S: "l7", Value: SP::L7)
1214 .Case(S: "g0", Value: SP::G0).Case(S: "g1", Value: SP::G1).Case(S: "g2", Value: SP::G2).Case(S: "g3", Value: SP::G3)
1215 .Case(S: "g4", Value: SP::G4).Case(S: "g5", Value: SP::G5).Case(S: "g6", Value: SP::G6).Case(S: "g7", Value: SP::G7)
1216 .Default(Value: 0);
1217
1218 // If we're directly referencing register names
1219 // (e.g in GCC C extension `register int r asm("g1");`),
1220 // make sure that said register is in the reserve list.
1221 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1222 if (!TRI->isReservedReg(MF, Reg))
1223 Reg = Register();
1224
1225 return Reg;
1226}
1227
1228// Fixup floating point arguments in the ... part of a varargs call.
1229//
1230// The SPARC v9 ABI requires that floating point arguments are treated the same
1231// as integers when calling a varargs function. This does not apply to the
1232// fixed arguments that are part of the function's prototype.
1233//
1234// This function post-processes a CCValAssign array created by
1235// AnalyzeCallOperands().
1236static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1237 ArrayRef<ISD::OutputArg> Outs) {
1238 for (CCValAssign &VA : ArgLocs) {
1239 MVT ValTy = VA.getLocVT();
1240 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1241 // varargs functions.
1242 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1243 continue;
1244 // The fixed arguments to a varargs function still go in FP registers.
1245 if (!Outs[VA.getValNo()].Flags.isVarArg())
1246 continue;
1247
1248 // This floating point argument should be reassigned.
1249 // Determine the offset into the argument array.
1250 Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1251 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1252 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1253 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1254
1255 if (Offset < 6*8) {
1256 // This argument should go in %i0-%i5.
1257 unsigned IReg = SP::I0 + Offset/8;
1258 if (ValTy == MVT::f64)
1259 // Full register, just bitconvert into i64.
1260 VA = CCValAssign::getReg(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Reg: IReg, LocVT: MVT::i64,
1261 HTP: CCValAssign::BCvt);
1262 else {
1263 assert(ValTy == MVT::f128 && "Unexpected type!");
1264 // Full register, just bitconvert into i128 -- We will lower this into
1265 // two i64s in LowerCall_64.
1266 VA = CCValAssign::getCustomReg(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Reg: IReg,
1267 LocVT: MVT::i128, HTP: CCValAssign::BCvt);
1268 }
1269 } else {
1270 // This needs to go to memory, we're out of integer registers.
1271 VA = CCValAssign::getMem(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Offset,
1272 LocVT: VA.getLocVT(), HTP: VA.getLocInfo());
1273 }
1274 }
1275}
1276
1277// Lower a call for the 64-bit ABI.
1278SDValue
1279SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1280 SmallVectorImpl<SDValue> &InVals) const {
1281 SelectionDAG &DAG = CLI.DAG;
1282 SDLoc DL = CLI.DL;
1283 SDValue Chain = CLI.Chain;
1284 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
1285 MachineFunction &MF = DAG.getMachineFunction();
1286
1287 // Analyze operands of the call, assigning locations to each operand.
1288 SmallVector<CCValAssign, 16> ArgLocs;
1289 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1290 *DAG.getContext());
1291 CCInfo.AnalyzeCallOperands(Outs: CLI.Outs, Fn: CC_Sparc64);
1292
1293 CLI.IsTailCall = CLI.IsTailCall && IsEligibleForTailCallOptimization(
1294 CCInfo, CLI, MF&: DAG.getMachineFunction());
1295
1296 // Get the size of the outgoing arguments stack space requirement.
1297 // The stack offset computed by CC_Sparc64 includes all arguments.
1298 // Called functions expect 6 argument words to exist in the stack frame, used
1299 // or not.
1300 unsigned StackReserved = 6 * 8u;
1301 unsigned ArgsSize = std::max<unsigned>(a: StackReserved, b: CCInfo.getStackSize());
1302
1303 // Keep stack frames 16-byte aligned.
1304 ArgsSize = alignTo(Value: ArgsSize, Align: 16);
1305
1306 // Varargs calls require special treatment.
1307 if (CLI.IsVarArg)
1308 fixupVariableFloatArgs(ArgLocs, Outs: CLI.Outs);
1309
1310 assert(!CLI.IsTailCall || ArgsSize == StackReserved);
1311
1312 // Adjust the stack pointer to make room for the arguments.
1313 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1314 // with more than 6 arguments.
1315 if (!CLI.IsTailCall)
1316 Chain = DAG.getCALLSEQ_START(Chain, InSize: ArgsSize, OutSize: 0, DL);
1317
1318 // Collect the set of registers to pass to the function and their values.
1319 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1320 // instruction.
1321 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
1322
1323 // Collect chains from all the memory opeations that copy arguments to the
1324 // stack. They must follow the stack pointer adjustment above and precede the
1325 // call instruction itself.
1326 SmallVector<SDValue, 8> MemOpChains;
1327
1328 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1329 const CCValAssign &VA = ArgLocs[i];
1330 SDValue Arg = CLI.OutVals[i];
1331
1332 // Promote the value if needed.
1333 switch (VA.getLocInfo()) {
1334 default:
1335 llvm_unreachable("Unknown location info!");
1336 case CCValAssign::Full:
1337 break;
1338 case CCValAssign::SExt:
1339 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1340 break;
1341 case CCValAssign::ZExt:
1342 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1343 break;
1344 case CCValAssign::AExt:
1345 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1346 break;
1347 case CCValAssign::BCvt:
1348 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1349 // SPARC does not support i128 natively. Lower it into two i64, see below.
1350 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1351 || VA.getLocVT() != MVT::i128)
1352 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: VA.getLocVT(), Operand: Arg);
1353 break;
1354 }
1355
1356 if (VA.isRegLoc()) {
1357 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1358 && VA.getLocVT() == MVT::i128) {
1359 // Store and reload into the integer register reg and reg+1.
1360 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1361 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1362 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: PtrVT);
1363 SDValue HiPtrOff = DAG.getIntPtrConstant(Val: StackOffset, DL);
1364 HiPtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: HiPtrOff);
1365 SDValue LoPtrOff = DAG.getIntPtrConstant(Val: StackOffset + 8, DL);
1366 LoPtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: LoPtrOff);
1367
1368 // Store to %sp+BIAS+128+Offset
1369 SDValue Store =
1370 DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: HiPtrOff, PtrInfo: MachinePointerInfo());
1371 // Load into Reg and Reg+1
1372 SDValue Hi64 =
1373 DAG.getLoad(VT: MVT::i64, dl: DL, Chain: Store, Ptr: HiPtrOff, PtrInfo: MachinePointerInfo());
1374 SDValue Lo64 =
1375 DAG.getLoad(VT: MVT::i64, dl: DL, Chain: Store, Ptr: LoPtrOff, PtrInfo: MachinePointerInfo());
1376
1377 Register HiReg = VA.getLocReg();
1378 Register LoReg = VA.getLocReg() + 1;
1379 if (!CLI.IsTailCall) {
1380 HiReg = toCallerWindow(Reg: HiReg);
1381 LoReg = toCallerWindow(Reg: LoReg);
1382 }
1383
1384 RegsToPass.push_back(Elt: std::make_pair(x&: HiReg, y&: Hi64));
1385 RegsToPass.push_back(Elt: std::make_pair(x&: LoReg, y&: Lo64));
1386 continue;
1387 }
1388
1389 // The custom bit on an i32 return value indicates that it should be
1390 // passed in the high bits of the register.
1391 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1392 Arg = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: Arg,
1393 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
1394
1395 // The next value may go in the low bits of the same register.
1396 // Handle both at once.
1397 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1398 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1399 SDValue NV = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i64,
1400 Operand: CLI.OutVals[i+1]);
1401 Arg = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i64, N1: Arg, N2: NV);
1402 // Skip the next value, it's already done.
1403 ++i;
1404 }
1405 }
1406
1407 Register Reg = VA.getLocReg();
1408 if (!CLI.IsTailCall)
1409 Reg = toCallerWindow(Reg);
1410 RegsToPass.push_back(Elt: std::make_pair(x&: Reg, y&: Arg));
1411 continue;
1412 }
1413
1414 assert(VA.isMemLoc());
1415
1416 // Create a store off the stack pointer for this argument.
1417 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: PtrVT);
1418 // The argument area starts at %fp+BIAS+128 in the callee frame,
1419 // %sp+BIAS+128 in ours.
1420 SDValue PtrOff = DAG.getIntPtrConstant(Val: VA.getLocMemOffset() +
1421 Subtarget->getStackPointerBias() +
1422 128, DL);
1423 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: PtrOff);
1424 MemOpChains.push_back(
1425 Elt: DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1426 }
1427
1428 // Emit all stores, make sure they occur before the call.
1429 if (!MemOpChains.empty())
1430 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOpChains);
1431
1432 // Build a sequence of CopyToReg nodes glued together with token chain and
1433 // glue operands which copy the outgoing args into registers. The InGlue is
1434 // necessary since all emitted instructions must be stuck together in order
1435 // to pass the live physical registers.
1436 SDValue InGlue;
1437 for (const auto &[Reg, N] : RegsToPass) {
1438 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg, N, Glue: InGlue);
1439 InGlue = Chain.getValue(R: 1);
1440 }
1441
1442 // If the callee is a GlobalAddress node (quite common, every direct call is)
1443 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1444 // Likewise ExternalSymbol -> TargetExternalSymbol.
1445 SDValue Callee = CLI.Callee;
1446 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, Call: CLI.CB);
1447 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
1448 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL, VT: PtrVT, offset: 0);
1449 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee))
1450 Callee = DAG.getTargetExternalSymbol(Sym: E->getSymbol(), VT: PtrVT);
1451
1452 // Build the operands for the call instruction itself.
1453 SmallVector<SDValue, 8> Ops;
1454 Ops.push_back(Elt: Chain);
1455 Ops.push_back(Elt: Callee);
1456 for (const auto &[Reg, N] : RegsToPass)
1457 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
1458
1459 // Add a register mask operand representing the call-preserved registers.
1460 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1461 const uint32_t *Mask =
1462 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CC: CLI.CallConv)
1463 : TRI->getCallPreservedMask(MF: DAG.getMachineFunction(),
1464 CC: CLI.CallConv));
1465
1466 if (isAnyArgRegReserved(TRI, MF))
1467 emitReservedArgRegCallError(MF);
1468
1469 assert(Mask && "Missing call preserved mask for calling convention");
1470 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
1471
1472 // Make sure the CopyToReg nodes are glued to the call instruction which
1473 // consumes the registers.
1474 if (InGlue.getNode())
1475 Ops.push_back(Elt: InGlue);
1476
1477 // Now the call itself.
1478 if (CLI.IsTailCall) {
1479 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
1480 return DAG.getNode(Opcode: SPISD::TAIL_CALL, DL, VT: MVT::Other, Ops);
1481 }
1482 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1483 Chain = DAG.getNode(Opcode: SPISD::CALL, DL, VTList: NodeTys, Ops);
1484 InGlue = Chain.getValue(R: 1);
1485
1486 // Revert the stack pointer immediately after the call.
1487 Chain = DAG.getCALLSEQ_END(Chain, Size1: ArgsSize, Size2: 0, Glue: InGlue, DL);
1488 InGlue = Chain.getValue(R: 1);
1489
1490 // Now extract the return values. This is more or less the same as
1491 // LowerFormalArguments_64.
1492
1493 // Assign locations to each value returned by this call.
1494 SmallVector<CCValAssign, 16> RVLocs;
1495 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1496 *DAG.getContext());
1497
1498 // Set inreg flag manually for codegen generated library calls that
1499 // return float.
1500 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB)
1501 CLI.Ins[0].Flags.setInReg();
1502
1503 RVInfo.AnalyzeCallResult(Ins: CLI.Ins, Fn: RetCC_Sparc64);
1504
1505 // Copy all of the result registers out of their specified physreg.
1506 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1507 CCValAssign &VA = RVLocs[i];
1508 assert(VA.isRegLoc() && "Can only return in registers!");
1509 unsigned Reg = toCallerWindow(Reg: VA.getLocReg());
1510
1511 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1512 // reside in the same register in the high and low bits. Reuse the
1513 // CopyFromReg previous node to avoid duplicate copies.
1514 SDValue RV;
1515 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Val: Chain.getOperand(i: 1)))
1516 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1517 RV = Chain.getValue(R: 0);
1518
1519 // But usually we'll create a new CopyFromReg for a different register.
1520 if (!RV.getNode()) {
1521 RV = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: RVLocs[i].getLocVT(), Glue: InGlue);
1522 Chain = RV.getValue(R: 1);
1523 InGlue = Chain.getValue(R: 2);
1524 }
1525
1526 // Get the high bits for i32 struct elements.
1527 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1528 RV = DAG.getNode(Opcode: ISD::SRL, DL, VT: VA.getLocVT(), N1: RV,
1529 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
1530
1531 // The callee promoted the return value, so insert an Assert?ext SDNode so
1532 // we won't promote the value again in this function.
1533 switch (VA.getLocInfo()) {
1534 case CCValAssign::SExt:
1535 RV = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: RV,
1536 N2: DAG.getValueType(VA.getValVT()));
1537 break;
1538 case CCValAssign::ZExt:
1539 RV = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: RV,
1540 N2: DAG.getValueType(VA.getValVT()));
1541 break;
1542 default:
1543 break;
1544 }
1545
1546 // Truncate the register down to the return value type.
1547 if (VA.isExtInLoc())
1548 RV = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: RV);
1549
1550 InVals.push_back(Elt: RV);
1551 }
1552
1553 return Chain;
1554}
1555
1556//===----------------------------------------------------------------------===//
1557// TargetLowering Implementation
1558//===----------------------------------------------------------------------===//
1559
1560TargetLowering::AtomicExpansionKind
1561SparcTargetLowering::shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const {
1562 if (AI->getOperation() == AtomicRMWInst::Xchg &&
1563 AI->getType()->getPrimitiveSizeInBits() == 32)
1564 return AtomicExpansionKind::None; // Uses xchg instruction
1565
1566 return AtomicExpansionKind::CmpXChg;
1567}
1568
1569/// intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC
1570/// rcond condition.
1571static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC) {
1572 switch (CC) {
1573 default:
1574 llvm_unreachable("Unknown/unsigned integer condition code!");
1575 case ISD::SETEQ:
1576 return SPCC::REG_Z;
1577 case ISD::SETNE:
1578 return SPCC::REG_NZ;
1579 case ISD::SETLT:
1580 return SPCC::REG_LZ;
1581 case ISD::SETGT:
1582 return SPCC::REG_GZ;
1583 case ISD::SETLE:
1584 return SPCC::REG_LEZ;
1585 case ISD::SETGE:
1586 return SPCC::REG_GEZ;
1587 }
1588}
1589
1590/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1591/// condition.
1592static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1593 switch (CC) {
1594 default: llvm_unreachable("Unknown integer condition code!");
1595 case ISD::SETEQ: return SPCC::ICC_E;
1596 case ISD::SETNE: return SPCC::ICC_NE;
1597 case ISD::SETLT: return SPCC::ICC_L;
1598 case ISD::SETGT: return SPCC::ICC_G;
1599 case ISD::SETLE: return SPCC::ICC_LE;
1600 case ISD::SETGE: return SPCC::ICC_GE;
1601 case ISD::SETULT: return SPCC::ICC_CS;
1602 case ISD::SETULE: return SPCC::ICC_LEU;
1603 case ISD::SETUGT: return SPCC::ICC_GU;
1604 case ISD::SETUGE: return SPCC::ICC_CC;
1605 }
1606}
1607
1608/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1609/// FCC condition.
1610static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1611 switch (CC) {
1612 default: llvm_unreachable("Unknown fp condition code!");
1613 case ISD::SETEQ:
1614 case ISD::SETOEQ: return SPCC::FCC_E;
1615 case ISD::SETNE:
1616 case ISD::SETUNE: return SPCC::FCC_NE;
1617 case ISD::SETLT:
1618 case ISD::SETOLT: return SPCC::FCC_L;
1619 case ISD::SETGT:
1620 case ISD::SETOGT: return SPCC::FCC_G;
1621 case ISD::SETLE:
1622 case ISD::SETOLE: return SPCC::FCC_LE;
1623 case ISD::SETGE:
1624 case ISD::SETOGE: return SPCC::FCC_GE;
1625 case ISD::SETULT: return SPCC::FCC_UL;
1626 case ISD::SETULE: return SPCC::FCC_ULE;
1627 case ISD::SETUGT: return SPCC::FCC_UG;
1628 case ISD::SETUGE: return SPCC::FCC_UGE;
1629 case ISD::SETUO: return SPCC::FCC_U;
1630 case ISD::SETO: return SPCC::FCC_O;
1631 case ISD::SETONE: return SPCC::FCC_LG;
1632 case ISD::SETUEQ: return SPCC::FCC_UE;
1633 }
1634}
1635
1636SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
1637 const SparcSubtarget &STI)
1638 : TargetLowering(TM, STI), Subtarget(&STI) {
1639 MVT PtrVT = MVT::getIntegerVT(BitWidth: TM.getPointerSizeInBits(AS: 0));
1640
1641 // Instructions which use registers as conditionals examine all the
1642 // bits (as does the pseudo SELECT_CC expansion). I don't think it
1643 // matters much whether it's ZeroOrOneBooleanContent, or
1644 // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
1645 // former.
1646 setBooleanContents(ZeroOrOneBooleanContent);
1647 setBooleanVectorContents(ZeroOrOneBooleanContent);
1648
1649 // Set up the register classes.
1650 addRegisterClass(VT: MVT::i32, RC: &SP::IntRegsRegClass);
1651 if (!Subtarget->useSoftFloat()) {
1652 addRegisterClass(VT: MVT::f32, RC: &SP::FPRegsRegClass);
1653 addRegisterClass(VT: MVT::f64, RC: &SP::DFPRegsRegClass);
1654 addRegisterClass(VT: MVT::f128, RC: &SP::QFPRegsRegClass);
1655 }
1656 if (Subtarget->is64Bit()) {
1657 addRegisterClass(VT: MVT::i64, RC: &SP::I64RegsRegClass);
1658 } else {
1659 // On 32bit sparc, we define a double-register 32bit register
1660 // class, as well. This is modeled in LLVM as a 2-vector of i32.
1661 addRegisterClass(VT: MVT::v2i32, RC: &SP::IntPairRegClass);
1662
1663 // ...but almost all operations must be expanded, so set that as
1664 // the default.
1665 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
1666 setOperationAction(Op, VT: MVT::v2i32, Action: Expand);
1667 }
1668 // Truncating/extending stores/loads are also not supported.
1669 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
1670 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1671 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1672 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1673
1674 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1675 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1676 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1677
1678 setTruncStoreAction(ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1679 setTruncStoreAction(ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1680 }
1681 // However, load and store *are* legal.
1682 setOperationAction(Op: ISD::LOAD, VT: MVT::v2i32, Action: Legal);
1683 setOperationAction(Op: ISD::STORE, VT: MVT::v2i32, Action: Legal);
1684 setOperationAction(Op: ISD::EXTRACT_VECTOR_ELT, VT: MVT::v2i32, Action: Legal);
1685 setOperationAction(Op: ISD::BUILD_VECTOR, VT: MVT::v2i32, Action: Legal);
1686
1687 // And we need to promote i64 loads/stores into vector load/store
1688 setOperationAction(Op: ISD::LOAD, VT: MVT::i64, Action: Custom);
1689 setOperationAction(Op: ISD::STORE, VT: MVT::i64, Action: Custom);
1690
1691 // Sadly, this doesn't work:
1692 // AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
1693 // AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
1694 }
1695
1696 // Turn FP extload into load/fpextend
1697 for (MVT VT : MVT::fp_valuetypes()) {
1698 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f16, Action: Expand);
1699 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f32, Action: Expand);
1700 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f64, Action: Expand);
1701 }
1702
1703 // Sparc doesn't have i1 sign extending load
1704 for (MVT VT : MVT::integer_valuetypes())
1705 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
1706
1707 // Turn FP truncstore into trunc + store.
1708 setTruncStoreAction(ValVT: MVT::f32, MemVT: MVT::f16, Action: Expand);
1709 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f16, Action: Expand);
1710 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f32, Action: Expand);
1711 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f16, Action: Expand);
1712 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f32, Action: Expand);
1713 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f64, Action: Expand);
1714
1715 // Custom legalize GlobalAddress nodes into LO/HI parts.
1716 setOperationAction(Op: ISD::GlobalAddress, VT: PtrVT, Action: Custom);
1717 setOperationAction(Op: ISD::GlobalTLSAddress, VT: PtrVT, Action: Custom);
1718 setOperationAction(Op: ISD::ConstantPool, VT: PtrVT, Action: Custom);
1719 setOperationAction(Op: ISD::BlockAddress, VT: PtrVT, Action: Custom);
1720
1721 // Sparc doesn't have sext_inreg, replace them with shl/sra
1722 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i16, Action: Expand);
1723 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i8 , Action: Expand);
1724 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i1 , Action: Expand);
1725
1726 // Sparc has no REM or DIVREM operations.
1727 setOperationAction(Op: ISD::UREM, VT: MVT::i32, Action: Expand);
1728 setOperationAction(Op: ISD::SREM, VT: MVT::i32, Action: Expand);
1729 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i32, Action: Expand);
1730 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i32, Action: Expand);
1731
1732 // ... nor does SparcV9.
1733 if (Subtarget->is64Bit()) {
1734 setOperationAction(Op: ISD::UREM, VT: MVT::i64, Action: Expand);
1735 setOperationAction(Op: ISD::SREM, VT: MVT::i64, Action: Expand);
1736 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i64, Action: Expand);
1737 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i64, Action: Expand);
1738 }
1739
1740 // Custom expand fp<->sint
1741 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::i32, Action: Custom);
1742 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::i32, Action: Custom);
1743 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::i64, Action: Custom);
1744 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::i64, Action: Custom);
1745
1746 // Custom Expand fp<->uint
1747 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i32, Action: Custom);
1748 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i32, Action: Custom);
1749 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i64, Action: Custom);
1750 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i64, Action: Custom);
1751
1752 // Lower f16 conversion operations into library calls
1753 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f32, Action: Expand);
1754 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f32, Action: Expand);
1755 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f64, Action: Expand);
1756 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f64, Action: Expand);
1757 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f128, Action: Expand);
1758 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f128, Action: Expand);
1759
1760 setOperationAction(Op: ISD::BITCAST, VT: MVT::f32,
1761 Action: Subtarget->isVIS3() ? Legal : Expand);
1762 setOperationAction(Op: ISD::BITCAST, VT: MVT::i32,
1763 Action: Subtarget->isVIS3() ? Legal : Expand);
1764
1765 // Sparc has no select or setcc: expand to SELECT_CC.
1766 setOperationAction(Op: ISD::SELECT, VT: MVT::i32, Action: Expand);
1767 setOperationAction(Op: ISD::SELECT, VT: MVT::f32, Action: Expand);
1768 setOperationAction(Op: ISD::SELECT, VT: MVT::f64, Action: Expand);
1769 setOperationAction(Op: ISD::SELECT, VT: MVT::f128, Action: Expand);
1770
1771 setOperationAction(Op: ISD::SETCC, VT: MVT::i32, Action: Expand);
1772 setOperationAction(Op: ISD::SETCC, VT: MVT::f32, Action: Expand);
1773 setOperationAction(Op: ISD::SETCC, VT: MVT::f64, Action: Expand);
1774 setOperationAction(Op: ISD::SETCC, VT: MVT::f128, Action: Expand);
1775
1776 // Sparc doesn't have BRCOND either, it has BR_CC.
1777 setOperationAction(Op: ISD::BRCOND, VT: MVT::Other, Action: Expand);
1778 setOperationAction(Op: ISD::BRIND, VT: MVT::Other, Action: Expand);
1779 setOperationAction(Op: ISD::BR_JT, VT: MVT::Other, Action: Expand);
1780 setOperationAction(Op: ISD::BR_CC, VT: MVT::i32, Action: Custom);
1781 setOperationAction(Op: ISD::BR_CC, VT: MVT::f32, Action: Custom);
1782 setOperationAction(Op: ISD::BR_CC, VT: MVT::f64, Action: Custom);
1783 setOperationAction(Op: ISD::BR_CC, VT: MVT::f128, Action: Custom);
1784
1785 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i32, Action: Custom);
1786 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f32, Action: Custom);
1787 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f64, Action: Custom);
1788 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f128, Action: Custom);
1789
1790 setOperationAction(Op: ISD::ADDC, VT: MVT::i32, Action: Legal);
1791 setOperationAction(Op: ISD::ADDE, VT: MVT::i32, Action: Legal);
1792 setOperationAction(Op: ISD::SUBC, VT: MVT::i32, Action: Legal);
1793 setOperationAction(Op: ISD::SUBE, VT: MVT::i32, Action: Legal);
1794
1795 if (Subtarget->isVIS3()) {
1796 setOperationAction(Op: ISD::ADDC, VT: MVT::i64, Action: Legal);
1797 setOperationAction(Op: ISD::ADDE, VT: MVT::i64, Action: Legal);
1798 }
1799
1800 if (Subtarget->is64Bit()) {
1801 setOperationAction(Op: ISD::BITCAST, VT: MVT::f64,
1802 Action: Subtarget->isVIS3() ? Legal : Expand);
1803 setOperationAction(Op: ISD::BITCAST, VT: MVT::i64,
1804 Action: Subtarget->isVIS3() ? Legal : Expand);
1805 setOperationAction(Op: ISD::SELECT, VT: MVT::i64, Action: Expand);
1806 setOperationAction(Op: ISD::SETCC, VT: MVT::i64, Action: Expand);
1807 setOperationAction(Op: ISD::BR_CC, VT: MVT::i64, Action: Custom);
1808 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i64, Action: Custom);
1809
1810 setOperationAction(Op: ISD::CTPOP, VT: MVT::i64,
1811 Action: Subtarget->usePopc() ? Legal : Expand);
1812 setOperationAction(Op: ISD::BSWAP, VT: MVT::i64, Action: Custom);
1813 setOperationAction(Op: ISD::ROTL , VT: MVT::i64, Action: Expand);
1814 setOperationAction(Op: ISD::ROTR , VT: MVT::i64, Action: Expand);
1815 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i64, Action: Custom);
1816 }
1817
1818 // ATOMICs.
1819 // Atomics are supported on SparcV9. 32-bit atomics are also
1820 // supported by some Leon SparcV8 variants. Otherwise, atomics
1821 // are unsupported.
1822 if (Subtarget->isV9()) {
1823 // TODO: we _ought_ to be able to support 64-bit atomics on 32-bit sparcv9,
1824 // but it hasn't been implemented in the backend yet.
1825 if (Subtarget->is64Bit())
1826 setMaxAtomicSizeInBitsSupported(64);
1827 else
1828 setMaxAtomicSizeInBitsSupported(32);
1829 } else if (Subtarget->hasLeonCasa())
1830 setMaxAtomicSizeInBitsSupported(32);
1831 else
1832 setMaxAtomicSizeInBitsSupported(0);
1833
1834 setMinCmpXchgSizeInBits(32);
1835
1836 setOperationAction(Op: ISD::ATOMIC_SWAP, VT: MVT::i32, Action: Legal);
1837
1838 setOperationAction(Op: ISD::ATOMIC_FENCE, VT: MVT::Other, Action: Legal);
1839
1840 // Custom Lower Atomic LOAD/STORE
1841 setOperationAction(Op: ISD::ATOMIC_LOAD, VT: MVT::i32, Action: Custom);
1842 setOperationAction(Op: ISD::ATOMIC_STORE, VT: MVT::i32, Action: Custom);
1843
1844 if (Subtarget->is64Bit()) {
1845 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP, VT: MVT::i64, Action: Legal);
1846 setOperationAction(Op: ISD::ATOMIC_SWAP, VT: MVT::i64, Action: Legal);
1847 setOperationAction(Op: ISD::ATOMIC_LOAD, VT: MVT::i64, Action: Custom);
1848 setOperationAction(Op: ISD::ATOMIC_STORE, VT: MVT::i64, Action: Custom);
1849 }
1850
1851 if (!Subtarget->isV9()) {
1852 // SparcV8 does not have FNEGD and FABSD.
1853 setOperationAction(Op: ISD::FNEG, VT: MVT::f64, Action: Custom);
1854 setOperationAction(Op: ISD::FABS, VT: MVT::f64, Action: Custom);
1855 }
1856
1857 setOperationAction(Op: ISD::FSIN , VT: MVT::f128, Action: Expand);
1858 setOperationAction(Op: ISD::FCOS , VT: MVT::f128, Action: Expand);
1859 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f128, Action: Expand);
1860 setOperationAction(Op: ISD::FREM, VT: MVT::f128, Action: LibCall);
1861 setOperationAction(Op: ISD::FMA , VT: MVT::f128, Action: Expand);
1862 setOperationAction(Op: ISD::FSIN , VT: MVT::f64, Action: Expand);
1863 setOperationAction(Op: ISD::FCOS , VT: MVT::f64, Action: Expand);
1864 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f64, Action: Expand);
1865 setOperationAction(Op: ISD::FREM, VT: MVT::f64, Action: LibCall);
1866 setOperationAction(Op: ISD::FMA, VT: MVT::f64,
1867 Action: Subtarget->isUA2007() ? Legal : Expand);
1868 setOperationAction(Op: ISD::FSIN , VT: MVT::f32, Action: Expand);
1869 setOperationAction(Op: ISD::FCOS , VT: MVT::f32, Action: Expand);
1870 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f32, Action: Expand);
1871 setOperationAction(Op: ISD::FREM, VT: MVT::f32, Action: LibCall);
1872 setOperationAction(Op: ISD::FMA, VT: MVT::f32,
1873 Action: Subtarget->isUA2007() ? Legal : Expand);
1874 setOperationAction(Op: ISD::ROTL , VT: MVT::i32, Action: Expand);
1875 setOperationAction(Op: ISD::ROTR , VT: MVT::i32, Action: Expand);
1876 setOperationAction(Op: ISD::BSWAP, VT: MVT::i32, Action: Subtarget->isV9() ? Custom : Expand);
1877 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f128, Action: Expand);
1878 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f64, Action: Expand);
1879 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f32, Action: Expand);
1880 setOperationAction(Op: ISD::FPOW , VT: MVT::f128, Action: Expand);
1881 setOperationAction(Op: ISD::FPOW , VT: MVT::f64, Action: Expand);
1882 setOperationAction(Op: ISD::FPOW , VT: MVT::f32, Action: Expand);
1883
1884 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i32, Action: Expand);
1885 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i32, Action: Expand);
1886 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i32, Action: Expand);
1887
1888 // Expands to [SU]MUL_LOHI.
1889 setOperationAction(Op: ISD::MULHU, VT: MVT::i32, Action: Expand);
1890 setOperationAction(Op: ISD::MULHS, VT: MVT::i32, Action: Expand);
1891 setOperationAction(Op: ISD::MUL, VT: MVT::i32, Action: Expand);
1892
1893 if (Subtarget->useSoftMulDiv()) {
1894 // .umul works for both signed and unsigned
1895 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i32, Action: Expand);
1896 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i32, Action: Expand);
1897 setOperationAction(Op: ISD::SDIV, VT: MVT::i32, Action: Expand);
1898 setOperationAction(Op: ISD::UDIV, VT: MVT::i32, Action: Expand);
1899 }
1900
1901 if (Subtarget->is64Bit()) {
1902 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i64, Action: Expand);
1903 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i64, Action: Expand);
1904 setOperationAction(Op: ISD::MULHU, VT: MVT::i64,
1905 Action: Subtarget->isVIS3() ? Legal : Expand);
1906 setOperationAction(Op: ISD::MULHS, VT: MVT::i64,
1907 Action: Subtarget->isVIS3() ? Legal : Expand);
1908
1909 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i64, Action: Expand);
1910 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i64, Action: Expand);
1911 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i64, Action: Expand);
1912 }
1913
1914 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1915 setOperationAction(Op: ISD::VASTART , VT: MVT::Other, Action: Custom);
1916 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1917 setOperationAction(Op: ISD::VAARG , VT: MVT::Other, Action: Custom);
1918
1919 setOperationAction(Op: ISD::TRAP , VT: MVT::Other, Action: Legal);
1920 setOperationAction(Op: ISD::DEBUGTRAP , VT: MVT::Other, Action: Legal);
1921
1922 // Use the default implementation.
1923 setOperationAction(Op: ISD::VACOPY , VT: MVT::Other, Action: Expand);
1924 setOperationAction(Op: ISD::VAEND , VT: MVT::Other, Action: Expand);
1925 setOperationAction(Op: ISD::STACKSAVE , VT: MVT::Other, Action: Expand);
1926 setOperationAction(Op: ISD::STACKRESTORE , VT: MVT::Other, Action: Expand);
1927 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i32 , Action: Custom);
1928 setOperationAction(Op: ISD::STACKADDRESS, VT: MVT::Other, Action: Custom);
1929
1930 setStackPointerRegisterToSaveRestore(SP::O6);
1931
1932 setOperationAction(Op: ISD::CTPOP, VT: MVT::i32,
1933 Action: Subtarget->usePopc() ? Legal : Expand);
1934
1935 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1936 setOperationAction(Op: ISD::LOAD, VT: MVT::f128, Action: Legal);
1937 setOperationAction(Op: ISD::STORE, VT: MVT::f128, Action: Legal);
1938 } else {
1939 setOperationAction(Op: ISD::LOAD, VT: MVT::f128, Action: Custom);
1940 setOperationAction(Op: ISD::STORE, VT: MVT::f128, Action: Custom);
1941 }
1942
1943 if (Subtarget->hasHardQuad()) {
1944 setOperationAction(Op: ISD::FADD, VT: MVT::f128, Action: Legal);
1945 setOperationAction(Op: ISD::FSUB, VT: MVT::f128, Action: Legal);
1946 setOperationAction(Op: ISD::FMUL, VT: MVT::f128, Action: Legal);
1947 setOperationAction(Op: ISD::FDIV, VT: MVT::f128, Action: Legal);
1948 setOperationAction(Op: ISD::FSQRT, VT: MVT::f128, Action: Legal);
1949 setOperationAction(Op: ISD::FP_EXTEND, VT: MVT::f128, Action: Legal);
1950 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f64, Action: Legal);
1951 if (Subtarget->isV9()) {
1952 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Legal);
1953 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Legal);
1954 } else {
1955 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Custom);
1956 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Custom);
1957 }
1958 } else {
1959 // Custom legalize f128 operations.
1960
1961 setOperationAction(Op: ISD::FADD, VT: MVT::f128, Action: Custom);
1962 setOperationAction(Op: ISD::FSUB, VT: MVT::f128, Action: Custom);
1963 setOperationAction(Op: ISD::FMUL, VT: MVT::f128, Action: Custom);
1964 setOperationAction(Op: ISD::FDIV, VT: MVT::f128, Action: Custom);
1965 setOperationAction(Op: ISD::FSQRT, VT: MVT::f128, Action: Custom);
1966 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Custom);
1967 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Custom);
1968
1969 setOperationAction(Op: ISD::FP_EXTEND, VT: MVT::f128, Action: Custom);
1970 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f64, Action: Custom);
1971 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f32, Action: Custom);
1972 }
1973
1974 if (Subtarget->fixAllFDIVSQRT()) {
1975 // Promote FDIVS and FSQRTS to FDIVD and FSQRTD instructions instead as
1976 // the former instructions generate errata on LEON processors.
1977 setOperationAction(Op: ISD::FDIV, VT: MVT::f32, Action: Promote);
1978 setOperationAction(Op: ISD::FSQRT, VT: MVT::f32, Action: Promote);
1979 }
1980
1981 if (Subtarget->hasNoFMULS()) {
1982 setOperationAction(Op: ISD::FMUL, VT: MVT::f32, Action: Promote);
1983 }
1984
1985 // Custom combine bitcast between f64 and v2i32
1986 if (!Subtarget->is64Bit())
1987 setTargetDAGCombine(ISD::BITCAST);
1988
1989 if (Subtarget->isV9())
1990 setTargetDAGCombine({ISD::BSWAP, ISD::STORE});
1991
1992 if (Subtarget->hasLeonCycleCounter())
1993 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Custom);
1994
1995 if (Subtarget->isVIS3()) {
1996 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Legal);
1997 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Legal);
1998 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i32, Action: Legal);
1999 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i64, Action: Legal);
2000
2001 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32,
2002 Action: Subtarget->is64Bit() ? Promote : Expand);
2003 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
2004 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i32,
2005 Action: Subtarget->is64Bit() ? Promote : Expand);
2006 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i64, Action: Expand);
2007 } else if (Subtarget->usePopc()) {
2008 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Expand);
2009 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Expand);
2010 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i32, Action: Expand);
2011 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i64, Action: Expand);
2012
2013 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32, Action: Expand);
2014 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
2015 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i32, Action: Expand);
2016 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i64, Action: Expand);
2017 } else {
2018 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Expand);
2019 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Expand);
2020 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i32,
2021 Action: Subtarget->is64Bit() ? Promote : LibCall);
2022 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i64, Action: LibCall);
2023
2024 // FIXME here we don't have any ISA extensions that could help us, so to
2025 // prevent large expansions those should be made into LibCalls.
2026 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32, Action: Expand);
2027 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
2028 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i32, Action: Expand);
2029 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i64, Action: Expand);
2030 }
2031
2032 setOperationAction(Op: ISD::INTRINSIC_WO_CHAIN, VT: MVT::Other, Action: Custom);
2033
2034 // Some processors have no branch predictor and have pipelines longer than
2035 // what can be covered by the delay slot. This results in a stall, so mark
2036 // branches to be expensive on those processors.
2037 setJumpIsExpensive(Subtarget->hasNoPredictor());
2038 // The high cost of branching means that using conditional moves will
2039 // still be profitable even if the condition is predictable.
2040 PredictableSelectIsExpensive = !isJumpExpensive();
2041
2042 setMinFunctionAlignment(Align(4));
2043
2044 computeRegisterProperties(TRI: Subtarget->getRegisterInfo());
2045}
2046
2047bool SparcTargetLowering::useSoftFloat() const {
2048 return Subtarget->useSoftFloat();
2049}
2050
2051EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
2052 EVT VT) const {
2053 if (!VT.isVector())
2054 return MVT::i32;
2055 return VT.changeVectorElementTypeToInteger();
2056}
2057
2058/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
2059/// be zero. Op is expected to be a target specific node. Used by DAG
2060/// combiner.
2061void SparcTargetLowering::computeKnownBitsForTargetNode
2062 (const SDValue Op,
2063 KnownBits &Known,
2064 const APInt &DemandedElts,
2065 const SelectionDAG &DAG,
2066 unsigned Depth) const {
2067 KnownBits Known2;
2068 Known.resetAll();
2069
2070 switch (Op.getOpcode()) {
2071 default: break;
2072 case SPISD::SELECT_ICC:
2073 case SPISD::SELECT_XCC:
2074 case SPISD::SELECT_FCC:
2075 Known = DAG.computeKnownBits(Op: Op.getOperand(i: 1), Depth: Depth + 1);
2076 Known2 = DAG.computeKnownBits(Op: Op.getOperand(i: 0), Depth: Depth + 1);
2077
2078 // Only known if known in both the LHS and RHS.
2079 Known = Known.intersectWith(RHS: Known2);
2080 break;
2081 }
2082}
2083
2084// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
2085// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
2086static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
2087 ISD::CondCode CC, unsigned &SPCC) {
2088 if (isNullConstant(V: RHS) && CC == ISD::SETNE &&
2089 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
2090 LHS.getOpcode() == SPISD::SELECT_XCC) &&
2091 LHS.getOperand(i: 3).getOpcode() == SPISD::CMPICC) ||
2092 (LHS.getOpcode() == SPISD::SELECT_FCC &&
2093 (LHS.getOperand(i: 3).getOpcode() == SPISD::CMPFCC ||
2094 LHS.getOperand(i: 3).getOpcode() == SPISD::CMPFCC_V9))) &&
2095 isOneConstant(V: LHS.getOperand(i: 0)) && isNullConstant(V: LHS.getOperand(i: 1))) {
2096 SDValue CMPCC = LHS.getOperand(i: 3);
2097 SPCC = LHS.getConstantOperandVal(i: 2);
2098 LHS = CMPCC.getOperand(i: 0);
2099 RHS = CMPCC.getOperand(i: 1);
2100 }
2101}
2102
2103// Convert to a target node and set target flags.
2104SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
2105 SelectionDAG &DAG) const {
2106 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Val&: Op))
2107 return DAG.getTargetGlobalAddress(GV: GA->getGlobal(),
2108 DL: SDLoc(GA),
2109 VT: GA->getValueType(ResNo: 0),
2110 offset: GA->getOffset(), TargetFlags: TF);
2111
2112 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Val&: Op))
2113 return DAG.getTargetConstantPool(C: CP->getConstVal(), VT: CP->getValueType(ResNo: 0),
2114 Align: CP->getAlign(), Offset: CP->getOffset(), TargetFlags: TF);
2115
2116 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Val&: Op))
2117 return DAG.getTargetBlockAddress(BA: BA->getBlockAddress(),
2118 VT: Op.getValueType(),
2119 Offset: 0,
2120 TargetFlags: TF);
2121
2122 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Val&: Op))
2123 return DAG.getTargetExternalSymbol(Sym: ES->getSymbol(),
2124 VT: ES->getValueType(ResNo: 0), TargetFlags: TF);
2125
2126 llvm_unreachable("Unhandled address SDNode");
2127}
2128
2129// Split Op into high and low parts according to HiTF and LoTF.
2130// Return an ADD node combining the parts.
2131SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
2132 unsigned HiTF, unsigned LoTF,
2133 SelectionDAG &DAG) const {
2134 SDLoc DL(Op);
2135 EVT VT = Op.getValueType();
2136 SDValue Hi = DAG.getNode(Opcode: SPISD::Hi, DL, VT, Operand: withTargetFlags(Op, TF: HiTF, DAG));
2137 SDValue Lo = DAG.getNode(Opcode: SPISD::Lo, DL, VT, Operand: withTargetFlags(Op, TF: LoTF, DAG));
2138 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Hi, N2: Lo);
2139}
2140
2141// Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
2142// or ExternalSymbol SDNode.
2143SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
2144 SDLoc DL(Op);
2145 EVT VT = getPointerTy(DL: DAG.getDataLayout());
2146
2147 // Handle PIC mode first. SPARC needs a got load for every variable!
2148 if (isPositionIndependent()) {
2149 const Module *M = DAG.getMachineFunction().getFunction().getParent();
2150 PICLevel::Level picLevel = M->getPICLevel();
2151 SDValue Idx;
2152
2153 if (picLevel == PICLevel::SmallPIC) {
2154 // This is the pic13 code model, the GOT is known to be smaller than 8KiB.
2155 Idx = DAG.getNode(Opcode: SPISD::Lo, DL, VT: Op.getValueType(),
2156 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_GOT13, DAG));
2157 } else {
2158 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
2159 Idx = makeHiLoPair(Op, HiTF: ELF::R_SPARC_GOT22, LoTF: ELF::R_SPARC_GOT10, DAG);
2160 }
2161
2162 SDValue GlobalBase = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT);
2163 SDValue AbsAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: GlobalBase, N2: Idx);
2164 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2165 // function has calls.
2166 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2167 MFI.setHasCalls(true);
2168 return DAG.getLoad(VT, dl: DL, Chain: DAG.getEntryNode(), Ptr: AbsAddr,
2169 PtrInfo: MachinePointerInfo::getGOT(MF&: DAG.getMachineFunction()));
2170 }
2171
2172 // This is one of the absolute code models.
2173 switch(getTargetMachine().getCodeModel()) {
2174 default:
2175 llvm_unreachable("Unsupported absolute code model");
2176 case CodeModel::Small:
2177 // abs32.
2178 return makeHiLoPair(Op, HiTF: ELF::R_SPARC_HI22, LoTF: ELF::R_SPARC_LO10, DAG);
2179 case CodeModel::Medium: {
2180 // abs44.
2181 SDValue H44 = makeHiLoPair(Op, HiTF: ELF::R_SPARC_H44, LoTF: ELF::R_SPARC_M44, DAG);
2182 H44 = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: H44, N2: DAG.getConstant(Val: 12, DL, VT: MVT::i32));
2183 SDValue L44 = withTargetFlags(Op, TF: ELF::R_SPARC_L44, DAG);
2184 L44 = DAG.getNode(Opcode: SPISD::Lo, DL, VT, Operand: L44);
2185 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: H44, N2: L44);
2186 }
2187 case CodeModel::Large: {
2188 // abs64.
2189 SDValue Hi = makeHiLoPair(Op, HiTF: ELF::R_SPARC_HH22, LoTF: ELF::R_SPARC_HM10, DAG);
2190 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi, N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
2191 SDValue Lo = makeHiLoPair(Op, HiTF: ELF::R_SPARC_HI22, LoTF: ELF::R_SPARC_LO10, DAG);
2192 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Hi, N2: Lo);
2193 }
2194 }
2195}
2196
2197SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
2198 SelectionDAG &DAG) const {
2199 return makeAddress(Op, DAG);
2200}
2201
2202SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
2203 SelectionDAG &DAG) const {
2204 return makeAddress(Op, DAG);
2205}
2206
2207SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
2208 SelectionDAG &DAG) const {
2209 return makeAddress(Op, DAG);
2210}
2211
2212SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2213 SelectionDAG &DAG) const {
2214
2215 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Val&: Op);
2216 if (DAG.getTarget().useEmulatedTLS())
2217 return LowerToTLSEmulatedModel(GA, DAG);
2218
2219 SDLoc DL(GA);
2220 const GlobalValue *GV = GA->getGlobal();
2221 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
2222
2223 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2224
2225 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2226 unsigned HiTF =
2227 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_HI22
2228 : ELF::R_SPARC_TLS_LDM_HI22);
2229 unsigned LoTF =
2230 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_LO10
2231 : ELF::R_SPARC_TLS_LDM_LO10);
2232 unsigned addTF =
2233 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_ADD
2234 : ELF::R_SPARC_TLS_LDM_ADD);
2235 unsigned callTF =
2236 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_CALL
2237 : ELF::R_SPARC_TLS_LDM_CALL);
2238
2239 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
2240 SDValue Base = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT: PtrVT);
2241 SDValue Argument = DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT, N1: Base, N2: HiLo,
2242 N3: withTargetFlags(Op, TF: addTF, DAG));
2243
2244 SDValue Chain = DAG.getEntryNode();
2245 SDValue InGlue;
2246
2247 Chain = DAG.getCALLSEQ_START(Chain, InSize: 0, OutSize: 0, DL);
2248 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SP::O0, N: Argument, Glue: InGlue);
2249 InGlue = Chain.getValue(R: 1);
2250 SDValue Callee = DAG.getTargetExternalSymbol(Sym: "__tls_get_addr", VT: PtrVT);
2251 SDValue Symbol = withTargetFlags(Op, TF: callTF, DAG);
2252
2253 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
2254 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
2255 MF: DAG.getMachineFunction(), CC: CallingConv::C);
2256 assert(Mask && "Missing call preserved mask for calling convention");
2257 SDValue Ops[] = {Chain,
2258 Callee,
2259 Symbol,
2260 DAG.getRegister(Reg: SP::O0, VT: PtrVT),
2261 DAG.getRegisterMask(RegMask: Mask),
2262 InGlue};
2263 Chain = DAG.getNode(Opcode: SPISD::TLS_CALL, DL, VTList: NodeTys, Ops);
2264 InGlue = Chain.getValue(R: 1);
2265 Chain = DAG.getCALLSEQ_END(Chain, Size1: 0, Size2: 0, Glue: InGlue, DL);
2266 InGlue = Chain.getValue(R: 1);
2267 SDValue Ret = DAG.getCopyFromReg(Chain, dl: DL, Reg: SP::O0, VT: PtrVT, Glue: InGlue);
2268
2269 if (model != TLSModel::LocalDynamic)
2270 return Ret;
2271
2272 SDValue Hi =
2273 DAG.getNode(Opcode: SPISD::Hi, DL, VT: PtrVT,
2274 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_HIX22, DAG));
2275 SDValue Lo =
2276 DAG.getNode(Opcode: SPISD::Lo, DL, VT: PtrVT,
2277 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_LOX10, DAG));
2278 HiLo = DAG.getNode(Opcode: ISD::XOR, DL, VT: PtrVT, N1: Hi, N2: Lo);
2279 return DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT, N1: Ret, N2: HiLo,
2280 N3: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_ADD, DAG));
2281 }
2282
2283 if (model == TLSModel::InitialExec) {
2284 unsigned ldTF = ((PtrVT == MVT::i64) ? ELF::R_SPARC_TLS_IE_LDX
2285 : ELF::R_SPARC_TLS_IE_LD);
2286
2287 SDValue Base = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT: PtrVT);
2288
2289 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2290 // function has calls.
2291 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2292 MFI.setHasCalls(true);
2293
2294 SDValue TGA = makeHiLoPair(Op, HiTF: ELF::R_SPARC_TLS_IE_HI22,
2295 LoTF: ELF::R_SPARC_TLS_IE_LO10, DAG);
2296 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: Base, N2: TGA);
2297 SDValue Offset = DAG.getNode(Opcode: SPISD::TLS_LD,
2298 DL, VT: PtrVT, N1: Ptr,
2299 N2: withTargetFlags(Op, TF: ldTF, DAG));
2300 return DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT,
2301 N1: DAG.getRegister(Reg: SP::G7, VT: PtrVT), N2: Offset,
2302 N3: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_IE_ADD, DAG));
2303 }
2304
2305 assert(model == TLSModel::LocalExec);
2306 SDValue Hi = DAG.getNode(Opcode: SPISD::Hi, DL, VT: PtrVT,
2307 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LE_HIX22, DAG));
2308 SDValue Lo = DAG.getNode(Opcode: SPISD::Lo, DL, VT: PtrVT,
2309 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LE_LOX10, DAG));
2310 SDValue Offset = DAG.getNode(Opcode: ISD::XOR, DL, VT: PtrVT, N1: Hi, N2: Lo);
2311
2312 return DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT,
2313 N1: DAG.getRegister(Reg: SP::G7, VT: PtrVT), N2: Offset);
2314}
2315
2316SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain,
2317 ArgListTy &Args, SDValue Arg,
2318 const SDLoc &DL,
2319 SelectionDAG &DAG) const {
2320 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2321 EVT ArgVT = Arg.getValueType();
2322 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
2323
2324 if (ArgTy->isFP128Ty()) {
2325 // Create a stack object and pass the pointer to the library function.
2326 int FI = MFI.CreateStackObject(Size: 16, Alignment: Align(8), isSpillSlot: false);
2327 SDValue FIPtr = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
2328 Chain = DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: FIPtr, PtrInfo: MachinePointerInfo(), Alignment: Align(8));
2329 Args.emplace_back(args&: FIPtr, args: PointerType::getUnqual(C&: ArgTy->getContext()));
2330 } else {
2331 Args.emplace_back(args&: Arg, args&: ArgTy);
2332 }
2333 return Chain;
2334}
2335
2336SDValue SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2337 RTLIB::Libcall LibFunc,
2338 unsigned numArgs) const {
2339 RTLIB::LibcallImpl LibFuncImpl = DAG.getLibcalls().getLibcallImpl(Call: LibFunc);
2340 if (LibFuncImpl == RTLIB::Unsupported)
2341 return SDValue();
2342
2343 ArgListTy Args;
2344
2345 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2346 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2347
2348 SDValue Callee = DAG.getExternalSymbol(LCImpl: LibFuncImpl, VT: PtrVT);
2349 Type *RetTy = Op.getValueType().getTypeForEVT(Context&: *DAG.getContext());
2350 Type *RetTyABI = RetTy;
2351 SDValue Chain = DAG.getEntryNode();
2352 SDValue RetPtr;
2353
2354 if (RetTy->isFP128Ty()) {
2355 // Create a Stack Object to receive the return value of type f128.
2356 int RetFI = MFI.CreateStackObject(Size: 16, Alignment: Align(8), isSpillSlot: false);
2357 RetPtr = DAG.getFrameIndex(FI: RetFI, VT: PtrVT);
2358 ArgListEntry Entry(RetPtr, PointerType::getUnqual(C&: RetTy->getContext()));
2359 if (!Subtarget->is64Bit()) {
2360 Entry.IsSRet = true;
2361 Entry.IndirectType = RetTy;
2362 }
2363 Entry.IsReturned = false;
2364 Args.push_back(x: Entry);
2365 RetTyABI = Type::getVoidTy(C&: *DAG.getContext());
2366 }
2367
2368 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2369 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2370 Chain = LowerF128_LibCallArg(Chain, Args, Arg: Op.getOperand(i), DL: SDLoc(Op), DAG);
2371 }
2372
2373 CallingConv::ID CC = DAG.getLibcalls().getLibcallImplCallingConv(Call: LibFuncImpl);
2374 TargetLowering::CallLoweringInfo CLI(DAG);
2375 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain).setCallee(CC, ResultType: RetTyABI, Target: Callee,
2376 ArgsList: std::move(Args));
2377
2378 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2379
2380 // chain is in second result.
2381 if (RetTyABI == RetTy)
2382 return CallInfo.first;
2383
2384 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2385
2386 Chain = CallInfo.second;
2387
2388 // Load RetPtr to get the return value.
2389 return DAG.getLoad(VT: Op.getValueType(), dl: SDLoc(Op), Chain, Ptr: RetPtr,
2390 PtrInfo: MachinePointerInfo(), Alignment: Align(8));
2391}
2392
2393SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2394 unsigned &SPCC, const SDLoc &DL,
2395 SelectionDAG &DAG) const {
2396
2397 const char *LibCall = nullptr;
2398 bool is64Bit = Subtarget->is64Bit();
2399 switch(SPCC) {
2400 default: llvm_unreachable("Unhandled conditional code!");
2401 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2402 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2403 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2404 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2405 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2406 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2407 case SPCC::FCC_UL :
2408 case SPCC::FCC_ULE:
2409 case SPCC::FCC_UG :
2410 case SPCC::FCC_UGE:
2411 case SPCC::FCC_U :
2412 case SPCC::FCC_O :
2413 case SPCC::FCC_LG :
2414 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2415 }
2416
2417 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2418 SDValue Callee = DAG.getExternalSymbol(Sym: LibCall, VT: PtrVT);
2419 Type *RetTy = Type::getInt32Ty(C&: *DAG.getContext());
2420 ArgListTy Args;
2421 SDValue Chain = DAG.getEntryNode();
2422 Chain = LowerF128_LibCallArg(Chain, Args, Arg: LHS, DL, DAG);
2423 Chain = LowerF128_LibCallArg(Chain, Args, Arg: RHS, DL, DAG);
2424
2425 TargetLowering::CallLoweringInfo CLI(DAG);
2426 CLI.setDebugLoc(DL).setChain(Chain)
2427 .setCallee(CC: CallingConv::C, ResultType: RetTy, Target: Callee, ArgsList: std::move(Args));
2428
2429 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2430
2431 // result is in first, and chain is in second result.
2432 SDValue Result = CallInfo.first;
2433
2434 switch(SPCC) {
2435 default: {
2436 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2437 SPCC = SPCC::ICC_NE;
2438 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2439 }
2440 case SPCC::FCC_UL : {
2441 SDValue Mask = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2442 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2443 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2444 SPCC = SPCC::ICC_NE;
2445 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2446 }
2447 case SPCC::FCC_ULE: {
2448 SDValue RHS = DAG.getConstant(Val: 2, DL, VT: Result.getValueType());
2449 SPCC = SPCC::ICC_NE;
2450 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2451 }
2452 case SPCC::FCC_UG : {
2453 SDValue RHS = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2454 SPCC = SPCC::ICC_G;
2455 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2456 }
2457 case SPCC::FCC_UGE: {
2458 SDValue RHS = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2459 SPCC = SPCC::ICC_NE;
2460 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2461 }
2462
2463 case SPCC::FCC_U : {
2464 SDValue RHS = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2465 SPCC = SPCC::ICC_E;
2466 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2467 }
2468 case SPCC::FCC_O : {
2469 SDValue RHS = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2470 SPCC = SPCC::ICC_NE;
2471 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2472 }
2473 case SPCC::FCC_LG : {
2474 SDValue Mask = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2475 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2476 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2477 SPCC = SPCC::ICC_NE;
2478 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2479 }
2480 case SPCC::FCC_UE : {
2481 SDValue Mask = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2482 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2483 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2484 SPCC = SPCC::ICC_E;
2485 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2486 }
2487 }
2488}
2489
2490static SDValue
2491LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2492 const SparcTargetLowering &TLI) {
2493
2494 if (Op.getOperand(i: 0).getValueType() == MVT::f64)
2495 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPEXT_F64_F128, numArgs: 1);
2496
2497 if (Op.getOperand(i: 0).getValueType() == MVT::f32)
2498 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPEXT_F32_F128, numArgs: 1);
2499
2500 llvm_unreachable("fpextend with non-float operand!");
2501 return SDValue();
2502}
2503
2504static SDValue
2505LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2506 const SparcTargetLowering &TLI) {
2507 // FP_ROUND on f64 and f32 are legal.
2508 if (Op.getOperand(i: 0).getValueType() != MVT::f128)
2509 return Op;
2510
2511 if (Op.getValueType() == MVT::f64)
2512 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPROUND_F128_F64, numArgs: 1);
2513 if (Op.getValueType() == MVT::f32)
2514 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPROUND_F128_F32, numArgs: 1);
2515
2516 llvm_unreachable("fpround to non-float!");
2517 return SDValue();
2518}
2519
2520static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2521 const SparcTargetLowering &TLI,
2522 bool hasHardQuad) {
2523 SDLoc dl(Op);
2524 EVT VT = Op.getValueType();
2525 assert(VT == MVT::i32 || VT == MVT::i64);
2526
2527 // Expand f128 operations to fp128 abi calls.
2528 if (Op.getOperand(i: 0).getValueType() == MVT::f128
2529 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2530 RTLIB::Libcall LibFunc =
2531 VT == MVT::i32 ? RTLIB::FPTOSINT_F128_I32 : RTLIB::FPTOSINT_F128_I64;
2532 return TLI.LowerF128Op(Op, DAG, LibFunc, numArgs: 1);
2533 }
2534
2535 // Expand if the resulting type is illegal.
2536 if (!TLI.isTypeLegal(VT))
2537 return SDValue();
2538
2539 // Otherwise, Convert the fp value to integer in an FP register.
2540 if (VT == MVT::i32)
2541 Op = DAG.getNode(Opcode: SPISD::FTOI, DL: dl, VT: MVT::f32, Operand: Op.getOperand(i: 0));
2542 else
2543 Op = DAG.getNode(Opcode: SPISD::FTOX, DL: dl, VT: MVT::f64, Operand: Op.getOperand(i: 0));
2544
2545 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT, Operand: Op);
2546}
2547
2548static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2549 const SparcTargetLowering &TLI,
2550 bool hasHardQuad) {
2551 SDLoc dl(Op);
2552 EVT OpVT = Op.getOperand(i: 0).getValueType();
2553 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2554
2555 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2556
2557 // Expand f128 operations to fp128 ABI calls.
2558 if (Op.getValueType() == MVT::f128
2559 && (!hasHardQuad || !TLI.isTypeLegal(VT: OpVT))) {
2560 RTLIB::Libcall LibFunc =
2561 OpVT == MVT::i32 ? RTLIB::SINTTOFP_I32_F128 : RTLIB::SINTTOFP_I64_F128;
2562 return TLI.LowerF128Op(Op, DAG, LibFunc, numArgs: 1);
2563 }
2564
2565 // Expand if the operand type is illegal.
2566 if (!TLI.isTypeLegal(VT: OpVT))
2567 return SDValue();
2568
2569 // Otherwise, Convert the int value to FP in an FP register.
2570 SDValue Tmp = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: floatVT, Operand: Op.getOperand(i: 0));
2571 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2572 return DAG.getNode(Opcode: opcode, DL: dl, VT: Op.getValueType(), Operand: Tmp);
2573}
2574
2575static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2576 const SparcTargetLowering &TLI,
2577 bool hasHardQuad) {
2578 EVT VT = Op.getValueType();
2579
2580 // Expand if it does not involve f128 or the target has support for
2581 // quad floating point instructions and the resulting type is legal.
2582 if (Op.getOperand(i: 0).getValueType() != MVT::f128 ||
2583 (hasHardQuad && TLI.isTypeLegal(VT)))
2584 return SDValue();
2585
2586 assert(VT == MVT::i32 || VT == MVT::i64);
2587
2588 return TLI.LowerF128Op(
2589 Op, DAG,
2590 LibFunc: VT == MVT::i32 ? RTLIB::FPTOUINT_F128_I32 : RTLIB::FPTOUINT_F128_I64, numArgs: 1);
2591}
2592
2593static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2594 const SparcTargetLowering &TLI,
2595 bool hasHardQuad) {
2596 EVT OpVT = Op.getOperand(i: 0).getValueType();
2597 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2598
2599 // Expand if it does not involve f128 or the target has support for
2600 // quad floating point instructions and the operand type is legal.
2601 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(VT: OpVT)))
2602 return SDValue();
2603
2604 return TLI.LowerF128Op(Op, DAG,
2605 LibFunc: OpVT == MVT::i32 ? RTLIB::UINTTOFP_I32_F128
2606 : RTLIB::UINTTOFP_I64_F128,
2607 numArgs: 1);
2608}
2609
2610static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2611 const SparcTargetLowering &TLI, bool hasHardQuad,
2612 bool isV9, bool is64Bit) {
2613 SDValue Chain = Op.getOperand(i: 0);
2614 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 1))->get();
2615 SDValue LHS = Op.getOperand(i: 2);
2616 SDValue RHS = Op.getOperand(i: 3);
2617 SDValue Dest = Op.getOperand(i: 4);
2618 SDLoc dl(Op);
2619 unsigned Opc, SPCC = ~0U;
2620
2621 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2622 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2623 LookThroughSetCC(LHS, RHS, CC, SPCC);
2624 assert(LHS.getValueType() == RHS.getValueType());
2625
2626 // Get the condition flag.
2627 SDValue CompareFlag;
2628 if (LHS.getValueType().isInteger()) {
2629 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2630 // and the RHS is zero we might be able to use a specialized branch.
2631 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2632 isNullConstant(V: RHS) && !ISD::isUnsignedIntSetCC(Code: CC))
2633 return DAG.getNode(Opcode: SPISD::BR_REG, DL: dl, VT: MVT::Other, N1: Chain, N2: Dest,
2634 N3: DAG.getConstant(Val: intCondCCodeToRcond(CC), DL: dl, VT: MVT::i32),
2635 N4: LHS);
2636
2637 CompareFlag = DAG.getNode(Opcode: SPISD::CMPICC, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2638 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2639 if (isV9)
2640 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2641 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BPICC : SPISD::BPXCC;
2642 else
2643 // Non-v9 targets don't have xcc.
2644 Opc = SPISD::BRICC;
2645 } else {
2646 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2647 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2648 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, DL: dl, DAG);
2649 Opc = isV9 ? SPISD::BPICC : SPISD::BRICC;
2650 } else {
2651 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2652 CompareFlag = DAG.getNode(Opcode: CmpOpc, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2653 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2654 Opc = isV9 ? SPISD::BRFCC_V9 : SPISD::BRFCC;
2655 }
2656 }
2657 return DAG.getNode(Opcode: Opc, DL: dl, VT: MVT::Other, N1: Chain, N2: Dest,
2658 N3: DAG.getConstant(Val: SPCC, DL: dl, VT: MVT::i32), N4: CompareFlag);
2659}
2660
2661static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2662 const SparcTargetLowering &TLI, bool hasHardQuad,
2663 bool isV9, bool is64Bit) {
2664 SDValue LHS = Op.getOperand(i: 0);
2665 SDValue RHS = Op.getOperand(i: 1);
2666 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 4))->get();
2667 SDValue TrueVal = Op.getOperand(i: 2);
2668 SDValue FalseVal = Op.getOperand(i: 3);
2669 SDLoc dl(Op);
2670 unsigned Opc, SPCC = ~0U;
2671
2672 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2673 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2674 LookThroughSetCC(LHS, RHS, CC, SPCC);
2675 assert(LHS.getValueType() == RHS.getValueType());
2676
2677 SDValue CompareFlag;
2678 if (LHS.getValueType().isInteger()) {
2679 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2680 // and the RHS is zero we might be able to use a specialized select.
2681 // All SELECT_CC between any two scalar integer types are eligible for
2682 // lowering to specialized instructions. Additionally, f32 and f64 types
2683 // are also eligible, but for f128 we can only use the specialized
2684 // instruction when we have hardquad.
2685 EVT ValType = TrueVal.getValueType();
2686 bool IsEligibleType = ValType.isScalarInteger() || ValType == MVT::f32 ||
2687 ValType == MVT::f64 ||
2688 (ValType == MVT::f128 && hasHardQuad);
2689 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2690 isNullConstant(V: RHS) && !ISD::isUnsignedIntSetCC(Code: CC) && IsEligibleType)
2691 return DAG.getNode(
2692 Opcode: SPISD::SELECT_REG, DL: dl, VT: TrueVal.getValueType(), N1: TrueVal, N2: FalseVal,
2693 N3: DAG.getConstant(Val: intCondCCodeToRcond(CC), DL: dl, VT: MVT::i32), N4: LHS);
2694
2695 CompareFlag = DAG.getNode(Opcode: SPISD::CMPICC, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2696 Opc = LHS.getValueType() == MVT::i32 ?
2697 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2698 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2699 } else {
2700 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2701 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2702 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, DL: dl, DAG);
2703 Opc = SPISD::SELECT_ICC;
2704 } else {
2705 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2706 CompareFlag = DAG.getNode(Opcode: CmpOpc, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2707 Opc = SPISD::SELECT_FCC;
2708 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2709 }
2710 }
2711 return DAG.getNode(Opcode: Opc, DL: dl, VT: TrueVal.getValueType(), N1: TrueVal, N2: FalseVal,
2712 N3: DAG.getConstant(Val: SPCC, DL: dl, VT: MVT::i32), N4: CompareFlag);
2713}
2714
2715static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2716 const SparcTargetLowering &TLI) {
2717 MachineFunction &MF = DAG.getMachineFunction();
2718 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2719 auto PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
2720
2721 // Need frame address to find the address of VarArgsFrameIndex.
2722 MF.getFrameInfo().setFrameAddressIsTaken(true);
2723
2724 // vastart just stores the address of the VarArgsFrameIndex slot into the
2725 // memory location argument.
2726 SDLoc DL(Op);
2727 SDValue Offset =
2728 DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: DAG.getRegister(Reg: SP::I6, VT: PtrVT),
2729 N2: DAG.getIntPtrConstant(Val: FuncInfo->getVarArgsFrameOffset(), DL));
2730 const Value *SV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 2))->getValue();
2731 return DAG.getStore(Chain: Op.getOperand(i: 0), dl: DL, Val: Offset, Ptr: Op.getOperand(i: 1),
2732 PtrInfo: MachinePointerInfo(SV));
2733}
2734
2735static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2736 SDNode *Node = Op.getNode();
2737 EVT VT = Node->getValueType(ResNo: 0);
2738 SDValue InChain = Node->getOperand(Num: 0);
2739 SDValue VAListPtr = Node->getOperand(Num: 1);
2740 EVT PtrVT = VAListPtr.getValueType();
2741 const Value *SV = cast<SrcValueSDNode>(Val: Node->getOperand(Num: 2))->getValue();
2742 SDLoc DL(Node);
2743 SDValue VAList =
2744 DAG.getLoad(VT: PtrVT, dl: DL, Chain: InChain, Ptr: VAListPtr, PtrInfo: MachinePointerInfo(SV));
2745 // Increment the pointer, VAList, to the next vaarg.
2746 SDValue NextPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: VAList,
2747 N2: DAG.getIntPtrConstant(Val: VT.getSizeInBits()/8,
2748 DL));
2749 // Store the incremented VAList to the legalized pointer.
2750 InChain = DAG.getStore(Chain: VAList.getValue(R: 1), dl: DL, Val: NextPtr, Ptr: VAListPtr,
2751 PtrInfo: MachinePointerInfo(SV));
2752 // Load the actual argument out of the pointer VAList.
2753 // We can't count on greater alignment than the word size.
2754 return DAG.getLoad(
2755 VT, dl: DL, Chain: InChain, Ptr: VAList, PtrInfo: MachinePointerInfo(),
2756 Alignment: Align(std::min(a: PtrVT.getFixedSizeInBits(), b: VT.getFixedSizeInBits()) / 8));
2757}
2758
2759static SDValue LowerSTACKADDRESS(SDValue Op, SelectionDAG &DAG,
2760 const SparcSubtarget &Subtarget) {
2761 SDValue Chain = Op.getOperand(i: 0);
2762 EVT VT = Op->getValueType(ResNo: 0);
2763 SDLoc DL(Op);
2764
2765 MCRegister SPReg = SP::O6;
2766 SDValue SP = DAG.getCopyFromReg(Chain, dl: DL, Reg: SPReg, VT);
2767
2768 // Unbias the stack pointer register.
2769 unsigned OffsetToStackStart = Subtarget.getStackPointerBias();
2770 // Move past the register save area: 8 in registers + 8 local registers.
2771 OffsetToStackStart += 16 * (Subtarget.is64Bit() ? 8 : 4);
2772 // Move past the struct return address slot (4 bytes) on SPARC 32-bit.
2773 if (!Subtarget.is64Bit())
2774 OffsetToStackStart += 4;
2775
2776 SDValue StackAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: SP,
2777 N2: DAG.getConstant(Val: OffsetToStackStart, DL, VT));
2778 return DAG.getMergeValues(Ops: {StackAddr, Chain}, dl: DL);
2779}
2780
2781static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2782 const SparcSubtarget *Subtarget) {
2783 SDValue Chain = Op.getOperand(i: 0);
2784 SDValue Size = Op.getOperand(i: 1);
2785 SDValue Alignment = Op.getOperand(i: 2);
2786 MaybeAlign MaybeAlignment =
2787 cast<ConstantSDNode>(Val&: Alignment)->getMaybeAlignValue();
2788 EVT VT = Size->getValueType(ResNo: 0);
2789 SDLoc dl(Op);
2790
2791 unsigned SPReg = SP::O6;
2792 SDValue SP = DAG.getCopyFromReg(Chain, dl, Reg: SPReg, VT);
2793
2794 // The resultant pointer needs to be above the register spill area
2795 // at the bottom of the stack.
2796 unsigned regSpillArea;
2797 if (Subtarget->is64Bit()) {
2798 regSpillArea = 128;
2799 } else {
2800 // On Sparc32, the size of the spill area is 92. Unfortunately,
2801 // that's only 4-byte aligned, not 8-byte aligned (the stack
2802 // pointer is 8-byte aligned). So, if the user asked for an 8-byte
2803 // aligned dynamic allocation, we actually need to add 96 to the
2804 // bottom of the stack, instead of 92, to ensure 8-byte alignment.
2805
2806 // That also means adding 4 to the size of the allocation --
2807 // before applying the 8-byte rounding. Unfortunately, we the
2808 // value we get here has already had rounding applied. So, we need
2809 // to add 8, instead, wasting a bit more memory.
2810
2811 // Further, this only actually needs to be done if the required
2812 // alignment is > 4, but, we've lost that info by this point, too,
2813 // so we always apply it.
2814
2815 // (An alternative approach would be to always reserve 96 bytes
2816 // instead of the required 92, but then we'd waste 4 extra bytes
2817 // in every frame, not just those with dynamic stack allocations)
2818
2819 // TODO: modify code in SelectionDAGBuilder to make this less sad.
2820
2821 Size = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: Size,
2822 N2: DAG.getConstant(Val: 8, DL: dl, VT));
2823 regSpillArea = 96;
2824 }
2825
2826 int64_t Bias = Subtarget->getStackPointerBias();
2827
2828 // Debias and increment SP past the reserved spill area.
2829 // We need the SP to point to the first usable region before calculating
2830 // anything to prevent any of the pointers from becoming out of alignment when
2831 // we rebias the SP later on.
2832 SDValue StartOfUsableStack = DAG.getNode(
2833 Opcode: ISD::ADD, DL: dl, VT, N1: SP, N2: DAG.getConstant(Val: regSpillArea + Bias, DL: dl, VT));
2834 SDValue AllocatedPtr =
2835 DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: StartOfUsableStack, N2: Size);
2836
2837 bool IsOveraligned = MaybeAlignment.has_value();
2838 SDValue AlignedPtr =
2839 IsOveraligned
2840 ? DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: AllocatedPtr,
2841 N2: DAG.getSignedConstant(Val: -MaybeAlignment->value(), DL: dl, VT))
2842 : AllocatedPtr;
2843
2844 // Now that we are done, restore the bias and reserved spill area.
2845 SDValue NewSP = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: AlignedPtr,
2846 N2: DAG.getConstant(Val: regSpillArea + Bias, DL: dl, VT));
2847 Chain = DAG.getCopyToReg(Chain: SP.getValue(R: 1), dl, Reg: SPReg, N: NewSP);
2848 SDValue Ops[2] = {AlignedPtr, Chain};
2849 return DAG.getMergeValues(Ops, dl);
2850}
2851
2852
2853static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2854 SDLoc dl(Op);
2855 SDValue Chain = DAG.getNode(Opcode: SPISD::FLUSHW,
2856 DL: dl, VT: MVT::Other, Operand: DAG.getEntryNode());
2857 return Chain;
2858}
2859
2860static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2861 const SparcSubtarget *Subtarget,
2862 bool AlwaysFlush = false) {
2863 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2864 MFI.setFrameAddressIsTaken(true);
2865
2866 EVT VT = Op.getValueType();
2867 SDLoc dl(Op);
2868 unsigned FrameReg = SP::I6;
2869 unsigned stackBias = Subtarget->getStackPointerBias();
2870
2871 SDValue FrameAddr;
2872 SDValue Chain;
2873
2874 // flush first to make sure the windowed registers' values are in stack
2875 Chain = (depth || AlwaysFlush) ? getFLUSHW(Op, DAG) : DAG.getEntryNode();
2876
2877 FrameAddr = DAG.getCopyFromReg(Chain, dl, Reg: FrameReg, VT);
2878
2879 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2880
2881 while (depth--) {
2882 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: FrameAddr,
2883 N2: DAG.getIntPtrConstant(Val: Offset, DL: dl));
2884 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, PtrInfo: MachinePointerInfo());
2885 }
2886 if (Subtarget->is64Bit())
2887 FrameAddr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: FrameAddr,
2888 N2: DAG.getIntPtrConstant(Val: stackBias, DL: dl));
2889 return FrameAddr;
2890}
2891
2892
2893static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2894 const SparcSubtarget *Subtarget) {
2895
2896 uint64_t depth = Op.getConstantOperandVal(i: 0);
2897
2898 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2899
2900}
2901
2902static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2903 const SparcTargetLowering &TLI,
2904 const SparcSubtarget *Subtarget) {
2905 MachineFunction &MF = DAG.getMachineFunction();
2906 MachineFrameInfo &MFI = MF.getFrameInfo();
2907 MFI.setReturnAddressIsTaken(true);
2908
2909 EVT VT = Op.getValueType();
2910 SDLoc dl(Op);
2911 uint64_t depth = Op.getConstantOperandVal(i: 0);
2912
2913 SDValue RetAddr;
2914 if (depth == 0) {
2915 auto PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
2916 Register RetReg = MF.addLiveIn(PReg: SP::I7, RC: TLI.getRegClassFor(VT: PtrVT));
2917 RetAddr = DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl, Reg: RetReg, VT);
2918 return RetAddr;
2919 }
2920
2921 // Need frame address to find return address of the caller.
2922 SDValue FrameAddr = getFRAMEADDR(depth: depth - 1, Op, DAG, Subtarget, AlwaysFlush: true);
2923
2924 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2925 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD,
2926 DL: dl, VT,
2927 N1: FrameAddr,
2928 N2: DAG.getIntPtrConstant(Val: Offset, DL: dl));
2929 RetAddr = DAG.getLoad(VT, dl, Chain: DAG.getEntryNode(), Ptr, PtrInfo: MachinePointerInfo());
2930
2931 return RetAddr;
2932}
2933
2934static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG,
2935 unsigned opcode) {
2936 assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2937 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2938
2939 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2940 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2941 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2942
2943 // Note: in little-endian, the floating-point value is stored in the
2944 // registers are in the opposite order, so the subreg with the sign
2945 // bit is the highest-numbered (odd), rather than the
2946 // lowest-numbered (even).
2947
2948 SDValue Hi32 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_even, DL: dl, VT: MVT::f32,
2949 Operand: SrcReg64);
2950 SDValue Lo32 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_odd, DL: dl, VT: MVT::f32,
2951 Operand: SrcReg64);
2952
2953 if (DAG.getDataLayout().isLittleEndian())
2954 Lo32 = DAG.getNode(Opcode: opcode, DL: dl, VT: MVT::f32, Operand: Lo32);
2955 else
2956 Hi32 = DAG.getNode(Opcode: opcode, DL: dl, VT: MVT::f32, Operand: Hi32);
2957
2958 SDValue DstReg64 = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
2959 dl, VT: MVT::f64), 0);
2960 DstReg64 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_even, DL: dl, VT: MVT::f64,
2961 Operand: DstReg64, Subreg: Hi32);
2962 DstReg64 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_odd, DL: dl, VT: MVT::f64,
2963 Operand: DstReg64, Subreg: Lo32);
2964 return DstReg64;
2965}
2966
2967// Lower a f128 load into two f64 loads.
2968static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2969{
2970 SDLoc dl(Op);
2971 LoadSDNode *LdNode = cast<LoadSDNode>(Val: Op.getNode());
2972 assert(LdNode->getOffset().isUndef() && "Unexpected node type");
2973
2974 Align Alignment = commonAlignment(A: LdNode->getBaseAlign(), Offset: 8);
2975
2976 SDValue Hi64 =
2977 DAG.getLoad(VT: MVT::f64, dl, Chain: LdNode->getChain(), Ptr: LdNode->getBasePtr(),
2978 PtrInfo: LdNode->getPointerInfo(), Alignment);
2979 EVT addrVT = LdNode->getBasePtr().getValueType();
2980 SDValue LoPtr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: addrVT,
2981 N1: LdNode->getBasePtr(),
2982 N2: DAG.getConstant(Val: 8, DL: dl, VT: addrVT));
2983 SDValue Lo64 = DAG.getLoad(VT: MVT::f64, dl, Chain: LdNode->getChain(), Ptr: LoPtr,
2984 PtrInfo: LdNode->getPointerInfo().getWithOffset(O: 8),
2985 Alignment);
2986
2987 SDValue SubRegEven = DAG.getTargetConstant(Val: SP::sub_even64, DL: dl, VT: MVT::i32);
2988 SDValue SubRegOdd = DAG.getTargetConstant(Val: SP::sub_odd64, DL: dl, VT: MVT::i32);
2989
2990 SDNode *InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
2991 dl, VT: MVT::f128);
2992 InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl,
2993 VT: MVT::f128,
2994 Op1: SDValue(InFP128, 0),
2995 Op2: Hi64,
2996 Op3: SubRegEven);
2997 InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl,
2998 VT: MVT::f128,
2999 Op1: SDValue(InFP128, 0),
3000 Op2: Lo64,
3001 Op3: SubRegOdd);
3002 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
3003 SDValue(Lo64.getNode(), 1) };
3004 SDValue OutChain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
3005 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
3006 return DAG.getMergeValues(Ops, dl);
3007}
3008
3009SDValue SparcTargetLowering::LowerBSWAP(SDValue Op, SelectionDAG &DAG) const {
3010 // We don't have an in-register bswap, so expand bswap(x) into
3011 // load(store-swapped(x)). The reason the swap is done during the store is
3012 // that on some implementations (mainly older ones) ASI-tagged memory
3013 // operations are not pipelined, and generally stores finish faster than
3014 // loads.
3015
3016 MachineFunction &MF = DAG.getMachineFunction();
3017 MachineFrameInfo &MFI = MF.getFrameInfo();
3018 MVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
3019 SDValue Chain = DAG.getEntryNode();
3020 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
3021 SDLoc DL(Op);
3022
3023 SDValue BSwapOp = Op.getOperand(i: 0);
3024 EVT VT = BSwapOp.getValueType();
3025 Type *Ty = VT.getTypeForEVT(Context&: *DAG.getContext());
3026 Align Al = DAG.getDataLayout().getPrefTypeAlign(Ty);
3027
3028 // Create a stack object to serve as temporary storage.
3029 int TmpFI = MFI.CreateStackObject(Size: VT.getStoreSize(), Alignment: Al, isSpillSlot: false);
3030 SDValue TmpPtr = DAG.getFrameIndex(FI: TmpFI, VT: PtrVT);
3031
3032 // Store-swap the value, then load it back.
3033 SDValue Ops[] = {Chain, BSwapOp, TmpPtr, DAG.getValueType(VT)};
3034 SDValue ST = DAG.getMemIntrinsicNode(
3035 Opcode: IsLittleEndian ? SPISD::STORE_BIG : SPISD::STORE_LITTLE, dl: DL,
3036 VTList: DAG.getVTList(VT: MVT::Other), Ops, MemVT: VT,
3037 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI: TmpFI), Alignment: std::nullopt,
3038 Flags: MachineMemOperand::MOStore);
3039 return DAG.getLoad(VT, dl: DL, Chain: ST, Ptr: TmpPtr,
3040 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI: TmpFI));
3041}
3042
3043static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
3044{
3045 LoadSDNode *LdNode = cast<LoadSDNode>(Val: Op.getNode());
3046
3047 EVT MemVT = LdNode->getMemoryVT();
3048 if (MemVT == MVT::f128)
3049 return LowerF128Load(Op, DAG);
3050
3051 return Op;
3052}
3053
3054// Lower a f128 store into two f64 stores.
3055static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
3056 SDLoc dl(Op);
3057 StoreSDNode *StNode = cast<StoreSDNode>(Val: Op.getNode());
3058 assert(StNode->getOffset().isUndef() && "Unexpected node type");
3059
3060 SDValue SubRegEven = DAG.getTargetConstant(Val: SP::sub_even64, DL: dl, VT: MVT::i32);
3061 SDValue SubRegOdd = DAG.getTargetConstant(Val: SP::sub_odd64, DL: dl, VT: MVT::i32);
3062
3063 SDNode *Hi64 = DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG,
3064 dl,
3065 VT: MVT::f64,
3066 Op1: StNode->getValue(),
3067 Op2: SubRegEven);
3068 SDNode *Lo64 = DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG,
3069 dl,
3070 VT: MVT::f64,
3071 Op1: StNode->getValue(),
3072 Op2: SubRegOdd);
3073
3074 Align Alignment = commonAlignment(A: StNode->getBaseAlign(), Offset: 8);
3075
3076 SDValue OutChains[2];
3077 OutChains[0] =
3078 DAG.getStore(Chain: StNode->getChain(), dl, Val: SDValue(Hi64, 0),
3079 Ptr: StNode->getBasePtr(), PtrInfo: StNode->getPointerInfo(),
3080 Alignment);
3081 EVT addrVT = StNode->getBasePtr().getValueType();
3082 SDValue LoPtr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: addrVT,
3083 N1: StNode->getBasePtr(),
3084 N2: DAG.getConstant(Val: 8, DL: dl, VT: addrVT));
3085 OutChains[1] = DAG.getStore(Chain: StNode->getChain(), dl, Val: SDValue(Lo64, 0), Ptr: LoPtr,
3086 PtrInfo: StNode->getPointerInfo().getWithOffset(O: 8),
3087 Alignment);
3088 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
3089}
3090
3091static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
3092{
3093 SDLoc dl(Op);
3094 StoreSDNode *St = cast<StoreSDNode>(Val: Op.getNode());
3095
3096 EVT MemVT = St->getMemoryVT();
3097 if (MemVT == MVT::f128)
3098 return LowerF128Store(Op, DAG);
3099
3100 if (MemVT == MVT::i64) {
3101 // Custom handling for i64 stores: turn it into a bitcast and a
3102 // v2i32 store.
3103 SDValue Val = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::v2i32, Operand: St->getValue());
3104 SDValue Chain = DAG.getStore(
3105 Chain: St->getChain(), dl, Val, Ptr: St->getBasePtr(), PtrInfo: St->getPointerInfo(),
3106 Alignment: St->getBaseAlign(), MMOFlags: St->getMemOperand()->getFlags(), AAInfo: St->getAAInfo());
3107 return Chain;
3108 }
3109
3110 return SDValue();
3111}
3112
3113static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
3114 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
3115 && "invalid opcode");
3116
3117 SDLoc dl(Op);
3118
3119 if (Op.getValueType() == MVT::f64)
3120 return LowerF64Op(SrcReg64: Op.getOperand(i: 0), dl, DAG, opcode: Op.getOpcode());
3121 if (Op.getValueType() != MVT::f128)
3122 return Op;
3123
3124 // Lower fabs/fneg on f128 to fabs/fneg on f64
3125 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
3126 // (As with LowerF64Op, on little-endian, we need to negate the odd
3127 // subreg)
3128
3129 SDValue SrcReg128 = Op.getOperand(i: 0);
3130 SDValue Hi64 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_even64, DL: dl, VT: MVT::f64,
3131 Operand: SrcReg128);
3132 SDValue Lo64 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_odd64, DL: dl, VT: MVT::f64,
3133 Operand: SrcReg128);
3134
3135 if (DAG.getDataLayout().isLittleEndian()) {
3136 if (isV9)
3137 Lo64 = DAG.getNode(Opcode: Op.getOpcode(), DL: dl, VT: MVT::f64, Operand: Lo64);
3138 else
3139 Lo64 = LowerF64Op(SrcReg64: Lo64, dl, DAG, opcode: Op.getOpcode());
3140 } else {
3141 if (isV9)
3142 Hi64 = DAG.getNode(Opcode: Op.getOpcode(), DL: dl, VT: MVT::f64, Operand: Hi64);
3143 else
3144 Hi64 = LowerF64Op(SrcReg64: Hi64, dl, DAG, opcode: Op.getOpcode());
3145 }
3146
3147 SDValue DstReg128 = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
3148 dl, VT: MVT::f128), 0);
3149 DstReg128 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_even64, DL: dl, VT: MVT::f128,
3150 Operand: DstReg128, Subreg: Hi64);
3151 DstReg128 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_odd64, DL: dl, VT: MVT::f128,
3152 Operand: DstReg128, Subreg: Lo64);
3153 return DstReg128;
3154}
3155
3156static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
3157 if (isStrongerThanMonotonic(AO: cast<AtomicSDNode>(Val&: Op)->getSuccessOrdering())) {
3158 // Expand with a fence.
3159 return SDValue();
3160 }
3161
3162 // Monotonic load/stores are legal.
3163 return Op;
3164}
3165
3166SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
3167 SelectionDAG &DAG) const {
3168 unsigned IntNo = Op.getConstantOperandVal(i: 0);
3169 switch (IntNo) {
3170 default: return SDValue(); // Don't custom lower most intrinsics.
3171 case Intrinsic::thread_pointer: {
3172 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
3173 return DAG.getRegister(Reg: SP::G7, VT: PtrVT);
3174 }
3175 }
3176}
3177
3178SDValue SparcTargetLowering::
3179LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3180
3181 bool hasHardQuad = Subtarget->hasHardQuad();
3182 bool isV9 = Subtarget->isV9();
3183 bool is64Bit = Subtarget->is64Bit();
3184
3185 switch (Op.getOpcode()) {
3186 default: llvm_unreachable("Should not custom lower this!");
3187
3188 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, TLI: *this,
3189 Subtarget);
3190 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
3191 Subtarget);
3192 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3193 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3194 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3195 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3196 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, TLI: *this,
3197 hasHardQuad);
3198 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, TLI: *this,
3199 hasHardQuad);
3200 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, TLI: *this,
3201 hasHardQuad);
3202 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, TLI: *this,
3203 hasHardQuad);
3204 case ISD::BR_CC:
3205 return LowerBR_CC(Op, DAG, TLI: *this, hasHardQuad, isV9, is64Bit);
3206 case ISD::SELECT_CC:
3207 return LowerSELECT_CC(Op, DAG, TLI: *this, hasHardQuad, isV9, is64Bit);
3208 case ISD::VASTART: return LowerVASTART(Op, DAG, TLI: *this);
3209 case ISD::VAARG: return LowerVAARG(Op, DAG);
3210 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
3211 Subtarget);
3212 case ISD::STACKADDRESS:
3213 return LowerSTACKADDRESS(Op, DAG, Subtarget: *Subtarget);
3214
3215 case ISD::BSWAP:
3216 return LowerBSWAP(Op, DAG);
3217
3218 case ISD::LOAD: return LowerLOAD(Op, DAG);
3219 case ISD::STORE: return LowerSTORE(Op, DAG);
3220 case ISD::FADD:
3221 return LowerF128Op(Op, DAG, LibFunc: RTLIB::ADD_F128, numArgs: 2);
3222 case ISD::FSUB:
3223 return LowerF128Op(Op, DAG, LibFunc: RTLIB::SUB_F128, numArgs: 2);
3224 case ISD::FMUL:
3225 return LowerF128Op(Op, DAG, LibFunc: RTLIB::MUL_F128, numArgs: 2);
3226 case ISD::FDIV:
3227 return LowerF128Op(Op, DAG, LibFunc: RTLIB::DIV_F128, numArgs: 2);
3228 case ISD::FSQRT:
3229 return LowerF128Op(Op, DAG, LibFunc: RTLIB::SQRT_F128, numArgs: 1);
3230 case ISD::FABS:
3231 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
3232 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, TLI: *this);
3233 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, TLI: *this);
3234 case ISD::ATOMIC_LOAD:
3235 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
3236 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3237 }
3238}
3239
3240SDValue SparcTargetLowering::bitcastConstantFPToInt(ConstantFPSDNode *C,
3241 const SDLoc &DL,
3242 SelectionDAG &DAG) const {
3243 APInt V = C->getValueAPF().bitcastToAPInt();
3244 SDValue Lo = DAG.getConstant(Val: V.zextOrTrunc(width: 32), DL, VT: MVT::i32);
3245 SDValue Hi = DAG.getConstant(Val: V.lshr(shiftAmt: 32).zextOrTrunc(width: 32), DL, VT: MVT::i32);
3246 if (DAG.getDataLayout().isLittleEndian())
3247 std::swap(a&: Lo, b&: Hi);
3248 return DAG.getBuildVector(VT: MVT::v2i32, DL, Ops: {Hi, Lo});
3249}
3250
3251SDValue SparcTargetLowering::PerformBITCASTCombine(SDNode *N,
3252 DAGCombinerInfo &DCI) const {
3253 SDLoc dl(N);
3254 SDValue Src = N->getOperand(Num: 0);
3255
3256 if (isa<ConstantFPSDNode>(Val: Src) && N->getSimpleValueType(ResNo: 0) == MVT::v2i32 &&
3257 Src.getSimpleValueType() == MVT::f64)
3258 return bitcastConstantFPToInt(C: cast<ConstantFPSDNode>(Val&: Src), DL: dl, DAG&: DCI.DAG);
3259
3260 return SDValue();
3261}
3262
3263SDValue SparcTargetLowering::PerformBSWAPCombine(SDNode *N,
3264 DAGCombinerInfo &DCI) const {
3265 SDLoc DL(N);
3266 SelectionDAG &DAG = DCI.DAG;
3267 SDValue Op = N->getOperand(Num: 0);
3268 EVT VT = N->getValueType(ResNo: 0);
3269 auto *LN = dyn_cast<LoadSDNode>(Val: Op.getNode());
3270
3271 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
3272 bool IsAlignedLoad = LN && ISD::isNormalLoad(N: Op.getNode()) &&
3273 LN->getAlign() >= VT.getScalarStoreSize();
3274
3275 // Turn BSWAP (aligned-LOAD) -> ld*a #ASI_P(_L) on V9.
3276 if (Subtarget->isV9() && IsAlignedLoad && Op.getNode()->hasOneUse() &&
3277 (VT == MVT::i16 || VT == MVT::i32 ||
3278 (Subtarget->is64Bit() && VT == MVT::i64))) {
3279 SDValue Load = Op;
3280 auto *LD = cast<LoadSDNode>(Val&: Load);
3281
3282 // Create the byte-swapping load.
3283 SDValue Ops[] = {LD->getChain(), LD->getBasePtr(), DAG.getValueType(VT)};
3284
3285 SDValue BSLoad = DAG.getMemIntrinsicNode(
3286 Opcode: IsLittleEndian ? SPISD::LOAD_BIG : SPISD::LOAD_LITTLE, dl: DL,
3287 VTList: DAG.getVTList(VT1: VT == MVT::i64 ? MVT::i64 : MVT::i32, VT2: MVT::Other), Ops,
3288 MemVT: LD->getMemoryVT(), MMO: LD->getMemOperand());
3289
3290 // If this is an i16 load, insert the truncate.
3291 SDValue ResVal = BSLoad;
3292 if (VT == MVT::i16)
3293 ResVal = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i16, Operand: BSLoad);
3294
3295 return DCI.CombineTo(N, Res: ResVal);
3296 }
3297
3298 return SDValue();
3299}
3300
3301SDValue SparcTargetLowering::PerformSTORECombine(SDNode *N,
3302 DAGCombinerInfo &DCI) const {
3303 SDLoc DL(N);
3304 SelectionDAG &DAG = DCI.DAG;
3305 SDValue Op = N->getOperand(Num: 1);
3306 EVT VT = Op.getValueType();
3307 EVT MemVT = cast<StoreSDNode>(Val: N)->getMemoryVT();
3308 unsigned Opcode = Op.getOpcode();
3309 auto *SN = dyn_cast<StoreSDNode>(Val: N);
3310
3311 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
3312 bool IsAlignedStore = SN && SN->getAlign() >= MemVT.getScalarStoreSize();
3313
3314 // Turn aligned-STORE (BSWAP) -> st*a #ASI_P(_L) on V9.
3315 if (Subtarget->isV9() && Opcode == ISD::BSWAP && Op.getNode()->hasOneUse() &&
3316 IsAlignedStore &&
3317 (VT == MVT::i16 || VT == MVT::i32 ||
3318 (Subtarget->is64Bit() && VT == MVT::i64))) {
3319
3320 // st*a can only handle simple types and it makes no sense to store less
3321 // than two bytes in byte-reversed order.
3322 if (MemVT.getSizeInBits() < 16)
3323 return SDValue();
3324
3325 SDValue BSwapOp = Op.getOperand(i: 0);
3326 // Do an any-extend to 32-bits if this is a half-word input.
3327 if (BSwapOp.getValueType() == MVT::i16)
3328 BSwapOp = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i32, Operand: BSwapOp);
3329
3330 // If the type of BSWAP operand is wider than stored memory width
3331 // it needs to be shifted to the right side before st*a.
3332 if (VT.bitsGT(VT: MemVT)) {
3333 unsigned Shift = VT.getSizeInBits() - MemVT.getSizeInBits();
3334 BSwapOp = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: BSwapOp,
3335 N2: DAG.getShiftAmountConstant(Val: Shift, VT, DL));
3336 }
3337
3338 SDValue Ops[] = {N->getOperand(Num: 0), BSwapOp, N->getOperand(Num: 2),
3339 DAG.getValueType(MemVT)};
3340 return DAG.getMemIntrinsicNode(
3341 Opcode: IsLittleEndian ? SPISD::STORE_BIG : SPISD::STORE_LITTLE, dl: DL,
3342 VTList: DAG.getVTList(VT: MVT::Other), Ops, MemVT: cast<StoreSDNode>(Val: N)->getMemoryVT(),
3343 MMO: cast<StoreSDNode>(Val: N)->getMemOperand());
3344 }
3345
3346 return SDValue();
3347}
3348
3349SDValue SparcTargetLowering::PerformDAGCombine(SDNode *N,
3350 DAGCombinerInfo &DCI) const {
3351 switch (N->getOpcode()) {
3352 default:
3353 break;
3354 case ISD::BITCAST:
3355 return PerformBITCASTCombine(N, DCI);
3356 case ISD::BSWAP:
3357 return PerformBSWAPCombine(N, DCI);
3358 case ISD::STORE:
3359 return PerformSTORECombine(N, DCI);
3360 }
3361 return SDValue();
3362}
3363
3364MachineBasicBlock *
3365SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3366 MachineBasicBlock *BB) const {
3367 switch (MI.getOpcode()) {
3368 default: llvm_unreachable("Unknown SELECT_CC!");
3369 case SP::SELECT_CC_Int_ICC:
3370 case SP::SELECT_CC_FP_ICC:
3371 case SP::SELECT_CC_DFP_ICC:
3372 case SP::SELECT_CC_QFP_ICC:
3373 if (Subtarget->isV9())
3374 return expandSelectCC(MI, BB, BROpcode: SP::BPICC);
3375 return expandSelectCC(MI, BB, BROpcode: SP::BCOND);
3376 case SP::SELECT_CC_Int_XCC:
3377 case SP::SELECT_CC_FP_XCC:
3378 case SP::SELECT_CC_DFP_XCC:
3379 case SP::SELECT_CC_QFP_XCC:
3380 return expandSelectCC(MI, BB, BROpcode: SP::BPXCC);
3381 case SP::SELECT_CC_Int_FCC:
3382 case SP::SELECT_CC_FP_FCC:
3383 case SP::SELECT_CC_DFP_FCC:
3384 case SP::SELECT_CC_QFP_FCC:
3385 if (Subtarget->isV9())
3386 return expandSelectCC(MI, BB, BROpcode: SP::FBCOND_V9);
3387 return expandSelectCC(MI, BB, BROpcode: SP::FBCOND);
3388 }
3389}
3390
3391MachineBasicBlock *
3392SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
3393 unsigned BROpcode) const {
3394 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
3395 DebugLoc dl = MI.getDebugLoc();
3396 unsigned CC = (SPCC::CondCodes)MI.getOperand(i: 3).getImm();
3397
3398 // To "insert" a SELECT_CC instruction, we actually have to insert the
3399 // triangle control-flow pattern. The incoming instruction knows the
3400 // destination vreg to set, the condition code register to branch on, the
3401 // true/false values to select between, and the condition code for the branch.
3402 //
3403 // We produce the following control flow:
3404 // ThisMBB
3405 // | \
3406 // | IfFalseMBB
3407 // | /
3408 // SinkMBB
3409 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3410 MachineFunction::iterator It = ++BB->getIterator();
3411
3412 MachineBasicBlock *ThisMBB = BB;
3413 MachineFunction *F = BB->getParent();
3414 MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
3415 MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
3416 F->insert(MBBI: It, MBB: IfFalseMBB);
3417 F->insert(MBBI: It, MBB: SinkMBB);
3418
3419 // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
3420 SinkMBB->splice(Where: SinkMBB->begin(), Other: ThisMBB,
3421 From: std::next(x: MachineBasicBlock::iterator(MI)), To: ThisMBB->end());
3422 SinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: ThisMBB);
3423
3424 // Set the new successors for ThisMBB.
3425 ThisMBB->addSuccessor(Succ: IfFalseMBB);
3426 ThisMBB->addSuccessor(Succ: SinkMBB);
3427
3428 BuildMI(BB: ThisMBB, MIMD: dl, MCID: TII.get(Opcode: BROpcode))
3429 .addMBB(MBB: SinkMBB)
3430 .addImm(Val: CC);
3431
3432 // IfFalseMBB just falls through to SinkMBB.
3433 IfFalseMBB->addSuccessor(Succ: SinkMBB);
3434
3435 // %Result = phi [ %TrueValue, ThisMBB ], [ %FalseValue, IfFalseMBB ]
3436 BuildMI(BB&: *SinkMBB, I: SinkMBB->begin(), MIMD: dl, MCID: TII.get(Opcode: SP::PHI),
3437 DestReg: MI.getOperand(i: 0).getReg())
3438 .addReg(RegNo: MI.getOperand(i: 1).getReg())
3439 .addMBB(MBB: ThisMBB)
3440 .addReg(RegNo: MI.getOperand(i: 2).getReg())
3441 .addMBB(MBB: IfFalseMBB);
3442
3443 MI.eraseFromParent(); // The pseudo instruction is gone now.
3444 return SinkMBB;
3445}
3446
3447//===----------------------------------------------------------------------===//
3448// Sparc Inline Assembly Support
3449//===----------------------------------------------------------------------===//
3450
3451/// getConstraintType - Given a constraint letter, return the type of
3452/// constraint it is for this target.
3453SparcTargetLowering::ConstraintType
3454SparcTargetLowering::getConstraintType(StringRef Constraint) const {
3455 if (Constraint.size() == 1) {
3456 switch (Constraint[0]) {
3457 default: break;
3458 case 'r':
3459 case 'f':
3460 case 'e':
3461 return C_RegisterClass;
3462 case 'I': // SIMM13
3463 return C_Immediate;
3464 }
3465 }
3466
3467 return TargetLowering::getConstraintType(Constraint);
3468}
3469
3470TargetLowering::ConstraintWeight SparcTargetLowering::
3471getSingleConstraintMatchWeight(AsmOperandInfo &info,
3472 const char *constraint) const {
3473 ConstraintWeight weight = CW_Invalid;
3474 Value *CallOperandVal = info.CallOperandVal;
3475 // If we don't have a value, we can't do a match,
3476 // but allow it at the lowest weight.
3477 if (!CallOperandVal)
3478 return CW_Default;
3479
3480 // Look at the constraint type.
3481 switch (*constraint) {
3482 default:
3483 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3484 break;
3485 case 'I': // SIMM13
3486 if (ConstantInt *C = dyn_cast<ConstantInt>(Val: info.CallOperandVal)) {
3487 if (isInt<13>(x: C->getSExtValue()))
3488 weight = CW_Constant;
3489 }
3490 break;
3491 }
3492 return weight;
3493}
3494
3495/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3496/// vector. If it is invalid, don't add anything to Ops.
3497void SparcTargetLowering::LowerAsmOperandForConstraint(
3498 SDValue Op, StringRef Constraint, std::vector<SDValue> &Ops,
3499 SelectionDAG &DAG) const {
3500 SDValue Result;
3501
3502 // Only support length 1 constraints for now.
3503 if (Constraint.size() > 1)
3504 return;
3505
3506 char ConstraintLetter = Constraint[0];
3507 switch (ConstraintLetter) {
3508 default: break;
3509 case 'I':
3510 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
3511 if (isInt<13>(x: C->getSExtValue())) {
3512 Result = DAG.getSignedTargetConstant(Val: C->getSExtValue(), DL: SDLoc(Op),
3513 VT: Op.getValueType());
3514 break;
3515 }
3516 return;
3517 }
3518 }
3519
3520 if (Result.getNode()) {
3521 Ops.push_back(x: Result);
3522 return;
3523 }
3524 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3525}
3526
3527std::pair<unsigned, const TargetRegisterClass *>
3528SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3529 StringRef Constraint,
3530 MVT VT) const {
3531 if (Constraint.empty())
3532 return std::make_pair(x: 0U, y: nullptr);
3533
3534 if (Constraint.size() == 1) {
3535 switch (Constraint[0]) {
3536 case 'r':
3537 if (VT == MVT::v2i32)
3538 return std::make_pair(x: 0U, y: &SP::IntPairRegClass);
3539 else if (Subtarget->is64Bit())
3540 return std::make_pair(x: 0U, y: &SP::I64RegsRegClass);
3541 else
3542 return std::make_pair(x: 0U, y: &SP::IntRegsRegClass);
3543 case 'f':
3544 if (VT == MVT::f32 || VT == MVT::i32)
3545 return std::make_pair(x: 0U, y: &SP::FPRegsRegClass);
3546 else if (VT == MVT::f64 || VT == MVT::i64)
3547 return std::make_pair(x: 0U, y: &SP::LowDFPRegsRegClass);
3548 else if (VT == MVT::f128)
3549 return std::make_pair(x: 0U, y: &SP::LowQFPRegsRegClass);
3550 // This will generate an error message
3551 return std::make_pair(x: 0U, y: nullptr);
3552 case 'e':
3553 if (VT == MVT::f32 || VT == MVT::i32)
3554 return std::make_pair(x: 0U, y: &SP::FPRegsRegClass);
3555 else if (VT == MVT::f64 || VT == MVT::i64 )
3556 return std::make_pair(x: 0U, y: &SP::DFPRegsRegClass);
3557 else if (VT == MVT::f128)
3558 return std::make_pair(x: 0U, y: &SP::QFPRegsRegClass);
3559 // This will generate an error message
3560 return std::make_pair(x: 0U, y: nullptr);
3561 }
3562 }
3563
3564 if (Constraint.front() != '{')
3565 return std::make_pair(x: 0U, y: nullptr);
3566
3567 assert(Constraint.back() == '}' && "Not a brace enclosed constraint?");
3568 StringRef RegName(Constraint.data() + 1, Constraint.size() - 2);
3569 if (RegName.empty())
3570 return std::make_pair(x: 0U, y: nullptr);
3571
3572 unsigned long long RegNo;
3573 // Handle numbered register aliases.
3574 if (RegName[0] == 'r' &&
3575 getAsUnsignedInteger(Str: RegName.begin() + 1, Radix: 10, Result&: RegNo)) {
3576 // r0-r7 -> g0-g7
3577 // r8-r15 -> o0-o7
3578 // r16-r23 -> l0-l7
3579 // r24-r31 -> i0-i7
3580 if (RegNo > 31)
3581 return std::make_pair(x: 0U, y: nullptr);
3582 const char RegTypes[] = {'g', 'o', 'l', 'i'};
3583 char RegType = RegTypes[RegNo / 8];
3584 char RegIndex = '0' + (RegNo % 8);
3585 char Tmp[] = {'{', RegType, RegIndex, '}', 0};
3586 return getRegForInlineAsmConstraint(TRI, Constraint: Tmp, VT);
3587 }
3588
3589 // Rewrite the fN constraint according to the value type if needed.
3590 if (VT != MVT::f32 && VT != MVT::Other && RegName[0] == 'f' &&
3591 getAsUnsignedInteger(Str: RegName.begin() + 1, Radix: 10, Result&: RegNo)) {
3592 if (VT == MVT::f64 && (RegNo % 2 == 0)) {
3593 return getRegForInlineAsmConstraint(
3594 TRI, Constraint: StringRef("{d" + utostr(X: RegNo / 2) + "}"), VT);
3595 } else if (VT == MVT::f128 && (RegNo % 4 == 0)) {
3596 return getRegForInlineAsmConstraint(
3597 TRI, Constraint: StringRef("{q" + utostr(X: RegNo / 4) + "}"), VT);
3598 } else {
3599 return std::make_pair(x: 0U, y: nullptr);
3600 }
3601 }
3602
3603 auto ResultPair =
3604 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3605 if (!ResultPair.second)
3606 return std::make_pair(x: 0U, y: nullptr);
3607
3608 // Force the use of I64Regs over IntRegs for 64-bit values.
3609 if (Subtarget->is64Bit() && VT == MVT::i64) {
3610 assert(ResultPair.second == &SP::IntRegsRegClass &&
3611 "Unexpected register class");
3612 return std::make_pair(x&: ResultPair.first, y: &SP::I64RegsRegClass);
3613 }
3614
3615 return ResultPair;
3616}
3617
3618bool
3619SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3620 // The Sparc target isn't yet aware of offsets.
3621 return false;
3622}
3623
3624void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3625 SmallVectorImpl<SDValue>& Results,
3626 SelectionDAG &DAG) const {
3627
3628 SDLoc dl(N);
3629
3630 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3631
3632 switch (N->getOpcode()) {
3633 default:
3634 llvm_unreachable("Do not know how to custom type legalize this operation!");
3635
3636 case ISD::FP_TO_SINT:
3637 case ISD::FP_TO_UINT:
3638 // Custom lower only if it involves f128 or i64.
3639 if (N->getOperand(Num: 0).getValueType() != MVT::f128
3640 || N->getValueType(ResNo: 0) != MVT::i64)
3641 return;
3642 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3643 ? RTLIB::FPTOSINT_F128_I64
3644 : RTLIB::FPTOUINT_F128_I64);
3645
3646 Results.push_back(Elt: LowerF128Op(Op: SDValue(N, 0), DAG, LibFunc: libCall, numArgs: 1));
3647 return;
3648 case ISD::READCYCLECOUNTER: {
3649 assert(Subtarget->hasLeonCycleCounter());
3650 SDValue Lo = DAG.getCopyFromReg(Chain: N->getOperand(Num: 0), dl, Reg: SP::ASR23, VT: MVT::i32);
3651 SDValue Hi = DAG.getCopyFromReg(Chain: Lo, dl, Reg: SP::G0, VT: MVT::i32);
3652 SDValue Ops[] = { Lo, Hi };
3653 SDValue Pair = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, Ops);
3654 Results.push_back(Elt: Pair);
3655 Results.push_back(Elt: N->getOperand(Num: 0));
3656 return;
3657 }
3658 case ISD::SINT_TO_FP:
3659 case ISD::UINT_TO_FP:
3660 // Custom lower only if it involves f128 or i64.
3661 if (N->getValueType(ResNo: 0) != MVT::f128
3662 || N->getOperand(Num: 0).getValueType() != MVT::i64)
3663 return;
3664
3665 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3666 ? RTLIB::SINTTOFP_I64_F128
3667 : RTLIB::UINTTOFP_I64_F128);
3668
3669 Results.push_back(Elt: LowerF128Op(Op: SDValue(N, 0), DAG, LibFunc: libCall, numArgs: 1));
3670 return;
3671 case ISD::LOAD: {
3672 LoadSDNode *Ld = cast<LoadSDNode>(Val: N);
3673 // Custom handling only for i64: turn i64 load into a v2i32 load,
3674 // and a bitcast.
3675 if (Ld->getValueType(ResNo: 0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64)
3676 return;
3677
3678 SDLoc dl(N);
3679 SDValue LoadRes = DAG.getExtLoad(
3680 ExtType: Ld->getExtensionType(), dl, VT: MVT::v2i32, Chain: Ld->getChain(),
3681 Ptr: Ld->getBasePtr(), PtrInfo: Ld->getPointerInfo(), MemVT: MVT::v2i32, Alignment: Ld->getBaseAlign(),
3682 MMOFlags: Ld->getMemOperand()->getFlags(), AAInfo: Ld->getAAInfo());
3683
3684 SDValue Res = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i64, Operand: LoadRes);
3685 Results.push_back(Elt: Res);
3686 Results.push_back(Elt: LoadRes.getValue(R: 1));
3687 return;
3688 }
3689 }
3690}
3691
3692// Override to enable LOAD_STACK_GUARD lowering on Linux.
3693bool SparcTargetLowering::useLoadStackGuardNode(const Module &M) const {
3694 if (!Subtarget->getTargetTriple().isOSLinux())
3695 return TargetLowering::useLoadStackGuardNode(M);
3696 return true;
3697}
3698
3699bool SparcTargetLowering::isFNegFree(EVT VT) const {
3700 if (Subtarget->isVIS3())
3701 return VT == MVT::f32 || VT == MVT::f64;
3702 return false;
3703}
3704
3705bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
3706 bool ForCodeSize) const {
3707 if (VT != MVT::f32 && VT != MVT::f64)
3708 return false;
3709 if (Subtarget->isVIS() && Imm.isZero())
3710 return true;
3711 if (Subtarget->isVIS3())
3712 return Imm.isExactlyValue(V: +0.5) || Imm.isExactlyValue(V: -0.5) ||
3713 Imm.getExactLog2Abs() == -1;
3714 return false;
3715}
3716
3717bool SparcTargetLowering::isCtlzFast() const { return Subtarget->isVIS3(); }
3718
3719bool SparcTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
3720 // We lack native cttz, however,
3721 // On 64-bit targets it is cheap to implement it in terms of popc.
3722 if (Subtarget->is64Bit() && Subtarget->usePopc())
3723 return true;
3724 // Otherwise, implementing cttz in terms of ctlz is still cheap.
3725 return isCheapToSpeculateCtlz(Ty);
3726}
3727
3728bool SparcTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
3729 EVT VT) const {
3730 return Subtarget->isUA2007() && !Subtarget->useSoftFloat();
3731}
3732
3733void SparcTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
3734 SDNode *Node) const {
3735 assert(MI.getOpcode() == SP::SUBCCrr || MI.getOpcode() == SP::SUBCCri);
3736 // If the result is dead, replace it with %g0.
3737 if (!Node->hasAnyUseOfValue(Value: 0))
3738 MI.getOperand(i: 0).setReg(SP::G0);
3739}
3740
3741Instruction *SparcTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
3742 Instruction *Inst,
3743 AtomicOrdering Ord) const {
3744 bool HasStoreSemantics =
3745 isa<AtomicCmpXchgInst, AtomicRMWInst, StoreInst>(Val: Inst);
3746 if (HasStoreSemantics && isReleaseOrStronger(AO: Ord))
3747 return Builder.CreateFence(Ordering: AtomicOrdering::Release);
3748 return nullptr;
3749}
3750
3751Instruction *SparcTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
3752 Instruction *Inst,
3753 AtomicOrdering Ord) const {
3754 // V8 loads already come with implicit acquire barrier so there's no need to
3755 // emit it again.
3756 bool HasLoadSemantics = isa<AtomicCmpXchgInst, AtomicRMWInst, LoadInst>(Val: Inst);
3757 if (Subtarget->isV9() && HasLoadSemantics && isAcquireOrStronger(AO: Ord))
3758 return Builder.CreateFence(Ordering: AtomicOrdering::Acquire);
3759
3760 // SC plain stores would need a trailing full barrier.
3761 if (isa<StoreInst>(Val: Inst) && Ord == AtomicOrdering::SequentiallyConsistent)
3762 return Builder.CreateFence(Ordering: Ord);
3763 return nullptr;
3764}
3765