1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the interfaces that Sparc uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcISelLowering.h"
15#include "MCTargetDesc/SparcMCTargetDesc.h"
16#include "SparcMachineFunctionInfo.h"
17#include "SparcRegisterInfo.h"
18#include "SparcSelectionDAGInfo.h"
19#include "SparcTargetMachine.h"
20#include "SparcTargetObjectFile.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/ADT/StringSwitch.h"
23#include "llvm/BinaryFormat/ELF.h"
24#include "llvm/CodeGen/CallingConvLower.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/SelectionDAG.h"
30#include "llvm/CodeGen/SelectionDAGNodes.h"
31#include "llvm/CodeGen/TargetLowering.h"
32#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
33#include "llvm/IR/DerivedTypes.h"
34#include "llvm/IR/DiagnosticInfo.h"
35#include "llvm/IR/Function.h"
36#include "llvm/IR/IRBuilder.h"
37#include "llvm/IR/Module.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/KnownBits.h"
40using namespace llvm;
41
42
43//===----------------------------------------------------------------------===//
44// Calling Convention Implementation
45//===----------------------------------------------------------------------===//
46
47static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
48 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
49 ISD::ArgFlagsTy &ArgFlags, CCState &State)
50{
51 assert (ArgFlags.isSRet());
52
53 // Assign SRet argument.
54 State.addLoc(V: CCValAssign::getCustomMem(ValNo, ValVT,
55 Offset: 0,
56 LocVT, HTP: LocInfo));
57 return true;
58}
59
60static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT,
61 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
62 ISD::ArgFlagsTy &ArgFlags, CCState &State)
63{
64 static const MCPhysReg RegList[] = {
65 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
66 };
67 // Try to get first reg.
68 if (Register Reg = State.AllocateReg(Regs: RegList)) {
69 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
70 } else {
71 // Assign whole thing in stack.
72 State.addLoc(V: CCValAssign::getCustomMem(
73 ValNo, ValVT, Offset: State.AllocateStack(Size: 8, Alignment: Align(4)), LocVT, HTP: LocInfo));
74 return true;
75 }
76
77 // Try to get second reg.
78 if (Register Reg = State.AllocateReg(Regs: RegList))
79 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
80 else
81 State.addLoc(V: CCValAssign::getCustomMem(
82 ValNo, ValVT, Offset: State.AllocateStack(Size: 4, Alignment: Align(4)), LocVT, HTP: LocInfo));
83 return true;
84}
85
86static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT,
87 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
88 ISD::ArgFlagsTy &ArgFlags, CCState &State)
89{
90 static const MCPhysReg RegList[] = {
91 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
92 };
93
94 // Try to get first reg.
95 if (Register Reg = State.AllocateReg(Regs: RegList))
96 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
97 else
98 return false;
99
100 // Try to get second reg.
101 if (Register Reg = State.AllocateReg(Regs: RegList))
102 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
103 else
104 return false;
105
106 return true;
107}
108
109// Allocate a full-sized argument for the 64-bit ABI.
110static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT,
111 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
112 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
113 assert((LocVT == MVT::f32 || LocVT == MVT::f128
114 || LocVT.getSizeInBits() == 64) &&
115 "Can't handle non-64 bits locations");
116
117 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
118 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
119 Align alignment =
120 (LocVT == MVT::f128 || ArgFlags.isSplit()) ? Align(16) : Align(8);
121 unsigned Offset = State.AllocateStack(Size: size, Alignment: alignment);
122 unsigned Reg = 0;
123
124 if (LocVT == MVT::i64 && Offset < 6*8)
125 // Promote integers to %i0-%i5.
126 Reg = SP::I0 + Offset/8;
127 else if (LocVT == MVT::f64 && Offset < 16*8)
128 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
129 Reg = SP::D0 + Offset/8;
130 else if (LocVT == MVT::f32 && Offset < 16*8)
131 // Promote floats to %f1, %f3, ...
132 Reg = SP::F1 + Offset/4;
133 else if (LocVT == MVT::f128 && Offset < 16*8)
134 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
135 Reg = SP::Q0 + Offset/16;
136
137 // Promote to register when possible, otherwise use the stack slot.
138 if (Reg) {
139 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
140 return true;
141 }
142
143 // Bail out if this is a return CC and we run out of registers to place
144 // values into.
145 if (IsReturn)
146 return false;
147
148 // This argument goes on the stack in an 8-byte slot.
149 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
150 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
151 if (LocVT == MVT::f32)
152 Offset += 4;
153
154 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, HTP: LocInfo));
155 return true;
156}
157
158// Allocate a half-sized argument for the 64-bit ABI.
159//
160// This is used when passing { float, int } structs by value in registers.
161static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT,
162 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
163 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
164 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
165 unsigned Offset = State.AllocateStack(Size: 4, Alignment: Align(4));
166
167 if (LocVT == MVT::f32 && Offset < 16*8) {
168 // Promote floats to %f0-%f31.
169 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg: SP::F0 + Offset/4,
170 LocVT, HTP: LocInfo));
171 return true;
172 }
173
174 if (LocVT == MVT::i32 && Offset < 6*8) {
175 // Promote integers to %i0-%i5, using half the register.
176 unsigned Reg = SP::I0 + Offset/8;
177 LocVT = MVT::i64;
178 LocInfo = CCValAssign::AExt;
179
180 // Set the Custom bit if this i32 goes in the high bits of a register.
181 if (Offset % 8 == 0)
182 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg,
183 LocVT, HTP: LocInfo));
184 else
185 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
186 return true;
187 }
188
189 // Bail out if this is a return CC and we run out of registers to place
190 // values into.
191 if (IsReturn)
192 return false;
193
194 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, HTP: LocInfo));
195 return true;
196}
197
198static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
199 CCValAssign::LocInfo &LocInfo,
200 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
201 return Analyze_CC_Sparc64_Full(IsReturn: false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
202 State);
203}
204
205static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
206 CCValAssign::LocInfo &LocInfo,
207 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
208 return Analyze_CC_Sparc64_Half(IsReturn: false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
209 State);
210}
211
212static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
213 CCValAssign::LocInfo &LocInfo,
214 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
215 return Analyze_CC_Sparc64_Full(IsReturn: true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
216 State);
217}
218
219static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
220 CCValAssign::LocInfo &LocInfo,
221 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
222 return Analyze_CC_Sparc64_Half(IsReturn: true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
223 State);
224}
225
226#include "SparcGenCallingConv.inc"
227
228// The calling conventions in SparcCallingConv.td are described in terms of the
229// callee's register window. This function translates registers to the
230// corresponding caller window %o register.
231static unsigned toCallerWindow(unsigned Reg) {
232 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
233 "Unexpected enum");
234 if (Reg >= SP::I0 && Reg <= SP::I7)
235 return Reg - SP::I0 + SP::O0;
236 return Reg;
237}
238
239bool SparcTargetLowering::CanLowerReturn(
240 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
241 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
242 const Type *RetTy) const {
243 SmallVector<CCValAssign, 16> RVLocs;
244 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
245 return CCInfo.CheckReturn(Outs, Fn: Subtarget->is64Bit() ? RetCC_Sparc64
246 : RetCC_Sparc32);
247}
248
249SDValue
250SparcTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
251 bool IsVarArg,
252 const SmallVectorImpl<ISD::OutputArg> &Outs,
253 const SmallVectorImpl<SDValue> &OutVals,
254 const SDLoc &DL, SelectionDAG &DAG) const {
255 if (Subtarget->is64Bit())
256 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
257 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
258}
259
260SDValue
261SparcTargetLowering::LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
262 bool IsVarArg,
263 const SmallVectorImpl<ISD::OutputArg> &Outs,
264 const SmallVectorImpl<SDValue> &OutVals,
265 const SDLoc &DL, SelectionDAG &DAG) const {
266 MachineFunction &MF = DAG.getMachineFunction();
267
268 // CCValAssign - represent the assignment of the return value to locations.
269 SmallVector<CCValAssign, 16> RVLocs;
270
271 // CCState - Info about the registers and stack slot.
272 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
273 *DAG.getContext());
274
275 // Analyze return values.
276 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_Sparc32);
277
278 SDValue Glue;
279 SmallVector<SDValue, 4> RetOps(1, Chain);
280 // Make room for the return address offset.
281 RetOps.push_back(Elt: SDValue());
282
283 // Copy the result values into the output registers.
284 for (unsigned i = 0, realRVLocIdx = 0;
285 i != RVLocs.size();
286 ++i, ++realRVLocIdx) {
287 CCValAssign &VA = RVLocs[i];
288 assert(VA.isRegLoc() && "Can only return in registers!");
289
290 SDValue Arg = OutVals[realRVLocIdx];
291
292 if (VA.needsCustom()) {
293 assert(VA.getLocVT() == MVT::v2i32);
294 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
295 // happen by default if this wasn't a legal type)
296
297 SDValue Part0 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32,
298 N1: Arg,
299 N2: DAG.getConstant(Val: 0, DL, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
300 SDValue Part1 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32,
301 N1: Arg,
302 N2: DAG.getConstant(Val: 1, DL, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
303
304 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Part0, Glue);
305 Glue = Chain.getValue(R: 1);
306 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
307 VA = RVLocs[++i]; // skip ahead to next loc
308 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Part1,
309 Glue);
310 } else
311 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Arg, Glue);
312
313 // Guarantee that all emitted copies are stuck together with flags.
314 Glue = Chain.getValue(R: 1);
315 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
316 }
317
318 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
319 // If the function returns a struct, copy the SRetReturnReg to I0
320 if (MF.getFunction().hasStructRetAttr()) {
321 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
322 Register Reg = SFI->getSRetReturnReg();
323 if (!Reg)
324 llvm_unreachable("sret virtual register not created in the entry block");
325 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
326 SDValue Val = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: PtrVT);
327 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SP::I0, N: Val, Glue);
328 Glue = Chain.getValue(R: 1);
329 RetOps.push_back(Elt: DAG.getRegister(Reg: SP::I0, VT: PtrVT));
330 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
331 }
332
333 RetOps[0] = Chain; // Update chain.
334 RetOps[1] = DAG.getConstant(Val: RetAddrOffset, DL, VT: MVT::i32);
335
336 // Add the glue if we have it.
337 if (Glue.getNode())
338 RetOps.push_back(Elt: Glue);
339
340 return DAG.getNode(Opcode: SPISD::RET_GLUE, DL, VT: MVT::Other, Ops: RetOps);
341}
342
343// Lower return values for the 64-bit ABI.
344// Return values are passed the exactly the same way as function arguments.
345SDValue
346SparcTargetLowering::LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
347 bool IsVarArg,
348 const SmallVectorImpl<ISD::OutputArg> &Outs,
349 const SmallVectorImpl<SDValue> &OutVals,
350 const SDLoc &DL, SelectionDAG &DAG) const {
351 // CCValAssign - represent the assignment of the return value to locations.
352 SmallVector<CCValAssign, 16> RVLocs;
353
354 // CCState - Info about the registers and stack slot.
355 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
356 *DAG.getContext());
357
358 // Analyze return values.
359 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_Sparc64);
360
361 SDValue Glue;
362 SmallVector<SDValue, 4> RetOps(1, Chain);
363
364 // The second operand on the return instruction is the return address offset.
365 // The return address is always %i7+8 with the 64-bit ABI.
366 RetOps.push_back(Elt: DAG.getConstant(Val: 8, DL, VT: MVT::i32));
367
368 // Copy the result values into the output registers.
369 for (unsigned i = 0; i != RVLocs.size(); ++i) {
370 CCValAssign &VA = RVLocs[i];
371 assert(VA.isRegLoc() && "Can only return in registers!");
372 SDValue OutVal = OutVals[i];
373
374 // Integer return values must be sign or zero extended by the callee.
375 switch (VA.getLocInfo()) {
376 case CCValAssign::Full: break;
377 case CCValAssign::SExt:
378 OutVal = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
379 break;
380 case CCValAssign::ZExt:
381 OutVal = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
382 break;
383 case CCValAssign::AExt:
384 OutVal = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
385 break;
386 default:
387 llvm_unreachable("Unknown loc info!");
388 }
389
390 // The custom bit on an i32 return value indicates that it should be passed
391 // in the high bits of the register.
392 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
393 OutVal = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: OutVal,
394 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
395
396 // The next value may go in the low bits of the same register.
397 // Handle both at once.
398 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
399 SDValue NV = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i64, Operand: OutVals[i+1]);
400 OutVal = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i64, N1: OutVal, N2: NV);
401 // Skip the next value, it's already done.
402 ++i;
403 }
404 }
405
406 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: OutVal, Glue);
407
408 // Guarantee that all emitted copies are stuck together with flags.
409 Glue = Chain.getValue(R: 1);
410 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
411 }
412
413 RetOps[0] = Chain; // Update chain.
414
415 // Add the flag if we have it.
416 if (Glue.getNode())
417 RetOps.push_back(Elt: Glue);
418
419 return DAG.getNode(Opcode: SPISD::RET_GLUE, DL, VT: MVT::Other, Ops: RetOps);
420}
421
422SDValue SparcTargetLowering::LowerFormalArguments(
423 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
424 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
425 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
426 if (Subtarget->is64Bit())
427 return LowerFormalArguments_64(Chain, CallConv, isVarArg: IsVarArg, Ins,
428 dl: DL, DAG, InVals);
429 return LowerFormalArguments_32(Chain, CallConv, isVarArg: IsVarArg, Ins,
430 dl: DL, DAG, InVals);
431}
432
433/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
434/// passed in either one or two GPRs, including FP values. TODO: we should
435/// pass FP values in FP registers for fastcc functions.
436SDValue SparcTargetLowering::LowerFormalArguments_32(
437 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
438 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
439 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
440 MachineFunction &MF = DAG.getMachineFunction();
441 MachineRegisterInfo &RegInfo = MF.getRegInfo();
442 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
443 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
444
445 // Assign locations to all of the incoming arguments.
446 SmallVector<CCValAssign, 16> ArgLocs;
447 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
448 *DAG.getContext());
449 CCInfo.AnalyzeFormalArguments(Ins, Fn: CC_Sparc32);
450
451 const unsigned StackOffset = 92;
452 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
453
454 unsigned InIdx = 0;
455 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
456 CCValAssign &VA = ArgLocs[i];
457 EVT LocVT = VA.getLocVT();
458
459 if (Ins[InIdx].Flags.isSRet()) {
460 if (InIdx != 0)
461 report_fatal_error(reason: "sparc only supports sret on the first parameter");
462 // Get SRet from [%fp+64].
463 int FrameIdx = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: 64, IsImmutable: true);
464 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
465 SDValue Arg =
466 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
467 InVals.push_back(Elt: Arg);
468 continue;
469 }
470
471 SDValue Arg;
472 if (VA.isRegLoc()) {
473 if (VA.needsCustom()) {
474 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
475
476 Register VRegHi = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
477 MF.getRegInfo().addLiveIn(Reg: VA.getLocReg(), vreg: VRegHi);
478 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, Reg: VRegHi, VT: MVT::i32);
479
480 assert(i+1 < e);
481 CCValAssign &NextVA = ArgLocs[++i];
482
483 SDValue LoVal;
484 if (NextVA.isMemLoc()) {
485 int FrameIdx = MF.getFrameInfo().
486 CreateFixedObject(Size: 4, SPOffset: StackOffset+NextVA.getLocMemOffset(),IsImmutable: true);
487 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
488 LoVal = DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
489 } else {
490 Register loReg = MF.addLiveIn(PReg: NextVA.getLocReg(),
491 RC: &SP::IntRegsRegClass);
492 LoVal = DAG.getCopyFromReg(Chain, dl, Reg: loReg, VT: MVT::i32);
493 }
494
495 if (IsLittleEndian)
496 std::swap(a&: LoVal, b&: HiVal);
497
498 SDValue WholeValue =
499 DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: LoVal, N2: HiVal);
500 WholeValue = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getLocVT(), Operand: WholeValue);
501 InVals.push_back(Elt: WholeValue);
502 continue;
503 }
504 Register VReg = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
505 MF.getRegInfo().addLiveIn(Reg: VA.getLocReg(), vreg: VReg);
506 Arg = DAG.getCopyFromReg(Chain, dl, Reg: VReg, VT: MVT::i32);
507 if (VA.getLocInfo() != CCValAssign::Indirect) {
508 if (VA.getLocVT() == MVT::f32)
509 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::f32, Operand: Arg);
510 else if (VA.getLocVT() != MVT::i32) {
511 Arg = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: MVT::i32, N1: Arg,
512 N2: DAG.getValueType(VA.getLocVT()));
513 Arg = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getLocVT(), Operand: Arg);
514 }
515 InVals.push_back(Elt: Arg);
516 continue;
517 }
518 } else {
519 assert(VA.isMemLoc());
520
521 unsigned Offset = VA.getLocMemOffset() + StackOffset;
522
523 if (VA.needsCustom()) {
524 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
525 // If it is double-word aligned, just load.
526 if (Offset % 8 == 0) {
527 int FI = MF.getFrameInfo().CreateFixedObject(Size: 8, SPOffset: Offset, IsImmutable: true);
528 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
529 SDValue Load = DAG.getLoad(VT: VA.getValVT(), dl, Chain, Ptr: FIPtr,
530 PtrInfo: MachinePointerInfo());
531 InVals.push_back(Elt: Load);
532 continue;
533 }
534
535 int FI = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: Offset, IsImmutable: true);
536 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
537 SDValue HiVal =
538 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
539 int FI2 = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: Offset + 4, IsImmutable: true);
540 SDValue FIPtr2 = DAG.getFrameIndex(FI: FI2, VT: PtrVT);
541
542 SDValue LoVal =
543 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr2, PtrInfo: MachinePointerInfo());
544
545 if (IsLittleEndian)
546 std::swap(a&: LoVal, b&: HiVal);
547
548 SDValue WholeValue =
549 DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: LoVal, N2: HiVal);
550 WholeValue = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getValVT(), Operand: WholeValue);
551 InVals.push_back(Elt: WholeValue);
552 continue;
553 }
554
555 int FI = MF.getFrameInfo().CreateFixedObject(Size: LocVT.getSizeInBits() / 8,
556 SPOffset: Offset, IsImmutable: true);
557 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
558 SDValue Load = DAG.getLoad(VT: LocVT, dl, Chain, Ptr: FIPtr,
559 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI));
560 if (VA.getLocInfo() != CCValAssign::Indirect) {
561 InVals.push_back(Elt: Load);
562 continue;
563 }
564 Arg = Load;
565 }
566
567 assert(VA.getLocInfo() == CCValAssign::Indirect);
568
569 SDValue ArgValue =
570 DAG.getLoad(VT: VA.getValVT(), dl, Chain, Ptr: Arg, PtrInfo: MachinePointerInfo());
571 InVals.push_back(Elt: ArgValue);
572
573 unsigned ArgIndex = Ins[InIdx].OrigArgIndex;
574 assert(Ins[InIdx].PartOffset == 0);
575 while (i + 1 != e && Ins[InIdx + 1].OrigArgIndex == ArgIndex) {
576 CCValAssign &PartVA = ArgLocs[i + 1];
577 unsigned PartOffset = Ins[InIdx + 1].PartOffset;
578 SDValue Address = DAG.getMemBasePlusOffset(
579 Base: ArgValue, Offset: TypeSize::getFixed(ExactSize: PartOffset), DL: dl);
580 InVals.push_back(Elt: DAG.getLoad(VT: PartVA.getValVT(), dl, Chain, Ptr: Address,
581 PtrInfo: MachinePointerInfo()));
582 ++i;
583 ++InIdx;
584 }
585 }
586
587 if (MF.getFunction().hasStructRetAttr()) {
588 // Copy the SRet Argument to SRetReturnReg.
589 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
590 Register Reg = SFI->getSRetReturnReg();
591 if (!Reg) {
592 Reg = MF.getRegInfo().createVirtualRegister(RegClass: &SP::IntRegsRegClass);
593 SFI->setSRetReturnReg(Reg);
594 }
595 SDValue Copy = DAG.getCopyToReg(Chain: DAG.getEntryNode(), dl, Reg, N: InVals[0]);
596 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Copy, N2: Chain);
597 }
598
599 // Store remaining ArgRegs to the stack if this is a varargs function.
600 if (isVarArg) {
601 static const MCPhysReg ArgRegs[] = {
602 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
603 };
604 unsigned NumAllocated = CCInfo.getFirstUnallocated(Regs: ArgRegs);
605 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
606 unsigned ArgOffset = CCInfo.getStackSize();
607 if (NumAllocated == 6)
608 ArgOffset += StackOffset;
609 else {
610 assert(!ArgOffset);
611 ArgOffset = 68+4*NumAllocated;
612 }
613
614 // Remember the vararg offset for the va_start implementation.
615 FuncInfo->setVarArgsFrameOffset(ArgOffset);
616
617 std::vector<SDValue> OutChains;
618
619 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
620 Register VReg = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
621 MF.getRegInfo().addLiveIn(Reg: *CurArgReg, vreg: VReg);
622 SDValue Arg = DAG.getCopyFromReg(Chain: DAG.getRoot(), dl, Reg: VReg, VT: MVT::i32);
623
624 int FrameIdx = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: ArgOffset,
625 IsImmutable: true);
626 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
627
628 OutChains.push_back(
629 x: DAG.getStore(Chain: DAG.getRoot(), dl, Val: Arg, Ptr: FIPtr, PtrInfo: MachinePointerInfo()));
630 ArgOffset += 4;
631 }
632
633 if (!OutChains.empty()) {
634 OutChains.push_back(x: Chain);
635 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
636 }
637 }
638
639 return Chain;
640}
641
642// Lower formal arguments for the 64 bit ABI.
643SDValue SparcTargetLowering::LowerFormalArguments_64(
644 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
645 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
646 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
647 MachineFunction &MF = DAG.getMachineFunction();
648
649 // Analyze arguments according to CC_Sparc64.
650 SmallVector<CCValAssign, 16> ArgLocs;
651 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
652 *DAG.getContext());
653 CCInfo.AnalyzeFormalArguments(Ins, Fn: CC_Sparc64);
654
655 // The argument array begins at %fp+BIAS+128, after the register save area.
656 const unsigned ArgArea = 128;
657
658 for (const CCValAssign &VA : ArgLocs) {
659 if (VA.isRegLoc()) {
660 // This argument is passed in a register.
661 // All integer register arguments are promoted by the caller to i64.
662
663 // Create a virtual register for the promoted live-in value.
664 Register VReg = MF.addLiveIn(PReg: VA.getLocReg(),
665 RC: getRegClassFor(VT: VA.getLocVT()));
666 SDValue Arg = DAG.getCopyFromReg(Chain, dl: DL, Reg: VReg, VT: VA.getLocVT());
667
668 // Get the high bits for i32 struct elements.
669 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
670 Arg = DAG.getNode(Opcode: ISD::SRL, DL, VT: VA.getLocVT(), N1: Arg,
671 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
672
673 // The caller promoted the argument, so insert an Assert?ext SDNode so we
674 // won't promote the value again in this function.
675 switch (VA.getLocInfo()) {
676 case CCValAssign::SExt:
677 Arg = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: Arg,
678 N2: DAG.getValueType(VA.getValVT()));
679 break;
680 case CCValAssign::ZExt:
681 Arg = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: Arg,
682 N2: DAG.getValueType(VA.getValVT()));
683 break;
684 default:
685 break;
686 }
687
688 // Truncate the register down to the argument type.
689 if (VA.isExtInLoc())
690 Arg = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: Arg);
691
692 InVals.push_back(Elt: Arg);
693 continue;
694 }
695
696 // The registers are exhausted. This argument was passed on the stack.
697 assert(VA.isMemLoc());
698 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
699 // beginning of the arguments area at %fp+BIAS+128.
700 unsigned Offset = VA.getLocMemOffset() + ArgArea;
701 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
702 // Adjust offset for extended arguments, SPARC is big-endian.
703 // The caller will have written the full slot with extended bytes, but we
704 // prefer our own extending loads.
705 if (VA.isExtInLoc())
706 Offset += 8 - ValSize;
707 int FI = MF.getFrameInfo().CreateFixedObject(Size: ValSize, SPOffset: Offset, IsImmutable: true);
708 InVals.push_back(
709 Elt: DAG.getLoad(VT: VA.getValVT(), dl: DL, Chain,
710 Ptr: DAG.getFrameIndex(FI, VT: getPointerTy(DL: MF.getDataLayout())),
711 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
712 }
713
714 if (!IsVarArg)
715 return Chain;
716
717 // This function takes variable arguments, some of which may have been passed
718 // in registers %i0-%i5. Variable floating point arguments are never passed
719 // in floating point registers. They go on %i0-%i5 or on the stack like
720 // integer arguments.
721 //
722 // The va_start intrinsic needs to know the offset to the first variable
723 // argument.
724 unsigned ArgOffset = CCInfo.getStackSize();
725 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
726 // Skip the 128 bytes of register save area.
727 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
728 Subtarget->getStackPointerBias());
729
730 // Save the variable arguments that were passed in registers.
731 // The caller is required to reserve stack space for 6 arguments regardless
732 // of how many arguments were actually passed.
733 SmallVector<SDValue, 8> OutChains;
734 for (; ArgOffset < 6*8; ArgOffset += 8) {
735 Register VReg = MF.addLiveIn(PReg: SP::I0 + ArgOffset/8, RC: &SP::I64RegsRegClass);
736 SDValue VArg = DAG.getCopyFromReg(Chain, dl: DL, Reg: VReg, VT: MVT::i64);
737 int FI = MF.getFrameInfo().CreateFixedObject(Size: 8, SPOffset: ArgOffset + ArgArea, IsImmutable: true);
738 auto PtrVT = getPointerTy(DL: MF.getDataLayout());
739 OutChains.push_back(
740 Elt: DAG.getStore(Chain, dl: DL, Val: VArg, Ptr: DAG.getFrameIndex(FI, VT: PtrVT),
741 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
742 }
743
744 if (!OutChains.empty())
745 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: OutChains);
746
747 return Chain;
748}
749
750// Check whether any of the argument registers are reserved
751static bool isAnyArgRegReserved(const SparcRegisterInfo *TRI,
752 const MachineFunction &MF) {
753 // The register window design means that outgoing parameters at O*
754 // will appear in the callee as I*.
755 // Be conservative and check both sides of the register names.
756 bool Outgoing =
757 llvm::any_of(Range: SP::GPROutgoingArgRegClass, P: [TRI, &MF](MCPhysReg r) {
758 return TRI->isReservedReg(MF, Reg: r);
759 });
760 bool Incoming =
761 llvm::any_of(Range: SP::GPRIncomingArgRegClass, P: [TRI, &MF](MCPhysReg r) {
762 return TRI->isReservedReg(MF, Reg: r);
763 });
764 return Outgoing || Incoming;
765}
766
767static void emitReservedArgRegCallError(const MachineFunction &MF) {
768 const Function &F = MF.getFunction();
769 F.getContext().diagnose(DI: DiagnosticInfoUnsupported{
770 F, ("SPARC doesn't support"
771 " function calls if any of the argument registers is reserved.")});
772}
773
774SDValue
775SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
776 SmallVectorImpl<SDValue> &InVals) const {
777 if (Subtarget->is64Bit())
778 return LowerCall_64(CLI, InVals);
779 return LowerCall_32(CLI, InVals);
780}
781
782static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
783 const CallBase *Call) {
784 if (Call)
785 return Call->hasFnAttr(Kind: Attribute::ReturnsTwice);
786
787 const Function *CalleeFn = nullptr;
788 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
789 CalleeFn = dyn_cast<Function>(Val: G->getGlobal());
790 } else if (ExternalSymbolSDNode *E =
791 dyn_cast<ExternalSymbolSDNode>(Val&: Callee)) {
792 const Function &Fn = DAG.getMachineFunction().getFunction();
793 const Module *M = Fn.getParent();
794 const char *CalleeName = E->getSymbol();
795 CalleeFn = M->getFunction(Name: CalleeName);
796 }
797
798 if (!CalleeFn)
799 return false;
800 return CalleeFn->hasFnAttribute(Kind: Attribute::ReturnsTwice);
801}
802
803/// IsEligibleForTailCallOptimization - Check whether the call is eligible
804/// for tail call optimization.
805bool SparcTargetLowering::IsEligibleForTailCallOptimization(
806 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const {
807
808 auto &Outs = CLI.Outs;
809 auto &Caller = MF.getFunction();
810
811 // Do not tail call opt functions with "disable-tail-calls" attribute.
812 if (Caller.getFnAttribute(Kind: "disable-tail-calls").getValueAsString() == "true")
813 return false;
814
815 // Do not tail call opt if the stack is used to pass parameters.
816 // 64-bit targets have a slightly higher limit since the ABI requires
817 // to allocate some space even when all the parameters fit inside registers.
818 unsigned StackSizeLimit = Subtarget->is64Bit() ? 48 : 0;
819 if (CCInfo.getStackSize() > StackSizeLimit)
820 return false;
821
822 // Do not tail call opt if either the callee or caller returns
823 // a struct and the other does not.
824 if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
825 return false;
826
827 // Byval parameters hand the function a pointer directly into the stack area
828 // we want to reuse during a tail call.
829 for (auto &Arg : Outs)
830 if (Arg.Flags.isByVal())
831 return false;
832
833 return true;
834}
835
836// Lower a call for the 32-bit ABI.
837SDValue
838SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
839 SmallVectorImpl<SDValue> &InVals) const {
840 SelectionDAG &DAG = CLI.DAG;
841 SDLoc &dl = CLI.DL;
842 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
843 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
844 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
845 SDValue Chain = CLI.Chain;
846 SDValue Callee = CLI.Callee;
847 bool &isTailCall = CLI.IsTailCall;
848 CallingConv::ID CallConv = CLI.CallConv;
849 bool isVarArg = CLI.IsVarArg;
850 MachineFunction &MF = DAG.getMachineFunction();
851 LLVMContext &Ctx = *DAG.getContext();
852 EVT PtrVT = getPointerTy(DL: MF.getDataLayout());
853
854 // Analyze operands of the call, assigning locations to each operand.
855 SmallVector<CCValAssign, 16> ArgLocs;
856 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
857 *DAG.getContext());
858 CCInfo.AnalyzeCallOperands(Outs, Fn: CC_Sparc32);
859
860 isTailCall = isTailCall && IsEligibleForTailCallOptimization(
861 CCInfo, CLI, MF&: DAG.getMachineFunction());
862
863 // Get the size of the outgoing arguments stack space requirement.
864 unsigned ArgsSize = CCInfo.getStackSize();
865
866 // Keep stack frames 8-byte aligned.
867 ArgsSize = (ArgsSize+7) & ~7;
868
869 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
870
871 // Create local copies for byval args.
872 SmallVector<SDValue, 8> ByValArgs;
873 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
874 ISD::ArgFlagsTy Flags = Outs[i].Flags;
875 if (!Flags.isByVal())
876 continue;
877
878 SDValue Arg = OutVals[i];
879 unsigned Size = Flags.getByValSize();
880 Align Alignment = Flags.getNonZeroByValAlign();
881
882 if (Size > 0U) {
883 int FI = MFI.CreateStackObject(Size, Alignment, isSpillSlot: false);
884 SDValue FIPtr = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
885 SDValue SizeNode = DAG.getConstant(Val: Size, DL: dl, VT: MVT::i32);
886
887 Chain =
888 DAG.getMemcpy(Chain, dl, Dst: FIPtr, Src: Arg, Size: SizeNode, DstAlign: Alignment, SrcAlign: Alignment,
889 isVol: false, // isVolatile,
890 AlwaysInline: (Size <= 32), // AlwaysInline if size <= 32,
891 /*CI=*/nullptr, OverrideTailCall: std::nullopt, DstPtrInfo: MachinePointerInfo(),
892 SrcPtrInfo: MachinePointerInfo());
893 ByValArgs.push_back(Elt: FIPtr);
894 }
895 else {
896 SDValue nullVal;
897 ByValArgs.push_back(Elt: nullVal);
898 }
899 }
900
901 assert(!isTailCall || ArgsSize == 0);
902
903 if (!isTailCall)
904 Chain = DAG.getCALLSEQ_START(Chain, InSize: ArgsSize, OutSize: 0, DL: dl);
905
906 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
907 SmallVector<SDValue, 8> MemOpChains;
908
909 const unsigned StackOffset = 92;
910 bool hasStructRetAttr = false;
911 unsigned SRetArgSize = 0;
912 // Walk the register/memloc assignments, inserting copies/loads.
913 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
914 i != e;
915 ++i, ++realArgIdx) {
916 CCValAssign &VA = ArgLocs[i];
917 SDValue Arg = OutVals[realArgIdx];
918
919 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
920
921 // Use local copy if it is a byval arg.
922 if (Flags.isByVal()) {
923 Arg = ByValArgs[byvalArgIdx++];
924 if (!Arg) {
925 continue;
926 }
927 }
928
929 // Promote the value if needed.
930 switch (VA.getLocInfo()) {
931 default: llvm_unreachable("Unknown loc info!");
932 case CCValAssign::Full:
933 case CCValAssign::Indirect:
934 break;
935 case CCValAssign::SExt:
936 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
937 break;
938 case CCValAssign::ZExt:
939 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
940 break;
941 case CCValAssign::AExt:
942 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
943 break;
944 case CCValAssign::BCvt:
945 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getLocVT(), Operand: Arg);
946 break;
947 }
948
949 if (Flags.isSRet()) {
950 assert(VA.needsCustom());
951
952 if (isTailCall)
953 continue;
954
955 // store SRet argument in %sp+64
956 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
957 SDValue PtrOff = DAG.getIntPtrConstant(Val: 64, DL: dl);
958 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
959 MemOpChains.push_back(
960 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
961 hasStructRetAttr = true;
962 // sret only allowed on first argument
963 assert(Outs[realArgIdx].OrigArgIndex == 0);
964 SRetArgSize =
965 DAG.getDataLayout().getTypeAllocSize(Ty: CLI.getArgs()[0].IndirectType);
966 continue;
967 }
968
969 if (VA.needsCustom()) {
970 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
971
972 if (VA.isMemLoc()) {
973 unsigned Offset = VA.getLocMemOffset() + StackOffset;
974 // if it is double-word aligned, just store.
975 if (Offset % 8 == 0) {
976 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
977 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
978 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
979 MemOpChains.push_back(
980 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
981 continue;
982 }
983 }
984
985 if (VA.getLocVT() == MVT::f64) {
986 // Move from the float value from float registers into the
987 // integer registers.
988 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val&: Arg))
989 Arg = bitcastConstantFPToInt(C, DL: dl, DAG);
990 else
991 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::v2i32, Operand: Arg);
992 }
993
994 SDValue Part0 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: MVT::i32,
995 N1: Arg,
996 N2: DAG.getConstant(Val: 0, DL: dl, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
997 SDValue Part1 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: MVT::i32,
998 N1: Arg,
999 N2: DAG.getConstant(Val: 1, DL: dl, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
1000
1001 if (VA.isRegLoc()) {
1002 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Part0));
1003 assert(i+1 != e);
1004 CCValAssign &NextVA = ArgLocs[++i];
1005 if (NextVA.isRegLoc()) {
1006 RegsToPass.push_back(Elt: std::make_pair(x: NextVA.getLocReg(), y&: Part1));
1007 } else {
1008 // Store the second part in stack.
1009 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
1010 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1011 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
1012 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1013 MemOpChains.push_back(
1014 Elt: DAG.getStore(Chain, dl, Val: Part1, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1015 }
1016 } else {
1017 unsigned Offset = VA.getLocMemOffset() + StackOffset;
1018 // Store the first part.
1019 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1020 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
1021 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1022 MemOpChains.push_back(
1023 Elt: DAG.getStore(Chain, dl, Val: Part0, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1024 // Store the second part.
1025 PtrOff = DAG.getIntPtrConstant(Val: Offset + 4, DL: dl);
1026 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1027 MemOpChains.push_back(
1028 Elt: DAG.getStore(Chain, dl, Val: Part1, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1029 }
1030 continue;
1031 }
1032
1033 if (VA.getLocInfo() == CCValAssign::Indirect) {
1034 // Store the argument in a stack slot and pass its address.
1035 unsigned ArgIndex = Outs[realArgIdx].OrigArgIndex;
1036 assert(Outs[realArgIdx].PartOffset == 0);
1037
1038 EVT SlotVT;
1039 if (i + 1 != e && Outs[realArgIdx + 1].OrigArgIndex == ArgIndex) {
1040 Type *OrigArgType = CLI.Args[ArgIndex].Ty;
1041 EVT OrigArgVT = getValueType(DL: MF.getDataLayout(), Ty: OrigArgType);
1042 MVT PartVT =
1043 getRegisterTypeForCallingConv(Context&: Ctx, CC: CLI.CallConv, VT: OrigArgVT);
1044 unsigned N =
1045 getNumRegistersForCallingConv(Context&: Ctx, CC: CLI.CallConv, VT: OrigArgVT);
1046 SlotVT = EVT::getIntegerVT(Context&: Ctx, BitWidth: PartVT.getSizeInBits() * N);
1047 } else {
1048 SlotVT = Outs[realArgIdx].VT;
1049 }
1050
1051 SDValue SpillSlot = DAG.CreateStackTemporary(VT: SlotVT);
1052 int FI = cast<FrameIndexSDNode>(Val&: SpillSlot)->getIndex();
1053 MemOpChains.push_back(
1054 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: SpillSlot,
1055 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
1056 // If the original argument was split (e.g. f128), we need
1057 // to store all parts of it here (and pass just one address).
1058 while (i + 1 != e && Outs[realArgIdx + 1].OrigArgIndex == ArgIndex) {
1059 SDValue PartValue = OutVals[realArgIdx + 1];
1060 unsigned PartOffset = Outs[realArgIdx + 1].PartOffset;
1061 SDValue Address = DAG.getMemBasePlusOffset(
1062 Base: DAG.getFrameIndex(FI, VT: PtrVT), Offset: TypeSize::getFixed(ExactSize: PartOffset), DL: dl);
1063 MemOpChains.push_back(
1064 Elt: DAG.getStore(Chain, dl, Val: PartValue, Ptr: Address,
1065 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
1066 assert((PartOffset + PartValue.getValueType().getStoreSize() <=
1067 SlotVT.getStoreSize()) &&
1068 "Not enough space for argument part!");
1069 ++i;
1070 ++realArgIdx;
1071 }
1072
1073 Arg = SpillSlot;
1074 }
1075
1076 // Arguments that can be passed on register must be kept at
1077 // RegsToPass vector
1078 if (VA.isRegLoc()) {
1079 if (VA.getLocVT() != MVT::f32) {
1080 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1081 continue;
1082 }
1083 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: Arg);
1084 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1085 continue;
1086 }
1087
1088 assert(VA.isMemLoc());
1089
1090 // Create a store off the stack pointer for this argument.
1091 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1092 SDValue PtrOff = DAG.getIntPtrConstant(Val: VA.getLocMemOffset() + StackOffset,
1093 DL: dl);
1094 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1095 MemOpChains.push_back(
1096 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1097 }
1098
1099
1100 // Emit all stores, make sure the occur before any copies into physregs.
1101 if (!MemOpChains.empty())
1102 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains);
1103
1104 // Build a sequence of copy-to-reg nodes chained together with token
1105 // chain and flag operands which copy the outgoing args into registers.
1106 // The InGlue in necessary since all emitted instructions must be
1107 // stuck together.
1108 SDValue InGlue;
1109 for (const auto &[OrigReg, N] : RegsToPass) {
1110 Register Reg = isTailCall ? OrigReg : toCallerWindow(Reg: OrigReg);
1111 Chain = DAG.getCopyToReg(Chain, dl, Reg, N, Glue: InGlue);
1112 InGlue = Chain.getValue(R: 1);
1113 }
1114
1115 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, Call: CLI.CB);
1116
1117 // If the callee is a GlobalAddress node (quite common, every direct call is)
1118 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1119 // Likewise ExternalSymbol -> TargetExternalSymbol.
1120 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
1121 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL: dl, VT: MVT::i32, offset: 0);
1122 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee))
1123 Callee = DAG.getTargetExternalSymbol(Sym: E->getSymbol(), VT: MVT::i32);
1124
1125 // Returns a chain & a flag for retval copy to use
1126 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1127 SmallVector<SDValue, 8> Ops;
1128 Ops.push_back(Elt: Chain);
1129 Ops.push_back(Elt: Callee);
1130 if (hasStructRetAttr)
1131 Ops.push_back(Elt: DAG.getTargetConstant(Val: SRetArgSize, DL: dl, VT: MVT::i32));
1132 for (const auto &[OrigReg, N] : RegsToPass) {
1133 Register Reg = isTailCall ? OrigReg : toCallerWindow(Reg: OrigReg);
1134 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
1135 }
1136
1137 // Add a register mask operand representing the call-preserved registers.
1138 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1139 const uint32_t *Mask =
1140 ((hasReturnsTwice)
1141 ? TRI->getRTCallPreservedMask(CC: CallConv)
1142 : TRI->getCallPreservedMask(MF: DAG.getMachineFunction(), CC: CallConv));
1143
1144 if (isAnyArgRegReserved(TRI, MF))
1145 emitReservedArgRegCallError(MF);
1146
1147 assert(Mask && "Missing call preserved mask for calling convention");
1148 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
1149
1150 if (InGlue.getNode())
1151 Ops.push_back(Elt: InGlue);
1152
1153 if (isTailCall) {
1154 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
1155 return DAG.getNode(Opcode: SPISD::TAIL_CALL, DL: dl, VT: MVT::Other, Ops);
1156 }
1157
1158 Chain = DAG.getNode(Opcode: SPISD::CALL, DL: dl, VTList: NodeTys, Ops);
1159 InGlue = Chain.getValue(R: 1);
1160
1161 Chain = DAG.getCALLSEQ_END(Chain, Size1: ArgsSize, Size2: 0, Glue: InGlue, DL: dl);
1162 InGlue = Chain.getValue(R: 1);
1163
1164 // Assign locations to each value returned by this call.
1165 SmallVector<CCValAssign, 16> RVLocs;
1166 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1167 *DAG.getContext());
1168
1169 RVInfo.AnalyzeCallResult(Ins, Fn: RetCC_Sparc32);
1170
1171 // Copy all of the result registers out of their specified physreg.
1172 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1173 assert(RVLocs[i].isRegLoc() && "Can only return in registers!");
1174 if (RVLocs[i].getLocVT() == MVT::v2i32) {
1175 SDValue Vec = DAG.getNode(Opcode: ISD::UNDEF, DL: dl, VT: MVT::v2i32);
1176 SDValue Lo = DAG.getCopyFromReg(
1177 Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i++].getLocReg()), VT: MVT::i32, Glue: InGlue);
1178 Chain = Lo.getValue(R: 1);
1179 InGlue = Lo.getValue(R: 2);
1180 Vec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: MVT::v2i32, N1: Vec, N2: Lo,
1181 N3: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
1182 SDValue Hi = DAG.getCopyFromReg(
1183 Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i].getLocReg()), VT: MVT::i32, Glue: InGlue);
1184 Chain = Hi.getValue(R: 1);
1185 InGlue = Hi.getValue(R: 2);
1186 Vec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: MVT::v2i32, N1: Vec, N2: Hi,
1187 N3: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i32));
1188 InVals.push_back(Elt: Vec);
1189 } else {
1190 Chain =
1191 DAG.getCopyFromReg(Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i].getLocReg()),
1192 VT: RVLocs[i].getValVT(), Glue: InGlue)
1193 .getValue(R: 1);
1194 InGlue = Chain.getValue(R: 2);
1195 InVals.push_back(Elt: Chain.getValue(R: 0));
1196 }
1197 }
1198
1199 return Chain;
1200}
1201
1202// FIXME? Maybe this could be a TableGen attribute on some registers and
1203// this table could be generated automatically from RegInfo.
1204Register SparcTargetLowering::getRegisterByName(const char* RegName, LLT VT,
1205 const MachineFunction &MF) const {
1206 Register Reg = StringSwitch<Register>(RegName)
1207 .Case(S: "i0", Value: SP::I0).Case(S: "i1", Value: SP::I1).Case(S: "i2", Value: SP::I2).Case(S: "i3", Value: SP::I3)
1208 .Case(S: "i4", Value: SP::I4).Case(S: "i5", Value: SP::I5).Case(S: "i6", Value: SP::I6).Case(S: "i7", Value: SP::I7)
1209 .Case(S: "o0", Value: SP::O0).Case(S: "o1", Value: SP::O1).Case(S: "o2", Value: SP::O2).Case(S: "o3", Value: SP::O3)
1210 .Case(S: "o4", Value: SP::O4).Case(S: "o5", Value: SP::O5).Case(S: "o6", Value: SP::O6).Case(S: "o7", Value: SP::O7)
1211 .Case(S: "l0", Value: SP::L0).Case(S: "l1", Value: SP::L1).Case(S: "l2", Value: SP::L2).Case(S: "l3", Value: SP::L3)
1212 .Case(S: "l4", Value: SP::L4).Case(S: "l5", Value: SP::L5).Case(S: "l6", Value: SP::L6).Case(S: "l7", Value: SP::L7)
1213 .Case(S: "g0", Value: SP::G0).Case(S: "g1", Value: SP::G1).Case(S: "g2", Value: SP::G2).Case(S: "g3", Value: SP::G3)
1214 .Case(S: "g4", Value: SP::G4).Case(S: "g5", Value: SP::G5).Case(S: "g6", Value: SP::G6).Case(S: "g7", Value: SP::G7)
1215 .Default(Value: 0);
1216
1217 // If we're directly referencing register names
1218 // (e.g in GCC C extension `register int r asm("g1");`),
1219 // make sure that said register is in the reserve list.
1220 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1221 if (!TRI->isReservedReg(MF, Reg))
1222 Reg = Register();
1223
1224 return Reg;
1225}
1226
1227// Fixup floating point arguments in the ... part of a varargs call.
1228//
1229// The SPARC v9 ABI requires that floating point arguments are treated the same
1230// as integers when calling a varargs function. This does not apply to the
1231// fixed arguments that are part of the function's prototype.
1232//
1233// This function post-processes a CCValAssign array created by
1234// AnalyzeCallOperands().
1235static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1236 ArrayRef<ISD::OutputArg> Outs) {
1237 for (CCValAssign &VA : ArgLocs) {
1238 MVT ValTy = VA.getLocVT();
1239 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1240 // varargs functions.
1241 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1242 continue;
1243 // The fixed arguments to a varargs function still go in FP registers.
1244 if (!Outs[VA.getValNo()].Flags.isVarArg())
1245 continue;
1246
1247 // This floating point argument should be reassigned.
1248 // Determine the offset into the argument array.
1249 Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1250 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1251 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1252 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1253
1254 if (Offset < 6*8) {
1255 // This argument should go in %i0-%i5.
1256 unsigned IReg = SP::I0 + Offset/8;
1257 if (ValTy == MVT::f64)
1258 // Full register, just bitconvert into i64.
1259 VA = CCValAssign::getReg(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Reg: IReg, LocVT: MVT::i64,
1260 HTP: CCValAssign::BCvt);
1261 else {
1262 assert(ValTy == MVT::f128 && "Unexpected type!");
1263 // Full register, just bitconvert into i128 -- We will lower this into
1264 // two i64s in LowerCall_64.
1265 VA = CCValAssign::getCustomReg(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Reg: IReg,
1266 LocVT: MVT::i128, HTP: CCValAssign::BCvt);
1267 }
1268 } else {
1269 // This needs to go to memory, we're out of integer registers.
1270 VA = CCValAssign::getMem(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Offset,
1271 LocVT: VA.getLocVT(), HTP: VA.getLocInfo());
1272 }
1273 }
1274}
1275
1276// Lower a call for the 64-bit ABI.
1277SDValue
1278SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1279 SmallVectorImpl<SDValue> &InVals) const {
1280 SelectionDAG &DAG = CLI.DAG;
1281 SDLoc DL = CLI.DL;
1282 SDValue Chain = CLI.Chain;
1283 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
1284 MachineFunction &MF = DAG.getMachineFunction();
1285
1286 // Analyze operands of the call, assigning locations to each operand.
1287 SmallVector<CCValAssign, 16> ArgLocs;
1288 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1289 *DAG.getContext());
1290 CCInfo.AnalyzeCallOperands(Outs: CLI.Outs, Fn: CC_Sparc64);
1291
1292 CLI.IsTailCall = CLI.IsTailCall && IsEligibleForTailCallOptimization(
1293 CCInfo, CLI, MF&: DAG.getMachineFunction());
1294
1295 // Get the size of the outgoing arguments stack space requirement.
1296 // The stack offset computed by CC_Sparc64 includes all arguments.
1297 // Called functions expect 6 argument words to exist in the stack frame, used
1298 // or not.
1299 unsigned StackReserved = 6 * 8u;
1300 unsigned ArgsSize = std::max<unsigned>(a: StackReserved, b: CCInfo.getStackSize());
1301
1302 // Keep stack frames 16-byte aligned.
1303 ArgsSize = alignTo(Value: ArgsSize, Align: 16);
1304
1305 // Varargs calls require special treatment.
1306 if (CLI.IsVarArg)
1307 fixupVariableFloatArgs(ArgLocs, Outs: CLI.Outs);
1308
1309 assert(!CLI.IsTailCall || ArgsSize == StackReserved);
1310
1311 // Adjust the stack pointer to make room for the arguments.
1312 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1313 // with more than 6 arguments.
1314 if (!CLI.IsTailCall)
1315 Chain = DAG.getCALLSEQ_START(Chain, InSize: ArgsSize, OutSize: 0, DL);
1316
1317 // Collect the set of registers to pass to the function and their values.
1318 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1319 // instruction.
1320 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
1321
1322 // Collect chains from all the memory opeations that copy arguments to the
1323 // stack. They must follow the stack pointer adjustment above and precede the
1324 // call instruction itself.
1325 SmallVector<SDValue, 8> MemOpChains;
1326
1327 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1328 const CCValAssign &VA = ArgLocs[i];
1329 SDValue Arg = CLI.OutVals[i];
1330
1331 // Promote the value if needed.
1332 switch (VA.getLocInfo()) {
1333 default:
1334 llvm_unreachable("Unknown location info!");
1335 case CCValAssign::Full:
1336 break;
1337 case CCValAssign::SExt:
1338 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1339 break;
1340 case CCValAssign::ZExt:
1341 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1342 break;
1343 case CCValAssign::AExt:
1344 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1345 break;
1346 case CCValAssign::BCvt:
1347 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1348 // SPARC does not support i128 natively. Lower it into two i64, see below.
1349 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1350 || VA.getLocVT() != MVT::i128)
1351 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: VA.getLocVT(), Operand: Arg);
1352 break;
1353 }
1354
1355 if (VA.isRegLoc()) {
1356 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1357 && VA.getLocVT() == MVT::i128) {
1358 // Store and reload into the integer register reg and reg+1.
1359 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1360 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1361 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: PtrVT);
1362 SDValue HiPtrOff = DAG.getIntPtrConstant(Val: StackOffset, DL);
1363 HiPtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: HiPtrOff);
1364 SDValue LoPtrOff = DAG.getIntPtrConstant(Val: StackOffset + 8, DL);
1365 LoPtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: LoPtrOff);
1366
1367 // Store to %sp+BIAS+128+Offset
1368 SDValue Store =
1369 DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: HiPtrOff, PtrInfo: MachinePointerInfo());
1370 // Load into Reg and Reg+1
1371 SDValue Hi64 =
1372 DAG.getLoad(VT: MVT::i64, dl: DL, Chain: Store, Ptr: HiPtrOff, PtrInfo: MachinePointerInfo());
1373 SDValue Lo64 =
1374 DAG.getLoad(VT: MVT::i64, dl: DL, Chain: Store, Ptr: LoPtrOff, PtrInfo: MachinePointerInfo());
1375
1376 Register HiReg = VA.getLocReg();
1377 Register LoReg = VA.getLocReg() + 1;
1378 if (!CLI.IsTailCall) {
1379 HiReg = toCallerWindow(Reg: HiReg);
1380 LoReg = toCallerWindow(Reg: LoReg);
1381 }
1382
1383 RegsToPass.push_back(Elt: std::make_pair(x&: HiReg, y&: Hi64));
1384 RegsToPass.push_back(Elt: std::make_pair(x&: LoReg, y&: Lo64));
1385 continue;
1386 }
1387
1388 // The custom bit on an i32 return value indicates that it should be
1389 // passed in the high bits of the register.
1390 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1391 Arg = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: Arg,
1392 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
1393
1394 // The next value may go in the low bits of the same register.
1395 // Handle both at once.
1396 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1397 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1398 SDValue NV = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i64,
1399 Operand: CLI.OutVals[i+1]);
1400 Arg = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i64, N1: Arg, N2: NV);
1401 // Skip the next value, it's already done.
1402 ++i;
1403 }
1404 }
1405
1406 Register Reg = VA.getLocReg();
1407 if (!CLI.IsTailCall)
1408 Reg = toCallerWindow(Reg);
1409 RegsToPass.push_back(Elt: std::make_pair(x&: Reg, y&: Arg));
1410 continue;
1411 }
1412
1413 assert(VA.isMemLoc());
1414
1415 // Create a store off the stack pointer for this argument.
1416 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: PtrVT);
1417 // The argument area starts at %fp+BIAS+128 in the callee frame,
1418 // %sp+BIAS+128 in ours.
1419 SDValue PtrOff = DAG.getIntPtrConstant(Val: VA.getLocMemOffset() +
1420 Subtarget->getStackPointerBias() +
1421 128, DL);
1422 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: PtrOff);
1423 MemOpChains.push_back(
1424 Elt: DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1425 }
1426
1427 // Emit all stores, make sure they occur before the call.
1428 if (!MemOpChains.empty())
1429 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOpChains);
1430
1431 // Build a sequence of CopyToReg nodes glued together with token chain and
1432 // glue operands which copy the outgoing args into registers. The InGlue is
1433 // necessary since all emitted instructions must be stuck together in order
1434 // to pass the live physical registers.
1435 SDValue InGlue;
1436 for (const auto &[Reg, N] : RegsToPass) {
1437 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg, N, Glue: InGlue);
1438 InGlue = Chain.getValue(R: 1);
1439 }
1440
1441 // If the callee is a GlobalAddress node (quite common, every direct call is)
1442 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1443 // Likewise ExternalSymbol -> TargetExternalSymbol.
1444 SDValue Callee = CLI.Callee;
1445 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, Call: CLI.CB);
1446 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
1447 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL, VT: PtrVT, offset: 0);
1448 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee))
1449 Callee = DAG.getTargetExternalSymbol(Sym: E->getSymbol(), VT: PtrVT);
1450
1451 // Build the operands for the call instruction itself.
1452 SmallVector<SDValue, 8> Ops;
1453 Ops.push_back(Elt: Chain);
1454 Ops.push_back(Elt: Callee);
1455 for (const auto &[Reg, N] : RegsToPass)
1456 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
1457
1458 // Add a register mask operand representing the call-preserved registers.
1459 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1460 const uint32_t *Mask =
1461 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CC: CLI.CallConv)
1462 : TRI->getCallPreservedMask(MF: DAG.getMachineFunction(),
1463 CC: CLI.CallConv));
1464
1465 if (isAnyArgRegReserved(TRI, MF))
1466 emitReservedArgRegCallError(MF);
1467
1468 assert(Mask && "Missing call preserved mask for calling convention");
1469 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
1470
1471 // Make sure the CopyToReg nodes are glued to the call instruction which
1472 // consumes the registers.
1473 if (InGlue.getNode())
1474 Ops.push_back(Elt: InGlue);
1475
1476 // Now the call itself.
1477 if (CLI.IsTailCall) {
1478 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
1479 return DAG.getNode(Opcode: SPISD::TAIL_CALL, DL, VT: MVT::Other, Ops);
1480 }
1481 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1482 Chain = DAG.getNode(Opcode: SPISD::CALL, DL, VTList: NodeTys, Ops);
1483 InGlue = Chain.getValue(R: 1);
1484
1485 // Revert the stack pointer immediately after the call.
1486 Chain = DAG.getCALLSEQ_END(Chain, Size1: ArgsSize, Size2: 0, Glue: InGlue, DL);
1487 InGlue = Chain.getValue(R: 1);
1488
1489 // Now extract the return values. This is more or less the same as
1490 // LowerFormalArguments_64.
1491
1492 // Assign locations to each value returned by this call.
1493 SmallVector<CCValAssign, 16> RVLocs;
1494 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1495 *DAG.getContext());
1496
1497 // Set inreg flag manually for codegen generated library calls that
1498 // return float.
1499 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB)
1500 CLI.Ins[0].Flags.setInReg();
1501
1502 RVInfo.AnalyzeCallResult(Ins: CLI.Ins, Fn: RetCC_Sparc64);
1503
1504 // Copy all of the result registers out of their specified physreg.
1505 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1506 CCValAssign &VA = RVLocs[i];
1507 assert(VA.isRegLoc() && "Can only return in registers!");
1508 unsigned Reg = toCallerWindow(Reg: VA.getLocReg());
1509
1510 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1511 // reside in the same register in the high and low bits. Reuse the
1512 // CopyFromReg previous node to avoid duplicate copies.
1513 SDValue RV;
1514 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Val: Chain.getOperand(i: 1)))
1515 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1516 RV = Chain.getValue(R: 0);
1517
1518 // But usually we'll create a new CopyFromReg for a different register.
1519 if (!RV.getNode()) {
1520 RV = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: RVLocs[i].getLocVT(), Glue: InGlue);
1521 Chain = RV.getValue(R: 1);
1522 InGlue = Chain.getValue(R: 2);
1523 }
1524
1525 // Get the high bits for i32 struct elements.
1526 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1527 RV = DAG.getNode(Opcode: ISD::SRL, DL, VT: VA.getLocVT(), N1: RV,
1528 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
1529
1530 // The callee promoted the return value, so insert an Assert?ext SDNode so
1531 // we won't promote the value again in this function.
1532 switch (VA.getLocInfo()) {
1533 case CCValAssign::SExt:
1534 RV = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: RV,
1535 N2: DAG.getValueType(VA.getValVT()));
1536 break;
1537 case CCValAssign::ZExt:
1538 RV = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: RV,
1539 N2: DAG.getValueType(VA.getValVT()));
1540 break;
1541 default:
1542 break;
1543 }
1544
1545 // Truncate the register down to the return value type.
1546 if (VA.isExtInLoc())
1547 RV = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: RV);
1548
1549 InVals.push_back(Elt: RV);
1550 }
1551
1552 return Chain;
1553}
1554
1555//===----------------------------------------------------------------------===//
1556// TargetLowering Implementation
1557//===----------------------------------------------------------------------===//
1558
1559TargetLowering::AtomicExpansionKind
1560SparcTargetLowering::shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const {
1561 if (AI->getOperation() == AtomicRMWInst::Xchg &&
1562 AI->getType()->getPrimitiveSizeInBits() == 32)
1563 return AtomicExpansionKind::None; // Uses xchg instruction
1564
1565 return AtomicExpansionKind::CmpXChg;
1566}
1567
1568/// intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC
1569/// rcond condition.
1570static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC) {
1571 switch (CC) {
1572 default:
1573 llvm_unreachable("Unknown/unsigned integer condition code!");
1574 case ISD::SETEQ:
1575 return SPCC::REG_Z;
1576 case ISD::SETNE:
1577 return SPCC::REG_NZ;
1578 case ISD::SETLT:
1579 return SPCC::REG_LZ;
1580 case ISD::SETGT:
1581 return SPCC::REG_GZ;
1582 case ISD::SETLE:
1583 return SPCC::REG_LEZ;
1584 case ISD::SETGE:
1585 return SPCC::REG_GEZ;
1586 }
1587}
1588
1589/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1590/// condition.
1591static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1592 switch (CC) {
1593 default: llvm_unreachable("Unknown integer condition code!");
1594 case ISD::SETEQ: return SPCC::ICC_E;
1595 case ISD::SETNE: return SPCC::ICC_NE;
1596 case ISD::SETLT: return SPCC::ICC_L;
1597 case ISD::SETGT: return SPCC::ICC_G;
1598 case ISD::SETLE: return SPCC::ICC_LE;
1599 case ISD::SETGE: return SPCC::ICC_GE;
1600 case ISD::SETULT: return SPCC::ICC_CS;
1601 case ISD::SETULE: return SPCC::ICC_LEU;
1602 case ISD::SETUGT: return SPCC::ICC_GU;
1603 case ISD::SETUGE: return SPCC::ICC_CC;
1604 }
1605}
1606
1607/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1608/// FCC condition.
1609static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1610 switch (CC) {
1611 default: llvm_unreachable("Unknown fp condition code!");
1612 case ISD::SETEQ:
1613 case ISD::SETOEQ: return SPCC::FCC_E;
1614 case ISD::SETNE:
1615 case ISD::SETUNE: return SPCC::FCC_NE;
1616 case ISD::SETLT:
1617 case ISD::SETOLT: return SPCC::FCC_L;
1618 case ISD::SETGT:
1619 case ISD::SETOGT: return SPCC::FCC_G;
1620 case ISD::SETLE:
1621 case ISD::SETOLE: return SPCC::FCC_LE;
1622 case ISD::SETGE:
1623 case ISD::SETOGE: return SPCC::FCC_GE;
1624 case ISD::SETULT: return SPCC::FCC_UL;
1625 case ISD::SETULE: return SPCC::FCC_ULE;
1626 case ISD::SETUGT: return SPCC::FCC_UG;
1627 case ISD::SETUGE: return SPCC::FCC_UGE;
1628 case ISD::SETUO: return SPCC::FCC_U;
1629 case ISD::SETO: return SPCC::FCC_O;
1630 case ISD::SETONE: return SPCC::FCC_LG;
1631 case ISD::SETUEQ: return SPCC::FCC_UE;
1632 }
1633}
1634
1635SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
1636 const SparcSubtarget &STI)
1637 : TargetLowering(TM, STI), Subtarget(&STI) {
1638 MVT PtrVT = MVT::getIntegerVT(BitWidth: TM.getPointerSizeInBits(AS: 0));
1639
1640 // Instructions which use registers as conditionals examine all the
1641 // bits (as does the pseudo SELECT_CC expansion). I don't think it
1642 // matters much whether it's ZeroOrOneBooleanContent, or
1643 // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
1644 // former.
1645 setBooleanContents(ZeroOrOneBooleanContent);
1646 setBooleanVectorContents(ZeroOrOneBooleanContent);
1647
1648 // Set up the register classes.
1649 addRegisterClass(VT: MVT::i32, RC: &SP::IntRegsRegClass);
1650 if (!Subtarget->useSoftFloat()) {
1651 addRegisterClass(VT: MVT::f32, RC: &SP::FPRegsRegClass);
1652 addRegisterClass(VT: MVT::f64, RC: &SP::DFPRegsRegClass);
1653 addRegisterClass(VT: MVT::f128, RC: &SP::QFPRegsRegClass);
1654 }
1655 if (Subtarget->is64Bit()) {
1656 addRegisterClass(VT: MVT::i64, RC: &SP::I64RegsRegClass);
1657 } else {
1658 // On 32bit sparc, we define a double-register 32bit register
1659 // class, as well. This is modeled in LLVM as a 2-vector of i32.
1660 addRegisterClass(VT: MVT::v2i32, RC: &SP::IntPairRegClass);
1661
1662 // ...but almost all operations must be expanded, so set that as
1663 // the default.
1664 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
1665 setOperationAction(Op, VT: MVT::v2i32, Action: Expand);
1666 }
1667 // Truncating/extending stores/loads are also not supported.
1668 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
1669 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1670 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1671 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1672
1673 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1674 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1675 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1676
1677 setTruncStoreAction(ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1678 setTruncStoreAction(ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1679 }
1680 // However, load and store *are* legal.
1681 setOperationAction(Op: ISD::LOAD, VT: MVT::v2i32, Action: Legal);
1682 setOperationAction(Op: ISD::STORE, VT: MVT::v2i32, Action: Legal);
1683 setOperationAction(Op: ISD::EXTRACT_VECTOR_ELT, VT: MVT::v2i32, Action: Legal);
1684 setOperationAction(Op: ISD::BUILD_VECTOR, VT: MVT::v2i32, Action: Legal);
1685
1686 // And we need to promote i64 loads/stores into vector load/store
1687 setOperationAction(Op: ISD::LOAD, VT: MVT::i64, Action: Custom);
1688 setOperationAction(Op: ISD::STORE, VT: MVT::i64, Action: Custom);
1689
1690 // Sadly, this doesn't work:
1691 // AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
1692 // AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
1693 }
1694
1695 // Turn FP extload into load/fpextend
1696 for (MVT VT : MVT::fp_valuetypes()) {
1697 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f16, Action: Expand);
1698 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f32, Action: Expand);
1699 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f64, Action: Expand);
1700 }
1701
1702 // Sparc doesn't have i1 sign extending load
1703 for (MVT VT : MVT::integer_valuetypes())
1704 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
1705
1706 // Turn FP truncstore into trunc + store.
1707 setTruncStoreAction(ValVT: MVT::f32, MemVT: MVT::f16, Action: Expand);
1708 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f16, Action: Expand);
1709 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f32, Action: Expand);
1710 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f16, Action: Expand);
1711 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f32, Action: Expand);
1712 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f64, Action: Expand);
1713
1714 // Custom legalize GlobalAddress nodes into LO/HI parts.
1715 setOperationAction(Op: ISD::GlobalAddress, VT: PtrVT, Action: Custom);
1716 setOperationAction(Op: ISD::GlobalTLSAddress, VT: PtrVT, Action: Custom);
1717 setOperationAction(Op: ISD::ConstantPool, VT: PtrVT, Action: Custom);
1718 setOperationAction(Op: ISD::BlockAddress, VT: PtrVT, Action: Custom);
1719
1720 // Sparc doesn't have sext_inreg, replace them with shl/sra
1721 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i16, Action: Expand);
1722 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i8 , Action: Expand);
1723 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i1 , Action: Expand);
1724
1725 // Sparc has no REM or DIVREM operations.
1726 setOperationAction(Op: ISD::UREM, VT: MVT::i32, Action: Expand);
1727 setOperationAction(Op: ISD::SREM, VT: MVT::i32, Action: Expand);
1728 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i32, Action: Expand);
1729 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i32, Action: Expand);
1730
1731 // ... nor does SparcV9.
1732 if (Subtarget->is64Bit()) {
1733 setOperationAction(Op: ISD::UREM, VT: MVT::i64, Action: Expand);
1734 setOperationAction(Op: ISD::SREM, VT: MVT::i64, Action: Expand);
1735 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i64, Action: Expand);
1736 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i64, Action: Expand);
1737 }
1738
1739 // Custom expand fp<->sint
1740 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::i32, Action: Custom);
1741 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::i32, Action: Custom);
1742 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::i64, Action: Custom);
1743 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::i64, Action: Custom);
1744
1745 // Custom Expand fp<->uint
1746 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i32, Action: Custom);
1747 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i32, Action: Custom);
1748 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i64, Action: Custom);
1749 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i64, Action: Custom);
1750
1751 // Lower f16 conversion operations into library calls
1752 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f32, Action: Expand);
1753 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f32, Action: Expand);
1754 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f64, Action: Expand);
1755 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f64, Action: Expand);
1756 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f128, Action: Expand);
1757 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f128, Action: Expand);
1758
1759 setOperationAction(Op: ISD::BITCAST, VT: MVT::f32,
1760 Action: Subtarget->isVIS3() ? Legal : Expand);
1761 setOperationAction(Op: ISD::BITCAST, VT: MVT::i32,
1762 Action: Subtarget->isVIS3() ? Legal : Expand);
1763
1764 // Sparc has no select or setcc: expand to SELECT_CC.
1765 setOperationAction(Op: ISD::SELECT, VT: MVT::i32, Action: Expand);
1766 setOperationAction(Op: ISD::SELECT, VT: MVT::f32, Action: Expand);
1767 setOperationAction(Op: ISD::SELECT, VT: MVT::f64, Action: Expand);
1768 setOperationAction(Op: ISD::SELECT, VT: MVT::f128, Action: Expand);
1769
1770 setOperationAction(Op: ISD::SETCC, VT: MVT::i32, Action: Expand);
1771 setOperationAction(Op: ISD::SETCC, VT: MVT::f32, Action: Expand);
1772 setOperationAction(Op: ISD::SETCC, VT: MVT::f64, Action: Expand);
1773 setOperationAction(Op: ISD::SETCC, VT: MVT::f128, Action: Expand);
1774
1775 // Sparc doesn't have BRCOND either, it has BR_CC.
1776 setOperationAction(Op: ISD::BRCOND, VT: MVT::Other, Action: Expand);
1777 setOperationAction(Op: ISD::BRIND, VT: MVT::Other, Action: Expand);
1778 setOperationAction(Op: ISD::BR_JT, VT: MVT::Other, Action: Expand);
1779 setOperationAction(Op: ISD::BR_CC, VT: MVT::i32, Action: Custom);
1780 setOperationAction(Op: ISD::BR_CC, VT: MVT::f32, Action: Custom);
1781 setOperationAction(Op: ISD::BR_CC, VT: MVT::f64, Action: Custom);
1782 setOperationAction(Op: ISD::BR_CC, VT: MVT::f128, Action: Custom);
1783
1784 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i32, Action: Custom);
1785 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f32, Action: Custom);
1786 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f64, Action: Custom);
1787 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f128, Action: Custom);
1788
1789 setOperationAction(Op: ISD::ADDC, VT: MVT::i32, Action: Legal);
1790 setOperationAction(Op: ISD::ADDE, VT: MVT::i32, Action: Legal);
1791 setOperationAction(Op: ISD::SUBC, VT: MVT::i32, Action: Legal);
1792 setOperationAction(Op: ISD::SUBE, VT: MVT::i32, Action: Legal);
1793
1794 if (Subtarget->isVIS3()) {
1795 setOperationAction(Op: ISD::ADDC, VT: MVT::i64, Action: Legal);
1796 setOperationAction(Op: ISD::ADDE, VT: MVT::i64, Action: Legal);
1797 }
1798
1799 if (Subtarget->is64Bit()) {
1800 setOperationAction(Op: ISD::BITCAST, VT: MVT::f64,
1801 Action: Subtarget->isVIS3() ? Legal : Expand);
1802 setOperationAction(Op: ISD::BITCAST, VT: MVT::i64,
1803 Action: Subtarget->isVIS3() ? Legal : Expand);
1804 setOperationAction(Op: ISD::SELECT, VT: MVT::i64, Action: Expand);
1805 setOperationAction(Op: ISD::SETCC, VT: MVT::i64, Action: Expand);
1806 setOperationAction(Op: ISD::BR_CC, VT: MVT::i64, Action: Custom);
1807 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i64, Action: Custom);
1808
1809 setOperationAction(Op: ISD::CTPOP, VT: MVT::i64,
1810 Action: Subtarget->usePopc() ? Legal : Expand);
1811 setOperationAction(Op: ISD::BSWAP, VT: MVT::i64, Action: Custom);
1812 setOperationAction(Op: ISD::ROTL , VT: MVT::i64, Action: Expand);
1813 setOperationAction(Op: ISD::ROTR , VT: MVT::i64, Action: Expand);
1814 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i64, Action: Custom);
1815 }
1816
1817 // ATOMICs.
1818 // Atomics are supported on SparcV9. 32-bit atomics are also
1819 // supported by some Leon SparcV8 variants. Otherwise, atomics
1820 // are unsupported.
1821 if (Subtarget->isV9()) {
1822 // TODO: we _ought_ to be able to support 64-bit atomics on 32-bit sparcv9,
1823 // but it hasn't been implemented in the backend yet.
1824 if (Subtarget->is64Bit())
1825 setMaxAtomicSizeInBitsSupported(64);
1826 else
1827 setMaxAtomicSizeInBitsSupported(32);
1828 } else if (Subtarget->hasLeonCasa())
1829 setMaxAtomicSizeInBitsSupported(32);
1830 else
1831 setMaxAtomicSizeInBitsSupported(0);
1832
1833 setMinCmpXchgSizeInBits(32);
1834
1835 setOperationAction(Op: ISD::ATOMIC_SWAP, VT: MVT::i32, Action: Legal);
1836
1837 setOperationAction(Op: ISD::ATOMIC_FENCE, VT: MVT::Other, Action: Legal);
1838
1839 // Custom Lower Atomic LOAD/STORE
1840 setOperationAction(Op: ISD::ATOMIC_LOAD, VT: MVT::i32, Action: Custom);
1841 setOperationAction(Op: ISD::ATOMIC_STORE, VT: MVT::i32, Action: Custom);
1842
1843 if (Subtarget->is64Bit()) {
1844 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP, VT: MVT::i64, Action: Legal);
1845 setOperationAction(Op: ISD::ATOMIC_SWAP, VT: MVT::i64, Action: Legal);
1846 setOperationAction(Op: ISD::ATOMIC_LOAD, VT: MVT::i64, Action: Custom);
1847 setOperationAction(Op: ISD::ATOMIC_STORE, VT: MVT::i64, Action: Custom);
1848 }
1849
1850 if (!Subtarget->isV9()) {
1851 // SparcV8 does not have FNEGD and FABSD.
1852 setOperationAction(Op: ISD::FNEG, VT: MVT::f64, Action: Custom);
1853 setOperationAction(Op: ISD::FABS, VT: MVT::f64, Action: Custom);
1854 }
1855
1856 setOperationAction(Op: ISD::FSIN , VT: MVT::f128, Action: Expand);
1857 setOperationAction(Op: ISD::FCOS , VT: MVT::f128, Action: Expand);
1858 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f128, Action: Expand);
1859 setOperationAction(Op: ISD::FREM, VT: MVT::f128, Action: LibCall);
1860 setOperationAction(Op: ISD::FMA , VT: MVT::f128, Action: Expand);
1861 setOperationAction(Op: ISD::FSIN , VT: MVT::f64, Action: Expand);
1862 setOperationAction(Op: ISD::FCOS , VT: MVT::f64, Action: Expand);
1863 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f64, Action: Expand);
1864 setOperationAction(Op: ISD::FREM, VT: MVT::f64, Action: LibCall);
1865 setOperationAction(Op: ISD::FMA, VT: MVT::f64,
1866 Action: Subtarget->isUA2007() ? Legal : Expand);
1867 setOperationAction(Op: ISD::FSIN , VT: MVT::f32, Action: Expand);
1868 setOperationAction(Op: ISD::FCOS , VT: MVT::f32, Action: Expand);
1869 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f32, Action: Expand);
1870 setOperationAction(Op: ISD::FREM, VT: MVT::f32, Action: LibCall);
1871 setOperationAction(Op: ISD::FMA, VT: MVT::f32,
1872 Action: Subtarget->isUA2007() ? Legal : Expand);
1873 setOperationAction(Op: ISD::ROTL , VT: MVT::i32, Action: Expand);
1874 setOperationAction(Op: ISD::ROTR , VT: MVT::i32, Action: Expand);
1875 setOperationAction(Op: ISD::BSWAP, VT: MVT::i32, Action: Subtarget->isV9() ? Custom : Expand);
1876 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f128, Action: Expand);
1877 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f64, Action: Expand);
1878 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f32, Action: Expand);
1879 setOperationAction(Op: ISD::FPOW , VT: MVT::f128, Action: Expand);
1880 setOperationAction(Op: ISD::FPOW , VT: MVT::f64, Action: Expand);
1881 setOperationAction(Op: ISD::FPOW , VT: MVT::f32, Action: Expand);
1882
1883 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i32, Action: Expand);
1884 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i32, Action: Expand);
1885 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i32, Action: Expand);
1886
1887 // Expands to [SU]MUL_LOHI.
1888 setOperationAction(Op: ISD::MULHU, VT: MVT::i32, Action: Expand);
1889 setOperationAction(Op: ISD::MULHS, VT: MVT::i32, Action: Expand);
1890 setOperationAction(Op: ISD::MUL, VT: MVT::i32, Action: Expand);
1891
1892 if (Subtarget->useSoftMulDiv()) {
1893 // .umul works for both signed and unsigned
1894 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i32, Action: Expand);
1895 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i32, Action: Expand);
1896 setOperationAction(Op: ISD::SDIV, VT: MVT::i32, Action: Expand);
1897 setOperationAction(Op: ISD::UDIV, VT: MVT::i32, Action: Expand);
1898 }
1899
1900 if (Subtarget->is64Bit()) {
1901 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i64, Action: Expand);
1902 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i64, Action: Expand);
1903 setOperationAction(Op: ISD::MULHU, VT: MVT::i64,
1904 Action: Subtarget->isVIS3() ? Legal : Expand);
1905 setOperationAction(Op: ISD::MULHS, VT: MVT::i64,
1906 Action: Subtarget->isVIS3() ? Legal : Expand);
1907
1908 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i64, Action: Expand);
1909 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i64, Action: Expand);
1910 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i64, Action: Expand);
1911 }
1912
1913 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1914 setOperationAction(Op: ISD::VASTART , VT: MVT::Other, Action: Custom);
1915 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1916 setOperationAction(Op: ISD::VAARG , VT: MVT::Other, Action: Custom);
1917
1918 setOperationAction(Op: ISD::TRAP , VT: MVT::Other, Action: Legal);
1919 setOperationAction(Op: ISD::DEBUGTRAP , VT: MVT::Other, Action: Legal);
1920
1921 // Use the default implementation.
1922 setOperationAction(Op: ISD::VACOPY , VT: MVT::Other, Action: Expand);
1923 setOperationAction(Op: ISD::VAEND , VT: MVT::Other, Action: Expand);
1924 setOperationAction(Op: ISD::STACKSAVE , VT: MVT::Other, Action: Expand);
1925 setOperationAction(Op: ISD::STACKRESTORE , VT: MVT::Other, Action: Expand);
1926 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i32 , Action: Custom);
1927 setOperationAction(Op: ISD::STACKADDRESS, VT: MVT::Other, Action: Custom);
1928
1929 setStackPointerRegisterToSaveRestore(SP::O6);
1930
1931 setOperationAction(Op: ISD::CTPOP, VT: MVT::i32,
1932 Action: Subtarget->usePopc() ? Legal : Expand);
1933
1934 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1935 setOperationAction(Op: ISD::LOAD, VT: MVT::f128, Action: Legal);
1936 setOperationAction(Op: ISD::STORE, VT: MVT::f128, Action: Legal);
1937 } else {
1938 setOperationAction(Op: ISD::LOAD, VT: MVT::f128, Action: Custom);
1939 setOperationAction(Op: ISD::STORE, VT: MVT::f128, Action: Custom);
1940 }
1941
1942 if (Subtarget->hasHardQuad()) {
1943 setOperationAction(Op: ISD::FADD, VT: MVT::f128, Action: Legal);
1944 setOperationAction(Op: ISD::FSUB, VT: MVT::f128, Action: Legal);
1945 setOperationAction(Op: ISD::FMUL, VT: MVT::f128, Action: Legal);
1946 setOperationAction(Op: ISD::FDIV, VT: MVT::f128, Action: Legal);
1947 setOperationAction(Op: ISD::FSQRT, VT: MVT::f128, Action: Legal);
1948 setOperationAction(Op: ISD::FP_EXTEND, VT: MVT::f128, Action: Legal);
1949 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f64, Action: Legal);
1950 if (Subtarget->isV9()) {
1951 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Legal);
1952 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Legal);
1953 } else {
1954 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Custom);
1955 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Custom);
1956 }
1957 } else {
1958 // Custom legalize f128 operations.
1959
1960 setOperationAction(Op: ISD::FADD, VT: MVT::f128, Action: Custom);
1961 setOperationAction(Op: ISD::FSUB, VT: MVT::f128, Action: Custom);
1962 setOperationAction(Op: ISD::FMUL, VT: MVT::f128, Action: Custom);
1963 setOperationAction(Op: ISD::FDIV, VT: MVT::f128, Action: Custom);
1964 setOperationAction(Op: ISD::FSQRT, VT: MVT::f128, Action: Custom);
1965 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Custom);
1966 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Custom);
1967
1968 setOperationAction(Op: ISD::FP_EXTEND, VT: MVT::f128, Action: Custom);
1969 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f64, Action: Custom);
1970 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f32, Action: Custom);
1971 }
1972
1973 if (Subtarget->fixAllFDIVSQRT()) {
1974 // Promote FDIVS and FSQRTS to FDIVD and FSQRTD instructions instead as
1975 // the former instructions generate errata on LEON processors.
1976 setOperationAction(Op: ISD::FDIV, VT: MVT::f32, Action: Promote);
1977 setOperationAction(Op: ISD::FSQRT, VT: MVT::f32, Action: Promote);
1978 }
1979
1980 if (Subtarget->hasNoFMULS()) {
1981 setOperationAction(Op: ISD::FMUL, VT: MVT::f32, Action: Promote);
1982 }
1983
1984 // Custom combine bitcast between f64 and v2i32
1985 if (!Subtarget->is64Bit())
1986 setTargetDAGCombine(ISD::BITCAST);
1987
1988 if (Subtarget->isV9())
1989 setTargetDAGCombine({ISD::BSWAP, ISD::STORE});
1990
1991 if (Subtarget->hasLeonCycleCounter())
1992 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Custom);
1993
1994 if (Subtarget->isVIS3()) {
1995 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Legal);
1996 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Legal);
1997 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i32, Action: Legal);
1998 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i64, Action: Legal);
1999
2000 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32,
2001 Action: Subtarget->is64Bit() ? Promote : Expand);
2002 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
2003 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i32,
2004 Action: Subtarget->is64Bit() ? Promote : Expand);
2005 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i64, Action: Expand);
2006 } else if (Subtarget->usePopc()) {
2007 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Expand);
2008 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Expand);
2009 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i32, Action: Expand);
2010 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i64, Action: Expand);
2011
2012 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32, Action: Expand);
2013 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
2014 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i32, Action: Expand);
2015 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i64, Action: Expand);
2016 } else {
2017 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Expand);
2018 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Expand);
2019 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i32,
2020 Action: Subtarget->is64Bit() ? Promote : LibCall);
2021 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i64, Action: LibCall);
2022
2023 // FIXME here we don't have any ISA extensions that could help us, so to
2024 // prevent large expansions those should be made into LibCalls.
2025 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32, Action: Expand);
2026 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
2027 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i32, Action: Expand);
2028 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i64, Action: Expand);
2029 }
2030
2031 setOperationAction(Op: ISD::INTRINSIC_WO_CHAIN, VT: MVT::Other, Action: Custom);
2032
2033 // Some processors have no branch predictor and have pipelines longer than
2034 // what can be covered by the delay slot. This results in a stall, so mark
2035 // branches to be expensive on those processors.
2036 setJumpIsExpensive(Subtarget->hasNoPredictor());
2037 // The high cost of branching means that using conditional moves will
2038 // still be profitable even if the condition is predictable.
2039 PredictableSelectIsExpensive = !isJumpExpensive();
2040
2041 setMinFunctionAlignment(Align(4));
2042
2043 computeRegisterProperties(TRI: Subtarget->getRegisterInfo());
2044}
2045
2046bool SparcTargetLowering::useSoftFloat() const {
2047 return Subtarget->useSoftFloat();
2048}
2049
2050EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
2051 EVT VT) const {
2052 if (!VT.isVector())
2053 return MVT::i32;
2054 return VT.changeVectorElementTypeToInteger();
2055}
2056
2057/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
2058/// be zero. Op is expected to be a target specific node. Used by DAG
2059/// combiner.
2060void SparcTargetLowering::computeKnownBitsForTargetNode
2061 (const SDValue Op,
2062 KnownBits &Known,
2063 const APInt &DemandedElts,
2064 const SelectionDAG &DAG,
2065 unsigned Depth) const {
2066 KnownBits Known2;
2067 Known.resetAll();
2068
2069 switch (Op.getOpcode()) {
2070 default: break;
2071 case SPISD::SELECT_ICC:
2072 case SPISD::SELECT_XCC:
2073 case SPISD::SELECT_FCC:
2074 Known = DAG.computeKnownBits(Op: Op.getOperand(i: 1), Depth: Depth + 1);
2075 Known2 = DAG.computeKnownBits(Op: Op.getOperand(i: 0), Depth: Depth + 1);
2076
2077 // Only known if known in both the LHS and RHS.
2078 Known = Known.intersectWith(RHS: Known2);
2079 break;
2080 }
2081}
2082
2083// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
2084// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
2085static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
2086 ISD::CondCode CC, unsigned &SPCC) {
2087 if (isNullConstant(V: RHS) && CC == ISD::SETNE &&
2088 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
2089 LHS.getOpcode() == SPISD::SELECT_XCC) &&
2090 LHS.getOperand(i: 3).getOpcode() == SPISD::CMPICC) ||
2091 (LHS.getOpcode() == SPISD::SELECT_FCC &&
2092 (LHS.getOperand(i: 3).getOpcode() == SPISD::CMPFCC ||
2093 LHS.getOperand(i: 3).getOpcode() == SPISD::CMPFCC_V9))) &&
2094 isOneConstant(V: LHS.getOperand(i: 0)) && isNullConstant(V: LHS.getOperand(i: 1))) {
2095 SDValue CMPCC = LHS.getOperand(i: 3);
2096 SPCC = LHS.getConstantOperandVal(i: 2);
2097 LHS = CMPCC.getOperand(i: 0);
2098 RHS = CMPCC.getOperand(i: 1);
2099 }
2100}
2101
2102// Convert to a target node and set target flags.
2103SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
2104 SelectionDAG &DAG) const {
2105 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Val&: Op))
2106 return DAG.getTargetGlobalAddress(GV: GA->getGlobal(),
2107 DL: SDLoc(GA),
2108 VT: GA->getValueType(ResNo: 0),
2109 offset: GA->getOffset(), TargetFlags: TF);
2110
2111 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Val&: Op))
2112 return DAG.getTargetConstantPool(C: CP->getConstVal(), VT: CP->getValueType(ResNo: 0),
2113 Align: CP->getAlign(), Offset: CP->getOffset(), TargetFlags: TF);
2114
2115 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Val&: Op))
2116 return DAG.getTargetBlockAddress(BA: BA->getBlockAddress(),
2117 VT: Op.getValueType(),
2118 Offset: 0,
2119 TargetFlags: TF);
2120
2121 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Val&: Op))
2122 return DAG.getTargetExternalSymbol(Sym: ES->getSymbol(),
2123 VT: ES->getValueType(ResNo: 0), TargetFlags: TF);
2124
2125 llvm_unreachable("Unhandled address SDNode");
2126}
2127
2128// Split Op into high and low parts according to HiTF and LoTF.
2129// Return an ADD node combining the parts.
2130SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
2131 unsigned HiTF, unsigned LoTF,
2132 SelectionDAG &DAG) const {
2133 SDLoc DL(Op);
2134 EVT VT = Op.getValueType();
2135 SDValue Hi = DAG.getNode(Opcode: SPISD::Hi, DL, VT, Operand: withTargetFlags(Op, TF: HiTF, DAG));
2136 SDValue Lo = DAG.getNode(Opcode: SPISD::Lo, DL, VT, Operand: withTargetFlags(Op, TF: LoTF, DAG));
2137 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Hi, N2: Lo);
2138}
2139
2140// Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
2141// or ExternalSymbol SDNode.
2142SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
2143 SDLoc DL(Op);
2144 EVT VT = getPointerTy(DL: DAG.getDataLayout());
2145
2146 // Handle PIC mode first. SPARC needs a got load for every variable!
2147 if (isPositionIndependent()) {
2148 const Module *M = DAG.getMachineFunction().getFunction().getParent();
2149 PICLevel::Level picLevel = M->getPICLevel();
2150 SDValue Idx;
2151
2152 if (picLevel == PICLevel::SmallPIC) {
2153 // This is the pic13 code model, the GOT is known to be smaller than 8KiB.
2154 Idx = DAG.getNode(Opcode: SPISD::Lo, DL, VT: Op.getValueType(),
2155 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_GOT13, DAG));
2156 } else {
2157 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
2158 Idx = makeHiLoPair(Op, HiTF: ELF::R_SPARC_GOT22, LoTF: ELF::R_SPARC_GOT10, DAG);
2159 }
2160
2161 SDValue GlobalBase = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT);
2162 SDValue AbsAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: GlobalBase, N2: Idx);
2163 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2164 // function has calls.
2165 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2166 MFI.setHasCalls(true);
2167 return DAG.getLoad(VT, dl: DL, Chain: DAG.getEntryNode(), Ptr: AbsAddr,
2168 PtrInfo: MachinePointerInfo::getGOT(MF&: DAG.getMachineFunction()));
2169 }
2170
2171 // This is one of the absolute code models.
2172 switch(getTargetMachine().getCodeModel()) {
2173 default:
2174 llvm_unreachable("Unsupported absolute code model");
2175 case CodeModel::Small:
2176 // abs32.
2177 return makeHiLoPair(Op, HiTF: ELF::R_SPARC_HI22, LoTF: ELF::R_SPARC_LO10, DAG);
2178 case CodeModel::Medium: {
2179 // abs44.
2180 SDValue H44 = makeHiLoPair(Op, HiTF: ELF::R_SPARC_H44, LoTF: ELF::R_SPARC_M44, DAG);
2181 H44 = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: H44, N2: DAG.getConstant(Val: 12, DL, VT: MVT::i32));
2182 SDValue L44 = withTargetFlags(Op, TF: ELF::R_SPARC_L44, DAG);
2183 L44 = DAG.getNode(Opcode: SPISD::Lo, DL, VT, Operand: L44);
2184 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: H44, N2: L44);
2185 }
2186 case CodeModel::Large: {
2187 // abs64.
2188 SDValue Hi = makeHiLoPair(Op, HiTF: ELF::R_SPARC_HH22, LoTF: ELF::R_SPARC_HM10, DAG);
2189 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi, N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
2190 SDValue Lo = makeHiLoPair(Op, HiTF: ELF::R_SPARC_HI22, LoTF: ELF::R_SPARC_LO10, DAG);
2191 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Hi, N2: Lo);
2192 }
2193 }
2194}
2195
2196SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
2197 SelectionDAG &DAG) const {
2198 return makeAddress(Op, DAG);
2199}
2200
2201SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
2202 SelectionDAG &DAG) const {
2203 return makeAddress(Op, DAG);
2204}
2205
2206SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
2207 SelectionDAG &DAG) const {
2208 return makeAddress(Op, DAG);
2209}
2210
2211SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2212 SelectionDAG &DAG) const {
2213
2214 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Val&: Op);
2215 if (DAG.getTarget().useEmulatedTLS())
2216 return LowerToTLSEmulatedModel(GA, DAG);
2217
2218 SDLoc DL(GA);
2219 const GlobalValue *GV = GA->getGlobal();
2220 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
2221
2222 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2223
2224 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2225 unsigned HiTF =
2226 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_HI22
2227 : ELF::R_SPARC_TLS_LDM_HI22);
2228 unsigned LoTF =
2229 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_LO10
2230 : ELF::R_SPARC_TLS_LDM_LO10);
2231 unsigned addTF =
2232 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_ADD
2233 : ELF::R_SPARC_TLS_LDM_ADD);
2234 unsigned callTF =
2235 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_CALL
2236 : ELF::R_SPARC_TLS_LDM_CALL);
2237
2238 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
2239 SDValue Base = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT: PtrVT);
2240 SDValue Argument = DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT, N1: Base, N2: HiLo,
2241 N3: withTargetFlags(Op, TF: addTF, DAG));
2242
2243 SDValue Chain = DAG.getEntryNode();
2244 SDValue InGlue;
2245
2246 Chain = DAG.getCALLSEQ_START(Chain, InSize: 0, OutSize: 0, DL);
2247 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SP::O0, N: Argument, Glue: InGlue);
2248 InGlue = Chain.getValue(R: 1);
2249 SDValue Callee = DAG.getTargetExternalSymbol(Sym: "__tls_get_addr", VT: PtrVT);
2250 SDValue Symbol = withTargetFlags(Op, TF: callTF, DAG);
2251
2252 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
2253 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
2254 MF: DAG.getMachineFunction(), CC: CallingConv::C);
2255 assert(Mask && "Missing call preserved mask for calling convention");
2256 SDValue Ops[] = {Chain,
2257 Callee,
2258 Symbol,
2259 DAG.getRegister(Reg: SP::O0, VT: PtrVT),
2260 DAG.getRegisterMask(RegMask: Mask),
2261 InGlue};
2262 Chain = DAG.getNode(Opcode: SPISD::TLS_CALL, DL, VTList: NodeTys, Ops);
2263 InGlue = Chain.getValue(R: 1);
2264 Chain = DAG.getCALLSEQ_END(Chain, Size1: 0, Size2: 0, Glue: InGlue, DL);
2265 InGlue = Chain.getValue(R: 1);
2266 SDValue Ret = DAG.getCopyFromReg(Chain, dl: DL, Reg: SP::O0, VT: PtrVT, Glue: InGlue);
2267
2268 if (model != TLSModel::LocalDynamic)
2269 return Ret;
2270
2271 SDValue Hi =
2272 DAG.getNode(Opcode: SPISD::Hi, DL, VT: PtrVT,
2273 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_HIX22, DAG));
2274 SDValue Lo =
2275 DAG.getNode(Opcode: SPISD::Lo, DL, VT: PtrVT,
2276 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_LOX10, DAG));
2277 HiLo = DAG.getNode(Opcode: ISD::XOR, DL, VT: PtrVT, N1: Hi, N2: Lo);
2278 return DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT, N1: Ret, N2: HiLo,
2279 N3: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_ADD, DAG));
2280 }
2281
2282 if (model == TLSModel::InitialExec) {
2283 unsigned ldTF = ((PtrVT == MVT::i64) ? ELF::R_SPARC_TLS_IE_LDX
2284 : ELF::R_SPARC_TLS_IE_LD);
2285
2286 SDValue Base = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT: PtrVT);
2287
2288 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2289 // function has calls.
2290 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2291 MFI.setHasCalls(true);
2292
2293 SDValue TGA = makeHiLoPair(Op, HiTF: ELF::R_SPARC_TLS_IE_HI22,
2294 LoTF: ELF::R_SPARC_TLS_IE_LO10, DAG);
2295 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: Base, N2: TGA);
2296 SDValue Offset = DAG.getNode(Opcode: SPISD::TLS_LD,
2297 DL, VT: PtrVT, N1: Ptr,
2298 N2: withTargetFlags(Op, TF: ldTF, DAG));
2299 return DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT,
2300 N1: DAG.getRegister(Reg: SP::G7, VT: PtrVT), N2: Offset,
2301 N3: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_IE_ADD, DAG));
2302 }
2303
2304 assert(model == TLSModel::LocalExec);
2305 SDValue Hi = DAG.getNode(Opcode: SPISD::Hi, DL, VT: PtrVT,
2306 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LE_HIX22, DAG));
2307 SDValue Lo = DAG.getNode(Opcode: SPISD::Lo, DL, VT: PtrVT,
2308 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LE_LOX10, DAG));
2309 SDValue Offset = DAG.getNode(Opcode: ISD::XOR, DL, VT: PtrVT, N1: Hi, N2: Lo);
2310
2311 return DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT,
2312 N1: DAG.getRegister(Reg: SP::G7, VT: PtrVT), N2: Offset);
2313}
2314
2315SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain,
2316 ArgListTy &Args, SDValue Arg,
2317 const SDLoc &DL,
2318 SelectionDAG &DAG) const {
2319 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2320 EVT ArgVT = Arg.getValueType();
2321 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
2322
2323 if (ArgTy->isFP128Ty()) {
2324 // Create a stack object and pass the pointer to the library function.
2325 int FI = MFI.CreateStackObject(Size: 16, Alignment: Align(8), isSpillSlot: false);
2326 SDValue FIPtr = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
2327 Chain = DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: FIPtr, PtrInfo: MachinePointerInfo(), Alignment: Align(8));
2328 Args.emplace_back(args&: FIPtr, args: PointerType::getUnqual(C&: ArgTy->getContext()));
2329 } else {
2330 Args.emplace_back(args&: Arg, args&: ArgTy);
2331 }
2332 return Chain;
2333}
2334
2335SDValue SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2336 RTLIB::Libcall LibFunc,
2337 unsigned numArgs) const {
2338 RTLIB::LibcallImpl LibFuncImpl = DAG.getLibcalls().getLibcallImpl(Call: LibFunc);
2339 if (LibFuncImpl == RTLIB::Unsupported)
2340 return SDValue();
2341
2342 ArgListTy Args;
2343
2344 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2345 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2346
2347 SDValue Callee = DAG.getExternalSymbol(LCImpl: LibFuncImpl, VT: PtrVT);
2348 Type *RetTy = Op.getValueType().getTypeForEVT(Context&: *DAG.getContext());
2349 Type *RetTyABI = RetTy;
2350 SDValue Chain = DAG.getEntryNode();
2351 SDValue RetPtr;
2352
2353 if (RetTy->isFP128Ty()) {
2354 // Create a Stack Object to receive the return value of type f128.
2355 int RetFI = MFI.CreateStackObject(Size: 16, Alignment: Align(8), isSpillSlot: false);
2356 RetPtr = DAG.getFrameIndex(FI: RetFI, VT: PtrVT);
2357 ArgListEntry Entry(RetPtr, PointerType::getUnqual(C&: RetTy->getContext()));
2358 if (!Subtarget->is64Bit()) {
2359 Entry.IsSRet = true;
2360 Entry.IndirectType = RetTy;
2361 }
2362 Entry.IsReturned = false;
2363 Args.push_back(x: Entry);
2364 RetTyABI = Type::getVoidTy(C&: *DAG.getContext());
2365 }
2366
2367 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2368 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2369 Chain = LowerF128_LibCallArg(Chain, Args, Arg: Op.getOperand(i), DL: SDLoc(Op), DAG);
2370 }
2371
2372 CallingConv::ID CC = DAG.getLibcalls().getLibcallImplCallingConv(Call: LibFuncImpl);
2373 TargetLowering::CallLoweringInfo CLI(DAG);
2374 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain).setCallee(CC, ResultType: RetTyABI, Target: Callee,
2375 ArgsList: std::move(Args));
2376
2377 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2378
2379 // chain is in second result.
2380 if (RetTyABI == RetTy)
2381 return CallInfo.first;
2382
2383 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2384
2385 Chain = CallInfo.second;
2386
2387 // Load RetPtr to get the return value.
2388 return DAG.getLoad(VT: Op.getValueType(), dl: SDLoc(Op), Chain, Ptr: RetPtr,
2389 PtrInfo: MachinePointerInfo(), Alignment: Align(8));
2390}
2391
2392SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2393 unsigned &SPCC, const SDLoc &DL,
2394 SelectionDAG &DAG) const {
2395
2396 const char *LibCall = nullptr;
2397 bool is64Bit = Subtarget->is64Bit();
2398 switch(SPCC) {
2399 default: llvm_unreachable("Unhandled conditional code!");
2400 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2401 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2402 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2403 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2404 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2405 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2406 case SPCC::FCC_UL :
2407 case SPCC::FCC_ULE:
2408 case SPCC::FCC_UG :
2409 case SPCC::FCC_UGE:
2410 case SPCC::FCC_U :
2411 case SPCC::FCC_O :
2412 case SPCC::FCC_LG :
2413 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2414 }
2415
2416 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2417 SDValue Callee = DAG.getExternalSymbol(Sym: LibCall, VT: PtrVT);
2418 Type *RetTy = Type::getInt32Ty(C&: *DAG.getContext());
2419 ArgListTy Args;
2420 SDValue Chain = DAG.getEntryNode();
2421 Chain = LowerF128_LibCallArg(Chain, Args, Arg: LHS, DL, DAG);
2422 Chain = LowerF128_LibCallArg(Chain, Args, Arg: RHS, DL, DAG);
2423
2424 TargetLowering::CallLoweringInfo CLI(DAG);
2425 CLI.setDebugLoc(DL).setChain(Chain)
2426 .setCallee(CC: CallingConv::C, ResultType: RetTy, Target: Callee, ArgsList: std::move(Args));
2427
2428 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2429
2430 // result is in first, and chain is in second result.
2431 SDValue Result = CallInfo.first;
2432
2433 switch(SPCC) {
2434 default: {
2435 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2436 SPCC = SPCC::ICC_NE;
2437 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2438 }
2439 case SPCC::FCC_UL : {
2440 SDValue Mask = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2441 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2442 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2443 SPCC = SPCC::ICC_NE;
2444 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2445 }
2446 case SPCC::FCC_ULE: {
2447 SDValue RHS = DAG.getConstant(Val: 2, DL, VT: Result.getValueType());
2448 SPCC = SPCC::ICC_NE;
2449 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2450 }
2451 case SPCC::FCC_UG : {
2452 SDValue RHS = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2453 SPCC = SPCC::ICC_G;
2454 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2455 }
2456 case SPCC::FCC_UGE: {
2457 SDValue RHS = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2458 SPCC = SPCC::ICC_NE;
2459 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2460 }
2461
2462 case SPCC::FCC_U : {
2463 SDValue RHS = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2464 SPCC = SPCC::ICC_E;
2465 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2466 }
2467 case SPCC::FCC_O : {
2468 SDValue RHS = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2469 SPCC = SPCC::ICC_NE;
2470 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2471 }
2472 case SPCC::FCC_LG : {
2473 SDValue Mask = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2474 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2475 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2476 SPCC = SPCC::ICC_NE;
2477 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2478 }
2479 case SPCC::FCC_UE : {
2480 SDValue Mask = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2481 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2482 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2483 SPCC = SPCC::ICC_E;
2484 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2485 }
2486 }
2487}
2488
2489static SDValue
2490LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2491 const SparcTargetLowering &TLI) {
2492
2493 if (Op.getOperand(i: 0).getValueType() == MVT::f64)
2494 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPEXT_F64_F128, numArgs: 1);
2495
2496 if (Op.getOperand(i: 0).getValueType() == MVT::f32)
2497 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPEXT_F32_F128, numArgs: 1);
2498
2499 llvm_unreachable("fpextend with non-float operand!");
2500 return SDValue();
2501}
2502
2503static SDValue
2504LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2505 const SparcTargetLowering &TLI) {
2506 // FP_ROUND on f64 and f32 are legal.
2507 if (Op.getOperand(i: 0).getValueType() != MVT::f128)
2508 return Op;
2509
2510 if (Op.getValueType() == MVT::f64)
2511 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPROUND_F128_F64, numArgs: 1);
2512 if (Op.getValueType() == MVT::f32)
2513 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPROUND_F128_F32, numArgs: 1);
2514
2515 llvm_unreachable("fpround to non-float!");
2516 return SDValue();
2517}
2518
2519static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2520 const SparcTargetLowering &TLI,
2521 bool hasHardQuad) {
2522 SDLoc dl(Op);
2523 EVT VT = Op.getValueType();
2524 assert(VT == MVT::i32 || VT == MVT::i64);
2525
2526 // Expand f128 operations to fp128 abi calls.
2527 if (Op.getOperand(i: 0).getValueType() == MVT::f128
2528 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2529 RTLIB::Libcall LibFunc =
2530 VT == MVT::i32 ? RTLIB::FPTOSINT_F128_I32 : RTLIB::FPTOSINT_F128_I64;
2531 return TLI.LowerF128Op(Op, DAG, LibFunc, numArgs: 1);
2532 }
2533
2534 // Expand if the resulting type is illegal.
2535 if (!TLI.isTypeLegal(VT))
2536 return SDValue();
2537
2538 // Otherwise, Convert the fp value to integer in an FP register.
2539 if (VT == MVT::i32)
2540 Op = DAG.getNode(Opcode: SPISD::FTOI, DL: dl, VT: MVT::f32, Operand: Op.getOperand(i: 0));
2541 else
2542 Op = DAG.getNode(Opcode: SPISD::FTOX, DL: dl, VT: MVT::f64, Operand: Op.getOperand(i: 0));
2543
2544 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT, Operand: Op);
2545}
2546
2547static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2548 const SparcTargetLowering &TLI,
2549 bool hasHardQuad) {
2550 SDLoc dl(Op);
2551 EVT OpVT = Op.getOperand(i: 0).getValueType();
2552 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2553
2554 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2555
2556 // Expand f128 operations to fp128 ABI calls.
2557 if (Op.getValueType() == MVT::f128
2558 && (!hasHardQuad || !TLI.isTypeLegal(VT: OpVT))) {
2559 RTLIB::Libcall LibFunc =
2560 OpVT == MVT::i32 ? RTLIB::SINTTOFP_I32_F128 : RTLIB::SINTTOFP_I64_F128;
2561 return TLI.LowerF128Op(Op, DAG, LibFunc, numArgs: 1);
2562 }
2563
2564 // Expand if the operand type is illegal.
2565 if (!TLI.isTypeLegal(VT: OpVT))
2566 return SDValue();
2567
2568 // Otherwise, Convert the int value to FP in an FP register.
2569 SDValue Tmp = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: floatVT, Operand: Op.getOperand(i: 0));
2570 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2571 return DAG.getNode(Opcode: opcode, DL: dl, VT: Op.getValueType(), Operand: Tmp);
2572}
2573
2574static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2575 const SparcTargetLowering &TLI,
2576 bool hasHardQuad) {
2577 EVT VT = Op.getValueType();
2578
2579 // Expand if it does not involve f128 or the target has support for
2580 // quad floating point instructions and the resulting type is legal.
2581 if (Op.getOperand(i: 0).getValueType() != MVT::f128 ||
2582 (hasHardQuad && TLI.isTypeLegal(VT)))
2583 return SDValue();
2584
2585 assert(VT == MVT::i32 || VT == MVT::i64);
2586
2587 return TLI.LowerF128Op(
2588 Op, DAG,
2589 LibFunc: VT == MVT::i32 ? RTLIB::FPTOUINT_F128_I32 : RTLIB::FPTOUINT_F128_I64, numArgs: 1);
2590}
2591
2592static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2593 const SparcTargetLowering &TLI,
2594 bool hasHardQuad) {
2595 EVT OpVT = Op.getOperand(i: 0).getValueType();
2596 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2597
2598 // Expand if it does not involve f128 or the target has support for
2599 // quad floating point instructions and the operand type is legal.
2600 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(VT: OpVT)))
2601 return SDValue();
2602
2603 return TLI.LowerF128Op(Op, DAG,
2604 LibFunc: OpVT == MVT::i32 ? RTLIB::UINTTOFP_I32_F128
2605 : RTLIB::UINTTOFP_I64_F128,
2606 numArgs: 1);
2607}
2608
2609static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2610 const SparcTargetLowering &TLI, bool hasHardQuad,
2611 bool isV9, bool is64Bit) {
2612 SDValue Chain = Op.getOperand(i: 0);
2613 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 1))->get();
2614 SDValue LHS = Op.getOperand(i: 2);
2615 SDValue RHS = Op.getOperand(i: 3);
2616 SDValue Dest = Op.getOperand(i: 4);
2617 SDLoc dl(Op);
2618 unsigned Opc, SPCC = ~0U;
2619
2620 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2621 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2622 LookThroughSetCC(LHS, RHS, CC, SPCC);
2623 assert(LHS.getValueType() == RHS.getValueType());
2624
2625 // Get the condition flag.
2626 SDValue CompareFlag;
2627 if (LHS.getValueType().isInteger()) {
2628 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2629 // and the RHS is zero we might be able to use a specialized branch.
2630 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2631 isNullConstant(V: RHS) && !ISD::isUnsignedIntSetCC(Code: CC))
2632 return DAG.getNode(Opcode: SPISD::BR_REG, DL: dl, VT: MVT::Other, N1: Chain, N2: Dest,
2633 N3: DAG.getConstant(Val: intCondCCodeToRcond(CC), DL: dl, VT: MVT::i32),
2634 N4: LHS);
2635
2636 CompareFlag = DAG.getNode(Opcode: SPISD::CMPICC, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2637 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2638 if (isV9)
2639 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2640 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BPICC : SPISD::BPXCC;
2641 else
2642 // Non-v9 targets don't have xcc.
2643 Opc = SPISD::BRICC;
2644 } else {
2645 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2646 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2647 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, DL: dl, DAG);
2648 Opc = isV9 ? SPISD::BPICC : SPISD::BRICC;
2649 } else {
2650 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2651 CompareFlag = DAG.getNode(Opcode: CmpOpc, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2652 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2653 Opc = isV9 ? SPISD::BRFCC_V9 : SPISD::BRFCC;
2654 }
2655 }
2656 return DAG.getNode(Opcode: Opc, DL: dl, VT: MVT::Other, N1: Chain, N2: Dest,
2657 N3: DAG.getConstant(Val: SPCC, DL: dl, VT: MVT::i32), N4: CompareFlag);
2658}
2659
2660static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2661 const SparcTargetLowering &TLI, bool hasHardQuad,
2662 bool isV9, bool is64Bit) {
2663 SDValue LHS = Op.getOperand(i: 0);
2664 SDValue RHS = Op.getOperand(i: 1);
2665 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 4))->get();
2666 SDValue TrueVal = Op.getOperand(i: 2);
2667 SDValue FalseVal = Op.getOperand(i: 3);
2668 SDLoc dl(Op);
2669 unsigned Opc, SPCC = ~0U;
2670
2671 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2672 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2673 LookThroughSetCC(LHS, RHS, CC, SPCC);
2674 assert(LHS.getValueType() == RHS.getValueType());
2675
2676 SDValue CompareFlag;
2677 if (LHS.getValueType().isInteger()) {
2678 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2679 // and the RHS is zero we might be able to use a specialized select.
2680 // All SELECT_CC between any two scalar integer types are eligible for
2681 // lowering to specialized instructions. Additionally, f32 and f64 types
2682 // are also eligible, but for f128 we can only use the specialized
2683 // instruction when we have hardquad.
2684 EVT ValType = TrueVal.getValueType();
2685 bool IsEligibleType = ValType.isScalarInteger() || ValType == MVT::f32 ||
2686 ValType == MVT::f64 ||
2687 (ValType == MVT::f128 && hasHardQuad);
2688 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2689 isNullConstant(V: RHS) && !ISD::isUnsignedIntSetCC(Code: CC) && IsEligibleType)
2690 return DAG.getNode(
2691 Opcode: SPISD::SELECT_REG, DL: dl, VT: TrueVal.getValueType(), N1: TrueVal, N2: FalseVal,
2692 N3: DAG.getConstant(Val: intCondCCodeToRcond(CC), DL: dl, VT: MVT::i32), N4: LHS);
2693
2694 CompareFlag = DAG.getNode(Opcode: SPISD::CMPICC, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2695 Opc = LHS.getValueType() == MVT::i32 ?
2696 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2697 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2698 } else {
2699 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2700 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2701 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, DL: dl, DAG);
2702 Opc = SPISD::SELECT_ICC;
2703 } else {
2704 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2705 CompareFlag = DAG.getNode(Opcode: CmpOpc, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2706 Opc = SPISD::SELECT_FCC;
2707 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2708 }
2709 }
2710 return DAG.getNode(Opcode: Opc, DL: dl, VT: TrueVal.getValueType(), N1: TrueVal, N2: FalseVal,
2711 N3: DAG.getConstant(Val: SPCC, DL: dl, VT: MVT::i32), N4: CompareFlag);
2712}
2713
2714static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2715 const SparcTargetLowering &TLI) {
2716 MachineFunction &MF = DAG.getMachineFunction();
2717 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2718 auto PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
2719
2720 // Need frame address to find the address of VarArgsFrameIndex.
2721 MF.getFrameInfo().setFrameAddressIsTaken(true);
2722
2723 // vastart just stores the address of the VarArgsFrameIndex slot into the
2724 // memory location argument.
2725 SDLoc DL(Op);
2726 SDValue Offset =
2727 DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: DAG.getRegister(Reg: SP::I6, VT: PtrVT),
2728 N2: DAG.getIntPtrConstant(Val: FuncInfo->getVarArgsFrameOffset(), DL));
2729 const Value *SV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 2))->getValue();
2730 return DAG.getStore(Chain: Op.getOperand(i: 0), dl: DL, Val: Offset, Ptr: Op.getOperand(i: 1),
2731 PtrInfo: MachinePointerInfo(SV));
2732}
2733
2734static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2735 SDNode *Node = Op.getNode();
2736 EVT VT = Node->getValueType(ResNo: 0);
2737 SDValue InChain = Node->getOperand(Num: 0);
2738 SDValue VAListPtr = Node->getOperand(Num: 1);
2739 EVT PtrVT = VAListPtr.getValueType();
2740 const Value *SV = cast<SrcValueSDNode>(Val: Node->getOperand(Num: 2))->getValue();
2741 SDLoc DL(Node);
2742 SDValue VAList =
2743 DAG.getLoad(VT: PtrVT, dl: DL, Chain: InChain, Ptr: VAListPtr, PtrInfo: MachinePointerInfo(SV));
2744 // Increment the pointer, VAList, to the next vaarg.
2745 SDValue NextPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: VAList,
2746 N2: DAG.getIntPtrConstant(Val: VT.getSizeInBits()/8,
2747 DL));
2748 // Store the incremented VAList to the legalized pointer.
2749 InChain = DAG.getStore(Chain: VAList.getValue(R: 1), dl: DL, Val: NextPtr, Ptr: VAListPtr,
2750 PtrInfo: MachinePointerInfo(SV));
2751 // Load the actual argument out of the pointer VAList.
2752 // We can't count on greater alignment than the word size.
2753 return DAG.getLoad(
2754 VT, dl: DL, Chain: InChain, Ptr: VAList, PtrInfo: MachinePointerInfo(),
2755 Alignment: Align(std::min(a: PtrVT.getFixedSizeInBits(), b: VT.getFixedSizeInBits()) / 8));
2756}
2757
2758static SDValue LowerSTACKADDRESS(SDValue Op, SelectionDAG &DAG,
2759 const SparcSubtarget &Subtarget) {
2760 SDValue Chain = Op.getOperand(i: 0);
2761 EVT VT = Op->getValueType(ResNo: 0);
2762 SDLoc DL(Op);
2763
2764 MCRegister SPReg = SP::O6;
2765 SDValue SP = DAG.getCopyFromReg(Chain, dl: DL, Reg: SPReg, VT);
2766
2767 // Unbias the stack pointer register.
2768 unsigned OffsetToStackStart = Subtarget.getStackPointerBias();
2769 // Move past the register save area: 8 in registers + 8 local registers.
2770 OffsetToStackStart += 16 * (Subtarget.is64Bit() ? 8 : 4);
2771 // Move past the struct return address slot (4 bytes) on SPARC 32-bit.
2772 if (!Subtarget.is64Bit())
2773 OffsetToStackStart += 4;
2774
2775 SDValue StackAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: SP,
2776 N2: DAG.getConstant(Val: OffsetToStackStart, DL, VT));
2777 return DAG.getMergeValues(Ops: {StackAddr, Chain}, dl: DL);
2778}
2779
2780static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2781 const SparcSubtarget *Subtarget) {
2782 SDValue Chain = Op.getOperand(i: 0);
2783 SDValue Size = Op.getOperand(i: 1);
2784 SDValue Alignment = Op.getOperand(i: 2);
2785 MaybeAlign MaybeAlignment =
2786 cast<ConstantSDNode>(Val&: Alignment)->getMaybeAlignValue();
2787 EVT VT = Size->getValueType(ResNo: 0);
2788 SDLoc dl(Op);
2789
2790 unsigned SPReg = SP::O6;
2791 SDValue SP = DAG.getCopyFromReg(Chain, dl, Reg: SPReg, VT);
2792
2793 // The resultant pointer needs to be above the register spill area
2794 // at the bottom of the stack.
2795 unsigned regSpillArea;
2796 if (Subtarget->is64Bit()) {
2797 regSpillArea = 128;
2798 } else {
2799 // On Sparc32, the size of the spill area is 92. Unfortunately,
2800 // that's only 4-byte aligned, not 8-byte aligned (the stack
2801 // pointer is 8-byte aligned). So, if the user asked for an 8-byte
2802 // aligned dynamic allocation, we actually need to add 96 to the
2803 // bottom of the stack, instead of 92, to ensure 8-byte alignment.
2804
2805 // That also means adding 4 to the size of the allocation --
2806 // before applying the 8-byte rounding. Unfortunately, we the
2807 // value we get here has already had rounding applied. So, we need
2808 // to add 8, instead, wasting a bit more memory.
2809
2810 // Further, this only actually needs to be done if the required
2811 // alignment is > 4, but, we've lost that info by this point, too,
2812 // so we always apply it.
2813
2814 // (An alternative approach would be to always reserve 96 bytes
2815 // instead of the required 92, but then we'd waste 4 extra bytes
2816 // in every frame, not just those with dynamic stack allocations)
2817
2818 // TODO: modify code in SelectionDAGBuilder to make this less sad.
2819
2820 Size = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: Size,
2821 N2: DAG.getConstant(Val: 8, DL: dl, VT));
2822 regSpillArea = 96;
2823 }
2824
2825 int64_t Bias = Subtarget->getStackPointerBias();
2826
2827 // Debias and increment SP past the reserved spill area.
2828 // We need the SP to point to the first usable region before calculating
2829 // anything to prevent any of the pointers from becoming out of alignment when
2830 // we rebias the SP later on.
2831 SDValue StartOfUsableStack = DAG.getNode(
2832 Opcode: ISD::ADD, DL: dl, VT, N1: SP, N2: DAG.getConstant(Val: regSpillArea + Bias, DL: dl, VT));
2833 SDValue AllocatedPtr =
2834 DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: StartOfUsableStack, N2: Size);
2835
2836 bool IsOveraligned = MaybeAlignment.has_value();
2837 SDValue AlignedPtr =
2838 IsOveraligned
2839 ? DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: AllocatedPtr,
2840 N2: DAG.getSignedConstant(Val: -MaybeAlignment->value(), DL: dl, VT))
2841 : AllocatedPtr;
2842
2843 // Now that we are done, restore the bias and reserved spill area.
2844 SDValue NewSP = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: AlignedPtr,
2845 N2: DAG.getConstant(Val: regSpillArea + Bias, DL: dl, VT));
2846 Chain = DAG.getCopyToReg(Chain: SP.getValue(R: 1), dl, Reg: SPReg, N: NewSP);
2847 SDValue Ops[2] = {AlignedPtr, Chain};
2848 return DAG.getMergeValues(Ops, dl);
2849}
2850
2851
2852static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2853 SDLoc dl(Op);
2854 SDValue Chain = DAG.getNode(Opcode: SPISD::FLUSHW,
2855 DL: dl, VT: MVT::Other, Operand: DAG.getEntryNode());
2856 return Chain;
2857}
2858
2859static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2860 const SparcSubtarget *Subtarget,
2861 bool AlwaysFlush = false) {
2862 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2863 MFI.setFrameAddressIsTaken(true);
2864
2865 EVT VT = Op.getValueType();
2866 SDLoc dl(Op);
2867 unsigned FrameReg = SP::I6;
2868 unsigned stackBias = Subtarget->getStackPointerBias();
2869
2870 SDValue FrameAddr;
2871 SDValue Chain;
2872
2873 // flush first to make sure the windowed registers' values are in stack
2874 Chain = (depth || AlwaysFlush) ? getFLUSHW(Op, DAG) : DAG.getEntryNode();
2875
2876 FrameAddr = DAG.getCopyFromReg(Chain, dl, Reg: FrameReg, VT);
2877
2878 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2879
2880 while (depth--) {
2881 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: FrameAddr,
2882 N2: DAG.getIntPtrConstant(Val: Offset, DL: dl));
2883 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, PtrInfo: MachinePointerInfo());
2884 }
2885 if (Subtarget->is64Bit())
2886 FrameAddr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: FrameAddr,
2887 N2: DAG.getIntPtrConstant(Val: stackBias, DL: dl));
2888 return FrameAddr;
2889}
2890
2891
2892static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2893 const SparcSubtarget *Subtarget) {
2894
2895 uint64_t depth = Op.getConstantOperandVal(i: 0);
2896
2897 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2898
2899}
2900
2901static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2902 const SparcTargetLowering &TLI,
2903 const SparcSubtarget *Subtarget) {
2904 MachineFunction &MF = DAG.getMachineFunction();
2905 MachineFrameInfo &MFI = MF.getFrameInfo();
2906 MFI.setReturnAddressIsTaken(true);
2907
2908 EVT VT = Op.getValueType();
2909 SDLoc dl(Op);
2910 uint64_t depth = Op.getConstantOperandVal(i: 0);
2911
2912 SDValue RetAddr;
2913 if (depth == 0) {
2914 auto PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
2915 Register RetReg = MF.addLiveIn(PReg: SP::I7, RC: TLI.getRegClassFor(VT: PtrVT));
2916 RetAddr = DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl, Reg: RetReg, VT);
2917 return RetAddr;
2918 }
2919
2920 // Need frame address to find return address of the caller.
2921 SDValue FrameAddr = getFRAMEADDR(depth: depth - 1, Op, DAG, Subtarget, AlwaysFlush: true);
2922
2923 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2924 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD,
2925 DL: dl, VT,
2926 N1: FrameAddr,
2927 N2: DAG.getIntPtrConstant(Val: Offset, DL: dl));
2928 RetAddr = DAG.getLoad(VT, dl, Chain: DAG.getEntryNode(), Ptr, PtrInfo: MachinePointerInfo());
2929
2930 return RetAddr;
2931}
2932
2933static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG,
2934 unsigned opcode) {
2935 assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2936 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2937
2938 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2939 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2940 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2941
2942 // Note: in little-endian, the floating-point value is stored in the
2943 // registers are in the opposite order, so the subreg with the sign
2944 // bit is the highest-numbered (odd), rather than the
2945 // lowest-numbered (even).
2946
2947 SDValue Hi32 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_even, DL: dl, VT: MVT::f32,
2948 Operand: SrcReg64);
2949 SDValue Lo32 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_odd, DL: dl, VT: MVT::f32,
2950 Operand: SrcReg64);
2951
2952 if (DAG.getDataLayout().isLittleEndian())
2953 Lo32 = DAG.getNode(Opcode: opcode, DL: dl, VT: MVT::f32, Operand: Lo32);
2954 else
2955 Hi32 = DAG.getNode(Opcode: opcode, DL: dl, VT: MVT::f32, Operand: Hi32);
2956
2957 SDValue DstReg64 = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
2958 dl, VT: MVT::f64), 0);
2959 DstReg64 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_even, DL: dl, VT: MVT::f64,
2960 Operand: DstReg64, Subreg: Hi32);
2961 DstReg64 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_odd, DL: dl, VT: MVT::f64,
2962 Operand: DstReg64, Subreg: Lo32);
2963 return DstReg64;
2964}
2965
2966// Lower a f128 load into two f64 loads.
2967static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2968{
2969 SDLoc dl(Op);
2970 LoadSDNode *LdNode = cast<LoadSDNode>(Val: Op.getNode());
2971 assert(LdNode->getOffset().isUndef() && "Unexpected node type");
2972
2973 Align Alignment = commonAlignment(A: LdNode->getBaseAlign(), Offset: 8);
2974
2975 SDValue Hi64 =
2976 DAG.getLoad(VT: MVT::f64, dl, Chain: LdNode->getChain(), Ptr: LdNode->getBasePtr(),
2977 PtrInfo: LdNode->getPointerInfo(), Alignment);
2978 EVT addrVT = LdNode->getBasePtr().getValueType();
2979 SDValue LoPtr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: addrVT,
2980 N1: LdNode->getBasePtr(),
2981 N2: DAG.getConstant(Val: 8, DL: dl, VT: addrVT));
2982 SDValue Lo64 = DAG.getLoad(VT: MVT::f64, dl, Chain: LdNode->getChain(), Ptr: LoPtr,
2983 PtrInfo: LdNode->getPointerInfo().getWithOffset(O: 8),
2984 Alignment);
2985
2986 SDValue SubRegEven = DAG.getTargetConstant(Val: SP::sub_even64, DL: dl, VT: MVT::i32);
2987 SDValue SubRegOdd = DAG.getTargetConstant(Val: SP::sub_odd64, DL: dl, VT: MVT::i32);
2988
2989 SDNode *InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
2990 dl, VT: MVT::f128);
2991 InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl,
2992 VT: MVT::f128,
2993 Op1: SDValue(InFP128, 0),
2994 Op2: Hi64,
2995 Op3: SubRegEven);
2996 InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl,
2997 VT: MVT::f128,
2998 Op1: SDValue(InFP128, 0),
2999 Op2: Lo64,
3000 Op3: SubRegOdd);
3001 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
3002 SDValue(Lo64.getNode(), 1) };
3003 SDValue OutChain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
3004 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
3005 return DAG.getMergeValues(Ops, dl);
3006}
3007
3008SDValue SparcTargetLowering::LowerBSWAP(SDValue Op, SelectionDAG &DAG) const {
3009 // We don't have an in-register bswap, so expand bswap(x) into
3010 // load(store-swapped(x)). The reason the swap is done during the store is
3011 // that on some implementations (mainly older ones) ASI-tagged memory
3012 // operations are not pipelined, and generally stores finish faster than
3013 // loads.
3014
3015 MachineFunction &MF = DAG.getMachineFunction();
3016 MachineFrameInfo &MFI = MF.getFrameInfo();
3017 MVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
3018 SDValue Chain = DAG.getEntryNode();
3019 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
3020 SDLoc DL(Op);
3021
3022 SDValue BSwapOp = Op.getOperand(i: 0);
3023 EVT VT = BSwapOp.getValueType();
3024 Type *Ty = VT.getTypeForEVT(Context&: *DAG.getContext());
3025 Align Al = DAG.getDataLayout().getPrefTypeAlign(Ty);
3026
3027 // Create a stack object to serve as temporary storage.
3028 int TmpFI = MFI.CreateStackObject(Size: VT.getStoreSize(), Alignment: Al, isSpillSlot: false);
3029 SDValue TmpPtr = DAG.getFrameIndex(FI: TmpFI, VT: PtrVT);
3030
3031 // Store-swap the value, then load it back.
3032 SDValue Ops[] = {Chain, BSwapOp, TmpPtr, DAG.getValueType(VT)};
3033 SDValue ST = DAG.getMemIntrinsicNode(
3034 Opcode: IsLittleEndian ? SPISD::STORE_BIG : SPISD::STORE_LITTLE, dl: DL,
3035 VTList: DAG.getVTList(VT: MVT::Other), Ops, MemVT: VT,
3036 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI: TmpFI));
3037 return DAG.getLoad(VT, dl: DL, Chain: ST, Ptr: TmpPtr,
3038 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI: TmpFI));
3039}
3040
3041static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
3042{
3043 LoadSDNode *LdNode = cast<LoadSDNode>(Val: Op.getNode());
3044
3045 EVT MemVT = LdNode->getMemoryVT();
3046 if (MemVT == MVT::f128)
3047 return LowerF128Load(Op, DAG);
3048
3049 return Op;
3050}
3051
3052// Lower a f128 store into two f64 stores.
3053static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
3054 SDLoc dl(Op);
3055 StoreSDNode *StNode = cast<StoreSDNode>(Val: Op.getNode());
3056 assert(StNode->getOffset().isUndef() && "Unexpected node type");
3057
3058 SDValue SubRegEven = DAG.getTargetConstant(Val: SP::sub_even64, DL: dl, VT: MVT::i32);
3059 SDValue SubRegOdd = DAG.getTargetConstant(Val: SP::sub_odd64, DL: dl, VT: MVT::i32);
3060
3061 SDNode *Hi64 = DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG,
3062 dl,
3063 VT: MVT::f64,
3064 Op1: StNode->getValue(),
3065 Op2: SubRegEven);
3066 SDNode *Lo64 = DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG,
3067 dl,
3068 VT: MVT::f64,
3069 Op1: StNode->getValue(),
3070 Op2: SubRegOdd);
3071
3072 Align Alignment = commonAlignment(A: StNode->getBaseAlign(), Offset: 8);
3073
3074 SDValue OutChains[2];
3075 OutChains[0] =
3076 DAG.getStore(Chain: StNode->getChain(), dl, Val: SDValue(Hi64, 0),
3077 Ptr: StNode->getBasePtr(), PtrInfo: StNode->getPointerInfo(),
3078 Alignment);
3079 EVT addrVT = StNode->getBasePtr().getValueType();
3080 SDValue LoPtr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: addrVT,
3081 N1: StNode->getBasePtr(),
3082 N2: DAG.getConstant(Val: 8, DL: dl, VT: addrVT));
3083 OutChains[1] = DAG.getStore(Chain: StNode->getChain(), dl, Val: SDValue(Lo64, 0), Ptr: LoPtr,
3084 PtrInfo: StNode->getPointerInfo().getWithOffset(O: 8),
3085 Alignment);
3086 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
3087}
3088
3089static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
3090{
3091 SDLoc dl(Op);
3092 StoreSDNode *St = cast<StoreSDNode>(Val: Op.getNode());
3093
3094 EVT MemVT = St->getMemoryVT();
3095 if (MemVT == MVT::f128)
3096 return LowerF128Store(Op, DAG);
3097
3098 if (MemVT == MVT::i64) {
3099 // Custom handling for i64 stores: turn it into a bitcast and a
3100 // v2i32 store.
3101 SDValue Val = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::v2i32, Operand: St->getValue());
3102 SDValue Chain = DAG.getStore(
3103 Chain: St->getChain(), dl, Val, Ptr: St->getBasePtr(), PtrInfo: St->getPointerInfo(),
3104 Alignment: St->getBaseAlign(), MMOFlags: St->getMemOperand()->getFlags(), AAInfo: St->getAAInfo());
3105 return Chain;
3106 }
3107
3108 return SDValue();
3109}
3110
3111static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
3112 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
3113 && "invalid opcode");
3114
3115 SDLoc dl(Op);
3116
3117 if (Op.getValueType() == MVT::f64)
3118 return LowerF64Op(SrcReg64: Op.getOperand(i: 0), dl, DAG, opcode: Op.getOpcode());
3119 if (Op.getValueType() != MVT::f128)
3120 return Op;
3121
3122 // Lower fabs/fneg on f128 to fabs/fneg on f64
3123 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
3124 // (As with LowerF64Op, on little-endian, we need to negate the odd
3125 // subreg)
3126
3127 SDValue SrcReg128 = Op.getOperand(i: 0);
3128 SDValue Hi64 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_even64, DL: dl, VT: MVT::f64,
3129 Operand: SrcReg128);
3130 SDValue Lo64 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_odd64, DL: dl, VT: MVT::f64,
3131 Operand: SrcReg128);
3132
3133 if (DAG.getDataLayout().isLittleEndian()) {
3134 if (isV9)
3135 Lo64 = DAG.getNode(Opcode: Op.getOpcode(), DL: dl, VT: MVT::f64, Operand: Lo64);
3136 else
3137 Lo64 = LowerF64Op(SrcReg64: Lo64, dl, DAG, opcode: Op.getOpcode());
3138 } else {
3139 if (isV9)
3140 Hi64 = DAG.getNode(Opcode: Op.getOpcode(), DL: dl, VT: MVT::f64, Operand: Hi64);
3141 else
3142 Hi64 = LowerF64Op(SrcReg64: Hi64, dl, DAG, opcode: Op.getOpcode());
3143 }
3144
3145 SDValue DstReg128 = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
3146 dl, VT: MVT::f128), 0);
3147 DstReg128 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_even64, DL: dl, VT: MVT::f128,
3148 Operand: DstReg128, Subreg: Hi64);
3149 DstReg128 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_odd64, DL: dl, VT: MVT::f128,
3150 Operand: DstReg128, Subreg: Lo64);
3151 return DstReg128;
3152}
3153
3154static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
3155 if (isStrongerThanMonotonic(AO: cast<AtomicSDNode>(Val&: Op)->getSuccessOrdering())) {
3156 // Expand with a fence.
3157 return SDValue();
3158 }
3159
3160 // Monotonic load/stores are legal.
3161 return Op;
3162}
3163
3164SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
3165 SelectionDAG &DAG) const {
3166 unsigned IntNo = Op.getConstantOperandVal(i: 0);
3167 switch (IntNo) {
3168 default: return SDValue(); // Don't custom lower most intrinsics.
3169 case Intrinsic::thread_pointer: {
3170 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
3171 return DAG.getRegister(Reg: SP::G7, VT: PtrVT);
3172 }
3173 }
3174}
3175
3176SDValue SparcTargetLowering::
3177LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3178
3179 bool hasHardQuad = Subtarget->hasHardQuad();
3180 bool isV9 = Subtarget->isV9();
3181 bool is64Bit = Subtarget->is64Bit();
3182
3183 switch (Op.getOpcode()) {
3184 default: llvm_unreachable("Should not custom lower this!");
3185
3186 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, TLI: *this,
3187 Subtarget);
3188 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
3189 Subtarget);
3190 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3191 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3192 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3193 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3194 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, TLI: *this,
3195 hasHardQuad);
3196 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, TLI: *this,
3197 hasHardQuad);
3198 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, TLI: *this,
3199 hasHardQuad);
3200 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, TLI: *this,
3201 hasHardQuad);
3202 case ISD::BR_CC:
3203 return LowerBR_CC(Op, DAG, TLI: *this, hasHardQuad, isV9, is64Bit);
3204 case ISD::SELECT_CC:
3205 return LowerSELECT_CC(Op, DAG, TLI: *this, hasHardQuad, isV9, is64Bit);
3206 case ISD::VASTART: return LowerVASTART(Op, DAG, TLI: *this);
3207 case ISD::VAARG: return LowerVAARG(Op, DAG);
3208 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
3209 Subtarget);
3210 case ISD::STACKADDRESS:
3211 return LowerSTACKADDRESS(Op, DAG, Subtarget: *Subtarget);
3212
3213 case ISD::BSWAP:
3214 return LowerBSWAP(Op, DAG);
3215
3216 case ISD::LOAD: return LowerLOAD(Op, DAG);
3217 case ISD::STORE: return LowerSTORE(Op, DAG);
3218 case ISD::FADD:
3219 return LowerF128Op(Op, DAG, LibFunc: RTLIB::ADD_F128, numArgs: 2);
3220 case ISD::FSUB:
3221 return LowerF128Op(Op, DAG, LibFunc: RTLIB::SUB_F128, numArgs: 2);
3222 case ISD::FMUL:
3223 return LowerF128Op(Op, DAG, LibFunc: RTLIB::MUL_F128, numArgs: 2);
3224 case ISD::FDIV:
3225 return LowerF128Op(Op, DAG, LibFunc: RTLIB::DIV_F128, numArgs: 2);
3226 case ISD::FSQRT:
3227 return LowerF128Op(Op, DAG, LibFunc: RTLIB::SQRT_F128, numArgs: 1);
3228 case ISD::FABS:
3229 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
3230 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, TLI: *this);
3231 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, TLI: *this);
3232 case ISD::ATOMIC_LOAD:
3233 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
3234 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3235 }
3236}
3237
3238SDValue SparcTargetLowering::bitcastConstantFPToInt(ConstantFPSDNode *C,
3239 const SDLoc &DL,
3240 SelectionDAG &DAG) const {
3241 APInt V = C->getValueAPF().bitcastToAPInt();
3242 SDValue Lo = DAG.getConstant(Val: V.zextOrTrunc(width: 32), DL, VT: MVT::i32);
3243 SDValue Hi = DAG.getConstant(Val: V.lshr(shiftAmt: 32).zextOrTrunc(width: 32), DL, VT: MVT::i32);
3244 if (DAG.getDataLayout().isLittleEndian())
3245 std::swap(a&: Lo, b&: Hi);
3246 return DAG.getBuildVector(VT: MVT::v2i32, DL, Ops: {Hi, Lo});
3247}
3248
3249SDValue SparcTargetLowering::PerformBITCASTCombine(SDNode *N,
3250 DAGCombinerInfo &DCI) const {
3251 SDLoc dl(N);
3252 SDValue Src = N->getOperand(Num: 0);
3253
3254 if (isa<ConstantFPSDNode>(Val: Src) && N->getSimpleValueType(ResNo: 0) == MVT::v2i32 &&
3255 Src.getSimpleValueType() == MVT::f64)
3256 return bitcastConstantFPToInt(C: cast<ConstantFPSDNode>(Val&: Src), DL: dl, DAG&: DCI.DAG);
3257
3258 return SDValue();
3259}
3260
3261SDValue SparcTargetLowering::PerformBSWAPCombine(SDNode *N,
3262 DAGCombinerInfo &DCI) const {
3263 SDLoc DL(N);
3264 SelectionDAG &DAG = DCI.DAG;
3265 SDValue Op = N->getOperand(Num: 0);
3266 EVT VT = N->getValueType(ResNo: 0);
3267 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
3268
3269 // Turn BSWAP (LOAD) -> ld*a #ASI_P(_L) on V9.
3270 if (Subtarget->isV9() && ISD::isNormalLoad(N: Op.getNode()) &&
3271 Op.getNode()->hasOneUse() &&
3272 (VT == MVT::i16 || VT == MVT::i32 ||
3273 (Subtarget->is64Bit() && VT == MVT::i64))) {
3274 SDValue Load = Op;
3275 auto *LD = cast<LoadSDNode>(Val&: Load);
3276
3277 // Create the byte-swapping load.
3278 SDValue Ops[] = {LD->getChain(), LD->getBasePtr(), DAG.getValueType(VT)};
3279
3280 SDValue BSLoad = DAG.getMemIntrinsicNode(
3281 Opcode: IsLittleEndian ? SPISD::LOAD_BIG : SPISD::LOAD_LITTLE, dl: DL,
3282 VTList: DAG.getVTList(VT1: VT == MVT::i64 ? MVT::i64 : MVT::i32, VT2: MVT::Other), Ops,
3283 MemVT: LD->getMemoryVT(), MMO: LD->getMemOperand());
3284
3285 // If this is an i16 load, insert the truncate.
3286 SDValue ResVal = BSLoad;
3287 if (VT == MVT::i16)
3288 ResVal = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i16, Operand: BSLoad);
3289
3290 return DCI.CombineTo(N, Res: ResVal);
3291 }
3292
3293 return SDValue();
3294}
3295
3296SDValue SparcTargetLowering::PerformSTORECombine(SDNode *N,
3297 DAGCombinerInfo &DCI) const {
3298 SDLoc DL(N);
3299 SelectionDAG &DAG = DCI.DAG;
3300 SDValue Op = N->getOperand(Num: 1);
3301 EVT VT = Op.getValueType();
3302 unsigned Opcode = Op.getOpcode();
3303 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
3304
3305 // Turn STORE (BSWAP) -> st*a #ASI_P(_L) on V9.
3306 if (Subtarget->isV9() && Opcode == ISD::BSWAP && Op.getNode()->hasOneUse() &&
3307 (VT == MVT::i16 || VT == MVT::i32 ||
3308 (Subtarget->is64Bit() && VT == MVT::i64))) {
3309
3310 // st*a can only handle simple types and it makes no sense to store less
3311 // than two bytes in byte-reversed order.
3312 EVT MemVT = cast<StoreSDNode>(Val: N)->getMemoryVT();
3313 if (MemVT.getSizeInBits() < 16)
3314 return SDValue();
3315
3316 SDValue BSwapOp = Op.getOperand(i: 0);
3317 // Do an any-extend to 32-bits if this is a half-word input.
3318 if (BSwapOp.getValueType() == MVT::i16)
3319 BSwapOp = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i32, Operand: BSwapOp);
3320
3321 // If the type of BSWAP operand is wider than stored memory width
3322 // it needs to be shifted to the right side before st*a.
3323 if (VT.bitsGT(VT: MemVT)) {
3324 unsigned Shift = VT.getSizeInBits() - MemVT.getSizeInBits();
3325 BSwapOp = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: BSwapOp,
3326 N2: DAG.getShiftAmountConstant(Val: Shift, VT, DL));
3327 }
3328
3329 SDValue Ops[] = {N->getOperand(Num: 0), BSwapOp, N->getOperand(Num: 2),
3330 DAG.getValueType(MemVT)};
3331 return DAG.getMemIntrinsicNode(
3332 Opcode: IsLittleEndian ? SPISD::STORE_BIG : SPISD::STORE_LITTLE, dl: DL,
3333 VTList: DAG.getVTList(VT: MVT::Other), Ops, MemVT: cast<StoreSDNode>(Val: N)->getMemoryVT(),
3334 MMO: cast<StoreSDNode>(Val: N)->getMemOperand());
3335 }
3336
3337 return SDValue();
3338}
3339
3340SDValue SparcTargetLowering::PerformDAGCombine(SDNode *N,
3341 DAGCombinerInfo &DCI) const {
3342 switch (N->getOpcode()) {
3343 default:
3344 break;
3345 case ISD::BITCAST:
3346 return PerformBITCASTCombine(N, DCI);
3347 case ISD::BSWAP:
3348 return PerformBSWAPCombine(N, DCI);
3349 case ISD::STORE:
3350 return PerformSTORECombine(N, DCI);
3351 }
3352 return SDValue();
3353}
3354
3355MachineBasicBlock *
3356SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3357 MachineBasicBlock *BB) const {
3358 switch (MI.getOpcode()) {
3359 default: llvm_unreachable("Unknown SELECT_CC!");
3360 case SP::SELECT_CC_Int_ICC:
3361 case SP::SELECT_CC_FP_ICC:
3362 case SP::SELECT_CC_DFP_ICC:
3363 case SP::SELECT_CC_QFP_ICC:
3364 if (Subtarget->isV9())
3365 return expandSelectCC(MI, BB, BROpcode: SP::BPICC);
3366 return expandSelectCC(MI, BB, BROpcode: SP::BCOND);
3367 case SP::SELECT_CC_Int_XCC:
3368 case SP::SELECT_CC_FP_XCC:
3369 case SP::SELECT_CC_DFP_XCC:
3370 case SP::SELECT_CC_QFP_XCC:
3371 return expandSelectCC(MI, BB, BROpcode: SP::BPXCC);
3372 case SP::SELECT_CC_Int_FCC:
3373 case SP::SELECT_CC_FP_FCC:
3374 case SP::SELECT_CC_DFP_FCC:
3375 case SP::SELECT_CC_QFP_FCC:
3376 if (Subtarget->isV9())
3377 return expandSelectCC(MI, BB, BROpcode: SP::FBCOND_V9);
3378 return expandSelectCC(MI, BB, BROpcode: SP::FBCOND);
3379 }
3380}
3381
3382MachineBasicBlock *
3383SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
3384 unsigned BROpcode) const {
3385 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
3386 DebugLoc dl = MI.getDebugLoc();
3387 unsigned CC = (SPCC::CondCodes)MI.getOperand(i: 3).getImm();
3388
3389 // To "insert" a SELECT_CC instruction, we actually have to insert the
3390 // triangle control-flow pattern. The incoming instruction knows the
3391 // destination vreg to set, the condition code register to branch on, the
3392 // true/false values to select between, and the condition code for the branch.
3393 //
3394 // We produce the following control flow:
3395 // ThisMBB
3396 // | \
3397 // | IfFalseMBB
3398 // | /
3399 // SinkMBB
3400 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3401 MachineFunction::iterator It = ++BB->getIterator();
3402
3403 MachineBasicBlock *ThisMBB = BB;
3404 MachineFunction *F = BB->getParent();
3405 MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
3406 MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
3407 F->insert(MBBI: It, MBB: IfFalseMBB);
3408 F->insert(MBBI: It, MBB: SinkMBB);
3409
3410 // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
3411 SinkMBB->splice(Where: SinkMBB->begin(), Other: ThisMBB,
3412 From: std::next(x: MachineBasicBlock::iterator(MI)), To: ThisMBB->end());
3413 SinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: ThisMBB);
3414
3415 // Set the new successors for ThisMBB.
3416 ThisMBB->addSuccessor(Succ: IfFalseMBB);
3417 ThisMBB->addSuccessor(Succ: SinkMBB);
3418
3419 BuildMI(BB: ThisMBB, MIMD: dl, MCID: TII.get(Opcode: BROpcode))
3420 .addMBB(MBB: SinkMBB)
3421 .addImm(Val: CC);
3422
3423 // IfFalseMBB just falls through to SinkMBB.
3424 IfFalseMBB->addSuccessor(Succ: SinkMBB);
3425
3426 // %Result = phi [ %TrueValue, ThisMBB ], [ %FalseValue, IfFalseMBB ]
3427 BuildMI(BB&: *SinkMBB, I: SinkMBB->begin(), MIMD: dl, MCID: TII.get(Opcode: SP::PHI),
3428 DestReg: MI.getOperand(i: 0).getReg())
3429 .addReg(RegNo: MI.getOperand(i: 1).getReg())
3430 .addMBB(MBB: ThisMBB)
3431 .addReg(RegNo: MI.getOperand(i: 2).getReg())
3432 .addMBB(MBB: IfFalseMBB);
3433
3434 MI.eraseFromParent(); // The pseudo instruction is gone now.
3435 return SinkMBB;
3436}
3437
3438//===----------------------------------------------------------------------===//
3439// Sparc Inline Assembly Support
3440//===----------------------------------------------------------------------===//
3441
3442/// getConstraintType - Given a constraint letter, return the type of
3443/// constraint it is for this target.
3444SparcTargetLowering::ConstraintType
3445SparcTargetLowering::getConstraintType(StringRef Constraint) const {
3446 if (Constraint.size() == 1) {
3447 switch (Constraint[0]) {
3448 default: break;
3449 case 'r':
3450 case 'f':
3451 case 'e':
3452 return C_RegisterClass;
3453 case 'I': // SIMM13
3454 return C_Immediate;
3455 }
3456 }
3457
3458 return TargetLowering::getConstraintType(Constraint);
3459}
3460
3461TargetLowering::ConstraintWeight SparcTargetLowering::
3462getSingleConstraintMatchWeight(AsmOperandInfo &info,
3463 const char *constraint) const {
3464 ConstraintWeight weight = CW_Invalid;
3465 Value *CallOperandVal = info.CallOperandVal;
3466 // If we don't have a value, we can't do a match,
3467 // but allow it at the lowest weight.
3468 if (!CallOperandVal)
3469 return CW_Default;
3470
3471 // Look at the constraint type.
3472 switch (*constraint) {
3473 default:
3474 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3475 break;
3476 case 'I': // SIMM13
3477 if (ConstantInt *C = dyn_cast<ConstantInt>(Val: info.CallOperandVal)) {
3478 if (isInt<13>(x: C->getSExtValue()))
3479 weight = CW_Constant;
3480 }
3481 break;
3482 }
3483 return weight;
3484}
3485
3486/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3487/// vector. If it is invalid, don't add anything to Ops.
3488void SparcTargetLowering::LowerAsmOperandForConstraint(
3489 SDValue Op, StringRef Constraint, std::vector<SDValue> &Ops,
3490 SelectionDAG &DAG) const {
3491 SDValue Result;
3492
3493 // Only support length 1 constraints for now.
3494 if (Constraint.size() > 1)
3495 return;
3496
3497 char ConstraintLetter = Constraint[0];
3498 switch (ConstraintLetter) {
3499 default: break;
3500 case 'I':
3501 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
3502 if (isInt<13>(x: C->getSExtValue())) {
3503 Result = DAG.getSignedTargetConstant(Val: C->getSExtValue(), DL: SDLoc(Op),
3504 VT: Op.getValueType());
3505 break;
3506 }
3507 return;
3508 }
3509 }
3510
3511 if (Result.getNode()) {
3512 Ops.push_back(x: Result);
3513 return;
3514 }
3515 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3516}
3517
3518std::pair<unsigned, const TargetRegisterClass *>
3519SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3520 StringRef Constraint,
3521 MVT VT) const {
3522 if (Constraint.empty())
3523 return std::make_pair(x: 0U, y: nullptr);
3524
3525 if (Constraint.size() == 1) {
3526 switch (Constraint[0]) {
3527 case 'r':
3528 if (VT == MVT::v2i32)
3529 return std::make_pair(x: 0U, y: &SP::IntPairRegClass);
3530 else if (Subtarget->is64Bit())
3531 return std::make_pair(x: 0U, y: &SP::I64RegsRegClass);
3532 else
3533 return std::make_pair(x: 0U, y: &SP::IntRegsRegClass);
3534 case 'f':
3535 if (VT == MVT::f32 || VT == MVT::i32)
3536 return std::make_pair(x: 0U, y: &SP::FPRegsRegClass);
3537 else if (VT == MVT::f64 || VT == MVT::i64)
3538 return std::make_pair(x: 0U, y: &SP::LowDFPRegsRegClass);
3539 else if (VT == MVT::f128)
3540 return std::make_pair(x: 0U, y: &SP::LowQFPRegsRegClass);
3541 // This will generate an error message
3542 return std::make_pair(x: 0U, y: nullptr);
3543 case 'e':
3544 if (VT == MVT::f32 || VT == MVT::i32)
3545 return std::make_pair(x: 0U, y: &SP::FPRegsRegClass);
3546 else if (VT == MVT::f64 || VT == MVT::i64 )
3547 return std::make_pair(x: 0U, y: &SP::DFPRegsRegClass);
3548 else if (VT == MVT::f128)
3549 return std::make_pair(x: 0U, y: &SP::QFPRegsRegClass);
3550 // This will generate an error message
3551 return std::make_pair(x: 0U, y: nullptr);
3552 }
3553 }
3554
3555 if (Constraint.front() != '{')
3556 return std::make_pair(x: 0U, y: nullptr);
3557
3558 assert(Constraint.back() == '}' && "Not a brace enclosed constraint?");
3559 StringRef RegName(Constraint.data() + 1, Constraint.size() - 2);
3560 if (RegName.empty())
3561 return std::make_pair(x: 0U, y: nullptr);
3562
3563 unsigned long long RegNo;
3564 // Handle numbered register aliases.
3565 if (RegName[0] == 'r' &&
3566 getAsUnsignedInteger(Str: RegName.begin() + 1, Radix: 10, Result&: RegNo)) {
3567 // r0-r7 -> g0-g7
3568 // r8-r15 -> o0-o7
3569 // r16-r23 -> l0-l7
3570 // r24-r31 -> i0-i7
3571 if (RegNo > 31)
3572 return std::make_pair(x: 0U, y: nullptr);
3573 const char RegTypes[] = {'g', 'o', 'l', 'i'};
3574 char RegType = RegTypes[RegNo / 8];
3575 char RegIndex = '0' + (RegNo % 8);
3576 char Tmp[] = {'{', RegType, RegIndex, '}', 0};
3577 return getRegForInlineAsmConstraint(TRI, Constraint: Tmp, VT);
3578 }
3579
3580 // Rewrite the fN constraint according to the value type if needed.
3581 if (VT != MVT::f32 && VT != MVT::Other && RegName[0] == 'f' &&
3582 getAsUnsignedInteger(Str: RegName.begin() + 1, Radix: 10, Result&: RegNo)) {
3583 if (VT == MVT::f64 && (RegNo % 2 == 0)) {
3584 return getRegForInlineAsmConstraint(
3585 TRI, Constraint: StringRef("{d" + utostr(X: RegNo / 2) + "}"), VT);
3586 } else if (VT == MVT::f128 && (RegNo % 4 == 0)) {
3587 return getRegForInlineAsmConstraint(
3588 TRI, Constraint: StringRef("{q" + utostr(X: RegNo / 4) + "}"), VT);
3589 } else {
3590 return std::make_pair(x: 0U, y: nullptr);
3591 }
3592 }
3593
3594 auto ResultPair =
3595 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3596 if (!ResultPair.second)
3597 return std::make_pair(x: 0U, y: nullptr);
3598
3599 // Force the use of I64Regs over IntRegs for 64-bit values.
3600 if (Subtarget->is64Bit() && VT == MVT::i64) {
3601 assert(ResultPair.second == &SP::IntRegsRegClass &&
3602 "Unexpected register class");
3603 return std::make_pair(x&: ResultPair.first, y: &SP::I64RegsRegClass);
3604 }
3605
3606 return ResultPair;
3607}
3608
3609bool
3610SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3611 // The Sparc target isn't yet aware of offsets.
3612 return false;
3613}
3614
3615void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3616 SmallVectorImpl<SDValue>& Results,
3617 SelectionDAG &DAG) const {
3618
3619 SDLoc dl(N);
3620
3621 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3622
3623 switch (N->getOpcode()) {
3624 default:
3625 llvm_unreachable("Do not know how to custom type legalize this operation!");
3626
3627 case ISD::FP_TO_SINT:
3628 case ISD::FP_TO_UINT:
3629 // Custom lower only if it involves f128 or i64.
3630 if (N->getOperand(Num: 0).getValueType() != MVT::f128
3631 || N->getValueType(ResNo: 0) != MVT::i64)
3632 return;
3633 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3634 ? RTLIB::FPTOSINT_F128_I64
3635 : RTLIB::FPTOUINT_F128_I64);
3636
3637 Results.push_back(Elt: LowerF128Op(Op: SDValue(N, 0), DAG, LibFunc: libCall, numArgs: 1));
3638 return;
3639 case ISD::READCYCLECOUNTER: {
3640 assert(Subtarget->hasLeonCycleCounter());
3641 SDValue Lo = DAG.getCopyFromReg(Chain: N->getOperand(Num: 0), dl, Reg: SP::ASR23, VT: MVT::i32);
3642 SDValue Hi = DAG.getCopyFromReg(Chain: Lo, dl, Reg: SP::G0, VT: MVT::i32);
3643 SDValue Ops[] = { Lo, Hi };
3644 SDValue Pair = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, Ops);
3645 Results.push_back(Elt: Pair);
3646 Results.push_back(Elt: N->getOperand(Num: 0));
3647 return;
3648 }
3649 case ISD::SINT_TO_FP:
3650 case ISD::UINT_TO_FP:
3651 // Custom lower only if it involves f128 or i64.
3652 if (N->getValueType(ResNo: 0) != MVT::f128
3653 || N->getOperand(Num: 0).getValueType() != MVT::i64)
3654 return;
3655
3656 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3657 ? RTLIB::SINTTOFP_I64_F128
3658 : RTLIB::UINTTOFP_I64_F128);
3659
3660 Results.push_back(Elt: LowerF128Op(Op: SDValue(N, 0), DAG, LibFunc: libCall, numArgs: 1));
3661 return;
3662 case ISD::LOAD: {
3663 LoadSDNode *Ld = cast<LoadSDNode>(Val: N);
3664 // Custom handling only for i64: turn i64 load into a v2i32 load,
3665 // and a bitcast.
3666 if (Ld->getValueType(ResNo: 0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64)
3667 return;
3668
3669 SDLoc dl(N);
3670 SDValue LoadRes = DAG.getExtLoad(
3671 ExtType: Ld->getExtensionType(), dl, VT: MVT::v2i32, Chain: Ld->getChain(),
3672 Ptr: Ld->getBasePtr(), PtrInfo: Ld->getPointerInfo(), MemVT: MVT::v2i32, Alignment: Ld->getBaseAlign(),
3673 MMOFlags: Ld->getMemOperand()->getFlags(), AAInfo: Ld->getAAInfo());
3674
3675 SDValue Res = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i64, Operand: LoadRes);
3676 Results.push_back(Elt: Res);
3677 Results.push_back(Elt: LoadRes.getValue(R: 1));
3678 return;
3679 }
3680 }
3681}
3682
3683// Override to enable LOAD_STACK_GUARD lowering on Linux.
3684bool SparcTargetLowering::useLoadStackGuardNode(const Module &M) const {
3685 if (!Subtarget->getTargetTriple().isOSLinux())
3686 return TargetLowering::useLoadStackGuardNode(M);
3687 return true;
3688}
3689
3690bool SparcTargetLowering::isFNegFree(EVT VT) const {
3691 if (Subtarget->isVIS3())
3692 return VT == MVT::f32 || VT == MVT::f64;
3693 return false;
3694}
3695
3696bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
3697 bool ForCodeSize) const {
3698 if (VT != MVT::f32 && VT != MVT::f64)
3699 return false;
3700 if (Subtarget->isVIS() && Imm.isZero())
3701 return true;
3702 if (Subtarget->isVIS3())
3703 return Imm.isExactlyValue(V: +0.5) || Imm.isExactlyValue(V: -0.5) ||
3704 Imm.getExactLog2Abs() == -1;
3705 return false;
3706}
3707
3708bool SparcTargetLowering::isCtlzFast() const { return Subtarget->isVIS3(); }
3709
3710bool SparcTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
3711 // We lack native cttz, however,
3712 // On 64-bit targets it is cheap to implement it in terms of popc.
3713 if (Subtarget->is64Bit() && Subtarget->usePopc())
3714 return true;
3715 // Otherwise, implementing cttz in terms of ctlz is still cheap.
3716 return isCheapToSpeculateCtlz(Ty);
3717}
3718
3719bool SparcTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
3720 EVT VT) const {
3721 return Subtarget->isUA2007() && !Subtarget->useSoftFloat();
3722}
3723
3724void SparcTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
3725 SDNode *Node) const {
3726 assert(MI.getOpcode() == SP::SUBCCrr || MI.getOpcode() == SP::SUBCCri);
3727 // If the result is dead, replace it with %g0.
3728 if (!Node->hasAnyUseOfValue(Value: 0))
3729 MI.getOperand(i: 0).setReg(SP::G0);
3730}
3731
3732Instruction *SparcTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
3733 Instruction *Inst,
3734 AtomicOrdering Ord) const {
3735 bool HasStoreSemantics =
3736 isa<AtomicCmpXchgInst, AtomicRMWInst, StoreInst>(Val: Inst);
3737 if (HasStoreSemantics && isReleaseOrStronger(AO: Ord))
3738 return Builder.CreateFence(Ordering: AtomicOrdering::Release);
3739 return nullptr;
3740}
3741
3742Instruction *SparcTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
3743 Instruction *Inst,
3744 AtomicOrdering Ord) const {
3745 // V8 loads already come with implicit acquire barrier so there's no need to
3746 // emit it again.
3747 bool HasLoadSemantics = isa<AtomicCmpXchgInst, AtomicRMWInst, LoadInst>(Val: Inst);
3748 if (Subtarget->isV9() && HasLoadSemantics && isAcquireOrStronger(AO: Ord))
3749 return Builder.CreateFence(Ordering: AtomicOrdering::Acquire);
3750
3751 // SC plain stores would need a trailing full barrier.
3752 if (isa<StoreInst>(Val: Inst) && Ord == AtomicOrdering::SequentiallyConsistent)
3753 return Builder.CreateFence(Ordering: Ord);
3754 return nullptr;
3755}
3756