1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the interfaces that Sparc uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcISelLowering.h"
15#include "MCTargetDesc/SparcMCTargetDesc.h"
16#include "SparcMachineFunctionInfo.h"
17#include "SparcRegisterInfo.h"
18#include "SparcSelectionDAGInfo.h"
19#include "SparcTargetMachine.h"
20#include "SparcTargetObjectFile.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/ADT/StringSwitch.h"
23#include "llvm/BinaryFormat/ELF.h"
24#include "llvm/CodeGen/CallingConvLower.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/SelectionDAG.h"
30#include "llvm/CodeGen/SelectionDAGNodes.h"
31#include "llvm/CodeGen/TargetLowering.h"
32#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
33#include "llvm/IR/DerivedTypes.h"
34#include "llvm/IR/DiagnosticInfo.h"
35#include "llvm/IR/Function.h"
36#include "llvm/IR/IRBuilder.h"
37#include "llvm/IR/Module.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/KnownBits.h"
40using namespace llvm;
41
42
43//===----------------------------------------------------------------------===//
44// Calling Convention Implementation
45//===----------------------------------------------------------------------===//
46
47static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
48 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
49 ISD::ArgFlagsTy &ArgFlags, CCState &State)
50{
51 assert (ArgFlags.isSRet());
52
53 // Assign SRet argument.
54 State.addLoc(V: CCValAssign::getCustomMem(ValNo, ValVT,
55 Offset: 0,
56 LocVT, HTP: LocInfo));
57 return true;
58}
59
60static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT,
61 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
62 ISD::ArgFlagsTy &ArgFlags, CCState &State)
63{
64 static const MCPhysReg RegList[] = {
65 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
66 };
67 // Try to get first reg.
68 if (Register Reg = State.AllocateReg(Regs: RegList)) {
69 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
70 } else {
71 // Assign whole thing in stack.
72 State.addLoc(V: CCValAssign::getCustomMem(
73 ValNo, ValVT, Offset: State.AllocateStack(Size: 8, Alignment: Align(4)), LocVT, HTP: LocInfo));
74 return true;
75 }
76
77 // Try to get second reg.
78 if (Register Reg = State.AllocateReg(Regs: RegList))
79 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
80 else
81 State.addLoc(V: CCValAssign::getCustomMem(
82 ValNo, ValVT, Offset: State.AllocateStack(Size: 4, Alignment: Align(4)), LocVT, HTP: LocInfo));
83 return true;
84}
85
86static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT,
87 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
88 ISD::ArgFlagsTy &ArgFlags, CCState &State)
89{
90 static const MCPhysReg RegList[] = {
91 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
92 };
93
94 // Try to get first reg.
95 if (Register Reg = State.AllocateReg(Regs: RegList))
96 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
97 else
98 return false;
99
100 // Try to get second reg.
101 if (Register Reg = State.AllocateReg(Regs: RegList))
102 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
103 else
104 return false;
105
106 return true;
107}
108
109// Allocate a full-sized argument for the 64-bit ABI.
110static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT,
111 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
112 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
113 assert((LocVT == MVT::f32 || LocVT == MVT::f128
114 || LocVT.getSizeInBits() == 64) &&
115 "Can't handle non-64 bits locations");
116
117 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
118 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
119 Align alignment =
120 (LocVT == MVT::f128 || ArgFlags.isSplit()) ? Align(16) : Align(8);
121 unsigned Offset = State.AllocateStack(Size: size, Alignment: alignment);
122 unsigned Reg = 0;
123
124 if (LocVT == MVT::i64 && Offset < 6*8)
125 // Promote integers to %i0-%i5.
126 Reg = SP::I0 + Offset/8;
127 else if (LocVT == MVT::f64 && Offset < 16*8)
128 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
129 Reg = SP::D0 + Offset/8;
130 else if (LocVT == MVT::f32 && Offset < 16*8)
131 // Promote floats to %f1, %f3, ...
132 Reg = SP::F1 + Offset/4;
133 else if (LocVT == MVT::f128 && Offset < 16*8)
134 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
135 Reg = SP::Q0 + Offset/16;
136
137 // Promote to register when possible, otherwise use the stack slot.
138 if (Reg) {
139 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
140 return true;
141 }
142
143 // Bail out if this is a return CC and we run out of registers to place
144 // values into.
145 if (IsReturn)
146 return false;
147
148 // This argument goes on the stack in an 8-byte slot.
149 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
150 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
151 if (LocVT == MVT::f32)
152 Offset += 4;
153
154 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, HTP: LocInfo));
155 return true;
156}
157
158// Allocate a half-sized argument for the 64-bit ABI.
159//
160// This is used when passing { float, int } structs by value in registers.
161static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT,
162 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
163 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
164 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
165 unsigned Offset = State.AllocateStack(Size: 4, Alignment: Align(4));
166
167 if (LocVT == MVT::f32 && Offset < 16*8) {
168 // Promote floats to %f0-%f31.
169 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg: SP::F0 + Offset/4,
170 LocVT, HTP: LocInfo));
171 return true;
172 }
173
174 if (LocVT == MVT::i32 && Offset < 6*8) {
175 // Promote integers to %i0-%i5, using half the register.
176 unsigned Reg = SP::I0 + Offset/8;
177 LocVT = MVT::i64;
178 LocInfo = CCValAssign::AExt;
179
180 // Set the Custom bit if this i32 goes in the high bits of a register.
181 if (Offset % 8 == 0)
182 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg,
183 LocVT, HTP: LocInfo));
184 else
185 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
186 return true;
187 }
188
189 // Bail out if this is a return CC and we run out of registers to place
190 // values into.
191 if (IsReturn)
192 return false;
193
194 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, HTP: LocInfo));
195 return true;
196}
197
198static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
199 CCValAssign::LocInfo &LocInfo,
200 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
201 return Analyze_CC_Sparc64_Full(IsReturn: false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
202 State);
203}
204
205static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
206 CCValAssign::LocInfo &LocInfo,
207 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
208 return Analyze_CC_Sparc64_Half(IsReturn: false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
209 State);
210}
211
212static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
213 CCValAssign::LocInfo &LocInfo,
214 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
215 return Analyze_CC_Sparc64_Full(IsReturn: true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
216 State);
217}
218
219static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
220 CCValAssign::LocInfo &LocInfo,
221 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
222 return Analyze_CC_Sparc64_Half(IsReturn: true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
223 State);
224}
225
226#include "SparcGenCallingConv.inc"
227
228// The calling conventions in SparcCallingConv.td are described in terms of the
229// callee's register window. This function translates registers to the
230// corresponding caller window %o register.
231static unsigned toCallerWindow(unsigned Reg) {
232 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
233 "Unexpected enum");
234 if (Reg >= SP::I0 && Reg <= SP::I7)
235 return Reg - SP::I0 + SP::O0;
236 return Reg;
237}
238
239bool SparcTargetLowering::CanLowerReturn(
240 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
241 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
242 const Type *RetTy) const {
243 SmallVector<CCValAssign, 16> RVLocs;
244 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
245 return CCInfo.CheckReturn(Outs, Fn: Subtarget->is64Bit() ? RetCC_Sparc64
246 : RetCC_Sparc32);
247}
248
249SDValue
250SparcTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
251 bool IsVarArg,
252 const SmallVectorImpl<ISD::OutputArg> &Outs,
253 const SmallVectorImpl<SDValue> &OutVals,
254 const SDLoc &DL, SelectionDAG &DAG) const {
255 if (Subtarget->is64Bit())
256 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
257 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
258}
259
260SDValue
261SparcTargetLowering::LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
262 bool IsVarArg,
263 const SmallVectorImpl<ISD::OutputArg> &Outs,
264 const SmallVectorImpl<SDValue> &OutVals,
265 const SDLoc &DL, SelectionDAG &DAG) const {
266 MachineFunction &MF = DAG.getMachineFunction();
267
268 // CCValAssign - represent the assignment of the return value to locations.
269 SmallVector<CCValAssign, 16> RVLocs;
270
271 // CCState - Info about the registers and stack slot.
272 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
273 *DAG.getContext());
274
275 // Analyze return values.
276 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_Sparc32);
277
278 SDValue Glue;
279 SmallVector<SDValue, 4> RetOps(1, Chain);
280 // Make room for the return address offset.
281 RetOps.push_back(Elt: SDValue());
282
283 // Copy the result values into the output registers.
284 for (unsigned i = 0, realRVLocIdx = 0;
285 i != RVLocs.size();
286 ++i, ++realRVLocIdx) {
287 CCValAssign &VA = RVLocs[i];
288 assert(VA.isRegLoc() && "Can only return in registers!");
289
290 SDValue Arg = OutVals[realRVLocIdx];
291
292 if (VA.needsCustom()) {
293 assert(VA.getLocVT() == MVT::v2i32);
294 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
295 // happen by default if this wasn't a legal type)
296
297 SDValue Part0 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32,
298 N1: Arg,
299 N2: DAG.getConstant(Val: 0, DL, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
300 SDValue Part1 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32,
301 N1: Arg,
302 N2: DAG.getConstant(Val: 1, DL, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
303
304 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Part0, Glue);
305 Glue = Chain.getValue(R: 1);
306 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
307 VA = RVLocs[++i]; // skip ahead to next loc
308 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Part1,
309 Glue);
310 } else
311 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Arg, Glue);
312
313 // Guarantee that all emitted copies are stuck together with flags.
314 Glue = Chain.getValue(R: 1);
315 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
316 }
317
318 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
319 // If the function returns a struct, copy the SRetReturnReg to I0
320 if (MF.getFunction().hasStructRetAttr()) {
321 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
322 Register Reg = SFI->getSRetReturnReg();
323 if (!Reg)
324 llvm_unreachable("sret virtual register not created in the entry block");
325 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
326 SDValue Val = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: PtrVT);
327 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SP::I0, N: Val, Glue);
328 Glue = Chain.getValue(R: 1);
329 RetOps.push_back(Elt: DAG.getRegister(Reg: SP::I0, VT: PtrVT));
330 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
331 }
332
333 RetOps[0] = Chain; // Update chain.
334 RetOps[1] = DAG.getConstant(Val: RetAddrOffset, DL, VT: MVT::i32);
335
336 // Add the glue if we have it.
337 if (Glue.getNode())
338 RetOps.push_back(Elt: Glue);
339
340 return DAG.getNode(Opcode: SPISD::RET_GLUE, DL, VT: MVT::Other, Ops: RetOps);
341}
342
343// Lower return values for the 64-bit ABI.
344// Return values are passed the exactly the same way as function arguments.
345SDValue
346SparcTargetLowering::LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
347 bool IsVarArg,
348 const SmallVectorImpl<ISD::OutputArg> &Outs,
349 const SmallVectorImpl<SDValue> &OutVals,
350 const SDLoc &DL, SelectionDAG &DAG) const {
351 // CCValAssign - represent the assignment of the return value to locations.
352 SmallVector<CCValAssign, 16> RVLocs;
353
354 // CCState - Info about the registers and stack slot.
355 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
356 *DAG.getContext());
357
358 // Analyze return values.
359 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_Sparc64);
360
361 SDValue Glue;
362 SmallVector<SDValue, 4> RetOps(1, Chain);
363
364 // The second operand on the return instruction is the return address offset.
365 // The return address is always %i7+8 with the 64-bit ABI.
366 RetOps.push_back(Elt: DAG.getConstant(Val: 8, DL, VT: MVT::i32));
367
368 // Copy the result values into the output registers.
369 for (unsigned i = 0; i != RVLocs.size(); ++i) {
370 CCValAssign &VA = RVLocs[i];
371 assert(VA.isRegLoc() && "Can only return in registers!");
372 SDValue OutVal = OutVals[i];
373
374 // Integer return values must be sign or zero extended by the callee.
375 switch (VA.getLocInfo()) {
376 case CCValAssign::Full: break;
377 case CCValAssign::SExt:
378 OutVal = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
379 break;
380 case CCValAssign::ZExt:
381 OutVal = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
382 break;
383 case CCValAssign::AExt:
384 OutVal = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
385 break;
386 default:
387 llvm_unreachable("Unknown loc info!");
388 }
389
390 // The custom bit on an i32 return value indicates that it should be passed
391 // in the high bits of the register.
392 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
393 OutVal = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: OutVal,
394 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
395
396 // The next value may go in the low bits of the same register.
397 // Handle both at once.
398 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
399 SDValue NV = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i64, Operand: OutVals[i+1]);
400 OutVal = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i64, N1: OutVal, N2: NV);
401 // Skip the next value, it's already done.
402 ++i;
403 }
404 }
405
406 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: OutVal, Glue);
407
408 // Guarantee that all emitted copies are stuck together with flags.
409 Glue = Chain.getValue(R: 1);
410 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
411 }
412
413 RetOps[0] = Chain; // Update chain.
414
415 // Add the flag if we have it.
416 if (Glue.getNode())
417 RetOps.push_back(Elt: Glue);
418
419 return DAG.getNode(Opcode: SPISD::RET_GLUE, DL, VT: MVT::Other, Ops: RetOps);
420}
421
422SDValue SparcTargetLowering::LowerFormalArguments(
423 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
424 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
425 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
426 if (Subtarget->is64Bit())
427 return LowerFormalArguments_64(Chain, CallConv, isVarArg: IsVarArg, Ins,
428 dl: DL, DAG, InVals);
429 return LowerFormalArguments_32(Chain, CallConv, isVarArg: IsVarArg, Ins,
430 dl: DL, DAG, InVals);
431}
432
433/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
434/// passed in either one or two GPRs, including FP values. TODO: we should
435/// pass FP values in FP registers for fastcc functions.
436SDValue SparcTargetLowering::LowerFormalArguments_32(
437 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
438 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
439 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
440 MachineFunction &MF = DAG.getMachineFunction();
441 MachineRegisterInfo &RegInfo = MF.getRegInfo();
442 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
443 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
444
445 // Assign locations to all of the incoming arguments.
446 SmallVector<CCValAssign, 16> ArgLocs;
447 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
448 *DAG.getContext());
449 CCInfo.AnalyzeFormalArguments(Ins, Fn: CC_Sparc32);
450
451 const unsigned StackOffset = 92;
452 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
453
454 unsigned InIdx = 0;
455 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
456 CCValAssign &VA = ArgLocs[i];
457 EVT LocVT = VA.getLocVT();
458
459 if (Ins[InIdx].Flags.isSRet()) {
460 if (InIdx != 0)
461 report_fatal_error(reason: "sparc only supports sret on the first parameter");
462 // Get SRet from [%fp+64].
463 int FrameIdx = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: 64, IsImmutable: true);
464 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
465 SDValue Arg =
466 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
467 InVals.push_back(Elt: Arg);
468 continue;
469 }
470
471 SDValue Arg;
472 if (VA.isRegLoc()) {
473 if (VA.needsCustom()) {
474 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
475
476 Register VRegHi = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
477 MF.getRegInfo().addLiveIn(Reg: VA.getLocReg(), vreg: VRegHi);
478 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, Reg: VRegHi, VT: MVT::i32);
479
480 assert(i+1 < e);
481 CCValAssign &NextVA = ArgLocs[++i];
482
483 SDValue LoVal;
484 if (NextVA.isMemLoc()) {
485 int FrameIdx = MF.getFrameInfo().
486 CreateFixedObject(Size: 4, SPOffset: StackOffset+NextVA.getLocMemOffset(),IsImmutable: true);
487 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
488 LoVal = DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
489 } else {
490 Register loReg = MF.addLiveIn(PReg: NextVA.getLocReg(),
491 RC: &SP::IntRegsRegClass);
492 LoVal = DAG.getCopyFromReg(Chain, dl, Reg: loReg, VT: MVT::i32);
493 }
494
495 if (IsLittleEndian)
496 std::swap(a&: LoVal, b&: HiVal);
497
498 SDValue WholeValue =
499 DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: LoVal, N2: HiVal);
500 WholeValue = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getLocVT(), Operand: WholeValue);
501 InVals.push_back(Elt: WholeValue);
502 continue;
503 }
504 Register VReg = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
505 MF.getRegInfo().addLiveIn(Reg: VA.getLocReg(), vreg: VReg);
506 Arg = DAG.getCopyFromReg(Chain, dl, Reg: VReg, VT: MVT::i32);
507 if (VA.getLocInfo() != CCValAssign::Indirect) {
508 if (VA.getLocVT() == MVT::f32)
509 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::f32, Operand: Arg);
510 else if (VA.getLocVT() != MVT::i32) {
511 Arg = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: MVT::i32, N1: Arg,
512 N2: DAG.getValueType(VA.getLocVT()));
513 Arg = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getLocVT(), Operand: Arg);
514 }
515 InVals.push_back(Elt: Arg);
516 continue;
517 }
518 } else {
519 assert(VA.isMemLoc());
520
521 unsigned Offset = VA.getLocMemOffset() + StackOffset;
522
523 if (VA.needsCustom()) {
524 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
525 // If it is double-word aligned, just load.
526 if (Offset % 8 == 0) {
527 int FI = MF.getFrameInfo().CreateFixedObject(Size: 8, SPOffset: Offset, IsImmutable: true);
528 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
529 SDValue Load = DAG.getLoad(VT: VA.getValVT(), dl, Chain, Ptr: FIPtr,
530 PtrInfo: MachinePointerInfo());
531 InVals.push_back(Elt: Load);
532 continue;
533 }
534
535 int FI = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: Offset, IsImmutable: true);
536 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
537 SDValue HiVal =
538 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
539 int FI2 = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: Offset + 4, IsImmutable: true);
540 SDValue FIPtr2 = DAG.getFrameIndex(FI: FI2, VT: PtrVT);
541
542 SDValue LoVal =
543 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr2, PtrInfo: MachinePointerInfo());
544
545 if (IsLittleEndian)
546 std::swap(a&: LoVal, b&: HiVal);
547
548 SDValue WholeValue =
549 DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: LoVal, N2: HiVal);
550 WholeValue = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getValVT(), Operand: WholeValue);
551 InVals.push_back(Elt: WholeValue);
552 continue;
553 }
554
555 int FI = MF.getFrameInfo().CreateFixedObject(Size: LocVT.getSizeInBits() / 8,
556 SPOffset: Offset, IsImmutable: true);
557 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
558 SDValue Load = DAG.getLoad(VT: LocVT, dl, Chain, Ptr: FIPtr,
559 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI));
560 if (VA.getLocInfo() != CCValAssign::Indirect) {
561 InVals.push_back(Elt: Load);
562 continue;
563 }
564 Arg = Load;
565 }
566
567 assert(VA.getLocInfo() == CCValAssign::Indirect);
568
569 SDValue ArgValue =
570 DAG.getLoad(VT: VA.getValVT(), dl, Chain, Ptr: Arg, PtrInfo: MachinePointerInfo());
571 InVals.push_back(Elt: ArgValue);
572
573 unsigned ArgIndex = Ins[InIdx].OrigArgIndex;
574 assert(Ins[InIdx].PartOffset == 0);
575 while (i + 1 != e && Ins[InIdx + 1].OrigArgIndex == ArgIndex) {
576 CCValAssign &PartVA = ArgLocs[i + 1];
577 unsigned PartOffset = Ins[InIdx + 1].PartOffset;
578 SDValue Address = DAG.getMemBasePlusOffset(
579 Base: ArgValue, Offset: TypeSize::getFixed(ExactSize: PartOffset), DL: dl);
580 InVals.push_back(Elt: DAG.getLoad(VT: PartVA.getValVT(), dl, Chain, Ptr: Address,
581 PtrInfo: MachinePointerInfo()));
582 ++i;
583 ++InIdx;
584 }
585 }
586
587 if (MF.getFunction().hasStructRetAttr()) {
588 // Copy the SRet Argument to SRetReturnReg.
589 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
590 Register Reg = SFI->getSRetReturnReg();
591 if (!Reg) {
592 Reg = MF.getRegInfo().createVirtualRegister(RegClass: &SP::IntRegsRegClass);
593 SFI->setSRetReturnReg(Reg);
594 }
595 SDValue Copy = DAG.getCopyToReg(Chain: DAG.getEntryNode(), dl, Reg, N: InVals[0]);
596 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Copy, N2: Chain);
597 }
598
599 // Store remaining ArgRegs to the stack if this is a varargs function.
600 if (isVarArg) {
601 static const MCPhysReg ArgRegs[] = {
602 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
603 };
604 unsigned NumAllocated = CCInfo.getFirstUnallocated(Regs: ArgRegs);
605 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
606 unsigned ArgOffset = CCInfo.getStackSize();
607 if (NumAllocated == 6)
608 ArgOffset += StackOffset;
609 else {
610 assert(!ArgOffset);
611 ArgOffset = 68+4*NumAllocated;
612 }
613
614 // Remember the vararg offset for the va_start implementation.
615 FuncInfo->setVarArgsFrameOffset(ArgOffset);
616
617 std::vector<SDValue> OutChains;
618
619 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
620 Register VReg = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
621 MF.getRegInfo().addLiveIn(Reg: *CurArgReg, vreg: VReg);
622 SDValue Arg = DAG.getCopyFromReg(Chain: DAG.getRoot(), dl, Reg: VReg, VT: MVT::i32);
623
624 int FrameIdx = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: ArgOffset,
625 IsImmutable: true);
626 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
627
628 OutChains.push_back(
629 x: DAG.getStore(Chain: DAG.getRoot(), dl, Val: Arg, Ptr: FIPtr, PtrInfo: MachinePointerInfo()));
630 ArgOffset += 4;
631 }
632
633 if (!OutChains.empty()) {
634 OutChains.push_back(x: Chain);
635 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
636 }
637 }
638
639 return Chain;
640}
641
642// Lower formal arguments for the 64 bit ABI.
643SDValue SparcTargetLowering::LowerFormalArguments_64(
644 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
645 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
646 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
647 MachineFunction &MF = DAG.getMachineFunction();
648
649 // Analyze arguments according to CC_Sparc64.
650 SmallVector<CCValAssign, 16> ArgLocs;
651 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
652 *DAG.getContext());
653 CCInfo.AnalyzeFormalArguments(Ins, Fn: CC_Sparc64);
654
655 // The argument array begins at %fp+BIAS+128, after the register save area.
656 const unsigned ArgArea = 128;
657
658 for (const CCValAssign &VA : ArgLocs) {
659 if (VA.isRegLoc()) {
660 // This argument is passed in a register.
661 // All integer register arguments are promoted by the caller to i64.
662
663 // Create a virtual register for the promoted live-in value.
664 Register VReg = MF.addLiveIn(PReg: VA.getLocReg(),
665 RC: getRegClassFor(VT: VA.getLocVT()));
666 SDValue Arg = DAG.getCopyFromReg(Chain, dl: DL, Reg: VReg, VT: VA.getLocVT());
667
668 // Get the high bits for i32 struct elements.
669 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
670 Arg = DAG.getNode(Opcode: ISD::SRL, DL, VT: VA.getLocVT(), N1: Arg,
671 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
672
673 // The caller promoted the argument, so insert an Assert?ext SDNode so we
674 // won't promote the value again in this function.
675 switch (VA.getLocInfo()) {
676 case CCValAssign::SExt:
677 Arg = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: Arg,
678 N2: DAG.getValueType(VA.getValVT()));
679 break;
680 case CCValAssign::ZExt:
681 Arg = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: Arg,
682 N2: DAG.getValueType(VA.getValVT()));
683 break;
684 default:
685 break;
686 }
687
688 // Truncate the register down to the argument type.
689 if (VA.isExtInLoc())
690 Arg = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: Arg);
691
692 InVals.push_back(Elt: Arg);
693 continue;
694 }
695
696 // The registers are exhausted. This argument was passed on the stack.
697 assert(VA.isMemLoc());
698 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
699 // beginning of the arguments area at %fp+BIAS+128.
700 unsigned Offset = VA.getLocMemOffset() + ArgArea;
701 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
702 // Adjust offset for extended arguments, SPARC is big-endian.
703 // The caller will have written the full slot with extended bytes, but we
704 // prefer our own extending loads.
705 if (VA.isExtInLoc())
706 Offset += 8 - ValSize;
707 int FI = MF.getFrameInfo().CreateFixedObject(Size: ValSize, SPOffset: Offset, IsImmutable: true);
708 InVals.push_back(
709 Elt: DAG.getLoad(VT: VA.getValVT(), dl: DL, Chain,
710 Ptr: DAG.getFrameIndex(FI, VT: getPointerTy(DL: MF.getDataLayout())),
711 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
712 }
713
714 if (!IsVarArg)
715 return Chain;
716
717 // This function takes variable arguments, some of which may have been passed
718 // in registers %i0-%i5. Variable floating point arguments are never passed
719 // in floating point registers. They go on %i0-%i5 or on the stack like
720 // integer arguments.
721 //
722 // The va_start intrinsic needs to know the offset to the first variable
723 // argument.
724 unsigned ArgOffset = CCInfo.getStackSize();
725 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
726 // Skip the 128 bytes of register save area.
727 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
728 Subtarget->getStackPointerBias());
729
730 // Save the variable arguments that were passed in registers.
731 // The caller is required to reserve stack space for 6 arguments regardless
732 // of how many arguments were actually passed.
733 SmallVector<SDValue, 8> OutChains;
734 for (; ArgOffset < 6*8; ArgOffset += 8) {
735 Register VReg = MF.addLiveIn(PReg: SP::I0 + ArgOffset/8, RC: &SP::I64RegsRegClass);
736 SDValue VArg = DAG.getCopyFromReg(Chain, dl: DL, Reg: VReg, VT: MVT::i64);
737 int FI = MF.getFrameInfo().CreateFixedObject(Size: 8, SPOffset: ArgOffset + ArgArea, IsImmutable: true);
738 auto PtrVT = getPointerTy(DL: MF.getDataLayout());
739 OutChains.push_back(
740 Elt: DAG.getStore(Chain, dl: DL, Val: VArg, Ptr: DAG.getFrameIndex(FI, VT: PtrVT),
741 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
742 }
743
744 if (!OutChains.empty())
745 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: OutChains);
746
747 return Chain;
748}
749
750// Check whether any of the argument registers are reserved
751static bool isAnyArgRegReserved(const SparcRegisterInfo *TRI,
752 const MachineFunction &MF) {
753 // The register window design means that outgoing parameters at O*
754 // will appear in the callee as I*.
755 // Be conservative and check both sides of the register names.
756 bool Outgoing =
757 llvm::any_of(Range: SP::GPROutgoingArgRegClass, P: [TRI, &MF](MCPhysReg r) {
758 return TRI->isReservedReg(MF, Reg: r);
759 });
760 bool Incoming =
761 llvm::any_of(Range: SP::GPRIncomingArgRegClass, P: [TRI, &MF](MCPhysReg r) {
762 return TRI->isReservedReg(MF, Reg: r);
763 });
764 return Outgoing || Incoming;
765}
766
767static void emitReservedArgRegCallError(const MachineFunction &MF) {
768 const Function &F = MF.getFunction();
769 F.getContext().diagnose(DI: DiagnosticInfoUnsupported{
770 F, ("SPARC doesn't support"
771 " function calls if any of the argument registers is reserved.")});
772}
773
774SDValue
775SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
776 SmallVectorImpl<SDValue> &InVals) const {
777 if (Subtarget->is64Bit())
778 return LowerCall_64(CLI, InVals);
779 return LowerCall_32(CLI, InVals);
780}
781
782static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
783 const CallBase *Call) {
784 if (Call)
785 return Call->hasFnAttr(Kind: Attribute::ReturnsTwice);
786
787 const Function *CalleeFn = nullptr;
788 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
789 CalleeFn = dyn_cast<Function>(Val: G->getGlobal());
790 } else if (ExternalSymbolSDNode *E =
791 dyn_cast<ExternalSymbolSDNode>(Val&: Callee)) {
792 const Function &Fn = DAG.getMachineFunction().getFunction();
793 const Module *M = Fn.getParent();
794 const char *CalleeName = E->getSymbol();
795 CalleeFn = M->getFunction(Name: CalleeName);
796 }
797
798 if (!CalleeFn)
799 return false;
800 return CalleeFn->hasFnAttribute(Kind: Attribute::ReturnsTwice);
801}
802
803/// IsEligibleForTailCallOptimization - Check whether the call is eligible
804/// for tail call optimization.
805bool SparcTargetLowering::IsEligibleForTailCallOptimization(
806 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const {
807
808 auto &Outs = CLI.Outs;
809 auto &Caller = MF.getFunction();
810
811 // Do not tail call opt functions with "disable-tail-calls" attribute.
812 if (Caller.getFnAttribute(Kind: "disable-tail-calls").getValueAsString() == "true")
813 return false;
814
815 // Do not tail call opt if the stack is used to pass parameters.
816 // 64-bit targets have a slightly higher limit since the ABI requires
817 // to allocate some space even when all the parameters fit inside registers.
818 unsigned StackSizeLimit = Subtarget->is64Bit() ? 48 : 0;
819 if (CCInfo.getStackSize() > StackSizeLimit)
820 return false;
821
822 // Do not tail call opt if either the callee or caller returns
823 // a struct and the other does not.
824 if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
825 return false;
826
827 // Byval parameters hand the function a pointer directly into the stack area
828 // we want to reuse during a tail call.
829 for (auto &Arg : Outs)
830 if (Arg.Flags.isByVal())
831 return false;
832
833 return true;
834}
835
836// Lower a call for the 32-bit ABI.
837SDValue
838SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
839 SmallVectorImpl<SDValue> &InVals) const {
840 SelectionDAG &DAG = CLI.DAG;
841 SDLoc &dl = CLI.DL;
842 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
843 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
844 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
845 SDValue Chain = CLI.Chain;
846 SDValue Callee = CLI.Callee;
847 bool &isTailCall = CLI.IsTailCall;
848 CallingConv::ID CallConv = CLI.CallConv;
849 bool isVarArg = CLI.IsVarArg;
850 MachineFunction &MF = DAG.getMachineFunction();
851 LLVMContext &Ctx = *DAG.getContext();
852 EVT PtrVT = getPointerTy(DL: MF.getDataLayout());
853
854 // Analyze operands of the call, assigning locations to each operand.
855 SmallVector<CCValAssign, 16> ArgLocs;
856 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
857 *DAG.getContext());
858 CCInfo.AnalyzeCallOperands(Outs, Fn: CC_Sparc32);
859
860 isTailCall = isTailCall && IsEligibleForTailCallOptimization(
861 CCInfo, CLI, MF&: DAG.getMachineFunction());
862
863 // Get the size of the outgoing arguments stack space requirement.
864 unsigned ArgsSize = CCInfo.getStackSize();
865
866 // Keep stack frames 8-byte aligned.
867 ArgsSize = (ArgsSize+7) & ~7;
868
869 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
870
871 // Create local copies for byval args.
872 SmallVector<SDValue, 8> ByValArgs;
873 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
874 ISD::ArgFlagsTy Flags = Outs[i].Flags;
875 if (!Flags.isByVal())
876 continue;
877
878 SDValue Arg = OutVals[i];
879 unsigned Size = Flags.getByValSize();
880 Align Alignment = Flags.getNonZeroByValAlign();
881
882 if (Size > 0U) {
883 int FI = MFI.CreateStackObject(Size, Alignment, isSpillSlot: false);
884 SDValue FIPtr = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
885 SDValue SizeNode = DAG.getConstant(Val: Size, DL: dl, VT: MVT::i32);
886
887 Chain = DAG.getMemcpy(Chain, dl, Dst: FIPtr, Src: Arg, Size: SizeNode, Alignment,
888 isVol: false, // isVolatile,
889 AlwaysInline: (Size <= 32), // AlwaysInline if size <= 32,
890 /*CI=*/nullptr, OverrideTailCall: std::nullopt, DstPtrInfo: MachinePointerInfo(),
891 SrcPtrInfo: MachinePointerInfo());
892 ByValArgs.push_back(Elt: FIPtr);
893 }
894 else {
895 SDValue nullVal;
896 ByValArgs.push_back(Elt: nullVal);
897 }
898 }
899
900 assert(!isTailCall || ArgsSize == 0);
901
902 if (!isTailCall)
903 Chain = DAG.getCALLSEQ_START(Chain, InSize: ArgsSize, OutSize: 0, DL: dl);
904
905 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
906 SmallVector<SDValue, 8> MemOpChains;
907
908 const unsigned StackOffset = 92;
909 bool hasStructRetAttr = false;
910 unsigned SRetArgSize = 0;
911 // Walk the register/memloc assignments, inserting copies/loads.
912 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
913 i != e;
914 ++i, ++realArgIdx) {
915 CCValAssign &VA = ArgLocs[i];
916 SDValue Arg = OutVals[realArgIdx];
917
918 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
919
920 // Use local copy if it is a byval arg.
921 if (Flags.isByVal()) {
922 Arg = ByValArgs[byvalArgIdx++];
923 if (!Arg) {
924 continue;
925 }
926 }
927
928 // Promote the value if needed.
929 switch (VA.getLocInfo()) {
930 default: llvm_unreachable("Unknown loc info!");
931 case CCValAssign::Full:
932 case CCValAssign::Indirect:
933 break;
934 case CCValAssign::SExt:
935 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
936 break;
937 case CCValAssign::ZExt:
938 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
939 break;
940 case CCValAssign::AExt:
941 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
942 break;
943 case CCValAssign::BCvt:
944 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getLocVT(), Operand: Arg);
945 break;
946 }
947
948 if (Flags.isSRet()) {
949 assert(VA.needsCustom());
950
951 if (isTailCall)
952 continue;
953
954 // store SRet argument in %sp+64
955 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
956 SDValue PtrOff = DAG.getIntPtrConstant(Val: 64, DL: dl);
957 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
958 MemOpChains.push_back(
959 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
960 hasStructRetAttr = true;
961 // sret only allowed on first argument
962 assert(Outs[realArgIdx].OrigArgIndex == 0);
963 SRetArgSize =
964 DAG.getDataLayout().getTypeAllocSize(Ty: CLI.getArgs()[0].IndirectType);
965 continue;
966 }
967
968 if (VA.needsCustom()) {
969 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
970
971 if (VA.isMemLoc()) {
972 unsigned Offset = VA.getLocMemOffset() + StackOffset;
973 // if it is double-word aligned, just store.
974 if (Offset % 8 == 0) {
975 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
976 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
977 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
978 MemOpChains.push_back(
979 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
980 continue;
981 }
982 }
983
984 if (VA.getLocVT() == MVT::f64) {
985 // Move from the float value from float registers into the
986 // integer registers.
987 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val&: Arg))
988 Arg = bitcastConstantFPToInt(C, DL: dl, DAG);
989 else
990 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::v2i32, Operand: Arg);
991 }
992
993 SDValue Part0 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: MVT::i32,
994 N1: Arg,
995 N2: DAG.getConstant(Val: 0, DL: dl, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
996 SDValue Part1 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: MVT::i32,
997 N1: Arg,
998 N2: DAG.getConstant(Val: 1, DL: dl, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
999
1000 if (VA.isRegLoc()) {
1001 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Part0));
1002 assert(i+1 != e);
1003 CCValAssign &NextVA = ArgLocs[++i];
1004 if (NextVA.isRegLoc()) {
1005 RegsToPass.push_back(Elt: std::make_pair(x: NextVA.getLocReg(), y&: Part1));
1006 } else {
1007 // Store the second part in stack.
1008 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
1009 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1010 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
1011 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1012 MemOpChains.push_back(
1013 Elt: DAG.getStore(Chain, dl, Val: Part1, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1014 }
1015 } else {
1016 unsigned Offset = VA.getLocMemOffset() + StackOffset;
1017 // Store the first part.
1018 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1019 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
1020 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1021 MemOpChains.push_back(
1022 Elt: DAG.getStore(Chain, dl, Val: Part0, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1023 // Store the second part.
1024 PtrOff = DAG.getIntPtrConstant(Val: Offset + 4, DL: dl);
1025 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1026 MemOpChains.push_back(
1027 Elt: DAG.getStore(Chain, dl, Val: Part1, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1028 }
1029 continue;
1030 }
1031
1032 if (VA.getLocInfo() == CCValAssign::Indirect) {
1033 // Store the argument in a stack slot and pass its address.
1034 unsigned ArgIndex = Outs[realArgIdx].OrigArgIndex;
1035 assert(Outs[realArgIdx].PartOffset == 0);
1036
1037 EVT SlotVT;
1038 if (i + 1 != e && Outs[realArgIdx + 1].OrigArgIndex == ArgIndex) {
1039 Type *OrigArgType = CLI.Args[ArgIndex].Ty;
1040 EVT OrigArgVT = getValueType(DL: MF.getDataLayout(), Ty: OrigArgType);
1041 MVT PartVT =
1042 getRegisterTypeForCallingConv(Context&: Ctx, CC: CLI.CallConv, VT: OrigArgVT);
1043 unsigned N =
1044 getNumRegistersForCallingConv(Context&: Ctx, CC: CLI.CallConv, VT: OrigArgVT);
1045 SlotVT = EVT::getIntegerVT(Context&: Ctx, BitWidth: PartVT.getSizeInBits() * N);
1046 } else {
1047 SlotVT = Outs[realArgIdx].VT;
1048 }
1049
1050 SDValue SpillSlot = DAG.CreateStackTemporary(VT: SlotVT);
1051 int FI = cast<FrameIndexSDNode>(Val&: SpillSlot)->getIndex();
1052 MemOpChains.push_back(
1053 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: SpillSlot,
1054 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
1055 // If the original argument was split (e.g. f128), we need
1056 // to store all parts of it here (and pass just one address).
1057 while (i + 1 != e && Outs[realArgIdx + 1].OrigArgIndex == ArgIndex) {
1058 SDValue PartValue = OutVals[realArgIdx + 1];
1059 unsigned PartOffset = Outs[realArgIdx + 1].PartOffset;
1060 SDValue Address = DAG.getMemBasePlusOffset(
1061 Base: DAG.getFrameIndex(FI, VT: PtrVT), Offset: TypeSize::getFixed(ExactSize: PartOffset), DL: dl);
1062 MemOpChains.push_back(
1063 Elt: DAG.getStore(Chain, dl, Val: PartValue, Ptr: Address,
1064 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
1065 assert((PartOffset + PartValue.getValueType().getStoreSize() <=
1066 SlotVT.getStoreSize()) &&
1067 "Not enough space for argument part!");
1068 ++i;
1069 ++realArgIdx;
1070 }
1071
1072 Arg = SpillSlot;
1073 }
1074
1075 // Arguments that can be passed on register must be kept at
1076 // RegsToPass vector
1077 if (VA.isRegLoc()) {
1078 if (VA.getLocVT() != MVT::f32) {
1079 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1080 continue;
1081 }
1082 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: Arg);
1083 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1084 continue;
1085 }
1086
1087 assert(VA.isMemLoc());
1088
1089 // Create a store off the stack pointer for this argument.
1090 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1091 SDValue PtrOff = DAG.getIntPtrConstant(Val: VA.getLocMemOffset() + StackOffset,
1092 DL: dl);
1093 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1094 MemOpChains.push_back(
1095 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1096 }
1097
1098
1099 // Emit all stores, make sure the occur before any copies into physregs.
1100 if (!MemOpChains.empty())
1101 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains);
1102
1103 // Build a sequence of copy-to-reg nodes chained together with token
1104 // chain and flag operands which copy the outgoing args into registers.
1105 // The InGlue in necessary since all emitted instructions must be
1106 // stuck together.
1107 SDValue InGlue;
1108 for (const auto &[OrigReg, N] : RegsToPass) {
1109 Register Reg = isTailCall ? OrigReg : toCallerWindow(Reg: OrigReg);
1110 Chain = DAG.getCopyToReg(Chain, dl, Reg, N, Glue: InGlue);
1111 InGlue = Chain.getValue(R: 1);
1112 }
1113
1114 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, Call: CLI.CB);
1115
1116 // If the callee is a GlobalAddress node (quite common, every direct call is)
1117 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1118 // Likewise ExternalSymbol -> TargetExternalSymbol.
1119 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
1120 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL: dl, VT: MVT::i32, offset: 0);
1121 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee))
1122 Callee = DAG.getTargetExternalSymbol(Sym: E->getSymbol(), VT: MVT::i32);
1123
1124 // Returns a chain & a flag for retval copy to use
1125 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1126 SmallVector<SDValue, 8> Ops;
1127 Ops.push_back(Elt: Chain);
1128 Ops.push_back(Elt: Callee);
1129 if (hasStructRetAttr)
1130 Ops.push_back(Elt: DAG.getTargetConstant(Val: SRetArgSize, DL: dl, VT: MVT::i32));
1131 for (const auto &[OrigReg, N] : RegsToPass) {
1132 Register Reg = isTailCall ? OrigReg : toCallerWindow(Reg: OrigReg);
1133 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
1134 }
1135
1136 // Add a register mask operand representing the call-preserved registers.
1137 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1138 const uint32_t *Mask =
1139 ((hasReturnsTwice)
1140 ? TRI->getRTCallPreservedMask(CC: CallConv)
1141 : TRI->getCallPreservedMask(MF: DAG.getMachineFunction(), CC: CallConv));
1142
1143 if (isAnyArgRegReserved(TRI, MF))
1144 emitReservedArgRegCallError(MF);
1145
1146 assert(Mask && "Missing call preserved mask for calling convention");
1147 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
1148
1149 if (InGlue.getNode())
1150 Ops.push_back(Elt: InGlue);
1151
1152 if (isTailCall) {
1153 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
1154 return DAG.getNode(Opcode: SPISD::TAIL_CALL, DL: dl, VT: MVT::Other, Ops);
1155 }
1156
1157 Chain = DAG.getNode(Opcode: SPISD::CALL, DL: dl, VTList: NodeTys, Ops);
1158 InGlue = Chain.getValue(R: 1);
1159
1160 Chain = DAG.getCALLSEQ_END(Chain, Size1: ArgsSize, Size2: 0, Glue: InGlue, DL: dl);
1161 InGlue = Chain.getValue(R: 1);
1162
1163 // Assign locations to each value returned by this call.
1164 SmallVector<CCValAssign, 16> RVLocs;
1165 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1166 *DAG.getContext());
1167
1168 RVInfo.AnalyzeCallResult(Ins, Fn: RetCC_Sparc32);
1169
1170 // Copy all of the result registers out of their specified physreg.
1171 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1172 assert(RVLocs[i].isRegLoc() && "Can only return in registers!");
1173 if (RVLocs[i].getLocVT() == MVT::v2i32) {
1174 SDValue Vec = DAG.getNode(Opcode: ISD::UNDEF, DL: dl, VT: MVT::v2i32);
1175 SDValue Lo = DAG.getCopyFromReg(
1176 Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i++].getLocReg()), VT: MVT::i32, Glue: InGlue);
1177 Chain = Lo.getValue(R: 1);
1178 InGlue = Lo.getValue(R: 2);
1179 Vec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: MVT::v2i32, N1: Vec, N2: Lo,
1180 N3: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
1181 SDValue Hi = DAG.getCopyFromReg(
1182 Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i].getLocReg()), VT: MVT::i32, Glue: InGlue);
1183 Chain = Hi.getValue(R: 1);
1184 InGlue = Hi.getValue(R: 2);
1185 Vec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: MVT::v2i32, N1: Vec, N2: Hi,
1186 N3: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i32));
1187 InVals.push_back(Elt: Vec);
1188 } else {
1189 Chain =
1190 DAG.getCopyFromReg(Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i].getLocReg()),
1191 VT: RVLocs[i].getValVT(), Glue: InGlue)
1192 .getValue(R: 1);
1193 InGlue = Chain.getValue(R: 2);
1194 InVals.push_back(Elt: Chain.getValue(R: 0));
1195 }
1196 }
1197
1198 return Chain;
1199}
1200
1201// FIXME? Maybe this could be a TableGen attribute on some registers and
1202// this table could be generated automatically from RegInfo.
1203Register SparcTargetLowering::getRegisterByName(const char* RegName, LLT VT,
1204 const MachineFunction &MF) const {
1205 Register Reg = StringSwitch<Register>(RegName)
1206 .Case(S: "i0", Value: SP::I0).Case(S: "i1", Value: SP::I1).Case(S: "i2", Value: SP::I2).Case(S: "i3", Value: SP::I3)
1207 .Case(S: "i4", Value: SP::I4).Case(S: "i5", Value: SP::I5).Case(S: "i6", Value: SP::I6).Case(S: "i7", Value: SP::I7)
1208 .Case(S: "o0", Value: SP::O0).Case(S: "o1", Value: SP::O1).Case(S: "o2", Value: SP::O2).Case(S: "o3", Value: SP::O3)
1209 .Case(S: "o4", Value: SP::O4).Case(S: "o5", Value: SP::O5).Case(S: "o6", Value: SP::O6).Case(S: "o7", Value: SP::O7)
1210 .Case(S: "l0", Value: SP::L0).Case(S: "l1", Value: SP::L1).Case(S: "l2", Value: SP::L2).Case(S: "l3", Value: SP::L3)
1211 .Case(S: "l4", Value: SP::L4).Case(S: "l5", Value: SP::L5).Case(S: "l6", Value: SP::L6).Case(S: "l7", Value: SP::L7)
1212 .Case(S: "g0", Value: SP::G0).Case(S: "g1", Value: SP::G1).Case(S: "g2", Value: SP::G2).Case(S: "g3", Value: SP::G3)
1213 .Case(S: "g4", Value: SP::G4).Case(S: "g5", Value: SP::G5).Case(S: "g6", Value: SP::G6).Case(S: "g7", Value: SP::G7)
1214 .Default(Value: 0);
1215
1216 // If we're directly referencing register names
1217 // (e.g in GCC C extension `register int r asm("g1");`),
1218 // make sure that said register is in the reserve list.
1219 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1220 if (!TRI->isReservedReg(MF, Reg))
1221 Reg = Register();
1222
1223 return Reg;
1224}
1225
1226// Fixup floating point arguments in the ... part of a varargs call.
1227//
1228// The SPARC v9 ABI requires that floating point arguments are treated the same
1229// as integers when calling a varargs function. This does not apply to the
1230// fixed arguments that are part of the function's prototype.
1231//
1232// This function post-processes a CCValAssign array created by
1233// AnalyzeCallOperands().
1234static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1235 ArrayRef<ISD::OutputArg> Outs) {
1236 for (CCValAssign &VA : ArgLocs) {
1237 MVT ValTy = VA.getLocVT();
1238 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1239 // varargs functions.
1240 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1241 continue;
1242 // The fixed arguments to a varargs function still go in FP registers.
1243 if (!Outs[VA.getValNo()].Flags.isVarArg())
1244 continue;
1245
1246 // This floating point argument should be reassigned.
1247 // Determine the offset into the argument array.
1248 Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1249 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1250 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1251 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1252
1253 if (Offset < 6*8) {
1254 // This argument should go in %i0-%i5.
1255 unsigned IReg = SP::I0 + Offset/8;
1256 if (ValTy == MVT::f64)
1257 // Full register, just bitconvert into i64.
1258 VA = CCValAssign::getReg(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Reg: IReg, LocVT: MVT::i64,
1259 HTP: CCValAssign::BCvt);
1260 else {
1261 assert(ValTy == MVT::f128 && "Unexpected type!");
1262 // Full register, just bitconvert into i128 -- We will lower this into
1263 // two i64s in LowerCall_64.
1264 VA = CCValAssign::getCustomReg(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Reg: IReg,
1265 LocVT: MVT::i128, HTP: CCValAssign::BCvt);
1266 }
1267 } else {
1268 // This needs to go to memory, we're out of integer registers.
1269 VA = CCValAssign::getMem(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Offset,
1270 LocVT: VA.getLocVT(), HTP: VA.getLocInfo());
1271 }
1272 }
1273}
1274
1275// Lower a call for the 64-bit ABI.
1276SDValue
1277SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1278 SmallVectorImpl<SDValue> &InVals) const {
1279 SelectionDAG &DAG = CLI.DAG;
1280 SDLoc DL = CLI.DL;
1281 SDValue Chain = CLI.Chain;
1282 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
1283 MachineFunction &MF = DAG.getMachineFunction();
1284
1285 // Analyze operands of the call, assigning locations to each operand.
1286 SmallVector<CCValAssign, 16> ArgLocs;
1287 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1288 *DAG.getContext());
1289 CCInfo.AnalyzeCallOperands(Outs: CLI.Outs, Fn: CC_Sparc64);
1290
1291 CLI.IsTailCall = CLI.IsTailCall && IsEligibleForTailCallOptimization(
1292 CCInfo, CLI, MF&: DAG.getMachineFunction());
1293
1294 // Get the size of the outgoing arguments stack space requirement.
1295 // The stack offset computed by CC_Sparc64 includes all arguments.
1296 // Called functions expect 6 argument words to exist in the stack frame, used
1297 // or not.
1298 unsigned StackReserved = 6 * 8u;
1299 unsigned ArgsSize = std::max<unsigned>(a: StackReserved, b: CCInfo.getStackSize());
1300
1301 // Keep stack frames 16-byte aligned.
1302 ArgsSize = alignTo(Value: ArgsSize, Align: 16);
1303
1304 // Varargs calls require special treatment.
1305 if (CLI.IsVarArg)
1306 fixupVariableFloatArgs(ArgLocs, Outs: CLI.Outs);
1307
1308 assert(!CLI.IsTailCall || ArgsSize == StackReserved);
1309
1310 // Adjust the stack pointer to make room for the arguments.
1311 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1312 // with more than 6 arguments.
1313 if (!CLI.IsTailCall)
1314 Chain = DAG.getCALLSEQ_START(Chain, InSize: ArgsSize, OutSize: 0, DL);
1315
1316 // Collect the set of registers to pass to the function and their values.
1317 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1318 // instruction.
1319 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
1320
1321 // Collect chains from all the memory opeations that copy arguments to the
1322 // stack. They must follow the stack pointer adjustment above and precede the
1323 // call instruction itself.
1324 SmallVector<SDValue, 8> MemOpChains;
1325
1326 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1327 const CCValAssign &VA = ArgLocs[i];
1328 SDValue Arg = CLI.OutVals[i];
1329
1330 // Promote the value if needed.
1331 switch (VA.getLocInfo()) {
1332 default:
1333 llvm_unreachable("Unknown location info!");
1334 case CCValAssign::Full:
1335 break;
1336 case CCValAssign::SExt:
1337 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1338 break;
1339 case CCValAssign::ZExt:
1340 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1341 break;
1342 case CCValAssign::AExt:
1343 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1344 break;
1345 case CCValAssign::BCvt:
1346 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1347 // SPARC does not support i128 natively. Lower it into two i64, see below.
1348 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1349 || VA.getLocVT() != MVT::i128)
1350 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: VA.getLocVT(), Operand: Arg);
1351 break;
1352 }
1353
1354 if (VA.isRegLoc()) {
1355 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1356 && VA.getLocVT() == MVT::i128) {
1357 // Store and reload into the integer register reg and reg+1.
1358 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1359 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1360 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: PtrVT);
1361 SDValue HiPtrOff = DAG.getIntPtrConstant(Val: StackOffset, DL);
1362 HiPtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: HiPtrOff);
1363 SDValue LoPtrOff = DAG.getIntPtrConstant(Val: StackOffset + 8, DL);
1364 LoPtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: LoPtrOff);
1365
1366 // Store to %sp+BIAS+128+Offset
1367 SDValue Store =
1368 DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: HiPtrOff, PtrInfo: MachinePointerInfo());
1369 // Load into Reg and Reg+1
1370 SDValue Hi64 =
1371 DAG.getLoad(VT: MVT::i64, dl: DL, Chain: Store, Ptr: HiPtrOff, PtrInfo: MachinePointerInfo());
1372 SDValue Lo64 =
1373 DAG.getLoad(VT: MVT::i64, dl: DL, Chain: Store, Ptr: LoPtrOff, PtrInfo: MachinePointerInfo());
1374
1375 Register HiReg = VA.getLocReg();
1376 Register LoReg = VA.getLocReg() + 1;
1377 if (!CLI.IsTailCall) {
1378 HiReg = toCallerWindow(Reg: HiReg);
1379 LoReg = toCallerWindow(Reg: LoReg);
1380 }
1381
1382 RegsToPass.push_back(Elt: std::make_pair(x&: HiReg, y&: Hi64));
1383 RegsToPass.push_back(Elt: std::make_pair(x&: LoReg, y&: Lo64));
1384 continue;
1385 }
1386
1387 // The custom bit on an i32 return value indicates that it should be
1388 // passed in the high bits of the register.
1389 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1390 Arg = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: Arg,
1391 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
1392
1393 // The next value may go in the low bits of the same register.
1394 // Handle both at once.
1395 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1396 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1397 SDValue NV = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i64,
1398 Operand: CLI.OutVals[i+1]);
1399 Arg = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i64, N1: Arg, N2: NV);
1400 // Skip the next value, it's already done.
1401 ++i;
1402 }
1403 }
1404
1405 Register Reg = VA.getLocReg();
1406 if (!CLI.IsTailCall)
1407 Reg = toCallerWindow(Reg);
1408 RegsToPass.push_back(Elt: std::make_pair(x&: Reg, y&: Arg));
1409 continue;
1410 }
1411
1412 assert(VA.isMemLoc());
1413
1414 // Create a store off the stack pointer for this argument.
1415 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: PtrVT);
1416 // The argument area starts at %fp+BIAS+128 in the callee frame,
1417 // %sp+BIAS+128 in ours.
1418 SDValue PtrOff = DAG.getIntPtrConstant(Val: VA.getLocMemOffset() +
1419 Subtarget->getStackPointerBias() +
1420 128, DL);
1421 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: PtrOff);
1422 MemOpChains.push_back(
1423 Elt: DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1424 }
1425
1426 // Emit all stores, make sure they occur before the call.
1427 if (!MemOpChains.empty())
1428 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOpChains);
1429
1430 // Build a sequence of CopyToReg nodes glued together with token chain and
1431 // glue operands which copy the outgoing args into registers. The InGlue is
1432 // necessary since all emitted instructions must be stuck together in order
1433 // to pass the live physical registers.
1434 SDValue InGlue;
1435 for (const auto &[Reg, N] : RegsToPass) {
1436 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg, N, Glue: InGlue);
1437 InGlue = Chain.getValue(R: 1);
1438 }
1439
1440 // If the callee is a GlobalAddress node (quite common, every direct call is)
1441 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1442 // Likewise ExternalSymbol -> TargetExternalSymbol.
1443 SDValue Callee = CLI.Callee;
1444 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, Call: CLI.CB);
1445 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
1446 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL, VT: PtrVT, offset: 0);
1447 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee))
1448 Callee = DAG.getTargetExternalSymbol(Sym: E->getSymbol(), VT: PtrVT);
1449
1450 // Build the operands for the call instruction itself.
1451 SmallVector<SDValue, 8> Ops;
1452 Ops.push_back(Elt: Chain);
1453 Ops.push_back(Elt: Callee);
1454 for (const auto &[Reg, N] : RegsToPass)
1455 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
1456
1457 // Add a register mask operand representing the call-preserved registers.
1458 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1459 const uint32_t *Mask =
1460 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CC: CLI.CallConv)
1461 : TRI->getCallPreservedMask(MF: DAG.getMachineFunction(),
1462 CC: CLI.CallConv));
1463
1464 if (isAnyArgRegReserved(TRI, MF))
1465 emitReservedArgRegCallError(MF);
1466
1467 assert(Mask && "Missing call preserved mask for calling convention");
1468 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
1469
1470 // Make sure the CopyToReg nodes are glued to the call instruction which
1471 // consumes the registers.
1472 if (InGlue.getNode())
1473 Ops.push_back(Elt: InGlue);
1474
1475 // Now the call itself.
1476 if (CLI.IsTailCall) {
1477 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
1478 return DAG.getNode(Opcode: SPISD::TAIL_CALL, DL, VT: MVT::Other, Ops);
1479 }
1480 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1481 Chain = DAG.getNode(Opcode: SPISD::CALL, DL, VTList: NodeTys, Ops);
1482 InGlue = Chain.getValue(R: 1);
1483
1484 // Revert the stack pointer immediately after the call.
1485 Chain = DAG.getCALLSEQ_END(Chain, Size1: ArgsSize, Size2: 0, Glue: InGlue, DL);
1486 InGlue = Chain.getValue(R: 1);
1487
1488 // Now extract the return values. This is more or less the same as
1489 // LowerFormalArguments_64.
1490
1491 // Assign locations to each value returned by this call.
1492 SmallVector<CCValAssign, 16> RVLocs;
1493 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1494 *DAG.getContext());
1495
1496 // Set inreg flag manually for codegen generated library calls that
1497 // return float.
1498 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB)
1499 CLI.Ins[0].Flags.setInReg();
1500
1501 RVInfo.AnalyzeCallResult(Ins: CLI.Ins, Fn: RetCC_Sparc64);
1502
1503 // Copy all of the result registers out of their specified physreg.
1504 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1505 CCValAssign &VA = RVLocs[i];
1506 assert(VA.isRegLoc() && "Can only return in registers!");
1507 unsigned Reg = toCallerWindow(Reg: VA.getLocReg());
1508
1509 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1510 // reside in the same register in the high and low bits. Reuse the
1511 // CopyFromReg previous node to avoid duplicate copies.
1512 SDValue RV;
1513 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Val: Chain.getOperand(i: 1)))
1514 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1515 RV = Chain.getValue(R: 0);
1516
1517 // But usually we'll create a new CopyFromReg for a different register.
1518 if (!RV.getNode()) {
1519 RV = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: RVLocs[i].getLocVT(), Glue: InGlue);
1520 Chain = RV.getValue(R: 1);
1521 InGlue = Chain.getValue(R: 2);
1522 }
1523
1524 // Get the high bits for i32 struct elements.
1525 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1526 RV = DAG.getNode(Opcode: ISD::SRL, DL, VT: VA.getLocVT(), N1: RV,
1527 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
1528
1529 // The callee promoted the return value, so insert an Assert?ext SDNode so
1530 // we won't promote the value again in this function.
1531 switch (VA.getLocInfo()) {
1532 case CCValAssign::SExt:
1533 RV = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: RV,
1534 N2: DAG.getValueType(VA.getValVT()));
1535 break;
1536 case CCValAssign::ZExt:
1537 RV = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: RV,
1538 N2: DAG.getValueType(VA.getValVT()));
1539 break;
1540 default:
1541 break;
1542 }
1543
1544 // Truncate the register down to the return value type.
1545 if (VA.isExtInLoc())
1546 RV = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: RV);
1547
1548 InVals.push_back(Elt: RV);
1549 }
1550
1551 return Chain;
1552}
1553
1554//===----------------------------------------------------------------------===//
1555// TargetLowering Implementation
1556//===----------------------------------------------------------------------===//
1557
1558TargetLowering::AtomicExpansionKind
1559SparcTargetLowering::shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const {
1560 if (AI->getOperation() == AtomicRMWInst::Xchg &&
1561 AI->getType()->getPrimitiveSizeInBits() == 32)
1562 return AtomicExpansionKind::None; // Uses xchg instruction
1563
1564 return AtomicExpansionKind::CmpXChg;
1565}
1566
1567/// intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC
1568/// rcond condition.
1569static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC) {
1570 switch (CC) {
1571 default:
1572 llvm_unreachable("Unknown/unsigned integer condition code!");
1573 case ISD::SETEQ:
1574 return SPCC::REG_Z;
1575 case ISD::SETNE:
1576 return SPCC::REG_NZ;
1577 case ISD::SETLT:
1578 return SPCC::REG_LZ;
1579 case ISD::SETGT:
1580 return SPCC::REG_GZ;
1581 case ISD::SETLE:
1582 return SPCC::REG_LEZ;
1583 case ISD::SETGE:
1584 return SPCC::REG_GEZ;
1585 }
1586}
1587
1588/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1589/// condition.
1590static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1591 switch (CC) {
1592 default: llvm_unreachable("Unknown integer condition code!");
1593 case ISD::SETEQ: return SPCC::ICC_E;
1594 case ISD::SETNE: return SPCC::ICC_NE;
1595 case ISD::SETLT: return SPCC::ICC_L;
1596 case ISD::SETGT: return SPCC::ICC_G;
1597 case ISD::SETLE: return SPCC::ICC_LE;
1598 case ISD::SETGE: return SPCC::ICC_GE;
1599 case ISD::SETULT: return SPCC::ICC_CS;
1600 case ISD::SETULE: return SPCC::ICC_LEU;
1601 case ISD::SETUGT: return SPCC::ICC_GU;
1602 case ISD::SETUGE: return SPCC::ICC_CC;
1603 }
1604}
1605
1606/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1607/// FCC condition.
1608static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1609 switch (CC) {
1610 default: llvm_unreachable("Unknown fp condition code!");
1611 case ISD::SETEQ:
1612 case ISD::SETOEQ: return SPCC::FCC_E;
1613 case ISD::SETNE:
1614 case ISD::SETUNE: return SPCC::FCC_NE;
1615 case ISD::SETLT:
1616 case ISD::SETOLT: return SPCC::FCC_L;
1617 case ISD::SETGT:
1618 case ISD::SETOGT: return SPCC::FCC_G;
1619 case ISD::SETLE:
1620 case ISD::SETOLE: return SPCC::FCC_LE;
1621 case ISD::SETGE:
1622 case ISD::SETOGE: return SPCC::FCC_GE;
1623 case ISD::SETULT: return SPCC::FCC_UL;
1624 case ISD::SETULE: return SPCC::FCC_ULE;
1625 case ISD::SETUGT: return SPCC::FCC_UG;
1626 case ISD::SETUGE: return SPCC::FCC_UGE;
1627 case ISD::SETUO: return SPCC::FCC_U;
1628 case ISD::SETO: return SPCC::FCC_O;
1629 case ISD::SETONE: return SPCC::FCC_LG;
1630 case ISD::SETUEQ: return SPCC::FCC_UE;
1631 }
1632}
1633
1634SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
1635 const SparcSubtarget &STI)
1636 : TargetLowering(TM, STI), Subtarget(&STI) {
1637 MVT PtrVT = MVT::getIntegerVT(BitWidth: TM.getPointerSizeInBits(AS: 0));
1638
1639 // Instructions which use registers as conditionals examine all the
1640 // bits (as does the pseudo SELECT_CC expansion). I don't think it
1641 // matters much whether it's ZeroOrOneBooleanContent, or
1642 // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
1643 // former.
1644 setBooleanContents(ZeroOrOneBooleanContent);
1645 setBooleanVectorContents(ZeroOrOneBooleanContent);
1646
1647 // Set up the register classes.
1648 addRegisterClass(VT: MVT::i32, RC: &SP::IntRegsRegClass);
1649 if (!Subtarget->useSoftFloat()) {
1650 addRegisterClass(VT: MVT::f32, RC: &SP::FPRegsRegClass);
1651 addRegisterClass(VT: MVT::f64, RC: &SP::DFPRegsRegClass);
1652 addRegisterClass(VT: MVT::f128, RC: &SP::QFPRegsRegClass);
1653 }
1654 if (Subtarget->is64Bit()) {
1655 addRegisterClass(VT: MVT::i64, RC: &SP::I64RegsRegClass);
1656 } else {
1657 // On 32bit sparc, we define a double-register 32bit register
1658 // class, as well. This is modeled in LLVM as a 2-vector of i32.
1659 addRegisterClass(VT: MVT::v2i32, RC: &SP::IntPairRegClass);
1660
1661 // ...but almost all operations must be expanded, so set that as
1662 // the default.
1663 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
1664 setOperationAction(Op, VT: MVT::v2i32, Action: Expand);
1665 }
1666 // Truncating/extending stores/loads are also not supported.
1667 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
1668 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1669 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1670 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1671
1672 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1673 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1674 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1675
1676 setTruncStoreAction(ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1677 setTruncStoreAction(ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1678 }
1679 // However, load and store *are* legal.
1680 setOperationAction(Op: ISD::LOAD, VT: MVT::v2i32, Action: Legal);
1681 setOperationAction(Op: ISD::STORE, VT: MVT::v2i32, Action: Legal);
1682 setOperationAction(Op: ISD::EXTRACT_VECTOR_ELT, VT: MVT::v2i32, Action: Legal);
1683 setOperationAction(Op: ISD::BUILD_VECTOR, VT: MVT::v2i32, Action: Legal);
1684
1685 // And we need to promote i64 loads/stores into vector load/store
1686 setOperationAction(Op: ISD::LOAD, VT: MVT::i64, Action: Custom);
1687 setOperationAction(Op: ISD::STORE, VT: MVT::i64, Action: Custom);
1688
1689 // Sadly, this doesn't work:
1690 // AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
1691 // AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
1692 }
1693
1694 // Turn FP extload into load/fpextend
1695 for (MVT VT : MVT::fp_valuetypes()) {
1696 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f16, Action: Expand);
1697 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f32, Action: Expand);
1698 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f64, Action: Expand);
1699 }
1700
1701 // Sparc doesn't have i1 sign extending load
1702 for (MVT VT : MVT::integer_valuetypes())
1703 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
1704
1705 // Turn FP truncstore into trunc + store.
1706 setTruncStoreAction(ValVT: MVT::f32, MemVT: MVT::f16, Action: Expand);
1707 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f16, Action: Expand);
1708 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f32, Action: Expand);
1709 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f16, Action: Expand);
1710 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f32, Action: Expand);
1711 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f64, Action: Expand);
1712
1713 // Custom legalize GlobalAddress nodes into LO/HI parts.
1714 setOperationAction(Op: ISD::GlobalAddress, VT: PtrVT, Action: Custom);
1715 setOperationAction(Op: ISD::GlobalTLSAddress, VT: PtrVT, Action: Custom);
1716 setOperationAction(Op: ISD::ConstantPool, VT: PtrVT, Action: Custom);
1717 setOperationAction(Op: ISD::BlockAddress, VT: PtrVT, Action: Custom);
1718
1719 // Sparc doesn't have sext_inreg, replace them with shl/sra
1720 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i16, Action: Expand);
1721 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i8 , Action: Expand);
1722 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i1 , Action: Expand);
1723
1724 // Sparc has no REM or DIVREM operations.
1725 setOperationAction(Op: ISD::UREM, VT: MVT::i32, Action: Expand);
1726 setOperationAction(Op: ISD::SREM, VT: MVT::i32, Action: Expand);
1727 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i32, Action: Expand);
1728 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i32, Action: Expand);
1729
1730 // ... nor does SparcV9.
1731 if (Subtarget->is64Bit()) {
1732 setOperationAction(Op: ISD::UREM, VT: MVT::i64, Action: Expand);
1733 setOperationAction(Op: ISD::SREM, VT: MVT::i64, Action: Expand);
1734 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i64, Action: Expand);
1735 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i64, Action: Expand);
1736 }
1737
1738 // Custom expand fp<->sint
1739 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::i32, Action: Custom);
1740 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::i32, Action: Custom);
1741 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::i64, Action: Custom);
1742 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::i64, Action: Custom);
1743
1744 // Custom Expand fp<->uint
1745 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i32, Action: Custom);
1746 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i32, Action: Custom);
1747 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i64, Action: Custom);
1748 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i64, Action: Custom);
1749
1750 // Lower f16 conversion operations into library calls
1751 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f32, Action: Expand);
1752 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f32, Action: Expand);
1753 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f64, Action: Expand);
1754 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f64, Action: Expand);
1755 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f128, Action: Expand);
1756 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f128, Action: Expand);
1757
1758 setOperationAction(Op: ISD::BITCAST, VT: MVT::f32,
1759 Action: Subtarget->isVIS3() ? Legal : Expand);
1760 setOperationAction(Op: ISD::BITCAST, VT: MVT::i32,
1761 Action: Subtarget->isVIS3() ? Legal : Expand);
1762
1763 // Sparc has no select or setcc: expand to SELECT_CC.
1764 setOperationAction(Op: ISD::SELECT, VT: MVT::i32, Action: Expand);
1765 setOperationAction(Op: ISD::SELECT, VT: MVT::f32, Action: Expand);
1766 setOperationAction(Op: ISD::SELECT, VT: MVT::f64, Action: Expand);
1767 setOperationAction(Op: ISD::SELECT, VT: MVT::f128, Action: Expand);
1768
1769 setOperationAction(Op: ISD::SETCC, VT: MVT::i32, Action: Expand);
1770 setOperationAction(Op: ISD::SETCC, VT: MVT::f32, Action: Expand);
1771 setOperationAction(Op: ISD::SETCC, VT: MVT::f64, Action: Expand);
1772 setOperationAction(Op: ISD::SETCC, VT: MVT::f128, Action: Expand);
1773
1774 // Sparc doesn't have BRCOND either, it has BR_CC.
1775 setOperationAction(Op: ISD::BRCOND, VT: MVT::Other, Action: Expand);
1776 setOperationAction(Op: ISD::BRIND, VT: MVT::Other, Action: Expand);
1777 setOperationAction(Op: ISD::BR_JT, VT: MVT::Other, Action: Expand);
1778 setOperationAction(Op: ISD::BR_CC, VT: MVT::i32, Action: Custom);
1779 setOperationAction(Op: ISD::BR_CC, VT: MVT::f32, Action: Custom);
1780 setOperationAction(Op: ISD::BR_CC, VT: MVT::f64, Action: Custom);
1781 setOperationAction(Op: ISD::BR_CC, VT: MVT::f128, Action: Custom);
1782
1783 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i32, Action: Custom);
1784 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f32, Action: Custom);
1785 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f64, Action: Custom);
1786 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f128, Action: Custom);
1787
1788 setOperationAction(Op: ISD::ADDC, VT: MVT::i32, Action: Legal);
1789 setOperationAction(Op: ISD::ADDE, VT: MVT::i32, Action: Legal);
1790 setOperationAction(Op: ISD::SUBC, VT: MVT::i32, Action: Legal);
1791 setOperationAction(Op: ISD::SUBE, VT: MVT::i32, Action: Legal);
1792
1793 if (Subtarget->isVIS3()) {
1794 setOperationAction(Op: ISD::ADDC, VT: MVT::i64, Action: Legal);
1795 setOperationAction(Op: ISD::ADDE, VT: MVT::i64, Action: Legal);
1796 }
1797
1798 if (Subtarget->is64Bit()) {
1799 setOperationAction(Op: ISD::BITCAST, VT: MVT::f64,
1800 Action: Subtarget->isVIS3() ? Legal : Expand);
1801 setOperationAction(Op: ISD::BITCAST, VT: MVT::i64,
1802 Action: Subtarget->isVIS3() ? Legal : Expand);
1803 setOperationAction(Op: ISD::SELECT, VT: MVT::i64, Action: Expand);
1804 setOperationAction(Op: ISD::SETCC, VT: MVT::i64, Action: Expand);
1805 setOperationAction(Op: ISD::BR_CC, VT: MVT::i64, Action: Custom);
1806 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i64, Action: Custom);
1807
1808 setOperationAction(Op: ISD::CTPOP, VT: MVT::i64,
1809 Action: Subtarget->usePopc() ? Legal : Expand);
1810 setOperationAction(Op: ISD::BSWAP, VT: MVT::i64, Action: Expand);
1811 setOperationAction(Op: ISD::ROTL , VT: MVT::i64, Action: Expand);
1812 setOperationAction(Op: ISD::ROTR , VT: MVT::i64, Action: Expand);
1813 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i64, Action: Custom);
1814 }
1815
1816 // ATOMICs.
1817 // Atomics are supported on SparcV9. 32-bit atomics are also
1818 // supported by some Leon SparcV8 variants. Otherwise, atomics
1819 // are unsupported.
1820 if (Subtarget->isV9()) {
1821 // TODO: we _ought_ to be able to support 64-bit atomics on 32-bit sparcv9,
1822 // but it hasn't been implemented in the backend yet.
1823 if (Subtarget->is64Bit())
1824 setMaxAtomicSizeInBitsSupported(64);
1825 else
1826 setMaxAtomicSizeInBitsSupported(32);
1827 } else if (Subtarget->hasLeonCasa())
1828 setMaxAtomicSizeInBitsSupported(32);
1829 else
1830 setMaxAtomicSizeInBitsSupported(0);
1831
1832 setMinCmpXchgSizeInBits(32);
1833
1834 setOperationAction(Op: ISD::ATOMIC_SWAP, VT: MVT::i32, Action: Legal);
1835
1836 setOperationAction(Op: ISD::ATOMIC_FENCE, VT: MVT::Other, Action: Legal);
1837
1838 // Custom Lower Atomic LOAD/STORE
1839 setOperationAction(Op: ISD::ATOMIC_LOAD, VT: MVT::i32, Action: Custom);
1840 setOperationAction(Op: ISD::ATOMIC_STORE, VT: MVT::i32, Action: Custom);
1841
1842 if (Subtarget->is64Bit()) {
1843 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP, VT: MVT::i64, Action: Legal);
1844 setOperationAction(Op: ISD::ATOMIC_SWAP, VT: MVT::i64, Action: Legal);
1845 setOperationAction(Op: ISD::ATOMIC_LOAD, VT: MVT::i64, Action: Custom);
1846 setOperationAction(Op: ISD::ATOMIC_STORE, VT: MVT::i64, Action: Custom);
1847 }
1848
1849 if (!Subtarget->isV9()) {
1850 // SparcV8 does not have FNEGD and FABSD.
1851 setOperationAction(Op: ISD::FNEG, VT: MVT::f64, Action: Custom);
1852 setOperationAction(Op: ISD::FABS, VT: MVT::f64, Action: Custom);
1853 }
1854
1855 setOperationAction(Op: ISD::FSIN , VT: MVT::f128, Action: Expand);
1856 setOperationAction(Op: ISD::FCOS , VT: MVT::f128, Action: Expand);
1857 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f128, Action: Expand);
1858 setOperationAction(Op: ISD::FREM, VT: MVT::f128, Action: LibCall);
1859 setOperationAction(Op: ISD::FMA , VT: MVT::f128, Action: Expand);
1860 setOperationAction(Op: ISD::FSIN , VT: MVT::f64, Action: Expand);
1861 setOperationAction(Op: ISD::FCOS , VT: MVT::f64, Action: Expand);
1862 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f64, Action: Expand);
1863 setOperationAction(Op: ISD::FREM, VT: MVT::f64, Action: LibCall);
1864 setOperationAction(Op: ISD::FMA, VT: MVT::f64,
1865 Action: Subtarget->isUA2007() ? Legal : Expand);
1866 setOperationAction(Op: ISD::FSIN , VT: MVT::f32, Action: Expand);
1867 setOperationAction(Op: ISD::FCOS , VT: MVT::f32, Action: Expand);
1868 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f32, Action: Expand);
1869 setOperationAction(Op: ISD::FREM, VT: MVT::f32, Action: LibCall);
1870 setOperationAction(Op: ISD::FMA, VT: MVT::f32,
1871 Action: Subtarget->isUA2007() ? Legal : Expand);
1872 setOperationAction(Op: ISD::ROTL , VT: MVT::i32, Action: Expand);
1873 setOperationAction(Op: ISD::ROTR , VT: MVT::i32, Action: Expand);
1874 setOperationAction(Op: ISD::BSWAP, VT: MVT::i32, Action: Expand);
1875 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f128, Action: Expand);
1876 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f64, Action: Expand);
1877 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f32, Action: Expand);
1878 setOperationAction(Op: ISD::FPOW , VT: MVT::f128, Action: Expand);
1879 setOperationAction(Op: ISD::FPOW , VT: MVT::f64, Action: Expand);
1880 setOperationAction(Op: ISD::FPOW , VT: MVT::f32, Action: Expand);
1881
1882 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i32, Action: Expand);
1883 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i32, Action: Expand);
1884 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i32, Action: Expand);
1885
1886 // Expands to [SU]MUL_LOHI.
1887 setOperationAction(Op: ISD::MULHU, VT: MVT::i32, Action: Expand);
1888 setOperationAction(Op: ISD::MULHS, VT: MVT::i32, Action: Expand);
1889 setOperationAction(Op: ISD::MUL, VT: MVT::i32, Action: Expand);
1890
1891 if (Subtarget->useSoftMulDiv()) {
1892 // .umul works for both signed and unsigned
1893 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i32, Action: Expand);
1894 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i32, Action: Expand);
1895 setOperationAction(Op: ISD::SDIV, VT: MVT::i32, Action: Expand);
1896 setOperationAction(Op: ISD::UDIV, VT: MVT::i32, Action: Expand);
1897 }
1898
1899 if (Subtarget->is64Bit()) {
1900 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i64, Action: Expand);
1901 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i64, Action: Expand);
1902 setOperationAction(Op: ISD::MULHU, VT: MVT::i64,
1903 Action: Subtarget->isVIS3() ? Legal : Expand);
1904 setOperationAction(Op: ISD::MULHS, VT: MVT::i64,
1905 Action: Subtarget->isVIS3() ? Legal : Expand);
1906
1907 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i64, Action: Expand);
1908 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i64, Action: Expand);
1909 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i64, Action: Expand);
1910 }
1911
1912 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1913 setOperationAction(Op: ISD::VASTART , VT: MVT::Other, Action: Custom);
1914 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1915 setOperationAction(Op: ISD::VAARG , VT: MVT::Other, Action: Custom);
1916
1917 setOperationAction(Op: ISD::TRAP , VT: MVT::Other, Action: Legal);
1918 setOperationAction(Op: ISD::DEBUGTRAP , VT: MVT::Other, Action: Legal);
1919
1920 // Use the default implementation.
1921 setOperationAction(Op: ISD::VACOPY , VT: MVT::Other, Action: Expand);
1922 setOperationAction(Op: ISD::VAEND , VT: MVT::Other, Action: Expand);
1923 setOperationAction(Op: ISD::STACKSAVE , VT: MVT::Other, Action: Expand);
1924 setOperationAction(Op: ISD::STACKRESTORE , VT: MVT::Other, Action: Expand);
1925 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i32 , Action: Custom);
1926 setOperationAction(Op: ISD::STACKADDRESS, VT: MVT::Other, Action: Custom);
1927
1928 setStackPointerRegisterToSaveRestore(SP::O6);
1929
1930 setOperationAction(Op: ISD::CTPOP, VT: MVT::i32,
1931 Action: Subtarget->usePopc() ? Legal : Expand);
1932
1933 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1934 setOperationAction(Op: ISD::LOAD, VT: MVT::f128, Action: Legal);
1935 setOperationAction(Op: ISD::STORE, VT: MVT::f128, Action: Legal);
1936 } else {
1937 setOperationAction(Op: ISD::LOAD, VT: MVT::f128, Action: Custom);
1938 setOperationAction(Op: ISD::STORE, VT: MVT::f128, Action: Custom);
1939 }
1940
1941 if (Subtarget->hasHardQuad()) {
1942 setOperationAction(Op: ISD::FADD, VT: MVT::f128, Action: Legal);
1943 setOperationAction(Op: ISD::FSUB, VT: MVT::f128, Action: Legal);
1944 setOperationAction(Op: ISD::FMUL, VT: MVT::f128, Action: Legal);
1945 setOperationAction(Op: ISD::FDIV, VT: MVT::f128, Action: Legal);
1946 setOperationAction(Op: ISD::FSQRT, VT: MVT::f128, Action: Legal);
1947 setOperationAction(Op: ISD::FP_EXTEND, VT: MVT::f128, Action: Legal);
1948 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f64, Action: Legal);
1949 if (Subtarget->isV9()) {
1950 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Legal);
1951 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Legal);
1952 } else {
1953 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Custom);
1954 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Custom);
1955 }
1956 } else {
1957 // Custom legalize f128 operations.
1958
1959 setOperationAction(Op: ISD::FADD, VT: MVT::f128, Action: Custom);
1960 setOperationAction(Op: ISD::FSUB, VT: MVT::f128, Action: Custom);
1961 setOperationAction(Op: ISD::FMUL, VT: MVT::f128, Action: Custom);
1962 setOperationAction(Op: ISD::FDIV, VT: MVT::f128, Action: Custom);
1963 setOperationAction(Op: ISD::FSQRT, VT: MVT::f128, Action: Custom);
1964 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Custom);
1965 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Custom);
1966
1967 setOperationAction(Op: ISD::FP_EXTEND, VT: MVT::f128, Action: Custom);
1968 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f64, Action: Custom);
1969 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f32, Action: Custom);
1970 }
1971
1972 if (Subtarget->fixAllFDIVSQRT()) {
1973 // Promote FDIVS and FSQRTS to FDIVD and FSQRTD instructions instead as
1974 // the former instructions generate errata on LEON processors.
1975 setOperationAction(Op: ISD::FDIV, VT: MVT::f32, Action: Promote);
1976 setOperationAction(Op: ISD::FSQRT, VT: MVT::f32, Action: Promote);
1977 }
1978
1979 if (Subtarget->hasNoFMULS()) {
1980 setOperationAction(Op: ISD::FMUL, VT: MVT::f32, Action: Promote);
1981 }
1982
1983 // Custom combine bitcast between f64 and v2i32
1984 if (!Subtarget->is64Bit())
1985 setTargetDAGCombine(ISD::BITCAST);
1986
1987 if (Subtarget->hasLeonCycleCounter())
1988 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Custom);
1989
1990 if (Subtarget->isVIS3()) {
1991 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Legal);
1992 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Legal);
1993 setOperationAction(Op: ISD::CTLZ_ZERO_UNDEF, VT: MVT::i32, Action: Legal);
1994 setOperationAction(Op: ISD::CTLZ_ZERO_UNDEF, VT: MVT::i64, Action: Legal);
1995
1996 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32,
1997 Action: Subtarget->is64Bit() ? Promote : Expand);
1998 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
1999 setOperationAction(Op: ISD::CTTZ_ZERO_UNDEF, VT: MVT::i32,
2000 Action: Subtarget->is64Bit() ? Promote : Expand);
2001 setOperationAction(Op: ISD::CTTZ_ZERO_UNDEF, VT: MVT::i64, Action: Expand);
2002 } else if (Subtarget->usePopc()) {
2003 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Expand);
2004 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Expand);
2005 setOperationAction(Op: ISD::CTLZ_ZERO_UNDEF, VT: MVT::i32, Action: Expand);
2006 setOperationAction(Op: ISD::CTLZ_ZERO_UNDEF, VT: MVT::i64, Action: Expand);
2007
2008 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32, Action: Expand);
2009 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
2010 setOperationAction(Op: ISD::CTTZ_ZERO_UNDEF, VT: MVT::i32, Action: Expand);
2011 setOperationAction(Op: ISD::CTTZ_ZERO_UNDEF, VT: MVT::i64, Action: Expand);
2012 } else {
2013 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Expand);
2014 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Expand);
2015 setOperationAction(Op: ISD::CTLZ_ZERO_UNDEF, VT: MVT::i32,
2016 Action: Subtarget->is64Bit() ? Promote : LibCall);
2017 setOperationAction(Op: ISD::CTLZ_ZERO_UNDEF, VT: MVT::i64, Action: LibCall);
2018
2019 // FIXME here we don't have any ISA extensions that could help us, so to
2020 // prevent large expansions those should be made into LibCalls.
2021 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32, Action: Expand);
2022 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
2023 setOperationAction(Op: ISD::CTTZ_ZERO_UNDEF, VT: MVT::i32, Action: Expand);
2024 setOperationAction(Op: ISD::CTTZ_ZERO_UNDEF, VT: MVT::i64, Action: Expand);
2025 }
2026
2027 setOperationAction(Op: ISD::INTRINSIC_WO_CHAIN, VT: MVT::Other, Action: Custom);
2028
2029 // Some processors have no branch predictor and have pipelines longer than
2030 // what can be covered by the delay slot. This results in a stall, so mark
2031 // branches to be expensive on those processors.
2032 setJumpIsExpensive(Subtarget->hasNoPredictor());
2033 // The high cost of branching means that using conditional moves will
2034 // still be profitable even if the condition is predictable.
2035 PredictableSelectIsExpensive = !isJumpExpensive();
2036
2037 setMinFunctionAlignment(Align(4));
2038
2039 computeRegisterProperties(TRI: Subtarget->getRegisterInfo());
2040}
2041
2042bool SparcTargetLowering::useSoftFloat() const {
2043 return Subtarget->useSoftFloat();
2044}
2045
2046EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
2047 EVT VT) const {
2048 if (!VT.isVector())
2049 return MVT::i32;
2050 return VT.changeVectorElementTypeToInteger();
2051}
2052
2053/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
2054/// be zero. Op is expected to be a target specific node. Used by DAG
2055/// combiner.
2056void SparcTargetLowering::computeKnownBitsForTargetNode
2057 (const SDValue Op,
2058 KnownBits &Known,
2059 const APInt &DemandedElts,
2060 const SelectionDAG &DAG,
2061 unsigned Depth) const {
2062 KnownBits Known2;
2063 Known.resetAll();
2064
2065 switch (Op.getOpcode()) {
2066 default: break;
2067 case SPISD::SELECT_ICC:
2068 case SPISD::SELECT_XCC:
2069 case SPISD::SELECT_FCC:
2070 Known = DAG.computeKnownBits(Op: Op.getOperand(i: 1), Depth: Depth + 1);
2071 Known2 = DAG.computeKnownBits(Op: Op.getOperand(i: 0), Depth: Depth + 1);
2072
2073 // Only known if known in both the LHS and RHS.
2074 Known = Known.intersectWith(RHS: Known2);
2075 break;
2076 }
2077}
2078
2079// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
2080// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
2081static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
2082 ISD::CondCode CC, unsigned &SPCC) {
2083 if (isNullConstant(V: RHS) && CC == ISD::SETNE &&
2084 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
2085 LHS.getOpcode() == SPISD::SELECT_XCC) &&
2086 LHS.getOperand(i: 3).getOpcode() == SPISD::CMPICC) ||
2087 (LHS.getOpcode() == SPISD::SELECT_FCC &&
2088 (LHS.getOperand(i: 3).getOpcode() == SPISD::CMPFCC ||
2089 LHS.getOperand(i: 3).getOpcode() == SPISD::CMPFCC_V9))) &&
2090 isOneConstant(V: LHS.getOperand(i: 0)) && isNullConstant(V: LHS.getOperand(i: 1))) {
2091 SDValue CMPCC = LHS.getOperand(i: 3);
2092 SPCC = LHS.getConstantOperandVal(i: 2);
2093 LHS = CMPCC.getOperand(i: 0);
2094 RHS = CMPCC.getOperand(i: 1);
2095 }
2096}
2097
2098// Convert to a target node and set target flags.
2099SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
2100 SelectionDAG &DAG) const {
2101 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Val&: Op))
2102 return DAG.getTargetGlobalAddress(GV: GA->getGlobal(),
2103 DL: SDLoc(GA),
2104 VT: GA->getValueType(ResNo: 0),
2105 offset: GA->getOffset(), TargetFlags: TF);
2106
2107 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Val&: Op))
2108 return DAG.getTargetConstantPool(C: CP->getConstVal(), VT: CP->getValueType(ResNo: 0),
2109 Align: CP->getAlign(), Offset: CP->getOffset(), TargetFlags: TF);
2110
2111 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Val&: Op))
2112 return DAG.getTargetBlockAddress(BA: BA->getBlockAddress(),
2113 VT: Op.getValueType(),
2114 Offset: 0,
2115 TargetFlags: TF);
2116
2117 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Val&: Op))
2118 return DAG.getTargetExternalSymbol(Sym: ES->getSymbol(),
2119 VT: ES->getValueType(ResNo: 0), TargetFlags: TF);
2120
2121 llvm_unreachable("Unhandled address SDNode");
2122}
2123
2124// Split Op into high and low parts according to HiTF and LoTF.
2125// Return an ADD node combining the parts.
2126SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
2127 unsigned HiTF, unsigned LoTF,
2128 SelectionDAG &DAG) const {
2129 SDLoc DL(Op);
2130 EVT VT = Op.getValueType();
2131 SDValue Hi = DAG.getNode(Opcode: SPISD::Hi, DL, VT, Operand: withTargetFlags(Op, TF: HiTF, DAG));
2132 SDValue Lo = DAG.getNode(Opcode: SPISD::Lo, DL, VT, Operand: withTargetFlags(Op, TF: LoTF, DAG));
2133 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Hi, N2: Lo);
2134}
2135
2136// Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
2137// or ExternalSymbol SDNode.
2138SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
2139 SDLoc DL(Op);
2140 EVT VT = getPointerTy(DL: DAG.getDataLayout());
2141
2142 // Handle PIC mode first. SPARC needs a got load for every variable!
2143 if (isPositionIndependent()) {
2144 const Module *M = DAG.getMachineFunction().getFunction().getParent();
2145 PICLevel::Level picLevel = M->getPICLevel();
2146 SDValue Idx;
2147
2148 if (picLevel == PICLevel::SmallPIC) {
2149 // This is the pic13 code model, the GOT is known to be smaller than 8KiB.
2150 Idx = DAG.getNode(Opcode: SPISD::Lo, DL, VT: Op.getValueType(),
2151 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_GOT13, DAG));
2152 } else {
2153 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
2154 Idx = makeHiLoPair(Op, HiTF: ELF::R_SPARC_GOT22, LoTF: ELF::R_SPARC_GOT10, DAG);
2155 }
2156
2157 SDValue GlobalBase = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT);
2158 SDValue AbsAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: GlobalBase, N2: Idx);
2159 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2160 // function has calls.
2161 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2162 MFI.setHasCalls(true);
2163 return DAG.getLoad(VT, dl: DL, Chain: DAG.getEntryNode(), Ptr: AbsAddr,
2164 PtrInfo: MachinePointerInfo::getGOT(MF&: DAG.getMachineFunction()));
2165 }
2166
2167 // This is one of the absolute code models.
2168 switch(getTargetMachine().getCodeModel()) {
2169 default:
2170 llvm_unreachable("Unsupported absolute code model");
2171 case CodeModel::Small:
2172 // abs32.
2173 return makeHiLoPair(Op, HiTF: ELF::R_SPARC_HI22, LoTF: ELF::R_SPARC_LO10, DAG);
2174 case CodeModel::Medium: {
2175 // abs44.
2176 SDValue H44 = makeHiLoPair(Op, HiTF: ELF::R_SPARC_H44, LoTF: ELF::R_SPARC_M44, DAG);
2177 H44 = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: H44, N2: DAG.getConstant(Val: 12, DL, VT: MVT::i32));
2178 SDValue L44 = withTargetFlags(Op, TF: ELF::R_SPARC_L44, DAG);
2179 L44 = DAG.getNode(Opcode: SPISD::Lo, DL, VT, Operand: L44);
2180 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: H44, N2: L44);
2181 }
2182 case CodeModel::Large: {
2183 // abs64.
2184 SDValue Hi = makeHiLoPair(Op, HiTF: ELF::R_SPARC_HH22, LoTF: ELF::R_SPARC_HM10, DAG);
2185 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi, N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
2186 SDValue Lo = makeHiLoPair(Op, HiTF: ELF::R_SPARC_HI22, LoTF: ELF::R_SPARC_LO10, DAG);
2187 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Hi, N2: Lo);
2188 }
2189 }
2190}
2191
2192SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
2193 SelectionDAG &DAG) const {
2194 return makeAddress(Op, DAG);
2195}
2196
2197SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
2198 SelectionDAG &DAG) const {
2199 return makeAddress(Op, DAG);
2200}
2201
2202SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
2203 SelectionDAG &DAG) const {
2204 return makeAddress(Op, DAG);
2205}
2206
2207SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2208 SelectionDAG &DAG) const {
2209
2210 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Val&: Op);
2211 if (DAG.getTarget().useEmulatedTLS())
2212 return LowerToTLSEmulatedModel(GA, DAG);
2213
2214 SDLoc DL(GA);
2215 const GlobalValue *GV = GA->getGlobal();
2216 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
2217
2218 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2219
2220 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2221 unsigned HiTF =
2222 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_HI22
2223 : ELF::R_SPARC_TLS_LDM_HI22);
2224 unsigned LoTF =
2225 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_LO10
2226 : ELF::R_SPARC_TLS_LDM_LO10);
2227 unsigned addTF =
2228 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_ADD
2229 : ELF::R_SPARC_TLS_LDM_ADD);
2230 unsigned callTF =
2231 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_CALL
2232 : ELF::R_SPARC_TLS_LDM_CALL);
2233
2234 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
2235 SDValue Base = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT: PtrVT);
2236 SDValue Argument = DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT, N1: Base, N2: HiLo,
2237 N3: withTargetFlags(Op, TF: addTF, DAG));
2238
2239 SDValue Chain = DAG.getEntryNode();
2240 SDValue InGlue;
2241
2242 Chain = DAG.getCALLSEQ_START(Chain, InSize: 0, OutSize: 0, DL);
2243 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SP::O0, N: Argument, Glue: InGlue);
2244 InGlue = Chain.getValue(R: 1);
2245 SDValue Callee = DAG.getTargetExternalSymbol(Sym: "__tls_get_addr", VT: PtrVT);
2246 SDValue Symbol = withTargetFlags(Op, TF: callTF, DAG);
2247
2248 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
2249 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
2250 MF: DAG.getMachineFunction(), CC: CallingConv::C);
2251 assert(Mask && "Missing call preserved mask for calling convention");
2252 SDValue Ops[] = {Chain,
2253 Callee,
2254 Symbol,
2255 DAG.getRegister(Reg: SP::O0, VT: PtrVT),
2256 DAG.getRegisterMask(RegMask: Mask),
2257 InGlue};
2258 Chain = DAG.getNode(Opcode: SPISD::TLS_CALL, DL, VTList: NodeTys, Ops);
2259 InGlue = Chain.getValue(R: 1);
2260 Chain = DAG.getCALLSEQ_END(Chain, Size1: 0, Size2: 0, Glue: InGlue, DL);
2261 InGlue = Chain.getValue(R: 1);
2262 SDValue Ret = DAG.getCopyFromReg(Chain, dl: DL, Reg: SP::O0, VT: PtrVT, Glue: InGlue);
2263
2264 if (model != TLSModel::LocalDynamic)
2265 return Ret;
2266
2267 SDValue Hi =
2268 DAG.getNode(Opcode: SPISD::Hi, DL, VT: PtrVT,
2269 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_HIX22, DAG));
2270 SDValue Lo =
2271 DAG.getNode(Opcode: SPISD::Lo, DL, VT: PtrVT,
2272 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_LOX10, DAG));
2273 HiLo = DAG.getNode(Opcode: ISD::XOR, DL, VT: PtrVT, N1: Hi, N2: Lo);
2274 return DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT, N1: Ret, N2: HiLo,
2275 N3: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_ADD, DAG));
2276 }
2277
2278 if (model == TLSModel::InitialExec) {
2279 unsigned ldTF = ((PtrVT == MVT::i64) ? ELF::R_SPARC_TLS_IE_LDX
2280 : ELF::R_SPARC_TLS_IE_LD);
2281
2282 SDValue Base = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT: PtrVT);
2283
2284 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2285 // function has calls.
2286 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2287 MFI.setHasCalls(true);
2288
2289 SDValue TGA = makeHiLoPair(Op, HiTF: ELF::R_SPARC_TLS_IE_HI22,
2290 LoTF: ELF::R_SPARC_TLS_IE_LO10, DAG);
2291 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: Base, N2: TGA);
2292 SDValue Offset = DAG.getNode(Opcode: SPISD::TLS_LD,
2293 DL, VT: PtrVT, N1: Ptr,
2294 N2: withTargetFlags(Op, TF: ldTF, DAG));
2295 return DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT,
2296 N1: DAG.getRegister(Reg: SP::G7, VT: PtrVT), N2: Offset,
2297 N3: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_IE_ADD, DAG));
2298 }
2299
2300 assert(model == TLSModel::LocalExec);
2301 SDValue Hi = DAG.getNode(Opcode: SPISD::Hi, DL, VT: PtrVT,
2302 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LE_HIX22, DAG));
2303 SDValue Lo = DAG.getNode(Opcode: SPISD::Lo, DL, VT: PtrVT,
2304 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LE_LOX10, DAG));
2305 SDValue Offset = DAG.getNode(Opcode: ISD::XOR, DL, VT: PtrVT, N1: Hi, N2: Lo);
2306
2307 return DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT,
2308 N1: DAG.getRegister(Reg: SP::G7, VT: PtrVT), N2: Offset);
2309}
2310
2311SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain,
2312 ArgListTy &Args, SDValue Arg,
2313 const SDLoc &DL,
2314 SelectionDAG &DAG) const {
2315 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2316 EVT ArgVT = Arg.getValueType();
2317 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
2318
2319 if (ArgTy->isFP128Ty()) {
2320 // Create a stack object and pass the pointer to the library function.
2321 int FI = MFI.CreateStackObject(Size: 16, Alignment: Align(8), isSpillSlot: false);
2322 SDValue FIPtr = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
2323 Chain = DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: FIPtr, PtrInfo: MachinePointerInfo(), Alignment: Align(8));
2324 Args.emplace_back(args&: FIPtr, args: PointerType::getUnqual(C&: ArgTy->getContext()));
2325 } else {
2326 Args.emplace_back(args&: Arg, args&: ArgTy);
2327 }
2328 return Chain;
2329}
2330
2331SDValue SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2332 RTLIB::Libcall LibFunc,
2333 unsigned numArgs) const {
2334 RTLIB::LibcallImpl LibFuncImpl = DAG.getLibcalls().getLibcallImpl(Call: LibFunc);
2335 if (LibFuncImpl == RTLIB::Unsupported)
2336 return SDValue();
2337
2338 ArgListTy Args;
2339
2340 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2341 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2342
2343 SDValue Callee = DAG.getExternalSymbol(LCImpl: LibFuncImpl, VT: PtrVT);
2344 Type *RetTy = Op.getValueType().getTypeForEVT(Context&: *DAG.getContext());
2345 Type *RetTyABI = RetTy;
2346 SDValue Chain = DAG.getEntryNode();
2347 SDValue RetPtr;
2348
2349 if (RetTy->isFP128Ty()) {
2350 // Create a Stack Object to receive the return value of type f128.
2351 int RetFI = MFI.CreateStackObject(Size: 16, Alignment: Align(8), isSpillSlot: false);
2352 RetPtr = DAG.getFrameIndex(FI: RetFI, VT: PtrVT);
2353 ArgListEntry Entry(RetPtr, PointerType::getUnqual(C&: RetTy->getContext()));
2354 if (!Subtarget->is64Bit()) {
2355 Entry.IsSRet = true;
2356 Entry.IndirectType = RetTy;
2357 }
2358 Entry.IsReturned = false;
2359 Args.push_back(x: Entry);
2360 RetTyABI = Type::getVoidTy(C&: *DAG.getContext());
2361 }
2362
2363 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2364 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2365 Chain = LowerF128_LibCallArg(Chain, Args, Arg: Op.getOperand(i), DL: SDLoc(Op), DAG);
2366 }
2367
2368 CallingConv::ID CC = DAG.getLibcalls().getLibcallImplCallingConv(Call: LibFuncImpl);
2369 TargetLowering::CallLoweringInfo CLI(DAG);
2370 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain).setCallee(CC, ResultType: RetTyABI, Target: Callee,
2371 ArgsList: std::move(Args));
2372
2373 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2374
2375 // chain is in second result.
2376 if (RetTyABI == RetTy)
2377 return CallInfo.first;
2378
2379 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2380
2381 Chain = CallInfo.second;
2382
2383 // Load RetPtr to get the return value.
2384 return DAG.getLoad(VT: Op.getValueType(), dl: SDLoc(Op), Chain, Ptr: RetPtr,
2385 PtrInfo: MachinePointerInfo(), Alignment: Align(8));
2386}
2387
2388SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2389 unsigned &SPCC, const SDLoc &DL,
2390 SelectionDAG &DAG) const {
2391
2392 const char *LibCall = nullptr;
2393 bool is64Bit = Subtarget->is64Bit();
2394 switch(SPCC) {
2395 default: llvm_unreachable("Unhandled conditional code!");
2396 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2397 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2398 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2399 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2400 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2401 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2402 case SPCC::FCC_UL :
2403 case SPCC::FCC_ULE:
2404 case SPCC::FCC_UG :
2405 case SPCC::FCC_UGE:
2406 case SPCC::FCC_U :
2407 case SPCC::FCC_O :
2408 case SPCC::FCC_LG :
2409 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2410 }
2411
2412 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2413 SDValue Callee = DAG.getExternalSymbol(Sym: LibCall, VT: PtrVT);
2414 Type *RetTy = Type::getInt32Ty(C&: *DAG.getContext());
2415 ArgListTy Args;
2416 SDValue Chain = DAG.getEntryNode();
2417 Chain = LowerF128_LibCallArg(Chain, Args, Arg: LHS, DL, DAG);
2418 Chain = LowerF128_LibCallArg(Chain, Args, Arg: RHS, DL, DAG);
2419
2420 TargetLowering::CallLoweringInfo CLI(DAG);
2421 CLI.setDebugLoc(DL).setChain(Chain)
2422 .setCallee(CC: CallingConv::C, ResultType: RetTy, Target: Callee, ArgsList: std::move(Args));
2423
2424 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2425
2426 // result is in first, and chain is in second result.
2427 SDValue Result = CallInfo.first;
2428
2429 switch(SPCC) {
2430 default: {
2431 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2432 SPCC = SPCC::ICC_NE;
2433 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2434 }
2435 case SPCC::FCC_UL : {
2436 SDValue Mask = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2437 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2438 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2439 SPCC = SPCC::ICC_NE;
2440 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2441 }
2442 case SPCC::FCC_ULE: {
2443 SDValue RHS = DAG.getConstant(Val: 2, DL, VT: Result.getValueType());
2444 SPCC = SPCC::ICC_NE;
2445 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2446 }
2447 case SPCC::FCC_UG : {
2448 SDValue RHS = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2449 SPCC = SPCC::ICC_G;
2450 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2451 }
2452 case SPCC::FCC_UGE: {
2453 SDValue RHS = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2454 SPCC = SPCC::ICC_NE;
2455 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2456 }
2457
2458 case SPCC::FCC_U : {
2459 SDValue RHS = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2460 SPCC = SPCC::ICC_E;
2461 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2462 }
2463 case SPCC::FCC_O : {
2464 SDValue RHS = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2465 SPCC = SPCC::ICC_NE;
2466 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2467 }
2468 case SPCC::FCC_LG : {
2469 SDValue Mask = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2470 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2471 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2472 SPCC = SPCC::ICC_NE;
2473 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2474 }
2475 case SPCC::FCC_UE : {
2476 SDValue Mask = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2477 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2478 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2479 SPCC = SPCC::ICC_E;
2480 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2481 }
2482 }
2483}
2484
2485static SDValue
2486LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2487 const SparcTargetLowering &TLI) {
2488
2489 if (Op.getOperand(i: 0).getValueType() == MVT::f64)
2490 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPEXT_F64_F128, numArgs: 1);
2491
2492 if (Op.getOperand(i: 0).getValueType() == MVT::f32)
2493 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPEXT_F32_F128, numArgs: 1);
2494
2495 llvm_unreachable("fpextend with non-float operand!");
2496 return SDValue();
2497}
2498
2499static SDValue
2500LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2501 const SparcTargetLowering &TLI) {
2502 // FP_ROUND on f64 and f32 are legal.
2503 if (Op.getOperand(i: 0).getValueType() != MVT::f128)
2504 return Op;
2505
2506 if (Op.getValueType() == MVT::f64)
2507 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPROUND_F128_F64, numArgs: 1);
2508 if (Op.getValueType() == MVT::f32)
2509 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPROUND_F128_F32, numArgs: 1);
2510
2511 llvm_unreachable("fpround to non-float!");
2512 return SDValue();
2513}
2514
2515static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2516 const SparcTargetLowering &TLI,
2517 bool hasHardQuad) {
2518 SDLoc dl(Op);
2519 EVT VT = Op.getValueType();
2520 assert(VT == MVT::i32 || VT == MVT::i64);
2521
2522 // Expand f128 operations to fp128 abi calls.
2523 if (Op.getOperand(i: 0).getValueType() == MVT::f128
2524 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2525 RTLIB::Libcall LibFunc =
2526 VT == MVT::i32 ? RTLIB::FPTOSINT_F128_I32 : RTLIB::FPTOSINT_F128_I64;
2527 return TLI.LowerF128Op(Op, DAG, LibFunc, numArgs: 1);
2528 }
2529
2530 // Expand if the resulting type is illegal.
2531 if (!TLI.isTypeLegal(VT))
2532 return SDValue();
2533
2534 // Otherwise, Convert the fp value to integer in an FP register.
2535 if (VT == MVT::i32)
2536 Op = DAG.getNode(Opcode: SPISD::FTOI, DL: dl, VT: MVT::f32, Operand: Op.getOperand(i: 0));
2537 else
2538 Op = DAG.getNode(Opcode: SPISD::FTOX, DL: dl, VT: MVT::f64, Operand: Op.getOperand(i: 0));
2539
2540 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT, Operand: Op);
2541}
2542
2543static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2544 const SparcTargetLowering &TLI,
2545 bool hasHardQuad) {
2546 SDLoc dl(Op);
2547 EVT OpVT = Op.getOperand(i: 0).getValueType();
2548 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2549
2550 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2551
2552 // Expand f128 operations to fp128 ABI calls.
2553 if (Op.getValueType() == MVT::f128
2554 && (!hasHardQuad || !TLI.isTypeLegal(VT: OpVT))) {
2555 RTLIB::Libcall LibFunc =
2556 OpVT == MVT::i32 ? RTLIB::SINTTOFP_I32_F128 : RTLIB::SINTTOFP_I64_F128;
2557 return TLI.LowerF128Op(Op, DAG, LibFunc, numArgs: 1);
2558 }
2559
2560 // Expand if the operand type is illegal.
2561 if (!TLI.isTypeLegal(VT: OpVT))
2562 return SDValue();
2563
2564 // Otherwise, Convert the int value to FP in an FP register.
2565 SDValue Tmp = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: floatVT, Operand: Op.getOperand(i: 0));
2566 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2567 return DAG.getNode(Opcode: opcode, DL: dl, VT: Op.getValueType(), Operand: Tmp);
2568}
2569
2570static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2571 const SparcTargetLowering &TLI,
2572 bool hasHardQuad) {
2573 EVT VT = Op.getValueType();
2574
2575 // Expand if it does not involve f128 or the target has support for
2576 // quad floating point instructions and the resulting type is legal.
2577 if (Op.getOperand(i: 0).getValueType() != MVT::f128 ||
2578 (hasHardQuad && TLI.isTypeLegal(VT)))
2579 return SDValue();
2580
2581 assert(VT == MVT::i32 || VT == MVT::i64);
2582
2583 return TLI.LowerF128Op(
2584 Op, DAG,
2585 LibFunc: VT == MVT::i32 ? RTLIB::FPTOUINT_F128_I32 : RTLIB::FPTOUINT_F128_I64, numArgs: 1);
2586}
2587
2588static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2589 const SparcTargetLowering &TLI,
2590 bool hasHardQuad) {
2591 EVT OpVT = Op.getOperand(i: 0).getValueType();
2592 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2593
2594 // Expand if it does not involve f128 or the target has support for
2595 // quad floating point instructions and the operand type is legal.
2596 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(VT: OpVT)))
2597 return SDValue();
2598
2599 return TLI.LowerF128Op(Op, DAG,
2600 LibFunc: OpVT == MVT::i32 ? RTLIB::UINTTOFP_I32_F128
2601 : RTLIB::UINTTOFP_I64_F128,
2602 numArgs: 1);
2603}
2604
2605static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2606 const SparcTargetLowering &TLI, bool hasHardQuad,
2607 bool isV9, bool is64Bit) {
2608 SDValue Chain = Op.getOperand(i: 0);
2609 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 1))->get();
2610 SDValue LHS = Op.getOperand(i: 2);
2611 SDValue RHS = Op.getOperand(i: 3);
2612 SDValue Dest = Op.getOperand(i: 4);
2613 SDLoc dl(Op);
2614 unsigned Opc, SPCC = ~0U;
2615
2616 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2617 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2618 LookThroughSetCC(LHS, RHS, CC, SPCC);
2619 assert(LHS.getValueType() == RHS.getValueType());
2620
2621 // Get the condition flag.
2622 SDValue CompareFlag;
2623 if (LHS.getValueType().isInteger()) {
2624 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2625 // and the RHS is zero we might be able to use a specialized branch.
2626 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2627 isNullConstant(V: RHS) && !ISD::isUnsignedIntSetCC(Code: CC))
2628 return DAG.getNode(Opcode: SPISD::BR_REG, DL: dl, VT: MVT::Other, N1: Chain, N2: Dest,
2629 N3: DAG.getConstant(Val: intCondCCodeToRcond(CC), DL: dl, VT: MVT::i32),
2630 N4: LHS);
2631
2632 CompareFlag = DAG.getNode(Opcode: SPISD::CMPICC, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2633 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2634 if (isV9)
2635 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2636 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BPICC : SPISD::BPXCC;
2637 else
2638 // Non-v9 targets don't have xcc.
2639 Opc = SPISD::BRICC;
2640 } else {
2641 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2642 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2643 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, DL: dl, DAG);
2644 Opc = isV9 ? SPISD::BPICC : SPISD::BRICC;
2645 } else {
2646 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2647 CompareFlag = DAG.getNode(Opcode: CmpOpc, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2648 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2649 Opc = isV9 ? SPISD::BRFCC_V9 : SPISD::BRFCC;
2650 }
2651 }
2652 return DAG.getNode(Opcode: Opc, DL: dl, VT: MVT::Other, N1: Chain, N2: Dest,
2653 N3: DAG.getConstant(Val: SPCC, DL: dl, VT: MVT::i32), N4: CompareFlag);
2654}
2655
2656static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2657 const SparcTargetLowering &TLI, bool hasHardQuad,
2658 bool isV9, bool is64Bit) {
2659 SDValue LHS = Op.getOperand(i: 0);
2660 SDValue RHS = Op.getOperand(i: 1);
2661 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 4))->get();
2662 SDValue TrueVal = Op.getOperand(i: 2);
2663 SDValue FalseVal = Op.getOperand(i: 3);
2664 SDLoc dl(Op);
2665 unsigned Opc, SPCC = ~0U;
2666
2667 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2668 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2669 LookThroughSetCC(LHS, RHS, CC, SPCC);
2670 assert(LHS.getValueType() == RHS.getValueType());
2671
2672 SDValue CompareFlag;
2673 if (LHS.getValueType().isInteger()) {
2674 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2675 // and the RHS is zero we might be able to use a specialized select.
2676 // All SELECT_CC between any two scalar integer types are eligible for
2677 // lowering to specialized instructions. Additionally, f32 and f64 types
2678 // are also eligible, but for f128 we can only use the specialized
2679 // instruction when we have hardquad.
2680 EVT ValType = TrueVal.getValueType();
2681 bool IsEligibleType = ValType.isScalarInteger() || ValType == MVT::f32 ||
2682 ValType == MVT::f64 ||
2683 (ValType == MVT::f128 && hasHardQuad);
2684 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2685 isNullConstant(V: RHS) && !ISD::isUnsignedIntSetCC(Code: CC) && IsEligibleType)
2686 return DAG.getNode(
2687 Opcode: SPISD::SELECT_REG, DL: dl, VT: TrueVal.getValueType(), N1: TrueVal, N2: FalseVal,
2688 N3: DAG.getConstant(Val: intCondCCodeToRcond(CC), DL: dl, VT: MVT::i32), N4: LHS);
2689
2690 CompareFlag = DAG.getNode(Opcode: SPISD::CMPICC, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2691 Opc = LHS.getValueType() == MVT::i32 ?
2692 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2693 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2694 } else {
2695 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2696 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2697 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, DL: dl, DAG);
2698 Opc = SPISD::SELECT_ICC;
2699 } else {
2700 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2701 CompareFlag = DAG.getNode(Opcode: CmpOpc, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2702 Opc = SPISD::SELECT_FCC;
2703 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2704 }
2705 }
2706 return DAG.getNode(Opcode: Opc, DL: dl, VT: TrueVal.getValueType(), N1: TrueVal, N2: FalseVal,
2707 N3: DAG.getConstant(Val: SPCC, DL: dl, VT: MVT::i32), N4: CompareFlag);
2708}
2709
2710static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2711 const SparcTargetLowering &TLI) {
2712 MachineFunction &MF = DAG.getMachineFunction();
2713 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2714 auto PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
2715
2716 // Need frame address to find the address of VarArgsFrameIndex.
2717 MF.getFrameInfo().setFrameAddressIsTaken(true);
2718
2719 // vastart just stores the address of the VarArgsFrameIndex slot into the
2720 // memory location argument.
2721 SDLoc DL(Op);
2722 SDValue Offset =
2723 DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: DAG.getRegister(Reg: SP::I6, VT: PtrVT),
2724 N2: DAG.getIntPtrConstant(Val: FuncInfo->getVarArgsFrameOffset(), DL));
2725 const Value *SV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 2))->getValue();
2726 return DAG.getStore(Chain: Op.getOperand(i: 0), dl: DL, Val: Offset, Ptr: Op.getOperand(i: 1),
2727 PtrInfo: MachinePointerInfo(SV));
2728}
2729
2730static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2731 SDNode *Node = Op.getNode();
2732 EVT VT = Node->getValueType(ResNo: 0);
2733 SDValue InChain = Node->getOperand(Num: 0);
2734 SDValue VAListPtr = Node->getOperand(Num: 1);
2735 EVT PtrVT = VAListPtr.getValueType();
2736 const Value *SV = cast<SrcValueSDNode>(Val: Node->getOperand(Num: 2))->getValue();
2737 SDLoc DL(Node);
2738 SDValue VAList =
2739 DAG.getLoad(VT: PtrVT, dl: DL, Chain: InChain, Ptr: VAListPtr, PtrInfo: MachinePointerInfo(SV));
2740 // Increment the pointer, VAList, to the next vaarg.
2741 SDValue NextPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: VAList,
2742 N2: DAG.getIntPtrConstant(Val: VT.getSizeInBits()/8,
2743 DL));
2744 // Store the incremented VAList to the legalized pointer.
2745 InChain = DAG.getStore(Chain: VAList.getValue(R: 1), dl: DL, Val: NextPtr, Ptr: VAListPtr,
2746 PtrInfo: MachinePointerInfo(SV));
2747 // Load the actual argument out of the pointer VAList.
2748 // We can't count on greater alignment than the word size.
2749 return DAG.getLoad(
2750 VT, dl: DL, Chain: InChain, Ptr: VAList, PtrInfo: MachinePointerInfo(),
2751 Alignment: Align(std::min(a: PtrVT.getFixedSizeInBits(), b: VT.getFixedSizeInBits()) / 8));
2752}
2753
2754static SDValue LowerSTACKADDRESS(SDValue Op, SelectionDAG &DAG,
2755 const SparcSubtarget &Subtarget) {
2756 SDValue Chain = Op.getOperand(i: 0);
2757 EVT VT = Op->getValueType(ResNo: 0);
2758 SDLoc DL(Op);
2759
2760 MCRegister SPReg = SP::O6;
2761 SDValue SP = DAG.getCopyFromReg(Chain, dl: DL, Reg: SPReg, VT);
2762
2763 // Unbias the stack pointer register.
2764 unsigned OffsetToStackStart = Subtarget.getStackPointerBias();
2765 // Move past the register save area: 8 in registers + 8 local registers.
2766 OffsetToStackStart += 16 * (Subtarget.is64Bit() ? 8 : 4);
2767 // Move past the struct return address slot (4 bytes) on SPARC 32-bit.
2768 if (!Subtarget.is64Bit())
2769 OffsetToStackStart += 4;
2770
2771 SDValue StackAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: SP,
2772 N2: DAG.getConstant(Val: OffsetToStackStart, DL, VT));
2773 return DAG.getMergeValues(Ops: {StackAddr, Chain}, dl: DL);
2774}
2775
2776static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2777 const SparcSubtarget *Subtarget) {
2778 SDValue Chain = Op.getOperand(i: 0);
2779 SDValue Size = Op.getOperand(i: 1);
2780 SDValue Alignment = Op.getOperand(i: 2);
2781 MaybeAlign MaybeAlignment =
2782 cast<ConstantSDNode>(Val&: Alignment)->getMaybeAlignValue();
2783 EVT VT = Size->getValueType(ResNo: 0);
2784 SDLoc dl(Op);
2785
2786 unsigned SPReg = SP::O6;
2787 SDValue SP = DAG.getCopyFromReg(Chain, dl, Reg: SPReg, VT);
2788
2789 // The resultant pointer needs to be above the register spill area
2790 // at the bottom of the stack.
2791 unsigned regSpillArea;
2792 if (Subtarget->is64Bit()) {
2793 regSpillArea = 128;
2794 } else {
2795 // On Sparc32, the size of the spill area is 92. Unfortunately,
2796 // that's only 4-byte aligned, not 8-byte aligned (the stack
2797 // pointer is 8-byte aligned). So, if the user asked for an 8-byte
2798 // aligned dynamic allocation, we actually need to add 96 to the
2799 // bottom of the stack, instead of 92, to ensure 8-byte alignment.
2800
2801 // That also means adding 4 to the size of the allocation --
2802 // before applying the 8-byte rounding. Unfortunately, we the
2803 // value we get here has already had rounding applied. So, we need
2804 // to add 8, instead, wasting a bit more memory.
2805
2806 // Further, this only actually needs to be done if the required
2807 // alignment is > 4, but, we've lost that info by this point, too,
2808 // so we always apply it.
2809
2810 // (An alternative approach would be to always reserve 96 bytes
2811 // instead of the required 92, but then we'd waste 4 extra bytes
2812 // in every frame, not just those with dynamic stack allocations)
2813
2814 // TODO: modify code in SelectionDAGBuilder to make this less sad.
2815
2816 Size = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: Size,
2817 N2: DAG.getConstant(Val: 8, DL: dl, VT));
2818 regSpillArea = 96;
2819 }
2820
2821 int64_t Bias = Subtarget->getStackPointerBias();
2822
2823 // Debias and increment SP past the reserved spill area.
2824 // We need the SP to point to the first usable region before calculating
2825 // anything to prevent any of the pointers from becoming out of alignment when
2826 // we rebias the SP later on.
2827 SDValue StartOfUsableStack = DAG.getNode(
2828 Opcode: ISD::ADD, DL: dl, VT, N1: SP, N2: DAG.getConstant(Val: regSpillArea + Bias, DL: dl, VT));
2829 SDValue AllocatedPtr =
2830 DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: StartOfUsableStack, N2: Size);
2831
2832 bool IsOveraligned = MaybeAlignment.has_value();
2833 SDValue AlignedPtr =
2834 IsOveraligned
2835 ? DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: AllocatedPtr,
2836 N2: DAG.getSignedConstant(Val: -MaybeAlignment->value(), DL: dl, VT))
2837 : AllocatedPtr;
2838
2839 // Now that we are done, restore the bias and reserved spill area.
2840 SDValue NewSP = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: AlignedPtr,
2841 N2: DAG.getConstant(Val: regSpillArea + Bias, DL: dl, VT));
2842 Chain = DAG.getCopyToReg(Chain: SP.getValue(R: 1), dl, Reg: SPReg, N: NewSP);
2843 SDValue Ops[2] = {AlignedPtr, Chain};
2844 return DAG.getMergeValues(Ops, dl);
2845}
2846
2847
2848static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2849 SDLoc dl(Op);
2850 SDValue Chain = DAG.getNode(Opcode: SPISD::FLUSHW,
2851 DL: dl, VT: MVT::Other, Operand: DAG.getEntryNode());
2852 return Chain;
2853}
2854
2855static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2856 const SparcSubtarget *Subtarget,
2857 bool AlwaysFlush = false) {
2858 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2859 MFI.setFrameAddressIsTaken(true);
2860
2861 EVT VT = Op.getValueType();
2862 SDLoc dl(Op);
2863 unsigned FrameReg = SP::I6;
2864 unsigned stackBias = Subtarget->getStackPointerBias();
2865
2866 SDValue FrameAddr;
2867 SDValue Chain;
2868
2869 // flush first to make sure the windowed registers' values are in stack
2870 Chain = (depth || AlwaysFlush) ? getFLUSHW(Op, DAG) : DAG.getEntryNode();
2871
2872 FrameAddr = DAG.getCopyFromReg(Chain, dl, Reg: FrameReg, VT);
2873
2874 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2875
2876 while (depth--) {
2877 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: FrameAddr,
2878 N2: DAG.getIntPtrConstant(Val: Offset, DL: dl));
2879 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, PtrInfo: MachinePointerInfo());
2880 }
2881 if (Subtarget->is64Bit())
2882 FrameAddr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: FrameAddr,
2883 N2: DAG.getIntPtrConstant(Val: stackBias, DL: dl));
2884 return FrameAddr;
2885}
2886
2887
2888static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2889 const SparcSubtarget *Subtarget) {
2890
2891 uint64_t depth = Op.getConstantOperandVal(i: 0);
2892
2893 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2894
2895}
2896
2897static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2898 const SparcTargetLowering &TLI,
2899 const SparcSubtarget *Subtarget) {
2900 MachineFunction &MF = DAG.getMachineFunction();
2901 MachineFrameInfo &MFI = MF.getFrameInfo();
2902 MFI.setReturnAddressIsTaken(true);
2903
2904 EVT VT = Op.getValueType();
2905 SDLoc dl(Op);
2906 uint64_t depth = Op.getConstantOperandVal(i: 0);
2907
2908 SDValue RetAddr;
2909 if (depth == 0) {
2910 auto PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
2911 Register RetReg = MF.addLiveIn(PReg: SP::I7, RC: TLI.getRegClassFor(VT: PtrVT));
2912 RetAddr = DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl, Reg: RetReg, VT);
2913 return RetAddr;
2914 }
2915
2916 // Need frame address to find return address of the caller.
2917 SDValue FrameAddr = getFRAMEADDR(depth: depth - 1, Op, DAG, Subtarget, AlwaysFlush: true);
2918
2919 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2920 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD,
2921 DL: dl, VT,
2922 N1: FrameAddr,
2923 N2: DAG.getIntPtrConstant(Val: Offset, DL: dl));
2924 RetAddr = DAG.getLoad(VT, dl, Chain: DAG.getEntryNode(), Ptr, PtrInfo: MachinePointerInfo());
2925
2926 return RetAddr;
2927}
2928
2929static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG,
2930 unsigned opcode) {
2931 assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2932 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2933
2934 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2935 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2936 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2937
2938 // Note: in little-endian, the floating-point value is stored in the
2939 // registers are in the opposite order, so the subreg with the sign
2940 // bit is the highest-numbered (odd), rather than the
2941 // lowest-numbered (even).
2942
2943 SDValue Hi32 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_even, DL: dl, VT: MVT::f32,
2944 Operand: SrcReg64);
2945 SDValue Lo32 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_odd, DL: dl, VT: MVT::f32,
2946 Operand: SrcReg64);
2947
2948 if (DAG.getDataLayout().isLittleEndian())
2949 Lo32 = DAG.getNode(Opcode: opcode, DL: dl, VT: MVT::f32, Operand: Lo32);
2950 else
2951 Hi32 = DAG.getNode(Opcode: opcode, DL: dl, VT: MVT::f32, Operand: Hi32);
2952
2953 SDValue DstReg64 = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
2954 dl, VT: MVT::f64), 0);
2955 DstReg64 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_even, DL: dl, VT: MVT::f64,
2956 Operand: DstReg64, Subreg: Hi32);
2957 DstReg64 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_odd, DL: dl, VT: MVT::f64,
2958 Operand: DstReg64, Subreg: Lo32);
2959 return DstReg64;
2960}
2961
2962// Lower a f128 load into two f64 loads.
2963static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2964{
2965 SDLoc dl(Op);
2966 LoadSDNode *LdNode = cast<LoadSDNode>(Val: Op.getNode());
2967 assert(LdNode->getOffset().isUndef() && "Unexpected node type");
2968
2969 Align Alignment = commonAlignment(A: LdNode->getBaseAlign(), Offset: 8);
2970
2971 SDValue Hi64 =
2972 DAG.getLoad(VT: MVT::f64, dl, Chain: LdNode->getChain(), Ptr: LdNode->getBasePtr(),
2973 PtrInfo: LdNode->getPointerInfo(), Alignment);
2974 EVT addrVT = LdNode->getBasePtr().getValueType();
2975 SDValue LoPtr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: addrVT,
2976 N1: LdNode->getBasePtr(),
2977 N2: DAG.getConstant(Val: 8, DL: dl, VT: addrVT));
2978 SDValue Lo64 = DAG.getLoad(VT: MVT::f64, dl, Chain: LdNode->getChain(), Ptr: LoPtr,
2979 PtrInfo: LdNode->getPointerInfo().getWithOffset(O: 8),
2980 Alignment);
2981
2982 SDValue SubRegEven = DAG.getTargetConstant(Val: SP::sub_even64, DL: dl, VT: MVT::i32);
2983 SDValue SubRegOdd = DAG.getTargetConstant(Val: SP::sub_odd64, DL: dl, VT: MVT::i32);
2984
2985 SDNode *InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
2986 dl, VT: MVT::f128);
2987 InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl,
2988 VT: MVT::f128,
2989 Op1: SDValue(InFP128, 0),
2990 Op2: Hi64,
2991 Op3: SubRegEven);
2992 InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl,
2993 VT: MVT::f128,
2994 Op1: SDValue(InFP128, 0),
2995 Op2: Lo64,
2996 Op3: SubRegOdd);
2997 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2998 SDValue(Lo64.getNode(), 1) };
2999 SDValue OutChain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
3000 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
3001 return DAG.getMergeValues(Ops, dl);
3002}
3003
3004static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
3005{
3006 LoadSDNode *LdNode = cast<LoadSDNode>(Val: Op.getNode());
3007
3008 EVT MemVT = LdNode->getMemoryVT();
3009 if (MemVT == MVT::f128)
3010 return LowerF128Load(Op, DAG);
3011
3012 return Op;
3013}
3014
3015// Lower a f128 store into two f64 stores.
3016static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
3017 SDLoc dl(Op);
3018 StoreSDNode *StNode = cast<StoreSDNode>(Val: Op.getNode());
3019 assert(StNode->getOffset().isUndef() && "Unexpected node type");
3020
3021 SDValue SubRegEven = DAG.getTargetConstant(Val: SP::sub_even64, DL: dl, VT: MVT::i32);
3022 SDValue SubRegOdd = DAG.getTargetConstant(Val: SP::sub_odd64, DL: dl, VT: MVT::i32);
3023
3024 SDNode *Hi64 = DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG,
3025 dl,
3026 VT: MVT::f64,
3027 Op1: StNode->getValue(),
3028 Op2: SubRegEven);
3029 SDNode *Lo64 = DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG,
3030 dl,
3031 VT: MVT::f64,
3032 Op1: StNode->getValue(),
3033 Op2: SubRegOdd);
3034
3035 Align Alignment = commonAlignment(A: StNode->getBaseAlign(), Offset: 8);
3036
3037 SDValue OutChains[2];
3038 OutChains[0] =
3039 DAG.getStore(Chain: StNode->getChain(), dl, Val: SDValue(Hi64, 0),
3040 Ptr: StNode->getBasePtr(), PtrInfo: StNode->getPointerInfo(),
3041 Alignment);
3042 EVT addrVT = StNode->getBasePtr().getValueType();
3043 SDValue LoPtr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: addrVT,
3044 N1: StNode->getBasePtr(),
3045 N2: DAG.getConstant(Val: 8, DL: dl, VT: addrVT));
3046 OutChains[1] = DAG.getStore(Chain: StNode->getChain(), dl, Val: SDValue(Lo64, 0), Ptr: LoPtr,
3047 PtrInfo: StNode->getPointerInfo().getWithOffset(O: 8),
3048 Alignment);
3049 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
3050}
3051
3052static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
3053{
3054 SDLoc dl(Op);
3055 StoreSDNode *St = cast<StoreSDNode>(Val: Op.getNode());
3056
3057 EVT MemVT = St->getMemoryVT();
3058 if (MemVT == MVT::f128)
3059 return LowerF128Store(Op, DAG);
3060
3061 if (MemVT == MVT::i64) {
3062 // Custom handling for i64 stores: turn it into a bitcast and a
3063 // v2i32 store.
3064 SDValue Val = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::v2i32, Operand: St->getValue());
3065 SDValue Chain = DAG.getStore(
3066 Chain: St->getChain(), dl, Val, Ptr: St->getBasePtr(), PtrInfo: St->getPointerInfo(),
3067 Alignment: St->getBaseAlign(), MMOFlags: St->getMemOperand()->getFlags(), AAInfo: St->getAAInfo());
3068 return Chain;
3069 }
3070
3071 return SDValue();
3072}
3073
3074static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
3075 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
3076 && "invalid opcode");
3077
3078 SDLoc dl(Op);
3079
3080 if (Op.getValueType() == MVT::f64)
3081 return LowerF64Op(SrcReg64: Op.getOperand(i: 0), dl, DAG, opcode: Op.getOpcode());
3082 if (Op.getValueType() != MVT::f128)
3083 return Op;
3084
3085 // Lower fabs/fneg on f128 to fabs/fneg on f64
3086 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
3087 // (As with LowerF64Op, on little-endian, we need to negate the odd
3088 // subreg)
3089
3090 SDValue SrcReg128 = Op.getOperand(i: 0);
3091 SDValue Hi64 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_even64, DL: dl, VT: MVT::f64,
3092 Operand: SrcReg128);
3093 SDValue Lo64 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_odd64, DL: dl, VT: MVT::f64,
3094 Operand: SrcReg128);
3095
3096 if (DAG.getDataLayout().isLittleEndian()) {
3097 if (isV9)
3098 Lo64 = DAG.getNode(Opcode: Op.getOpcode(), DL: dl, VT: MVT::f64, Operand: Lo64);
3099 else
3100 Lo64 = LowerF64Op(SrcReg64: Lo64, dl, DAG, opcode: Op.getOpcode());
3101 } else {
3102 if (isV9)
3103 Hi64 = DAG.getNode(Opcode: Op.getOpcode(), DL: dl, VT: MVT::f64, Operand: Hi64);
3104 else
3105 Hi64 = LowerF64Op(SrcReg64: Hi64, dl, DAG, opcode: Op.getOpcode());
3106 }
3107
3108 SDValue DstReg128 = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
3109 dl, VT: MVT::f128), 0);
3110 DstReg128 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_even64, DL: dl, VT: MVT::f128,
3111 Operand: DstReg128, Subreg: Hi64);
3112 DstReg128 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_odd64, DL: dl, VT: MVT::f128,
3113 Operand: DstReg128, Subreg: Lo64);
3114 return DstReg128;
3115}
3116
3117static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
3118 if (isStrongerThanMonotonic(AO: cast<AtomicSDNode>(Val&: Op)->getSuccessOrdering())) {
3119 // Expand with a fence.
3120 return SDValue();
3121 }
3122
3123 // Monotonic load/stores are legal.
3124 return Op;
3125}
3126
3127SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
3128 SelectionDAG &DAG) const {
3129 unsigned IntNo = Op.getConstantOperandVal(i: 0);
3130 switch (IntNo) {
3131 default: return SDValue(); // Don't custom lower most intrinsics.
3132 case Intrinsic::thread_pointer: {
3133 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
3134 return DAG.getRegister(Reg: SP::G7, VT: PtrVT);
3135 }
3136 }
3137}
3138
3139SDValue SparcTargetLowering::
3140LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3141
3142 bool hasHardQuad = Subtarget->hasHardQuad();
3143 bool isV9 = Subtarget->isV9();
3144 bool is64Bit = Subtarget->is64Bit();
3145
3146 switch (Op.getOpcode()) {
3147 default: llvm_unreachable("Should not custom lower this!");
3148
3149 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, TLI: *this,
3150 Subtarget);
3151 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
3152 Subtarget);
3153 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3154 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3155 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3156 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3157 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, TLI: *this,
3158 hasHardQuad);
3159 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, TLI: *this,
3160 hasHardQuad);
3161 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, TLI: *this,
3162 hasHardQuad);
3163 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, TLI: *this,
3164 hasHardQuad);
3165 case ISD::BR_CC:
3166 return LowerBR_CC(Op, DAG, TLI: *this, hasHardQuad, isV9, is64Bit);
3167 case ISD::SELECT_CC:
3168 return LowerSELECT_CC(Op, DAG, TLI: *this, hasHardQuad, isV9, is64Bit);
3169 case ISD::VASTART: return LowerVASTART(Op, DAG, TLI: *this);
3170 case ISD::VAARG: return LowerVAARG(Op, DAG);
3171 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
3172 Subtarget);
3173 case ISD::STACKADDRESS:
3174 return LowerSTACKADDRESS(Op, DAG, Subtarget: *Subtarget);
3175
3176 case ISD::LOAD: return LowerLOAD(Op, DAG);
3177 case ISD::STORE: return LowerSTORE(Op, DAG);
3178 case ISD::FADD:
3179 return LowerF128Op(Op, DAG, LibFunc: RTLIB::ADD_F128, numArgs: 2);
3180 case ISD::FSUB:
3181 return LowerF128Op(Op, DAG, LibFunc: RTLIB::SUB_F128, numArgs: 2);
3182 case ISD::FMUL:
3183 return LowerF128Op(Op, DAG, LibFunc: RTLIB::MUL_F128, numArgs: 2);
3184 case ISD::FDIV:
3185 return LowerF128Op(Op, DAG, LibFunc: RTLIB::DIV_F128, numArgs: 2);
3186 case ISD::FSQRT:
3187 return LowerF128Op(Op, DAG, LibFunc: RTLIB::SQRT_F128, numArgs: 1);
3188 case ISD::FABS:
3189 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
3190 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, TLI: *this);
3191 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, TLI: *this);
3192 case ISD::ATOMIC_LOAD:
3193 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
3194 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3195 }
3196}
3197
3198SDValue SparcTargetLowering::bitcastConstantFPToInt(ConstantFPSDNode *C,
3199 const SDLoc &DL,
3200 SelectionDAG &DAG) const {
3201 APInt V = C->getValueAPF().bitcastToAPInt();
3202 SDValue Lo = DAG.getConstant(Val: V.zextOrTrunc(width: 32), DL, VT: MVT::i32);
3203 SDValue Hi = DAG.getConstant(Val: V.lshr(shiftAmt: 32).zextOrTrunc(width: 32), DL, VT: MVT::i32);
3204 if (DAG.getDataLayout().isLittleEndian())
3205 std::swap(a&: Lo, b&: Hi);
3206 return DAG.getBuildVector(VT: MVT::v2i32, DL, Ops: {Hi, Lo});
3207}
3208
3209SDValue SparcTargetLowering::PerformBITCASTCombine(SDNode *N,
3210 DAGCombinerInfo &DCI) const {
3211 SDLoc dl(N);
3212 SDValue Src = N->getOperand(Num: 0);
3213
3214 if (isa<ConstantFPSDNode>(Val: Src) && N->getSimpleValueType(ResNo: 0) == MVT::v2i32 &&
3215 Src.getSimpleValueType() == MVT::f64)
3216 return bitcastConstantFPToInt(C: cast<ConstantFPSDNode>(Val&: Src), DL: dl, DAG&: DCI.DAG);
3217
3218 return SDValue();
3219}
3220
3221SDValue SparcTargetLowering::PerformDAGCombine(SDNode *N,
3222 DAGCombinerInfo &DCI) const {
3223 switch (N->getOpcode()) {
3224 default:
3225 break;
3226 case ISD::BITCAST:
3227 return PerformBITCASTCombine(N, DCI);
3228 }
3229 return SDValue();
3230}
3231
3232MachineBasicBlock *
3233SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3234 MachineBasicBlock *BB) const {
3235 switch (MI.getOpcode()) {
3236 default: llvm_unreachable("Unknown SELECT_CC!");
3237 case SP::SELECT_CC_Int_ICC:
3238 case SP::SELECT_CC_FP_ICC:
3239 case SP::SELECT_CC_DFP_ICC:
3240 case SP::SELECT_CC_QFP_ICC:
3241 if (Subtarget->isV9())
3242 return expandSelectCC(MI, BB, BROpcode: SP::BPICC);
3243 return expandSelectCC(MI, BB, BROpcode: SP::BCOND);
3244 case SP::SELECT_CC_Int_XCC:
3245 case SP::SELECT_CC_FP_XCC:
3246 case SP::SELECT_CC_DFP_XCC:
3247 case SP::SELECT_CC_QFP_XCC:
3248 return expandSelectCC(MI, BB, BROpcode: SP::BPXCC);
3249 case SP::SELECT_CC_Int_FCC:
3250 case SP::SELECT_CC_FP_FCC:
3251 case SP::SELECT_CC_DFP_FCC:
3252 case SP::SELECT_CC_QFP_FCC:
3253 if (Subtarget->isV9())
3254 return expandSelectCC(MI, BB, BROpcode: SP::FBCOND_V9);
3255 return expandSelectCC(MI, BB, BROpcode: SP::FBCOND);
3256 }
3257}
3258
3259MachineBasicBlock *
3260SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
3261 unsigned BROpcode) const {
3262 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
3263 DebugLoc dl = MI.getDebugLoc();
3264 unsigned CC = (SPCC::CondCodes)MI.getOperand(i: 3).getImm();
3265
3266 // To "insert" a SELECT_CC instruction, we actually have to insert the
3267 // triangle control-flow pattern. The incoming instruction knows the
3268 // destination vreg to set, the condition code register to branch on, the
3269 // true/false values to select between, and the condition code for the branch.
3270 //
3271 // We produce the following control flow:
3272 // ThisMBB
3273 // | \
3274 // | IfFalseMBB
3275 // | /
3276 // SinkMBB
3277 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3278 MachineFunction::iterator It = ++BB->getIterator();
3279
3280 MachineBasicBlock *ThisMBB = BB;
3281 MachineFunction *F = BB->getParent();
3282 MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
3283 MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
3284 F->insert(MBBI: It, MBB: IfFalseMBB);
3285 F->insert(MBBI: It, MBB: SinkMBB);
3286
3287 // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
3288 SinkMBB->splice(Where: SinkMBB->begin(), Other: ThisMBB,
3289 From: std::next(x: MachineBasicBlock::iterator(MI)), To: ThisMBB->end());
3290 SinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: ThisMBB);
3291
3292 // Set the new successors for ThisMBB.
3293 ThisMBB->addSuccessor(Succ: IfFalseMBB);
3294 ThisMBB->addSuccessor(Succ: SinkMBB);
3295
3296 BuildMI(BB: ThisMBB, MIMD: dl, MCID: TII.get(Opcode: BROpcode))
3297 .addMBB(MBB: SinkMBB)
3298 .addImm(Val: CC);
3299
3300 // IfFalseMBB just falls through to SinkMBB.
3301 IfFalseMBB->addSuccessor(Succ: SinkMBB);
3302
3303 // %Result = phi [ %TrueValue, ThisMBB ], [ %FalseValue, IfFalseMBB ]
3304 BuildMI(BB&: *SinkMBB, I: SinkMBB->begin(), MIMD: dl, MCID: TII.get(Opcode: SP::PHI),
3305 DestReg: MI.getOperand(i: 0).getReg())
3306 .addReg(RegNo: MI.getOperand(i: 1).getReg())
3307 .addMBB(MBB: ThisMBB)
3308 .addReg(RegNo: MI.getOperand(i: 2).getReg())
3309 .addMBB(MBB: IfFalseMBB);
3310
3311 MI.eraseFromParent(); // The pseudo instruction is gone now.
3312 return SinkMBB;
3313}
3314
3315//===----------------------------------------------------------------------===//
3316// Sparc Inline Assembly Support
3317//===----------------------------------------------------------------------===//
3318
3319/// getConstraintType - Given a constraint letter, return the type of
3320/// constraint it is for this target.
3321SparcTargetLowering::ConstraintType
3322SparcTargetLowering::getConstraintType(StringRef Constraint) const {
3323 if (Constraint.size() == 1) {
3324 switch (Constraint[0]) {
3325 default: break;
3326 case 'r':
3327 case 'f':
3328 case 'e':
3329 return C_RegisterClass;
3330 case 'I': // SIMM13
3331 return C_Immediate;
3332 }
3333 }
3334
3335 return TargetLowering::getConstraintType(Constraint);
3336}
3337
3338TargetLowering::ConstraintWeight SparcTargetLowering::
3339getSingleConstraintMatchWeight(AsmOperandInfo &info,
3340 const char *constraint) const {
3341 ConstraintWeight weight = CW_Invalid;
3342 Value *CallOperandVal = info.CallOperandVal;
3343 // If we don't have a value, we can't do a match,
3344 // but allow it at the lowest weight.
3345 if (!CallOperandVal)
3346 return CW_Default;
3347
3348 // Look at the constraint type.
3349 switch (*constraint) {
3350 default:
3351 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3352 break;
3353 case 'I': // SIMM13
3354 if (ConstantInt *C = dyn_cast<ConstantInt>(Val: info.CallOperandVal)) {
3355 if (isInt<13>(x: C->getSExtValue()))
3356 weight = CW_Constant;
3357 }
3358 break;
3359 }
3360 return weight;
3361}
3362
3363/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3364/// vector. If it is invalid, don't add anything to Ops.
3365void SparcTargetLowering::LowerAsmOperandForConstraint(
3366 SDValue Op, StringRef Constraint, std::vector<SDValue> &Ops,
3367 SelectionDAG &DAG) const {
3368 SDValue Result;
3369
3370 // Only support length 1 constraints for now.
3371 if (Constraint.size() > 1)
3372 return;
3373
3374 char ConstraintLetter = Constraint[0];
3375 switch (ConstraintLetter) {
3376 default: break;
3377 case 'I':
3378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
3379 if (isInt<13>(x: C->getSExtValue())) {
3380 Result = DAG.getSignedTargetConstant(Val: C->getSExtValue(), DL: SDLoc(Op),
3381 VT: Op.getValueType());
3382 break;
3383 }
3384 return;
3385 }
3386 }
3387
3388 if (Result.getNode()) {
3389 Ops.push_back(x: Result);
3390 return;
3391 }
3392 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3393}
3394
3395std::pair<unsigned, const TargetRegisterClass *>
3396SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3397 StringRef Constraint,
3398 MVT VT) const {
3399 if (Constraint.empty())
3400 return std::make_pair(x: 0U, y: nullptr);
3401
3402 if (Constraint.size() == 1) {
3403 switch (Constraint[0]) {
3404 case 'r':
3405 if (VT == MVT::v2i32)
3406 return std::make_pair(x: 0U, y: &SP::IntPairRegClass);
3407 else if (Subtarget->is64Bit())
3408 return std::make_pair(x: 0U, y: &SP::I64RegsRegClass);
3409 else
3410 return std::make_pair(x: 0U, y: &SP::IntRegsRegClass);
3411 case 'f':
3412 if (VT == MVT::f32 || VT == MVT::i32)
3413 return std::make_pair(x: 0U, y: &SP::FPRegsRegClass);
3414 else if (VT == MVT::f64 || VT == MVT::i64)
3415 return std::make_pair(x: 0U, y: &SP::LowDFPRegsRegClass);
3416 else if (VT == MVT::f128)
3417 return std::make_pair(x: 0U, y: &SP::LowQFPRegsRegClass);
3418 // This will generate an error message
3419 return std::make_pair(x: 0U, y: nullptr);
3420 case 'e':
3421 if (VT == MVT::f32 || VT == MVT::i32)
3422 return std::make_pair(x: 0U, y: &SP::FPRegsRegClass);
3423 else if (VT == MVT::f64 || VT == MVT::i64 )
3424 return std::make_pair(x: 0U, y: &SP::DFPRegsRegClass);
3425 else if (VT == MVT::f128)
3426 return std::make_pair(x: 0U, y: &SP::QFPRegsRegClass);
3427 // This will generate an error message
3428 return std::make_pair(x: 0U, y: nullptr);
3429 }
3430 }
3431
3432 if (Constraint.front() != '{')
3433 return std::make_pair(x: 0U, y: nullptr);
3434
3435 assert(Constraint.back() == '}' && "Not a brace enclosed constraint?");
3436 StringRef RegName(Constraint.data() + 1, Constraint.size() - 2);
3437 if (RegName.empty())
3438 return std::make_pair(x: 0U, y: nullptr);
3439
3440 unsigned long long RegNo;
3441 // Handle numbered register aliases.
3442 if (RegName[0] == 'r' &&
3443 getAsUnsignedInteger(Str: RegName.begin() + 1, Radix: 10, Result&: RegNo)) {
3444 // r0-r7 -> g0-g7
3445 // r8-r15 -> o0-o7
3446 // r16-r23 -> l0-l7
3447 // r24-r31 -> i0-i7
3448 if (RegNo > 31)
3449 return std::make_pair(x: 0U, y: nullptr);
3450 const char RegTypes[] = {'g', 'o', 'l', 'i'};
3451 char RegType = RegTypes[RegNo / 8];
3452 char RegIndex = '0' + (RegNo % 8);
3453 char Tmp[] = {'{', RegType, RegIndex, '}', 0};
3454 return getRegForInlineAsmConstraint(TRI, Constraint: Tmp, VT);
3455 }
3456
3457 // Rewrite the fN constraint according to the value type if needed.
3458 if (VT != MVT::f32 && VT != MVT::Other && RegName[0] == 'f' &&
3459 getAsUnsignedInteger(Str: RegName.begin() + 1, Radix: 10, Result&: RegNo)) {
3460 if (VT == MVT::f64 && (RegNo % 2 == 0)) {
3461 return getRegForInlineAsmConstraint(
3462 TRI, Constraint: StringRef("{d" + utostr(X: RegNo / 2) + "}"), VT);
3463 } else if (VT == MVT::f128 && (RegNo % 4 == 0)) {
3464 return getRegForInlineAsmConstraint(
3465 TRI, Constraint: StringRef("{q" + utostr(X: RegNo / 4) + "}"), VT);
3466 } else {
3467 return std::make_pair(x: 0U, y: nullptr);
3468 }
3469 }
3470
3471 auto ResultPair =
3472 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3473 if (!ResultPair.second)
3474 return std::make_pair(x: 0U, y: nullptr);
3475
3476 // Force the use of I64Regs over IntRegs for 64-bit values.
3477 if (Subtarget->is64Bit() && VT == MVT::i64) {
3478 assert(ResultPair.second == &SP::IntRegsRegClass &&
3479 "Unexpected register class");
3480 return std::make_pair(x&: ResultPair.first, y: &SP::I64RegsRegClass);
3481 }
3482
3483 return ResultPair;
3484}
3485
3486bool
3487SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3488 // The Sparc target isn't yet aware of offsets.
3489 return false;
3490}
3491
3492void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3493 SmallVectorImpl<SDValue>& Results,
3494 SelectionDAG &DAG) const {
3495
3496 SDLoc dl(N);
3497
3498 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3499
3500 switch (N->getOpcode()) {
3501 default:
3502 llvm_unreachable("Do not know how to custom type legalize this operation!");
3503
3504 case ISD::FP_TO_SINT:
3505 case ISD::FP_TO_UINT:
3506 // Custom lower only if it involves f128 or i64.
3507 if (N->getOperand(Num: 0).getValueType() != MVT::f128
3508 || N->getValueType(ResNo: 0) != MVT::i64)
3509 return;
3510 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3511 ? RTLIB::FPTOSINT_F128_I64
3512 : RTLIB::FPTOUINT_F128_I64);
3513
3514 Results.push_back(Elt: LowerF128Op(Op: SDValue(N, 0), DAG, LibFunc: libCall, numArgs: 1));
3515 return;
3516 case ISD::READCYCLECOUNTER: {
3517 assert(Subtarget->hasLeonCycleCounter());
3518 SDValue Lo = DAG.getCopyFromReg(Chain: N->getOperand(Num: 0), dl, Reg: SP::ASR23, VT: MVT::i32);
3519 SDValue Hi = DAG.getCopyFromReg(Chain: Lo, dl, Reg: SP::G0, VT: MVT::i32);
3520 SDValue Ops[] = { Lo, Hi };
3521 SDValue Pair = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, Ops);
3522 Results.push_back(Elt: Pair);
3523 Results.push_back(Elt: N->getOperand(Num: 0));
3524 return;
3525 }
3526 case ISD::SINT_TO_FP:
3527 case ISD::UINT_TO_FP:
3528 // Custom lower only if it involves f128 or i64.
3529 if (N->getValueType(ResNo: 0) != MVT::f128
3530 || N->getOperand(Num: 0).getValueType() != MVT::i64)
3531 return;
3532
3533 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3534 ? RTLIB::SINTTOFP_I64_F128
3535 : RTLIB::UINTTOFP_I64_F128);
3536
3537 Results.push_back(Elt: LowerF128Op(Op: SDValue(N, 0), DAG, LibFunc: libCall, numArgs: 1));
3538 return;
3539 case ISD::LOAD: {
3540 LoadSDNode *Ld = cast<LoadSDNode>(Val: N);
3541 // Custom handling only for i64: turn i64 load into a v2i32 load,
3542 // and a bitcast.
3543 if (Ld->getValueType(ResNo: 0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64)
3544 return;
3545
3546 SDLoc dl(N);
3547 SDValue LoadRes = DAG.getExtLoad(
3548 ExtType: Ld->getExtensionType(), dl, VT: MVT::v2i32, Chain: Ld->getChain(),
3549 Ptr: Ld->getBasePtr(), PtrInfo: Ld->getPointerInfo(), MemVT: MVT::v2i32, Alignment: Ld->getBaseAlign(),
3550 MMOFlags: Ld->getMemOperand()->getFlags(), AAInfo: Ld->getAAInfo());
3551
3552 SDValue Res = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i64, Operand: LoadRes);
3553 Results.push_back(Elt: Res);
3554 Results.push_back(Elt: LoadRes.getValue(R: 1));
3555 return;
3556 }
3557 }
3558}
3559
3560// Override to enable LOAD_STACK_GUARD lowering on Linux.
3561bool SparcTargetLowering::useLoadStackGuardNode(const Module &M) const {
3562 if (!Subtarget->getTargetTriple().isOSLinux())
3563 return TargetLowering::useLoadStackGuardNode(M);
3564 return true;
3565}
3566
3567bool SparcTargetLowering::isFNegFree(EVT VT) const {
3568 if (Subtarget->isVIS3())
3569 return VT == MVT::f32 || VT == MVT::f64;
3570 return false;
3571}
3572
3573bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
3574 bool ForCodeSize) const {
3575 if (VT != MVT::f32 && VT != MVT::f64)
3576 return false;
3577 if (Subtarget->isVIS() && Imm.isZero())
3578 return true;
3579 if (Subtarget->isVIS3())
3580 return Imm.isExactlyValue(V: +0.5) || Imm.isExactlyValue(V: -0.5) ||
3581 Imm.getExactLog2Abs() == -1;
3582 return false;
3583}
3584
3585bool SparcTargetLowering::isCtlzFast() const { return Subtarget->isVIS3(); }
3586
3587bool SparcTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
3588 // We lack native cttz, however,
3589 // On 64-bit targets it is cheap to implement it in terms of popc.
3590 if (Subtarget->is64Bit() && Subtarget->usePopc())
3591 return true;
3592 // Otherwise, implementing cttz in terms of ctlz is still cheap.
3593 return isCheapToSpeculateCtlz(Ty);
3594}
3595
3596bool SparcTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
3597 EVT VT) const {
3598 return Subtarget->isUA2007() && !Subtarget->useSoftFloat();
3599}
3600
3601void SparcTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
3602 SDNode *Node) const {
3603 assert(MI.getOpcode() == SP::SUBCCrr || MI.getOpcode() == SP::SUBCCri);
3604 // If the result is dead, replace it with %g0.
3605 if (!Node->hasAnyUseOfValue(Value: 0))
3606 MI.getOperand(i: 0).setReg(SP::G0);
3607}
3608
3609Instruction *SparcTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
3610 Instruction *Inst,
3611 AtomicOrdering Ord) const {
3612 bool HasStoreSemantics =
3613 isa<AtomicCmpXchgInst, AtomicRMWInst, StoreInst>(Val: Inst);
3614 if (HasStoreSemantics && isReleaseOrStronger(AO: Ord))
3615 return Builder.CreateFence(Ordering: AtomicOrdering::Release);
3616 return nullptr;
3617}
3618
3619Instruction *SparcTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
3620 Instruction *Inst,
3621 AtomicOrdering Ord) const {
3622 // V8 loads already come with implicit acquire barrier so there's no need to
3623 // emit it again.
3624 bool HasLoadSemantics = isa<AtomicCmpXchgInst, AtomicRMWInst, LoadInst>(Val: Inst);
3625 if (Subtarget->isV9() && HasLoadSemantics && isAcquireOrStronger(AO: Ord))
3626 return Builder.CreateFence(Ordering: AtomicOrdering::Acquire);
3627
3628 // SC plain stores would need a trailing full barrier.
3629 if (isa<StoreInst>(Val: Inst) && Ord == AtomicOrdering::SequentiallyConsistent)
3630 return Builder.CreateFence(Ordering: Ord);
3631 return nullptr;
3632}
3633