1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the interfaces that Sparc uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcISelLowering.h"
15#include "MCTargetDesc/SparcMCTargetDesc.h"
16#include "SparcMachineFunctionInfo.h"
17#include "SparcRegisterInfo.h"
18#include "SparcSelectionDAGInfo.h"
19#include "SparcTargetMachine.h"
20#include "SparcTargetObjectFile.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/ADT/StringSwitch.h"
23#include "llvm/BinaryFormat/ELF.h"
24#include "llvm/CodeGen/CallingConvLower.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/SelectionDAG.h"
30#include "llvm/CodeGen/SelectionDAGNodes.h"
31#include "llvm/CodeGen/TargetLowering.h"
32#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
33#include "llvm/IR/DerivedTypes.h"
34#include "llvm/IR/DiagnosticInfo.h"
35#include "llvm/IR/Function.h"
36#include "llvm/IR/IRBuilder.h"
37#include "llvm/IR/Module.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/KnownBits.h"
40using namespace llvm;
41
42
43//===----------------------------------------------------------------------===//
44// Calling Convention Implementation
45//===----------------------------------------------------------------------===//
46
47static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
48 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
49 ISD::ArgFlagsTy &ArgFlags, CCState &State)
50{
51 assert (ArgFlags.isSRet());
52
53 // Assign SRet argument.
54 State.addLoc(V: CCValAssign::getCustomMem(ValNo, ValVT,
55 Offset: 0,
56 LocVT, HTP: LocInfo));
57 return true;
58}
59
60static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT,
61 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
62 ISD::ArgFlagsTy &ArgFlags, CCState &State)
63{
64 static const MCPhysReg RegList[] = {
65 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
66 };
67 // Try to get first reg.
68 if (Register Reg = State.AllocateReg(Regs: RegList)) {
69 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
70 } else {
71 // Assign whole thing in stack.
72 State.addLoc(V: CCValAssign::getCustomMem(
73 ValNo, ValVT, Offset: State.AllocateStack(Size: 8, Alignment: Align(4)), LocVT, HTP: LocInfo));
74 return true;
75 }
76
77 // Try to get second reg.
78 if (Register Reg = State.AllocateReg(Regs: RegList))
79 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
80 else
81 State.addLoc(V: CCValAssign::getCustomMem(
82 ValNo, ValVT, Offset: State.AllocateStack(Size: 4, Alignment: Align(4)), LocVT, HTP: LocInfo));
83 return true;
84}
85
86static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT,
87 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
88 ISD::ArgFlagsTy &ArgFlags, CCState &State)
89{
90 static const MCPhysReg RegList[] = {
91 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
92 };
93
94 // Try to get first reg.
95 if (Register Reg = State.AllocateReg(Regs: RegList))
96 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
97 else
98 return false;
99
100 // Try to get second reg.
101 if (Register Reg = State.AllocateReg(Regs: RegList))
102 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
103 else
104 return false;
105
106 return true;
107}
108
109// Allocate a full-sized argument for the 64-bit ABI.
110static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT,
111 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
112 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
113 assert((LocVT == MVT::f32 || LocVT == MVT::f128
114 || LocVT.getSizeInBits() == 64) &&
115 "Can't handle non-64 bits locations");
116
117 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
118 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
119 Align alignment =
120 (LocVT == MVT::f128 || ArgFlags.isSplit()) ? Align(16) : Align(8);
121 unsigned Offset = State.AllocateStack(Size: size, Alignment: alignment);
122 unsigned Reg = 0;
123
124 if (LocVT == MVT::i64 && Offset < 6*8)
125 // Promote integers to %i0-%i5.
126 Reg = SP::I0 + Offset/8;
127 else if (LocVT == MVT::f64 && Offset < 16*8)
128 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
129 Reg = SP::D0 + Offset/8;
130 else if (LocVT == MVT::f32 && Offset < 16*8)
131 // Promote floats to %f1, %f3, ...
132 Reg = SP::F1 + Offset/4;
133 else if (LocVT == MVT::f128 && Offset < 16*8)
134 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
135 Reg = SP::Q0 + Offset/16;
136
137 // Promote to register when possible, otherwise use the stack slot.
138 if (Reg) {
139 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
140 return true;
141 }
142
143 // Bail out if this is a return CC and we run out of registers to place
144 // values into.
145 if (IsReturn)
146 return false;
147
148 // This argument goes on the stack in an 8-byte slot.
149 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
150 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
151 if (LocVT == MVT::f32)
152 Offset += 4;
153
154 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, HTP: LocInfo));
155 return true;
156}
157
158// Allocate a half-sized argument for the 64-bit ABI.
159//
160// This is used when passing { float, int } structs by value in registers.
161static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT,
162 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
163 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
164 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
165 unsigned Offset = State.AllocateStack(Size: 4, Alignment: Align(4));
166
167 if (LocVT == MVT::f32 && Offset < 16*8) {
168 // Promote floats to %f0-%f31.
169 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg: SP::F0 + Offset/4,
170 LocVT, HTP: LocInfo));
171 return true;
172 }
173
174 if (LocVT == MVT::i32 && Offset < 6*8) {
175 // Promote integers to %i0-%i5, using half the register.
176 unsigned Reg = SP::I0 + Offset/8;
177 LocVT = MVT::i64;
178 LocInfo = CCValAssign::AExt;
179
180 // Set the Custom bit if this i32 goes in the high bits of a register.
181 if (Offset % 8 == 0)
182 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg,
183 LocVT, HTP: LocInfo));
184 else
185 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
186 return true;
187 }
188
189 // Bail out if this is a return CC and we run out of registers to place
190 // values into.
191 if (IsReturn)
192 return false;
193
194 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, HTP: LocInfo));
195 return true;
196}
197
198static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
199 CCValAssign::LocInfo &LocInfo,
200 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
201 return Analyze_CC_Sparc64_Full(IsReturn: false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
202 State);
203}
204
205static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
206 CCValAssign::LocInfo &LocInfo,
207 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
208 return Analyze_CC_Sparc64_Half(IsReturn: false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
209 State);
210}
211
212static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
213 CCValAssign::LocInfo &LocInfo,
214 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
215 return Analyze_CC_Sparc64_Full(IsReturn: true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
216 State);
217}
218
219static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
220 CCValAssign::LocInfo &LocInfo,
221 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
222 return Analyze_CC_Sparc64_Half(IsReturn: true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
223 State);
224}
225
226#define GET_CALLING_CONV_IMPL
227#include "SparcGenCallingConv.inc"
228
229// The calling conventions in SparcCallingConv.td are described in terms of the
230// callee's register window. This function translates registers to the
231// corresponding caller window %o register.
232static unsigned toCallerWindow(unsigned Reg) {
233 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
234 "Unexpected enum");
235 if (Reg >= SP::I0 && Reg <= SP::I7)
236 return Reg - SP::I0 + SP::O0;
237 return Reg;
238}
239
240bool SparcTargetLowering::CanLowerReturn(
241 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
242 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
243 const Type *RetTy) const {
244 SmallVector<CCValAssign, 16> RVLocs;
245 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
246 return CCInfo.CheckReturn(Outs, Fn: Subtarget->is64Bit() ? RetCC_Sparc64
247 : RetCC_Sparc32);
248}
249
250SDValue
251SparcTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
252 bool IsVarArg,
253 const SmallVectorImpl<ISD::OutputArg> &Outs,
254 const SmallVectorImpl<SDValue> &OutVals,
255 const SDLoc &DL, SelectionDAG &DAG) const {
256 if (Subtarget->is64Bit())
257 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
258 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
259}
260
261SDValue
262SparcTargetLowering::LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
263 bool IsVarArg,
264 const SmallVectorImpl<ISD::OutputArg> &Outs,
265 const SmallVectorImpl<SDValue> &OutVals,
266 const SDLoc &DL, SelectionDAG &DAG) const {
267 MachineFunction &MF = DAG.getMachineFunction();
268
269 // CCValAssign - represent the assignment of the return value to locations.
270 SmallVector<CCValAssign, 16> RVLocs;
271
272 // CCState - Info about the registers and stack slot.
273 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
274 *DAG.getContext());
275
276 // Analyze return values.
277 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_Sparc32);
278
279 SDValue Glue;
280 SmallVector<SDValue, 4> RetOps(1, Chain);
281 // Make room for the return address offset.
282 RetOps.push_back(Elt: SDValue());
283
284 // Copy the result values into the output registers.
285 for (unsigned i = 0, realRVLocIdx = 0;
286 i != RVLocs.size();
287 ++i, ++realRVLocIdx) {
288 CCValAssign &VA = RVLocs[i];
289 assert(VA.isRegLoc() && "Can only return in registers!");
290
291 SDValue Arg = OutVals[realRVLocIdx];
292
293 if (VA.needsCustom()) {
294 assert(VA.getLocVT() == MVT::v2i32);
295 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
296 // happen by default if this wasn't a legal type)
297
298 SDValue Part0 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32,
299 N1: Arg,
300 N2: DAG.getConstant(Val: 0, DL, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
301 SDValue Part1 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32,
302 N1: Arg,
303 N2: DAG.getConstant(Val: 1, DL, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
304
305 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Part0, Glue);
306 Glue = Chain.getValue(R: 1);
307 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
308 VA = RVLocs[++i]; // skip ahead to next loc
309 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Part1,
310 Glue);
311 } else
312 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Arg, Glue);
313
314 // Guarantee that all emitted copies are stuck together with flags.
315 Glue = Chain.getValue(R: 1);
316 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
317 }
318
319 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
320 // If the function returns a struct, copy the SRetReturnReg to I0
321 if (MF.getFunction().hasStructRetAttr()) {
322 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
323 Register Reg = SFI->getSRetReturnReg();
324 if (!Reg)
325 llvm_unreachable("sret virtual register not created in the entry block");
326 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
327 SDValue Val = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: PtrVT);
328 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SP::I0, N: Val, Glue);
329 Glue = Chain.getValue(R: 1);
330 RetOps.push_back(Elt: DAG.getRegister(Reg: SP::I0, VT: PtrVT));
331
332 // A zero-sized return value, e.g. an empty struct or union, is returned
333 // without an unimp instruction after the call, so there is nothing for the
334 // return to skip over.
335 Type *RetType = MF.getFunction().getParamStructRetType(ArgNo: 0);
336 if (!RetType->isEmptyTy())
337 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
338 }
339
340 RetOps[0] = Chain; // Update chain.
341 RetOps[1] = DAG.getConstant(Val: RetAddrOffset, DL, VT: MVT::i32);
342
343 // Add the glue if we have it.
344 if (Glue.getNode())
345 RetOps.push_back(Elt: Glue);
346
347 return DAG.getNode(Opcode: SPISD::RET_GLUE, DL, VT: MVT::Other, Ops: RetOps);
348}
349
350// Lower return values for the 64-bit ABI.
351// Return values are passed the exactly the same way as function arguments.
352SDValue
353SparcTargetLowering::LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
354 bool IsVarArg,
355 const SmallVectorImpl<ISD::OutputArg> &Outs,
356 const SmallVectorImpl<SDValue> &OutVals,
357 const SDLoc &DL, SelectionDAG &DAG) const {
358 // CCValAssign - represent the assignment of the return value to locations.
359 SmallVector<CCValAssign, 16> RVLocs;
360
361 // CCState - Info about the registers and stack slot.
362 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
363 *DAG.getContext());
364
365 // Analyze return values.
366 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_Sparc64);
367
368 SDValue Glue;
369 SmallVector<SDValue, 4> RetOps(1, Chain);
370
371 // The second operand on the return instruction is the return address offset.
372 // The return address is always %i7+8 with the 64-bit ABI.
373 RetOps.push_back(Elt: DAG.getConstant(Val: 8, DL, VT: MVT::i32));
374
375 // Copy the result values into the output registers.
376 for (unsigned i = 0; i != RVLocs.size(); ++i) {
377 CCValAssign &VA = RVLocs[i];
378 assert(VA.isRegLoc() && "Can only return in registers!");
379 SDValue OutVal = OutVals[i];
380
381 // Integer return values must be sign or zero extended by the callee.
382 switch (VA.getLocInfo()) {
383 case CCValAssign::Full: break;
384 case CCValAssign::SExt:
385 OutVal = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
386 break;
387 case CCValAssign::ZExt:
388 OutVal = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
389 break;
390 case CCValAssign::AExt:
391 OutVal = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
392 break;
393 default:
394 llvm_unreachable("Unknown loc info!");
395 }
396
397 // The custom bit on an i32 return value indicates that it should be passed
398 // in the high bits of the register.
399 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
400 OutVal = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: OutVal,
401 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
402
403 // The next value may go in the low bits of the same register.
404 // Handle both at once.
405 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
406 SDValue NV = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i64, Operand: OutVals[i+1]);
407 OutVal = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i64, N1: OutVal, N2: NV);
408 // Skip the next value, it's already done.
409 ++i;
410 }
411 }
412
413 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: OutVal, Glue);
414
415 // Guarantee that all emitted copies are stuck together with flags.
416 Glue = Chain.getValue(R: 1);
417 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
418 }
419
420 RetOps[0] = Chain; // Update chain.
421
422 // Add the flag if we have it.
423 if (Glue.getNode())
424 RetOps.push_back(Elt: Glue);
425
426 return DAG.getNode(Opcode: SPISD::RET_GLUE, DL, VT: MVT::Other, Ops: RetOps);
427}
428
429SDValue SparcTargetLowering::LowerFormalArguments(
430 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
431 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
432 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
433 if (Subtarget->is64Bit())
434 return LowerFormalArguments_64(Chain, CallConv, isVarArg: IsVarArg, Ins,
435 dl: DL, DAG, InVals);
436 return LowerFormalArguments_32(Chain, CallConv, isVarArg: IsVarArg, Ins,
437 dl: DL, DAG, InVals);
438}
439
440/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
441/// passed in either one or two GPRs, including FP values. TODO: we should
442/// pass FP values in FP registers for fastcc functions.
443SDValue SparcTargetLowering::LowerFormalArguments_32(
444 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
445 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
446 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
447 MachineFunction &MF = DAG.getMachineFunction();
448 MachineRegisterInfo &RegInfo = MF.getRegInfo();
449 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
450 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
451
452 // Assign locations to all of the incoming arguments.
453 SmallVector<CCValAssign, 16> ArgLocs;
454 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
455 *DAG.getContext());
456 CCInfo.AnalyzeFormalArguments(Ins, Fn: CC_Sparc32);
457
458 const unsigned StackOffset = 92;
459 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
460
461 unsigned InIdx = 0;
462 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
463 CCValAssign &VA = ArgLocs[i];
464 EVT LocVT = VA.getLocVT();
465
466 if (Ins[InIdx].Flags.isSRet()) {
467 if (InIdx != 0)
468 report_fatal_error(reason: "sparc only supports sret on the first parameter");
469 // Get SRet from [%fp+64].
470 int FrameIdx = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: 64, IsImmutable: true);
471 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
472 SDValue Arg =
473 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
474 InVals.push_back(Elt: Arg);
475 continue;
476 }
477
478 SDValue Arg;
479 if (VA.isRegLoc()) {
480 if (VA.needsCustom()) {
481 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
482
483 Register VRegHi = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
484 MF.getRegInfo().addLiveIn(Reg: VA.getLocReg(), vreg: VRegHi);
485 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, Reg: VRegHi, VT: MVT::i32);
486
487 assert(i+1 < e);
488 CCValAssign &NextVA = ArgLocs[++i];
489
490 SDValue LoVal;
491 if (NextVA.isMemLoc()) {
492 int FrameIdx = MF.getFrameInfo().
493 CreateFixedObject(Size: 4, SPOffset: StackOffset+NextVA.getLocMemOffset(),IsImmutable: true);
494 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
495 LoVal = DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
496 } else {
497 Register loReg = MF.addLiveIn(PReg: NextVA.getLocReg(),
498 RC: &SP::IntRegsRegClass);
499 LoVal = DAG.getCopyFromReg(Chain, dl, Reg: loReg, VT: MVT::i32);
500 }
501
502 if (IsLittleEndian)
503 std::swap(a&: LoVal, b&: HiVal);
504
505 SDValue WholeValue =
506 DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: LoVal, N2: HiVal);
507 WholeValue = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getLocVT(), Operand: WholeValue);
508 InVals.push_back(Elt: WholeValue);
509 continue;
510 }
511 Register VReg = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
512 MF.getRegInfo().addLiveIn(Reg: VA.getLocReg(), vreg: VReg);
513 Arg = DAG.getCopyFromReg(Chain, dl, Reg: VReg, VT: MVT::i32);
514 if (VA.getLocInfo() != CCValAssign::Indirect) {
515 if (VA.getLocVT() == MVT::f32)
516 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::f32, Operand: Arg);
517 else if (VA.getLocVT() != MVT::i32) {
518 Arg = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: MVT::i32, N1: Arg,
519 N2: DAG.getValueType(VA.getLocVT()));
520 Arg = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getLocVT(), Operand: Arg);
521 }
522 InVals.push_back(Elt: Arg);
523 continue;
524 }
525 } else {
526 assert(VA.isMemLoc());
527
528 unsigned Offset = VA.getLocMemOffset() + StackOffset;
529
530 if (VA.needsCustom()) {
531 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
532 // If it is double-word aligned, just load.
533 if (Offset % 8 == 0) {
534 int FI = MF.getFrameInfo().CreateFixedObject(Size: 8, SPOffset: Offset, IsImmutable: true);
535 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
536 SDValue Load = DAG.getLoad(VT: VA.getValVT(), dl, Chain, Ptr: FIPtr,
537 PtrInfo: MachinePointerInfo());
538 InVals.push_back(Elt: Load);
539 continue;
540 }
541
542 int FI = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: Offset, IsImmutable: true);
543 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
544 SDValue HiVal =
545 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
546 int FI2 = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: Offset + 4, IsImmutable: true);
547 SDValue FIPtr2 = DAG.getFrameIndex(FI: FI2, VT: PtrVT);
548
549 SDValue LoVal =
550 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr2, PtrInfo: MachinePointerInfo());
551
552 if (IsLittleEndian)
553 std::swap(a&: LoVal, b&: HiVal);
554
555 SDValue WholeValue =
556 DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: LoVal, N2: HiVal);
557 WholeValue = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getValVT(), Operand: WholeValue);
558 InVals.push_back(Elt: WholeValue);
559 continue;
560 }
561
562 int FI = MF.getFrameInfo().CreateFixedObject(Size: LocVT.getSizeInBits() / 8,
563 SPOffset: Offset, IsImmutable: true);
564 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
565 SDValue Load = DAG.getLoad(VT: LocVT, dl, Chain, Ptr: FIPtr,
566 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI));
567 if (VA.getLocInfo() != CCValAssign::Indirect) {
568 InVals.push_back(Elt: Load);
569 continue;
570 }
571 Arg = Load;
572 }
573
574 assert(VA.getLocInfo() == CCValAssign::Indirect);
575
576 SDValue ArgValue =
577 DAG.getLoad(VT: VA.getValVT(), dl, Chain, Ptr: Arg, PtrInfo: MachinePointerInfo());
578 InVals.push_back(Elt: ArgValue);
579
580 unsigned ArgIndex = Ins[InIdx].OrigArgIndex;
581 assert(Ins[InIdx].PartOffset == 0);
582 while (i + 1 != e && Ins[InIdx + 1].OrigArgIndex == ArgIndex) {
583 CCValAssign &PartVA = ArgLocs[i + 1];
584 unsigned PartOffset = Ins[InIdx + 1].PartOffset;
585 SDValue Address = DAG.getMemBasePlusOffset(
586 Base: ArgValue, Offset: TypeSize::getFixed(ExactSize: PartOffset), DL: dl);
587 InVals.push_back(Elt: DAG.getLoad(VT: PartVA.getValVT(), dl, Chain, Ptr: Address,
588 PtrInfo: MachinePointerInfo()));
589 ++i;
590 ++InIdx;
591 }
592 }
593
594 if (MF.getFunction().hasStructRetAttr()) {
595 // Copy the SRet Argument to SRetReturnReg.
596 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
597 Register Reg = SFI->getSRetReturnReg();
598 if (!Reg) {
599 Reg = MF.getRegInfo().createVirtualRegister(RegClass: &SP::IntRegsRegClass);
600 SFI->setSRetReturnReg(Reg);
601 }
602 SDValue Copy = DAG.getCopyToReg(Chain: DAG.getEntryNode(), dl, Reg, N: InVals[0]);
603 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Copy, N2: Chain);
604 }
605
606 // Store remaining ArgRegs to the stack if this is a varargs function.
607 if (isVarArg) {
608 static const MCPhysReg ArgRegs[] = {
609 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
610 };
611 unsigned NumAllocated = CCInfo.getFirstUnallocated(Regs: ArgRegs);
612 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
613 unsigned ArgOffset = CCInfo.getStackSize();
614 if (NumAllocated == 6)
615 ArgOffset += StackOffset;
616 else {
617 assert(!ArgOffset);
618 ArgOffset = 68+4*NumAllocated;
619 }
620
621 // Remember the vararg offset for the va_start implementation.
622 FuncInfo->setVarArgsFrameOffset(ArgOffset);
623
624 std::vector<SDValue> OutChains;
625
626 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
627 Register VReg = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
628 MF.getRegInfo().addLiveIn(Reg: *CurArgReg, vreg: VReg);
629 SDValue Arg = DAG.getCopyFromReg(Chain: DAG.getRoot(), dl, Reg: VReg, VT: MVT::i32);
630
631 int FrameIdx = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: ArgOffset,
632 IsImmutable: true);
633 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
634
635 OutChains.push_back(
636 x: DAG.getStore(Chain: DAG.getRoot(), dl, Val: Arg, Ptr: FIPtr, PtrInfo: MachinePointerInfo()));
637 ArgOffset += 4;
638 }
639
640 if (!OutChains.empty()) {
641 OutChains.push_back(x: Chain);
642 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
643 }
644 }
645
646 return Chain;
647}
648
649// Lower formal arguments for the 64 bit ABI.
650SDValue SparcTargetLowering::LowerFormalArguments_64(
651 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
652 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
653 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
654 MachineFunction &MF = DAG.getMachineFunction();
655
656 // Analyze arguments according to CC_Sparc64.
657 SmallVector<CCValAssign, 16> ArgLocs;
658 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
659 *DAG.getContext());
660 CCInfo.AnalyzeFormalArguments(Ins, Fn: CC_Sparc64);
661
662 // The argument array begins at %fp+BIAS+128, after the register save area.
663 const unsigned ArgArea = 128;
664
665 for (const CCValAssign &VA : ArgLocs) {
666 if (VA.isRegLoc()) {
667 // This argument is passed in a register.
668 // All integer register arguments are promoted by the caller to i64.
669
670 // Create a virtual register for the promoted live-in value.
671 Register VReg = MF.addLiveIn(PReg: VA.getLocReg(),
672 RC: getRegClassFor(VT: VA.getLocVT()));
673 SDValue Arg = DAG.getCopyFromReg(Chain, dl: DL, Reg: VReg, VT: VA.getLocVT());
674
675 // Get the high bits for i32 struct elements.
676 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
677 Arg = DAG.getNode(Opcode: ISD::SRL, DL, VT: VA.getLocVT(), N1: Arg,
678 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
679
680 // The caller promoted the argument, so insert an Assert?ext SDNode so we
681 // won't promote the value again in this function.
682 switch (VA.getLocInfo()) {
683 case CCValAssign::SExt:
684 Arg = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: Arg,
685 N2: DAG.getValueType(VA.getValVT()));
686 break;
687 case CCValAssign::ZExt:
688 Arg = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: Arg,
689 N2: DAG.getValueType(VA.getValVT()));
690 break;
691 default:
692 break;
693 }
694
695 // Truncate the register down to the argument type.
696 if (VA.isExtInLoc())
697 Arg = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: Arg);
698
699 InVals.push_back(Elt: Arg);
700 continue;
701 }
702
703 // The registers are exhausted. This argument was passed on the stack.
704 assert(VA.isMemLoc());
705 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
706 // beginning of the arguments area at %fp+BIAS+128.
707 unsigned Offset = VA.getLocMemOffset() + ArgArea;
708 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
709 // Adjust offset for extended arguments, SPARC is big-endian.
710 // The caller will have written the full slot with extended bytes, but we
711 // prefer our own extending loads.
712 if (VA.isExtInLoc())
713 Offset += 8 - ValSize;
714 int FI = MF.getFrameInfo().CreateFixedObject(Size: ValSize, SPOffset: Offset, IsImmutable: true);
715 InVals.push_back(
716 Elt: DAG.getLoad(VT: VA.getValVT(), dl: DL, Chain,
717 Ptr: DAG.getFrameIndex(FI, VT: getPointerTy(DL: MF.getDataLayout())),
718 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
719 }
720
721 if (!IsVarArg)
722 return Chain;
723
724 // This function takes variable arguments, some of which may have been passed
725 // in registers %i0-%i5. Variable floating point arguments are never passed
726 // in floating point registers. They go on %i0-%i5 or on the stack like
727 // integer arguments.
728 //
729 // The va_start intrinsic needs to know the offset to the first variable
730 // argument.
731 unsigned ArgOffset = CCInfo.getStackSize();
732 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
733 // Skip the 128 bytes of register save area.
734 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
735 Subtarget->getStackPointerBias());
736
737 // Save the variable arguments that were passed in registers.
738 // The caller is required to reserve stack space for 6 arguments regardless
739 // of how many arguments were actually passed.
740 SmallVector<SDValue, 8> OutChains;
741 for (; ArgOffset < 6*8; ArgOffset += 8) {
742 Register VReg = MF.addLiveIn(PReg: SP::I0 + ArgOffset/8, RC: &SP::I64RegsRegClass);
743 SDValue VArg = DAG.getCopyFromReg(Chain, dl: DL, Reg: VReg, VT: MVT::i64);
744 int FI = MF.getFrameInfo().CreateFixedObject(Size: 8, SPOffset: ArgOffset + ArgArea, IsImmutable: true);
745 auto PtrVT = getPointerTy(DL: MF.getDataLayout());
746 OutChains.push_back(
747 Elt: DAG.getStore(Chain, dl: DL, Val: VArg, Ptr: DAG.getFrameIndex(FI, VT: PtrVT),
748 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
749 }
750
751 if (!OutChains.empty())
752 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: OutChains);
753
754 return Chain;
755}
756
757// Check whether any of the argument registers are reserved
758static bool isAnyArgRegReserved(const SparcRegisterInfo *TRI,
759 const MachineFunction &MF) {
760 // The register window design means that outgoing parameters at O*
761 // will appear in the callee as I*.
762 // Be conservative and check both sides of the register names.
763 bool Outgoing =
764 llvm::any_of(Range: SP::GPROutgoingArgRegClass, P: [TRI, &MF](MCPhysReg r) {
765 return TRI->isReservedReg(MF, Reg: r);
766 });
767 bool Incoming =
768 llvm::any_of(Range: SP::GPRIncomingArgRegClass, P: [TRI, &MF](MCPhysReg r) {
769 return TRI->isReservedReg(MF, Reg: r);
770 });
771 return Outgoing || Incoming;
772}
773
774static void emitReservedArgRegCallError(const MachineFunction &MF) {
775 const Function &F = MF.getFunction();
776 F.getContext().diagnose(DI: DiagnosticInfoUnsupported{
777 F, ("SPARC doesn't support"
778 " function calls if any of the argument registers is reserved.")});
779}
780
781SDValue
782SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
783 SmallVectorImpl<SDValue> &InVals) const {
784 if (Subtarget->is64Bit())
785 return LowerCall_64(CLI, InVals);
786 return LowerCall_32(CLI, InVals);
787}
788
789static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
790 const CallBase *Call) {
791 if (Call)
792 return Call->hasFnAttr(Kind: Attribute::ReturnsTwice);
793
794 const Function *CalleeFn = nullptr;
795 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
796 CalleeFn = dyn_cast<Function>(Val: G->getGlobal());
797 } else if (ExternalSymbolSDNode *E =
798 dyn_cast<ExternalSymbolSDNode>(Val&: Callee)) {
799 const Function &Fn = DAG.getMachineFunction().getFunction();
800 const Module *M = Fn.getParent();
801 const char *CalleeName = E->getSymbol();
802 CalleeFn = M->getFunction(Name: CalleeName);
803 }
804
805 if (!CalleeFn)
806 return false;
807 return CalleeFn->hasFnAttribute(Kind: Attribute::ReturnsTwice);
808}
809
810/// IsEligibleForTailCallOptimization - Check whether the call is eligible
811/// for tail call optimization.
812bool SparcTargetLowering::IsEligibleForTailCallOptimization(
813 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const {
814
815 auto &Outs = CLI.Outs;
816 auto &Caller = MF.getFunction();
817
818 // Do not tail call opt functions with "disable-tail-calls" attribute.
819 if (Caller.getFnAttribute(Kind: "disable-tail-calls").getValueAsString() == "true")
820 return false;
821
822 // Do not tail call opt if the stack is used to pass parameters.
823 // 64-bit targets have a slightly higher limit since the ABI requires
824 // to allocate some space even when all the parameters fit inside registers.
825 unsigned StackSizeLimit = Subtarget->is64Bit() ? 48 : 0;
826 if (CCInfo.getStackSize() > StackSizeLimit)
827 return false;
828
829 // Do not tail call opt if either the callee or caller returns
830 // a struct and the other does not.
831 if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
832 return false;
833
834 // Byval parameters hand the function a pointer directly into the stack area
835 // we want to reuse during a tail call.
836 for (auto &Arg : Outs)
837 if (Arg.Flags.isByVal())
838 return false;
839
840 return true;
841}
842
843// Lower a call for the 32-bit ABI.
844SDValue
845SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
846 SmallVectorImpl<SDValue> &InVals) const {
847 SelectionDAG &DAG = CLI.DAG;
848 SDLoc &dl = CLI.DL;
849 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
850 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
851 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
852 SDValue Chain = CLI.Chain;
853 SDValue Callee = CLI.Callee;
854 bool &isTailCall = CLI.IsTailCall;
855 CallingConv::ID CallConv = CLI.CallConv;
856 bool isVarArg = CLI.IsVarArg;
857 MachineFunction &MF = DAG.getMachineFunction();
858 LLVMContext &Ctx = *DAG.getContext();
859 EVT PtrVT = getPointerTy(DL: MF.getDataLayout());
860
861 // Analyze operands of the call, assigning locations to each operand.
862 SmallVector<CCValAssign, 16> ArgLocs;
863 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
864 *DAG.getContext());
865 CCInfo.AnalyzeCallOperands(Outs, Fn: CC_Sparc32);
866
867 isTailCall = isTailCall && IsEligibleForTailCallOptimization(
868 CCInfo, CLI, MF&: DAG.getMachineFunction());
869
870 // Get the size of the outgoing arguments stack space requirement.
871 unsigned ArgsSize = CCInfo.getStackSize();
872
873 // Keep stack frames 8-byte aligned.
874 ArgsSize = (ArgsSize+7) & ~7;
875
876 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
877
878 // Create local copies for byval args.
879 SmallVector<SDValue, 8> ByValArgs;
880 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
881 ISD::ArgFlagsTy Flags = Outs[i].Flags;
882 if (!Flags.isByVal())
883 continue;
884
885 SDValue Arg = OutVals[i];
886 unsigned Size = Flags.getByValSize();
887 Align Alignment = Flags.getNonZeroByValAlign();
888
889 if (Size > 0U) {
890 int FI = MFI.CreateStackObject(Size, Alignment, isSpillSlot: false);
891 SDValue FIPtr = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
892 SDValue SizeNode = DAG.getConstant(Val: Size, DL: dl, VT: MVT::i32);
893
894 Chain =
895 DAG.getMemcpy(Chain, dl, Dst: FIPtr, Src: Arg, Size: SizeNode, DstAlign: Alignment, SrcAlign: Alignment,
896 isVol: false, // isVolatile,
897 AlwaysInline: (Size <= 32), // AlwaysInline if size <= 32,
898 /*CI=*/nullptr, OverrideTailCall: std::nullopt, DstPtrInfo: MachinePointerInfo(),
899 SrcPtrInfo: MachinePointerInfo());
900 ByValArgs.push_back(Elt: FIPtr);
901 }
902 else {
903 SDValue nullVal;
904 ByValArgs.push_back(Elt: nullVal);
905 }
906 }
907
908 assert(!isTailCall || ArgsSize == 0);
909
910 if (!isTailCall)
911 Chain = DAG.getCALLSEQ_START(Chain, InSize: ArgsSize, OutSize: 0, DL: dl);
912
913 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
914 SmallVector<SDValue, 8> MemOpChains;
915
916 const unsigned StackOffset = 92;
917 bool hasStructRetAttr = false;
918 unsigned SRetArgSize = 0;
919 // Walk the register/memloc assignments, inserting copies/loads.
920 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
921 i != e;
922 ++i, ++realArgIdx) {
923 CCValAssign &VA = ArgLocs[i];
924 SDValue Arg = OutVals[realArgIdx];
925
926 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
927
928 // Use local copy if it is a byval arg.
929 if (Flags.isByVal()) {
930 Arg = ByValArgs[byvalArgIdx++];
931 if (!Arg) {
932 continue;
933 }
934 }
935
936 // Promote the value if needed.
937 switch (VA.getLocInfo()) {
938 default: llvm_unreachable("Unknown loc info!");
939 case CCValAssign::Full:
940 case CCValAssign::Indirect:
941 break;
942 case CCValAssign::SExt:
943 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
944 break;
945 case CCValAssign::ZExt:
946 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
947 break;
948 case CCValAssign::AExt:
949 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
950 break;
951 case CCValAssign::BCvt:
952 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getLocVT(), Operand: Arg);
953 break;
954 }
955
956 if (Flags.isSRet()) {
957 assert(VA.needsCustom());
958
959 if (isTailCall)
960 continue;
961
962 // store SRet argument in %sp+64
963 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
964 SDValue PtrOff = DAG.getIntPtrConstant(Val: 64, DL: dl);
965 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
966 MemOpChains.push_back(
967 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
968 hasStructRetAttr = true;
969 // sret only allowed on first argument
970 assert(Outs[realArgIdx].OrigArgIndex == 0);
971 SRetArgSize =
972 DAG.getDataLayout().getTypeAllocSize(Ty: CLI.getArgs()[0].IndirectType);
973 continue;
974 }
975
976 if (VA.needsCustom()) {
977 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
978
979 if (VA.isMemLoc()) {
980 unsigned Offset = VA.getLocMemOffset() + StackOffset;
981 // if it is double-word aligned, just store.
982 if (Offset % 8 == 0) {
983 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
984 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
985 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
986 MemOpChains.push_back(
987 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
988 continue;
989 }
990 }
991
992 if (VA.getLocVT() == MVT::f64) {
993 // Move from the float value from float registers into the
994 // integer registers.
995 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val&: Arg))
996 Arg = bitcastConstantFPToInt(C, DL: dl, DAG);
997 else
998 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::v2i32, Operand: Arg);
999 }
1000
1001 SDValue Part0 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: MVT::i32,
1002 N1: Arg,
1003 N2: DAG.getConstant(Val: 0, DL: dl, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
1004 SDValue Part1 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: MVT::i32,
1005 N1: Arg,
1006 N2: DAG.getConstant(Val: 1, DL: dl, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
1007
1008 if (VA.isRegLoc()) {
1009 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Part0));
1010 assert(i+1 != e);
1011 CCValAssign &NextVA = ArgLocs[++i];
1012 if (NextVA.isRegLoc()) {
1013 RegsToPass.push_back(Elt: std::make_pair(x: NextVA.getLocReg(), y&: Part1));
1014 } else {
1015 // Store the second part in stack.
1016 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
1017 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1018 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
1019 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1020 MemOpChains.push_back(
1021 Elt: DAG.getStore(Chain, dl, Val: Part1, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1022 }
1023 } else {
1024 unsigned Offset = VA.getLocMemOffset() + StackOffset;
1025 // Store the first part.
1026 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1027 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
1028 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1029 MemOpChains.push_back(
1030 Elt: DAG.getStore(Chain, dl, Val: Part0, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1031 // Store the second part.
1032 PtrOff = DAG.getIntPtrConstant(Val: Offset + 4, DL: dl);
1033 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1034 MemOpChains.push_back(
1035 Elt: DAG.getStore(Chain, dl, Val: Part1, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1036 }
1037 continue;
1038 }
1039
1040 if (VA.getLocInfo() == CCValAssign::Indirect) {
1041 // Store the argument in a stack slot and pass its address.
1042 unsigned ArgIndex = Outs[realArgIdx].OrigArgIndex;
1043 assert(Outs[realArgIdx].PartOffset == 0);
1044
1045 EVT SlotVT;
1046 if (i + 1 != e && Outs[realArgIdx + 1].OrigArgIndex == ArgIndex) {
1047 Type *OrigArgType = CLI.Args[ArgIndex].Ty;
1048 EVT OrigArgVT = getValueType(DL: MF.getDataLayout(), Ty: OrigArgType);
1049 MVT PartVT =
1050 getRegisterTypeForCallingConv(Context&: Ctx, CC: CLI.CallConv, VT: OrigArgVT);
1051 unsigned N =
1052 getNumRegistersForCallingConv(Context&: Ctx, CC: CLI.CallConv, VT: OrigArgVT);
1053 SlotVT = EVT::getIntegerVT(Context&: Ctx, BitWidth: PartVT.getSizeInBits() * N);
1054 } else {
1055 SlotVT = Outs[realArgIdx].VT;
1056 }
1057
1058 SDValue SpillSlot = DAG.CreateStackTemporary(VT: SlotVT);
1059 int FI = cast<FrameIndexSDNode>(Val&: SpillSlot)->getIndex();
1060 MemOpChains.push_back(
1061 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: SpillSlot,
1062 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
1063 // If the original argument was split (e.g. f128), we need
1064 // to store all parts of it here (and pass just one address).
1065 while (i + 1 != e && Outs[realArgIdx + 1].OrigArgIndex == ArgIndex) {
1066 SDValue PartValue = OutVals[realArgIdx + 1];
1067 unsigned PartOffset = Outs[realArgIdx + 1].PartOffset;
1068 SDValue Address = DAG.getMemBasePlusOffset(
1069 Base: DAG.getFrameIndex(FI, VT: PtrVT), Offset: TypeSize::getFixed(ExactSize: PartOffset), DL: dl);
1070 MemOpChains.push_back(
1071 Elt: DAG.getStore(Chain, dl, Val: PartValue, Ptr: Address,
1072 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
1073 assert((PartOffset + PartValue.getValueType().getStoreSize() <=
1074 SlotVT.getStoreSize()) &&
1075 "Not enough space for argument part!");
1076 ++i;
1077 ++realArgIdx;
1078 }
1079
1080 Arg = SpillSlot;
1081 }
1082
1083 // Arguments that can be passed on register must be kept at
1084 // RegsToPass vector
1085 if (VA.isRegLoc()) {
1086 if (VA.getLocVT() != MVT::f32) {
1087 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1088 continue;
1089 }
1090 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: Arg);
1091 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1092 continue;
1093 }
1094
1095 assert(VA.isMemLoc());
1096
1097 // Create a store off the stack pointer for this argument.
1098 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1099 SDValue PtrOff = DAG.getIntPtrConstant(Val: VA.getLocMemOffset() + StackOffset,
1100 DL: dl);
1101 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1102 MemOpChains.push_back(
1103 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1104 }
1105
1106
1107 // Emit all stores, make sure the occur before any copies into physregs.
1108 if (!MemOpChains.empty())
1109 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains);
1110
1111 // Build a sequence of copy-to-reg nodes chained together with token
1112 // chain and flag operands which copy the outgoing args into registers.
1113 // The InGlue in necessary since all emitted instructions must be
1114 // stuck together.
1115 SDValue InGlue;
1116 for (const auto &[OrigReg, N] : RegsToPass) {
1117 Register Reg = isTailCall ? OrigReg : toCallerWindow(Reg: OrigReg);
1118 Chain = DAG.getCopyToReg(Chain, dl, Reg, N, Glue: InGlue);
1119 InGlue = Chain.getValue(R: 1);
1120 }
1121
1122 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, Call: CLI.CB);
1123
1124 // If the callee is a GlobalAddress node (quite common, every direct call is)
1125 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1126 // Likewise ExternalSymbol -> TargetExternalSymbol.
1127 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
1128 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL: dl, VT: MVT::i32, offset: 0);
1129 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee))
1130 Callee = DAG.getTargetExternalSymbol(Sym: E->getSymbol(), VT: MVT::i32);
1131
1132 // Returns a chain & a flag for retval copy to use
1133 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1134 SmallVector<SDValue, 8> Ops;
1135 Ops.push_back(Elt: Chain);
1136 Ops.push_back(Elt: Callee);
1137 if (hasStructRetAttr)
1138 Ops.push_back(Elt: DAG.getTargetConstant(Val: SRetArgSize, DL: dl, VT: MVT::i32));
1139 for (const auto &[OrigReg, N] : RegsToPass) {
1140 Register Reg = isTailCall ? OrigReg : toCallerWindow(Reg: OrigReg);
1141 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
1142 }
1143
1144 // Add a register mask operand representing the call-preserved registers.
1145 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1146 const uint32_t *Mask =
1147 ((hasReturnsTwice)
1148 ? TRI->getRTCallPreservedMask(CC: CallConv)
1149 : TRI->getCallPreservedMask(MF: DAG.getMachineFunction(), CC: CallConv));
1150
1151 if (isAnyArgRegReserved(TRI, MF))
1152 emitReservedArgRegCallError(MF);
1153
1154 assert(Mask && "Missing call preserved mask for calling convention");
1155 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
1156
1157 if (InGlue.getNode())
1158 Ops.push_back(Elt: InGlue);
1159
1160 if (isTailCall) {
1161 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
1162 return DAG.getNode(Opcode: SPISD::TAIL_CALL, DL: dl, VT: MVT::Other, Ops);
1163 }
1164
1165 Chain = DAG.getNode(Opcode: SPISD::CALL, DL: dl, VTList: NodeTys, Ops);
1166 InGlue = Chain.getValue(R: 1);
1167
1168 Chain = DAG.getCALLSEQ_END(Chain, Size1: ArgsSize, Size2: 0, Glue: InGlue, DL: dl);
1169 InGlue = Chain.getValue(R: 1);
1170
1171 // Assign locations to each value returned by this call.
1172 SmallVector<CCValAssign, 16> RVLocs;
1173 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1174 *DAG.getContext());
1175
1176 RVInfo.AnalyzeCallResult(Ins, Fn: RetCC_Sparc32);
1177
1178 // Copy all of the result registers out of their specified physreg.
1179 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1180 assert(RVLocs[i].isRegLoc() && "Can only return in registers!");
1181 if (RVLocs[i].getLocVT() == MVT::v2i32) {
1182 SDValue Vec = DAG.getNode(Opcode: ISD::UNDEF, DL: dl, VT: MVT::v2i32);
1183 SDValue Lo = DAG.getCopyFromReg(
1184 Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i++].getLocReg()), VT: MVT::i32, Glue: InGlue);
1185 Chain = Lo.getValue(R: 1);
1186 InGlue = Lo.getValue(R: 2);
1187 Vec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: MVT::v2i32, N1: Vec, N2: Lo,
1188 N3: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
1189 SDValue Hi = DAG.getCopyFromReg(
1190 Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i].getLocReg()), VT: MVT::i32, Glue: InGlue);
1191 Chain = Hi.getValue(R: 1);
1192 InGlue = Hi.getValue(R: 2);
1193 Vec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: MVT::v2i32, N1: Vec, N2: Hi,
1194 N3: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i32));
1195 InVals.push_back(Elt: Vec);
1196 } else {
1197 Chain =
1198 DAG.getCopyFromReg(Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i].getLocReg()),
1199 VT: RVLocs[i].getValVT(), Glue: InGlue)
1200 .getValue(R: 1);
1201 InGlue = Chain.getValue(R: 2);
1202 InVals.push_back(Elt: Chain.getValue(R: 0));
1203 }
1204 }
1205
1206 return Chain;
1207}
1208
1209// FIXME? Maybe this could be a TableGen attribute on some registers and
1210// this table could be generated automatically from RegInfo.
1211Register SparcTargetLowering::getRegisterByName(const char* RegName, LLT VT,
1212 const MachineFunction &MF) const {
1213 Register Reg = StringSwitch<Register>(RegName)
1214 .Case(S: "i0", Value: SP::I0).Case(S: "i1", Value: SP::I1).Case(S: "i2", Value: SP::I2).Case(S: "i3", Value: SP::I3)
1215 .Case(S: "i4", Value: SP::I4).Case(S: "i5", Value: SP::I5).Case(S: "i6", Value: SP::I6).Case(S: "i7", Value: SP::I7)
1216 .Case(S: "o0", Value: SP::O0).Case(S: "o1", Value: SP::O1).Case(S: "o2", Value: SP::O2).Case(S: "o3", Value: SP::O3)
1217 .Case(S: "o4", Value: SP::O4).Case(S: "o5", Value: SP::O5).Case(S: "o6", Value: SP::O6).Case(S: "o7", Value: SP::O7)
1218 .Case(S: "l0", Value: SP::L0).Case(S: "l1", Value: SP::L1).Case(S: "l2", Value: SP::L2).Case(S: "l3", Value: SP::L3)
1219 .Case(S: "l4", Value: SP::L4).Case(S: "l5", Value: SP::L5).Case(S: "l6", Value: SP::L6).Case(S: "l7", Value: SP::L7)
1220 .Case(S: "g0", Value: SP::G0).Case(S: "g1", Value: SP::G1).Case(S: "g2", Value: SP::G2).Case(S: "g3", Value: SP::G3)
1221 .Case(S: "g4", Value: SP::G4).Case(S: "g5", Value: SP::G5).Case(S: "g6", Value: SP::G6).Case(S: "g7", Value: SP::G7)
1222 .Default(Value: 0);
1223
1224 // If we're directly referencing register names
1225 // (e.g in GCC C extension `register int r asm("g1");`),
1226 // make sure that said register is in the reserve list.
1227 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1228 if (!TRI->isReservedReg(MF, Reg))
1229 Reg = Register();
1230
1231 return Reg;
1232}
1233
1234// Fixup floating point arguments in the ... part of a varargs call.
1235//
1236// The SPARC v9 ABI requires that floating point arguments are treated the same
1237// as integers when calling a varargs function. This does not apply to the
1238// fixed arguments that are part of the function's prototype.
1239//
1240// This function post-processes a CCValAssign array created by
1241// AnalyzeCallOperands().
1242static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1243 ArrayRef<ISD::OutputArg> Outs) {
1244 for (CCValAssign &VA : ArgLocs) {
1245 MVT ValTy = VA.getLocVT();
1246 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1247 // varargs functions.
1248 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1249 continue;
1250 // The fixed arguments to a varargs function still go in FP registers.
1251 if (!Outs[VA.getValNo()].Flags.isVarArg())
1252 continue;
1253
1254 // This floating point argument should be reassigned.
1255 // Determine the offset into the argument array.
1256 Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1257 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1258 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1259 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1260
1261 if (Offset < 6*8) {
1262 // This argument should go in %i0-%i5.
1263 unsigned IReg = SP::I0 + Offset/8;
1264 if (ValTy == MVT::f64)
1265 // Full register, just bitconvert into i64.
1266 VA = CCValAssign::getReg(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Reg: IReg, LocVT: MVT::i64,
1267 HTP: CCValAssign::BCvt);
1268 else {
1269 assert(ValTy == MVT::f128 && "Unexpected type!");
1270 // Full register, just bitconvert into i128 -- We will lower this into
1271 // two i64s in LowerCall_64.
1272 VA = CCValAssign::getCustomReg(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Reg: IReg,
1273 LocVT: MVT::i128, HTP: CCValAssign::BCvt);
1274 }
1275 } else {
1276 // This needs to go to memory, we're out of integer registers.
1277 VA = CCValAssign::getMem(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Offset,
1278 LocVT: VA.getLocVT(), HTP: VA.getLocInfo());
1279 }
1280 }
1281}
1282
1283// Lower a call for the 64-bit ABI.
1284SDValue
1285SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1286 SmallVectorImpl<SDValue> &InVals) const {
1287 SelectionDAG &DAG = CLI.DAG;
1288 SDLoc DL = CLI.DL;
1289 SDValue Chain = CLI.Chain;
1290 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
1291 MachineFunction &MF = DAG.getMachineFunction();
1292
1293 // Analyze operands of the call, assigning locations to each operand.
1294 SmallVector<CCValAssign, 16> ArgLocs;
1295 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1296 *DAG.getContext());
1297 CCInfo.AnalyzeCallOperands(Outs: CLI.Outs, Fn: CC_Sparc64);
1298
1299 CLI.IsTailCall = CLI.IsTailCall && IsEligibleForTailCallOptimization(
1300 CCInfo, CLI, MF&: DAG.getMachineFunction());
1301
1302 // Get the size of the outgoing arguments stack space requirement.
1303 // The stack offset computed by CC_Sparc64 includes all arguments.
1304 // Called functions expect 6 argument words to exist in the stack frame, used
1305 // or not.
1306 unsigned StackReserved = 6 * 8u;
1307 unsigned ArgsSize = std::max<unsigned>(a: StackReserved, b: CCInfo.getStackSize());
1308
1309 // Keep stack frames 16-byte aligned.
1310 ArgsSize = alignTo(Value: ArgsSize, Align: 16);
1311
1312 // Varargs calls require special treatment.
1313 if (CLI.IsVarArg)
1314 fixupVariableFloatArgs(ArgLocs, Outs: CLI.Outs);
1315
1316 assert(!CLI.IsTailCall || ArgsSize == StackReserved);
1317
1318 // Adjust the stack pointer to make room for the arguments.
1319 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1320 // with more than 6 arguments.
1321 if (!CLI.IsTailCall)
1322 Chain = DAG.getCALLSEQ_START(Chain, InSize: ArgsSize, OutSize: 0, DL);
1323
1324 // Collect the set of registers to pass to the function and their values.
1325 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1326 // instruction.
1327 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
1328
1329 // Collect chains from all the memory opeations that copy arguments to the
1330 // stack. They must follow the stack pointer adjustment above and precede the
1331 // call instruction itself.
1332 SmallVector<SDValue, 8> MemOpChains;
1333
1334 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1335 const CCValAssign &VA = ArgLocs[i];
1336 SDValue Arg = CLI.OutVals[i];
1337
1338 // Promote the value if needed.
1339 switch (VA.getLocInfo()) {
1340 default:
1341 llvm_unreachable("Unknown location info!");
1342 case CCValAssign::Full:
1343 break;
1344 case CCValAssign::SExt:
1345 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1346 break;
1347 case CCValAssign::ZExt:
1348 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1349 break;
1350 case CCValAssign::AExt:
1351 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1352 break;
1353 case CCValAssign::BCvt:
1354 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1355 // SPARC does not support i128 natively. Lower it into two i64, see below.
1356 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1357 || VA.getLocVT() != MVT::i128)
1358 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: VA.getLocVT(), Operand: Arg);
1359 break;
1360 }
1361
1362 if (VA.isRegLoc()) {
1363 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1364 && VA.getLocVT() == MVT::i128) {
1365 // Store and reload into the integer register reg and reg+1.
1366 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1367 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1368 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: PtrVT);
1369 SDValue HiPtrOff = DAG.getIntPtrConstant(Val: StackOffset, DL);
1370 HiPtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: HiPtrOff);
1371 SDValue LoPtrOff = DAG.getIntPtrConstant(Val: StackOffset + 8, DL);
1372 LoPtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: LoPtrOff);
1373
1374 // Store to %sp+BIAS+128+Offset
1375 SDValue Store =
1376 DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: HiPtrOff, PtrInfo: MachinePointerInfo());
1377 // Load into Reg and Reg+1
1378 SDValue Hi64 =
1379 DAG.getLoad(VT: MVT::i64, dl: DL, Chain: Store, Ptr: HiPtrOff, PtrInfo: MachinePointerInfo());
1380 SDValue Lo64 =
1381 DAG.getLoad(VT: MVT::i64, dl: DL, Chain: Store, Ptr: LoPtrOff, PtrInfo: MachinePointerInfo());
1382
1383 Register HiReg = VA.getLocReg();
1384 Register LoReg = VA.getLocReg() + 1;
1385 if (!CLI.IsTailCall) {
1386 HiReg = toCallerWindow(Reg: HiReg);
1387 LoReg = toCallerWindow(Reg: LoReg);
1388 }
1389
1390 RegsToPass.push_back(Elt: std::make_pair(x&: HiReg, y&: Hi64));
1391 RegsToPass.push_back(Elt: std::make_pair(x&: LoReg, y&: Lo64));
1392 continue;
1393 }
1394
1395 // The custom bit on an i32 return value indicates that it should be
1396 // passed in the high bits of the register.
1397 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1398 Arg = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: Arg,
1399 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
1400
1401 // The next value may go in the low bits of the same register.
1402 // Handle both at once.
1403 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1404 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1405 SDValue NV = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i64,
1406 Operand: CLI.OutVals[i+1]);
1407 Arg = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i64, N1: Arg, N2: NV);
1408 // Skip the next value, it's already done.
1409 ++i;
1410 }
1411 }
1412
1413 Register Reg = VA.getLocReg();
1414 if (!CLI.IsTailCall)
1415 Reg = toCallerWindow(Reg);
1416 RegsToPass.push_back(Elt: std::make_pair(x&: Reg, y&: Arg));
1417 continue;
1418 }
1419
1420 assert(VA.isMemLoc());
1421
1422 // Create a store off the stack pointer for this argument.
1423 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: PtrVT);
1424 // The argument area starts at %fp+BIAS+128 in the callee frame,
1425 // %sp+BIAS+128 in ours.
1426 SDValue PtrOff = DAG.getIntPtrConstant(Val: VA.getLocMemOffset() +
1427 Subtarget->getStackPointerBias() +
1428 128, DL);
1429 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: PtrOff);
1430 MemOpChains.push_back(
1431 Elt: DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1432 }
1433
1434 // Emit all stores, make sure they occur before the call.
1435 if (!MemOpChains.empty())
1436 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOpChains);
1437
1438 // Build a sequence of CopyToReg nodes glued together with token chain and
1439 // glue operands which copy the outgoing args into registers. The InGlue is
1440 // necessary since all emitted instructions must be stuck together in order
1441 // to pass the live physical registers.
1442 SDValue InGlue;
1443 for (const auto &[Reg, N] : RegsToPass) {
1444 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg, N, Glue: InGlue);
1445 InGlue = Chain.getValue(R: 1);
1446 }
1447
1448 // If the callee is a GlobalAddress node (quite common, every direct call is)
1449 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1450 // Likewise ExternalSymbol -> TargetExternalSymbol.
1451 SDValue Callee = CLI.Callee;
1452 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, Call: CLI.CB);
1453 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
1454 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL, VT: PtrVT, offset: 0);
1455 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee))
1456 Callee = DAG.getTargetExternalSymbol(Sym: E->getSymbol(), VT: PtrVT);
1457
1458 // Build the operands for the call instruction itself.
1459 SmallVector<SDValue, 8> Ops;
1460 Ops.push_back(Elt: Chain);
1461 Ops.push_back(Elt: Callee);
1462 for (const auto &[Reg, N] : RegsToPass)
1463 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
1464
1465 // Add a register mask operand representing the call-preserved registers.
1466 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1467 const uint32_t *Mask =
1468 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CC: CLI.CallConv)
1469 : TRI->getCallPreservedMask(MF: DAG.getMachineFunction(),
1470 CC: CLI.CallConv));
1471
1472 if (isAnyArgRegReserved(TRI, MF))
1473 emitReservedArgRegCallError(MF);
1474
1475 assert(Mask && "Missing call preserved mask for calling convention");
1476 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
1477
1478 // Make sure the CopyToReg nodes are glued to the call instruction which
1479 // consumes the registers.
1480 if (InGlue.getNode())
1481 Ops.push_back(Elt: InGlue);
1482
1483 // Now the call itself.
1484 if (CLI.IsTailCall) {
1485 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
1486 return DAG.getNode(Opcode: SPISD::TAIL_CALL, DL, VT: MVT::Other, Ops);
1487 }
1488 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1489 Chain = DAG.getNode(Opcode: SPISD::CALL, DL, VTList: NodeTys, Ops);
1490 InGlue = Chain.getValue(R: 1);
1491
1492 // Revert the stack pointer immediately after the call.
1493 Chain = DAG.getCALLSEQ_END(Chain, Size1: ArgsSize, Size2: 0, Glue: InGlue, DL);
1494 InGlue = Chain.getValue(R: 1);
1495
1496 // Now extract the return values. This is more or less the same as
1497 // LowerFormalArguments_64.
1498
1499 // Assign locations to each value returned by this call.
1500 SmallVector<CCValAssign, 16> RVLocs;
1501 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1502 *DAG.getContext());
1503
1504 // Set inreg flag manually for codegen generated library calls that
1505 // return float.
1506 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB)
1507 CLI.Ins[0].Flags.setInReg();
1508
1509 RVInfo.AnalyzeCallResult(Ins: CLI.Ins, Fn: RetCC_Sparc64);
1510
1511 // Copy all of the result registers out of their specified physreg.
1512 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1513 CCValAssign &VA = RVLocs[i];
1514 assert(VA.isRegLoc() && "Can only return in registers!");
1515 unsigned Reg = toCallerWindow(Reg: VA.getLocReg());
1516
1517 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1518 // reside in the same register in the high and low bits. Reuse the
1519 // CopyFromReg previous node to avoid duplicate copies.
1520 SDValue RV;
1521 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Val: Chain.getOperand(i: 1)))
1522 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1523 RV = Chain.getValue(R: 0);
1524
1525 // But usually we'll create a new CopyFromReg for a different register.
1526 if (!RV.getNode()) {
1527 RV = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: RVLocs[i].getLocVT(), Glue: InGlue);
1528 Chain = RV.getValue(R: 1);
1529 InGlue = Chain.getValue(R: 2);
1530 }
1531
1532 // Get the high bits for i32 struct elements.
1533 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1534 RV = DAG.getNode(Opcode: ISD::SRL, DL, VT: VA.getLocVT(), N1: RV,
1535 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
1536
1537 // The callee promoted the return value, so insert an Assert?ext SDNode so
1538 // we won't promote the value again in this function.
1539 switch (VA.getLocInfo()) {
1540 case CCValAssign::SExt:
1541 RV = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: RV,
1542 N2: DAG.getValueType(VA.getValVT()));
1543 break;
1544 case CCValAssign::ZExt:
1545 RV = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: RV,
1546 N2: DAG.getValueType(VA.getValVT()));
1547 break;
1548 default:
1549 break;
1550 }
1551
1552 // Truncate the register down to the return value type.
1553 if (VA.isExtInLoc())
1554 RV = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: RV);
1555
1556 InVals.push_back(Elt: RV);
1557 }
1558
1559 return Chain;
1560}
1561
1562//===----------------------------------------------------------------------===//
1563// TargetLowering Implementation
1564//===----------------------------------------------------------------------===//
1565
1566TargetLowering::AtomicExpansionKind
1567SparcTargetLowering::shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const {
1568 if (AI->getOperation() == AtomicRMWInst::Xchg &&
1569 AI->getType()->getPrimitiveSizeInBits() == 32)
1570 return AtomicExpansionKind::None; // Uses xchg instruction
1571
1572 return AtomicExpansionKind::CmpXChg;
1573}
1574
1575/// intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC
1576/// rcond condition.
1577static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC) {
1578 switch (CC) {
1579 default:
1580 llvm_unreachable("Unknown/unsigned integer condition code!");
1581 case ISD::SETEQ:
1582 return SPCC::REG_Z;
1583 case ISD::SETNE:
1584 return SPCC::REG_NZ;
1585 case ISD::SETLT:
1586 return SPCC::REG_LZ;
1587 case ISD::SETGT:
1588 return SPCC::REG_GZ;
1589 case ISD::SETLE:
1590 return SPCC::REG_LEZ;
1591 case ISD::SETGE:
1592 return SPCC::REG_GEZ;
1593 }
1594}
1595
1596/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1597/// condition.
1598static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1599 switch (CC) {
1600 default: llvm_unreachable("Unknown integer condition code!");
1601 case ISD::SETEQ: return SPCC::ICC_E;
1602 case ISD::SETNE: return SPCC::ICC_NE;
1603 case ISD::SETLT: return SPCC::ICC_L;
1604 case ISD::SETGT: return SPCC::ICC_G;
1605 case ISD::SETLE: return SPCC::ICC_LE;
1606 case ISD::SETGE: return SPCC::ICC_GE;
1607 case ISD::SETULT: return SPCC::ICC_CS;
1608 case ISD::SETULE: return SPCC::ICC_LEU;
1609 case ISD::SETUGT: return SPCC::ICC_GU;
1610 case ISD::SETUGE: return SPCC::ICC_CC;
1611 }
1612}
1613
1614/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1615/// FCC condition.
1616static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1617 switch (CC) {
1618 default: llvm_unreachable("Unknown fp condition code!");
1619 case ISD::SETEQ:
1620 case ISD::SETOEQ: return SPCC::FCC_E;
1621 case ISD::SETNE:
1622 case ISD::SETUNE: return SPCC::FCC_NE;
1623 case ISD::SETLT:
1624 case ISD::SETOLT: return SPCC::FCC_L;
1625 case ISD::SETGT:
1626 case ISD::SETOGT: return SPCC::FCC_G;
1627 case ISD::SETLE:
1628 case ISD::SETOLE: return SPCC::FCC_LE;
1629 case ISD::SETGE:
1630 case ISD::SETOGE: return SPCC::FCC_GE;
1631 case ISD::SETULT: return SPCC::FCC_UL;
1632 case ISD::SETULE: return SPCC::FCC_ULE;
1633 case ISD::SETUGT: return SPCC::FCC_UG;
1634 case ISD::SETUGE: return SPCC::FCC_UGE;
1635 case ISD::SETUO: return SPCC::FCC_U;
1636 case ISD::SETO: return SPCC::FCC_O;
1637 case ISD::SETONE: return SPCC::FCC_LG;
1638 case ISD::SETUEQ: return SPCC::FCC_UE;
1639 }
1640}
1641
1642SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
1643 const SparcSubtarget &STI)
1644 : TargetLowering(TM, STI), Subtarget(&STI) {
1645 MVT PtrVT = MVT::getIntegerVT(BitWidth: TM.getPointerSizeInBits(AS: 0));
1646
1647 // Instructions which use registers as conditionals examine all the
1648 // bits (as does the pseudo SELECT_CC expansion). I don't think it
1649 // matters much whether it's ZeroOrOneBooleanContent, or
1650 // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
1651 // former.
1652 setBooleanContents(ZeroOrOneBooleanContent);
1653 setBooleanVectorContents(ZeroOrOneBooleanContent);
1654
1655 // Set up the register classes.
1656 addRegisterClass(VT: MVT::i32, RC: &SP::IntRegsRegClass);
1657 if (!Subtarget->useSoftFloat()) {
1658 addRegisterClass(VT: MVT::f32, RC: &SP::FPRegsRegClass);
1659 addRegisterClass(VT: MVT::f64, RC: &SP::DFPRegsRegClass);
1660 addRegisterClass(VT: MVT::f128, RC: &SP::QFPRegsRegClass);
1661 }
1662 if (Subtarget->is64Bit()) {
1663 addRegisterClass(VT: MVT::i64, RC: &SP::I64RegsRegClass);
1664 } else {
1665 // On 32bit sparc, we define a double-register 32bit register
1666 // class, as well. This is modeled in LLVM as a 2-vector of i32.
1667 addRegisterClass(VT: MVT::v2i32, RC: &SP::IntPairRegClass);
1668
1669 // ...but almost all operations must be expanded, so set that as
1670 // the default.
1671 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
1672 setOperationAction(Op, VT: MVT::v2i32, Action: Expand);
1673 }
1674 // Truncating/extending stores/loads are also not supported.
1675 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
1676 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1677 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1678 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1679
1680 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1681 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1682 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1683
1684 setTruncStoreAction(ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1685 setTruncStoreAction(ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1686 }
1687 // However, load and store *are* legal.
1688 setOperationAction(Op: ISD::LOAD, VT: MVT::v2i32, Action: Legal);
1689 setOperationAction(Op: ISD::STORE, VT: MVT::v2i32, Action: Legal);
1690 setOperationAction(Op: ISD::EXTRACT_VECTOR_ELT, VT: MVT::v2i32, Action: Legal);
1691 setOperationAction(Op: ISD::BUILD_VECTOR, VT: MVT::v2i32, Action: Legal);
1692
1693 // And we need to promote i64 loads/stores into vector load/store
1694 setOperationAction(Op: ISD::LOAD, VT: MVT::i64, Action: Custom);
1695 setOperationAction(Op: ISD::STORE, VT: MVT::i64, Action: Custom);
1696
1697 // Sadly, this doesn't work:
1698 // AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
1699 // AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
1700 }
1701
1702 // Turn FP extload into load/fpextend
1703 for (MVT VT : MVT::fp_valuetypes()) {
1704 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f16, Action: Expand);
1705 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f32, Action: Expand);
1706 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f64, Action: Expand);
1707 }
1708
1709 // Sparc doesn't have i1 sign extending load
1710 for (MVT VT : MVT::integer_valuetypes())
1711 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
1712
1713 // Turn FP truncstore into trunc + store.
1714 setTruncStoreAction(ValVT: MVT::f32, MemVT: MVT::f16, Action: Expand);
1715 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f16, Action: Expand);
1716 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f32, Action: Expand);
1717 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f16, Action: Expand);
1718 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f32, Action: Expand);
1719 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f64, Action: Expand);
1720
1721 // Custom legalize GlobalAddress nodes into LO/HI parts.
1722 setOperationAction(Op: ISD::GlobalAddress, VT: PtrVT, Action: Custom);
1723 setOperationAction(Op: ISD::GlobalTLSAddress, VT: PtrVT, Action: Custom);
1724 setOperationAction(Op: ISD::ConstantPool, VT: PtrVT, Action: Custom);
1725 setOperationAction(Op: ISD::BlockAddress, VT: PtrVT, Action: Custom);
1726
1727 // Sparc doesn't have sext_inreg, replace them with shl/sra
1728 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i16, Action: Expand);
1729 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i8 , Action: Expand);
1730 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i1 , Action: Expand);
1731
1732 // Sparc has no REM or DIVREM operations.
1733 setOperationAction(Op: ISD::UREM, VT: MVT::i32, Action: Expand);
1734 setOperationAction(Op: ISD::SREM, VT: MVT::i32, Action: Expand);
1735 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i32, Action: Expand);
1736 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i32, Action: Expand);
1737
1738 // ... nor does SparcV9.
1739 if (Subtarget->is64Bit()) {
1740 setOperationAction(Op: ISD::UREM, VT: MVT::i64, Action: Expand);
1741 setOperationAction(Op: ISD::SREM, VT: MVT::i64, Action: Expand);
1742 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i64, Action: Expand);
1743 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i64, Action: Expand);
1744 }
1745
1746 // Custom expand fp<->sint
1747 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::i32, Action: Custom);
1748 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::i32, Action: Custom);
1749 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::i64, Action: Custom);
1750 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::i64, Action: Custom);
1751
1752 // Custom Expand fp<->uint
1753 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i32, Action: Custom);
1754 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i32, Action: Custom);
1755 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i64, Action: Custom);
1756 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i64, Action: Custom);
1757
1758 // Lower f16 conversion operations into library calls
1759 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f32, Action: Expand);
1760 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f32, Action: Expand);
1761 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f64, Action: Expand);
1762 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f64, Action: Expand);
1763 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f128, Action: Expand);
1764 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f128, Action: Expand);
1765
1766 setOperationAction(Op: ISD::BITCAST, VT: MVT::f32,
1767 Action: Subtarget->isVIS3() ? Legal : Expand);
1768 setOperationAction(Op: ISD::BITCAST, VT: MVT::i32,
1769 Action: Subtarget->isVIS3() ? Legal : Expand);
1770
1771 // Sparc has no select or setcc: expand to SELECT_CC.
1772 setOperationAction(Op: ISD::SELECT, VT: MVT::i32, Action: Expand);
1773 setOperationAction(Op: ISD::SELECT, VT: MVT::f32, Action: Expand);
1774 setOperationAction(Op: ISD::SELECT, VT: MVT::f64, Action: Expand);
1775 setOperationAction(Op: ISD::SELECT, VT: MVT::f128, Action: Expand);
1776
1777 setOperationAction(Op: ISD::SETCC, VT: MVT::i32, Action: Expand);
1778 setOperationAction(Op: ISD::SETCC, VT: MVT::f32, Action: Expand);
1779 setOperationAction(Op: ISD::SETCC, VT: MVT::f64, Action: Expand);
1780 setOperationAction(Op: ISD::SETCC, VT: MVT::f128, Action: Expand);
1781
1782 // Sparc doesn't have BRCOND either, it has BR_CC.
1783 setOperationAction(Op: ISD::BRCOND, VT: MVT::Other, Action: Expand);
1784 setOperationAction(Op: ISD::BRIND, VT: MVT::Other, Action: Expand);
1785 setOperationAction(Op: ISD::BR_JT, VT: MVT::Other, Action: Expand);
1786 setOperationAction(Op: ISD::BR_CC, VT: MVT::i32, Action: Custom);
1787 setOperationAction(Op: ISD::BR_CC, VT: MVT::f32, Action: Custom);
1788 setOperationAction(Op: ISD::BR_CC, VT: MVT::f64, Action: Custom);
1789 setOperationAction(Op: ISD::BR_CC, VT: MVT::f128, Action: Custom);
1790
1791 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i32, Action: Custom);
1792 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f32, Action: Custom);
1793 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f64, Action: Custom);
1794 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f128, Action: Custom);
1795
1796 setOperationAction(Op: ISD::ADDC, VT: MVT::i32, Action: Legal);
1797 setOperationAction(Op: ISD::ADDE, VT: MVT::i32, Action: Legal);
1798 setOperationAction(Op: ISD::SUBC, VT: MVT::i32, Action: Legal);
1799 setOperationAction(Op: ISD::SUBE, VT: MVT::i32, Action: Legal);
1800
1801 if (Subtarget->isVIS3()) {
1802 setOperationAction(Op: ISD::ADDC, VT: MVT::i64, Action: Legal);
1803 setOperationAction(Op: ISD::ADDE, VT: MVT::i64, Action: Legal);
1804 }
1805
1806 if (Subtarget->is64Bit()) {
1807 setOperationAction(Op: ISD::BITCAST, VT: MVT::f64,
1808 Action: Subtarget->isVIS3() ? Legal : Expand);
1809 setOperationAction(Op: ISD::BITCAST, VT: MVT::i64,
1810 Action: Subtarget->isVIS3() ? Legal : Expand);
1811 setOperationAction(Op: ISD::SELECT, VT: MVT::i64, Action: Expand);
1812 setOperationAction(Op: ISD::SETCC, VT: MVT::i64, Action: Expand);
1813 setOperationAction(Op: ISD::BR_CC, VT: MVT::i64, Action: Custom);
1814 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i64, Action: Custom);
1815
1816 setOperationAction(Op: ISD::CTPOP, VT: MVT::i64,
1817 Action: Subtarget->usePopc() ? Legal : Expand);
1818 setOperationAction(Op: ISD::BSWAP, VT: MVT::i64, Action: Custom);
1819 setOperationAction(Op: ISD::ROTL , VT: MVT::i64, Action: Expand);
1820 setOperationAction(Op: ISD::ROTR , VT: MVT::i64, Action: Expand);
1821 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i64, Action: Custom);
1822 }
1823
1824 // ATOMICs.
1825 // Atomics are supported on SparcV9. 32-bit atomics are also
1826 // supported by some Leon SparcV8 variants. Otherwise, atomics
1827 // are unsupported.
1828 if (Subtarget->isV9()) {
1829 // TODO: we _ought_ to be able to support 64-bit atomics on 32-bit sparcv9,
1830 // but it hasn't been implemented in the backend yet.
1831 if (Subtarget->is64Bit())
1832 setMaxAtomicSizeInBitsSupported(64);
1833 else
1834 setMaxAtomicSizeInBitsSupported(32);
1835 } else if (Subtarget->hasLeonCasa())
1836 setMaxAtomicSizeInBitsSupported(32);
1837 else
1838 setMaxAtomicSizeInBitsSupported(0);
1839
1840 setMinCmpXchgSizeInBits(32);
1841
1842 setOperationAction(Op: ISD::ATOMIC_SWAP, VT: MVT::i32, Action: Legal);
1843
1844 setOperationAction(Op: ISD::ATOMIC_FENCE, VT: MVT::Other, Action: Legal);
1845
1846 // Custom Lower Atomic LOAD/STORE
1847 setOperationAction(Op: ISD::ATOMIC_LOAD, VT: MVT::i32, Action: Custom);
1848 setOperationAction(Op: ISD::ATOMIC_STORE, VT: MVT::i32, Action: Custom);
1849
1850 if (Subtarget->is64Bit()) {
1851 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP, VT: MVT::i64, Action: Legal);
1852 setOperationAction(Op: ISD::ATOMIC_SWAP, VT: MVT::i64, Action: Legal);
1853 setOperationAction(Op: ISD::ATOMIC_LOAD, VT: MVT::i64, Action: Custom);
1854 setOperationAction(Op: ISD::ATOMIC_STORE, VT: MVT::i64, Action: Custom);
1855 }
1856
1857 if (!Subtarget->isV9()) {
1858 // SparcV8 does not have FNEGD and FABSD.
1859 setOperationAction(Op: ISD::FNEG, VT: MVT::f64, Action: Custom);
1860 setOperationAction(Op: ISD::FABS, VT: MVT::f64, Action: Custom);
1861 }
1862
1863 setOperationAction(Op: ISD::FSIN , VT: MVT::f128, Action: Expand);
1864 setOperationAction(Op: ISD::FCOS , VT: MVT::f128, Action: Expand);
1865 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f128, Action: Expand);
1866 setOperationAction(Op: ISD::FREM, VT: MVT::f128, Action: LibCall);
1867 setOperationAction(Op: ISD::FMA , VT: MVT::f128, Action: Expand);
1868 setOperationAction(Op: ISD::FSIN , VT: MVT::f64, Action: Expand);
1869 setOperationAction(Op: ISD::FCOS , VT: MVT::f64, Action: Expand);
1870 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f64, Action: Expand);
1871 setOperationAction(Op: ISD::FREM, VT: MVT::f64, Action: LibCall);
1872 setOperationAction(Op: ISD::FMA, VT: MVT::f64,
1873 Action: Subtarget->isUA2007() ? Legal : Expand);
1874 setOperationAction(Op: ISD::FSIN , VT: MVT::f32, Action: Expand);
1875 setOperationAction(Op: ISD::FCOS , VT: MVT::f32, Action: Expand);
1876 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f32, Action: Expand);
1877 setOperationAction(Op: ISD::FREM, VT: MVT::f32, Action: LibCall);
1878 setOperationAction(Op: ISD::FMA, VT: MVT::f32,
1879 Action: Subtarget->isUA2007() ? Legal : Expand);
1880 setOperationAction(Op: ISD::ROTL , VT: MVT::i32, Action: Expand);
1881 setOperationAction(Op: ISD::ROTR , VT: MVT::i32, Action: Expand);
1882 setOperationAction(Op: ISD::BSWAP, VT: MVT::i32, Action: Subtarget->isV9() ? Custom : Expand);
1883 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f128, Action: Expand);
1884 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f64, Action: Expand);
1885 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f32, Action: Expand);
1886 setOperationAction(Op: ISD::FPOW , VT: MVT::f128, Action: Expand);
1887 setOperationAction(Op: ISD::FPOW , VT: MVT::f64, Action: Expand);
1888 setOperationAction(Op: ISD::FPOW , VT: MVT::f32, Action: Expand);
1889
1890 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i32, Action: Expand);
1891 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i32, Action: Expand);
1892 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i32, Action: Expand);
1893
1894 // Expands to [SU]MUL_LOHI.
1895 setOperationAction(Op: ISD::MULHU, VT: MVT::i32, Action: Expand);
1896 setOperationAction(Op: ISD::MULHS, VT: MVT::i32, Action: Expand);
1897 setOperationAction(Op: ISD::MUL, VT: MVT::i32, Action: Expand);
1898
1899 if (Subtarget->useSoftMulDiv()) {
1900 // .umul works for both signed and unsigned
1901 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i32, Action: Expand);
1902 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i32, Action: Expand);
1903 setOperationAction(Op: ISD::SDIV, VT: MVT::i32, Action: Expand);
1904 setOperationAction(Op: ISD::UDIV, VT: MVT::i32, Action: Expand);
1905 }
1906
1907 if (Subtarget->is64Bit()) {
1908 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i64, Action: Expand);
1909 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i64, Action: Expand);
1910 setOperationAction(Op: ISD::MULHU, VT: MVT::i64,
1911 Action: Subtarget->isVIS3() ? Legal : Expand);
1912 setOperationAction(Op: ISD::MULHS, VT: MVT::i64,
1913 Action: Subtarget->isVIS3() ? Legal : Expand);
1914
1915 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i64, Action: Expand);
1916 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i64, Action: Expand);
1917 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i64, Action: Expand);
1918 }
1919
1920 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1921 setOperationAction(Op: ISD::VASTART , VT: MVT::Other, Action: Custom);
1922 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1923 setOperationAction(Op: ISD::VAARG , VT: MVT::Other, Action: Custom);
1924
1925 setOperationAction(Op: ISD::TRAP , VT: MVT::Other, Action: Legal);
1926 setOperationAction(Op: ISD::DEBUGTRAP , VT: MVT::Other, Action: Legal);
1927
1928 // Use the default implementation.
1929 setOperationAction(Op: ISD::VACOPY , VT: MVT::Other, Action: Expand);
1930 setOperationAction(Op: ISD::VAEND , VT: MVT::Other, Action: Expand);
1931 setOperationAction(Op: ISD::STACKSAVE , VT: MVT::Other, Action: Expand);
1932 setOperationAction(Op: ISD::STACKRESTORE , VT: MVT::Other, Action: Expand);
1933 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i32 , Action: Custom);
1934 setOperationAction(Op: ISD::STACKADDRESS, VT: MVT::Other, Action: Custom);
1935
1936 setStackPointerRegisterToSaveRestore(SP::O6);
1937
1938 setOperationAction(Op: ISD::CTPOP, VT: MVT::i32,
1939 Action: Subtarget->usePopc() ? Legal : Expand);
1940
1941 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1942 setOperationAction(Op: ISD::LOAD, VT: MVT::f128, Action: Legal);
1943 setOperationAction(Op: ISD::STORE, VT: MVT::f128, Action: Legal);
1944 } else {
1945 setOperationAction(Op: ISD::LOAD, VT: MVT::f128, Action: Custom);
1946 setOperationAction(Op: ISD::STORE, VT: MVT::f128, Action: Custom);
1947 }
1948
1949 if (Subtarget->hasHardQuad()) {
1950 setOperationAction(Op: ISD::FADD, VT: MVT::f128, Action: Legal);
1951 setOperationAction(Op: ISD::FSUB, VT: MVT::f128, Action: Legal);
1952 setOperationAction(Op: ISD::FMUL, VT: MVT::f128, Action: Legal);
1953 setOperationAction(Op: ISD::FDIV, VT: MVT::f128, Action: Legal);
1954 setOperationAction(Op: ISD::FSQRT, VT: MVT::f128, Action: Legal);
1955 setOperationAction(Op: ISD::FP_EXTEND, VT: MVT::f128, Action: Legal);
1956 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f64, Action: Legal);
1957 if (Subtarget->isV9()) {
1958 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Legal);
1959 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Legal);
1960 } else {
1961 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Custom);
1962 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Custom);
1963 }
1964 } else {
1965 // Custom legalize f128 operations.
1966
1967 setOperationAction(Op: ISD::FADD, VT: MVT::f128, Action: Custom);
1968 setOperationAction(Op: ISD::FSUB, VT: MVT::f128, Action: Custom);
1969 setOperationAction(Op: ISD::FMUL, VT: MVT::f128, Action: Custom);
1970 setOperationAction(Op: ISD::FDIV, VT: MVT::f128, Action: Custom);
1971 setOperationAction(Op: ISD::FSQRT, VT: MVT::f128, Action: Custom);
1972 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Custom);
1973 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Custom);
1974
1975 setOperationAction(Op: ISD::FP_EXTEND, VT: MVT::f128, Action: Custom);
1976 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f64, Action: Custom);
1977 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f32, Action: Custom);
1978 }
1979
1980 if (Subtarget->fixAllFDIVSQRT()) {
1981 // Promote FDIVS and FSQRTS to FDIVD and FSQRTD instructions instead as
1982 // the former instructions generate errata on LEON processors.
1983 setOperationAction(Op: ISD::FDIV, VT: MVT::f32, Action: Promote);
1984 setOperationAction(Op: ISD::FSQRT, VT: MVT::f32, Action: Promote);
1985 }
1986
1987 if (Subtarget->hasNoFMULS()) {
1988 setOperationAction(Op: ISD::FMUL, VT: MVT::f32, Action: Promote);
1989 }
1990
1991 // Custom combine bitcast between f64 and v2i32
1992 if (!Subtarget->is64Bit())
1993 setTargetDAGCombine(ISD::BITCAST);
1994
1995 if (Subtarget->isV9())
1996 setTargetDAGCombine({ISD::BSWAP, ISD::STORE});
1997
1998 if (Subtarget->hasLeonCycleCounter())
1999 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Custom);
2000
2001 if (Subtarget->isVIS3()) {
2002 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Legal);
2003 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Legal);
2004 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i32, Action: Legal);
2005 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i64, Action: Legal);
2006
2007 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32,
2008 Action: Subtarget->is64Bit() ? Promote : Expand);
2009 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
2010 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i32,
2011 Action: Subtarget->is64Bit() ? Promote : Expand);
2012 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i64, Action: Expand);
2013 } else if (Subtarget->usePopc()) {
2014 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Expand);
2015 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Expand);
2016 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i32, Action: Expand);
2017 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i64, Action: Expand);
2018
2019 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32, Action: Expand);
2020 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
2021 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i32, Action: Expand);
2022 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i64, Action: Expand);
2023 } else {
2024 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Expand);
2025 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Expand);
2026 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i32,
2027 Action: Subtarget->is64Bit() ? Promote : LibCall);
2028 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i64, Action: LibCall);
2029
2030 // FIXME here we don't have any ISA extensions that could help us, so to
2031 // prevent large expansions those should be made into LibCalls.
2032 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32, Action: Expand);
2033 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
2034 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i32, Action: Expand);
2035 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i64, Action: Expand);
2036 }
2037
2038 setOperationAction(Op: ISD::INTRINSIC_WO_CHAIN, VT: MVT::Other, Action: Custom);
2039
2040 // Some processors have no branch predictor and have pipelines longer than
2041 // what can be covered by the delay slot. This results in a stall, so mark
2042 // branches to be expensive on those processors.
2043 setJumpIsExpensive(Subtarget->hasNoPredictor());
2044 // The high cost of branching means that using conditional moves will
2045 // still be profitable even if the condition is predictable.
2046 PredictableSelectIsExpensive = !isJumpExpensive();
2047
2048 setMinFunctionAlignment(Align(4));
2049
2050 computeRegisterProperties(TRI: Subtarget->getRegisterInfo());
2051}
2052
2053bool SparcTargetLowering::useSoftFloat() const {
2054 return Subtarget->useSoftFloat();
2055}
2056
2057EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
2058 EVT VT) const {
2059 if (!VT.isVector())
2060 return MVT::i32;
2061 return VT.changeVectorElementTypeToInteger();
2062}
2063
2064/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
2065/// be zero. Op is expected to be a target specific node. Used by DAG
2066/// combiner.
2067void SparcTargetLowering::computeKnownBitsForTargetNode
2068 (const SDValue Op,
2069 KnownBits &Known,
2070 const APInt &DemandedElts,
2071 const SelectionDAG &DAG,
2072 unsigned Depth) const {
2073 KnownBits Known2;
2074 Known.resetAll();
2075
2076 switch (Op.getOpcode()) {
2077 default: break;
2078 case SPISD::SELECT_ICC:
2079 case SPISD::SELECT_XCC:
2080 case SPISD::SELECT_FCC:
2081 Known = DAG.computeKnownBits(Op: Op.getOperand(i: 1), Depth: Depth + 1);
2082 Known2 = DAG.computeKnownBits(Op: Op.getOperand(i: 0), Depth: Depth + 1);
2083
2084 // Only known if known in both the LHS and RHS.
2085 Known = Known.intersectWith(RHS: Known2);
2086 break;
2087 }
2088}
2089
2090// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
2091// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
2092static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
2093 ISD::CondCode CC, unsigned &SPCC) {
2094 if (isNullConstant(V: RHS) && CC == ISD::SETNE &&
2095 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
2096 LHS.getOpcode() == SPISD::SELECT_XCC) &&
2097 LHS.getOperand(i: 3).getOpcode() == SPISD::CMPICC) ||
2098 (LHS.getOpcode() == SPISD::SELECT_FCC &&
2099 (LHS.getOperand(i: 3).getOpcode() == SPISD::CMPFCC ||
2100 LHS.getOperand(i: 3).getOpcode() == SPISD::CMPFCC_V9))) &&
2101 isOneConstant(V: LHS.getOperand(i: 0)) && isNullConstant(V: LHS.getOperand(i: 1))) {
2102 SDValue CMPCC = LHS.getOperand(i: 3);
2103 SPCC = LHS.getConstantOperandVal(i: 2);
2104 LHS = CMPCC.getOperand(i: 0);
2105 RHS = CMPCC.getOperand(i: 1);
2106 }
2107}
2108
2109// Convert to a target node and set target flags.
2110SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
2111 SelectionDAG &DAG) const {
2112 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Val&: Op))
2113 return DAG.getTargetGlobalAddress(GV: GA->getGlobal(),
2114 DL: SDLoc(GA),
2115 VT: GA->getValueType(ResNo: 0),
2116 offset: GA->getOffset(), TargetFlags: TF);
2117
2118 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Val&: Op))
2119 return DAG.getTargetConstantPool(C: CP->getConstVal(), VT: CP->getValueType(ResNo: 0),
2120 Align: CP->getAlign(), Offset: CP->getOffset(), TargetFlags: TF);
2121
2122 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Val&: Op))
2123 return DAG.getTargetBlockAddress(BA: BA->getBlockAddress(),
2124 VT: Op.getValueType(),
2125 Offset: 0,
2126 TargetFlags: TF);
2127
2128 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Val&: Op))
2129 return DAG.getTargetExternalSymbol(Sym: ES->getSymbol(),
2130 VT: ES->getValueType(ResNo: 0), TargetFlags: TF);
2131
2132 llvm_unreachable("Unhandled address SDNode");
2133}
2134
2135// Split Op into high and low parts according to HiTF and LoTF.
2136// Return an ADD node combining the parts.
2137SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
2138 unsigned HiTF, unsigned LoTF,
2139 SelectionDAG &DAG) const {
2140 SDLoc DL(Op);
2141 EVT VT = Op.getValueType();
2142 SDValue Hi = DAG.getNode(Opcode: SPISD::Hi, DL, VT, Operand: withTargetFlags(Op, TF: HiTF, DAG));
2143 SDValue Lo = DAG.getNode(Opcode: SPISD::Lo, DL, VT, Operand: withTargetFlags(Op, TF: LoTF, DAG));
2144 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Hi, N2: Lo);
2145}
2146
2147// Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
2148// or ExternalSymbol SDNode.
2149SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
2150 SDLoc DL(Op);
2151 EVT VT = getPointerTy(DL: DAG.getDataLayout());
2152
2153 // Handle PIC mode first. SPARC needs a got load for every variable!
2154 if (isPositionIndependent()) {
2155 const Module *M = DAG.getMachineFunction().getFunction().getParent();
2156 PICLevel::Level picLevel = M->getPICLevel();
2157 SDValue Idx;
2158
2159 if (picLevel == PICLevel::SmallPIC) {
2160 // This is the pic13 code model, the GOT is known to be smaller than 8KiB.
2161 Idx = DAG.getNode(Opcode: SPISD::Lo, DL, VT: Op.getValueType(),
2162 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_GOT13, DAG));
2163 } else {
2164 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
2165 Idx = makeHiLoPair(Op, HiTF: ELF::R_SPARC_GOT22, LoTF: ELF::R_SPARC_GOT10, DAG);
2166 }
2167
2168 SDValue GlobalBase = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT);
2169 SDValue AbsAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: GlobalBase, N2: Idx);
2170 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2171 // function has calls.
2172 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2173 MFI.setHasCalls(true);
2174 return DAG.getLoad(VT, dl: DL, Chain: DAG.getEntryNode(), Ptr: AbsAddr,
2175 PtrInfo: MachinePointerInfo::getGOT(MF&: DAG.getMachineFunction()));
2176 }
2177
2178 // This is one of the absolute code models.
2179 switch(getTargetMachine().getCodeModel()) {
2180 default:
2181 llvm_unreachable("Unsupported absolute code model");
2182 case CodeModel::Small:
2183 // abs32.
2184 return makeHiLoPair(Op, HiTF: ELF::R_SPARC_HI22, LoTF: ELF::R_SPARC_LO10, DAG);
2185 case CodeModel::Medium: {
2186 // abs44.
2187 SDValue H44 = makeHiLoPair(Op, HiTF: ELF::R_SPARC_H44, LoTF: ELF::R_SPARC_M44, DAG);
2188 H44 = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: H44, N2: DAG.getConstant(Val: 12, DL, VT: MVT::i32));
2189 SDValue L44 = withTargetFlags(Op, TF: ELF::R_SPARC_L44, DAG);
2190 L44 = DAG.getNode(Opcode: SPISD::Lo, DL, VT, Operand: L44);
2191 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: H44, N2: L44);
2192 }
2193 case CodeModel::Large: {
2194 // abs64.
2195 SDValue Hi = makeHiLoPair(Op, HiTF: ELF::R_SPARC_HH22, LoTF: ELF::R_SPARC_HM10, DAG);
2196 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi, N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
2197 SDValue Lo = makeHiLoPair(Op, HiTF: ELF::R_SPARC_HI22, LoTF: ELF::R_SPARC_LO10, DAG);
2198 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Hi, N2: Lo);
2199 }
2200 }
2201}
2202
2203SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
2204 SelectionDAG &DAG) const {
2205 return makeAddress(Op, DAG);
2206}
2207
2208SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
2209 SelectionDAG &DAG) const {
2210 return makeAddress(Op, DAG);
2211}
2212
2213SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
2214 SelectionDAG &DAG) const {
2215 return makeAddress(Op, DAG);
2216}
2217
2218SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2219 SelectionDAG &DAG) const {
2220
2221 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Val&: Op);
2222 if (DAG.getTarget().useEmulatedTLS())
2223 return LowerToTLSEmulatedModel(GA, DAG);
2224
2225 SDLoc DL(GA);
2226 const GlobalValue *GV = GA->getGlobal();
2227 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
2228
2229 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2230
2231 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2232 unsigned HiTF =
2233 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_HI22
2234 : ELF::R_SPARC_TLS_LDM_HI22);
2235 unsigned LoTF =
2236 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_LO10
2237 : ELF::R_SPARC_TLS_LDM_LO10);
2238 unsigned addTF =
2239 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_ADD
2240 : ELF::R_SPARC_TLS_LDM_ADD);
2241 unsigned callTF =
2242 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_CALL
2243 : ELF::R_SPARC_TLS_LDM_CALL);
2244
2245 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
2246 SDValue Base = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT: PtrVT);
2247 SDValue Argument = DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT, N1: Base, N2: HiLo,
2248 N3: withTargetFlags(Op, TF: addTF, DAG));
2249
2250 SDValue Chain = DAG.getEntryNode();
2251 SDValue InGlue;
2252
2253 Chain = DAG.getCALLSEQ_START(Chain, InSize: 0, OutSize: 0, DL);
2254 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SP::O0, N: Argument, Glue: InGlue);
2255 InGlue = Chain.getValue(R: 1);
2256 SDValue Callee = DAG.getTargetExternalSymbol(Sym: "__tls_get_addr", VT: PtrVT);
2257 SDValue Symbol = withTargetFlags(Op, TF: callTF, DAG);
2258
2259 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
2260 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
2261 MF: DAG.getMachineFunction(), CC: CallingConv::C);
2262 assert(Mask && "Missing call preserved mask for calling convention");
2263 SDValue Ops[] = {Chain,
2264 Callee,
2265 Symbol,
2266 DAG.getRegister(Reg: SP::O0, VT: PtrVT),
2267 DAG.getRegisterMask(RegMask: Mask),
2268 InGlue};
2269 Chain = DAG.getNode(Opcode: SPISD::TLS_CALL, DL, VTList: NodeTys, Ops);
2270 InGlue = Chain.getValue(R: 1);
2271 Chain = DAG.getCALLSEQ_END(Chain, Size1: 0, Size2: 0, Glue: InGlue, DL);
2272 InGlue = Chain.getValue(R: 1);
2273 SDValue Ret = DAG.getCopyFromReg(Chain, dl: DL, Reg: SP::O0, VT: PtrVT, Glue: InGlue);
2274
2275 if (model != TLSModel::LocalDynamic)
2276 return Ret;
2277
2278 SDValue Hi =
2279 DAG.getNode(Opcode: SPISD::Hi, DL, VT: PtrVT,
2280 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_HIX22, DAG));
2281 SDValue Lo =
2282 DAG.getNode(Opcode: SPISD::Lo, DL, VT: PtrVT,
2283 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_LOX10, DAG));
2284 HiLo = DAG.getNode(Opcode: ISD::XOR, DL, VT: PtrVT, N1: Hi, N2: Lo);
2285 return DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT, N1: Ret, N2: HiLo,
2286 N3: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_ADD, DAG));
2287 }
2288
2289 if (model == TLSModel::InitialExec) {
2290 unsigned ldTF = ((PtrVT == MVT::i64) ? ELF::R_SPARC_TLS_IE_LDX
2291 : ELF::R_SPARC_TLS_IE_LD);
2292
2293 SDValue Base = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT: PtrVT);
2294
2295 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2296 // function has calls.
2297 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2298 MFI.setHasCalls(true);
2299
2300 SDValue TGA = makeHiLoPair(Op, HiTF: ELF::R_SPARC_TLS_IE_HI22,
2301 LoTF: ELF::R_SPARC_TLS_IE_LO10, DAG);
2302 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: Base, N2: TGA);
2303 SDValue Offset = DAG.getNode(Opcode: SPISD::TLS_LD,
2304 DL, VT: PtrVT, N1: Ptr,
2305 N2: withTargetFlags(Op, TF: ldTF, DAG));
2306 return DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT,
2307 N1: DAG.getRegister(Reg: SP::G7, VT: PtrVT), N2: Offset,
2308 N3: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_IE_ADD, DAG));
2309 }
2310
2311 assert(model == TLSModel::LocalExec);
2312 SDValue Hi = DAG.getNode(Opcode: SPISD::Hi, DL, VT: PtrVT,
2313 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LE_HIX22, DAG));
2314 SDValue Lo = DAG.getNode(Opcode: SPISD::Lo, DL, VT: PtrVT,
2315 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LE_LOX10, DAG));
2316 SDValue Offset = DAG.getNode(Opcode: ISD::XOR, DL, VT: PtrVT, N1: Hi, N2: Lo);
2317
2318 return DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT,
2319 N1: DAG.getRegister(Reg: SP::G7, VT: PtrVT), N2: Offset);
2320}
2321
2322SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain,
2323 ArgListTy &Args, SDValue Arg,
2324 const SDLoc &DL,
2325 SelectionDAG &DAG) const {
2326 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2327 EVT ArgVT = Arg.getValueType();
2328 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
2329
2330 if (ArgTy->isFP128Ty()) {
2331 // Create a stack object and pass the pointer to the library function.
2332 int FI = MFI.CreateStackObject(Size: 16, Alignment: Align(8), isSpillSlot: false);
2333 SDValue FIPtr = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
2334 Chain = DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: FIPtr, PtrInfo: MachinePointerInfo(), Alignment: Align(8));
2335 Args.emplace_back(args&: FIPtr, args: PointerType::getUnqual(C&: ArgTy->getContext()));
2336 } else {
2337 Args.emplace_back(args&: Arg, args&: ArgTy);
2338 }
2339 return Chain;
2340}
2341
2342SDValue SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2343 RTLIB::Libcall LibFunc,
2344 unsigned numArgs) const {
2345 RTLIB::LibcallImpl LibFuncImpl = DAG.getLibcalls().getLibcallImpl(Call: LibFunc);
2346 if (LibFuncImpl == RTLIB::Unsupported)
2347 return SDValue();
2348
2349 ArgListTy Args;
2350
2351 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2352 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2353
2354 SDValue Callee = DAG.getExternalSymbol(LCImpl: LibFuncImpl, VT: PtrVT);
2355 Type *RetTy = Op.getValueType().getTypeForEVT(Context&: *DAG.getContext());
2356 Type *RetTyABI = RetTy;
2357 SDValue Chain = DAG.getEntryNode();
2358 SDValue RetPtr;
2359
2360 if (RetTy->isFP128Ty()) {
2361 // Create a Stack Object to receive the return value of type f128.
2362 int RetFI = MFI.CreateStackObject(Size: 16, Alignment: Align(8), isSpillSlot: false);
2363 RetPtr = DAG.getFrameIndex(FI: RetFI, VT: PtrVT);
2364 ArgListEntry Entry(RetPtr, PointerType::getUnqual(C&: RetTy->getContext()));
2365 if (!Subtarget->is64Bit()) {
2366 Entry.IsSRet = true;
2367 Entry.IndirectType = RetTy;
2368 }
2369 Entry.IsReturned = false;
2370 Args.push_back(x: Entry);
2371 RetTyABI = Type::getVoidTy(C&: *DAG.getContext());
2372 }
2373
2374 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2375 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2376 Chain = LowerF128_LibCallArg(Chain, Args, Arg: Op.getOperand(i), DL: SDLoc(Op), DAG);
2377 }
2378
2379 CallingConv::ID CC = DAG.getLibcalls().getLibcallImplCallingConv(Call: LibFuncImpl);
2380 TargetLowering::CallLoweringInfo CLI(DAG);
2381 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain).setCallee(CC, ResultType: RetTyABI, Target: Callee,
2382 ArgsList: std::move(Args));
2383
2384 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2385
2386 // chain is in second result.
2387 if (RetTyABI == RetTy)
2388 return CallInfo.first;
2389
2390 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2391
2392 Chain = CallInfo.second;
2393
2394 // Load RetPtr to get the return value.
2395 return DAG.getLoad(VT: Op.getValueType(), dl: SDLoc(Op), Chain, Ptr: RetPtr,
2396 PtrInfo: MachinePointerInfo(), Alignment: Align(8));
2397}
2398
2399SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2400 unsigned &SPCC, const SDLoc &DL,
2401 SelectionDAG &DAG) const {
2402
2403 const char *LibCall = nullptr;
2404 bool is64Bit = Subtarget->is64Bit();
2405 switch(SPCC) {
2406 default: llvm_unreachable("Unhandled conditional code!");
2407 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2408 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2409 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2410 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2411 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2412 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2413 case SPCC::FCC_UL :
2414 case SPCC::FCC_ULE:
2415 case SPCC::FCC_UG :
2416 case SPCC::FCC_UGE:
2417 case SPCC::FCC_U :
2418 case SPCC::FCC_O :
2419 case SPCC::FCC_LG :
2420 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2421 }
2422
2423 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2424 SDValue Callee = DAG.getExternalSymbol(Sym: LibCall, VT: PtrVT);
2425 Type *RetTy = Type::getInt32Ty(C&: *DAG.getContext());
2426 ArgListTy Args;
2427 SDValue Chain = DAG.getEntryNode();
2428 Chain = LowerF128_LibCallArg(Chain, Args, Arg: LHS, DL, DAG);
2429 Chain = LowerF128_LibCallArg(Chain, Args, Arg: RHS, DL, DAG);
2430
2431 TargetLowering::CallLoweringInfo CLI(DAG);
2432 CLI.setDebugLoc(DL).setChain(Chain)
2433 .setCallee(CC: CallingConv::C, ResultType: RetTy, Target: Callee, ArgsList: std::move(Args));
2434
2435 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2436
2437 // result is in first, and chain is in second result.
2438 SDValue Result = CallInfo.first;
2439
2440 switch(SPCC) {
2441 default: {
2442 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2443 SPCC = SPCC::ICC_NE;
2444 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2445 }
2446 case SPCC::FCC_UL : {
2447 SDValue Mask = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2448 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2449 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2450 SPCC = SPCC::ICC_NE;
2451 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2452 }
2453 case SPCC::FCC_ULE: {
2454 SDValue RHS = DAG.getConstant(Val: 2, DL, VT: Result.getValueType());
2455 SPCC = SPCC::ICC_NE;
2456 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2457 }
2458 case SPCC::FCC_UG : {
2459 SDValue RHS = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2460 SPCC = SPCC::ICC_G;
2461 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2462 }
2463 case SPCC::FCC_UGE: {
2464 SDValue RHS = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2465 SPCC = SPCC::ICC_NE;
2466 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2467 }
2468
2469 case SPCC::FCC_U : {
2470 SDValue RHS = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2471 SPCC = SPCC::ICC_E;
2472 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2473 }
2474 case SPCC::FCC_O : {
2475 SDValue RHS = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2476 SPCC = SPCC::ICC_NE;
2477 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2478 }
2479 case SPCC::FCC_LG : {
2480 SDValue Mask = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2481 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2482 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2483 SPCC = SPCC::ICC_NE;
2484 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2485 }
2486 case SPCC::FCC_UE : {
2487 SDValue Mask = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2488 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2489 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2490 SPCC = SPCC::ICC_E;
2491 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2492 }
2493 }
2494}
2495
2496static SDValue
2497LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2498 const SparcTargetLowering &TLI) {
2499
2500 if (Op.getOperand(i: 0).getValueType() == MVT::f64)
2501 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPEXT_F64_F128, numArgs: 1);
2502
2503 if (Op.getOperand(i: 0).getValueType() == MVT::f32)
2504 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPEXT_F32_F128, numArgs: 1);
2505
2506 llvm_unreachable("fpextend with non-float operand!");
2507 return SDValue();
2508}
2509
2510static SDValue
2511LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2512 const SparcTargetLowering &TLI) {
2513 // FP_ROUND on f64 and f32 are legal.
2514 if (Op.getOperand(i: 0).getValueType() != MVT::f128)
2515 return Op;
2516
2517 if (Op.getValueType() == MVT::f64)
2518 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPROUND_F128_F64, numArgs: 1);
2519 if (Op.getValueType() == MVT::f32)
2520 return TLI.LowerF128Op(Op, DAG, LibFunc: RTLIB::FPROUND_F128_F32, numArgs: 1);
2521
2522 llvm_unreachable("fpround to non-float!");
2523 return SDValue();
2524}
2525
2526static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2527 const SparcTargetLowering &TLI,
2528 bool hasHardQuad) {
2529 SDLoc dl(Op);
2530 EVT VT = Op.getValueType();
2531 assert(VT == MVT::i32 || VT == MVT::i64);
2532
2533 // Expand f128 operations to fp128 abi calls.
2534 if (Op.getOperand(i: 0).getValueType() == MVT::f128
2535 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2536 RTLIB::Libcall LibFunc =
2537 VT == MVT::i32 ? RTLIB::FPTOSINT_F128_I32 : RTLIB::FPTOSINT_F128_I64;
2538 return TLI.LowerF128Op(Op, DAG, LibFunc, numArgs: 1);
2539 }
2540
2541 // Expand if the resulting type is illegal.
2542 if (!TLI.isTypeLegal(VT))
2543 return SDValue();
2544
2545 // Otherwise, Convert the fp value to integer in an FP register.
2546 if (VT == MVT::i32)
2547 Op = DAG.getNode(Opcode: SPISD::FTOI, DL: dl, VT: MVT::f32, Operand: Op.getOperand(i: 0));
2548 else
2549 Op = DAG.getNode(Opcode: SPISD::FTOX, DL: dl, VT: MVT::f64, Operand: Op.getOperand(i: 0));
2550
2551 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT, Operand: Op);
2552}
2553
2554static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2555 const SparcTargetLowering &TLI,
2556 bool hasHardQuad) {
2557 SDLoc dl(Op);
2558 EVT OpVT = Op.getOperand(i: 0).getValueType();
2559 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2560
2561 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2562
2563 // Expand f128 operations to fp128 ABI calls.
2564 if (Op.getValueType() == MVT::f128
2565 && (!hasHardQuad || !TLI.isTypeLegal(VT: OpVT))) {
2566 RTLIB::Libcall LibFunc =
2567 OpVT == MVT::i32 ? RTLIB::SINTTOFP_I32_F128 : RTLIB::SINTTOFP_I64_F128;
2568 return TLI.LowerF128Op(Op, DAG, LibFunc, numArgs: 1);
2569 }
2570
2571 // Expand if the operand type is illegal.
2572 if (!TLI.isTypeLegal(VT: OpVT))
2573 return SDValue();
2574
2575 // Otherwise, Convert the int value to FP in an FP register.
2576 SDValue Tmp = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: floatVT, Operand: Op.getOperand(i: 0));
2577 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2578 return DAG.getNode(Opcode: opcode, DL: dl, VT: Op.getValueType(), Operand: Tmp);
2579}
2580
2581static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2582 const SparcTargetLowering &TLI,
2583 bool hasHardQuad) {
2584 EVT VT = Op.getValueType();
2585
2586 // Expand if it does not involve f128 or the target has support for
2587 // quad floating point instructions and the resulting type is legal.
2588 if (Op.getOperand(i: 0).getValueType() != MVT::f128 ||
2589 (hasHardQuad && TLI.isTypeLegal(VT)))
2590 return SDValue();
2591
2592 assert(VT == MVT::i32 || VT == MVT::i64);
2593
2594 return TLI.LowerF128Op(
2595 Op, DAG,
2596 LibFunc: VT == MVT::i32 ? RTLIB::FPTOUINT_F128_I32 : RTLIB::FPTOUINT_F128_I64, numArgs: 1);
2597}
2598
2599static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2600 const SparcTargetLowering &TLI,
2601 bool hasHardQuad) {
2602 EVT OpVT = Op.getOperand(i: 0).getValueType();
2603 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2604
2605 // Expand if it does not involve f128 or the target has support for
2606 // quad floating point instructions and the operand type is legal.
2607 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(VT: OpVT)))
2608 return SDValue();
2609
2610 return TLI.LowerF128Op(Op, DAG,
2611 LibFunc: OpVT == MVT::i32 ? RTLIB::UINTTOFP_I32_F128
2612 : RTLIB::UINTTOFP_I64_F128,
2613 numArgs: 1);
2614}
2615
2616static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2617 const SparcTargetLowering &TLI, bool hasHardQuad,
2618 bool isV9, bool is64Bit) {
2619 SDValue Chain = Op.getOperand(i: 0);
2620 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 1))->get();
2621 SDValue LHS = Op.getOperand(i: 2);
2622 SDValue RHS = Op.getOperand(i: 3);
2623 SDValue Dest = Op.getOperand(i: 4);
2624 SDLoc dl(Op);
2625 unsigned Opc, SPCC = ~0U;
2626
2627 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2628 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2629 LookThroughSetCC(LHS, RHS, CC, SPCC);
2630 assert(LHS.getValueType() == RHS.getValueType());
2631
2632 // Get the condition flag.
2633 SDValue CompareFlag;
2634 if (LHS.getValueType().isInteger()) {
2635 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2636 // and the RHS is zero we might be able to use a specialized branch.
2637 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2638 isNullConstant(V: RHS) && !ISD::isUnsignedIntSetCC(Code: CC))
2639 return DAG.getNode(Opcode: SPISD::BR_REG, DL: dl, VT: MVT::Other, N1: Chain, N2: Dest,
2640 N3: DAG.getConstant(Val: intCondCCodeToRcond(CC), DL: dl, VT: MVT::i32),
2641 N4: LHS);
2642
2643 CompareFlag = DAG.getNode(Opcode: SPISD::CMPICC, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2644 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2645 if (isV9)
2646 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2647 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BPICC : SPISD::BPXCC;
2648 else
2649 // Non-v9 targets don't have xcc.
2650 Opc = SPISD::BRICC;
2651 } else {
2652 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2653 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2654 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, DL: dl, DAG);
2655 Opc = isV9 ? SPISD::BPICC : SPISD::BRICC;
2656 } else {
2657 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2658 CompareFlag = DAG.getNode(Opcode: CmpOpc, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2659 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2660 Opc = isV9 ? SPISD::BRFCC_V9 : SPISD::BRFCC;
2661 }
2662 }
2663 return DAG.getNode(Opcode: Opc, DL: dl, VT: MVT::Other, N1: Chain, N2: Dest,
2664 N3: DAG.getConstant(Val: SPCC, DL: dl, VT: MVT::i32), N4: CompareFlag);
2665}
2666
2667static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2668 const SparcTargetLowering &TLI, bool hasHardQuad,
2669 bool isV9, bool is64Bit) {
2670 SDValue LHS = Op.getOperand(i: 0);
2671 SDValue RHS = Op.getOperand(i: 1);
2672 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 4))->get();
2673 SDValue TrueVal = Op.getOperand(i: 2);
2674 SDValue FalseVal = Op.getOperand(i: 3);
2675 SDLoc dl(Op);
2676 unsigned Opc, SPCC = ~0U;
2677
2678 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2679 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2680 LookThroughSetCC(LHS, RHS, CC, SPCC);
2681 assert(LHS.getValueType() == RHS.getValueType());
2682
2683 SDValue CompareFlag;
2684 if (LHS.getValueType().isInteger()) {
2685 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2686 // and the RHS is zero we might be able to use a specialized select.
2687 // All SELECT_CC between any two scalar integer types are eligible for
2688 // lowering to specialized instructions. Additionally, f32 and f64 types
2689 // are also eligible, but for f128 we can only use the specialized
2690 // instruction when we have hardquad.
2691 EVT ValType = TrueVal.getValueType();
2692 bool IsEligibleType = ValType.isScalarInteger() || ValType == MVT::f32 ||
2693 ValType == MVT::f64 ||
2694 (ValType == MVT::f128 && hasHardQuad);
2695 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2696 isNullConstant(V: RHS) && !ISD::isUnsignedIntSetCC(Code: CC) && IsEligibleType)
2697 return DAG.getNode(
2698 Opcode: SPISD::SELECT_REG, DL: dl, VT: TrueVal.getValueType(), N1: TrueVal, N2: FalseVal,
2699 N3: DAG.getConstant(Val: intCondCCodeToRcond(CC), DL: dl, VT: MVT::i32), N4: LHS);
2700
2701 CompareFlag = DAG.getNode(Opcode: SPISD::CMPICC, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2702 Opc = LHS.getValueType() == MVT::i32 ?
2703 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2704 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2705 } else {
2706 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2707 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2708 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, DL: dl, DAG);
2709 Opc = SPISD::SELECT_ICC;
2710 } else {
2711 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2712 CompareFlag = DAG.getNode(Opcode: CmpOpc, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2713 Opc = SPISD::SELECT_FCC;
2714 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2715 }
2716 }
2717 return DAG.getNode(Opcode: Opc, DL: dl, VT: TrueVal.getValueType(), N1: TrueVal, N2: FalseVal,
2718 N3: DAG.getConstant(Val: SPCC, DL: dl, VT: MVT::i32), N4: CompareFlag);
2719}
2720
2721static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2722 const SparcTargetLowering &TLI) {
2723 MachineFunction &MF = DAG.getMachineFunction();
2724 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2725 auto PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
2726
2727 // Need frame address to find the address of VarArgsFrameIndex.
2728 MF.getFrameInfo().setFrameAddressIsTaken(true);
2729
2730 // vastart just stores the address of the VarArgsFrameIndex slot into the
2731 // memory location argument.
2732 SDLoc DL(Op);
2733 SDValue Offset =
2734 DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: DAG.getRegister(Reg: SP::I6, VT: PtrVT),
2735 N2: DAG.getIntPtrConstant(Val: FuncInfo->getVarArgsFrameOffset(), DL));
2736 const Value *SV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 2))->getValue();
2737 return DAG.getStore(Chain: Op.getOperand(i: 0), dl: DL, Val: Offset, Ptr: Op.getOperand(i: 1),
2738 PtrInfo: MachinePointerInfo(SV));
2739}
2740
2741static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2742 SDNode *Node = Op.getNode();
2743 EVT VT = Node->getValueType(ResNo: 0);
2744 SDValue InChain = Node->getOperand(Num: 0);
2745 SDValue VAListPtr = Node->getOperand(Num: 1);
2746 EVT PtrVT = VAListPtr.getValueType();
2747 const Value *SV = cast<SrcValueSDNode>(Val: Node->getOperand(Num: 2))->getValue();
2748 SDLoc DL(Node);
2749 SDValue VAList =
2750 DAG.getLoad(VT: PtrVT, dl: DL, Chain: InChain, Ptr: VAListPtr, PtrInfo: MachinePointerInfo(SV));
2751 // Increment the pointer, VAList, to the next vaarg.
2752 SDValue NextPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: VAList,
2753 N2: DAG.getIntPtrConstant(Val: VT.getSizeInBits()/8,
2754 DL));
2755 // Store the incremented VAList to the legalized pointer.
2756 InChain = DAG.getStore(Chain: VAList.getValue(R: 1), dl: DL, Val: NextPtr, Ptr: VAListPtr,
2757 PtrInfo: MachinePointerInfo(SV));
2758 // Load the actual argument out of the pointer VAList.
2759 // We can't count on greater alignment than the word size.
2760 return DAG.getLoad(
2761 VT, dl: DL, Chain: InChain, Ptr: VAList, PtrInfo: MachinePointerInfo(),
2762 Alignment: Align(std::min(a: PtrVT.getFixedSizeInBits(), b: VT.getFixedSizeInBits()) / 8));
2763}
2764
2765static SDValue LowerSTACKADDRESS(SDValue Op, SelectionDAG &DAG,
2766 const SparcSubtarget &Subtarget) {
2767 SDValue Chain = Op.getOperand(i: 0);
2768 EVT VT = Op->getValueType(ResNo: 0);
2769 SDLoc DL(Op);
2770
2771 MCRegister SPReg = SP::O6;
2772 SDValue SP = DAG.getCopyFromReg(Chain, dl: DL, Reg: SPReg, VT);
2773
2774 // Unbias the stack pointer register.
2775 unsigned OffsetToStackStart = Subtarget.getStackPointerBias();
2776 // Move past the register save area: 8 in registers + 8 local registers.
2777 OffsetToStackStart += 16 * (Subtarget.is64Bit() ? 8 : 4);
2778 // Move past the struct return address slot (4 bytes) on SPARC 32-bit.
2779 if (!Subtarget.is64Bit())
2780 OffsetToStackStart += 4;
2781
2782 SDValue StackAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: SP,
2783 N2: DAG.getConstant(Val: OffsetToStackStart, DL, VT));
2784 return DAG.getMergeValues(Ops: {StackAddr, Chain}, dl: DL);
2785}
2786
2787static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2788 const SparcSubtarget *Subtarget) {
2789 SDValue Chain = Op.getOperand(i: 0);
2790 SDValue Size = Op.getOperand(i: 1);
2791 SDValue Alignment = Op.getOperand(i: 2);
2792 MaybeAlign MaybeAlignment =
2793 cast<ConstantSDNode>(Val&: Alignment)->getMaybeAlignValue();
2794 EVT VT = Size->getValueType(ResNo: 0);
2795 SDLoc dl(Op);
2796
2797 unsigned SPReg = SP::O6;
2798 SDValue SP = DAG.getCopyFromReg(Chain, dl, Reg: SPReg, VT);
2799
2800 // The resultant pointer needs to be above the register spill area
2801 // at the bottom of the stack.
2802 unsigned regSpillArea;
2803 if (Subtarget->is64Bit()) {
2804 regSpillArea = 128;
2805 } else {
2806 // On Sparc32, the size of the spill area is 92. Unfortunately,
2807 // that's only 4-byte aligned, not 8-byte aligned (the stack
2808 // pointer is 8-byte aligned). So, if the user asked for an 8-byte
2809 // aligned dynamic allocation, we actually need to add 96 to the
2810 // bottom of the stack, instead of 92, to ensure 8-byte alignment.
2811
2812 // That also means adding 4 to the size of the allocation --
2813 // before applying the 8-byte rounding. Unfortunately, we the
2814 // value we get here has already had rounding applied. So, we need
2815 // to add 8, instead, wasting a bit more memory.
2816
2817 // Further, this only actually needs to be done if the required
2818 // alignment is > 4, but, we've lost that info by this point, too,
2819 // so we always apply it.
2820
2821 // (An alternative approach would be to always reserve 96 bytes
2822 // instead of the required 92, but then we'd waste 4 extra bytes
2823 // in every frame, not just those with dynamic stack allocations)
2824
2825 // TODO: modify code in SelectionDAGBuilder to make this less sad.
2826
2827 Size = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: Size,
2828 N2: DAG.getConstant(Val: 8, DL: dl, VT));
2829 regSpillArea = 96;
2830 }
2831
2832 int64_t Bias = Subtarget->getStackPointerBias();
2833
2834 // Debias and increment SP past the reserved spill area.
2835 // We need the SP to point to the first usable region before calculating
2836 // anything to prevent any of the pointers from becoming out of alignment when
2837 // we rebias the SP later on.
2838 SDValue StartOfUsableStack = DAG.getNode(
2839 Opcode: ISD::ADD, DL: dl, VT, N1: SP, N2: DAG.getConstant(Val: regSpillArea + Bias, DL: dl, VT));
2840 SDValue AllocatedPtr =
2841 DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: StartOfUsableStack, N2: Size);
2842
2843 bool IsOveraligned = MaybeAlignment.has_value();
2844 SDValue AlignedPtr =
2845 IsOveraligned
2846 ? DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: AllocatedPtr,
2847 N2: DAG.getSignedConstant(Val: -MaybeAlignment->value(), DL: dl, VT))
2848 : AllocatedPtr;
2849
2850 // Now that we are done, restore the bias and reserved spill area.
2851 SDValue NewSP = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: AlignedPtr,
2852 N2: DAG.getConstant(Val: regSpillArea + Bias, DL: dl, VT));
2853 Chain = DAG.getCopyToReg(Chain: SP.getValue(R: 1), dl, Reg: SPReg, N: NewSP);
2854 SDValue Ops[2] = {AlignedPtr, Chain};
2855 return DAG.getMergeValues(Ops, dl);
2856}
2857
2858
2859static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2860 SDLoc dl(Op);
2861 SDValue Chain = DAG.getNode(Opcode: SPISD::FLUSHW,
2862 DL: dl, VT: MVT::Other, Operand: DAG.getEntryNode());
2863 return Chain;
2864}
2865
2866static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2867 const SparcSubtarget *Subtarget,
2868 bool AlwaysFlush = false) {
2869 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2870 MFI.setFrameAddressIsTaken(true);
2871
2872 EVT VT = Op.getValueType();
2873 SDLoc dl(Op);
2874 unsigned FrameReg = SP::I6;
2875 unsigned stackBias = Subtarget->getStackPointerBias();
2876
2877 SDValue FrameAddr;
2878 SDValue Chain;
2879
2880 // flush first to make sure the windowed registers' values are in stack
2881 Chain = (depth || AlwaysFlush) ? getFLUSHW(Op, DAG) : DAG.getEntryNode();
2882
2883 FrameAddr = DAG.getCopyFromReg(Chain, dl, Reg: FrameReg, VT);
2884
2885 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2886
2887 while (depth--) {
2888 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: FrameAddr,
2889 N2: DAG.getIntPtrConstant(Val: Offset, DL: dl));
2890 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, PtrInfo: MachinePointerInfo());
2891 }
2892 if (Subtarget->is64Bit())
2893 FrameAddr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: FrameAddr,
2894 N2: DAG.getIntPtrConstant(Val: stackBias, DL: dl));
2895 return FrameAddr;
2896}
2897
2898
2899static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2900 const SparcSubtarget *Subtarget) {
2901
2902 uint64_t depth = Op.getConstantOperandVal(i: 0);
2903
2904 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2905
2906}
2907
2908static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2909 const SparcTargetLowering &TLI,
2910 const SparcSubtarget *Subtarget) {
2911 MachineFunction &MF = DAG.getMachineFunction();
2912 MachineFrameInfo &MFI = MF.getFrameInfo();
2913 MFI.setReturnAddressIsTaken(true);
2914
2915 EVT VT = Op.getValueType();
2916 SDLoc dl(Op);
2917 uint64_t depth = Op.getConstantOperandVal(i: 0);
2918
2919 SDValue RetAddr;
2920 if (depth == 0) {
2921 auto PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
2922 Register RetReg = MF.addLiveIn(PReg: SP::I7, RC: TLI.getRegClassFor(VT: PtrVT));
2923 RetAddr = DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl, Reg: RetReg, VT);
2924 return RetAddr;
2925 }
2926
2927 // Need frame address to find return address of the caller.
2928 SDValue FrameAddr = getFRAMEADDR(depth: depth - 1, Op, DAG, Subtarget, AlwaysFlush: true);
2929
2930 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2931 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD,
2932 DL: dl, VT,
2933 N1: FrameAddr,
2934 N2: DAG.getIntPtrConstant(Val: Offset, DL: dl));
2935 RetAddr = DAG.getLoad(VT, dl, Chain: DAG.getEntryNode(), Ptr, PtrInfo: MachinePointerInfo());
2936
2937 return RetAddr;
2938}
2939
2940static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG,
2941 unsigned opcode) {
2942 assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2943 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2944
2945 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2946 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2947 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2948
2949 // Note: in little-endian, the floating-point value is stored in the
2950 // registers are in the opposite order, so the subreg with the sign
2951 // bit is the highest-numbered (odd), rather than the
2952 // lowest-numbered (even).
2953
2954 SDValue Hi32 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_even, DL: dl, VT: MVT::f32,
2955 Operand: SrcReg64);
2956 SDValue Lo32 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_odd, DL: dl, VT: MVT::f32,
2957 Operand: SrcReg64);
2958
2959 if (DAG.getDataLayout().isLittleEndian())
2960 Lo32 = DAG.getNode(Opcode: opcode, DL: dl, VT: MVT::f32, Operand: Lo32);
2961 else
2962 Hi32 = DAG.getNode(Opcode: opcode, DL: dl, VT: MVT::f32, Operand: Hi32);
2963
2964 SDValue DstReg64 = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
2965 dl, VT: MVT::f64), 0);
2966 DstReg64 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_even, DL: dl, VT: MVT::f64,
2967 Operand: DstReg64, Subreg: Hi32);
2968 DstReg64 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_odd, DL: dl, VT: MVT::f64,
2969 Operand: DstReg64, Subreg: Lo32);
2970 return DstReg64;
2971}
2972
2973// Lower a f128 load into two f64 loads.
2974static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2975{
2976 SDLoc dl(Op);
2977 LoadSDNode *LdNode = cast<LoadSDNode>(Val: Op.getNode());
2978 assert(LdNode->getOffset().isUndef() && "Unexpected node type");
2979
2980 Align Alignment = commonAlignment(A: LdNode->getBaseAlign(), Offset: 8);
2981
2982 SDValue Hi64 =
2983 DAG.getLoad(VT: MVT::f64, dl, Chain: LdNode->getChain(), Ptr: LdNode->getBasePtr(),
2984 PtrInfo: LdNode->getPointerInfo(), Alignment);
2985 EVT addrVT = LdNode->getBasePtr().getValueType();
2986 SDValue LoPtr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: addrVT,
2987 N1: LdNode->getBasePtr(),
2988 N2: DAG.getConstant(Val: 8, DL: dl, VT: addrVT));
2989 SDValue Lo64 = DAG.getLoad(VT: MVT::f64, dl, Chain: LdNode->getChain(), Ptr: LoPtr,
2990 PtrInfo: LdNode->getPointerInfo().getWithOffset(O: 8),
2991 Alignment);
2992
2993 SDValue SubRegEven = DAG.getTargetConstant(Val: SP::sub_even64, DL: dl, VT: MVT::i32);
2994 SDValue SubRegOdd = DAG.getTargetConstant(Val: SP::sub_odd64, DL: dl, VT: MVT::i32);
2995
2996 SDNode *InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
2997 dl, VT: MVT::f128);
2998 InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl,
2999 VT: MVT::f128,
3000 Op1: SDValue(InFP128, 0),
3001 Op2: Hi64,
3002 Op3: SubRegEven);
3003 InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl,
3004 VT: MVT::f128,
3005 Op1: SDValue(InFP128, 0),
3006 Op2: Lo64,
3007 Op3: SubRegOdd);
3008 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
3009 SDValue(Lo64.getNode(), 1) };
3010 SDValue OutChain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
3011 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
3012 return DAG.getMergeValues(Ops, dl);
3013}
3014
3015SDValue SparcTargetLowering::LowerBSWAP(SDValue Op, SelectionDAG &DAG) const {
3016 // We don't have an in-register bswap, so expand bswap(x) into
3017 // load(store-swapped(x)). The reason the swap is done during the store is
3018 // that on some implementations (mainly older ones) ASI-tagged memory
3019 // operations are not pipelined, and generally stores finish faster than
3020 // loads.
3021
3022 MachineFunction &MF = DAG.getMachineFunction();
3023 MachineFrameInfo &MFI = MF.getFrameInfo();
3024 MVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
3025 SDValue Chain = DAG.getEntryNode();
3026 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
3027 SDLoc DL(Op);
3028
3029 SDValue BSwapOp = Op.getOperand(i: 0);
3030 EVT VT = BSwapOp.getValueType();
3031 Type *Ty = VT.getTypeForEVT(Context&: *DAG.getContext());
3032 Align Al = DAG.getDataLayout().getPrefTypeAlign(Ty);
3033
3034 // Create a stack object to serve as temporary storage.
3035 int TmpFI = MFI.CreateStackObject(Size: VT.getStoreSize(), Alignment: Al, isSpillSlot: false);
3036 SDValue TmpPtr = DAG.getFrameIndex(FI: TmpFI, VT: PtrVT);
3037
3038 // Store-swap the value, then load it back.
3039 SDValue Ops[] = {Chain, BSwapOp, TmpPtr, DAG.getValueType(VT)};
3040 SDValue ST = DAG.getMemIntrinsicNode(
3041 Opcode: IsLittleEndian ? SPISD::STORE_BIG : SPISD::STORE_LITTLE, dl: DL,
3042 VTList: DAG.getVTList(VT: MVT::Other), Ops, MemVT: VT,
3043 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI: TmpFI), Alignment: std::nullopt,
3044 Flags: MachineMemOperand::MOStore);
3045 return DAG.getLoad(VT, dl: DL, Chain: ST, Ptr: TmpPtr,
3046 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI: TmpFI));
3047}
3048
3049static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
3050{
3051 LoadSDNode *LdNode = cast<LoadSDNode>(Val: Op.getNode());
3052
3053 EVT MemVT = LdNode->getMemoryVT();
3054 if (MemVT == MVT::f128)
3055 return LowerF128Load(Op, DAG);
3056
3057 return Op;
3058}
3059
3060// Lower a f128 store into two f64 stores.
3061static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
3062 SDLoc dl(Op);
3063 StoreSDNode *StNode = cast<StoreSDNode>(Val: Op.getNode());
3064 assert(StNode->getOffset().isUndef() && "Unexpected node type");
3065
3066 SDValue SubRegEven = DAG.getTargetConstant(Val: SP::sub_even64, DL: dl, VT: MVT::i32);
3067 SDValue SubRegOdd = DAG.getTargetConstant(Val: SP::sub_odd64, DL: dl, VT: MVT::i32);
3068
3069 SDNode *Hi64 = DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG,
3070 dl,
3071 VT: MVT::f64,
3072 Op1: StNode->getValue(),
3073 Op2: SubRegEven);
3074 SDNode *Lo64 = DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG,
3075 dl,
3076 VT: MVT::f64,
3077 Op1: StNode->getValue(),
3078 Op2: SubRegOdd);
3079
3080 Align Alignment = commonAlignment(A: StNode->getBaseAlign(), Offset: 8);
3081
3082 SDValue OutChains[2];
3083 OutChains[0] =
3084 DAG.getStore(Chain: StNode->getChain(), dl, Val: SDValue(Hi64, 0),
3085 Ptr: StNode->getBasePtr(), PtrInfo: StNode->getPointerInfo(),
3086 Alignment);
3087 EVT addrVT = StNode->getBasePtr().getValueType();
3088 SDValue LoPtr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: addrVT,
3089 N1: StNode->getBasePtr(),
3090 N2: DAG.getConstant(Val: 8, DL: dl, VT: addrVT));
3091 OutChains[1] = DAG.getStore(Chain: StNode->getChain(), dl, Val: SDValue(Lo64, 0), Ptr: LoPtr,
3092 PtrInfo: StNode->getPointerInfo().getWithOffset(O: 8),
3093 Alignment);
3094 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
3095}
3096
3097static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
3098{
3099 SDLoc dl(Op);
3100 StoreSDNode *St = cast<StoreSDNode>(Val: Op.getNode());
3101
3102 EVT MemVT = St->getMemoryVT();
3103 if (MemVT == MVT::f128)
3104 return LowerF128Store(Op, DAG);
3105
3106 if (MemVT == MVT::i64) {
3107 // Custom handling for i64 stores: turn it into a bitcast and a
3108 // v2i32 store.
3109 SDValue Val = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::v2i32, Operand: St->getValue());
3110 SDValue Chain = DAG.getStore(
3111 Chain: St->getChain(), dl, Val, Ptr: St->getBasePtr(), PtrInfo: St->getPointerInfo(),
3112 Alignment: St->getBaseAlign(), MMOFlags: St->getMemOperand()->getFlags(), Metadata: St->getAAInfo());
3113 return Chain;
3114 }
3115
3116 return SDValue();
3117}
3118
3119static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
3120 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
3121 && "invalid opcode");
3122
3123 SDLoc dl(Op);
3124
3125 if (Op.getValueType() == MVT::f64)
3126 return LowerF64Op(SrcReg64: Op.getOperand(i: 0), dl, DAG, opcode: Op.getOpcode());
3127 if (Op.getValueType() != MVT::f128)
3128 return Op;
3129
3130 // Lower fabs/fneg on f128 to fabs/fneg on f64
3131 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
3132 // (As with LowerF64Op, on little-endian, we need to negate the odd
3133 // subreg)
3134
3135 SDValue SrcReg128 = Op.getOperand(i: 0);
3136 SDValue Hi64 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_even64, DL: dl, VT: MVT::f64,
3137 Operand: SrcReg128);
3138 SDValue Lo64 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_odd64, DL: dl, VT: MVT::f64,
3139 Operand: SrcReg128);
3140
3141 if (DAG.getDataLayout().isLittleEndian()) {
3142 if (isV9)
3143 Lo64 = DAG.getNode(Opcode: Op.getOpcode(), DL: dl, VT: MVT::f64, Operand: Lo64);
3144 else
3145 Lo64 = LowerF64Op(SrcReg64: Lo64, dl, DAG, opcode: Op.getOpcode());
3146 } else {
3147 if (isV9)
3148 Hi64 = DAG.getNode(Opcode: Op.getOpcode(), DL: dl, VT: MVT::f64, Operand: Hi64);
3149 else
3150 Hi64 = LowerF64Op(SrcReg64: Hi64, dl, DAG, opcode: Op.getOpcode());
3151 }
3152
3153 SDValue DstReg128 = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
3154 dl, VT: MVT::f128), 0);
3155 DstReg128 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_even64, DL: dl, VT: MVT::f128,
3156 Operand: DstReg128, Subreg: Hi64);
3157 DstReg128 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_odd64, DL: dl, VT: MVT::f128,
3158 Operand: DstReg128, Subreg: Lo64);
3159 return DstReg128;
3160}
3161
3162static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
3163 if (isStrongerThanMonotonic(AO: cast<AtomicSDNode>(Val&: Op)->getSuccessOrdering())) {
3164 // Expand with a fence.
3165 return SDValue();
3166 }
3167
3168 // Monotonic load/stores are legal.
3169 return Op;
3170}
3171
3172SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
3173 SelectionDAG &DAG) const {
3174 unsigned IntNo = Op.getConstantOperandVal(i: 0);
3175 switch (IntNo) {
3176 default: return SDValue(); // Don't custom lower most intrinsics.
3177 case Intrinsic::thread_pointer: {
3178 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
3179 return DAG.getRegister(Reg: SP::G7, VT: PtrVT);
3180 }
3181 }
3182}
3183
3184SDValue SparcTargetLowering::
3185LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3186
3187 bool hasHardQuad = Subtarget->hasHardQuad();
3188 bool isV9 = Subtarget->isV9();
3189 bool is64Bit = Subtarget->is64Bit();
3190
3191 switch (Op.getOpcode()) {
3192 default: llvm_unreachable("Should not custom lower this!");
3193
3194 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, TLI: *this,
3195 Subtarget);
3196 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
3197 Subtarget);
3198 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3199 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3200 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3201 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3202 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, TLI: *this,
3203 hasHardQuad);
3204 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, TLI: *this,
3205 hasHardQuad);
3206 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, TLI: *this,
3207 hasHardQuad);
3208 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, TLI: *this,
3209 hasHardQuad);
3210 case ISD::BR_CC:
3211 return LowerBR_CC(Op, DAG, TLI: *this, hasHardQuad, isV9, is64Bit);
3212 case ISD::SELECT_CC:
3213 return LowerSELECT_CC(Op, DAG, TLI: *this, hasHardQuad, isV9, is64Bit);
3214 case ISD::VASTART: return LowerVASTART(Op, DAG, TLI: *this);
3215 case ISD::VAARG: return LowerVAARG(Op, DAG);
3216 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
3217 Subtarget);
3218 case ISD::STACKADDRESS:
3219 return LowerSTACKADDRESS(Op, DAG, Subtarget: *Subtarget);
3220
3221 case ISD::BSWAP:
3222 return LowerBSWAP(Op, DAG);
3223
3224 case ISD::LOAD: return LowerLOAD(Op, DAG);
3225 case ISD::STORE: return LowerSTORE(Op, DAG);
3226 case ISD::FADD:
3227 return LowerF128Op(Op, DAG, LibFunc: RTLIB::ADD_F128, numArgs: 2);
3228 case ISD::FSUB:
3229 return LowerF128Op(Op, DAG, LibFunc: RTLIB::SUB_F128, numArgs: 2);
3230 case ISD::FMUL:
3231 return LowerF128Op(Op, DAG, LibFunc: RTLIB::MUL_F128, numArgs: 2);
3232 case ISD::FDIV:
3233 return LowerF128Op(Op, DAG, LibFunc: RTLIB::DIV_F128, numArgs: 2);
3234 case ISD::FSQRT:
3235 return LowerF128Op(Op, DAG, LibFunc: RTLIB::SQRT_F128, numArgs: 1);
3236 case ISD::FABS:
3237 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
3238 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, TLI: *this);
3239 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, TLI: *this);
3240 case ISD::ATOMIC_LOAD:
3241 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
3242 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3243 }
3244}
3245
3246SDValue SparcTargetLowering::bitcastConstantFPToInt(ConstantFPSDNode *C,
3247 const SDLoc &DL,
3248 SelectionDAG &DAG) const {
3249 APInt V = C->getValueAPF().bitcastToAPInt();
3250 SDValue Lo = DAG.getConstant(Val: V.zextOrTrunc(width: 32), DL, VT: MVT::i32);
3251 SDValue Hi = DAG.getConstant(Val: V.lshr(shiftAmt: 32).zextOrTrunc(width: 32), DL, VT: MVT::i32);
3252 if (DAG.getDataLayout().isLittleEndian())
3253 std::swap(a&: Lo, b&: Hi);
3254 return DAG.getBuildVector(VT: MVT::v2i32, DL, Ops: {Hi, Lo});
3255}
3256
3257SDValue SparcTargetLowering::PerformBITCASTCombine(SDNode *N,
3258 DAGCombinerInfo &DCI) const {
3259 SDLoc dl(N);
3260 SDValue Src = N->getOperand(Num: 0);
3261
3262 if (isa<ConstantFPSDNode>(Val: Src) && N->getSimpleValueType(ResNo: 0) == MVT::v2i32 &&
3263 Src.getSimpleValueType() == MVT::f64)
3264 return bitcastConstantFPToInt(C: cast<ConstantFPSDNode>(Val&: Src), DL: dl, DAG&: DCI.DAG);
3265
3266 return SDValue();
3267}
3268
3269SDValue SparcTargetLowering::PerformBSWAPCombine(SDNode *N,
3270 DAGCombinerInfo &DCI) const {
3271 SDLoc DL(N);
3272 SelectionDAG &DAG = DCI.DAG;
3273 SDValue Op = N->getOperand(Num: 0);
3274 EVT VT = N->getValueType(ResNo: 0);
3275 auto *LN = dyn_cast<LoadSDNode>(Val: Op.getNode());
3276
3277 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
3278 bool IsAlignedLoad = LN && ISD::isNormalLoad(N: Op.getNode()) &&
3279 LN->getAlign() >= VT.getScalarStoreSize();
3280
3281 // Turn BSWAP (aligned-LOAD) -> ld*a #ASI_P(_L) on V9.
3282 if (Subtarget->isV9() && IsAlignedLoad && Op.getNode()->hasOneUse() &&
3283 (VT == MVT::i16 || VT == MVT::i32 ||
3284 (Subtarget->is64Bit() && VT == MVT::i64))) {
3285 SDValue Load = Op;
3286 auto *LD = cast<LoadSDNode>(Val&: Load);
3287
3288 // Create the byte-swapping load.
3289 SDValue Ops[] = {LD->getChain(), LD->getBasePtr(), DAG.getValueType(VT)};
3290
3291 SDValue BSLoad = DAG.getMemIntrinsicNode(
3292 Opcode: IsLittleEndian ? SPISD::LOAD_BIG : SPISD::LOAD_LITTLE, dl: DL,
3293 VTList: DAG.getVTList(VT1: VT == MVT::i64 ? MVT::i64 : MVT::i32, VT2: MVT::Other), Ops,
3294 MemVT: LD->getMemoryVT(), MMO: LD->getMemOperand());
3295
3296 // If this is an i16 load, insert the truncate.
3297 SDValue ResVal = BSLoad;
3298 if (VT == MVT::i16)
3299 ResVal = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i16, Operand: BSLoad);
3300
3301 return DCI.CombineTo(N, Res: ResVal);
3302 }
3303
3304 return SDValue();
3305}
3306
3307SDValue SparcTargetLowering::PerformSTORECombine(SDNode *N,
3308 DAGCombinerInfo &DCI) const {
3309 SDLoc DL(N);
3310 SelectionDAG &DAG = DCI.DAG;
3311 SDValue Op = N->getOperand(Num: 1);
3312 EVT VT = Op.getValueType();
3313 EVT MemVT = cast<StoreSDNode>(Val: N)->getMemoryVT();
3314 unsigned Opcode = Op.getOpcode();
3315 auto *SN = dyn_cast<StoreSDNode>(Val: N);
3316
3317 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
3318 bool IsAlignedStore = SN && SN->getAlign() >= MemVT.getScalarStoreSize();
3319
3320 // Turn aligned-STORE (BSWAP) -> st*a #ASI_P(_L) on V9.
3321 if (Subtarget->isV9() && Opcode == ISD::BSWAP && Op.getNode()->hasOneUse() &&
3322 IsAlignedStore &&
3323 (VT == MVT::i16 || VT == MVT::i32 ||
3324 (Subtarget->is64Bit() && VT == MVT::i64))) {
3325
3326 // st*a can only handle simple types and it makes no sense to store less
3327 // than two bytes in byte-reversed order.
3328 if (MemVT.getSizeInBits() < 16)
3329 return SDValue();
3330
3331 SDValue BSwapOp = Op.getOperand(i: 0);
3332 // Do an any-extend to 32-bits if this is a half-word input.
3333 if (BSwapOp.getValueType() == MVT::i16)
3334 BSwapOp = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i32, Operand: BSwapOp);
3335
3336 // If the type of BSWAP operand is wider than stored memory width
3337 // it needs to be shifted to the right side before st*a.
3338 if (VT.bitsGT(VT: MemVT)) {
3339 unsigned Shift = VT.getSizeInBits() - MemVT.getSizeInBits();
3340 BSwapOp = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: BSwapOp,
3341 N2: DAG.getShiftAmountConstant(Val: Shift, VT, DL));
3342 }
3343
3344 SDValue Ops[] = {N->getOperand(Num: 0), BSwapOp, N->getOperand(Num: 2),
3345 DAG.getValueType(MemVT)};
3346 return DAG.getMemIntrinsicNode(
3347 Opcode: IsLittleEndian ? SPISD::STORE_BIG : SPISD::STORE_LITTLE, dl: DL,
3348 VTList: DAG.getVTList(VT: MVT::Other), Ops, MemVT: cast<StoreSDNode>(Val: N)->getMemoryVT(),
3349 MMO: cast<StoreSDNode>(Val: N)->getMemOperand());
3350 }
3351
3352 return SDValue();
3353}
3354
3355SDValue SparcTargetLowering::PerformDAGCombine(SDNode *N,
3356 DAGCombinerInfo &DCI) const {
3357 switch (N->getOpcode()) {
3358 default:
3359 break;
3360 case ISD::BITCAST:
3361 return PerformBITCASTCombine(N, DCI);
3362 case ISD::BSWAP:
3363 return PerformBSWAPCombine(N, DCI);
3364 case ISD::STORE:
3365 return PerformSTORECombine(N, DCI);
3366 }
3367 return SDValue();
3368}
3369
3370MachineBasicBlock *
3371SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3372 MachineBasicBlock *BB) const {
3373 switch (MI.getOpcode()) {
3374 default: llvm_unreachable("Unknown SELECT_CC!");
3375 case SP::SELECT_CC_Int_ICC:
3376 case SP::SELECT_CC_FP_ICC:
3377 case SP::SELECT_CC_DFP_ICC:
3378 case SP::SELECT_CC_QFP_ICC:
3379 if (Subtarget->isV9())
3380 return expandSelectCC(MI, BB, BROpcode: SP::BPICC);
3381 return expandSelectCC(MI, BB, BROpcode: SP::BCOND);
3382 case SP::SELECT_CC_Int_XCC:
3383 case SP::SELECT_CC_FP_XCC:
3384 case SP::SELECT_CC_DFP_XCC:
3385 case SP::SELECT_CC_QFP_XCC:
3386 return expandSelectCC(MI, BB, BROpcode: SP::BPXCC);
3387 case SP::SELECT_CC_Int_FCC:
3388 case SP::SELECT_CC_FP_FCC:
3389 case SP::SELECT_CC_DFP_FCC:
3390 case SP::SELECT_CC_QFP_FCC:
3391 if (Subtarget->isV9())
3392 return expandSelectCC(MI, BB, BROpcode: SP::FBCOND_V9);
3393 return expandSelectCC(MI, BB, BROpcode: SP::FBCOND);
3394 }
3395}
3396
3397MachineBasicBlock *
3398SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
3399 unsigned BROpcode) const {
3400 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
3401 DebugLoc dl = MI.getDebugLoc();
3402 unsigned CC = (SPCC::CondCodes)MI.getOperand(i: 3).getImm();
3403
3404 // To "insert" a SELECT_CC instruction, we actually have to insert the
3405 // triangle control-flow pattern. The incoming instruction knows the
3406 // destination vreg to set, the condition code register to branch on, the
3407 // true/false values to select between, and the condition code for the branch.
3408 //
3409 // We produce the following control flow:
3410 // ThisMBB
3411 // | \
3412 // | IfFalseMBB
3413 // | /
3414 // SinkMBB
3415 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3416 MachineFunction::iterator It = ++BB->getIterator();
3417
3418 MachineBasicBlock *ThisMBB = BB;
3419 MachineFunction *F = BB->getParent();
3420 MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
3421 MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
3422 F->insert(MBBI: It, MBB: IfFalseMBB);
3423 F->insert(MBBI: It, MBB: SinkMBB);
3424
3425 // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
3426 SinkMBB->splice(Where: SinkMBB->begin(), Other: ThisMBB,
3427 From: std::next(x: MachineBasicBlock::iterator(MI)), To: ThisMBB->end());
3428 SinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: ThisMBB);
3429
3430 // Set the new successors for ThisMBB.
3431 ThisMBB->addSuccessor(Succ: IfFalseMBB);
3432 ThisMBB->addSuccessor(Succ: SinkMBB);
3433
3434 BuildMI(BB: ThisMBB, MIMD: dl, MCID: TII.get(Opcode: BROpcode))
3435 .addMBB(MBB: SinkMBB)
3436 .addImm(Val: CC);
3437
3438 // IfFalseMBB just falls through to SinkMBB.
3439 IfFalseMBB->addSuccessor(Succ: SinkMBB);
3440
3441 // %Result = phi [ %TrueValue, ThisMBB ], [ %FalseValue, IfFalseMBB ]
3442 BuildMI(BB&: *SinkMBB, I: SinkMBB->begin(), MIMD: dl, MCID: TII.get(Opcode: SP::PHI),
3443 DestReg: MI.getOperand(i: 0).getReg())
3444 .addReg(RegNo: MI.getOperand(i: 1).getReg())
3445 .addMBB(MBB: ThisMBB)
3446 .addReg(RegNo: MI.getOperand(i: 2).getReg())
3447 .addMBB(MBB: IfFalseMBB);
3448
3449 MI.eraseFromParent(); // The pseudo instruction is gone now.
3450 return SinkMBB;
3451}
3452
3453//===----------------------------------------------------------------------===//
3454// Sparc Inline Assembly Support
3455//===----------------------------------------------------------------------===//
3456
3457/// getConstraintType - Given a constraint letter, return the type of
3458/// constraint it is for this target.
3459SparcTargetLowering::ConstraintType
3460SparcTargetLowering::getConstraintType(StringRef Constraint) const {
3461 if (Constraint.size() == 1) {
3462 switch (Constraint[0]) {
3463 default: break;
3464 case 'r':
3465 case 'f':
3466 case 'e':
3467 return C_RegisterClass;
3468 case 'I': // SIMM13
3469 return C_Immediate;
3470 }
3471 }
3472
3473 return TargetLowering::getConstraintType(Constraint);
3474}
3475
3476TargetLowering::ConstraintWeight SparcTargetLowering::
3477getSingleConstraintMatchWeight(AsmOperandInfo &info,
3478 const char *constraint) const {
3479 ConstraintWeight weight = CW_Invalid;
3480 Value *CallOperandVal = info.CallOperandVal;
3481 // If we don't have a value, we can't do a match,
3482 // but allow it at the lowest weight.
3483 if (!CallOperandVal)
3484 return CW_Default;
3485
3486 // Look at the constraint type.
3487 switch (*constraint) {
3488 default:
3489 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3490 break;
3491 case 'I': // SIMM13
3492 if (ConstantInt *C = dyn_cast<ConstantInt>(Val: info.CallOperandVal)) {
3493 if (isInt<13>(x: C->getSExtValue()))
3494 weight = CW_Constant;
3495 }
3496 break;
3497 }
3498 return weight;
3499}
3500
3501/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3502/// vector. If it is invalid, don't add anything to Ops.
3503void SparcTargetLowering::LowerAsmOperandForConstraint(
3504 SDValue Op, StringRef Constraint, std::vector<SDValue> &Ops,
3505 SelectionDAG &DAG) const {
3506 SDValue Result;
3507
3508 // Only support length 1 constraints for now.
3509 if (Constraint.size() > 1)
3510 return;
3511
3512 char ConstraintLetter = Constraint[0];
3513 switch (ConstraintLetter) {
3514 default: break;
3515 case 'I':
3516 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
3517 if (isInt<13>(x: C->getSExtValue())) {
3518 Result = DAG.getSignedTargetConstant(Val: C->getSExtValue(), DL: SDLoc(Op),
3519 VT: Op.getValueType());
3520 break;
3521 }
3522 return;
3523 }
3524 }
3525
3526 if (Result.getNode()) {
3527 Ops.push_back(x: Result);
3528 return;
3529 }
3530 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3531}
3532
3533std::pair<unsigned, const TargetRegisterClass *>
3534SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3535 StringRef Constraint,
3536 MVT VT) const {
3537 if (Constraint.empty())
3538 return std::make_pair(x: 0U, y: nullptr);
3539
3540 if (Constraint.size() == 1) {
3541 switch (Constraint[0]) {
3542 case 'r':
3543 if (VT == MVT::v2i32)
3544 return std::make_pair(x: 0U, y: &SP::IntPairRegClass);
3545 else if (Subtarget->is64Bit())
3546 return std::make_pair(x: 0U, y: &SP::I64RegsRegClass);
3547 else
3548 return std::make_pair(x: 0U, y: &SP::IntRegsRegClass);
3549 case 'f':
3550 if (VT == MVT::f32 || VT == MVT::i32)
3551 return std::make_pair(x: 0U, y: &SP::FPRegsRegClass);
3552 else if (VT == MVT::f64 || VT == MVT::i64)
3553 return std::make_pair(x: 0U, y: &SP::LowDFPRegsRegClass);
3554 else if (VT == MVT::f128)
3555 return std::make_pair(x: 0U, y: &SP::LowQFPRegsRegClass);
3556 // This will generate an error message
3557 return std::make_pair(x: 0U, y: nullptr);
3558 case 'e':
3559 if (VT == MVT::f32 || VT == MVT::i32)
3560 return std::make_pair(x: 0U, y: &SP::FPRegsRegClass);
3561 else if (VT == MVT::f64 || VT == MVT::i64 )
3562 return std::make_pair(x: 0U, y: &SP::DFPRegsRegClass);
3563 else if (VT == MVT::f128)
3564 return std::make_pair(x: 0U, y: &SP::QFPRegsRegClass);
3565 // This will generate an error message
3566 return std::make_pair(x: 0U, y: nullptr);
3567 }
3568 }
3569
3570 if (Constraint.front() != '{')
3571 return std::make_pair(x: 0U, y: nullptr);
3572
3573 assert(Constraint.back() == '}' && "Not a brace enclosed constraint?");
3574 StringRef RegName(Constraint.data() + 1, Constraint.size() - 2);
3575 if (RegName.empty())
3576 return std::make_pair(x: 0U, y: nullptr);
3577
3578 unsigned long long RegNo;
3579 // Handle numbered register aliases.
3580 if (RegName[0] == 'r' &&
3581 getAsUnsignedInteger(Str: RegName.begin() + 1, Radix: 10, Result&: RegNo)) {
3582 // r0-r7 -> g0-g7
3583 // r8-r15 -> o0-o7
3584 // r16-r23 -> l0-l7
3585 // r24-r31 -> i0-i7
3586 if (RegNo > 31)
3587 return std::make_pair(x: 0U, y: nullptr);
3588 const char RegTypes[] = {'g', 'o', 'l', 'i'};
3589 char RegType = RegTypes[RegNo / 8];
3590 char RegIndex = '0' + (RegNo % 8);
3591 char Tmp[] = {'{', RegType, RegIndex, '}', 0};
3592 return getRegForInlineAsmConstraint(TRI, Constraint: Tmp, VT);
3593 }
3594
3595 // Rewrite the fN constraint according to the value type if needed.
3596 if (VT != MVT::f32 && VT != MVT::Other && RegName[0] == 'f' &&
3597 getAsUnsignedInteger(Str: RegName.begin() + 1, Radix: 10, Result&: RegNo)) {
3598 if (VT == MVT::f64 && (RegNo % 2 == 0)) {
3599 return getRegForInlineAsmConstraint(
3600 TRI, Constraint: StringRef("{d" + utostr(X: RegNo / 2) + "}"), VT);
3601 } else if (VT == MVT::f128 && (RegNo % 4 == 0)) {
3602 return getRegForInlineAsmConstraint(
3603 TRI, Constraint: StringRef("{q" + utostr(X: RegNo / 4) + "}"), VT);
3604 } else {
3605 return std::make_pair(x: 0U, y: nullptr);
3606 }
3607 }
3608
3609 auto ResultPair =
3610 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3611 if (!ResultPair.second)
3612 return std::make_pair(x: 0U, y: nullptr);
3613
3614 // Force the use of I64Regs over IntRegs for 64-bit values.
3615 if (Subtarget->is64Bit() && VT == MVT::i64) {
3616 assert(ResultPair.second == &SP::IntRegsRegClass &&
3617 "Unexpected register class");
3618 return std::make_pair(x&: ResultPair.first, y: &SP::I64RegsRegClass);
3619 }
3620
3621 return ResultPair;
3622}
3623
3624bool
3625SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3626 // The Sparc target isn't yet aware of offsets.
3627 return false;
3628}
3629
3630void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3631 SmallVectorImpl<SDValue>& Results,
3632 SelectionDAG &DAG) const {
3633
3634 SDLoc dl(N);
3635
3636 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3637
3638 switch (N->getOpcode()) {
3639 default:
3640 llvm_unreachable("Do not know how to custom type legalize this operation!");
3641
3642 case ISD::FP_TO_SINT:
3643 case ISD::FP_TO_UINT:
3644 // Custom lower only if it involves f128 or i64.
3645 if (N->getOperand(Num: 0).getValueType() != MVT::f128
3646 || N->getValueType(ResNo: 0) != MVT::i64)
3647 return;
3648 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3649 ? RTLIB::FPTOSINT_F128_I64
3650 : RTLIB::FPTOUINT_F128_I64);
3651
3652 Results.push_back(Elt: LowerF128Op(Op: SDValue(N, 0), DAG, LibFunc: libCall, numArgs: 1));
3653 return;
3654 case ISD::READCYCLECOUNTER: {
3655 assert(Subtarget->hasLeonCycleCounter());
3656 SDValue Lo = DAG.getCopyFromReg(Chain: N->getOperand(Num: 0), dl, Reg: SP::ASR23, VT: MVT::i32);
3657 SDValue Hi = DAG.getCopyFromReg(Chain: Lo, dl, Reg: SP::G0, VT: MVT::i32);
3658 SDValue Ops[] = { Lo, Hi };
3659 SDValue Pair = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, Ops);
3660 Results.push_back(Elt: Pair);
3661 Results.push_back(Elt: N->getOperand(Num: 0));
3662 return;
3663 }
3664 case ISD::SINT_TO_FP:
3665 case ISD::UINT_TO_FP:
3666 // Custom lower only if it involves f128 or i64.
3667 if (N->getValueType(ResNo: 0) != MVT::f128
3668 || N->getOperand(Num: 0).getValueType() != MVT::i64)
3669 return;
3670
3671 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3672 ? RTLIB::SINTTOFP_I64_F128
3673 : RTLIB::UINTTOFP_I64_F128);
3674
3675 Results.push_back(Elt: LowerF128Op(Op: SDValue(N, 0), DAG, LibFunc: libCall, numArgs: 1));
3676 return;
3677 case ISD::LOAD: {
3678 LoadSDNode *Ld = cast<LoadSDNode>(Val: N);
3679 // Custom handling only for i64: turn i64 load into a v2i32 load,
3680 // and a bitcast.
3681 if (Ld->getValueType(ResNo: 0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64)
3682 return;
3683
3684 SDLoc dl(N);
3685 SDValue LoadRes = DAG.getExtLoad(
3686 ExtType: Ld->getExtensionType(), dl, VT: MVT::v2i32, Chain: Ld->getChain(),
3687 Ptr: Ld->getBasePtr(), PtrInfo: Ld->getPointerInfo(), MemVT: MVT::v2i32, Alignment: Ld->getBaseAlign(),
3688 MMOFlags: Ld->getMemOperand()->getFlags(), Metadata: Ld->getAAInfo());
3689
3690 SDValue Res = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i64, Operand: LoadRes);
3691 Results.push_back(Elt: Res);
3692 Results.push_back(Elt: LoadRes.getValue(R: 1));
3693 return;
3694 }
3695 }
3696}
3697
3698// Override to enable LOAD_STACK_GUARD lowering on Linux.
3699bool SparcTargetLowering::useLoadStackGuardNode(const Module &M) const {
3700 if (!Subtarget->getTargetTriple().isOSLinux())
3701 return TargetLowering::useLoadStackGuardNode(M);
3702 return true;
3703}
3704
3705bool SparcTargetLowering::isFNegFree(EVT VT) const {
3706 if (Subtarget->isVIS3())
3707 return VT == MVT::f32 || VT == MVT::f64;
3708 return false;
3709}
3710
3711bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
3712 bool ForCodeSize) const {
3713 if (VT != MVT::f32 && VT != MVT::f64)
3714 return false;
3715 if (Subtarget->isVIS() && Imm.isZero())
3716 return true;
3717 if (Subtarget->isVIS3())
3718 return Imm.isExactlyValue(V: +0.5) || Imm.isExactlyValue(V: -0.5) ||
3719 Imm.getExactLog2Abs() == -1;
3720 return false;
3721}
3722
3723bool SparcTargetLowering::isCtlzFast() const { return Subtarget->isVIS3(); }
3724
3725bool SparcTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
3726 // We lack native cttz, however,
3727 // On 64-bit targets it is cheap to implement it in terms of popc.
3728 if (Subtarget->is64Bit() && Subtarget->usePopc())
3729 return true;
3730 // Otherwise, implementing cttz in terms of ctlz is still cheap.
3731 return isCheapToSpeculateCtlz(Ty);
3732}
3733
3734bool SparcTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
3735 EVT VT) const {
3736 return Subtarget->isUA2007() && !Subtarget->useSoftFloat();
3737}
3738
3739void SparcTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
3740 SDNode *Node) const {
3741 assert(MI.getOpcode() == SP::SUBCCrr || MI.getOpcode() == SP::SUBCCri);
3742 // If the result is dead, replace it with %g0.
3743 if (!Node->hasAnyUseOfValue(Value: 0))
3744 MI.getOperand(i: 0).setReg(SP::G0);
3745}
3746
3747Instruction *SparcTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
3748 Instruction *Inst,
3749 AtomicOrdering Ord) const {
3750 bool HasStoreSemantics =
3751 isa<AtomicCmpXchgInst, AtomicRMWInst, StoreInst>(Val: Inst);
3752 if (HasStoreSemantics && isReleaseOrStronger(AO: Ord))
3753 return Builder.CreateFence(Ordering: AtomicOrdering::Release);
3754 return nullptr;
3755}
3756
3757Instruction *SparcTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
3758 Instruction *Inst,
3759 AtomicOrdering Ord) const {
3760 // V8 loads already come with implicit acquire barrier so there's no need to
3761 // emit it again.
3762 bool HasLoadSemantics = isa<AtomicCmpXchgInst, AtomicRMWInst, LoadInst>(Val: Inst);
3763 if (Subtarget->isV9() && HasLoadSemantics && isAcquireOrStronger(AO: Ord))
3764 return Builder.CreateFence(Ordering: AtomicOrdering::Acquire);
3765
3766 // SC plain stores would need a trailing full barrier.
3767 if (isa<StoreInst>(Val: Inst) && Ord == AtomicOrdering::SequentiallyConsistent)
3768 return Builder.CreateFence(Ordering: Ord);
3769 return nullptr;
3770}
3771