1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t SystemZRegDiffLists[] = {
12 /* 0 */ -64, 72, -40, -30, 72, -40, 0,
13 /* 7 */ -62, 72, -40, -30, 72, -40, 0,
14 /* 14 */ -60, 72, -40, -30, 72, -40, 0,
15 /* 21 */ -58, 72, -40, -30, 72, -40, 0,
16 /* 28 */ 32, 72, -40, 0,
17 /* 32 */ 40, -72, -32, 0,
18 /* 36 */ -48, 32, -16, -15, 32, -16, 0,
19 /* 43 */ -47, 32, -16, -15, 32, -16, 0,
20 /* 50 */ -46, 32, -16, -15, 32, -16, 0,
21 /* 57 */ -45, 32, -16, -15, 32, -16, 0,
22 /* 64 */ -44, 32, -16, -15, 32, -16, 0,
23 /* 71 */ -43, 32, -16, -15, 32, -16, 0,
24 /* 78 */ -42, 32, -16, -15, 32, -16, 0,
25 /* 85 */ -41, 32, -16, -15, 32, -16, 0,
26 /* 92 */ 1, 1, 1, 0,
27 /* 96 */ 2, 0,
28 /* 98 */ -32, 40, 0,
29 /* 101 */ -16, 40, 0,
30 /* 104 */ -32, 41, 0,
31 /* 107 */ -16, 41, 0,
32 /* 110 */ -32, 42, 0,
33 /* 113 */ -16, 42, 0,
34 /* 116 */ -32, 43, 0,
35 /* 119 */ -16, 43, 0,
36 /* 122 */ -32, 44, 0,
37 /* 125 */ -16, 44, 0,
38 /* 128 */ -32, 45, 0,
39 /* 131 */ -16, 45, 0,
40 /* 134 */ -32, 46, 0,
41 /* 137 */ -16, 46, 0,
42 /* 140 */ -32, 47, 0,
43 /* 143 */ -16, 47, 0,
44 /* 146 */ -32, 48, 0,
45 /* 149 */ -16, 48, 0,
46 /* 152 */ 40, -72, -32, 88, 0,
47 /* 157 */ 40, -72, -32, 90, 0,
48 /* 162 */ 40, -72, -32, 92, 0,
49 /* 167 */ 40, -72, -32, 94, 0,
50 /* 172 */ 40, -72, -32, 96, 0,
51};
52
53extern const LaneBitmask SystemZLaneMaskLists[] = {
54 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
55 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000008),
56 /* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
57 /* 8 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
58};
59
60extern const uint16_t SystemZSubRegIdxLists[] = {
61 /* 0 */ 3, 2, 1,
62 /* 3 */ 4, 2,
63 /* 5 */ 3, 4, 2, 5, 7, 6,
64 /* 11 */ 3, 2, 1, 5, 6, 8,
65};
66
67
68#ifdef __GNUC__
69#pragma GCC diagnostic push
70#pragma GCC diagnostic ignored "-Woverlength-strings"
71#endif
72extern const char SystemZRegStrings[] = {
73 /* 0 */ "A10\000"
74 /* 4 */ "C10\000"
75 /* 8 */ "V10\000"
76 /* 12 */ "V20\000"
77 /* 16 */ "V30\000"
78 /* 20 */ "A0\000"
79 /* 23 */ "C0\000"
80 /* 26 */ "V0\000"
81 /* 29 */ "A11\000"
82 /* 33 */ "C11\000"
83 /* 37 */ "V11\000"
84 /* 41 */ "V21\000"
85 /* 45 */ "V31\000"
86 /* 49 */ "A1\000"
87 /* 52 */ "C1\000"
88 /* 55 */ "V1\000"
89 /* 58 */ "A12\000"
90 /* 62 */ "C12\000"
91 /* 66 */ "V12\000"
92 /* 70 */ "V22\000"
93 /* 74 */ "A2\000"
94 /* 77 */ "C2\000"
95 /* 80 */ "V2\000"
96 /* 83 */ "A13\000"
97 /* 87 */ "C13\000"
98 /* 91 */ "V13\000"
99 /* 95 */ "V23\000"
100 /* 99 */ "A3\000"
101 /* 102 */ "C3\000"
102 /* 105 */ "V3\000"
103 /* 108 */ "A14\000"
104 /* 112 */ "C14\000"
105 /* 116 */ "V14\000"
106 /* 120 */ "V24\000"
107 /* 124 */ "A4\000"
108 /* 127 */ "C4\000"
109 /* 130 */ "V4\000"
110 /* 133 */ "A15\000"
111 /* 137 */ "C15\000"
112 /* 141 */ "V15\000"
113 /* 145 */ "V25\000"
114 /* 149 */ "A5\000"
115 /* 152 */ "C5\000"
116 /* 155 */ "V5\000"
117 /* 158 */ "V16\000"
118 /* 162 */ "V26\000"
119 /* 166 */ "A6\000"
120 /* 169 */ "C6\000"
121 /* 172 */ "V6\000"
122 /* 175 */ "V17\000"
123 /* 179 */ "V27\000"
124 /* 183 */ "A7\000"
125 /* 186 */ "C7\000"
126 /* 189 */ "V7\000"
127 /* 192 */ "V18\000"
128 /* 196 */ "V28\000"
129 /* 200 */ "A8\000"
130 /* 203 */ "C8\000"
131 /* 206 */ "V8\000"
132 /* 209 */ "V19\000"
133 /* 213 */ "V29\000"
134 /* 217 */ "A9\000"
135 /* 220 */ "C9\000"
136 /* 223 */ "V9\000"
137 /* 226 */ "CC\000"
138 /* 229 */ "FPC\000"
139 /* 233 */ "F10D\000"
140 /* 238 */ "R10D\000"
141 /* 243 */ "F20D\000"
142 /* 248 */ "F30D\000"
143 /* 253 */ "F0D\000"
144 /* 257 */ "R0D\000"
145 /* 261 */ "F11D\000"
146 /* 266 */ "R11D\000"
147 /* 271 */ "F21D\000"
148 /* 276 */ "F31D\000"
149 /* 281 */ "F1D\000"
150 /* 285 */ "R1D\000"
151 /* 289 */ "F12D\000"
152 /* 294 */ "R12D\000"
153 /* 299 */ "F22D\000"
154 /* 304 */ "F2D\000"
155 /* 308 */ "R2D\000"
156 /* 312 */ "F13D\000"
157 /* 317 */ "R13D\000"
158 /* 322 */ "F23D\000"
159 /* 327 */ "F3D\000"
160 /* 331 */ "R3D\000"
161 /* 335 */ "F14D\000"
162 /* 340 */ "R14D\000"
163 /* 345 */ "F24D\000"
164 /* 350 */ "F4D\000"
165 /* 354 */ "R4D\000"
166 /* 358 */ "F15D\000"
167 /* 363 */ "R15D\000"
168 /* 368 */ "F25D\000"
169 /* 373 */ "F5D\000"
170 /* 377 */ "R5D\000"
171 /* 381 */ "F16D\000"
172 /* 386 */ "F26D\000"
173 /* 391 */ "F6D\000"
174 /* 395 */ "R6D\000"
175 /* 399 */ "F17D\000"
176 /* 404 */ "F27D\000"
177 /* 409 */ "F7D\000"
178 /* 413 */ "R7D\000"
179 /* 417 */ "F18D\000"
180 /* 422 */ "F28D\000"
181 /* 427 */ "F8D\000"
182 /* 431 */ "R8D\000"
183 /* 435 */ "F19D\000"
184 /* 440 */ "F29D\000"
185 /* 445 */ "F9D\000"
186 /* 449 */ "R9D\000"
187 /* 453 */ "F10H\000"
188 /* 458 */ "R10H\000"
189 /* 463 */ "F20H\000"
190 /* 468 */ "F30H\000"
191 /* 473 */ "F0H\000"
192 /* 477 */ "R0H\000"
193 /* 481 */ "F11H\000"
194 /* 486 */ "R11H\000"
195 /* 491 */ "F21H\000"
196 /* 496 */ "F31H\000"
197 /* 501 */ "F1H\000"
198 /* 505 */ "R1H\000"
199 /* 509 */ "F12H\000"
200 /* 514 */ "R12H\000"
201 /* 519 */ "F22H\000"
202 /* 524 */ "F2H\000"
203 /* 528 */ "R2H\000"
204 /* 532 */ "F13H\000"
205 /* 537 */ "R13H\000"
206 /* 542 */ "F23H\000"
207 /* 547 */ "F3H\000"
208 /* 551 */ "R3H\000"
209 /* 555 */ "F14H\000"
210 /* 560 */ "R14H\000"
211 /* 565 */ "F24H\000"
212 /* 570 */ "F4H\000"
213 /* 574 */ "R4H\000"
214 /* 578 */ "F15H\000"
215 /* 583 */ "R15H\000"
216 /* 588 */ "F25H\000"
217 /* 593 */ "F5H\000"
218 /* 597 */ "R5H\000"
219 /* 601 */ "F16H\000"
220 /* 606 */ "F26H\000"
221 /* 611 */ "F6H\000"
222 /* 615 */ "R6H\000"
223 /* 619 */ "F17H\000"
224 /* 624 */ "F27H\000"
225 /* 629 */ "F7H\000"
226 /* 633 */ "R7H\000"
227 /* 637 */ "F18H\000"
228 /* 642 */ "F28H\000"
229 /* 647 */ "F8H\000"
230 /* 651 */ "R8H\000"
231 /* 655 */ "F19H\000"
232 /* 660 */ "F29H\000"
233 /* 665 */ "F9H\000"
234 /* 669 */ "R9H\000"
235 /* 673 */ "R10L\000"
236 /* 678 */ "R0L\000"
237 /* 682 */ "R11L\000"
238 /* 687 */ "R1L\000"
239 /* 691 */ "R12L\000"
240 /* 696 */ "R2L\000"
241 /* 700 */ "R13L\000"
242 /* 705 */ "R3L\000"
243 /* 709 */ "R14L\000"
244 /* 714 */ "R4L\000"
245 /* 718 */ "R15L\000"
246 /* 723 */ "R5L\000"
247 /* 727 */ "R6L\000"
248 /* 731 */ "R7L\000"
249 /* 735 */ "R8L\000"
250 /* 739 */ "R9L\000"
251 /* 743 */ "R10Q\000"
252 /* 748 */ "F0Q\000"
253 /* 752 */ "R0Q\000"
254 /* 756 */ "F1Q\000"
255 /* 760 */ "F12Q\000"
256 /* 765 */ "R12Q\000"
257 /* 770 */ "R2Q\000"
258 /* 774 */ "F13Q\000"
259 /* 779 */ "R14Q\000"
260 /* 784 */ "F4Q\000"
261 /* 788 */ "R4Q\000"
262 /* 792 */ "F5Q\000"
263 /* 796 */ "R6Q\000"
264 /* 800 */ "F8Q\000"
265 /* 804 */ "R8Q\000"
266 /* 808 */ "F9Q\000"
267 /* 812 */ "F10S\000"
268 /* 817 */ "F20S\000"
269 /* 822 */ "F30S\000"
270 /* 827 */ "F0S\000"
271 /* 831 */ "F11S\000"
272 /* 836 */ "F21S\000"
273 /* 841 */ "F31S\000"
274 /* 846 */ "F1S\000"
275 /* 850 */ "F12S\000"
276 /* 855 */ "F22S\000"
277 /* 860 */ "F2S\000"
278 /* 864 */ "F13S\000"
279 /* 869 */ "F23S\000"
280 /* 874 */ "F3S\000"
281 /* 878 */ "F14S\000"
282 /* 883 */ "F24S\000"
283 /* 888 */ "F4S\000"
284 /* 892 */ "F15S\000"
285 /* 897 */ "F25S\000"
286 /* 902 */ "F5S\000"
287 /* 906 */ "F16S\000"
288 /* 911 */ "F26S\000"
289 /* 916 */ "F6S\000"
290 /* 920 */ "F17S\000"
291 /* 925 */ "F27S\000"
292 /* 930 */ "F7S\000"
293 /* 934 */ "F18S\000"
294 /* 939 */ "F28S\000"
295 /* 944 */ "F8S\000"
296 /* 948 */ "F19S\000"
297 /* 953 */ "F29S\000"
298 /* 958 */ "F9S\000"
299};
300#ifdef __GNUC__
301#pragma GCC diagnostic pop
302#endif
303
304extern const MCRegisterDesc SystemZRegDesc[] = { // Descriptors
305 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
306 { .Name: 226, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24576, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
307 { .Name: 229, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24577, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
308 { .Name: 20, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24578, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
309 { .Name: 49, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24579, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
310 { .Name: 74, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24580, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
311 { .Name: 99, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24581, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
312 { .Name: 124, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24582, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
313 { .Name: 149, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24583, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
314 { .Name: 166, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24584, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
315 { .Name: 183, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24585, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
316 { .Name: 200, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24586, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
317 { .Name: 217, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24587, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
318 { .Name: 0, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24588, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
319 { .Name: 29, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24589, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
320 { .Name: 58, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24590, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
321 { .Name: 83, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24591, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
322 { .Name: 108, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24592, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
323 { .Name: 133, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24593, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
324 { .Name: 23, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24594, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
325 { .Name: 52, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24595, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
326 { .Name: 77, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24596, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
327 { .Name: 102, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24597, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
328 { .Name: 127, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24598, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
329 { .Name: 152, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24599, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
330 { .Name: 169, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24600, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
331 { .Name: 186, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24601, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
332 { .Name: 203, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24602, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
333 { .Name: 220, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24603, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
334 { .Name: 4, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24604, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
335 { .Name: 33, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24605, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
336 { .Name: 62, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24606, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
337 { .Name: 87, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24607, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
338 { .Name: 112, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24608, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
339 { .Name: 137, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24609, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
340 { .Name: 26, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24610, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
341 { .Name: 55, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24611, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
342 { .Name: 80, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24612, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
343 { .Name: 105, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24613, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
344 { .Name: 130, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24614, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
345 { .Name: 155, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24615, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
346 { .Name: 172, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24616, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
347 { .Name: 189, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24617, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
348 { .Name: 206, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24618, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
349 { .Name: 223, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24619, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
350 { .Name: 8, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24620, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
351 { .Name: 37, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24621, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
352 { .Name: 66, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24622, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
353 { .Name: 91, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24623, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
354 { .Name: 116, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24624, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
355 { .Name: 141, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24625, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
356 { .Name: 158, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24626, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
357 { .Name: 175, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24627, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
358 { .Name: 192, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24628, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
359 { .Name: 209, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24629, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
360 { .Name: 12, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24630, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
361 { .Name: 41, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24631, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
362 { .Name: 70, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24632, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
363 { .Name: 95, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24633, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
364 { .Name: 120, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24634, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
365 { .Name: 145, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24635, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
366 { .Name: 162, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24636, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
367 { .Name: 179, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24637, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
368 { .Name: 196, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24638, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
369 { .Name: 213, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24639, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
370 { .Name: 16, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24640, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
371 { .Name: 45, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24641, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
372 { .Name: 253, .SubRegs: 4, .SuperRegs: 174, .SubRegIndices: 1, .RegUnits: 24610, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
373 { .Name: 281, .SubRegs: 4, .SuperRegs: 174, .SubRegIndices: 1, .RegUnits: 24611, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
374 { .Name: 304, .SubRegs: 4, .SuperRegs: 169, .SubRegIndices: 1, .RegUnits: 24612, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
375 { .Name: 327, .SubRegs: 4, .SuperRegs: 169, .SubRegIndices: 1, .RegUnits: 24613, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
376 { .Name: 350, .SubRegs: 4, .SuperRegs: 169, .SubRegIndices: 1, .RegUnits: 24614, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
377 { .Name: 373, .SubRegs: 4, .SuperRegs: 169, .SubRegIndices: 1, .RegUnits: 24615, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
378 { .Name: 391, .SubRegs: 4, .SuperRegs: 164, .SubRegIndices: 1, .RegUnits: 24616, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
379 { .Name: 409, .SubRegs: 4, .SuperRegs: 164, .SubRegIndices: 1, .RegUnits: 24617, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
380 { .Name: 427, .SubRegs: 4, .SuperRegs: 164, .SubRegIndices: 1, .RegUnits: 24618, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
381 { .Name: 445, .SubRegs: 4, .SuperRegs: 164, .SubRegIndices: 1, .RegUnits: 24619, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
382 { .Name: 233, .SubRegs: 4, .SuperRegs: 159, .SubRegIndices: 1, .RegUnits: 24620, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
383 { .Name: 261, .SubRegs: 4, .SuperRegs: 159, .SubRegIndices: 1, .RegUnits: 24621, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
384 { .Name: 289, .SubRegs: 4, .SuperRegs: 159, .SubRegIndices: 1, .RegUnits: 24622, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
385 { .Name: 312, .SubRegs: 4, .SuperRegs: 159, .SubRegIndices: 1, .RegUnits: 24623, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
386 { .Name: 335, .SubRegs: 4, .SuperRegs: 154, .SubRegIndices: 1, .RegUnits: 24624, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
387 { .Name: 358, .SubRegs: 4, .SuperRegs: 154, .SubRegIndices: 1, .RegUnits: 24625, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
388 { .Name: 381, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24626, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
389 { .Name: 399, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24627, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
390 { .Name: 417, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24628, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
391 { .Name: 435, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24629, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
392 { .Name: 243, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24630, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
393 { .Name: 271, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24631, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
394 { .Name: 299, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24632, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
395 { .Name: 322, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24633, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
396 { .Name: 345, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24634, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
397 { .Name: 368, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24635, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
398 { .Name: 386, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24636, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
399 { .Name: 404, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24637, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
400 { .Name: 422, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24638, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
401 { .Name: 440, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24639, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
402 { .Name: 248, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24640, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
403 { .Name: 276, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24641, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
404 { .Name: 473, .SubRegs: 6, .SuperRegs: 172, .SubRegIndices: 3, .RegUnits: 24610, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
405 { .Name: 501, .SubRegs: 6, .SuperRegs: 172, .SubRegIndices: 3, .RegUnits: 24611, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
406 { .Name: 524, .SubRegs: 6, .SuperRegs: 167, .SubRegIndices: 3, .RegUnits: 24612, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
407 { .Name: 547, .SubRegs: 6, .SuperRegs: 167, .SubRegIndices: 3, .RegUnits: 24613, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
408 { .Name: 570, .SubRegs: 6, .SuperRegs: 167, .SubRegIndices: 3, .RegUnits: 24614, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
409 { .Name: 593, .SubRegs: 6, .SuperRegs: 167, .SubRegIndices: 3, .RegUnits: 24615, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
410 { .Name: 611, .SubRegs: 6, .SuperRegs: 162, .SubRegIndices: 3, .RegUnits: 24616, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
411 { .Name: 629, .SubRegs: 6, .SuperRegs: 162, .SubRegIndices: 3, .RegUnits: 24617, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
412 { .Name: 647, .SubRegs: 6, .SuperRegs: 162, .SubRegIndices: 3, .RegUnits: 24618, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
413 { .Name: 665, .SubRegs: 6, .SuperRegs: 162, .SubRegIndices: 3, .RegUnits: 24619, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
414 { .Name: 453, .SubRegs: 6, .SuperRegs: 157, .SubRegIndices: 3, .RegUnits: 24620, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
415 { .Name: 481, .SubRegs: 6, .SuperRegs: 157, .SubRegIndices: 3, .RegUnits: 24621, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
416 { .Name: 509, .SubRegs: 6, .SuperRegs: 157, .SubRegIndices: 3, .RegUnits: 24622, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
417 { .Name: 532, .SubRegs: 6, .SuperRegs: 157, .SubRegIndices: 3, .RegUnits: 24623, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
418 { .Name: 555, .SubRegs: 6, .SuperRegs: 152, .SubRegIndices: 3, .RegUnits: 24624, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
419 { .Name: 578, .SubRegs: 6, .SuperRegs: 152, .SubRegIndices: 3, .RegUnits: 24625, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
420 { .Name: 601, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24626, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
421 { .Name: 619, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24627, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
422 { .Name: 637, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24628, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
423 { .Name: 655, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24629, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
424 { .Name: 463, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24630, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
425 { .Name: 491, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24631, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
426 { .Name: 519, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24632, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
427 { .Name: 542, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24633, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
428 { .Name: 565, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24634, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
429 { .Name: 588, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24635, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
430 { .Name: 606, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24636, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
431 { .Name: 624, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24637, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
432 { .Name: 642, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24638, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
433 { .Name: 660, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24639, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
434 { .Name: 468, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24640, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
435 { .Name: 496, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24641, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
436 { .Name: 748, .SubRegs: 0, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393250, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
437 { .Name: 756, .SubRegs: 0, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393251, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
438 { .Name: 784, .SubRegs: 7, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393254, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
439 { .Name: 792, .SubRegs: 7, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393255, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
440 { .Name: 800, .SubRegs: 14, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393258, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
441 { .Name: 808, .SubRegs: 14, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393259, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
442 { .Name: 760, .SubRegs: 21, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393262, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
443 { .Name: 774, .SubRegs: 21, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393263, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
444 { .Name: 827, .SubRegs: 5, .SuperRegs: 173, .SubRegIndices: 2, .RegUnits: 24610, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
445 { .Name: 846, .SubRegs: 5, .SuperRegs: 173, .SubRegIndices: 2, .RegUnits: 24611, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
446 { .Name: 860, .SubRegs: 5, .SuperRegs: 168, .SubRegIndices: 2, .RegUnits: 24612, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
447 { .Name: 874, .SubRegs: 5, .SuperRegs: 168, .SubRegIndices: 2, .RegUnits: 24613, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
448 { .Name: 888, .SubRegs: 5, .SuperRegs: 168, .SubRegIndices: 2, .RegUnits: 24614, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
449 { .Name: 902, .SubRegs: 5, .SuperRegs: 168, .SubRegIndices: 2, .RegUnits: 24615, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
450 { .Name: 916, .SubRegs: 5, .SuperRegs: 163, .SubRegIndices: 2, .RegUnits: 24616, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
451 { .Name: 930, .SubRegs: 5, .SuperRegs: 163, .SubRegIndices: 2, .RegUnits: 24617, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
452 { .Name: 944, .SubRegs: 5, .SuperRegs: 163, .SubRegIndices: 2, .RegUnits: 24618, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
453 { .Name: 958, .SubRegs: 5, .SuperRegs: 163, .SubRegIndices: 2, .RegUnits: 24619, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
454 { .Name: 812, .SubRegs: 5, .SuperRegs: 158, .SubRegIndices: 2, .RegUnits: 24620, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
455 { .Name: 831, .SubRegs: 5, .SuperRegs: 158, .SubRegIndices: 2, .RegUnits: 24621, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
456 { .Name: 850, .SubRegs: 5, .SuperRegs: 158, .SubRegIndices: 2, .RegUnits: 24622, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
457 { .Name: 864, .SubRegs: 5, .SuperRegs: 158, .SubRegIndices: 2, .RegUnits: 24623, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
458 { .Name: 878, .SubRegs: 5, .SuperRegs: 153, .SubRegIndices: 2, .RegUnits: 24624, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
459 { .Name: 892, .SubRegs: 5, .SuperRegs: 153, .SubRegIndices: 2, .RegUnits: 24625, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
460 { .Name: 906, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24626, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
461 { .Name: 920, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24627, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
462 { .Name: 934, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24628, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
463 { .Name: 948, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24629, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
464 { .Name: 817, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24630, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
465 { .Name: 836, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24631, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
466 { .Name: 855, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24632, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
467 { .Name: 869, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24633, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
468 { .Name: 883, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24634, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
469 { .Name: 897, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24635, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
470 { .Name: 911, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24636, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
471 { .Name: 925, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24637, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
472 { .Name: 939, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24638, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
473 { .Name: 953, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24639, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
474 { .Name: 822, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24640, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
475 { .Name: 841, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24641, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
476 { .Name: 257, .SubRegs: 40, .SuperRegs: 147, .SubRegIndices: 3, .RegUnits: 385090, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
477 { .Name: 285, .SubRegs: 40, .SuperRegs: 141, .SubRegIndices: 3, .RegUnits: 385092, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
478 { .Name: 308, .SubRegs: 40, .SuperRegs: 141, .SubRegIndices: 3, .RegUnits: 385094, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
479 { .Name: 331, .SubRegs: 40, .SuperRegs: 135, .SubRegIndices: 3, .RegUnits: 385096, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
480 { .Name: 354, .SubRegs: 40, .SuperRegs: 135, .SubRegIndices: 3, .RegUnits: 385098, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
481 { .Name: 377, .SubRegs: 40, .SuperRegs: 129, .SubRegIndices: 3, .RegUnits: 385100, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
482 { .Name: 395, .SubRegs: 40, .SuperRegs: 129, .SubRegIndices: 3, .RegUnits: 385102, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
483 { .Name: 413, .SubRegs: 40, .SuperRegs: 123, .SubRegIndices: 3, .RegUnits: 385104, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
484 { .Name: 431, .SubRegs: 40, .SuperRegs: 123, .SubRegIndices: 3, .RegUnits: 385106, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
485 { .Name: 449, .SubRegs: 40, .SuperRegs: 117, .SubRegIndices: 3, .RegUnits: 385108, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
486 { .Name: 238, .SubRegs: 40, .SuperRegs: 117, .SubRegIndices: 3, .RegUnits: 385110, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
487 { .Name: 266, .SubRegs: 40, .SuperRegs: 111, .SubRegIndices: 3, .RegUnits: 385112, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
488 { .Name: 294, .SubRegs: 40, .SuperRegs: 111, .SubRegIndices: 3, .RegUnits: 385114, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
489 { .Name: 317, .SubRegs: 40, .SuperRegs: 105, .SubRegIndices: 3, .RegUnits: 385116, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
490 { .Name: 340, .SubRegs: 40, .SuperRegs: 105, .SubRegIndices: 3, .RegUnits: 385118, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
491 { .Name: 363, .SubRegs: 40, .SuperRegs: 99, .SubRegIndices: 3, .RegUnits: 385120, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
492 { .Name: 477, .SubRegs: 6, .SuperRegs: 149, .SubRegIndices: 3, .RegUnits: 24643, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
493 { .Name: 505, .SubRegs: 6, .SuperRegs: 143, .SubRegIndices: 3, .RegUnits: 24645, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
494 { .Name: 528, .SubRegs: 6, .SuperRegs: 143, .SubRegIndices: 3, .RegUnits: 24647, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
495 { .Name: 551, .SubRegs: 6, .SuperRegs: 137, .SubRegIndices: 3, .RegUnits: 24649, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
496 { .Name: 574, .SubRegs: 6, .SuperRegs: 137, .SubRegIndices: 3, .RegUnits: 24651, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
497 { .Name: 597, .SubRegs: 6, .SuperRegs: 131, .SubRegIndices: 3, .RegUnits: 24653, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
498 { .Name: 615, .SubRegs: 6, .SuperRegs: 131, .SubRegIndices: 3, .RegUnits: 24655, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
499 { .Name: 633, .SubRegs: 6, .SuperRegs: 125, .SubRegIndices: 3, .RegUnits: 24657, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
500 { .Name: 651, .SubRegs: 6, .SuperRegs: 125, .SubRegIndices: 3, .RegUnits: 24659, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
501 { .Name: 669, .SubRegs: 6, .SuperRegs: 119, .SubRegIndices: 3, .RegUnits: 24661, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
502 { .Name: 458, .SubRegs: 6, .SuperRegs: 119, .SubRegIndices: 3, .RegUnits: 24663, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
503 { .Name: 486, .SubRegs: 6, .SuperRegs: 113, .SubRegIndices: 3, .RegUnits: 24665, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
504 { .Name: 514, .SubRegs: 6, .SuperRegs: 113, .SubRegIndices: 3, .RegUnits: 24667, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
505 { .Name: 537, .SubRegs: 6, .SuperRegs: 107, .SubRegIndices: 3, .RegUnits: 24669, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
506 { .Name: 560, .SubRegs: 6, .SuperRegs: 107, .SubRegIndices: 3, .RegUnits: 24671, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
507 { .Name: 583, .SubRegs: 6, .SuperRegs: 101, .SubRegIndices: 3, .RegUnits: 24673, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
508 { .Name: 678, .SubRegs: 6, .SuperRegs: 146, .SubRegIndices: 3, .RegUnits: 24642, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
509 { .Name: 687, .SubRegs: 6, .SuperRegs: 140, .SubRegIndices: 3, .RegUnits: 24644, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
510 { .Name: 696, .SubRegs: 6, .SuperRegs: 140, .SubRegIndices: 3, .RegUnits: 24646, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
511 { .Name: 705, .SubRegs: 6, .SuperRegs: 134, .SubRegIndices: 3, .RegUnits: 24648, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
512 { .Name: 714, .SubRegs: 6, .SuperRegs: 134, .SubRegIndices: 3, .RegUnits: 24650, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
513 { .Name: 723, .SubRegs: 6, .SuperRegs: 128, .SubRegIndices: 3, .RegUnits: 24652, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
514 { .Name: 727, .SubRegs: 6, .SuperRegs: 128, .SubRegIndices: 3, .RegUnits: 24654, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
515 { .Name: 731, .SubRegs: 6, .SuperRegs: 122, .SubRegIndices: 3, .RegUnits: 24656, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
516 { .Name: 735, .SubRegs: 6, .SuperRegs: 122, .SubRegIndices: 3, .RegUnits: 24658, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
517 { .Name: 739, .SubRegs: 6, .SuperRegs: 116, .SubRegIndices: 3, .RegUnits: 24660, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
518 { .Name: 673, .SubRegs: 6, .SuperRegs: 116, .SubRegIndices: 3, .RegUnits: 24662, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
519 { .Name: 682, .SubRegs: 6, .SuperRegs: 110, .SubRegIndices: 3, .RegUnits: 24664, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
520 { .Name: 691, .SubRegs: 6, .SuperRegs: 110, .SubRegIndices: 3, .RegUnits: 24666, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
521 { .Name: 700, .SubRegs: 6, .SuperRegs: 104, .SubRegIndices: 3, .RegUnits: 24668, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
522 { .Name: 709, .SubRegs: 6, .SuperRegs: 104, .SubRegIndices: 3, .RegUnits: 24670, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
523 { .Name: 718, .SubRegs: 6, .SuperRegs: 98, .SubRegIndices: 3, .RegUnits: 24672, .RegUnitLaneMasks: 8, .IsConstant: 0, .IsArtificial: 0 },
524 { .Name: 752, .SubRegs: 36, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376898, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
525 { .Name: 770, .SubRegs: 43, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376902, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
526 { .Name: 788, .SubRegs: 50, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376906, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
527 { .Name: 796, .SubRegs: 57, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376910, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
528 { .Name: 804, .SubRegs: 64, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376914, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
529 { .Name: 743, .SubRegs: 71, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376918, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
530 { .Name: 765, .SubRegs: 78, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376922, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
531 { .Name: 779, .SubRegs: 85, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376926, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
532};
533
534extern const MCPhysReg SystemZRegUnitRoots[][2] = {
535 { SystemZ::CC },
536 { SystemZ::FPC },
537 { SystemZ::A0 },
538 { SystemZ::A1 },
539 { SystemZ::A2 },
540 { SystemZ::A3 },
541 { SystemZ::A4 },
542 { SystemZ::A5 },
543 { SystemZ::A6 },
544 { SystemZ::A7 },
545 { SystemZ::A8 },
546 { SystemZ::A9 },
547 { SystemZ::A10 },
548 { SystemZ::A11 },
549 { SystemZ::A12 },
550 { SystemZ::A13 },
551 { SystemZ::A14 },
552 { SystemZ::A15 },
553 { SystemZ::C0 },
554 { SystemZ::C1 },
555 { SystemZ::C2 },
556 { SystemZ::C3 },
557 { SystemZ::C4 },
558 { SystemZ::C5 },
559 { SystemZ::C6 },
560 { SystemZ::C7 },
561 { SystemZ::C8 },
562 { SystemZ::C9 },
563 { SystemZ::C10 },
564 { SystemZ::C11 },
565 { SystemZ::C12 },
566 { SystemZ::C13 },
567 { SystemZ::C14 },
568 { SystemZ::C15 },
569 { SystemZ::F0H },
570 { SystemZ::F1H },
571 { SystemZ::F2H },
572 { SystemZ::F3H },
573 { SystemZ::F4H },
574 { SystemZ::F5H },
575 { SystemZ::F6H },
576 { SystemZ::F7H },
577 { SystemZ::F8H },
578 { SystemZ::F9H },
579 { SystemZ::F10H },
580 { SystemZ::F11H },
581 { SystemZ::F12H },
582 { SystemZ::F13H },
583 { SystemZ::F14H },
584 { SystemZ::F15H },
585 { SystemZ::F16H },
586 { SystemZ::F17H },
587 { SystemZ::F18H },
588 { SystemZ::F19H },
589 { SystemZ::F20H },
590 { SystemZ::F21H },
591 { SystemZ::F22H },
592 { SystemZ::F23H },
593 { SystemZ::F24H },
594 { SystemZ::F25H },
595 { SystemZ::F26H },
596 { SystemZ::F27H },
597 { SystemZ::F28H },
598 { SystemZ::F29H },
599 { SystemZ::F30H },
600 { SystemZ::F31H },
601 { SystemZ::R0L },
602 { SystemZ::R0H },
603 { SystemZ::R1L },
604 { SystemZ::R1H },
605 { SystemZ::R2L },
606 { SystemZ::R2H },
607 { SystemZ::R3L },
608 { SystemZ::R3H },
609 { SystemZ::R4L },
610 { SystemZ::R4H },
611 { SystemZ::R5L },
612 { SystemZ::R5H },
613 { SystemZ::R6L },
614 { SystemZ::R6H },
615 { SystemZ::R7L },
616 { SystemZ::R7H },
617 { SystemZ::R8L },
618 { SystemZ::R8H },
619 { SystemZ::R9L },
620 { SystemZ::R9H },
621 { SystemZ::R10L },
622 { SystemZ::R10H },
623 { SystemZ::R11L },
624 { SystemZ::R11H },
625 { SystemZ::R12L },
626 { SystemZ::R12H },
627 { SystemZ::R13L },
628 { SystemZ::R13H },
629 { SystemZ::R14L },
630 { SystemZ::R14H },
631 { SystemZ::R15L },
632 { SystemZ::R15H },
633};
634
635namespace { // Register classes...
636 // VR16Bit Register Class...
637 const MCPhysReg VR16Bit[] = {
638 SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F16H, SystemZ::F17H, SystemZ::F18H, SystemZ::F19H, SystemZ::F20H, SystemZ::F21H, SystemZ::F22H, SystemZ::F23H, SystemZ::F24H, SystemZ::F25H, SystemZ::F26H, SystemZ::F27H, SystemZ::F28H, SystemZ::F29H, SystemZ::F30H, SystemZ::F31H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H,
639 };
640
641 // VR16Bit Bit set.
642 const uint8_t VR16BitBits[] = {
643 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
644 };
645
646 // FP16Bit Register Class...
647 const MCPhysReg FP16Bit[] = {
648 SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H,
649 };
650
651 // FP16Bit Bit set.
652 const uint8_t FP16BitBits[] = {
653 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
654 };
655
656 // GRX32Bit Register Class...
657 const MCPhysReg GRX32Bit[] = {
658 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15L, SystemZ::R15H, SystemZ::R14L, SystemZ::R14H, SystemZ::R13L, SystemZ::R13H, SystemZ::R12L, SystemZ::R12H, SystemZ::R11L, SystemZ::R11H, SystemZ::R10L, SystemZ::R10H, SystemZ::R9L, SystemZ::R9H, SystemZ::R8L, SystemZ::R8H, SystemZ::R7L, SystemZ::R7H, SystemZ::R6L, SystemZ::R6H,
659 };
660
661 // GRX32Bit Bit set.
662 const uint8_t GRX32BitBits[] = {
663 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
664 };
665
666 // VR32Bit Register Class...
667 const MCPhysReg VR32Bit[] = {
668 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
669 };
670
671 // VR32Bit Bit set.
672 const uint8_t VR32BitBits[] = {
673 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
674 };
675
676 // AR32Bit Register Class...
677 const MCPhysReg AR32Bit[] = {
678 SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3, SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7, SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11, SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15,
679 };
680
681 // AR32Bit Bit set.
682 const uint8_t AR32BitBits[] = {
683 0xf8, 0xff, 0x07,
684 };
685
686 // FP32Bit Register Class...
687 const MCPhysReg FP32Bit[] = {
688 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
689 };
690
691 // FP32Bit Bit set.
692 const uint8_t FP32BitBits[] = {
693 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
694 };
695
696 // GR32Bit Register Class...
697 const MCPhysReg GR32Bit[] = {
698 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L,
699 };
700
701 // GR32Bit Bit set.
702 const uint8_t GR32BitBits[] = {
703 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
704 };
705
706 // GRH32Bit Register Class...
707 const MCPhysReg GRH32Bit[] = {
708 SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15H, SystemZ::R14H, SystemZ::R13H, SystemZ::R12H, SystemZ::R11H, SystemZ::R10H, SystemZ::R9H, SystemZ::R8H, SystemZ::R7H, SystemZ::R6H,
709 };
710
711 // GRH32Bit Bit set.
712 const uint8_t GRH32BitBits[] = {
713 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
714 };
715
716 // ADDR32Bit Register Class...
717 const MCPhysReg ADDR32Bit[] = {
718 SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L,
719 };
720
721 // ADDR32Bit Bit set.
722 const uint8_t ADDR32BitBits[] = {
723 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
724 };
725
726 // CCR Register Class...
727 const MCPhysReg CCR[] = {
728 SystemZ::CC,
729 };
730
731 // CCR Bit set.
732 const uint8_t CCRBits[] = {
733 0x02,
734 };
735
736 // FPCRegs Register Class...
737 const MCPhysReg FPCRegs[] = {
738 SystemZ::FPC,
739 };
740
741 // FPCRegs Bit set.
742 const uint8_t FPCRegsBits[] = {
743 0x04,
744 };
745
746 // AnyRegBit Register Class...
747 const MCPhysReg AnyRegBit[] = {
748 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
749 };
750
751 // AnyRegBit Bit set.
752 const uint8_t AnyRegBitBits[] = {
753 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
754 };
755
756 // AnyRegBit_with_subreg_h16 Register Class...
757 const MCPhysReg AnyRegBit_with_subreg_h16[] = {
758 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
759 };
760
761 // AnyRegBit_with_subreg_h16 Bit set.
762 const uint8_t AnyRegBit_with_subreg_h16Bits[] = {
763 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, 0x07,
764 };
765
766 // VR64Bit Register Class...
767 const MCPhysReg VR64Bit[] = {
768 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
769 };
770
771 // VR64Bit Bit set.
772 const uint8_t VR64BitBits[] = {
773 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
774 };
775
776 // AnyRegBit_with_subreg_h64 Register Class...
777 const MCPhysReg AnyRegBit_with_subreg_h64[] = {
778 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
779 };
780
781 // AnyRegBit_with_subreg_h64 Bit set.
782 const uint8_t AnyRegBit_with_subreg_h64Bits[] = {
783 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
784 };
785
786 // CR64Bit Register Class...
787 const MCPhysReg CR64Bit[] = {
788 SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3, SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7, SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11, SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15,
789 };
790
791 // CR64Bit Bit set.
792 const uint8_t CR64BitBits[] = {
793 0x00, 0x00, 0xf8, 0xff, 0x07,
794 };
795
796 // FP64Bit Register Class...
797 const MCPhysReg FP64Bit[] = {
798 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
799 };
800
801 // FP64Bit Bit set.
802 const uint8_t FP64BitBits[] = {
803 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
804 };
805
806 // GR64Bit Register Class...
807 const MCPhysReg GR64Bit[] = {
808 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D,
809 };
810
811 // GR64Bit Bit set.
812 const uint8_t GR64BitBits[] = {
813 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
814 };
815
816 // ADDR64Bit Register Class...
817 const MCPhysReg ADDR64Bit[] = {
818 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D,
819 };
820
821 // ADDR64Bit Bit set.
822 const uint8_t ADDR64BitBits[] = {
823 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
824 };
825
826 // VR128Bit Register Class...
827 const MCPhysReg VR128Bit[] = {
828 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
829 };
830
831 // VR128Bit Bit set.
832 const uint8_t VR128BitBits[] = {
833 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
834 };
835
836 // VF128Bit Register Class...
837 const MCPhysReg VF128Bit[] = {
838 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
839 };
840
841 // VF128Bit Bit set.
842 const uint8_t VF128BitBits[] = {
843 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
844 };
845
846 // FP128Bit Register Class...
847 const MCPhysReg FP128Bit[] = {
848 SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q,
849 };
850
851 // FP128Bit Bit set.
852 const uint8_t FP128BitBits[] = {
853 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
854 };
855
856 // GR128Bit Register Class...
857 const MCPhysReg GR128Bit[] = {
858 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q,
859 };
860
861 // GR128Bit Bit set.
862 const uint8_t GR128BitBits[] = {
863 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
864 };
865
866 // ADDR128Bit Register Class...
867 const MCPhysReg ADDR128Bit[] = {
868 SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q,
869 };
870
871 // ADDR128Bit Bit set.
872 const uint8_t ADDR128BitBits[] = {
873 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
874 };
875
876} // end anonymous namespace
877
878
879#ifdef __GNUC__
880#pragma GCC diagnostic push
881#pragma GCC diagnostic ignored "-Woverlength-strings"
882#endif
883extern const char SystemZRegClassStrings[] = {
884 /* 0 */ "AnyRegBit_with_subreg_h64\000"
885 /* 26 */ "AnyRegBit_with_subreg_h16\000"
886 /* 52 */ "CCR\000"
887 /* 56 */ "FPCRegs\000"
888 /* 64 */ "GRH32Bit\000"
889 /* 73 */ "FP32Bit\000"
890 /* 81 */ "AR32Bit\000"
891 /* 89 */ "ADDR32Bit\000"
892 /* 99 */ "GR32Bit\000"
893 /* 107 */ "VR32Bit\000"
894 /* 115 */ "GRX32Bit\000"
895 /* 124 */ "FP64Bit\000"
896 /* 132 */ "CR64Bit\000"
897 /* 140 */ "ADDR64Bit\000"
898 /* 150 */ "GR64Bit\000"
899 /* 158 */ "VR64Bit\000"
900 /* 166 */ "FP16Bit\000"
901 /* 174 */ "VR16Bit\000"
902 /* 182 */ "VF128Bit\000"
903 /* 191 */ "FP128Bit\000"
904 /* 200 */ "ADDR128Bit\000"
905 /* 211 */ "GR128Bit\000"
906 /* 220 */ "VR128Bit\000"
907 /* 229 */ "AnyRegBit\000"
908};
909#ifdef __GNUC__
910#pragma GCC diagnostic pop
911#endif
912
913extern const MCRegisterClass SystemZMCRegisterClasses[] = {
914 { .RegsBegin: VR16Bit, .RegSet: VR16BitBits, .NameIdx: 174, .RegsSize: 32, .RegSetSize: sizeof(VR16BitBits), .ID: SystemZ::VR16BitRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
915 { .RegsBegin: FP16Bit, .RegSet: FP16BitBits, .NameIdx: 166, .RegsSize: 16, .RegSetSize: sizeof(FP16BitBits), .ID: SystemZ::FP16BitRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
916 { .RegsBegin: GRX32Bit, .RegSet: GRX32BitBits, .NameIdx: 115, .RegsSize: 32, .RegSetSize: sizeof(GRX32BitBits), .ID: SystemZ::GRX32BitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
917 { .RegsBegin: VR32Bit, .RegSet: VR32BitBits, .NameIdx: 107, .RegsSize: 32, .RegSetSize: sizeof(VR32BitBits), .ID: SystemZ::VR32BitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
918 { .RegsBegin: AR32Bit, .RegSet: AR32BitBits, .NameIdx: 81, .RegsSize: 16, .RegSetSize: sizeof(AR32BitBits), .ID: SystemZ::AR32BitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
919 { .RegsBegin: FP32Bit, .RegSet: FP32BitBits, .NameIdx: 73, .RegsSize: 16, .RegSetSize: sizeof(FP32BitBits), .ID: SystemZ::FP32BitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
920 { .RegsBegin: GR32Bit, .RegSet: GR32BitBits, .NameIdx: 99, .RegsSize: 16, .RegSetSize: sizeof(GR32BitBits), .ID: SystemZ::GR32BitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
921 { .RegsBegin: GRH32Bit, .RegSet: GRH32BitBits, .NameIdx: 64, .RegsSize: 16, .RegSetSize: sizeof(GRH32BitBits), .ID: SystemZ::GRH32BitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
922 { .RegsBegin: ADDR32Bit, .RegSet: ADDR32BitBits, .NameIdx: 89, .RegsSize: 15, .RegSetSize: sizeof(ADDR32BitBits), .ID: SystemZ::ADDR32BitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
923 { .RegsBegin: CCR, .RegSet: CCRBits, .NameIdx: 52, .RegsSize: 1, .RegSetSize: sizeof(CCRBits), .ID: SystemZ::CCRRegClassID, .RegSizeInBits: 32, .CopyCost: 255, .Allocatable: false, .BaseClass: false },
924 { .RegsBegin: FPCRegs, .RegSet: FPCRegsBits, .NameIdx: 56, .RegsSize: 1, .RegSetSize: sizeof(FPCRegsBits), .ID: SystemZ::FPCRegsRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
925 { .RegsBegin: AnyRegBit, .RegSet: AnyRegBitBits, .NameIdx: 229, .RegsSize: 48, .RegSetSize: sizeof(AnyRegBitBits), .ID: SystemZ::AnyRegBitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
926 { .RegsBegin: AnyRegBit_with_subreg_h16, .RegSet: AnyRegBit_with_subreg_h16Bits, .NameIdx: 26, .RegsSize: 32, .RegSetSize: sizeof(AnyRegBit_with_subreg_h16Bits), .ID: SystemZ::AnyRegBit_with_subreg_h16RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
927 { .RegsBegin: VR64Bit, .RegSet: VR64BitBits, .NameIdx: 158, .RegsSize: 32, .RegSetSize: sizeof(VR64BitBits), .ID: SystemZ::VR64BitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
928 { .RegsBegin: AnyRegBit_with_subreg_h64, .RegSet: AnyRegBit_with_subreg_h64Bits, .NameIdx: 0, .RegsSize: 16, .RegSetSize: sizeof(AnyRegBit_with_subreg_h64Bits), .ID: SystemZ::AnyRegBit_with_subreg_h64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
929 { .RegsBegin: CR64Bit, .RegSet: CR64BitBits, .NameIdx: 132, .RegsSize: 16, .RegSetSize: sizeof(CR64BitBits), .ID: SystemZ::CR64BitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
930 { .RegsBegin: FP64Bit, .RegSet: FP64BitBits, .NameIdx: 124, .RegsSize: 16, .RegSetSize: sizeof(FP64BitBits), .ID: SystemZ::FP64BitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
931 { .RegsBegin: GR64Bit, .RegSet: GR64BitBits, .NameIdx: 150, .RegsSize: 16, .RegSetSize: sizeof(GR64BitBits), .ID: SystemZ::GR64BitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
932 { .RegsBegin: ADDR64Bit, .RegSet: ADDR64BitBits, .NameIdx: 140, .RegsSize: 15, .RegSetSize: sizeof(ADDR64BitBits), .ID: SystemZ::ADDR64BitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
933 { .RegsBegin: VR128Bit, .RegSet: VR128BitBits, .NameIdx: 220, .RegsSize: 32, .RegSetSize: sizeof(VR128BitBits), .ID: SystemZ::VR128BitRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
934 { .RegsBegin: VF128Bit, .RegSet: VF128BitBits, .NameIdx: 182, .RegsSize: 16, .RegSetSize: sizeof(VF128BitBits), .ID: SystemZ::VF128BitRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
935 { .RegsBegin: FP128Bit, .RegSet: FP128BitBits, .NameIdx: 191, .RegsSize: 8, .RegSetSize: sizeof(FP128BitBits), .ID: SystemZ::FP128BitRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
936 { .RegsBegin: GR128Bit, .RegSet: GR128BitBits, .NameIdx: 211, .RegsSize: 8, .RegSetSize: sizeof(GR128BitBits), .ID: SystemZ::GR128BitRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
937 { .RegsBegin: ADDR128Bit, .RegSet: ADDR128BitBits, .NameIdx: 200, .RegsSize: 7, .RegSetSize: sizeof(ADDR128BitBits), .ID: SystemZ::ADDR128BitRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
938};
939
940// SystemZ Dwarf<->LLVM register mappings.
941extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[] = {
942 { .FromReg: 0U, .ToReg: SystemZ::R0D },
943 { .FromReg: 1U, .ToReg: SystemZ::R1D },
944 { .FromReg: 2U, .ToReg: SystemZ::R2D },
945 { .FromReg: 3U, .ToReg: SystemZ::R3D },
946 { .FromReg: 4U, .ToReg: SystemZ::R4D },
947 { .FromReg: 5U, .ToReg: SystemZ::R5D },
948 { .FromReg: 6U, .ToReg: SystemZ::R6D },
949 { .FromReg: 7U, .ToReg: SystemZ::R7D },
950 { .FromReg: 8U, .ToReg: SystemZ::R8D },
951 { .FromReg: 9U, .ToReg: SystemZ::R9D },
952 { .FromReg: 10U, .ToReg: SystemZ::R10D },
953 { .FromReg: 11U, .ToReg: SystemZ::R11D },
954 { .FromReg: 12U, .ToReg: SystemZ::R12D },
955 { .FromReg: 13U, .ToReg: SystemZ::R13D },
956 { .FromReg: 14U, .ToReg: SystemZ::R14D },
957 { .FromReg: 15U, .ToReg: SystemZ::R15D },
958 { .FromReg: 16U, .ToReg: SystemZ::F0D },
959 { .FromReg: 17U, .ToReg: SystemZ::F2D },
960 { .FromReg: 18U, .ToReg: SystemZ::F4D },
961 { .FromReg: 19U, .ToReg: SystemZ::F6D },
962 { .FromReg: 20U, .ToReg: SystemZ::F1D },
963 { .FromReg: 21U, .ToReg: SystemZ::F3D },
964 { .FromReg: 22U, .ToReg: SystemZ::F5D },
965 { .FromReg: 23U, .ToReg: SystemZ::F7D },
966 { .FromReg: 24U, .ToReg: SystemZ::F8D },
967 { .FromReg: 25U, .ToReg: SystemZ::F10D },
968 { .FromReg: 26U, .ToReg: SystemZ::F12D },
969 { .FromReg: 27U, .ToReg: SystemZ::F14D },
970 { .FromReg: 28U, .ToReg: SystemZ::F9D },
971 { .FromReg: 29U, .ToReg: SystemZ::F11D },
972 { .FromReg: 30U, .ToReg: SystemZ::F13D },
973 { .FromReg: 31U, .ToReg: SystemZ::F15D },
974 { .FromReg: 32U, .ToReg: SystemZ::C0 },
975 { .FromReg: 33U, .ToReg: SystemZ::C1 },
976 { .FromReg: 34U, .ToReg: SystemZ::C2 },
977 { .FromReg: 35U, .ToReg: SystemZ::C3 },
978 { .FromReg: 36U, .ToReg: SystemZ::C4 },
979 { .FromReg: 37U, .ToReg: SystemZ::C5 },
980 { .FromReg: 38U, .ToReg: SystemZ::C6 },
981 { .FromReg: 39U, .ToReg: SystemZ::C7 },
982 { .FromReg: 40U, .ToReg: SystemZ::C8 },
983 { .FromReg: 41U, .ToReg: SystemZ::C9 },
984 { .FromReg: 42U, .ToReg: SystemZ::C10 },
985 { .FromReg: 43U, .ToReg: SystemZ::C11 },
986 { .FromReg: 44U, .ToReg: SystemZ::C12 },
987 { .FromReg: 45U, .ToReg: SystemZ::C13 },
988 { .FromReg: 46U, .ToReg: SystemZ::C14 },
989 { .FromReg: 47U, .ToReg: SystemZ::C15 },
990 { .FromReg: 48U, .ToReg: SystemZ::A0 },
991 { .FromReg: 49U, .ToReg: SystemZ::A1 },
992 { .FromReg: 50U, .ToReg: SystemZ::A2 },
993 { .FromReg: 51U, .ToReg: SystemZ::A3 },
994 { .FromReg: 52U, .ToReg: SystemZ::A4 },
995 { .FromReg: 53U, .ToReg: SystemZ::A5 },
996 { .FromReg: 54U, .ToReg: SystemZ::A6 },
997 { .FromReg: 55U, .ToReg: SystemZ::A7 },
998 { .FromReg: 56U, .ToReg: SystemZ::A8 },
999 { .FromReg: 57U, .ToReg: SystemZ::A9 },
1000 { .FromReg: 58U, .ToReg: SystemZ::A10 },
1001 { .FromReg: 59U, .ToReg: SystemZ::A11 },
1002 { .FromReg: 60U, .ToReg: SystemZ::A12 },
1003 { .FromReg: 61U, .ToReg: SystemZ::A13 },
1004 { .FromReg: 62U, .ToReg: SystemZ::A14 },
1005 { .FromReg: 63U, .ToReg: SystemZ::A15 },
1006 { .FromReg: 68U, .ToReg: SystemZ::F16D },
1007 { .FromReg: 69U, .ToReg: SystemZ::F18D },
1008 { .FromReg: 70U, .ToReg: SystemZ::F20D },
1009 { .FromReg: 71U, .ToReg: SystemZ::F22D },
1010 { .FromReg: 72U, .ToReg: SystemZ::F17D },
1011 { .FromReg: 73U, .ToReg: SystemZ::F19D },
1012 { .FromReg: 74U, .ToReg: SystemZ::F21D },
1013 { .FromReg: 75U, .ToReg: SystemZ::F23D },
1014 { .FromReg: 76U, .ToReg: SystemZ::F24D },
1015 { .FromReg: 77U, .ToReg: SystemZ::F26D },
1016 { .FromReg: 78U, .ToReg: SystemZ::F28D },
1017 { .FromReg: 79U, .ToReg: SystemZ::F30D },
1018 { .FromReg: 80U, .ToReg: SystemZ::F25D },
1019 { .FromReg: 81U, .ToReg: SystemZ::F27D },
1020 { .FromReg: 82U, .ToReg: SystemZ::F29D },
1021 { .FromReg: 83U, .ToReg: SystemZ::F31D },
1022};
1023extern const unsigned SystemZDwarfFlavour0Dwarf2LSize = std::size(SystemZDwarfFlavour0Dwarf2L);
1024
1025extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[] = {
1026 { .FromReg: 0U, .ToReg: SystemZ::R0D },
1027 { .FromReg: 1U, .ToReg: SystemZ::R1D },
1028 { .FromReg: 2U, .ToReg: SystemZ::R2D },
1029 { .FromReg: 3U, .ToReg: SystemZ::R3D },
1030 { .FromReg: 4U, .ToReg: SystemZ::R4D },
1031 { .FromReg: 5U, .ToReg: SystemZ::R5D },
1032 { .FromReg: 6U, .ToReg: SystemZ::R6D },
1033 { .FromReg: 7U, .ToReg: SystemZ::R7D },
1034 { .FromReg: 8U, .ToReg: SystemZ::R8D },
1035 { .FromReg: 9U, .ToReg: SystemZ::R9D },
1036 { .FromReg: 10U, .ToReg: SystemZ::R10D },
1037 { .FromReg: 11U, .ToReg: SystemZ::R11D },
1038 { .FromReg: 12U, .ToReg: SystemZ::R12D },
1039 { .FromReg: 13U, .ToReg: SystemZ::R13D },
1040 { .FromReg: 14U, .ToReg: SystemZ::R14D },
1041 { .FromReg: 15U, .ToReg: SystemZ::R15D },
1042 { .FromReg: 16U, .ToReg: SystemZ::F0D },
1043 { .FromReg: 17U, .ToReg: SystemZ::F2D },
1044 { .FromReg: 18U, .ToReg: SystemZ::F4D },
1045 { .FromReg: 19U, .ToReg: SystemZ::F6D },
1046 { .FromReg: 20U, .ToReg: SystemZ::F1D },
1047 { .FromReg: 21U, .ToReg: SystemZ::F3D },
1048 { .FromReg: 22U, .ToReg: SystemZ::F5D },
1049 { .FromReg: 23U, .ToReg: SystemZ::F7D },
1050 { .FromReg: 24U, .ToReg: SystemZ::F8D },
1051 { .FromReg: 25U, .ToReg: SystemZ::F10D },
1052 { .FromReg: 26U, .ToReg: SystemZ::F12D },
1053 { .FromReg: 27U, .ToReg: SystemZ::F14D },
1054 { .FromReg: 28U, .ToReg: SystemZ::F9D },
1055 { .FromReg: 29U, .ToReg: SystemZ::F11D },
1056 { .FromReg: 30U, .ToReg: SystemZ::F13D },
1057 { .FromReg: 31U, .ToReg: SystemZ::F15D },
1058 { .FromReg: 32U, .ToReg: SystemZ::C0 },
1059 { .FromReg: 33U, .ToReg: SystemZ::C1 },
1060 { .FromReg: 34U, .ToReg: SystemZ::C2 },
1061 { .FromReg: 35U, .ToReg: SystemZ::C3 },
1062 { .FromReg: 36U, .ToReg: SystemZ::C4 },
1063 { .FromReg: 37U, .ToReg: SystemZ::C5 },
1064 { .FromReg: 38U, .ToReg: SystemZ::C6 },
1065 { .FromReg: 39U, .ToReg: SystemZ::C7 },
1066 { .FromReg: 40U, .ToReg: SystemZ::C8 },
1067 { .FromReg: 41U, .ToReg: SystemZ::C9 },
1068 { .FromReg: 42U, .ToReg: SystemZ::C10 },
1069 { .FromReg: 43U, .ToReg: SystemZ::C11 },
1070 { .FromReg: 44U, .ToReg: SystemZ::C12 },
1071 { .FromReg: 45U, .ToReg: SystemZ::C13 },
1072 { .FromReg: 46U, .ToReg: SystemZ::C14 },
1073 { .FromReg: 47U, .ToReg: SystemZ::C15 },
1074 { .FromReg: 48U, .ToReg: SystemZ::A0 },
1075 { .FromReg: 49U, .ToReg: SystemZ::A1 },
1076 { .FromReg: 50U, .ToReg: SystemZ::A2 },
1077 { .FromReg: 51U, .ToReg: SystemZ::A3 },
1078 { .FromReg: 52U, .ToReg: SystemZ::A4 },
1079 { .FromReg: 53U, .ToReg: SystemZ::A5 },
1080 { .FromReg: 54U, .ToReg: SystemZ::A6 },
1081 { .FromReg: 55U, .ToReg: SystemZ::A7 },
1082 { .FromReg: 56U, .ToReg: SystemZ::A8 },
1083 { .FromReg: 57U, .ToReg: SystemZ::A9 },
1084 { .FromReg: 58U, .ToReg: SystemZ::A10 },
1085 { .FromReg: 59U, .ToReg: SystemZ::A11 },
1086 { .FromReg: 60U, .ToReg: SystemZ::A12 },
1087 { .FromReg: 61U, .ToReg: SystemZ::A13 },
1088 { .FromReg: 62U, .ToReg: SystemZ::A14 },
1089 { .FromReg: 63U, .ToReg: SystemZ::A15 },
1090 { .FromReg: 68U, .ToReg: SystemZ::F16D },
1091 { .FromReg: 69U, .ToReg: SystemZ::F18D },
1092 { .FromReg: 70U, .ToReg: SystemZ::F20D },
1093 { .FromReg: 71U, .ToReg: SystemZ::F22D },
1094 { .FromReg: 72U, .ToReg: SystemZ::F17D },
1095 { .FromReg: 73U, .ToReg: SystemZ::F19D },
1096 { .FromReg: 74U, .ToReg: SystemZ::F21D },
1097 { .FromReg: 75U, .ToReg: SystemZ::F23D },
1098 { .FromReg: 76U, .ToReg: SystemZ::F24D },
1099 { .FromReg: 77U, .ToReg: SystemZ::F26D },
1100 { .FromReg: 78U, .ToReg: SystemZ::F28D },
1101 { .FromReg: 79U, .ToReg: SystemZ::F30D },
1102 { .FromReg: 80U, .ToReg: SystemZ::F25D },
1103 { .FromReg: 81U, .ToReg: SystemZ::F27D },
1104 { .FromReg: 82U, .ToReg: SystemZ::F29D },
1105 { .FromReg: 83U, .ToReg: SystemZ::F31D },
1106};
1107extern const unsigned SystemZEHFlavour0Dwarf2LSize = std::size(SystemZEHFlavour0Dwarf2L);
1108
1109extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[] = {
1110 { .FromReg: SystemZ::A0, .ToReg: 48U },
1111 { .FromReg: SystemZ::A1, .ToReg: 49U },
1112 { .FromReg: SystemZ::A2, .ToReg: 50U },
1113 { .FromReg: SystemZ::A3, .ToReg: 51U },
1114 { .FromReg: SystemZ::A4, .ToReg: 52U },
1115 { .FromReg: SystemZ::A5, .ToReg: 53U },
1116 { .FromReg: SystemZ::A6, .ToReg: 54U },
1117 { .FromReg: SystemZ::A7, .ToReg: 55U },
1118 { .FromReg: SystemZ::A8, .ToReg: 56U },
1119 { .FromReg: SystemZ::A9, .ToReg: 57U },
1120 { .FromReg: SystemZ::A10, .ToReg: 58U },
1121 { .FromReg: SystemZ::A11, .ToReg: 59U },
1122 { .FromReg: SystemZ::A12, .ToReg: 60U },
1123 { .FromReg: SystemZ::A13, .ToReg: 61U },
1124 { .FromReg: SystemZ::A14, .ToReg: 62U },
1125 { .FromReg: SystemZ::A15, .ToReg: 63U },
1126 { .FromReg: SystemZ::C0, .ToReg: 32U },
1127 { .FromReg: SystemZ::C1, .ToReg: 33U },
1128 { .FromReg: SystemZ::C2, .ToReg: 34U },
1129 { .FromReg: SystemZ::C3, .ToReg: 35U },
1130 { .FromReg: SystemZ::C4, .ToReg: 36U },
1131 { .FromReg: SystemZ::C5, .ToReg: 37U },
1132 { .FromReg: SystemZ::C6, .ToReg: 38U },
1133 { .FromReg: SystemZ::C7, .ToReg: 39U },
1134 { .FromReg: SystemZ::C8, .ToReg: 40U },
1135 { .FromReg: SystemZ::C9, .ToReg: 41U },
1136 { .FromReg: SystemZ::C10, .ToReg: 42U },
1137 { .FromReg: SystemZ::C11, .ToReg: 43U },
1138 { .FromReg: SystemZ::C12, .ToReg: 44U },
1139 { .FromReg: SystemZ::C13, .ToReg: 45U },
1140 { .FromReg: SystemZ::C14, .ToReg: 46U },
1141 { .FromReg: SystemZ::C15, .ToReg: 47U },
1142 { .FromReg: SystemZ::V0, .ToReg: 16U },
1143 { .FromReg: SystemZ::V1, .ToReg: 20U },
1144 { .FromReg: SystemZ::V2, .ToReg: 17U },
1145 { .FromReg: SystemZ::V3, .ToReg: 21U },
1146 { .FromReg: SystemZ::V4, .ToReg: 18U },
1147 { .FromReg: SystemZ::V5, .ToReg: 22U },
1148 { .FromReg: SystemZ::V6, .ToReg: 19U },
1149 { .FromReg: SystemZ::V7, .ToReg: 23U },
1150 { .FromReg: SystemZ::V8, .ToReg: 24U },
1151 { .FromReg: SystemZ::V9, .ToReg: 28U },
1152 { .FromReg: SystemZ::V10, .ToReg: 25U },
1153 { .FromReg: SystemZ::V11, .ToReg: 29U },
1154 { .FromReg: SystemZ::V12, .ToReg: 26U },
1155 { .FromReg: SystemZ::V13, .ToReg: 30U },
1156 { .FromReg: SystemZ::V14, .ToReg: 27U },
1157 { .FromReg: SystemZ::V15, .ToReg: 31U },
1158 { .FromReg: SystemZ::V16, .ToReg: 68U },
1159 { .FromReg: SystemZ::V17, .ToReg: 72U },
1160 { .FromReg: SystemZ::V18, .ToReg: 69U },
1161 { .FromReg: SystemZ::V19, .ToReg: 73U },
1162 { .FromReg: SystemZ::V20, .ToReg: 70U },
1163 { .FromReg: SystemZ::V21, .ToReg: 74U },
1164 { .FromReg: SystemZ::V22, .ToReg: 71U },
1165 { .FromReg: SystemZ::V23, .ToReg: 75U },
1166 { .FromReg: SystemZ::V24, .ToReg: 76U },
1167 { .FromReg: SystemZ::V25, .ToReg: 80U },
1168 { .FromReg: SystemZ::V26, .ToReg: 77U },
1169 { .FromReg: SystemZ::V27, .ToReg: 81U },
1170 { .FromReg: SystemZ::V28, .ToReg: 78U },
1171 { .FromReg: SystemZ::V29, .ToReg: 82U },
1172 { .FromReg: SystemZ::V30, .ToReg: 79U },
1173 { .FromReg: SystemZ::V31, .ToReg: 83U },
1174 { .FromReg: SystemZ::F0D, .ToReg: 16U },
1175 { .FromReg: SystemZ::F1D, .ToReg: 20U },
1176 { .FromReg: SystemZ::F2D, .ToReg: 17U },
1177 { .FromReg: SystemZ::F3D, .ToReg: 21U },
1178 { .FromReg: SystemZ::F4D, .ToReg: 18U },
1179 { .FromReg: SystemZ::F5D, .ToReg: 22U },
1180 { .FromReg: SystemZ::F6D, .ToReg: 19U },
1181 { .FromReg: SystemZ::F7D, .ToReg: 23U },
1182 { .FromReg: SystemZ::F8D, .ToReg: 24U },
1183 { .FromReg: SystemZ::F9D, .ToReg: 28U },
1184 { .FromReg: SystemZ::F10D, .ToReg: 25U },
1185 { .FromReg: SystemZ::F11D, .ToReg: 29U },
1186 { .FromReg: SystemZ::F12D, .ToReg: 26U },
1187 { .FromReg: SystemZ::F13D, .ToReg: 30U },
1188 { .FromReg: SystemZ::F14D, .ToReg: 27U },
1189 { .FromReg: SystemZ::F15D, .ToReg: 31U },
1190 { .FromReg: SystemZ::F16D, .ToReg: 68U },
1191 { .FromReg: SystemZ::F17D, .ToReg: 72U },
1192 { .FromReg: SystemZ::F18D, .ToReg: 69U },
1193 { .FromReg: SystemZ::F19D, .ToReg: 73U },
1194 { .FromReg: SystemZ::F20D, .ToReg: 70U },
1195 { .FromReg: SystemZ::F21D, .ToReg: 74U },
1196 { .FromReg: SystemZ::F22D, .ToReg: 71U },
1197 { .FromReg: SystemZ::F23D, .ToReg: 75U },
1198 { .FromReg: SystemZ::F24D, .ToReg: 76U },
1199 { .FromReg: SystemZ::F25D, .ToReg: 80U },
1200 { .FromReg: SystemZ::F26D, .ToReg: 77U },
1201 { .FromReg: SystemZ::F27D, .ToReg: 81U },
1202 { .FromReg: SystemZ::F28D, .ToReg: 78U },
1203 { .FromReg: SystemZ::F29D, .ToReg: 82U },
1204 { .FromReg: SystemZ::F30D, .ToReg: 79U },
1205 { .FromReg: SystemZ::F31D, .ToReg: 83U },
1206 { .FromReg: SystemZ::R0D, .ToReg: 0U },
1207 { .FromReg: SystemZ::R1D, .ToReg: 1U },
1208 { .FromReg: SystemZ::R2D, .ToReg: 2U },
1209 { .FromReg: SystemZ::R3D, .ToReg: 3U },
1210 { .FromReg: SystemZ::R4D, .ToReg: 4U },
1211 { .FromReg: SystemZ::R5D, .ToReg: 5U },
1212 { .FromReg: SystemZ::R6D, .ToReg: 6U },
1213 { .FromReg: SystemZ::R7D, .ToReg: 7U },
1214 { .FromReg: SystemZ::R8D, .ToReg: 8U },
1215 { .FromReg: SystemZ::R9D, .ToReg: 9U },
1216 { .FromReg: SystemZ::R10D, .ToReg: 10U },
1217 { .FromReg: SystemZ::R11D, .ToReg: 11U },
1218 { .FromReg: SystemZ::R12D, .ToReg: 12U },
1219 { .FromReg: SystemZ::R13D, .ToReg: 13U },
1220 { .FromReg: SystemZ::R14D, .ToReg: 14U },
1221 { .FromReg: SystemZ::R15D, .ToReg: 15U },
1222};
1223extern const unsigned SystemZDwarfFlavour0L2DwarfSize = std::size(SystemZDwarfFlavour0L2Dwarf);
1224
1225extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[] = {
1226 { .FromReg: SystemZ::A0, .ToReg: 48U },
1227 { .FromReg: SystemZ::A1, .ToReg: 49U },
1228 { .FromReg: SystemZ::A2, .ToReg: 50U },
1229 { .FromReg: SystemZ::A3, .ToReg: 51U },
1230 { .FromReg: SystemZ::A4, .ToReg: 52U },
1231 { .FromReg: SystemZ::A5, .ToReg: 53U },
1232 { .FromReg: SystemZ::A6, .ToReg: 54U },
1233 { .FromReg: SystemZ::A7, .ToReg: 55U },
1234 { .FromReg: SystemZ::A8, .ToReg: 56U },
1235 { .FromReg: SystemZ::A9, .ToReg: 57U },
1236 { .FromReg: SystemZ::A10, .ToReg: 58U },
1237 { .FromReg: SystemZ::A11, .ToReg: 59U },
1238 { .FromReg: SystemZ::A12, .ToReg: 60U },
1239 { .FromReg: SystemZ::A13, .ToReg: 61U },
1240 { .FromReg: SystemZ::A14, .ToReg: 62U },
1241 { .FromReg: SystemZ::A15, .ToReg: 63U },
1242 { .FromReg: SystemZ::C0, .ToReg: 32U },
1243 { .FromReg: SystemZ::C1, .ToReg: 33U },
1244 { .FromReg: SystemZ::C2, .ToReg: 34U },
1245 { .FromReg: SystemZ::C3, .ToReg: 35U },
1246 { .FromReg: SystemZ::C4, .ToReg: 36U },
1247 { .FromReg: SystemZ::C5, .ToReg: 37U },
1248 { .FromReg: SystemZ::C6, .ToReg: 38U },
1249 { .FromReg: SystemZ::C7, .ToReg: 39U },
1250 { .FromReg: SystemZ::C8, .ToReg: 40U },
1251 { .FromReg: SystemZ::C9, .ToReg: 41U },
1252 { .FromReg: SystemZ::C10, .ToReg: 42U },
1253 { .FromReg: SystemZ::C11, .ToReg: 43U },
1254 { .FromReg: SystemZ::C12, .ToReg: 44U },
1255 { .FromReg: SystemZ::C13, .ToReg: 45U },
1256 { .FromReg: SystemZ::C14, .ToReg: 46U },
1257 { .FromReg: SystemZ::C15, .ToReg: 47U },
1258 { .FromReg: SystemZ::V0, .ToReg: 16U },
1259 { .FromReg: SystemZ::V1, .ToReg: 20U },
1260 { .FromReg: SystemZ::V2, .ToReg: 17U },
1261 { .FromReg: SystemZ::V3, .ToReg: 21U },
1262 { .FromReg: SystemZ::V4, .ToReg: 18U },
1263 { .FromReg: SystemZ::V5, .ToReg: 22U },
1264 { .FromReg: SystemZ::V6, .ToReg: 19U },
1265 { .FromReg: SystemZ::V7, .ToReg: 23U },
1266 { .FromReg: SystemZ::V8, .ToReg: 24U },
1267 { .FromReg: SystemZ::V9, .ToReg: 28U },
1268 { .FromReg: SystemZ::V10, .ToReg: 25U },
1269 { .FromReg: SystemZ::V11, .ToReg: 29U },
1270 { .FromReg: SystemZ::V12, .ToReg: 26U },
1271 { .FromReg: SystemZ::V13, .ToReg: 30U },
1272 { .FromReg: SystemZ::V14, .ToReg: 27U },
1273 { .FromReg: SystemZ::V15, .ToReg: 31U },
1274 { .FromReg: SystemZ::V16, .ToReg: 68U },
1275 { .FromReg: SystemZ::V17, .ToReg: 72U },
1276 { .FromReg: SystemZ::V18, .ToReg: 69U },
1277 { .FromReg: SystemZ::V19, .ToReg: 73U },
1278 { .FromReg: SystemZ::V20, .ToReg: 70U },
1279 { .FromReg: SystemZ::V21, .ToReg: 74U },
1280 { .FromReg: SystemZ::V22, .ToReg: 71U },
1281 { .FromReg: SystemZ::V23, .ToReg: 75U },
1282 { .FromReg: SystemZ::V24, .ToReg: 76U },
1283 { .FromReg: SystemZ::V25, .ToReg: 80U },
1284 { .FromReg: SystemZ::V26, .ToReg: 77U },
1285 { .FromReg: SystemZ::V27, .ToReg: 81U },
1286 { .FromReg: SystemZ::V28, .ToReg: 78U },
1287 { .FromReg: SystemZ::V29, .ToReg: 82U },
1288 { .FromReg: SystemZ::V30, .ToReg: 79U },
1289 { .FromReg: SystemZ::V31, .ToReg: 83U },
1290 { .FromReg: SystemZ::F0D, .ToReg: 16U },
1291 { .FromReg: SystemZ::F1D, .ToReg: 20U },
1292 { .FromReg: SystemZ::F2D, .ToReg: 17U },
1293 { .FromReg: SystemZ::F3D, .ToReg: 21U },
1294 { .FromReg: SystemZ::F4D, .ToReg: 18U },
1295 { .FromReg: SystemZ::F5D, .ToReg: 22U },
1296 { .FromReg: SystemZ::F6D, .ToReg: 19U },
1297 { .FromReg: SystemZ::F7D, .ToReg: 23U },
1298 { .FromReg: SystemZ::F8D, .ToReg: 24U },
1299 { .FromReg: SystemZ::F9D, .ToReg: 28U },
1300 { .FromReg: SystemZ::F10D, .ToReg: 25U },
1301 { .FromReg: SystemZ::F11D, .ToReg: 29U },
1302 { .FromReg: SystemZ::F12D, .ToReg: 26U },
1303 { .FromReg: SystemZ::F13D, .ToReg: 30U },
1304 { .FromReg: SystemZ::F14D, .ToReg: 27U },
1305 { .FromReg: SystemZ::F15D, .ToReg: 31U },
1306 { .FromReg: SystemZ::F16D, .ToReg: 68U },
1307 { .FromReg: SystemZ::F17D, .ToReg: 72U },
1308 { .FromReg: SystemZ::F18D, .ToReg: 69U },
1309 { .FromReg: SystemZ::F19D, .ToReg: 73U },
1310 { .FromReg: SystemZ::F20D, .ToReg: 70U },
1311 { .FromReg: SystemZ::F21D, .ToReg: 74U },
1312 { .FromReg: SystemZ::F22D, .ToReg: 71U },
1313 { .FromReg: SystemZ::F23D, .ToReg: 75U },
1314 { .FromReg: SystemZ::F24D, .ToReg: 76U },
1315 { .FromReg: SystemZ::F25D, .ToReg: 80U },
1316 { .FromReg: SystemZ::F26D, .ToReg: 77U },
1317 { .FromReg: SystemZ::F27D, .ToReg: 81U },
1318 { .FromReg: SystemZ::F28D, .ToReg: 78U },
1319 { .FromReg: SystemZ::F29D, .ToReg: 82U },
1320 { .FromReg: SystemZ::F30D, .ToReg: 79U },
1321 { .FromReg: SystemZ::F31D, .ToReg: 83U },
1322 { .FromReg: SystemZ::R0D, .ToReg: 0U },
1323 { .FromReg: SystemZ::R1D, .ToReg: 1U },
1324 { .FromReg: SystemZ::R2D, .ToReg: 2U },
1325 { .FromReg: SystemZ::R3D, .ToReg: 3U },
1326 { .FromReg: SystemZ::R4D, .ToReg: 4U },
1327 { .FromReg: SystemZ::R5D, .ToReg: 5U },
1328 { .FromReg: SystemZ::R6D, .ToReg: 6U },
1329 { .FromReg: SystemZ::R7D, .ToReg: 7U },
1330 { .FromReg: SystemZ::R8D, .ToReg: 8U },
1331 { .FromReg: SystemZ::R9D, .ToReg: 9U },
1332 { .FromReg: SystemZ::R10D, .ToReg: 10U },
1333 { .FromReg: SystemZ::R11D, .ToReg: 11U },
1334 { .FromReg: SystemZ::R12D, .ToReg: 12U },
1335 { .FromReg: SystemZ::R13D, .ToReg: 13U },
1336 { .FromReg: SystemZ::R14D, .ToReg: 14U },
1337 { .FromReg: SystemZ::R15D, .ToReg: 15U },
1338};
1339extern const unsigned SystemZEHFlavour0L2DwarfSize = std::size(SystemZEHFlavour0L2Dwarf);
1340
1341extern const uint16_t SystemZRegEncodingTable[] = {
1342 0,
1343 0,
1344 0,
1345 0,
1346 1,
1347 2,
1348 3,
1349 4,
1350 5,
1351 6,
1352 7,
1353 8,
1354 9,
1355 10,
1356 11,
1357 12,
1358 13,
1359 14,
1360 15,
1361 0,
1362 1,
1363 2,
1364 3,
1365 4,
1366 5,
1367 6,
1368 7,
1369 8,
1370 9,
1371 10,
1372 11,
1373 12,
1374 13,
1375 14,
1376 15,
1377 0,
1378 1,
1379 2,
1380 3,
1381 4,
1382 5,
1383 6,
1384 7,
1385 8,
1386 9,
1387 10,
1388 11,
1389 12,
1390 13,
1391 14,
1392 15,
1393 16,
1394 17,
1395 18,
1396 19,
1397 20,
1398 21,
1399 22,
1400 23,
1401 24,
1402 25,
1403 26,
1404 27,
1405 28,
1406 29,
1407 30,
1408 31,
1409 0,
1410 1,
1411 2,
1412 3,
1413 4,
1414 5,
1415 6,
1416 7,
1417 8,
1418 9,
1419 10,
1420 11,
1421 12,
1422 13,
1423 14,
1424 15,
1425 16,
1426 17,
1427 18,
1428 19,
1429 20,
1430 21,
1431 22,
1432 23,
1433 24,
1434 25,
1435 26,
1436 27,
1437 28,
1438 29,
1439 30,
1440 31,
1441 0,
1442 1,
1443 2,
1444 3,
1445 4,
1446 5,
1447 6,
1448 7,
1449 8,
1450 9,
1451 10,
1452 11,
1453 12,
1454 13,
1455 14,
1456 15,
1457 16,
1458 17,
1459 18,
1460 19,
1461 20,
1462 21,
1463 22,
1464 23,
1465 24,
1466 25,
1467 26,
1468 27,
1469 28,
1470 29,
1471 30,
1472 31,
1473 0,
1474 1,
1475 4,
1476 5,
1477 8,
1478 9,
1479 12,
1480 13,
1481 0,
1482 1,
1483 2,
1484 3,
1485 4,
1486 5,
1487 6,
1488 7,
1489 8,
1490 9,
1491 10,
1492 11,
1493 12,
1494 13,
1495 14,
1496 15,
1497 16,
1498 17,
1499 18,
1500 19,
1501 20,
1502 21,
1503 22,
1504 23,
1505 24,
1506 25,
1507 26,
1508 27,
1509 28,
1510 29,
1511 30,
1512 31,
1513 0,
1514 1,
1515 2,
1516 3,
1517 4,
1518 5,
1519 6,
1520 7,
1521 8,
1522 9,
1523 10,
1524 11,
1525 12,
1526 13,
1527 14,
1528 15,
1529 0,
1530 1,
1531 2,
1532 3,
1533 4,
1534 5,
1535 6,
1536 7,
1537 8,
1538 9,
1539 10,
1540 11,
1541 12,
1542 13,
1543 14,
1544 15,
1545 0,
1546 1,
1547 2,
1548 3,
1549 4,
1550 5,
1551 6,
1552 7,
1553 8,
1554 9,
1555 10,
1556 11,
1557 12,
1558 13,
1559 14,
1560 15,
1561 0,
1562 2,
1563 4,
1564 6,
1565 8,
1566 10,
1567 12,
1568 14,
1569};
1570static inline void InitSystemZMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1571 RI->InitMCRegisterInfo(D: SystemZRegDesc, NR: 227, RA, PC, C: SystemZMCRegisterClasses, NC: 24, RURoots: SystemZRegUnitRoots, NRU: 98, DL: SystemZRegDiffLists, RUMS: SystemZLaneMaskLists, Strings: SystemZRegStrings, ClassStrings: SystemZRegClassStrings, SubIndices: SystemZSubRegIdxLists, NumIndices: 9,
1572RET: SystemZRegEncodingTable);
1573
1574 switch (DwarfFlavour) {
1575 default:
1576 llvm_unreachable("Unknown DWARF flavour");
1577 case 0:
1578 RI->mapDwarfRegsToLLVMRegs(Map: SystemZDwarfFlavour0Dwarf2L, Size: SystemZDwarfFlavour0Dwarf2LSize, isEH: false);
1579 break;
1580 }
1581 switch (EHFlavour) {
1582 default:
1583 llvm_unreachable("Unknown DWARF flavour");
1584 case 0:
1585 RI->mapDwarfRegsToLLVMRegs(Map: SystemZEHFlavour0Dwarf2L, Size: SystemZEHFlavour0Dwarf2LSize, isEH: true);
1586 break;
1587 }
1588 switch (DwarfFlavour) {
1589 default:
1590 llvm_unreachable("Unknown DWARF flavour");
1591 case 0:
1592 RI->mapLLVMRegsToDwarfRegs(Map: SystemZDwarfFlavour0L2Dwarf, Size: SystemZDwarfFlavour0L2DwarfSize, isEH: false);
1593 break;
1594 }
1595 switch (EHFlavour) {
1596 default:
1597 llvm_unreachable("Unknown DWARF flavour");
1598 case 0:
1599 RI->mapLLVMRegsToDwarfRegs(Map: SystemZEHFlavour0L2Dwarf, Size: SystemZEHFlavour0L2DwarfSize, isEH: true);
1600 break;
1601 }
1602}
1603
1604} // end namespace llvm
1605
1606