1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t SystemZRegDiffLists[] = {
12 /* 0 */ -64, 72, -40, -30, 72, -40, 0,
13 /* 7 */ -62, 72, -40, -30, 72, -40, 0,
14 /* 14 */ -60, 72, -40, -30, 72, -40, 0,
15 /* 21 */ -58, 72, -40, -30, 72, -40, 0,
16 /* 28 */ 32, 72, -40, 0,
17 /* 32 */ 40, -72, -32, 0,
18 /* 36 */ -48, 32, -16, -15, 32, -16, 0,
19 /* 43 */ -47, 32, -16, -15, 32, -16, 0,
20 /* 50 */ -46, 32, -16, -15, 32, -16, 0,
21 /* 57 */ -45, 32, -16, -15, 32, -16, 0,
22 /* 64 */ -44, 32, -16, -15, 32, -16, 0,
23 /* 71 */ -43, 32, -16, -15, 32, -16, 0,
24 /* 78 */ -42, 32, -16, -15, 32, -16, 0,
25 /* 85 */ -41, 32, -16, -15, 32, -16, 0,
26 /* 92 */ 1, 1, 1, 0,
27 /* 96 */ 2, 0,
28 /* 98 */ -32, 40, 0,
29 /* 101 */ -16, 40, 0,
30 /* 104 */ -32, 41, 0,
31 /* 107 */ -16, 41, 0,
32 /* 110 */ -32, 42, 0,
33 /* 113 */ -16, 42, 0,
34 /* 116 */ -32, 43, 0,
35 /* 119 */ -16, 43, 0,
36 /* 122 */ -32, 44, 0,
37 /* 125 */ -16, 44, 0,
38 /* 128 */ -32, 45, 0,
39 /* 131 */ -16, 45, 0,
40 /* 134 */ -32, 46, 0,
41 /* 137 */ -16, 46, 0,
42 /* 140 */ -32, 47, 0,
43 /* 143 */ -16, 47, 0,
44 /* 146 */ -32, 48, 0,
45 /* 149 */ -16, 48, 0,
46 /* 152 */ 40, -72, -32, 88, 0,
47 /* 157 */ 40, -72, -32, 90, 0,
48 /* 162 */ 40, -72, -32, 92, 0,
49 /* 167 */ 40, -72, -32, 94, 0,
50 /* 172 */ 40, -72, -32, 96, 0,
51};
52
53extern const LaneBitmask SystemZLaneMaskLists[] = {
54 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
55 /* 2 */ LaneBitmask(0x0000000000000003),
56 /* 3 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
57 /* 7 */ LaneBitmask(0x0000000000000003), LaneBitmask(0x000000000000000C),
58 /* 9 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
59};
60
61extern const uint16_t SystemZSubRegIdxLists[] = {
62 /* 0 */ 3, 2, 1,
63 /* 3 */ 4, 2,
64 /* 5 */ 3, 4, 2, 5, 7, 6,
65 /* 11 */ 3, 2, 1, 5, 6, 8,
66};
67
68
69#ifdef __GNUC__
70#pragma GCC diagnostic push
71#pragma GCC diagnostic ignored "-Woverlength-strings"
72#endif
73extern const char SystemZRegStrings[] = {
74 /* 0 */ "A10\000"
75 /* 4 */ "C10\000"
76 /* 8 */ "V10\000"
77 /* 12 */ "V20\000"
78 /* 16 */ "V30\000"
79 /* 20 */ "A0\000"
80 /* 23 */ "C0\000"
81 /* 26 */ "V0\000"
82 /* 29 */ "A11\000"
83 /* 33 */ "C11\000"
84 /* 37 */ "V11\000"
85 /* 41 */ "V21\000"
86 /* 45 */ "V31\000"
87 /* 49 */ "A1\000"
88 /* 52 */ "C1\000"
89 /* 55 */ "V1\000"
90 /* 58 */ "A12\000"
91 /* 62 */ "C12\000"
92 /* 66 */ "V12\000"
93 /* 70 */ "V22\000"
94 /* 74 */ "A2\000"
95 /* 77 */ "C2\000"
96 /* 80 */ "V2\000"
97 /* 83 */ "A13\000"
98 /* 87 */ "C13\000"
99 /* 91 */ "V13\000"
100 /* 95 */ "V23\000"
101 /* 99 */ "A3\000"
102 /* 102 */ "C3\000"
103 /* 105 */ "V3\000"
104 /* 108 */ "A14\000"
105 /* 112 */ "C14\000"
106 /* 116 */ "V14\000"
107 /* 120 */ "V24\000"
108 /* 124 */ "A4\000"
109 /* 127 */ "C4\000"
110 /* 130 */ "V4\000"
111 /* 133 */ "A15\000"
112 /* 137 */ "C15\000"
113 /* 141 */ "V15\000"
114 /* 145 */ "V25\000"
115 /* 149 */ "A5\000"
116 /* 152 */ "C5\000"
117 /* 155 */ "V5\000"
118 /* 158 */ "V16\000"
119 /* 162 */ "V26\000"
120 /* 166 */ "A6\000"
121 /* 169 */ "C6\000"
122 /* 172 */ "V6\000"
123 /* 175 */ "V17\000"
124 /* 179 */ "V27\000"
125 /* 183 */ "A7\000"
126 /* 186 */ "C7\000"
127 /* 189 */ "V7\000"
128 /* 192 */ "V18\000"
129 /* 196 */ "V28\000"
130 /* 200 */ "A8\000"
131 /* 203 */ "C8\000"
132 /* 206 */ "V8\000"
133 /* 209 */ "V19\000"
134 /* 213 */ "V29\000"
135 /* 217 */ "A9\000"
136 /* 220 */ "C9\000"
137 /* 223 */ "V9\000"
138 /* 226 */ "CC\000"
139 /* 229 */ "FPC\000"
140 /* 233 */ "F10D\000"
141 /* 238 */ "R10D\000"
142 /* 243 */ "F20D\000"
143 /* 248 */ "F30D\000"
144 /* 253 */ "F0D\000"
145 /* 257 */ "R0D\000"
146 /* 261 */ "F11D\000"
147 /* 266 */ "R11D\000"
148 /* 271 */ "F21D\000"
149 /* 276 */ "F31D\000"
150 /* 281 */ "F1D\000"
151 /* 285 */ "R1D\000"
152 /* 289 */ "F12D\000"
153 /* 294 */ "R12D\000"
154 /* 299 */ "F22D\000"
155 /* 304 */ "F2D\000"
156 /* 308 */ "R2D\000"
157 /* 312 */ "F13D\000"
158 /* 317 */ "R13D\000"
159 /* 322 */ "F23D\000"
160 /* 327 */ "F3D\000"
161 /* 331 */ "R3D\000"
162 /* 335 */ "F14D\000"
163 /* 340 */ "R14D\000"
164 /* 345 */ "F24D\000"
165 /* 350 */ "F4D\000"
166 /* 354 */ "R4D\000"
167 /* 358 */ "F15D\000"
168 /* 363 */ "R15D\000"
169 /* 368 */ "F25D\000"
170 /* 373 */ "F5D\000"
171 /* 377 */ "R5D\000"
172 /* 381 */ "F16D\000"
173 /* 386 */ "F26D\000"
174 /* 391 */ "F6D\000"
175 /* 395 */ "R6D\000"
176 /* 399 */ "F17D\000"
177 /* 404 */ "F27D\000"
178 /* 409 */ "F7D\000"
179 /* 413 */ "R7D\000"
180 /* 417 */ "F18D\000"
181 /* 422 */ "F28D\000"
182 /* 427 */ "F8D\000"
183 /* 431 */ "R8D\000"
184 /* 435 */ "F19D\000"
185 /* 440 */ "F29D\000"
186 /* 445 */ "F9D\000"
187 /* 449 */ "R9D\000"
188 /* 453 */ "F10H\000"
189 /* 458 */ "R10H\000"
190 /* 463 */ "F20H\000"
191 /* 468 */ "F30H\000"
192 /* 473 */ "F0H\000"
193 /* 477 */ "R0H\000"
194 /* 481 */ "F11H\000"
195 /* 486 */ "R11H\000"
196 /* 491 */ "F21H\000"
197 /* 496 */ "F31H\000"
198 /* 501 */ "F1H\000"
199 /* 505 */ "R1H\000"
200 /* 509 */ "F12H\000"
201 /* 514 */ "R12H\000"
202 /* 519 */ "F22H\000"
203 /* 524 */ "F2H\000"
204 /* 528 */ "R2H\000"
205 /* 532 */ "F13H\000"
206 /* 537 */ "R13H\000"
207 /* 542 */ "F23H\000"
208 /* 547 */ "F3H\000"
209 /* 551 */ "R3H\000"
210 /* 555 */ "F14H\000"
211 /* 560 */ "R14H\000"
212 /* 565 */ "F24H\000"
213 /* 570 */ "F4H\000"
214 /* 574 */ "R4H\000"
215 /* 578 */ "F15H\000"
216 /* 583 */ "R15H\000"
217 /* 588 */ "F25H\000"
218 /* 593 */ "F5H\000"
219 /* 597 */ "R5H\000"
220 /* 601 */ "F16H\000"
221 /* 606 */ "F26H\000"
222 /* 611 */ "F6H\000"
223 /* 615 */ "R6H\000"
224 /* 619 */ "F17H\000"
225 /* 624 */ "F27H\000"
226 /* 629 */ "F7H\000"
227 /* 633 */ "R7H\000"
228 /* 637 */ "F18H\000"
229 /* 642 */ "F28H\000"
230 /* 647 */ "F8H\000"
231 /* 651 */ "R8H\000"
232 /* 655 */ "F19H\000"
233 /* 660 */ "F29H\000"
234 /* 665 */ "F9H\000"
235 /* 669 */ "R9H\000"
236 /* 673 */ "R10L\000"
237 /* 678 */ "R0L\000"
238 /* 682 */ "R11L\000"
239 /* 687 */ "R1L\000"
240 /* 691 */ "R12L\000"
241 /* 696 */ "R2L\000"
242 /* 700 */ "R13L\000"
243 /* 705 */ "R3L\000"
244 /* 709 */ "R14L\000"
245 /* 714 */ "R4L\000"
246 /* 718 */ "R15L\000"
247 /* 723 */ "R5L\000"
248 /* 727 */ "R6L\000"
249 /* 731 */ "R7L\000"
250 /* 735 */ "R8L\000"
251 /* 739 */ "R9L\000"
252 /* 743 */ "R10Q\000"
253 /* 748 */ "F0Q\000"
254 /* 752 */ "R0Q\000"
255 /* 756 */ "F1Q\000"
256 /* 760 */ "F12Q\000"
257 /* 765 */ "R12Q\000"
258 /* 770 */ "R2Q\000"
259 /* 774 */ "F13Q\000"
260 /* 779 */ "R14Q\000"
261 /* 784 */ "F4Q\000"
262 /* 788 */ "R4Q\000"
263 /* 792 */ "F5Q\000"
264 /* 796 */ "R6Q\000"
265 /* 800 */ "F8Q\000"
266 /* 804 */ "R8Q\000"
267 /* 808 */ "F9Q\000"
268 /* 812 */ "F10S\000"
269 /* 817 */ "F20S\000"
270 /* 822 */ "F30S\000"
271 /* 827 */ "F0S\000"
272 /* 831 */ "F11S\000"
273 /* 836 */ "F21S\000"
274 /* 841 */ "F31S\000"
275 /* 846 */ "F1S\000"
276 /* 850 */ "F12S\000"
277 /* 855 */ "F22S\000"
278 /* 860 */ "F2S\000"
279 /* 864 */ "F13S\000"
280 /* 869 */ "F23S\000"
281 /* 874 */ "F3S\000"
282 /* 878 */ "F14S\000"
283 /* 883 */ "F24S\000"
284 /* 888 */ "F4S\000"
285 /* 892 */ "F15S\000"
286 /* 897 */ "F25S\000"
287 /* 902 */ "F5S\000"
288 /* 906 */ "F16S\000"
289 /* 911 */ "F26S\000"
290 /* 916 */ "F6S\000"
291 /* 920 */ "F17S\000"
292 /* 925 */ "F27S\000"
293 /* 930 */ "F7S\000"
294 /* 934 */ "F18S\000"
295 /* 939 */ "F28S\000"
296 /* 944 */ "F8S\000"
297 /* 948 */ "F19S\000"
298 /* 953 */ "F29S\000"
299 /* 958 */ "F9S\000"
300};
301#ifdef __GNUC__
302#pragma GCC diagnostic pop
303#endif
304
305extern const MCRegisterDesc SystemZRegDesc[] = { // Descriptors
306 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
307 { .Name: 226, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24576, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
308 { .Name: 229, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24577, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
309 { .Name: 20, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24578, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
310 { .Name: 49, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24579, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
311 { .Name: 74, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24580, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
312 { .Name: 99, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24581, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
313 { .Name: 124, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24582, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
314 { .Name: 149, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24583, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
315 { .Name: 166, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24584, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
316 { .Name: 183, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24585, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
317 { .Name: 200, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24586, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
318 { .Name: 217, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24587, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
319 { .Name: 0, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24588, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
320 { .Name: 29, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24589, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
321 { .Name: 58, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24590, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
322 { .Name: 83, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24591, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
323 { .Name: 108, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24592, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
324 { .Name: 133, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24593, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
325 { .Name: 23, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24594, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
326 { .Name: 52, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24595, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
327 { .Name: 77, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24596, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
328 { .Name: 102, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24597, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
329 { .Name: 127, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24598, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
330 { .Name: 152, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24599, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
331 { .Name: 169, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24600, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
332 { .Name: 186, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24601, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
333 { .Name: 203, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24602, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
334 { .Name: 220, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24603, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
335 { .Name: 4, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24604, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
336 { .Name: 33, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24605, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
337 { .Name: 62, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24606, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
338 { .Name: 87, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24607, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
339 { .Name: 112, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24608, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
340 { .Name: 137, .SubRegs: 6, .SuperRegs: 6, .SubRegIndices: 3, .RegUnits: 24609, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
341 { .Name: 26, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24610, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
342 { .Name: 55, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24611, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
343 { .Name: 80, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24612, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
344 { .Name: 105, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24613, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
345 { .Name: 130, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24614, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
346 { .Name: 155, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24615, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
347 { .Name: 172, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24616, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
348 { .Name: 189, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24617, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
349 { .Name: 206, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24618, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
350 { .Name: 223, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24619, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
351 { .Name: 8, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24620, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
352 { .Name: 37, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24621, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
353 { .Name: 66, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24622, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
354 { .Name: 91, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24623, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
355 { .Name: 116, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24624, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
356 { .Name: 141, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24625, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
357 { .Name: 158, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24626, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
358 { .Name: 175, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24627, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
359 { .Name: 192, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24628, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
360 { .Name: 209, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24629, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
361 { .Name: 12, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24630, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
362 { .Name: 41, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24631, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
363 { .Name: 70, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24632, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
364 { .Name: 95, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24633, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
365 { .Name: 120, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24634, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
366 { .Name: 145, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24635, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
367 { .Name: 162, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24636, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
368 { .Name: 179, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24637, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
369 { .Name: 196, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24638, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
370 { .Name: 213, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24639, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
371 { .Name: 16, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24640, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
372 { .Name: 45, .SubRegs: 28, .SuperRegs: 6, .SubRegIndices: 0, .RegUnits: 24641, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
373 { .Name: 253, .SubRegs: 4, .SuperRegs: 174, .SubRegIndices: 1, .RegUnits: 24610, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
374 { .Name: 281, .SubRegs: 4, .SuperRegs: 174, .SubRegIndices: 1, .RegUnits: 24611, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
375 { .Name: 304, .SubRegs: 4, .SuperRegs: 169, .SubRegIndices: 1, .RegUnits: 24612, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
376 { .Name: 327, .SubRegs: 4, .SuperRegs: 169, .SubRegIndices: 1, .RegUnits: 24613, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
377 { .Name: 350, .SubRegs: 4, .SuperRegs: 169, .SubRegIndices: 1, .RegUnits: 24614, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
378 { .Name: 373, .SubRegs: 4, .SuperRegs: 169, .SubRegIndices: 1, .RegUnits: 24615, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
379 { .Name: 391, .SubRegs: 4, .SuperRegs: 164, .SubRegIndices: 1, .RegUnits: 24616, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
380 { .Name: 409, .SubRegs: 4, .SuperRegs: 164, .SubRegIndices: 1, .RegUnits: 24617, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
381 { .Name: 427, .SubRegs: 4, .SuperRegs: 164, .SubRegIndices: 1, .RegUnits: 24618, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
382 { .Name: 445, .SubRegs: 4, .SuperRegs: 164, .SubRegIndices: 1, .RegUnits: 24619, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
383 { .Name: 233, .SubRegs: 4, .SuperRegs: 159, .SubRegIndices: 1, .RegUnits: 24620, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
384 { .Name: 261, .SubRegs: 4, .SuperRegs: 159, .SubRegIndices: 1, .RegUnits: 24621, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
385 { .Name: 289, .SubRegs: 4, .SuperRegs: 159, .SubRegIndices: 1, .RegUnits: 24622, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
386 { .Name: 312, .SubRegs: 4, .SuperRegs: 159, .SubRegIndices: 1, .RegUnits: 24623, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
387 { .Name: 335, .SubRegs: 4, .SuperRegs: 154, .SubRegIndices: 1, .RegUnits: 24624, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
388 { .Name: 358, .SubRegs: 4, .SuperRegs: 154, .SubRegIndices: 1, .RegUnits: 24625, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
389 { .Name: 381, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24626, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
390 { .Name: 399, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24627, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
391 { .Name: 417, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24628, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
392 { .Name: 435, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24629, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
393 { .Name: 243, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24630, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
394 { .Name: 271, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24631, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
395 { .Name: 299, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24632, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
396 { .Name: 322, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24633, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
397 { .Name: 345, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24634, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
398 { .Name: 368, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24635, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
399 { .Name: 386, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24636, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
400 { .Name: 404, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24637, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
401 { .Name: 422, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24638, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
402 { .Name: 440, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24639, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
403 { .Name: 248, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24640, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
404 { .Name: 276, .SubRegs: 4, .SuperRegs: 34, .SubRegIndices: 1, .RegUnits: 24641, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
405 { .Name: 473, .SubRegs: 6, .SuperRegs: 172, .SubRegIndices: 3, .RegUnits: 24610, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
406 { .Name: 501, .SubRegs: 6, .SuperRegs: 172, .SubRegIndices: 3, .RegUnits: 24611, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
407 { .Name: 524, .SubRegs: 6, .SuperRegs: 167, .SubRegIndices: 3, .RegUnits: 24612, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
408 { .Name: 547, .SubRegs: 6, .SuperRegs: 167, .SubRegIndices: 3, .RegUnits: 24613, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
409 { .Name: 570, .SubRegs: 6, .SuperRegs: 167, .SubRegIndices: 3, .RegUnits: 24614, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
410 { .Name: 593, .SubRegs: 6, .SuperRegs: 167, .SubRegIndices: 3, .RegUnits: 24615, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
411 { .Name: 611, .SubRegs: 6, .SuperRegs: 162, .SubRegIndices: 3, .RegUnits: 24616, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
412 { .Name: 629, .SubRegs: 6, .SuperRegs: 162, .SubRegIndices: 3, .RegUnits: 24617, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
413 { .Name: 647, .SubRegs: 6, .SuperRegs: 162, .SubRegIndices: 3, .RegUnits: 24618, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
414 { .Name: 665, .SubRegs: 6, .SuperRegs: 162, .SubRegIndices: 3, .RegUnits: 24619, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
415 { .Name: 453, .SubRegs: 6, .SuperRegs: 157, .SubRegIndices: 3, .RegUnits: 24620, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
416 { .Name: 481, .SubRegs: 6, .SuperRegs: 157, .SubRegIndices: 3, .RegUnits: 24621, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
417 { .Name: 509, .SubRegs: 6, .SuperRegs: 157, .SubRegIndices: 3, .RegUnits: 24622, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
418 { .Name: 532, .SubRegs: 6, .SuperRegs: 157, .SubRegIndices: 3, .RegUnits: 24623, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
419 { .Name: 555, .SubRegs: 6, .SuperRegs: 152, .SubRegIndices: 3, .RegUnits: 24624, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
420 { .Name: 578, .SubRegs: 6, .SuperRegs: 152, .SubRegIndices: 3, .RegUnits: 24625, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
421 { .Name: 601, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24626, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
422 { .Name: 619, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24627, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
423 { .Name: 637, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24628, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
424 { .Name: 655, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24629, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
425 { .Name: 463, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24630, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
426 { .Name: 491, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24631, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
427 { .Name: 519, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24632, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
428 { .Name: 542, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24633, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
429 { .Name: 565, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24634, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
430 { .Name: 588, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24635, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
431 { .Name: 606, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24636, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
432 { .Name: 624, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24637, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
433 { .Name: 642, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24638, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
434 { .Name: 660, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24639, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
435 { .Name: 468, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24640, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
436 { .Name: 496, .SubRegs: 6, .SuperRegs: 32, .SubRegIndices: 3, .RegUnits: 24641, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
437 { .Name: 748, .SubRegs: 0, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393250, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
438 { .Name: 756, .SubRegs: 0, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393251, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
439 { .Name: 784, .SubRegs: 7, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393254, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
440 { .Name: 792, .SubRegs: 7, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393255, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
441 { .Name: 800, .SubRegs: 14, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393258, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
442 { .Name: 808, .SubRegs: 14, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393259, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
443 { .Name: 760, .SubRegs: 21, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393262, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
444 { .Name: 774, .SubRegs: 21, .SuperRegs: 6, .SubRegIndices: 11, .RegUnits: 393263, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
445 { .Name: 827, .SubRegs: 5, .SuperRegs: 173, .SubRegIndices: 2, .RegUnits: 24610, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
446 { .Name: 846, .SubRegs: 5, .SuperRegs: 173, .SubRegIndices: 2, .RegUnits: 24611, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
447 { .Name: 860, .SubRegs: 5, .SuperRegs: 168, .SubRegIndices: 2, .RegUnits: 24612, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
448 { .Name: 874, .SubRegs: 5, .SuperRegs: 168, .SubRegIndices: 2, .RegUnits: 24613, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
449 { .Name: 888, .SubRegs: 5, .SuperRegs: 168, .SubRegIndices: 2, .RegUnits: 24614, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
450 { .Name: 902, .SubRegs: 5, .SuperRegs: 168, .SubRegIndices: 2, .RegUnits: 24615, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
451 { .Name: 916, .SubRegs: 5, .SuperRegs: 163, .SubRegIndices: 2, .RegUnits: 24616, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
452 { .Name: 930, .SubRegs: 5, .SuperRegs: 163, .SubRegIndices: 2, .RegUnits: 24617, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
453 { .Name: 944, .SubRegs: 5, .SuperRegs: 163, .SubRegIndices: 2, .RegUnits: 24618, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
454 { .Name: 958, .SubRegs: 5, .SuperRegs: 163, .SubRegIndices: 2, .RegUnits: 24619, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
455 { .Name: 812, .SubRegs: 5, .SuperRegs: 158, .SubRegIndices: 2, .RegUnits: 24620, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
456 { .Name: 831, .SubRegs: 5, .SuperRegs: 158, .SubRegIndices: 2, .RegUnits: 24621, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
457 { .Name: 850, .SubRegs: 5, .SuperRegs: 158, .SubRegIndices: 2, .RegUnits: 24622, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
458 { .Name: 864, .SubRegs: 5, .SuperRegs: 158, .SubRegIndices: 2, .RegUnits: 24623, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
459 { .Name: 878, .SubRegs: 5, .SuperRegs: 153, .SubRegIndices: 2, .RegUnits: 24624, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
460 { .Name: 892, .SubRegs: 5, .SuperRegs: 153, .SubRegIndices: 2, .RegUnits: 24625, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
461 { .Name: 906, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24626, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
462 { .Name: 920, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24627, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
463 { .Name: 934, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24628, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
464 { .Name: 948, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24629, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
465 { .Name: 817, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24630, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
466 { .Name: 836, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24631, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
467 { .Name: 855, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24632, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
468 { .Name: 869, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24633, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
469 { .Name: 883, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24634, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
470 { .Name: 897, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24635, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
471 { .Name: 911, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24636, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
472 { .Name: 925, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24637, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
473 { .Name: 939, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24638, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
474 { .Name: 953, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24639, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
475 { .Name: 822, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24640, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
476 { .Name: 841, .SubRegs: 5, .SuperRegs: 33, .SubRegIndices: 2, .RegUnits: 24641, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
477 { .Name: 257, .SubRegs: 40, .SuperRegs: 147, .SubRegIndices: 3, .RegUnits: 385090, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
478 { .Name: 285, .SubRegs: 40, .SuperRegs: 141, .SubRegIndices: 3, .RegUnits: 385092, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
479 { .Name: 308, .SubRegs: 40, .SuperRegs: 141, .SubRegIndices: 3, .RegUnits: 385094, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
480 { .Name: 331, .SubRegs: 40, .SuperRegs: 135, .SubRegIndices: 3, .RegUnits: 385096, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
481 { .Name: 354, .SubRegs: 40, .SuperRegs: 135, .SubRegIndices: 3, .RegUnits: 385098, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
482 { .Name: 377, .SubRegs: 40, .SuperRegs: 129, .SubRegIndices: 3, .RegUnits: 385100, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
483 { .Name: 395, .SubRegs: 40, .SuperRegs: 129, .SubRegIndices: 3, .RegUnits: 385102, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
484 { .Name: 413, .SubRegs: 40, .SuperRegs: 123, .SubRegIndices: 3, .RegUnits: 385104, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
485 { .Name: 431, .SubRegs: 40, .SuperRegs: 123, .SubRegIndices: 3, .RegUnits: 385106, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
486 { .Name: 449, .SubRegs: 40, .SuperRegs: 117, .SubRegIndices: 3, .RegUnits: 385108, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
487 { .Name: 238, .SubRegs: 40, .SuperRegs: 117, .SubRegIndices: 3, .RegUnits: 385110, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
488 { .Name: 266, .SubRegs: 40, .SuperRegs: 111, .SubRegIndices: 3, .RegUnits: 385112, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
489 { .Name: 294, .SubRegs: 40, .SuperRegs: 111, .SubRegIndices: 3, .RegUnits: 385114, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
490 { .Name: 317, .SubRegs: 40, .SuperRegs: 105, .SubRegIndices: 3, .RegUnits: 385116, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
491 { .Name: 340, .SubRegs: 40, .SuperRegs: 105, .SubRegIndices: 3, .RegUnits: 385118, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
492 { .Name: 363, .SubRegs: 40, .SuperRegs: 99, .SubRegIndices: 3, .RegUnits: 385120, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
493 { .Name: 477, .SubRegs: 6, .SuperRegs: 149, .SubRegIndices: 3, .RegUnits: 24643, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
494 { .Name: 505, .SubRegs: 6, .SuperRegs: 143, .SubRegIndices: 3, .RegUnits: 24645, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
495 { .Name: 528, .SubRegs: 6, .SuperRegs: 143, .SubRegIndices: 3, .RegUnits: 24647, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
496 { .Name: 551, .SubRegs: 6, .SuperRegs: 137, .SubRegIndices: 3, .RegUnits: 24649, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
497 { .Name: 574, .SubRegs: 6, .SuperRegs: 137, .SubRegIndices: 3, .RegUnits: 24651, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
498 { .Name: 597, .SubRegs: 6, .SuperRegs: 131, .SubRegIndices: 3, .RegUnits: 24653, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
499 { .Name: 615, .SubRegs: 6, .SuperRegs: 131, .SubRegIndices: 3, .RegUnits: 24655, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
500 { .Name: 633, .SubRegs: 6, .SuperRegs: 125, .SubRegIndices: 3, .RegUnits: 24657, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
501 { .Name: 651, .SubRegs: 6, .SuperRegs: 125, .SubRegIndices: 3, .RegUnits: 24659, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
502 { .Name: 669, .SubRegs: 6, .SuperRegs: 119, .SubRegIndices: 3, .RegUnits: 24661, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
503 { .Name: 458, .SubRegs: 6, .SuperRegs: 119, .SubRegIndices: 3, .RegUnits: 24663, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
504 { .Name: 486, .SubRegs: 6, .SuperRegs: 113, .SubRegIndices: 3, .RegUnits: 24665, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
505 { .Name: 514, .SubRegs: 6, .SuperRegs: 113, .SubRegIndices: 3, .RegUnits: 24667, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
506 { .Name: 537, .SubRegs: 6, .SuperRegs: 107, .SubRegIndices: 3, .RegUnits: 24669, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
507 { .Name: 560, .SubRegs: 6, .SuperRegs: 107, .SubRegIndices: 3, .RegUnits: 24671, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
508 { .Name: 583, .SubRegs: 6, .SuperRegs: 101, .SubRegIndices: 3, .RegUnits: 24673, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
509 { .Name: 678, .SubRegs: 6, .SuperRegs: 146, .SubRegIndices: 3, .RegUnits: 24642, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
510 { .Name: 687, .SubRegs: 6, .SuperRegs: 140, .SubRegIndices: 3, .RegUnits: 24644, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
511 { .Name: 696, .SubRegs: 6, .SuperRegs: 140, .SubRegIndices: 3, .RegUnits: 24646, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
512 { .Name: 705, .SubRegs: 6, .SuperRegs: 134, .SubRegIndices: 3, .RegUnits: 24648, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
513 { .Name: 714, .SubRegs: 6, .SuperRegs: 134, .SubRegIndices: 3, .RegUnits: 24650, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
514 { .Name: 723, .SubRegs: 6, .SuperRegs: 128, .SubRegIndices: 3, .RegUnits: 24652, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
515 { .Name: 727, .SubRegs: 6, .SuperRegs: 128, .SubRegIndices: 3, .RegUnits: 24654, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
516 { .Name: 731, .SubRegs: 6, .SuperRegs: 122, .SubRegIndices: 3, .RegUnits: 24656, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
517 { .Name: 735, .SubRegs: 6, .SuperRegs: 122, .SubRegIndices: 3, .RegUnits: 24658, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
518 { .Name: 739, .SubRegs: 6, .SuperRegs: 116, .SubRegIndices: 3, .RegUnits: 24660, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
519 { .Name: 673, .SubRegs: 6, .SuperRegs: 116, .SubRegIndices: 3, .RegUnits: 24662, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
520 { .Name: 682, .SubRegs: 6, .SuperRegs: 110, .SubRegIndices: 3, .RegUnits: 24664, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
521 { .Name: 691, .SubRegs: 6, .SuperRegs: 110, .SubRegIndices: 3, .RegUnits: 24666, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
522 { .Name: 700, .SubRegs: 6, .SuperRegs: 104, .SubRegIndices: 3, .RegUnits: 24668, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
523 { .Name: 709, .SubRegs: 6, .SuperRegs: 104, .SubRegIndices: 3, .RegUnits: 24670, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
524 { .Name: 718, .SubRegs: 6, .SuperRegs: 98, .SubRegIndices: 3, .RegUnits: 24672, .RegUnitLaneMasks: 9, .IsConstant: 0, .IsArtificial: 0 },
525 { .Name: 752, .SubRegs: 36, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376898, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 },
526 { .Name: 770, .SubRegs: 43, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376902, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 },
527 { .Name: 788, .SubRegs: 50, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376906, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 },
528 { .Name: 796, .SubRegs: 57, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376910, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 },
529 { .Name: 804, .SubRegs: 64, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376914, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 },
530 { .Name: 743, .SubRegs: 71, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376918, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 },
531 { .Name: 765, .SubRegs: 78, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376922, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 },
532 { .Name: 779, .SubRegs: 85, .SuperRegs: 6, .SubRegIndices: 5, .RegUnits: 376926, .RegUnitLaneMasks: 3, .IsConstant: 0, .IsArtificial: 0 },
533};
534
535extern const MCPhysReg SystemZRegUnitRoots[][2] = {
536 { SystemZ::CC },
537 { SystemZ::FPC },
538 { SystemZ::A0 },
539 { SystemZ::A1 },
540 { SystemZ::A2 },
541 { SystemZ::A3 },
542 { SystemZ::A4 },
543 { SystemZ::A5 },
544 { SystemZ::A6 },
545 { SystemZ::A7 },
546 { SystemZ::A8 },
547 { SystemZ::A9 },
548 { SystemZ::A10 },
549 { SystemZ::A11 },
550 { SystemZ::A12 },
551 { SystemZ::A13 },
552 { SystemZ::A14 },
553 { SystemZ::A15 },
554 { SystemZ::C0 },
555 { SystemZ::C1 },
556 { SystemZ::C2 },
557 { SystemZ::C3 },
558 { SystemZ::C4 },
559 { SystemZ::C5 },
560 { SystemZ::C6 },
561 { SystemZ::C7 },
562 { SystemZ::C8 },
563 { SystemZ::C9 },
564 { SystemZ::C10 },
565 { SystemZ::C11 },
566 { SystemZ::C12 },
567 { SystemZ::C13 },
568 { SystemZ::C14 },
569 { SystemZ::C15 },
570 { SystemZ::F0H },
571 { SystemZ::F1H },
572 { SystemZ::F2H },
573 { SystemZ::F3H },
574 { SystemZ::F4H },
575 { SystemZ::F5H },
576 { SystemZ::F6H },
577 { SystemZ::F7H },
578 { SystemZ::F8H },
579 { SystemZ::F9H },
580 { SystemZ::F10H },
581 { SystemZ::F11H },
582 { SystemZ::F12H },
583 { SystemZ::F13H },
584 { SystemZ::F14H },
585 { SystemZ::F15H },
586 { SystemZ::F16H },
587 { SystemZ::F17H },
588 { SystemZ::F18H },
589 { SystemZ::F19H },
590 { SystemZ::F20H },
591 { SystemZ::F21H },
592 { SystemZ::F22H },
593 { SystemZ::F23H },
594 { SystemZ::F24H },
595 { SystemZ::F25H },
596 { SystemZ::F26H },
597 { SystemZ::F27H },
598 { SystemZ::F28H },
599 { SystemZ::F29H },
600 { SystemZ::F30H },
601 { SystemZ::F31H },
602 { SystemZ::R0L },
603 { SystemZ::R0H },
604 { SystemZ::R1L },
605 { SystemZ::R1H },
606 { SystemZ::R2L },
607 { SystemZ::R2H },
608 { SystemZ::R3L },
609 { SystemZ::R3H },
610 { SystemZ::R4L },
611 { SystemZ::R4H },
612 { SystemZ::R5L },
613 { SystemZ::R5H },
614 { SystemZ::R6L },
615 { SystemZ::R6H },
616 { SystemZ::R7L },
617 { SystemZ::R7H },
618 { SystemZ::R8L },
619 { SystemZ::R8H },
620 { SystemZ::R9L },
621 { SystemZ::R9H },
622 { SystemZ::R10L },
623 { SystemZ::R10H },
624 { SystemZ::R11L },
625 { SystemZ::R11H },
626 { SystemZ::R12L },
627 { SystemZ::R12H },
628 { SystemZ::R13L },
629 { SystemZ::R13H },
630 { SystemZ::R14L },
631 { SystemZ::R14H },
632 { SystemZ::R15L },
633 { SystemZ::R15H },
634};
635
636// Register classes...
637
638#ifdef __GNUC__
639#pragma GCC diagnostic push
640#pragma GCC diagnostic ignored "-Woverlength-strings"
641#endif
642extern const char SystemZRegClassStrings[] = {
643 /* 0 */ "AnyRegBit_with_subreg_h64\000"
644 /* 26 */ "AnyRegBit_with_subreg_h16\000"
645 /* 52 */ "CCR\000"
646 /* 56 */ "FPCRegs\000"
647 /* 64 */ "GRH32Bit\000"
648 /* 73 */ "FP32Bit\000"
649 /* 81 */ "AR32Bit\000"
650 /* 89 */ "ADDR32Bit\000"
651 /* 99 */ "GR32Bit\000"
652 /* 107 */ "VR32Bit\000"
653 /* 115 */ "GRX32Bit\000"
654 /* 124 */ "FP64Bit\000"
655 /* 132 */ "CR64Bit\000"
656 /* 140 */ "ADDR64Bit\000"
657 /* 150 */ "GR64Bit\000"
658 /* 158 */ "VR64Bit\000"
659 /* 166 */ "FP16Bit\000"
660 /* 174 */ "VR16Bit\000"
661 /* 182 */ "VF128Bit\000"
662 /* 191 */ "FP128Bit\000"
663 /* 200 */ "ADDR128Bit\000"
664 /* 211 */ "GR128Bit\000"
665 /* 220 */ "VR128Bit\000"
666 /* 229 */ "AnyRegBit\000"
667};
668#ifdef __GNUC__
669#pragma GCC diagnostic pop
670#endif
671
672using SystemZRegisterClassStorage = MCRegisterClassStorage<24, 455, 74, 54, 17, 20>;
673extern const MCRegisterClassStorage<24, 455, 74, 54, 17, 20> SystemZMCRegisterClassStorage = {
674 .Classes: {
675 {
676 offsetof(SystemZRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
677 offsetof(SystemZRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
678 .NameIdx: 174,
679 .RegSizeInBits: 16,
680 .RegsSize: 32,
681 .RegSetBegin: 99, /* MinRegVal */
682 .RegSetSize: 32, /* RegSetSize */
683 .ID: SystemZ::VR16BitRegClassID,
684 .CopyCost: 1, /* CopyCost */
685 .Allocatable: true, /* Allocatable */
686 .BaseClass: false,
687 offsetof(SystemZRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
688 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[14]) - 0 * sizeof(MCRegisterClass),
689 .LaneMask: LaneBitmask(0x0000000000000001),
690 .AllocationPriority: 0,
691 .GlobalPriority: false,
692 .TSFlags: 0x00, /* TSFlags */
693 .SpillStackID: 0, /* SpillStackID */
694 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
695 .CoveredBySubRegs: false, /* CoveredBySubRegs */
696 offsetof(SystemZRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
697 .SuperClassesSize: 0
698 },
699 {
700 offsetof(SystemZRegisterClassStorage, Regs[32]) - 1 * sizeof(MCRegisterClass),
701 offsetof(SystemZRegisterClassStorage, BitSets[4]) - 1 * sizeof(MCRegisterClass),
702 .NameIdx: 166,
703 .RegSizeInBits: 0,
704 .RegsSize: 16,
705 .RegSetBegin: 99, /* MinRegVal */
706 .RegSetSize: 16, /* RegSetSize */
707 .ID: SystemZ::FP16BitRegClassID,
708 .CopyCost: 1, /* CopyCost */
709 .Allocatable: true, /* Allocatable */
710 .BaseClass: false,
711 offsetof(SystemZRegisterClassStorage, SubClassMasks[3]) - 1 * sizeof(MCRegisterClass),
712 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[14]) - 1 * sizeof(MCRegisterClass),
713 .LaneMask: LaneBitmask(0x0000000000000001),
714 .AllocationPriority: 0,
715 .GlobalPriority: false,
716 .TSFlags: 0x00, /* TSFlags */
717 .SpillStackID: 0, /* SpillStackID */
718 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
719 .CoveredBySubRegs: false, /* CoveredBySubRegs */
720 offsetof(SystemZRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
721 .SuperClassesSize: 1
722 },
723 {
724 offsetof(SystemZRegisterClassStorage, Regs[48]) - 2 * sizeof(MCRegisterClass),
725 offsetof(SystemZRegisterClassStorage, BitSets[6]) - 2 * sizeof(MCRegisterClass),
726 .NameIdx: 115,
727 .RegSizeInBits: 32,
728 .RegsSize: 32,
729 .RegSetBegin: 187, /* MinRegVal */
730 .RegSetSize: 32, /* RegSetSize */
731 .ID: SystemZ::GRX32BitRegClassID,
732 .CopyCost: 1, /* CopyCost */
733 .Allocatable: true, /* Allocatable */
734 .BaseClass: false,
735 offsetof(SystemZRegisterClassStorage, SubClassMasks[6]) - 2 * sizeof(MCRegisterClass),
736 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[9]) - 2 * sizeof(MCRegisterClass),
737 .LaneMask: LaneBitmask(0x0000000000000001),
738 .AllocationPriority: 0,
739 .GlobalPriority: false,
740 .TSFlags: 0x00, /* TSFlags */
741 .SpillStackID: 0, /* SpillStackID */
742 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
743 .CoveredBySubRegs: false, /* CoveredBySubRegs */
744 offsetof(SystemZRegisterClassStorage, SuperClasses[1]) - 2 * sizeof(MCRegisterClass),
745 .SuperClassesSize: 0
746 },
747 {
748 offsetof(SystemZRegisterClassStorage, Regs[80]) - 3 * sizeof(MCRegisterClass),
749 offsetof(SystemZRegisterClassStorage, BitSets[10]) - 3 * sizeof(MCRegisterClass),
750 .NameIdx: 107,
751 .RegSizeInBits: 32,
752 .RegsSize: 32,
753 .RegSetBegin: 139, /* MinRegVal */
754 .RegSetSize: 32, /* RegSetSize */
755 .ID: SystemZ::VR32BitRegClassID,
756 .CopyCost: 1, /* CopyCost */
757 .Allocatable: true, /* Allocatable */
758 .BaseClass: false,
759 offsetof(SystemZRegisterClassStorage, SubClassMasks[11]) - 3 * sizeof(MCRegisterClass),
760 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[3]) - 3 * sizeof(MCRegisterClass),
761 .LaneMask: LaneBitmask(0x0000000000000001),
762 .AllocationPriority: 0,
763 .GlobalPriority: false,
764 .TSFlags: 0x00, /* TSFlags */
765 .SpillStackID: 0, /* SpillStackID */
766 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
767 .CoveredBySubRegs: false, /* CoveredBySubRegs */
768 offsetof(SystemZRegisterClassStorage, SuperClasses[1]) - 3 * sizeof(MCRegisterClass),
769 .SuperClassesSize: 0
770 },
771 {
772 offsetof(SystemZRegisterClassStorage, Regs[112]) - 4 * sizeof(MCRegisterClass),
773 offsetof(SystemZRegisterClassStorage, BitSets[14]) - 4 * sizeof(MCRegisterClass),
774 .NameIdx: 81,
775 .RegSizeInBits: 32,
776 .RegsSize: 16,
777 .RegSetBegin: 3, /* MinRegVal */
778 .RegSetSize: 16, /* RegSetSize */
779 .ID: SystemZ::AR32BitRegClassID,
780 .CopyCost: 1, /* CopyCost */
781 .Allocatable: false, /* Allocatable */
782 .BaseClass: false,
783 offsetof(SystemZRegisterClassStorage, SubClassMasks[14]) - 4 * sizeof(MCRegisterClass),
784 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[2]) - 4 * sizeof(MCRegisterClass),
785 .LaneMask: LaneBitmask(0x0000000000000001),
786 .AllocationPriority: 0,
787 .GlobalPriority: false,
788 .TSFlags: 0x00, /* TSFlags */
789 .SpillStackID: 0, /* SpillStackID */
790 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
791 .CoveredBySubRegs: false, /* CoveredBySubRegs */
792 offsetof(SystemZRegisterClassStorage, SuperClasses[1]) - 4 * sizeof(MCRegisterClass),
793 .SuperClassesSize: 0
794 },
795 {
796 offsetof(SystemZRegisterClassStorage, Regs[128]) - 5 * sizeof(MCRegisterClass),
797 offsetof(SystemZRegisterClassStorage, BitSets[16]) - 5 * sizeof(MCRegisterClass),
798 .NameIdx: 73,
799 .RegSizeInBits: 32,
800 .RegsSize: 16,
801 .RegSetBegin: 139, /* MinRegVal */
802 .RegSetSize: 16, /* RegSetSize */
803 .ID: SystemZ::FP32BitRegClassID,
804 .CopyCost: 1, /* CopyCost */
805 .Allocatable: true, /* Allocatable */
806 .BaseClass: false,
807 offsetof(SystemZRegisterClassStorage, SubClassMasks[15]) - 5 * sizeof(MCRegisterClass),
808 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[3]) - 5 * sizeof(MCRegisterClass),
809 .LaneMask: LaneBitmask(0x0000000000000001),
810 .AllocationPriority: 0,
811 .GlobalPriority: false,
812 .TSFlags: 0x00, /* TSFlags */
813 .SpillStackID: 0, /* SpillStackID */
814 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
815 .CoveredBySubRegs: false, /* CoveredBySubRegs */
816 offsetof(SystemZRegisterClassStorage, SuperClasses[1]) - 5 * sizeof(MCRegisterClass),
817 .SuperClassesSize: 1
818 },
819 {
820 offsetof(SystemZRegisterClassStorage, Regs[144]) - 6 * sizeof(MCRegisterClass),
821 offsetof(SystemZRegisterClassStorage, BitSets[18]) - 6 * sizeof(MCRegisterClass),
822 .NameIdx: 99,
823 .RegSizeInBits: 32,
824 .RegsSize: 16,
825 .RegSetBegin: 203, /* MinRegVal */
826 .RegSetSize: 16, /* RegSetSize */
827 .ID: SystemZ::GR32BitRegClassID,
828 .CopyCost: 1, /* CopyCost */
829 .Allocatable: true, /* Allocatable */
830 .BaseClass: false,
831 offsetof(SystemZRegisterClassStorage, SubClassMasks[18]) - 6 * sizeof(MCRegisterClass),
832 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[6]) - 6 * sizeof(MCRegisterClass),
833 .LaneMask: LaneBitmask(0x0000000000000001),
834 .AllocationPriority: 0,
835 .GlobalPriority: false,
836 .TSFlags: 0x00, /* TSFlags */
837 .SpillStackID: 0, /* SpillStackID */
838 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
839 .CoveredBySubRegs: false, /* CoveredBySubRegs */
840 offsetof(SystemZRegisterClassStorage, SuperClasses[2]) - 6 * sizeof(MCRegisterClass),
841 .SuperClassesSize: 1
842 },
843 {
844 offsetof(SystemZRegisterClassStorage, Regs[160]) - 7 * sizeof(MCRegisterClass),
845 offsetof(SystemZRegisterClassStorage, BitSets[20]) - 7 * sizeof(MCRegisterClass),
846 .NameIdx: 64,
847 .RegSizeInBits: 32,
848 .RegsSize: 16,
849 .RegSetBegin: 187, /* MinRegVal */
850 .RegSetSize: 16, /* RegSetSize */
851 .ID: SystemZ::GRH32BitRegClassID,
852 .CopyCost: 1, /* CopyCost */
853 .Allocatable: true, /* Allocatable */
854 .BaseClass: false,
855 offsetof(SystemZRegisterClassStorage, SubClassMasks[21]) - 7 * sizeof(MCRegisterClass),
856 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[3]) - 7 * sizeof(MCRegisterClass),
857 .LaneMask: LaneBitmask(0x0000000000000001),
858 .AllocationPriority: 0,
859 .GlobalPriority: false,
860 .TSFlags: 0x00, /* TSFlags */
861 .SpillStackID: 0, /* SpillStackID */
862 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
863 .CoveredBySubRegs: false, /* CoveredBySubRegs */
864 offsetof(SystemZRegisterClassStorage, SuperClasses[3]) - 7 * sizeof(MCRegisterClass),
865 .SuperClassesSize: 1
866 },
867 {
868 offsetof(SystemZRegisterClassStorage, Regs[176]) - 8 * sizeof(MCRegisterClass),
869 offsetof(SystemZRegisterClassStorage, BitSets[22]) - 8 * sizeof(MCRegisterClass),
870 .NameIdx: 89,
871 .RegSizeInBits: 32,
872 .RegsSize: 15,
873 .RegSetBegin: 204, /* MinRegVal */
874 .RegSetSize: 15, /* RegSetSize */
875 .ID: SystemZ::ADDR32BitRegClassID,
876 .CopyCost: 1, /* CopyCost */
877 .Allocatable: true, /* Allocatable */
878 .BaseClass: false,
879 offsetof(SystemZRegisterClassStorage, SubClassMasks[24]) - 8 * sizeof(MCRegisterClass),
880 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[6]) - 8 * sizeof(MCRegisterClass),
881 .LaneMask: LaneBitmask(0x0000000000000001),
882 .AllocationPriority: 0,
883 .GlobalPriority: false,
884 .TSFlags: 0x00, /* TSFlags */
885 .SpillStackID: 0, /* SpillStackID */
886 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
887 .CoveredBySubRegs: false, /* CoveredBySubRegs */
888 offsetof(SystemZRegisterClassStorage, SuperClasses[4]) - 8 * sizeof(MCRegisterClass),
889 .SuperClassesSize: 2
890 },
891 {
892 offsetof(SystemZRegisterClassStorage, Regs[191]) - 9 * sizeof(MCRegisterClass),
893 offsetof(SystemZRegisterClassStorage, BitSets[24]) - 9 * sizeof(MCRegisterClass),
894 .NameIdx: 52,
895 .RegSizeInBits: 32,
896 .RegsSize: 1,
897 .RegSetBegin: 1, /* MinRegVal */
898 .RegSetSize: 1, /* RegSetSize */
899 .ID: SystemZ::CCRRegClassID,
900 .CopyCost: 255, /* CopyCost */
901 .Allocatable: false, /* Allocatable */
902 .BaseClass: false,
903 offsetof(SystemZRegisterClassStorage, SubClassMasks[27]) - 9 * sizeof(MCRegisterClass),
904 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[2]) - 9 * sizeof(MCRegisterClass),
905 .LaneMask: LaneBitmask(0x0000000000000001),
906 .AllocationPriority: 0,
907 .GlobalPriority: false,
908 .TSFlags: 0x00, /* TSFlags */
909 .SpillStackID: 0, /* SpillStackID */
910 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
911 .CoveredBySubRegs: false, /* CoveredBySubRegs */
912 offsetof(SystemZRegisterClassStorage, SuperClasses[6]) - 9 * sizeof(MCRegisterClass),
913 .SuperClassesSize: 0
914 },
915 {
916 offsetof(SystemZRegisterClassStorage, Regs[192]) - 10 * sizeof(MCRegisterClass),
917 offsetof(SystemZRegisterClassStorage, BitSets[25]) - 10 * sizeof(MCRegisterClass),
918 .NameIdx: 56,
919 .RegSizeInBits: 32,
920 .RegsSize: 1,
921 .RegSetBegin: 2, /* MinRegVal */
922 .RegSetSize: 1, /* RegSetSize */
923 .ID: SystemZ::FPCRegsRegClassID,
924 .CopyCost: 1, /* CopyCost */
925 .Allocatable: false, /* Allocatable */
926 .BaseClass: false,
927 offsetof(SystemZRegisterClassStorage, SubClassMasks[28]) - 10 * sizeof(MCRegisterClass),
928 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[2]) - 10 * sizeof(MCRegisterClass),
929 .LaneMask: LaneBitmask(0x0000000000000001),
930 .AllocationPriority: 0,
931 .GlobalPriority: false,
932 .TSFlags: 0x00, /* TSFlags */
933 .SpillStackID: 0, /* SpillStackID */
934 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
935 .CoveredBySubRegs: false, /* CoveredBySubRegs */
936 offsetof(SystemZRegisterClassStorage, SuperClasses[6]) - 10 * sizeof(MCRegisterClass),
937 .SuperClassesSize: 0
938 },
939 {
940 offsetof(SystemZRegisterClassStorage, Regs[193]) - 11 * sizeof(MCRegisterClass),
941 offsetof(SystemZRegisterClassStorage, BitSets[26]) - 11 * sizeof(MCRegisterClass),
942 .NameIdx: 229,
943 .RegSizeInBits: 64,
944 .RegsSize: 48,
945 .RegSetBegin: 35, /* MinRegVal */
946 .RegSetSize: 152, /* RegSetSize */
947 .ID: SystemZ::AnyRegBitRegClassID,
948 .CopyCost: 1, /* CopyCost */
949 .Allocatable: false, /* Allocatable */
950 .BaseClass: false,
951 offsetof(SystemZRegisterClassStorage, SubClassMasks[29]) - 11 * sizeof(MCRegisterClass),
952 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[0]) - 11 * sizeof(MCRegisterClass),
953 .LaneMask: LaneBitmask(0x0000000000000003),
954 .AllocationPriority: 0,
955 .GlobalPriority: false,
956 .TSFlags: 0x00, /* TSFlags */
957 .SpillStackID: 0, /* SpillStackID */
958 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
959 .CoveredBySubRegs: false, /* CoveredBySubRegs */
960 offsetof(SystemZRegisterClassStorage, SuperClasses[6]) - 11 * sizeof(MCRegisterClass),
961 .SuperClassesSize: 0
962 },
963 {
964 offsetof(SystemZRegisterClassStorage, Regs[241]) - 12 * sizeof(MCRegisterClass),
965 offsetof(SystemZRegisterClassStorage, BitSets[45]) - 12 * sizeof(MCRegisterClass),
966 .NameIdx: 26,
967 .RegSizeInBits: 64,
968 .RegsSize: 32,
969 .RegSetBegin: 35, /* MinRegVal */
970 .RegSetSize: 48, /* RegSetSize */
971 .ID: SystemZ::AnyRegBit_with_subreg_h16RegClassID,
972 .CopyCost: 1, /* CopyCost */
973 .Allocatable: false, /* Allocatable */
974 .BaseClass: false,
975 offsetof(SystemZRegisterClassStorage, SubClassMasks[32]) - 12 * sizeof(MCRegisterClass),
976 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[0]) - 12 * sizeof(MCRegisterClass),
977 .LaneMask: LaneBitmask(0x0000000000000003),
978 .AllocationPriority: 0,
979 .GlobalPriority: false,
980 .TSFlags: 0x00, /* TSFlags */
981 .SpillStackID: 0, /* SpillStackID */
982 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
983 .CoveredBySubRegs: false, /* CoveredBySubRegs */
984 offsetof(SystemZRegisterClassStorage, SuperClasses[6]) - 12 * sizeof(MCRegisterClass),
985 .SuperClassesSize: 1
986 },
987 {
988 offsetof(SystemZRegisterClassStorage, Regs[273]) - 13 * sizeof(MCRegisterClass),
989 offsetof(SystemZRegisterClassStorage, BitSets[51]) - 13 * sizeof(MCRegisterClass),
990 .NameIdx: 158,
991 .RegSizeInBits: 64,
992 .RegsSize: 32,
993 .RegSetBegin: 67, /* MinRegVal */
994 .RegSetSize: 32, /* RegSetSize */
995 .ID: SystemZ::VR64BitRegClassID,
996 .CopyCost: 1, /* CopyCost */
997 .Allocatable: true, /* Allocatable */
998 .BaseClass: false,
999 offsetof(SystemZRegisterClassStorage, SubClassMasks[35]) - 13 * sizeof(MCRegisterClass),
1000 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[0]) - 13 * sizeof(MCRegisterClass),
1001 .LaneMask: LaneBitmask(0x0000000000000001),
1002 .AllocationPriority: 0,
1003 .GlobalPriority: false,
1004 .TSFlags: 0x00, /* TSFlags */
1005 .SpillStackID: 0, /* SpillStackID */
1006 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1007 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1008 offsetof(SystemZRegisterClassStorage, SuperClasses[7]) - 13 * sizeof(MCRegisterClass),
1009 .SuperClassesSize: 0
1010 },
1011 {
1012 offsetof(SystemZRegisterClassStorage, Regs[305]) - 14 * sizeof(MCRegisterClass),
1013 offsetof(SystemZRegisterClassStorage, BitSets[55]) - 14 * sizeof(MCRegisterClass),
1014 .NameIdx: 0,
1015 .RegSizeInBits: 64,
1016 .RegsSize: 16,
1017 .RegSetBegin: 35, /* MinRegVal */
1018 .RegSetSize: 16, /* RegSetSize */
1019 .ID: SystemZ::AnyRegBit_with_subreg_h64RegClassID,
1020 .CopyCost: 1, /* CopyCost */
1021 .Allocatable: false, /* Allocatable */
1022 .BaseClass: false,
1023 offsetof(SystemZRegisterClassStorage, SubClassMasks[38]) - 14 * sizeof(MCRegisterClass),
1024 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[2]) - 14 * sizeof(MCRegisterClass),
1025 .LaneMask: LaneBitmask(0x0000000000000003),
1026 .AllocationPriority: 0,
1027 .GlobalPriority: false,
1028 .TSFlags: 0x00, /* TSFlags */
1029 .SpillStackID: 0, /* SpillStackID */
1030 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1031 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1032 offsetof(SystemZRegisterClassStorage, SuperClasses[7]) - 14 * sizeof(MCRegisterClass),
1033 .SuperClassesSize: 2
1034 },
1035 {
1036 offsetof(SystemZRegisterClassStorage, Regs[321]) - 15 * sizeof(MCRegisterClass),
1037 offsetof(SystemZRegisterClassStorage, BitSets[57]) - 15 * sizeof(MCRegisterClass),
1038 .NameIdx: 132,
1039 .RegSizeInBits: 64,
1040 .RegsSize: 16,
1041 .RegSetBegin: 19, /* MinRegVal */
1042 .RegSetSize: 16, /* RegSetSize */
1043 .ID: SystemZ::CR64BitRegClassID,
1044 .CopyCost: 1, /* CopyCost */
1045 .Allocatable: false, /* Allocatable */
1046 .BaseClass: false,
1047 offsetof(SystemZRegisterClassStorage, SubClassMasks[39]) - 15 * sizeof(MCRegisterClass),
1048 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[2]) - 15 * sizeof(MCRegisterClass),
1049 .LaneMask: LaneBitmask(0x0000000000000001),
1050 .AllocationPriority: 0,
1051 .GlobalPriority: false,
1052 .TSFlags: 0x00, /* TSFlags */
1053 .SpillStackID: 0, /* SpillStackID */
1054 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1055 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1056 offsetof(SystemZRegisterClassStorage, SuperClasses[9]) - 15 * sizeof(MCRegisterClass),
1057 .SuperClassesSize: 0
1058 },
1059 {
1060 offsetof(SystemZRegisterClassStorage, Regs[337]) - 16 * sizeof(MCRegisterClass),
1061 offsetof(SystemZRegisterClassStorage, BitSets[59]) - 16 * sizeof(MCRegisterClass),
1062 .NameIdx: 124,
1063 .RegSizeInBits: 64,
1064 .RegsSize: 16,
1065 .RegSetBegin: 67, /* MinRegVal */
1066 .RegSetSize: 16, /* RegSetSize */
1067 .ID: SystemZ::FP64BitRegClassID,
1068 .CopyCost: 1, /* CopyCost */
1069 .Allocatable: true, /* Allocatable */
1070 .BaseClass: false,
1071 offsetof(SystemZRegisterClassStorage, SubClassMasks[40]) - 16 * sizeof(MCRegisterClass),
1072 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[0]) - 16 * sizeof(MCRegisterClass),
1073 .LaneMask: LaneBitmask(0x0000000000000001),
1074 .AllocationPriority: 0,
1075 .GlobalPriority: false,
1076 .TSFlags: 0x00, /* TSFlags */
1077 .SpillStackID: 0, /* SpillStackID */
1078 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1079 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1080 offsetof(SystemZRegisterClassStorage, SuperClasses[9]) - 16 * sizeof(MCRegisterClass),
1081 .SuperClassesSize: 3
1082 },
1083 {
1084 offsetof(SystemZRegisterClassStorage, Regs[353]) - 17 * sizeof(MCRegisterClass),
1085 offsetof(SystemZRegisterClassStorage, BitSets[61]) - 17 * sizeof(MCRegisterClass),
1086 .NameIdx: 150,
1087 .RegSizeInBits: 64,
1088 .RegsSize: 16,
1089 .RegSetBegin: 171, /* MinRegVal */
1090 .RegSetSize: 16, /* RegSetSize */
1091 .ID: SystemZ::GR64BitRegClassID,
1092 .CopyCost: 1, /* CopyCost */
1093 .Allocatable: true, /* Allocatable */
1094 .BaseClass: false,
1095 offsetof(SystemZRegisterClassStorage, SubClassMasks[43]) - 17 * sizeof(MCRegisterClass),
1096 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[0]) - 17 * sizeof(MCRegisterClass),
1097 .LaneMask: LaneBitmask(0x0000000000000003),
1098 .AllocationPriority: 0,
1099 .GlobalPriority: false,
1100 .TSFlags: 0x00, /* TSFlags */
1101 .SpillStackID: 0, /* SpillStackID */
1102 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1103 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1104 offsetof(SystemZRegisterClassStorage, SuperClasses[12]) - 17 * sizeof(MCRegisterClass),
1105 .SuperClassesSize: 1
1106 },
1107 {
1108 offsetof(SystemZRegisterClassStorage, Regs[369]) - 18 * sizeof(MCRegisterClass),
1109 offsetof(SystemZRegisterClassStorage, BitSets[63]) - 18 * sizeof(MCRegisterClass),
1110 .NameIdx: 140,
1111 .RegSizeInBits: 64,
1112 .RegsSize: 15,
1113 .RegSetBegin: 172, /* MinRegVal */
1114 .RegSetSize: 15, /* RegSetSize */
1115 .ID: SystemZ::ADDR64BitRegClassID,
1116 .CopyCost: 1, /* CopyCost */
1117 .Allocatable: true, /* Allocatable */
1118 .BaseClass: false,
1119 offsetof(SystemZRegisterClassStorage, SubClassMasks[46]) - 18 * sizeof(MCRegisterClass),
1120 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[0]) - 18 * sizeof(MCRegisterClass),
1121 .LaneMask: LaneBitmask(0x0000000000000003),
1122 .AllocationPriority: 0,
1123 .GlobalPriority: false,
1124 .TSFlags: 0x00, /* TSFlags */
1125 .SpillStackID: 0, /* SpillStackID */
1126 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1127 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1128 offsetof(SystemZRegisterClassStorage, SuperClasses[13]) - 18 * sizeof(MCRegisterClass),
1129 .SuperClassesSize: 2
1130 },
1131 {
1132 offsetof(SystemZRegisterClassStorage, Regs[384]) - 19 * sizeof(MCRegisterClass),
1133 offsetof(SystemZRegisterClassStorage, BitSets[65]) - 19 * sizeof(MCRegisterClass),
1134 .NameIdx: 220,
1135 .RegSizeInBits: 128,
1136 .RegsSize: 32,
1137 .RegSetBegin: 35, /* MinRegVal */
1138 .RegSetSize: 32, /* RegSetSize */
1139 .ID: SystemZ::VR128BitRegClassID,
1140 .CopyCost: 1, /* CopyCost */
1141 .Allocatable: true, /* Allocatable */
1142 .BaseClass: false,
1143 offsetof(SystemZRegisterClassStorage, SubClassMasks[49]) - 19 * sizeof(MCRegisterClass),
1144 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[2]) - 19 * sizeof(MCRegisterClass),
1145 .LaneMask: LaneBitmask(0x0000000000000003),
1146 .AllocationPriority: 0,
1147 .GlobalPriority: false,
1148 .TSFlags: 0x00, /* TSFlags */
1149 .SpillStackID: 0, /* SpillStackID */
1150 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1151 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1152 offsetof(SystemZRegisterClassStorage, SuperClasses[15]) - 19 * sizeof(MCRegisterClass),
1153 .SuperClassesSize: 0
1154 },
1155 {
1156 offsetof(SystemZRegisterClassStorage, Regs[416]) - 20 * sizeof(MCRegisterClass),
1157 offsetof(SystemZRegisterClassStorage, BitSets[69]) - 20 * sizeof(MCRegisterClass),
1158 .NameIdx: 182,
1159 .RegSizeInBits: 128,
1160 .RegsSize: 16,
1161 .RegSetBegin: 35, /* MinRegVal */
1162 .RegSetSize: 16, /* RegSetSize */
1163 .ID: SystemZ::VF128BitRegClassID,
1164 .CopyCost: 1, /* CopyCost */
1165 .Allocatable: true, /* Allocatable */
1166 .BaseClass: false,
1167 offsetof(SystemZRegisterClassStorage, SubClassMasks[50]) - 20 * sizeof(MCRegisterClass),
1168 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[2]) - 20 * sizeof(MCRegisterClass),
1169 .LaneMask: LaneBitmask(0x0000000000000003),
1170 .AllocationPriority: 0,
1171 .GlobalPriority: false,
1172 .TSFlags: 0x00, /* TSFlags */
1173 .SpillStackID: 0, /* SpillStackID */
1174 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1175 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1176 offsetof(SystemZRegisterClassStorage, SuperClasses[15]) - 20 * sizeof(MCRegisterClass),
1177 .SuperClassesSize: 4
1178 },
1179 {
1180 offsetof(SystemZRegisterClassStorage, Regs[432]) - 21 * sizeof(MCRegisterClass),
1181 offsetof(SystemZRegisterClassStorage, BitSets[71]) - 21 * sizeof(MCRegisterClass),
1182 .NameIdx: 191,
1183 .RegSizeInBits: 128,
1184 .RegsSize: 8,
1185 .RegSetBegin: 131, /* MinRegVal */
1186 .RegSetSize: 8, /* RegSetSize */
1187 .ID: SystemZ::FP128BitRegClassID,
1188 .CopyCost: 1, /* CopyCost */
1189 .Allocatable: true, /* Allocatable */
1190 .BaseClass: false,
1191 offsetof(SystemZRegisterClassStorage, SubClassMasks[51]) - 21 * sizeof(MCRegisterClass),
1192 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[2]) - 21 * sizeof(MCRegisterClass),
1193 .LaneMask: LaneBitmask(0x000000000000000F),
1194 .AllocationPriority: 0,
1195 .GlobalPriority: false,
1196 .TSFlags: 0x00, /* TSFlags */
1197 .SpillStackID: 0, /* SpillStackID */
1198 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1199 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1200 offsetof(SystemZRegisterClassStorage, SuperClasses[19]) - 21 * sizeof(MCRegisterClass),
1201 .SuperClassesSize: 0
1202 },
1203 {
1204 offsetof(SystemZRegisterClassStorage, Regs[440]) - 22 * sizeof(MCRegisterClass),
1205 offsetof(SystemZRegisterClassStorage, BitSets[72]) - 22 * sizeof(MCRegisterClass),
1206 .NameIdx: 211,
1207 .RegSizeInBits: 128,
1208 .RegsSize: 8,
1209 .RegSetBegin: 219, /* MinRegVal */
1210 .RegSetSize: 8, /* RegSetSize */
1211 .ID: SystemZ::GR128BitRegClassID,
1212 .CopyCost: 1, /* CopyCost */
1213 .Allocatable: true, /* Allocatable */
1214 .BaseClass: false,
1215 offsetof(SystemZRegisterClassStorage, SubClassMasks[52]) - 22 * sizeof(MCRegisterClass),
1216 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[2]) - 22 * sizeof(MCRegisterClass),
1217 .LaneMask: LaneBitmask(0x000000000000000F),
1218 .AllocationPriority: 0,
1219 .GlobalPriority: false,
1220 .TSFlags: 0x00, /* TSFlags */
1221 .SpillStackID: 0, /* SpillStackID */
1222 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1223 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1224 offsetof(SystemZRegisterClassStorage, SuperClasses[19]) - 22 * sizeof(MCRegisterClass),
1225 .SuperClassesSize: 0
1226 },
1227 {
1228 offsetof(SystemZRegisterClassStorage, Regs[448]) - 23 * sizeof(MCRegisterClass),
1229 offsetof(SystemZRegisterClassStorage, BitSets[73]) - 23 * sizeof(MCRegisterClass),
1230 .NameIdx: 200,
1231 .RegSizeInBits: 128,
1232 .RegsSize: 7,
1233 .RegSetBegin: 220, /* MinRegVal */
1234 .RegSetSize: 7, /* RegSetSize */
1235 .ID: SystemZ::ADDR128BitRegClassID,
1236 .CopyCost: 1, /* CopyCost */
1237 .Allocatable: true, /* Allocatable */
1238 .BaseClass: false,
1239 offsetof(SystemZRegisterClassStorage, SubClassMasks[53]) - 23 * sizeof(MCRegisterClass),
1240 offsetof(SystemZRegisterClassStorage, SuperRegIdxSeqs[2]) - 23 * sizeof(MCRegisterClass),
1241 .LaneMask: LaneBitmask(0x000000000000000F),
1242 .AllocationPriority: 0,
1243 .GlobalPriority: false,
1244 .TSFlags: 0x00, /* TSFlags */
1245 .SpillStackID: 0, /* SpillStackID */
1246 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1247 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1248 offsetof(SystemZRegisterClassStorage, SuperClasses[19]) - 23 * sizeof(MCRegisterClass),
1249 .SuperClassesSize: 1
1250 },
1251 },
1252 .Regs: {
1253 /* 0 */ SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F16H, SystemZ::F17H, SystemZ::F18H, SystemZ::F19H, SystemZ::F20H, SystemZ::F21H, SystemZ::F22H, SystemZ::F23H, SystemZ::F24H, SystemZ::F25H, SystemZ::F26H, SystemZ::F27H, SystemZ::F28H, SystemZ::F29H, SystemZ::F30H, SystemZ::F31H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H,
1254 /* 32 */ SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H,
1255 /* 48 */ SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15L, SystemZ::R15H, SystemZ::R14L, SystemZ::R14H, SystemZ::R13L, SystemZ::R13H, SystemZ::R12L, SystemZ::R12H, SystemZ::R11L, SystemZ::R11H, SystemZ::R10L, SystemZ::R10H, SystemZ::R9L, SystemZ::R9H, SystemZ::R8L, SystemZ::R8H, SystemZ::R7L, SystemZ::R7H, SystemZ::R6L, SystemZ::R6H,
1256 /* 80 */ SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
1257 /* 112 */ SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3, SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7, SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11, SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15,
1258 /* 128 */ SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
1259 /* 144 */ SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L,
1260 /* 160 */ SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15H, SystemZ::R14H, SystemZ::R13H, SystemZ::R12H, SystemZ::R11H, SystemZ::R10H, SystemZ::R9H, SystemZ::R8H, SystemZ::R7H, SystemZ::R6H,
1261 /* 176 */ SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L,
1262 /* 191 */ SystemZ::CC,
1263 /* 192 */ SystemZ::FPC,
1264 /* 193 */ SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
1265 /* 241 */ SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
1266 /* 273 */ SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
1267 /* 305 */ SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
1268 /* 321 */ SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3, SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7, SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11, SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15,
1269 /* 337 */ SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
1270 /* 353 */ SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D,
1271 /* 369 */ SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D,
1272 /* 384 */ SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
1273 /* 416 */ SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
1274 /* 432 */ SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q,
1275 /* 440 */ SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q,
1276 /* 448 */ SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q,
1277 },
1278 .BitSets: {
1279 /* 0 */ 0xff, 0xff, 0xff, 0xff,
1280 /* 4 */ 0xff, 0xff,
1281 /* 6 */ 0xff, 0xff, 0xff, 0xff,
1282 /* 10 */ 0xff, 0xff, 0xff, 0xff,
1283 /* 14 */ 0xff, 0xff,
1284 /* 16 */ 0xff, 0xff,
1285 /* 18 */ 0xff, 0xff,
1286 /* 20 */ 0xff, 0xff,
1287 /* 22 */ 0xff, 0x7f,
1288 /* 24 */ 0x01,
1289 /* 25 */ 0x01,
1290 /* 26 */ 0xff, 0xff, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
1291 /* 45 */ 0xff, 0xff, 0x00, 0x00, 0xff, 0xff,
1292 /* 51 */ 0xff, 0xff, 0xff, 0xff,
1293 /* 55 */ 0xff, 0xff,
1294 /* 57 */ 0xff, 0xff,
1295 /* 59 */ 0xff, 0xff,
1296 /* 61 */ 0xff, 0xff,
1297 /* 63 */ 0xff, 0x7f,
1298 /* 65 */ 0xff, 0xff, 0xff, 0xff,
1299 /* 69 */ 0xff, 0xff,
1300 /* 71 */ 0xff,
1301 /* 72 */ 0xff,
1302 /* 73 */ 0x7f,
1303 },
1304 .SubClassMasks: {
1305 // 0 VR16Bit
1306 0x00000003,
1307 0x00397028, // subreg_h16
1308 0x00200000, // subreg_lh32_then_subreg_h16
1309 // 3 FP16Bit
1310 0x00000002,
1311 0x00315020, // subreg_h16
1312 0x00200000, // subreg_lh32_then_subreg_h16
1313 // 6 GRX32Bit
1314 0x000001c4,
1315 0x00c60000, // subreg_h32
1316 0x00c60000, // subreg_l32
1317 0x00c00000, // subreg_lh32
1318 0x00c00000, // subreg_ll32
1319 // 11 VR32Bit
1320 0x00000028,
1321 0x00397000, // subreg_h32
1322 0x00200000, // subreg_lh32
1323 // 14 AR32Bit
1324 0x00000010,
1325 // 15 FP32Bit
1326 0x00000020,
1327 0x00315000, // subreg_h32
1328 0x00200000, // subreg_lh32
1329 // 18 GR32Bit
1330 0x00000140,
1331 0x00c60000, // subreg_l32
1332 0x00c00000, // subreg_ll32
1333 // 21 GRH32Bit
1334 0x00000080,
1335 0x00c60000, // subreg_h32
1336 0x00c00000, // subreg_lh32
1337 // 24 ADDR32Bit
1338 0x00000100,
1339 0x00840000, // subreg_l32
1340 0x00c00000, // subreg_ll32
1341 // 27 CCR
1342 0x00000200,
1343 // 28 FPCRegs
1344 0x00000400,
1345 // 29 AnyRegBit
1346 0x00175800,
1347 0x00f04000, // subreg_h64
1348 0x00e00000, // subreg_l64
1349 // 32 AnyRegBit_with_subreg_h16
1350 0x00115000,
1351 0x00304000, // subreg_h64
1352 0x00200000, // subreg_l64
1353 // 35 VR64Bit
1354 0x00012000,
1355 0x00384000, // subreg_h64
1356 0x00200000, // subreg_l64
1357 // 38 AnyRegBit_with_subreg_h64
1358 0x00104000,
1359 // 39 CR64Bit
1360 0x00008000,
1361 // 40 FP64Bit
1362 0x00010000,
1363 0x00304000, // subreg_h64
1364 0x00200000, // subreg_l64
1365 // 43 GR64Bit
1366 0x00060000,
1367 0x00c00000, // subreg_h64
1368 0x00c00000, // subreg_l64
1369 // 46 ADDR64Bit
1370 0x00040000,
1371 0x00800000, // subreg_h64
1372 0x00c00000, // subreg_l64
1373 // 49 VR128Bit
1374 0x00180000,
1375 // 50 VF128Bit
1376 0x00100000,
1377 // 51 FP128Bit
1378 0x00200000,
1379 // 52 GR128Bit
1380 0x00c00000,
1381 // 53 ADDR128Bit
1382 0x00800000,
1383 },
1384 .SuperRegIdxSeqs: {
1385 /* 0 */ 3, 5, 0,
1386 /* 3 */ 2, 6, 0,
1387 /* 6 */ 4, 7, 0,
1388 /* 9 */ 2, 4, 6, 7, 0,
1389 /* 14 */ 1, 8, 0,
1390 },
1391 .SuperClasses: {
1392 /* 0 VR16Bit */
1393 /* 0 FP16Bit */ SystemZ::VR16BitRegClassID,
1394 /* 1 GRX32Bit */
1395 /* 1 VR32Bit */
1396 /* 1 AR32Bit */
1397 /* 1 FP32Bit */ SystemZ::VR32BitRegClassID,
1398 /* 2 GR32Bit */ SystemZ::GRX32BitRegClassID,
1399 /* 3 GRH32Bit */ SystemZ::GRX32BitRegClassID,
1400 /* 4 ADDR32Bit */ SystemZ::GRX32BitRegClassID, SystemZ::GR32BitRegClassID,
1401 /* 6 CCR */
1402 /* 6 FPCRegs */
1403 /* 6 AnyRegBit */
1404 /* 6 AnyRegBit_with_subreg_h16 */ SystemZ::AnyRegBitRegClassID,
1405 /* 7 VR64Bit */
1406 /* 7 AnyRegBit_with_subreg_h64 */ SystemZ::AnyRegBitRegClassID, SystemZ::AnyRegBit_with_subreg_h16RegClassID,
1407 /* 9 CR64Bit */
1408 /* 9 FP64Bit */ SystemZ::AnyRegBitRegClassID, SystemZ::AnyRegBit_with_subreg_h16RegClassID, SystemZ::VR64BitRegClassID,
1409 /* 12 GR64Bit */ SystemZ::AnyRegBitRegClassID,
1410 /* 13 ADDR64Bit */ SystemZ::AnyRegBitRegClassID, SystemZ::GR64BitRegClassID,
1411 /* 15 VR128Bit */
1412 /* 15 VF128Bit */ SystemZ::AnyRegBitRegClassID, SystemZ::AnyRegBit_with_subreg_h16RegClassID, SystemZ::AnyRegBit_with_subreg_h64RegClassID, SystemZ::VR128BitRegClassID,
1413 /* 19 FP128Bit */
1414 /* 19 GR128Bit */
1415 /* 19 ADDR128Bit */ SystemZ::GR128BitRegClassID,
1416 }
1417};
1418
1419const MCRegisterClass &getSystemZMCRegisterClass(unsigned RC) {
1420 return SystemZMCRegisterClassStorage.Classes[RC];
1421}
1422
1423// SystemZ Dwarf<->LLVM register mappings.
1424extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[] = {
1425 { .FromReg: 0U, .ToReg: SystemZ::R0D },
1426 { .FromReg: 1U, .ToReg: SystemZ::R1D },
1427 { .FromReg: 2U, .ToReg: SystemZ::R2D },
1428 { .FromReg: 3U, .ToReg: SystemZ::R3D },
1429 { .FromReg: 4U, .ToReg: SystemZ::R4D },
1430 { .FromReg: 5U, .ToReg: SystemZ::R5D },
1431 { .FromReg: 6U, .ToReg: SystemZ::R6D },
1432 { .FromReg: 7U, .ToReg: SystemZ::R7D },
1433 { .FromReg: 8U, .ToReg: SystemZ::R8D },
1434 { .FromReg: 9U, .ToReg: SystemZ::R9D },
1435 { .FromReg: 10U, .ToReg: SystemZ::R10D },
1436 { .FromReg: 11U, .ToReg: SystemZ::R11D },
1437 { .FromReg: 12U, .ToReg: SystemZ::R12D },
1438 { .FromReg: 13U, .ToReg: SystemZ::R13D },
1439 { .FromReg: 14U, .ToReg: SystemZ::R14D },
1440 { .FromReg: 15U, .ToReg: SystemZ::R15D },
1441 { .FromReg: 16U, .ToReg: SystemZ::F0D },
1442 { .FromReg: 17U, .ToReg: SystemZ::F2D },
1443 { .FromReg: 18U, .ToReg: SystemZ::F4D },
1444 { .FromReg: 19U, .ToReg: SystemZ::F6D },
1445 { .FromReg: 20U, .ToReg: SystemZ::F1D },
1446 { .FromReg: 21U, .ToReg: SystemZ::F3D },
1447 { .FromReg: 22U, .ToReg: SystemZ::F5D },
1448 { .FromReg: 23U, .ToReg: SystemZ::F7D },
1449 { .FromReg: 24U, .ToReg: SystemZ::F8D },
1450 { .FromReg: 25U, .ToReg: SystemZ::F10D },
1451 { .FromReg: 26U, .ToReg: SystemZ::F12D },
1452 { .FromReg: 27U, .ToReg: SystemZ::F14D },
1453 { .FromReg: 28U, .ToReg: SystemZ::F9D },
1454 { .FromReg: 29U, .ToReg: SystemZ::F11D },
1455 { .FromReg: 30U, .ToReg: SystemZ::F13D },
1456 { .FromReg: 31U, .ToReg: SystemZ::F15D },
1457 { .FromReg: 32U, .ToReg: SystemZ::C0 },
1458 { .FromReg: 33U, .ToReg: SystemZ::C1 },
1459 { .FromReg: 34U, .ToReg: SystemZ::C2 },
1460 { .FromReg: 35U, .ToReg: SystemZ::C3 },
1461 { .FromReg: 36U, .ToReg: SystemZ::C4 },
1462 { .FromReg: 37U, .ToReg: SystemZ::C5 },
1463 { .FromReg: 38U, .ToReg: SystemZ::C6 },
1464 { .FromReg: 39U, .ToReg: SystemZ::C7 },
1465 { .FromReg: 40U, .ToReg: SystemZ::C8 },
1466 { .FromReg: 41U, .ToReg: SystemZ::C9 },
1467 { .FromReg: 42U, .ToReg: SystemZ::C10 },
1468 { .FromReg: 43U, .ToReg: SystemZ::C11 },
1469 { .FromReg: 44U, .ToReg: SystemZ::C12 },
1470 { .FromReg: 45U, .ToReg: SystemZ::C13 },
1471 { .FromReg: 46U, .ToReg: SystemZ::C14 },
1472 { .FromReg: 47U, .ToReg: SystemZ::C15 },
1473 { .FromReg: 48U, .ToReg: SystemZ::A0 },
1474 { .FromReg: 49U, .ToReg: SystemZ::A1 },
1475 { .FromReg: 50U, .ToReg: SystemZ::A2 },
1476 { .FromReg: 51U, .ToReg: SystemZ::A3 },
1477 { .FromReg: 52U, .ToReg: SystemZ::A4 },
1478 { .FromReg: 53U, .ToReg: SystemZ::A5 },
1479 { .FromReg: 54U, .ToReg: SystemZ::A6 },
1480 { .FromReg: 55U, .ToReg: SystemZ::A7 },
1481 { .FromReg: 56U, .ToReg: SystemZ::A8 },
1482 { .FromReg: 57U, .ToReg: SystemZ::A9 },
1483 { .FromReg: 58U, .ToReg: SystemZ::A10 },
1484 { .FromReg: 59U, .ToReg: SystemZ::A11 },
1485 { .FromReg: 60U, .ToReg: SystemZ::A12 },
1486 { .FromReg: 61U, .ToReg: SystemZ::A13 },
1487 { .FromReg: 62U, .ToReg: SystemZ::A14 },
1488 { .FromReg: 63U, .ToReg: SystemZ::A15 },
1489 { .FromReg: 68U, .ToReg: SystemZ::F16D },
1490 { .FromReg: 69U, .ToReg: SystemZ::F18D },
1491 { .FromReg: 70U, .ToReg: SystemZ::F20D },
1492 { .FromReg: 71U, .ToReg: SystemZ::F22D },
1493 { .FromReg: 72U, .ToReg: SystemZ::F17D },
1494 { .FromReg: 73U, .ToReg: SystemZ::F19D },
1495 { .FromReg: 74U, .ToReg: SystemZ::F21D },
1496 { .FromReg: 75U, .ToReg: SystemZ::F23D },
1497 { .FromReg: 76U, .ToReg: SystemZ::F24D },
1498 { .FromReg: 77U, .ToReg: SystemZ::F26D },
1499 { .FromReg: 78U, .ToReg: SystemZ::F28D },
1500 { .FromReg: 79U, .ToReg: SystemZ::F30D },
1501 { .FromReg: 80U, .ToReg: SystemZ::F25D },
1502 { .FromReg: 81U, .ToReg: SystemZ::F27D },
1503 { .FromReg: 82U, .ToReg: SystemZ::F29D },
1504 { .FromReg: 83U, .ToReg: SystemZ::F31D },
1505};
1506extern const unsigned SystemZDwarfFlavour0Dwarf2LSize = std::size(SystemZDwarfFlavour0Dwarf2L);
1507
1508extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[] = {
1509 { .FromReg: 0U, .ToReg: SystemZ::R0D },
1510 { .FromReg: 1U, .ToReg: SystemZ::R1D },
1511 { .FromReg: 2U, .ToReg: SystemZ::R2D },
1512 { .FromReg: 3U, .ToReg: SystemZ::R3D },
1513 { .FromReg: 4U, .ToReg: SystemZ::R4D },
1514 { .FromReg: 5U, .ToReg: SystemZ::R5D },
1515 { .FromReg: 6U, .ToReg: SystemZ::R6D },
1516 { .FromReg: 7U, .ToReg: SystemZ::R7D },
1517 { .FromReg: 8U, .ToReg: SystemZ::R8D },
1518 { .FromReg: 9U, .ToReg: SystemZ::R9D },
1519 { .FromReg: 10U, .ToReg: SystemZ::R10D },
1520 { .FromReg: 11U, .ToReg: SystemZ::R11D },
1521 { .FromReg: 12U, .ToReg: SystemZ::R12D },
1522 { .FromReg: 13U, .ToReg: SystemZ::R13D },
1523 { .FromReg: 14U, .ToReg: SystemZ::R14D },
1524 { .FromReg: 15U, .ToReg: SystemZ::R15D },
1525 { .FromReg: 16U, .ToReg: SystemZ::F0D },
1526 { .FromReg: 17U, .ToReg: SystemZ::F2D },
1527 { .FromReg: 18U, .ToReg: SystemZ::F4D },
1528 { .FromReg: 19U, .ToReg: SystemZ::F6D },
1529 { .FromReg: 20U, .ToReg: SystemZ::F1D },
1530 { .FromReg: 21U, .ToReg: SystemZ::F3D },
1531 { .FromReg: 22U, .ToReg: SystemZ::F5D },
1532 { .FromReg: 23U, .ToReg: SystemZ::F7D },
1533 { .FromReg: 24U, .ToReg: SystemZ::F8D },
1534 { .FromReg: 25U, .ToReg: SystemZ::F10D },
1535 { .FromReg: 26U, .ToReg: SystemZ::F12D },
1536 { .FromReg: 27U, .ToReg: SystemZ::F14D },
1537 { .FromReg: 28U, .ToReg: SystemZ::F9D },
1538 { .FromReg: 29U, .ToReg: SystemZ::F11D },
1539 { .FromReg: 30U, .ToReg: SystemZ::F13D },
1540 { .FromReg: 31U, .ToReg: SystemZ::F15D },
1541 { .FromReg: 32U, .ToReg: SystemZ::C0 },
1542 { .FromReg: 33U, .ToReg: SystemZ::C1 },
1543 { .FromReg: 34U, .ToReg: SystemZ::C2 },
1544 { .FromReg: 35U, .ToReg: SystemZ::C3 },
1545 { .FromReg: 36U, .ToReg: SystemZ::C4 },
1546 { .FromReg: 37U, .ToReg: SystemZ::C5 },
1547 { .FromReg: 38U, .ToReg: SystemZ::C6 },
1548 { .FromReg: 39U, .ToReg: SystemZ::C7 },
1549 { .FromReg: 40U, .ToReg: SystemZ::C8 },
1550 { .FromReg: 41U, .ToReg: SystemZ::C9 },
1551 { .FromReg: 42U, .ToReg: SystemZ::C10 },
1552 { .FromReg: 43U, .ToReg: SystemZ::C11 },
1553 { .FromReg: 44U, .ToReg: SystemZ::C12 },
1554 { .FromReg: 45U, .ToReg: SystemZ::C13 },
1555 { .FromReg: 46U, .ToReg: SystemZ::C14 },
1556 { .FromReg: 47U, .ToReg: SystemZ::C15 },
1557 { .FromReg: 48U, .ToReg: SystemZ::A0 },
1558 { .FromReg: 49U, .ToReg: SystemZ::A1 },
1559 { .FromReg: 50U, .ToReg: SystemZ::A2 },
1560 { .FromReg: 51U, .ToReg: SystemZ::A3 },
1561 { .FromReg: 52U, .ToReg: SystemZ::A4 },
1562 { .FromReg: 53U, .ToReg: SystemZ::A5 },
1563 { .FromReg: 54U, .ToReg: SystemZ::A6 },
1564 { .FromReg: 55U, .ToReg: SystemZ::A7 },
1565 { .FromReg: 56U, .ToReg: SystemZ::A8 },
1566 { .FromReg: 57U, .ToReg: SystemZ::A9 },
1567 { .FromReg: 58U, .ToReg: SystemZ::A10 },
1568 { .FromReg: 59U, .ToReg: SystemZ::A11 },
1569 { .FromReg: 60U, .ToReg: SystemZ::A12 },
1570 { .FromReg: 61U, .ToReg: SystemZ::A13 },
1571 { .FromReg: 62U, .ToReg: SystemZ::A14 },
1572 { .FromReg: 63U, .ToReg: SystemZ::A15 },
1573 { .FromReg: 68U, .ToReg: SystemZ::F16D },
1574 { .FromReg: 69U, .ToReg: SystemZ::F18D },
1575 { .FromReg: 70U, .ToReg: SystemZ::F20D },
1576 { .FromReg: 71U, .ToReg: SystemZ::F22D },
1577 { .FromReg: 72U, .ToReg: SystemZ::F17D },
1578 { .FromReg: 73U, .ToReg: SystemZ::F19D },
1579 { .FromReg: 74U, .ToReg: SystemZ::F21D },
1580 { .FromReg: 75U, .ToReg: SystemZ::F23D },
1581 { .FromReg: 76U, .ToReg: SystemZ::F24D },
1582 { .FromReg: 77U, .ToReg: SystemZ::F26D },
1583 { .FromReg: 78U, .ToReg: SystemZ::F28D },
1584 { .FromReg: 79U, .ToReg: SystemZ::F30D },
1585 { .FromReg: 80U, .ToReg: SystemZ::F25D },
1586 { .FromReg: 81U, .ToReg: SystemZ::F27D },
1587 { .FromReg: 82U, .ToReg: SystemZ::F29D },
1588 { .FromReg: 83U, .ToReg: SystemZ::F31D },
1589};
1590extern const unsigned SystemZEHFlavour0Dwarf2LSize = std::size(SystemZEHFlavour0Dwarf2L);
1591
1592extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[] = {
1593 { .FromReg: SystemZ::A0, .ToReg: 48U },
1594 { .FromReg: SystemZ::A1, .ToReg: 49U },
1595 { .FromReg: SystemZ::A2, .ToReg: 50U },
1596 { .FromReg: SystemZ::A3, .ToReg: 51U },
1597 { .FromReg: SystemZ::A4, .ToReg: 52U },
1598 { .FromReg: SystemZ::A5, .ToReg: 53U },
1599 { .FromReg: SystemZ::A6, .ToReg: 54U },
1600 { .FromReg: SystemZ::A7, .ToReg: 55U },
1601 { .FromReg: SystemZ::A8, .ToReg: 56U },
1602 { .FromReg: SystemZ::A9, .ToReg: 57U },
1603 { .FromReg: SystemZ::A10, .ToReg: 58U },
1604 { .FromReg: SystemZ::A11, .ToReg: 59U },
1605 { .FromReg: SystemZ::A12, .ToReg: 60U },
1606 { .FromReg: SystemZ::A13, .ToReg: 61U },
1607 { .FromReg: SystemZ::A14, .ToReg: 62U },
1608 { .FromReg: SystemZ::A15, .ToReg: 63U },
1609 { .FromReg: SystemZ::C0, .ToReg: 32U },
1610 { .FromReg: SystemZ::C1, .ToReg: 33U },
1611 { .FromReg: SystemZ::C2, .ToReg: 34U },
1612 { .FromReg: SystemZ::C3, .ToReg: 35U },
1613 { .FromReg: SystemZ::C4, .ToReg: 36U },
1614 { .FromReg: SystemZ::C5, .ToReg: 37U },
1615 { .FromReg: SystemZ::C6, .ToReg: 38U },
1616 { .FromReg: SystemZ::C7, .ToReg: 39U },
1617 { .FromReg: SystemZ::C8, .ToReg: 40U },
1618 { .FromReg: SystemZ::C9, .ToReg: 41U },
1619 { .FromReg: SystemZ::C10, .ToReg: 42U },
1620 { .FromReg: SystemZ::C11, .ToReg: 43U },
1621 { .FromReg: SystemZ::C12, .ToReg: 44U },
1622 { .FromReg: SystemZ::C13, .ToReg: 45U },
1623 { .FromReg: SystemZ::C14, .ToReg: 46U },
1624 { .FromReg: SystemZ::C15, .ToReg: 47U },
1625 { .FromReg: SystemZ::V0, .ToReg: 16U },
1626 { .FromReg: SystemZ::V1, .ToReg: 20U },
1627 { .FromReg: SystemZ::V2, .ToReg: 17U },
1628 { .FromReg: SystemZ::V3, .ToReg: 21U },
1629 { .FromReg: SystemZ::V4, .ToReg: 18U },
1630 { .FromReg: SystemZ::V5, .ToReg: 22U },
1631 { .FromReg: SystemZ::V6, .ToReg: 19U },
1632 { .FromReg: SystemZ::V7, .ToReg: 23U },
1633 { .FromReg: SystemZ::V8, .ToReg: 24U },
1634 { .FromReg: SystemZ::V9, .ToReg: 28U },
1635 { .FromReg: SystemZ::V10, .ToReg: 25U },
1636 { .FromReg: SystemZ::V11, .ToReg: 29U },
1637 { .FromReg: SystemZ::V12, .ToReg: 26U },
1638 { .FromReg: SystemZ::V13, .ToReg: 30U },
1639 { .FromReg: SystemZ::V14, .ToReg: 27U },
1640 { .FromReg: SystemZ::V15, .ToReg: 31U },
1641 { .FromReg: SystemZ::V16, .ToReg: 68U },
1642 { .FromReg: SystemZ::V17, .ToReg: 72U },
1643 { .FromReg: SystemZ::V18, .ToReg: 69U },
1644 { .FromReg: SystemZ::V19, .ToReg: 73U },
1645 { .FromReg: SystemZ::V20, .ToReg: 70U },
1646 { .FromReg: SystemZ::V21, .ToReg: 74U },
1647 { .FromReg: SystemZ::V22, .ToReg: 71U },
1648 { .FromReg: SystemZ::V23, .ToReg: 75U },
1649 { .FromReg: SystemZ::V24, .ToReg: 76U },
1650 { .FromReg: SystemZ::V25, .ToReg: 80U },
1651 { .FromReg: SystemZ::V26, .ToReg: 77U },
1652 { .FromReg: SystemZ::V27, .ToReg: 81U },
1653 { .FromReg: SystemZ::V28, .ToReg: 78U },
1654 { .FromReg: SystemZ::V29, .ToReg: 82U },
1655 { .FromReg: SystemZ::V30, .ToReg: 79U },
1656 { .FromReg: SystemZ::V31, .ToReg: 83U },
1657 { .FromReg: SystemZ::F0D, .ToReg: 16U },
1658 { .FromReg: SystemZ::F1D, .ToReg: 20U },
1659 { .FromReg: SystemZ::F2D, .ToReg: 17U },
1660 { .FromReg: SystemZ::F3D, .ToReg: 21U },
1661 { .FromReg: SystemZ::F4D, .ToReg: 18U },
1662 { .FromReg: SystemZ::F5D, .ToReg: 22U },
1663 { .FromReg: SystemZ::F6D, .ToReg: 19U },
1664 { .FromReg: SystemZ::F7D, .ToReg: 23U },
1665 { .FromReg: SystemZ::F8D, .ToReg: 24U },
1666 { .FromReg: SystemZ::F9D, .ToReg: 28U },
1667 { .FromReg: SystemZ::F10D, .ToReg: 25U },
1668 { .FromReg: SystemZ::F11D, .ToReg: 29U },
1669 { .FromReg: SystemZ::F12D, .ToReg: 26U },
1670 { .FromReg: SystemZ::F13D, .ToReg: 30U },
1671 { .FromReg: SystemZ::F14D, .ToReg: 27U },
1672 { .FromReg: SystemZ::F15D, .ToReg: 31U },
1673 { .FromReg: SystemZ::F16D, .ToReg: 68U },
1674 { .FromReg: SystemZ::F17D, .ToReg: 72U },
1675 { .FromReg: SystemZ::F18D, .ToReg: 69U },
1676 { .FromReg: SystemZ::F19D, .ToReg: 73U },
1677 { .FromReg: SystemZ::F20D, .ToReg: 70U },
1678 { .FromReg: SystemZ::F21D, .ToReg: 74U },
1679 { .FromReg: SystemZ::F22D, .ToReg: 71U },
1680 { .FromReg: SystemZ::F23D, .ToReg: 75U },
1681 { .FromReg: SystemZ::F24D, .ToReg: 76U },
1682 { .FromReg: SystemZ::F25D, .ToReg: 80U },
1683 { .FromReg: SystemZ::F26D, .ToReg: 77U },
1684 { .FromReg: SystemZ::F27D, .ToReg: 81U },
1685 { .FromReg: SystemZ::F28D, .ToReg: 78U },
1686 { .FromReg: SystemZ::F29D, .ToReg: 82U },
1687 { .FromReg: SystemZ::F30D, .ToReg: 79U },
1688 { .FromReg: SystemZ::F31D, .ToReg: 83U },
1689 { .FromReg: SystemZ::R0D, .ToReg: 0U },
1690 { .FromReg: SystemZ::R1D, .ToReg: 1U },
1691 { .FromReg: SystemZ::R2D, .ToReg: 2U },
1692 { .FromReg: SystemZ::R3D, .ToReg: 3U },
1693 { .FromReg: SystemZ::R4D, .ToReg: 4U },
1694 { .FromReg: SystemZ::R5D, .ToReg: 5U },
1695 { .FromReg: SystemZ::R6D, .ToReg: 6U },
1696 { .FromReg: SystemZ::R7D, .ToReg: 7U },
1697 { .FromReg: SystemZ::R8D, .ToReg: 8U },
1698 { .FromReg: SystemZ::R9D, .ToReg: 9U },
1699 { .FromReg: SystemZ::R10D, .ToReg: 10U },
1700 { .FromReg: SystemZ::R11D, .ToReg: 11U },
1701 { .FromReg: SystemZ::R12D, .ToReg: 12U },
1702 { .FromReg: SystemZ::R13D, .ToReg: 13U },
1703 { .FromReg: SystemZ::R14D, .ToReg: 14U },
1704 { .FromReg: SystemZ::R15D, .ToReg: 15U },
1705};
1706extern const unsigned SystemZDwarfFlavour0L2DwarfSize = std::size(SystemZDwarfFlavour0L2Dwarf);
1707
1708extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[] = {
1709 { .FromReg: SystemZ::A0, .ToReg: 48U },
1710 { .FromReg: SystemZ::A1, .ToReg: 49U },
1711 { .FromReg: SystemZ::A2, .ToReg: 50U },
1712 { .FromReg: SystemZ::A3, .ToReg: 51U },
1713 { .FromReg: SystemZ::A4, .ToReg: 52U },
1714 { .FromReg: SystemZ::A5, .ToReg: 53U },
1715 { .FromReg: SystemZ::A6, .ToReg: 54U },
1716 { .FromReg: SystemZ::A7, .ToReg: 55U },
1717 { .FromReg: SystemZ::A8, .ToReg: 56U },
1718 { .FromReg: SystemZ::A9, .ToReg: 57U },
1719 { .FromReg: SystemZ::A10, .ToReg: 58U },
1720 { .FromReg: SystemZ::A11, .ToReg: 59U },
1721 { .FromReg: SystemZ::A12, .ToReg: 60U },
1722 { .FromReg: SystemZ::A13, .ToReg: 61U },
1723 { .FromReg: SystemZ::A14, .ToReg: 62U },
1724 { .FromReg: SystemZ::A15, .ToReg: 63U },
1725 { .FromReg: SystemZ::C0, .ToReg: 32U },
1726 { .FromReg: SystemZ::C1, .ToReg: 33U },
1727 { .FromReg: SystemZ::C2, .ToReg: 34U },
1728 { .FromReg: SystemZ::C3, .ToReg: 35U },
1729 { .FromReg: SystemZ::C4, .ToReg: 36U },
1730 { .FromReg: SystemZ::C5, .ToReg: 37U },
1731 { .FromReg: SystemZ::C6, .ToReg: 38U },
1732 { .FromReg: SystemZ::C7, .ToReg: 39U },
1733 { .FromReg: SystemZ::C8, .ToReg: 40U },
1734 { .FromReg: SystemZ::C9, .ToReg: 41U },
1735 { .FromReg: SystemZ::C10, .ToReg: 42U },
1736 { .FromReg: SystemZ::C11, .ToReg: 43U },
1737 { .FromReg: SystemZ::C12, .ToReg: 44U },
1738 { .FromReg: SystemZ::C13, .ToReg: 45U },
1739 { .FromReg: SystemZ::C14, .ToReg: 46U },
1740 { .FromReg: SystemZ::C15, .ToReg: 47U },
1741 { .FromReg: SystemZ::V0, .ToReg: 16U },
1742 { .FromReg: SystemZ::V1, .ToReg: 20U },
1743 { .FromReg: SystemZ::V2, .ToReg: 17U },
1744 { .FromReg: SystemZ::V3, .ToReg: 21U },
1745 { .FromReg: SystemZ::V4, .ToReg: 18U },
1746 { .FromReg: SystemZ::V5, .ToReg: 22U },
1747 { .FromReg: SystemZ::V6, .ToReg: 19U },
1748 { .FromReg: SystemZ::V7, .ToReg: 23U },
1749 { .FromReg: SystemZ::V8, .ToReg: 24U },
1750 { .FromReg: SystemZ::V9, .ToReg: 28U },
1751 { .FromReg: SystemZ::V10, .ToReg: 25U },
1752 { .FromReg: SystemZ::V11, .ToReg: 29U },
1753 { .FromReg: SystemZ::V12, .ToReg: 26U },
1754 { .FromReg: SystemZ::V13, .ToReg: 30U },
1755 { .FromReg: SystemZ::V14, .ToReg: 27U },
1756 { .FromReg: SystemZ::V15, .ToReg: 31U },
1757 { .FromReg: SystemZ::V16, .ToReg: 68U },
1758 { .FromReg: SystemZ::V17, .ToReg: 72U },
1759 { .FromReg: SystemZ::V18, .ToReg: 69U },
1760 { .FromReg: SystemZ::V19, .ToReg: 73U },
1761 { .FromReg: SystemZ::V20, .ToReg: 70U },
1762 { .FromReg: SystemZ::V21, .ToReg: 74U },
1763 { .FromReg: SystemZ::V22, .ToReg: 71U },
1764 { .FromReg: SystemZ::V23, .ToReg: 75U },
1765 { .FromReg: SystemZ::V24, .ToReg: 76U },
1766 { .FromReg: SystemZ::V25, .ToReg: 80U },
1767 { .FromReg: SystemZ::V26, .ToReg: 77U },
1768 { .FromReg: SystemZ::V27, .ToReg: 81U },
1769 { .FromReg: SystemZ::V28, .ToReg: 78U },
1770 { .FromReg: SystemZ::V29, .ToReg: 82U },
1771 { .FromReg: SystemZ::V30, .ToReg: 79U },
1772 { .FromReg: SystemZ::V31, .ToReg: 83U },
1773 { .FromReg: SystemZ::F0D, .ToReg: 16U },
1774 { .FromReg: SystemZ::F1D, .ToReg: 20U },
1775 { .FromReg: SystemZ::F2D, .ToReg: 17U },
1776 { .FromReg: SystemZ::F3D, .ToReg: 21U },
1777 { .FromReg: SystemZ::F4D, .ToReg: 18U },
1778 { .FromReg: SystemZ::F5D, .ToReg: 22U },
1779 { .FromReg: SystemZ::F6D, .ToReg: 19U },
1780 { .FromReg: SystemZ::F7D, .ToReg: 23U },
1781 { .FromReg: SystemZ::F8D, .ToReg: 24U },
1782 { .FromReg: SystemZ::F9D, .ToReg: 28U },
1783 { .FromReg: SystemZ::F10D, .ToReg: 25U },
1784 { .FromReg: SystemZ::F11D, .ToReg: 29U },
1785 { .FromReg: SystemZ::F12D, .ToReg: 26U },
1786 { .FromReg: SystemZ::F13D, .ToReg: 30U },
1787 { .FromReg: SystemZ::F14D, .ToReg: 27U },
1788 { .FromReg: SystemZ::F15D, .ToReg: 31U },
1789 { .FromReg: SystemZ::F16D, .ToReg: 68U },
1790 { .FromReg: SystemZ::F17D, .ToReg: 72U },
1791 { .FromReg: SystemZ::F18D, .ToReg: 69U },
1792 { .FromReg: SystemZ::F19D, .ToReg: 73U },
1793 { .FromReg: SystemZ::F20D, .ToReg: 70U },
1794 { .FromReg: SystemZ::F21D, .ToReg: 74U },
1795 { .FromReg: SystemZ::F22D, .ToReg: 71U },
1796 { .FromReg: SystemZ::F23D, .ToReg: 75U },
1797 { .FromReg: SystemZ::F24D, .ToReg: 76U },
1798 { .FromReg: SystemZ::F25D, .ToReg: 80U },
1799 { .FromReg: SystemZ::F26D, .ToReg: 77U },
1800 { .FromReg: SystemZ::F27D, .ToReg: 81U },
1801 { .FromReg: SystemZ::F28D, .ToReg: 78U },
1802 { .FromReg: SystemZ::F29D, .ToReg: 82U },
1803 { .FromReg: SystemZ::F30D, .ToReg: 79U },
1804 { .FromReg: SystemZ::F31D, .ToReg: 83U },
1805 { .FromReg: SystemZ::R0D, .ToReg: 0U },
1806 { .FromReg: SystemZ::R1D, .ToReg: 1U },
1807 { .FromReg: SystemZ::R2D, .ToReg: 2U },
1808 { .FromReg: SystemZ::R3D, .ToReg: 3U },
1809 { .FromReg: SystemZ::R4D, .ToReg: 4U },
1810 { .FromReg: SystemZ::R5D, .ToReg: 5U },
1811 { .FromReg: SystemZ::R6D, .ToReg: 6U },
1812 { .FromReg: SystemZ::R7D, .ToReg: 7U },
1813 { .FromReg: SystemZ::R8D, .ToReg: 8U },
1814 { .FromReg: SystemZ::R9D, .ToReg: 9U },
1815 { .FromReg: SystemZ::R10D, .ToReg: 10U },
1816 { .FromReg: SystemZ::R11D, .ToReg: 11U },
1817 { .FromReg: SystemZ::R12D, .ToReg: 12U },
1818 { .FromReg: SystemZ::R13D, .ToReg: 13U },
1819 { .FromReg: SystemZ::R14D, .ToReg: 14U },
1820 { .FromReg: SystemZ::R15D, .ToReg: 15U },
1821};
1822extern const unsigned SystemZEHFlavour0L2DwarfSize = std::size(SystemZEHFlavour0L2Dwarf);
1823
1824extern const uint16_t SystemZRegEncodingTable[] = {
1825 0,
1826 0,
1827 0,
1828 0,
1829 1,
1830 2,
1831 3,
1832 4,
1833 5,
1834 6,
1835 7,
1836 8,
1837 9,
1838 10,
1839 11,
1840 12,
1841 13,
1842 14,
1843 15,
1844 0,
1845 1,
1846 2,
1847 3,
1848 4,
1849 5,
1850 6,
1851 7,
1852 8,
1853 9,
1854 10,
1855 11,
1856 12,
1857 13,
1858 14,
1859 15,
1860 0,
1861 1,
1862 2,
1863 3,
1864 4,
1865 5,
1866 6,
1867 7,
1868 8,
1869 9,
1870 10,
1871 11,
1872 12,
1873 13,
1874 14,
1875 15,
1876 16,
1877 17,
1878 18,
1879 19,
1880 20,
1881 21,
1882 22,
1883 23,
1884 24,
1885 25,
1886 26,
1887 27,
1888 28,
1889 29,
1890 30,
1891 31,
1892 0,
1893 1,
1894 2,
1895 3,
1896 4,
1897 5,
1898 6,
1899 7,
1900 8,
1901 9,
1902 10,
1903 11,
1904 12,
1905 13,
1906 14,
1907 15,
1908 16,
1909 17,
1910 18,
1911 19,
1912 20,
1913 21,
1914 22,
1915 23,
1916 24,
1917 25,
1918 26,
1919 27,
1920 28,
1921 29,
1922 30,
1923 31,
1924 0,
1925 1,
1926 2,
1927 3,
1928 4,
1929 5,
1930 6,
1931 7,
1932 8,
1933 9,
1934 10,
1935 11,
1936 12,
1937 13,
1938 14,
1939 15,
1940 16,
1941 17,
1942 18,
1943 19,
1944 20,
1945 21,
1946 22,
1947 23,
1948 24,
1949 25,
1950 26,
1951 27,
1952 28,
1953 29,
1954 30,
1955 31,
1956 0,
1957 1,
1958 4,
1959 5,
1960 8,
1961 9,
1962 12,
1963 13,
1964 0,
1965 1,
1966 2,
1967 3,
1968 4,
1969 5,
1970 6,
1971 7,
1972 8,
1973 9,
1974 10,
1975 11,
1976 12,
1977 13,
1978 14,
1979 15,
1980 16,
1981 17,
1982 18,
1983 19,
1984 20,
1985 21,
1986 22,
1987 23,
1988 24,
1989 25,
1990 26,
1991 27,
1992 28,
1993 29,
1994 30,
1995 31,
1996 0,
1997 1,
1998 2,
1999 3,
2000 4,
2001 5,
2002 6,
2003 7,
2004 8,
2005 9,
2006 10,
2007 11,
2008 12,
2009 13,
2010 14,
2011 15,
2012 0,
2013 1,
2014 2,
2015 3,
2016 4,
2017 5,
2018 6,
2019 7,
2020 8,
2021 9,
2022 10,
2023 11,
2024 12,
2025 13,
2026 14,
2027 15,
2028 0,
2029 1,
2030 2,
2031 3,
2032 4,
2033 5,
2034 6,
2035 7,
2036 8,
2037 9,
2038 10,
2039 11,
2040 12,
2041 13,
2042 14,
2043 15,
2044 0,
2045 2,
2046 4,
2047 6,
2048 8,
2049 10,
2050 12,
2051 14,
2052};
2053static inline void InitSystemZMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
2054 RI->InitMCRegisterInfo(D: SystemZRegDesc, NR: 227, RA, PC, C: SystemZMCRegisterClassStorage.Classes, NC: 24, RURoots: SystemZRegUnitRoots, NRU: 98, DL: SystemZRegDiffLists, RUMS: SystemZLaneMaskLists, Strings: SystemZRegStrings, ClassStrings: SystemZRegClassStrings, SubIndices: SystemZSubRegIdxLists, NumIndices: 9,
2055RET: SystemZRegEncodingTable, RUI: nullptr);
2056
2057 switch (DwarfFlavour) {
2058 default:
2059 llvm_unreachable("Unknown DWARF flavour");
2060 case 0:
2061 RI->mapDwarfRegsToLLVMRegs(Map: SystemZDwarfFlavour0Dwarf2L, Size: SystemZDwarfFlavour0Dwarf2LSize, isEH: false);
2062 break;
2063 }
2064 switch (EHFlavour) {
2065 default:
2066 llvm_unreachable("Unknown DWARF flavour");
2067 case 0:
2068 RI->mapDwarfRegsToLLVMRegs(Map: SystemZEHFlavour0Dwarf2L, Size: SystemZEHFlavour0Dwarf2LSize, isEH: true);
2069 break;
2070 }
2071 switch (DwarfFlavour) {
2072 default:
2073 llvm_unreachable("Unknown DWARF flavour");
2074 case 0:
2075 RI->mapLLVMRegsToDwarfRegs(Map: SystemZDwarfFlavour0L2Dwarf, Size: SystemZDwarfFlavour0L2DwarfSize, isEH: false);
2076 break;
2077 }
2078 switch (EHFlavour) {
2079 default:
2080 llvm_unreachable("Unknown DWARF flavour");
2081 case 0:
2082 RI->mapLLVMRegsToDwarfRegs(Map: SystemZEHFlavour0L2Dwarf, Size: SystemZEHFlavour0L2DwarfSize, isEH: true);
2083 break;
2084 }
2085}
2086
2087
2088} // namespace llvm
2089