1//===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "SystemZMCTargetDesc.h"
10#include "SystemZGNUInstPrinter.h"
11#include "SystemZHLASMAsmStreamer.h"
12#include "SystemZHLASMInstPrinter.h"
13#include "SystemZMCAsmInfo.h"
14#include "SystemZTargetStreamer.h"
15#include "TargetInfo/SystemZTargetInfo.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDwarf.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstrAnalysis.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCStreamer.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Support/Compiler.h"
26
27using namespace llvm;
28
29#define GET_INSTRINFO_MC_DESC
30#define ENABLE_INSTR_PREDICATE_VERIFIER
31#include "SystemZGenInstrInfo.inc"
32
33#define GET_SUBTARGETINFO_MC_DESC
34#include "SystemZGenSubtargetInfo.inc"
35
36#define GET_REGINFO_MC_DESC
37#include "SystemZGenRegisterInfo.inc"
38
39const unsigned SystemZMC::GR32Regs[16] = {
40 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
41 SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
42 SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L,
43 SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L};
44
45const unsigned SystemZMC::GRH32Regs[16] = {
46 SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H,
47 SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H,
48 SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H,
49 SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H};
50
51const unsigned SystemZMC::GR64Regs[16] = {
52 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D,
53 SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D,
54 SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D,
55 SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D};
56
57const unsigned SystemZMC::GR128Regs[16] = {
58 SystemZ::R0Q, 0, SystemZ::R2Q, 0, SystemZ::R4Q, 0, SystemZ::R6Q, 0,
59 SystemZ::R8Q, 0, SystemZ::R10Q, 0, SystemZ::R12Q, 0, SystemZ::R14Q, 0};
60
61const unsigned SystemZMC::FP16Regs[16] = {
62 SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H,
63 SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H,
64 SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H,
65 SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H};
66
67const unsigned SystemZMC::FP32Regs[16] = {
68 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
69 SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
70 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
71 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S};
72
73const unsigned SystemZMC::FP64Regs[16] = {
74 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
75 SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
76 SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
77 SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D};
78
79const unsigned SystemZMC::FP128Regs[16] = {
80 SystemZ::F0Q, SystemZ::F1Q, 0, 0, SystemZ::F4Q, SystemZ::F5Q, 0, 0,
81 SystemZ::F8Q, SystemZ::F9Q, 0, 0, SystemZ::F12Q, SystemZ::F13Q, 0, 0};
82
83const unsigned SystemZMC::VR16Regs[32] = {
84 SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H,
85 SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F8H, SystemZ::F9H,
86 SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H,
87 SystemZ::F15H, SystemZ::F16H, SystemZ::F17H, SystemZ::F18H, SystemZ::F19H,
88 SystemZ::F20H, SystemZ::F21H, SystemZ::F22H, SystemZ::F23H, SystemZ::F24H,
89 SystemZ::F25H, SystemZ::F26H, SystemZ::F27H, SystemZ::F28H, SystemZ::F29H,
90 SystemZ::F30H, SystemZ::F31H};
91
92const unsigned SystemZMC::VR32Regs[32] = {
93 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S,
94 SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S,
95 SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S,
96 SystemZ::F15S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S,
97 SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S,
98 SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S,
99 SystemZ::F30S, SystemZ::F31S};
100
101const unsigned SystemZMC::VR64Regs[32] = {
102 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D,
103 SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D,
104 SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D,
105 SystemZ::F15D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D,
106 SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D,
107 SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D,
108 SystemZ::F30D, SystemZ::F31D};
109
110const unsigned SystemZMC::VR128Regs[32] = {
111 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4,
112 SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9,
113 SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14,
114 SystemZ::V15, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19,
115 SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24,
116 SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29,
117 SystemZ::V30, SystemZ::V31};
118
119const unsigned SystemZMC::AR32Regs[16] = {
120 SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3,
121 SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7,
122 SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11,
123 SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15};
124
125const unsigned SystemZMC::CR64Regs[16] = {
126 SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3,
127 SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7,
128 SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11,
129 SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15};
130
131unsigned SystemZMC::getFirstReg(unsigned Reg) {
132 static unsigned Map[SystemZ::NUM_TARGET_REGS];
133 static bool Initialized = false;
134 if (!Initialized) {
135 for (unsigned I = 0; I < 16; ++I) {
136 Map[GR32Regs[I]] = I;
137 Map[GRH32Regs[I]] = I;
138 Map[GR64Regs[I]] = I;
139 Map[GR128Regs[I]] = I;
140 Map[FP128Regs[I]] = I;
141 Map[AR32Regs[I]] = I;
142 }
143 for (unsigned I = 0; I < 32; ++I) {
144 Map[VR16Regs[I]] = I;
145 Map[VR32Regs[I]] = I;
146 Map[VR64Regs[I]] = I;
147 Map[VR128Regs[I]] = I;
148 }
149 }
150 assert(Reg < SystemZ::NUM_TARGET_REGS);
151 return Map[Reg];
152}
153
154static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
155 const Triple &TT,
156 const MCTargetOptions &Options) {
157 if (TT.isOSzOS())
158 return new SystemZMCAsmInfoGOFF(TT, Options);
159
160 MCAsmInfo *MAI = new SystemZMCAsmInfoELF(TT, Options);
161 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
162 L: nullptr, Register: MRI.getDwarfRegNum(Reg: SystemZ::R15D, isEH: true),
163 Offset: SystemZMC::ELFCFAOffsetFromInitialSP);
164 MAI->addInitialFrameState(Inst);
165 return MAI;
166}
167
168static MCInstrInfo *createSystemZMCInstrInfo() {
169 MCInstrInfo *X = new MCInstrInfo();
170 InitSystemZMCInstrInfo(II: X);
171 return X;
172}
173
174static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) {
175 MCRegisterInfo *X = new MCRegisterInfo();
176 InitSystemZMCRegisterInfo(RI: X, RA: SystemZ::R14D);
177 return X;
178}
179
180static MCSubtargetInfo *
181createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
182 return createSystemZMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
183}
184
185static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
186 unsigned SyntaxVariant,
187 const MCAsmInfo &MAI,
188 const MCInstrInfo &MII,
189 const MCRegisterInfo &MRI) {
190 if (SyntaxVariant == AD_HLASM)
191 return new SystemZHLASMInstPrinter(MAI, MII, MRI);
192
193 return new SystemZGNUInstPrinter(MAI, MII, MRI);
194}
195
196static MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
197 formatted_raw_ostream &OS,
198 MCInstPrinter *InstPrint) {
199 if (S.getContext().getTargetTriple().isOSzOS())
200 return new SystemZTargetHLASMStreamer(S, OS);
201 else
202 return new SystemZTargetGNUStreamer(S, OS);
203}
204
205static MCStreamer *createSystemZAsmStreamer(
206 MCContext &Ctx, std::unique_ptr<formatted_raw_ostream> OS,
207 std::unique_ptr<MCInstPrinter> IP, std::unique_ptr<MCCodeEmitter> CE,
208 std::unique_ptr<MCAsmBackend> TAB) {
209
210 auto TT = Ctx.getTargetTriple();
211 if (TT.isOSzOS())
212 return new SystemZHLASMAsmStreamer(Ctx, std::move(OS), std::move(IP),
213 std::move(CE), std::move(TAB));
214
215 return llvm::createAsmStreamer(Ctx, OS: std::move(OS), InstPrint: std::move(IP),
216 CE: std::move(CE), TAB: std::move(TAB));
217}
218
219static MCTargetStreamer *
220createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
221 if (S.getContext().getTargetTriple().isOSzOS())
222 return new SystemZTargetGOFFStreamer(S);
223 else
224 return new SystemZTargetELFStreamer(S);
225}
226
227static MCTargetStreamer *
228createNullTargetStreamer(MCStreamer &S) {
229 return new SystemZTargetStreamer(S);
230}
231
232static MCInstrAnalysis *createSystemZMCInstrAnalysis(const MCInstrInfo *Info) {
233 return new MCInstrAnalysis(Info);
234}
235
236extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
237LLVMInitializeSystemZTargetMC() {
238 // Register the MCAsmInfo.
239 TargetRegistry::RegisterMCAsmInfo(T&: getTheSystemZTarget(),
240 Fn: createSystemZMCAsmInfo);
241
242 // Register the MCCodeEmitter.
243 TargetRegistry::RegisterMCCodeEmitter(T&: getTheSystemZTarget(),
244 Fn: createSystemZMCCodeEmitter);
245
246 // Register the MCInstrInfo.
247 TargetRegistry::RegisterMCInstrInfo(T&: getTheSystemZTarget(),
248 Fn: createSystemZMCInstrInfo);
249
250 // Register the MCRegisterInfo.
251 TargetRegistry::RegisterMCRegInfo(T&: getTheSystemZTarget(),
252 Fn: createSystemZMCRegisterInfo);
253
254 // Register the MCSubtargetInfo.
255 TargetRegistry::RegisterMCSubtargetInfo(T&: getTheSystemZTarget(),
256 Fn: createSystemZMCSubtargetInfo);
257
258 // Register the MCAsmBackend.
259 TargetRegistry::RegisterMCAsmBackend(T&: getTheSystemZTarget(),
260 Fn: createSystemZMCAsmBackend);
261
262 // Register the MCInstPrinter.
263 TargetRegistry::RegisterMCInstPrinter(T&: getTheSystemZTarget(),
264 Fn: createSystemZMCInstPrinter);
265
266 // Register the asm streamer.
267 TargetRegistry::RegisterAsmStreamer(T&: getTheSystemZTarget(),
268 Fn: createSystemZAsmStreamer);
269
270 // Register the asm target streamer.
271 TargetRegistry::RegisterAsmTargetStreamer(T&: getTheSystemZTarget(),
272 Fn: createAsmTargetStreamer);
273
274 // Register the obj streamer
275 TargetRegistry::RegisterObjectTargetStreamer(T&: getTheSystemZTarget(),
276 Fn: createObjectTargetStreamer);
277
278 // Register the null streamer
279 TargetRegistry::RegisterNullTargetStreamer(T&: getTheSystemZTarget(),
280 Fn: createNullTargetStreamer);
281
282 // Register the MCInstrAnalysis.
283 TargetRegistry::RegisterMCInstrAnalysis(T&: getTheSystemZTarget(),
284 Fn: createSystemZMCInstrAnalysis);
285}
286