1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass SystemZMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f16, MVT::Other,
17 /* 6 */ MVT::f32, MVT::Other,
18 /* 8 */ MVT::f64, MVT::Other,
19 /* 10 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::i128, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
20 /* 20 */ MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
21 /* 24 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v2f32, MVT::Other,
22 /* 31 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::Other,
23 /* 39 */ MVT::Untyped, MVT::Other,
24};
25
26#ifdef __GNUC__
27#pragma GCC diagnostic push
28#pragma GCC diagnostic ignored "-Woverlength-strings"
29#endif
30static constexpr char SystemZSubRegIndexStrings[] = {
31 /* 0 */ "subreg_h32\000"
32 /* 11 */ "subreg_lh32\000"
33 /* 23 */ "subreg_l32\000"
34 /* 34 */ "subreg_ll32\000"
35 /* 46 */ "subreg_h64\000"
36 /* 57 */ "subreg_l64\000"
37 /* 68 */ "subreg_lh32_then_subreg_h16\000"
38};
39#ifdef __GNUC__
40#pragma GCC diagnostic pop
41#endif
42
43
44static constexpr uint32_t SystemZSubRegIndexNameOffsets[] = {
45 85,
46 0,
47 46,
48 23,
49 57,
50 11,
51 34,
52 68,
53};
54
55static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
56 { .Offset: 65535, .Size: 65535 },
57 { .Offset: 16, .Size: 16 }, // subreg_h16
58 { .Offset: 32, .Size: 32 }, // subreg_h32
59 { .Offset: 64, .Size: 64 }, // subreg_h64
60 { .Offset: 0, .Size: 32 }, // subreg_l32
61 { .Offset: 0, .Size: 64 }, // subreg_l64
62 { .Offset: 32, .Size: 32 }, // subreg_lh32
63 { .Offset: 0, .Size: 32 }, // subreg_ll32
64 { .Offset: 48, .Size: 16 }, // subreg_lh32_then_subreg_h16
65 { .Offset: 65535, .Size: 65535 },
66 { .Offset: 16, .Size: 16 }, // subreg_h16
67 { .Offset: 32, .Size: 32 }, // subreg_h32
68 { .Offset: 64, .Size: 64 }, // subreg_h64
69 { .Offset: 0, .Size: 32 }, // subreg_l32
70 { .Offset: 0, .Size: 64 }, // subreg_l64
71 { .Offset: 32, .Size: 32 }, // subreg_lh32
72 { .Offset: 0, .Size: 32 }, // subreg_ll32
73 { .Offset: 48, .Size: 16 }, // subreg_lh32_then_subreg_h16
74};
75
76
77static const LaneBitmask SubRegIndexLaneMaskTable[] = {
78 LaneBitmask::getAll(),
79 LaneBitmask(0x0000000000000001), // subreg_h16
80 LaneBitmask(0x0000000000000001), // subreg_h32
81 LaneBitmask(0x0000000000000003), // subreg_h64
82 LaneBitmask(0x0000000000000002), // subreg_l32
83 LaneBitmask(0x000000000000000C), // subreg_l64
84 LaneBitmask(0x0000000000000008), // subreg_lh32
85 LaneBitmask(0x0000000000000004), // subreg_ll32
86 LaneBitmask(0x0000000000000008), // subreg_lh32_then_subreg_h16
87 };
88
89
90
91static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
92 // Mode = 0 (DefaultMode)
93 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 4 }, // VR16Bit
94 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 4 }, // FP16Bit
95 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GRX32Bit
96 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 20 }, // VR32Bit
97 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // AR32Bit
98 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 6 }, // FP32Bit
99 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GR32Bit
100 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GRH32Bit
101 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // ADDR32Bit
102 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // CCR
103 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // FPCRegs
104 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 24 }, // AnyRegBit
105 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h16
106 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 25 }, // VR64Bit
107 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h64
108 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // CR64Bit
109 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 8 }, // FP64Bit
110 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // GR64Bit
111 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // ADDR64Bit
112 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 10 }, // VR128Bit
113 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 31 }, // VF128Bit
114 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 18 }, // FP128Bit
115 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 39 }, // GR128Bit
116 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 39 }, // ADDR128Bit
117 // Mode = 1 (NoVecHwMode)
118 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 4 }, // VR16Bit
119 { .RegSize: 16, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // FP16Bit
120 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GRX32Bit
121 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 20 }, // VR32Bit
122 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // AR32Bit
123 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 6 }, // FP32Bit
124 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GR32Bit
125 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GRH32Bit
126 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // ADDR32Bit
127 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // CCR
128 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // FPCRegs
129 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 24 }, // AnyRegBit
130 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h16
131 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 25 }, // VR64Bit
132 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h64
133 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // CR64Bit
134 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 8 }, // FP64Bit
135 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // GR64Bit
136 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // ADDR64Bit
137 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 10 }, // VR128Bit
138 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 31 }, // VF128Bit
139 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 18 }, // FP128Bit
140 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 39 }, // GR128Bit
141 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 39 }, // ADDR128Bit
142};
143static const uint32_t VR16BitSubClassMask[] = {
144 0x00000003,
145 0x00397028, // subreg_h16
146 0x00200000, // subreg_lh32_then_subreg_h16
147};
148
149static const uint32_t FP16BitSubClassMask[] = {
150 0x00000002,
151 0x00315020, // subreg_h16
152 0x00200000, // subreg_lh32_then_subreg_h16
153};
154
155static const uint32_t GRX32BitSubClassMask[] = {
156 0x000001c4,
157 0x00c60000, // subreg_h32
158 0x00c60000, // subreg_l32
159 0x00c00000, // subreg_lh32
160 0x00c00000, // subreg_ll32
161};
162
163static const uint32_t VR32BitSubClassMask[] = {
164 0x00000028,
165 0x00397000, // subreg_h32
166 0x00200000, // subreg_lh32
167};
168
169static const uint32_t AR32BitSubClassMask[] = {
170 0x00000010,
171};
172
173static const uint32_t FP32BitSubClassMask[] = {
174 0x00000020,
175 0x00315000, // subreg_h32
176 0x00200000, // subreg_lh32
177};
178
179static const uint32_t GR32BitSubClassMask[] = {
180 0x00000140,
181 0x00c60000, // subreg_l32
182 0x00c00000, // subreg_ll32
183};
184
185static const uint32_t GRH32BitSubClassMask[] = {
186 0x00000080,
187 0x00c60000, // subreg_h32
188 0x00c00000, // subreg_lh32
189};
190
191static const uint32_t ADDR32BitSubClassMask[] = {
192 0x00000100,
193 0x00840000, // subreg_l32
194 0x00c00000, // subreg_ll32
195};
196
197static const uint32_t CCRSubClassMask[] = {
198 0x00000200,
199};
200
201static const uint32_t FPCRegsSubClassMask[] = {
202 0x00000400,
203};
204
205static const uint32_t AnyRegBitSubClassMask[] = {
206 0x00175800,
207 0x00f04000, // subreg_h64
208 0x00e00000, // subreg_l64
209};
210
211static const uint32_t AnyRegBit_with_subreg_h16SubClassMask[] = {
212 0x00115000,
213 0x00304000, // subreg_h64
214 0x00200000, // subreg_l64
215};
216
217static const uint32_t VR64BitSubClassMask[] = {
218 0x00012000,
219 0x00384000, // subreg_h64
220 0x00200000, // subreg_l64
221};
222
223static const uint32_t AnyRegBit_with_subreg_h64SubClassMask[] = {
224 0x00104000,
225};
226
227static const uint32_t CR64BitSubClassMask[] = {
228 0x00008000,
229};
230
231static const uint32_t FP64BitSubClassMask[] = {
232 0x00010000,
233 0x00304000, // subreg_h64
234 0x00200000, // subreg_l64
235};
236
237static const uint32_t GR64BitSubClassMask[] = {
238 0x00060000,
239 0x00c00000, // subreg_h64
240 0x00c00000, // subreg_l64
241};
242
243static const uint32_t ADDR64BitSubClassMask[] = {
244 0x00040000,
245 0x00800000, // subreg_h64
246 0x00c00000, // subreg_l64
247};
248
249static const uint32_t VR128BitSubClassMask[] = {
250 0x00180000,
251};
252
253static const uint32_t VF128BitSubClassMask[] = {
254 0x00100000,
255};
256
257static const uint32_t FP128BitSubClassMask[] = {
258 0x00200000,
259};
260
261static const uint32_t GR128BitSubClassMask[] = {
262 0x00c00000,
263};
264
265static const uint32_t ADDR128BitSubClassMask[] = {
266 0x00800000,
267};
268
269static const uint16_t SuperRegIdxSeqs[] = {
270 /* 0 */ 3, 5, 0,
271 /* 3 */ 2, 6, 0,
272 /* 6 */ 4, 7, 0,
273 /* 9 */ 2, 4, 6, 7, 0,
274 /* 14 */ 1, 8, 0,
275};
276
277static unsigned const FP16BitSuperclasses[] = {
278 SystemZ::VR16BitRegClassID,
279};
280
281static unsigned const FP32BitSuperclasses[] = {
282 SystemZ::VR32BitRegClassID,
283};
284
285static unsigned const GR32BitSuperclasses[] = {
286 SystemZ::GRX32BitRegClassID,
287};
288
289static unsigned const GRH32BitSuperclasses[] = {
290 SystemZ::GRX32BitRegClassID,
291};
292
293static unsigned const ADDR32BitSuperclasses[] = {
294 SystemZ::GRX32BitRegClassID,
295 SystemZ::GR32BitRegClassID,
296};
297
298static unsigned const AnyRegBit_with_subreg_h16Superclasses[] = {
299 SystemZ::AnyRegBitRegClassID,
300};
301
302static unsigned const AnyRegBit_with_subreg_h64Superclasses[] = {
303 SystemZ::AnyRegBitRegClassID,
304 SystemZ::AnyRegBit_with_subreg_h16RegClassID,
305};
306
307static unsigned const FP64BitSuperclasses[] = {
308 SystemZ::AnyRegBitRegClassID,
309 SystemZ::AnyRegBit_with_subreg_h16RegClassID,
310 SystemZ::VR64BitRegClassID,
311};
312
313static unsigned const GR64BitSuperclasses[] = {
314 SystemZ::AnyRegBitRegClassID,
315};
316
317static unsigned const ADDR64BitSuperclasses[] = {
318 SystemZ::AnyRegBitRegClassID,
319 SystemZ::GR64BitRegClassID,
320};
321
322static unsigned const VF128BitSuperclasses[] = {
323 SystemZ::AnyRegBitRegClassID,
324 SystemZ::AnyRegBit_with_subreg_h16RegClassID,
325 SystemZ::AnyRegBit_with_subreg_h64RegClassID,
326 SystemZ::VR128BitRegClassID,
327};
328
329static unsigned const ADDR128BitSuperclasses[] = {
330 SystemZ::GR128BitRegClassID,
331};
332
333
334static inline unsigned VR16BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
335 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
336 return S.isTargetXPLINK64();
337 }
338
339static ArrayRef<MCPhysReg> VR16BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
340 static const MCPhysReg AltOrder1[] = { SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F16H, SystemZ::F17H, SystemZ::F18H, SystemZ::F19H, SystemZ::F20H, SystemZ::F21H, SystemZ::F22H, SystemZ::F23H, SystemZ::F24H, SystemZ::F25H, SystemZ::F26H, SystemZ::F27H, SystemZ::F28H, SystemZ::F29H, SystemZ::F30H, SystemZ::F31H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H };
341 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR16BitRegClassID];
342 const ArrayRef<MCPhysReg> Order[] = {
343 ArrayRef(MCR.begin(), MCR.getNumRegs()),
344 ArrayRef(AltOrder1)
345 };
346 const unsigned Select = VR16BitAltOrderSelect(MF, Rev);
347 assert(Select < 2);
348 return Order[Select];
349}
350
351static inline unsigned FP16BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
352 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
353 return S.isTargetXPLINK64();
354 }
355
356static ArrayRef<MCPhysReg> FP16BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
357 static const MCPhysReg AltOrder1[] = { SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H };
358 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP16BitRegClassID];
359 const ArrayRef<MCPhysReg> Order[] = {
360 ArrayRef(MCR.begin(), MCR.getNumRegs()),
361 ArrayRef(AltOrder1)
362 };
363 const unsigned Select = FP16BitAltOrderSelect(MF, Rev);
364 assert(Select < 2);
365 return Order[Select];
366}
367
368static inline unsigned GRX32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
369 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
370 return S.isTargetXPLINK64();
371 }
372
373static ArrayRef<MCPhysReg> GRX32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
374 static const MCPhysReg AltOrder1[] = { SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4L, SystemZ::R4H, SystemZ::R5L, SystemZ::R5H, SystemZ::R6L, SystemZ::R6H, SystemZ::R7L, SystemZ::R7H, SystemZ::R8L, SystemZ::R8H, SystemZ::R9L, SystemZ::R9H, SystemZ::R10L, SystemZ::R10H, SystemZ::R11L, SystemZ::R11H, SystemZ::R12L, SystemZ::R12H, SystemZ::R13L, SystemZ::R13H, SystemZ::R14L, SystemZ::R14H, SystemZ::R15L, SystemZ::R15H };
375 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GRX32BitRegClassID];
376 const ArrayRef<MCPhysReg> Order[] = {
377 ArrayRef(MCR.begin(), MCR.getNumRegs()),
378 ArrayRef(AltOrder1)
379 };
380 const unsigned Select = GRX32BitAltOrderSelect(MF, Rev);
381 assert(Select < 2);
382 return Order[Select];
383}
384
385static inline unsigned VR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
386 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
387 return S.isTargetXPLINK64();
388 }
389
390static ArrayRef<MCPhysReg> VR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
391 static const MCPhysReg AltOrder1[] = { SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
392 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR32BitRegClassID];
393 const ArrayRef<MCPhysReg> Order[] = {
394 ArrayRef(MCR.begin(), MCR.getNumRegs()),
395 ArrayRef(AltOrder1)
396 };
397 const unsigned Select = VR32BitAltOrderSelect(MF, Rev);
398 assert(Select < 2);
399 return Order[Select];
400}
401
402static inline unsigned AR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
403 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
404 return S.isTargetXPLINK64();
405 }
406
407static ArrayRef<MCPhysReg> AR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
408 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AR32BitRegClassID];
409 const ArrayRef<MCPhysReg> Order[] = {
410 ArrayRef(MCR.begin(), MCR.getNumRegs())
411 };
412 const unsigned Select = AR32BitAltOrderSelect(MF, Rev);
413 assert(Select < 1);
414 return Order[Select];
415}
416
417static inline unsigned FP32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
418 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
419 return S.isTargetXPLINK64();
420 }
421
422static ArrayRef<MCPhysReg> FP32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
423 static const MCPhysReg AltOrder1[] = { SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
424 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP32BitRegClassID];
425 const ArrayRef<MCPhysReg> Order[] = {
426 ArrayRef(MCR.begin(), MCR.getNumRegs()),
427 ArrayRef(AltOrder1)
428 };
429 const unsigned Select = FP32BitAltOrderSelect(MF, Rev);
430 assert(Select < 2);
431 return Order[Select];
432}
433
434static inline unsigned GR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
435 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
436 return S.isTargetXPLINK64();
437 }
438
439static ArrayRef<MCPhysReg> GR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
440 static const MCPhysReg AltOrder1[] = { SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L };
441 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR32BitRegClassID];
442 const ArrayRef<MCPhysReg> Order[] = {
443 ArrayRef(MCR.begin(), MCR.getNumRegs()),
444 ArrayRef(AltOrder1)
445 };
446 const unsigned Select = GR32BitAltOrderSelect(MF, Rev);
447 assert(Select < 2);
448 return Order[Select];
449}
450
451static inline unsigned GRH32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
452 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
453 return S.isTargetXPLINK64();
454 }
455
456static ArrayRef<MCPhysReg> GRH32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
457 static const MCPhysReg AltOrder1[] = { SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H, SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H, SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H };
458 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GRH32BitRegClassID];
459 const ArrayRef<MCPhysReg> Order[] = {
460 ArrayRef(MCR.begin(), MCR.getNumRegs()),
461 ArrayRef(AltOrder1)
462 };
463 const unsigned Select = GRH32BitAltOrderSelect(MF, Rev);
464 assert(Select < 2);
465 return Order[Select];
466}
467
468static inline unsigned ADDR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
469 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
470 return S.isTargetXPLINK64();
471 }
472
473static ArrayRef<MCPhysReg> ADDR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
474 static const MCPhysReg AltOrder1[] = { SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L };
475 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR32BitRegClassID];
476 const ArrayRef<MCPhysReg> Order[] = {
477 ArrayRef(MCR.begin(), MCR.getNumRegs()),
478 ArrayRef(AltOrder1)
479 };
480 const unsigned Select = ADDR32BitAltOrderSelect(MF, Rev);
481 assert(Select < 2);
482 return Order[Select];
483}
484
485static inline unsigned AnyRegBitAltOrderSelect(const MachineFunction &MF, bool Rev) {
486 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
487 return S.isTargetXPLINK64();
488 }
489
490static ArrayRef<MCPhysReg> AnyRegBitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
491 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBitRegClassID];
492 const ArrayRef<MCPhysReg> Order[] = {
493 ArrayRef(MCR.begin(), MCR.getNumRegs())
494 };
495 const unsigned Select = AnyRegBitAltOrderSelect(MF, Rev);
496 assert(Select < 1);
497 return Order[Select];
498}
499
500static inline unsigned AnyRegBit_with_subreg_h16AltOrderSelect(const MachineFunction &MF, bool Rev) {
501 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
502 return S.isTargetXPLINK64();
503 }
504
505static ArrayRef<MCPhysReg> AnyRegBit_with_subreg_h16GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
506 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBit_with_subreg_h16RegClassID];
507 const ArrayRef<MCPhysReg> Order[] = {
508 ArrayRef(MCR.begin(), MCR.getNumRegs())
509 };
510 const unsigned Select = AnyRegBit_with_subreg_h16AltOrderSelect(MF, Rev);
511 assert(Select < 1);
512 return Order[Select];
513}
514
515static inline unsigned VR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
516 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
517 return S.isTargetXPLINK64();
518 }
519
520static ArrayRef<MCPhysReg> VR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
521 static const MCPhysReg AltOrder1[] = { SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D };
522 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR64BitRegClassID];
523 const ArrayRef<MCPhysReg> Order[] = {
524 ArrayRef(MCR.begin(), MCR.getNumRegs()),
525 ArrayRef(AltOrder1)
526 };
527 const unsigned Select = VR64BitAltOrderSelect(MF, Rev);
528 assert(Select < 2);
529 return Order[Select];
530}
531
532static inline unsigned AnyRegBit_with_subreg_h64AltOrderSelect(const MachineFunction &MF, bool Rev) {
533 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
534 return S.isTargetXPLINK64();
535 }
536
537static ArrayRef<MCPhysReg> AnyRegBit_with_subreg_h64GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
538 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBit_with_subreg_h64RegClassID];
539 const ArrayRef<MCPhysReg> Order[] = {
540 ArrayRef(MCR.begin(), MCR.getNumRegs())
541 };
542 const unsigned Select = AnyRegBit_with_subreg_h64AltOrderSelect(MF, Rev);
543 assert(Select < 1);
544 return Order[Select];
545}
546
547static inline unsigned CR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
548 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
549 return S.isTargetXPLINK64();
550 }
551
552static ArrayRef<MCPhysReg> CR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
553 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::CR64BitRegClassID];
554 const ArrayRef<MCPhysReg> Order[] = {
555 ArrayRef(MCR.begin(), MCR.getNumRegs())
556 };
557 const unsigned Select = CR64BitAltOrderSelect(MF, Rev);
558 assert(Select < 1);
559 return Order[Select];
560}
561
562static inline unsigned FP64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
563 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
564 return S.isTargetXPLINK64();
565 }
566
567static ArrayRef<MCPhysReg> FP64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
568 static const MCPhysReg AltOrder1[] = { SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D };
569 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP64BitRegClassID];
570 const ArrayRef<MCPhysReg> Order[] = {
571 ArrayRef(MCR.begin(), MCR.getNumRegs()),
572 ArrayRef(AltOrder1)
573 };
574 const unsigned Select = FP64BitAltOrderSelect(MF, Rev);
575 assert(Select < 2);
576 return Order[Select];
577}
578
579static inline unsigned GR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
580 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
581 return S.isTargetXPLINK64();
582 }
583
584static ArrayRef<MCPhysReg> GR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
585 static const MCPhysReg AltOrder1[] = { SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D };
586 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR64BitRegClassID];
587 const ArrayRef<MCPhysReg> Order[] = {
588 ArrayRef(MCR.begin(), MCR.getNumRegs()),
589 ArrayRef(AltOrder1)
590 };
591 const unsigned Select = GR64BitAltOrderSelect(MF, Rev);
592 assert(Select < 2);
593 return Order[Select];
594}
595
596static inline unsigned ADDR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
597 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
598 return S.isTargetXPLINK64();
599 }
600
601static ArrayRef<MCPhysReg> ADDR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
602 static const MCPhysReg AltOrder1[] = { SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D };
603 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR64BitRegClassID];
604 const ArrayRef<MCPhysReg> Order[] = {
605 ArrayRef(MCR.begin(), MCR.getNumRegs()),
606 ArrayRef(AltOrder1)
607 };
608 const unsigned Select = ADDR64BitAltOrderSelect(MF, Rev);
609 assert(Select < 2);
610 return Order[Select];
611}
612
613static inline unsigned VR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
614 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
615 return S.isTargetXPLINK64();
616 }
617
618static ArrayRef<MCPhysReg> VR128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
619 static const MCPhysReg AltOrder1[] = { SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15 };
620 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR128BitRegClassID];
621 const ArrayRef<MCPhysReg> Order[] = {
622 ArrayRef(MCR.begin(), MCR.getNumRegs()),
623 ArrayRef(AltOrder1)
624 };
625 const unsigned Select = VR128BitAltOrderSelect(MF, Rev);
626 assert(Select < 2);
627 return Order[Select];
628}
629
630static inline unsigned VF128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
631 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
632 return S.isTargetXPLINK64();
633 }
634
635static ArrayRef<MCPhysReg> VF128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
636 static const MCPhysReg AltOrder1[] = { SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15 };
637 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VF128BitRegClassID];
638 const ArrayRef<MCPhysReg> Order[] = {
639 ArrayRef(MCR.begin(), MCR.getNumRegs()),
640 ArrayRef(AltOrder1)
641 };
642 const unsigned Select = VF128BitAltOrderSelect(MF, Rev);
643 assert(Select < 2);
644 return Order[Select];
645}
646
647static inline unsigned FP128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
648 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
649 return S.isTargetXPLINK64();
650 }
651
652static ArrayRef<MCPhysReg> FP128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
653 static const MCPhysReg AltOrder1[] = { SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q };
654 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP128BitRegClassID];
655 const ArrayRef<MCPhysReg> Order[] = {
656 ArrayRef(MCR.begin(), MCR.getNumRegs()),
657 ArrayRef(AltOrder1)
658 };
659 const unsigned Select = FP128BitAltOrderSelect(MF, Rev);
660 assert(Select < 2);
661 return Order[Select];
662}
663
664static inline unsigned GR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
665 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
666 return S.isTargetXPLINK64();
667 }
668
669static ArrayRef<MCPhysReg> GR128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
670 static const MCPhysReg AltOrder1[] = { SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R6Q, SystemZ::R8Q, SystemZ::R10Q, SystemZ::R12Q, SystemZ::R14Q };
671 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR128BitRegClassID];
672 const ArrayRef<MCPhysReg> Order[] = {
673 ArrayRef(MCR.begin(), MCR.getNumRegs()),
674 ArrayRef(AltOrder1)
675 };
676 const unsigned Select = GR128BitAltOrderSelect(MF, Rev);
677 assert(Select < 2);
678 return Order[Select];
679}
680
681static inline unsigned ADDR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
682 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
683 return S.isTargetXPLINK64();
684 }
685
686static ArrayRef<MCPhysReg> ADDR128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
687 static const MCPhysReg AltOrder1[] = { SystemZ::R2Q, SystemZ::R4Q, SystemZ::R6Q, SystemZ::R8Q, SystemZ::R10Q, SystemZ::R12Q, SystemZ::R14Q };
688 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR128BitRegClassID];
689 const ArrayRef<MCPhysReg> Order[] = {
690 ArrayRef(MCR.begin(), MCR.getNumRegs()),
691 ArrayRef(AltOrder1)
692 };
693 const unsigned Select = ADDR128BitAltOrderSelect(MF, Rev);
694 assert(Select < 2);
695 return Order[Select];
696}
697namespace SystemZ {
698
699// Register class instances
700 extern const TargetRegisterClass VR16BitRegClass = {
701 .MC: &SystemZMCRegisterClasses[VR16BitRegClassID],
702 .SubClassMask: VR16BitSubClassMask,
703 .SuperRegIndices: SuperRegIdxSeqs + 14,
704 .LaneMask: LaneBitmask(0x0000000000000001),
705 .AllocationPriority: 0,
706 .GlobalPriority: false,
707 .TSFlags: 0x00, /* TSFlags */
708 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
709 .CoveredBySubRegs: false, /* CoveredBySubRegs */
710 .SuperClasses: nullptr, .SuperClassesSize: 0,
711 .OrderFunc: VR16BitGetRawAllocationOrder
712 };
713
714 extern const TargetRegisterClass FP16BitRegClass = {
715 .MC: &SystemZMCRegisterClasses[FP16BitRegClassID],
716 .SubClassMask: FP16BitSubClassMask,
717 .SuperRegIndices: SuperRegIdxSeqs + 14,
718 .LaneMask: LaneBitmask(0x0000000000000001),
719 .AllocationPriority: 0,
720 .GlobalPriority: false,
721 .TSFlags: 0x00, /* TSFlags */
722 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
723 .CoveredBySubRegs: false, /* CoveredBySubRegs */
724 .SuperClasses: FP16BitSuperclasses, .SuperClassesSize: 1,
725 .OrderFunc: FP16BitGetRawAllocationOrder
726 };
727
728 extern const TargetRegisterClass GRX32BitRegClass = {
729 .MC: &SystemZMCRegisterClasses[GRX32BitRegClassID],
730 .SubClassMask: GRX32BitSubClassMask,
731 .SuperRegIndices: SuperRegIdxSeqs + 9,
732 .LaneMask: LaneBitmask(0x0000000000000001),
733 .AllocationPriority: 0,
734 .GlobalPriority: false,
735 .TSFlags: 0x00, /* TSFlags */
736 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
737 .CoveredBySubRegs: false, /* CoveredBySubRegs */
738 .SuperClasses: nullptr, .SuperClassesSize: 0,
739 .OrderFunc: GRX32BitGetRawAllocationOrder
740 };
741
742 extern const TargetRegisterClass VR32BitRegClass = {
743 .MC: &SystemZMCRegisterClasses[VR32BitRegClassID],
744 .SubClassMask: VR32BitSubClassMask,
745 .SuperRegIndices: SuperRegIdxSeqs + 3,
746 .LaneMask: LaneBitmask(0x0000000000000001),
747 .AllocationPriority: 0,
748 .GlobalPriority: false,
749 .TSFlags: 0x00, /* TSFlags */
750 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
751 .CoveredBySubRegs: false, /* CoveredBySubRegs */
752 .SuperClasses: nullptr, .SuperClassesSize: 0,
753 .OrderFunc: VR32BitGetRawAllocationOrder
754 };
755
756 extern const TargetRegisterClass AR32BitRegClass = {
757 .MC: &SystemZMCRegisterClasses[AR32BitRegClassID],
758 .SubClassMask: AR32BitSubClassMask,
759 .SuperRegIndices: SuperRegIdxSeqs + 2,
760 .LaneMask: LaneBitmask(0x0000000000000001),
761 .AllocationPriority: 0,
762 .GlobalPriority: false,
763 .TSFlags: 0x00, /* TSFlags */
764 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
765 .CoveredBySubRegs: false, /* CoveredBySubRegs */
766 .SuperClasses: nullptr, .SuperClassesSize: 0,
767 .OrderFunc: AR32BitGetRawAllocationOrder
768 };
769
770 extern const TargetRegisterClass FP32BitRegClass = {
771 .MC: &SystemZMCRegisterClasses[FP32BitRegClassID],
772 .SubClassMask: FP32BitSubClassMask,
773 .SuperRegIndices: SuperRegIdxSeqs + 3,
774 .LaneMask: LaneBitmask(0x0000000000000001),
775 .AllocationPriority: 0,
776 .GlobalPriority: false,
777 .TSFlags: 0x00, /* TSFlags */
778 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
779 .CoveredBySubRegs: false, /* CoveredBySubRegs */
780 .SuperClasses: FP32BitSuperclasses, .SuperClassesSize: 1,
781 .OrderFunc: FP32BitGetRawAllocationOrder
782 };
783
784 extern const TargetRegisterClass GR32BitRegClass = {
785 .MC: &SystemZMCRegisterClasses[GR32BitRegClassID],
786 .SubClassMask: GR32BitSubClassMask,
787 .SuperRegIndices: SuperRegIdxSeqs + 6,
788 .LaneMask: LaneBitmask(0x0000000000000001),
789 .AllocationPriority: 0,
790 .GlobalPriority: false,
791 .TSFlags: 0x00, /* TSFlags */
792 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
793 .CoveredBySubRegs: false, /* CoveredBySubRegs */
794 .SuperClasses: GR32BitSuperclasses, .SuperClassesSize: 1,
795 .OrderFunc: GR32BitGetRawAllocationOrder
796 };
797
798 extern const TargetRegisterClass GRH32BitRegClass = {
799 .MC: &SystemZMCRegisterClasses[GRH32BitRegClassID],
800 .SubClassMask: GRH32BitSubClassMask,
801 .SuperRegIndices: SuperRegIdxSeqs + 3,
802 .LaneMask: LaneBitmask(0x0000000000000001),
803 .AllocationPriority: 0,
804 .GlobalPriority: false,
805 .TSFlags: 0x00, /* TSFlags */
806 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
807 .CoveredBySubRegs: false, /* CoveredBySubRegs */
808 .SuperClasses: GRH32BitSuperclasses, .SuperClassesSize: 1,
809 .OrderFunc: GRH32BitGetRawAllocationOrder
810 };
811
812 extern const TargetRegisterClass ADDR32BitRegClass = {
813 .MC: &SystemZMCRegisterClasses[ADDR32BitRegClassID],
814 .SubClassMask: ADDR32BitSubClassMask,
815 .SuperRegIndices: SuperRegIdxSeqs + 6,
816 .LaneMask: LaneBitmask(0x0000000000000001),
817 .AllocationPriority: 0,
818 .GlobalPriority: false,
819 .TSFlags: 0x00, /* TSFlags */
820 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
821 .CoveredBySubRegs: false, /* CoveredBySubRegs */
822 .SuperClasses: ADDR32BitSuperclasses, .SuperClassesSize: 2,
823 .OrderFunc: ADDR32BitGetRawAllocationOrder
824 };
825
826 extern const TargetRegisterClass CCRRegClass = {
827 .MC: &SystemZMCRegisterClasses[CCRRegClassID],
828 .SubClassMask: CCRSubClassMask,
829 .SuperRegIndices: SuperRegIdxSeqs + 2,
830 .LaneMask: LaneBitmask(0x0000000000000001),
831 .AllocationPriority: 0,
832 .GlobalPriority: false,
833 .TSFlags: 0x00, /* TSFlags */
834 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
835 .CoveredBySubRegs: false, /* CoveredBySubRegs */
836 .SuperClasses: nullptr, .SuperClassesSize: 0,
837 .OrderFunc: nullptr
838 };
839
840 extern const TargetRegisterClass FPCRegsRegClass = {
841 .MC: &SystemZMCRegisterClasses[FPCRegsRegClassID],
842 .SubClassMask: FPCRegsSubClassMask,
843 .SuperRegIndices: SuperRegIdxSeqs + 2,
844 .LaneMask: LaneBitmask(0x0000000000000001),
845 .AllocationPriority: 0,
846 .GlobalPriority: false,
847 .TSFlags: 0x00, /* TSFlags */
848 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
849 .CoveredBySubRegs: false, /* CoveredBySubRegs */
850 .SuperClasses: nullptr, .SuperClassesSize: 0,
851 .OrderFunc: nullptr
852 };
853
854 extern const TargetRegisterClass AnyRegBitRegClass = {
855 .MC: &SystemZMCRegisterClasses[AnyRegBitRegClassID],
856 .SubClassMask: AnyRegBitSubClassMask,
857 .SuperRegIndices: SuperRegIdxSeqs + 0,
858 .LaneMask: LaneBitmask(0x0000000000000003),
859 .AllocationPriority: 0,
860 .GlobalPriority: false,
861 .TSFlags: 0x00, /* TSFlags */
862 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
863 .CoveredBySubRegs: false, /* CoveredBySubRegs */
864 .SuperClasses: nullptr, .SuperClassesSize: 0,
865 .OrderFunc: AnyRegBitGetRawAllocationOrder
866 };
867
868 extern const TargetRegisterClass AnyRegBit_with_subreg_h16RegClass = {
869 .MC: &SystemZMCRegisterClasses[AnyRegBit_with_subreg_h16RegClassID],
870 .SubClassMask: AnyRegBit_with_subreg_h16SubClassMask,
871 .SuperRegIndices: SuperRegIdxSeqs + 0,
872 .LaneMask: LaneBitmask(0x0000000000000003),
873 .AllocationPriority: 0,
874 .GlobalPriority: false,
875 .TSFlags: 0x00, /* TSFlags */
876 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
877 .CoveredBySubRegs: false, /* CoveredBySubRegs */
878 .SuperClasses: AnyRegBit_with_subreg_h16Superclasses, .SuperClassesSize: 1,
879 .OrderFunc: AnyRegBit_with_subreg_h16GetRawAllocationOrder
880 };
881
882 extern const TargetRegisterClass VR64BitRegClass = {
883 .MC: &SystemZMCRegisterClasses[VR64BitRegClassID],
884 .SubClassMask: VR64BitSubClassMask,
885 .SuperRegIndices: SuperRegIdxSeqs + 0,
886 .LaneMask: LaneBitmask(0x0000000000000001),
887 .AllocationPriority: 0,
888 .GlobalPriority: false,
889 .TSFlags: 0x00, /* TSFlags */
890 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
891 .CoveredBySubRegs: false, /* CoveredBySubRegs */
892 .SuperClasses: nullptr, .SuperClassesSize: 0,
893 .OrderFunc: VR64BitGetRawAllocationOrder
894 };
895
896 extern const TargetRegisterClass AnyRegBit_with_subreg_h64RegClass = {
897 .MC: &SystemZMCRegisterClasses[AnyRegBit_with_subreg_h64RegClassID],
898 .SubClassMask: AnyRegBit_with_subreg_h64SubClassMask,
899 .SuperRegIndices: SuperRegIdxSeqs + 2,
900 .LaneMask: LaneBitmask(0x0000000000000003),
901 .AllocationPriority: 0,
902 .GlobalPriority: false,
903 .TSFlags: 0x00, /* TSFlags */
904 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
905 .CoveredBySubRegs: false, /* CoveredBySubRegs */
906 .SuperClasses: AnyRegBit_with_subreg_h64Superclasses, .SuperClassesSize: 2,
907 .OrderFunc: AnyRegBit_with_subreg_h64GetRawAllocationOrder
908 };
909
910 extern const TargetRegisterClass CR64BitRegClass = {
911 .MC: &SystemZMCRegisterClasses[CR64BitRegClassID],
912 .SubClassMask: CR64BitSubClassMask,
913 .SuperRegIndices: SuperRegIdxSeqs + 2,
914 .LaneMask: LaneBitmask(0x0000000000000001),
915 .AllocationPriority: 0,
916 .GlobalPriority: false,
917 .TSFlags: 0x00, /* TSFlags */
918 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
919 .CoveredBySubRegs: false, /* CoveredBySubRegs */
920 .SuperClasses: nullptr, .SuperClassesSize: 0,
921 .OrderFunc: CR64BitGetRawAllocationOrder
922 };
923
924 extern const TargetRegisterClass FP64BitRegClass = {
925 .MC: &SystemZMCRegisterClasses[FP64BitRegClassID],
926 .SubClassMask: FP64BitSubClassMask,
927 .SuperRegIndices: SuperRegIdxSeqs + 0,
928 .LaneMask: LaneBitmask(0x0000000000000001),
929 .AllocationPriority: 0,
930 .GlobalPriority: false,
931 .TSFlags: 0x00, /* TSFlags */
932 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
933 .CoveredBySubRegs: false, /* CoveredBySubRegs */
934 .SuperClasses: FP64BitSuperclasses, .SuperClassesSize: 3,
935 .OrderFunc: FP64BitGetRawAllocationOrder
936 };
937
938 extern const TargetRegisterClass GR64BitRegClass = {
939 .MC: &SystemZMCRegisterClasses[GR64BitRegClassID],
940 .SubClassMask: GR64BitSubClassMask,
941 .SuperRegIndices: SuperRegIdxSeqs + 0,
942 .LaneMask: LaneBitmask(0x0000000000000003),
943 .AllocationPriority: 0,
944 .GlobalPriority: false,
945 .TSFlags: 0x00, /* TSFlags */
946 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
947 .CoveredBySubRegs: true, /* CoveredBySubRegs */
948 .SuperClasses: GR64BitSuperclasses, .SuperClassesSize: 1,
949 .OrderFunc: GR64BitGetRawAllocationOrder
950 };
951
952 extern const TargetRegisterClass ADDR64BitRegClass = {
953 .MC: &SystemZMCRegisterClasses[ADDR64BitRegClassID],
954 .SubClassMask: ADDR64BitSubClassMask,
955 .SuperRegIndices: SuperRegIdxSeqs + 0,
956 .LaneMask: LaneBitmask(0x0000000000000003),
957 .AllocationPriority: 0,
958 .GlobalPriority: false,
959 .TSFlags: 0x00, /* TSFlags */
960 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
961 .CoveredBySubRegs: true, /* CoveredBySubRegs */
962 .SuperClasses: ADDR64BitSuperclasses, .SuperClassesSize: 2,
963 .OrderFunc: ADDR64BitGetRawAllocationOrder
964 };
965
966 extern const TargetRegisterClass VR128BitRegClass = {
967 .MC: &SystemZMCRegisterClasses[VR128BitRegClassID],
968 .SubClassMask: VR128BitSubClassMask,
969 .SuperRegIndices: SuperRegIdxSeqs + 2,
970 .LaneMask: LaneBitmask(0x0000000000000003),
971 .AllocationPriority: 0,
972 .GlobalPriority: false,
973 .TSFlags: 0x00, /* TSFlags */
974 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
975 .CoveredBySubRegs: false, /* CoveredBySubRegs */
976 .SuperClasses: nullptr, .SuperClassesSize: 0,
977 .OrderFunc: VR128BitGetRawAllocationOrder
978 };
979
980 extern const TargetRegisterClass VF128BitRegClass = {
981 .MC: &SystemZMCRegisterClasses[VF128BitRegClassID],
982 .SubClassMask: VF128BitSubClassMask,
983 .SuperRegIndices: SuperRegIdxSeqs + 2,
984 .LaneMask: LaneBitmask(0x0000000000000003),
985 .AllocationPriority: 0,
986 .GlobalPriority: false,
987 .TSFlags: 0x00, /* TSFlags */
988 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
989 .CoveredBySubRegs: false, /* CoveredBySubRegs */
990 .SuperClasses: VF128BitSuperclasses, .SuperClassesSize: 4,
991 .OrderFunc: VF128BitGetRawAllocationOrder
992 };
993
994 extern const TargetRegisterClass FP128BitRegClass = {
995 .MC: &SystemZMCRegisterClasses[FP128BitRegClassID],
996 .SubClassMask: FP128BitSubClassMask,
997 .SuperRegIndices: SuperRegIdxSeqs + 2,
998 .LaneMask: LaneBitmask(0x000000000000000F),
999 .AllocationPriority: 0,
1000 .GlobalPriority: false,
1001 .TSFlags: 0x00, /* TSFlags */
1002 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1003 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1004 .SuperClasses: nullptr, .SuperClassesSize: 0,
1005 .OrderFunc: FP128BitGetRawAllocationOrder
1006 };
1007
1008 extern const TargetRegisterClass GR128BitRegClass = {
1009 .MC: &SystemZMCRegisterClasses[GR128BitRegClassID],
1010 .SubClassMask: GR128BitSubClassMask,
1011 .SuperRegIndices: SuperRegIdxSeqs + 2,
1012 .LaneMask: LaneBitmask(0x000000000000000F),
1013 .AllocationPriority: 0,
1014 .GlobalPriority: false,
1015 .TSFlags: 0x00, /* TSFlags */
1016 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1017 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1018 .SuperClasses: nullptr, .SuperClassesSize: 0,
1019 .OrderFunc: GR128BitGetRawAllocationOrder
1020 };
1021
1022 extern const TargetRegisterClass ADDR128BitRegClass = {
1023 .MC: &SystemZMCRegisterClasses[ADDR128BitRegClassID],
1024 .SubClassMask: ADDR128BitSubClassMask,
1025 .SuperRegIndices: SuperRegIdxSeqs + 2,
1026 .LaneMask: LaneBitmask(0x000000000000000F),
1027 .AllocationPriority: 0,
1028 .GlobalPriority: false,
1029 .TSFlags: 0x00, /* TSFlags */
1030 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1031 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1032 .SuperClasses: ADDR128BitSuperclasses, .SuperClassesSize: 1,
1033 .OrderFunc: ADDR128BitGetRawAllocationOrder
1034 };
1035
1036
1037} // namespace SystemZ
1038namespace {
1039
1040 const TargetRegisterClass *const RegisterClasses[] = {
1041 &SystemZ::VR16BitRegClass,
1042 &SystemZ::FP16BitRegClass,
1043 &SystemZ::GRX32BitRegClass,
1044 &SystemZ::VR32BitRegClass,
1045 &SystemZ::AR32BitRegClass,
1046 &SystemZ::FP32BitRegClass,
1047 &SystemZ::GR32BitRegClass,
1048 &SystemZ::GRH32BitRegClass,
1049 &SystemZ::ADDR32BitRegClass,
1050 &SystemZ::CCRRegClass,
1051 &SystemZ::FPCRegsRegClass,
1052 &SystemZ::AnyRegBitRegClass,
1053 &SystemZ::AnyRegBit_with_subreg_h16RegClass,
1054 &SystemZ::VR64BitRegClass,
1055 &SystemZ::AnyRegBit_with_subreg_h64RegClass,
1056 &SystemZ::CR64BitRegClass,
1057 &SystemZ::FP64BitRegClass,
1058 &SystemZ::GR64BitRegClass,
1059 &SystemZ::ADDR64BitRegClass,
1060 &SystemZ::VR128BitRegClass,
1061 &SystemZ::VF128BitRegClass,
1062 &SystemZ::FP128BitRegClass,
1063 &SystemZ::GR128BitRegClass,
1064 &SystemZ::ADDR128BitRegClass,
1065 };
1066} // namespace
1067
1068static const uint8_t CostPerUseTable[] = {
10690, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1070
1071
1072static const bool InAllocatableClassTable[] = {
1073false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
1074
1075
1076static const TargetRegisterInfoDesc SystemZRegInfoDesc = { // Extra Descriptors
1077.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
1078
1079unsigned SystemZGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1080 static const uint8_t RowMap[8] = {
1081 0, 0, 0, 0, 1, 1, 0, 0,
1082 };
1083 static const uint8_t Rows[2][8] = {
1084 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1085 { SystemZ::subreg_lh32_then_subreg_h16, SystemZ::subreg_lh32, 0, SystemZ::subreg_ll32, 0, 0, 0, 0, },
1086 };
1087
1088 --IdxA; assert(IdxA < 8); (void) IdxA;
1089 --IdxB; assert(IdxB < 8);
1090 return Rows[RowMap[IdxA]][IdxB];
1091}
1092
1093unsigned SystemZGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1094 static const uint8_t Table[8][8] = {
1095 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1096 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1097 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1098 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1099 { 0, 0, 0, 0, 0, SystemZ::subreg_h32, SystemZ::subreg_l32, SystemZ::subreg_h16, },
1100 { 0, 0, 0, 0, 0, SystemZ::subreg_h32, SystemZ::subreg_l32, SystemZ::subreg_h16, },
1101 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1102 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1103 };
1104
1105 --IdxA; assert(IdxA < 8);
1106 --IdxB; assert(IdxB < 8);
1107 return Table[IdxA][IdxB];
1108 }
1109
1110 struct MaskRolOp {
1111 LaneBitmask Mask;
1112 uint8_t RotateLeft;
1113 };
1114 static const MaskRolOp LaneMaskComposeSequences[] = {
1115 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
1116 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
1117 { .Mask: LaneBitmask(0x0000000000000001), .RotateLeft: 3 }, { .Mask: LaneBitmask(0x0000000000000002), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
1118 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 7
1119 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 9
1120 };
1121 static const uint8_t CompositeSequences[] = {
1122 0, // to subreg_h16
1123 0, // to subreg_h32
1124 0, // to subreg_h64
1125 2, // to subreg_l32
1126 4, // to subreg_l64
1127 7, // to subreg_lh32
1128 9, // to subreg_ll32
1129 7 // to subreg_lh32_then_subreg_h16
1130 };
1131
1132LaneBitmask SystemZGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1133 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
1134 LaneBitmask Result;
1135 for (const MaskRolOp *Ops =
1136 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1137 Ops->Mask.any(); ++Ops) {
1138 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
1139 if (unsigned S = Ops->RotateLeft)
1140 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
1141 else
1142 Result |= LaneBitmask(M);
1143 }
1144 return Result;
1145}
1146
1147LaneBitmask SystemZGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1148 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
1149 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
1150 LaneBitmask Result;
1151 for (const MaskRolOp *Ops =
1152 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1153 Ops->Mask.any(); ++Ops) {
1154 LaneBitmask::Type M = LaneMask.getAsInteger();
1155 if (unsigned S = Ops->RotateLeft)
1156 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
1157 else
1158 Result |= LaneBitmask(M);
1159 }
1160 return Result;
1161}
1162
1163const TargetRegisterClass *SystemZGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1164 static constexpr uint8_t Table[24][8] = {
1165 { // VR16Bit
1166 0, // subreg_h16
1167 0, // subreg_h32
1168 0, // subreg_h64
1169 0, // subreg_l32
1170 0, // subreg_l64
1171 0, // subreg_lh32
1172 0, // subreg_ll32
1173 0, // subreg_lh32_then_subreg_h16
1174 },
1175 { // FP16Bit
1176 0, // subreg_h16
1177 0, // subreg_h32
1178 0, // subreg_h64
1179 0, // subreg_l32
1180 0, // subreg_l64
1181 0, // subreg_lh32
1182 0, // subreg_ll32
1183 0, // subreg_lh32_then_subreg_h16
1184 },
1185 { // GRX32Bit
1186 0, // subreg_h16
1187 0, // subreg_h32
1188 0, // subreg_h64
1189 0, // subreg_l32
1190 0, // subreg_l64
1191 0, // subreg_lh32
1192 0, // subreg_ll32
1193 0, // subreg_lh32_then_subreg_h16
1194 },
1195 { // VR32Bit
1196 4, // subreg_h16 -> VR32Bit
1197 0, // subreg_h32
1198 0, // subreg_h64
1199 0, // subreg_l32
1200 0, // subreg_l64
1201 0, // subreg_lh32
1202 0, // subreg_ll32
1203 0, // subreg_lh32_then_subreg_h16
1204 },
1205 { // AR32Bit
1206 0, // subreg_h16
1207 0, // subreg_h32
1208 0, // subreg_h64
1209 0, // subreg_l32
1210 0, // subreg_l64
1211 0, // subreg_lh32
1212 0, // subreg_ll32
1213 0, // subreg_lh32_then_subreg_h16
1214 },
1215 { // FP32Bit
1216 6, // subreg_h16 -> FP32Bit
1217 0, // subreg_h32
1218 0, // subreg_h64
1219 0, // subreg_l32
1220 0, // subreg_l64
1221 0, // subreg_lh32
1222 0, // subreg_ll32
1223 0, // subreg_lh32_then_subreg_h16
1224 },
1225 { // GR32Bit
1226 0, // subreg_h16
1227 0, // subreg_h32
1228 0, // subreg_h64
1229 0, // subreg_l32
1230 0, // subreg_l64
1231 0, // subreg_lh32
1232 0, // subreg_ll32
1233 0, // subreg_lh32_then_subreg_h16
1234 },
1235 { // GRH32Bit
1236 0, // subreg_h16
1237 0, // subreg_h32
1238 0, // subreg_h64
1239 0, // subreg_l32
1240 0, // subreg_l64
1241 0, // subreg_lh32
1242 0, // subreg_ll32
1243 0, // subreg_lh32_then_subreg_h16
1244 },
1245 { // ADDR32Bit
1246 0, // subreg_h16
1247 0, // subreg_h32
1248 0, // subreg_h64
1249 0, // subreg_l32
1250 0, // subreg_l64
1251 0, // subreg_lh32
1252 0, // subreg_ll32
1253 0, // subreg_lh32_then_subreg_h16
1254 },
1255 { // CCR
1256 0, // subreg_h16
1257 0, // subreg_h32
1258 0, // subreg_h64
1259 0, // subreg_l32
1260 0, // subreg_l64
1261 0, // subreg_lh32
1262 0, // subreg_ll32
1263 0, // subreg_lh32_then_subreg_h16
1264 },
1265 { // FPCRegs
1266 0, // subreg_h16
1267 0, // subreg_h32
1268 0, // subreg_h64
1269 0, // subreg_l32
1270 0, // subreg_l64
1271 0, // subreg_lh32
1272 0, // subreg_ll32
1273 0, // subreg_lh32_then_subreg_h16
1274 },
1275 { // AnyRegBit
1276 13, // subreg_h16 -> AnyRegBit_with_subreg_h16
1277 12, // subreg_h32 -> AnyRegBit
1278 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
1279 18, // subreg_l32 -> GR64Bit
1280 0, // subreg_l64
1281 0, // subreg_lh32
1282 0, // subreg_ll32
1283 0, // subreg_lh32_then_subreg_h16
1284 },
1285 { // AnyRegBit_with_subreg_h16
1286 13, // subreg_h16 -> AnyRegBit_with_subreg_h16
1287 13, // subreg_h32 -> AnyRegBit_with_subreg_h16
1288 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
1289 0, // subreg_l32
1290 0, // subreg_l64
1291 0, // subreg_lh32
1292 0, // subreg_ll32
1293 0, // subreg_lh32_then_subreg_h16
1294 },
1295 { // VR64Bit
1296 14, // subreg_h16 -> VR64Bit
1297 14, // subreg_h32 -> VR64Bit
1298 0, // subreg_h64
1299 0, // subreg_l32
1300 0, // subreg_l64
1301 0, // subreg_lh32
1302 0, // subreg_ll32
1303 0, // subreg_lh32_then_subreg_h16
1304 },
1305 { // AnyRegBit_with_subreg_h64
1306 15, // subreg_h16 -> AnyRegBit_with_subreg_h64
1307 15, // subreg_h32 -> AnyRegBit_with_subreg_h64
1308 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
1309 0, // subreg_l32
1310 0, // subreg_l64
1311 0, // subreg_lh32
1312 0, // subreg_ll32
1313 0, // subreg_lh32_then_subreg_h16
1314 },
1315 { // CR64Bit
1316 0, // subreg_h16
1317 0, // subreg_h32
1318 0, // subreg_h64
1319 0, // subreg_l32
1320 0, // subreg_l64
1321 0, // subreg_lh32
1322 0, // subreg_ll32
1323 0, // subreg_lh32_then_subreg_h16
1324 },
1325 { // FP64Bit
1326 17, // subreg_h16 -> FP64Bit
1327 17, // subreg_h32 -> FP64Bit
1328 0, // subreg_h64
1329 0, // subreg_l32
1330 0, // subreg_l64
1331 0, // subreg_lh32
1332 0, // subreg_ll32
1333 0, // subreg_lh32_then_subreg_h16
1334 },
1335 { // GR64Bit
1336 0, // subreg_h16
1337 18, // subreg_h32 -> GR64Bit
1338 0, // subreg_h64
1339 18, // subreg_l32 -> GR64Bit
1340 0, // subreg_l64
1341 0, // subreg_lh32
1342 0, // subreg_ll32
1343 0, // subreg_lh32_then_subreg_h16
1344 },
1345 { // ADDR64Bit
1346 0, // subreg_h16
1347 19, // subreg_h32 -> ADDR64Bit
1348 0, // subreg_h64
1349 19, // subreg_l32 -> ADDR64Bit
1350 0, // subreg_l64
1351 0, // subreg_lh32
1352 0, // subreg_ll32
1353 0, // subreg_lh32_then_subreg_h16
1354 },
1355 { // VR128Bit
1356 20, // subreg_h16 -> VR128Bit
1357 20, // subreg_h32 -> VR128Bit
1358 20, // subreg_h64 -> VR128Bit
1359 0, // subreg_l32
1360 0, // subreg_l64
1361 0, // subreg_lh32
1362 0, // subreg_ll32
1363 0, // subreg_lh32_then_subreg_h16
1364 },
1365 { // VF128Bit
1366 21, // subreg_h16 -> VF128Bit
1367 21, // subreg_h32 -> VF128Bit
1368 21, // subreg_h64 -> VF128Bit
1369 0, // subreg_l32
1370 0, // subreg_l64
1371 0, // subreg_lh32
1372 0, // subreg_ll32
1373 0, // subreg_lh32_then_subreg_h16
1374 },
1375 { // FP128Bit
1376 22, // subreg_h16 -> FP128Bit
1377 22, // subreg_h32 -> FP128Bit
1378 22, // subreg_h64 -> FP128Bit
1379 0, // subreg_l32
1380 22, // subreg_l64 -> FP128Bit
1381 22, // subreg_lh32 -> FP128Bit
1382 0, // subreg_ll32
1383 22, // subreg_lh32_then_subreg_h16 -> FP128Bit
1384 },
1385 { // GR128Bit
1386 0, // subreg_h16
1387 23, // subreg_h32 -> GR128Bit
1388 23, // subreg_h64 -> GR128Bit
1389 23, // subreg_l32 -> GR128Bit
1390 23, // subreg_l64 -> GR128Bit
1391 23, // subreg_lh32 -> GR128Bit
1392 23, // subreg_ll32 -> GR128Bit
1393 0, // subreg_lh32_then_subreg_h16
1394 },
1395 { // ADDR128Bit
1396 0, // subreg_h16
1397 24, // subreg_h32 -> ADDR128Bit
1398 24, // subreg_h64 -> ADDR128Bit
1399 24, // subreg_l32 -> ADDR128Bit
1400 24, // subreg_l64 -> ADDR128Bit
1401 24, // subreg_lh32 -> ADDR128Bit
1402 24, // subreg_ll32 -> ADDR128Bit
1403 0, // subreg_lh32_then_subreg_h16
1404 },
1405
1406 };
1407 assert(RC && "Missing regclass");
1408 if (!Idx) return RC;
1409 --Idx;
1410 assert(Idx < 8 && "Bad subreg");
1411 unsigned TV = Table[RC->getID()][Idx];
1412 return TV ? getRegClass(i: TV - 1) : nullptr;
1413}const TargetRegisterClass *SystemZGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1414 static constexpr uint8_t Table[24][8] = {
1415 { // VR16Bit
1416 0, // VR16Bit:subreg_h16
1417 0, // VR16Bit:subreg_h32
1418 0, // VR16Bit:subreg_h64
1419 0, // VR16Bit:subreg_l32
1420 0, // VR16Bit:subreg_l64
1421 0, // VR16Bit:subreg_lh32
1422 0, // VR16Bit:subreg_ll32
1423 0, // VR16Bit:subreg_lh32_then_subreg_h16
1424 },
1425 { // FP16Bit
1426 0, // FP16Bit:subreg_h16
1427 0, // FP16Bit:subreg_h32
1428 0, // FP16Bit:subreg_h64
1429 0, // FP16Bit:subreg_l32
1430 0, // FP16Bit:subreg_l64
1431 0, // FP16Bit:subreg_lh32
1432 0, // FP16Bit:subreg_ll32
1433 0, // FP16Bit:subreg_lh32_then_subreg_h16
1434 },
1435 { // GRX32Bit
1436 0, // GRX32Bit:subreg_h16
1437 0, // GRX32Bit:subreg_h32
1438 0, // GRX32Bit:subreg_h64
1439 0, // GRX32Bit:subreg_l32
1440 0, // GRX32Bit:subreg_l64
1441 0, // GRX32Bit:subreg_lh32
1442 0, // GRX32Bit:subreg_ll32
1443 0, // GRX32Bit:subreg_lh32_then_subreg_h16
1444 },
1445 { // VR32Bit
1446 1, // VR32Bit:subreg_h16 -> VR16Bit
1447 0, // VR32Bit:subreg_h32
1448 0, // VR32Bit:subreg_h64
1449 0, // VR32Bit:subreg_l32
1450 0, // VR32Bit:subreg_l64
1451 0, // VR32Bit:subreg_lh32
1452 0, // VR32Bit:subreg_ll32
1453 0, // VR32Bit:subreg_lh32_then_subreg_h16
1454 },
1455 { // AR32Bit
1456 0, // AR32Bit:subreg_h16
1457 0, // AR32Bit:subreg_h32
1458 0, // AR32Bit:subreg_h64
1459 0, // AR32Bit:subreg_l32
1460 0, // AR32Bit:subreg_l64
1461 0, // AR32Bit:subreg_lh32
1462 0, // AR32Bit:subreg_ll32
1463 0, // AR32Bit:subreg_lh32_then_subreg_h16
1464 },
1465 { // FP32Bit
1466 2, // FP32Bit:subreg_h16 -> FP16Bit
1467 0, // FP32Bit:subreg_h32
1468 0, // FP32Bit:subreg_h64
1469 0, // FP32Bit:subreg_l32
1470 0, // FP32Bit:subreg_l64
1471 0, // FP32Bit:subreg_lh32
1472 0, // FP32Bit:subreg_ll32
1473 0, // FP32Bit:subreg_lh32_then_subreg_h16
1474 },
1475 { // GR32Bit
1476 0, // GR32Bit:subreg_h16
1477 0, // GR32Bit:subreg_h32
1478 0, // GR32Bit:subreg_h64
1479 0, // GR32Bit:subreg_l32
1480 0, // GR32Bit:subreg_l64
1481 0, // GR32Bit:subreg_lh32
1482 0, // GR32Bit:subreg_ll32
1483 0, // GR32Bit:subreg_lh32_then_subreg_h16
1484 },
1485 { // GRH32Bit
1486 0, // GRH32Bit:subreg_h16
1487 0, // GRH32Bit:subreg_h32
1488 0, // GRH32Bit:subreg_h64
1489 0, // GRH32Bit:subreg_l32
1490 0, // GRH32Bit:subreg_l64
1491 0, // GRH32Bit:subreg_lh32
1492 0, // GRH32Bit:subreg_ll32
1493 0, // GRH32Bit:subreg_lh32_then_subreg_h16
1494 },
1495 { // ADDR32Bit
1496 0, // ADDR32Bit:subreg_h16
1497 0, // ADDR32Bit:subreg_h32
1498 0, // ADDR32Bit:subreg_h64
1499 0, // ADDR32Bit:subreg_l32
1500 0, // ADDR32Bit:subreg_l64
1501 0, // ADDR32Bit:subreg_lh32
1502 0, // ADDR32Bit:subreg_ll32
1503 0, // ADDR32Bit:subreg_lh32_then_subreg_h16
1504 },
1505 { // CCR
1506 0, // CCR:subreg_h16
1507 0, // CCR:subreg_h32
1508 0, // CCR:subreg_h64
1509 0, // CCR:subreg_l32
1510 0, // CCR:subreg_l64
1511 0, // CCR:subreg_lh32
1512 0, // CCR:subreg_ll32
1513 0, // CCR:subreg_lh32_then_subreg_h16
1514 },
1515 { // FPCRegs
1516 0, // FPCRegs:subreg_h16
1517 0, // FPCRegs:subreg_h32
1518 0, // FPCRegs:subreg_h64
1519 0, // FPCRegs:subreg_l32
1520 0, // FPCRegs:subreg_l64
1521 0, // FPCRegs:subreg_lh32
1522 0, // FPCRegs:subreg_ll32
1523 0, // FPCRegs:subreg_lh32_then_subreg_h16
1524 },
1525 { // AnyRegBit
1526 1, // AnyRegBit:subreg_h16 -> VR16Bit
1527 4, // AnyRegBit:subreg_h32 -> VR32Bit
1528 17, // AnyRegBit:subreg_h64 -> FP64Bit
1529 7, // AnyRegBit:subreg_l32 -> GR32Bit
1530 0, // AnyRegBit:subreg_l64
1531 0, // AnyRegBit:subreg_lh32
1532 0, // AnyRegBit:subreg_ll32
1533 0, // AnyRegBit:subreg_lh32_then_subreg_h16
1534 },
1535 { // AnyRegBit_with_subreg_h16
1536 1, // AnyRegBit_with_subreg_h16:subreg_h16 -> VR16Bit
1537 4, // AnyRegBit_with_subreg_h16:subreg_h32 -> VR32Bit
1538 17, // AnyRegBit_with_subreg_h16:subreg_h64 -> FP64Bit
1539 0, // AnyRegBit_with_subreg_h16:subreg_l32
1540 0, // AnyRegBit_with_subreg_h16:subreg_l64
1541 0, // AnyRegBit_with_subreg_h16:subreg_lh32
1542 0, // AnyRegBit_with_subreg_h16:subreg_ll32
1543 0, // AnyRegBit_with_subreg_h16:subreg_lh32_then_subreg_h16
1544 },
1545 { // VR64Bit
1546 1, // VR64Bit:subreg_h16 -> VR16Bit
1547 4, // VR64Bit:subreg_h32 -> VR32Bit
1548 0, // VR64Bit:subreg_h64
1549 0, // VR64Bit:subreg_l32
1550 0, // VR64Bit:subreg_l64
1551 0, // VR64Bit:subreg_lh32
1552 0, // VR64Bit:subreg_ll32
1553 0, // VR64Bit:subreg_lh32_then_subreg_h16
1554 },
1555 { // AnyRegBit_with_subreg_h64
1556 2, // AnyRegBit_with_subreg_h64:subreg_h16 -> FP16Bit
1557 6, // AnyRegBit_with_subreg_h64:subreg_h32 -> FP32Bit
1558 17, // AnyRegBit_with_subreg_h64:subreg_h64 -> FP64Bit
1559 0, // AnyRegBit_with_subreg_h64:subreg_l32
1560 0, // AnyRegBit_with_subreg_h64:subreg_l64
1561 0, // AnyRegBit_with_subreg_h64:subreg_lh32
1562 0, // AnyRegBit_with_subreg_h64:subreg_ll32
1563 0, // AnyRegBit_with_subreg_h64:subreg_lh32_then_subreg_h16
1564 },
1565 { // CR64Bit
1566 0, // CR64Bit:subreg_h16
1567 0, // CR64Bit:subreg_h32
1568 0, // CR64Bit:subreg_h64
1569 0, // CR64Bit:subreg_l32
1570 0, // CR64Bit:subreg_l64
1571 0, // CR64Bit:subreg_lh32
1572 0, // CR64Bit:subreg_ll32
1573 0, // CR64Bit:subreg_lh32_then_subreg_h16
1574 },
1575 { // FP64Bit
1576 2, // FP64Bit:subreg_h16 -> FP16Bit
1577 6, // FP64Bit:subreg_h32 -> FP32Bit
1578 0, // FP64Bit:subreg_h64
1579 0, // FP64Bit:subreg_l32
1580 0, // FP64Bit:subreg_l64
1581 0, // FP64Bit:subreg_lh32
1582 0, // FP64Bit:subreg_ll32
1583 0, // FP64Bit:subreg_lh32_then_subreg_h16
1584 },
1585 { // GR64Bit
1586 0, // GR64Bit:subreg_h16
1587 8, // GR64Bit:subreg_h32 -> GRH32Bit
1588 0, // GR64Bit:subreg_h64
1589 7, // GR64Bit:subreg_l32 -> GR32Bit
1590 0, // GR64Bit:subreg_l64
1591 0, // GR64Bit:subreg_lh32
1592 0, // GR64Bit:subreg_ll32
1593 0, // GR64Bit:subreg_lh32_then_subreg_h16
1594 },
1595 { // ADDR64Bit
1596 0, // ADDR64Bit:subreg_h16
1597 8, // ADDR64Bit:subreg_h32 -> GRH32Bit
1598 0, // ADDR64Bit:subreg_h64
1599 9, // ADDR64Bit:subreg_l32 -> ADDR32Bit
1600 0, // ADDR64Bit:subreg_l64
1601 0, // ADDR64Bit:subreg_lh32
1602 0, // ADDR64Bit:subreg_ll32
1603 0, // ADDR64Bit:subreg_lh32_then_subreg_h16
1604 },
1605 { // VR128Bit
1606 1, // VR128Bit:subreg_h16 -> VR16Bit
1607 4, // VR128Bit:subreg_h32 -> VR32Bit
1608 14, // VR128Bit:subreg_h64 -> VR64Bit
1609 0, // VR128Bit:subreg_l32
1610 0, // VR128Bit:subreg_l64
1611 0, // VR128Bit:subreg_lh32
1612 0, // VR128Bit:subreg_ll32
1613 0, // VR128Bit:subreg_lh32_then_subreg_h16
1614 },
1615 { // VF128Bit
1616 2, // VF128Bit:subreg_h16 -> FP16Bit
1617 6, // VF128Bit:subreg_h32 -> FP32Bit
1618 17, // VF128Bit:subreg_h64 -> FP64Bit
1619 0, // VF128Bit:subreg_l32
1620 0, // VF128Bit:subreg_l64
1621 0, // VF128Bit:subreg_lh32
1622 0, // VF128Bit:subreg_ll32
1623 0, // VF128Bit:subreg_lh32_then_subreg_h16
1624 },
1625 { // FP128Bit
1626 2, // FP128Bit:subreg_h16 -> FP16Bit
1627 6, // FP128Bit:subreg_h32 -> FP32Bit
1628 17, // FP128Bit:subreg_h64 -> FP64Bit
1629 0, // FP128Bit:subreg_l32
1630 17, // FP128Bit:subreg_l64 -> FP64Bit
1631 6, // FP128Bit:subreg_lh32 -> FP32Bit
1632 0, // FP128Bit:subreg_ll32
1633 2, // FP128Bit:subreg_lh32_then_subreg_h16 -> FP16Bit
1634 },
1635 { // GR128Bit
1636 0, // GR128Bit:subreg_h16
1637 8, // GR128Bit:subreg_h32 -> GRH32Bit
1638 18, // GR128Bit:subreg_h64 -> GR64Bit
1639 7, // GR128Bit:subreg_l32 -> GR32Bit
1640 19, // GR128Bit:subreg_l64 -> ADDR64Bit
1641 8, // GR128Bit:subreg_lh32 -> GRH32Bit
1642 9, // GR128Bit:subreg_ll32 -> ADDR32Bit
1643 0, // GR128Bit:subreg_lh32_then_subreg_h16
1644 },
1645 { // ADDR128Bit
1646 0, // ADDR128Bit:subreg_h16
1647 8, // ADDR128Bit:subreg_h32 -> GRH32Bit
1648 19, // ADDR128Bit:subreg_h64 -> ADDR64Bit
1649 9, // ADDR128Bit:subreg_l32 -> ADDR32Bit
1650 19, // ADDR128Bit:subreg_l64 -> ADDR64Bit
1651 8, // ADDR128Bit:subreg_lh32 -> GRH32Bit
1652 9, // ADDR128Bit:subreg_ll32 -> ADDR32Bit
1653 0, // ADDR128Bit:subreg_lh32_then_subreg_h16
1654 },
1655
1656 };
1657 assert(RC && "Missing regclass");
1658 if (!Idx) return RC;
1659 --Idx;
1660 assert(Idx < 8 && "Bad subreg");
1661 unsigned TV = Table[RC->getID()][Idx];
1662 return TV ? getRegClass(i: TV - 1) : nullptr;
1663}/// Get the weight in units of pressure for this register class.
1664const RegClassWeight &SystemZGenRegisterInfo::
1665getRegClassWeight(const TargetRegisterClass *RC) const {
1666 static const RegClassWeight RCWeightTable[] = {
1667 {.RegWeight: 1, .WeightLimit: 32}, // VR16Bit
1668 {.RegWeight: 1, .WeightLimit: 16}, // FP16Bit
1669 {.RegWeight: 1, .WeightLimit: 32}, // GRX32Bit
1670 {.RegWeight: 1, .WeightLimit: 32}, // VR32Bit
1671 {.RegWeight: 0, .WeightLimit: 0}, // AR32Bit
1672 {.RegWeight: 1, .WeightLimit: 16}, // FP32Bit
1673 {.RegWeight: 1, .WeightLimit: 16}, // GR32Bit
1674 {.RegWeight: 1, .WeightLimit: 16}, // GRH32Bit
1675 {.RegWeight: 1, .WeightLimit: 15}, // ADDR32Bit
1676 {.RegWeight: 0, .WeightLimit: 0}, // CCR
1677 {.RegWeight: 0, .WeightLimit: 0}, // FPCRegs
1678 {.RegWeight: 1, .WeightLimit: 48}, // AnyRegBit
1679 {.RegWeight: 1, .WeightLimit: 16}, // AnyRegBit_with_subreg_h16
1680 {.RegWeight: 1, .WeightLimit: 32}, // VR64Bit
1681 {.RegWeight: 1, .WeightLimit: 16}, // AnyRegBit_with_subreg_h64
1682 {.RegWeight: 0, .WeightLimit: 0}, // CR64Bit
1683 {.RegWeight: 1, .WeightLimit: 16}, // FP64Bit
1684 {.RegWeight: 2, .WeightLimit: 32}, // GR64Bit
1685 {.RegWeight: 2, .WeightLimit: 30}, // ADDR64Bit
1686 {.RegWeight: 1, .WeightLimit: 32}, // VR128Bit
1687 {.RegWeight: 1, .WeightLimit: 16}, // VF128Bit
1688 {.RegWeight: 2, .WeightLimit: 16}, // FP128Bit
1689 {.RegWeight: 4, .WeightLimit: 32}, // GR128Bit
1690 {.RegWeight: 4, .WeightLimit: 28}, // ADDR128Bit
1691 };
1692 return RCWeightTable[RC->getID()];
1693}
1694
1695/// Get the weight in units of pressure for this register unit.
1696unsigned SystemZGenRegisterInfo::
1697getRegUnitWeight(MCRegUnit RegUnit) const {
1698 assert(static_cast<unsigned>(RegUnit) < 98 && "invalid register unit");
1699 // All register units have unit weight.
1700 return 1;
1701}
1702
1703
1704// Get the number of dimensions of register pressure.
1705unsigned SystemZGenRegisterInfo::getNumRegPressureSets() const {
1706 return 5;
1707}
1708
1709// Get the name of this register unit pressure set.
1710const char *SystemZGenRegisterInfo::
1711getRegPressureSetName(unsigned Idx) const {
1712 static const char *PressureNameTable[] = {
1713 "FP16Bit",
1714 "GR32Bit",
1715 "GRH32Bit",
1716 "VR16Bit",
1717 "GRX32Bit",
1718 };
1719 return PressureNameTable[Idx];
1720}
1721
1722// Get the register unit pressure limit for this dimension.
1723// This limit must be adjusted dynamically for reserved registers.
1724unsigned SystemZGenRegisterInfo::
1725getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1726 static const uint8_t PressureLimitTable[] = {
1727 16, // 0: FP16Bit
1728 16, // 1: GR32Bit
1729 16, // 2: GRH32Bit
1730 32, // 3: VR16Bit
1731 32, // 4: GRX32Bit
1732 };
1733 return PressureLimitTable[Idx];
1734}
1735
1736/// Table of pressure sets per register class or unit.
1737static const int RCSetsTable[] = {
1738 /* 0 */ 0, 3, -1,
1739 /* 3 */ 1, 4, -1,
1740 /* 6 */ 2, 4, -1,
1741};
1742
1743/// Get the dimensions of register pressure impacted by this register class.
1744/// Returns a -1 terminated array of pressure set IDs
1745const int *SystemZGenRegisterInfo::
1746getRegClassPressureSets(const TargetRegisterClass *RC) const {
1747 static const uint8_t RCSetStartTable[] = {
1748 1,0,4,1,2,0,3,6,3,2,2,2,2,1,2,2,0,4,4,1,0,0,4,4,};
1749 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1750}
1751
1752/// Get the dimensions of register pressure impacted by this register unit.
1753/// Returns a -1 terminated array of pressure set IDs
1754const int *SystemZGenRegisterInfo::
1755getRegUnitPressureSets(MCRegUnit RegUnit) const {
1756 assert(static_cast<unsigned>(RegUnit) < 98 && "invalid register unit");
1757 static const uint8_t RUSetStartTable[] = {
1758 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,};
1759 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1760}
1761
1762extern const MCRegisterDesc SystemZRegDesc[];
1763extern const int16_t SystemZRegDiffLists[];
1764extern const LaneBitmask SystemZLaneMaskLists[];
1765extern const char SystemZRegStrings[];
1766extern const char SystemZRegClassStrings[];
1767extern const MCPhysReg SystemZRegUnitRoots[][2];
1768extern const uint16_t SystemZSubRegIdxLists[];
1769extern const uint16_t SystemZRegEncodingTable[];
1770// SystemZ Dwarf<->LLVM register mappings.
1771extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[];
1772extern const unsigned SystemZDwarfFlavour0Dwarf2LSize;
1773
1774extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[];
1775extern const unsigned SystemZEHFlavour0Dwarf2LSize;
1776
1777extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[];
1778extern const unsigned SystemZDwarfFlavour0L2DwarfSize;
1779
1780extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[];
1781extern const unsigned SystemZEHFlavour0L2DwarfSize;
1782
1783
1784SystemZGenRegisterInfo::
1785SystemZGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1786 unsigned PC, unsigned HwMode)
1787 : TargetRegisterInfo(&SystemZRegInfoDesc, RegisterClasses, RegisterClasses+24,
1788 SystemZSubRegIndexStrings, SystemZSubRegIndexNameOffsets,
1789 SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
1790
1791 LaneBitmask(0xFFFFFFFFFFFFFFFC), RegClassInfos, VTLists, HwMode) {
1792 InitMCRegisterInfo(D: SystemZRegDesc, NR: 227, RA, PC,
1793 C: SystemZMCRegisterClasses, NC: 24,
1794 RURoots: SystemZRegUnitRoots,
1795 NRU: 98,
1796 DL: SystemZRegDiffLists,
1797 RUMS: SystemZLaneMaskLists,
1798 Strings: SystemZRegStrings,
1799 ClassStrings: SystemZRegClassStrings,
1800 SubIndices: SystemZSubRegIdxLists,
1801 NumIndices: 9,
1802 RET: SystemZRegEncodingTable,
1803 RUI: nullptr);
1804
1805 switch (DwarfFlavour) {
1806 default:
1807 llvm_unreachable("Unknown DWARF flavour");
1808 case 0:
1809 mapDwarfRegsToLLVMRegs(Map: SystemZDwarfFlavour0Dwarf2L, Size: SystemZDwarfFlavour0Dwarf2LSize, isEH: false);
1810 break;
1811 }
1812 switch (EHFlavour) {
1813 default:
1814 llvm_unreachable("Unknown DWARF flavour");
1815 case 0:
1816 mapDwarfRegsToLLVMRegs(Map: SystemZEHFlavour0Dwarf2L, Size: SystemZEHFlavour0Dwarf2LSize, isEH: true);
1817 break;
1818 }
1819 switch (DwarfFlavour) {
1820 default:
1821 llvm_unreachable("Unknown DWARF flavour");
1822 case 0:
1823 mapLLVMRegsToDwarfRegs(Map: SystemZDwarfFlavour0L2Dwarf, Size: SystemZDwarfFlavour0L2DwarfSize, isEH: false);
1824 break;
1825 }
1826 switch (EHFlavour) {
1827 default:
1828 llvm_unreachable("Unknown DWARF flavour");
1829 case 0:
1830 mapLLVMRegsToDwarfRegs(Map: SystemZEHFlavour0L2Dwarf, Size: SystemZEHFlavour0L2DwarfSize, isEH: true);
1831 break;
1832 }
1833}
1834
1835static const MCPhysReg CSR_SystemZ_AllRegs_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
1836static const uint32_t CSR_SystemZ_AllRegs_RegMask[] = { 0x00000000, 0x00000000, 0x0007fff8, 0x0007fff8, 0x07fffff8, 0xe7ffe000, 0xf7ffe7ff, 0x00000007, };
1837static const MCPhysReg CSR_SystemZ_AllRegs_Vector_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, 0 };
1838static const uint32_t CSR_SystemZ_AllRegs_Vector_RegMask[] = { 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xffffffff, 0xe7ffe7ff, 0xf7ffe7ff, 0x00000007, };
1839static const MCPhysReg CSR_SystemZ_ELF_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
1840static const uint32_t CSR_SystemZ_ELF_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07fe0000, 0xc7fe07fe, 0x00000007, };
1841static const MCPhysReg CSR_SystemZ_NoRegs_SaveList[] = { 0 };
1842static const uint32_t CSR_SystemZ_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
1843static const MCPhysReg CSR_SystemZ_SwiftError_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
1844static const uint32_t CSR_SystemZ_SwiftError_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07ee0000, 0x47ee07ee, 0x00000007, };
1845static const MCPhysReg CSR_SystemZ_XPLINK64_SaveList[] = { SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F15D, SystemZ::F14D, SystemZ::F13D, SystemZ::F12D, SystemZ::F11D, SystemZ::F10D, SystemZ::F9D, SystemZ::F8D, 0 };
1846static const uint32_t CSR_SystemZ_XPLINK64_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07f80000, 0x87f807f8, 0x00000007, };
1847static const MCPhysReg CSR_SystemZ_XPLINK64_Vector_SaveList[] = { SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F15D, SystemZ::F14D, SystemZ::F13D, SystemZ::F12D, SystemZ::F11D, SystemZ::F10D, SystemZ::F9D, SystemZ::F8D, SystemZ::V23, SystemZ::V22, SystemZ::V21, SystemZ::V20, SystemZ::V19, SystemZ::V18, SystemZ::V17, SystemZ::V16, 0 };
1848static const uint32_t CSR_SystemZ_XPLINK64_Vector_RegMask[] = { 0x00000000, 0x07f80000, 0x07fff800, 0x07fff800, 0xfff80780, 0x07f80007, 0x87f807f8, 0x00000007, };
1849
1850
1851ArrayRef<const uint32_t *> SystemZGenRegisterInfo::getRegMasks() const {
1852 static const uint32_t *const Masks[] = {
1853 CSR_SystemZ_AllRegs_RegMask,
1854 CSR_SystemZ_AllRegs_Vector_RegMask,
1855 CSR_SystemZ_ELF_RegMask,
1856 CSR_SystemZ_NoRegs_RegMask,
1857 CSR_SystemZ_SwiftError_RegMask,
1858 CSR_SystemZ_XPLINK64_RegMask,
1859 CSR_SystemZ_XPLINK64_Vector_RegMask,
1860 };
1861 return ArrayRef(Masks);
1862}
1863
1864bool SystemZGenRegisterInfo::
1865isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1866 return
1867 false;
1868}
1869
1870bool SystemZGenRegisterInfo::
1871isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1872 return
1873 false;
1874}
1875
1876bool SystemZGenRegisterInfo::
1877isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1878 return
1879 false;
1880}
1881
1882bool SystemZGenRegisterInfo::
1883isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1884 return
1885 false;
1886}
1887
1888bool SystemZGenRegisterInfo::
1889isConstantPhysReg(MCRegister PhysReg) const {
1890 return
1891 false;
1892}
1893
1894ArrayRef<const char *> SystemZGenRegisterInfo::getRegMaskNames() const {
1895 static const char *Names[] = {
1896 "CSR_SystemZ_AllRegs",
1897 "CSR_SystemZ_AllRegs_Vector",
1898 "CSR_SystemZ_ELF",
1899 "CSR_SystemZ_NoRegs",
1900 "CSR_SystemZ_SwiftError",
1901 "CSR_SystemZ_XPLINK64",
1902 "CSR_SystemZ_XPLINK64_Vector",
1903 };
1904 return ArrayRef(Names);
1905}
1906
1907const SystemZFrameLowering *
1908SystemZGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1909 return static_cast<const SystemZFrameLowering *>(
1910 MF.getSubtarget().getFrameLowering());
1911}
1912
1913
1914} // namespace llvm
1915