1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass SystemZMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f16, MVT::Other,
17 /* 6 */ MVT::f32, MVT::Other,
18 /* 8 */ MVT::f64, MVT::Other,
19 /* 10 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::i128, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
20 /* 20 */ MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
21 /* 24 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v2f32, MVT::Other,
22 /* 31 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::Other,
23 /* 39 */ MVT::Untyped, MVT::Other,
24};
25
26static const char *SubRegIndexNameTable[] = { "subreg_h16", "subreg_h32", "subreg_h64", "subreg_l32", "subreg_l64", "subreg_lh32", "subreg_ll32", "subreg_lh32_then_subreg_h16", "" };
27
28static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
29 { .Offset: 65535, .Size: 65535 },
30 { .Offset: 16, .Size: 16 }, // subreg_h16
31 { .Offset: 32, .Size: 32 }, // subreg_h32
32 { .Offset: 64, .Size: 64 }, // subreg_h64
33 { .Offset: 0, .Size: 32 }, // subreg_l32
34 { .Offset: 0, .Size: 64 }, // subreg_l64
35 { .Offset: 32, .Size: 32 }, // subreg_lh32
36 { .Offset: 0, .Size: 32 }, // subreg_ll32
37 { .Offset: 48, .Size: 16 }, // subreg_lh32_then_subreg_h16
38 { .Offset: 65535, .Size: 65535 },
39 { .Offset: 16, .Size: 16 }, // subreg_h16
40 { .Offset: 32, .Size: 32 }, // subreg_h32
41 { .Offset: 64, .Size: 64 }, // subreg_h64
42 { .Offset: 0, .Size: 32 }, // subreg_l32
43 { .Offset: 0, .Size: 64 }, // subreg_l64
44 { .Offset: 32, .Size: 32 }, // subreg_lh32
45 { .Offset: 0, .Size: 32 }, // subreg_ll32
46 { .Offset: 48, .Size: 16 }, // subreg_lh32_then_subreg_h16
47};
48
49
50static const LaneBitmask SubRegIndexLaneMaskTable[] = {
51 LaneBitmask::getAll(),
52 LaneBitmask(0x0000000000000001), // subreg_h16
53 LaneBitmask(0x0000000000000001), // subreg_h32
54 LaneBitmask(0x0000000000000003), // subreg_h64
55 LaneBitmask(0x0000000000000002), // subreg_l32
56 LaneBitmask(0x000000000000000C), // subreg_l64
57 LaneBitmask(0x0000000000000008), // subreg_lh32
58 LaneBitmask(0x0000000000000004), // subreg_ll32
59 LaneBitmask(0x0000000000000008), // subreg_lh32_then_subreg_h16
60 };
61
62
63
64static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
65 // Mode = 0 (Default)
66 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 4 }, // VR16Bit
67 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 4 }, // FP16Bit
68 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GRX32Bit
69 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 20 }, // VR32Bit
70 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // AR32Bit
71 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 6 }, // FP32Bit
72 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GR32Bit
73 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GRH32Bit
74 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // ADDR32Bit
75 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // CCR
76 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // FPCRegs
77 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 24 }, // AnyRegBit
78 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h16
79 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 25 }, // VR64Bit
80 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h64
81 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // CR64Bit
82 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 8 }, // FP64Bit
83 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // GR64Bit
84 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // ADDR64Bit
85 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 10 }, // VR128Bit
86 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 31 }, // VF128Bit
87 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 18 }, // FP128Bit
88 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 39 }, // GR128Bit
89 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 39 }, // ADDR128Bit
90 // Mode = 1 (NoVecHwMode)
91 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 4 }, // VR16Bit
92 { .RegSize: 16, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // FP16Bit
93 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GRX32Bit
94 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 20 }, // VR32Bit
95 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // AR32Bit
96 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 6 }, // FP32Bit
97 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GR32Bit
98 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GRH32Bit
99 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // ADDR32Bit
100 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // CCR
101 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // FPCRegs
102 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 24 }, // AnyRegBit
103 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h16
104 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 25 }, // VR64Bit
105 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h64
106 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // CR64Bit
107 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 8 }, // FP64Bit
108 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // GR64Bit
109 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // ADDR64Bit
110 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 10 }, // VR128Bit
111 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 31 }, // VF128Bit
112 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 18 }, // FP128Bit
113 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 39 }, // GR128Bit
114 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 39 }, // ADDR128Bit
115};
116static const uint32_t VR16BitSubClassMask[] = {
117 0x00000003,
118 0x00397028, // subreg_h16
119 0x00200000, // subreg_lh32_then_subreg_h16
120};
121
122static const uint32_t FP16BitSubClassMask[] = {
123 0x00000002,
124 0x00315020, // subreg_h16
125 0x00200000, // subreg_lh32_then_subreg_h16
126};
127
128static const uint32_t GRX32BitSubClassMask[] = {
129 0x000001c4,
130 0x00c60000, // subreg_h32
131 0x00c60000, // subreg_l32
132 0x00c00000, // subreg_lh32
133 0x00c00000, // subreg_ll32
134};
135
136static const uint32_t VR32BitSubClassMask[] = {
137 0x00000028,
138 0x00397000, // subreg_h32
139 0x00200000, // subreg_lh32
140};
141
142static const uint32_t AR32BitSubClassMask[] = {
143 0x00000010,
144};
145
146static const uint32_t FP32BitSubClassMask[] = {
147 0x00000020,
148 0x00315000, // subreg_h32
149 0x00200000, // subreg_lh32
150};
151
152static const uint32_t GR32BitSubClassMask[] = {
153 0x00000140,
154 0x00c60000, // subreg_l32
155 0x00c00000, // subreg_ll32
156};
157
158static const uint32_t GRH32BitSubClassMask[] = {
159 0x00000080,
160 0x00c60000, // subreg_h32
161 0x00c00000, // subreg_lh32
162};
163
164static const uint32_t ADDR32BitSubClassMask[] = {
165 0x00000100,
166 0x00840000, // subreg_l32
167 0x00c00000, // subreg_ll32
168};
169
170static const uint32_t CCRSubClassMask[] = {
171 0x00000200,
172};
173
174static const uint32_t FPCRegsSubClassMask[] = {
175 0x00000400,
176};
177
178static const uint32_t AnyRegBitSubClassMask[] = {
179 0x00175800,
180 0x00f04000, // subreg_h64
181 0x00e00000, // subreg_l64
182};
183
184static const uint32_t AnyRegBit_with_subreg_h16SubClassMask[] = {
185 0x00115000,
186 0x00304000, // subreg_h64
187 0x00200000, // subreg_l64
188};
189
190static const uint32_t VR64BitSubClassMask[] = {
191 0x00012000,
192 0x00384000, // subreg_h64
193 0x00200000, // subreg_l64
194};
195
196static const uint32_t AnyRegBit_with_subreg_h64SubClassMask[] = {
197 0x00104000,
198};
199
200static const uint32_t CR64BitSubClassMask[] = {
201 0x00008000,
202};
203
204static const uint32_t FP64BitSubClassMask[] = {
205 0x00010000,
206 0x00304000, // subreg_h64
207 0x00200000, // subreg_l64
208};
209
210static const uint32_t GR64BitSubClassMask[] = {
211 0x00060000,
212 0x00c00000, // subreg_h64
213 0x00c00000, // subreg_l64
214};
215
216static const uint32_t ADDR64BitSubClassMask[] = {
217 0x00040000,
218 0x00800000, // subreg_h64
219 0x00c00000, // subreg_l64
220};
221
222static const uint32_t VR128BitSubClassMask[] = {
223 0x00180000,
224};
225
226static const uint32_t VF128BitSubClassMask[] = {
227 0x00100000,
228};
229
230static const uint32_t FP128BitSubClassMask[] = {
231 0x00200000,
232};
233
234static const uint32_t GR128BitSubClassMask[] = {
235 0x00c00000,
236};
237
238static const uint32_t ADDR128BitSubClassMask[] = {
239 0x00800000,
240};
241
242static const uint16_t SuperRegIdxSeqs[] = {
243 /* 0 */ 3, 5, 0,
244 /* 3 */ 2, 6, 0,
245 /* 6 */ 4, 7, 0,
246 /* 9 */ 2, 4, 6, 7, 0,
247 /* 14 */ 1, 8, 0,
248};
249
250static unsigned const FP16BitSuperclasses[] = {
251 SystemZ::VR16BitRegClassID,
252};
253
254static unsigned const FP32BitSuperclasses[] = {
255 SystemZ::VR32BitRegClassID,
256};
257
258static unsigned const GR32BitSuperclasses[] = {
259 SystemZ::GRX32BitRegClassID,
260};
261
262static unsigned const GRH32BitSuperclasses[] = {
263 SystemZ::GRX32BitRegClassID,
264};
265
266static unsigned const ADDR32BitSuperclasses[] = {
267 SystemZ::GRX32BitRegClassID,
268 SystemZ::GR32BitRegClassID,
269};
270
271static unsigned const AnyRegBit_with_subreg_h16Superclasses[] = {
272 SystemZ::AnyRegBitRegClassID,
273};
274
275static unsigned const AnyRegBit_with_subreg_h64Superclasses[] = {
276 SystemZ::AnyRegBitRegClassID,
277 SystemZ::AnyRegBit_with_subreg_h16RegClassID,
278};
279
280static unsigned const FP64BitSuperclasses[] = {
281 SystemZ::AnyRegBitRegClassID,
282 SystemZ::AnyRegBit_with_subreg_h16RegClassID,
283 SystemZ::VR64BitRegClassID,
284};
285
286static unsigned const GR64BitSuperclasses[] = {
287 SystemZ::AnyRegBitRegClassID,
288};
289
290static unsigned const ADDR64BitSuperclasses[] = {
291 SystemZ::AnyRegBitRegClassID,
292 SystemZ::GR64BitRegClassID,
293};
294
295static unsigned const VF128BitSuperclasses[] = {
296 SystemZ::AnyRegBitRegClassID,
297 SystemZ::AnyRegBit_with_subreg_h16RegClassID,
298 SystemZ::AnyRegBit_with_subreg_h64RegClassID,
299 SystemZ::VR128BitRegClassID,
300};
301
302static unsigned const ADDR128BitSuperclasses[] = {
303 SystemZ::GR128BitRegClassID,
304};
305
306
307static inline unsigned VR16BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
308 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
309 return S.isTargetXPLINK64();
310 }
311
312static ArrayRef<MCPhysReg> VR16BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
313 static const MCPhysReg AltOrder1[] = { SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F16H, SystemZ::F17H, SystemZ::F18H, SystemZ::F19H, SystemZ::F20H, SystemZ::F21H, SystemZ::F22H, SystemZ::F23H, SystemZ::F24H, SystemZ::F25H, SystemZ::F26H, SystemZ::F27H, SystemZ::F28H, SystemZ::F29H, SystemZ::F30H, SystemZ::F31H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H };
314 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR16BitRegClassID];
315 const ArrayRef<MCPhysReg> Order[] = {
316 ArrayRef(MCR.begin(), MCR.getNumRegs()),
317 ArrayRef(AltOrder1)
318 };
319 const unsigned Select = VR16BitAltOrderSelect(MF, Rev);
320 assert(Select < 2);
321 return Order[Select];
322}
323
324static inline unsigned FP16BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
325 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
326 return S.isTargetXPLINK64();
327 }
328
329static ArrayRef<MCPhysReg> FP16BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
330 static const MCPhysReg AltOrder1[] = { SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H };
331 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP16BitRegClassID];
332 const ArrayRef<MCPhysReg> Order[] = {
333 ArrayRef(MCR.begin(), MCR.getNumRegs()),
334 ArrayRef(AltOrder1)
335 };
336 const unsigned Select = FP16BitAltOrderSelect(MF, Rev);
337 assert(Select < 2);
338 return Order[Select];
339}
340
341static inline unsigned GRX32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
342 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
343 return S.isTargetXPLINK64();
344 }
345
346static ArrayRef<MCPhysReg> GRX32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
347 static const MCPhysReg AltOrder1[] = { SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4L, SystemZ::R4H, SystemZ::R5L, SystemZ::R5H, SystemZ::R6L, SystemZ::R6H, SystemZ::R7L, SystemZ::R7H, SystemZ::R8L, SystemZ::R8H, SystemZ::R9L, SystemZ::R9H, SystemZ::R10L, SystemZ::R10H, SystemZ::R11L, SystemZ::R11H, SystemZ::R12L, SystemZ::R12H, SystemZ::R13L, SystemZ::R13H, SystemZ::R14L, SystemZ::R14H, SystemZ::R15L, SystemZ::R15H };
348 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GRX32BitRegClassID];
349 const ArrayRef<MCPhysReg> Order[] = {
350 ArrayRef(MCR.begin(), MCR.getNumRegs()),
351 ArrayRef(AltOrder1)
352 };
353 const unsigned Select = GRX32BitAltOrderSelect(MF, Rev);
354 assert(Select < 2);
355 return Order[Select];
356}
357
358static inline unsigned VR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
359 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
360 return S.isTargetXPLINK64();
361 }
362
363static ArrayRef<MCPhysReg> VR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
364 static const MCPhysReg AltOrder1[] = { SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
365 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR32BitRegClassID];
366 const ArrayRef<MCPhysReg> Order[] = {
367 ArrayRef(MCR.begin(), MCR.getNumRegs()),
368 ArrayRef(AltOrder1)
369 };
370 const unsigned Select = VR32BitAltOrderSelect(MF, Rev);
371 assert(Select < 2);
372 return Order[Select];
373}
374
375static inline unsigned AR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
376 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
377 return S.isTargetXPLINK64();
378 }
379
380static ArrayRef<MCPhysReg> AR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
381 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AR32BitRegClassID];
382 const ArrayRef<MCPhysReg> Order[] = {
383 ArrayRef(MCR.begin(), MCR.getNumRegs())
384 };
385 const unsigned Select = AR32BitAltOrderSelect(MF, Rev);
386 assert(Select < 1);
387 return Order[Select];
388}
389
390static inline unsigned FP32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
391 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
392 return S.isTargetXPLINK64();
393 }
394
395static ArrayRef<MCPhysReg> FP32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
396 static const MCPhysReg AltOrder1[] = { SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
397 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP32BitRegClassID];
398 const ArrayRef<MCPhysReg> Order[] = {
399 ArrayRef(MCR.begin(), MCR.getNumRegs()),
400 ArrayRef(AltOrder1)
401 };
402 const unsigned Select = FP32BitAltOrderSelect(MF, Rev);
403 assert(Select < 2);
404 return Order[Select];
405}
406
407static inline unsigned GR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
408 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
409 return S.isTargetXPLINK64();
410 }
411
412static ArrayRef<MCPhysReg> GR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
413 static const MCPhysReg AltOrder1[] = { SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L };
414 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR32BitRegClassID];
415 const ArrayRef<MCPhysReg> Order[] = {
416 ArrayRef(MCR.begin(), MCR.getNumRegs()),
417 ArrayRef(AltOrder1)
418 };
419 const unsigned Select = GR32BitAltOrderSelect(MF, Rev);
420 assert(Select < 2);
421 return Order[Select];
422}
423
424static inline unsigned GRH32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
425 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
426 return S.isTargetXPLINK64();
427 }
428
429static ArrayRef<MCPhysReg> GRH32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
430 static const MCPhysReg AltOrder1[] = { SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H, SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H, SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H };
431 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GRH32BitRegClassID];
432 const ArrayRef<MCPhysReg> Order[] = {
433 ArrayRef(MCR.begin(), MCR.getNumRegs()),
434 ArrayRef(AltOrder1)
435 };
436 const unsigned Select = GRH32BitAltOrderSelect(MF, Rev);
437 assert(Select < 2);
438 return Order[Select];
439}
440
441static inline unsigned ADDR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
442 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
443 return S.isTargetXPLINK64();
444 }
445
446static ArrayRef<MCPhysReg> ADDR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
447 static const MCPhysReg AltOrder1[] = { SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L };
448 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR32BitRegClassID];
449 const ArrayRef<MCPhysReg> Order[] = {
450 ArrayRef(MCR.begin(), MCR.getNumRegs()),
451 ArrayRef(AltOrder1)
452 };
453 const unsigned Select = ADDR32BitAltOrderSelect(MF, Rev);
454 assert(Select < 2);
455 return Order[Select];
456}
457
458static inline unsigned AnyRegBitAltOrderSelect(const MachineFunction &MF, bool Rev) {
459 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
460 return S.isTargetXPLINK64();
461 }
462
463static ArrayRef<MCPhysReg> AnyRegBitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
464 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBitRegClassID];
465 const ArrayRef<MCPhysReg> Order[] = {
466 ArrayRef(MCR.begin(), MCR.getNumRegs())
467 };
468 const unsigned Select = AnyRegBitAltOrderSelect(MF, Rev);
469 assert(Select < 1);
470 return Order[Select];
471}
472
473static inline unsigned AnyRegBit_with_subreg_h16AltOrderSelect(const MachineFunction &MF, bool Rev) {
474 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
475 return S.isTargetXPLINK64();
476 }
477
478static ArrayRef<MCPhysReg> AnyRegBit_with_subreg_h16GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
479 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBit_with_subreg_h16RegClassID];
480 const ArrayRef<MCPhysReg> Order[] = {
481 ArrayRef(MCR.begin(), MCR.getNumRegs())
482 };
483 const unsigned Select = AnyRegBit_with_subreg_h16AltOrderSelect(MF, Rev);
484 assert(Select < 1);
485 return Order[Select];
486}
487
488static inline unsigned VR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
489 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
490 return S.isTargetXPLINK64();
491 }
492
493static ArrayRef<MCPhysReg> VR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
494 static const MCPhysReg AltOrder1[] = { SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D };
495 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR64BitRegClassID];
496 const ArrayRef<MCPhysReg> Order[] = {
497 ArrayRef(MCR.begin(), MCR.getNumRegs()),
498 ArrayRef(AltOrder1)
499 };
500 const unsigned Select = VR64BitAltOrderSelect(MF, Rev);
501 assert(Select < 2);
502 return Order[Select];
503}
504
505static inline unsigned AnyRegBit_with_subreg_h64AltOrderSelect(const MachineFunction &MF, bool Rev) {
506 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
507 return S.isTargetXPLINK64();
508 }
509
510static ArrayRef<MCPhysReg> AnyRegBit_with_subreg_h64GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
511 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBit_with_subreg_h64RegClassID];
512 const ArrayRef<MCPhysReg> Order[] = {
513 ArrayRef(MCR.begin(), MCR.getNumRegs())
514 };
515 const unsigned Select = AnyRegBit_with_subreg_h64AltOrderSelect(MF, Rev);
516 assert(Select < 1);
517 return Order[Select];
518}
519
520static inline unsigned CR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
521 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
522 return S.isTargetXPLINK64();
523 }
524
525static ArrayRef<MCPhysReg> CR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
526 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::CR64BitRegClassID];
527 const ArrayRef<MCPhysReg> Order[] = {
528 ArrayRef(MCR.begin(), MCR.getNumRegs())
529 };
530 const unsigned Select = CR64BitAltOrderSelect(MF, Rev);
531 assert(Select < 1);
532 return Order[Select];
533}
534
535static inline unsigned FP64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
536 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
537 return S.isTargetXPLINK64();
538 }
539
540static ArrayRef<MCPhysReg> FP64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
541 static const MCPhysReg AltOrder1[] = { SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D };
542 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP64BitRegClassID];
543 const ArrayRef<MCPhysReg> Order[] = {
544 ArrayRef(MCR.begin(), MCR.getNumRegs()),
545 ArrayRef(AltOrder1)
546 };
547 const unsigned Select = FP64BitAltOrderSelect(MF, Rev);
548 assert(Select < 2);
549 return Order[Select];
550}
551
552static inline unsigned GR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
553 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
554 return S.isTargetXPLINK64();
555 }
556
557static ArrayRef<MCPhysReg> GR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
558 static const MCPhysReg AltOrder1[] = { SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D };
559 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR64BitRegClassID];
560 const ArrayRef<MCPhysReg> Order[] = {
561 ArrayRef(MCR.begin(), MCR.getNumRegs()),
562 ArrayRef(AltOrder1)
563 };
564 const unsigned Select = GR64BitAltOrderSelect(MF, Rev);
565 assert(Select < 2);
566 return Order[Select];
567}
568
569static inline unsigned ADDR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
570 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
571 return S.isTargetXPLINK64();
572 }
573
574static ArrayRef<MCPhysReg> ADDR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
575 static const MCPhysReg AltOrder1[] = { SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D };
576 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR64BitRegClassID];
577 const ArrayRef<MCPhysReg> Order[] = {
578 ArrayRef(MCR.begin(), MCR.getNumRegs()),
579 ArrayRef(AltOrder1)
580 };
581 const unsigned Select = ADDR64BitAltOrderSelect(MF, Rev);
582 assert(Select < 2);
583 return Order[Select];
584}
585
586static inline unsigned VR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
587 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
588 return S.isTargetXPLINK64();
589 }
590
591static ArrayRef<MCPhysReg> VR128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
592 static const MCPhysReg AltOrder1[] = { SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15 };
593 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR128BitRegClassID];
594 const ArrayRef<MCPhysReg> Order[] = {
595 ArrayRef(MCR.begin(), MCR.getNumRegs()),
596 ArrayRef(AltOrder1)
597 };
598 const unsigned Select = VR128BitAltOrderSelect(MF, Rev);
599 assert(Select < 2);
600 return Order[Select];
601}
602
603static inline unsigned VF128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
604 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
605 return S.isTargetXPLINK64();
606 }
607
608static ArrayRef<MCPhysReg> VF128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
609 static const MCPhysReg AltOrder1[] = { SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15 };
610 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VF128BitRegClassID];
611 const ArrayRef<MCPhysReg> Order[] = {
612 ArrayRef(MCR.begin(), MCR.getNumRegs()),
613 ArrayRef(AltOrder1)
614 };
615 const unsigned Select = VF128BitAltOrderSelect(MF, Rev);
616 assert(Select < 2);
617 return Order[Select];
618}
619
620static inline unsigned FP128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
621 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
622 return S.isTargetXPLINK64();
623 }
624
625static ArrayRef<MCPhysReg> FP128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
626 static const MCPhysReg AltOrder1[] = { SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q };
627 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP128BitRegClassID];
628 const ArrayRef<MCPhysReg> Order[] = {
629 ArrayRef(MCR.begin(), MCR.getNumRegs()),
630 ArrayRef(AltOrder1)
631 };
632 const unsigned Select = FP128BitAltOrderSelect(MF, Rev);
633 assert(Select < 2);
634 return Order[Select];
635}
636
637static inline unsigned GR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
638 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
639 return S.isTargetXPLINK64();
640 }
641
642static ArrayRef<MCPhysReg> GR128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
643 static const MCPhysReg AltOrder1[] = { SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R6Q, SystemZ::R8Q, SystemZ::R10Q, SystemZ::R12Q, SystemZ::R14Q };
644 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR128BitRegClassID];
645 const ArrayRef<MCPhysReg> Order[] = {
646 ArrayRef(MCR.begin(), MCR.getNumRegs()),
647 ArrayRef(AltOrder1)
648 };
649 const unsigned Select = GR128BitAltOrderSelect(MF, Rev);
650 assert(Select < 2);
651 return Order[Select];
652}
653
654static inline unsigned ADDR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
655 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
656 return S.isTargetXPLINK64();
657 }
658
659static ArrayRef<MCPhysReg> ADDR128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
660 static const MCPhysReg AltOrder1[] = { SystemZ::R2Q, SystemZ::R4Q, SystemZ::R6Q, SystemZ::R8Q, SystemZ::R10Q, SystemZ::R12Q, SystemZ::R14Q };
661 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR128BitRegClassID];
662 const ArrayRef<MCPhysReg> Order[] = {
663 ArrayRef(MCR.begin(), MCR.getNumRegs()),
664 ArrayRef(AltOrder1)
665 };
666 const unsigned Select = ADDR128BitAltOrderSelect(MF, Rev);
667 assert(Select < 2);
668 return Order[Select];
669}
670
671namespace SystemZ { // Register class instances
672 extern const TargetRegisterClass VR16BitRegClass = {
673 .MC: &SystemZMCRegisterClasses[VR16BitRegClassID],
674 .SubClassMask: VR16BitSubClassMask,
675 .SuperRegIndices: SuperRegIdxSeqs + 14,
676 .LaneMask: LaneBitmask(0x0000000000000001),
677 .AllocationPriority: 0,
678 .GlobalPriority: false,
679 .TSFlags: 0x00, /* TSFlags */
680 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
681 .CoveredBySubRegs: false, /* CoveredBySubRegs */
682 .SuperClasses: nullptr, .SuperClassesSize: 0,
683 .OrderFunc: VR16BitGetRawAllocationOrder
684 };
685
686 extern const TargetRegisterClass FP16BitRegClass = {
687 .MC: &SystemZMCRegisterClasses[FP16BitRegClassID],
688 .SubClassMask: FP16BitSubClassMask,
689 .SuperRegIndices: SuperRegIdxSeqs + 14,
690 .LaneMask: LaneBitmask(0x0000000000000001),
691 .AllocationPriority: 0,
692 .GlobalPriority: false,
693 .TSFlags: 0x00, /* TSFlags */
694 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
695 .CoveredBySubRegs: false, /* CoveredBySubRegs */
696 .SuperClasses: FP16BitSuperclasses, .SuperClassesSize: 1,
697 .OrderFunc: FP16BitGetRawAllocationOrder
698 };
699
700 extern const TargetRegisterClass GRX32BitRegClass = {
701 .MC: &SystemZMCRegisterClasses[GRX32BitRegClassID],
702 .SubClassMask: GRX32BitSubClassMask,
703 .SuperRegIndices: SuperRegIdxSeqs + 9,
704 .LaneMask: LaneBitmask(0x0000000000000001),
705 .AllocationPriority: 0,
706 .GlobalPriority: false,
707 .TSFlags: 0x00, /* TSFlags */
708 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
709 .CoveredBySubRegs: false, /* CoveredBySubRegs */
710 .SuperClasses: nullptr, .SuperClassesSize: 0,
711 .OrderFunc: GRX32BitGetRawAllocationOrder
712 };
713
714 extern const TargetRegisterClass VR32BitRegClass = {
715 .MC: &SystemZMCRegisterClasses[VR32BitRegClassID],
716 .SubClassMask: VR32BitSubClassMask,
717 .SuperRegIndices: SuperRegIdxSeqs + 3,
718 .LaneMask: LaneBitmask(0x0000000000000001),
719 .AllocationPriority: 0,
720 .GlobalPriority: false,
721 .TSFlags: 0x00, /* TSFlags */
722 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
723 .CoveredBySubRegs: false, /* CoveredBySubRegs */
724 .SuperClasses: nullptr, .SuperClassesSize: 0,
725 .OrderFunc: VR32BitGetRawAllocationOrder
726 };
727
728 extern const TargetRegisterClass AR32BitRegClass = {
729 .MC: &SystemZMCRegisterClasses[AR32BitRegClassID],
730 .SubClassMask: AR32BitSubClassMask,
731 .SuperRegIndices: SuperRegIdxSeqs + 2,
732 .LaneMask: LaneBitmask(0x0000000000000001),
733 .AllocationPriority: 0,
734 .GlobalPriority: false,
735 .TSFlags: 0x00, /* TSFlags */
736 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
737 .CoveredBySubRegs: false, /* CoveredBySubRegs */
738 .SuperClasses: nullptr, .SuperClassesSize: 0,
739 .OrderFunc: AR32BitGetRawAllocationOrder
740 };
741
742 extern const TargetRegisterClass FP32BitRegClass = {
743 .MC: &SystemZMCRegisterClasses[FP32BitRegClassID],
744 .SubClassMask: FP32BitSubClassMask,
745 .SuperRegIndices: SuperRegIdxSeqs + 3,
746 .LaneMask: LaneBitmask(0x0000000000000001),
747 .AllocationPriority: 0,
748 .GlobalPriority: false,
749 .TSFlags: 0x00, /* TSFlags */
750 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
751 .CoveredBySubRegs: false, /* CoveredBySubRegs */
752 .SuperClasses: FP32BitSuperclasses, .SuperClassesSize: 1,
753 .OrderFunc: FP32BitGetRawAllocationOrder
754 };
755
756 extern const TargetRegisterClass GR32BitRegClass = {
757 .MC: &SystemZMCRegisterClasses[GR32BitRegClassID],
758 .SubClassMask: GR32BitSubClassMask,
759 .SuperRegIndices: SuperRegIdxSeqs + 6,
760 .LaneMask: LaneBitmask(0x0000000000000001),
761 .AllocationPriority: 0,
762 .GlobalPriority: false,
763 .TSFlags: 0x00, /* TSFlags */
764 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
765 .CoveredBySubRegs: false, /* CoveredBySubRegs */
766 .SuperClasses: GR32BitSuperclasses, .SuperClassesSize: 1,
767 .OrderFunc: GR32BitGetRawAllocationOrder
768 };
769
770 extern const TargetRegisterClass GRH32BitRegClass = {
771 .MC: &SystemZMCRegisterClasses[GRH32BitRegClassID],
772 .SubClassMask: GRH32BitSubClassMask,
773 .SuperRegIndices: SuperRegIdxSeqs + 3,
774 .LaneMask: LaneBitmask(0x0000000000000001),
775 .AllocationPriority: 0,
776 .GlobalPriority: false,
777 .TSFlags: 0x00, /* TSFlags */
778 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
779 .CoveredBySubRegs: false, /* CoveredBySubRegs */
780 .SuperClasses: GRH32BitSuperclasses, .SuperClassesSize: 1,
781 .OrderFunc: GRH32BitGetRawAllocationOrder
782 };
783
784 extern const TargetRegisterClass ADDR32BitRegClass = {
785 .MC: &SystemZMCRegisterClasses[ADDR32BitRegClassID],
786 .SubClassMask: ADDR32BitSubClassMask,
787 .SuperRegIndices: SuperRegIdxSeqs + 6,
788 .LaneMask: LaneBitmask(0x0000000000000001),
789 .AllocationPriority: 0,
790 .GlobalPriority: false,
791 .TSFlags: 0x00, /* TSFlags */
792 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
793 .CoveredBySubRegs: false, /* CoveredBySubRegs */
794 .SuperClasses: ADDR32BitSuperclasses, .SuperClassesSize: 2,
795 .OrderFunc: ADDR32BitGetRawAllocationOrder
796 };
797
798 extern const TargetRegisterClass CCRRegClass = {
799 .MC: &SystemZMCRegisterClasses[CCRRegClassID],
800 .SubClassMask: CCRSubClassMask,
801 .SuperRegIndices: SuperRegIdxSeqs + 2,
802 .LaneMask: LaneBitmask(0x0000000000000001),
803 .AllocationPriority: 0,
804 .GlobalPriority: false,
805 .TSFlags: 0x00, /* TSFlags */
806 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
807 .CoveredBySubRegs: false, /* CoveredBySubRegs */
808 .SuperClasses: nullptr, .SuperClassesSize: 0,
809 .OrderFunc: nullptr
810 };
811
812 extern const TargetRegisterClass FPCRegsRegClass = {
813 .MC: &SystemZMCRegisterClasses[FPCRegsRegClassID],
814 .SubClassMask: FPCRegsSubClassMask,
815 .SuperRegIndices: SuperRegIdxSeqs + 2,
816 .LaneMask: LaneBitmask(0x0000000000000001),
817 .AllocationPriority: 0,
818 .GlobalPriority: false,
819 .TSFlags: 0x00, /* TSFlags */
820 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
821 .CoveredBySubRegs: false, /* CoveredBySubRegs */
822 .SuperClasses: nullptr, .SuperClassesSize: 0,
823 .OrderFunc: nullptr
824 };
825
826 extern const TargetRegisterClass AnyRegBitRegClass = {
827 .MC: &SystemZMCRegisterClasses[AnyRegBitRegClassID],
828 .SubClassMask: AnyRegBitSubClassMask,
829 .SuperRegIndices: SuperRegIdxSeqs + 0,
830 .LaneMask: LaneBitmask(0x0000000000000003),
831 .AllocationPriority: 0,
832 .GlobalPriority: false,
833 .TSFlags: 0x00, /* TSFlags */
834 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
835 .CoveredBySubRegs: false, /* CoveredBySubRegs */
836 .SuperClasses: nullptr, .SuperClassesSize: 0,
837 .OrderFunc: AnyRegBitGetRawAllocationOrder
838 };
839
840 extern const TargetRegisterClass AnyRegBit_with_subreg_h16RegClass = {
841 .MC: &SystemZMCRegisterClasses[AnyRegBit_with_subreg_h16RegClassID],
842 .SubClassMask: AnyRegBit_with_subreg_h16SubClassMask,
843 .SuperRegIndices: SuperRegIdxSeqs + 0,
844 .LaneMask: LaneBitmask(0x0000000000000003),
845 .AllocationPriority: 0,
846 .GlobalPriority: false,
847 .TSFlags: 0x00, /* TSFlags */
848 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
849 .CoveredBySubRegs: false, /* CoveredBySubRegs */
850 .SuperClasses: AnyRegBit_with_subreg_h16Superclasses, .SuperClassesSize: 1,
851 .OrderFunc: AnyRegBit_with_subreg_h16GetRawAllocationOrder
852 };
853
854 extern const TargetRegisterClass VR64BitRegClass = {
855 .MC: &SystemZMCRegisterClasses[VR64BitRegClassID],
856 .SubClassMask: VR64BitSubClassMask,
857 .SuperRegIndices: SuperRegIdxSeqs + 0,
858 .LaneMask: LaneBitmask(0x0000000000000001),
859 .AllocationPriority: 0,
860 .GlobalPriority: false,
861 .TSFlags: 0x00, /* TSFlags */
862 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
863 .CoveredBySubRegs: false, /* CoveredBySubRegs */
864 .SuperClasses: nullptr, .SuperClassesSize: 0,
865 .OrderFunc: VR64BitGetRawAllocationOrder
866 };
867
868 extern const TargetRegisterClass AnyRegBit_with_subreg_h64RegClass = {
869 .MC: &SystemZMCRegisterClasses[AnyRegBit_with_subreg_h64RegClassID],
870 .SubClassMask: AnyRegBit_with_subreg_h64SubClassMask,
871 .SuperRegIndices: SuperRegIdxSeqs + 2,
872 .LaneMask: LaneBitmask(0x0000000000000003),
873 .AllocationPriority: 0,
874 .GlobalPriority: false,
875 .TSFlags: 0x00, /* TSFlags */
876 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
877 .CoveredBySubRegs: false, /* CoveredBySubRegs */
878 .SuperClasses: AnyRegBit_with_subreg_h64Superclasses, .SuperClassesSize: 2,
879 .OrderFunc: AnyRegBit_with_subreg_h64GetRawAllocationOrder
880 };
881
882 extern const TargetRegisterClass CR64BitRegClass = {
883 .MC: &SystemZMCRegisterClasses[CR64BitRegClassID],
884 .SubClassMask: CR64BitSubClassMask,
885 .SuperRegIndices: SuperRegIdxSeqs + 2,
886 .LaneMask: LaneBitmask(0x0000000000000001),
887 .AllocationPriority: 0,
888 .GlobalPriority: false,
889 .TSFlags: 0x00, /* TSFlags */
890 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
891 .CoveredBySubRegs: false, /* CoveredBySubRegs */
892 .SuperClasses: nullptr, .SuperClassesSize: 0,
893 .OrderFunc: CR64BitGetRawAllocationOrder
894 };
895
896 extern const TargetRegisterClass FP64BitRegClass = {
897 .MC: &SystemZMCRegisterClasses[FP64BitRegClassID],
898 .SubClassMask: FP64BitSubClassMask,
899 .SuperRegIndices: SuperRegIdxSeqs + 0,
900 .LaneMask: LaneBitmask(0x0000000000000001),
901 .AllocationPriority: 0,
902 .GlobalPriority: false,
903 .TSFlags: 0x00, /* TSFlags */
904 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
905 .CoveredBySubRegs: false, /* CoveredBySubRegs */
906 .SuperClasses: FP64BitSuperclasses, .SuperClassesSize: 3,
907 .OrderFunc: FP64BitGetRawAllocationOrder
908 };
909
910 extern const TargetRegisterClass GR64BitRegClass = {
911 .MC: &SystemZMCRegisterClasses[GR64BitRegClassID],
912 .SubClassMask: GR64BitSubClassMask,
913 .SuperRegIndices: SuperRegIdxSeqs + 0,
914 .LaneMask: LaneBitmask(0x0000000000000003),
915 .AllocationPriority: 0,
916 .GlobalPriority: false,
917 .TSFlags: 0x00, /* TSFlags */
918 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
919 .CoveredBySubRegs: true, /* CoveredBySubRegs */
920 .SuperClasses: GR64BitSuperclasses, .SuperClassesSize: 1,
921 .OrderFunc: GR64BitGetRawAllocationOrder
922 };
923
924 extern const TargetRegisterClass ADDR64BitRegClass = {
925 .MC: &SystemZMCRegisterClasses[ADDR64BitRegClassID],
926 .SubClassMask: ADDR64BitSubClassMask,
927 .SuperRegIndices: SuperRegIdxSeqs + 0,
928 .LaneMask: LaneBitmask(0x0000000000000003),
929 .AllocationPriority: 0,
930 .GlobalPriority: false,
931 .TSFlags: 0x00, /* TSFlags */
932 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
933 .CoveredBySubRegs: true, /* CoveredBySubRegs */
934 .SuperClasses: ADDR64BitSuperclasses, .SuperClassesSize: 2,
935 .OrderFunc: ADDR64BitGetRawAllocationOrder
936 };
937
938 extern const TargetRegisterClass VR128BitRegClass = {
939 .MC: &SystemZMCRegisterClasses[VR128BitRegClassID],
940 .SubClassMask: VR128BitSubClassMask,
941 .SuperRegIndices: SuperRegIdxSeqs + 2,
942 .LaneMask: LaneBitmask(0x0000000000000003),
943 .AllocationPriority: 0,
944 .GlobalPriority: false,
945 .TSFlags: 0x00, /* TSFlags */
946 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
947 .CoveredBySubRegs: false, /* CoveredBySubRegs */
948 .SuperClasses: nullptr, .SuperClassesSize: 0,
949 .OrderFunc: VR128BitGetRawAllocationOrder
950 };
951
952 extern const TargetRegisterClass VF128BitRegClass = {
953 .MC: &SystemZMCRegisterClasses[VF128BitRegClassID],
954 .SubClassMask: VF128BitSubClassMask,
955 .SuperRegIndices: SuperRegIdxSeqs + 2,
956 .LaneMask: LaneBitmask(0x0000000000000003),
957 .AllocationPriority: 0,
958 .GlobalPriority: false,
959 .TSFlags: 0x00, /* TSFlags */
960 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
961 .CoveredBySubRegs: false, /* CoveredBySubRegs */
962 .SuperClasses: VF128BitSuperclasses, .SuperClassesSize: 4,
963 .OrderFunc: VF128BitGetRawAllocationOrder
964 };
965
966 extern const TargetRegisterClass FP128BitRegClass = {
967 .MC: &SystemZMCRegisterClasses[FP128BitRegClassID],
968 .SubClassMask: FP128BitSubClassMask,
969 .SuperRegIndices: SuperRegIdxSeqs + 2,
970 .LaneMask: LaneBitmask(0x000000000000000F),
971 .AllocationPriority: 0,
972 .GlobalPriority: false,
973 .TSFlags: 0x00, /* TSFlags */
974 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
975 .CoveredBySubRegs: true, /* CoveredBySubRegs */
976 .SuperClasses: nullptr, .SuperClassesSize: 0,
977 .OrderFunc: FP128BitGetRawAllocationOrder
978 };
979
980 extern const TargetRegisterClass GR128BitRegClass = {
981 .MC: &SystemZMCRegisterClasses[GR128BitRegClassID],
982 .SubClassMask: GR128BitSubClassMask,
983 .SuperRegIndices: SuperRegIdxSeqs + 2,
984 .LaneMask: LaneBitmask(0x000000000000000F),
985 .AllocationPriority: 0,
986 .GlobalPriority: false,
987 .TSFlags: 0x00, /* TSFlags */
988 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
989 .CoveredBySubRegs: true, /* CoveredBySubRegs */
990 .SuperClasses: nullptr, .SuperClassesSize: 0,
991 .OrderFunc: GR128BitGetRawAllocationOrder
992 };
993
994 extern const TargetRegisterClass ADDR128BitRegClass = {
995 .MC: &SystemZMCRegisterClasses[ADDR128BitRegClassID],
996 .SubClassMask: ADDR128BitSubClassMask,
997 .SuperRegIndices: SuperRegIdxSeqs + 2,
998 .LaneMask: LaneBitmask(0x000000000000000F),
999 .AllocationPriority: 0,
1000 .GlobalPriority: false,
1001 .TSFlags: 0x00, /* TSFlags */
1002 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1003 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1004 .SuperClasses: ADDR128BitSuperclasses, .SuperClassesSize: 1,
1005 .OrderFunc: ADDR128BitGetRawAllocationOrder
1006 };
1007
1008} // end namespace SystemZ
1009
1010namespace {
1011 const TargetRegisterClass *const RegisterClasses[] = {
1012 &SystemZ::VR16BitRegClass,
1013 &SystemZ::FP16BitRegClass,
1014 &SystemZ::GRX32BitRegClass,
1015 &SystemZ::VR32BitRegClass,
1016 &SystemZ::AR32BitRegClass,
1017 &SystemZ::FP32BitRegClass,
1018 &SystemZ::GR32BitRegClass,
1019 &SystemZ::GRH32BitRegClass,
1020 &SystemZ::ADDR32BitRegClass,
1021 &SystemZ::CCRRegClass,
1022 &SystemZ::FPCRegsRegClass,
1023 &SystemZ::AnyRegBitRegClass,
1024 &SystemZ::AnyRegBit_with_subreg_h16RegClass,
1025 &SystemZ::VR64BitRegClass,
1026 &SystemZ::AnyRegBit_with_subreg_h64RegClass,
1027 &SystemZ::CR64BitRegClass,
1028 &SystemZ::FP64BitRegClass,
1029 &SystemZ::GR64BitRegClass,
1030 &SystemZ::ADDR64BitRegClass,
1031 &SystemZ::VR128BitRegClass,
1032 &SystemZ::VF128BitRegClass,
1033 &SystemZ::FP128BitRegClass,
1034 &SystemZ::GR128BitRegClass,
1035 &SystemZ::ADDR128BitRegClass,
1036 };
1037} // end anonymous namespace
1038
1039static const uint8_t CostPerUseTable[] = {
10400, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1041
1042
1043static const bool InAllocatableClassTable[] = {
1044false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
1045
1046
1047static const TargetRegisterInfoDesc SystemZRegInfoDesc = { // Extra Descriptors
1048.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
1049
1050unsigned SystemZGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1051 static const uint8_t RowMap[8] = {
1052 0, 0, 0, 0, 1, 1, 0, 0,
1053 };
1054 static const uint8_t Rows[2][8] = {
1055 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1056 { SystemZ::subreg_lh32_then_subreg_h16, SystemZ::subreg_lh32, 0, SystemZ::subreg_ll32, 0, 0, 0, 0, },
1057 };
1058
1059 --IdxA; assert(IdxA < 8); (void) IdxA;
1060 --IdxB; assert(IdxB < 8);
1061 return Rows[RowMap[IdxA]][IdxB];
1062}
1063
1064unsigned SystemZGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1065 static const uint8_t Table[8][8] = {
1066 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1067 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1068 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1069 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1070 { 0, 0, 0, 0, 0, SystemZ::subreg_h32, SystemZ::subreg_l32, SystemZ::subreg_h16, },
1071 { 0, 0, 0, 0, 0, SystemZ::subreg_h32, SystemZ::subreg_l32, SystemZ::subreg_h16, },
1072 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1073 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1074 };
1075
1076 --IdxA; assert(IdxA < 8);
1077 --IdxB; assert(IdxB < 8);
1078 return Table[IdxA][IdxB];
1079 }
1080
1081 struct MaskRolOp {
1082 LaneBitmask Mask;
1083 uint8_t RotateLeft;
1084 };
1085 static const MaskRolOp LaneMaskComposeSequences[] = {
1086 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
1087 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
1088 { .Mask: LaneBitmask(0x0000000000000001), .RotateLeft: 3 }, { .Mask: LaneBitmask(0x0000000000000002), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
1089 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 7
1090 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 9
1091 };
1092 static const uint8_t CompositeSequences[] = {
1093 0, // to subreg_h16
1094 0, // to subreg_h32
1095 0, // to subreg_h64
1096 2, // to subreg_l32
1097 4, // to subreg_l64
1098 7, // to subreg_lh32
1099 9, // to subreg_ll32
1100 7 // to subreg_lh32_then_subreg_h16
1101 };
1102
1103LaneBitmask SystemZGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1104 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
1105 LaneBitmask Result;
1106 for (const MaskRolOp *Ops =
1107 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1108 Ops->Mask.any(); ++Ops) {
1109 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
1110 if (unsigned S = Ops->RotateLeft)
1111 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
1112 else
1113 Result |= LaneBitmask(M);
1114 }
1115 return Result;
1116}
1117
1118LaneBitmask SystemZGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1119 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
1120 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
1121 LaneBitmask Result;
1122 for (const MaskRolOp *Ops =
1123 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1124 Ops->Mask.any(); ++Ops) {
1125 LaneBitmask::Type M = LaneMask.getAsInteger();
1126 if (unsigned S = Ops->RotateLeft)
1127 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
1128 else
1129 Result |= LaneBitmask(M);
1130 }
1131 return Result;
1132}
1133
1134const TargetRegisterClass *SystemZGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1135 static const uint8_t Table[24][8] = {
1136 { // VR16Bit
1137 0, // subreg_h16
1138 0, // subreg_h32
1139 0, // subreg_h64
1140 0, // subreg_l32
1141 0, // subreg_l64
1142 0, // subreg_lh32
1143 0, // subreg_ll32
1144 0, // subreg_lh32_then_subreg_h16
1145 },
1146 { // FP16Bit
1147 0, // subreg_h16
1148 0, // subreg_h32
1149 0, // subreg_h64
1150 0, // subreg_l32
1151 0, // subreg_l64
1152 0, // subreg_lh32
1153 0, // subreg_ll32
1154 0, // subreg_lh32_then_subreg_h16
1155 },
1156 { // GRX32Bit
1157 0, // subreg_h16
1158 0, // subreg_h32
1159 0, // subreg_h64
1160 0, // subreg_l32
1161 0, // subreg_l64
1162 0, // subreg_lh32
1163 0, // subreg_ll32
1164 0, // subreg_lh32_then_subreg_h16
1165 },
1166 { // VR32Bit
1167 4, // subreg_h16 -> VR32Bit
1168 0, // subreg_h32
1169 0, // subreg_h64
1170 0, // subreg_l32
1171 0, // subreg_l64
1172 0, // subreg_lh32
1173 0, // subreg_ll32
1174 0, // subreg_lh32_then_subreg_h16
1175 },
1176 { // AR32Bit
1177 0, // subreg_h16
1178 0, // subreg_h32
1179 0, // subreg_h64
1180 0, // subreg_l32
1181 0, // subreg_l64
1182 0, // subreg_lh32
1183 0, // subreg_ll32
1184 0, // subreg_lh32_then_subreg_h16
1185 },
1186 { // FP32Bit
1187 6, // subreg_h16 -> FP32Bit
1188 0, // subreg_h32
1189 0, // subreg_h64
1190 0, // subreg_l32
1191 0, // subreg_l64
1192 0, // subreg_lh32
1193 0, // subreg_ll32
1194 0, // subreg_lh32_then_subreg_h16
1195 },
1196 { // GR32Bit
1197 0, // subreg_h16
1198 0, // subreg_h32
1199 0, // subreg_h64
1200 0, // subreg_l32
1201 0, // subreg_l64
1202 0, // subreg_lh32
1203 0, // subreg_ll32
1204 0, // subreg_lh32_then_subreg_h16
1205 },
1206 { // GRH32Bit
1207 0, // subreg_h16
1208 0, // subreg_h32
1209 0, // subreg_h64
1210 0, // subreg_l32
1211 0, // subreg_l64
1212 0, // subreg_lh32
1213 0, // subreg_ll32
1214 0, // subreg_lh32_then_subreg_h16
1215 },
1216 { // ADDR32Bit
1217 0, // subreg_h16
1218 0, // subreg_h32
1219 0, // subreg_h64
1220 0, // subreg_l32
1221 0, // subreg_l64
1222 0, // subreg_lh32
1223 0, // subreg_ll32
1224 0, // subreg_lh32_then_subreg_h16
1225 },
1226 { // CCR
1227 0, // subreg_h16
1228 0, // subreg_h32
1229 0, // subreg_h64
1230 0, // subreg_l32
1231 0, // subreg_l64
1232 0, // subreg_lh32
1233 0, // subreg_ll32
1234 0, // subreg_lh32_then_subreg_h16
1235 },
1236 { // FPCRegs
1237 0, // subreg_h16
1238 0, // subreg_h32
1239 0, // subreg_h64
1240 0, // subreg_l32
1241 0, // subreg_l64
1242 0, // subreg_lh32
1243 0, // subreg_ll32
1244 0, // subreg_lh32_then_subreg_h16
1245 },
1246 { // AnyRegBit
1247 13, // subreg_h16 -> AnyRegBit_with_subreg_h16
1248 12, // subreg_h32 -> AnyRegBit
1249 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
1250 18, // subreg_l32 -> GR64Bit
1251 0, // subreg_l64
1252 0, // subreg_lh32
1253 0, // subreg_ll32
1254 0, // subreg_lh32_then_subreg_h16
1255 },
1256 { // AnyRegBit_with_subreg_h16
1257 13, // subreg_h16 -> AnyRegBit_with_subreg_h16
1258 13, // subreg_h32 -> AnyRegBit_with_subreg_h16
1259 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
1260 0, // subreg_l32
1261 0, // subreg_l64
1262 0, // subreg_lh32
1263 0, // subreg_ll32
1264 0, // subreg_lh32_then_subreg_h16
1265 },
1266 { // VR64Bit
1267 14, // subreg_h16 -> VR64Bit
1268 14, // subreg_h32 -> VR64Bit
1269 0, // subreg_h64
1270 0, // subreg_l32
1271 0, // subreg_l64
1272 0, // subreg_lh32
1273 0, // subreg_ll32
1274 0, // subreg_lh32_then_subreg_h16
1275 },
1276 { // AnyRegBit_with_subreg_h64
1277 15, // subreg_h16 -> AnyRegBit_with_subreg_h64
1278 15, // subreg_h32 -> AnyRegBit_with_subreg_h64
1279 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
1280 0, // subreg_l32
1281 0, // subreg_l64
1282 0, // subreg_lh32
1283 0, // subreg_ll32
1284 0, // subreg_lh32_then_subreg_h16
1285 },
1286 { // CR64Bit
1287 0, // subreg_h16
1288 0, // subreg_h32
1289 0, // subreg_h64
1290 0, // subreg_l32
1291 0, // subreg_l64
1292 0, // subreg_lh32
1293 0, // subreg_ll32
1294 0, // subreg_lh32_then_subreg_h16
1295 },
1296 { // FP64Bit
1297 17, // subreg_h16 -> FP64Bit
1298 17, // subreg_h32 -> FP64Bit
1299 0, // subreg_h64
1300 0, // subreg_l32
1301 0, // subreg_l64
1302 0, // subreg_lh32
1303 0, // subreg_ll32
1304 0, // subreg_lh32_then_subreg_h16
1305 },
1306 { // GR64Bit
1307 0, // subreg_h16
1308 18, // subreg_h32 -> GR64Bit
1309 0, // subreg_h64
1310 18, // subreg_l32 -> GR64Bit
1311 0, // subreg_l64
1312 0, // subreg_lh32
1313 0, // subreg_ll32
1314 0, // subreg_lh32_then_subreg_h16
1315 },
1316 { // ADDR64Bit
1317 0, // subreg_h16
1318 19, // subreg_h32 -> ADDR64Bit
1319 0, // subreg_h64
1320 19, // subreg_l32 -> ADDR64Bit
1321 0, // subreg_l64
1322 0, // subreg_lh32
1323 0, // subreg_ll32
1324 0, // subreg_lh32_then_subreg_h16
1325 },
1326 { // VR128Bit
1327 20, // subreg_h16 -> VR128Bit
1328 20, // subreg_h32 -> VR128Bit
1329 20, // subreg_h64 -> VR128Bit
1330 0, // subreg_l32
1331 0, // subreg_l64
1332 0, // subreg_lh32
1333 0, // subreg_ll32
1334 0, // subreg_lh32_then_subreg_h16
1335 },
1336 { // VF128Bit
1337 21, // subreg_h16 -> VF128Bit
1338 21, // subreg_h32 -> VF128Bit
1339 21, // subreg_h64 -> VF128Bit
1340 0, // subreg_l32
1341 0, // subreg_l64
1342 0, // subreg_lh32
1343 0, // subreg_ll32
1344 0, // subreg_lh32_then_subreg_h16
1345 },
1346 { // FP128Bit
1347 22, // subreg_h16 -> FP128Bit
1348 22, // subreg_h32 -> FP128Bit
1349 22, // subreg_h64 -> FP128Bit
1350 0, // subreg_l32
1351 22, // subreg_l64 -> FP128Bit
1352 22, // subreg_lh32 -> FP128Bit
1353 0, // subreg_ll32
1354 22, // subreg_lh32_then_subreg_h16 -> FP128Bit
1355 },
1356 { // GR128Bit
1357 0, // subreg_h16
1358 23, // subreg_h32 -> GR128Bit
1359 23, // subreg_h64 -> GR128Bit
1360 23, // subreg_l32 -> GR128Bit
1361 23, // subreg_l64 -> GR128Bit
1362 23, // subreg_lh32 -> GR128Bit
1363 23, // subreg_ll32 -> GR128Bit
1364 0, // subreg_lh32_then_subreg_h16
1365 },
1366 { // ADDR128Bit
1367 0, // subreg_h16
1368 24, // subreg_h32 -> ADDR128Bit
1369 24, // subreg_h64 -> ADDR128Bit
1370 24, // subreg_l32 -> ADDR128Bit
1371 24, // subreg_l64 -> ADDR128Bit
1372 24, // subreg_lh32 -> ADDR128Bit
1373 24, // subreg_ll32 -> ADDR128Bit
1374 0, // subreg_lh32_then_subreg_h16
1375 },
1376 };
1377 assert(RC && "Missing regclass");
1378 if (!Idx) return RC;
1379 --Idx;
1380 assert(Idx < 8 && "Bad subreg");
1381 unsigned TV = Table[RC->getID()][Idx];
1382 return TV ? getRegClass(i: TV - 1) : nullptr;
1383}
1384
1385const TargetRegisterClass *SystemZGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1386 static const uint8_t Table[24][8] = {
1387 { // VR16Bit
1388 0, // VR16Bit:subreg_h16
1389 0, // VR16Bit:subreg_h32
1390 0, // VR16Bit:subreg_h64
1391 0, // VR16Bit:subreg_l32
1392 0, // VR16Bit:subreg_l64
1393 0, // VR16Bit:subreg_lh32
1394 0, // VR16Bit:subreg_ll32
1395 0, // VR16Bit:subreg_lh32_then_subreg_h16
1396 },
1397 { // FP16Bit
1398 0, // FP16Bit:subreg_h16
1399 0, // FP16Bit:subreg_h32
1400 0, // FP16Bit:subreg_h64
1401 0, // FP16Bit:subreg_l32
1402 0, // FP16Bit:subreg_l64
1403 0, // FP16Bit:subreg_lh32
1404 0, // FP16Bit:subreg_ll32
1405 0, // FP16Bit:subreg_lh32_then_subreg_h16
1406 },
1407 { // GRX32Bit
1408 0, // GRX32Bit:subreg_h16
1409 0, // GRX32Bit:subreg_h32
1410 0, // GRX32Bit:subreg_h64
1411 0, // GRX32Bit:subreg_l32
1412 0, // GRX32Bit:subreg_l64
1413 0, // GRX32Bit:subreg_lh32
1414 0, // GRX32Bit:subreg_ll32
1415 0, // GRX32Bit:subreg_lh32_then_subreg_h16
1416 },
1417 { // VR32Bit
1418 1, // VR32Bit:subreg_h16 -> VR16Bit
1419 0, // VR32Bit:subreg_h32
1420 0, // VR32Bit:subreg_h64
1421 0, // VR32Bit:subreg_l32
1422 0, // VR32Bit:subreg_l64
1423 0, // VR32Bit:subreg_lh32
1424 0, // VR32Bit:subreg_ll32
1425 0, // VR32Bit:subreg_lh32_then_subreg_h16
1426 },
1427 { // AR32Bit
1428 0, // AR32Bit:subreg_h16
1429 0, // AR32Bit:subreg_h32
1430 0, // AR32Bit:subreg_h64
1431 0, // AR32Bit:subreg_l32
1432 0, // AR32Bit:subreg_l64
1433 0, // AR32Bit:subreg_lh32
1434 0, // AR32Bit:subreg_ll32
1435 0, // AR32Bit:subreg_lh32_then_subreg_h16
1436 },
1437 { // FP32Bit
1438 2, // FP32Bit:subreg_h16 -> FP16Bit
1439 0, // FP32Bit:subreg_h32
1440 0, // FP32Bit:subreg_h64
1441 0, // FP32Bit:subreg_l32
1442 0, // FP32Bit:subreg_l64
1443 0, // FP32Bit:subreg_lh32
1444 0, // FP32Bit:subreg_ll32
1445 0, // FP32Bit:subreg_lh32_then_subreg_h16
1446 },
1447 { // GR32Bit
1448 0, // GR32Bit:subreg_h16
1449 0, // GR32Bit:subreg_h32
1450 0, // GR32Bit:subreg_h64
1451 0, // GR32Bit:subreg_l32
1452 0, // GR32Bit:subreg_l64
1453 0, // GR32Bit:subreg_lh32
1454 0, // GR32Bit:subreg_ll32
1455 0, // GR32Bit:subreg_lh32_then_subreg_h16
1456 },
1457 { // GRH32Bit
1458 0, // GRH32Bit:subreg_h16
1459 0, // GRH32Bit:subreg_h32
1460 0, // GRH32Bit:subreg_h64
1461 0, // GRH32Bit:subreg_l32
1462 0, // GRH32Bit:subreg_l64
1463 0, // GRH32Bit:subreg_lh32
1464 0, // GRH32Bit:subreg_ll32
1465 0, // GRH32Bit:subreg_lh32_then_subreg_h16
1466 },
1467 { // ADDR32Bit
1468 0, // ADDR32Bit:subreg_h16
1469 0, // ADDR32Bit:subreg_h32
1470 0, // ADDR32Bit:subreg_h64
1471 0, // ADDR32Bit:subreg_l32
1472 0, // ADDR32Bit:subreg_l64
1473 0, // ADDR32Bit:subreg_lh32
1474 0, // ADDR32Bit:subreg_ll32
1475 0, // ADDR32Bit:subreg_lh32_then_subreg_h16
1476 },
1477 { // CCR
1478 0, // CCR:subreg_h16
1479 0, // CCR:subreg_h32
1480 0, // CCR:subreg_h64
1481 0, // CCR:subreg_l32
1482 0, // CCR:subreg_l64
1483 0, // CCR:subreg_lh32
1484 0, // CCR:subreg_ll32
1485 0, // CCR:subreg_lh32_then_subreg_h16
1486 },
1487 { // FPCRegs
1488 0, // FPCRegs:subreg_h16
1489 0, // FPCRegs:subreg_h32
1490 0, // FPCRegs:subreg_h64
1491 0, // FPCRegs:subreg_l32
1492 0, // FPCRegs:subreg_l64
1493 0, // FPCRegs:subreg_lh32
1494 0, // FPCRegs:subreg_ll32
1495 0, // FPCRegs:subreg_lh32_then_subreg_h16
1496 },
1497 { // AnyRegBit
1498 1, // AnyRegBit:subreg_h16 -> VR16Bit
1499 4, // AnyRegBit:subreg_h32 -> VR32Bit
1500 17, // AnyRegBit:subreg_h64 -> FP64Bit
1501 7, // AnyRegBit:subreg_l32 -> GR32Bit
1502 0, // AnyRegBit:subreg_l64
1503 0, // AnyRegBit:subreg_lh32
1504 0, // AnyRegBit:subreg_ll32
1505 0, // AnyRegBit:subreg_lh32_then_subreg_h16
1506 },
1507 { // AnyRegBit_with_subreg_h16
1508 1, // AnyRegBit_with_subreg_h16:subreg_h16 -> VR16Bit
1509 4, // AnyRegBit_with_subreg_h16:subreg_h32 -> VR32Bit
1510 17, // AnyRegBit_with_subreg_h16:subreg_h64 -> FP64Bit
1511 0, // AnyRegBit_with_subreg_h16:subreg_l32
1512 0, // AnyRegBit_with_subreg_h16:subreg_l64
1513 0, // AnyRegBit_with_subreg_h16:subreg_lh32
1514 0, // AnyRegBit_with_subreg_h16:subreg_ll32
1515 0, // AnyRegBit_with_subreg_h16:subreg_lh32_then_subreg_h16
1516 },
1517 { // VR64Bit
1518 1, // VR64Bit:subreg_h16 -> VR16Bit
1519 4, // VR64Bit:subreg_h32 -> VR32Bit
1520 0, // VR64Bit:subreg_h64
1521 0, // VR64Bit:subreg_l32
1522 0, // VR64Bit:subreg_l64
1523 0, // VR64Bit:subreg_lh32
1524 0, // VR64Bit:subreg_ll32
1525 0, // VR64Bit:subreg_lh32_then_subreg_h16
1526 },
1527 { // AnyRegBit_with_subreg_h64
1528 2, // AnyRegBit_with_subreg_h64:subreg_h16 -> FP16Bit
1529 6, // AnyRegBit_with_subreg_h64:subreg_h32 -> FP32Bit
1530 17, // AnyRegBit_with_subreg_h64:subreg_h64 -> FP64Bit
1531 0, // AnyRegBit_with_subreg_h64:subreg_l32
1532 0, // AnyRegBit_with_subreg_h64:subreg_l64
1533 0, // AnyRegBit_with_subreg_h64:subreg_lh32
1534 0, // AnyRegBit_with_subreg_h64:subreg_ll32
1535 0, // AnyRegBit_with_subreg_h64:subreg_lh32_then_subreg_h16
1536 },
1537 { // CR64Bit
1538 0, // CR64Bit:subreg_h16
1539 0, // CR64Bit:subreg_h32
1540 0, // CR64Bit:subreg_h64
1541 0, // CR64Bit:subreg_l32
1542 0, // CR64Bit:subreg_l64
1543 0, // CR64Bit:subreg_lh32
1544 0, // CR64Bit:subreg_ll32
1545 0, // CR64Bit:subreg_lh32_then_subreg_h16
1546 },
1547 { // FP64Bit
1548 2, // FP64Bit:subreg_h16 -> FP16Bit
1549 6, // FP64Bit:subreg_h32 -> FP32Bit
1550 0, // FP64Bit:subreg_h64
1551 0, // FP64Bit:subreg_l32
1552 0, // FP64Bit:subreg_l64
1553 0, // FP64Bit:subreg_lh32
1554 0, // FP64Bit:subreg_ll32
1555 0, // FP64Bit:subreg_lh32_then_subreg_h16
1556 },
1557 { // GR64Bit
1558 0, // GR64Bit:subreg_h16
1559 8, // GR64Bit:subreg_h32 -> GRH32Bit
1560 0, // GR64Bit:subreg_h64
1561 7, // GR64Bit:subreg_l32 -> GR32Bit
1562 0, // GR64Bit:subreg_l64
1563 0, // GR64Bit:subreg_lh32
1564 0, // GR64Bit:subreg_ll32
1565 0, // GR64Bit:subreg_lh32_then_subreg_h16
1566 },
1567 { // ADDR64Bit
1568 0, // ADDR64Bit:subreg_h16
1569 8, // ADDR64Bit:subreg_h32 -> GRH32Bit
1570 0, // ADDR64Bit:subreg_h64
1571 9, // ADDR64Bit:subreg_l32 -> ADDR32Bit
1572 0, // ADDR64Bit:subreg_l64
1573 0, // ADDR64Bit:subreg_lh32
1574 0, // ADDR64Bit:subreg_ll32
1575 0, // ADDR64Bit:subreg_lh32_then_subreg_h16
1576 },
1577 { // VR128Bit
1578 1, // VR128Bit:subreg_h16 -> VR16Bit
1579 4, // VR128Bit:subreg_h32 -> VR32Bit
1580 14, // VR128Bit:subreg_h64 -> VR64Bit
1581 0, // VR128Bit:subreg_l32
1582 0, // VR128Bit:subreg_l64
1583 0, // VR128Bit:subreg_lh32
1584 0, // VR128Bit:subreg_ll32
1585 0, // VR128Bit:subreg_lh32_then_subreg_h16
1586 },
1587 { // VF128Bit
1588 2, // VF128Bit:subreg_h16 -> FP16Bit
1589 6, // VF128Bit:subreg_h32 -> FP32Bit
1590 17, // VF128Bit:subreg_h64 -> FP64Bit
1591 0, // VF128Bit:subreg_l32
1592 0, // VF128Bit:subreg_l64
1593 0, // VF128Bit:subreg_lh32
1594 0, // VF128Bit:subreg_ll32
1595 0, // VF128Bit:subreg_lh32_then_subreg_h16
1596 },
1597 { // FP128Bit
1598 2, // FP128Bit:subreg_h16 -> FP16Bit
1599 6, // FP128Bit:subreg_h32 -> FP32Bit
1600 17, // FP128Bit:subreg_h64 -> FP64Bit
1601 0, // FP128Bit:subreg_l32
1602 17, // FP128Bit:subreg_l64 -> FP64Bit
1603 6, // FP128Bit:subreg_lh32 -> FP32Bit
1604 0, // FP128Bit:subreg_ll32
1605 2, // FP128Bit:subreg_lh32_then_subreg_h16 -> FP16Bit
1606 },
1607 { // GR128Bit
1608 0, // GR128Bit:subreg_h16
1609 8, // GR128Bit:subreg_h32 -> GRH32Bit
1610 18, // GR128Bit:subreg_h64 -> GR64Bit
1611 7, // GR128Bit:subreg_l32 -> GR32Bit
1612 19, // GR128Bit:subreg_l64 -> ADDR64Bit
1613 8, // GR128Bit:subreg_lh32 -> GRH32Bit
1614 9, // GR128Bit:subreg_ll32 -> ADDR32Bit
1615 0, // GR128Bit:subreg_lh32_then_subreg_h16
1616 },
1617 { // ADDR128Bit
1618 0, // ADDR128Bit:subreg_h16
1619 8, // ADDR128Bit:subreg_h32 -> GRH32Bit
1620 19, // ADDR128Bit:subreg_h64 -> ADDR64Bit
1621 9, // ADDR128Bit:subreg_l32 -> ADDR32Bit
1622 19, // ADDR128Bit:subreg_l64 -> ADDR64Bit
1623 8, // ADDR128Bit:subreg_lh32 -> GRH32Bit
1624 9, // ADDR128Bit:subreg_ll32 -> ADDR32Bit
1625 0, // ADDR128Bit:subreg_lh32_then_subreg_h16
1626 },
1627 };
1628 assert(RC && "Missing regclass");
1629 if (!Idx) return RC;
1630 --Idx;
1631 assert(Idx < 8 && "Bad subreg");
1632 unsigned TV = Table[RC->getID()][Idx];
1633 return TV ? getRegClass(i: TV - 1) : nullptr;
1634}
1635
1636/// Get the weight in units of pressure for this register class.
1637const RegClassWeight &SystemZGenRegisterInfo::
1638getRegClassWeight(const TargetRegisterClass *RC) const {
1639 static const RegClassWeight RCWeightTable[] = {
1640 {.RegWeight: 1, .WeightLimit: 32}, // VR16Bit
1641 {.RegWeight: 1, .WeightLimit: 16}, // FP16Bit
1642 {.RegWeight: 1, .WeightLimit: 32}, // GRX32Bit
1643 {.RegWeight: 1, .WeightLimit: 32}, // VR32Bit
1644 {.RegWeight: 0, .WeightLimit: 0}, // AR32Bit
1645 {.RegWeight: 1, .WeightLimit: 16}, // FP32Bit
1646 {.RegWeight: 1, .WeightLimit: 16}, // GR32Bit
1647 {.RegWeight: 1, .WeightLimit: 16}, // GRH32Bit
1648 {.RegWeight: 1, .WeightLimit: 15}, // ADDR32Bit
1649 {.RegWeight: 0, .WeightLimit: 0}, // CCR
1650 {.RegWeight: 0, .WeightLimit: 0}, // FPCRegs
1651 {.RegWeight: 1, .WeightLimit: 48}, // AnyRegBit
1652 {.RegWeight: 1, .WeightLimit: 16}, // AnyRegBit_with_subreg_h16
1653 {.RegWeight: 1, .WeightLimit: 32}, // VR64Bit
1654 {.RegWeight: 1, .WeightLimit: 16}, // AnyRegBit_with_subreg_h64
1655 {.RegWeight: 0, .WeightLimit: 0}, // CR64Bit
1656 {.RegWeight: 1, .WeightLimit: 16}, // FP64Bit
1657 {.RegWeight: 2, .WeightLimit: 32}, // GR64Bit
1658 {.RegWeight: 2, .WeightLimit: 30}, // ADDR64Bit
1659 {.RegWeight: 1, .WeightLimit: 32}, // VR128Bit
1660 {.RegWeight: 1, .WeightLimit: 16}, // VF128Bit
1661 {.RegWeight: 2, .WeightLimit: 16}, // FP128Bit
1662 {.RegWeight: 4, .WeightLimit: 32}, // GR128Bit
1663 {.RegWeight: 4, .WeightLimit: 28}, // ADDR128Bit
1664 };
1665 return RCWeightTable[RC->getID()];
1666}
1667
1668/// Get the weight in units of pressure for this register unit.
1669unsigned SystemZGenRegisterInfo::
1670getRegUnitWeight(MCRegUnit RegUnit) const {
1671 assert(static_cast<unsigned>(RegUnit) < 98 && "invalid register unit");
1672 // All register units have unit weight.
1673 return 1;
1674}
1675
1676
1677// Get the number of dimensions of register pressure.
1678unsigned SystemZGenRegisterInfo::getNumRegPressureSets() const {
1679 return 5;
1680}
1681
1682// Get the name of this register unit pressure set.
1683const char *SystemZGenRegisterInfo::
1684getRegPressureSetName(unsigned Idx) const {
1685 static const char *PressureNameTable[] = {
1686 "FP16Bit",
1687 "GR32Bit",
1688 "GRH32Bit",
1689 "VR16Bit",
1690 "GRX32Bit",
1691 };
1692 return PressureNameTable[Idx];
1693}
1694
1695// Get the register unit pressure limit for this dimension.
1696// This limit must be adjusted dynamically for reserved registers.
1697unsigned SystemZGenRegisterInfo::
1698getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1699 static const uint8_t PressureLimitTable[] = {
1700 16, // 0: FP16Bit
1701 16, // 1: GR32Bit
1702 16, // 2: GRH32Bit
1703 32, // 3: VR16Bit
1704 32, // 4: GRX32Bit
1705 };
1706 return PressureLimitTable[Idx];
1707}
1708
1709/// Table of pressure sets per register class or unit.
1710static const int RCSetsTable[] = {
1711 /* 0 */ 0, 3, -1,
1712 /* 3 */ 1, 4, -1,
1713 /* 6 */ 2, 4, -1,
1714};
1715
1716/// Get the dimensions of register pressure impacted by this register class.
1717/// Returns a -1 terminated array of pressure set IDs
1718const int *SystemZGenRegisterInfo::
1719getRegClassPressureSets(const TargetRegisterClass *RC) const {
1720 static const uint8_t RCSetStartTable[] = {
1721 1,0,4,1,2,0,3,6,3,2,2,2,2,1,2,2,0,4,4,1,0,0,4,4,};
1722 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1723}
1724
1725/// Get the dimensions of register pressure impacted by this register unit.
1726/// Returns a -1 terminated array of pressure set IDs
1727const int *SystemZGenRegisterInfo::
1728getRegUnitPressureSets(MCRegUnit RegUnit) const {
1729 assert(static_cast<unsigned>(RegUnit) < 98 && "invalid register unit");
1730 static const uint8_t RUSetStartTable[] = {
1731 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,};
1732 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1733}
1734
1735extern const MCRegisterDesc SystemZRegDesc[];
1736extern const int16_t SystemZRegDiffLists[];
1737extern const LaneBitmask SystemZLaneMaskLists[];
1738extern const char SystemZRegStrings[];
1739extern const char SystemZRegClassStrings[];
1740extern const MCPhysReg SystemZRegUnitRoots[][2];
1741extern const uint16_t SystemZSubRegIdxLists[];
1742extern const uint16_t SystemZRegEncodingTable[];
1743// SystemZ Dwarf<->LLVM register mappings.
1744extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[];
1745extern const unsigned SystemZDwarfFlavour0Dwarf2LSize;
1746
1747extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[];
1748extern const unsigned SystemZEHFlavour0Dwarf2LSize;
1749
1750extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[];
1751extern const unsigned SystemZDwarfFlavour0L2DwarfSize;
1752
1753extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[];
1754extern const unsigned SystemZEHFlavour0L2DwarfSize;
1755
1756SystemZGenRegisterInfo::
1757SystemZGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1758 unsigned PC, unsigned HwMode)
1759 : TargetRegisterInfo(&SystemZRegInfoDesc, RegisterClasses, RegisterClasses+24,
1760 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
1761 LaneBitmask(0xFFFFFFFFFFFFFFFC), RegClassInfos, VTLists, HwMode) {
1762 InitMCRegisterInfo(D: SystemZRegDesc, NR: 227, RA, PC,
1763 C: SystemZMCRegisterClasses, NC: 24,
1764 RURoots: SystemZRegUnitRoots,
1765 NRU: 98,
1766 DL: SystemZRegDiffLists,
1767 RUMS: SystemZLaneMaskLists,
1768 Strings: SystemZRegStrings,
1769 ClassStrings: SystemZRegClassStrings,
1770 SubIndices: SystemZSubRegIdxLists,
1771 NumIndices: 9,
1772 RET: SystemZRegEncodingTable);
1773
1774 switch (DwarfFlavour) {
1775 default:
1776 llvm_unreachable("Unknown DWARF flavour");
1777 case 0:
1778 mapDwarfRegsToLLVMRegs(Map: SystemZDwarfFlavour0Dwarf2L, Size: SystemZDwarfFlavour0Dwarf2LSize, isEH: false);
1779 break;
1780 }
1781 switch (EHFlavour) {
1782 default:
1783 llvm_unreachable("Unknown DWARF flavour");
1784 case 0:
1785 mapDwarfRegsToLLVMRegs(Map: SystemZEHFlavour0Dwarf2L, Size: SystemZEHFlavour0Dwarf2LSize, isEH: true);
1786 break;
1787 }
1788 switch (DwarfFlavour) {
1789 default:
1790 llvm_unreachable("Unknown DWARF flavour");
1791 case 0:
1792 mapLLVMRegsToDwarfRegs(Map: SystemZDwarfFlavour0L2Dwarf, Size: SystemZDwarfFlavour0L2DwarfSize, isEH: false);
1793 break;
1794 }
1795 switch (EHFlavour) {
1796 default:
1797 llvm_unreachable("Unknown DWARF flavour");
1798 case 0:
1799 mapLLVMRegsToDwarfRegs(Map: SystemZEHFlavour0L2Dwarf, Size: SystemZEHFlavour0L2DwarfSize, isEH: true);
1800 break;
1801 }
1802}
1803
1804static const MCPhysReg CSR_SystemZ_AllRegs_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
1805static const uint32_t CSR_SystemZ_AllRegs_RegMask[] = { 0x00000000, 0x00000000, 0x0007fff8, 0x0007fff8, 0x07fffff8, 0xe7ffe000, 0xf7ffe7ff, 0x00000007, };
1806static const MCPhysReg CSR_SystemZ_AllRegs_Vector_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, 0 };
1807static const uint32_t CSR_SystemZ_AllRegs_Vector_RegMask[] = { 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xffffffff, 0xe7ffe7ff, 0xf7ffe7ff, 0x00000007, };
1808static const MCPhysReg CSR_SystemZ_ELF_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
1809static const uint32_t CSR_SystemZ_ELF_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07fe0000, 0xc7fe07fe, 0x00000007, };
1810static const MCPhysReg CSR_SystemZ_NoRegs_SaveList[] = { 0 };
1811static const uint32_t CSR_SystemZ_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
1812static const MCPhysReg CSR_SystemZ_SwiftError_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
1813static const uint32_t CSR_SystemZ_SwiftError_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07ee0000, 0x47ee07ee, 0x00000007, };
1814static const MCPhysReg CSR_SystemZ_XPLINK64_SaveList[] = { SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F15D, SystemZ::F14D, SystemZ::F13D, SystemZ::F12D, SystemZ::F11D, SystemZ::F10D, SystemZ::F9D, SystemZ::F8D, 0 };
1815static const uint32_t CSR_SystemZ_XPLINK64_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07f80000, 0x87f807f8, 0x00000007, };
1816static const MCPhysReg CSR_SystemZ_XPLINK64_Vector_SaveList[] = { SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F15D, SystemZ::F14D, SystemZ::F13D, SystemZ::F12D, SystemZ::F11D, SystemZ::F10D, SystemZ::F9D, SystemZ::F8D, SystemZ::V23, SystemZ::V22, SystemZ::V21, SystemZ::V20, SystemZ::V19, SystemZ::V18, SystemZ::V17, SystemZ::V16, 0 };
1817static const uint32_t CSR_SystemZ_XPLINK64_Vector_RegMask[] = { 0x00000000, 0x07f80000, 0x07fff800, 0x07fff800, 0xfff80780, 0x07f80007, 0x87f807f8, 0x00000007, };
1818
1819
1820ArrayRef<const uint32_t *> SystemZGenRegisterInfo::getRegMasks() const {
1821 static const uint32_t *const Masks[] = {
1822 CSR_SystemZ_AllRegs_RegMask,
1823 CSR_SystemZ_AllRegs_Vector_RegMask,
1824 CSR_SystemZ_ELF_RegMask,
1825 CSR_SystemZ_NoRegs_RegMask,
1826 CSR_SystemZ_SwiftError_RegMask,
1827 CSR_SystemZ_XPLINK64_RegMask,
1828 CSR_SystemZ_XPLINK64_Vector_RegMask,
1829 };
1830 return ArrayRef(Masks);
1831}
1832
1833bool SystemZGenRegisterInfo::
1834isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1835 return
1836 false;
1837}
1838
1839bool SystemZGenRegisterInfo::
1840isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1841 return
1842 false;
1843}
1844
1845bool SystemZGenRegisterInfo::
1846isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1847 return
1848 false;
1849}
1850
1851bool SystemZGenRegisterInfo::
1852isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1853 return
1854 false;
1855}
1856
1857bool SystemZGenRegisterInfo::
1858isConstantPhysReg(MCRegister PhysReg) const {
1859 return
1860 false;
1861}
1862
1863ArrayRef<const char *> SystemZGenRegisterInfo::getRegMaskNames() const {
1864 static const char *Names[] = {
1865 "CSR_SystemZ_AllRegs",
1866 "CSR_SystemZ_AllRegs_Vector",
1867 "CSR_SystemZ_ELF",
1868 "CSR_SystemZ_NoRegs",
1869 "CSR_SystemZ_SwiftError",
1870 "CSR_SystemZ_XPLINK64",
1871 "CSR_SystemZ_XPLINK64_Vector",
1872 };
1873 return ArrayRef(Names);
1874}
1875
1876const SystemZFrameLowering *
1877SystemZGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1878 return static_cast<const SystemZFrameLowering *>(
1879 MF.getSubtarget().getFrameLowering());
1880}
1881
1882} // end namespace llvm
1883
1884