1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<24, 455, 400, 54, 17, 20> SystemZMCRegisterClassStorage;
12
13static const MVT::SimpleValueType SystemZVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f16, MVT::Other,
17 /* 6 */ MVT::f32, MVT::Other,
18 /* 8 */ MVT::f64, MVT::Other,
19 /* 10 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::i128, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
20 /* 20 */ MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
21 /* 24 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v2f32, MVT::Other,
22 /* 31 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::Other,
23 /* 39 */ MVT::Untyped, MVT::Other,
24};
25
26#ifdef __GNUC__
27#pragma GCC diagnostic push
28#pragma GCC diagnostic ignored "-Woverlength-strings"
29#endif
30static constexpr char SystemZSubRegIndexStrings[] = {
31 /* 0 */ "subreg_h32\000"
32 /* 11 */ "subreg_lh32\000"
33 /* 23 */ "subreg_l32\000"
34 /* 34 */ "subreg_ll32\000"
35 /* 46 */ "subreg_h64\000"
36 /* 57 */ "subreg_l64\000"
37 /* 68 */ "subreg_lh32_then_subreg_h16\000"
38};
39#ifdef __GNUC__
40#pragma GCC diagnostic pop
41#endif
42
43
44static constexpr uint32_t SystemZSubRegIndexNameOffsets[] = {
45 85,
46 0,
47 46,
48 23,
49 57,
50 11,
51 34,
52 68,
53};
54
55static const TargetRegisterInfo::SubRegCoveredBits SystemZSubRegIdxRangeTable[] = {
56 { .Offset: 4294967295, .Size: 4294967295 },
57 { .Offset: 16, .Size: 16 }, // subreg_h16
58 { .Offset: 32, .Size: 32 }, // subreg_h32
59 { .Offset: 64, .Size: 64 }, // subreg_h64
60 { .Offset: 0, .Size: 32 }, // subreg_l32
61 { .Offset: 0, .Size: 64 }, // subreg_l64
62 { .Offset: 32, .Size: 32 }, // subreg_lh32
63 { .Offset: 0, .Size: 32 }, // subreg_ll32
64 { .Offset: 48, .Size: 16 }, // subreg_lh32_then_subreg_h16
65 { .Offset: 4294967295, .Size: 4294967295 },
66 { .Offset: 16, .Size: 16 }, // subreg_h16
67 { .Offset: 32, .Size: 32 }, // subreg_h32
68 { .Offset: 64, .Size: 64 }, // subreg_h64
69 { .Offset: 0, .Size: 32 }, // subreg_l32
70 { .Offset: 0, .Size: 64 }, // subreg_l64
71 { .Offset: 32, .Size: 32 }, // subreg_lh32
72 { .Offset: 0, .Size: 32 }, // subreg_ll32
73 { .Offset: 48, .Size: 16 }, // subreg_lh32_then_subreg_h16
74};
75
76
77static const LaneBitmask SystemZSubRegIndexLaneMaskTable[] = {
78 LaneBitmask::getAll(),
79 LaneBitmask(0x0000000000000001), // subreg_h16
80 LaneBitmask(0x0000000000000001), // subreg_h32
81 LaneBitmask(0x0000000000000003), // subreg_h64
82 LaneBitmask(0x0000000000000002), // subreg_l32
83 LaneBitmask(0x000000000000000C), // subreg_l64
84 LaneBitmask(0x0000000000000008), // subreg_lh32
85 LaneBitmask(0x0000000000000004), // subreg_ll32
86 LaneBitmask(0x0000000000000008), // subreg_lh32_then_subreg_h16
87 };
88
89
90
91static const TargetRegisterInfo::RegClassInfo SystemZRegClassInfos[] = {
92 // Mode = 0 (DefaultMode)
93 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*SystemZVTLists+*/.VTListOffset: 4 }, // VR16Bit
94 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*SystemZVTLists+*/.VTListOffset: 4 }, // FP16Bit
95 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // GRX32Bit
96 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 20 }, // VR32Bit
97 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // AR32Bit
98 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 6 }, // FP32Bit
99 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // GR32Bit
100 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // GRH32Bit
101 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // ADDR32Bit
102 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // CCR
103 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // FPCRegs
104 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 24 }, // AnyRegBit
105 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h16
106 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 25 }, // VR64Bit
107 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h64
108 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 2 }, // CR64Bit
109 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 8 }, // FP64Bit
110 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 2 }, // GR64Bit
111 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 2 }, // ADDR64Bit
112 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 10 }, // VR128Bit
113 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 31 }, // VF128Bit
114 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 18 }, // FP128Bit
115 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 39 }, // GR128Bit
116 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 39 }, // ADDR128Bit
117 // Mode = 1 (NoVecHwMode)
118 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*SystemZVTLists+*/.VTListOffset: 4 }, // VR16Bit
119 { .RegSize: 16, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 4 }, // FP16Bit
120 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // GRX32Bit
121 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 20 }, // VR32Bit
122 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // AR32Bit
123 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 6 }, // FP32Bit
124 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // GR32Bit
125 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // GRH32Bit
126 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // ADDR32Bit
127 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // CCR
128 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // FPCRegs
129 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 24 }, // AnyRegBit
130 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h16
131 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 25 }, // VR64Bit
132 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h64
133 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 2 }, // CR64Bit
134 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 8 }, // FP64Bit
135 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 2 }, // GR64Bit
136 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 2 }, // ADDR64Bit
137 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 10 }, // VR128Bit
138 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 31 }, // VF128Bit
139 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 18 }, // FP128Bit
140 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 39 }, // GR128Bit
141 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 39 }, // ADDR128Bit
142};
143
144static inline unsigned VR16BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
145 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
146 return S.isTargetXPLINK64();
147 }
148
149static ArrayRef<MCPhysReg> VR16BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
150 static const MCPhysReg AltOrder1[] = { SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F16H, SystemZ::F17H, SystemZ::F18H, SystemZ::F19H, SystemZ::F20H, SystemZ::F21H, SystemZ::F22H, SystemZ::F23H, SystemZ::F24H, SystemZ::F25H, SystemZ::F26H, SystemZ::F27H, SystemZ::F28H, SystemZ::F29H, SystemZ::F30H, SystemZ::F31H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H };
151 const ArrayRef<MCPhysReg> Order[] = {
152 RC.getRegisters(),
153 ArrayRef(AltOrder1)
154 };
155 const unsigned Select = VR16BitAltOrderSelect(MF, Rev);
156 assert(Select < 2);
157 return Order[Select];
158}
159
160static inline unsigned FP16BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
161 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
162 return S.isTargetXPLINK64();
163 }
164
165static ArrayRef<MCPhysReg> FP16BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
166 static const MCPhysReg AltOrder1[] = { SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H };
167 const ArrayRef<MCPhysReg> Order[] = {
168 RC.getRegisters(),
169 ArrayRef(AltOrder1)
170 };
171 const unsigned Select = FP16BitAltOrderSelect(MF, Rev);
172 assert(Select < 2);
173 return Order[Select];
174}
175
176static inline unsigned GRX32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
177 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
178 return S.isTargetXPLINK64();
179 }
180
181static ArrayRef<MCPhysReg> GRX32BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
182 static const MCPhysReg AltOrder1[] = { SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4L, SystemZ::R4H, SystemZ::R5L, SystemZ::R5H, SystemZ::R6L, SystemZ::R6H, SystemZ::R7L, SystemZ::R7H, SystemZ::R8L, SystemZ::R8H, SystemZ::R9L, SystemZ::R9H, SystemZ::R10L, SystemZ::R10H, SystemZ::R11L, SystemZ::R11H, SystemZ::R12L, SystemZ::R12H, SystemZ::R13L, SystemZ::R13H, SystemZ::R14L, SystemZ::R14H, SystemZ::R15L, SystemZ::R15H };
183 const ArrayRef<MCPhysReg> Order[] = {
184 RC.getRegisters(),
185 ArrayRef(AltOrder1)
186 };
187 const unsigned Select = GRX32BitAltOrderSelect(MF, Rev);
188 assert(Select < 2);
189 return Order[Select];
190}
191
192static inline unsigned VR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
193 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
194 return S.isTargetXPLINK64();
195 }
196
197static ArrayRef<MCPhysReg> VR32BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
198 static const MCPhysReg AltOrder1[] = { SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
199 const ArrayRef<MCPhysReg> Order[] = {
200 RC.getRegisters(),
201 ArrayRef(AltOrder1)
202 };
203 const unsigned Select = VR32BitAltOrderSelect(MF, Rev);
204 assert(Select < 2);
205 return Order[Select];
206}
207
208static inline unsigned AR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
209 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
210 return S.isTargetXPLINK64();
211 }
212
213static ArrayRef<MCPhysReg> AR32BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
214 const ArrayRef<MCPhysReg> Order[] = {
215 RC.getRegisters()
216 };
217 const unsigned Select = AR32BitAltOrderSelect(MF, Rev);
218 assert(Select < 1);
219 return Order[Select];
220}
221
222static inline unsigned FP32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
223 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
224 return S.isTargetXPLINK64();
225 }
226
227static ArrayRef<MCPhysReg> FP32BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
228 static const MCPhysReg AltOrder1[] = { SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
229 const ArrayRef<MCPhysReg> Order[] = {
230 RC.getRegisters(),
231 ArrayRef(AltOrder1)
232 };
233 const unsigned Select = FP32BitAltOrderSelect(MF, Rev);
234 assert(Select < 2);
235 return Order[Select];
236}
237
238static inline unsigned GR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
239 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
240 return S.isTargetXPLINK64();
241 }
242
243static ArrayRef<MCPhysReg> GR32BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
244 static const MCPhysReg AltOrder1[] = { SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L };
245 const ArrayRef<MCPhysReg> Order[] = {
246 RC.getRegisters(),
247 ArrayRef(AltOrder1)
248 };
249 const unsigned Select = GR32BitAltOrderSelect(MF, Rev);
250 assert(Select < 2);
251 return Order[Select];
252}
253
254static inline unsigned GRH32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
255 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
256 return S.isTargetXPLINK64();
257 }
258
259static ArrayRef<MCPhysReg> GRH32BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
260 static const MCPhysReg AltOrder1[] = { SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H, SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H, SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H };
261 const ArrayRef<MCPhysReg> Order[] = {
262 RC.getRegisters(),
263 ArrayRef(AltOrder1)
264 };
265 const unsigned Select = GRH32BitAltOrderSelect(MF, Rev);
266 assert(Select < 2);
267 return Order[Select];
268}
269
270static inline unsigned ADDR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
271 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
272 return S.isTargetXPLINK64();
273 }
274
275static ArrayRef<MCPhysReg> ADDR32BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
276 static const MCPhysReg AltOrder1[] = { SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L };
277 const ArrayRef<MCPhysReg> Order[] = {
278 RC.getRegisters(),
279 ArrayRef(AltOrder1)
280 };
281 const unsigned Select = ADDR32BitAltOrderSelect(MF, Rev);
282 assert(Select < 2);
283 return Order[Select];
284}
285
286static inline unsigned AnyRegBitAltOrderSelect(const MachineFunction &MF, bool Rev) {
287 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
288 return S.isTargetXPLINK64();
289 }
290
291static ArrayRef<MCPhysReg> AnyRegBitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
292 const ArrayRef<MCPhysReg> Order[] = {
293 RC.getRegisters()
294 };
295 const unsigned Select = AnyRegBitAltOrderSelect(MF, Rev);
296 assert(Select < 1);
297 return Order[Select];
298}
299
300static inline unsigned AnyRegBit_with_subreg_h16AltOrderSelect(const MachineFunction &MF, bool Rev) {
301 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
302 return S.isTargetXPLINK64();
303 }
304
305static ArrayRef<MCPhysReg> AnyRegBit_with_subreg_h16GetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
306 const ArrayRef<MCPhysReg> Order[] = {
307 RC.getRegisters()
308 };
309 const unsigned Select = AnyRegBit_with_subreg_h16AltOrderSelect(MF, Rev);
310 assert(Select < 1);
311 return Order[Select];
312}
313
314static inline unsigned VR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
315 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
316 return S.isTargetXPLINK64();
317 }
318
319static ArrayRef<MCPhysReg> VR64BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
320 static const MCPhysReg AltOrder1[] = { SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D };
321 const ArrayRef<MCPhysReg> Order[] = {
322 RC.getRegisters(),
323 ArrayRef(AltOrder1)
324 };
325 const unsigned Select = VR64BitAltOrderSelect(MF, Rev);
326 assert(Select < 2);
327 return Order[Select];
328}
329
330static inline unsigned AnyRegBit_with_subreg_h64AltOrderSelect(const MachineFunction &MF, bool Rev) {
331 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
332 return S.isTargetXPLINK64();
333 }
334
335static ArrayRef<MCPhysReg> AnyRegBit_with_subreg_h64GetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
336 const ArrayRef<MCPhysReg> Order[] = {
337 RC.getRegisters()
338 };
339 const unsigned Select = AnyRegBit_with_subreg_h64AltOrderSelect(MF, Rev);
340 assert(Select < 1);
341 return Order[Select];
342}
343
344static inline unsigned CR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
345 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
346 return S.isTargetXPLINK64();
347 }
348
349static ArrayRef<MCPhysReg> CR64BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
350 const ArrayRef<MCPhysReg> Order[] = {
351 RC.getRegisters()
352 };
353 const unsigned Select = CR64BitAltOrderSelect(MF, Rev);
354 assert(Select < 1);
355 return Order[Select];
356}
357
358static inline unsigned FP64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
359 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
360 return S.isTargetXPLINK64();
361 }
362
363static ArrayRef<MCPhysReg> FP64BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
364 static const MCPhysReg AltOrder1[] = { SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D };
365 const ArrayRef<MCPhysReg> Order[] = {
366 RC.getRegisters(),
367 ArrayRef(AltOrder1)
368 };
369 const unsigned Select = FP64BitAltOrderSelect(MF, Rev);
370 assert(Select < 2);
371 return Order[Select];
372}
373
374static inline unsigned GR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
375 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
376 return S.isTargetXPLINK64();
377 }
378
379static ArrayRef<MCPhysReg> GR64BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
380 static const MCPhysReg AltOrder1[] = { SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D };
381 const ArrayRef<MCPhysReg> Order[] = {
382 RC.getRegisters(),
383 ArrayRef(AltOrder1)
384 };
385 const unsigned Select = GR64BitAltOrderSelect(MF, Rev);
386 assert(Select < 2);
387 return Order[Select];
388}
389
390static inline unsigned ADDR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
391 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
392 return S.isTargetXPLINK64();
393 }
394
395static ArrayRef<MCPhysReg> ADDR64BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
396 static const MCPhysReg AltOrder1[] = { SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D };
397 const ArrayRef<MCPhysReg> Order[] = {
398 RC.getRegisters(),
399 ArrayRef(AltOrder1)
400 };
401 const unsigned Select = ADDR64BitAltOrderSelect(MF, Rev);
402 assert(Select < 2);
403 return Order[Select];
404}
405
406static inline unsigned VR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
407 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
408 return S.isTargetXPLINK64();
409 }
410
411static ArrayRef<MCPhysReg> VR128BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
412 static const MCPhysReg AltOrder1[] = { SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15 };
413 const ArrayRef<MCPhysReg> Order[] = {
414 RC.getRegisters(),
415 ArrayRef(AltOrder1)
416 };
417 const unsigned Select = VR128BitAltOrderSelect(MF, Rev);
418 assert(Select < 2);
419 return Order[Select];
420}
421
422static inline unsigned VF128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
423 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
424 return S.isTargetXPLINK64();
425 }
426
427static ArrayRef<MCPhysReg> VF128BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
428 static const MCPhysReg AltOrder1[] = { SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15 };
429 const ArrayRef<MCPhysReg> Order[] = {
430 RC.getRegisters(),
431 ArrayRef(AltOrder1)
432 };
433 const unsigned Select = VF128BitAltOrderSelect(MF, Rev);
434 assert(Select < 2);
435 return Order[Select];
436}
437
438static inline unsigned FP128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
439 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
440 return S.isTargetXPLINK64();
441 }
442
443static ArrayRef<MCPhysReg> FP128BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
444 static const MCPhysReg AltOrder1[] = { SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q };
445 const ArrayRef<MCPhysReg> Order[] = {
446 RC.getRegisters(),
447 ArrayRef(AltOrder1)
448 };
449 const unsigned Select = FP128BitAltOrderSelect(MF, Rev);
450 assert(Select < 2);
451 return Order[Select];
452}
453
454static inline unsigned GR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
455 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
456 return S.isTargetXPLINK64();
457 }
458
459static ArrayRef<MCPhysReg> GR128BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
460 static const MCPhysReg AltOrder1[] = { SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R6Q, SystemZ::R8Q, SystemZ::R10Q, SystemZ::R12Q, SystemZ::R14Q };
461 const ArrayRef<MCPhysReg> Order[] = {
462 RC.getRegisters(),
463 ArrayRef(AltOrder1)
464 };
465 const unsigned Select = GR128BitAltOrderSelect(MF, Rev);
466 assert(Select < 2);
467 return Order[Select];
468}
469
470static inline unsigned ADDR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
471 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
472 return S.isTargetXPLINK64();
473 }
474
475static ArrayRef<MCPhysReg> ADDR128BitGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
476 static const MCPhysReg AltOrder1[] = { SystemZ::R2Q, SystemZ::R4Q, SystemZ::R6Q, SystemZ::R8Q, SystemZ::R10Q, SystemZ::R12Q, SystemZ::R14Q };
477 const ArrayRef<MCPhysReg> Order[] = {
478 RC.getRegisters(),
479 ArrayRef(AltOrder1)
480 };
481 const unsigned Select = ADDR128BitAltOrderSelect(MF, Rev);
482 assert(Select < 2);
483 return Order[Select];
484}
485
486static const uint8_t SystemZCostPerUseTable[] = {
4870, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
488
489
490static const bool SystemZInAllocatableClassTable[] = {
491false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
492
493
494static const TargetRegisterInfoDesc SystemZRegInfoDesc = { // Extra Descriptors
495.CostPerUse: SystemZCostPerUseTable, .NumCosts: 1, .InAllocatableClass: SystemZInAllocatableClassTable};
496
497unsigned SystemZGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
498 static const uint8_t RowMap[8] = {
499 0, 0, 0, 0, 1, 1, 0, 0,
500 };
501 static const uint8_t Rows[2][8] = {
502 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
503 { SystemZ::subreg_lh32_then_subreg_h16, SystemZ::subreg_lh32, 0, SystemZ::subreg_ll32, 0, 0, 0, 0, },
504 };
505
506 --IdxA; assert(IdxA < 8); (void) IdxA;
507 --IdxB; assert(IdxB < 8);
508 return Rows[RowMap[IdxA]][IdxB];
509}
510
511unsigned SystemZGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
512 static const uint8_t Table[8][8] = {
513 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
514 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
515 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
516 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
517 { 0, 0, 0, 0, 0, SystemZ::subreg_h32, SystemZ::subreg_l32, SystemZ::subreg_h16, },
518 { 0, 0, 0, 0, 0, SystemZ::subreg_h32, SystemZ::subreg_l32, SystemZ::subreg_h16, },
519 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
520 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
521 };
522
523 --IdxA; assert(IdxA < 8);
524 --IdxB; assert(IdxB < 8);
525 return Table[IdxA][IdxB];
526 }
527
528 struct MaskRolOp {
529 LaneBitmask Mask;
530 uint8_t RotateLeft;
531 };
532 static const MaskRolOp LaneMaskComposeSequences[] = {
533 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
534 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
535 { .Mask: LaneBitmask(0x0000000000000001), .RotateLeft: 3 }, { .Mask: LaneBitmask(0x0000000000000002), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
536 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 7
537 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 9
538 };
539 static const uint8_t CompositeSequences[] = {
540 0, // to subreg_h16
541 0, // to subreg_h32
542 0, // to subreg_h64
543 2, // to subreg_l32
544 4, // to subreg_l64
545 7, // to subreg_lh32
546 9, // to subreg_ll32
547 7 // to subreg_lh32_then_subreg_h16
548 };
549
550LaneBitmask SystemZGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
551 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
552 LaneBitmask Result;
553 for (const MaskRolOp *Ops =
554 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
555 Ops->Mask.any(); ++Ops) {
556 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
557 if (unsigned S = Ops->RotateLeft)
558 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
559 else
560 Result |= LaneBitmask(M);
561 }
562 return Result;
563}
564
565LaneBitmask SystemZGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
566 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
567 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
568 LaneBitmask Result;
569 for (const MaskRolOp *Ops =
570 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
571 Ops->Mask.any(); ++Ops) {
572 LaneBitmask::Type M = LaneMask.getAsInteger();
573 if (unsigned S = Ops->RotateLeft)
574 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
575 else
576 Result |= LaneBitmask(M);
577 }
578 return Result;
579}
580
581const TargetRegisterClass *SystemZGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
582 static constexpr uint8_t Table[24][8] = {
583 { // VR16Bit
584 0, // subreg_h16
585 0, // subreg_h32
586 0, // subreg_h64
587 0, // subreg_l32
588 0, // subreg_l64
589 0, // subreg_lh32
590 0, // subreg_ll32
591 0, // subreg_lh32_then_subreg_h16
592 },
593 { // FP16Bit
594 0, // subreg_h16
595 0, // subreg_h32
596 0, // subreg_h64
597 0, // subreg_l32
598 0, // subreg_l64
599 0, // subreg_lh32
600 0, // subreg_ll32
601 0, // subreg_lh32_then_subreg_h16
602 },
603 { // GRX32Bit
604 0, // subreg_h16
605 0, // subreg_h32
606 0, // subreg_h64
607 0, // subreg_l32
608 0, // subreg_l64
609 0, // subreg_lh32
610 0, // subreg_ll32
611 0, // subreg_lh32_then_subreg_h16
612 },
613 { // VR32Bit
614 4, // subreg_h16 -> VR32Bit
615 0, // subreg_h32
616 0, // subreg_h64
617 0, // subreg_l32
618 0, // subreg_l64
619 0, // subreg_lh32
620 0, // subreg_ll32
621 0, // subreg_lh32_then_subreg_h16
622 },
623 { // AR32Bit
624 0, // subreg_h16
625 0, // subreg_h32
626 0, // subreg_h64
627 0, // subreg_l32
628 0, // subreg_l64
629 0, // subreg_lh32
630 0, // subreg_ll32
631 0, // subreg_lh32_then_subreg_h16
632 },
633 { // FP32Bit
634 6, // subreg_h16 -> FP32Bit
635 0, // subreg_h32
636 0, // subreg_h64
637 0, // subreg_l32
638 0, // subreg_l64
639 0, // subreg_lh32
640 0, // subreg_ll32
641 0, // subreg_lh32_then_subreg_h16
642 },
643 { // GR32Bit
644 0, // subreg_h16
645 0, // subreg_h32
646 0, // subreg_h64
647 0, // subreg_l32
648 0, // subreg_l64
649 0, // subreg_lh32
650 0, // subreg_ll32
651 0, // subreg_lh32_then_subreg_h16
652 },
653 { // GRH32Bit
654 0, // subreg_h16
655 0, // subreg_h32
656 0, // subreg_h64
657 0, // subreg_l32
658 0, // subreg_l64
659 0, // subreg_lh32
660 0, // subreg_ll32
661 0, // subreg_lh32_then_subreg_h16
662 },
663 { // ADDR32Bit
664 0, // subreg_h16
665 0, // subreg_h32
666 0, // subreg_h64
667 0, // subreg_l32
668 0, // subreg_l64
669 0, // subreg_lh32
670 0, // subreg_ll32
671 0, // subreg_lh32_then_subreg_h16
672 },
673 { // CCR
674 0, // subreg_h16
675 0, // subreg_h32
676 0, // subreg_h64
677 0, // subreg_l32
678 0, // subreg_l64
679 0, // subreg_lh32
680 0, // subreg_ll32
681 0, // subreg_lh32_then_subreg_h16
682 },
683 { // FPCRegs
684 0, // subreg_h16
685 0, // subreg_h32
686 0, // subreg_h64
687 0, // subreg_l32
688 0, // subreg_l64
689 0, // subreg_lh32
690 0, // subreg_ll32
691 0, // subreg_lh32_then_subreg_h16
692 },
693 { // AnyRegBit
694 13, // subreg_h16 -> AnyRegBit_with_subreg_h16
695 12, // subreg_h32 -> AnyRegBit
696 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
697 18, // subreg_l32 -> GR64Bit
698 0, // subreg_l64
699 0, // subreg_lh32
700 0, // subreg_ll32
701 0, // subreg_lh32_then_subreg_h16
702 },
703 { // AnyRegBit_with_subreg_h16
704 13, // subreg_h16 -> AnyRegBit_with_subreg_h16
705 13, // subreg_h32 -> AnyRegBit_with_subreg_h16
706 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
707 0, // subreg_l32
708 0, // subreg_l64
709 0, // subreg_lh32
710 0, // subreg_ll32
711 0, // subreg_lh32_then_subreg_h16
712 },
713 { // VR64Bit
714 14, // subreg_h16 -> VR64Bit
715 14, // subreg_h32 -> VR64Bit
716 0, // subreg_h64
717 0, // subreg_l32
718 0, // subreg_l64
719 0, // subreg_lh32
720 0, // subreg_ll32
721 0, // subreg_lh32_then_subreg_h16
722 },
723 { // AnyRegBit_with_subreg_h64
724 15, // subreg_h16 -> AnyRegBit_with_subreg_h64
725 15, // subreg_h32 -> AnyRegBit_with_subreg_h64
726 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
727 0, // subreg_l32
728 0, // subreg_l64
729 0, // subreg_lh32
730 0, // subreg_ll32
731 0, // subreg_lh32_then_subreg_h16
732 },
733 { // CR64Bit
734 0, // subreg_h16
735 0, // subreg_h32
736 0, // subreg_h64
737 0, // subreg_l32
738 0, // subreg_l64
739 0, // subreg_lh32
740 0, // subreg_ll32
741 0, // subreg_lh32_then_subreg_h16
742 },
743 { // FP64Bit
744 17, // subreg_h16 -> FP64Bit
745 17, // subreg_h32 -> FP64Bit
746 0, // subreg_h64
747 0, // subreg_l32
748 0, // subreg_l64
749 0, // subreg_lh32
750 0, // subreg_ll32
751 0, // subreg_lh32_then_subreg_h16
752 },
753 { // GR64Bit
754 0, // subreg_h16
755 18, // subreg_h32 -> GR64Bit
756 0, // subreg_h64
757 18, // subreg_l32 -> GR64Bit
758 0, // subreg_l64
759 0, // subreg_lh32
760 0, // subreg_ll32
761 0, // subreg_lh32_then_subreg_h16
762 },
763 { // ADDR64Bit
764 0, // subreg_h16
765 19, // subreg_h32 -> ADDR64Bit
766 0, // subreg_h64
767 19, // subreg_l32 -> ADDR64Bit
768 0, // subreg_l64
769 0, // subreg_lh32
770 0, // subreg_ll32
771 0, // subreg_lh32_then_subreg_h16
772 },
773 { // VR128Bit
774 20, // subreg_h16 -> VR128Bit
775 20, // subreg_h32 -> VR128Bit
776 20, // subreg_h64 -> VR128Bit
777 0, // subreg_l32
778 0, // subreg_l64
779 0, // subreg_lh32
780 0, // subreg_ll32
781 0, // subreg_lh32_then_subreg_h16
782 },
783 { // VF128Bit
784 21, // subreg_h16 -> VF128Bit
785 21, // subreg_h32 -> VF128Bit
786 21, // subreg_h64 -> VF128Bit
787 0, // subreg_l32
788 0, // subreg_l64
789 0, // subreg_lh32
790 0, // subreg_ll32
791 0, // subreg_lh32_then_subreg_h16
792 },
793 { // FP128Bit
794 22, // subreg_h16 -> FP128Bit
795 22, // subreg_h32 -> FP128Bit
796 22, // subreg_h64 -> FP128Bit
797 0, // subreg_l32
798 22, // subreg_l64 -> FP128Bit
799 22, // subreg_lh32 -> FP128Bit
800 0, // subreg_ll32
801 22, // subreg_lh32_then_subreg_h16 -> FP128Bit
802 },
803 { // GR128Bit
804 0, // subreg_h16
805 23, // subreg_h32 -> GR128Bit
806 23, // subreg_h64 -> GR128Bit
807 23, // subreg_l32 -> GR128Bit
808 23, // subreg_l64 -> GR128Bit
809 23, // subreg_lh32 -> GR128Bit
810 23, // subreg_ll32 -> GR128Bit
811 0, // subreg_lh32_then_subreg_h16
812 },
813 { // ADDR128Bit
814 0, // subreg_h16
815 24, // subreg_h32 -> ADDR128Bit
816 24, // subreg_h64 -> ADDR128Bit
817 24, // subreg_l32 -> ADDR128Bit
818 24, // subreg_l64 -> ADDR128Bit
819 24, // subreg_lh32 -> ADDR128Bit
820 24, // subreg_ll32 -> ADDR128Bit
821 0, // subreg_lh32_then_subreg_h16
822 },
823
824 };
825 assert(RC && "Missing regclass");
826 if (!Idx) return RC;
827 --Idx;
828 assert(Idx < 8 && "Bad subreg");
829 unsigned TV = Table[RC->getID()][Idx];
830 return TV ? getRegClass(i: TV - 1) : nullptr;
831}const TargetRegisterClass *SystemZGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
832 static constexpr uint8_t Table[24][8] = {
833 { // VR16Bit
834 0, // VR16Bit:subreg_h16
835 0, // VR16Bit:subreg_h32
836 0, // VR16Bit:subreg_h64
837 0, // VR16Bit:subreg_l32
838 0, // VR16Bit:subreg_l64
839 0, // VR16Bit:subreg_lh32
840 0, // VR16Bit:subreg_ll32
841 0, // VR16Bit:subreg_lh32_then_subreg_h16
842 },
843 { // FP16Bit
844 0, // FP16Bit:subreg_h16
845 0, // FP16Bit:subreg_h32
846 0, // FP16Bit:subreg_h64
847 0, // FP16Bit:subreg_l32
848 0, // FP16Bit:subreg_l64
849 0, // FP16Bit:subreg_lh32
850 0, // FP16Bit:subreg_ll32
851 0, // FP16Bit:subreg_lh32_then_subreg_h16
852 },
853 { // GRX32Bit
854 0, // GRX32Bit:subreg_h16
855 0, // GRX32Bit:subreg_h32
856 0, // GRX32Bit:subreg_h64
857 0, // GRX32Bit:subreg_l32
858 0, // GRX32Bit:subreg_l64
859 0, // GRX32Bit:subreg_lh32
860 0, // GRX32Bit:subreg_ll32
861 0, // GRX32Bit:subreg_lh32_then_subreg_h16
862 },
863 { // VR32Bit
864 1, // VR32Bit:subreg_h16 -> VR16Bit
865 0, // VR32Bit:subreg_h32
866 0, // VR32Bit:subreg_h64
867 0, // VR32Bit:subreg_l32
868 0, // VR32Bit:subreg_l64
869 0, // VR32Bit:subreg_lh32
870 0, // VR32Bit:subreg_ll32
871 0, // VR32Bit:subreg_lh32_then_subreg_h16
872 },
873 { // AR32Bit
874 0, // AR32Bit:subreg_h16
875 0, // AR32Bit:subreg_h32
876 0, // AR32Bit:subreg_h64
877 0, // AR32Bit:subreg_l32
878 0, // AR32Bit:subreg_l64
879 0, // AR32Bit:subreg_lh32
880 0, // AR32Bit:subreg_ll32
881 0, // AR32Bit:subreg_lh32_then_subreg_h16
882 },
883 { // FP32Bit
884 2, // FP32Bit:subreg_h16 -> FP16Bit
885 0, // FP32Bit:subreg_h32
886 0, // FP32Bit:subreg_h64
887 0, // FP32Bit:subreg_l32
888 0, // FP32Bit:subreg_l64
889 0, // FP32Bit:subreg_lh32
890 0, // FP32Bit:subreg_ll32
891 0, // FP32Bit:subreg_lh32_then_subreg_h16
892 },
893 { // GR32Bit
894 0, // GR32Bit:subreg_h16
895 0, // GR32Bit:subreg_h32
896 0, // GR32Bit:subreg_h64
897 0, // GR32Bit:subreg_l32
898 0, // GR32Bit:subreg_l64
899 0, // GR32Bit:subreg_lh32
900 0, // GR32Bit:subreg_ll32
901 0, // GR32Bit:subreg_lh32_then_subreg_h16
902 },
903 { // GRH32Bit
904 0, // GRH32Bit:subreg_h16
905 0, // GRH32Bit:subreg_h32
906 0, // GRH32Bit:subreg_h64
907 0, // GRH32Bit:subreg_l32
908 0, // GRH32Bit:subreg_l64
909 0, // GRH32Bit:subreg_lh32
910 0, // GRH32Bit:subreg_ll32
911 0, // GRH32Bit:subreg_lh32_then_subreg_h16
912 },
913 { // ADDR32Bit
914 0, // ADDR32Bit:subreg_h16
915 0, // ADDR32Bit:subreg_h32
916 0, // ADDR32Bit:subreg_h64
917 0, // ADDR32Bit:subreg_l32
918 0, // ADDR32Bit:subreg_l64
919 0, // ADDR32Bit:subreg_lh32
920 0, // ADDR32Bit:subreg_ll32
921 0, // ADDR32Bit:subreg_lh32_then_subreg_h16
922 },
923 { // CCR
924 0, // CCR:subreg_h16
925 0, // CCR:subreg_h32
926 0, // CCR:subreg_h64
927 0, // CCR:subreg_l32
928 0, // CCR:subreg_l64
929 0, // CCR:subreg_lh32
930 0, // CCR:subreg_ll32
931 0, // CCR:subreg_lh32_then_subreg_h16
932 },
933 { // FPCRegs
934 0, // FPCRegs:subreg_h16
935 0, // FPCRegs:subreg_h32
936 0, // FPCRegs:subreg_h64
937 0, // FPCRegs:subreg_l32
938 0, // FPCRegs:subreg_l64
939 0, // FPCRegs:subreg_lh32
940 0, // FPCRegs:subreg_ll32
941 0, // FPCRegs:subreg_lh32_then_subreg_h16
942 },
943 { // AnyRegBit
944 1, // AnyRegBit:subreg_h16 -> VR16Bit
945 4, // AnyRegBit:subreg_h32 -> VR32Bit
946 17, // AnyRegBit:subreg_h64 -> FP64Bit
947 7, // AnyRegBit:subreg_l32 -> GR32Bit
948 0, // AnyRegBit:subreg_l64
949 0, // AnyRegBit:subreg_lh32
950 0, // AnyRegBit:subreg_ll32
951 0, // AnyRegBit:subreg_lh32_then_subreg_h16
952 },
953 { // AnyRegBit_with_subreg_h16
954 1, // AnyRegBit_with_subreg_h16:subreg_h16 -> VR16Bit
955 4, // AnyRegBit_with_subreg_h16:subreg_h32 -> VR32Bit
956 17, // AnyRegBit_with_subreg_h16:subreg_h64 -> FP64Bit
957 0, // AnyRegBit_with_subreg_h16:subreg_l32
958 0, // AnyRegBit_with_subreg_h16:subreg_l64
959 0, // AnyRegBit_with_subreg_h16:subreg_lh32
960 0, // AnyRegBit_with_subreg_h16:subreg_ll32
961 0, // AnyRegBit_with_subreg_h16:subreg_lh32_then_subreg_h16
962 },
963 { // VR64Bit
964 1, // VR64Bit:subreg_h16 -> VR16Bit
965 4, // VR64Bit:subreg_h32 -> VR32Bit
966 0, // VR64Bit:subreg_h64
967 0, // VR64Bit:subreg_l32
968 0, // VR64Bit:subreg_l64
969 0, // VR64Bit:subreg_lh32
970 0, // VR64Bit:subreg_ll32
971 0, // VR64Bit:subreg_lh32_then_subreg_h16
972 },
973 { // AnyRegBit_with_subreg_h64
974 2, // AnyRegBit_with_subreg_h64:subreg_h16 -> FP16Bit
975 6, // AnyRegBit_with_subreg_h64:subreg_h32 -> FP32Bit
976 17, // AnyRegBit_with_subreg_h64:subreg_h64 -> FP64Bit
977 0, // AnyRegBit_with_subreg_h64:subreg_l32
978 0, // AnyRegBit_with_subreg_h64:subreg_l64
979 0, // AnyRegBit_with_subreg_h64:subreg_lh32
980 0, // AnyRegBit_with_subreg_h64:subreg_ll32
981 0, // AnyRegBit_with_subreg_h64:subreg_lh32_then_subreg_h16
982 },
983 { // CR64Bit
984 0, // CR64Bit:subreg_h16
985 0, // CR64Bit:subreg_h32
986 0, // CR64Bit:subreg_h64
987 0, // CR64Bit:subreg_l32
988 0, // CR64Bit:subreg_l64
989 0, // CR64Bit:subreg_lh32
990 0, // CR64Bit:subreg_ll32
991 0, // CR64Bit:subreg_lh32_then_subreg_h16
992 },
993 { // FP64Bit
994 2, // FP64Bit:subreg_h16 -> FP16Bit
995 6, // FP64Bit:subreg_h32 -> FP32Bit
996 0, // FP64Bit:subreg_h64
997 0, // FP64Bit:subreg_l32
998 0, // FP64Bit:subreg_l64
999 0, // FP64Bit:subreg_lh32
1000 0, // FP64Bit:subreg_ll32
1001 0, // FP64Bit:subreg_lh32_then_subreg_h16
1002 },
1003 { // GR64Bit
1004 0, // GR64Bit:subreg_h16
1005 8, // GR64Bit:subreg_h32 -> GRH32Bit
1006 0, // GR64Bit:subreg_h64
1007 7, // GR64Bit:subreg_l32 -> GR32Bit
1008 0, // GR64Bit:subreg_l64
1009 0, // GR64Bit:subreg_lh32
1010 0, // GR64Bit:subreg_ll32
1011 0, // GR64Bit:subreg_lh32_then_subreg_h16
1012 },
1013 { // ADDR64Bit
1014 0, // ADDR64Bit:subreg_h16
1015 8, // ADDR64Bit:subreg_h32 -> GRH32Bit
1016 0, // ADDR64Bit:subreg_h64
1017 9, // ADDR64Bit:subreg_l32 -> ADDR32Bit
1018 0, // ADDR64Bit:subreg_l64
1019 0, // ADDR64Bit:subreg_lh32
1020 0, // ADDR64Bit:subreg_ll32
1021 0, // ADDR64Bit:subreg_lh32_then_subreg_h16
1022 },
1023 { // VR128Bit
1024 1, // VR128Bit:subreg_h16 -> VR16Bit
1025 4, // VR128Bit:subreg_h32 -> VR32Bit
1026 14, // VR128Bit:subreg_h64 -> VR64Bit
1027 0, // VR128Bit:subreg_l32
1028 0, // VR128Bit:subreg_l64
1029 0, // VR128Bit:subreg_lh32
1030 0, // VR128Bit:subreg_ll32
1031 0, // VR128Bit:subreg_lh32_then_subreg_h16
1032 },
1033 { // VF128Bit
1034 2, // VF128Bit:subreg_h16 -> FP16Bit
1035 6, // VF128Bit:subreg_h32 -> FP32Bit
1036 17, // VF128Bit:subreg_h64 -> FP64Bit
1037 0, // VF128Bit:subreg_l32
1038 0, // VF128Bit:subreg_l64
1039 0, // VF128Bit:subreg_lh32
1040 0, // VF128Bit:subreg_ll32
1041 0, // VF128Bit:subreg_lh32_then_subreg_h16
1042 },
1043 { // FP128Bit
1044 2, // FP128Bit:subreg_h16 -> FP16Bit
1045 6, // FP128Bit:subreg_h32 -> FP32Bit
1046 17, // FP128Bit:subreg_h64 -> FP64Bit
1047 0, // FP128Bit:subreg_l32
1048 17, // FP128Bit:subreg_l64 -> FP64Bit
1049 6, // FP128Bit:subreg_lh32 -> FP32Bit
1050 0, // FP128Bit:subreg_ll32
1051 2, // FP128Bit:subreg_lh32_then_subreg_h16 -> FP16Bit
1052 },
1053 { // GR128Bit
1054 0, // GR128Bit:subreg_h16
1055 8, // GR128Bit:subreg_h32 -> GRH32Bit
1056 18, // GR128Bit:subreg_h64 -> GR64Bit
1057 7, // GR128Bit:subreg_l32 -> GR32Bit
1058 19, // GR128Bit:subreg_l64 -> ADDR64Bit
1059 8, // GR128Bit:subreg_lh32 -> GRH32Bit
1060 9, // GR128Bit:subreg_ll32 -> ADDR32Bit
1061 0, // GR128Bit:subreg_lh32_then_subreg_h16
1062 },
1063 { // ADDR128Bit
1064 0, // ADDR128Bit:subreg_h16
1065 8, // ADDR128Bit:subreg_h32 -> GRH32Bit
1066 19, // ADDR128Bit:subreg_h64 -> ADDR64Bit
1067 9, // ADDR128Bit:subreg_l32 -> ADDR32Bit
1068 19, // ADDR128Bit:subreg_l64 -> ADDR64Bit
1069 8, // ADDR128Bit:subreg_lh32 -> GRH32Bit
1070 9, // ADDR128Bit:subreg_ll32 -> ADDR32Bit
1071 0, // ADDR128Bit:subreg_lh32_then_subreg_h16
1072 },
1073
1074 };
1075 assert(RC && "Missing regclass");
1076 if (!Idx) return RC;
1077 --Idx;
1078 assert(Idx < 8 && "Bad subreg");
1079 unsigned TV = Table[RC->getID()][Idx];
1080 return TV ? getRegClass(i: TV - 1) : nullptr;
1081}/// Get the weight in units of pressure for this register class.
1082const RegClassWeight &SystemZGenRegisterInfo::
1083getRegClassWeight(const TargetRegisterClass *RC) const {
1084 static const RegClassWeight RCWeightTable[] = {
1085 {.RegWeight: 1, .WeightLimit: 32}, // VR16Bit
1086 {.RegWeight: 1, .WeightLimit: 16}, // FP16Bit
1087 {.RegWeight: 1, .WeightLimit: 32}, // GRX32Bit
1088 {.RegWeight: 1, .WeightLimit: 32}, // VR32Bit
1089 {.RegWeight: 0, .WeightLimit: 0}, // AR32Bit
1090 {.RegWeight: 1, .WeightLimit: 16}, // FP32Bit
1091 {.RegWeight: 1, .WeightLimit: 16}, // GR32Bit
1092 {.RegWeight: 1, .WeightLimit: 16}, // GRH32Bit
1093 {.RegWeight: 1, .WeightLimit: 15}, // ADDR32Bit
1094 {.RegWeight: 0, .WeightLimit: 0}, // CCR
1095 {.RegWeight: 0, .WeightLimit: 0}, // FPCRegs
1096 {.RegWeight: 1, .WeightLimit: 48}, // AnyRegBit
1097 {.RegWeight: 1, .WeightLimit: 16}, // AnyRegBit_with_subreg_h16
1098 {.RegWeight: 1, .WeightLimit: 32}, // VR64Bit
1099 {.RegWeight: 1, .WeightLimit: 16}, // AnyRegBit_with_subreg_h64
1100 {.RegWeight: 0, .WeightLimit: 0}, // CR64Bit
1101 {.RegWeight: 1, .WeightLimit: 16}, // FP64Bit
1102 {.RegWeight: 2, .WeightLimit: 32}, // GR64Bit
1103 {.RegWeight: 2, .WeightLimit: 30}, // ADDR64Bit
1104 {.RegWeight: 1, .WeightLimit: 32}, // VR128Bit
1105 {.RegWeight: 1, .WeightLimit: 16}, // VF128Bit
1106 {.RegWeight: 2, .WeightLimit: 16}, // FP128Bit
1107 {.RegWeight: 4, .WeightLimit: 32}, // GR128Bit
1108 {.RegWeight: 4, .WeightLimit: 28}, // ADDR128Bit
1109 };
1110 return RCWeightTable[RC->getID()];
1111}
1112
1113/// Get the weight in units of pressure for this register unit.
1114unsigned SystemZGenRegisterInfo::
1115getRegUnitWeight(MCRegUnit RegUnit) const {
1116 assert(static_cast<unsigned>(RegUnit) < 98 && "invalid register unit");
1117 // All register units have unit weight.
1118 return 1;
1119}
1120
1121
1122// Get the number of dimensions of register pressure.
1123unsigned SystemZGenRegisterInfo::getNumRegPressureSets() const {
1124 return 5;
1125}
1126
1127// Get the name of this register unit pressure set.
1128const char *SystemZGenRegisterInfo::
1129getRegPressureSetName(unsigned Idx) const {
1130 static const char *PressureNameTable[] = {
1131 "FP16Bit",
1132 "GR32Bit",
1133 "GRH32Bit",
1134 "VR16Bit",
1135 "GRX32Bit",
1136 };
1137 return PressureNameTable[Idx];
1138}
1139
1140// Get the register unit pressure limit for this dimension.
1141// This limit must be adjusted dynamically for reserved registers.
1142unsigned SystemZGenRegisterInfo::
1143getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1144 static const uint8_t PressureLimitTable[] = {
1145 16, // 0: FP16Bit
1146 16, // 1: GR32Bit
1147 16, // 2: GRH32Bit
1148 32, // 3: VR16Bit
1149 32, // 4: GRX32Bit
1150 };
1151 return PressureLimitTable[Idx];
1152}
1153
1154/// Table of pressure sets per register class or unit.
1155static const int RCSetsTable[] = {
1156 /* 0 */ 0, 3, -1,
1157 /* 3 */ 1, 4, -1,
1158 /* 6 */ 2, 4, -1,
1159};
1160
1161/// Get the dimensions of register pressure impacted by this register class.
1162/// Returns a -1 terminated array of pressure set IDs
1163const int *SystemZGenRegisterInfo::
1164getRegClassPressureSets(const TargetRegisterClass *RC) const {
1165 static const uint8_t RCSetStartTable[] = {
1166 1,0,4,1,2,0,3,6,3,2,2,2,2,1,2,2,0,4,4,1,0,0,4,4,};
1167 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1168}
1169
1170/// Get the dimensions of register pressure impacted by this register unit.
1171/// Returns a -1 terminated array of pressure set IDs
1172const int *SystemZGenRegisterInfo::
1173getRegUnitPressureSets(MCRegUnit RegUnit) const {
1174 assert(static_cast<unsigned>(RegUnit) < 98 && "invalid register unit");
1175 static const uint8_t RUSetStartTable[] = {
1176 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,};
1177 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1178}
1179
1180ArrayRef<MCPhysReg> SystemZGenRegisterInfo::getRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) const {
1181 switch (RC.getID()) {
1182 case SystemZ::VR16BitRegClassID:
1183 return VR16BitGetRawAllocationOrder(RC, MF, Rev);
1184 case SystemZ::FP16BitRegClassID:
1185 return FP16BitGetRawAllocationOrder(RC, MF, Rev);
1186 case SystemZ::GRX32BitRegClassID:
1187 return GRX32BitGetRawAllocationOrder(RC, MF, Rev);
1188 case SystemZ::VR32BitRegClassID:
1189 return VR32BitGetRawAllocationOrder(RC, MF, Rev);
1190 case SystemZ::AR32BitRegClassID:
1191 return AR32BitGetRawAllocationOrder(RC, MF, Rev);
1192 case SystemZ::FP32BitRegClassID:
1193 return FP32BitGetRawAllocationOrder(RC, MF, Rev);
1194 case SystemZ::GR32BitRegClassID:
1195 return GR32BitGetRawAllocationOrder(RC, MF, Rev);
1196 case SystemZ::GRH32BitRegClassID:
1197 return GRH32BitGetRawAllocationOrder(RC, MF, Rev);
1198 case SystemZ::ADDR32BitRegClassID:
1199 return ADDR32BitGetRawAllocationOrder(RC, MF, Rev);
1200 case SystemZ::AnyRegBitRegClassID:
1201 return AnyRegBitGetRawAllocationOrder(RC, MF, Rev);
1202 case SystemZ::AnyRegBit_with_subreg_h16RegClassID:
1203 return AnyRegBit_with_subreg_h16GetRawAllocationOrder(RC, MF, Rev);
1204 case SystemZ::VR64BitRegClassID:
1205 return VR64BitGetRawAllocationOrder(RC, MF, Rev);
1206 case SystemZ::AnyRegBit_with_subreg_h64RegClassID:
1207 return AnyRegBit_with_subreg_h64GetRawAllocationOrder(RC, MF, Rev);
1208 case SystemZ::CR64BitRegClassID:
1209 return CR64BitGetRawAllocationOrder(RC, MF, Rev);
1210 case SystemZ::FP64BitRegClassID:
1211 return FP64BitGetRawAllocationOrder(RC, MF, Rev);
1212 case SystemZ::GR64BitRegClassID:
1213 return GR64BitGetRawAllocationOrder(RC, MF, Rev);
1214 case SystemZ::ADDR64BitRegClassID:
1215 return ADDR64BitGetRawAllocationOrder(RC, MF, Rev);
1216 case SystemZ::VR128BitRegClassID:
1217 return VR128BitGetRawAllocationOrder(RC, MF, Rev);
1218 case SystemZ::VF128BitRegClassID:
1219 return VF128BitGetRawAllocationOrder(RC, MF, Rev);
1220 case SystemZ::FP128BitRegClassID:
1221 return FP128BitGetRawAllocationOrder(RC, MF, Rev);
1222 case SystemZ::GR128BitRegClassID:
1223 return GR128BitGetRawAllocationOrder(RC, MF, Rev);
1224 case SystemZ::ADDR128BitRegClassID:
1225 return ADDR128BitGetRawAllocationOrder(RC, MF, Rev);
1226 }
1227 return RC.getRegisters();
1228}
1229
1230
1231// Register to minimal register class mapping
1232
1233const TargetRegisterClass *SystemZGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
1234 static const uint16_t InvalidRegClassID = UINT16_MAX;
1235
1236 static const uint16_t Mapping[227] = {
1237 InvalidRegClassID, // NoRegister
1238 SystemZ::CCRRegClassID, // CC
1239 SystemZ::FPCRegsRegClassID, // FPC
1240 SystemZ::AR32BitRegClassID, // A0
1241 SystemZ::AR32BitRegClassID, // A1
1242 SystemZ::AR32BitRegClassID, // A2
1243 SystemZ::AR32BitRegClassID, // A3
1244 SystemZ::AR32BitRegClassID, // A4
1245 SystemZ::AR32BitRegClassID, // A5
1246 SystemZ::AR32BitRegClassID, // A6
1247 SystemZ::AR32BitRegClassID, // A7
1248 SystemZ::AR32BitRegClassID, // A8
1249 SystemZ::AR32BitRegClassID, // A9
1250 SystemZ::AR32BitRegClassID, // A10
1251 SystemZ::AR32BitRegClassID, // A11
1252 SystemZ::AR32BitRegClassID, // A12
1253 SystemZ::AR32BitRegClassID, // A13
1254 SystemZ::AR32BitRegClassID, // A14
1255 SystemZ::AR32BitRegClassID, // A15
1256 SystemZ::CR64BitRegClassID, // C0
1257 SystemZ::CR64BitRegClassID, // C1
1258 SystemZ::CR64BitRegClassID, // C2
1259 SystemZ::CR64BitRegClassID, // C3
1260 SystemZ::CR64BitRegClassID, // C4
1261 SystemZ::CR64BitRegClassID, // C5
1262 SystemZ::CR64BitRegClassID, // C6
1263 SystemZ::CR64BitRegClassID, // C7
1264 SystemZ::CR64BitRegClassID, // C8
1265 SystemZ::CR64BitRegClassID, // C9
1266 SystemZ::CR64BitRegClassID, // C10
1267 SystemZ::CR64BitRegClassID, // C11
1268 SystemZ::CR64BitRegClassID, // C12
1269 SystemZ::CR64BitRegClassID, // C13
1270 SystemZ::CR64BitRegClassID, // C14
1271 SystemZ::CR64BitRegClassID, // C15
1272 SystemZ::VF128BitRegClassID, // V0
1273 SystemZ::VF128BitRegClassID, // V1
1274 SystemZ::VF128BitRegClassID, // V2
1275 SystemZ::VF128BitRegClassID, // V3
1276 SystemZ::VF128BitRegClassID, // V4
1277 SystemZ::VF128BitRegClassID, // V5
1278 SystemZ::VF128BitRegClassID, // V6
1279 SystemZ::VF128BitRegClassID, // V7
1280 SystemZ::VF128BitRegClassID, // V8
1281 SystemZ::VF128BitRegClassID, // V9
1282 SystemZ::VF128BitRegClassID, // V10
1283 SystemZ::VF128BitRegClassID, // V11
1284 SystemZ::VF128BitRegClassID, // V12
1285 SystemZ::VF128BitRegClassID, // V13
1286 SystemZ::VF128BitRegClassID, // V14
1287 SystemZ::VF128BitRegClassID, // V15
1288 SystemZ::VR128BitRegClassID, // V16
1289 SystemZ::VR128BitRegClassID, // V17
1290 SystemZ::VR128BitRegClassID, // V18
1291 SystemZ::VR128BitRegClassID, // V19
1292 SystemZ::VR128BitRegClassID, // V20
1293 SystemZ::VR128BitRegClassID, // V21
1294 SystemZ::VR128BitRegClassID, // V22
1295 SystemZ::VR128BitRegClassID, // V23
1296 SystemZ::VR128BitRegClassID, // V24
1297 SystemZ::VR128BitRegClassID, // V25
1298 SystemZ::VR128BitRegClassID, // V26
1299 SystemZ::VR128BitRegClassID, // V27
1300 SystemZ::VR128BitRegClassID, // V28
1301 SystemZ::VR128BitRegClassID, // V29
1302 SystemZ::VR128BitRegClassID, // V30
1303 SystemZ::VR128BitRegClassID, // V31
1304 SystemZ::FP64BitRegClassID, // F0D
1305 SystemZ::FP64BitRegClassID, // F1D
1306 SystemZ::FP64BitRegClassID, // F2D
1307 SystemZ::FP64BitRegClassID, // F3D
1308 SystemZ::FP64BitRegClassID, // F4D
1309 SystemZ::FP64BitRegClassID, // F5D
1310 SystemZ::FP64BitRegClassID, // F6D
1311 SystemZ::FP64BitRegClassID, // F7D
1312 SystemZ::FP64BitRegClassID, // F8D
1313 SystemZ::FP64BitRegClassID, // F9D
1314 SystemZ::FP64BitRegClassID, // F10D
1315 SystemZ::FP64BitRegClassID, // F11D
1316 SystemZ::FP64BitRegClassID, // F12D
1317 SystemZ::FP64BitRegClassID, // F13D
1318 SystemZ::FP64BitRegClassID, // F14D
1319 SystemZ::FP64BitRegClassID, // F15D
1320 SystemZ::VR64BitRegClassID, // F16D
1321 SystemZ::VR64BitRegClassID, // F17D
1322 SystemZ::VR64BitRegClassID, // F18D
1323 SystemZ::VR64BitRegClassID, // F19D
1324 SystemZ::VR64BitRegClassID, // F20D
1325 SystemZ::VR64BitRegClassID, // F21D
1326 SystemZ::VR64BitRegClassID, // F22D
1327 SystemZ::VR64BitRegClassID, // F23D
1328 SystemZ::VR64BitRegClassID, // F24D
1329 SystemZ::VR64BitRegClassID, // F25D
1330 SystemZ::VR64BitRegClassID, // F26D
1331 SystemZ::VR64BitRegClassID, // F27D
1332 SystemZ::VR64BitRegClassID, // F28D
1333 SystemZ::VR64BitRegClassID, // F29D
1334 SystemZ::VR64BitRegClassID, // F30D
1335 SystemZ::VR64BitRegClassID, // F31D
1336 SystemZ::FP16BitRegClassID, // F0H
1337 SystemZ::FP16BitRegClassID, // F1H
1338 SystemZ::FP16BitRegClassID, // F2H
1339 SystemZ::FP16BitRegClassID, // F3H
1340 SystemZ::FP16BitRegClassID, // F4H
1341 SystemZ::FP16BitRegClassID, // F5H
1342 SystemZ::FP16BitRegClassID, // F6H
1343 SystemZ::FP16BitRegClassID, // F7H
1344 SystemZ::FP16BitRegClassID, // F8H
1345 SystemZ::FP16BitRegClassID, // F9H
1346 SystemZ::FP16BitRegClassID, // F10H
1347 SystemZ::FP16BitRegClassID, // F11H
1348 SystemZ::FP16BitRegClassID, // F12H
1349 SystemZ::FP16BitRegClassID, // F13H
1350 SystemZ::FP16BitRegClassID, // F14H
1351 SystemZ::FP16BitRegClassID, // F15H
1352 SystemZ::VR16BitRegClassID, // F16H
1353 SystemZ::VR16BitRegClassID, // F17H
1354 SystemZ::VR16BitRegClassID, // F18H
1355 SystemZ::VR16BitRegClassID, // F19H
1356 SystemZ::VR16BitRegClassID, // F20H
1357 SystemZ::VR16BitRegClassID, // F21H
1358 SystemZ::VR16BitRegClassID, // F22H
1359 SystemZ::VR16BitRegClassID, // F23H
1360 SystemZ::VR16BitRegClassID, // F24H
1361 SystemZ::VR16BitRegClassID, // F25H
1362 SystemZ::VR16BitRegClassID, // F26H
1363 SystemZ::VR16BitRegClassID, // F27H
1364 SystemZ::VR16BitRegClassID, // F28H
1365 SystemZ::VR16BitRegClassID, // F29H
1366 SystemZ::VR16BitRegClassID, // F30H
1367 SystemZ::VR16BitRegClassID, // F31H
1368 SystemZ::FP128BitRegClassID, // F0Q
1369 SystemZ::FP128BitRegClassID, // F1Q
1370 SystemZ::FP128BitRegClassID, // F4Q
1371 SystemZ::FP128BitRegClassID, // F5Q
1372 SystemZ::FP128BitRegClassID, // F8Q
1373 SystemZ::FP128BitRegClassID, // F9Q
1374 SystemZ::FP128BitRegClassID, // F12Q
1375 SystemZ::FP128BitRegClassID, // F13Q
1376 SystemZ::FP32BitRegClassID, // F0S
1377 SystemZ::FP32BitRegClassID, // F1S
1378 SystemZ::FP32BitRegClassID, // F2S
1379 SystemZ::FP32BitRegClassID, // F3S
1380 SystemZ::FP32BitRegClassID, // F4S
1381 SystemZ::FP32BitRegClassID, // F5S
1382 SystemZ::FP32BitRegClassID, // F6S
1383 SystemZ::FP32BitRegClassID, // F7S
1384 SystemZ::FP32BitRegClassID, // F8S
1385 SystemZ::FP32BitRegClassID, // F9S
1386 SystemZ::FP32BitRegClassID, // F10S
1387 SystemZ::FP32BitRegClassID, // F11S
1388 SystemZ::FP32BitRegClassID, // F12S
1389 SystemZ::FP32BitRegClassID, // F13S
1390 SystemZ::FP32BitRegClassID, // F14S
1391 SystemZ::FP32BitRegClassID, // F15S
1392 SystemZ::VR32BitRegClassID, // F16S
1393 SystemZ::VR32BitRegClassID, // F17S
1394 SystemZ::VR32BitRegClassID, // F18S
1395 SystemZ::VR32BitRegClassID, // F19S
1396 SystemZ::VR32BitRegClassID, // F20S
1397 SystemZ::VR32BitRegClassID, // F21S
1398 SystemZ::VR32BitRegClassID, // F22S
1399 SystemZ::VR32BitRegClassID, // F23S
1400 SystemZ::VR32BitRegClassID, // F24S
1401 SystemZ::VR32BitRegClassID, // F25S
1402 SystemZ::VR32BitRegClassID, // F26S
1403 SystemZ::VR32BitRegClassID, // F27S
1404 SystemZ::VR32BitRegClassID, // F28S
1405 SystemZ::VR32BitRegClassID, // F29S
1406 SystemZ::VR32BitRegClassID, // F30S
1407 SystemZ::VR32BitRegClassID, // F31S
1408 SystemZ::GR64BitRegClassID, // R0D
1409 SystemZ::ADDR64BitRegClassID, // R1D
1410 SystemZ::ADDR64BitRegClassID, // R2D
1411 SystemZ::ADDR64BitRegClassID, // R3D
1412 SystemZ::ADDR64BitRegClassID, // R4D
1413 SystemZ::ADDR64BitRegClassID, // R5D
1414 SystemZ::ADDR64BitRegClassID, // R6D
1415 SystemZ::ADDR64BitRegClassID, // R7D
1416 SystemZ::ADDR64BitRegClassID, // R8D
1417 SystemZ::ADDR64BitRegClassID, // R9D
1418 SystemZ::ADDR64BitRegClassID, // R10D
1419 SystemZ::ADDR64BitRegClassID, // R11D
1420 SystemZ::ADDR64BitRegClassID, // R12D
1421 SystemZ::ADDR64BitRegClassID, // R13D
1422 SystemZ::ADDR64BitRegClassID, // R14D
1423 SystemZ::ADDR64BitRegClassID, // R15D
1424 SystemZ::GRH32BitRegClassID, // R0H
1425 SystemZ::GRH32BitRegClassID, // R1H
1426 SystemZ::GRH32BitRegClassID, // R2H
1427 SystemZ::GRH32BitRegClassID, // R3H
1428 SystemZ::GRH32BitRegClassID, // R4H
1429 SystemZ::GRH32BitRegClassID, // R5H
1430 SystemZ::GRH32BitRegClassID, // R6H
1431 SystemZ::GRH32BitRegClassID, // R7H
1432 SystemZ::GRH32BitRegClassID, // R8H
1433 SystemZ::GRH32BitRegClassID, // R9H
1434 SystemZ::GRH32BitRegClassID, // R10H
1435 SystemZ::GRH32BitRegClassID, // R11H
1436 SystemZ::GRH32BitRegClassID, // R12H
1437 SystemZ::GRH32BitRegClassID, // R13H
1438 SystemZ::GRH32BitRegClassID, // R14H
1439 SystemZ::GRH32BitRegClassID, // R15H
1440 SystemZ::GR32BitRegClassID, // R0L
1441 SystemZ::ADDR32BitRegClassID, // R1L
1442 SystemZ::ADDR32BitRegClassID, // R2L
1443 SystemZ::ADDR32BitRegClassID, // R3L
1444 SystemZ::ADDR32BitRegClassID, // R4L
1445 SystemZ::ADDR32BitRegClassID, // R5L
1446 SystemZ::ADDR32BitRegClassID, // R6L
1447 SystemZ::ADDR32BitRegClassID, // R7L
1448 SystemZ::ADDR32BitRegClassID, // R8L
1449 SystemZ::ADDR32BitRegClassID, // R9L
1450 SystemZ::ADDR32BitRegClassID, // R10L
1451 SystemZ::ADDR32BitRegClassID, // R11L
1452 SystemZ::ADDR32BitRegClassID, // R12L
1453 SystemZ::ADDR32BitRegClassID, // R13L
1454 SystemZ::ADDR32BitRegClassID, // R14L
1455 SystemZ::ADDR32BitRegClassID, // R15L
1456 SystemZ::GR128BitRegClassID, // R0Q
1457 SystemZ::ADDR128BitRegClassID, // R2Q
1458 SystemZ::ADDR128BitRegClassID, // R4Q
1459 SystemZ::ADDR128BitRegClassID, // R6Q
1460 SystemZ::ADDR128BitRegClassID, // R8Q
1461 SystemZ::ADDR128BitRegClassID, // R10Q
1462 SystemZ::ADDR128BitRegClassID, // R12Q
1463 SystemZ::ADDR128BitRegClassID, // R14Q
1464 };
1465
1466 assert(Reg < ArrayRef(Mapping).size());
1467 unsigned RCID = Mapping[Reg.id()];
1468 if (RCID == InvalidRegClassID)
1469 return nullptr;
1470 return &SystemZMCRegisterClassStorage.Classes[RCID];
1471}
1472extern const MCRegisterDesc SystemZRegDesc[];
1473extern const int16_t SystemZRegDiffLists[];
1474extern const LaneBitmask SystemZLaneMaskLists[];
1475extern const char SystemZRegStrings[];
1476extern const char SystemZRegClassStrings[];
1477extern const MCPhysReg SystemZRegUnitRoots[][2];
1478extern const uint16_t SystemZSubRegIdxLists[];
1479extern const uint16_t SystemZRegEncodingTable[];
1480// SystemZ Dwarf<->LLVM register mappings.
1481extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[];
1482extern const unsigned SystemZDwarfFlavour0Dwarf2LSize;
1483
1484extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[];
1485extern const unsigned SystemZEHFlavour0Dwarf2LSize;
1486
1487extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[];
1488extern const unsigned SystemZDwarfFlavour0L2DwarfSize;
1489
1490extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[];
1491extern const unsigned SystemZEHFlavour0L2DwarfSize;
1492
1493
1494SystemZGenRegisterInfo::
1495SystemZGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1496 unsigned PC, unsigned HwMode)
1497 : TargetRegisterInfo(&SystemZRegInfoDesc,
1498 SystemZSubRegIndexStrings, SystemZSubRegIndexNameOffsets,
1499 SystemZSubRegIdxRangeTable, SystemZSubRegIndexLaneMaskTable,
1500
1501 LaneBitmask(0xFFFFFFFFFFFFFFFC), SystemZRegClassInfos, SystemZVTLists, HwMode) {
1502 InitMCRegisterInfo(D: SystemZRegDesc, NR: 227, RA, PC,
1503 C: &getSystemZMCRegisterClass(RC: 0), NC: 24, RURoots: SystemZRegUnitRoots, NRU: 98, DL: SystemZRegDiffLists,
1504 RUMS: SystemZLaneMaskLists, Strings: SystemZRegStrings, ClassStrings: SystemZRegClassStrings, SubIndices: SystemZSubRegIdxLists, NumIndices: 9,
1505 RET: SystemZRegEncodingTable, RUI: nullptr);
1506
1507 switch (DwarfFlavour) {
1508 default:
1509 llvm_unreachable("Unknown DWARF flavour");
1510 case 0:
1511 mapDwarfRegsToLLVMRegs(Map: SystemZDwarfFlavour0Dwarf2L, Size: SystemZDwarfFlavour0Dwarf2LSize, isEH: false);
1512 break;
1513 }
1514 switch (EHFlavour) {
1515 default:
1516 llvm_unreachable("Unknown DWARF flavour");
1517 case 0:
1518 mapDwarfRegsToLLVMRegs(Map: SystemZEHFlavour0Dwarf2L, Size: SystemZEHFlavour0Dwarf2LSize, isEH: true);
1519 break;
1520 }
1521 switch (DwarfFlavour) {
1522 default:
1523 llvm_unreachable("Unknown DWARF flavour");
1524 case 0:
1525 mapLLVMRegsToDwarfRegs(Map: SystemZDwarfFlavour0L2Dwarf, Size: SystemZDwarfFlavour0L2DwarfSize, isEH: false);
1526 break;
1527 }
1528 switch (EHFlavour) {
1529 default:
1530 llvm_unreachable("Unknown DWARF flavour");
1531 case 0:
1532 mapLLVMRegsToDwarfRegs(Map: SystemZEHFlavour0L2Dwarf, Size: SystemZEHFlavour0L2DwarfSize, isEH: true);
1533 break;
1534 }
1535}
1536
1537static const MCPhysReg CSR_SystemZ_AllRegs_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
1538static const uint32_t CSR_SystemZ_AllRegs_RegMask[] = { 0x00000000, 0x00000000, 0x0007fff8, 0x0007fff8, 0x07fffff8, 0xe7ffe000, 0xf7ffe7ff, 0x00000007, };
1539static const MCPhysReg CSR_SystemZ_AllRegs_Vector_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, 0 };
1540static const uint32_t CSR_SystemZ_AllRegs_Vector_RegMask[] = { 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xffffffff, 0xe7ffe7ff, 0xf7ffe7ff, 0x00000007, };
1541static const MCPhysReg CSR_SystemZ_ELF_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
1542static const uint32_t CSR_SystemZ_ELF_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07fe0000, 0xc7fe07fe, 0x00000007, };
1543static const MCPhysReg CSR_SystemZ_NoRegs_SaveList[] = { 0 };
1544static const uint32_t CSR_SystemZ_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
1545static const MCPhysReg CSR_SystemZ_SwiftError_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
1546static const uint32_t CSR_SystemZ_SwiftError_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07ee0000, 0x47ee07ee, 0x00000007, };
1547static const MCPhysReg CSR_SystemZ_XPLINK64_SaveList[] = { SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F15D, SystemZ::F14D, SystemZ::F13D, SystemZ::F12D, SystemZ::F11D, SystemZ::F10D, SystemZ::F9D, SystemZ::F8D, 0 };
1548static const uint32_t CSR_SystemZ_XPLINK64_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07f80000, 0x87f807f8, 0x00000007, };
1549static const MCPhysReg CSR_SystemZ_XPLINK64_Vector_SaveList[] = { SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F15D, SystemZ::F14D, SystemZ::F13D, SystemZ::F12D, SystemZ::F11D, SystemZ::F10D, SystemZ::F9D, SystemZ::F8D, SystemZ::V23, SystemZ::V22, SystemZ::V21, SystemZ::V20, SystemZ::V19, SystemZ::V18, SystemZ::V17, SystemZ::V16, 0 };
1550static const uint32_t CSR_SystemZ_XPLINK64_Vector_RegMask[] = { 0x00000000, 0x07f80000, 0x07fff800, 0x07fff800, 0xfff80780, 0x07f80007, 0x87f807f8, 0x00000007, };
1551
1552
1553ArrayRef<const uint32_t *> SystemZGenRegisterInfo::getRegMasks() const {
1554 static const uint32_t *const Masks[] = {
1555 CSR_SystemZ_AllRegs_RegMask,
1556 CSR_SystemZ_AllRegs_Vector_RegMask,
1557 CSR_SystemZ_ELF_RegMask,
1558 CSR_SystemZ_NoRegs_RegMask,
1559 CSR_SystemZ_SwiftError_RegMask,
1560 CSR_SystemZ_XPLINK64_RegMask,
1561 CSR_SystemZ_XPLINK64_Vector_RegMask,
1562 };
1563 return ArrayRef(Masks);
1564}
1565
1566bool SystemZGenRegisterInfo::
1567isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1568 return
1569 false;
1570}
1571
1572bool SystemZGenRegisterInfo::
1573isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1574 return
1575 false;
1576}
1577
1578bool SystemZGenRegisterInfo::
1579isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1580 return
1581 false;
1582}
1583
1584bool SystemZGenRegisterInfo::
1585isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1586 return
1587 false;
1588}
1589
1590bool SystemZGenRegisterInfo::
1591isConstantPhysReg(MCRegister PhysReg) const {
1592 return
1593 false;
1594}
1595
1596ArrayRef<const char *> SystemZGenRegisterInfo::getRegMaskNames() const {
1597 static const char *Names[] = {
1598 "CSR_SystemZ_AllRegs",
1599 "CSR_SystemZ_AllRegs_Vector",
1600 "CSR_SystemZ_ELF",
1601 "CSR_SystemZ_NoRegs",
1602 "CSR_SystemZ_SwiftError",
1603 "CSR_SystemZ_XPLINK64",
1604 "CSR_SystemZ_XPLINK64_Vector",
1605 };
1606 return ArrayRef(Names);
1607}
1608
1609const SystemZFrameLowering *
1610SystemZGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1611 return static_cast<const SystemZFrameLowering *>(
1612 MF.getSubtarget().getFrameLowering());
1613}
1614
1615
1616} // namespace llvm
1617