1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass SystemZMCRegisterClasses[];
12
13static const MVT::SimpleValueType SystemZVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f16, MVT::Other,
17 /* 6 */ MVT::f32, MVT::Other,
18 /* 8 */ MVT::f64, MVT::Other,
19 /* 10 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::i128, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
20 /* 20 */ MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
21 /* 24 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v2f32, MVT::Other,
22 /* 31 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::Other,
23 /* 39 */ MVT::Untyped, MVT::Other,
24};
25
26#ifdef __GNUC__
27#pragma GCC diagnostic push
28#pragma GCC diagnostic ignored "-Woverlength-strings"
29#endif
30static constexpr char SystemZSubRegIndexStrings[] = {
31 /* 0 */ "subreg_h32\000"
32 /* 11 */ "subreg_lh32\000"
33 /* 23 */ "subreg_l32\000"
34 /* 34 */ "subreg_ll32\000"
35 /* 46 */ "subreg_h64\000"
36 /* 57 */ "subreg_l64\000"
37 /* 68 */ "subreg_lh32_then_subreg_h16\000"
38};
39#ifdef __GNUC__
40#pragma GCC diagnostic pop
41#endif
42
43
44static constexpr uint32_t SystemZSubRegIndexNameOffsets[] = {
45 85,
46 0,
47 46,
48 23,
49 57,
50 11,
51 34,
52 68,
53};
54
55static const TargetRegisterInfo::SubRegCoveredBits SystemZSubRegIdxRangeTable[] = {
56 { .Offset: 4294967295, .Size: 4294967295 },
57 { .Offset: 16, .Size: 16 }, // subreg_h16
58 { .Offset: 32, .Size: 32 }, // subreg_h32
59 { .Offset: 64, .Size: 64 }, // subreg_h64
60 { .Offset: 0, .Size: 32 }, // subreg_l32
61 { .Offset: 0, .Size: 64 }, // subreg_l64
62 { .Offset: 32, .Size: 32 }, // subreg_lh32
63 { .Offset: 0, .Size: 32 }, // subreg_ll32
64 { .Offset: 48, .Size: 16 }, // subreg_lh32_then_subreg_h16
65 { .Offset: 4294967295, .Size: 4294967295 },
66 { .Offset: 16, .Size: 16 }, // subreg_h16
67 { .Offset: 32, .Size: 32 }, // subreg_h32
68 { .Offset: 64, .Size: 64 }, // subreg_h64
69 { .Offset: 0, .Size: 32 }, // subreg_l32
70 { .Offset: 0, .Size: 64 }, // subreg_l64
71 { .Offset: 32, .Size: 32 }, // subreg_lh32
72 { .Offset: 0, .Size: 32 }, // subreg_ll32
73 { .Offset: 48, .Size: 16 }, // subreg_lh32_then_subreg_h16
74};
75
76
77static const LaneBitmask SystemZSubRegIndexLaneMaskTable[] = {
78 LaneBitmask::getAll(),
79 LaneBitmask(0x0000000000000001), // subreg_h16
80 LaneBitmask(0x0000000000000001), // subreg_h32
81 LaneBitmask(0x0000000000000003), // subreg_h64
82 LaneBitmask(0x0000000000000002), // subreg_l32
83 LaneBitmask(0x000000000000000C), // subreg_l64
84 LaneBitmask(0x0000000000000008), // subreg_lh32
85 LaneBitmask(0x0000000000000004), // subreg_ll32
86 LaneBitmask(0x0000000000000008), // subreg_lh32_then_subreg_h16
87 };
88
89
90
91static const TargetRegisterInfo::RegClassInfo SystemZRegClassInfos[] = {
92 // Mode = 0 (DefaultMode)
93 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*SystemZVTLists+*/.VTListOffset: 4 }, // VR16Bit
94 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*SystemZVTLists+*/.VTListOffset: 4 }, // FP16Bit
95 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // GRX32Bit
96 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 20 }, // VR32Bit
97 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // AR32Bit
98 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 6 }, // FP32Bit
99 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // GR32Bit
100 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // GRH32Bit
101 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // ADDR32Bit
102 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // CCR
103 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // FPCRegs
104 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 24 }, // AnyRegBit
105 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h16
106 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 25 }, // VR64Bit
107 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h64
108 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 2 }, // CR64Bit
109 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 8 }, // FP64Bit
110 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 2 }, // GR64Bit
111 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 2 }, // ADDR64Bit
112 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 10 }, // VR128Bit
113 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 31 }, // VF128Bit
114 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 18 }, // FP128Bit
115 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 39 }, // GR128Bit
116 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 39 }, // ADDR128Bit
117 // Mode = 1 (NoVecHwMode)
118 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*SystemZVTLists+*/.VTListOffset: 4 }, // VR16Bit
119 { .RegSize: 16, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 4 }, // FP16Bit
120 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // GRX32Bit
121 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 20 }, // VR32Bit
122 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // AR32Bit
123 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 6 }, // FP32Bit
124 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // GR32Bit
125 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // GRH32Bit
126 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // ADDR32Bit
127 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // CCR
128 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SystemZVTLists+*/.VTListOffset: 0 }, // FPCRegs
129 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 24 }, // AnyRegBit
130 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h16
131 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 25 }, // VR64Bit
132 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 24 }, // AnyRegBit_with_subreg_h64
133 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 2 }, // CR64Bit
134 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 8 }, // FP64Bit
135 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 2 }, // GR64Bit
136 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SystemZVTLists+*/.VTListOffset: 2 }, // ADDR64Bit
137 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 10 }, // VR128Bit
138 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 31 }, // VF128Bit
139 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 18 }, // FP128Bit
140 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 39 }, // GR128Bit
141 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SystemZVTLists+*/.VTListOffset: 39 }, // ADDR128Bit
142};
143static const uint32_t VR16BitSubClassMask[] = {
144 0x00000003,
145 0x00397028, // subreg_h16
146 0x00200000, // subreg_lh32_then_subreg_h16
147};
148
149static const uint32_t FP16BitSubClassMask[] = {
150 0x00000002,
151 0x00315020, // subreg_h16
152 0x00200000, // subreg_lh32_then_subreg_h16
153};
154
155static const uint32_t GRX32BitSubClassMask[] = {
156 0x000001c4,
157 0x00c60000, // subreg_h32
158 0x00c60000, // subreg_l32
159 0x00c00000, // subreg_lh32
160 0x00c00000, // subreg_ll32
161};
162
163static const uint32_t VR32BitSubClassMask[] = {
164 0x00000028,
165 0x00397000, // subreg_h32
166 0x00200000, // subreg_lh32
167};
168
169static const uint32_t AR32BitSubClassMask[] = {
170 0x00000010,
171};
172
173static const uint32_t FP32BitSubClassMask[] = {
174 0x00000020,
175 0x00315000, // subreg_h32
176 0x00200000, // subreg_lh32
177};
178
179static const uint32_t GR32BitSubClassMask[] = {
180 0x00000140,
181 0x00c60000, // subreg_l32
182 0x00c00000, // subreg_ll32
183};
184
185static const uint32_t GRH32BitSubClassMask[] = {
186 0x00000080,
187 0x00c60000, // subreg_h32
188 0x00c00000, // subreg_lh32
189};
190
191static const uint32_t ADDR32BitSubClassMask[] = {
192 0x00000100,
193 0x00840000, // subreg_l32
194 0x00c00000, // subreg_ll32
195};
196
197static const uint32_t CCRSubClassMask[] = {
198 0x00000200,
199};
200
201static const uint32_t FPCRegsSubClassMask[] = {
202 0x00000400,
203};
204
205static const uint32_t AnyRegBitSubClassMask[] = {
206 0x00175800,
207 0x00f04000, // subreg_h64
208 0x00e00000, // subreg_l64
209};
210
211static const uint32_t AnyRegBit_with_subreg_h16SubClassMask[] = {
212 0x00115000,
213 0x00304000, // subreg_h64
214 0x00200000, // subreg_l64
215};
216
217static const uint32_t VR64BitSubClassMask[] = {
218 0x00012000,
219 0x00384000, // subreg_h64
220 0x00200000, // subreg_l64
221};
222
223static const uint32_t AnyRegBit_with_subreg_h64SubClassMask[] = {
224 0x00104000,
225};
226
227static const uint32_t CR64BitSubClassMask[] = {
228 0x00008000,
229};
230
231static const uint32_t FP64BitSubClassMask[] = {
232 0x00010000,
233 0x00304000, // subreg_h64
234 0x00200000, // subreg_l64
235};
236
237static const uint32_t GR64BitSubClassMask[] = {
238 0x00060000,
239 0x00c00000, // subreg_h64
240 0x00c00000, // subreg_l64
241};
242
243static const uint32_t ADDR64BitSubClassMask[] = {
244 0x00040000,
245 0x00800000, // subreg_h64
246 0x00c00000, // subreg_l64
247};
248
249static const uint32_t VR128BitSubClassMask[] = {
250 0x00180000,
251};
252
253static const uint32_t VF128BitSubClassMask[] = {
254 0x00100000,
255};
256
257static const uint32_t FP128BitSubClassMask[] = {
258 0x00200000,
259};
260
261static const uint32_t GR128BitSubClassMask[] = {
262 0x00c00000,
263};
264
265static const uint32_t ADDR128BitSubClassMask[] = {
266 0x00800000,
267};
268
269static const uint16_t SuperRegIdxSeqs[] = {
270 /* 0 */ 3, 5, 0,
271 /* 3 */ 2, 6, 0,
272 /* 6 */ 4, 7, 0,
273 /* 9 */ 2, 4, 6, 7, 0,
274 /* 14 */ 1, 8, 0,
275};
276
277static unsigned const FP16BitSuperclasses[] = {
278 SystemZ::VR16BitRegClassID,
279};
280
281static unsigned const FP32BitSuperclasses[] = {
282 SystemZ::VR32BitRegClassID,
283};
284
285static unsigned const GR32BitSuperclasses[] = {
286 SystemZ::GRX32BitRegClassID,
287};
288
289static unsigned const GRH32BitSuperclasses[] = {
290 SystemZ::GRX32BitRegClassID,
291};
292
293static unsigned const ADDR32BitSuperclasses[] = {
294 SystemZ::GRX32BitRegClassID,
295 SystemZ::GR32BitRegClassID,
296};
297
298static unsigned const AnyRegBit_with_subreg_h16Superclasses[] = {
299 SystemZ::AnyRegBitRegClassID,
300};
301
302static unsigned const AnyRegBit_with_subreg_h64Superclasses[] = {
303 SystemZ::AnyRegBitRegClassID,
304 SystemZ::AnyRegBit_with_subreg_h16RegClassID,
305};
306
307static unsigned const FP64BitSuperclasses[] = {
308 SystemZ::AnyRegBitRegClassID,
309 SystemZ::AnyRegBit_with_subreg_h16RegClassID,
310 SystemZ::VR64BitRegClassID,
311};
312
313static unsigned const GR64BitSuperclasses[] = {
314 SystemZ::AnyRegBitRegClassID,
315};
316
317static unsigned const ADDR64BitSuperclasses[] = {
318 SystemZ::AnyRegBitRegClassID,
319 SystemZ::GR64BitRegClassID,
320};
321
322static unsigned const VF128BitSuperclasses[] = {
323 SystemZ::AnyRegBitRegClassID,
324 SystemZ::AnyRegBit_with_subreg_h16RegClassID,
325 SystemZ::AnyRegBit_with_subreg_h64RegClassID,
326 SystemZ::VR128BitRegClassID,
327};
328
329static unsigned const ADDR128BitSuperclasses[] = {
330 SystemZ::GR128BitRegClassID,
331};
332
333
334static inline unsigned VR16BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
335 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
336 return S.isTargetXPLINK64();
337 }
338
339static ArrayRef<MCPhysReg> VR16BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
340 static const MCPhysReg AltOrder1[] = { SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F16H, SystemZ::F17H, SystemZ::F18H, SystemZ::F19H, SystemZ::F20H, SystemZ::F21H, SystemZ::F22H, SystemZ::F23H, SystemZ::F24H, SystemZ::F25H, SystemZ::F26H, SystemZ::F27H, SystemZ::F28H, SystemZ::F29H, SystemZ::F30H, SystemZ::F31H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H };
341 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR16BitRegClassID];
342 const ArrayRef<MCPhysReg> Order[] = {
343 ArrayRef(MCR.begin(), MCR.getNumRegs()),
344 ArrayRef(AltOrder1)
345 };
346 const unsigned Select = VR16BitAltOrderSelect(MF, Rev);
347 assert(Select < 2);
348 return Order[Select];
349}
350
351static inline unsigned FP16BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
352 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
353 return S.isTargetXPLINK64();
354 }
355
356static ArrayRef<MCPhysReg> FP16BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
357 static const MCPhysReg AltOrder1[] = { SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H };
358 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP16BitRegClassID];
359 const ArrayRef<MCPhysReg> Order[] = {
360 ArrayRef(MCR.begin(), MCR.getNumRegs()),
361 ArrayRef(AltOrder1)
362 };
363 const unsigned Select = FP16BitAltOrderSelect(MF, Rev);
364 assert(Select < 2);
365 return Order[Select];
366}
367
368static inline unsigned GRX32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
369 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
370 return S.isTargetXPLINK64();
371 }
372
373static ArrayRef<MCPhysReg> GRX32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
374 static const MCPhysReg AltOrder1[] = { SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4L, SystemZ::R4H, SystemZ::R5L, SystemZ::R5H, SystemZ::R6L, SystemZ::R6H, SystemZ::R7L, SystemZ::R7H, SystemZ::R8L, SystemZ::R8H, SystemZ::R9L, SystemZ::R9H, SystemZ::R10L, SystemZ::R10H, SystemZ::R11L, SystemZ::R11H, SystemZ::R12L, SystemZ::R12H, SystemZ::R13L, SystemZ::R13H, SystemZ::R14L, SystemZ::R14H, SystemZ::R15L, SystemZ::R15H };
375 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GRX32BitRegClassID];
376 const ArrayRef<MCPhysReg> Order[] = {
377 ArrayRef(MCR.begin(), MCR.getNumRegs()),
378 ArrayRef(AltOrder1)
379 };
380 const unsigned Select = GRX32BitAltOrderSelect(MF, Rev);
381 assert(Select < 2);
382 return Order[Select];
383}
384
385static inline unsigned VR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
386 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
387 return S.isTargetXPLINK64();
388 }
389
390static ArrayRef<MCPhysReg> VR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
391 static const MCPhysReg AltOrder1[] = { SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
392 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR32BitRegClassID];
393 const ArrayRef<MCPhysReg> Order[] = {
394 ArrayRef(MCR.begin(), MCR.getNumRegs()),
395 ArrayRef(AltOrder1)
396 };
397 const unsigned Select = VR32BitAltOrderSelect(MF, Rev);
398 assert(Select < 2);
399 return Order[Select];
400}
401
402static inline unsigned AR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
403 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
404 return S.isTargetXPLINK64();
405 }
406
407static ArrayRef<MCPhysReg> AR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
408 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AR32BitRegClassID];
409 const ArrayRef<MCPhysReg> Order[] = {
410 ArrayRef(MCR.begin(), MCR.getNumRegs())
411 };
412 const unsigned Select = AR32BitAltOrderSelect(MF, Rev);
413 assert(Select < 1);
414 return Order[Select];
415}
416
417static inline unsigned FP32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
418 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
419 return S.isTargetXPLINK64();
420 }
421
422static ArrayRef<MCPhysReg> FP32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
423 static const MCPhysReg AltOrder1[] = { SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
424 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP32BitRegClassID];
425 const ArrayRef<MCPhysReg> Order[] = {
426 ArrayRef(MCR.begin(), MCR.getNumRegs()),
427 ArrayRef(AltOrder1)
428 };
429 const unsigned Select = FP32BitAltOrderSelect(MF, Rev);
430 assert(Select < 2);
431 return Order[Select];
432}
433
434static inline unsigned GR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
435 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
436 return S.isTargetXPLINK64();
437 }
438
439static ArrayRef<MCPhysReg> GR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
440 static const MCPhysReg AltOrder1[] = { SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L };
441 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR32BitRegClassID];
442 const ArrayRef<MCPhysReg> Order[] = {
443 ArrayRef(MCR.begin(), MCR.getNumRegs()),
444 ArrayRef(AltOrder1)
445 };
446 const unsigned Select = GR32BitAltOrderSelect(MF, Rev);
447 assert(Select < 2);
448 return Order[Select];
449}
450
451static inline unsigned GRH32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
452 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
453 return S.isTargetXPLINK64();
454 }
455
456static ArrayRef<MCPhysReg> GRH32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
457 static const MCPhysReg AltOrder1[] = { SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H, SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H, SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H };
458 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GRH32BitRegClassID];
459 const ArrayRef<MCPhysReg> Order[] = {
460 ArrayRef(MCR.begin(), MCR.getNumRegs()),
461 ArrayRef(AltOrder1)
462 };
463 const unsigned Select = GRH32BitAltOrderSelect(MF, Rev);
464 assert(Select < 2);
465 return Order[Select];
466}
467
468static inline unsigned ADDR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
469 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
470 return S.isTargetXPLINK64();
471 }
472
473static ArrayRef<MCPhysReg> ADDR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
474 static const MCPhysReg AltOrder1[] = { SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L };
475 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR32BitRegClassID];
476 const ArrayRef<MCPhysReg> Order[] = {
477 ArrayRef(MCR.begin(), MCR.getNumRegs()),
478 ArrayRef(AltOrder1)
479 };
480 const unsigned Select = ADDR32BitAltOrderSelect(MF, Rev);
481 assert(Select < 2);
482 return Order[Select];
483}
484
485static inline unsigned AnyRegBitAltOrderSelect(const MachineFunction &MF, bool Rev) {
486 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
487 return S.isTargetXPLINK64();
488 }
489
490static ArrayRef<MCPhysReg> AnyRegBitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
491 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBitRegClassID];
492 const ArrayRef<MCPhysReg> Order[] = {
493 ArrayRef(MCR.begin(), MCR.getNumRegs())
494 };
495 const unsigned Select = AnyRegBitAltOrderSelect(MF, Rev);
496 assert(Select < 1);
497 return Order[Select];
498}
499
500static inline unsigned AnyRegBit_with_subreg_h16AltOrderSelect(const MachineFunction &MF, bool Rev) {
501 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
502 return S.isTargetXPLINK64();
503 }
504
505static ArrayRef<MCPhysReg> AnyRegBit_with_subreg_h16GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
506 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBit_with_subreg_h16RegClassID];
507 const ArrayRef<MCPhysReg> Order[] = {
508 ArrayRef(MCR.begin(), MCR.getNumRegs())
509 };
510 const unsigned Select = AnyRegBit_with_subreg_h16AltOrderSelect(MF, Rev);
511 assert(Select < 1);
512 return Order[Select];
513}
514
515static inline unsigned VR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
516 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
517 return S.isTargetXPLINK64();
518 }
519
520static ArrayRef<MCPhysReg> VR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
521 static const MCPhysReg AltOrder1[] = { SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D };
522 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR64BitRegClassID];
523 const ArrayRef<MCPhysReg> Order[] = {
524 ArrayRef(MCR.begin(), MCR.getNumRegs()),
525 ArrayRef(AltOrder1)
526 };
527 const unsigned Select = VR64BitAltOrderSelect(MF, Rev);
528 assert(Select < 2);
529 return Order[Select];
530}
531
532static inline unsigned AnyRegBit_with_subreg_h64AltOrderSelect(const MachineFunction &MF, bool Rev) {
533 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
534 return S.isTargetXPLINK64();
535 }
536
537static ArrayRef<MCPhysReg> AnyRegBit_with_subreg_h64GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
538 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBit_with_subreg_h64RegClassID];
539 const ArrayRef<MCPhysReg> Order[] = {
540 ArrayRef(MCR.begin(), MCR.getNumRegs())
541 };
542 const unsigned Select = AnyRegBit_with_subreg_h64AltOrderSelect(MF, Rev);
543 assert(Select < 1);
544 return Order[Select];
545}
546
547static inline unsigned CR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
548 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
549 return S.isTargetXPLINK64();
550 }
551
552static ArrayRef<MCPhysReg> CR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
553 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::CR64BitRegClassID];
554 const ArrayRef<MCPhysReg> Order[] = {
555 ArrayRef(MCR.begin(), MCR.getNumRegs())
556 };
557 const unsigned Select = CR64BitAltOrderSelect(MF, Rev);
558 assert(Select < 1);
559 return Order[Select];
560}
561
562static inline unsigned FP64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
563 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
564 return S.isTargetXPLINK64();
565 }
566
567static ArrayRef<MCPhysReg> FP64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
568 static const MCPhysReg AltOrder1[] = { SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D };
569 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP64BitRegClassID];
570 const ArrayRef<MCPhysReg> Order[] = {
571 ArrayRef(MCR.begin(), MCR.getNumRegs()),
572 ArrayRef(AltOrder1)
573 };
574 const unsigned Select = FP64BitAltOrderSelect(MF, Rev);
575 assert(Select < 2);
576 return Order[Select];
577}
578
579static inline unsigned GR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
580 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
581 return S.isTargetXPLINK64();
582 }
583
584static ArrayRef<MCPhysReg> GR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
585 static const MCPhysReg AltOrder1[] = { SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D };
586 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR64BitRegClassID];
587 const ArrayRef<MCPhysReg> Order[] = {
588 ArrayRef(MCR.begin(), MCR.getNumRegs()),
589 ArrayRef(AltOrder1)
590 };
591 const unsigned Select = GR64BitAltOrderSelect(MF, Rev);
592 assert(Select < 2);
593 return Order[Select];
594}
595
596static inline unsigned ADDR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
597 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
598 return S.isTargetXPLINK64();
599 }
600
601static ArrayRef<MCPhysReg> ADDR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
602 static const MCPhysReg AltOrder1[] = { SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D };
603 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR64BitRegClassID];
604 const ArrayRef<MCPhysReg> Order[] = {
605 ArrayRef(MCR.begin(), MCR.getNumRegs()),
606 ArrayRef(AltOrder1)
607 };
608 const unsigned Select = ADDR64BitAltOrderSelect(MF, Rev);
609 assert(Select < 2);
610 return Order[Select];
611}
612
613static inline unsigned VR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
614 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
615 return S.isTargetXPLINK64();
616 }
617
618static ArrayRef<MCPhysReg> VR128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
619 static const MCPhysReg AltOrder1[] = { SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15 };
620 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR128BitRegClassID];
621 const ArrayRef<MCPhysReg> Order[] = {
622 ArrayRef(MCR.begin(), MCR.getNumRegs()),
623 ArrayRef(AltOrder1)
624 };
625 const unsigned Select = VR128BitAltOrderSelect(MF, Rev);
626 assert(Select < 2);
627 return Order[Select];
628}
629
630static inline unsigned VF128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
631 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
632 return S.isTargetXPLINK64();
633 }
634
635static ArrayRef<MCPhysReg> VF128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
636 static const MCPhysReg AltOrder1[] = { SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15 };
637 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VF128BitRegClassID];
638 const ArrayRef<MCPhysReg> Order[] = {
639 ArrayRef(MCR.begin(), MCR.getNumRegs()),
640 ArrayRef(AltOrder1)
641 };
642 const unsigned Select = VF128BitAltOrderSelect(MF, Rev);
643 assert(Select < 2);
644 return Order[Select];
645}
646
647static inline unsigned FP128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
648 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
649 return S.isTargetXPLINK64();
650 }
651
652static ArrayRef<MCPhysReg> FP128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
653 static const MCPhysReg AltOrder1[] = { SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q };
654 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP128BitRegClassID];
655 const ArrayRef<MCPhysReg> Order[] = {
656 ArrayRef(MCR.begin(), MCR.getNumRegs()),
657 ArrayRef(AltOrder1)
658 };
659 const unsigned Select = FP128BitAltOrderSelect(MF, Rev);
660 assert(Select < 2);
661 return Order[Select];
662}
663
664static inline unsigned GR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
665 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
666 return S.isTargetXPLINK64();
667 }
668
669static ArrayRef<MCPhysReg> GR128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
670 static const MCPhysReg AltOrder1[] = { SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R6Q, SystemZ::R8Q, SystemZ::R10Q, SystemZ::R12Q, SystemZ::R14Q };
671 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR128BitRegClassID];
672 const ArrayRef<MCPhysReg> Order[] = {
673 ArrayRef(MCR.begin(), MCR.getNumRegs()),
674 ArrayRef(AltOrder1)
675 };
676 const unsigned Select = GR128BitAltOrderSelect(MF, Rev);
677 assert(Select < 2);
678 return Order[Select];
679}
680
681static inline unsigned ADDR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
682 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
683 return S.isTargetXPLINK64();
684 }
685
686static ArrayRef<MCPhysReg> ADDR128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
687 static const MCPhysReg AltOrder1[] = { SystemZ::R2Q, SystemZ::R4Q, SystemZ::R6Q, SystemZ::R8Q, SystemZ::R10Q, SystemZ::R12Q, SystemZ::R14Q };
688 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR128BitRegClassID];
689 const ArrayRef<MCPhysReg> Order[] = {
690 ArrayRef(MCR.begin(), MCR.getNumRegs()),
691 ArrayRef(AltOrder1)
692 };
693 const unsigned Select = ADDR128BitAltOrderSelect(MF, Rev);
694 assert(Select < 2);
695 return Order[Select];
696}
697namespace SystemZ {
698
699// Register class instances.
700 extern const TargetRegisterClass VR16BitRegClass = {
701 .MC: &SystemZMCRegisterClasses[VR16BitRegClassID],
702 .SubClassMask: VR16BitSubClassMask,
703 .SuperRegIndices: SuperRegIdxSeqs + 14,
704 .LaneMask: LaneBitmask(0x0000000000000001),
705 .AllocationPriority: 0,
706 .GlobalPriority: false,
707 .TSFlags: 0x00, /* TSFlags */
708 .SpillStackID: 0, /* SpillStackID */
709 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
710 .CoveredBySubRegs: false, /* CoveredBySubRegs */
711 .SuperClasses: nullptr, .SuperClassesSize: 0,
712 .OrderFunc: VR16BitGetRawAllocationOrder
713 };
714
715 extern const TargetRegisterClass FP16BitRegClass = {
716 .MC: &SystemZMCRegisterClasses[FP16BitRegClassID],
717 .SubClassMask: FP16BitSubClassMask,
718 .SuperRegIndices: SuperRegIdxSeqs + 14,
719 .LaneMask: LaneBitmask(0x0000000000000001),
720 .AllocationPriority: 0,
721 .GlobalPriority: false,
722 .TSFlags: 0x00, /* TSFlags */
723 .SpillStackID: 0, /* SpillStackID */
724 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
725 .CoveredBySubRegs: false, /* CoveredBySubRegs */
726 .SuperClasses: FP16BitSuperclasses, .SuperClassesSize: 1,
727 .OrderFunc: FP16BitGetRawAllocationOrder
728 };
729
730 extern const TargetRegisterClass GRX32BitRegClass = {
731 .MC: &SystemZMCRegisterClasses[GRX32BitRegClassID],
732 .SubClassMask: GRX32BitSubClassMask,
733 .SuperRegIndices: SuperRegIdxSeqs + 9,
734 .LaneMask: LaneBitmask(0x0000000000000001),
735 .AllocationPriority: 0,
736 .GlobalPriority: false,
737 .TSFlags: 0x00, /* TSFlags */
738 .SpillStackID: 0, /* SpillStackID */
739 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
740 .CoveredBySubRegs: false, /* CoveredBySubRegs */
741 .SuperClasses: nullptr, .SuperClassesSize: 0,
742 .OrderFunc: GRX32BitGetRawAllocationOrder
743 };
744
745 extern const TargetRegisterClass VR32BitRegClass = {
746 .MC: &SystemZMCRegisterClasses[VR32BitRegClassID],
747 .SubClassMask: VR32BitSubClassMask,
748 .SuperRegIndices: SuperRegIdxSeqs + 3,
749 .LaneMask: LaneBitmask(0x0000000000000001),
750 .AllocationPriority: 0,
751 .GlobalPriority: false,
752 .TSFlags: 0x00, /* TSFlags */
753 .SpillStackID: 0, /* SpillStackID */
754 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
755 .CoveredBySubRegs: false, /* CoveredBySubRegs */
756 .SuperClasses: nullptr, .SuperClassesSize: 0,
757 .OrderFunc: VR32BitGetRawAllocationOrder
758 };
759
760 extern const TargetRegisterClass AR32BitRegClass = {
761 .MC: &SystemZMCRegisterClasses[AR32BitRegClassID],
762 .SubClassMask: AR32BitSubClassMask,
763 .SuperRegIndices: SuperRegIdxSeqs + 2,
764 .LaneMask: LaneBitmask(0x0000000000000001),
765 .AllocationPriority: 0,
766 .GlobalPriority: false,
767 .TSFlags: 0x00, /* TSFlags */
768 .SpillStackID: 0, /* SpillStackID */
769 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
770 .CoveredBySubRegs: false, /* CoveredBySubRegs */
771 .SuperClasses: nullptr, .SuperClassesSize: 0,
772 .OrderFunc: AR32BitGetRawAllocationOrder
773 };
774
775 extern const TargetRegisterClass FP32BitRegClass = {
776 .MC: &SystemZMCRegisterClasses[FP32BitRegClassID],
777 .SubClassMask: FP32BitSubClassMask,
778 .SuperRegIndices: SuperRegIdxSeqs + 3,
779 .LaneMask: LaneBitmask(0x0000000000000001),
780 .AllocationPriority: 0,
781 .GlobalPriority: false,
782 .TSFlags: 0x00, /* TSFlags */
783 .SpillStackID: 0, /* SpillStackID */
784 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
785 .CoveredBySubRegs: false, /* CoveredBySubRegs */
786 .SuperClasses: FP32BitSuperclasses, .SuperClassesSize: 1,
787 .OrderFunc: FP32BitGetRawAllocationOrder
788 };
789
790 extern const TargetRegisterClass GR32BitRegClass = {
791 .MC: &SystemZMCRegisterClasses[GR32BitRegClassID],
792 .SubClassMask: GR32BitSubClassMask,
793 .SuperRegIndices: SuperRegIdxSeqs + 6,
794 .LaneMask: LaneBitmask(0x0000000000000001),
795 .AllocationPriority: 0,
796 .GlobalPriority: false,
797 .TSFlags: 0x00, /* TSFlags */
798 .SpillStackID: 0, /* SpillStackID */
799 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
800 .CoveredBySubRegs: false, /* CoveredBySubRegs */
801 .SuperClasses: GR32BitSuperclasses, .SuperClassesSize: 1,
802 .OrderFunc: GR32BitGetRawAllocationOrder
803 };
804
805 extern const TargetRegisterClass GRH32BitRegClass = {
806 .MC: &SystemZMCRegisterClasses[GRH32BitRegClassID],
807 .SubClassMask: GRH32BitSubClassMask,
808 .SuperRegIndices: SuperRegIdxSeqs + 3,
809 .LaneMask: LaneBitmask(0x0000000000000001),
810 .AllocationPriority: 0,
811 .GlobalPriority: false,
812 .TSFlags: 0x00, /* TSFlags */
813 .SpillStackID: 0, /* SpillStackID */
814 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
815 .CoveredBySubRegs: false, /* CoveredBySubRegs */
816 .SuperClasses: GRH32BitSuperclasses, .SuperClassesSize: 1,
817 .OrderFunc: GRH32BitGetRawAllocationOrder
818 };
819
820 extern const TargetRegisterClass ADDR32BitRegClass = {
821 .MC: &SystemZMCRegisterClasses[ADDR32BitRegClassID],
822 .SubClassMask: ADDR32BitSubClassMask,
823 .SuperRegIndices: SuperRegIdxSeqs + 6,
824 .LaneMask: LaneBitmask(0x0000000000000001),
825 .AllocationPriority: 0,
826 .GlobalPriority: false,
827 .TSFlags: 0x00, /* TSFlags */
828 .SpillStackID: 0, /* SpillStackID */
829 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
830 .CoveredBySubRegs: false, /* CoveredBySubRegs */
831 .SuperClasses: ADDR32BitSuperclasses, .SuperClassesSize: 2,
832 .OrderFunc: ADDR32BitGetRawAllocationOrder
833 };
834
835 extern const TargetRegisterClass CCRRegClass = {
836 .MC: &SystemZMCRegisterClasses[CCRRegClassID],
837 .SubClassMask: CCRSubClassMask,
838 .SuperRegIndices: SuperRegIdxSeqs + 2,
839 .LaneMask: LaneBitmask(0x0000000000000001),
840 .AllocationPriority: 0,
841 .GlobalPriority: false,
842 .TSFlags: 0x00, /* TSFlags */
843 .SpillStackID: 0, /* SpillStackID */
844 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
845 .CoveredBySubRegs: false, /* CoveredBySubRegs */
846 .SuperClasses: nullptr, .SuperClassesSize: 0,
847 .OrderFunc: nullptr
848 };
849
850 extern const TargetRegisterClass FPCRegsRegClass = {
851 .MC: &SystemZMCRegisterClasses[FPCRegsRegClassID],
852 .SubClassMask: FPCRegsSubClassMask,
853 .SuperRegIndices: SuperRegIdxSeqs + 2,
854 .LaneMask: LaneBitmask(0x0000000000000001),
855 .AllocationPriority: 0,
856 .GlobalPriority: false,
857 .TSFlags: 0x00, /* TSFlags */
858 .SpillStackID: 0, /* SpillStackID */
859 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
860 .CoveredBySubRegs: false, /* CoveredBySubRegs */
861 .SuperClasses: nullptr, .SuperClassesSize: 0,
862 .OrderFunc: nullptr
863 };
864
865 extern const TargetRegisterClass AnyRegBitRegClass = {
866 .MC: &SystemZMCRegisterClasses[AnyRegBitRegClassID],
867 .SubClassMask: AnyRegBitSubClassMask,
868 .SuperRegIndices: SuperRegIdxSeqs + 0,
869 .LaneMask: LaneBitmask(0x0000000000000003),
870 .AllocationPriority: 0,
871 .GlobalPriority: false,
872 .TSFlags: 0x00, /* TSFlags */
873 .SpillStackID: 0, /* SpillStackID */
874 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
875 .CoveredBySubRegs: false, /* CoveredBySubRegs */
876 .SuperClasses: nullptr, .SuperClassesSize: 0,
877 .OrderFunc: AnyRegBitGetRawAllocationOrder
878 };
879
880 extern const TargetRegisterClass AnyRegBit_with_subreg_h16RegClass = {
881 .MC: &SystemZMCRegisterClasses[AnyRegBit_with_subreg_h16RegClassID],
882 .SubClassMask: AnyRegBit_with_subreg_h16SubClassMask,
883 .SuperRegIndices: SuperRegIdxSeqs + 0,
884 .LaneMask: LaneBitmask(0x0000000000000003),
885 .AllocationPriority: 0,
886 .GlobalPriority: false,
887 .TSFlags: 0x00, /* TSFlags */
888 .SpillStackID: 0, /* SpillStackID */
889 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
890 .CoveredBySubRegs: false, /* CoveredBySubRegs */
891 .SuperClasses: AnyRegBit_with_subreg_h16Superclasses, .SuperClassesSize: 1,
892 .OrderFunc: AnyRegBit_with_subreg_h16GetRawAllocationOrder
893 };
894
895 extern const TargetRegisterClass VR64BitRegClass = {
896 .MC: &SystemZMCRegisterClasses[VR64BitRegClassID],
897 .SubClassMask: VR64BitSubClassMask,
898 .SuperRegIndices: SuperRegIdxSeqs + 0,
899 .LaneMask: LaneBitmask(0x0000000000000001),
900 .AllocationPriority: 0,
901 .GlobalPriority: false,
902 .TSFlags: 0x00, /* TSFlags */
903 .SpillStackID: 0, /* SpillStackID */
904 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
905 .CoveredBySubRegs: false, /* CoveredBySubRegs */
906 .SuperClasses: nullptr, .SuperClassesSize: 0,
907 .OrderFunc: VR64BitGetRawAllocationOrder
908 };
909
910 extern const TargetRegisterClass AnyRegBit_with_subreg_h64RegClass = {
911 .MC: &SystemZMCRegisterClasses[AnyRegBit_with_subreg_h64RegClassID],
912 .SubClassMask: AnyRegBit_with_subreg_h64SubClassMask,
913 .SuperRegIndices: SuperRegIdxSeqs + 2,
914 .LaneMask: LaneBitmask(0x0000000000000003),
915 .AllocationPriority: 0,
916 .GlobalPriority: false,
917 .TSFlags: 0x00, /* TSFlags */
918 .SpillStackID: 0, /* SpillStackID */
919 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
920 .CoveredBySubRegs: false, /* CoveredBySubRegs */
921 .SuperClasses: AnyRegBit_with_subreg_h64Superclasses, .SuperClassesSize: 2,
922 .OrderFunc: AnyRegBit_with_subreg_h64GetRawAllocationOrder
923 };
924
925 extern const TargetRegisterClass CR64BitRegClass = {
926 .MC: &SystemZMCRegisterClasses[CR64BitRegClassID],
927 .SubClassMask: CR64BitSubClassMask,
928 .SuperRegIndices: SuperRegIdxSeqs + 2,
929 .LaneMask: LaneBitmask(0x0000000000000001),
930 .AllocationPriority: 0,
931 .GlobalPriority: false,
932 .TSFlags: 0x00, /* TSFlags */
933 .SpillStackID: 0, /* SpillStackID */
934 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
935 .CoveredBySubRegs: false, /* CoveredBySubRegs */
936 .SuperClasses: nullptr, .SuperClassesSize: 0,
937 .OrderFunc: CR64BitGetRawAllocationOrder
938 };
939
940 extern const TargetRegisterClass FP64BitRegClass = {
941 .MC: &SystemZMCRegisterClasses[FP64BitRegClassID],
942 .SubClassMask: FP64BitSubClassMask,
943 .SuperRegIndices: SuperRegIdxSeqs + 0,
944 .LaneMask: LaneBitmask(0x0000000000000001),
945 .AllocationPriority: 0,
946 .GlobalPriority: false,
947 .TSFlags: 0x00, /* TSFlags */
948 .SpillStackID: 0, /* SpillStackID */
949 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
950 .CoveredBySubRegs: false, /* CoveredBySubRegs */
951 .SuperClasses: FP64BitSuperclasses, .SuperClassesSize: 3,
952 .OrderFunc: FP64BitGetRawAllocationOrder
953 };
954
955 extern const TargetRegisterClass GR64BitRegClass = {
956 .MC: &SystemZMCRegisterClasses[GR64BitRegClassID],
957 .SubClassMask: GR64BitSubClassMask,
958 .SuperRegIndices: SuperRegIdxSeqs + 0,
959 .LaneMask: LaneBitmask(0x0000000000000003),
960 .AllocationPriority: 0,
961 .GlobalPriority: false,
962 .TSFlags: 0x00, /* TSFlags */
963 .SpillStackID: 0, /* SpillStackID */
964 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
965 .CoveredBySubRegs: true, /* CoveredBySubRegs */
966 .SuperClasses: GR64BitSuperclasses, .SuperClassesSize: 1,
967 .OrderFunc: GR64BitGetRawAllocationOrder
968 };
969
970 extern const TargetRegisterClass ADDR64BitRegClass = {
971 .MC: &SystemZMCRegisterClasses[ADDR64BitRegClassID],
972 .SubClassMask: ADDR64BitSubClassMask,
973 .SuperRegIndices: SuperRegIdxSeqs + 0,
974 .LaneMask: LaneBitmask(0x0000000000000003),
975 .AllocationPriority: 0,
976 .GlobalPriority: false,
977 .TSFlags: 0x00, /* TSFlags */
978 .SpillStackID: 0, /* SpillStackID */
979 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
980 .CoveredBySubRegs: true, /* CoveredBySubRegs */
981 .SuperClasses: ADDR64BitSuperclasses, .SuperClassesSize: 2,
982 .OrderFunc: ADDR64BitGetRawAllocationOrder
983 };
984
985 extern const TargetRegisterClass VR128BitRegClass = {
986 .MC: &SystemZMCRegisterClasses[VR128BitRegClassID],
987 .SubClassMask: VR128BitSubClassMask,
988 .SuperRegIndices: SuperRegIdxSeqs + 2,
989 .LaneMask: LaneBitmask(0x0000000000000003),
990 .AllocationPriority: 0,
991 .GlobalPriority: false,
992 .TSFlags: 0x00, /* TSFlags */
993 .SpillStackID: 0, /* SpillStackID */
994 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
995 .CoveredBySubRegs: false, /* CoveredBySubRegs */
996 .SuperClasses: nullptr, .SuperClassesSize: 0,
997 .OrderFunc: VR128BitGetRawAllocationOrder
998 };
999
1000 extern const TargetRegisterClass VF128BitRegClass = {
1001 .MC: &SystemZMCRegisterClasses[VF128BitRegClassID],
1002 .SubClassMask: VF128BitSubClassMask,
1003 .SuperRegIndices: SuperRegIdxSeqs + 2,
1004 .LaneMask: LaneBitmask(0x0000000000000003),
1005 .AllocationPriority: 0,
1006 .GlobalPriority: false,
1007 .TSFlags: 0x00, /* TSFlags */
1008 .SpillStackID: 0, /* SpillStackID */
1009 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1010 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1011 .SuperClasses: VF128BitSuperclasses, .SuperClassesSize: 4,
1012 .OrderFunc: VF128BitGetRawAllocationOrder
1013 };
1014
1015 extern const TargetRegisterClass FP128BitRegClass = {
1016 .MC: &SystemZMCRegisterClasses[FP128BitRegClassID],
1017 .SubClassMask: FP128BitSubClassMask,
1018 .SuperRegIndices: SuperRegIdxSeqs + 2,
1019 .LaneMask: LaneBitmask(0x000000000000000F),
1020 .AllocationPriority: 0,
1021 .GlobalPriority: false,
1022 .TSFlags: 0x00, /* TSFlags */
1023 .SpillStackID: 0, /* SpillStackID */
1024 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1025 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1026 .SuperClasses: nullptr, .SuperClassesSize: 0,
1027 .OrderFunc: FP128BitGetRawAllocationOrder
1028 };
1029
1030 extern const TargetRegisterClass GR128BitRegClass = {
1031 .MC: &SystemZMCRegisterClasses[GR128BitRegClassID],
1032 .SubClassMask: GR128BitSubClassMask,
1033 .SuperRegIndices: SuperRegIdxSeqs + 2,
1034 .LaneMask: LaneBitmask(0x000000000000000F),
1035 .AllocationPriority: 0,
1036 .GlobalPriority: false,
1037 .TSFlags: 0x00, /* TSFlags */
1038 .SpillStackID: 0, /* SpillStackID */
1039 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1040 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1041 .SuperClasses: nullptr, .SuperClassesSize: 0,
1042 .OrderFunc: GR128BitGetRawAllocationOrder
1043 };
1044
1045 extern const TargetRegisterClass ADDR128BitRegClass = {
1046 .MC: &SystemZMCRegisterClasses[ADDR128BitRegClassID],
1047 .SubClassMask: ADDR128BitSubClassMask,
1048 .SuperRegIndices: SuperRegIdxSeqs + 2,
1049 .LaneMask: LaneBitmask(0x000000000000000F),
1050 .AllocationPriority: 0,
1051 .GlobalPriority: false,
1052 .TSFlags: 0x00, /* TSFlags */
1053 .SpillStackID: 0, /* SpillStackID */
1054 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1055 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1056 .SuperClasses: ADDR128BitSuperclasses, .SuperClassesSize: 1,
1057 .OrderFunc: ADDR128BitGetRawAllocationOrder
1058 };
1059
1060
1061} // namespace SystemZ
1062static const TargetRegisterClass *const SystemZRegisterClasses[] = {
1063 &SystemZ::VR16BitRegClass,
1064 &SystemZ::FP16BitRegClass,
1065 &SystemZ::GRX32BitRegClass,
1066 &SystemZ::VR32BitRegClass,
1067 &SystemZ::AR32BitRegClass,
1068 &SystemZ::FP32BitRegClass,
1069 &SystemZ::GR32BitRegClass,
1070 &SystemZ::GRH32BitRegClass,
1071 &SystemZ::ADDR32BitRegClass,
1072 &SystemZ::CCRRegClass,
1073 &SystemZ::FPCRegsRegClass,
1074 &SystemZ::AnyRegBitRegClass,
1075 &SystemZ::AnyRegBit_with_subreg_h16RegClass,
1076 &SystemZ::VR64BitRegClass,
1077 &SystemZ::AnyRegBit_with_subreg_h64RegClass,
1078 &SystemZ::CR64BitRegClass,
1079 &SystemZ::FP64BitRegClass,
1080 &SystemZ::GR64BitRegClass,
1081 &SystemZ::ADDR64BitRegClass,
1082 &SystemZ::VR128BitRegClass,
1083 &SystemZ::VF128BitRegClass,
1084 &SystemZ::FP128BitRegClass,
1085 &SystemZ::GR128BitRegClass,
1086 &SystemZ::ADDR128BitRegClass,
1087 };
1088
1089static const uint8_t SystemZCostPerUseTable[] = {
10900, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1091
1092
1093static const bool SystemZInAllocatableClassTable[] = {
1094false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
1095
1096
1097static const TargetRegisterInfoDesc SystemZRegInfoDesc = { // Extra Descriptors
1098.CostPerUse: SystemZCostPerUseTable, .NumCosts: 1, .InAllocatableClass: SystemZInAllocatableClassTable};
1099
1100unsigned SystemZGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1101 static const uint8_t RowMap[8] = {
1102 0, 0, 0, 0, 1, 1, 0, 0,
1103 };
1104 static const uint8_t Rows[2][8] = {
1105 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1106 { SystemZ::subreg_lh32_then_subreg_h16, SystemZ::subreg_lh32, 0, SystemZ::subreg_ll32, 0, 0, 0, 0, },
1107 };
1108
1109 --IdxA; assert(IdxA < 8); (void) IdxA;
1110 --IdxB; assert(IdxB < 8);
1111 return Rows[RowMap[IdxA]][IdxB];
1112}
1113
1114unsigned SystemZGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1115 static const uint8_t Table[8][8] = {
1116 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1117 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1118 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1119 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1120 { 0, 0, 0, 0, 0, SystemZ::subreg_h32, SystemZ::subreg_l32, SystemZ::subreg_h16, },
1121 { 0, 0, 0, 0, 0, SystemZ::subreg_h32, SystemZ::subreg_l32, SystemZ::subreg_h16, },
1122 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1123 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
1124 };
1125
1126 --IdxA; assert(IdxA < 8);
1127 --IdxB; assert(IdxB < 8);
1128 return Table[IdxA][IdxB];
1129 }
1130
1131 struct MaskRolOp {
1132 LaneBitmask Mask;
1133 uint8_t RotateLeft;
1134 };
1135 static const MaskRolOp LaneMaskComposeSequences[] = {
1136 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
1137 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
1138 { .Mask: LaneBitmask(0x0000000000000001), .RotateLeft: 3 }, { .Mask: LaneBitmask(0x0000000000000002), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
1139 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 7
1140 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 9
1141 };
1142 static const uint8_t CompositeSequences[] = {
1143 0, // to subreg_h16
1144 0, // to subreg_h32
1145 0, // to subreg_h64
1146 2, // to subreg_l32
1147 4, // to subreg_l64
1148 7, // to subreg_lh32
1149 9, // to subreg_ll32
1150 7 // to subreg_lh32_then_subreg_h16
1151 };
1152
1153LaneBitmask SystemZGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1154 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
1155 LaneBitmask Result;
1156 for (const MaskRolOp *Ops =
1157 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1158 Ops->Mask.any(); ++Ops) {
1159 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
1160 if (unsigned S = Ops->RotateLeft)
1161 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
1162 else
1163 Result |= LaneBitmask(M);
1164 }
1165 return Result;
1166}
1167
1168LaneBitmask SystemZGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1169 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
1170 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
1171 LaneBitmask Result;
1172 for (const MaskRolOp *Ops =
1173 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1174 Ops->Mask.any(); ++Ops) {
1175 LaneBitmask::Type M = LaneMask.getAsInteger();
1176 if (unsigned S = Ops->RotateLeft)
1177 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
1178 else
1179 Result |= LaneBitmask(M);
1180 }
1181 return Result;
1182}
1183
1184const TargetRegisterClass *SystemZGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1185 static constexpr uint8_t Table[24][8] = {
1186 { // VR16Bit
1187 0, // subreg_h16
1188 0, // subreg_h32
1189 0, // subreg_h64
1190 0, // subreg_l32
1191 0, // subreg_l64
1192 0, // subreg_lh32
1193 0, // subreg_ll32
1194 0, // subreg_lh32_then_subreg_h16
1195 },
1196 { // FP16Bit
1197 0, // subreg_h16
1198 0, // subreg_h32
1199 0, // subreg_h64
1200 0, // subreg_l32
1201 0, // subreg_l64
1202 0, // subreg_lh32
1203 0, // subreg_ll32
1204 0, // subreg_lh32_then_subreg_h16
1205 },
1206 { // GRX32Bit
1207 0, // subreg_h16
1208 0, // subreg_h32
1209 0, // subreg_h64
1210 0, // subreg_l32
1211 0, // subreg_l64
1212 0, // subreg_lh32
1213 0, // subreg_ll32
1214 0, // subreg_lh32_then_subreg_h16
1215 },
1216 { // VR32Bit
1217 4, // subreg_h16 -> VR32Bit
1218 0, // subreg_h32
1219 0, // subreg_h64
1220 0, // subreg_l32
1221 0, // subreg_l64
1222 0, // subreg_lh32
1223 0, // subreg_ll32
1224 0, // subreg_lh32_then_subreg_h16
1225 },
1226 { // AR32Bit
1227 0, // subreg_h16
1228 0, // subreg_h32
1229 0, // subreg_h64
1230 0, // subreg_l32
1231 0, // subreg_l64
1232 0, // subreg_lh32
1233 0, // subreg_ll32
1234 0, // subreg_lh32_then_subreg_h16
1235 },
1236 { // FP32Bit
1237 6, // subreg_h16 -> FP32Bit
1238 0, // subreg_h32
1239 0, // subreg_h64
1240 0, // subreg_l32
1241 0, // subreg_l64
1242 0, // subreg_lh32
1243 0, // subreg_ll32
1244 0, // subreg_lh32_then_subreg_h16
1245 },
1246 { // GR32Bit
1247 0, // subreg_h16
1248 0, // subreg_h32
1249 0, // subreg_h64
1250 0, // subreg_l32
1251 0, // subreg_l64
1252 0, // subreg_lh32
1253 0, // subreg_ll32
1254 0, // subreg_lh32_then_subreg_h16
1255 },
1256 { // GRH32Bit
1257 0, // subreg_h16
1258 0, // subreg_h32
1259 0, // subreg_h64
1260 0, // subreg_l32
1261 0, // subreg_l64
1262 0, // subreg_lh32
1263 0, // subreg_ll32
1264 0, // subreg_lh32_then_subreg_h16
1265 },
1266 { // ADDR32Bit
1267 0, // subreg_h16
1268 0, // subreg_h32
1269 0, // subreg_h64
1270 0, // subreg_l32
1271 0, // subreg_l64
1272 0, // subreg_lh32
1273 0, // subreg_ll32
1274 0, // subreg_lh32_then_subreg_h16
1275 },
1276 { // CCR
1277 0, // subreg_h16
1278 0, // subreg_h32
1279 0, // subreg_h64
1280 0, // subreg_l32
1281 0, // subreg_l64
1282 0, // subreg_lh32
1283 0, // subreg_ll32
1284 0, // subreg_lh32_then_subreg_h16
1285 },
1286 { // FPCRegs
1287 0, // subreg_h16
1288 0, // subreg_h32
1289 0, // subreg_h64
1290 0, // subreg_l32
1291 0, // subreg_l64
1292 0, // subreg_lh32
1293 0, // subreg_ll32
1294 0, // subreg_lh32_then_subreg_h16
1295 },
1296 { // AnyRegBit
1297 13, // subreg_h16 -> AnyRegBit_with_subreg_h16
1298 12, // subreg_h32 -> AnyRegBit
1299 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
1300 18, // subreg_l32 -> GR64Bit
1301 0, // subreg_l64
1302 0, // subreg_lh32
1303 0, // subreg_ll32
1304 0, // subreg_lh32_then_subreg_h16
1305 },
1306 { // AnyRegBit_with_subreg_h16
1307 13, // subreg_h16 -> AnyRegBit_with_subreg_h16
1308 13, // subreg_h32 -> AnyRegBit_with_subreg_h16
1309 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
1310 0, // subreg_l32
1311 0, // subreg_l64
1312 0, // subreg_lh32
1313 0, // subreg_ll32
1314 0, // subreg_lh32_then_subreg_h16
1315 },
1316 { // VR64Bit
1317 14, // subreg_h16 -> VR64Bit
1318 14, // subreg_h32 -> VR64Bit
1319 0, // subreg_h64
1320 0, // subreg_l32
1321 0, // subreg_l64
1322 0, // subreg_lh32
1323 0, // subreg_ll32
1324 0, // subreg_lh32_then_subreg_h16
1325 },
1326 { // AnyRegBit_with_subreg_h64
1327 15, // subreg_h16 -> AnyRegBit_with_subreg_h64
1328 15, // subreg_h32 -> AnyRegBit_with_subreg_h64
1329 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
1330 0, // subreg_l32
1331 0, // subreg_l64
1332 0, // subreg_lh32
1333 0, // subreg_ll32
1334 0, // subreg_lh32_then_subreg_h16
1335 },
1336 { // CR64Bit
1337 0, // subreg_h16
1338 0, // subreg_h32
1339 0, // subreg_h64
1340 0, // subreg_l32
1341 0, // subreg_l64
1342 0, // subreg_lh32
1343 0, // subreg_ll32
1344 0, // subreg_lh32_then_subreg_h16
1345 },
1346 { // FP64Bit
1347 17, // subreg_h16 -> FP64Bit
1348 17, // subreg_h32 -> FP64Bit
1349 0, // subreg_h64
1350 0, // subreg_l32
1351 0, // subreg_l64
1352 0, // subreg_lh32
1353 0, // subreg_ll32
1354 0, // subreg_lh32_then_subreg_h16
1355 },
1356 { // GR64Bit
1357 0, // subreg_h16
1358 18, // subreg_h32 -> GR64Bit
1359 0, // subreg_h64
1360 18, // subreg_l32 -> GR64Bit
1361 0, // subreg_l64
1362 0, // subreg_lh32
1363 0, // subreg_ll32
1364 0, // subreg_lh32_then_subreg_h16
1365 },
1366 { // ADDR64Bit
1367 0, // subreg_h16
1368 19, // subreg_h32 -> ADDR64Bit
1369 0, // subreg_h64
1370 19, // subreg_l32 -> ADDR64Bit
1371 0, // subreg_l64
1372 0, // subreg_lh32
1373 0, // subreg_ll32
1374 0, // subreg_lh32_then_subreg_h16
1375 },
1376 { // VR128Bit
1377 20, // subreg_h16 -> VR128Bit
1378 20, // subreg_h32 -> VR128Bit
1379 20, // subreg_h64 -> VR128Bit
1380 0, // subreg_l32
1381 0, // subreg_l64
1382 0, // subreg_lh32
1383 0, // subreg_ll32
1384 0, // subreg_lh32_then_subreg_h16
1385 },
1386 { // VF128Bit
1387 21, // subreg_h16 -> VF128Bit
1388 21, // subreg_h32 -> VF128Bit
1389 21, // subreg_h64 -> VF128Bit
1390 0, // subreg_l32
1391 0, // subreg_l64
1392 0, // subreg_lh32
1393 0, // subreg_ll32
1394 0, // subreg_lh32_then_subreg_h16
1395 },
1396 { // FP128Bit
1397 22, // subreg_h16 -> FP128Bit
1398 22, // subreg_h32 -> FP128Bit
1399 22, // subreg_h64 -> FP128Bit
1400 0, // subreg_l32
1401 22, // subreg_l64 -> FP128Bit
1402 22, // subreg_lh32 -> FP128Bit
1403 0, // subreg_ll32
1404 22, // subreg_lh32_then_subreg_h16 -> FP128Bit
1405 },
1406 { // GR128Bit
1407 0, // subreg_h16
1408 23, // subreg_h32 -> GR128Bit
1409 23, // subreg_h64 -> GR128Bit
1410 23, // subreg_l32 -> GR128Bit
1411 23, // subreg_l64 -> GR128Bit
1412 23, // subreg_lh32 -> GR128Bit
1413 23, // subreg_ll32 -> GR128Bit
1414 0, // subreg_lh32_then_subreg_h16
1415 },
1416 { // ADDR128Bit
1417 0, // subreg_h16
1418 24, // subreg_h32 -> ADDR128Bit
1419 24, // subreg_h64 -> ADDR128Bit
1420 24, // subreg_l32 -> ADDR128Bit
1421 24, // subreg_l64 -> ADDR128Bit
1422 24, // subreg_lh32 -> ADDR128Bit
1423 24, // subreg_ll32 -> ADDR128Bit
1424 0, // subreg_lh32_then_subreg_h16
1425 },
1426
1427 };
1428 assert(RC && "Missing regclass");
1429 if (!Idx) return RC;
1430 --Idx;
1431 assert(Idx < 8 && "Bad subreg");
1432 unsigned TV = Table[RC->getID()][Idx];
1433 return TV ? getRegClass(i: TV - 1) : nullptr;
1434}const TargetRegisterClass *SystemZGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1435 static constexpr uint8_t Table[24][8] = {
1436 { // VR16Bit
1437 0, // VR16Bit:subreg_h16
1438 0, // VR16Bit:subreg_h32
1439 0, // VR16Bit:subreg_h64
1440 0, // VR16Bit:subreg_l32
1441 0, // VR16Bit:subreg_l64
1442 0, // VR16Bit:subreg_lh32
1443 0, // VR16Bit:subreg_ll32
1444 0, // VR16Bit:subreg_lh32_then_subreg_h16
1445 },
1446 { // FP16Bit
1447 0, // FP16Bit:subreg_h16
1448 0, // FP16Bit:subreg_h32
1449 0, // FP16Bit:subreg_h64
1450 0, // FP16Bit:subreg_l32
1451 0, // FP16Bit:subreg_l64
1452 0, // FP16Bit:subreg_lh32
1453 0, // FP16Bit:subreg_ll32
1454 0, // FP16Bit:subreg_lh32_then_subreg_h16
1455 },
1456 { // GRX32Bit
1457 0, // GRX32Bit:subreg_h16
1458 0, // GRX32Bit:subreg_h32
1459 0, // GRX32Bit:subreg_h64
1460 0, // GRX32Bit:subreg_l32
1461 0, // GRX32Bit:subreg_l64
1462 0, // GRX32Bit:subreg_lh32
1463 0, // GRX32Bit:subreg_ll32
1464 0, // GRX32Bit:subreg_lh32_then_subreg_h16
1465 },
1466 { // VR32Bit
1467 1, // VR32Bit:subreg_h16 -> VR16Bit
1468 0, // VR32Bit:subreg_h32
1469 0, // VR32Bit:subreg_h64
1470 0, // VR32Bit:subreg_l32
1471 0, // VR32Bit:subreg_l64
1472 0, // VR32Bit:subreg_lh32
1473 0, // VR32Bit:subreg_ll32
1474 0, // VR32Bit:subreg_lh32_then_subreg_h16
1475 },
1476 { // AR32Bit
1477 0, // AR32Bit:subreg_h16
1478 0, // AR32Bit:subreg_h32
1479 0, // AR32Bit:subreg_h64
1480 0, // AR32Bit:subreg_l32
1481 0, // AR32Bit:subreg_l64
1482 0, // AR32Bit:subreg_lh32
1483 0, // AR32Bit:subreg_ll32
1484 0, // AR32Bit:subreg_lh32_then_subreg_h16
1485 },
1486 { // FP32Bit
1487 2, // FP32Bit:subreg_h16 -> FP16Bit
1488 0, // FP32Bit:subreg_h32
1489 0, // FP32Bit:subreg_h64
1490 0, // FP32Bit:subreg_l32
1491 0, // FP32Bit:subreg_l64
1492 0, // FP32Bit:subreg_lh32
1493 0, // FP32Bit:subreg_ll32
1494 0, // FP32Bit:subreg_lh32_then_subreg_h16
1495 },
1496 { // GR32Bit
1497 0, // GR32Bit:subreg_h16
1498 0, // GR32Bit:subreg_h32
1499 0, // GR32Bit:subreg_h64
1500 0, // GR32Bit:subreg_l32
1501 0, // GR32Bit:subreg_l64
1502 0, // GR32Bit:subreg_lh32
1503 0, // GR32Bit:subreg_ll32
1504 0, // GR32Bit:subreg_lh32_then_subreg_h16
1505 },
1506 { // GRH32Bit
1507 0, // GRH32Bit:subreg_h16
1508 0, // GRH32Bit:subreg_h32
1509 0, // GRH32Bit:subreg_h64
1510 0, // GRH32Bit:subreg_l32
1511 0, // GRH32Bit:subreg_l64
1512 0, // GRH32Bit:subreg_lh32
1513 0, // GRH32Bit:subreg_ll32
1514 0, // GRH32Bit:subreg_lh32_then_subreg_h16
1515 },
1516 { // ADDR32Bit
1517 0, // ADDR32Bit:subreg_h16
1518 0, // ADDR32Bit:subreg_h32
1519 0, // ADDR32Bit:subreg_h64
1520 0, // ADDR32Bit:subreg_l32
1521 0, // ADDR32Bit:subreg_l64
1522 0, // ADDR32Bit:subreg_lh32
1523 0, // ADDR32Bit:subreg_ll32
1524 0, // ADDR32Bit:subreg_lh32_then_subreg_h16
1525 },
1526 { // CCR
1527 0, // CCR:subreg_h16
1528 0, // CCR:subreg_h32
1529 0, // CCR:subreg_h64
1530 0, // CCR:subreg_l32
1531 0, // CCR:subreg_l64
1532 0, // CCR:subreg_lh32
1533 0, // CCR:subreg_ll32
1534 0, // CCR:subreg_lh32_then_subreg_h16
1535 },
1536 { // FPCRegs
1537 0, // FPCRegs:subreg_h16
1538 0, // FPCRegs:subreg_h32
1539 0, // FPCRegs:subreg_h64
1540 0, // FPCRegs:subreg_l32
1541 0, // FPCRegs:subreg_l64
1542 0, // FPCRegs:subreg_lh32
1543 0, // FPCRegs:subreg_ll32
1544 0, // FPCRegs:subreg_lh32_then_subreg_h16
1545 },
1546 { // AnyRegBit
1547 1, // AnyRegBit:subreg_h16 -> VR16Bit
1548 4, // AnyRegBit:subreg_h32 -> VR32Bit
1549 17, // AnyRegBit:subreg_h64 -> FP64Bit
1550 7, // AnyRegBit:subreg_l32 -> GR32Bit
1551 0, // AnyRegBit:subreg_l64
1552 0, // AnyRegBit:subreg_lh32
1553 0, // AnyRegBit:subreg_ll32
1554 0, // AnyRegBit:subreg_lh32_then_subreg_h16
1555 },
1556 { // AnyRegBit_with_subreg_h16
1557 1, // AnyRegBit_with_subreg_h16:subreg_h16 -> VR16Bit
1558 4, // AnyRegBit_with_subreg_h16:subreg_h32 -> VR32Bit
1559 17, // AnyRegBit_with_subreg_h16:subreg_h64 -> FP64Bit
1560 0, // AnyRegBit_with_subreg_h16:subreg_l32
1561 0, // AnyRegBit_with_subreg_h16:subreg_l64
1562 0, // AnyRegBit_with_subreg_h16:subreg_lh32
1563 0, // AnyRegBit_with_subreg_h16:subreg_ll32
1564 0, // AnyRegBit_with_subreg_h16:subreg_lh32_then_subreg_h16
1565 },
1566 { // VR64Bit
1567 1, // VR64Bit:subreg_h16 -> VR16Bit
1568 4, // VR64Bit:subreg_h32 -> VR32Bit
1569 0, // VR64Bit:subreg_h64
1570 0, // VR64Bit:subreg_l32
1571 0, // VR64Bit:subreg_l64
1572 0, // VR64Bit:subreg_lh32
1573 0, // VR64Bit:subreg_ll32
1574 0, // VR64Bit:subreg_lh32_then_subreg_h16
1575 },
1576 { // AnyRegBit_with_subreg_h64
1577 2, // AnyRegBit_with_subreg_h64:subreg_h16 -> FP16Bit
1578 6, // AnyRegBit_with_subreg_h64:subreg_h32 -> FP32Bit
1579 17, // AnyRegBit_with_subreg_h64:subreg_h64 -> FP64Bit
1580 0, // AnyRegBit_with_subreg_h64:subreg_l32
1581 0, // AnyRegBit_with_subreg_h64:subreg_l64
1582 0, // AnyRegBit_with_subreg_h64:subreg_lh32
1583 0, // AnyRegBit_with_subreg_h64:subreg_ll32
1584 0, // AnyRegBit_with_subreg_h64:subreg_lh32_then_subreg_h16
1585 },
1586 { // CR64Bit
1587 0, // CR64Bit:subreg_h16
1588 0, // CR64Bit:subreg_h32
1589 0, // CR64Bit:subreg_h64
1590 0, // CR64Bit:subreg_l32
1591 0, // CR64Bit:subreg_l64
1592 0, // CR64Bit:subreg_lh32
1593 0, // CR64Bit:subreg_ll32
1594 0, // CR64Bit:subreg_lh32_then_subreg_h16
1595 },
1596 { // FP64Bit
1597 2, // FP64Bit:subreg_h16 -> FP16Bit
1598 6, // FP64Bit:subreg_h32 -> FP32Bit
1599 0, // FP64Bit:subreg_h64
1600 0, // FP64Bit:subreg_l32
1601 0, // FP64Bit:subreg_l64
1602 0, // FP64Bit:subreg_lh32
1603 0, // FP64Bit:subreg_ll32
1604 0, // FP64Bit:subreg_lh32_then_subreg_h16
1605 },
1606 { // GR64Bit
1607 0, // GR64Bit:subreg_h16
1608 8, // GR64Bit:subreg_h32 -> GRH32Bit
1609 0, // GR64Bit:subreg_h64
1610 7, // GR64Bit:subreg_l32 -> GR32Bit
1611 0, // GR64Bit:subreg_l64
1612 0, // GR64Bit:subreg_lh32
1613 0, // GR64Bit:subreg_ll32
1614 0, // GR64Bit:subreg_lh32_then_subreg_h16
1615 },
1616 { // ADDR64Bit
1617 0, // ADDR64Bit:subreg_h16
1618 8, // ADDR64Bit:subreg_h32 -> GRH32Bit
1619 0, // ADDR64Bit:subreg_h64
1620 9, // ADDR64Bit:subreg_l32 -> ADDR32Bit
1621 0, // ADDR64Bit:subreg_l64
1622 0, // ADDR64Bit:subreg_lh32
1623 0, // ADDR64Bit:subreg_ll32
1624 0, // ADDR64Bit:subreg_lh32_then_subreg_h16
1625 },
1626 { // VR128Bit
1627 1, // VR128Bit:subreg_h16 -> VR16Bit
1628 4, // VR128Bit:subreg_h32 -> VR32Bit
1629 14, // VR128Bit:subreg_h64 -> VR64Bit
1630 0, // VR128Bit:subreg_l32
1631 0, // VR128Bit:subreg_l64
1632 0, // VR128Bit:subreg_lh32
1633 0, // VR128Bit:subreg_ll32
1634 0, // VR128Bit:subreg_lh32_then_subreg_h16
1635 },
1636 { // VF128Bit
1637 2, // VF128Bit:subreg_h16 -> FP16Bit
1638 6, // VF128Bit:subreg_h32 -> FP32Bit
1639 17, // VF128Bit:subreg_h64 -> FP64Bit
1640 0, // VF128Bit:subreg_l32
1641 0, // VF128Bit:subreg_l64
1642 0, // VF128Bit:subreg_lh32
1643 0, // VF128Bit:subreg_ll32
1644 0, // VF128Bit:subreg_lh32_then_subreg_h16
1645 },
1646 { // FP128Bit
1647 2, // FP128Bit:subreg_h16 -> FP16Bit
1648 6, // FP128Bit:subreg_h32 -> FP32Bit
1649 17, // FP128Bit:subreg_h64 -> FP64Bit
1650 0, // FP128Bit:subreg_l32
1651 17, // FP128Bit:subreg_l64 -> FP64Bit
1652 6, // FP128Bit:subreg_lh32 -> FP32Bit
1653 0, // FP128Bit:subreg_ll32
1654 2, // FP128Bit:subreg_lh32_then_subreg_h16 -> FP16Bit
1655 },
1656 { // GR128Bit
1657 0, // GR128Bit:subreg_h16
1658 8, // GR128Bit:subreg_h32 -> GRH32Bit
1659 18, // GR128Bit:subreg_h64 -> GR64Bit
1660 7, // GR128Bit:subreg_l32 -> GR32Bit
1661 19, // GR128Bit:subreg_l64 -> ADDR64Bit
1662 8, // GR128Bit:subreg_lh32 -> GRH32Bit
1663 9, // GR128Bit:subreg_ll32 -> ADDR32Bit
1664 0, // GR128Bit:subreg_lh32_then_subreg_h16
1665 },
1666 { // ADDR128Bit
1667 0, // ADDR128Bit:subreg_h16
1668 8, // ADDR128Bit:subreg_h32 -> GRH32Bit
1669 19, // ADDR128Bit:subreg_h64 -> ADDR64Bit
1670 9, // ADDR128Bit:subreg_l32 -> ADDR32Bit
1671 19, // ADDR128Bit:subreg_l64 -> ADDR64Bit
1672 8, // ADDR128Bit:subreg_lh32 -> GRH32Bit
1673 9, // ADDR128Bit:subreg_ll32 -> ADDR32Bit
1674 0, // ADDR128Bit:subreg_lh32_then_subreg_h16
1675 },
1676
1677 };
1678 assert(RC && "Missing regclass");
1679 if (!Idx) return RC;
1680 --Idx;
1681 assert(Idx < 8 && "Bad subreg");
1682 unsigned TV = Table[RC->getID()][Idx];
1683 return TV ? getRegClass(i: TV - 1) : nullptr;
1684}/// Get the weight in units of pressure for this register class.
1685const RegClassWeight &SystemZGenRegisterInfo::
1686getRegClassWeight(const TargetRegisterClass *RC) const {
1687 static const RegClassWeight RCWeightTable[] = {
1688 {.RegWeight: 1, .WeightLimit: 32}, // VR16Bit
1689 {.RegWeight: 1, .WeightLimit: 16}, // FP16Bit
1690 {.RegWeight: 1, .WeightLimit: 32}, // GRX32Bit
1691 {.RegWeight: 1, .WeightLimit: 32}, // VR32Bit
1692 {.RegWeight: 0, .WeightLimit: 0}, // AR32Bit
1693 {.RegWeight: 1, .WeightLimit: 16}, // FP32Bit
1694 {.RegWeight: 1, .WeightLimit: 16}, // GR32Bit
1695 {.RegWeight: 1, .WeightLimit: 16}, // GRH32Bit
1696 {.RegWeight: 1, .WeightLimit: 15}, // ADDR32Bit
1697 {.RegWeight: 0, .WeightLimit: 0}, // CCR
1698 {.RegWeight: 0, .WeightLimit: 0}, // FPCRegs
1699 {.RegWeight: 1, .WeightLimit: 48}, // AnyRegBit
1700 {.RegWeight: 1, .WeightLimit: 16}, // AnyRegBit_with_subreg_h16
1701 {.RegWeight: 1, .WeightLimit: 32}, // VR64Bit
1702 {.RegWeight: 1, .WeightLimit: 16}, // AnyRegBit_with_subreg_h64
1703 {.RegWeight: 0, .WeightLimit: 0}, // CR64Bit
1704 {.RegWeight: 1, .WeightLimit: 16}, // FP64Bit
1705 {.RegWeight: 2, .WeightLimit: 32}, // GR64Bit
1706 {.RegWeight: 2, .WeightLimit: 30}, // ADDR64Bit
1707 {.RegWeight: 1, .WeightLimit: 32}, // VR128Bit
1708 {.RegWeight: 1, .WeightLimit: 16}, // VF128Bit
1709 {.RegWeight: 2, .WeightLimit: 16}, // FP128Bit
1710 {.RegWeight: 4, .WeightLimit: 32}, // GR128Bit
1711 {.RegWeight: 4, .WeightLimit: 28}, // ADDR128Bit
1712 };
1713 return RCWeightTable[RC->getID()];
1714}
1715
1716/// Get the weight in units of pressure for this register unit.
1717unsigned SystemZGenRegisterInfo::
1718getRegUnitWeight(MCRegUnit RegUnit) const {
1719 assert(static_cast<unsigned>(RegUnit) < 98 && "invalid register unit");
1720 // All register units have unit weight.
1721 return 1;
1722}
1723
1724
1725// Get the number of dimensions of register pressure.
1726unsigned SystemZGenRegisterInfo::getNumRegPressureSets() const {
1727 return 5;
1728}
1729
1730// Get the name of this register unit pressure set.
1731const char *SystemZGenRegisterInfo::
1732getRegPressureSetName(unsigned Idx) const {
1733 static const char *PressureNameTable[] = {
1734 "FP16Bit",
1735 "GR32Bit",
1736 "GRH32Bit",
1737 "VR16Bit",
1738 "GRX32Bit",
1739 };
1740 return PressureNameTable[Idx];
1741}
1742
1743// Get the register unit pressure limit for this dimension.
1744// This limit must be adjusted dynamically for reserved registers.
1745unsigned SystemZGenRegisterInfo::
1746getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1747 static const uint8_t PressureLimitTable[] = {
1748 16, // 0: FP16Bit
1749 16, // 1: GR32Bit
1750 16, // 2: GRH32Bit
1751 32, // 3: VR16Bit
1752 32, // 4: GRX32Bit
1753 };
1754 return PressureLimitTable[Idx];
1755}
1756
1757/// Table of pressure sets per register class or unit.
1758static const int RCSetsTable[] = {
1759 /* 0 */ 0, 3, -1,
1760 /* 3 */ 1, 4, -1,
1761 /* 6 */ 2, 4, -1,
1762};
1763
1764/// Get the dimensions of register pressure impacted by this register class.
1765/// Returns a -1 terminated array of pressure set IDs
1766const int *SystemZGenRegisterInfo::
1767getRegClassPressureSets(const TargetRegisterClass *RC) const {
1768 static const uint8_t RCSetStartTable[] = {
1769 1,0,4,1,2,0,3,6,3,2,2,2,2,1,2,2,0,4,4,1,0,0,4,4,};
1770 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1771}
1772
1773/// Get the dimensions of register pressure impacted by this register unit.
1774/// Returns a -1 terminated array of pressure set IDs
1775const int *SystemZGenRegisterInfo::
1776getRegUnitPressureSets(MCRegUnit RegUnit) const {
1777 assert(static_cast<unsigned>(RegUnit) < 98 && "invalid register unit");
1778 static const uint8_t RUSetStartTable[] = {
1779 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,};
1780 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1781}
1782
1783
1784// Register to minimal register class mapping
1785
1786const TargetRegisterClass *SystemZGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
1787 static const uint16_t InvalidRegClassID = UINT16_MAX;
1788
1789 static const uint16_t Mapping[227] = {
1790 InvalidRegClassID, // NoRegister
1791 SystemZ::CCRRegClassID, // CC
1792 SystemZ::FPCRegsRegClassID, // FPC
1793 SystemZ::AR32BitRegClassID, // A0
1794 SystemZ::AR32BitRegClassID, // A1
1795 SystemZ::AR32BitRegClassID, // A2
1796 SystemZ::AR32BitRegClassID, // A3
1797 SystemZ::AR32BitRegClassID, // A4
1798 SystemZ::AR32BitRegClassID, // A5
1799 SystemZ::AR32BitRegClassID, // A6
1800 SystemZ::AR32BitRegClassID, // A7
1801 SystemZ::AR32BitRegClassID, // A8
1802 SystemZ::AR32BitRegClassID, // A9
1803 SystemZ::AR32BitRegClassID, // A10
1804 SystemZ::AR32BitRegClassID, // A11
1805 SystemZ::AR32BitRegClassID, // A12
1806 SystemZ::AR32BitRegClassID, // A13
1807 SystemZ::AR32BitRegClassID, // A14
1808 SystemZ::AR32BitRegClassID, // A15
1809 SystemZ::CR64BitRegClassID, // C0
1810 SystemZ::CR64BitRegClassID, // C1
1811 SystemZ::CR64BitRegClassID, // C2
1812 SystemZ::CR64BitRegClassID, // C3
1813 SystemZ::CR64BitRegClassID, // C4
1814 SystemZ::CR64BitRegClassID, // C5
1815 SystemZ::CR64BitRegClassID, // C6
1816 SystemZ::CR64BitRegClassID, // C7
1817 SystemZ::CR64BitRegClassID, // C8
1818 SystemZ::CR64BitRegClassID, // C9
1819 SystemZ::CR64BitRegClassID, // C10
1820 SystemZ::CR64BitRegClassID, // C11
1821 SystemZ::CR64BitRegClassID, // C12
1822 SystemZ::CR64BitRegClassID, // C13
1823 SystemZ::CR64BitRegClassID, // C14
1824 SystemZ::CR64BitRegClassID, // C15
1825 SystemZ::VF128BitRegClassID, // V0
1826 SystemZ::VF128BitRegClassID, // V1
1827 SystemZ::VF128BitRegClassID, // V2
1828 SystemZ::VF128BitRegClassID, // V3
1829 SystemZ::VF128BitRegClassID, // V4
1830 SystemZ::VF128BitRegClassID, // V5
1831 SystemZ::VF128BitRegClassID, // V6
1832 SystemZ::VF128BitRegClassID, // V7
1833 SystemZ::VF128BitRegClassID, // V8
1834 SystemZ::VF128BitRegClassID, // V9
1835 SystemZ::VF128BitRegClassID, // V10
1836 SystemZ::VF128BitRegClassID, // V11
1837 SystemZ::VF128BitRegClassID, // V12
1838 SystemZ::VF128BitRegClassID, // V13
1839 SystemZ::VF128BitRegClassID, // V14
1840 SystemZ::VF128BitRegClassID, // V15
1841 SystemZ::VR128BitRegClassID, // V16
1842 SystemZ::VR128BitRegClassID, // V17
1843 SystemZ::VR128BitRegClassID, // V18
1844 SystemZ::VR128BitRegClassID, // V19
1845 SystemZ::VR128BitRegClassID, // V20
1846 SystemZ::VR128BitRegClassID, // V21
1847 SystemZ::VR128BitRegClassID, // V22
1848 SystemZ::VR128BitRegClassID, // V23
1849 SystemZ::VR128BitRegClassID, // V24
1850 SystemZ::VR128BitRegClassID, // V25
1851 SystemZ::VR128BitRegClassID, // V26
1852 SystemZ::VR128BitRegClassID, // V27
1853 SystemZ::VR128BitRegClassID, // V28
1854 SystemZ::VR128BitRegClassID, // V29
1855 SystemZ::VR128BitRegClassID, // V30
1856 SystemZ::VR128BitRegClassID, // V31
1857 SystemZ::FP64BitRegClassID, // F0D
1858 SystemZ::FP64BitRegClassID, // F1D
1859 SystemZ::FP64BitRegClassID, // F2D
1860 SystemZ::FP64BitRegClassID, // F3D
1861 SystemZ::FP64BitRegClassID, // F4D
1862 SystemZ::FP64BitRegClassID, // F5D
1863 SystemZ::FP64BitRegClassID, // F6D
1864 SystemZ::FP64BitRegClassID, // F7D
1865 SystemZ::FP64BitRegClassID, // F8D
1866 SystemZ::FP64BitRegClassID, // F9D
1867 SystemZ::FP64BitRegClassID, // F10D
1868 SystemZ::FP64BitRegClassID, // F11D
1869 SystemZ::FP64BitRegClassID, // F12D
1870 SystemZ::FP64BitRegClassID, // F13D
1871 SystemZ::FP64BitRegClassID, // F14D
1872 SystemZ::FP64BitRegClassID, // F15D
1873 SystemZ::VR64BitRegClassID, // F16D
1874 SystemZ::VR64BitRegClassID, // F17D
1875 SystemZ::VR64BitRegClassID, // F18D
1876 SystemZ::VR64BitRegClassID, // F19D
1877 SystemZ::VR64BitRegClassID, // F20D
1878 SystemZ::VR64BitRegClassID, // F21D
1879 SystemZ::VR64BitRegClassID, // F22D
1880 SystemZ::VR64BitRegClassID, // F23D
1881 SystemZ::VR64BitRegClassID, // F24D
1882 SystemZ::VR64BitRegClassID, // F25D
1883 SystemZ::VR64BitRegClassID, // F26D
1884 SystemZ::VR64BitRegClassID, // F27D
1885 SystemZ::VR64BitRegClassID, // F28D
1886 SystemZ::VR64BitRegClassID, // F29D
1887 SystemZ::VR64BitRegClassID, // F30D
1888 SystemZ::VR64BitRegClassID, // F31D
1889 SystemZ::FP16BitRegClassID, // F0H
1890 SystemZ::FP16BitRegClassID, // F1H
1891 SystemZ::FP16BitRegClassID, // F2H
1892 SystemZ::FP16BitRegClassID, // F3H
1893 SystemZ::FP16BitRegClassID, // F4H
1894 SystemZ::FP16BitRegClassID, // F5H
1895 SystemZ::FP16BitRegClassID, // F6H
1896 SystemZ::FP16BitRegClassID, // F7H
1897 SystemZ::FP16BitRegClassID, // F8H
1898 SystemZ::FP16BitRegClassID, // F9H
1899 SystemZ::FP16BitRegClassID, // F10H
1900 SystemZ::FP16BitRegClassID, // F11H
1901 SystemZ::FP16BitRegClassID, // F12H
1902 SystemZ::FP16BitRegClassID, // F13H
1903 SystemZ::FP16BitRegClassID, // F14H
1904 SystemZ::FP16BitRegClassID, // F15H
1905 SystemZ::VR16BitRegClassID, // F16H
1906 SystemZ::VR16BitRegClassID, // F17H
1907 SystemZ::VR16BitRegClassID, // F18H
1908 SystemZ::VR16BitRegClassID, // F19H
1909 SystemZ::VR16BitRegClassID, // F20H
1910 SystemZ::VR16BitRegClassID, // F21H
1911 SystemZ::VR16BitRegClassID, // F22H
1912 SystemZ::VR16BitRegClassID, // F23H
1913 SystemZ::VR16BitRegClassID, // F24H
1914 SystemZ::VR16BitRegClassID, // F25H
1915 SystemZ::VR16BitRegClassID, // F26H
1916 SystemZ::VR16BitRegClassID, // F27H
1917 SystemZ::VR16BitRegClassID, // F28H
1918 SystemZ::VR16BitRegClassID, // F29H
1919 SystemZ::VR16BitRegClassID, // F30H
1920 SystemZ::VR16BitRegClassID, // F31H
1921 SystemZ::FP128BitRegClassID, // F0Q
1922 SystemZ::FP128BitRegClassID, // F1Q
1923 SystemZ::FP128BitRegClassID, // F4Q
1924 SystemZ::FP128BitRegClassID, // F5Q
1925 SystemZ::FP128BitRegClassID, // F8Q
1926 SystemZ::FP128BitRegClassID, // F9Q
1927 SystemZ::FP128BitRegClassID, // F12Q
1928 SystemZ::FP128BitRegClassID, // F13Q
1929 SystemZ::FP32BitRegClassID, // F0S
1930 SystemZ::FP32BitRegClassID, // F1S
1931 SystemZ::FP32BitRegClassID, // F2S
1932 SystemZ::FP32BitRegClassID, // F3S
1933 SystemZ::FP32BitRegClassID, // F4S
1934 SystemZ::FP32BitRegClassID, // F5S
1935 SystemZ::FP32BitRegClassID, // F6S
1936 SystemZ::FP32BitRegClassID, // F7S
1937 SystemZ::FP32BitRegClassID, // F8S
1938 SystemZ::FP32BitRegClassID, // F9S
1939 SystemZ::FP32BitRegClassID, // F10S
1940 SystemZ::FP32BitRegClassID, // F11S
1941 SystemZ::FP32BitRegClassID, // F12S
1942 SystemZ::FP32BitRegClassID, // F13S
1943 SystemZ::FP32BitRegClassID, // F14S
1944 SystemZ::FP32BitRegClassID, // F15S
1945 SystemZ::VR32BitRegClassID, // F16S
1946 SystemZ::VR32BitRegClassID, // F17S
1947 SystemZ::VR32BitRegClassID, // F18S
1948 SystemZ::VR32BitRegClassID, // F19S
1949 SystemZ::VR32BitRegClassID, // F20S
1950 SystemZ::VR32BitRegClassID, // F21S
1951 SystemZ::VR32BitRegClassID, // F22S
1952 SystemZ::VR32BitRegClassID, // F23S
1953 SystemZ::VR32BitRegClassID, // F24S
1954 SystemZ::VR32BitRegClassID, // F25S
1955 SystemZ::VR32BitRegClassID, // F26S
1956 SystemZ::VR32BitRegClassID, // F27S
1957 SystemZ::VR32BitRegClassID, // F28S
1958 SystemZ::VR32BitRegClassID, // F29S
1959 SystemZ::VR32BitRegClassID, // F30S
1960 SystemZ::VR32BitRegClassID, // F31S
1961 SystemZ::GR64BitRegClassID, // R0D
1962 SystemZ::ADDR64BitRegClassID, // R1D
1963 SystemZ::ADDR64BitRegClassID, // R2D
1964 SystemZ::ADDR64BitRegClassID, // R3D
1965 SystemZ::ADDR64BitRegClassID, // R4D
1966 SystemZ::ADDR64BitRegClassID, // R5D
1967 SystemZ::ADDR64BitRegClassID, // R6D
1968 SystemZ::ADDR64BitRegClassID, // R7D
1969 SystemZ::ADDR64BitRegClassID, // R8D
1970 SystemZ::ADDR64BitRegClassID, // R9D
1971 SystemZ::ADDR64BitRegClassID, // R10D
1972 SystemZ::ADDR64BitRegClassID, // R11D
1973 SystemZ::ADDR64BitRegClassID, // R12D
1974 SystemZ::ADDR64BitRegClassID, // R13D
1975 SystemZ::ADDR64BitRegClassID, // R14D
1976 SystemZ::ADDR64BitRegClassID, // R15D
1977 SystemZ::GRH32BitRegClassID, // R0H
1978 SystemZ::GRH32BitRegClassID, // R1H
1979 SystemZ::GRH32BitRegClassID, // R2H
1980 SystemZ::GRH32BitRegClassID, // R3H
1981 SystemZ::GRH32BitRegClassID, // R4H
1982 SystemZ::GRH32BitRegClassID, // R5H
1983 SystemZ::GRH32BitRegClassID, // R6H
1984 SystemZ::GRH32BitRegClassID, // R7H
1985 SystemZ::GRH32BitRegClassID, // R8H
1986 SystemZ::GRH32BitRegClassID, // R9H
1987 SystemZ::GRH32BitRegClassID, // R10H
1988 SystemZ::GRH32BitRegClassID, // R11H
1989 SystemZ::GRH32BitRegClassID, // R12H
1990 SystemZ::GRH32BitRegClassID, // R13H
1991 SystemZ::GRH32BitRegClassID, // R14H
1992 SystemZ::GRH32BitRegClassID, // R15H
1993 SystemZ::GR32BitRegClassID, // R0L
1994 SystemZ::ADDR32BitRegClassID, // R1L
1995 SystemZ::ADDR32BitRegClassID, // R2L
1996 SystemZ::ADDR32BitRegClassID, // R3L
1997 SystemZ::ADDR32BitRegClassID, // R4L
1998 SystemZ::ADDR32BitRegClassID, // R5L
1999 SystemZ::ADDR32BitRegClassID, // R6L
2000 SystemZ::ADDR32BitRegClassID, // R7L
2001 SystemZ::ADDR32BitRegClassID, // R8L
2002 SystemZ::ADDR32BitRegClassID, // R9L
2003 SystemZ::ADDR32BitRegClassID, // R10L
2004 SystemZ::ADDR32BitRegClassID, // R11L
2005 SystemZ::ADDR32BitRegClassID, // R12L
2006 SystemZ::ADDR32BitRegClassID, // R13L
2007 SystemZ::ADDR32BitRegClassID, // R14L
2008 SystemZ::ADDR32BitRegClassID, // R15L
2009 SystemZ::GR128BitRegClassID, // R0Q
2010 SystemZ::ADDR128BitRegClassID, // R2Q
2011 SystemZ::ADDR128BitRegClassID, // R4Q
2012 SystemZ::ADDR128BitRegClassID, // R6Q
2013 SystemZ::ADDR128BitRegClassID, // R8Q
2014 SystemZ::ADDR128BitRegClassID, // R10Q
2015 SystemZ::ADDR128BitRegClassID, // R12Q
2016 SystemZ::ADDR128BitRegClassID, // R14Q
2017 };
2018
2019 assert(Reg < ArrayRef(Mapping).size());
2020 unsigned RCID = Mapping[Reg.id()];
2021 if (RCID == InvalidRegClassID)
2022 return nullptr;
2023 return SystemZRegisterClasses[RCID];
2024}
2025extern const MCRegisterDesc SystemZRegDesc[];
2026extern const int16_t SystemZRegDiffLists[];
2027extern const LaneBitmask SystemZLaneMaskLists[];
2028extern const char SystemZRegStrings[];
2029extern const char SystemZRegClassStrings[];
2030extern const MCPhysReg SystemZRegUnitRoots[][2];
2031extern const uint16_t SystemZSubRegIdxLists[];
2032extern const uint16_t SystemZRegEncodingTable[];
2033// SystemZ Dwarf<->LLVM register mappings.
2034extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[];
2035extern const unsigned SystemZDwarfFlavour0Dwarf2LSize;
2036
2037extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[];
2038extern const unsigned SystemZEHFlavour0Dwarf2LSize;
2039
2040extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[];
2041extern const unsigned SystemZDwarfFlavour0L2DwarfSize;
2042
2043extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[];
2044extern const unsigned SystemZEHFlavour0L2DwarfSize;
2045
2046
2047SystemZGenRegisterInfo::
2048SystemZGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
2049 unsigned PC, unsigned HwMode)
2050 : TargetRegisterInfo(&SystemZRegInfoDesc, SystemZRegisterClasses,
2051 SystemZSubRegIndexStrings, SystemZSubRegIndexNameOffsets,
2052 SystemZSubRegIdxRangeTable, SystemZSubRegIndexLaneMaskTable,
2053
2054 LaneBitmask(0xFFFFFFFFFFFFFFFC), SystemZRegClassInfos, SystemZVTLists, HwMode) {
2055 InitMCRegisterInfo(D: SystemZRegDesc, NR: 227, RA, PC,
2056 C: SystemZMCRegisterClasses, NC: 24, RURoots: SystemZRegUnitRoots, NRU: 98, DL: SystemZRegDiffLists,
2057 RUMS: SystemZLaneMaskLists, Strings: SystemZRegStrings, ClassStrings: SystemZRegClassStrings, SubIndices: SystemZSubRegIdxLists, NumIndices: 9,
2058 RET: SystemZRegEncodingTable, RUI: nullptr);
2059
2060 switch (DwarfFlavour) {
2061 default:
2062 llvm_unreachable("Unknown DWARF flavour");
2063 case 0:
2064 mapDwarfRegsToLLVMRegs(Map: SystemZDwarfFlavour0Dwarf2L, Size: SystemZDwarfFlavour0Dwarf2LSize, isEH: false);
2065 break;
2066 }
2067 switch (EHFlavour) {
2068 default:
2069 llvm_unreachable("Unknown DWARF flavour");
2070 case 0:
2071 mapDwarfRegsToLLVMRegs(Map: SystemZEHFlavour0Dwarf2L, Size: SystemZEHFlavour0Dwarf2LSize, isEH: true);
2072 break;
2073 }
2074 switch (DwarfFlavour) {
2075 default:
2076 llvm_unreachable("Unknown DWARF flavour");
2077 case 0:
2078 mapLLVMRegsToDwarfRegs(Map: SystemZDwarfFlavour0L2Dwarf, Size: SystemZDwarfFlavour0L2DwarfSize, isEH: false);
2079 break;
2080 }
2081 switch (EHFlavour) {
2082 default:
2083 llvm_unreachable("Unknown DWARF flavour");
2084 case 0:
2085 mapLLVMRegsToDwarfRegs(Map: SystemZEHFlavour0L2Dwarf, Size: SystemZEHFlavour0L2DwarfSize, isEH: true);
2086 break;
2087 }
2088}
2089
2090static const MCPhysReg CSR_SystemZ_AllRegs_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
2091static const uint32_t CSR_SystemZ_AllRegs_RegMask[] = { 0x00000000, 0x00000000, 0x0007fff8, 0x0007fff8, 0x07fffff8, 0xe7ffe000, 0xf7ffe7ff, 0x00000007, };
2092static const MCPhysReg CSR_SystemZ_AllRegs_Vector_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, 0 };
2093static const uint32_t CSR_SystemZ_AllRegs_Vector_RegMask[] = { 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xffffffff, 0xe7ffe7ff, 0xf7ffe7ff, 0x00000007, };
2094static const MCPhysReg CSR_SystemZ_ELF_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
2095static const uint32_t CSR_SystemZ_ELF_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07fe0000, 0xc7fe07fe, 0x00000007, };
2096static const MCPhysReg CSR_SystemZ_NoRegs_SaveList[] = { 0 };
2097static const uint32_t CSR_SystemZ_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
2098static const MCPhysReg CSR_SystemZ_SwiftError_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
2099static const uint32_t CSR_SystemZ_SwiftError_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07ee0000, 0x47ee07ee, 0x00000007, };
2100static const MCPhysReg CSR_SystemZ_XPLINK64_SaveList[] = { SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F15D, SystemZ::F14D, SystemZ::F13D, SystemZ::F12D, SystemZ::F11D, SystemZ::F10D, SystemZ::F9D, SystemZ::F8D, 0 };
2101static const uint32_t CSR_SystemZ_XPLINK64_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07f80000, 0x87f807f8, 0x00000007, };
2102static const MCPhysReg CSR_SystemZ_XPLINK64_Vector_SaveList[] = { SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F15D, SystemZ::F14D, SystemZ::F13D, SystemZ::F12D, SystemZ::F11D, SystemZ::F10D, SystemZ::F9D, SystemZ::F8D, SystemZ::V23, SystemZ::V22, SystemZ::V21, SystemZ::V20, SystemZ::V19, SystemZ::V18, SystemZ::V17, SystemZ::V16, 0 };
2103static const uint32_t CSR_SystemZ_XPLINK64_Vector_RegMask[] = { 0x00000000, 0x07f80000, 0x07fff800, 0x07fff800, 0xfff80780, 0x07f80007, 0x87f807f8, 0x00000007, };
2104
2105
2106ArrayRef<const uint32_t *> SystemZGenRegisterInfo::getRegMasks() const {
2107 static const uint32_t *const Masks[] = {
2108 CSR_SystemZ_AllRegs_RegMask,
2109 CSR_SystemZ_AllRegs_Vector_RegMask,
2110 CSR_SystemZ_ELF_RegMask,
2111 CSR_SystemZ_NoRegs_RegMask,
2112 CSR_SystemZ_SwiftError_RegMask,
2113 CSR_SystemZ_XPLINK64_RegMask,
2114 CSR_SystemZ_XPLINK64_Vector_RegMask,
2115 };
2116 return ArrayRef(Masks);
2117}
2118
2119bool SystemZGenRegisterInfo::
2120isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2121 return
2122 false;
2123}
2124
2125bool SystemZGenRegisterInfo::
2126isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
2127 return
2128 false;
2129}
2130
2131bool SystemZGenRegisterInfo::
2132isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2133 return
2134 false;
2135}
2136
2137bool SystemZGenRegisterInfo::
2138isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2139 return
2140 false;
2141}
2142
2143bool SystemZGenRegisterInfo::
2144isConstantPhysReg(MCRegister PhysReg) const {
2145 return
2146 false;
2147}
2148
2149ArrayRef<const char *> SystemZGenRegisterInfo::getRegMaskNames() const {
2150 static const char *Names[] = {
2151 "CSR_SystemZ_AllRegs",
2152 "CSR_SystemZ_AllRegs_Vector",
2153 "CSR_SystemZ_ELF",
2154 "CSR_SystemZ_NoRegs",
2155 "CSR_SystemZ_SwiftError",
2156 "CSR_SystemZ_XPLINK64",
2157 "CSR_SystemZ_XPLINK64_Vector",
2158 };
2159 return ArrayRef(Names);
2160}
2161
2162const SystemZFrameLowering *
2163SystemZGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
2164 return static_cast<const SystemZFrameLowering *>(
2165 MF.getSubtarget().getFrameLowering());
2166}
2167
2168
2169} // namespace llvm
2170