1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_CALLING_CONV_IMPL
10#undef GET_CALLING_CONV_IMPL
11
12static bool CC_VE2(unsigned ValNo, MVT ValVT,
13 MVT LocVT, CCValAssign::LocInfo LocInfo,
14 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
15static bool CC_VE_C(unsigned ValNo, MVT ValVT,
16 MVT LocVT, CCValAssign::LocInfo LocInfo,
17 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
18static bool CC_VE_C_Stack(unsigned ValNo, MVT ValVT,
19 MVT LocVT, CCValAssign::LocInfo LocInfo,
20 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
21static bool CC_VE_Fast(unsigned ValNo, MVT ValVT,
22 MVT LocVT, CCValAssign::LocInfo LocInfo,
23 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
24static bool RetCC_VE_C(unsigned ValNo, MVT ValVT,
25 MVT LocVT, CCValAssign::LocInfo LocInfo,
26 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
27static bool RetCC_VE_Fast(unsigned ValNo, MVT ValVT,
28 MVT LocVT, CCValAssign::LocInfo LocInfo,
29 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
30
31
32static bool CC_VE2(unsigned ValNo, MVT ValVT,
33 MVT LocVT, CCValAssign::LocInfo LocInfo,
34 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
35
36 if (LocVT == MVT::i1 ||
37 LocVT == MVT::i8 ||
38 LocVT == MVT::i16 ||
39 LocVT == MVT::i32) {
40 LocVT = MVT::i64;
41 if (ArgFlags.isSExt())
42 LocInfo = CCValAssign::SExt;
43 else if (ArgFlags.isZExt())
44 LocInfo = CCValAssign::ZExt;
45 else
46 LocInfo = CCValAssign::AExt;
47 }
48
49 if (LocVT == MVT::f32) {
50 LocVT = MVT::i64;
51 LocInfo = CCValAssign::BCvt;
52 }
53
54 if (LocVT == MVT::f128) {
55 int64_t Offset1 = State.AllocateStack(Size: 16, Alignment: Align(16));
56 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
57 return false;
58 }
59
60 int64_t Offset2 = State.AllocateStack(
61 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())), Alignment: Align(8));
62 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
63 return false;
64
65 return true; // CC didn't match.
66}
67
68
69static bool CC_VE_C(unsigned ValNo, MVT ValVT,
70 MVT LocVT, CCValAssign::LocInfo LocInfo,
71 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
72
73 if (LocVT == MVT::i1 ||
74 LocVT == MVT::i8 ||
75 LocVT == MVT::i16 ||
76 LocVT == MVT::i32) {
77 LocVT = MVT::i64;
78 if (ArgFlags.isSExt())
79 LocInfo = CCValAssign::SExt;
80 else if (ArgFlags.isZExt())
81 LocInfo = CCValAssign::ZExt;
82 else
83 LocInfo = CCValAssign::AExt;
84 }
85
86 if (LocVT == MVT::f32) {
87 LocVT = MVT::i64;
88 LocInfo = CCValAssign::BCvt;
89 }
90
91 if (LocVT == MVT::i64 ||
92 LocVT == MVT::f64) {
93 static const MCPhysReg RegList1[] = {
94 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7
95 };
96 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
97 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
98 return false;
99 }
100 }
101
102 if (LocVT == MVT::f128) {
103 static const MCPhysReg RegList2[] = {
104 VE::Q0, VE::Q1, VE::Q2, VE::Q3
105 };
106 static const MCPhysReg RegList3[] = {
107 VE::SX0, VE::SX1, VE::SX3, VE::SX5
108 };
109 if (MCRegister Reg = State.AllocateReg(Regs: RegList2, ShadowRegs: RegList3)) {
110 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
111 return false;
112 }
113 }
114
115 if (!CC_VE_C_Stack(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
116 return false;
117
118 return true; // CC didn't match.
119}
120
121
122static bool CC_VE_C_Stack(unsigned ValNo, MVT ValVT,
123 MVT LocVT, CCValAssign::LocInfo LocInfo,
124 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
125
126 if (LocVT == MVT::f128) {
127 static const MCPhysReg ShadowRegList1[] = {
128 VE::SX7
129 };
130 int64_t Offset2 = State.AllocateStack(Size: 16, Alignment: Align(16), ShadowRegs: ShadowRegList1);
131 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
132 return false;
133 }
134
135 int64_t Offset3 = State.AllocateStack(
136 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())), Alignment: Align(8));
137 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
138 return false;
139
140 return true; // CC didn't match.
141}
142
143
144static bool CC_VE_Fast(unsigned ValNo, MVT ValVT,
145 MVT LocVT, CCValAssign::LocInfo LocInfo,
146 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
147
148 if (LocVT == MVT::v256i32 ||
149 LocVT == MVT::v256f32 ||
150 LocVT == MVT::v256i64 ||
151 LocVT == MVT::v256f64) {
152 static const MCPhysReg RegList1[] = {
153 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
154 };
155 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
156 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
157 return false;
158 }
159 }
160
161 if (LocVT == MVT::v512i32 ||
162 LocVT == MVT::v512f32) {
163 static const MCPhysReg RegList2[] = {
164 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
165 };
166 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
167 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
168 return false;
169 }
170 }
171
172 if (LocVT == MVT::v256i1) {
173 static const MCPhysReg RegList3[] = {
174 VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7
175 };
176 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
177 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
178 return false;
179 }
180 }
181
182 if (LocVT == MVT::v512i1) {
183 static const MCPhysReg RegList4[] = {
184 VE::VMP1, VE::VMP2, VE::VMP3
185 };
186 static const MCPhysReg RegList5[] = {
187 VE::VM1, VE::VM3, VE::VM5
188 };
189 if (MCRegister Reg = State.AllocateReg(Regs: RegList4, ShadowRegs: RegList5)) {
190 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
191 return false;
192 }
193 }
194
195 if (!CC_VE_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
196 return false;
197
198 return true; // CC didn't match.
199}
200
201
202static bool RetCC_VE_C(unsigned ValNo, MVT ValVT,
203 MVT LocVT, CCValAssign::LocInfo LocInfo,
204 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
205
206 if (LocVT == MVT::i1 ||
207 LocVT == MVT::i8 ||
208 LocVT == MVT::i16 ||
209 LocVT == MVT::i32) {
210 LocVT = MVT::i64;
211 if (ArgFlags.isSExt())
212 LocInfo = CCValAssign::SExt;
213 else if (ArgFlags.isZExt())
214 LocInfo = CCValAssign::ZExt;
215 else
216 LocInfo = CCValAssign::AExt;
217 }
218
219 if (LocVT == MVT::f32) {
220 LocVT = MVT::i64;
221 LocInfo = CCValAssign::BCvt;
222 }
223
224 if (LocVT == MVT::i64 ||
225 LocVT == MVT::f64) {
226 static const MCPhysReg RegList1[] = {
227 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7
228 };
229 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
230 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
231 return false;
232 }
233 }
234
235 if (LocVT == MVT::f128) {
236 static const MCPhysReg RegList2[] = {
237 VE::Q0, VE::Q1, VE::Q2, VE::Q3
238 };
239 static const MCPhysReg RegList3[] = {
240 VE::SX0, VE::SX1, VE::SX3, VE::SX5
241 };
242 if (MCRegister Reg = State.AllocateReg(Regs: RegList2, ShadowRegs: RegList3)) {
243 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
244 return false;
245 }
246 }
247
248 return true; // CC didn't match.
249}
250
251
252static bool RetCC_VE_Fast(unsigned ValNo, MVT ValVT,
253 MVT LocVT, CCValAssign::LocInfo LocInfo,
254 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
255
256 if (LocVT == MVT::v256i32 ||
257 LocVT == MVT::v256f32 ||
258 LocVT == MVT::v256i64 ||
259 LocVT == MVT::v256f64) {
260 static const MCPhysReg RegList1[] = {
261 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
262 };
263 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
264 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
265 return false;
266 }
267 }
268
269 if (LocVT == MVT::v512i32 ||
270 LocVT == MVT::v512f32) {
271 static const MCPhysReg RegList2[] = {
272 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
273 };
274 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
275 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
276 return false;
277 }
278 }
279
280 if (LocVT == MVT::v256i1) {
281 static const MCPhysReg RegList3[] = {
282 VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7
283 };
284 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
285 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
286 return false;
287 }
288 }
289
290 if (LocVT == MVT::v512i1) {
291 static const MCPhysReg RegList4[] = {
292 VE::VMP1, VE::VMP2, VE::VMP3
293 };
294 static const MCPhysReg RegList5[] = {
295 VE::VM1, VE::VM3, VE::VM5
296 };
297 if (MCRegister Reg = State.AllocateReg(Regs: RegList4, ShadowRegs: RegList5)) {
298 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
299 return false;
300 }
301 }
302
303 if (!RetCC_VE_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
304 return false;
305
306 return true; // CC didn't match.
307}
308
309#endif // GET_CALLING_CONV_IMPL
310
311#ifdef GET_CC_REGISTER_LISTS
312#undef GET_CC_REGISTER_LISTS
313
314const MCRegister CC_VE2_ArgRegs[] = { 0 };
315const MCRegister CC_VE_C_ArgRegs[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7 };
316const MCRegister CC_VE_C_Stack_ArgRegs[] = { 0 };
317const MCRegister CC_VE_Fast_ArgRegs[] = { VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7 };
318const MCRegister RetCC_VE_C_ArgRegs[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7 };
319const MCRegister RetCC_VE_Fast_ArgRegs[] = { VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7 };
320
321#endif // GET_CC_REGISTER_LISTS
322
323