1//===-- VEISelLowering.cpp - VE DAG Lowering Implementation ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the interfaces that VE uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "VEISelLowering.h"
15#include "MCTargetDesc/VEMCAsmInfo.h"
16#include "VECustomDAG.h"
17#include "VEInstrBuilder.h"
18#include "VEMachineFunctionInfo.h"
19#include "VERegisterInfo.h"
20#include "VESelectionDAGInfo.h"
21#include "VETargetMachine.h"
22#include "llvm/ADT/StringSwitch.h"
23#include "llvm/CodeGen/CallingConvLower.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineJumpTableInfo.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/SelectionDAG.h"
31#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32#include "llvm/IR/DerivedTypes.h"
33#include "llvm/IR/Function.h"
34#include "llvm/IR/IRBuilder.h"
35#include "llvm/IR/Module.h"
36#include "llvm/Support/ErrorHandling.h"
37using namespace llvm;
38
39#define DEBUG_TYPE "ve-lower"
40
41//===----------------------------------------------------------------------===//
42// Calling Convention Implementation
43//===----------------------------------------------------------------------===//
44
45#define GET_CALLING_CONV_IMPL
46#include "VEGenCallingConv.inc"
47
48CCAssignFn *getReturnCC(CallingConv::ID CallConv) {
49 switch (CallConv) {
50 default:
51 return RetCC_VE_C;
52 case CallingConv::Fast:
53 return RetCC_VE_Fast;
54 }
55}
56
57CCAssignFn *getParamCC(CallingConv::ID CallConv, bool IsVarArg) {
58 if (IsVarArg)
59 return CC_VE2;
60 switch (CallConv) {
61 default:
62 return CC_VE_C;
63 case CallingConv::Fast:
64 return CC_VE_Fast;
65 }
66}
67
68bool VETargetLowering::CanLowerReturn(
69 CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
70 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
71 const Type *RetTy) const {
72 CCAssignFn *RetCC = getReturnCC(CallConv);
73 SmallVector<CCValAssign, 16> RVLocs;
74 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
75 return CCInfo.CheckReturn(Outs, Fn: RetCC);
76}
77
78static const MVT AllVectorVTs[] = {MVT::v256i32, MVT::v512i32, MVT::v256i64,
79 MVT::v256f32, MVT::v512f32, MVT::v256f64};
80
81static const MVT AllMaskVTs[] = {MVT::v256i1, MVT::v512i1};
82
83static const MVT AllPackedVTs[] = {MVT::v512i32, MVT::v512f32};
84
85void VETargetLowering::initRegisterClasses() {
86 // Set up the register classes.
87 addRegisterClass(VT: MVT::i32, RC: &VE::I32RegClass);
88 addRegisterClass(VT: MVT::i64, RC: &VE::I64RegClass);
89 addRegisterClass(VT: MVT::f32, RC: &VE::F32RegClass);
90 addRegisterClass(VT: MVT::f64, RC: &VE::I64RegClass);
91 addRegisterClass(VT: MVT::f128, RC: &VE::F128RegClass);
92
93 if (Subtarget->enableVPU()) {
94 for (MVT VecVT : AllVectorVTs)
95 addRegisterClass(VT: VecVT, RC: &VE::V64RegClass);
96 addRegisterClass(VT: MVT::v256i1, RC: &VE::VMRegClass);
97 addRegisterClass(VT: MVT::v512i1, RC: &VE::VM512RegClass);
98 }
99}
100
101void VETargetLowering::initSPUActions() {
102 const auto &TM = getTargetMachine();
103 /// Load & Store {
104
105 // VE doesn't have i1 sign extending load.
106 for (MVT VT : MVT::integer_valuetypes()) {
107 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
108 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
109 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
110 setTruncStoreAction(ValVT: VT, MemVT: MVT::i1, Action: Expand);
111 }
112
113 // VE doesn't have floating point extload/truncstore, so expand them.
114 for (MVT FPVT : MVT::fp_valuetypes()) {
115 for (MVT OtherFPVT : MVT::fp_valuetypes()) {
116 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: FPVT, MemVT: OtherFPVT, Action: Expand);
117 setTruncStoreAction(ValVT: FPVT, MemVT: OtherFPVT, Action: Expand);
118 }
119 }
120
121 // VE doesn't have fp128 load/store, so expand them in custom lower.
122 setOperationAction(Op: ISD::LOAD, VT: MVT::f128, Action: Custom);
123 setOperationAction(Op: ISD::STORE, VT: MVT::f128, Action: Custom);
124
125 /// } Load & Store
126
127 // Custom legalize address nodes into LO/HI parts.
128 MVT PtrVT = MVT::getIntegerVT(BitWidth: TM.getPointerSizeInBits(AS: 0));
129 setOperationAction(Op: ISD::BlockAddress, VT: PtrVT, Action: Custom);
130 setOperationAction(Op: ISD::GlobalAddress, VT: PtrVT, Action: Custom);
131 setOperationAction(Op: ISD::GlobalTLSAddress, VT: PtrVT, Action: Custom);
132 setOperationAction(Op: ISD::ConstantPool, VT: PtrVT, Action: Custom);
133 setOperationAction(Op: ISD::JumpTable, VT: PtrVT, Action: Custom);
134
135 /// VAARG handling {
136 setOperationAction(Op: ISD::VASTART, VT: MVT::Other, Action: Custom);
137 // VAARG needs to be lowered to access with 8 bytes alignment.
138 setOperationAction(Op: ISD::VAARG, VT: MVT::Other, Action: Custom);
139 // Use the default implementation.
140 setOperationAction(Op: ISD::VACOPY, VT: MVT::Other, Action: Expand);
141 setOperationAction(Op: ISD::VAEND, VT: MVT::Other, Action: Expand);
142 /// } VAARG handling
143
144 /// Stack {
145 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i32, Action: Custom);
146 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i64, Action: Custom);
147
148 // Use the default implementation.
149 setOperationAction(Op: ISD::STACKSAVE, VT: MVT::Other, Action: Expand);
150 setOperationAction(Op: ISD::STACKRESTORE, VT: MVT::Other, Action: Expand);
151 /// } Stack
152
153 /// Branch {
154
155 // VE doesn't have BRCOND
156 setOperationAction(Op: ISD::BRCOND, VT: MVT::Other, Action: Expand);
157
158 // BR_JT is not implemented yet.
159 setOperationAction(Op: ISD::BR_JT, VT: MVT::Other, Action: Expand);
160
161 /// } Branch
162
163 /// Int Ops {
164 for (MVT IntVT : {MVT::i32, MVT::i64}) {
165 // VE has no REM or DIVREM operations.
166 setOperationAction(Op: ISD::UREM, VT: IntVT, Action: Expand);
167 setOperationAction(Op: ISD::SREM, VT: IntVT, Action: Expand);
168 setOperationAction(Op: ISD::SDIVREM, VT: IntVT, Action: Expand);
169 setOperationAction(Op: ISD::UDIVREM, VT: IntVT, Action: Expand);
170
171 // VE has no SHL_PARTS/SRA_PARTS/SRL_PARTS operations.
172 setOperationAction(Op: ISD::SHL_PARTS, VT: IntVT, Action: Expand);
173 setOperationAction(Op: ISD::SRA_PARTS, VT: IntVT, Action: Expand);
174 setOperationAction(Op: ISD::SRL_PARTS, VT: IntVT, Action: Expand);
175
176 // VE has no MULHU/S or U/SMUL_LOHI operations.
177 // TODO: Use MPD instruction to implement SMUL_LOHI for i32 type.
178 setOperationAction(Op: ISD::MULHU, VT: IntVT, Action: Expand);
179 setOperationAction(Op: ISD::MULHS, VT: IntVT, Action: Expand);
180 setOperationAction(Op: ISD::UMUL_LOHI, VT: IntVT, Action: Expand);
181 setOperationAction(Op: ISD::SMUL_LOHI, VT: IntVT, Action: Expand);
182
183 // VE has no CTTZ, ROTL, ROTR operations.
184 setOperationAction(Op: ISD::CTTZ, VT: IntVT, Action: Expand);
185 setOperationAction(Op: ISD::ROTL, VT: IntVT, Action: Expand);
186 setOperationAction(Op: ISD::ROTR, VT: IntVT, Action: Expand);
187
188 // VE has 64 bits instruction which works as i64 BSWAP operation. This
189 // instruction works fine as i32 BSWAP operation with an additional
190 // parameter. Use isel patterns to lower BSWAP.
191 setOperationAction(Op: ISD::BSWAP, VT: IntVT, Action: Legal);
192
193 // VE has only 64 bits instructions which work as i64 BITREVERSE/CTLZ/CTPOP
194 // operations. Use isel patterns for i64, promote for i32.
195 LegalizeAction Act = (IntVT == MVT::i32) ? Promote : Legal;
196 setOperationAction(Op: ISD::BITREVERSE, VT: IntVT, Action: Act);
197 setOperationAction(Op: ISD::CTLZ, VT: IntVT, Action: Act);
198 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: IntVT, Action: Act);
199 setOperationAction(Op: ISD::CTPOP, VT: IntVT, Action: Act);
200
201 // VE has only 64 bits instructions which work as i64 AND/OR/XOR operations.
202 // Use isel patterns for i64, promote for i32.
203 setOperationAction(Op: ISD::AND, VT: IntVT, Action: Act);
204 setOperationAction(Op: ISD::OR, VT: IntVT, Action: Act);
205 setOperationAction(Op: ISD::XOR, VT: IntVT, Action: Act);
206
207 // Legal smax and smin
208 setOperationAction(Op: ISD::SMAX, VT: IntVT, Action: Legal);
209 setOperationAction(Op: ISD::SMIN, VT: IntVT, Action: Legal);
210 }
211 /// } Int Ops
212
213 /// Conversion {
214 // VE doesn't have instructions for fp<->uint, so expand them by llvm
215 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i32, Action: Promote); // use i64
216 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i32, Action: Promote); // use i64
217 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i64, Action: Expand);
218 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i64, Action: Expand);
219
220 // fp16 not supported
221 for (MVT FPVT : MVT::fp_valuetypes()) {
222 setOperationAction(Op: ISD::FP16_TO_FP, VT: FPVT, Action: Expand);
223 setOperationAction(Op: ISD::FP_TO_FP16, VT: FPVT, Action: Expand);
224 }
225 /// } Conversion
226
227 /// Floating-point Ops {
228 /// Note: Floating-point operations are fneg, fadd, fsub, fmul, fdiv, frem,
229 /// and fcmp.
230
231 // VE doesn't have following floating point operations.
232 for (MVT VT : MVT::fp_valuetypes()) {
233 setOperationAction(Op: ISD::FNEG, VT, Action: Expand);
234 setOperationAction(Op: ISD::FREM, VT, Action: LibCall);
235 }
236
237 // VE doesn't have fdiv of f128.
238 setOperationAction(Op: ISD::FDIV, VT: MVT::f128, Action: Expand);
239
240 for (MVT FPVT : {MVT::f32, MVT::f64}) {
241 // f32 and f64 uses ConstantFP. f128 uses ConstantPool.
242 setOperationAction(Op: ISD::ConstantFP, VT: FPVT, Action: Legal);
243 }
244 /// } Floating-point Ops
245
246 /// Floating-point math functions {
247
248 // VE doesn't have following floating point math functions.
249 for (MVT VT : MVT::fp_valuetypes()) {
250 setOperationAction(Op: ISD::FABS, VT, Action: Expand);
251 setOperationAction(Op: ISD::FCOPYSIGN, VT, Action: Expand);
252 setOperationAction(Op: ISD::FCOS, VT, Action: Expand);
253 setOperationAction(Op: ISD::FMA, VT, Action: Expand);
254 setOperationAction(Op: ISD::FPOW, VT, Action: Expand);
255 setOperationAction(Op: ISD::FSIN, VT, Action: Expand);
256 setOperationAction(Op: ISD::FSQRT, VT, Action: Expand);
257 }
258
259 // VE has single and double FMINNUM and FMAXNUM
260 for (MVT VT : {MVT::f32, MVT::f64}) {
261 setOperationAction(Ops: {ISD::FMAXNUM, ISD::FMINNUM}, VT, Action: Legal);
262 }
263
264 /// } Floating-point math functions
265
266 /// Atomic instructions {
267
268 setMaxAtomicSizeInBitsSupported(64);
269 setMinCmpXchgSizeInBits(32);
270 setSupportsUnalignedAtomics(false);
271
272 // Use custom inserter for ATOMIC_FENCE.
273 setOperationAction(Op: ISD::ATOMIC_FENCE, VT: MVT::Other, Action: Custom);
274
275 // Other atomic instructions.
276 for (MVT VT : MVT::integer_valuetypes()) {
277 // Support i8/i16 atomic swap.
278 setOperationAction(Op: ISD::ATOMIC_SWAP, VT, Action: Custom);
279
280 // FIXME: Support "atmam" instructions.
281 setOperationAction(Op: ISD::ATOMIC_LOAD_ADD, VT, Action: Expand);
282 setOperationAction(Op: ISD::ATOMIC_LOAD_SUB, VT, Action: Expand);
283 setOperationAction(Op: ISD::ATOMIC_LOAD_AND, VT, Action: Expand);
284 setOperationAction(Op: ISD::ATOMIC_LOAD_OR, VT, Action: Expand);
285
286 // VE doesn't have follwing instructions.
287 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Action: Expand);
288 setOperationAction(Op: ISD::ATOMIC_LOAD_CLR, VT, Action: Expand);
289 setOperationAction(Op: ISD::ATOMIC_LOAD_XOR, VT, Action: Expand);
290 setOperationAction(Op: ISD::ATOMIC_LOAD_NAND, VT, Action: Expand);
291 setOperationAction(Op: ISD::ATOMIC_LOAD_MIN, VT, Action: Expand);
292 setOperationAction(Op: ISD::ATOMIC_LOAD_MAX, VT, Action: Expand);
293 setOperationAction(Op: ISD::ATOMIC_LOAD_UMIN, VT, Action: Expand);
294 setOperationAction(Op: ISD::ATOMIC_LOAD_UMAX, VT, Action: Expand);
295 }
296
297 /// } Atomic instructions
298
299 /// SJLJ instructions {
300 setOperationAction(Op: ISD::EH_SJLJ_LONGJMP, VT: MVT::Other, Action: Custom);
301 setOperationAction(Op: ISD::EH_SJLJ_SETJMP, VT: MVT::i32, Action: Custom);
302 setOperationAction(Op: ISD::EH_SJLJ_SETUP_DISPATCH, VT: MVT::Other, Action: Custom);
303 /// } SJLJ instructions
304
305 // Intrinsic instructions
306 setOperationAction(Op: ISD::INTRINSIC_WO_CHAIN, VT: MVT::Other, Action: Custom);
307}
308
309void VETargetLowering::initVPUActions() {
310 for (MVT LegalMaskVT : AllMaskVTs)
311 setOperationAction(Op: ISD::BUILD_VECTOR, VT: LegalMaskVT, Action: Custom);
312
313 for (unsigned Opc : {ISD::AND, ISD::OR, ISD::XOR})
314 setOperationAction(Op: Opc, VT: MVT::v512i1, Action: Custom);
315
316 for (MVT LegalVecVT : AllVectorVTs) {
317 setOperationAction(Op: ISD::BUILD_VECTOR, VT: LegalVecVT, Action: Custom);
318 setOperationAction(Op: ISD::INSERT_VECTOR_ELT, VT: LegalVecVT, Action: Legal);
319 setOperationAction(Op: ISD::EXTRACT_VECTOR_ELT, VT: LegalVecVT, Action: Legal);
320 // Translate all vector instructions with legal element types to VVP_*
321 // nodes.
322 // TODO We will custom-widen into VVP_* nodes in the future. While we are
323 // buildling the infrastructure for this, we only do this for legal vector
324 // VTs.
325#define HANDLE_VP_TO_VVP(VP_OPC, VVP_NAME) \
326 setOperationAction(ISD::VP_OPC, LegalVecVT, Custom);
327#define ADD_VVP_OP(VVP_NAME, ISD_NAME) \
328 setOperationAction(ISD::ISD_NAME, LegalVecVT, Custom);
329 setOperationAction(Op: ISD::EXPERIMENTAL_VP_STRIDED_LOAD, VT: LegalVecVT, Action: Custom);
330 setOperationAction(Op: ISD::EXPERIMENTAL_VP_STRIDED_STORE, VT: LegalVecVT, Action: Custom);
331#include "VVPNodes.def"
332 }
333
334 for (MVT LegalPackedVT : AllPackedVTs) {
335 setOperationAction(Op: ISD::INSERT_VECTOR_ELT, VT: LegalPackedVT, Action: Custom);
336 setOperationAction(Op: ISD::EXTRACT_VECTOR_ELT, VT: LegalPackedVT, Action: Custom);
337 }
338
339 // vNt32, vNt64 ops (legal element types)
340 for (MVT VT : MVT::vector_valuetypes()) {
341 MVT ElemVT = VT.getVectorElementType();
342 unsigned ElemBits = ElemVT.getScalarSizeInBits();
343 if (ElemBits != 32 && ElemBits != 64)
344 continue;
345
346 for (unsigned MemOpc : {ISD::MLOAD, ISD::MSTORE, ISD::LOAD, ISD::STORE})
347 setOperationAction(Op: MemOpc, VT, Action: Custom);
348
349 const ISD::NodeType IntReductionOCs[] = {
350 ISD::VECREDUCE_ADD, ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND,
351 ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMIN,
352 ISD::VECREDUCE_SMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_UMAX};
353
354 for (unsigned IntRedOpc : IntReductionOCs)
355 setOperationAction(Op: IntRedOpc, VT, Action: Custom);
356 }
357
358 // v256i1 and v512i1 ops
359 for (MVT MaskVT : AllMaskVTs) {
360 // Custom lower mask ops
361 setOperationAction(Op: ISD::STORE, VT: MaskVT, Action: Custom);
362 setOperationAction(Op: ISD::LOAD, VT: MaskVT, Action: Custom);
363 }
364}
365
366SDValue
367VETargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
368 bool IsVarArg,
369 const SmallVectorImpl<ISD::OutputArg> &Outs,
370 const SmallVectorImpl<SDValue> &OutVals,
371 const SDLoc &DL, SelectionDAG &DAG) const {
372 // CCValAssign - represent the assignment of the return value to locations.
373 SmallVector<CCValAssign, 16> RVLocs;
374
375 // CCState - Info about the registers and stack slot.
376 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
377 *DAG.getContext());
378
379 // Analyze return values.
380 CCInfo.AnalyzeReturn(Outs, Fn: getReturnCC(CallConv));
381
382 SDValue Glue;
383 SmallVector<SDValue, 4> RetOps(1, Chain);
384
385 // Copy the result values into the output registers.
386 for (unsigned i = 0; i != RVLocs.size(); ++i) {
387 CCValAssign &VA = RVLocs[i];
388 assert(VA.isRegLoc() && "Can only return in registers!");
389 assert(!VA.needsCustom() && "Unexpected custom lowering");
390 SDValue OutVal = OutVals[i];
391
392 // Integer return values must be sign or zero extended by the callee.
393 switch (VA.getLocInfo()) {
394 case CCValAssign::Full:
395 break;
396 case CCValAssign::SExt:
397 OutVal = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
398 break;
399 case CCValAssign::ZExt:
400 OutVal = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
401 break;
402 case CCValAssign::AExt:
403 OutVal = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
404 break;
405 case CCValAssign::BCvt: {
406 // Convert a float return value to i64 with padding.
407 // 63 31 0
408 // +------+------+
409 // | float| 0 |
410 // +------+------+
411 assert(VA.getLocVT() == MVT::i64);
412 assert(VA.getValVT() == MVT::f32);
413 SDValue Undef = SDValue(
414 DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF, dl: DL, VT: MVT::i64), 0);
415 SDValue Sub_f32 = DAG.getTargetConstant(Val: VE::sub_f32, DL, VT: MVT::i32);
416 OutVal = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl: DL,
417 VT: MVT::i64, Op1: Undef, Op2: OutVal, Op3: Sub_f32),
418 0);
419 break;
420 }
421 default:
422 llvm_unreachable("Unknown loc info!");
423 }
424
425 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: OutVal, Glue);
426
427 // Guarantee that all emitted copies are stuck together with flags.
428 Glue = Chain.getValue(R: 1);
429 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
430 }
431
432 RetOps[0] = Chain; // Update chain.
433
434 // Add the glue if we have it.
435 if (Glue.getNode())
436 RetOps.push_back(Elt: Glue);
437
438 return DAG.getNode(Opcode: VEISD::RET_GLUE, DL, VT: MVT::Other, Ops: RetOps);
439}
440
441SDValue VETargetLowering::LowerFormalArguments(
442 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
443 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
444 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
445 MachineFunction &MF = DAG.getMachineFunction();
446
447 // Get the base offset of the incoming arguments stack space.
448 unsigned ArgsBaseOffset = Subtarget->getRsaSize();
449 // Get the size of the preserved arguments area
450 unsigned ArgsPreserved = 64;
451
452 // Analyze arguments according to CC_VE.
453 SmallVector<CCValAssign, 16> ArgLocs;
454 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
455 *DAG.getContext());
456 // Allocate the preserved area first.
457 CCInfo.AllocateStack(Size: ArgsPreserved, Alignment: Align(8));
458 // We already allocated the preserved area, so the stack offset computed
459 // by CC_VE would be correct now.
460 CCInfo.AnalyzeFormalArguments(Ins, Fn: getParamCC(CallConv, IsVarArg: false));
461
462 for (const CCValAssign &VA : ArgLocs) {
463 assert(!VA.needsCustom() && "Unexpected custom lowering");
464 if (VA.isRegLoc()) {
465 // This argument is passed in a register.
466 // All integer register arguments are promoted by the caller to i64.
467
468 // Create a virtual register for the promoted live-in value.
469 Register VReg =
470 MF.addLiveIn(PReg: VA.getLocReg(), RC: getRegClassFor(VT: VA.getLocVT()));
471 SDValue Arg = DAG.getCopyFromReg(Chain, dl: DL, Reg: VReg, VT: VA.getLocVT());
472
473 // The caller promoted the argument, so insert an Assert?ext SDNode so we
474 // won't promote the value again in this function.
475 switch (VA.getLocInfo()) {
476 case CCValAssign::SExt:
477 Arg = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: Arg,
478 N2: DAG.getValueType(VA.getValVT()));
479 break;
480 case CCValAssign::ZExt:
481 Arg = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: Arg,
482 N2: DAG.getValueType(VA.getValVT()));
483 break;
484 case CCValAssign::BCvt: {
485 // Extract a float argument from i64 with padding.
486 // 63 31 0
487 // +------+------+
488 // | float| 0 |
489 // +------+------+
490 assert(VA.getLocVT() == MVT::i64);
491 assert(VA.getValVT() == MVT::f32);
492 SDValue Sub_f32 = DAG.getTargetConstant(Val: VE::sub_f32, DL, VT: MVT::i32);
493 Arg = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG, dl: DL,
494 VT: MVT::f32, Op1: Arg, Op2: Sub_f32),
495 0);
496 break;
497 }
498 default:
499 break;
500 }
501
502 // Truncate the register down to the argument type.
503 if (VA.isExtInLoc())
504 Arg = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: Arg);
505
506 InVals.push_back(Elt: Arg);
507 continue;
508 }
509
510 // The registers are exhausted. This argument was passed on the stack.
511 assert(VA.isMemLoc());
512 // The CC_VE_Full/Half functions compute stack offsets relative to the
513 // beginning of the arguments area at %fp + the size of reserved area.
514 unsigned Offset = VA.getLocMemOffset() + ArgsBaseOffset;
515 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
516
517 // Adjust offset for a float argument by adding 4 since the argument is
518 // stored in 8 bytes buffer with offset like below. LLVM generates
519 // 4 bytes load instruction, so need to adjust offset here. This
520 // adjustment is required in only LowerFormalArguments. In LowerCall,
521 // a float argument is converted to i64 first, and stored as 8 bytes
522 // data, which is required by ABI, so no need for adjustment.
523 // 0 4
524 // +------+------+
525 // | empty| float|
526 // +------+------+
527 if (VA.getValVT() == MVT::f32)
528 Offset += 4;
529
530 int FI = MF.getFrameInfo().CreateFixedObject(Size: ValSize, SPOffset: Offset, IsImmutable: true);
531 InVals.push_back(
532 Elt: DAG.getLoad(VT: VA.getValVT(), dl: DL, Chain,
533 Ptr: DAG.getFrameIndex(FI, VT: getPointerTy(DL: MF.getDataLayout())),
534 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
535 }
536
537 if (!IsVarArg)
538 return Chain;
539
540 // This function takes variable arguments, some of which may have been passed
541 // in registers %s0-%s8.
542 //
543 // The va_start intrinsic needs to know the offset to the first variable
544 // argument.
545 // TODO: need to calculate offset correctly once we support f128.
546 unsigned ArgOffset = ArgLocs.size() * 8;
547 VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
548 // Skip the reserved area at the top of stack.
549 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgsBaseOffset);
550
551 return Chain;
552}
553
554// FIXME? Maybe this could be a TableGen attribute on some registers and
555// this table could be generated automatically from RegInfo.
556Register VETargetLowering::getRegisterByName(const char *RegName, LLT VT,
557 const MachineFunction &MF) const {
558 Register Reg = StringSwitch<Register>(RegName)
559 .Case(S: "sp", Value: VE::SX11) // Stack pointer
560 .Case(S: "fp", Value: VE::SX9) // Frame pointer
561 .Case(S: "sl", Value: VE::SX8) // Stack limit
562 .Case(S: "lr", Value: VE::SX10) // Link register
563 .Case(S: "tp", Value: VE::SX14) // Thread pointer
564 .Case(S: "outer", Value: VE::SX12) // Outer regiser
565 .Case(S: "info", Value: VE::SX17) // Info area register
566 .Case(S: "got", Value: VE::SX15) // Global offset table register
567 .Case(S: "plt", Value: VE::SX16) // Procedure linkage table register
568 .Default(Value: Register());
569 return Reg;
570}
571
572//===----------------------------------------------------------------------===//
573// TargetLowering Implementation
574//===----------------------------------------------------------------------===//
575
576SDValue VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
577 SmallVectorImpl<SDValue> &InVals) const {
578 SelectionDAG &DAG = CLI.DAG;
579 SDLoc DL = CLI.DL;
580 SDValue Chain = CLI.Chain;
581 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
582
583 // VE target does not yet support tail call optimization.
584 CLI.IsTailCall = false;
585
586 // Get the base offset of the outgoing arguments stack space.
587 unsigned ArgsBaseOffset = Subtarget->getRsaSize();
588 // Get the size of the preserved arguments area
589 unsigned ArgsPreserved = 8 * 8u;
590
591 // Analyze operands of the call, assigning locations to each operand.
592 SmallVector<CCValAssign, 16> ArgLocs;
593 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
594 *DAG.getContext());
595 // Allocate the preserved area first.
596 CCInfo.AllocateStack(Size: ArgsPreserved, Alignment: Align(8));
597 // We already allocated the preserved area, so the stack offset computed
598 // by CC_VE would be correct now.
599 CCInfo.AnalyzeCallOperands(Outs: CLI.Outs, Fn: getParamCC(CallConv: CLI.CallConv, IsVarArg: false));
600
601 // VE requires to use both register and stack for varargs or no-prototyped
602 // functions.
603 bool UseBoth = CLI.IsVarArg;
604
605 // Analyze operands again if it is required to store BOTH.
606 SmallVector<CCValAssign, 16> ArgLocs2;
607 CCState CCInfo2(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
608 ArgLocs2, *DAG.getContext());
609 if (UseBoth)
610 CCInfo2.AnalyzeCallOperands(Outs: CLI.Outs, Fn: getParamCC(CallConv: CLI.CallConv, IsVarArg: true));
611
612 // Get the size of the outgoing arguments stack space requirement.
613 unsigned ArgsSize = CCInfo.getStackSize();
614
615 // Keep stack frames 16-byte aligned.
616 ArgsSize = alignTo(Value: ArgsSize, Align: 16);
617
618 // Adjust the stack pointer to make room for the arguments.
619 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
620 // with more than 6 arguments.
621 Chain = DAG.getCALLSEQ_START(Chain, InSize: ArgsSize, OutSize: 0, DL);
622
623 // Collect the set of registers to pass to the function and their values.
624 // This will be emitted as a sequence of CopyToReg nodes glued to the call
625 // instruction.
626 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
627
628 // Collect chains from all the memory opeations that copy arguments to the
629 // stack. They must follow the stack pointer adjustment above and precede the
630 // call instruction itself.
631 SmallVector<SDValue, 8> MemOpChains;
632
633 // VE needs to get address of callee function in a register
634 // So, prepare to copy it to SX12 here.
635
636 // If the callee is a GlobalAddress node (quite common, every direct call is)
637 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
638 // Likewise ExternalSymbol -> TargetExternalSymbol.
639 SDValue Callee = CLI.Callee;
640
641 bool IsPICCall = isPositionIndependent();
642
643 // PC-relative references to external symbols should go through $stub.
644 // If so, we need to prepare GlobalBaseReg first.
645 const TargetMachine &TM = DAG.getTarget();
646 const GlobalValue *GV = nullptr;
647 auto *CalleeG = dyn_cast<GlobalAddressSDNode>(Val&: Callee);
648 if (CalleeG)
649 GV = CalleeG->getGlobal();
650 bool Local = TM.shouldAssumeDSOLocal(GV);
651 bool UsePlt = !Local;
652 MachineFunction &MF = DAG.getMachineFunction();
653
654 // Turn GlobalAddress/ExternalSymbol node into a value node
655 // containing the address of them here.
656 if (CalleeG) {
657 if (IsPICCall) {
658 if (UsePlt)
659 Subtarget->getInstrInfo()->getGlobalBaseReg(MF: &MF);
660 Callee = DAG.getTargetGlobalAddress(GV, DL, VT: PtrVT, offset: 0, TargetFlags: 0);
661 Callee = DAG.getNode(Opcode: VEISD::GETFUNPLT, DL, VT: PtrVT, Operand: Callee);
662 } else {
663 Callee = makeHiLoPair(Op: Callee, HiTF: VE::S_HI32, LoTF: VE::S_LO32, DAG);
664 }
665 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee)) {
666 if (IsPICCall) {
667 if (UsePlt)
668 Subtarget->getInstrInfo()->getGlobalBaseReg(MF: &MF);
669 Callee = DAG.getTargetExternalSymbol(Sym: E->getSymbol(), VT: PtrVT, TargetFlags: 0);
670 Callee = DAG.getNode(Opcode: VEISD::GETFUNPLT, DL, VT: PtrVT, Operand: Callee);
671 } else {
672 Callee = makeHiLoPair(Op: Callee, HiTF: VE::S_HI32, LoTF: VE::S_LO32, DAG);
673 }
674 }
675
676 RegsToPass.push_back(Elt: std::make_pair(x: VE::SX12, y&: Callee));
677
678 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
679 CCValAssign &VA = ArgLocs[i];
680 SDValue Arg = CLI.OutVals[i];
681
682 // Promote the value if needed.
683 switch (VA.getLocInfo()) {
684 default:
685 llvm_unreachable("Unknown location info!");
686 case CCValAssign::Full:
687 break;
688 case CCValAssign::SExt:
689 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
690 break;
691 case CCValAssign::ZExt:
692 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
693 break;
694 case CCValAssign::AExt:
695 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
696 break;
697 case CCValAssign::BCvt: {
698 // Convert a float argument to i64 with padding.
699 // 63 31 0
700 // +------+------+
701 // | float| 0 |
702 // +------+------+
703 assert(VA.getLocVT() == MVT::i64);
704 assert(VA.getValVT() == MVT::f32);
705 SDValue Undef = SDValue(
706 DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF, dl: DL, VT: MVT::i64), 0);
707 SDValue Sub_f32 = DAG.getTargetConstant(Val: VE::sub_f32, DL, VT: MVT::i32);
708 Arg = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl: DL,
709 VT: MVT::i64, Op1: Undef, Op2: Arg, Op3: Sub_f32),
710 0);
711 break;
712 }
713 }
714
715 if (VA.isRegLoc()) {
716 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
717 if (!UseBoth)
718 continue;
719 VA = ArgLocs2[i];
720 }
721
722 assert(VA.isMemLoc());
723
724 // Create a store off the stack pointer for this argument.
725 SDValue StackPtr = DAG.getRegister(Reg: VE::SX11, VT: PtrVT);
726 // The argument area starts at %fp/%sp + the size of reserved area.
727 SDValue PtrOff =
728 DAG.getIntPtrConstant(Val: VA.getLocMemOffset() + ArgsBaseOffset, DL);
729 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: PtrOff);
730 MemOpChains.push_back(
731 Elt: DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
732 }
733
734 // Emit all stores, make sure they occur before the call.
735 if (!MemOpChains.empty())
736 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOpChains);
737
738 // Build a sequence of CopyToReg nodes glued together with token chain and
739 // glue operands which copy the outgoing args into registers. The InGlue is
740 // necessary since all emitted instructions must be stuck together in order
741 // to pass the live physical registers.
742 SDValue InGlue;
743 for (const auto &[Reg, N] : RegsToPass) {
744 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg, N, Glue: InGlue);
745 InGlue = Chain.getValue(R: 1);
746 }
747
748 // Build the operands for the call instruction itself.
749 SmallVector<SDValue, 8> Ops;
750 Ops.push_back(Elt: Chain);
751 for (const auto &[Reg, N] : RegsToPass)
752 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
753
754 // Add a register mask operand representing the call-preserved registers.
755 const VERegisterInfo *TRI = Subtarget->getRegisterInfo();
756 const uint32_t *Mask =
757 TRI->getCallPreservedMask(MF: DAG.getMachineFunction(), CC: CLI.CallConv);
758 assert(Mask && "Missing call preserved mask for calling convention");
759 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
760
761 // Make sure the CopyToReg nodes are glued to the call instruction which
762 // consumes the registers.
763 if (InGlue.getNode())
764 Ops.push_back(Elt: InGlue);
765
766 // Now the call itself.
767 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
768 Chain = DAG.getNode(Opcode: VEISD::CALL, DL, VTList: NodeTys, Ops);
769 InGlue = Chain.getValue(R: 1);
770
771 // Revert the stack pointer immediately after the call.
772 Chain = DAG.getCALLSEQ_END(Chain, Size1: ArgsSize, Size2: 0, Glue: InGlue, DL);
773 InGlue = Chain.getValue(R: 1);
774
775 // Now extract the return values. This is more or less the same as
776 // LowerFormalArguments.
777
778 // Assign locations to each value returned by this call.
779 SmallVector<CCValAssign, 16> RVLocs;
780 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
781 *DAG.getContext());
782
783 // Set inreg flag manually for codegen generated library calls that
784 // return float.
785 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB)
786 CLI.Ins[0].Flags.setInReg();
787
788 RVInfo.AnalyzeCallResult(Ins: CLI.Ins, Fn: getReturnCC(CallConv: CLI.CallConv));
789
790 // Copy all of the result registers out of their specified physreg.
791 for (unsigned i = 0; i != RVLocs.size(); ++i) {
792 CCValAssign &VA = RVLocs[i];
793 assert(!VA.needsCustom() && "Unexpected custom lowering");
794 Register Reg = VA.getLocReg();
795
796 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
797 // reside in the same register in the high and low bits. Reuse the
798 // CopyFromReg previous node to avoid duplicate copies.
799 SDValue RV;
800 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Val: Chain.getOperand(i: 1)))
801 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
802 RV = Chain.getValue(R: 0);
803
804 // But usually we'll create a new CopyFromReg for a different register.
805 if (!RV.getNode()) {
806 RV = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: RVLocs[i].getLocVT(), Glue: InGlue);
807 Chain = RV.getValue(R: 1);
808 InGlue = Chain.getValue(R: 2);
809 }
810
811 // The callee promoted the return value, so insert an Assert?ext SDNode so
812 // we won't promote the value again in this function.
813 switch (VA.getLocInfo()) {
814 case CCValAssign::SExt:
815 RV = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: RV,
816 N2: DAG.getValueType(VA.getValVT()));
817 break;
818 case CCValAssign::ZExt:
819 RV = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: RV,
820 N2: DAG.getValueType(VA.getValVT()));
821 break;
822 case CCValAssign::BCvt: {
823 // Extract a float return value from i64 with padding.
824 // 63 31 0
825 // +------+------+
826 // | float| 0 |
827 // +------+------+
828 assert(VA.getLocVT() == MVT::i64);
829 assert(VA.getValVT() == MVT::f32);
830 SDValue Sub_f32 = DAG.getTargetConstant(Val: VE::sub_f32, DL, VT: MVT::i32);
831 RV = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG, dl: DL,
832 VT: MVT::f32, Op1: RV, Op2: Sub_f32),
833 0);
834 break;
835 }
836 default:
837 break;
838 }
839
840 // Truncate the register down to the return value type.
841 if (VA.isExtInLoc())
842 RV = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: RV);
843
844 InVals.push_back(Elt: RV);
845 }
846
847 return Chain;
848}
849
850bool VETargetLowering::isOffsetFoldingLegal(
851 const GlobalAddressSDNode *GA) const {
852 // VE uses 64 bit addressing, so we need multiple instructions to generate
853 // an address. Folding address with offset increases the number of
854 // instructions, so that we disable it here. Offsets will be folded in
855 // the DAG combine later if it worth to do so.
856 return false;
857}
858
859/// isFPImmLegal - Returns true if the target can instruction select the
860/// specified FP immediate natively. If false, the legalizer will
861/// materialize the FP immediate as a load from a constant pool.
862bool VETargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
863 bool ForCodeSize) const {
864 return VT == MVT::f32 || VT == MVT::f64;
865}
866
867/// Determine if the target supports unaligned memory accesses.
868///
869/// This function returns true if the target allows unaligned memory accesses
870/// of the specified type in the given address space. If true, it also returns
871/// whether the unaligned memory access is "fast" in the last argument by
872/// reference. This is used, for example, in situations where an array
873/// copy/move/set is converted to a sequence of store operations. Its use
874/// helps to ensure that such replacements don't generate code that causes an
875/// alignment error (trap) on the target machine.
876bool VETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
877 unsigned AddrSpace,
878 Align A,
879 MachineMemOperand::Flags,
880 unsigned *Fast) const {
881 if (Fast) {
882 // It's fast anytime on VE
883 *Fast = 1;
884 }
885 return true;
886}
887
888VETargetLowering::VETargetLowering(const TargetMachine &TM,
889 const VESubtarget &STI)
890 : TargetLowering(TM, STI), Subtarget(&STI) {
891 // Instructions which use registers as conditionals examine all the
892 // bits (as does the pseudo SELECT_CC expansion). I don't think it
893 // matters much whether it's ZeroOrOneBooleanContent, or
894 // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
895 // former.
896 setBooleanContents(ZeroOrOneBooleanContent);
897 setBooleanVectorContents(ZeroOrOneBooleanContent);
898
899 initRegisterClasses();
900 initSPUActions();
901 initVPUActions();
902
903 setStackPointerRegisterToSaveRestore(VE::SX11);
904
905 // We have target-specific dag combine patterns for the following nodes:
906 setTargetDAGCombine(ISD::TRUNCATE);
907 setTargetDAGCombine(ISD::SELECT);
908 setTargetDAGCombine(ISD::SELECT_CC);
909
910 // Set function alignment to 16 bytes
911 setMinFunctionAlignment(Align(16));
912
913 // VE stores all argument by 8 bytes alignment
914 setMinStackArgumentAlignment(Align(8));
915
916 computeRegisterProperties(TRI: Subtarget->getRegisterInfo());
917}
918
919EVT VETargetLowering::getSetCCResultType(const DataLayout &,
920 LLVMContext &Context, EVT VT) const {
921 if (VT.isVector())
922 return VT.changeVectorElementType(Context, EltVT: MVT::i1);
923 return MVT::i32;
924}
925
926// Convert to a target node and set target flags.
927SDValue VETargetLowering::withTargetFlags(SDValue Op, unsigned TF,
928 SelectionDAG &DAG) const {
929 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Val&: Op))
930 return DAG.getTargetGlobalAddress(GV: GA->getGlobal(), DL: SDLoc(GA),
931 VT: GA->getValueType(ResNo: 0), offset: GA->getOffset(), TargetFlags: TF);
932
933 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Val&: Op))
934 return DAG.getTargetBlockAddress(BA: BA->getBlockAddress(), VT: Op.getValueType(),
935 Offset: 0, TargetFlags: TF);
936
937 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Val&: Op))
938 return DAG.getTargetConstantPool(C: CP->getConstVal(), VT: CP->getValueType(ResNo: 0),
939 Align: CP->getAlign(), Offset: CP->getOffset(), TargetFlags: TF);
940
941 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Val&: Op))
942 return DAG.getTargetExternalSymbol(Sym: ES->getSymbol(), VT: ES->getValueType(ResNo: 0),
943 TargetFlags: TF);
944
945 if (const JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Val&: Op))
946 return DAG.getTargetJumpTable(JTI: JT->getIndex(), VT: JT->getValueType(ResNo: 0), TargetFlags: TF);
947
948 llvm_unreachable("Unhandled address SDNode");
949}
950
951// Split Op into high and low parts according to HiTF and LoTF.
952// Return an ADD node combining the parts.
953SDValue VETargetLowering::makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
954 SelectionDAG &DAG) const {
955 SDLoc DL(Op);
956 EVT VT = Op.getValueType();
957 SDValue Hi = DAG.getNode(Opcode: VEISD::Hi, DL, VT, Operand: withTargetFlags(Op, TF: HiTF, DAG));
958 SDValue Lo = DAG.getNode(Opcode: VEISD::Lo, DL, VT, Operand: withTargetFlags(Op, TF: LoTF, DAG));
959 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Hi, N2: Lo);
960}
961
962// Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
963// or ExternalSymbol SDNode.
964SDValue VETargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
965 SDLoc DL(Op);
966 EVT PtrVT = Op.getValueType();
967
968 // Handle PIC mode first. VE needs a got load for every variable!
969 if (isPositionIndependent()) {
970 auto GlobalN = dyn_cast<GlobalAddressSDNode>(Val&: Op);
971
972 if (isa<ConstantPoolSDNode>(Val: Op) || isa<JumpTableSDNode>(Val: Op) ||
973 (GlobalN && GlobalN->getGlobal()->hasLocalLinkage())) {
974 // Create following instructions for local linkage PIC code.
975 // lea %reg, label@gotoff_lo
976 // and %reg, %reg, (32)0
977 // lea.sl %reg, label@gotoff_hi(%reg, %got)
978 SDValue HiLo =
979 makeHiLoPair(Op, HiTF: VE::S_GOTOFF_HI32, LoTF: VE::S_GOTOFF_LO32, DAG);
980 SDValue GlobalBase = DAG.getNode(Opcode: VEISD::GLOBAL_BASE_REG, DL, VT: PtrVT);
981 return DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: GlobalBase, N2: HiLo);
982 }
983 // Create following instructions for not local linkage PIC code.
984 // lea %reg, label@got_lo
985 // and %reg, %reg, (32)0
986 // lea.sl %reg, label@got_hi(%reg)
987 // ld %reg, (%reg, %got)
988 SDValue HiLo = makeHiLoPair(Op, HiTF: VE::S_GOT_HI32, LoTF: VE::S_GOT_LO32, DAG);
989 SDValue GlobalBase = DAG.getNode(Opcode: VEISD::GLOBAL_BASE_REG, DL, VT: PtrVT);
990 SDValue AbsAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: GlobalBase, N2: HiLo);
991 return DAG.getLoad(VT: PtrVT, dl: DL, Chain: DAG.getEntryNode(), Ptr: AbsAddr,
992 PtrInfo: MachinePointerInfo::getGOT(MF&: DAG.getMachineFunction()));
993 }
994
995 // This is one of the absolute code models.
996 switch (getTargetMachine().getCodeModel()) {
997 default:
998 llvm_unreachable("Unsupported absolute code model");
999 case CodeModel::Small:
1000 case CodeModel::Medium:
1001 case CodeModel::Large:
1002 // abs64.
1003 return makeHiLoPair(Op, HiTF: VE::S_HI32, LoTF: VE::S_LO32, DAG);
1004 }
1005}
1006
1007/// Custom Lower {
1008
1009// The mappings for emitLeading/TrailingFence for VE is designed by following
1010// http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
1011Instruction *VETargetLowering::emitLeadingFence(IRBuilderBase &Builder,
1012 Instruction *Inst,
1013 AtomicOrdering Ord) const {
1014 switch (Ord) {
1015 case AtomicOrdering::NotAtomic:
1016 case AtomicOrdering::Unordered:
1017 llvm_unreachable("Invalid fence: unordered/non-atomic");
1018 case AtomicOrdering::Monotonic:
1019 case AtomicOrdering::Acquire:
1020 return nullptr; // Nothing to do
1021 case AtomicOrdering::Release:
1022 case AtomicOrdering::AcquireRelease:
1023 return Builder.CreateFence(Ordering: AtomicOrdering::Release);
1024 case AtomicOrdering::SequentiallyConsistent:
1025 if (!Inst->hasAtomicStore())
1026 return nullptr; // Nothing to do
1027 return Builder.CreateFence(Ordering: AtomicOrdering::SequentiallyConsistent);
1028 }
1029 llvm_unreachable("Unknown fence ordering in emitLeadingFence");
1030}
1031
1032Instruction *VETargetLowering::emitTrailingFence(IRBuilderBase &Builder,
1033 Instruction *Inst,
1034 AtomicOrdering Ord) const {
1035 switch (Ord) {
1036 case AtomicOrdering::NotAtomic:
1037 case AtomicOrdering::Unordered:
1038 llvm_unreachable("Invalid fence: unordered/not-atomic");
1039 case AtomicOrdering::Monotonic:
1040 case AtomicOrdering::Release:
1041 return nullptr; // Nothing to do
1042 case AtomicOrdering::Acquire:
1043 case AtomicOrdering::AcquireRelease:
1044 return Builder.CreateFence(Ordering: AtomicOrdering::Acquire);
1045 case AtomicOrdering::SequentiallyConsistent:
1046 return Builder.CreateFence(Ordering: AtomicOrdering::SequentiallyConsistent);
1047 }
1048 llvm_unreachable("Unknown fence ordering in emitTrailingFence");
1049}
1050
1051SDValue VETargetLowering::lowerATOMIC_FENCE(SDValue Op,
1052 SelectionDAG &DAG) const {
1053 SDLoc DL(Op);
1054 AtomicOrdering FenceOrdering =
1055 static_cast<AtomicOrdering>(Op.getConstantOperandVal(i: 1));
1056 SyncScope::ID FenceSSID =
1057 static_cast<SyncScope::ID>(Op.getConstantOperandVal(i: 2));
1058
1059 // VE uses Release consistency, so need a fence instruction if it is a
1060 // cross-thread fence.
1061 if (FenceSSID == SyncScope::System) {
1062 switch (FenceOrdering) {
1063 case AtomicOrdering::NotAtomic:
1064 case AtomicOrdering::Unordered:
1065 case AtomicOrdering::Monotonic:
1066 // No need to generate fencem instruction here.
1067 break;
1068 case AtomicOrdering::Acquire:
1069 // Generate "fencem 2" as acquire fence.
1070 return SDValue(DAG.getMachineNode(Opcode: VE::FENCEM, dl: DL, VT: MVT::Other,
1071 Op1: DAG.getTargetConstant(Val: 2, DL, VT: MVT::i32),
1072 Op2: Op.getOperand(i: 0)),
1073 0);
1074 case AtomicOrdering::Release:
1075 // Generate "fencem 1" as release fence.
1076 return SDValue(DAG.getMachineNode(Opcode: VE::FENCEM, dl: DL, VT: MVT::Other,
1077 Op1: DAG.getTargetConstant(Val: 1, DL, VT: MVT::i32),
1078 Op2: Op.getOperand(i: 0)),
1079 0);
1080 case AtomicOrdering::AcquireRelease:
1081 case AtomicOrdering::SequentiallyConsistent:
1082 // Generate "fencem 3" as acq_rel and seq_cst fence.
1083 // FIXME: "fencem 3" doesn't wait for PCIe deveices accesses,
1084 // so seq_cst may require more instruction for them.
1085 return SDValue(DAG.getMachineNode(Opcode: VE::FENCEM, dl: DL, VT: MVT::Other,
1086 Op1: DAG.getTargetConstant(Val: 3, DL, VT: MVT::i32),
1087 Op2: Op.getOperand(i: 0)),
1088 0);
1089 }
1090 }
1091
1092 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
1093 return DAG.getNode(Opcode: ISD::MEMBARRIER, DL, VT: MVT::Other, Operand: Op.getOperand(i: 0));
1094}
1095
1096TargetLowering::AtomicExpansionKind
1097VETargetLowering::shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const {
1098 // We have TS1AM implementation for i8/i16/i32/i64, so use it.
1099 if (AI->getOperation() == AtomicRMWInst::Xchg) {
1100 return AtomicExpansionKind::None;
1101 }
1102 // FIXME: Support "ATMAM" instruction for LOAD_ADD/SUB/AND/OR.
1103
1104 // Otherwise, expand it using compare and exchange instruction to not call
1105 // __sync_fetch_and_* functions.
1106 return AtomicExpansionKind::CmpXChg;
1107}
1108
1109static SDValue prepareTS1AM(SDValue Op, SelectionDAG &DAG, SDValue &Flag,
1110 SDValue &Bits) {
1111 SDLoc DL(Op);
1112 AtomicSDNode *N = cast<AtomicSDNode>(Val&: Op);
1113 SDValue Ptr = N->getOperand(Num: 1);
1114 SDValue Val = N->getOperand(Num: 2);
1115 EVT PtrVT = Ptr.getValueType();
1116 bool Byte = N->getMemoryVT() == MVT::i8;
1117 // Remainder = AND Ptr, 3
1118 // Flag = 1 << Remainder ; If Byte is true (1 byte swap flag)
1119 // Flag = 3 << Remainder ; If Byte is false (2 bytes swap flag)
1120 // Bits = Remainder << 3
1121 // NewVal = Val << Bits
1122 SDValue Const3 = DAG.getConstant(Val: 3, DL, VT: PtrVT);
1123 SDValue Remainder = DAG.getNode(Opcode: ISD::AND, DL, VT: PtrVT, Ops: {Ptr, Const3});
1124 SDValue Mask = Byte ? DAG.getConstant(Val: 1, DL, VT: MVT::i32)
1125 : DAG.getConstant(Val: 3, DL, VT: MVT::i32);
1126 Flag = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32, Ops: {Mask, Remainder});
1127 Bits = DAG.getNode(Opcode: ISD::SHL, DL, VT: PtrVT, Ops: {Remainder, Const3});
1128 return DAG.getNode(Opcode: ISD::SHL, DL, VT: Val.getValueType(), Ops: {Val, Bits});
1129}
1130
1131static SDValue finalizeTS1AM(SDValue Op, SelectionDAG &DAG, SDValue Data,
1132 SDValue Bits) {
1133 SDLoc DL(Op);
1134 EVT VT = Data.getValueType();
1135 bool Byte = cast<AtomicSDNode>(Val&: Op)->getMemoryVT() == MVT::i8;
1136 // NewData = Data >> Bits
1137 // Result = NewData & 0xff ; If Byte is true (1 byte)
1138 // Result = NewData & 0xffff ; If Byte is false (2 bytes)
1139
1140 SDValue NewData = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Data, N2: Bits);
1141 return DAG.getNode(Opcode: ISD::AND, DL, VT,
1142 Ops: {NewData, DAG.getConstant(Val: Byte ? 0xff : 0xffff, DL, VT)});
1143}
1144
1145SDValue VETargetLowering::lowerATOMIC_SWAP(SDValue Op,
1146 SelectionDAG &DAG) const {
1147 SDLoc DL(Op);
1148 AtomicSDNode *N = cast<AtomicSDNode>(Val&: Op);
1149
1150 if (N->getMemoryVT() == MVT::i8) {
1151 // For i8, use "ts1am"
1152 // Input:
1153 // ATOMIC_SWAP Ptr, Val, Order
1154 //
1155 // Output:
1156 // Remainder = AND Ptr, 3
1157 // Flag = 1 << Remainder ; 1 byte swap flag for TS1AM inst.
1158 // Bits = Remainder << 3
1159 // NewVal = Val << Bits
1160 //
1161 // Aligned = AND Ptr, -4
1162 // Data = TS1AM Aligned, Flag, NewVal
1163 //
1164 // NewData = Data >> Bits
1165 // Result = NewData & 0xff ; 1 byte result
1166 SDValue Flag;
1167 SDValue Bits;
1168 SDValue NewVal = prepareTS1AM(Op, DAG, Flag, Bits);
1169
1170 SDValue Ptr = N->getOperand(Num: 1);
1171 SDValue Aligned =
1172 DAG.getNode(Opcode: ISD::AND, DL, VT: Ptr.getValueType(),
1173 Ops: {Ptr, DAG.getSignedConstant(Val: -4, DL, VT: MVT::i64)});
1174 SDValue TS1AM = DAG.getAtomic(Opcode: VEISD::TS1AM, dl: DL, MemVT: N->getMemoryVT(),
1175 VTList: DAG.getVTList(VT1: Op.getNode()->getValueType(ResNo: 0),
1176 VT2: Op.getNode()->getValueType(ResNo: 1)),
1177 Ops: {N->getChain(), Aligned, Flag, NewVal},
1178 MMO: N->getMemOperand());
1179
1180 SDValue Result = finalizeTS1AM(Op, DAG, Data: TS1AM, Bits);
1181 SDValue Chain = TS1AM.getValue(R: 1);
1182 return DAG.getMergeValues(Ops: {Result, Chain}, dl: DL);
1183 }
1184 if (N->getMemoryVT() == MVT::i16) {
1185 // For i16, use "ts1am"
1186 SDValue Flag;
1187 SDValue Bits;
1188 SDValue NewVal = prepareTS1AM(Op, DAG, Flag, Bits);
1189
1190 SDValue Ptr = N->getOperand(Num: 1);
1191 SDValue Aligned =
1192 DAG.getNode(Opcode: ISD::AND, DL, VT: Ptr.getValueType(),
1193 Ops: {Ptr, DAG.getSignedConstant(Val: -4, DL, VT: MVT::i64)});
1194 SDValue TS1AM = DAG.getAtomic(Opcode: VEISD::TS1AM, dl: DL, MemVT: N->getMemoryVT(),
1195 VTList: DAG.getVTList(VT1: Op.getNode()->getValueType(ResNo: 0),
1196 VT2: Op.getNode()->getValueType(ResNo: 1)),
1197 Ops: {N->getChain(), Aligned, Flag, NewVal},
1198 MMO: N->getMemOperand());
1199
1200 SDValue Result = finalizeTS1AM(Op, DAG, Data: TS1AM, Bits);
1201 SDValue Chain = TS1AM.getValue(R: 1);
1202 return DAG.getMergeValues(Ops: {Result, Chain}, dl: DL);
1203 }
1204 // Otherwise, let llvm legalize it.
1205 return Op;
1206}
1207
1208SDValue VETargetLowering::lowerGlobalAddress(SDValue Op,
1209 SelectionDAG &DAG) const {
1210 return makeAddress(Op, DAG);
1211}
1212
1213SDValue VETargetLowering::lowerBlockAddress(SDValue Op,
1214 SelectionDAG &DAG) const {
1215 return makeAddress(Op, DAG);
1216}
1217
1218SDValue VETargetLowering::lowerConstantPool(SDValue Op,
1219 SelectionDAG &DAG) const {
1220 return makeAddress(Op, DAG);
1221}
1222
1223SDValue
1224VETargetLowering::lowerToTLSGeneralDynamicModel(SDValue Op,
1225 SelectionDAG &DAG) const {
1226 SDLoc DL(Op);
1227
1228 // Generate the following code:
1229 // t1: ch,glue = callseq_start t0, 0, 0
1230 // t2: i64,ch,glue = VEISD::GETTLSADDR t1, label, t1:1
1231 // t3: ch,glue = callseq_end t2, 0, 0, t2:2
1232 // t4: i64,ch,glue = CopyFromReg t3, Register:i64 $sx0, t3:1
1233 SDValue Label = withTargetFlags(Op, TF: 0, DAG);
1234 EVT PtrVT = Op.getValueType();
1235
1236 // Lowering the machine isd will make sure everything is in the right
1237 // location.
1238 SDValue Chain = DAG.getEntryNode();
1239 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1240 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
1241 MF: DAG.getMachineFunction(), CC: CallingConv::C);
1242 Chain = DAG.getCALLSEQ_START(Chain, InSize: 64, OutSize: 0, DL);
1243 SDValue Args[] = {Chain, Label, DAG.getRegisterMask(RegMask: Mask), Chain.getValue(R: 1)};
1244 Chain = DAG.getNode(Opcode: VEISD::GETTLSADDR, DL, VTList: NodeTys, Ops: Args);
1245 Chain = DAG.getCALLSEQ_END(Chain, Size1: 64, Size2: 0, Glue: Chain.getValue(R: 1), DL);
1246 Chain = DAG.getCopyFromReg(Chain, dl: DL, Reg: VE::SX0, VT: PtrVT, Glue: Chain.getValue(R: 1));
1247
1248 // GETTLSADDR will be codegen'ed as call. Inform MFI that function has calls.
1249 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1250 MFI.setHasCalls(true);
1251
1252 // Also generate code to prepare a GOT register if it is PIC.
1253 if (isPositionIndependent()) {
1254 MachineFunction &MF = DAG.getMachineFunction();
1255 Subtarget->getInstrInfo()->getGlobalBaseReg(MF: &MF);
1256 }
1257
1258 return Chain;
1259}
1260
1261SDValue VETargetLowering::lowerGlobalTLSAddress(SDValue Op,
1262 SelectionDAG &DAG) const {
1263 // The current implementation of nld (2.26) doesn't allow local exec model
1264 // code described in VE-tls_v1.1.pdf (*1) as its input. Instead, we always
1265 // generate the general dynamic model code sequence.
1266 //
1267 // *1: https://www.nec.com/en/global/prod/hpc/aurora/document/VE-tls_v1.1.pdf
1268 return lowerToTLSGeneralDynamicModel(Op, DAG);
1269}
1270
1271SDValue VETargetLowering::lowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1272 return makeAddress(Op, DAG);
1273}
1274
1275// Lower a f128 load into two f64 loads.
1276static SDValue lowerLoadF128(SDValue Op, SelectionDAG &DAG) {
1277 SDLoc DL(Op);
1278 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Val: Op.getNode());
1279 assert(LdNode && LdNode->getOffset().isUndef() && "Unexpected node type");
1280 Align Alignment = LdNode->getAlign();
1281 if (Alignment > 8)
1282 Alignment = Align(8);
1283
1284 SDValue Lo64 =
1285 DAG.getLoad(VT: MVT::f64, dl: DL, Chain: LdNode->getChain(), Ptr: LdNode->getBasePtr(),
1286 PtrInfo: LdNode->getPointerInfo(), Alignment,
1287 MMOFlags: LdNode->isVolatile() ? MachineMemOperand::MOVolatile
1288 : MachineMemOperand::MONone);
1289 EVT AddrVT = LdNode->getBasePtr().getValueType();
1290 SDValue HiPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: AddrVT, N1: LdNode->getBasePtr(),
1291 N2: DAG.getConstant(Val: 8, DL, VT: AddrVT));
1292 SDValue Hi64 =
1293 DAG.getLoad(VT: MVT::f64, dl: DL, Chain: LdNode->getChain(), Ptr: HiPtr,
1294 PtrInfo: LdNode->getPointerInfo(), Alignment,
1295 MMOFlags: LdNode->isVolatile() ? MachineMemOperand::MOVolatile
1296 : MachineMemOperand::MONone);
1297
1298 SDValue SubRegEven = DAG.getTargetConstant(Val: VE::sub_even, DL, VT: MVT::i32);
1299 SDValue SubRegOdd = DAG.getTargetConstant(Val: VE::sub_odd, DL, VT: MVT::i32);
1300
1301 // VE stores Hi64 to 8(addr) and Lo64 to 0(addr)
1302 SDNode *InFP128 =
1303 DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF, dl: DL, VT: MVT::f128);
1304 InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl: DL, VT: MVT::f128,
1305 Op1: SDValue(InFP128, 0), Op2: Hi64, Op3: SubRegEven);
1306 InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl: DL, VT: MVT::f128,
1307 Op1: SDValue(InFP128, 0), Op2: Lo64, Op3: SubRegOdd);
1308 SDValue OutChains[2] = {SDValue(Lo64.getNode(), 1),
1309 SDValue(Hi64.getNode(), 1)};
1310 SDValue OutChain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: OutChains);
1311 SDValue Ops[2] = {SDValue(InFP128, 0), OutChain};
1312 return DAG.getMergeValues(Ops, dl: DL);
1313}
1314
1315// Lower a vXi1 load into following instructions
1316// LDrii %1, (,%addr)
1317// LVMxir %vm, 0, %1
1318// LDrii %2, 8(,%addr)
1319// LVMxir %vm, 0, %2
1320// ...
1321static SDValue lowerLoadI1(SDValue Op, SelectionDAG &DAG) {
1322 SDLoc DL(Op);
1323 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Val: Op.getNode());
1324 assert(LdNode && LdNode->getOffset().isUndef() && "Unexpected node type");
1325
1326 SDValue BasePtr = LdNode->getBasePtr();
1327 Align Alignment = LdNode->getAlign();
1328 if (Alignment > 8)
1329 Alignment = Align(8);
1330
1331 EVT AddrVT = BasePtr.getValueType();
1332 EVT MemVT = LdNode->getMemoryVT();
1333 if (MemVT == MVT::v256i1 || MemVT == MVT::v4i64) {
1334 SDValue OutChains[4];
1335 SDNode *VM = DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF, dl: DL, VT: MemVT);
1336 for (int i = 0; i < 4; ++i) {
1337 // Generate load dag and prepare chains.
1338 SDValue Addr = DAG.getNode(Opcode: ISD::ADD, DL, VT: AddrVT, N1: BasePtr,
1339 N2: DAG.getConstant(Val: 8 * i, DL, VT: AddrVT));
1340 SDValue Val =
1341 DAG.getLoad(VT: MVT::i64, dl: DL, Chain: LdNode->getChain(), Ptr: Addr,
1342 PtrInfo: LdNode->getPointerInfo(), Alignment,
1343 MMOFlags: LdNode->isVolatile() ? MachineMemOperand::MOVolatile
1344 : MachineMemOperand::MONone);
1345 OutChains[i] = SDValue(Val.getNode(), 1);
1346
1347 VM = DAG.getMachineNode(Opcode: VE::LVMir_m, dl: DL, VT: MVT::i64,
1348 Op1: DAG.getTargetConstant(Val: i, DL, VT: MVT::i64), Op2: Val,
1349 Op3: SDValue(VM, 0));
1350 }
1351 SDValue OutChain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: OutChains);
1352 SDValue Ops[2] = {SDValue(VM, 0), OutChain};
1353 return DAG.getMergeValues(Ops, dl: DL);
1354 } else if (MemVT == MVT::v512i1 || MemVT == MVT::v8i64) {
1355 SDValue OutChains[8];
1356 SDNode *VM = DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF, dl: DL, VT: MemVT);
1357 for (int i = 0; i < 8; ++i) {
1358 // Generate load dag and prepare chains.
1359 SDValue Addr = DAG.getNode(Opcode: ISD::ADD, DL, VT: AddrVT, N1: BasePtr,
1360 N2: DAG.getConstant(Val: 8 * i, DL, VT: AddrVT));
1361 SDValue Val =
1362 DAG.getLoad(VT: MVT::i64, dl: DL, Chain: LdNode->getChain(), Ptr: Addr,
1363 PtrInfo: LdNode->getPointerInfo(), Alignment,
1364 MMOFlags: LdNode->isVolatile() ? MachineMemOperand::MOVolatile
1365 : MachineMemOperand::MONone);
1366 OutChains[i] = SDValue(Val.getNode(), 1);
1367
1368 VM = DAG.getMachineNode(Opcode: VE::LVMyir_y, dl: DL, VT: MVT::i64,
1369 Op1: DAG.getTargetConstant(Val: i, DL, VT: MVT::i64), Op2: Val,
1370 Op3: SDValue(VM, 0));
1371 }
1372 SDValue OutChain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: OutChains);
1373 SDValue Ops[2] = {SDValue(VM, 0), OutChain};
1374 return DAG.getMergeValues(Ops, dl: DL);
1375 } else {
1376 // Otherwise, ask llvm to expand it.
1377 return SDValue();
1378 }
1379}
1380
1381SDValue VETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1382 LoadSDNode *LdNode = cast<LoadSDNode>(Val: Op.getNode());
1383 EVT MemVT = LdNode->getMemoryVT();
1384
1385 // If VPU is enabled, always expand non-mask vector loads to VVP
1386 if (Subtarget->enableVPU() && MemVT.isVector() && !isMaskType(SomeVT: MemVT))
1387 return lowerToVVP(Op, DAG);
1388
1389 SDValue BasePtr = LdNode->getBasePtr();
1390 if (isa<FrameIndexSDNode>(Val: BasePtr.getNode())) {
1391 // Do not expand store instruction with frame index here because of
1392 // dependency problems. We expand it later in eliminateFrameIndex().
1393 return Op;
1394 }
1395
1396 if (MemVT == MVT::f128)
1397 return lowerLoadF128(Op, DAG);
1398 if (isMaskType(SomeVT: MemVT))
1399 return lowerLoadI1(Op, DAG);
1400
1401 return Op;
1402}
1403
1404// Lower a f128 store into two f64 stores.
1405static SDValue lowerStoreF128(SDValue Op, SelectionDAG &DAG) {
1406 SDLoc DL(Op);
1407 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Val: Op.getNode());
1408 assert(StNode && StNode->getOffset().isUndef() && "Unexpected node type");
1409
1410 SDValue SubRegEven = DAG.getTargetConstant(Val: VE::sub_even, DL, VT: MVT::i32);
1411 SDValue SubRegOdd = DAG.getTargetConstant(Val: VE::sub_odd, DL, VT: MVT::i32);
1412
1413 SDNode *Hi64 = DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG, dl: DL, VT: MVT::i64,
1414 Op1: StNode->getValue(), Op2: SubRegEven);
1415 SDNode *Lo64 = DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG, dl: DL, VT: MVT::i64,
1416 Op1: StNode->getValue(), Op2: SubRegOdd);
1417
1418 Align Alignment = StNode->getAlign();
1419 if (Alignment > 8)
1420 Alignment = Align(8);
1421
1422 // VE stores Hi64 to 8(addr) and Lo64 to 0(addr)
1423 SDValue OutChains[2];
1424 OutChains[0] =
1425 DAG.getStore(Chain: StNode->getChain(), dl: DL, Val: SDValue(Lo64, 0),
1426 Ptr: StNode->getBasePtr(), PtrInfo: MachinePointerInfo(), Alignment,
1427 MMOFlags: StNode->isVolatile() ? MachineMemOperand::MOVolatile
1428 : MachineMemOperand::MONone);
1429 EVT AddrVT = StNode->getBasePtr().getValueType();
1430 SDValue HiPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: AddrVT, N1: StNode->getBasePtr(),
1431 N2: DAG.getConstant(Val: 8, DL, VT: AddrVT));
1432 OutChains[1] =
1433 DAG.getStore(Chain: StNode->getChain(), dl: DL, Val: SDValue(Hi64, 0), Ptr: HiPtr,
1434 PtrInfo: MachinePointerInfo(), Alignment,
1435 MMOFlags: StNode->isVolatile() ? MachineMemOperand::MOVolatile
1436 : MachineMemOperand::MONone);
1437 return DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: OutChains);
1438}
1439
1440// Lower a vXi1 store into following instructions
1441// SVMi %1, %vm, 0
1442// STrii %1, (,%addr)
1443// SVMi %2, %vm, 1
1444// STrii %2, 8(,%addr)
1445// ...
1446static SDValue lowerStoreI1(SDValue Op, SelectionDAG &DAG) {
1447 SDLoc DL(Op);
1448 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Val: Op.getNode());
1449 assert(StNode && StNode->getOffset().isUndef() && "Unexpected node type");
1450
1451 SDValue BasePtr = StNode->getBasePtr();
1452 Align Alignment = StNode->getAlign();
1453 if (Alignment > 8)
1454 Alignment = Align(8);
1455 EVT AddrVT = BasePtr.getValueType();
1456 EVT MemVT = StNode->getMemoryVT();
1457 if (MemVT == MVT::v256i1 || MemVT == MVT::v4i64) {
1458 SDValue OutChains[4];
1459 for (int i = 0; i < 4; ++i) {
1460 SDNode *V =
1461 DAG.getMachineNode(Opcode: VE::SVMmi, dl: DL, VT: MVT::i64, Op1: StNode->getValue(),
1462 Op2: DAG.getTargetConstant(Val: i, DL, VT: MVT::i64));
1463 SDValue Addr = DAG.getNode(Opcode: ISD::ADD, DL, VT: AddrVT, N1: BasePtr,
1464 N2: DAG.getConstant(Val: 8 * i, DL, VT: AddrVT));
1465 OutChains[i] =
1466 DAG.getStore(Chain: StNode->getChain(), dl: DL, Val: SDValue(V, 0), Ptr: Addr,
1467 PtrInfo: MachinePointerInfo(), Alignment,
1468 MMOFlags: StNode->isVolatile() ? MachineMemOperand::MOVolatile
1469 : MachineMemOperand::MONone);
1470 }
1471 return DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: OutChains);
1472 } else if (MemVT == MVT::v512i1 || MemVT == MVT::v8i64) {
1473 SDValue OutChains[8];
1474 for (int i = 0; i < 8; ++i) {
1475 SDNode *V =
1476 DAG.getMachineNode(Opcode: VE::SVMyi, dl: DL, VT: MVT::i64, Op1: StNode->getValue(),
1477 Op2: DAG.getTargetConstant(Val: i, DL, VT: MVT::i64));
1478 SDValue Addr = DAG.getNode(Opcode: ISD::ADD, DL, VT: AddrVT, N1: BasePtr,
1479 N2: DAG.getConstant(Val: 8 * i, DL, VT: AddrVT));
1480 OutChains[i] =
1481 DAG.getStore(Chain: StNode->getChain(), dl: DL, Val: SDValue(V, 0), Ptr: Addr,
1482 PtrInfo: MachinePointerInfo(), Alignment,
1483 MMOFlags: StNode->isVolatile() ? MachineMemOperand::MOVolatile
1484 : MachineMemOperand::MONone);
1485 }
1486 return DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: OutChains);
1487 } else {
1488 // Otherwise, ask llvm to expand it.
1489 return SDValue();
1490 }
1491}
1492
1493SDValue VETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1494 StoreSDNode *StNode = cast<StoreSDNode>(Val: Op.getNode());
1495 assert(StNode && StNode->getOffset().isUndef() && "Unexpected node type");
1496 EVT MemVT = StNode->getMemoryVT();
1497
1498 // If VPU is enabled, always expand non-mask vector stores to VVP
1499 if (Subtarget->enableVPU() && MemVT.isVector() && !isMaskType(SomeVT: MemVT))
1500 return lowerToVVP(Op, DAG);
1501
1502 SDValue BasePtr = StNode->getBasePtr();
1503 if (isa<FrameIndexSDNode>(Val: BasePtr.getNode())) {
1504 // Do not expand store instruction with frame index here because of
1505 // dependency problems. We expand it later in eliminateFrameIndex().
1506 return Op;
1507 }
1508
1509 if (MemVT == MVT::f128)
1510 return lowerStoreF128(Op, DAG);
1511 if (isMaskType(SomeVT: MemVT))
1512 return lowerStoreI1(Op, DAG);
1513
1514 // Otherwise, ask llvm to expand it.
1515 return SDValue();
1516}
1517
1518SDValue VETargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1519 MachineFunction &MF = DAG.getMachineFunction();
1520 VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
1521 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
1522
1523 // Need frame address to find the address of VarArgsFrameIndex.
1524 MF.getFrameInfo().setFrameAddressIsTaken(true);
1525
1526 // vastart just stores the address of the VarArgsFrameIndex slot into the
1527 // memory location argument.
1528 SDLoc DL(Op);
1529 SDValue Offset =
1530 DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: DAG.getRegister(Reg: VE::SX9, VT: PtrVT),
1531 N2: DAG.getIntPtrConstant(Val: FuncInfo->getVarArgsFrameOffset(), DL));
1532 const Value *SV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 2))->getValue();
1533 return DAG.getStore(Chain: Op.getOperand(i: 0), dl: DL, Val: Offset, Ptr: Op.getOperand(i: 1),
1534 PtrInfo: MachinePointerInfo(SV));
1535}
1536
1537SDValue VETargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
1538 SDNode *Node = Op.getNode();
1539 EVT VT = Node->getValueType(ResNo: 0);
1540 SDValue InChain = Node->getOperand(Num: 0);
1541 SDValue VAListPtr = Node->getOperand(Num: 1);
1542 EVT PtrVT = VAListPtr.getValueType();
1543 const Value *SV = cast<SrcValueSDNode>(Val: Node->getOperand(Num: 2))->getValue();
1544 SDLoc DL(Node);
1545 SDValue VAList =
1546 DAG.getLoad(VT: PtrVT, dl: DL, Chain: InChain, Ptr: VAListPtr, PtrInfo: MachinePointerInfo(SV));
1547 SDValue Chain = VAList.getValue(R: 1);
1548 SDValue NextPtr;
1549
1550 if (VT == MVT::f128) {
1551 // VE f128 values must be stored with 16 bytes alignment. We don't
1552 // know the actual alignment of VAList, so we take alignment of it
1553 // dynamically.
1554 int Align = 16;
1555 VAList = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: VAList,
1556 N2: DAG.getConstant(Val: Align - 1, DL, VT: PtrVT));
1557 VAList = DAG.getNode(Opcode: ISD::AND, DL, VT: PtrVT, N1: VAList,
1558 N2: DAG.getSignedConstant(Val: -Align, DL, VT: PtrVT));
1559 // Increment the pointer, VAList, by 16 to the next vaarg.
1560 NextPtr =
1561 DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: VAList, N2: DAG.getIntPtrConstant(Val: 16, DL));
1562 } else if (VT == MVT::f32) {
1563 // float --> need special handling like below.
1564 // 0 4
1565 // +------+------+
1566 // | empty| float|
1567 // +------+------+
1568 // Increment the pointer, VAList, by 8 to the next vaarg.
1569 NextPtr =
1570 DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: VAList, N2: DAG.getIntPtrConstant(Val: 8, DL));
1571 // Then, adjust VAList.
1572 unsigned InternalOffset = 4;
1573 VAList = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: VAList,
1574 N2: DAG.getConstant(Val: InternalOffset, DL, VT: PtrVT));
1575 } else {
1576 // Increment the pointer, VAList, by 8 to the next vaarg.
1577 NextPtr =
1578 DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: VAList, N2: DAG.getIntPtrConstant(Val: 8, DL));
1579 }
1580
1581 // Store the incremented VAList to the legalized pointer.
1582 InChain = DAG.getStore(Chain, dl: DL, Val: NextPtr, Ptr: VAListPtr, PtrInfo: MachinePointerInfo(SV));
1583
1584 // Load the actual argument out of the pointer VAList.
1585 // We can't count on greater alignment than the word size.
1586 return DAG.getLoad(
1587 VT, dl: DL, Chain: InChain, Ptr: VAList, PtrInfo: MachinePointerInfo(),
1588 Alignment: Align(std::min(a: PtrVT.getSizeInBits(), b: VT.getSizeInBits()) / 8));
1589}
1590
1591SDValue VETargetLowering::lowerDYNAMIC_STACKALLOC(SDValue Op,
1592 SelectionDAG &DAG) const {
1593 // Generate following code.
1594 // (void)__llvm_grow_stack(size);
1595 // ret = GETSTACKTOP; // pseudo instruction
1596 SDLoc DL(Op);
1597
1598 // Get the inputs.
1599 SDNode *Node = Op.getNode();
1600 SDValue Chain = Op.getOperand(i: 0);
1601 SDValue Size = Op.getOperand(i: 1);
1602 MaybeAlign Alignment(Op.getConstantOperandVal(i: 2));
1603 EVT VT = Node->getValueType(ResNo: 0);
1604
1605 // Chain the dynamic stack allocation so that it doesn't modify the stack
1606 // pointer when other instructions are using the stack.
1607 Chain = DAG.getCALLSEQ_START(Chain, InSize: 0, OutSize: 0, DL);
1608
1609 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
1610 Align StackAlign = TFI.getStackAlign();
1611 bool NeedsAlign = Alignment.valueOrOne() > StackAlign;
1612
1613 // Prepare arguments
1614 TargetLowering::ArgListTy Args;
1615 Args.emplace_back(args&: Size, args: Size.getValueType().getTypeForEVT(Context&: *DAG.getContext()));
1616 if (NeedsAlign) {
1617 SDValue Align = DAG.getConstant(Val: ~(Alignment->value() - 1ULL), DL, VT);
1618 Args.emplace_back(args&: Align,
1619 args: Align.getValueType().getTypeForEVT(Context&: *DAG.getContext()));
1620 }
1621 Type *RetTy = Type::getVoidTy(C&: *DAG.getContext());
1622
1623 EVT PtrVT = Op.getValueType();
1624 SDValue Callee;
1625 if (NeedsAlign) {
1626 Callee = DAG.getTargetExternalSymbol(Sym: "__ve_grow_stack_align", VT: PtrVT, TargetFlags: 0);
1627 } else {
1628 Callee = DAG.getTargetExternalSymbol(Sym: "__ve_grow_stack", VT: PtrVT, TargetFlags: 0);
1629 }
1630
1631 TargetLowering::CallLoweringInfo CLI(DAG);
1632 CLI.setDebugLoc(DL)
1633 .setChain(Chain)
1634 .setCallee(CC: CallingConv::PreserveAll, ResultType: RetTy, Target: Callee, ArgsList: std::move(Args))
1635 .setDiscardResult(true);
1636 std::pair<SDValue, SDValue> pair = LowerCallTo(CLI);
1637 Chain = pair.second;
1638 SDValue Result = DAG.getNode(Opcode: VEISD::GETSTACKTOP, DL, VT, Operand: Chain);
1639 if (NeedsAlign) {
1640 Result = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Result,
1641 N2: DAG.getConstant(Val: (Alignment->value() - 1ULL), DL, VT));
1642 Result = DAG.getNode(Opcode: ISD::AND, DL, VT, N1: Result,
1643 N2: DAG.getConstant(Val: ~(Alignment->value() - 1ULL), DL, VT));
1644 }
1645 // Chain = Result.getValue(1);
1646 Chain = DAG.getCALLSEQ_END(Chain, Size1: 0, Size2: 0, Glue: SDValue(), DL);
1647
1648 SDValue Ops[2] = {Result, Chain};
1649 return DAG.getMergeValues(Ops, dl: DL);
1650}
1651
1652SDValue VETargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
1653 SelectionDAG &DAG) const {
1654 SDLoc DL(Op);
1655 return DAG.getNode(Opcode: VEISD::EH_SJLJ_LONGJMP, DL, VT: MVT::Other, N1: Op.getOperand(i: 0),
1656 N2: Op.getOperand(i: 1));
1657}
1658
1659SDValue VETargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
1660 SelectionDAG &DAG) const {
1661 SDLoc DL(Op);
1662 return DAG.getNode(Opcode: VEISD::EH_SJLJ_SETJMP, DL,
1663 VTList: DAG.getVTList(VT1: MVT::i32, VT2: MVT::Other), N1: Op.getOperand(i: 0),
1664 N2: Op.getOperand(i: 1));
1665}
1666
1667SDValue VETargetLowering::lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
1668 SelectionDAG &DAG) const {
1669 SDLoc DL(Op);
1670 return DAG.getNode(Opcode: VEISD::EH_SJLJ_SETUP_DISPATCH, DL, VT: MVT::Other,
1671 Operand: Op.getOperand(i: 0));
1672}
1673
1674static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
1675 const VETargetLowering &TLI,
1676 const VESubtarget *Subtarget) {
1677 SDLoc DL(Op);
1678 MachineFunction &MF = DAG.getMachineFunction();
1679 EVT PtrVT = TLI.getPointerTy(DL: MF.getDataLayout());
1680
1681 MachineFrameInfo &MFI = MF.getFrameInfo();
1682 MFI.setFrameAddressIsTaken(true);
1683
1684 unsigned Depth = Op.getConstantOperandVal(i: 0);
1685 const VERegisterInfo *RegInfo = Subtarget->getRegisterInfo();
1686 Register FrameReg = RegInfo->getFrameRegister(MF);
1687 SDValue FrameAddr =
1688 DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl: DL, Reg: FrameReg, VT: PtrVT);
1689 while (Depth--)
1690 FrameAddr = DAG.getLoad(VT: Op.getValueType(), dl: DL, Chain: DAG.getEntryNode(),
1691 Ptr: FrameAddr, PtrInfo: MachinePointerInfo());
1692 return FrameAddr;
1693}
1694
1695static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
1696 const VETargetLowering &TLI,
1697 const VESubtarget *Subtarget) {
1698 MachineFunction &MF = DAG.getMachineFunction();
1699 MachineFrameInfo &MFI = MF.getFrameInfo();
1700 MFI.setReturnAddressIsTaken(true);
1701
1702 SDValue FrameAddr = lowerFRAMEADDR(Op, DAG, TLI, Subtarget);
1703
1704 SDLoc DL(Op);
1705 EVT VT = Op.getValueType();
1706 SDValue Offset = DAG.getConstant(Val: 8, DL, VT);
1707 return DAG.getLoad(VT, dl: DL, Chain: DAG.getEntryNode(),
1708 Ptr: DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: FrameAddr, N2: Offset),
1709 PtrInfo: MachinePointerInfo());
1710}
1711
1712SDValue VETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1713 SelectionDAG &DAG) const {
1714 SDLoc DL(Op);
1715 unsigned IntNo = Op.getConstantOperandVal(i: 0);
1716 switch (IntNo) {
1717 default: // Don't custom lower most intrinsics.
1718 return SDValue();
1719 case Intrinsic::eh_sjlj_lsda: {
1720 MachineFunction &MF = DAG.getMachineFunction();
1721 MVT VT = Op.getSimpleValueType();
1722 const VETargetMachine *TM =
1723 static_cast<const VETargetMachine *>(&DAG.getTarget());
1724
1725 // Create GCC_except_tableXX string. The real symbol for that will be
1726 // generated in EHStreamer::emitExceptionTable() later. So, we just
1727 // borrow it's name here.
1728 TM->getStrList()->push_back(x: std::string(
1729 (Twine("GCC_except_table") + Twine(MF.getFunctionNumber())).str()));
1730 SDValue Addr =
1731 DAG.getTargetExternalSymbol(Sym: TM->getStrList()->back().c_str(), VT, TargetFlags: 0);
1732 if (isPositionIndependent()) {
1733 Addr = makeHiLoPair(Op: Addr, HiTF: VE::S_GOTOFF_HI32, LoTF: VE::S_GOTOFF_LO32, DAG);
1734 SDValue GlobalBase = DAG.getNode(Opcode: VEISD::GLOBAL_BASE_REG, DL, VT);
1735 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: GlobalBase, N2: Addr);
1736 }
1737 return makeHiLoPair(Op: Addr, HiTF: VE::S_HI32, LoTF: VE::S_LO32, DAG);
1738 }
1739 }
1740}
1741
1742static bool getUniqueInsertion(SDNode *N, unsigned &UniqueIdx) {
1743 if (!isa<BuildVectorSDNode>(Val: N))
1744 return false;
1745 const auto *BVN = cast<BuildVectorSDNode>(Val: N);
1746
1747 // Find first non-undef insertion.
1748 unsigned Idx;
1749 for (Idx = 0; Idx < BVN->getNumOperands(); ++Idx) {
1750 auto ElemV = BVN->getOperand(Num: Idx);
1751 if (!ElemV->isUndef())
1752 break;
1753 }
1754 // Catch the (hypothetical) all-undef case.
1755 if (Idx == BVN->getNumOperands())
1756 return false;
1757 // Remember insertion.
1758 UniqueIdx = Idx++;
1759 // Verify that all other insertions are undef.
1760 for (; Idx < BVN->getNumOperands(); ++Idx) {
1761 auto ElemV = BVN->getOperand(Num: Idx);
1762 if (!ElemV->isUndef())
1763 return false;
1764 }
1765 return true;
1766}
1767
1768static SDValue getSplatValue(SDNode *N) {
1769 if (auto *BuildVec = dyn_cast<BuildVectorSDNode>(Val: N)) {
1770 return BuildVec->getSplatValue();
1771 }
1772 return SDValue();
1773}
1774
1775SDValue VETargetLowering::lowerBUILD_VECTOR(SDValue Op,
1776 SelectionDAG &DAG) const {
1777 VECustomDAG CDAG(DAG, Op);
1778 MVT ResultVT = Op.getSimpleValueType();
1779
1780 // If there is just one element, expand to INSERT_VECTOR_ELT.
1781 unsigned UniqueIdx;
1782 if (getUniqueInsertion(N: Op.getNode(), UniqueIdx)) {
1783 SDValue AccuV = CDAG.getUNDEF(VT: Op.getValueType());
1784 auto ElemV = Op->getOperand(Num: UniqueIdx);
1785 SDValue IdxV = CDAG.getConstant(Val: UniqueIdx, VT: MVT::i64);
1786 return CDAG.getNode(OC: ISD::INSERT_VECTOR_ELT, ResVT: ResultVT, OpV: {AccuV, ElemV, IdxV});
1787 }
1788
1789 // Else emit a broadcast.
1790 if (SDValue ScalarV = getSplatValue(N: Op.getNode())) {
1791 unsigned NumEls = ResultVT.getVectorNumElements();
1792 auto AVL = CDAG.getConstant(Val: NumEls, VT: MVT::i32);
1793 return CDAG.getBroadcast(ResultVT, Scalar: ScalarV, AVL);
1794 }
1795
1796 // Expand
1797 return SDValue();
1798}
1799
1800TargetLowering::LegalizeAction
1801VETargetLowering::getCustomOperationAction(SDNode &Op) const {
1802 // Custom legalization on VVP_* and VEC_* opcodes is required to pack-legalize
1803 // these operations (transform nodes such that their AVL parameter refers to
1804 // packs of 64bit, instead of number of elements.
1805
1806 // Packing opcodes are created with a pack-legal AVL (LEGALAVL). No need to
1807 // re-visit them.
1808 if (isPackingSupportOpcode(Opc: Op.getOpcode()))
1809 return Legal;
1810
1811 // Custom lower to legalize AVL for packed mode.
1812 if (isVVPOrVEC(Op.getOpcode()))
1813 return Custom;
1814 return Legal;
1815}
1816
1817SDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1818 LLVM_DEBUG(dbgs() << "::LowerOperation "; Op.dump(&DAG));
1819 unsigned Opcode = Op.getOpcode();
1820
1821 /// Scalar isel.
1822 switch (Opcode) {
1823 case ISD::ATOMIC_FENCE:
1824 return lowerATOMIC_FENCE(Op, DAG);
1825 case ISD::ATOMIC_SWAP:
1826 return lowerATOMIC_SWAP(Op, DAG);
1827 case ISD::BlockAddress:
1828 return lowerBlockAddress(Op, DAG);
1829 case ISD::ConstantPool:
1830 return lowerConstantPool(Op, DAG);
1831 case ISD::DYNAMIC_STACKALLOC:
1832 return lowerDYNAMIC_STACKALLOC(Op, DAG);
1833 case ISD::EH_SJLJ_LONGJMP:
1834 return lowerEH_SJLJ_LONGJMP(Op, DAG);
1835 case ISD::EH_SJLJ_SETJMP:
1836 return lowerEH_SJLJ_SETJMP(Op, DAG);
1837 case ISD::EH_SJLJ_SETUP_DISPATCH:
1838 return lowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
1839 case ISD::FRAMEADDR:
1840 return lowerFRAMEADDR(Op, DAG, TLI: *this, Subtarget);
1841 case ISD::GlobalAddress:
1842 return lowerGlobalAddress(Op, DAG);
1843 case ISD::GlobalTLSAddress:
1844 return lowerGlobalTLSAddress(Op, DAG);
1845 case ISD::INTRINSIC_WO_CHAIN:
1846 return lowerINTRINSIC_WO_CHAIN(Op, DAG);
1847 case ISD::JumpTable:
1848 return lowerJumpTable(Op, DAG);
1849 case ISD::LOAD:
1850 return lowerLOAD(Op, DAG);
1851 case ISD::RETURNADDR:
1852 return lowerRETURNADDR(Op, DAG, TLI: *this, Subtarget);
1853 case ISD::BUILD_VECTOR:
1854 return lowerBUILD_VECTOR(Op, DAG);
1855 case ISD::STORE:
1856 return lowerSTORE(Op, DAG);
1857 case ISD::VASTART:
1858 return lowerVASTART(Op, DAG);
1859 case ISD::VAARG:
1860 return lowerVAARG(Op, DAG);
1861
1862 case ISD::INSERT_VECTOR_ELT:
1863 return lowerINSERT_VECTOR_ELT(Op, DAG);
1864 case ISD::EXTRACT_VECTOR_ELT:
1865 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
1866 }
1867
1868 /// Vector isel.
1869 if (ISD::isVPOpcode(Opcode))
1870 return lowerToVVP(Op, DAG);
1871
1872 switch (Opcode) {
1873 default:
1874 llvm_unreachable("Should not custom lower this!");
1875
1876 // Legalize the AVL of this internal node.
1877 case VEISD::VEC_BROADCAST:
1878#define ADD_VVP_OP(VVP_NAME, ...) case VEISD::VVP_NAME:
1879#include "VVPNodes.def"
1880 // AVL already legalized.
1881 if (getAnnotatedNodeAVL(Op).second)
1882 return Op;
1883 return legalizeInternalVectorOp(Op, DAG);
1884
1885 // Translate into a VEC_*/VVP_* layer operation.
1886 case ISD::MLOAD:
1887 case ISD::MSTORE:
1888#define ADD_VVP_OP(VVP_NAME, ISD_NAME) case ISD::ISD_NAME:
1889#include "VVPNodes.def"
1890 if (isMaskArithmetic(Op) && isPackedVectorType(SomeVT: Op.getValueType()))
1891 return splitMaskArithmetic(Op, DAG);
1892 return lowerToVVP(Op, DAG);
1893 }
1894}
1895/// } Custom Lower
1896
1897void VETargetLowering::ReplaceNodeResults(SDNode *N,
1898 SmallVectorImpl<SDValue> &Results,
1899 SelectionDAG &DAG) const {
1900 switch (N->getOpcode()) {
1901 case ISD::ATOMIC_SWAP:
1902 // Let LLVM expand atomic swap instruction through LowerOperation.
1903 return;
1904 default:
1905 LLVM_DEBUG(N->dumpr(&DAG));
1906 llvm_unreachable("Do not know how to custom type legalize this operation!");
1907 }
1908}
1909
1910/// JumpTable for VE.
1911///
1912/// VE cannot generate relocatable symbol in jump table. VE cannot
1913/// generate expressions using symbols in both text segment and data
1914/// segment like below.
1915/// .4byte .LBB0_2-.LJTI0_0
1916/// So, we generate offset from the top of function like below as
1917/// a custom label.
1918/// .4byte .LBB0_2-<function name>
1919
1920unsigned VETargetLowering::getJumpTableEncoding() const {
1921 // Use custom label for PIC.
1922 if (isPositionIndependent())
1923 return MachineJumpTableInfo::EK_Custom32;
1924
1925 // Otherwise, use the normal jump table encoding heuristics.
1926 return TargetLowering::getJumpTableEncoding();
1927}
1928
1929const MCExpr *VETargetLowering::LowerCustomJumpTableEntry(
1930 const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB,
1931 unsigned Uid, MCContext &Ctx) const {
1932 assert(isPositionIndependent());
1933
1934 // Generate custom label for PIC like below.
1935 // .4bytes .LBB0_2-<function name>
1936 const auto *Value = MCSymbolRefExpr::create(Symbol: MBB->getSymbol(), Ctx);
1937 MCSymbol *Sym = Ctx.getOrCreateSymbol(Name: MBB->getParent()->getName().data());
1938 const auto *Base = MCSymbolRefExpr::create(Symbol: Sym, Ctx);
1939 return MCBinaryExpr::createSub(LHS: Value, RHS: Base, Ctx);
1940}
1941
1942SDValue VETargetLowering::getPICJumpTableRelocBase(SDValue Table,
1943 SelectionDAG &DAG) const {
1944 assert(isPositionIndependent());
1945 SDLoc DL(Table);
1946 Function *Function = &DAG.getMachineFunction().getFunction();
1947 assert(Function != nullptr);
1948 auto PtrTy = getPointerTy(DL: DAG.getDataLayout(), AS: Function->getAddressSpace());
1949
1950 // In the jump table, we have following values in PIC mode.
1951 // .4bytes .LBB0_2-<function name>
1952 // We need to add this value and the address of this function to generate
1953 // .LBB0_2 label correctly under PIC mode. So, we want to generate following
1954 // instructions:
1955 // lea %reg, fun@gotoff_lo
1956 // and %reg, %reg, (32)0
1957 // lea.sl %reg, fun@gotoff_hi(%reg, %got)
1958 // In order to do so, we need to genarate correctly marked DAG node using
1959 // makeHiLoPair.
1960 SDValue Op = DAG.getGlobalAddress(GV: Function, DL, VT: PtrTy);
1961 SDValue HiLo = makeHiLoPair(Op, HiTF: VE::S_GOTOFF_HI32, LoTF: VE::S_GOTOFF_LO32, DAG);
1962 SDValue GlobalBase = DAG.getNode(Opcode: VEISD::GLOBAL_BASE_REG, DL, VT: PtrTy);
1963 return DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrTy, N1: GlobalBase, N2: HiLo);
1964}
1965
1966Register VETargetLowering::prepareMBB(MachineBasicBlock &MBB,
1967 MachineBasicBlock::iterator I,
1968 MachineBasicBlock *TargetBB,
1969 const DebugLoc &DL) const {
1970 MachineFunction *MF = MBB.getParent();
1971 MachineRegisterInfo &MRI = MF->getRegInfo();
1972 const VEInstrInfo *TII = Subtarget->getInstrInfo();
1973
1974 const TargetRegisterClass *RC = &VE::I64RegClass;
1975 Register Tmp1 = MRI.createVirtualRegister(RegClass: RC);
1976 Register Tmp2 = MRI.createVirtualRegister(RegClass: RC);
1977 Register Result = MRI.createVirtualRegister(RegClass: RC);
1978
1979 if (isPositionIndependent()) {
1980 // Create following instructions for local linkage PIC code.
1981 // lea %Tmp1, TargetBB@gotoff_lo
1982 // and %Tmp2, %Tmp1, (32)0
1983 // lea.sl %Result, TargetBB@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
1984 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::LEAzii), DestReg: Tmp1)
1985 .addImm(Val: 0)
1986 .addImm(Val: 0)
1987 .addMBB(MBB: TargetBB, TargetFlags: VE::S_GOTOFF_LO32);
1988 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::ANDrm), DestReg: Tmp2)
1989 .addReg(RegNo: Tmp1, Flags: getKillRegState(B: true))
1990 .addImm(Val: M0(Val: 32));
1991 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::LEASLrri), DestReg: Result)
1992 .addReg(RegNo: VE::SX15)
1993 .addReg(RegNo: Tmp2, Flags: getKillRegState(B: true))
1994 .addMBB(MBB: TargetBB, TargetFlags: VE::S_GOTOFF_HI32);
1995 } else {
1996 // Create following instructions for non-PIC code.
1997 // lea %Tmp1, TargetBB@lo
1998 // and %Tmp2, %Tmp1, (32)0
1999 // lea.sl %Result, TargetBB@hi(%Tmp2)
2000 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::LEAzii), DestReg: Tmp1)
2001 .addImm(Val: 0)
2002 .addImm(Val: 0)
2003 .addMBB(MBB: TargetBB, TargetFlags: VE::S_LO32);
2004 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::ANDrm), DestReg: Tmp2)
2005 .addReg(RegNo: Tmp1, Flags: getKillRegState(B: true))
2006 .addImm(Val: M0(Val: 32));
2007 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::LEASLrii), DestReg: Result)
2008 .addReg(RegNo: Tmp2, Flags: getKillRegState(B: true))
2009 .addImm(Val: 0)
2010 .addMBB(MBB: TargetBB, TargetFlags: VE::S_HI32);
2011 }
2012 return Result;
2013}
2014
2015Register VETargetLowering::prepareSymbol(MachineBasicBlock &MBB,
2016 MachineBasicBlock::iterator I,
2017 StringRef Symbol, const DebugLoc &DL,
2018 bool IsLocal = false,
2019 bool IsCall = false) const {
2020 MachineFunction *MF = MBB.getParent();
2021 MachineRegisterInfo &MRI = MF->getRegInfo();
2022 const VEInstrInfo *TII = Subtarget->getInstrInfo();
2023
2024 const TargetRegisterClass *RC = &VE::I64RegClass;
2025 Register Result = MRI.createVirtualRegister(RegClass: RC);
2026
2027 if (isPositionIndependent()) {
2028 if (IsCall && !IsLocal) {
2029 // Create following instructions for non-local linkage PIC code function
2030 // calls. These instructions uses IC and magic number -24, so we expand
2031 // them in VEAsmPrinter.cpp from GETFUNPLT pseudo instruction.
2032 // lea %Reg, Symbol@plt_lo(-24)
2033 // and %Reg, %Reg, (32)0
2034 // sic %s16
2035 // lea.sl %Result, Symbol@plt_hi(%Reg, %s16) ; %s16 is PLT
2036 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::GETFUNPLT), DestReg: Result)
2037 .addExternalSymbol(FnName: "abort");
2038 } else if (IsLocal) {
2039 Register Tmp1 = MRI.createVirtualRegister(RegClass: RC);
2040 Register Tmp2 = MRI.createVirtualRegister(RegClass: RC);
2041 // Create following instructions for local linkage PIC code.
2042 // lea %Tmp1, Symbol@gotoff_lo
2043 // and %Tmp2, %Tmp1, (32)0
2044 // lea.sl %Result, Symbol@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
2045 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::LEAzii), DestReg: Tmp1)
2046 .addImm(Val: 0)
2047 .addImm(Val: 0)
2048 .addExternalSymbol(FnName: Symbol.data(), TargetFlags: VE::S_GOTOFF_LO32);
2049 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::ANDrm), DestReg: Tmp2)
2050 .addReg(RegNo: Tmp1, Flags: getKillRegState(B: true))
2051 .addImm(Val: M0(Val: 32));
2052 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::LEASLrri), DestReg: Result)
2053 .addReg(RegNo: VE::SX15)
2054 .addReg(RegNo: Tmp2, Flags: getKillRegState(B: true))
2055 .addExternalSymbol(FnName: Symbol.data(), TargetFlags: VE::S_GOTOFF_HI32);
2056 } else {
2057 Register Tmp1 = MRI.createVirtualRegister(RegClass: RC);
2058 Register Tmp2 = MRI.createVirtualRegister(RegClass: RC);
2059 // Create following instructions for not local linkage PIC code.
2060 // lea %Tmp1, Symbol@got_lo
2061 // and %Tmp2, %Tmp1, (32)0
2062 // lea.sl %Tmp3, Symbol@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
2063 // ld %Result, 0(%Tmp3)
2064 Register Tmp3 = MRI.createVirtualRegister(RegClass: RC);
2065 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::LEAzii), DestReg: Tmp1)
2066 .addImm(Val: 0)
2067 .addImm(Val: 0)
2068 .addExternalSymbol(FnName: Symbol.data(), TargetFlags: VE::S_GOT_LO32);
2069 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::ANDrm), DestReg: Tmp2)
2070 .addReg(RegNo: Tmp1, Flags: getKillRegState(B: true))
2071 .addImm(Val: M0(Val: 32));
2072 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::LEASLrri), DestReg: Tmp3)
2073 .addReg(RegNo: VE::SX15)
2074 .addReg(RegNo: Tmp2, Flags: getKillRegState(B: true))
2075 .addExternalSymbol(FnName: Symbol.data(), TargetFlags: VE::S_GOT_HI32);
2076 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::LDrii), DestReg: Result)
2077 .addReg(RegNo: Tmp3, Flags: getKillRegState(B: true))
2078 .addImm(Val: 0)
2079 .addImm(Val: 0);
2080 }
2081 } else {
2082 Register Tmp1 = MRI.createVirtualRegister(RegClass: RC);
2083 Register Tmp2 = MRI.createVirtualRegister(RegClass: RC);
2084 // Create following instructions for non-PIC code.
2085 // lea %Tmp1, Symbol@lo
2086 // and %Tmp2, %Tmp1, (32)0
2087 // lea.sl %Result, Symbol@hi(%Tmp2)
2088 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::LEAzii), DestReg: Tmp1)
2089 .addImm(Val: 0)
2090 .addImm(Val: 0)
2091 .addExternalSymbol(FnName: Symbol.data(), TargetFlags: VE::S_LO32);
2092 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::ANDrm), DestReg: Tmp2)
2093 .addReg(RegNo: Tmp1, Flags: getKillRegState(B: true))
2094 .addImm(Val: M0(Val: 32));
2095 BuildMI(BB&: MBB, I, MIMD: DL, MCID: TII->get(Opcode: VE::LEASLrii), DestReg: Result)
2096 .addReg(RegNo: Tmp2, Flags: getKillRegState(B: true))
2097 .addImm(Val: 0)
2098 .addExternalSymbol(FnName: Symbol.data(), TargetFlags: VE::S_HI32);
2099 }
2100 return Result;
2101}
2102
2103void VETargetLowering::setupEntryBlockForSjLj(MachineInstr &MI,
2104 MachineBasicBlock *MBB,
2105 MachineBasicBlock *DispatchBB,
2106 int FI, int Offset) const {
2107 DebugLoc DL = MI.getDebugLoc();
2108 const VEInstrInfo *TII = Subtarget->getInstrInfo();
2109
2110 Register LabelReg =
2111 prepareMBB(MBB&: *MBB, I: MachineBasicBlock::iterator(MI), TargetBB: DispatchBB, DL);
2112
2113 // Store an address of DispatchBB to a given jmpbuf[1] where has next IC
2114 // referenced by longjmp (throw) later.
2115 MachineInstrBuilder MIB = BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: VE::STrii));
2116 addFrameReference(MIB, FI, Offset); // jmpbuf[1]
2117 MIB.addReg(RegNo: LabelReg, Flags: getKillRegState(B: true));
2118}
2119
2120MachineBasicBlock *
2121VETargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
2122 MachineBasicBlock *MBB) const {
2123 DebugLoc DL = MI.getDebugLoc();
2124 MachineFunction *MF = MBB->getParent();
2125 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2126 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
2127 MachineRegisterInfo &MRI = MF->getRegInfo();
2128
2129 const BasicBlock *BB = MBB->getBasicBlock();
2130 MachineFunction::iterator I = ++MBB->getIterator();
2131
2132 // Memory Reference.
2133 SmallVector<MachineMemOperand *, 2> MMOs(MI.memoperands());
2134 Register BufReg = MI.getOperand(i: 1).getReg();
2135
2136 Register DstReg;
2137
2138 DstReg = MI.getOperand(i: 0).getReg();
2139 const TargetRegisterClass *RC = MRI.getRegClass(Reg: DstReg);
2140 assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!");
2141 (void)TRI;
2142 Register MainDestReg = MRI.createVirtualRegister(RegClass: RC);
2143 Register RestoreDestReg = MRI.createVirtualRegister(RegClass: RC);
2144
2145 // For `v = call @llvm.eh.sjlj.setjmp(buf)`, we generate following
2146 // instructions. SP/FP must be saved in jmpbuf before `llvm.eh.sjlj.setjmp`.
2147 //
2148 // ThisMBB:
2149 // buf[3] = %s17 iff %s17 is used as BP
2150 // buf[1] = RestoreMBB as IC after longjmp
2151 // # SjLjSetup RestoreMBB
2152 //
2153 // MainMBB:
2154 // v_main = 0
2155 //
2156 // SinkMBB:
2157 // v = phi(v_main, MainMBB, v_restore, RestoreMBB)
2158 // ...
2159 //
2160 // RestoreMBB:
2161 // %s17 = buf[3] = iff %s17 is used as BP
2162 // v_restore = 1
2163 // goto SinkMBB
2164
2165 MachineBasicBlock *ThisMBB = MBB;
2166 MachineBasicBlock *MainMBB = MF->CreateMachineBasicBlock(BB);
2167 MachineBasicBlock *SinkMBB = MF->CreateMachineBasicBlock(BB);
2168 MachineBasicBlock *RestoreMBB = MF->CreateMachineBasicBlock(BB);
2169 MF->insert(MBBI: I, MBB: MainMBB);
2170 MF->insert(MBBI: I, MBB: SinkMBB);
2171 MF->push_back(MBB: RestoreMBB);
2172 RestoreMBB->setMachineBlockAddressTaken();
2173
2174 // Transfer the remainder of BB and its successor edges to SinkMBB.
2175 SinkMBB->splice(Where: SinkMBB->begin(), Other: MBB,
2176 From: std::next(x: MachineBasicBlock::iterator(MI)), To: MBB->end());
2177 SinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: MBB);
2178
2179 // ThisMBB:
2180 Register LabelReg =
2181 prepareMBB(MBB&: *MBB, I: MachineBasicBlock::iterator(MI), TargetBB: RestoreMBB, DL);
2182
2183 // Store BP in buf[3] iff this function is using BP.
2184 const VEFrameLowering *TFI = Subtarget->getFrameLowering();
2185 if (TFI->hasBP(MF: *MF)) {
2186 MachineInstrBuilder MIB = BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: VE::STrii));
2187 MIB.addReg(RegNo: BufReg);
2188 MIB.addImm(Val: 0);
2189 MIB.addImm(Val: 24);
2190 MIB.addReg(RegNo: VE::SX17);
2191 MIB.setMemRefs(MMOs);
2192 }
2193
2194 // Store IP in buf[1].
2195 MachineInstrBuilder MIB = BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: VE::STrii));
2196 MIB.add(MO: MI.getOperand(i: 1)); // we can preserve the kill flags here.
2197 MIB.addImm(Val: 0);
2198 MIB.addImm(Val: 8);
2199 MIB.addReg(RegNo: LabelReg, Flags: getKillRegState(B: true));
2200 MIB.setMemRefs(MMOs);
2201
2202 // SP/FP are already stored in jmpbuf before `llvm.eh.sjlj.setjmp`.
2203
2204 // Insert setup.
2205 MIB =
2206 BuildMI(BB&: *ThisMBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: VE::EH_SjLj_Setup)).addMBB(MBB: RestoreMBB);
2207
2208 const VERegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2209 MIB.addRegMask(Mask: RegInfo->getNoPreservedMask());
2210 ThisMBB->addSuccessor(Succ: MainMBB);
2211 ThisMBB->addSuccessor(Succ: RestoreMBB);
2212
2213 // MainMBB:
2214 BuildMI(BB: MainMBB, MIMD: DL, MCID: TII->get(Opcode: VE::LEAzii), DestReg: MainDestReg)
2215 .addImm(Val: 0)
2216 .addImm(Val: 0)
2217 .addImm(Val: 0);
2218 MainMBB->addSuccessor(Succ: SinkMBB);
2219
2220 // SinkMBB:
2221 BuildMI(BB&: *SinkMBB, I: SinkMBB->begin(), MIMD: DL, MCID: TII->get(Opcode: VE::PHI), DestReg: DstReg)
2222 .addReg(RegNo: MainDestReg)
2223 .addMBB(MBB: MainMBB)
2224 .addReg(RegNo: RestoreDestReg)
2225 .addMBB(MBB: RestoreMBB);
2226
2227 // RestoreMBB:
2228 // Restore BP from buf[3] iff this function is using BP. The address of
2229 // buf is in SX10.
2230 // FIXME: Better to not use SX10 here
2231 if (TFI->hasBP(MF: *MF)) {
2232 MachineInstrBuilder MIB =
2233 BuildMI(BB: RestoreMBB, MIMD: DL, MCID: TII->get(Opcode: VE::LDrii), DestReg: VE::SX17);
2234 MIB.addReg(RegNo: VE::SX10);
2235 MIB.addImm(Val: 0);
2236 MIB.addImm(Val: 24);
2237 MIB.setMemRefs(MMOs);
2238 }
2239 BuildMI(BB: RestoreMBB, MIMD: DL, MCID: TII->get(Opcode: VE::LEAzii), DestReg: RestoreDestReg)
2240 .addImm(Val: 0)
2241 .addImm(Val: 0)
2242 .addImm(Val: 1);
2243 BuildMI(BB: RestoreMBB, MIMD: DL, MCID: TII->get(Opcode: VE::BRCFLa_t)).addMBB(MBB: SinkMBB);
2244 RestoreMBB->addSuccessor(Succ: SinkMBB);
2245
2246 MI.eraseFromParent();
2247 return SinkMBB;
2248}
2249
2250MachineBasicBlock *
2251VETargetLowering::emitEHSjLjLongJmp(MachineInstr &MI,
2252 MachineBasicBlock *MBB) const {
2253 DebugLoc DL = MI.getDebugLoc();
2254 MachineFunction *MF = MBB->getParent();
2255 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2256 MachineRegisterInfo &MRI = MF->getRegInfo();
2257
2258 // Memory Reference.
2259 SmallVector<MachineMemOperand *, 2> MMOs(MI.memoperands());
2260 Register BufReg = MI.getOperand(i: 0).getReg();
2261
2262 Register Tmp = MRI.createVirtualRegister(RegClass: &VE::I64RegClass);
2263 // Since FP is only updated here but NOT referenced, it's treated as GPR.
2264 Register FP = VE::SX9;
2265 Register SP = VE::SX11;
2266
2267 MachineInstrBuilder MIB;
2268
2269 MachineBasicBlock *ThisMBB = MBB;
2270
2271 // For `call @llvm.eh.sjlj.longjmp(buf)`, we generate following instructions.
2272 //
2273 // ThisMBB:
2274 // %fp = load buf[0]
2275 // %jmp = load buf[1]
2276 // %s10 = buf ; Store an address of buf to SX10 for RestoreMBB
2277 // %sp = load buf[2] ; generated by llvm.eh.sjlj.setjmp.
2278 // jmp %jmp
2279
2280 // Reload FP.
2281 MIB = BuildMI(BB&: *ThisMBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: VE::LDrii), DestReg: FP);
2282 MIB.addReg(RegNo: BufReg);
2283 MIB.addImm(Val: 0);
2284 MIB.addImm(Val: 0);
2285 MIB.setMemRefs(MMOs);
2286
2287 // Reload IP.
2288 MIB = BuildMI(BB&: *ThisMBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: VE::LDrii), DestReg: Tmp);
2289 MIB.addReg(RegNo: BufReg);
2290 MIB.addImm(Val: 0);
2291 MIB.addImm(Val: 8);
2292 MIB.setMemRefs(MMOs);
2293
2294 // Copy BufReg to SX10 for later use in setjmp.
2295 // FIXME: Better to not use SX10 here
2296 BuildMI(BB&: *ThisMBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: VE::ORri), DestReg: VE::SX10)
2297 .addReg(RegNo: BufReg)
2298 .addImm(Val: 0);
2299
2300 // Reload SP.
2301 MIB = BuildMI(BB&: *ThisMBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: VE::LDrii), DestReg: SP);
2302 MIB.add(MO: MI.getOperand(i: 0)); // we can preserve the kill flags here.
2303 MIB.addImm(Val: 0);
2304 MIB.addImm(Val: 16);
2305 MIB.setMemRefs(MMOs);
2306
2307 // Jump.
2308 BuildMI(BB&: *ThisMBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: VE::BCFLari_t))
2309 .addReg(RegNo: Tmp, Flags: getKillRegState(B: true))
2310 .addImm(Val: 0);
2311
2312 MI.eraseFromParent();
2313 return ThisMBB;
2314}
2315
2316MachineBasicBlock *
2317VETargetLowering::emitSjLjDispatchBlock(MachineInstr &MI,
2318 MachineBasicBlock *BB) const {
2319 DebugLoc DL = MI.getDebugLoc();
2320 MachineFunction *MF = BB->getParent();
2321 MachineFrameInfo &MFI = MF->getFrameInfo();
2322 MachineRegisterInfo &MRI = MF->getRegInfo();
2323 const VEInstrInfo *TII = Subtarget->getInstrInfo();
2324 int FI = MFI.getFunctionContextIndex();
2325
2326 // Get a mapping of the call site numbers to all of the landing pads they're
2327 // associated with.
2328 DenseMap<unsigned, SmallVector<MachineBasicBlock *, 2>> CallSiteNumToLPad;
2329 unsigned MaxCSNum = 0;
2330 for (auto &MBB : *MF) {
2331 if (!MBB.isEHPad())
2332 continue;
2333
2334 MCSymbol *Sym = nullptr;
2335 for (const auto &MI : MBB) {
2336 if (MI.isDebugInstr())
2337 continue;
2338
2339 assert(MI.isEHLabel() && "expected EH_LABEL");
2340 Sym = MI.getOperand(i: 0).getMCSymbol();
2341 break;
2342 }
2343
2344 if (!MF->hasCallSiteLandingPad(Sym))
2345 continue;
2346
2347 for (unsigned CSI : MF->getCallSiteLandingPad(Sym)) {
2348 CallSiteNumToLPad[CSI].push_back(Elt: &MBB);
2349 MaxCSNum = std::max(a: MaxCSNum, b: CSI);
2350 }
2351 }
2352
2353 // Get an ordered list of the machine basic blocks for the jump table.
2354 std::vector<MachineBasicBlock *> LPadList;
2355 SmallPtrSet<MachineBasicBlock *, 32> InvokeBBs;
2356 LPadList.reserve(n: CallSiteNumToLPad.size());
2357
2358 for (unsigned CSI = 1; CSI <= MaxCSNum; ++CSI) {
2359 for (auto &LP : CallSiteNumToLPad[CSI]) {
2360 LPadList.push_back(x: LP);
2361 InvokeBBs.insert_range(R: LP->predecessors());
2362 }
2363 }
2364
2365 assert(!LPadList.empty() &&
2366 "No landing pad destinations for the dispatch jump table!");
2367
2368 // The %fn_context is allocated like below (from --print-after=sjljehprepare):
2369 // %fn_context = alloca { i8*, i64, [4 x i64], i8*, i8*, [5 x i8*] }
2370 //
2371 // This `[5 x i8*]` is jmpbuf, so jmpbuf[1] is FI+72.
2372 // First `i64` is callsite, so callsite is FI+8.
2373 static const int OffsetIC = 72;
2374 static const int OffsetCS = 8;
2375
2376 // Create the MBBs for the dispatch code like following:
2377 //
2378 // ThisMBB:
2379 // Prepare DispatchBB address and store it to buf[1].
2380 // ...
2381 //
2382 // DispatchBB:
2383 // %s15 = GETGOT iff isPositionIndependent
2384 // %callsite = load callsite
2385 // brgt.l.t #size of callsites, %callsite, DispContBB
2386 //
2387 // TrapBB:
2388 // Call abort.
2389 //
2390 // DispContBB:
2391 // %breg = address of jump table
2392 // %pc = load and calculate next pc from %breg and %callsite
2393 // jmp %pc
2394
2395 // Shove the dispatch's address into the return slot in the function context.
2396 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
2397 DispatchBB->setIsEHPad(true);
2398
2399 // Trap BB will causes trap like `assert(0)`.
2400 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
2401 DispatchBB->addSuccessor(Succ: TrapBB);
2402
2403 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
2404 DispatchBB->addSuccessor(Succ: DispContBB);
2405
2406 // Insert MBBs.
2407 MF->push_back(MBB: DispatchBB);
2408 MF->push_back(MBB: DispContBB);
2409 MF->push_back(MBB: TrapBB);
2410
2411 // Insert code to call abort in the TrapBB.
2412 Register Abort = prepareSymbol(MBB&: *TrapBB, I: TrapBB->end(), Symbol: "abort", DL,
2413 /* Local */ IsLocal: false, /* Call */ IsCall: true);
2414 BuildMI(BB: TrapBB, MIMD: DL, MCID: TII->get(Opcode: VE::BSICrii), DestReg: VE::SX10)
2415 .addReg(RegNo: Abort, Flags: getKillRegState(B: true))
2416 .addImm(Val: 0)
2417 .addImm(Val: 0);
2418
2419 // Insert code into the entry block that creates and registers the function
2420 // context.
2421 setupEntryBlockForSjLj(MI, MBB: BB, DispatchBB, FI, Offset: OffsetIC);
2422
2423 // Create the jump table and associated information
2424 unsigned JTE = getJumpTableEncoding();
2425 MachineJumpTableInfo *JTI = MF->getOrCreateJumpTableInfo(JTEntryKind: JTE);
2426 unsigned MJTI = JTI->createJumpTableIndex(DestBBs: LPadList);
2427
2428 const VERegisterInfo &RI = TII->getRegisterInfo();
2429 // Add a register mask with no preserved registers. This results in all
2430 // registers being marked as clobbered.
2431 BuildMI(BB: DispatchBB, MIMD: DL, MCID: TII->get(Opcode: VE::NOP))
2432 .addRegMask(Mask: RI.getNoPreservedMask());
2433
2434 if (isPositionIndependent()) {
2435 // Force to generate GETGOT, since current implementation doesn't store GOT
2436 // register.
2437 BuildMI(BB: DispatchBB, MIMD: DL, MCID: TII->get(Opcode: VE::GETGOT), DestReg: VE::SX15);
2438 }
2439
2440 // IReg is used as an index in a memory operand and therefore can't be SP
2441 const TargetRegisterClass *RC = &VE::I64RegClass;
2442 Register IReg = MRI.createVirtualRegister(RegClass: RC);
2443 addFrameReference(MIB: BuildMI(BB: DispatchBB, MIMD: DL, MCID: TII->get(Opcode: VE::LDLZXrii), DestReg: IReg), FI,
2444 Offset: OffsetCS);
2445 if (LPadList.size() < 64) {
2446 BuildMI(BB: DispatchBB, MIMD: DL, MCID: TII->get(Opcode: VE::BRCFLir_t))
2447 .addImm(Val: VECC::CC_ILE)
2448 .addImm(Val: LPadList.size())
2449 .addReg(RegNo: IReg)
2450 .addMBB(MBB: TrapBB);
2451 } else {
2452 assert(LPadList.size() <= 0x7FFFFFFF && "Too large Landing Pad!");
2453 Register TmpReg = MRI.createVirtualRegister(RegClass: RC);
2454 BuildMI(BB: DispatchBB, MIMD: DL, MCID: TII->get(Opcode: VE::LEAzii), DestReg: TmpReg)
2455 .addImm(Val: 0)
2456 .addImm(Val: 0)
2457 .addImm(Val: LPadList.size());
2458 BuildMI(BB: DispatchBB, MIMD: DL, MCID: TII->get(Opcode: VE::BRCFLrr_t))
2459 .addImm(Val: VECC::CC_ILE)
2460 .addReg(RegNo: TmpReg, Flags: getKillRegState(B: true))
2461 .addReg(RegNo: IReg)
2462 .addMBB(MBB: TrapBB);
2463 }
2464
2465 Register BReg = MRI.createVirtualRegister(RegClass: RC);
2466 Register Tmp1 = MRI.createVirtualRegister(RegClass: RC);
2467 Register Tmp2 = MRI.createVirtualRegister(RegClass: RC);
2468
2469 if (isPositionIndependent()) {
2470 // Create following instructions for local linkage PIC code.
2471 // lea %Tmp1, .LJTI0_0@gotoff_lo
2472 // and %Tmp2, %Tmp1, (32)0
2473 // lea.sl %BReg, .LJTI0_0@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
2474 BuildMI(BB: DispContBB, MIMD: DL, MCID: TII->get(Opcode: VE::LEAzii), DestReg: Tmp1)
2475 .addImm(Val: 0)
2476 .addImm(Val: 0)
2477 .addJumpTableIndex(Idx: MJTI, TargetFlags: VE::S_GOTOFF_LO32);
2478 BuildMI(BB: DispContBB, MIMD: DL, MCID: TII->get(Opcode: VE::ANDrm), DestReg: Tmp2)
2479 .addReg(RegNo: Tmp1, Flags: getKillRegState(B: true))
2480 .addImm(Val: M0(Val: 32));
2481 BuildMI(BB: DispContBB, MIMD: DL, MCID: TII->get(Opcode: VE::LEASLrri), DestReg: BReg)
2482 .addReg(RegNo: VE::SX15)
2483 .addReg(RegNo: Tmp2, Flags: getKillRegState(B: true))
2484 .addJumpTableIndex(Idx: MJTI, TargetFlags: VE::S_GOTOFF_HI32);
2485 } else {
2486 // Create following instructions for non-PIC code.
2487 // lea %Tmp1, .LJTI0_0@lo
2488 // and %Tmp2, %Tmp1, (32)0
2489 // lea.sl %BReg, .LJTI0_0@hi(%Tmp2)
2490 BuildMI(BB: DispContBB, MIMD: DL, MCID: TII->get(Opcode: VE::LEAzii), DestReg: Tmp1)
2491 .addImm(Val: 0)
2492 .addImm(Val: 0)
2493 .addJumpTableIndex(Idx: MJTI, TargetFlags: VE::S_LO32);
2494 BuildMI(BB: DispContBB, MIMD: DL, MCID: TII->get(Opcode: VE::ANDrm), DestReg: Tmp2)
2495 .addReg(RegNo: Tmp1, Flags: getKillRegState(B: true))
2496 .addImm(Val: M0(Val: 32));
2497 BuildMI(BB: DispContBB, MIMD: DL, MCID: TII->get(Opcode: VE::LEASLrii), DestReg: BReg)
2498 .addReg(RegNo: Tmp2, Flags: getKillRegState(B: true))
2499 .addImm(Val: 0)
2500 .addJumpTableIndex(Idx: MJTI, TargetFlags: VE::S_HI32);
2501 }
2502
2503 switch (JTE) {
2504 case MachineJumpTableInfo::EK_BlockAddress: {
2505 // Generate simple block address code for no-PIC model.
2506 // sll %Tmp1, %IReg, 3
2507 // lds %TReg, 0(%Tmp1, %BReg)
2508 // bcfla %TReg
2509
2510 Register TReg = MRI.createVirtualRegister(RegClass: RC);
2511 Register Tmp1 = MRI.createVirtualRegister(RegClass: RC);
2512
2513 BuildMI(BB: DispContBB, MIMD: DL, MCID: TII->get(Opcode: VE::SLLri), DestReg: Tmp1)
2514 .addReg(RegNo: IReg, Flags: getKillRegState(B: true))
2515 .addImm(Val: 3);
2516 BuildMI(BB: DispContBB, MIMD: DL, MCID: TII->get(Opcode: VE::LDrri), DestReg: TReg)
2517 .addReg(RegNo: BReg, Flags: getKillRegState(B: true))
2518 .addReg(RegNo: Tmp1, Flags: getKillRegState(B: true))
2519 .addImm(Val: 0);
2520 BuildMI(BB: DispContBB, MIMD: DL, MCID: TII->get(Opcode: VE::BCFLari_t))
2521 .addReg(RegNo: TReg, Flags: getKillRegState(B: true))
2522 .addImm(Val: 0);
2523 break;
2524 }
2525 case MachineJumpTableInfo::EK_Custom32: {
2526 // Generate block address code using differences from the function pointer
2527 // for PIC model.
2528 // sll %Tmp1, %IReg, 2
2529 // ldl.zx %OReg, 0(%Tmp1, %BReg)
2530 // Prepare function address in BReg2.
2531 // adds.l %TReg, %BReg2, %OReg
2532 // bcfla %TReg
2533
2534 assert(isPositionIndependent());
2535 Register OReg = MRI.createVirtualRegister(RegClass: RC);
2536 Register TReg = MRI.createVirtualRegister(RegClass: RC);
2537 Register Tmp1 = MRI.createVirtualRegister(RegClass: RC);
2538
2539 BuildMI(BB: DispContBB, MIMD: DL, MCID: TII->get(Opcode: VE::SLLri), DestReg: Tmp1)
2540 .addReg(RegNo: IReg, Flags: getKillRegState(B: true))
2541 .addImm(Val: 2);
2542 BuildMI(BB: DispContBB, MIMD: DL, MCID: TII->get(Opcode: VE::LDLZXrri), DestReg: OReg)
2543 .addReg(RegNo: BReg, Flags: getKillRegState(B: true))
2544 .addReg(RegNo: Tmp1, Flags: getKillRegState(B: true))
2545 .addImm(Val: 0);
2546 Register BReg2 =
2547 prepareSymbol(MBB&: *DispContBB, I: DispContBB->end(),
2548 Symbol: DispContBB->getParent()->getName(), DL, /* Local */ IsLocal: true);
2549 BuildMI(BB: DispContBB, MIMD: DL, MCID: TII->get(Opcode: VE::ADDSLrr), DestReg: TReg)
2550 .addReg(RegNo: OReg, Flags: getKillRegState(B: true))
2551 .addReg(RegNo: BReg2, Flags: getKillRegState(B: true));
2552 BuildMI(BB: DispContBB, MIMD: DL, MCID: TII->get(Opcode: VE::BCFLari_t))
2553 .addReg(RegNo: TReg, Flags: getKillRegState(B: true))
2554 .addImm(Val: 0);
2555 break;
2556 }
2557 default:
2558 llvm_unreachable("Unexpected jump table encoding");
2559 }
2560
2561 // Add the jump table entries as successors to the MBB.
2562 SmallPtrSet<MachineBasicBlock *, 8> SeenMBBs;
2563 for (auto &LP : LPadList)
2564 if (SeenMBBs.insert(Ptr: LP).second)
2565 DispContBB->addSuccessor(Succ: LP);
2566
2567 // N.B. the order the invoke BBs are processed in doesn't matter here.
2568 SmallVector<MachineBasicBlock *, 64> MBBLPads;
2569 const MCPhysReg *SavedRegs = MF->getRegInfo().getCalleeSavedRegs();
2570 for (MachineBasicBlock *MBB : InvokeBBs) {
2571 // Remove the landing pad successor from the invoke block and replace it
2572 // with the new dispatch block.
2573 // Keep a copy of Successors since it's modified inside the loop.
2574 SmallVector<MachineBasicBlock *, 8> Successors(MBB->succ_rbegin(),
2575 MBB->succ_rend());
2576 // FIXME: Avoid quadratic complexity.
2577 for (auto *MBBS : Successors) {
2578 if (MBBS->isEHPad()) {
2579 MBB->removeSuccessor(Succ: MBBS);
2580 MBBLPads.push_back(Elt: MBBS);
2581 }
2582 }
2583
2584 MBB->addSuccessor(Succ: DispatchBB);
2585
2586 // Find the invoke call and mark all of the callee-saved registers as
2587 // 'implicit defined' so that they're spilled. This prevents code from
2588 // moving instructions to before the EH block, where they will never be
2589 // executed.
2590 for (auto &II : reverse(C&: *MBB)) {
2591 if (!II.isCall())
2592 continue;
2593
2594 DenseSet<Register> DefRegs;
2595 for (auto &MOp : II.operands())
2596 if (MOp.isReg())
2597 DefRegs.insert(V: MOp.getReg());
2598
2599 MachineInstrBuilder MIB(*MF, &II);
2600 for (unsigned RI = 0; SavedRegs[RI]; ++RI) {
2601 Register Reg = SavedRegs[RI];
2602 if (!DefRegs.contains(V: Reg))
2603 MIB.addReg(RegNo: Reg, Flags: RegState::ImplicitDefine | RegState::Dead);
2604 }
2605
2606 break;
2607 }
2608 }
2609
2610 // Mark all former landing pads as non-landing pads. The dispatch is the only
2611 // landing pad now.
2612 for (auto &LP : MBBLPads)
2613 LP->setIsEHPad(false);
2614
2615 // The instruction is gone now.
2616 MI.eraseFromParent();
2617 return BB;
2618}
2619
2620MachineBasicBlock *
2621VETargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
2622 MachineBasicBlock *BB) const {
2623 switch (MI.getOpcode()) {
2624 default:
2625 llvm_unreachable("Unknown Custom Instruction!");
2626 case VE::EH_SjLj_LongJmp:
2627 return emitEHSjLjLongJmp(MI, MBB: BB);
2628 case VE::EH_SjLj_SetJmp:
2629 return emitEHSjLjSetJmp(MI, MBB: BB);
2630 case VE::EH_SjLj_Setup_Dispatch:
2631 return emitSjLjDispatchBlock(MI, BB);
2632 }
2633}
2634
2635static bool isSimm7(SDValue V) {
2636 EVT VT = V.getValueType();
2637 if (VT.isVector())
2638 return false;
2639
2640 if (VT.isInteger()) {
2641 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: V))
2642 return isInt<7>(x: C->getSExtValue());
2643 } else if (VT.isFloatingPoint()) {
2644 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val&: V)) {
2645 if (VT == MVT::f32 || VT == MVT::f64) {
2646 const APInt &Imm = C->getValueAPF().bitcastToAPInt();
2647 uint64_t Val = Imm.getSExtValue();
2648 if (Imm.getBitWidth() == 32)
2649 Val <<= 32; // Immediate value of float place at higher bits on VE.
2650 return isInt<7>(x: Val);
2651 }
2652 }
2653 }
2654 return false;
2655}
2656
2657static bool isMImm(SDValue V) {
2658 EVT VT = V.getValueType();
2659 if (VT.isVector())
2660 return false;
2661
2662 if (VT.isInteger()) {
2663 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: V))
2664 return isMImmVal(Val: getImmVal(N: C));
2665 } else if (VT.isFloatingPoint()) {
2666 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val&: V)) {
2667 if (VT == MVT::f32) {
2668 // Float value places at higher bits, so ignore lower 32 bits.
2669 return isMImm32Val(Val: getFpImmVal(N: C) >> 32);
2670 } else if (VT == MVT::f64) {
2671 return isMImmVal(Val: getFpImmVal(N: C));
2672 }
2673 }
2674 }
2675 return false;
2676}
2677
2678static unsigned decideComp(EVT SrcVT, ISD::CondCode CC) {
2679 if (SrcVT.isFloatingPoint()) {
2680 if (SrcVT == MVT::f128)
2681 return VEISD::CMPQ;
2682 return VEISD::CMPF;
2683 }
2684 return isSignedIntSetCC(Code: CC) ? VEISD::CMPI : VEISD::CMPU;
2685}
2686
2687static EVT decideCompType(EVT SrcVT) {
2688 if (SrcVT == MVT::f128)
2689 return MVT::f64;
2690 return SrcVT;
2691}
2692
2693static bool safeWithoutCompWithNull(EVT SrcVT, ISD::CondCode CC,
2694 bool WithCMov) {
2695 if (SrcVT.isFloatingPoint()) {
2696 // For the case of floating point setcc, only unordered comparison
2697 // or general comparison with -enable-no-nans-fp-math option reach
2698 // here, so it is safe even if values are NaN. Only f128 doesn't
2699 // safe since VE uses f64 result of f128 comparison.
2700 return SrcVT != MVT::f128;
2701 }
2702 if (isIntEqualitySetCC(Code: CC)) {
2703 // For the case of equal or not equal, it is safe without comparison with 0.
2704 return true;
2705 }
2706 if (WithCMov) {
2707 // For the case of integer setcc with cmov, all signed comparison with 0
2708 // are safe.
2709 return isSignedIntSetCC(Code: CC);
2710 }
2711 // For the case of integer setcc, only signed 64 bits comparison is safe.
2712 // For unsigned, "CMPU 0x80000000, 0" has to be greater than 0, but it becomes
2713 // less than 0 witout CMPU. For 32 bits, other half of 32 bits are
2714 // uncoditional, so it is not safe too without CMPI..
2715 return isSignedIntSetCC(Code: CC) && SrcVT == MVT::i64;
2716}
2717
2718static SDValue generateComparison(EVT VT, SDValue LHS, SDValue RHS,
2719 ISD::CondCode CC, bool WithCMov,
2720 const SDLoc &DL, SelectionDAG &DAG) {
2721 // Compare values. If RHS is 0 and it is safe to calculate without
2722 // comparison, we don't generate an instruction for comparison.
2723 EVT CompVT = decideCompType(SrcVT: VT);
2724 if (CompVT == VT && safeWithoutCompWithNull(SrcVT: VT, CC, WithCMov) &&
2725 (isNullConstant(V: RHS) || isNullFPConstant(V: RHS))) {
2726 return LHS;
2727 }
2728 return DAG.getNode(Opcode: decideComp(SrcVT: VT, CC), DL, VT: CompVT, N1: LHS, N2: RHS);
2729}
2730
2731SDValue VETargetLowering::combineSelect(SDNode *N,
2732 DAGCombinerInfo &DCI) const {
2733 assert(N->getOpcode() == ISD::SELECT &&
2734 "Should be called with a SELECT node");
2735 ISD::CondCode CC = ISD::CondCode::SETNE;
2736 SDValue Cond = N->getOperand(Num: 0);
2737 SDValue True = N->getOperand(Num: 1);
2738 SDValue False = N->getOperand(Num: 2);
2739
2740 // We handle only scalar SELECT.
2741 EVT VT = N->getValueType(ResNo: 0);
2742 if (VT.isVector())
2743 return SDValue();
2744
2745 // Peform combineSelect after leagalize DAG.
2746 if (!DCI.isAfterLegalizeDAG())
2747 return SDValue();
2748
2749 EVT VT0 = Cond.getValueType();
2750 if (isMImm(V: True)) {
2751 // VE's condition move can handle MImm in True clause, so nothing to do.
2752 } else if (isMImm(V: False)) {
2753 // VE's condition move can handle MImm in True clause, so swap True and
2754 // False clauses if False has MImm value. And, update condition code.
2755 std::swap(a&: True, b&: False);
2756 CC = getSetCCInverse(Operation: CC, Type: VT0);
2757 }
2758
2759 SDLoc DL(N);
2760 SelectionDAG &DAG = DCI.DAG;
2761 VECC::CondCode VECCVal;
2762 if (VT0.isFloatingPoint()) {
2763 VECCVal = fpCondCode2Fcc(CC);
2764 } else {
2765 VECCVal = intCondCode2Icc(CC);
2766 }
2767 SDValue Ops[] = {Cond, True, False,
2768 DAG.getConstant(Val: VECCVal, DL, VT: MVT::i32)};
2769 return DAG.getNode(Opcode: VEISD::CMOV, DL, VT, Ops);
2770}
2771
2772SDValue VETargetLowering::combineSelectCC(SDNode *N,
2773 DAGCombinerInfo &DCI) const {
2774 assert(N->getOpcode() == ISD::SELECT_CC &&
2775 "Should be called with a SELECT_CC node");
2776 ISD::CondCode CC = cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get();
2777 SDValue LHS = N->getOperand(Num: 0);
2778 SDValue RHS = N->getOperand(Num: 1);
2779 SDValue True = N->getOperand(Num: 2);
2780 SDValue False = N->getOperand(Num: 3);
2781
2782 // We handle only scalar SELECT_CC.
2783 EVT VT = N->getValueType(ResNo: 0);
2784 if (VT.isVector())
2785 return SDValue();
2786
2787 // Peform combineSelectCC after leagalize DAG.
2788 if (!DCI.isAfterLegalizeDAG())
2789 return SDValue();
2790
2791 // We handle only i32/i64/f32/f64/f128 comparisons.
2792 EVT LHSVT = LHS.getValueType();
2793 assert(LHSVT == RHS.getValueType());
2794 switch (LHSVT.getSimpleVT().SimpleTy) {
2795 case MVT::i32:
2796 case MVT::i64:
2797 case MVT::f32:
2798 case MVT::f64:
2799 case MVT::f128:
2800 break;
2801 default:
2802 // Return SDValue to let llvm handle other types.
2803 return SDValue();
2804 }
2805
2806 if (isMImm(V: RHS)) {
2807 // VE's comparison can handle MImm in RHS, so nothing to do.
2808 } else if (isSimm7(V: RHS)) {
2809 // VE's comparison can handle Simm7 in LHS, so swap LHS and RHS, and
2810 // update condition code.
2811 std::swap(a&: LHS, b&: RHS);
2812 CC = getSetCCSwappedOperands(Operation: CC);
2813 }
2814 if (isMImm(V: True)) {
2815 // VE's condition move can handle MImm in True clause, so nothing to do.
2816 } else if (isMImm(V: False)) {
2817 // VE's condition move can handle MImm in True clause, so swap True and
2818 // False clauses if False has MImm value. And, update condition code.
2819 std::swap(a&: True, b&: False);
2820 CC = getSetCCInverse(Operation: CC, Type: LHSVT);
2821 }
2822
2823 SDLoc DL(N);
2824 SelectionDAG &DAG = DCI.DAG;
2825
2826 bool WithCMov = true;
2827 SDValue CompNode = generateComparison(VT: LHSVT, LHS, RHS, CC, WithCMov, DL, DAG);
2828
2829 VECC::CondCode VECCVal;
2830 if (LHSVT.isFloatingPoint()) {
2831 VECCVal = fpCondCode2Fcc(CC);
2832 } else {
2833 VECCVal = intCondCode2Icc(CC);
2834 }
2835 SDValue Ops[] = {CompNode, True, False,
2836 DAG.getConstant(Val: VECCVal, DL, VT: MVT::i32)};
2837 return DAG.getNode(Opcode: VEISD::CMOV, DL, VT, Ops);
2838}
2839
2840static bool isI32InsnAllUses(const SDNode *User, const SDNode *N);
2841static bool isI32Insn(const SDNode *User, const SDNode *N) {
2842 switch (User->getOpcode()) {
2843 default:
2844 return false;
2845 case ISD::ADD:
2846 case ISD::SUB:
2847 case ISD::MUL:
2848 case ISD::SDIV:
2849 case ISD::UDIV:
2850 case ISD::SETCC:
2851 case ISD::SMIN:
2852 case ISD::SMAX:
2853 case ISD::SHL:
2854 case ISD::SRA:
2855 case ISD::BSWAP:
2856 case ISD::SINT_TO_FP:
2857 case ISD::UINT_TO_FP:
2858 case ISD::BR_CC:
2859 case ISD::BITCAST:
2860 case ISD::ATOMIC_CMP_SWAP:
2861 case ISD::ATOMIC_SWAP:
2862 case VEISD::CMPU:
2863 case VEISD::CMPI:
2864 return true;
2865 case ISD::SRL:
2866 if (N->getOperand(Num: 0).getOpcode() != ISD::SRL)
2867 return true;
2868 // (srl (trunc (srl ...))) may be optimized by combining srl, so
2869 // doesn't optimize trunc now.
2870 return false;
2871 case ISD::SELECT_CC:
2872 if (User->getOperand(Num: 2).getNode() != N &&
2873 User->getOperand(Num: 3).getNode() != N)
2874 return true;
2875 return isI32InsnAllUses(User, N);
2876 case VEISD::CMOV:
2877 // CMOV in (cmov (trunc ...), true, false, int-comparison) is safe.
2878 // However, trunc in true or false clauses is not safe.
2879 if (User->getOperand(Num: 1).getNode() != N &&
2880 User->getOperand(Num: 2).getNode() != N &&
2881 isa<ConstantSDNode>(Val: User->getOperand(Num: 3))) {
2882 VECC::CondCode VECCVal =
2883 static_cast<VECC::CondCode>(User->getConstantOperandVal(Num: 3));
2884 return isIntVECondCode(CC: VECCVal);
2885 }
2886 [[fallthrough]];
2887 case ISD::AND:
2888 case ISD::OR:
2889 case ISD::XOR:
2890 case ISD::SELECT:
2891 case ISD::CopyToReg:
2892 // Check all use of selections, bit operations, and copies. If all of them
2893 // are safe, optimize truncate to extract_subreg.
2894 return isI32InsnAllUses(User, N);
2895 }
2896}
2897
2898static bool isI32InsnAllUses(const SDNode *User, const SDNode *N) {
2899 // Check all use of User node. If all of them are safe, optimize
2900 // truncate to extract_subreg.
2901 for (const SDNode *U : User->users()) {
2902 switch (U->getOpcode()) {
2903 default:
2904 // If the use is an instruction which treats the source operand as i32,
2905 // it is safe to avoid truncate here.
2906 if (isI32Insn(User: U, N))
2907 continue;
2908 break;
2909 case ISD::ANY_EXTEND:
2910 case ISD::SIGN_EXTEND:
2911 case ISD::ZERO_EXTEND: {
2912 // Special optimizations to the combination of ext and trunc.
2913 // (ext ... (select ... (trunc ...))) is safe to avoid truncate here
2914 // since this truncate instruction clears higher 32 bits which is filled
2915 // by one of ext instructions later.
2916 assert(N->getValueType(0) == MVT::i32 &&
2917 "find truncate to not i32 integer");
2918 if (User->getOpcode() == ISD::SELECT_CC ||
2919 User->getOpcode() == ISD::SELECT || User->getOpcode() == VEISD::CMOV)
2920 continue;
2921 break;
2922 }
2923 }
2924 return false;
2925 }
2926 return true;
2927}
2928
2929// Optimize TRUNCATE in DAG combining. Optimizing it in CUSTOM lower is
2930// sometime too early. Optimizing it in DAG pattern matching in VEInstrInfo.td
2931// is sometime too late. So, doing it at here.
2932SDValue VETargetLowering::combineTRUNCATE(SDNode *N,
2933 DAGCombinerInfo &DCI) const {
2934 assert(N->getOpcode() == ISD::TRUNCATE &&
2935 "Should be called with a TRUNCATE node");
2936
2937 SelectionDAG &DAG = DCI.DAG;
2938 SDLoc DL(N);
2939 EVT VT = N->getValueType(ResNo: 0);
2940
2941 // We prefer to do this when all types are legal.
2942 if (!DCI.isAfterLegalizeDAG())
2943 return SDValue();
2944
2945 // Skip combine TRUNCATE atm if the operand of TRUNCATE might be a constant.
2946 if (N->getOperand(Num: 0)->getOpcode() == ISD::SELECT_CC &&
2947 isa<ConstantSDNode>(Val: N->getOperand(Num: 0)->getOperand(Num: 0)) &&
2948 isa<ConstantSDNode>(Val: N->getOperand(Num: 0)->getOperand(Num: 1)))
2949 return SDValue();
2950
2951 // Check all use of this TRUNCATE.
2952 for (const SDNode *User : N->users()) {
2953 // Make sure that we're not going to replace TRUNCATE for non i32
2954 // instructions.
2955 //
2956 // FIXME: Although we could sometimes handle this, and it does occur in
2957 // practice that one of the condition inputs to the select is also one of
2958 // the outputs, we currently can't deal with this.
2959 if (isI32Insn(User, N))
2960 continue;
2961
2962 return SDValue();
2963 }
2964
2965 SDValue SubI32 = DAG.getTargetConstant(Val: VE::sub_i32, DL, VT: MVT::i32);
2966 return SDValue(DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG, dl: DL, VT,
2967 Op1: N->getOperand(Num: 0), Op2: SubI32),
2968 0);
2969}
2970
2971SDValue VETargetLowering::PerformDAGCombine(SDNode *N,
2972 DAGCombinerInfo &DCI) const {
2973 switch (N->getOpcode()) {
2974 default:
2975 break;
2976 case ISD::SELECT:
2977 return combineSelect(N, DCI);
2978 case ISD::SELECT_CC:
2979 return combineSelectCC(N, DCI);
2980 case ISD::TRUNCATE:
2981 return combineTRUNCATE(N, DCI);
2982 }
2983
2984 return SDValue();
2985}
2986
2987//===----------------------------------------------------------------------===//
2988// VE Inline Assembly Support
2989//===----------------------------------------------------------------------===//
2990
2991VETargetLowering::ConstraintType
2992VETargetLowering::getConstraintType(StringRef Constraint) const {
2993 if (Constraint.size() == 1) {
2994 switch (Constraint[0]) {
2995 default:
2996 break;
2997 case 'v': // vector registers
2998 return C_RegisterClass;
2999 }
3000 }
3001 return TargetLowering::getConstraintType(Constraint);
3002}
3003
3004std::pair<unsigned, const TargetRegisterClass *>
3005VETargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3006 StringRef Constraint,
3007 MVT VT) const {
3008 const TargetRegisterClass *RC = nullptr;
3009 if (Constraint.size() == 1) {
3010 switch (Constraint[0]) {
3011 default:
3012 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3013 case 'r':
3014 RC = &VE::I64RegClass;
3015 break;
3016 case 'v':
3017 RC = &VE::V64RegClass;
3018 break;
3019 }
3020 return std::make_pair(x: 0U, y&: RC);
3021 }
3022
3023 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3024}
3025
3026//===----------------------------------------------------------------------===//
3027// VE Target Optimization Support
3028//===----------------------------------------------------------------------===//
3029
3030unsigned VETargetLowering::getMinimumJumpTableEntries() const {
3031 // Specify 8 for PIC model to relieve the impact of PIC load instructions.
3032 if (isJumpTableRelative())
3033 return 8;
3034
3035 return TargetLowering::getMinimumJumpTableEntries();
3036}
3037
3038bool VETargetLowering::hasAndNot(SDValue Y) const {
3039 EVT VT = Y.getValueType();
3040
3041 // VE doesn't have vector and not instruction.
3042 if (VT.isVector())
3043 return false;
3044
3045 // VE allows different immediate values for X and Y where ~X & Y.
3046 // Only simm7 works for X, and only mimm works for Y on VE. However, this
3047 // function is used to check whether an immediate value is OK for and-not
3048 // instruction as both X and Y. Generating additional instruction to
3049 // retrieve an immediate value is no good since the purpose of this
3050 // function is to convert a series of 3 instructions to another series of
3051 // 3 instructions with better parallelism. Therefore, we return false
3052 // for all immediate values now.
3053 // FIXME: Change hasAndNot function to have two operands to make it work
3054 // correctly with Aurora VE.
3055 if (isa<ConstantSDNode>(Val: Y))
3056 return false;
3057
3058 // It's ok for generic registers.
3059 return true;
3060}
3061
3062SDValue VETargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
3063 SelectionDAG &DAG) const {
3064 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
3065 MVT VT = Op.getOperand(i: 0).getSimpleValueType();
3066
3067 // Special treatment for packed V64 types.
3068 assert(VT == MVT::v512i32 || VT == MVT::v512f32);
3069 (void)VT;
3070 // Example of codes:
3071 // %packed_v = extractelt %vr, %idx / 2
3072 // %v = %packed_v >> (%idx % 2 * 32)
3073 // %res = %v & 0xffffffff
3074
3075 SDValue Vec = Op.getOperand(i: 0);
3076 SDValue Idx = Op.getOperand(i: 1);
3077 SDLoc DL(Op);
3078 SDValue Result = Op;
3079 if (false /* Idx->isConstant() */) {
3080 // TODO: optimized implementation using constant values
3081 } else {
3082 SDValue Const1 = DAG.getConstant(Val: 1, DL, VT: MVT::i64);
3083 SDValue HalfIdx = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i64, Ops: {Idx, Const1});
3084 SDValue PackedElt =
3085 SDValue(DAG.getMachineNode(Opcode: VE::LVSvr, dl: DL, VT: MVT::i64, Ops: {Vec, HalfIdx}), 0);
3086 SDValue AndIdx = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i64, Ops: {Idx, Const1});
3087 SDValue Shift = DAG.getNode(Opcode: ISD::XOR, DL, VT: MVT::i64, Ops: {AndIdx, Const1});
3088 SDValue Const5 = DAG.getConstant(Val: 5, DL, VT: MVT::i64);
3089 Shift = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, Ops: {Shift, Const5});
3090 PackedElt = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i64, Ops: {PackedElt, Shift});
3091 SDValue Mask = DAG.getConstant(Val: 0xFFFFFFFFL, DL, VT: MVT::i64);
3092 PackedElt = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i64, Ops: {PackedElt, Mask});
3093 SDValue SubI32 = DAG.getTargetConstant(Val: VE::sub_i32, DL, VT: MVT::i32);
3094 Result = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG, dl: DL,
3095 VT: MVT::i32, Op1: PackedElt, Op2: SubI32),
3096 0);
3097
3098 if (Op.getSimpleValueType() == MVT::f32) {
3099 Result = DAG.getBitcast(VT: MVT::f32, V: Result);
3100 } else {
3101 assert(Op.getSimpleValueType() == MVT::i32);
3102 }
3103 }
3104 return Result;
3105}
3106
3107SDValue VETargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
3108 SelectionDAG &DAG) const {
3109 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
3110 MVT VT = Op.getOperand(i: 0).getSimpleValueType();
3111
3112 // Special treatment for packed V64 types.
3113 assert(VT == MVT::v512i32 || VT == MVT::v512f32);
3114 (void)VT;
3115 // The v512i32 and v512f32 starts from upper bits (0..31). This "upper
3116 // bits" required `val << 32` from C implementation's point of view.
3117 //
3118 // Example of codes:
3119 // %packed_elt = extractelt %vr, (%idx >> 1)
3120 // %shift = ((%idx & 1) ^ 1) << 5
3121 // %packed_elt &= 0xffffffff00000000 >> shift
3122 // %packed_elt |= (zext %val) << shift
3123 // %vr = insertelt %vr, %packed_elt, (%idx >> 1)
3124
3125 SDLoc DL(Op);
3126 SDValue Vec = Op.getOperand(i: 0);
3127 SDValue Val = Op.getOperand(i: 1);
3128 SDValue Idx = Op.getOperand(i: 2);
3129 if (Idx.getSimpleValueType() == MVT::i32)
3130 Idx = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i64, Operand: Idx);
3131 if (Val.getSimpleValueType() == MVT::f32)
3132 Val = DAG.getBitcast(VT: MVT::i32, V: Val);
3133 assert(Val.getSimpleValueType() == MVT::i32);
3134 Val = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i64, Operand: Val);
3135
3136 SDValue Result = Op;
3137 if (false /* Idx->isConstant()*/) {
3138 // TODO: optimized implementation using constant values
3139 } else {
3140 SDValue Const1 = DAG.getConstant(Val: 1, DL, VT: MVT::i64);
3141 SDValue HalfIdx = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i64, Ops: {Idx, Const1});
3142 SDValue PackedElt =
3143 SDValue(DAG.getMachineNode(Opcode: VE::LVSvr, dl: DL, VT: MVT::i64, Ops: {Vec, HalfIdx}), 0);
3144 SDValue AndIdx = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i64, Ops: {Idx, Const1});
3145 SDValue Shift = DAG.getNode(Opcode: ISD::XOR, DL, VT: MVT::i64, Ops: {AndIdx, Const1});
3146 SDValue Const5 = DAG.getConstant(Val: 5, DL, VT: MVT::i64);
3147 Shift = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, Ops: {Shift, Const5});
3148 SDValue Mask = DAG.getConstant(Val: 0xFFFFFFFF00000000L, DL, VT: MVT::i64);
3149 Mask = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i64, Ops: {Mask, Shift});
3150 PackedElt = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i64, Ops: {PackedElt, Mask});
3151 Val = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, Ops: {Val, Shift});
3152 PackedElt = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i64, Ops: {PackedElt, Val});
3153 Result =
3154 SDValue(DAG.getMachineNode(Opcode: VE::LSVrr_v, dl: DL, VT: Vec.getSimpleValueType(),
3155 Ops: {HalfIdx, PackedElt, Vec}),
3156 0);
3157 }
3158 return Result;
3159}
3160