1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass VEMCRegisterClasses[];
12
13static const MVT::SimpleValueType VEVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f32, MVT::Other,
17 /* 6 */ MVT::i64, MVT::f64, MVT::Other,
18 /* 9 */ MVT::f128, MVT::Other,
19 /* 11 */ MVT::v256i1, MVT::Other,
20 /* 13 */ MVT::v512i1, MVT::Other,
21 /* 15 */ MVT::v256f64, MVT::v512i32, MVT::v512f32, MVT::v256i64, MVT::v256i32, MVT::v256f32, MVT::Other,
22};
23
24#ifdef __GNUC__
25#pragma GCC diagnostic push
26#pragma GCC diagnostic ignored "-Woverlength-strings"
27#endif
28static constexpr char VESubRegIndexStrings[] = {
29 /* 0 */ "sub_odd_then_sub_f32\000"
30 /* 21 */ "sub_odd_then_sub_i32\000"
31 /* 42 */ "sub_odd\000"
32 /* 50 */ "sub_vm_odd\000"
33 /* 61 */ "sub_even\000"
34 /* 70 */ "sub_vm_even\000"
35};
36#ifdef __GNUC__
37#pragma GCC diagnostic pop
38#endif
39
40
41static constexpr uint32_t VESubRegIndexNameOffsets[] = {
42 61,
43 13,
44 34,
45 42,
46 70,
47 50,
48 0,
49 21,
50};
51
52static const TargetRegisterInfo::SubRegCoveredBits VESubRegIdxRangeTable[] = {
53 { .Offset: 4294967295, .Size: 4294967295 },
54 { .Offset: 0, .Size: 64 }, // sub_even
55 { .Offset: 0, .Size: 32 }, // sub_f32
56 { .Offset: 32, .Size: 32 }, // sub_i32
57 { .Offset: 64, .Size: 64 }, // sub_odd
58 { .Offset: 0, .Size: 256 }, // sub_vm_even
59 { .Offset: 256, .Size: 256 }, // sub_vm_odd
60 { .Offset: 64, .Size: 32 }, // sub_odd_then_sub_f32
61 { .Offset: 96, .Size: 32 }, // sub_odd_then_sub_i32
62};
63
64
65static const LaneBitmask VESubRegIndexLaneMaskTable[] = {
66 LaneBitmask::getAll(),
67 LaneBitmask(0x0000000000000003), // sub_even
68 LaneBitmask(0x0000000000000001), // sub_f32
69 LaneBitmask(0x0000000000000002), // sub_i32
70 LaneBitmask(0x0000000000000030), // sub_odd
71 LaneBitmask(0x0000000000000004), // sub_vm_even
72 LaneBitmask(0x0000000000000008), // sub_vm_odd
73 LaneBitmask(0x0000000000000010), // sub_odd_then_sub_f32
74 LaneBitmask(0x0000000000000020), // sub_odd_then_sub_i32
75 };
76
77
78
79static const TargetRegisterInfo::RegClassInfo VERegClassInfos[] = {
80 // Mode = 0 (DefaultMode)
81 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VEVTLists+*/.VTListOffset: 4 }, // F32
82 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VEVTLists+*/.VTListOffset: 0 }, // I32
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 0 }, // VLS
84 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 6 }, // I64
85 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 2 }, // MISC
86 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VEVTLists+*/.VTListOffset: 9 }, // F128
87 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 11 }, // VM
88 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 13 }, // VM512
89 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 13 }, // VM512_with_sub_vm_even
90 { .RegSize: 16384, .SpillSize: 16384, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 15 }, // V64
91};
92static const uint32_t F32SubClassMask[] = {
93 0x00000001,
94 0x00000028, // sub_f32
95 0x00000020, // sub_odd_then_sub_f32
96};
97
98static const uint32_t I32SubClassMask[] = {
99 0x00000002,
100 0x00000028, // sub_i32
101 0x00000020, // sub_odd_then_sub_i32
102};
103
104static const uint32_t VLSSubClassMask[] = {
105 0x00000004,
106};
107
108static const uint32_t I64SubClassMask[] = {
109 0x00000008,
110 0x00000020, // sub_even
111 0x00000020, // sub_odd
112};
113
114static const uint32_t MISCSubClassMask[] = {
115 0x00000010,
116};
117
118static const uint32_t F128SubClassMask[] = {
119 0x00000020,
120};
121
122static const uint32_t VMSubClassMask[] = {
123 0x00000040,
124 0x00000100, // sub_vm_even
125 0x00000100, // sub_vm_odd
126};
127
128static const uint32_t VM512SubClassMask[] = {
129 0x00000180,
130};
131
132static const uint32_t VM512_with_sub_vm_evenSubClassMask[] = {
133 0x00000100,
134};
135
136static const uint32_t V64SubClassMask[] = {
137 0x00000200,
138};
139
140static const uint16_t SuperRegIdxSeqs[] = {
141 /* 0 */ 1, 4, 0,
142 /* 3 */ 5, 6, 0,
143 /* 6 */ 2, 7, 0,
144 /* 9 */ 3, 8, 0,
145};
146
147static unsigned const VM512_with_sub_vm_evenSuperclasses[] = {
148 VE::VM512RegClassID,
149};
150
151namespace VE {
152
153// Register class instances.
154 extern const TargetRegisterClass F32RegClass = {
155 .MC: &VEMCRegisterClasses[F32RegClassID],
156 .SubClassMask: F32SubClassMask,
157 .SuperRegIndices: SuperRegIdxSeqs + 6,
158 .LaneMask: LaneBitmask(0x0000000000000001),
159 .AllocationPriority: 0,
160 .GlobalPriority: false,
161 .TSFlags: 0x00, /* TSFlags */
162 .SpillStackID: 0, /* SpillStackID */
163 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
164 .CoveredBySubRegs: false, /* CoveredBySubRegs */
165 .SuperClasses: nullptr, .SuperClassesSize: 0,
166 .OrderFunc: nullptr
167 };
168
169 extern const TargetRegisterClass I32RegClass = {
170 .MC: &VEMCRegisterClasses[I32RegClassID],
171 .SubClassMask: I32SubClassMask,
172 .SuperRegIndices: SuperRegIdxSeqs + 9,
173 .LaneMask: LaneBitmask(0x0000000000000001),
174 .AllocationPriority: 0,
175 .GlobalPriority: false,
176 .TSFlags: 0x00, /* TSFlags */
177 .SpillStackID: 0, /* SpillStackID */
178 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
179 .CoveredBySubRegs: false, /* CoveredBySubRegs */
180 .SuperClasses: nullptr, .SuperClassesSize: 0,
181 .OrderFunc: nullptr
182 };
183
184 extern const TargetRegisterClass VLSRegClass = {
185 .MC: &VEMCRegisterClasses[VLSRegClassID],
186 .SubClassMask: VLSSubClassMask,
187 .SuperRegIndices: SuperRegIdxSeqs + 2,
188 .LaneMask: LaneBitmask(0x0000000000000001),
189 .AllocationPriority: 0,
190 .GlobalPriority: false,
191 .TSFlags: 0x00, /* TSFlags */
192 .SpillStackID: 0, /* SpillStackID */
193 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
194 .CoveredBySubRegs: false, /* CoveredBySubRegs */
195 .SuperClasses: nullptr, .SuperClassesSize: 0,
196 .OrderFunc: nullptr
197 };
198
199 extern const TargetRegisterClass I64RegClass = {
200 .MC: &VEMCRegisterClasses[I64RegClassID],
201 .SubClassMask: I64SubClassMask,
202 .SuperRegIndices: SuperRegIdxSeqs + 0,
203 .LaneMask: LaneBitmask(0x0000000000000003),
204 .AllocationPriority: 0,
205 .GlobalPriority: false,
206 .TSFlags: 0x00, /* TSFlags */
207 .SpillStackID: 0, /* SpillStackID */
208 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
209 .CoveredBySubRegs: true, /* CoveredBySubRegs */
210 .SuperClasses: nullptr, .SuperClassesSize: 0,
211 .OrderFunc: nullptr
212 };
213
214 extern const TargetRegisterClass MISCRegClass = {
215 .MC: &VEMCRegisterClasses[MISCRegClassID],
216 .SubClassMask: MISCSubClassMask,
217 .SuperRegIndices: SuperRegIdxSeqs + 2,
218 .LaneMask: LaneBitmask(0x0000000000000001),
219 .AllocationPriority: 0,
220 .GlobalPriority: false,
221 .TSFlags: 0x00, /* TSFlags */
222 .SpillStackID: 0, /* SpillStackID */
223 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
224 .CoveredBySubRegs: false, /* CoveredBySubRegs */
225 .SuperClasses: nullptr, .SuperClassesSize: 0,
226 .OrderFunc: nullptr
227 };
228
229 extern const TargetRegisterClass F128RegClass = {
230 .MC: &VEMCRegisterClasses[F128RegClassID],
231 .SubClassMask: F128SubClassMask,
232 .SuperRegIndices: SuperRegIdxSeqs + 2,
233 .LaneMask: LaneBitmask(0x0000000000000033),
234 .AllocationPriority: 0,
235 .GlobalPriority: false,
236 .TSFlags: 0x00, /* TSFlags */
237 .SpillStackID: 0, /* SpillStackID */
238 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
239 .CoveredBySubRegs: true, /* CoveredBySubRegs */
240 .SuperClasses: nullptr, .SuperClassesSize: 0,
241 .OrderFunc: nullptr
242 };
243
244 extern const TargetRegisterClass VMRegClass = {
245 .MC: &VEMCRegisterClasses[VMRegClassID],
246 .SubClassMask: VMSubClassMask,
247 .SuperRegIndices: SuperRegIdxSeqs + 3,
248 .LaneMask: LaneBitmask(0x0000000000000001),
249 .AllocationPriority: 0,
250 .GlobalPriority: false,
251 .TSFlags: 0x00, /* TSFlags */
252 .SpillStackID: 0, /* SpillStackID */
253 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
254 .CoveredBySubRegs: false, /* CoveredBySubRegs */
255 .SuperClasses: nullptr, .SuperClassesSize: 0,
256 .OrderFunc: nullptr
257 };
258
259 extern const TargetRegisterClass VM512RegClass = {
260 .MC: &VEMCRegisterClasses[VM512RegClassID],
261 .SubClassMask: VM512SubClassMask,
262 .SuperRegIndices: SuperRegIdxSeqs + 2,
263 .LaneMask: LaneBitmask(0x000000000000000C),
264 .AllocationPriority: 0,
265 .GlobalPriority: false,
266 .TSFlags: 0x00, /* TSFlags */
267 .SpillStackID: 0, /* SpillStackID */
268 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
269 .CoveredBySubRegs: false, /* CoveredBySubRegs */
270 .SuperClasses: nullptr, .SuperClassesSize: 0,
271 .OrderFunc: nullptr
272 };
273
274 extern const TargetRegisterClass VM512_with_sub_vm_evenRegClass = {
275 .MC: &VEMCRegisterClasses[VM512_with_sub_vm_evenRegClassID],
276 .SubClassMask: VM512_with_sub_vm_evenSubClassMask,
277 .SuperRegIndices: SuperRegIdxSeqs + 2,
278 .LaneMask: LaneBitmask(0x000000000000000C),
279 .AllocationPriority: 0,
280 .GlobalPriority: false,
281 .TSFlags: 0x00, /* TSFlags */
282 .SpillStackID: 0, /* SpillStackID */
283 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
284 .CoveredBySubRegs: true, /* CoveredBySubRegs */
285 .SuperClasses: VM512_with_sub_vm_evenSuperclasses, .SuperClassesSize: 1,
286 .OrderFunc: nullptr
287 };
288
289 extern const TargetRegisterClass V64RegClass = {
290 .MC: &VEMCRegisterClasses[V64RegClassID],
291 .SubClassMask: V64SubClassMask,
292 .SuperRegIndices: SuperRegIdxSeqs + 2,
293 .LaneMask: LaneBitmask(0x0000000000000001),
294 .AllocationPriority: 0,
295 .GlobalPriority: false,
296 .TSFlags: 0x00, /* TSFlags */
297 .SpillStackID: 0, /* SpillStackID */
298 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
299 .CoveredBySubRegs: false, /* CoveredBySubRegs */
300 .SuperClasses: nullptr, .SuperClassesSize: 0,
301 .OrderFunc: nullptr
302 };
303
304
305} // namespace VE
306static const TargetRegisterClass *const VERegisterClasses[] = {
307 &VE::F32RegClass,
308 &VE::I32RegClass,
309 &VE::VLSRegClass,
310 &VE::I64RegClass,
311 &VE::MISCRegClass,
312 &VE::F128RegClass,
313 &VE::VMRegClass,
314 &VE::VM512RegClass,
315 &VE::VM512_with_sub_vm_evenRegClass,
316 &VE::V64RegClass,
317 };
318
319static const uint8_t VECostPerUseTable[] = {
3200, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
321
322
323static const bool VEInAllocatableClassTable[] = {
324false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
325
326
327static const TargetRegisterInfoDesc VERegInfoDesc = { // Extra Descriptors
328.CostPerUse: VECostPerUseTable, .NumCosts: 1, .InAllocatableClass: VEInAllocatableClassTable};
329
330unsigned VEGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
331 static const uint8_t RowMap[8] = {
332 0, 0, 0, 1, 0, 0, 0, 0,
333 };
334 static const uint8_t Rows[2][8] = {
335 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
336 { 0, VE::sub_odd_then_sub_f32, VE::sub_odd_then_sub_i32, 0, 0, 0, 0, 0, },
337 };
338
339 --IdxA; assert(IdxA < 8); (void) IdxA;
340 --IdxB; assert(IdxB < 8);
341 return Rows[RowMap[IdxA]][IdxB];
342}
343
344unsigned VEGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
345 static const uint8_t Table[8][8] = {
346 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
347 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
348 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
349 { 0, 0, 0, 0, 0, 0, VE::sub_f32, VE::sub_i32, },
350 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
351 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
352 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
353 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
354 };
355
356 --IdxA; assert(IdxA < 8);
357 --IdxB; assert(IdxB < 8);
358 return Table[IdxA][IdxB];
359 }
360
361 struct MaskRolOp {
362 LaneBitmask Mask;
363 uint8_t RotateLeft;
364 };
365 static const MaskRolOp LaneMaskComposeSequences[] = {
366 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
367 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
368 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
369 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
370 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
371 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 10
372 };
373 static const uint8_t CompositeSequences[] = {
374 0, // to sub_even
375 0, // to sub_f32
376 2, // to sub_i32
377 4, // to sub_odd
378 6, // to sub_vm_even
379 8, // to sub_vm_odd
380 4, // to sub_odd_then_sub_f32
381 10 // to sub_odd_then_sub_i32
382 };
383
384LaneBitmask VEGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
385 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
386 LaneBitmask Result;
387 for (const MaskRolOp *Ops =
388 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
389 Ops->Mask.any(); ++Ops) {
390 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
391 if (unsigned S = Ops->RotateLeft)
392 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
393 else
394 Result |= LaneBitmask(M);
395 }
396 return Result;
397}
398
399LaneBitmask VEGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
400 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
401 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
402 LaneBitmask Result;
403 for (const MaskRolOp *Ops =
404 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
405 Ops->Mask.any(); ++Ops) {
406 LaneBitmask::Type M = LaneMask.getAsInteger();
407 if (unsigned S = Ops->RotateLeft)
408 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
409 else
410 Result |= LaneBitmask(M);
411 }
412 return Result;
413}
414
415const TargetRegisterClass *VEGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
416 static constexpr uint8_t Table[10][8] = {
417 { // F32
418 0, // sub_even
419 0, // sub_f32
420 0, // sub_i32
421 0, // sub_odd
422 0, // sub_vm_even
423 0, // sub_vm_odd
424 0, // sub_odd_then_sub_f32
425 0, // sub_odd_then_sub_i32
426 },
427 { // I32
428 0, // sub_even
429 0, // sub_f32
430 0, // sub_i32
431 0, // sub_odd
432 0, // sub_vm_even
433 0, // sub_vm_odd
434 0, // sub_odd_then_sub_f32
435 0, // sub_odd_then_sub_i32
436 },
437 { // VLS
438 0, // sub_even
439 0, // sub_f32
440 0, // sub_i32
441 0, // sub_odd
442 0, // sub_vm_even
443 0, // sub_vm_odd
444 0, // sub_odd_then_sub_f32
445 0, // sub_odd_then_sub_i32
446 },
447 { // I64
448 0, // sub_even
449 4, // sub_f32 -> I64
450 4, // sub_i32 -> I64
451 0, // sub_odd
452 0, // sub_vm_even
453 0, // sub_vm_odd
454 0, // sub_odd_then_sub_f32
455 0, // sub_odd_then_sub_i32
456 },
457 { // MISC
458 0, // sub_even
459 0, // sub_f32
460 0, // sub_i32
461 0, // sub_odd
462 0, // sub_vm_even
463 0, // sub_vm_odd
464 0, // sub_odd_then_sub_f32
465 0, // sub_odd_then_sub_i32
466 },
467 { // F128
468 6, // sub_even -> F128
469 6, // sub_f32 -> F128
470 6, // sub_i32 -> F128
471 6, // sub_odd -> F128
472 0, // sub_vm_even
473 0, // sub_vm_odd
474 6, // sub_odd_then_sub_f32 -> F128
475 6, // sub_odd_then_sub_i32 -> F128
476 },
477 { // VM
478 0, // sub_even
479 0, // sub_f32
480 0, // sub_i32
481 0, // sub_odd
482 0, // sub_vm_even
483 0, // sub_vm_odd
484 0, // sub_odd_then_sub_f32
485 0, // sub_odd_then_sub_i32
486 },
487 { // VM512
488 0, // sub_even
489 0, // sub_f32
490 0, // sub_i32
491 0, // sub_odd
492 9, // sub_vm_even -> VM512_with_sub_vm_even
493 9, // sub_vm_odd -> VM512_with_sub_vm_even
494 0, // sub_odd_then_sub_f32
495 0, // sub_odd_then_sub_i32
496 },
497 { // VM512_with_sub_vm_even
498 0, // sub_even
499 0, // sub_f32
500 0, // sub_i32
501 0, // sub_odd
502 9, // sub_vm_even -> VM512_with_sub_vm_even
503 9, // sub_vm_odd -> VM512_with_sub_vm_even
504 0, // sub_odd_then_sub_f32
505 0, // sub_odd_then_sub_i32
506 },
507 { // V64
508 0, // sub_even
509 0, // sub_f32
510 0, // sub_i32
511 0, // sub_odd
512 0, // sub_vm_even
513 0, // sub_vm_odd
514 0, // sub_odd_then_sub_f32
515 0, // sub_odd_then_sub_i32
516 },
517
518 };
519 assert(RC && "Missing regclass");
520 if (!Idx) return RC;
521 --Idx;
522 assert(Idx < 8 && "Bad subreg");
523 unsigned TV = Table[RC->getID()][Idx];
524 return TV ? getRegClass(i: TV - 1) : nullptr;
525}const TargetRegisterClass *VEGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
526 static constexpr uint8_t Table[10][8] = {
527 { // F32
528 0, // F32:sub_even
529 0, // F32:sub_f32
530 0, // F32:sub_i32
531 0, // F32:sub_odd
532 0, // F32:sub_vm_even
533 0, // F32:sub_vm_odd
534 0, // F32:sub_odd_then_sub_f32
535 0, // F32:sub_odd_then_sub_i32
536 },
537 { // I32
538 0, // I32:sub_even
539 0, // I32:sub_f32
540 0, // I32:sub_i32
541 0, // I32:sub_odd
542 0, // I32:sub_vm_even
543 0, // I32:sub_vm_odd
544 0, // I32:sub_odd_then_sub_f32
545 0, // I32:sub_odd_then_sub_i32
546 },
547 { // VLS
548 0, // VLS:sub_even
549 0, // VLS:sub_f32
550 0, // VLS:sub_i32
551 0, // VLS:sub_odd
552 0, // VLS:sub_vm_even
553 0, // VLS:sub_vm_odd
554 0, // VLS:sub_odd_then_sub_f32
555 0, // VLS:sub_odd_then_sub_i32
556 },
557 { // I64
558 0, // I64:sub_even
559 1, // I64:sub_f32 -> F32
560 2, // I64:sub_i32 -> I32
561 0, // I64:sub_odd
562 0, // I64:sub_vm_even
563 0, // I64:sub_vm_odd
564 0, // I64:sub_odd_then_sub_f32
565 0, // I64:sub_odd_then_sub_i32
566 },
567 { // MISC
568 0, // MISC:sub_even
569 0, // MISC:sub_f32
570 0, // MISC:sub_i32
571 0, // MISC:sub_odd
572 0, // MISC:sub_vm_even
573 0, // MISC:sub_vm_odd
574 0, // MISC:sub_odd_then_sub_f32
575 0, // MISC:sub_odd_then_sub_i32
576 },
577 { // F128
578 4, // F128:sub_even -> I64
579 1, // F128:sub_f32 -> F32
580 2, // F128:sub_i32 -> I32
581 4, // F128:sub_odd -> I64
582 0, // F128:sub_vm_even
583 0, // F128:sub_vm_odd
584 1, // F128:sub_odd_then_sub_f32 -> F32
585 2, // F128:sub_odd_then_sub_i32 -> I32
586 },
587 { // VM
588 0, // VM:sub_even
589 0, // VM:sub_f32
590 0, // VM:sub_i32
591 0, // VM:sub_odd
592 0, // VM:sub_vm_even
593 0, // VM:sub_vm_odd
594 0, // VM:sub_odd_then_sub_f32
595 0, // VM:sub_odd_then_sub_i32
596 },
597 { // VM512
598 0, // VM512:sub_even
599 0, // VM512:sub_f32
600 0, // VM512:sub_i32
601 0, // VM512:sub_odd
602 7, // VM512:sub_vm_even -> VM
603 7, // VM512:sub_vm_odd -> VM
604 0, // VM512:sub_odd_then_sub_f32
605 0, // VM512:sub_odd_then_sub_i32
606 },
607 { // VM512_with_sub_vm_even
608 0, // VM512_with_sub_vm_even:sub_even
609 0, // VM512_with_sub_vm_even:sub_f32
610 0, // VM512_with_sub_vm_even:sub_i32
611 0, // VM512_with_sub_vm_even:sub_odd
612 7, // VM512_with_sub_vm_even:sub_vm_even -> VM
613 7, // VM512_with_sub_vm_even:sub_vm_odd -> VM
614 0, // VM512_with_sub_vm_even:sub_odd_then_sub_f32
615 0, // VM512_with_sub_vm_even:sub_odd_then_sub_i32
616 },
617 { // V64
618 0, // V64:sub_even
619 0, // V64:sub_f32
620 0, // V64:sub_i32
621 0, // V64:sub_odd
622 0, // V64:sub_vm_even
623 0, // V64:sub_vm_odd
624 0, // V64:sub_odd_then_sub_f32
625 0, // V64:sub_odd_then_sub_i32
626 },
627
628 };
629 assert(RC && "Missing regclass");
630 if (!Idx) return RC;
631 --Idx;
632 assert(Idx < 8 && "Bad subreg");
633 unsigned TV = Table[RC->getID()][Idx];
634 return TV ? getRegClass(i: TV - 1) : nullptr;
635}/// Get the weight in units of pressure for this register class.
636const RegClassWeight &VEGenRegisterInfo::
637getRegClassWeight(const TargetRegisterClass *RC) const {
638 static const RegClassWeight RCWeightTable[] = {
639 {.RegWeight: 2, .WeightLimit: 128}, // F32
640 {.RegWeight: 2, .WeightLimit: 128}, // I32
641 {.RegWeight: 1, .WeightLimit: 1}, // VLS
642 {.RegWeight: 3, .WeightLimit: 192}, // I64
643 {.RegWeight: 1, .WeightLimit: 23}, // MISC
644 {.RegWeight: 6, .WeightLimit: 192}, // F128
645 {.RegWeight: 1, .WeightLimit: 16}, // VM
646 {.RegWeight: 2, .WeightLimit: 16}, // VM512
647 {.RegWeight: 2, .WeightLimit: 14}, // VM512_with_sub_vm_even
648 {.RegWeight: 1, .WeightLimit: 65}, // V64
649 };
650 return RCWeightTable[RC->getID()];
651}
652
653/// Get the weight in units of pressure for this register unit.
654unsigned VEGenRegisterInfo::
655getRegUnitWeight(MCRegUnit RegUnit) const {
656 assert(static_cast<unsigned>(RegUnit) < 299 && "invalid register unit");
657 static const uint8_t RUWeightTable[] = {
658 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, };
659 return RUWeightTable[static_cast<unsigned>(RegUnit)];
660}
661
662
663// Get the number of dimensions of register pressure.
664unsigned VEGenRegisterInfo::getNumRegPressureSets() const {
665 return 9;
666}
667
668// Get the name of this register unit pressure set.
669const char *VEGenRegisterInfo::
670getRegPressureSetName(unsigned Idx) const {
671 static const char *PressureNameTable[] = {
672 "VLS",
673 "VM512",
674 "VM",
675 "VM_with_VM512",
676 "MISC",
677 "V64",
678 "F32",
679 "I32",
680 "I64",
681 };
682 return PressureNameTable[Idx];
683}
684
685// Get the register unit pressure limit for this dimension.
686// This limit must be adjusted dynamically for reserved registers.
687unsigned VEGenRegisterInfo::
688getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
689 static const uint8_t PressureLimitTable[] = {
690 1, // 0: VLS
691 16, // 1: VM512
692 16, // 2: VM
693 18, // 3: VM_with_VM512
694 23, // 4: MISC
695 65, // 5: V64
696 128, // 6: F32
697 128, // 7: I32
698 192, // 8: I64
699 };
700 return PressureLimitTable[Idx];
701}
702
703/// Table of pressure sets per register class or unit.
704static const int RCSetsTable[] = {
705 /* 0 */ 0, -1,
706 /* 2 */ 1, 3, -1,
707 /* 5 */ 1, 2, 3, -1,
708 /* 9 */ 4, -1,
709 /* 11 */ 5, -1,
710 /* 13 */ 6, 8, -1,
711 /* 16 */ 6, 7, 8, -1,
712};
713
714/// Get the dimensions of register pressure impacted by this register class.
715/// Returns a -1 terminated array of pressure set IDs
716const int *VEGenRegisterInfo::
717getRegClassPressureSets(const TargetRegisterClass *RC) const {
718 static const uint8_t RCSetStartTable[] = {
719 13,17,0,14,9,14,6,2,5,11,};
720 return &RCSetsTable[RCSetStartTable[RC->getID()]];
721}
722
723/// Get the dimensions of register pressure impacted by this register unit.
724/// Returns a -1 terminated array of pressure set IDs
725const int *VEGenRegisterInfo::
726getRegUnitPressureSets(MCRegUnit RegUnit) const {
727 assert(static_cast<unsigned>(RegUnit) < 299 && "invalid register unit");
728 static const uint8_t RUSetStartTable[] = {
729 1,9,9,9,9,11,0,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,6,6,5,5,5,5,5,5,5,5,5,5,5,5,5,5,2,};
730 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
731}
732
733
734// Register to minimal register class mapping
735
736const TargetRegisterClass *VEGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
737 static const uint16_t InvalidRegClassID = UINT16_MAX;
738
739 static const uint16_t Mapping[339] = {
740 InvalidRegClassID, // NoRegister
741 InvalidRegClassID, // IC
742 VE::MISCRegClassID, // PMMR
743 VE::MISCRegClassID, // PSW
744 VE::MISCRegClassID, // SAR
745 VE::MISCRegClassID, // USRCC
746 VE::V64RegClassID, // VIX
747 VE::VLSRegClassID, // VL
748 VE::MISCRegClassID, // PMC0
749 VE::MISCRegClassID, // PMC1
750 VE::MISCRegClassID, // PMC2
751 VE::MISCRegClassID, // PMC3
752 VE::MISCRegClassID, // PMC4
753 VE::MISCRegClassID, // PMC5
754 VE::MISCRegClassID, // PMC6
755 VE::MISCRegClassID, // PMC7
756 VE::MISCRegClassID, // PMC8
757 VE::MISCRegClassID, // PMC9
758 VE::MISCRegClassID, // PMC10
759 VE::MISCRegClassID, // PMC11
760 VE::MISCRegClassID, // PMC12
761 VE::MISCRegClassID, // PMC13
762 VE::MISCRegClassID, // PMC14
763 VE::MISCRegClassID, // PMCR0
764 VE::MISCRegClassID, // PMCR1
765 VE::MISCRegClassID, // PMCR2
766 VE::MISCRegClassID, // PMCR3
767 VE::F128RegClassID, // Q0
768 VE::F128RegClassID, // Q1
769 VE::F128RegClassID, // Q2
770 VE::F128RegClassID, // Q3
771 VE::F128RegClassID, // Q4
772 VE::F128RegClassID, // Q5
773 VE::F128RegClassID, // Q6
774 VE::F128RegClassID, // Q7
775 VE::F128RegClassID, // Q8
776 VE::F128RegClassID, // Q9
777 VE::F128RegClassID, // Q10
778 VE::F128RegClassID, // Q11
779 VE::F128RegClassID, // Q12
780 VE::F128RegClassID, // Q13
781 VE::F128RegClassID, // Q14
782 VE::F128RegClassID, // Q15
783 VE::F128RegClassID, // Q16
784 VE::F128RegClassID, // Q17
785 VE::F128RegClassID, // Q18
786 VE::F128RegClassID, // Q19
787 VE::F128RegClassID, // Q20
788 VE::F128RegClassID, // Q21
789 VE::F128RegClassID, // Q22
790 VE::F128RegClassID, // Q23
791 VE::F128RegClassID, // Q24
792 VE::F128RegClassID, // Q25
793 VE::F128RegClassID, // Q26
794 VE::F128RegClassID, // Q27
795 VE::F128RegClassID, // Q28
796 VE::F128RegClassID, // Q29
797 VE::F128RegClassID, // Q30
798 VE::F128RegClassID, // Q31
799 VE::F32RegClassID, // SF0
800 VE::F32RegClassID, // SF1
801 VE::F32RegClassID, // SF2
802 VE::F32RegClassID, // SF3
803 VE::F32RegClassID, // SF4
804 VE::F32RegClassID, // SF5
805 VE::F32RegClassID, // SF6
806 VE::F32RegClassID, // SF7
807 VE::F32RegClassID, // SF8
808 VE::F32RegClassID, // SF9
809 VE::F32RegClassID, // SF10
810 VE::F32RegClassID, // SF11
811 VE::F32RegClassID, // SF12
812 VE::F32RegClassID, // SF13
813 VE::F32RegClassID, // SF14
814 VE::F32RegClassID, // SF15
815 VE::F32RegClassID, // SF16
816 VE::F32RegClassID, // SF17
817 VE::F32RegClassID, // SF18
818 VE::F32RegClassID, // SF19
819 VE::F32RegClassID, // SF20
820 VE::F32RegClassID, // SF21
821 VE::F32RegClassID, // SF22
822 VE::F32RegClassID, // SF23
823 VE::F32RegClassID, // SF24
824 VE::F32RegClassID, // SF25
825 VE::F32RegClassID, // SF26
826 VE::F32RegClassID, // SF27
827 VE::F32RegClassID, // SF28
828 VE::F32RegClassID, // SF29
829 VE::F32RegClassID, // SF30
830 VE::F32RegClassID, // SF31
831 VE::F32RegClassID, // SF32
832 VE::F32RegClassID, // SF33
833 VE::F32RegClassID, // SF34
834 VE::F32RegClassID, // SF35
835 VE::F32RegClassID, // SF36
836 VE::F32RegClassID, // SF37
837 VE::F32RegClassID, // SF38
838 VE::F32RegClassID, // SF39
839 VE::F32RegClassID, // SF40
840 VE::F32RegClassID, // SF41
841 VE::F32RegClassID, // SF42
842 VE::F32RegClassID, // SF43
843 VE::F32RegClassID, // SF44
844 VE::F32RegClassID, // SF45
845 VE::F32RegClassID, // SF46
846 VE::F32RegClassID, // SF47
847 VE::F32RegClassID, // SF48
848 VE::F32RegClassID, // SF49
849 VE::F32RegClassID, // SF50
850 VE::F32RegClassID, // SF51
851 VE::F32RegClassID, // SF52
852 VE::F32RegClassID, // SF53
853 VE::F32RegClassID, // SF54
854 VE::F32RegClassID, // SF55
855 VE::F32RegClassID, // SF56
856 VE::F32RegClassID, // SF57
857 VE::F32RegClassID, // SF58
858 VE::F32RegClassID, // SF59
859 VE::F32RegClassID, // SF60
860 VE::F32RegClassID, // SF61
861 VE::F32RegClassID, // SF62
862 VE::F32RegClassID, // SF63
863 VE::I32RegClassID, // SW0
864 VE::I32RegClassID, // SW1
865 VE::I32RegClassID, // SW2
866 VE::I32RegClassID, // SW3
867 VE::I32RegClassID, // SW4
868 VE::I32RegClassID, // SW5
869 VE::I32RegClassID, // SW6
870 VE::I32RegClassID, // SW7
871 VE::I32RegClassID, // SW8
872 VE::I32RegClassID, // SW9
873 VE::I32RegClassID, // SW10
874 VE::I32RegClassID, // SW11
875 VE::I32RegClassID, // SW12
876 VE::I32RegClassID, // SW13
877 VE::I32RegClassID, // SW14
878 VE::I32RegClassID, // SW15
879 VE::I32RegClassID, // SW16
880 VE::I32RegClassID, // SW17
881 VE::I32RegClassID, // SW18
882 VE::I32RegClassID, // SW19
883 VE::I32RegClassID, // SW20
884 VE::I32RegClassID, // SW21
885 VE::I32RegClassID, // SW22
886 VE::I32RegClassID, // SW23
887 VE::I32RegClassID, // SW24
888 VE::I32RegClassID, // SW25
889 VE::I32RegClassID, // SW26
890 VE::I32RegClassID, // SW27
891 VE::I32RegClassID, // SW28
892 VE::I32RegClassID, // SW29
893 VE::I32RegClassID, // SW30
894 VE::I32RegClassID, // SW31
895 VE::I32RegClassID, // SW32
896 VE::I32RegClassID, // SW33
897 VE::I32RegClassID, // SW34
898 VE::I32RegClassID, // SW35
899 VE::I32RegClassID, // SW36
900 VE::I32RegClassID, // SW37
901 VE::I32RegClassID, // SW38
902 VE::I32RegClassID, // SW39
903 VE::I32RegClassID, // SW40
904 VE::I32RegClassID, // SW41
905 VE::I32RegClassID, // SW42
906 VE::I32RegClassID, // SW43
907 VE::I32RegClassID, // SW44
908 VE::I32RegClassID, // SW45
909 VE::I32RegClassID, // SW46
910 VE::I32RegClassID, // SW47
911 VE::I32RegClassID, // SW48
912 VE::I32RegClassID, // SW49
913 VE::I32RegClassID, // SW50
914 VE::I32RegClassID, // SW51
915 VE::I32RegClassID, // SW52
916 VE::I32RegClassID, // SW53
917 VE::I32RegClassID, // SW54
918 VE::I32RegClassID, // SW55
919 VE::I32RegClassID, // SW56
920 VE::I32RegClassID, // SW57
921 VE::I32RegClassID, // SW58
922 VE::I32RegClassID, // SW59
923 VE::I32RegClassID, // SW60
924 VE::I32RegClassID, // SW61
925 VE::I32RegClassID, // SW62
926 VE::I32RegClassID, // SW63
927 VE::I64RegClassID, // SX0
928 VE::I64RegClassID, // SX1
929 VE::I64RegClassID, // SX2
930 VE::I64RegClassID, // SX3
931 VE::I64RegClassID, // SX4
932 VE::I64RegClassID, // SX5
933 VE::I64RegClassID, // SX6
934 VE::I64RegClassID, // SX7
935 VE::I64RegClassID, // SX8
936 VE::I64RegClassID, // SX9
937 VE::I64RegClassID, // SX10
938 VE::I64RegClassID, // SX11
939 VE::I64RegClassID, // SX12
940 VE::I64RegClassID, // SX13
941 VE::I64RegClassID, // SX14
942 VE::I64RegClassID, // SX15
943 VE::I64RegClassID, // SX16
944 VE::I64RegClassID, // SX17
945 VE::I64RegClassID, // SX18
946 VE::I64RegClassID, // SX19
947 VE::I64RegClassID, // SX20
948 VE::I64RegClassID, // SX21
949 VE::I64RegClassID, // SX22
950 VE::I64RegClassID, // SX23
951 VE::I64RegClassID, // SX24
952 VE::I64RegClassID, // SX25
953 VE::I64RegClassID, // SX26
954 VE::I64RegClassID, // SX27
955 VE::I64RegClassID, // SX28
956 VE::I64RegClassID, // SX29
957 VE::I64RegClassID, // SX30
958 VE::I64RegClassID, // SX31
959 VE::I64RegClassID, // SX32
960 VE::I64RegClassID, // SX33
961 VE::I64RegClassID, // SX34
962 VE::I64RegClassID, // SX35
963 VE::I64RegClassID, // SX36
964 VE::I64RegClassID, // SX37
965 VE::I64RegClassID, // SX38
966 VE::I64RegClassID, // SX39
967 VE::I64RegClassID, // SX40
968 VE::I64RegClassID, // SX41
969 VE::I64RegClassID, // SX42
970 VE::I64RegClassID, // SX43
971 VE::I64RegClassID, // SX44
972 VE::I64RegClassID, // SX45
973 VE::I64RegClassID, // SX46
974 VE::I64RegClassID, // SX47
975 VE::I64RegClassID, // SX48
976 VE::I64RegClassID, // SX49
977 VE::I64RegClassID, // SX50
978 VE::I64RegClassID, // SX51
979 VE::I64RegClassID, // SX52
980 VE::I64RegClassID, // SX53
981 VE::I64RegClassID, // SX54
982 VE::I64RegClassID, // SX55
983 VE::I64RegClassID, // SX56
984 VE::I64RegClassID, // SX57
985 VE::I64RegClassID, // SX58
986 VE::I64RegClassID, // SX59
987 VE::I64RegClassID, // SX60
988 VE::I64RegClassID, // SX61
989 VE::I64RegClassID, // SX62
990 VE::I64RegClassID, // SX63
991 VE::V64RegClassID, // V0
992 VE::V64RegClassID, // V1
993 VE::V64RegClassID, // V2
994 VE::V64RegClassID, // V3
995 VE::V64RegClassID, // V4
996 VE::V64RegClassID, // V5
997 VE::V64RegClassID, // V6
998 VE::V64RegClassID, // V7
999 VE::V64RegClassID, // V8
1000 VE::V64RegClassID, // V9
1001 VE::V64RegClassID, // V10
1002 VE::V64RegClassID, // V11
1003 VE::V64RegClassID, // V12
1004 VE::V64RegClassID, // V13
1005 VE::V64RegClassID, // V14
1006 VE::V64RegClassID, // V15
1007 VE::V64RegClassID, // V16
1008 VE::V64RegClassID, // V17
1009 VE::V64RegClassID, // V18
1010 VE::V64RegClassID, // V19
1011 VE::V64RegClassID, // V20
1012 VE::V64RegClassID, // V21
1013 VE::V64RegClassID, // V22
1014 VE::V64RegClassID, // V23
1015 VE::V64RegClassID, // V24
1016 VE::V64RegClassID, // V25
1017 VE::V64RegClassID, // V26
1018 VE::V64RegClassID, // V27
1019 VE::V64RegClassID, // V28
1020 VE::V64RegClassID, // V29
1021 VE::V64RegClassID, // V30
1022 VE::V64RegClassID, // V31
1023 VE::V64RegClassID, // V32
1024 VE::V64RegClassID, // V33
1025 VE::V64RegClassID, // V34
1026 VE::V64RegClassID, // V35
1027 VE::V64RegClassID, // V36
1028 VE::V64RegClassID, // V37
1029 VE::V64RegClassID, // V38
1030 VE::V64RegClassID, // V39
1031 VE::V64RegClassID, // V40
1032 VE::V64RegClassID, // V41
1033 VE::V64RegClassID, // V42
1034 VE::V64RegClassID, // V43
1035 VE::V64RegClassID, // V44
1036 VE::V64RegClassID, // V45
1037 VE::V64RegClassID, // V46
1038 VE::V64RegClassID, // V47
1039 VE::V64RegClassID, // V48
1040 VE::V64RegClassID, // V49
1041 VE::V64RegClassID, // V50
1042 VE::V64RegClassID, // V51
1043 VE::V64RegClassID, // V52
1044 VE::V64RegClassID, // V53
1045 VE::V64RegClassID, // V54
1046 VE::V64RegClassID, // V55
1047 VE::V64RegClassID, // V56
1048 VE::V64RegClassID, // V57
1049 VE::V64RegClassID, // V58
1050 VE::V64RegClassID, // V59
1051 VE::V64RegClassID, // V60
1052 VE::V64RegClassID, // V61
1053 VE::V64RegClassID, // V62
1054 VE::V64RegClassID, // V63
1055 VE::VMRegClassID, // VM0
1056 VE::VMRegClassID, // VM1
1057 VE::VMRegClassID, // VM2
1058 VE::VMRegClassID, // VM3
1059 VE::VMRegClassID, // VM4
1060 VE::VMRegClassID, // VM5
1061 VE::VMRegClassID, // VM6
1062 VE::VMRegClassID, // VM7
1063 VE::VMRegClassID, // VM8
1064 VE::VMRegClassID, // VM9
1065 VE::VMRegClassID, // VM10
1066 VE::VMRegClassID, // VM11
1067 VE::VMRegClassID, // VM12
1068 VE::VMRegClassID, // VM13
1069 VE::VMRegClassID, // VM14
1070 VE::VMRegClassID, // VM15
1071 VE::VM512RegClassID, // VMP0
1072 VE::VM512_with_sub_vm_evenRegClassID, // VMP1
1073 VE::VM512_with_sub_vm_evenRegClassID, // VMP2
1074 VE::VM512_with_sub_vm_evenRegClassID, // VMP3
1075 VE::VM512_with_sub_vm_evenRegClassID, // VMP4
1076 VE::VM512_with_sub_vm_evenRegClassID, // VMP5
1077 VE::VM512_with_sub_vm_evenRegClassID, // VMP6
1078 VE::VM512_with_sub_vm_evenRegClassID, // VMP7
1079 };
1080
1081 assert(Reg < ArrayRef(Mapping).size());
1082 unsigned RCID = Mapping[Reg.id()];
1083 if (RCID == InvalidRegClassID)
1084 return nullptr;
1085 return VERegisterClasses[RCID];
1086}
1087extern const MCRegisterDesc VERegDesc[];
1088extern const int16_t VERegDiffLists[];
1089extern const LaneBitmask VELaneMaskLists[];
1090extern const char VERegStrings[];
1091extern const char VERegClassStrings[];
1092extern const MCPhysReg VERegUnitRoots[][2];
1093extern const uint16_t VESubRegIdxLists[];
1094extern const uint16_t VERegEncodingTable[];
1095// VE Dwarf<->LLVM register mappings.
1096extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0Dwarf2L[];
1097extern const unsigned VEDwarfFlavour0Dwarf2LSize;
1098
1099extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0Dwarf2L[];
1100extern const unsigned VEEHFlavour0Dwarf2LSize;
1101
1102extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0L2Dwarf[];
1103extern const unsigned VEDwarfFlavour0L2DwarfSize;
1104
1105extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0L2Dwarf[];
1106extern const unsigned VEEHFlavour0L2DwarfSize;
1107
1108
1109VEGenRegisterInfo::
1110VEGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1111 unsigned PC, unsigned HwMode)
1112 : TargetRegisterInfo(&VERegInfoDesc, VERegisterClasses,
1113 VESubRegIndexStrings, VESubRegIndexNameOffsets,
1114 VESubRegIdxRangeTable, VESubRegIndexLaneMaskTable,
1115
1116 LaneBitmask(0xFFFFFFFFFFFFFFFF), VERegClassInfos, VEVTLists, HwMode) {
1117 InitMCRegisterInfo(D: VERegDesc, NR: 339, RA, PC,
1118 C: VEMCRegisterClasses, NC: 10, RURoots: VERegUnitRoots, NRU: 299, DL: VERegDiffLists,
1119 RUMS: VELaneMaskLists, Strings: VERegStrings, ClassStrings: VERegClassStrings, SubIndices: VESubRegIdxLists, NumIndices: 9,
1120 RET: VERegEncodingTable, RUI: nullptr);
1121
1122 switch (DwarfFlavour) {
1123 default:
1124 llvm_unreachable("Unknown DWARF flavour");
1125 case 0:
1126 mapDwarfRegsToLLVMRegs(Map: VEDwarfFlavour0Dwarf2L, Size: VEDwarfFlavour0Dwarf2LSize, isEH: false);
1127 break;
1128 }
1129 switch (EHFlavour) {
1130 default:
1131 llvm_unreachable("Unknown DWARF flavour");
1132 case 0:
1133 mapDwarfRegsToLLVMRegs(Map: VEEHFlavour0Dwarf2L, Size: VEEHFlavour0Dwarf2LSize, isEH: true);
1134 break;
1135 }
1136 switch (DwarfFlavour) {
1137 default:
1138 llvm_unreachable("Unknown DWARF flavour");
1139 case 0:
1140 mapLLVMRegsToDwarfRegs(Map: VEDwarfFlavour0L2Dwarf, Size: VEDwarfFlavour0L2DwarfSize, isEH: false);
1141 break;
1142 }
1143 switch (EHFlavour) {
1144 default:
1145 llvm_unreachable("Unknown DWARF flavour");
1146 case 0:
1147 mapLLVMRegsToDwarfRegs(Map: VEEHFlavour0L2Dwarf, Size: VEEHFlavour0L2DwarfSize, isEH: true);
1148 break;
1149 }
1150}
1151
1152static const MCPhysReg CSR_SaveList[] = { VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, 0 };
1153static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000ff0, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
1154static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
1155static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
1156static const MCPhysReg CSR_preserve_all_SaveList[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, VE::VM12, VE::VM13, VE::VM14, VE::VM15, 0 };
1157static const uint32_t CSR_preserve_all_RegMask[] = { 0xf8000000, 0xfbffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xffffffff, 0x0007ffff, };
1158
1159
1160ArrayRef<const uint32_t *> VEGenRegisterInfo::getRegMasks() const {
1161 static const uint32_t *const Masks[] = {
1162 CSR_RegMask,
1163 CSR_NoRegs_RegMask,
1164 CSR_preserve_all_RegMask,
1165 };
1166 return ArrayRef(Masks);
1167}
1168
1169bool VEGenRegisterInfo::
1170isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1171 return
1172 false;
1173}
1174
1175bool VEGenRegisterInfo::
1176isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1177 return
1178 false;
1179}
1180
1181bool VEGenRegisterInfo::
1182isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1183 return
1184 false;
1185}
1186
1187bool VEGenRegisterInfo::
1188isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1189 return
1190 false;
1191}
1192
1193bool VEGenRegisterInfo::
1194isConstantPhysReg(MCRegister PhysReg) const {
1195 return
1196 PhysReg == VE::VM0 ||
1197 PhysReg == VE::VMP0 ||
1198 false;
1199}
1200
1201ArrayRef<const char *> VEGenRegisterInfo::getRegMaskNames() const {
1202 static const char *Names[] = {
1203 "CSR",
1204 "CSR_NoRegs",
1205 "CSR_preserve_all",
1206 };
1207 return ArrayRef(Names);
1208}
1209
1210const VEFrameLowering *
1211VEGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1212 return static_cast<const VEFrameLowering *>(
1213 MF.getSubtarget().getFrameLowering());
1214}
1215
1216
1217} // namespace llvm
1218