1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<10, 344, 253, 18, 12, 1> VEMCRegisterClassStorage;
12
13static const MVT::SimpleValueType VEVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f32, MVT::Other,
17 /* 6 */ MVT::i64, MVT::f64, MVT::Other,
18 /* 9 */ MVT::f128, MVT::Other,
19 /* 11 */ MVT::v256i1, MVT::Other,
20 /* 13 */ MVT::v512i1, MVT::Other,
21 /* 15 */ MVT::v256f64, MVT::v512i32, MVT::v512f32, MVT::v256i64, MVT::v256i32, MVT::v256f32, MVT::Other,
22};
23
24#ifdef __GNUC__
25#pragma GCC diagnostic push
26#pragma GCC diagnostic ignored "-Woverlength-strings"
27#endif
28static constexpr char VESubRegIndexStrings[] = {
29 /* 0 */ "sub_odd_then_sub_f32\000"
30 /* 21 */ "sub_odd_then_sub_i32\000"
31 /* 42 */ "sub_odd\000"
32 /* 50 */ "sub_vm_odd\000"
33 /* 61 */ "sub_even\000"
34 /* 70 */ "sub_vm_even\000"
35};
36#ifdef __GNUC__
37#pragma GCC diagnostic pop
38#endif
39
40
41static constexpr uint32_t VESubRegIndexNameOffsets[] = {
42 61,
43 13,
44 34,
45 42,
46 70,
47 50,
48 0,
49 21,
50};
51
52static const TargetRegisterInfo::SubRegCoveredBits VESubRegIdxRangeTable[] = {
53 { .Offset: 4294967295, .Size: 4294967295 },
54 { .Offset: 0, .Size: 64 }, // sub_even
55 { .Offset: 0, .Size: 32 }, // sub_f32
56 { .Offset: 32, .Size: 32 }, // sub_i32
57 { .Offset: 64, .Size: 64 }, // sub_odd
58 { .Offset: 0, .Size: 256 }, // sub_vm_even
59 { .Offset: 256, .Size: 256 }, // sub_vm_odd
60 { .Offset: 64, .Size: 32 }, // sub_odd_then_sub_f32
61 { .Offset: 96, .Size: 32 }, // sub_odd_then_sub_i32
62};
63
64
65static const LaneBitmask VESubRegIndexLaneMaskTable[] = {
66 LaneBitmask::getAll(),
67 LaneBitmask(0x0000000000000003), // sub_even
68 LaneBitmask(0x0000000000000001), // sub_f32
69 LaneBitmask(0x0000000000000002), // sub_i32
70 LaneBitmask(0x0000000000000030), // sub_odd
71 LaneBitmask(0x0000000000000004), // sub_vm_even
72 LaneBitmask(0x0000000000000008), // sub_vm_odd
73 LaneBitmask(0x0000000000000010), // sub_odd_then_sub_f32
74 LaneBitmask(0x0000000000000020), // sub_odd_then_sub_i32
75 };
76
77
78
79static const TargetRegisterInfo::RegClassInfo VERegClassInfos[] = {
80 // Mode = 0 (DefaultMode)
81 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VEVTLists+*/.VTListOffset: 4 }, // F32
82 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VEVTLists+*/.VTListOffset: 0 }, // I32
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 0 }, // VLS
84 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 6 }, // I64
85 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 2 }, // MISC
86 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VEVTLists+*/.VTListOffset: 9 }, // F128
87 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 11 }, // VM
88 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 13 }, // VM512
89 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 13 }, // VM512_with_sub_vm_even
90 { .RegSize: 16384, .SpillSize: 16384, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 15 }, // V64
91};
92
93static const uint8_t VECostPerUseTable[] = {
940, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
95
96
97static const bool VEInAllocatableClassTable[] = {
98false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
99
100
101static const TargetRegisterInfoDesc VERegInfoDesc = { // Extra Descriptors
102.CostPerUse: VECostPerUseTable, .NumCosts: 1, .InAllocatableClass: VEInAllocatableClassTable};
103
104unsigned VEGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
105 static const uint8_t RowMap[8] = {
106 0, 0, 0, 1, 0, 0, 0, 0,
107 };
108 static const uint8_t Rows[2][8] = {
109 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
110 { 0, VE::sub_odd_then_sub_f32, VE::sub_odd_then_sub_i32, 0, 0, 0, 0, 0, },
111 };
112
113 --IdxA; assert(IdxA < 8); (void) IdxA;
114 --IdxB; assert(IdxB < 8);
115 return Rows[RowMap[IdxA]][IdxB];
116}
117
118unsigned VEGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
119 static const uint8_t Table[8][8] = {
120 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
121 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
122 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
123 { 0, 0, 0, 0, 0, 0, VE::sub_f32, VE::sub_i32, },
124 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
125 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
126 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
127 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
128 };
129
130 --IdxA; assert(IdxA < 8);
131 --IdxB; assert(IdxB < 8);
132 return Table[IdxA][IdxB];
133 }
134
135 struct MaskRolOp {
136 LaneBitmask Mask;
137 uint8_t RotateLeft;
138 };
139 static const MaskRolOp LaneMaskComposeSequences[] = {
140 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
141 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
142 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
143 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
144 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
145 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 10
146 };
147 static const uint8_t CompositeSequences[] = {
148 0, // to sub_even
149 0, // to sub_f32
150 2, // to sub_i32
151 4, // to sub_odd
152 6, // to sub_vm_even
153 8, // to sub_vm_odd
154 4, // to sub_odd_then_sub_f32
155 10 // to sub_odd_then_sub_i32
156 };
157
158LaneBitmask VEGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
159 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
160 LaneBitmask Result;
161 for (const MaskRolOp *Ops =
162 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
163 Ops->Mask.any(); ++Ops) {
164 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
165 if (unsigned S = Ops->RotateLeft)
166 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
167 else
168 Result |= LaneBitmask(M);
169 }
170 return Result;
171}
172
173LaneBitmask VEGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
174 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
175 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
176 LaneBitmask Result;
177 for (const MaskRolOp *Ops =
178 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
179 Ops->Mask.any(); ++Ops) {
180 LaneBitmask::Type M = LaneMask.getAsInteger();
181 if (unsigned S = Ops->RotateLeft)
182 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
183 else
184 Result |= LaneBitmask(M);
185 }
186 return Result;
187}
188
189const TargetRegisterClass *VEGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
190 static constexpr uint8_t Table[10][8] = {
191 { // F32
192 0, // sub_even
193 0, // sub_f32
194 0, // sub_i32
195 0, // sub_odd
196 0, // sub_vm_even
197 0, // sub_vm_odd
198 0, // sub_odd_then_sub_f32
199 0, // sub_odd_then_sub_i32
200 },
201 { // I32
202 0, // sub_even
203 0, // sub_f32
204 0, // sub_i32
205 0, // sub_odd
206 0, // sub_vm_even
207 0, // sub_vm_odd
208 0, // sub_odd_then_sub_f32
209 0, // sub_odd_then_sub_i32
210 },
211 { // VLS
212 0, // sub_even
213 0, // sub_f32
214 0, // sub_i32
215 0, // sub_odd
216 0, // sub_vm_even
217 0, // sub_vm_odd
218 0, // sub_odd_then_sub_f32
219 0, // sub_odd_then_sub_i32
220 },
221 { // I64
222 0, // sub_even
223 4, // sub_f32 -> I64
224 4, // sub_i32 -> I64
225 0, // sub_odd
226 0, // sub_vm_even
227 0, // sub_vm_odd
228 0, // sub_odd_then_sub_f32
229 0, // sub_odd_then_sub_i32
230 },
231 { // MISC
232 0, // sub_even
233 0, // sub_f32
234 0, // sub_i32
235 0, // sub_odd
236 0, // sub_vm_even
237 0, // sub_vm_odd
238 0, // sub_odd_then_sub_f32
239 0, // sub_odd_then_sub_i32
240 },
241 { // F128
242 6, // sub_even -> F128
243 6, // sub_f32 -> F128
244 6, // sub_i32 -> F128
245 6, // sub_odd -> F128
246 0, // sub_vm_even
247 0, // sub_vm_odd
248 6, // sub_odd_then_sub_f32 -> F128
249 6, // sub_odd_then_sub_i32 -> F128
250 },
251 { // VM
252 0, // sub_even
253 0, // sub_f32
254 0, // sub_i32
255 0, // sub_odd
256 0, // sub_vm_even
257 0, // sub_vm_odd
258 0, // sub_odd_then_sub_f32
259 0, // sub_odd_then_sub_i32
260 },
261 { // VM512
262 0, // sub_even
263 0, // sub_f32
264 0, // sub_i32
265 0, // sub_odd
266 9, // sub_vm_even -> VM512_with_sub_vm_even
267 9, // sub_vm_odd -> VM512_with_sub_vm_even
268 0, // sub_odd_then_sub_f32
269 0, // sub_odd_then_sub_i32
270 },
271 { // VM512_with_sub_vm_even
272 0, // sub_even
273 0, // sub_f32
274 0, // sub_i32
275 0, // sub_odd
276 9, // sub_vm_even -> VM512_with_sub_vm_even
277 9, // sub_vm_odd -> VM512_with_sub_vm_even
278 0, // sub_odd_then_sub_f32
279 0, // sub_odd_then_sub_i32
280 },
281 { // V64
282 0, // sub_even
283 0, // sub_f32
284 0, // sub_i32
285 0, // sub_odd
286 0, // sub_vm_even
287 0, // sub_vm_odd
288 0, // sub_odd_then_sub_f32
289 0, // sub_odd_then_sub_i32
290 },
291
292 };
293 assert(RC && "Missing regclass");
294 if (!Idx) return RC;
295 --Idx;
296 assert(Idx < 8 && "Bad subreg");
297 unsigned TV = Table[RC->getID()][Idx];
298 return TV ? getRegClass(i: TV - 1) : nullptr;
299}const TargetRegisterClass *VEGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
300 static constexpr uint8_t Table[10][8] = {
301 { // F32
302 0, // F32:sub_even
303 0, // F32:sub_f32
304 0, // F32:sub_i32
305 0, // F32:sub_odd
306 0, // F32:sub_vm_even
307 0, // F32:sub_vm_odd
308 0, // F32:sub_odd_then_sub_f32
309 0, // F32:sub_odd_then_sub_i32
310 },
311 { // I32
312 0, // I32:sub_even
313 0, // I32:sub_f32
314 0, // I32:sub_i32
315 0, // I32:sub_odd
316 0, // I32:sub_vm_even
317 0, // I32:sub_vm_odd
318 0, // I32:sub_odd_then_sub_f32
319 0, // I32:sub_odd_then_sub_i32
320 },
321 { // VLS
322 0, // VLS:sub_even
323 0, // VLS:sub_f32
324 0, // VLS:sub_i32
325 0, // VLS:sub_odd
326 0, // VLS:sub_vm_even
327 0, // VLS:sub_vm_odd
328 0, // VLS:sub_odd_then_sub_f32
329 0, // VLS:sub_odd_then_sub_i32
330 },
331 { // I64
332 0, // I64:sub_even
333 1, // I64:sub_f32 -> F32
334 2, // I64:sub_i32 -> I32
335 0, // I64:sub_odd
336 0, // I64:sub_vm_even
337 0, // I64:sub_vm_odd
338 0, // I64:sub_odd_then_sub_f32
339 0, // I64:sub_odd_then_sub_i32
340 },
341 { // MISC
342 0, // MISC:sub_even
343 0, // MISC:sub_f32
344 0, // MISC:sub_i32
345 0, // MISC:sub_odd
346 0, // MISC:sub_vm_even
347 0, // MISC:sub_vm_odd
348 0, // MISC:sub_odd_then_sub_f32
349 0, // MISC:sub_odd_then_sub_i32
350 },
351 { // F128
352 4, // F128:sub_even -> I64
353 1, // F128:sub_f32 -> F32
354 2, // F128:sub_i32 -> I32
355 4, // F128:sub_odd -> I64
356 0, // F128:sub_vm_even
357 0, // F128:sub_vm_odd
358 1, // F128:sub_odd_then_sub_f32 -> F32
359 2, // F128:sub_odd_then_sub_i32 -> I32
360 },
361 { // VM
362 0, // VM:sub_even
363 0, // VM:sub_f32
364 0, // VM:sub_i32
365 0, // VM:sub_odd
366 0, // VM:sub_vm_even
367 0, // VM:sub_vm_odd
368 0, // VM:sub_odd_then_sub_f32
369 0, // VM:sub_odd_then_sub_i32
370 },
371 { // VM512
372 0, // VM512:sub_even
373 0, // VM512:sub_f32
374 0, // VM512:sub_i32
375 0, // VM512:sub_odd
376 7, // VM512:sub_vm_even -> VM
377 7, // VM512:sub_vm_odd -> VM
378 0, // VM512:sub_odd_then_sub_f32
379 0, // VM512:sub_odd_then_sub_i32
380 },
381 { // VM512_with_sub_vm_even
382 0, // VM512_with_sub_vm_even:sub_even
383 0, // VM512_with_sub_vm_even:sub_f32
384 0, // VM512_with_sub_vm_even:sub_i32
385 0, // VM512_with_sub_vm_even:sub_odd
386 7, // VM512_with_sub_vm_even:sub_vm_even -> VM
387 7, // VM512_with_sub_vm_even:sub_vm_odd -> VM
388 0, // VM512_with_sub_vm_even:sub_odd_then_sub_f32
389 0, // VM512_with_sub_vm_even:sub_odd_then_sub_i32
390 },
391 { // V64
392 0, // V64:sub_even
393 0, // V64:sub_f32
394 0, // V64:sub_i32
395 0, // V64:sub_odd
396 0, // V64:sub_vm_even
397 0, // V64:sub_vm_odd
398 0, // V64:sub_odd_then_sub_f32
399 0, // V64:sub_odd_then_sub_i32
400 },
401
402 };
403 assert(RC && "Missing regclass");
404 if (!Idx) return RC;
405 --Idx;
406 assert(Idx < 8 && "Bad subreg");
407 unsigned TV = Table[RC->getID()][Idx];
408 return TV ? getRegClass(i: TV - 1) : nullptr;
409}/// Get the weight in units of pressure for this register class.
410const RegClassWeight &VEGenRegisterInfo::
411getRegClassWeight(const TargetRegisterClass *RC) const {
412 static const RegClassWeight RCWeightTable[] = {
413 {.RegWeight: 2, .WeightLimit: 128}, // F32
414 {.RegWeight: 2, .WeightLimit: 128}, // I32
415 {.RegWeight: 1, .WeightLimit: 1}, // VLS
416 {.RegWeight: 3, .WeightLimit: 192}, // I64
417 {.RegWeight: 1, .WeightLimit: 23}, // MISC
418 {.RegWeight: 6, .WeightLimit: 192}, // F128
419 {.RegWeight: 1, .WeightLimit: 16}, // VM
420 {.RegWeight: 2, .WeightLimit: 16}, // VM512
421 {.RegWeight: 2, .WeightLimit: 14}, // VM512_with_sub_vm_even
422 {.RegWeight: 1, .WeightLimit: 65}, // V64
423 };
424 return RCWeightTable[RC->getID()];
425}
426
427/// Get the weight in units of pressure for this register unit.
428unsigned VEGenRegisterInfo::
429getRegUnitWeight(MCRegUnit RegUnit) const {
430 assert(static_cast<unsigned>(RegUnit) < 299 && "invalid register unit");
431 static const uint8_t RUWeightTable[] = {
432 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, };
433 return RUWeightTable[static_cast<unsigned>(RegUnit)];
434}
435
436
437// Get the number of dimensions of register pressure.
438unsigned VEGenRegisterInfo::getNumRegPressureSets() const {
439 return 9;
440}
441
442// Get the name of this register unit pressure set.
443const char *VEGenRegisterInfo::
444getRegPressureSetName(unsigned Idx) const {
445 static const char *PressureNameTable[] = {
446 "VLS",
447 "VM512",
448 "VM",
449 "VM_with_VM512",
450 "MISC",
451 "V64",
452 "F32",
453 "I32",
454 "I64",
455 };
456 return PressureNameTable[Idx];
457}
458
459// Get the register unit pressure limit for this dimension.
460// This limit must be adjusted dynamically for reserved registers.
461unsigned VEGenRegisterInfo::
462getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
463 static const uint8_t PressureLimitTable[] = {
464 1, // 0: VLS
465 16, // 1: VM512
466 16, // 2: VM
467 18, // 3: VM_with_VM512
468 23, // 4: MISC
469 65, // 5: V64
470 128, // 6: F32
471 128, // 7: I32
472 192, // 8: I64
473 };
474 return PressureLimitTable[Idx];
475}
476
477/// Table of pressure sets per register class or unit.
478static const int RCSetsTable[] = {
479 /* 0 */ 0, -1,
480 /* 2 */ 1, 3, -1,
481 /* 5 */ 1, 2, 3, -1,
482 /* 9 */ 4, -1,
483 /* 11 */ 5, -1,
484 /* 13 */ 6, 8, -1,
485 /* 16 */ 6, 7, 8, -1,
486};
487
488/// Get the dimensions of register pressure impacted by this register class.
489/// Returns a -1 terminated array of pressure set IDs
490const int *VEGenRegisterInfo::
491getRegClassPressureSets(const TargetRegisterClass *RC) const {
492 static const uint8_t RCSetStartTable[] = {
493 13,17,0,14,9,14,6,2,5,11,};
494 return &RCSetsTable[RCSetStartTable[RC->getID()]];
495}
496
497/// Get the dimensions of register pressure impacted by this register unit.
498/// Returns a -1 terminated array of pressure set IDs
499const int *VEGenRegisterInfo::
500getRegUnitPressureSets(MCRegUnit RegUnit) const {
501 assert(static_cast<unsigned>(RegUnit) < 299 && "invalid register unit");
502 static const uint8_t RUSetStartTable[] = {
503 1,9,9,9,9,11,0,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,6,6,5,5,5,5,5,5,5,5,5,5,5,5,5,5,2,};
504 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
505}
506
507
508// Register to minimal register class mapping
509
510const TargetRegisterClass *VEGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
511 static const uint16_t InvalidRegClassID = UINT16_MAX;
512
513 static const uint16_t Mapping[339] = {
514 InvalidRegClassID, // NoRegister
515 InvalidRegClassID, // IC
516 VE::MISCRegClassID, // PMMR
517 VE::MISCRegClassID, // PSW
518 VE::MISCRegClassID, // SAR
519 VE::MISCRegClassID, // USRCC
520 VE::V64RegClassID, // VIX
521 VE::VLSRegClassID, // VL
522 VE::MISCRegClassID, // PMC0
523 VE::MISCRegClassID, // PMC1
524 VE::MISCRegClassID, // PMC2
525 VE::MISCRegClassID, // PMC3
526 VE::MISCRegClassID, // PMC4
527 VE::MISCRegClassID, // PMC5
528 VE::MISCRegClassID, // PMC6
529 VE::MISCRegClassID, // PMC7
530 VE::MISCRegClassID, // PMC8
531 VE::MISCRegClassID, // PMC9
532 VE::MISCRegClassID, // PMC10
533 VE::MISCRegClassID, // PMC11
534 VE::MISCRegClassID, // PMC12
535 VE::MISCRegClassID, // PMC13
536 VE::MISCRegClassID, // PMC14
537 VE::MISCRegClassID, // PMCR0
538 VE::MISCRegClassID, // PMCR1
539 VE::MISCRegClassID, // PMCR2
540 VE::MISCRegClassID, // PMCR3
541 VE::F128RegClassID, // Q0
542 VE::F128RegClassID, // Q1
543 VE::F128RegClassID, // Q2
544 VE::F128RegClassID, // Q3
545 VE::F128RegClassID, // Q4
546 VE::F128RegClassID, // Q5
547 VE::F128RegClassID, // Q6
548 VE::F128RegClassID, // Q7
549 VE::F128RegClassID, // Q8
550 VE::F128RegClassID, // Q9
551 VE::F128RegClassID, // Q10
552 VE::F128RegClassID, // Q11
553 VE::F128RegClassID, // Q12
554 VE::F128RegClassID, // Q13
555 VE::F128RegClassID, // Q14
556 VE::F128RegClassID, // Q15
557 VE::F128RegClassID, // Q16
558 VE::F128RegClassID, // Q17
559 VE::F128RegClassID, // Q18
560 VE::F128RegClassID, // Q19
561 VE::F128RegClassID, // Q20
562 VE::F128RegClassID, // Q21
563 VE::F128RegClassID, // Q22
564 VE::F128RegClassID, // Q23
565 VE::F128RegClassID, // Q24
566 VE::F128RegClassID, // Q25
567 VE::F128RegClassID, // Q26
568 VE::F128RegClassID, // Q27
569 VE::F128RegClassID, // Q28
570 VE::F128RegClassID, // Q29
571 VE::F128RegClassID, // Q30
572 VE::F128RegClassID, // Q31
573 VE::F32RegClassID, // SF0
574 VE::F32RegClassID, // SF1
575 VE::F32RegClassID, // SF2
576 VE::F32RegClassID, // SF3
577 VE::F32RegClassID, // SF4
578 VE::F32RegClassID, // SF5
579 VE::F32RegClassID, // SF6
580 VE::F32RegClassID, // SF7
581 VE::F32RegClassID, // SF8
582 VE::F32RegClassID, // SF9
583 VE::F32RegClassID, // SF10
584 VE::F32RegClassID, // SF11
585 VE::F32RegClassID, // SF12
586 VE::F32RegClassID, // SF13
587 VE::F32RegClassID, // SF14
588 VE::F32RegClassID, // SF15
589 VE::F32RegClassID, // SF16
590 VE::F32RegClassID, // SF17
591 VE::F32RegClassID, // SF18
592 VE::F32RegClassID, // SF19
593 VE::F32RegClassID, // SF20
594 VE::F32RegClassID, // SF21
595 VE::F32RegClassID, // SF22
596 VE::F32RegClassID, // SF23
597 VE::F32RegClassID, // SF24
598 VE::F32RegClassID, // SF25
599 VE::F32RegClassID, // SF26
600 VE::F32RegClassID, // SF27
601 VE::F32RegClassID, // SF28
602 VE::F32RegClassID, // SF29
603 VE::F32RegClassID, // SF30
604 VE::F32RegClassID, // SF31
605 VE::F32RegClassID, // SF32
606 VE::F32RegClassID, // SF33
607 VE::F32RegClassID, // SF34
608 VE::F32RegClassID, // SF35
609 VE::F32RegClassID, // SF36
610 VE::F32RegClassID, // SF37
611 VE::F32RegClassID, // SF38
612 VE::F32RegClassID, // SF39
613 VE::F32RegClassID, // SF40
614 VE::F32RegClassID, // SF41
615 VE::F32RegClassID, // SF42
616 VE::F32RegClassID, // SF43
617 VE::F32RegClassID, // SF44
618 VE::F32RegClassID, // SF45
619 VE::F32RegClassID, // SF46
620 VE::F32RegClassID, // SF47
621 VE::F32RegClassID, // SF48
622 VE::F32RegClassID, // SF49
623 VE::F32RegClassID, // SF50
624 VE::F32RegClassID, // SF51
625 VE::F32RegClassID, // SF52
626 VE::F32RegClassID, // SF53
627 VE::F32RegClassID, // SF54
628 VE::F32RegClassID, // SF55
629 VE::F32RegClassID, // SF56
630 VE::F32RegClassID, // SF57
631 VE::F32RegClassID, // SF58
632 VE::F32RegClassID, // SF59
633 VE::F32RegClassID, // SF60
634 VE::F32RegClassID, // SF61
635 VE::F32RegClassID, // SF62
636 VE::F32RegClassID, // SF63
637 VE::I32RegClassID, // SW0
638 VE::I32RegClassID, // SW1
639 VE::I32RegClassID, // SW2
640 VE::I32RegClassID, // SW3
641 VE::I32RegClassID, // SW4
642 VE::I32RegClassID, // SW5
643 VE::I32RegClassID, // SW6
644 VE::I32RegClassID, // SW7
645 VE::I32RegClassID, // SW8
646 VE::I32RegClassID, // SW9
647 VE::I32RegClassID, // SW10
648 VE::I32RegClassID, // SW11
649 VE::I32RegClassID, // SW12
650 VE::I32RegClassID, // SW13
651 VE::I32RegClassID, // SW14
652 VE::I32RegClassID, // SW15
653 VE::I32RegClassID, // SW16
654 VE::I32RegClassID, // SW17
655 VE::I32RegClassID, // SW18
656 VE::I32RegClassID, // SW19
657 VE::I32RegClassID, // SW20
658 VE::I32RegClassID, // SW21
659 VE::I32RegClassID, // SW22
660 VE::I32RegClassID, // SW23
661 VE::I32RegClassID, // SW24
662 VE::I32RegClassID, // SW25
663 VE::I32RegClassID, // SW26
664 VE::I32RegClassID, // SW27
665 VE::I32RegClassID, // SW28
666 VE::I32RegClassID, // SW29
667 VE::I32RegClassID, // SW30
668 VE::I32RegClassID, // SW31
669 VE::I32RegClassID, // SW32
670 VE::I32RegClassID, // SW33
671 VE::I32RegClassID, // SW34
672 VE::I32RegClassID, // SW35
673 VE::I32RegClassID, // SW36
674 VE::I32RegClassID, // SW37
675 VE::I32RegClassID, // SW38
676 VE::I32RegClassID, // SW39
677 VE::I32RegClassID, // SW40
678 VE::I32RegClassID, // SW41
679 VE::I32RegClassID, // SW42
680 VE::I32RegClassID, // SW43
681 VE::I32RegClassID, // SW44
682 VE::I32RegClassID, // SW45
683 VE::I32RegClassID, // SW46
684 VE::I32RegClassID, // SW47
685 VE::I32RegClassID, // SW48
686 VE::I32RegClassID, // SW49
687 VE::I32RegClassID, // SW50
688 VE::I32RegClassID, // SW51
689 VE::I32RegClassID, // SW52
690 VE::I32RegClassID, // SW53
691 VE::I32RegClassID, // SW54
692 VE::I32RegClassID, // SW55
693 VE::I32RegClassID, // SW56
694 VE::I32RegClassID, // SW57
695 VE::I32RegClassID, // SW58
696 VE::I32RegClassID, // SW59
697 VE::I32RegClassID, // SW60
698 VE::I32RegClassID, // SW61
699 VE::I32RegClassID, // SW62
700 VE::I32RegClassID, // SW63
701 VE::I64RegClassID, // SX0
702 VE::I64RegClassID, // SX1
703 VE::I64RegClassID, // SX2
704 VE::I64RegClassID, // SX3
705 VE::I64RegClassID, // SX4
706 VE::I64RegClassID, // SX5
707 VE::I64RegClassID, // SX6
708 VE::I64RegClassID, // SX7
709 VE::I64RegClassID, // SX8
710 VE::I64RegClassID, // SX9
711 VE::I64RegClassID, // SX10
712 VE::I64RegClassID, // SX11
713 VE::I64RegClassID, // SX12
714 VE::I64RegClassID, // SX13
715 VE::I64RegClassID, // SX14
716 VE::I64RegClassID, // SX15
717 VE::I64RegClassID, // SX16
718 VE::I64RegClassID, // SX17
719 VE::I64RegClassID, // SX18
720 VE::I64RegClassID, // SX19
721 VE::I64RegClassID, // SX20
722 VE::I64RegClassID, // SX21
723 VE::I64RegClassID, // SX22
724 VE::I64RegClassID, // SX23
725 VE::I64RegClassID, // SX24
726 VE::I64RegClassID, // SX25
727 VE::I64RegClassID, // SX26
728 VE::I64RegClassID, // SX27
729 VE::I64RegClassID, // SX28
730 VE::I64RegClassID, // SX29
731 VE::I64RegClassID, // SX30
732 VE::I64RegClassID, // SX31
733 VE::I64RegClassID, // SX32
734 VE::I64RegClassID, // SX33
735 VE::I64RegClassID, // SX34
736 VE::I64RegClassID, // SX35
737 VE::I64RegClassID, // SX36
738 VE::I64RegClassID, // SX37
739 VE::I64RegClassID, // SX38
740 VE::I64RegClassID, // SX39
741 VE::I64RegClassID, // SX40
742 VE::I64RegClassID, // SX41
743 VE::I64RegClassID, // SX42
744 VE::I64RegClassID, // SX43
745 VE::I64RegClassID, // SX44
746 VE::I64RegClassID, // SX45
747 VE::I64RegClassID, // SX46
748 VE::I64RegClassID, // SX47
749 VE::I64RegClassID, // SX48
750 VE::I64RegClassID, // SX49
751 VE::I64RegClassID, // SX50
752 VE::I64RegClassID, // SX51
753 VE::I64RegClassID, // SX52
754 VE::I64RegClassID, // SX53
755 VE::I64RegClassID, // SX54
756 VE::I64RegClassID, // SX55
757 VE::I64RegClassID, // SX56
758 VE::I64RegClassID, // SX57
759 VE::I64RegClassID, // SX58
760 VE::I64RegClassID, // SX59
761 VE::I64RegClassID, // SX60
762 VE::I64RegClassID, // SX61
763 VE::I64RegClassID, // SX62
764 VE::I64RegClassID, // SX63
765 VE::V64RegClassID, // V0
766 VE::V64RegClassID, // V1
767 VE::V64RegClassID, // V2
768 VE::V64RegClassID, // V3
769 VE::V64RegClassID, // V4
770 VE::V64RegClassID, // V5
771 VE::V64RegClassID, // V6
772 VE::V64RegClassID, // V7
773 VE::V64RegClassID, // V8
774 VE::V64RegClassID, // V9
775 VE::V64RegClassID, // V10
776 VE::V64RegClassID, // V11
777 VE::V64RegClassID, // V12
778 VE::V64RegClassID, // V13
779 VE::V64RegClassID, // V14
780 VE::V64RegClassID, // V15
781 VE::V64RegClassID, // V16
782 VE::V64RegClassID, // V17
783 VE::V64RegClassID, // V18
784 VE::V64RegClassID, // V19
785 VE::V64RegClassID, // V20
786 VE::V64RegClassID, // V21
787 VE::V64RegClassID, // V22
788 VE::V64RegClassID, // V23
789 VE::V64RegClassID, // V24
790 VE::V64RegClassID, // V25
791 VE::V64RegClassID, // V26
792 VE::V64RegClassID, // V27
793 VE::V64RegClassID, // V28
794 VE::V64RegClassID, // V29
795 VE::V64RegClassID, // V30
796 VE::V64RegClassID, // V31
797 VE::V64RegClassID, // V32
798 VE::V64RegClassID, // V33
799 VE::V64RegClassID, // V34
800 VE::V64RegClassID, // V35
801 VE::V64RegClassID, // V36
802 VE::V64RegClassID, // V37
803 VE::V64RegClassID, // V38
804 VE::V64RegClassID, // V39
805 VE::V64RegClassID, // V40
806 VE::V64RegClassID, // V41
807 VE::V64RegClassID, // V42
808 VE::V64RegClassID, // V43
809 VE::V64RegClassID, // V44
810 VE::V64RegClassID, // V45
811 VE::V64RegClassID, // V46
812 VE::V64RegClassID, // V47
813 VE::V64RegClassID, // V48
814 VE::V64RegClassID, // V49
815 VE::V64RegClassID, // V50
816 VE::V64RegClassID, // V51
817 VE::V64RegClassID, // V52
818 VE::V64RegClassID, // V53
819 VE::V64RegClassID, // V54
820 VE::V64RegClassID, // V55
821 VE::V64RegClassID, // V56
822 VE::V64RegClassID, // V57
823 VE::V64RegClassID, // V58
824 VE::V64RegClassID, // V59
825 VE::V64RegClassID, // V60
826 VE::V64RegClassID, // V61
827 VE::V64RegClassID, // V62
828 VE::V64RegClassID, // V63
829 VE::VMRegClassID, // VM0
830 VE::VMRegClassID, // VM1
831 VE::VMRegClassID, // VM2
832 VE::VMRegClassID, // VM3
833 VE::VMRegClassID, // VM4
834 VE::VMRegClassID, // VM5
835 VE::VMRegClassID, // VM6
836 VE::VMRegClassID, // VM7
837 VE::VMRegClassID, // VM8
838 VE::VMRegClassID, // VM9
839 VE::VMRegClassID, // VM10
840 VE::VMRegClassID, // VM11
841 VE::VMRegClassID, // VM12
842 VE::VMRegClassID, // VM13
843 VE::VMRegClassID, // VM14
844 VE::VMRegClassID, // VM15
845 VE::VM512RegClassID, // VMP0
846 VE::VM512_with_sub_vm_evenRegClassID, // VMP1
847 VE::VM512_with_sub_vm_evenRegClassID, // VMP2
848 VE::VM512_with_sub_vm_evenRegClassID, // VMP3
849 VE::VM512_with_sub_vm_evenRegClassID, // VMP4
850 VE::VM512_with_sub_vm_evenRegClassID, // VMP5
851 VE::VM512_with_sub_vm_evenRegClassID, // VMP6
852 VE::VM512_with_sub_vm_evenRegClassID, // VMP7
853 };
854
855 assert(Reg < ArrayRef(Mapping).size());
856 unsigned RCID = Mapping[Reg.id()];
857 if (RCID == InvalidRegClassID)
858 return nullptr;
859 return &VEMCRegisterClassStorage.Classes[RCID];
860}
861extern const MCRegisterDesc VERegDesc[];
862extern const int16_t VERegDiffLists[];
863extern const LaneBitmask VELaneMaskLists[];
864extern const char VERegStrings[];
865extern const char VERegClassStrings[];
866extern const MCPhysReg VERegUnitRoots[][2];
867extern const uint16_t VESubRegIdxLists[];
868extern const uint16_t VERegEncodingTable[];
869// VE Dwarf<->LLVM register mappings.
870extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0Dwarf2L[];
871extern const unsigned VEDwarfFlavour0Dwarf2LSize;
872
873extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0Dwarf2L[];
874extern const unsigned VEEHFlavour0Dwarf2LSize;
875
876extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0L2Dwarf[];
877extern const unsigned VEDwarfFlavour0L2DwarfSize;
878
879extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0L2Dwarf[];
880extern const unsigned VEEHFlavour0L2DwarfSize;
881
882
883VEGenRegisterInfo::
884VEGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
885 unsigned PC, unsigned HwMode)
886 : TargetRegisterInfo(&VERegInfoDesc,
887 VESubRegIndexStrings, VESubRegIndexNameOffsets,
888 VESubRegIdxRangeTable, VESubRegIndexLaneMaskTable,
889
890 LaneBitmask(0xFFFFFFFFFFFFFFFF), VERegClassInfos, VEVTLists, HwMode) {
891 InitMCRegisterInfo(D: VERegDesc, NR: 339, RA, PC,
892 C: &getVEMCRegisterClass(RC: 0), NC: 10, RURoots: VERegUnitRoots, NRU: 299, DL: VERegDiffLists,
893 RUMS: VELaneMaskLists, Strings: VERegStrings, ClassStrings: VERegClassStrings, SubIndices: VESubRegIdxLists, NumIndices: 9,
894 RET: VERegEncodingTable, RUI: nullptr);
895
896 switch (DwarfFlavour) {
897 default:
898 llvm_unreachable("Unknown DWARF flavour");
899 case 0:
900 mapDwarfRegsToLLVMRegs(Map: VEDwarfFlavour0Dwarf2L, Size: VEDwarfFlavour0Dwarf2LSize, isEH: false);
901 break;
902 }
903 switch (EHFlavour) {
904 default:
905 llvm_unreachable("Unknown DWARF flavour");
906 case 0:
907 mapDwarfRegsToLLVMRegs(Map: VEEHFlavour0Dwarf2L, Size: VEEHFlavour0Dwarf2LSize, isEH: true);
908 break;
909 }
910 switch (DwarfFlavour) {
911 default:
912 llvm_unreachable("Unknown DWARF flavour");
913 case 0:
914 mapLLVMRegsToDwarfRegs(Map: VEDwarfFlavour0L2Dwarf, Size: VEDwarfFlavour0L2DwarfSize, isEH: false);
915 break;
916 }
917 switch (EHFlavour) {
918 default:
919 llvm_unreachable("Unknown DWARF flavour");
920 case 0:
921 mapLLVMRegsToDwarfRegs(Map: VEEHFlavour0L2Dwarf, Size: VEEHFlavour0L2DwarfSize, isEH: true);
922 break;
923 }
924}
925
926static const MCPhysReg CSR_SaveList[] = { VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, 0 };
927static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000ff0, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
928static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
929static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
930static const MCPhysReg CSR_preserve_all_SaveList[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, VE::VM12, VE::VM13, VE::VM14, VE::VM15, 0 };
931static const uint32_t CSR_preserve_all_RegMask[] = { 0xf8000000, 0xfbffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xffffffff, 0x0007ffff, };
932
933
934ArrayRef<const uint32_t *> VEGenRegisterInfo::getRegMasks() const {
935 static const uint32_t *const Masks[] = {
936 CSR_RegMask,
937 CSR_NoRegs_RegMask,
938 CSR_preserve_all_RegMask,
939 };
940 return ArrayRef(Masks);
941}
942
943bool VEGenRegisterInfo::
944isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
945 return
946 false;
947}
948
949bool VEGenRegisterInfo::
950isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
951 return
952 false;
953}
954
955bool VEGenRegisterInfo::
956isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
957 return
958 false;
959}
960
961bool VEGenRegisterInfo::
962isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
963 return
964 false;
965}
966
967bool VEGenRegisterInfo::
968isConstantPhysReg(MCRegister PhysReg) const {
969 return
970 PhysReg == VE::VM0 ||
971 PhysReg == VE::VMP0 ||
972 false;
973}
974
975ArrayRef<const char *> VEGenRegisterInfo::getRegMaskNames() const {
976 static const char *Names[] = {
977 "CSR",
978 "CSR_NoRegs",
979 "CSR_preserve_all",
980 };
981 return ArrayRef(Names);
982}
983
984const VEFrameLowering *
985VEGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
986 return static_cast<const VEFrameLowering *>(
987 MF.getSubtarget().getFrameLowering());
988}
989
990
991} // namespace llvm
992