1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass VEMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f32, MVT::Other,
17 /* 6 */ MVT::i64, MVT::f64, MVT::Other,
18 /* 9 */ MVT::f128, MVT::Other,
19 /* 11 */ MVT::v256i1, MVT::Other,
20 /* 13 */ MVT::v512i1, MVT::Other,
21 /* 15 */ MVT::v256f64, MVT::v512i32, MVT::v512f32, MVT::v256i64, MVT::v256i32, MVT::v256f32, MVT::Other,
22};
23
24#ifdef __GNUC__
25#pragma GCC diagnostic push
26#pragma GCC diagnostic ignored "-Woverlength-strings"
27#endif
28static constexpr char VESubRegIndexStrings[] = {
29 /* 0 */ "sub_odd_then_sub_f32\000"
30 /* 21 */ "sub_odd_then_sub_i32\000"
31 /* 42 */ "sub_odd\000"
32 /* 50 */ "sub_vm_odd\000"
33 /* 61 */ "sub_even\000"
34 /* 70 */ "sub_vm_even\000"
35};
36#ifdef __GNUC__
37#pragma GCC diagnostic pop
38#endif
39
40
41static constexpr uint32_t VESubRegIndexNameOffsets[] = {
42 61,
43 13,
44 34,
45 42,
46 70,
47 50,
48 0,
49 21,
50};
51
52static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
53 { .Offset: 65535, .Size: 65535 },
54 { .Offset: 0, .Size: 64 }, // sub_even
55 { .Offset: 0, .Size: 32 }, // sub_f32
56 { .Offset: 32, .Size: 32 }, // sub_i32
57 { .Offset: 64, .Size: 64 }, // sub_odd
58 { .Offset: 0, .Size: 256 }, // sub_vm_even
59 { .Offset: 256, .Size: 256 }, // sub_vm_odd
60 { .Offset: 64, .Size: 32 }, // sub_odd_then_sub_f32
61 { .Offset: 96, .Size: 32 }, // sub_odd_then_sub_i32
62};
63
64
65static const LaneBitmask SubRegIndexLaneMaskTable[] = {
66 LaneBitmask::getAll(),
67 LaneBitmask(0x0000000000000003), // sub_even
68 LaneBitmask(0x0000000000000001), // sub_f32
69 LaneBitmask(0x0000000000000002), // sub_i32
70 LaneBitmask(0x0000000000000030), // sub_odd
71 LaneBitmask(0x0000000000000004), // sub_vm_even
72 LaneBitmask(0x0000000000000008), // sub_vm_odd
73 LaneBitmask(0x0000000000000010), // sub_odd_then_sub_f32
74 LaneBitmask(0x0000000000000020), // sub_odd_then_sub_i32
75 };
76
77
78
79static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
80 // Mode = 0 (DefaultMode)
81 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // F32
82 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // I32
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 0 }, // VLS
84 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // I64
85 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // MISC
86 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 9 }, // F128
87 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 11 }, // VM
88 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // VM512
89 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // VM512_with_sub_vm_even
90 { .RegSize: 16384, .SpillSize: 16384, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 15 }, // V64
91};
92static const uint32_t F32SubClassMask[] = {
93 0x00000001,
94 0x00000028, // sub_f32
95 0x00000020, // sub_odd_then_sub_f32
96};
97
98static const uint32_t I32SubClassMask[] = {
99 0x00000002,
100 0x00000028, // sub_i32
101 0x00000020, // sub_odd_then_sub_i32
102};
103
104static const uint32_t VLSSubClassMask[] = {
105 0x00000004,
106};
107
108static const uint32_t I64SubClassMask[] = {
109 0x00000008,
110 0x00000020, // sub_even
111 0x00000020, // sub_odd
112};
113
114static const uint32_t MISCSubClassMask[] = {
115 0x00000010,
116};
117
118static const uint32_t F128SubClassMask[] = {
119 0x00000020,
120};
121
122static const uint32_t VMSubClassMask[] = {
123 0x00000040,
124 0x00000100, // sub_vm_even
125 0x00000100, // sub_vm_odd
126};
127
128static const uint32_t VM512SubClassMask[] = {
129 0x00000180,
130};
131
132static const uint32_t VM512_with_sub_vm_evenSubClassMask[] = {
133 0x00000100,
134};
135
136static const uint32_t V64SubClassMask[] = {
137 0x00000200,
138};
139
140static const uint16_t SuperRegIdxSeqs[] = {
141 /* 0 */ 1, 4, 0,
142 /* 3 */ 5, 6, 0,
143 /* 6 */ 2, 7, 0,
144 /* 9 */ 3, 8, 0,
145};
146
147static unsigned const VM512_with_sub_vm_evenSuperclasses[] = {
148 VE::VM512RegClassID,
149};
150
151namespace VE {
152
153// Register class instances
154 extern const TargetRegisterClass F32RegClass = {
155 .MC: &VEMCRegisterClasses[F32RegClassID],
156 .SubClassMask: F32SubClassMask,
157 .SuperRegIndices: SuperRegIdxSeqs + 6,
158 .LaneMask: LaneBitmask(0x0000000000000001),
159 .AllocationPriority: 0,
160 .GlobalPriority: false,
161 .TSFlags: 0x00, /* TSFlags */
162 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
163 .CoveredBySubRegs: false, /* CoveredBySubRegs */
164 .SuperClasses: nullptr, .SuperClassesSize: 0,
165 .OrderFunc: nullptr
166 };
167
168 extern const TargetRegisterClass I32RegClass = {
169 .MC: &VEMCRegisterClasses[I32RegClassID],
170 .SubClassMask: I32SubClassMask,
171 .SuperRegIndices: SuperRegIdxSeqs + 9,
172 .LaneMask: LaneBitmask(0x0000000000000001),
173 .AllocationPriority: 0,
174 .GlobalPriority: false,
175 .TSFlags: 0x00, /* TSFlags */
176 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
177 .CoveredBySubRegs: false, /* CoveredBySubRegs */
178 .SuperClasses: nullptr, .SuperClassesSize: 0,
179 .OrderFunc: nullptr
180 };
181
182 extern const TargetRegisterClass VLSRegClass = {
183 .MC: &VEMCRegisterClasses[VLSRegClassID],
184 .SubClassMask: VLSSubClassMask,
185 .SuperRegIndices: SuperRegIdxSeqs + 2,
186 .LaneMask: LaneBitmask(0x0000000000000001),
187 .AllocationPriority: 0,
188 .GlobalPriority: false,
189 .TSFlags: 0x00, /* TSFlags */
190 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
191 .CoveredBySubRegs: false, /* CoveredBySubRegs */
192 .SuperClasses: nullptr, .SuperClassesSize: 0,
193 .OrderFunc: nullptr
194 };
195
196 extern const TargetRegisterClass I64RegClass = {
197 .MC: &VEMCRegisterClasses[I64RegClassID],
198 .SubClassMask: I64SubClassMask,
199 .SuperRegIndices: SuperRegIdxSeqs + 0,
200 .LaneMask: LaneBitmask(0x0000000000000003),
201 .AllocationPriority: 0,
202 .GlobalPriority: false,
203 .TSFlags: 0x00, /* TSFlags */
204 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
205 .CoveredBySubRegs: true, /* CoveredBySubRegs */
206 .SuperClasses: nullptr, .SuperClassesSize: 0,
207 .OrderFunc: nullptr
208 };
209
210 extern const TargetRegisterClass MISCRegClass = {
211 .MC: &VEMCRegisterClasses[MISCRegClassID],
212 .SubClassMask: MISCSubClassMask,
213 .SuperRegIndices: SuperRegIdxSeqs + 2,
214 .LaneMask: LaneBitmask(0x0000000000000001),
215 .AllocationPriority: 0,
216 .GlobalPriority: false,
217 .TSFlags: 0x00, /* TSFlags */
218 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
219 .CoveredBySubRegs: false, /* CoveredBySubRegs */
220 .SuperClasses: nullptr, .SuperClassesSize: 0,
221 .OrderFunc: nullptr
222 };
223
224 extern const TargetRegisterClass F128RegClass = {
225 .MC: &VEMCRegisterClasses[F128RegClassID],
226 .SubClassMask: F128SubClassMask,
227 .SuperRegIndices: SuperRegIdxSeqs + 2,
228 .LaneMask: LaneBitmask(0x0000000000000033),
229 .AllocationPriority: 0,
230 .GlobalPriority: false,
231 .TSFlags: 0x00, /* TSFlags */
232 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
233 .CoveredBySubRegs: true, /* CoveredBySubRegs */
234 .SuperClasses: nullptr, .SuperClassesSize: 0,
235 .OrderFunc: nullptr
236 };
237
238 extern const TargetRegisterClass VMRegClass = {
239 .MC: &VEMCRegisterClasses[VMRegClassID],
240 .SubClassMask: VMSubClassMask,
241 .SuperRegIndices: SuperRegIdxSeqs + 3,
242 .LaneMask: LaneBitmask(0x0000000000000001),
243 .AllocationPriority: 0,
244 .GlobalPriority: false,
245 .TSFlags: 0x00, /* TSFlags */
246 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
247 .CoveredBySubRegs: false, /* CoveredBySubRegs */
248 .SuperClasses: nullptr, .SuperClassesSize: 0,
249 .OrderFunc: nullptr
250 };
251
252 extern const TargetRegisterClass VM512RegClass = {
253 .MC: &VEMCRegisterClasses[VM512RegClassID],
254 .SubClassMask: VM512SubClassMask,
255 .SuperRegIndices: SuperRegIdxSeqs + 2,
256 .LaneMask: LaneBitmask(0x000000000000000C),
257 .AllocationPriority: 0,
258 .GlobalPriority: false,
259 .TSFlags: 0x00, /* TSFlags */
260 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
261 .CoveredBySubRegs: false, /* CoveredBySubRegs */
262 .SuperClasses: nullptr, .SuperClassesSize: 0,
263 .OrderFunc: nullptr
264 };
265
266 extern const TargetRegisterClass VM512_with_sub_vm_evenRegClass = {
267 .MC: &VEMCRegisterClasses[VM512_with_sub_vm_evenRegClassID],
268 .SubClassMask: VM512_with_sub_vm_evenSubClassMask,
269 .SuperRegIndices: SuperRegIdxSeqs + 2,
270 .LaneMask: LaneBitmask(0x000000000000000C),
271 .AllocationPriority: 0,
272 .GlobalPriority: false,
273 .TSFlags: 0x00, /* TSFlags */
274 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
275 .CoveredBySubRegs: true, /* CoveredBySubRegs */
276 .SuperClasses: VM512_with_sub_vm_evenSuperclasses, .SuperClassesSize: 1,
277 .OrderFunc: nullptr
278 };
279
280 extern const TargetRegisterClass V64RegClass = {
281 .MC: &VEMCRegisterClasses[V64RegClassID],
282 .SubClassMask: V64SubClassMask,
283 .SuperRegIndices: SuperRegIdxSeqs + 2,
284 .LaneMask: LaneBitmask(0x0000000000000001),
285 .AllocationPriority: 0,
286 .GlobalPriority: false,
287 .TSFlags: 0x00, /* TSFlags */
288 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
289 .CoveredBySubRegs: false, /* CoveredBySubRegs */
290 .SuperClasses: nullptr, .SuperClassesSize: 0,
291 .OrderFunc: nullptr
292 };
293
294
295} // namespace VE
296namespace {
297
298 const TargetRegisterClass *const RegisterClasses[] = {
299 &VE::F32RegClass,
300 &VE::I32RegClass,
301 &VE::VLSRegClass,
302 &VE::I64RegClass,
303 &VE::MISCRegClass,
304 &VE::F128RegClass,
305 &VE::VMRegClass,
306 &VE::VM512RegClass,
307 &VE::VM512_with_sub_vm_evenRegClass,
308 &VE::V64RegClass,
309 };
310} // namespace
311
312static const uint8_t CostPerUseTable[] = {
3130, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
314
315
316static const bool InAllocatableClassTable[] = {
317false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
318
319
320static const TargetRegisterInfoDesc VERegInfoDesc = { // Extra Descriptors
321.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
322
323unsigned VEGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
324 static const uint8_t RowMap[8] = {
325 0, 0, 0, 1, 0, 0, 0, 0,
326 };
327 static const uint8_t Rows[2][8] = {
328 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
329 { 0, VE::sub_odd_then_sub_f32, VE::sub_odd_then_sub_i32, 0, 0, 0, 0, 0, },
330 };
331
332 --IdxA; assert(IdxA < 8); (void) IdxA;
333 --IdxB; assert(IdxB < 8);
334 return Rows[RowMap[IdxA]][IdxB];
335}
336
337unsigned VEGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
338 static const uint8_t Table[8][8] = {
339 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
340 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
341 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
342 { 0, 0, 0, 0, 0, 0, VE::sub_f32, VE::sub_i32, },
343 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
344 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
345 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
346 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
347 };
348
349 --IdxA; assert(IdxA < 8);
350 --IdxB; assert(IdxB < 8);
351 return Table[IdxA][IdxB];
352 }
353
354 struct MaskRolOp {
355 LaneBitmask Mask;
356 uint8_t RotateLeft;
357 };
358 static const MaskRolOp LaneMaskComposeSequences[] = {
359 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
360 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
361 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
362 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
363 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
364 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 10
365 };
366 static const uint8_t CompositeSequences[] = {
367 0, // to sub_even
368 0, // to sub_f32
369 2, // to sub_i32
370 4, // to sub_odd
371 6, // to sub_vm_even
372 8, // to sub_vm_odd
373 4, // to sub_odd_then_sub_f32
374 10 // to sub_odd_then_sub_i32
375 };
376
377LaneBitmask VEGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
378 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
379 LaneBitmask Result;
380 for (const MaskRolOp *Ops =
381 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
382 Ops->Mask.any(); ++Ops) {
383 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
384 if (unsigned S = Ops->RotateLeft)
385 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
386 else
387 Result |= LaneBitmask(M);
388 }
389 return Result;
390}
391
392LaneBitmask VEGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
393 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
394 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
395 LaneBitmask Result;
396 for (const MaskRolOp *Ops =
397 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
398 Ops->Mask.any(); ++Ops) {
399 LaneBitmask::Type M = LaneMask.getAsInteger();
400 if (unsigned S = Ops->RotateLeft)
401 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
402 else
403 Result |= LaneBitmask(M);
404 }
405 return Result;
406}
407
408const TargetRegisterClass *VEGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
409 static constexpr uint8_t Table[10][8] = {
410 { // F32
411 0, // sub_even
412 0, // sub_f32
413 0, // sub_i32
414 0, // sub_odd
415 0, // sub_vm_even
416 0, // sub_vm_odd
417 0, // sub_odd_then_sub_f32
418 0, // sub_odd_then_sub_i32
419 },
420 { // I32
421 0, // sub_even
422 0, // sub_f32
423 0, // sub_i32
424 0, // sub_odd
425 0, // sub_vm_even
426 0, // sub_vm_odd
427 0, // sub_odd_then_sub_f32
428 0, // sub_odd_then_sub_i32
429 },
430 { // VLS
431 0, // sub_even
432 0, // sub_f32
433 0, // sub_i32
434 0, // sub_odd
435 0, // sub_vm_even
436 0, // sub_vm_odd
437 0, // sub_odd_then_sub_f32
438 0, // sub_odd_then_sub_i32
439 },
440 { // I64
441 0, // sub_even
442 4, // sub_f32 -> I64
443 4, // sub_i32 -> I64
444 0, // sub_odd
445 0, // sub_vm_even
446 0, // sub_vm_odd
447 0, // sub_odd_then_sub_f32
448 0, // sub_odd_then_sub_i32
449 },
450 { // MISC
451 0, // sub_even
452 0, // sub_f32
453 0, // sub_i32
454 0, // sub_odd
455 0, // sub_vm_even
456 0, // sub_vm_odd
457 0, // sub_odd_then_sub_f32
458 0, // sub_odd_then_sub_i32
459 },
460 { // F128
461 6, // sub_even -> F128
462 6, // sub_f32 -> F128
463 6, // sub_i32 -> F128
464 6, // sub_odd -> F128
465 0, // sub_vm_even
466 0, // sub_vm_odd
467 6, // sub_odd_then_sub_f32 -> F128
468 6, // sub_odd_then_sub_i32 -> F128
469 },
470 { // VM
471 0, // sub_even
472 0, // sub_f32
473 0, // sub_i32
474 0, // sub_odd
475 0, // sub_vm_even
476 0, // sub_vm_odd
477 0, // sub_odd_then_sub_f32
478 0, // sub_odd_then_sub_i32
479 },
480 { // VM512
481 0, // sub_even
482 0, // sub_f32
483 0, // sub_i32
484 0, // sub_odd
485 9, // sub_vm_even -> VM512_with_sub_vm_even
486 9, // sub_vm_odd -> VM512_with_sub_vm_even
487 0, // sub_odd_then_sub_f32
488 0, // sub_odd_then_sub_i32
489 },
490 { // VM512_with_sub_vm_even
491 0, // sub_even
492 0, // sub_f32
493 0, // sub_i32
494 0, // sub_odd
495 9, // sub_vm_even -> VM512_with_sub_vm_even
496 9, // sub_vm_odd -> VM512_with_sub_vm_even
497 0, // sub_odd_then_sub_f32
498 0, // sub_odd_then_sub_i32
499 },
500 { // V64
501 0, // sub_even
502 0, // sub_f32
503 0, // sub_i32
504 0, // sub_odd
505 0, // sub_vm_even
506 0, // sub_vm_odd
507 0, // sub_odd_then_sub_f32
508 0, // sub_odd_then_sub_i32
509 },
510
511 };
512 assert(RC && "Missing regclass");
513 if (!Idx) return RC;
514 --Idx;
515 assert(Idx < 8 && "Bad subreg");
516 unsigned TV = Table[RC->getID()][Idx];
517 return TV ? getRegClass(i: TV - 1) : nullptr;
518}const TargetRegisterClass *VEGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
519 static constexpr uint8_t Table[10][8] = {
520 { // F32
521 0, // F32:sub_even
522 0, // F32:sub_f32
523 0, // F32:sub_i32
524 0, // F32:sub_odd
525 0, // F32:sub_vm_even
526 0, // F32:sub_vm_odd
527 0, // F32:sub_odd_then_sub_f32
528 0, // F32:sub_odd_then_sub_i32
529 },
530 { // I32
531 0, // I32:sub_even
532 0, // I32:sub_f32
533 0, // I32:sub_i32
534 0, // I32:sub_odd
535 0, // I32:sub_vm_even
536 0, // I32:sub_vm_odd
537 0, // I32:sub_odd_then_sub_f32
538 0, // I32:sub_odd_then_sub_i32
539 },
540 { // VLS
541 0, // VLS:sub_even
542 0, // VLS:sub_f32
543 0, // VLS:sub_i32
544 0, // VLS:sub_odd
545 0, // VLS:sub_vm_even
546 0, // VLS:sub_vm_odd
547 0, // VLS:sub_odd_then_sub_f32
548 0, // VLS:sub_odd_then_sub_i32
549 },
550 { // I64
551 0, // I64:sub_even
552 1, // I64:sub_f32 -> F32
553 2, // I64:sub_i32 -> I32
554 0, // I64:sub_odd
555 0, // I64:sub_vm_even
556 0, // I64:sub_vm_odd
557 0, // I64:sub_odd_then_sub_f32
558 0, // I64:sub_odd_then_sub_i32
559 },
560 { // MISC
561 0, // MISC:sub_even
562 0, // MISC:sub_f32
563 0, // MISC:sub_i32
564 0, // MISC:sub_odd
565 0, // MISC:sub_vm_even
566 0, // MISC:sub_vm_odd
567 0, // MISC:sub_odd_then_sub_f32
568 0, // MISC:sub_odd_then_sub_i32
569 },
570 { // F128
571 4, // F128:sub_even -> I64
572 1, // F128:sub_f32 -> F32
573 2, // F128:sub_i32 -> I32
574 4, // F128:sub_odd -> I64
575 0, // F128:sub_vm_even
576 0, // F128:sub_vm_odd
577 1, // F128:sub_odd_then_sub_f32 -> F32
578 2, // F128:sub_odd_then_sub_i32 -> I32
579 },
580 { // VM
581 0, // VM:sub_even
582 0, // VM:sub_f32
583 0, // VM:sub_i32
584 0, // VM:sub_odd
585 0, // VM:sub_vm_even
586 0, // VM:sub_vm_odd
587 0, // VM:sub_odd_then_sub_f32
588 0, // VM:sub_odd_then_sub_i32
589 },
590 { // VM512
591 0, // VM512:sub_even
592 0, // VM512:sub_f32
593 0, // VM512:sub_i32
594 0, // VM512:sub_odd
595 7, // VM512:sub_vm_even -> VM
596 7, // VM512:sub_vm_odd -> VM
597 0, // VM512:sub_odd_then_sub_f32
598 0, // VM512:sub_odd_then_sub_i32
599 },
600 { // VM512_with_sub_vm_even
601 0, // VM512_with_sub_vm_even:sub_even
602 0, // VM512_with_sub_vm_even:sub_f32
603 0, // VM512_with_sub_vm_even:sub_i32
604 0, // VM512_with_sub_vm_even:sub_odd
605 7, // VM512_with_sub_vm_even:sub_vm_even -> VM
606 7, // VM512_with_sub_vm_even:sub_vm_odd -> VM
607 0, // VM512_with_sub_vm_even:sub_odd_then_sub_f32
608 0, // VM512_with_sub_vm_even:sub_odd_then_sub_i32
609 },
610 { // V64
611 0, // V64:sub_even
612 0, // V64:sub_f32
613 0, // V64:sub_i32
614 0, // V64:sub_odd
615 0, // V64:sub_vm_even
616 0, // V64:sub_vm_odd
617 0, // V64:sub_odd_then_sub_f32
618 0, // V64:sub_odd_then_sub_i32
619 },
620
621 };
622 assert(RC && "Missing regclass");
623 if (!Idx) return RC;
624 --Idx;
625 assert(Idx < 8 && "Bad subreg");
626 unsigned TV = Table[RC->getID()][Idx];
627 return TV ? getRegClass(i: TV - 1) : nullptr;
628}/// Get the weight in units of pressure for this register class.
629const RegClassWeight &VEGenRegisterInfo::
630getRegClassWeight(const TargetRegisterClass *RC) const {
631 static const RegClassWeight RCWeightTable[] = {
632 {.RegWeight: 2, .WeightLimit: 128}, // F32
633 {.RegWeight: 2, .WeightLimit: 128}, // I32
634 {.RegWeight: 1, .WeightLimit: 1}, // VLS
635 {.RegWeight: 3, .WeightLimit: 192}, // I64
636 {.RegWeight: 1, .WeightLimit: 23}, // MISC
637 {.RegWeight: 6, .WeightLimit: 192}, // F128
638 {.RegWeight: 1, .WeightLimit: 16}, // VM
639 {.RegWeight: 2, .WeightLimit: 16}, // VM512
640 {.RegWeight: 2, .WeightLimit: 14}, // VM512_with_sub_vm_even
641 {.RegWeight: 1, .WeightLimit: 65}, // V64
642 };
643 return RCWeightTable[RC->getID()];
644}
645
646/// Get the weight in units of pressure for this register unit.
647unsigned VEGenRegisterInfo::
648getRegUnitWeight(MCRegUnit RegUnit) const {
649 assert(static_cast<unsigned>(RegUnit) < 299 && "invalid register unit");
650 static const uint8_t RUWeightTable[] = {
651 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, };
652 return RUWeightTable[static_cast<unsigned>(RegUnit)];
653}
654
655
656// Get the number of dimensions of register pressure.
657unsigned VEGenRegisterInfo::getNumRegPressureSets() const {
658 return 9;
659}
660
661// Get the name of this register unit pressure set.
662const char *VEGenRegisterInfo::
663getRegPressureSetName(unsigned Idx) const {
664 static const char *PressureNameTable[] = {
665 "VLS",
666 "VM512",
667 "VM",
668 "VM_with_VM512",
669 "MISC",
670 "V64",
671 "F32",
672 "I32",
673 "I64",
674 };
675 return PressureNameTable[Idx];
676}
677
678// Get the register unit pressure limit for this dimension.
679// This limit must be adjusted dynamically for reserved registers.
680unsigned VEGenRegisterInfo::
681getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
682 static const uint8_t PressureLimitTable[] = {
683 1, // 0: VLS
684 16, // 1: VM512
685 16, // 2: VM
686 18, // 3: VM_with_VM512
687 23, // 4: MISC
688 65, // 5: V64
689 128, // 6: F32
690 128, // 7: I32
691 192, // 8: I64
692 };
693 return PressureLimitTable[Idx];
694}
695
696/// Table of pressure sets per register class or unit.
697static const int RCSetsTable[] = {
698 /* 0 */ 0, -1,
699 /* 2 */ 1, 3, -1,
700 /* 5 */ 1, 2, 3, -1,
701 /* 9 */ 4, -1,
702 /* 11 */ 5, -1,
703 /* 13 */ 6, 8, -1,
704 /* 16 */ 6, 7, 8, -1,
705};
706
707/// Get the dimensions of register pressure impacted by this register class.
708/// Returns a -1 terminated array of pressure set IDs
709const int *VEGenRegisterInfo::
710getRegClassPressureSets(const TargetRegisterClass *RC) const {
711 static const uint8_t RCSetStartTable[] = {
712 13,17,0,14,9,14,6,2,5,11,};
713 return &RCSetsTable[RCSetStartTable[RC->getID()]];
714}
715
716/// Get the dimensions of register pressure impacted by this register unit.
717/// Returns a -1 terminated array of pressure set IDs
718const int *VEGenRegisterInfo::
719getRegUnitPressureSets(MCRegUnit RegUnit) const {
720 assert(static_cast<unsigned>(RegUnit) < 299 && "invalid register unit");
721 static const uint8_t RUSetStartTable[] = {
722 1,9,9,9,9,11,0,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,6,6,5,5,5,5,5,5,5,5,5,5,5,5,5,5,2,};
723 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
724}
725
726extern const MCRegisterDesc VERegDesc[];
727extern const int16_t VERegDiffLists[];
728extern const LaneBitmask VELaneMaskLists[];
729extern const char VERegStrings[];
730extern const char VERegClassStrings[];
731extern const MCPhysReg VERegUnitRoots[][2];
732extern const uint16_t VESubRegIdxLists[];
733extern const uint16_t VERegEncodingTable[];
734// VE Dwarf<->LLVM register mappings.
735extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0Dwarf2L[];
736extern const unsigned VEDwarfFlavour0Dwarf2LSize;
737
738extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0Dwarf2L[];
739extern const unsigned VEEHFlavour0Dwarf2LSize;
740
741extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0L2Dwarf[];
742extern const unsigned VEDwarfFlavour0L2DwarfSize;
743
744extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0L2Dwarf[];
745extern const unsigned VEEHFlavour0L2DwarfSize;
746
747
748VEGenRegisterInfo::
749VEGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
750 unsigned PC, unsigned HwMode)
751 : TargetRegisterInfo(&VERegInfoDesc, RegisterClasses, RegisterClasses+10,
752 VESubRegIndexStrings, VESubRegIndexNameOffsets,
753 SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
754
755 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
756 InitMCRegisterInfo(D: VERegDesc, NR: 339, RA, PC,
757 C: VEMCRegisterClasses, NC: 10,
758 RURoots: VERegUnitRoots,
759 NRU: 299,
760 DL: VERegDiffLists,
761 RUMS: VELaneMaskLists,
762 Strings: VERegStrings,
763 ClassStrings: VERegClassStrings,
764 SubIndices: VESubRegIdxLists,
765 NumIndices: 9,
766 RET: VERegEncodingTable,
767 RUI: nullptr);
768
769 switch (DwarfFlavour) {
770 default:
771 llvm_unreachable("Unknown DWARF flavour");
772 case 0:
773 mapDwarfRegsToLLVMRegs(Map: VEDwarfFlavour0Dwarf2L, Size: VEDwarfFlavour0Dwarf2LSize, isEH: false);
774 break;
775 }
776 switch (EHFlavour) {
777 default:
778 llvm_unreachable("Unknown DWARF flavour");
779 case 0:
780 mapDwarfRegsToLLVMRegs(Map: VEEHFlavour0Dwarf2L, Size: VEEHFlavour0Dwarf2LSize, isEH: true);
781 break;
782 }
783 switch (DwarfFlavour) {
784 default:
785 llvm_unreachable("Unknown DWARF flavour");
786 case 0:
787 mapLLVMRegsToDwarfRegs(Map: VEDwarfFlavour0L2Dwarf, Size: VEDwarfFlavour0L2DwarfSize, isEH: false);
788 break;
789 }
790 switch (EHFlavour) {
791 default:
792 llvm_unreachable("Unknown DWARF flavour");
793 case 0:
794 mapLLVMRegsToDwarfRegs(Map: VEEHFlavour0L2Dwarf, Size: VEEHFlavour0L2DwarfSize, isEH: true);
795 break;
796 }
797}
798
799static const MCPhysReg CSR_SaveList[] = { VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, 0 };
800static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000ff0, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
801static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
802static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
803static const MCPhysReg CSR_preserve_all_SaveList[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, VE::VM12, VE::VM13, VE::VM14, VE::VM15, 0 };
804static const uint32_t CSR_preserve_all_RegMask[] = { 0xf8000000, 0xfbffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xffffffff, 0x0007ffff, };
805
806
807ArrayRef<const uint32_t *> VEGenRegisterInfo::getRegMasks() const {
808 static const uint32_t *const Masks[] = {
809 CSR_RegMask,
810 CSR_NoRegs_RegMask,
811 CSR_preserve_all_RegMask,
812 };
813 return ArrayRef(Masks);
814}
815
816bool VEGenRegisterInfo::
817isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
818 return
819 false;
820}
821
822bool VEGenRegisterInfo::
823isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
824 return
825 false;
826}
827
828bool VEGenRegisterInfo::
829isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
830 return
831 false;
832}
833
834bool VEGenRegisterInfo::
835isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
836 return
837 false;
838}
839
840bool VEGenRegisterInfo::
841isConstantPhysReg(MCRegister PhysReg) const {
842 return
843 PhysReg == VE::VM0 ||
844 PhysReg == VE::VMP0 ||
845 false;
846}
847
848ArrayRef<const char *> VEGenRegisterInfo::getRegMaskNames() const {
849 static const char *Names[] = {
850 "CSR",
851 "CSR_NoRegs",
852 "CSR_preserve_all",
853 };
854 return ArrayRef(Names);
855}
856
857const VEFrameLowering *
858VEGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
859 return static_cast<const VEFrameLowering *>(
860 MF.getSubtarget().getFrameLowering());
861}
862
863
864} // namespace llvm
865