1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass VEMCRegisterClasses[];
12
13static const MVT::SimpleValueType VEVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f32, MVT::Other,
17 /* 6 */ MVT::i64, MVT::f64, MVT::Other,
18 /* 9 */ MVT::f128, MVT::Other,
19 /* 11 */ MVT::v256i1, MVT::Other,
20 /* 13 */ MVT::v512i1, MVT::Other,
21 /* 15 */ MVT::v256f64, MVT::v512i32, MVT::v512f32, MVT::v256i64, MVT::v256i32, MVT::v256f32, MVT::Other,
22};
23
24#ifdef __GNUC__
25#pragma GCC diagnostic push
26#pragma GCC diagnostic ignored "-Woverlength-strings"
27#endif
28static constexpr char VESubRegIndexStrings[] = {
29 /* 0 */ "sub_odd_then_sub_f32\000"
30 /* 21 */ "sub_odd_then_sub_i32\000"
31 /* 42 */ "sub_odd\000"
32 /* 50 */ "sub_vm_odd\000"
33 /* 61 */ "sub_even\000"
34 /* 70 */ "sub_vm_even\000"
35};
36#ifdef __GNUC__
37#pragma GCC diagnostic pop
38#endif
39
40
41static constexpr uint32_t VESubRegIndexNameOffsets[] = {
42 61,
43 13,
44 34,
45 42,
46 70,
47 50,
48 0,
49 21,
50};
51
52static const TargetRegisterInfo::SubRegCoveredBits VESubRegIdxRangeTable[] = {
53 { .Offset: 65535, .Size: 65535 },
54 { .Offset: 0, .Size: 64 }, // sub_even
55 { .Offset: 0, .Size: 32 }, // sub_f32
56 { .Offset: 32, .Size: 32 }, // sub_i32
57 { .Offset: 64, .Size: 64 }, // sub_odd
58 { .Offset: 0, .Size: 256 }, // sub_vm_even
59 { .Offset: 256, .Size: 256 }, // sub_vm_odd
60 { .Offset: 64, .Size: 32 }, // sub_odd_then_sub_f32
61 { .Offset: 96, .Size: 32 }, // sub_odd_then_sub_i32
62};
63
64
65static const LaneBitmask VESubRegIndexLaneMaskTable[] = {
66 LaneBitmask::getAll(),
67 LaneBitmask(0x0000000000000003), // sub_even
68 LaneBitmask(0x0000000000000001), // sub_f32
69 LaneBitmask(0x0000000000000002), // sub_i32
70 LaneBitmask(0x0000000000000030), // sub_odd
71 LaneBitmask(0x0000000000000004), // sub_vm_even
72 LaneBitmask(0x0000000000000008), // sub_vm_odd
73 LaneBitmask(0x0000000000000010), // sub_odd_then_sub_f32
74 LaneBitmask(0x0000000000000020), // sub_odd_then_sub_i32
75 };
76
77
78
79static const TargetRegisterInfo::RegClassInfo VERegClassInfos[] = {
80 // Mode = 0 (DefaultMode)
81 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VEVTLists+*/.VTListOffset: 4 }, // F32
82 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VEVTLists+*/.VTListOffset: 0 }, // I32
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 0 }, // VLS
84 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 6 }, // I64
85 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 2 }, // MISC
86 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VEVTLists+*/.VTListOffset: 9 }, // F128
87 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 11 }, // VM
88 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 13 }, // VM512
89 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 13 }, // VM512_with_sub_vm_even
90 { .RegSize: 16384, .SpillSize: 16384, .SpillAlignment: 64, /*VEVTLists+*/.VTListOffset: 15 }, // V64
91};
92static const uint32_t F32SubClassMask[] = {
93 0x00000001,
94 0x00000028, // sub_f32
95 0x00000020, // sub_odd_then_sub_f32
96};
97
98static const uint32_t I32SubClassMask[] = {
99 0x00000002,
100 0x00000028, // sub_i32
101 0x00000020, // sub_odd_then_sub_i32
102};
103
104static const uint32_t VLSSubClassMask[] = {
105 0x00000004,
106};
107
108static const uint32_t I64SubClassMask[] = {
109 0x00000008,
110 0x00000020, // sub_even
111 0x00000020, // sub_odd
112};
113
114static const uint32_t MISCSubClassMask[] = {
115 0x00000010,
116};
117
118static const uint32_t F128SubClassMask[] = {
119 0x00000020,
120};
121
122static const uint32_t VMSubClassMask[] = {
123 0x00000040,
124 0x00000100, // sub_vm_even
125 0x00000100, // sub_vm_odd
126};
127
128static const uint32_t VM512SubClassMask[] = {
129 0x00000180,
130};
131
132static const uint32_t VM512_with_sub_vm_evenSubClassMask[] = {
133 0x00000100,
134};
135
136static const uint32_t V64SubClassMask[] = {
137 0x00000200,
138};
139
140static const uint16_t SuperRegIdxSeqs[] = {
141 /* 0 */ 1, 4, 0,
142 /* 3 */ 5, 6, 0,
143 /* 6 */ 2, 7, 0,
144 /* 9 */ 3, 8, 0,
145};
146
147static unsigned const VM512_with_sub_vm_evenSuperclasses[] = {
148 VE::VM512RegClassID,
149};
150
151namespace VE {
152
153// Register class instances.
154 extern const TargetRegisterClass F32RegClass = {
155 .MC: &VEMCRegisterClasses[F32RegClassID],
156 .SubClassMask: F32SubClassMask,
157 .SuperRegIndices: SuperRegIdxSeqs + 6,
158 .LaneMask: LaneBitmask(0x0000000000000001),
159 .AllocationPriority: 0,
160 .GlobalPriority: false,
161 .TSFlags: 0x00, /* TSFlags */
162 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
163 .CoveredBySubRegs: false, /* CoveredBySubRegs */
164 .SuperClasses: nullptr, .SuperClassesSize: 0,
165 .OrderFunc: nullptr
166 };
167
168 extern const TargetRegisterClass I32RegClass = {
169 .MC: &VEMCRegisterClasses[I32RegClassID],
170 .SubClassMask: I32SubClassMask,
171 .SuperRegIndices: SuperRegIdxSeqs + 9,
172 .LaneMask: LaneBitmask(0x0000000000000001),
173 .AllocationPriority: 0,
174 .GlobalPriority: false,
175 .TSFlags: 0x00, /* TSFlags */
176 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
177 .CoveredBySubRegs: false, /* CoveredBySubRegs */
178 .SuperClasses: nullptr, .SuperClassesSize: 0,
179 .OrderFunc: nullptr
180 };
181
182 extern const TargetRegisterClass VLSRegClass = {
183 .MC: &VEMCRegisterClasses[VLSRegClassID],
184 .SubClassMask: VLSSubClassMask,
185 .SuperRegIndices: SuperRegIdxSeqs + 2,
186 .LaneMask: LaneBitmask(0x0000000000000001),
187 .AllocationPriority: 0,
188 .GlobalPriority: false,
189 .TSFlags: 0x00, /* TSFlags */
190 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
191 .CoveredBySubRegs: false, /* CoveredBySubRegs */
192 .SuperClasses: nullptr, .SuperClassesSize: 0,
193 .OrderFunc: nullptr
194 };
195
196 extern const TargetRegisterClass I64RegClass = {
197 .MC: &VEMCRegisterClasses[I64RegClassID],
198 .SubClassMask: I64SubClassMask,
199 .SuperRegIndices: SuperRegIdxSeqs + 0,
200 .LaneMask: LaneBitmask(0x0000000000000003),
201 .AllocationPriority: 0,
202 .GlobalPriority: false,
203 .TSFlags: 0x00, /* TSFlags */
204 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
205 .CoveredBySubRegs: true, /* CoveredBySubRegs */
206 .SuperClasses: nullptr, .SuperClassesSize: 0,
207 .OrderFunc: nullptr
208 };
209
210 extern const TargetRegisterClass MISCRegClass = {
211 .MC: &VEMCRegisterClasses[MISCRegClassID],
212 .SubClassMask: MISCSubClassMask,
213 .SuperRegIndices: SuperRegIdxSeqs + 2,
214 .LaneMask: LaneBitmask(0x0000000000000001),
215 .AllocationPriority: 0,
216 .GlobalPriority: false,
217 .TSFlags: 0x00, /* TSFlags */
218 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
219 .CoveredBySubRegs: false, /* CoveredBySubRegs */
220 .SuperClasses: nullptr, .SuperClassesSize: 0,
221 .OrderFunc: nullptr
222 };
223
224 extern const TargetRegisterClass F128RegClass = {
225 .MC: &VEMCRegisterClasses[F128RegClassID],
226 .SubClassMask: F128SubClassMask,
227 .SuperRegIndices: SuperRegIdxSeqs + 2,
228 .LaneMask: LaneBitmask(0x0000000000000033),
229 .AllocationPriority: 0,
230 .GlobalPriority: false,
231 .TSFlags: 0x00, /* TSFlags */
232 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
233 .CoveredBySubRegs: true, /* CoveredBySubRegs */
234 .SuperClasses: nullptr, .SuperClassesSize: 0,
235 .OrderFunc: nullptr
236 };
237
238 extern const TargetRegisterClass VMRegClass = {
239 .MC: &VEMCRegisterClasses[VMRegClassID],
240 .SubClassMask: VMSubClassMask,
241 .SuperRegIndices: SuperRegIdxSeqs + 3,
242 .LaneMask: LaneBitmask(0x0000000000000001),
243 .AllocationPriority: 0,
244 .GlobalPriority: false,
245 .TSFlags: 0x00, /* TSFlags */
246 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
247 .CoveredBySubRegs: false, /* CoveredBySubRegs */
248 .SuperClasses: nullptr, .SuperClassesSize: 0,
249 .OrderFunc: nullptr
250 };
251
252 extern const TargetRegisterClass VM512RegClass = {
253 .MC: &VEMCRegisterClasses[VM512RegClassID],
254 .SubClassMask: VM512SubClassMask,
255 .SuperRegIndices: SuperRegIdxSeqs + 2,
256 .LaneMask: LaneBitmask(0x000000000000000C),
257 .AllocationPriority: 0,
258 .GlobalPriority: false,
259 .TSFlags: 0x00, /* TSFlags */
260 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
261 .CoveredBySubRegs: false, /* CoveredBySubRegs */
262 .SuperClasses: nullptr, .SuperClassesSize: 0,
263 .OrderFunc: nullptr
264 };
265
266 extern const TargetRegisterClass VM512_with_sub_vm_evenRegClass = {
267 .MC: &VEMCRegisterClasses[VM512_with_sub_vm_evenRegClassID],
268 .SubClassMask: VM512_with_sub_vm_evenSubClassMask,
269 .SuperRegIndices: SuperRegIdxSeqs + 2,
270 .LaneMask: LaneBitmask(0x000000000000000C),
271 .AllocationPriority: 0,
272 .GlobalPriority: false,
273 .TSFlags: 0x00, /* TSFlags */
274 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
275 .CoveredBySubRegs: true, /* CoveredBySubRegs */
276 .SuperClasses: VM512_with_sub_vm_evenSuperclasses, .SuperClassesSize: 1,
277 .OrderFunc: nullptr
278 };
279
280 extern const TargetRegisterClass V64RegClass = {
281 .MC: &VEMCRegisterClasses[V64RegClassID],
282 .SubClassMask: V64SubClassMask,
283 .SuperRegIndices: SuperRegIdxSeqs + 2,
284 .LaneMask: LaneBitmask(0x0000000000000001),
285 .AllocationPriority: 0,
286 .GlobalPriority: false,
287 .TSFlags: 0x00, /* TSFlags */
288 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
289 .CoveredBySubRegs: false, /* CoveredBySubRegs */
290 .SuperClasses: nullptr, .SuperClassesSize: 0,
291 .OrderFunc: nullptr
292 };
293
294
295} // namespace VE
296static const TargetRegisterClass *const VERegisterClasses[] = {
297 &VE::F32RegClass,
298 &VE::I32RegClass,
299 &VE::VLSRegClass,
300 &VE::I64RegClass,
301 &VE::MISCRegClass,
302 &VE::F128RegClass,
303 &VE::VMRegClass,
304 &VE::VM512RegClass,
305 &VE::VM512_with_sub_vm_evenRegClass,
306 &VE::V64RegClass,
307 };
308
309static const uint8_t VECostPerUseTable[] = {
3100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
311
312
313static const bool VEInAllocatableClassTable[] = {
314false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
315
316
317static const TargetRegisterInfoDesc VERegInfoDesc = { // Extra Descriptors
318.CostPerUse: VECostPerUseTable, .NumCosts: 1, .InAllocatableClass: VEInAllocatableClassTable};
319
320unsigned VEGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
321 static const uint8_t RowMap[8] = {
322 0, 0, 0, 1, 0, 0, 0, 0,
323 };
324 static const uint8_t Rows[2][8] = {
325 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
326 { 0, VE::sub_odd_then_sub_f32, VE::sub_odd_then_sub_i32, 0, 0, 0, 0, 0, },
327 };
328
329 --IdxA; assert(IdxA < 8); (void) IdxA;
330 --IdxB; assert(IdxB < 8);
331 return Rows[RowMap[IdxA]][IdxB];
332}
333
334unsigned VEGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
335 static const uint8_t Table[8][8] = {
336 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
337 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
338 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
339 { 0, 0, 0, 0, 0, 0, VE::sub_f32, VE::sub_i32, },
340 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
341 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
342 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
343 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
344 };
345
346 --IdxA; assert(IdxA < 8);
347 --IdxB; assert(IdxB < 8);
348 return Table[IdxA][IdxB];
349 }
350
351 struct MaskRolOp {
352 LaneBitmask Mask;
353 uint8_t RotateLeft;
354 };
355 static const MaskRolOp LaneMaskComposeSequences[] = {
356 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
357 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
358 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
359 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
360 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
361 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 10
362 };
363 static const uint8_t CompositeSequences[] = {
364 0, // to sub_even
365 0, // to sub_f32
366 2, // to sub_i32
367 4, // to sub_odd
368 6, // to sub_vm_even
369 8, // to sub_vm_odd
370 4, // to sub_odd_then_sub_f32
371 10 // to sub_odd_then_sub_i32
372 };
373
374LaneBitmask VEGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
375 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
376 LaneBitmask Result;
377 for (const MaskRolOp *Ops =
378 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
379 Ops->Mask.any(); ++Ops) {
380 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
381 if (unsigned S = Ops->RotateLeft)
382 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
383 else
384 Result |= LaneBitmask(M);
385 }
386 return Result;
387}
388
389LaneBitmask VEGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
390 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
391 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
392 LaneBitmask Result;
393 for (const MaskRolOp *Ops =
394 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
395 Ops->Mask.any(); ++Ops) {
396 LaneBitmask::Type M = LaneMask.getAsInteger();
397 if (unsigned S = Ops->RotateLeft)
398 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
399 else
400 Result |= LaneBitmask(M);
401 }
402 return Result;
403}
404
405const TargetRegisterClass *VEGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
406 static constexpr uint8_t Table[10][8] = {
407 { // F32
408 0, // sub_even
409 0, // sub_f32
410 0, // sub_i32
411 0, // sub_odd
412 0, // sub_vm_even
413 0, // sub_vm_odd
414 0, // sub_odd_then_sub_f32
415 0, // sub_odd_then_sub_i32
416 },
417 { // I32
418 0, // sub_even
419 0, // sub_f32
420 0, // sub_i32
421 0, // sub_odd
422 0, // sub_vm_even
423 0, // sub_vm_odd
424 0, // sub_odd_then_sub_f32
425 0, // sub_odd_then_sub_i32
426 },
427 { // VLS
428 0, // sub_even
429 0, // sub_f32
430 0, // sub_i32
431 0, // sub_odd
432 0, // sub_vm_even
433 0, // sub_vm_odd
434 0, // sub_odd_then_sub_f32
435 0, // sub_odd_then_sub_i32
436 },
437 { // I64
438 0, // sub_even
439 4, // sub_f32 -> I64
440 4, // sub_i32 -> I64
441 0, // sub_odd
442 0, // sub_vm_even
443 0, // sub_vm_odd
444 0, // sub_odd_then_sub_f32
445 0, // sub_odd_then_sub_i32
446 },
447 { // MISC
448 0, // sub_even
449 0, // sub_f32
450 0, // sub_i32
451 0, // sub_odd
452 0, // sub_vm_even
453 0, // sub_vm_odd
454 0, // sub_odd_then_sub_f32
455 0, // sub_odd_then_sub_i32
456 },
457 { // F128
458 6, // sub_even -> F128
459 6, // sub_f32 -> F128
460 6, // sub_i32 -> F128
461 6, // sub_odd -> F128
462 0, // sub_vm_even
463 0, // sub_vm_odd
464 6, // sub_odd_then_sub_f32 -> F128
465 6, // sub_odd_then_sub_i32 -> F128
466 },
467 { // VM
468 0, // sub_even
469 0, // sub_f32
470 0, // sub_i32
471 0, // sub_odd
472 0, // sub_vm_even
473 0, // sub_vm_odd
474 0, // sub_odd_then_sub_f32
475 0, // sub_odd_then_sub_i32
476 },
477 { // VM512
478 0, // sub_even
479 0, // sub_f32
480 0, // sub_i32
481 0, // sub_odd
482 9, // sub_vm_even -> VM512_with_sub_vm_even
483 9, // sub_vm_odd -> VM512_with_sub_vm_even
484 0, // sub_odd_then_sub_f32
485 0, // sub_odd_then_sub_i32
486 },
487 { // VM512_with_sub_vm_even
488 0, // sub_even
489 0, // sub_f32
490 0, // sub_i32
491 0, // sub_odd
492 9, // sub_vm_even -> VM512_with_sub_vm_even
493 9, // sub_vm_odd -> VM512_with_sub_vm_even
494 0, // sub_odd_then_sub_f32
495 0, // sub_odd_then_sub_i32
496 },
497 { // V64
498 0, // sub_even
499 0, // sub_f32
500 0, // sub_i32
501 0, // sub_odd
502 0, // sub_vm_even
503 0, // sub_vm_odd
504 0, // sub_odd_then_sub_f32
505 0, // sub_odd_then_sub_i32
506 },
507
508 };
509 assert(RC && "Missing regclass");
510 if (!Idx) return RC;
511 --Idx;
512 assert(Idx < 8 && "Bad subreg");
513 unsigned TV = Table[RC->getID()][Idx];
514 return TV ? getRegClass(i: TV - 1) : nullptr;
515}const TargetRegisterClass *VEGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
516 static constexpr uint8_t Table[10][8] = {
517 { // F32
518 0, // F32:sub_even
519 0, // F32:sub_f32
520 0, // F32:sub_i32
521 0, // F32:sub_odd
522 0, // F32:sub_vm_even
523 0, // F32:sub_vm_odd
524 0, // F32:sub_odd_then_sub_f32
525 0, // F32:sub_odd_then_sub_i32
526 },
527 { // I32
528 0, // I32:sub_even
529 0, // I32:sub_f32
530 0, // I32:sub_i32
531 0, // I32:sub_odd
532 0, // I32:sub_vm_even
533 0, // I32:sub_vm_odd
534 0, // I32:sub_odd_then_sub_f32
535 0, // I32:sub_odd_then_sub_i32
536 },
537 { // VLS
538 0, // VLS:sub_even
539 0, // VLS:sub_f32
540 0, // VLS:sub_i32
541 0, // VLS:sub_odd
542 0, // VLS:sub_vm_even
543 0, // VLS:sub_vm_odd
544 0, // VLS:sub_odd_then_sub_f32
545 0, // VLS:sub_odd_then_sub_i32
546 },
547 { // I64
548 0, // I64:sub_even
549 1, // I64:sub_f32 -> F32
550 2, // I64:sub_i32 -> I32
551 0, // I64:sub_odd
552 0, // I64:sub_vm_even
553 0, // I64:sub_vm_odd
554 0, // I64:sub_odd_then_sub_f32
555 0, // I64:sub_odd_then_sub_i32
556 },
557 { // MISC
558 0, // MISC:sub_even
559 0, // MISC:sub_f32
560 0, // MISC:sub_i32
561 0, // MISC:sub_odd
562 0, // MISC:sub_vm_even
563 0, // MISC:sub_vm_odd
564 0, // MISC:sub_odd_then_sub_f32
565 0, // MISC:sub_odd_then_sub_i32
566 },
567 { // F128
568 4, // F128:sub_even -> I64
569 1, // F128:sub_f32 -> F32
570 2, // F128:sub_i32 -> I32
571 4, // F128:sub_odd -> I64
572 0, // F128:sub_vm_even
573 0, // F128:sub_vm_odd
574 1, // F128:sub_odd_then_sub_f32 -> F32
575 2, // F128:sub_odd_then_sub_i32 -> I32
576 },
577 { // VM
578 0, // VM:sub_even
579 0, // VM:sub_f32
580 0, // VM:sub_i32
581 0, // VM:sub_odd
582 0, // VM:sub_vm_even
583 0, // VM:sub_vm_odd
584 0, // VM:sub_odd_then_sub_f32
585 0, // VM:sub_odd_then_sub_i32
586 },
587 { // VM512
588 0, // VM512:sub_even
589 0, // VM512:sub_f32
590 0, // VM512:sub_i32
591 0, // VM512:sub_odd
592 7, // VM512:sub_vm_even -> VM
593 7, // VM512:sub_vm_odd -> VM
594 0, // VM512:sub_odd_then_sub_f32
595 0, // VM512:sub_odd_then_sub_i32
596 },
597 { // VM512_with_sub_vm_even
598 0, // VM512_with_sub_vm_even:sub_even
599 0, // VM512_with_sub_vm_even:sub_f32
600 0, // VM512_with_sub_vm_even:sub_i32
601 0, // VM512_with_sub_vm_even:sub_odd
602 7, // VM512_with_sub_vm_even:sub_vm_even -> VM
603 7, // VM512_with_sub_vm_even:sub_vm_odd -> VM
604 0, // VM512_with_sub_vm_even:sub_odd_then_sub_f32
605 0, // VM512_with_sub_vm_even:sub_odd_then_sub_i32
606 },
607 { // V64
608 0, // V64:sub_even
609 0, // V64:sub_f32
610 0, // V64:sub_i32
611 0, // V64:sub_odd
612 0, // V64:sub_vm_even
613 0, // V64:sub_vm_odd
614 0, // V64:sub_odd_then_sub_f32
615 0, // V64:sub_odd_then_sub_i32
616 },
617
618 };
619 assert(RC && "Missing regclass");
620 if (!Idx) return RC;
621 --Idx;
622 assert(Idx < 8 && "Bad subreg");
623 unsigned TV = Table[RC->getID()][Idx];
624 return TV ? getRegClass(i: TV - 1) : nullptr;
625}/// Get the weight in units of pressure for this register class.
626const RegClassWeight &VEGenRegisterInfo::
627getRegClassWeight(const TargetRegisterClass *RC) const {
628 static const RegClassWeight RCWeightTable[] = {
629 {.RegWeight: 2, .WeightLimit: 128}, // F32
630 {.RegWeight: 2, .WeightLimit: 128}, // I32
631 {.RegWeight: 1, .WeightLimit: 1}, // VLS
632 {.RegWeight: 3, .WeightLimit: 192}, // I64
633 {.RegWeight: 1, .WeightLimit: 23}, // MISC
634 {.RegWeight: 6, .WeightLimit: 192}, // F128
635 {.RegWeight: 1, .WeightLimit: 16}, // VM
636 {.RegWeight: 2, .WeightLimit: 16}, // VM512
637 {.RegWeight: 2, .WeightLimit: 14}, // VM512_with_sub_vm_even
638 {.RegWeight: 1, .WeightLimit: 65}, // V64
639 };
640 return RCWeightTable[RC->getID()];
641}
642
643/// Get the weight in units of pressure for this register unit.
644unsigned VEGenRegisterInfo::
645getRegUnitWeight(MCRegUnit RegUnit) const {
646 assert(static_cast<unsigned>(RegUnit) < 299 && "invalid register unit");
647 static const uint8_t RUWeightTable[] = {
648 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, };
649 return RUWeightTable[static_cast<unsigned>(RegUnit)];
650}
651
652
653// Get the number of dimensions of register pressure.
654unsigned VEGenRegisterInfo::getNumRegPressureSets() const {
655 return 9;
656}
657
658// Get the name of this register unit pressure set.
659const char *VEGenRegisterInfo::
660getRegPressureSetName(unsigned Idx) const {
661 static const char *PressureNameTable[] = {
662 "VLS",
663 "VM512",
664 "VM",
665 "VM_with_VM512",
666 "MISC",
667 "V64",
668 "F32",
669 "I32",
670 "I64",
671 };
672 return PressureNameTable[Idx];
673}
674
675// Get the register unit pressure limit for this dimension.
676// This limit must be adjusted dynamically for reserved registers.
677unsigned VEGenRegisterInfo::
678getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
679 static const uint8_t PressureLimitTable[] = {
680 1, // 0: VLS
681 16, // 1: VM512
682 16, // 2: VM
683 18, // 3: VM_with_VM512
684 23, // 4: MISC
685 65, // 5: V64
686 128, // 6: F32
687 128, // 7: I32
688 192, // 8: I64
689 };
690 return PressureLimitTable[Idx];
691}
692
693/// Table of pressure sets per register class or unit.
694static const int RCSetsTable[] = {
695 /* 0 */ 0, -1,
696 /* 2 */ 1, 3, -1,
697 /* 5 */ 1, 2, 3, -1,
698 /* 9 */ 4, -1,
699 /* 11 */ 5, -1,
700 /* 13 */ 6, 8, -1,
701 /* 16 */ 6, 7, 8, -1,
702};
703
704/// Get the dimensions of register pressure impacted by this register class.
705/// Returns a -1 terminated array of pressure set IDs
706const int *VEGenRegisterInfo::
707getRegClassPressureSets(const TargetRegisterClass *RC) const {
708 static const uint8_t RCSetStartTable[] = {
709 13,17,0,14,9,14,6,2,5,11,};
710 return &RCSetsTable[RCSetStartTable[RC->getID()]];
711}
712
713/// Get the dimensions of register pressure impacted by this register unit.
714/// Returns a -1 terminated array of pressure set IDs
715const int *VEGenRegisterInfo::
716getRegUnitPressureSets(MCRegUnit RegUnit) const {
717 assert(static_cast<unsigned>(RegUnit) < 299 && "invalid register unit");
718 static const uint8_t RUSetStartTable[] = {
719 1,9,9,9,9,11,0,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,6,6,5,5,5,5,5,5,5,5,5,5,5,5,5,5,2,};
720 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
721}
722
723extern const MCRegisterDesc VERegDesc[];
724extern const int16_t VERegDiffLists[];
725extern const LaneBitmask VELaneMaskLists[];
726extern const char VERegStrings[];
727extern const char VERegClassStrings[];
728extern const MCPhysReg VERegUnitRoots[][2];
729extern const uint16_t VESubRegIdxLists[];
730extern const uint16_t VERegEncodingTable[];
731// VE Dwarf<->LLVM register mappings.
732extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0Dwarf2L[];
733extern const unsigned VEDwarfFlavour0Dwarf2LSize;
734
735extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0Dwarf2L[];
736extern const unsigned VEEHFlavour0Dwarf2LSize;
737
738extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0L2Dwarf[];
739extern const unsigned VEDwarfFlavour0L2DwarfSize;
740
741extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0L2Dwarf[];
742extern const unsigned VEEHFlavour0L2DwarfSize;
743
744
745VEGenRegisterInfo::
746VEGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
747 unsigned PC, unsigned HwMode)
748 : TargetRegisterInfo(&VERegInfoDesc, VERegisterClasses,
749 VESubRegIndexStrings, VESubRegIndexNameOffsets,
750 VESubRegIdxRangeTable, VESubRegIndexLaneMaskTable,
751
752 LaneBitmask(0xFFFFFFFFFFFFFFFF), VERegClassInfos, VEVTLists, HwMode) {
753 InitMCRegisterInfo(D: VERegDesc, NR: 339, RA, PC,
754 C: VEMCRegisterClasses, NC: 10, RURoots: VERegUnitRoots, NRU: 299, DL: VERegDiffLists,
755 RUMS: VELaneMaskLists, Strings: VERegStrings, ClassStrings: VERegClassStrings, SubIndices: VESubRegIdxLists, NumIndices: 9,
756 RET: VERegEncodingTable, RUI: nullptr);
757
758 switch (DwarfFlavour) {
759 default:
760 llvm_unreachable("Unknown DWARF flavour");
761 case 0:
762 mapDwarfRegsToLLVMRegs(Map: VEDwarfFlavour0Dwarf2L, Size: VEDwarfFlavour0Dwarf2LSize, isEH: false);
763 break;
764 }
765 switch (EHFlavour) {
766 default:
767 llvm_unreachable("Unknown DWARF flavour");
768 case 0:
769 mapDwarfRegsToLLVMRegs(Map: VEEHFlavour0Dwarf2L, Size: VEEHFlavour0Dwarf2LSize, isEH: true);
770 break;
771 }
772 switch (DwarfFlavour) {
773 default:
774 llvm_unreachable("Unknown DWARF flavour");
775 case 0:
776 mapLLVMRegsToDwarfRegs(Map: VEDwarfFlavour0L2Dwarf, Size: VEDwarfFlavour0L2DwarfSize, isEH: false);
777 break;
778 }
779 switch (EHFlavour) {
780 default:
781 llvm_unreachable("Unknown DWARF flavour");
782 case 0:
783 mapLLVMRegsToDwarfRegs(Map: VEEHFlavour0L2Dwarf, Size: VEEHFlavour0L2DwarfSize, isEH: true);
784 break;
785 }
786}
787
788static const MCPhysReg CSR_SaveList[] = { VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, 0 };
789static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000ff0, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
790static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
791static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
792static const MCPhysReg CSR_preserve_all_SaveList[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, VE::VM12, VE::VM13, VE::VM14, VE::VM15, 0 };
793static const uint32_t CSR_preserve_all_RegMask[] = { 0xf8000000, 0xfbffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xffffffff, 0x0007ffff, };
794
795
796ArrayRef<const uint32_t *> VEGenRegisterInfo::getRegMasks() const {
797 static const uint32_t *const Masks[] = {
798 CSR_RegMask,
799 CSR_NoRegs_RegMask,
800 CSR_preserve_all_RegMask,
801 };
802 return ArrayRef(Masks);
803}
804
805bool VEGenRegisterInfo::
806isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
807 return
808 false;
809}
810
811bool VEGenRegisterInfo::
812isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
813 return
814 false;
815}
816
817bool VEGenRegisterInfo::
818isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
819 return
820 false;
821}
822
823bool VEGenRegisterInfo::
824isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
825 return
826 false;
827}
828
829bool VEGenRegisterInfo::
830isConstantPhysReg(MCRegister PhysReg) const {
831 return
832 PhysReg == VE::VM0 ||
833 PhysReg == VE::VMP0 ||
834 false;
835}
836
837ArrayRef<const char *> VEGenRegisterInfo::getRegMaskNames() const {
838 static const char *Names[] = {
839 "CSR",
840 "CSR_NoRegs",
841 "CSR_preserve_all",
842 };
843 return ArrayRef(Names);
844}
845
846const VEFrameLowering *
847VEGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
848 return static_cast<const VEFrameLowering *>(
849 MF.getSubtarget().getFrameLowering());
850}
851
852
853} // namespace llvm
854