1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass VEMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f32, MVT::Other,
17 /* 6 */ MVT::i64, MVT::f64, MVT::Other,
18 /* 9 */ MVT::f128, MVT::Other,
19 /* 11 */ MVT::v256i1, MVT::Other,
20 /* 13 */ MVT::v512i1, MVT::Other,
21 /* 15 */ MVT::v256f64, MVT::v512i32, MVT::v512f32, MVT::v256i64, MVT::v256i32, MVT::v256f32, MVT::Other,
22};
23
24static const char *SubRegIndexNameTable[] = { "sub_even", "sub_f32", "sub_i32", "sub_odd", "sub_vm_even", "sub_vm_odd", "sub_odd_then_sub_f32", "sub_odd_then_sub_i32", "" };
25
26static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
27 { .Offset: 65535, .Size: 65535 },
28 { .Offset: 0, .Size: 64 }, // sub_even
29 { .Offset: 0, .Size: 32 }, // sub_f32
30 { .Offset: 32, .Size: 32 }, // sub_i32
31 { .Offset: 64, .Size: 64 }, // sub_odd
32 { .Offset: 0, .Size: 256 }, // sub_vm_even
33 { .Offset: 256, .Size: 256 }, // sub_vm_odd
34 { .Offset: 64, .Size: 32 }, // sub_odd_then_sub_f32
35 { .Offset: 96, .Size: 32 }, // sub_odd_then_sub_i32
36};
37
38
39static const LaneBitmask SubRegIndexLaneMaskTable[] = {
40 LaneBitmask::getAll(),
41 LaneBitmask(0x0000000000000003), // sub_even
42 LaneBitmask(0x0000000000000001), // sub_f32
43 LaneBitmask(0x0000000000000002), // sub_i32
44 LaneBitmask(0x0000000000000030), // sub_odd
45 LaneBitmask(0x0000000000000004), // sub_vm_even
46 LaneBitmask(0x0000000000000008), // sub_vm_odd
47 LaneBitmask(0x0000000000000010), // sub_odd_then_sub_f32
48 LaneBitmask(0x0000000000000020), // sub_odd_then_sub_i32
49 };
50
51
52
53static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
54 // Mode = 0 (Default)
55 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // F32
56 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // I32
57 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 0 }, // VLS
58 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // I64
59 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // MISC
60 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 9 }, // F128
61 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 11 }, // VM
62 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // VM512
63 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // VM512_with_sub_vm_even
64 { .RegSize: 16384, .SpillSize: 16384, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 15 }, // V64
65};
66static const uint32_t F32SubClassMask[] = {
67 0x00000001,
68 0x00000028, // sub_f32
69 0x00000020, // sub_odd_then_sub_f32
70};
71
72static const uint32_t I32SubClassMask[] = {
73 0x00000002,
74 0x00000028, // sub_i32
75 0x00000020, // sub_odd_then_sub_i32
76};
77
78static const uint32_t VLSSubClassMask[] = {
79 0x00000004,
80};
81
82static const uint32_t I64SubClassMask[] = {
83 0x00000008,
84 0x00000020, // sub_even
85 0x00000020, // sub_odd
86};
87
88static const uint32_t MISCSubClassMask[] = {
89 0x00000010,
90};
91
92static const uint32_t F128SubClassMask[] = {
93 0x00000020,
94};
95
96static const uint32_t VMSubClassMask[] = {
97 0x00000040,
98 0x00000100, // sub_vm_even
99 0x00000100, // sub_vm_odd
100};
101
102static const uint32_t VM512SubClassMask[] = {
103 0x00000180,
104};
105
106static const uint32_t VM512_with_sub_vm_evenSubClassMask[] = {
107 0x00000100,
108};
109
110static const uint32_t V64SubClassMask[] = {
111 0x00000200,
112};
113
114static const uint16_t SuperRegIdxSeqs[] = {
115 /* 0 */ 1, 4, 0,
116 /* 3 */ 5, 6, 0,
117 /* 6 */ 2, 7, 0,
118 /* 9 */ 3, 8, 0,
119};
120
121static unsigned const VM512_with_sub_vm_evenSuperclasses[] = {
122 VE::VM512RegClassID,
123};
124
125
126namespace VE { // Register class instances
127 extern const TargetRegisterClass F32RegClass = {
128 .MC: &VEMCRegisterClasses[F32RegClassID],
129 .SubClassMask: F32SubClassMask,
130 .SuperRegIndices: SuperRegIdxSeqs + 6,
131 .LaneMask: LaneBitmask(0x0000000000000001),
132 .AllocationPriority: 0,
133 .GlobalPriority: false,
134 .TSFlags: 0x00, /* TSFlags */
135 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
136 .CoveredBySubRegs: false, /* CoveredBySubRegs */
137 .SuperClasses: nullptr, .SuperClassesSize: 0,
138 .OrderFunc: nullptr
139 };
140
141 extern const TargetRegisterClass I32RegClass = {
142 .MC: &VEMCRegisterClasses[I32RegClassID],
143 .SubClassMask: I32SubClassMask,
144 .SuperRegIndices: SuperRegIdxSeqs + 9,
145 .LaneMask: LaneBitmask(0x0000000000000001),
146 .AllocationPriority: 0,
147 .GlobalPriority: false,
148 .TSFlags: 0x00, /* TSFlags */
149 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
150 .CoveredBySubRegs: false, /* CoveredBySubRegs */
151 .SuperClasses: nullptr, .SuperClassesSize: 0,
152 .OrderFunc: nullptr
153 };
154
155 extern const TargetRegisterClass VLSRegClass = {
156 .MC: &VEMCRegisterClasses[VLSRegClassID],
157 .SubClassMask: VLSSubClassMask,
158 .SuperRegIndices: SuperRegIdxSeqs + 2,
159 .LaneMask: LaneBitmask(0x0000000000000001),
160 .AllocationPriority: 0,
161 .GlobalPriority: false,
162 .TSFlags: 0x00, /* TSFlags */
163 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
164 .CoveredBySubRegs: false, /* CoveredBySubRegs */
165 .SuperClasses: nullptr, .SuperClassesSize: 0,
166 .OrderFunc: nullptr
167 };
168
169 extern const TargetRegisterClass I64RegClass = {
170 .MC: &VEMCRegisterClasses[I64RegClassID],
171 .SubClassMask: I64SubClassMask,
172 .SuperRegIndices: SuperRegIdxSeqs + 0,
173 .LaneMask: LaneBitmask(0x0000000000000003),
174 .AllocationPriority: 0,
175 .GlobalPriority: false,
176 .TSFlags: 0x00, /* TSFlags */
177 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
178 .CoveredBySubRegs: true, /* CoveredBySubRegs */
179 .SuperClasses: nullptr, .SuperClassesSize: 0,
180 .OrderFunc: nullptr
181 };
182
183 extern const TargetRegisterClass MISCRegClass = {
184 .MC: &VEMCRegisterClasses[MISCRegClassID],
185 .SubClassMask: MISCSubClassMask,
186 .SuperRegIndices: SuperRegIdxSeqs + 2,
187 .LaneMask: LaneBitmask(0x0000000000000001),
188 .AllocationPriority: 0,
189 .GlobalPriority: false,
190 .TSFlags: 0x00, /* TSFlags */
191 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
192 .CoveredBySubRegs: false, /* CoveredBySubRegs */
193 .SuperClasses: nullptr, .SuperClassesSize: 0,
194 .OrderFunc: nullptr
195 };
196
197 extern const TargetRegisterClass F128RegClass = {
198 .MC: &VEMCRegisterClasses[F128RegClassID],
199 .SubClassMask: F128SubClassMask,
200 .SuperRegIndices: SuperRegIdxSeqs + 2,
201 .LaneMask: LaneBitmask(0x0000000000000033),
202 .AllocationPriority: 0,
203 .GlobalPriority: false,
204 .TSFlags: 0x00, /* TSFlags */
205 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
206 .CoveredBySubRegs: true, /* CoveredBySubRegs */
207 .SuperClasses: nullptr, .SuperClassesSize: 0,
208 .OrderFunc: nullptr
209 };
210
211 extern const TargetRegisterClass VMRegClass = {
212 .MC: &VEMCRegisterClasses[VMRegClassID],
213 .SubClassMask: VMSubClassMask,
214 .SuperRegIndices: SuperRegIdxSeqs + 3,
215 .LaneMask: LaneBitmask(0x0000000000000001),
216 .AllocationPriority: 0,
217 .GlobalPriority: false,
218 .TSFlags: 0x00, /* TSFlags */
219 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
220 .CoveredBySubRegs: false, /* CoveredBySubRegs */
221 .SuperClasses: nullptr, .SuperClassesSize: 0,
222 .OrderFunc: nullptr
223 };
224
225 extern const TargetRegisterClass VM512RegClass = {
226 .MC: &VEMCRegisterClasses[VM512RegClassID],
227 .SubClassMask: VM512SubClassMask,
228 .SuperRegIndices: SuperRegIdxSeqs + 2,
229 .LaneMask: LaneBitmask(0x000000000000000C),
230 .AllocationPriority: 0,
231 .GlobalPriority: false,
232 .TSFlags: 0x00, /* TSFlags */
233 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
234 .CoveredBySubRegs: false, /* CoveredBySubRegs */
235 .SuperClasses: nullptr, .SuperClassesSize: 0,
236 .OrderFunc: nullptr
237 };
238
239 extern const TargetRegisterClass VM512_with_sub_vm_evenRegClass = {
240 .MC: &VEMCRegisterClasses[VM512_with_sub_vm_evenRegClassID],
241 .SubClassMask: VM512_with_sub_vm_evenSubClassMask,
242 .SuperRegIndices: SuperRegIdxSeqs + 2,
243 .LaneMask: LaneBitmask(0x000000000000000C),
244 .AllocationPriority: 0,
245 .GlobalPriority: false,
246 .TSFlags: 0x00, /* TSFlags */
247 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
248 .CoveredBySubRegs: true, /* CoveredBySubRegs */
249 .SuperClasses: VM512_with_sub_vm_evenSuperclasses, .SuperClassesSize: 1,
250 .OrderFunc: nullptr
251 };
252
253 extern const TargetRegisterClass V64RegClass = {
254 .MC: &VEMCRegisterClasses[V64RegClassID],
255 .SubClassMask: V64SubClassMask,
256 .SuperRegIndices: SuperRegIdxSeqs + 2,
257 .LaneMask: LaneBitmask(0x0000000000000001),
258 .AllocationPriority: 0,
259 .GlobalPriority: false,
260 .TSFlags: 0x00, /* TSFlags */
261 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
262 .CoveredBySubRegs: false, /* CoveredBySubRegs */
263 .SuperClasses: nullptr, .SuperClassesSize: 0,
264 .OrderFunc: nullptr
265 };
266
267} // end namespace VE
268
269namespace {
270 const TargetRegisterClass *const RegisterClasses[] = {
271 &VE::F32RegClass,
272 &VE::I32RegClass,
273 &VE::VLSRegClass,
274 &VE::I64RegClass,
275 &VE::MISCRegClass,
276 &VE::F128RegClass,
277 &VE::VMRegClass,
278 &VE::VM512RegClass,
279 &VE::VM512_with_sub_vm_evenRegClass,
280 &VE::V64RegClass,
281 };
282} // end anonymous namespace
283
284static const uint8_t CostPerUseTable[] = {
2850, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
286
287
288static const bool InAllocatableClassTable[] = {
289false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
290
291
292static const TargetRegisterInfoDesc VERegInfoDesc = { // Extra Descriptors
293.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
294
295unsigned VEGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
296 static const uint8_t RowMap[8] = {
297 0, 0, 0, 1, 0, 0, 0, 0,
298 };
299 static const uint8_t Rows[2][8] = {
300 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
301 { 0, VE::sub_odd_then_sub_f32, VE::sub_odd_then_sub_i32, 0, 0, 0, 0, 0, },
302 };
303
304 --IdxA; assert(IdxA < 8); (void) IdxA;
305 --IdxB; assert(IdxB < 8);
306 return Rows[RowMap[IdxA]][IdxB];
307}
308
309unsigned VEGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
310 static const uint8_t Table[8][8] = {
311 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
312 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
313 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
314 { 0, 0, 0, 0, 0, 0, VE::sub_f32, VE::sub_i32, },
315 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
316 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
317 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
318 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
319 };
320
321 --IdxA; assert(IdxA < 8);
322 --IdxB; assert(IdxB < 8);
323 return Table[IdxA][IdxB];
324 }
325
326 struct MaskRolOp {
327 LaneBitmask Mask;
328 uint8_t RotateLeft;
329 };
330 static const MaskRolOp LaneMaskComposeSequences[] = {
331 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
332 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
333 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
334 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
335 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
336 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 10
337 };
338 static const uint8_t CompositeSequences[] = {
339 0, // to sub_even
340 0, // to sub_f32
341 2, // to sub_i32
342 4, // to sub_odd
343 6, // to sub_vm_even
344 8, // to sub_vm_odd
345 4, // to sub_odd_then_sub_f32
346 10 // to sub_odd_then_sub_i32
347 };
348
349LaneBitmask VEGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
350 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
351 LaneBitmask Result;
352 for (const MaskRolOp *Ops =
353 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
354 Ops->Mask.any(); ++Ops) {
355 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
356 if (unsigned S = Ops->RotateLeft)
357 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
358 else
359 Result |= LaneBitmask(M);
360 }
361 return Result;
362}
363
364LaneBitmask VEGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
365 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
366 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
367 LaneBitmask Result;
368 for (const MaskRolOp *Ops =
369 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
370 Ops->Mask.any(); ++Ops) {
371 LaneBitmask::Type M = LaneMask.getAsInteger();
372 if (unsigned S = Ops->RotateLeft)
373 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
374 else
375 Result |= LaneBitmask(M);
376 }
377 return Result;
378}
379
380const TargetRegisterClass *VEGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
381 static const uint8_t Table[10][8] = {
382 { // F32
383 0, // sub_even
384 0, // sub_f32
385 0, // sub_i32
386 0, // sub_odd
387 0, // sub_vm_even
388 0, // sub_vm_odd
389 0, // sub_odd_then_sub_f32
390 0, // sub_odd_then_sub_i32
391 },
392 { // I32
393 0, // sub_even
394 0, // sub_f32
395 0, // sub_i32
396 0, // sub_odd
397 0, // sub_vm_even
398 0, // sub_vm_odd
399 0, // sub_odd_then_sub_f32
400 0, // sub_odd_then_sub_i32
401 },
402 { // VLS
403 0, // sub_even
404 0, // sub_f32
405 0, // sub_i32
406 0, // sub_odd
407 0, // sub_vm_even
408 0, // sub_vm_odd
409 0, // sub_odd_then_sub_f32
410 0, // sub_odd_then_sub_i32
411 },
412 { // I64
413 0, // sub_even
414 4, // sub_f32 -> I64
415 4, // sub_i32 -> I64
416 0, // sub_odd
417 0, // sub_vm_even
418 0, // sub_vm_odd
419 0, // sub_odd_then_sub_f32
420 0, // sub_odd_then_sub_i32
421 },
422 { // MISC
423 0, // sub_even
424 0, // sub_f32
425 0, // sub_i32
426 0, // sub_odd
427 0, // sub_vm_even
428 0, // sub_vm_odd
429 0, // sub_odd_then_sub_f32
430 0, // sub_odd_then_sub_i32
431 },
432 { // F128
433 6, // sub_even -> F128
434 6, // sub_f32 -> F128
435 6, // sub_i32 -> F128
436 6, // sub_odd -> F128
437 0, // sub_vm_even
438 0, // sub_vm_odd
439 6, // sub_odd_then_sub_f32 -> F128
440 6, // sub_odd_then_sub_i32 -> F128
441 },
442 { // VM
443 0, // sub_even
444 0, // sub_f32
445 0, // sub_i32
446 0, // sub_odd
447 0, // sub_vm_even
448 0, // sub_vm_odd
449 0, // sub_odd_then_sub_f32
450 0, // sub_odd_then_sub_i32
451 },
452 { // VM512
453 0, // sub_even
454 0, // sub_f32
455 0, // sub_i32
456 0, // sub_odd
457 9, // sub_vm_even -> VM512_with_sub_vm_even
458 9, // sub_vm_odd -> VM512_with_sub_vm_even
459 0, // sub_odd_then_sub_f32
460 0, // sub_odd_then_sub_i32
461 },
462 { // VM512_with_sub_vm_even
463 0, // sub_even
464 0, // sub_f32
465 0, // sub_i32
466 0, // sub_odd
467 9, // sub_vm_even -> VM512_with_sub_vm_even
468 9, // sub_vm_odd -> VM512_with_sub_vm_even
469 0, // sub_odd_then_sub_f32
470 0, // sub_odd_then_sub_i32
471 },
472 { // V64
473 0, // sub_even
474 0, // sub_f32
475 0, // sub_i32
476 0, // sub_odd
477 0, // sub_vm_even
478 0, // sub_vm_odd
479 0, // sub_odd_then_sub_f32
480 0, // sub_odd_then_sub_i32
481 },
482 };
483 assert(RC && "Missing regclass");
484 if (!Idx) return RC;
485 --Idx;
486 assert(Idx < 8 && "Bad subreg");
487 unsigned TV = Table[RC->getID()][Idx];
488 return TV ? getRegClass(i: TV - 1) : nullptr;
489}
490
491const TargetRegisterClass *VEGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
492 static const uint8_t Table[10][8] = {
493 { // F32
494 0, // F32:sub_even
495 0, // F32:sub_f32
496 0, // F32:sub_i32
497 0, // F32:sub_odd
498 0, // F32:sub_vm_even
499 0, // F32:sub_vm_odd
500 0, // F32:sub_odd_then_sub_f32
501 0, // F32:sub_odd_then_sub_i32
502 },
503 { // I32
504 0, // I32:sub_even
505 0, // I32:sub_f32
506 0, // I32:sub_i32
507 0, // I32:sub_odd
508 0, // I32:sub_vm_even
509 0, // I32:sub_vm_odd
510 0, // I32:sub_odd_then_sub_f32
511 0, // I32:sub_odd_then_sub_i32
512 },
513 { // VLS
514 0, // VLS:sub_even
515 0, // VLS:sub_f32
516 0, // VLS:sub_i32
517 0, // VLS:sub_odd
518 0, // VLS:sub_vm_even
519 0, // VLS:sub_vm_odd
520 0, // VLS:sub_odd_then_sub_f32
521 0, // VLS:sub_odd_then_sub_i32
522 },
523 { // I64
524 0, // I64:sub_even
525 1, // I64:sub_f32 -> F32
526 2, // I64:sub_i32 -> I32
527 0, // I64:sub_odd
528 0, // I64:sub_vm_even
529 0, // I64:sub_vm_odd
530 0, // I64:sub_odd_then_sub_f32
531 0, // I64:sub_odd_then_sub_i32
532 },
533 { // MISC
534 0, // MISC:sub_even
535 0, // MISC:sub_f32
536 0, // MISC:sub_i32
537 0, // MISC:sub_odd
538 0, // MISC:sub_vm_even
539 0, // MISC:sub_vm_odd
540 0, // MISC:sub_odd_then_sub_f32
541 0, // MISC:sub_odd_then_sub_i32
542 },
543 { // F128
544 4, // F128:sub_even -> I64
545 1, // F128:sub_f32 -> F32
546 2, // F128:sub_i32 -> I32
547 4, // F128:sub_odd -> I64
548 0, // F128:sub_vm_even
549 0, // F128:sub_vm_odd
550 1, // F128:sub_odd_then_sub_f32 -> F32
551 2, // F128:sub_odd_then_sub_i32 -> I32
552 },
553 { // VM
554 0, // VM:sub_even
555 0, // VM:sub_f32
556 0, // VM:sub_i32
557 0, // VM:sub_odd
558 0, // VM:sub_vm_even
559 0, // VM:sub_vm_odd
560 0, // VM:sub_odd_then_sub_f32
561 0, // VM:sub_odd_then_sub_i32
562 },
563 { // VM512
564 0, // VM512:sub_even
565 0, // VM512:sub_f32
566 0, // VM512:sub_i32
567 0, // VM512:sub_odd
568 7, // VM512:sub_vm_even -> VM
569 7, // VM512:sub_vm_odd -> VM
570 0, // VM512:sub_odd_then_sub_f32
571 0, // VM512:sub_odd_then_sub_i32
572 },
573 { // VM512_with_sub_vm_even
574 0, // VM512_with_sub_vm_even:sub_even
575 0, // VM512_with_sub_vm_even:sub_f32
576 0, // VM512_with_sub_vm_even:sub_i32
577 0, // VM512_with_sub_vm_even:sub_odd
578 7, // VM512_with_sub_vm_even:sub_vm_even -> VM
579 7, // VM512_with_sub_vm_even:sub_vm_odd -> VM
580 0, // VM512_with_sub_vm_even:sub_odd_then_sub_f32
581 0, // VM512_with_sub_vm_even:sub_odd_then_sub_i32
582 },
583 { // V64
584 0, // V64:sub_even
585 0, // V64:sub_f32
586 0, // V64:sub_i32
587 0, // V64:sub_odd
588 0, // V64:sub_vm_even
589 0, // V64:sub_vm_odd
590 0, // V64:sub_odd_then_sub_f32
591 0, // V64:sub_odd_then_sub_i32
592 },
593 };
594 assert(RC && "Missing regclass");
595 if (!Idx) return RC;
596 --Idx;
597 assert(Idx < 8 && "Bad subreg");
598 unsigned TV = Table[RC->getID()][Idx];
599 return TV ? getRegClass(i: TV - 1) : nullptr;
600}
601
602/// Get the weight in units of pressure for this register class.
603const RegClassWeight &VEGenRegisterInfo::
604getRegClassWeight(const TargetRegisterClass *RC) const {
605 static const RegClassWeight RCWeightTable[] = {
606 {.RegWeight: 2, .WeightLimit: 128}, // F32
607 {.RegWeight: 2, .WeightLimit: 128}, // I32
608 {.RegWeight: 1, .WeightLimit: 1}, // VLS
609 {.RegWeight: 3, .WeightLimit: 192}, // I64
610 {.RegWeight: 1, .WeightLimit: 23}, // MISC
611 {.RegWeight: 6, .WeightLimit: 192}, // F128
612 {.RegWeight: 1, .WeightLimit: 16}, // VM
613 {.RegWeight: 2, .WeightLimit: 16}, // VM512
614 {.RegWeight: 2, .WeightLimit: 14}, // VM512_with_sub_vm_even
615 {.RegWeight: 1, .WeightLimit: 65}, // V64
616 };
617 return RCWeightTable[RC->getID()];
618}
619
620/// Get the weight in units of pressure for this register unit.
621unsigned VEGenRegisterInfo::
622getRegUnitWeight(MCRegUnit RegUnit) const {
623 assert(static_cast<unsigned>(RegUnit) < 299 && "invalid register unit");
624 static const uint8_t RUWeightTable[] = {
625 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, };
626 return RUWeightTable[static_cast<unsigned>(RegUnit)];
627}
628
629
630// Get the number of dimensions of register pressure.
631unsigned VEGenRegisterInfo::getNumRegPressureSets() const {
632 return 9;
633}
634
635// Get the name of this register unit pressure set.
636const char *VEGenRegisterInfo::
637getRegPressureSetName(unsigned Idx) const {
638 static const char *PressureNameTable[] = {
639 "VLS",
640 "VM512",
641 "VM",
642 "VM_with_VM512",
643 "MISC",
644 "V64",
645 "F32",
646 "I32",
647 "I64",
648 };
649 return PressureNameTable[Idx];
650}
651
652// Get the register unit pressure limit for this dimension.
653// This limit must be adjusted dynamically for reserved registers.
654unsigned VEGenRegisterInfo::
655getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
656 static const uint8_t PressureLimitTable[] = {
657 1, // 0: VLS
658 16, // 1: VM512
659 16, // 2: VM
660 18, // 3: VM_with_VM512
661 23, // 4: MISC
662 65, // 5: V64
663 128, // 6: F32
664 128, // 7: I32
665 192, // 8: I64
666 };
667 return PressureLimitTable[Idx];
668}
669
670/// Table of pressure sets per register class or unit.
671static const int RCSetsTable[] = {
672 /* 0 */ 0, -1,
673 /* 2 */ 1, 3, -1,
674 /* 5 */ 1, 2, 3, -1,
675 /* 9 */ 4, -1,
676 /* 11 */ 5, -1,
677 /* 13 */ 6, 8, -1,
678 /* 16 */ 6, 7, 8, -1,
679};
680
681/// Get the dimensions of register pressure impacted by this register class.
682/// Returns a -1 terminated array of pressure set IDs
683const int *VEGenRegisterInfo::
684getRegClassPressureSets(const TargetRegisterClass *RC) const {
685 static const uint8_t RCSetStartTable[] = {
686 13,17,0,14,9,14,6,2,5,11,};
687 return &RCSetsTable[RCSetStartTable[RC->getID()]];
688}
689
690/// Get the dimensions of register pressure impacted by this register unit.
691/// Returns a -1 terminated array of pressure set IDs
692const int *VEGenRegisterInfo::
693getRegUnitPressureSets(MCRegUnit RegUnit) const {
694 assert(static_cast<unsigned>(RegUnit) < 299 && "invalid register unit");
695 static const uint8_t RUSetStartTable[] = {
696 1,9,9,9,9,11,0,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,6,6,5,5,5,5,5,5,5,5,5,5,5,5,5,5,2,};
697 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
698}
699
700extern const MCRegisterDesc VERegDesc[];
701extern const int16_t VERegDiffLists[];
702extern const LaneBitmask VELaneMaskLists[];
703extern const char VERegStrings[];
704extern const char VERegClassStrings[];
705extern const MCPhysReg VERegUnitRoots[][2];
706extern const uint16_t VESubRegIdxLists[];
707extern const uint16_t VERegEncodingTable[];
708// VE Dwarf<->LLVM register mappings.
709extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0Dwarf2L[];
710extern const unsigned VEDwarfFlavour0Dwarf2LSize;
711
712extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0Dwarf2L[];
713extern const unsigned VEEHFlavour0Dwarf2LSize;
714
715extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0L2Dwarf[];
716extern const unsigned VEDwarfFlavour0L2DwarfSize;
717
718extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0L2Dwarf[];
719extern const unsigned VEEHFlavour0L2DwarfSize;
720
721VEGenRegisterInfo::
722VEGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
723 unsigned PC, unsigned HwMode)
724 : TargetRegisterInfo(&VERegInfoDesc, RegisterClasses, RegisterClasses+10,
725 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
726 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
727 InitMCRegisterInfo(D: VERegDesc, NR: 339, RA, PC,
728 C: VEMCRegisterClasses, NC: 10,
729 RURoots: VERegUnitRoots,
730 NRU: 299,
731 DL: VERegDiffLists,
732 RUMS: VELaneMaskLists,
733 Strings: VERegStrings,
734 ClassStrings: VERegClassStrings,
735 SubIndices: VESubRegIdxLists,
736 NumIndices: 9,
737 RET: VERegEncodingTable);
738
739 switch (DwarfFlavour) {
740 default:
741 llvm_unreachable("Unknown DWARF flavour");
742 case 0:
743 mapDwarfRegsToLLVMRegs(Map: VEDwarfFlavour0Dwarf2L, Size: VEDwarfFlavour0Dwarf2LSize, isEH: false);
744 break;
745 }
746 switch (EHFlavour) {
747 default:
748 llvm_unreachable("Unknown DWARF flavour");
749 case 0:
750 mapDwarfRegsToLLVMRegs(Map: VEEHFlavour0Dwarf2L, Size: VEEHFlavour0Dwarf2LSize, isEH: true);
751 break;
752 }
753 switch (DwarfFlavour) {
754 default:
755 llvm_unreachable("Unknown DWARF flavour");
756 case 0:
757 mapLLVMRegsToDwarfRegs(Map: VEDwarfFlavour0L2Dwarf, Size: VEDwarfFlavour0L2DwarfSize, isEH: false);
758 break;
759 }
760 switch (EHFlavour) {
761 default:
762 llvm_unreachable("Unknown DWARF flavour");
763 case 0:
764 mapLLVMRegsToDwarfRegs(Map: VEEHFlavour0L2Dwarf, Size: VEEHFlavour0L2DwarfSize, isEH: true);
765 break;
766 }
767}
768
769static const MCPhysReg CSR_SaveList[] = { VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, 0 };
770static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000ff0, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
771static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
772static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
773static const MCPhysReg CSR_preserve_all_SaveList[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, VE::VM12, VE::VM13, VE::VM14, VE::VM15, 0 };
774static const uint32_t CSR_preserve_all_RegMask[] = { 0xf8000000, 0xfbffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xffffffff, 0x0007ffff, };
775
776
777ArrayRef<const uint32_t *> VEGenRegisterInfo::getRegMasks() const {
778 static const uint32_t *const Masks[] = {
779 CSR_RegMask,
780 CSR_NoRegs_RegMask,
781 CSR_preserve_all_RegMask,
782 };
783 return ArrayRef(Masks);
784}
785
786bool VEGenRegisterInfo::
787isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
788 return
789 false;
790}
791
792bool VEGenRegisterInfo::
793isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
794 return
795 false;
796}
797
798bool VEGenRegisterInfo::
799isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
800 return
801 false;
802}
803
804bool VEGenRegisterInfo::
805isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
806 return
807 false;
808}
809
810bool VEGenRegisterInfo::
811isConstantPhysReg(MCRegister PhysReg) const {
812 return
813 PhysReg == VE::VM0 ||
814 PhysReg == VE::VMP0 ||
815 false;
816}
817
818ArrayRef<const char *> VEGenRegisterInfo::getRegMaskNames() const {
819 static const char *Names[] = {
820 "CSR",
821 "CSR_NoRegs",
822 "CSR_preserve_all",
823 };
824 return ArrayRef(Names);
825}
826
827const VEFrameLowering *
828VEGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
829 return static_cast<const VEFrameLowering *>(
830 MF.getSubtarget().getFrameLowering());
831}
832
833} // end namespace llvm
834
835