1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the WebAssembly target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_ImmI8(int64_t Imm) {
12return -(1 << (8 - 1)) <= Imm && Imm < (1 << 8);
13}
14static bool Predicate_ImmI16(int64_t Imm) {
15return -(1 << (16 - 1)) <= Imm && Imm < (1 << 16);
16}
17static bool Predicate_LaneIdx32(int64_t Imm) {
18return 0 <= Imm && Imm < 32;
19}
20static bool Predicate_LaneIdx16(int64_t Imm) {
21return 0 <= Imm && Imm < 16;
22}
23static bool Predicate_LaneIdx8(int64_t Imm) {
24return 0 <= Imm && Imm < 8;
25}
26static bool Predicate_LaneIdx4(int64_t Imm) {
27return 0 <= Imm && Imm < 4;
28}
29static bool Predicate_LaneIdx2(int64_t Imm) {
30return 0 <= Imm && Imm < 2;
31}
32
33
34// FastEmit functions for ISD::ABS.
35
36Register fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, Register Op0) {
37 if (RetVT.SimpleTy != MVT::v16i8)
38 return Register();
39 if ((Subtarget->hasSIMD128())) {
40 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I8x16, RC: &WebAssembly::V128RegClass, Op0);
41 }
42 return Register();
43}
44
45Register fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, Register Op0) {
46 if (RetVT.SimpleTy != MVT::v8i16)
47 return Register();
48 if ((Subtarget->hasSIMD128())) {
49 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I16x8, RC: &WebAssembly::V128RegClass, Op0);
50 }
51 return Register();
52}
53
54Register fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, Register Op0) {
55 if (RetVT.SimpleTy != MVT::v4i32)
56 return Register();
57 if ((Subtarget->hasSIMD128())) {
58 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I32x4, RC: &WebAssembly::V128RegClass, Op0);
59 }
60 return Register();
61}
62
63Register fastEmit_ISD_ABS_MVT_v2i64_r(MVT RetVT, Register Op0) {
64 if (RetVT.SimpleTy != MVT::v2i64)
65 return Register();
66 if ((Subtarget->hasSIMD128())) {
67 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I64x2, RC: &WebAssembly::V128RegClass, Op0);
68 }
69 return Register();
70}
71
72Register fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, Register Op0) {
73 switch (VT.SimpleTy) {
74 case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0);
75 case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0);
76 case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0);
77 case MVT::v2i64: return fastEmit_ISD_ABS_MVT_v2i64_r(RetVT, Op0);
78 default: return Register();
79 }
80}
81
82// FastEmit functions for ISD::ANY_EXTEND.
83
84Register fastEmit_ISD_ANY_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
85 if (RetVT.SimpleTy != MVT::i64)
86 return Register();
87 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_U_I32, RC: &WebAssembly::I64RegClass, Op0);
88}
89
90Register fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
91 switch (VT.SimpleTy) {
92 case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i32_r(RetVT, Op0);
93 default: return Register();
94 }
95}
96
97// FastEmit functions for ISD::BITCAST.
98
99Register fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, Register Op0) {
100 if (RetVT.SimpleTy != MVT::f32)
101 return Register();
102 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_REINTERPRET_I32, RC: &WebAssembly::F32RegClass, Op0);
103}
104
105Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
106 if (RetVT.SimpleTy != MVT::f64)
107 return Register();
108 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_REINTERPRET_I64, RC: &WebAssembly::F64RegClass, Op0);
109}
110
111Register fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, Register Op0) {
112 if (RetVT.SimpleTy != MVT::i32)
113 return Register();
114 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_REINTERPRET_F32, RC: &WebAssembly::I32RegClass, Op0);
115}
116
117Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
118 if (RetVT.SimpleTy != MVT::i64)
119 return Register();
120 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_REINTERPRET_F64, RC: &WebAssembly::I64RegClass, Op0);
121}
122
123Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
124 switch (VT.SimpleTy) {
125 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
126 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
127 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
128 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
129 default: return Register();
130 }
131}
132
133// FastEmit functions for ISD::CTLZ.
134
135Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
136 if (RetVT.SimpleTy != MVT::i32)
137 return Register();
138 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CLZ_I32, RC: &WebAssembly::I32RegClass, Op0);
139}
140
141Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
142 if (RetVT.SimpleTy != MVT::i64)
143 return Register();
144 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CLZ_I64, RC: &WebAssembly::I64RegClass, Op0);
145}
146
147Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
148 switch (VT.SimpleTy) {
149 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
150 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
151 default: return Register();
152 }
153}
154
155// FastEmit functions for ISD::CTPOP.
156
157Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
158 if (RetVT.SimpleTy != MVT::i32)
159 return Register();
160 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I32, RC: &WebAssembly::I32RegClass, Op0);
161}
162
163Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
164 if (RetVT.SimpleTy != MVT::i64)
165 return Register();
166 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I64, RC: &WebAssembly::I64RegClass, Op0);
167}
168
169Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
170 if (RetVT.SimpleTy != MVT::v16i8)
171 return Register();
172 if ((Subtarget->hasSIMD128())) {
173 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
174 }
175 return Register();
176}
177
178Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
179 switch (VT.SimpleTy) {
180 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
181 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
182 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
183 default: return Register();
184 }
185}
186
187// FastEmit functions for ISD::CTTZ.
188
189Register fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, Register Op0) {
190 if (RetVT.SimpleTy != MVT::i32)
191 return Register();
192 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CTZ_I32, RC: &WebAssembly::I32RegClass, Op0);
193}
194
195Register fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, Register Op0) {
196 if (RetVT.SimpleTy != MVT::i64)
197 return Register();
198 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CTZ_I64, RC: &WebAssembly::I64RegClass, Op0);
199}
200
201Register fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, Register Op0) {
202 switch (VT.SimpleTy) {
203 case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0);
204 case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0);
205 default: return Register();
206 }
207}
208
209// FastEmit functions for ISD::FABS.
210
211Register fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, Register Op0) {
212 if (RetVT.SimpleTy != MVT::f32)
213 return Register();
214 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F32, RC: &WebAssembly::F32RegClass, Op0);
215}
216
217Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
218 if (RetVT.SimpleTy != MVT::f64)
219 return Register();
220 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F64, RC: &WebAssembly::F64RegClass, Op0);
221}
222
223Register fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, Register Op0) {
224 if (RetVT.SimpleTy != MVT::v8f16)
225 return Register();
226 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
227 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F16x8, RC: &WebAssembly::V128RegClass, Op0);
228 }
229 return Register();
230}
231
232Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
233 if (RetVT.SimpleTy != MVT::v4f32)
234 return Register();
235 if ((Subtarget->hasSIMD128())) {
236 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F32x4, RC: &WebAssembly::V128RegClass, Op0);
237 }
238 return Register();
239}
240
241Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
242 if (RetVT.SimpleTy != MVT::v2f64)
243 return Register();
244 if ((Subtarget->hasSIMD128())) {
245 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F64x2, RC: &WebAssembly::V128RegClass, Op0);
246 }
247 return Register();
248}
249
250Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
251 switch (VT.SimpleTy) {
252 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
253 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
254 case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0);
255 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
256 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
257 default: return Register();
258 }
259}
260
261// FastEmit functions for ISD::FCEIL.
262
263Register fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, Register Op0) {
264 if (RetVT.SimpleTy != MVT::f32)
265 return Register();
266 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F32, RC: &WebAssembly::F32RegClass, Op0);
267}
268
269Register fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, Register Op0) {
270 if (RetVT.SimpleTy != MVT::f64)
271 return Register();
272 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F64, RC: &WebAssembly::F64RegClass, Op0);
273}
274
275Register fastEmit_ISD_FCEIL_MVT_v8f16_r(MVT RetVT, Register Op0) {
276 if (RetVT.SimpleTy != MVT::v8f16)
277 return Register();
278 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
279 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F16x8, RC: &WebAssembly::V128RegClass, Op0);
280 }
281 return Register();
282}
283
284Register fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, Register Op0) {
285 if (RetVT.SimpleTy != MVT::v4f32)
286 return Register();
287 if ((Subtarget->hasSIMD128())) {
288 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F32x4, RC: &WebAssembly::V128RegClass, Op0);
289 }
290 return Register();
291}
292
293Register fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, Register Op0) {
294 if (RetVT.SimpleTy != MVT::v2f64)
295 return Register();
296 if ((Subtarget->hasSIMD128())) {
297 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F64x2, RC: &WebAssembly::V128RegClass, Op0);
298 }
299 return Register();
300}
301
302Register fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, Register Op0) {
303 switch (VT.SimpleTy) {
304 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0);
305 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0);
306 case MVT::v8f16: return fastEmit_ISD_FCEIL_MVT_v8f16_r(RetVT, Op0);
307 case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0);
308 case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0);
309 default: return Register();
310 }
311}
312
313// FastEmit functions for ISD::FFLOOR.
314
315Register fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, Register Op0) {
316 if (RetVT.SimpleTy != MVT::f32)
317 return Register();
318 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F32, RC: &WebAssembly::F32RegClass, Op0);
319}
320
321Register fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, Register Op0) {
322 if (RetVT.SimpleTy != MVT::f64)
323 return Register();
324 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F64, RC: &WebAssembly::F64RegClass, Op0);
325}
326
327Register fastEmit_ISD_FFLOOR_MVT_v8f16_r(MVT RetVT, Register Op0) {
328 if (RetVT.SimpleTy != MVT::v8f16)
329 return Register();
330 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
331 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F16x8, RC: &WebAssembly::V128RegClass, Op0);
332 }
333 return Register();
334}
335
336Register fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, Register Op0) {
337 if (RetVT.SimpleTy != MVT::v4f32)
338 return Register();
339 if ((Subtarget->hasSIMD128())) {
340 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F32x4, RC: &WebAssembly::V128RegClass, Op0);
341 }
342 return Register();
343}
344
345Register fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, Register Op0) {
346 if (RetVT.SimpleTy != MVT::v2f64)
347 return Register();
348 if ((Subtarget->hasSIMD128())) {
349 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F64x2, RC: &WebAssembly::V128RegClass, Op0);
350 }
351 return Register();
352}
353
354Register fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, Register Op0) {
355 switch (VT.SimpleTy) {
356 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0);
357 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0);
358 case MVT::v8f16: return fastEmit_ISD_FFLOOR_MVT_v8f16_r(RetVT, Op0);
359 case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0);
360 case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0);
361 default: return Register();
362 }
363}
364
365// FastEmit functions for ISD::FNEARBYINT.
366
367Register fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, Register Op0) {
368 if (RetVT.SimpleTy != MVT::f32)
369 return Register();
370 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
371}
372
373Register fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, Register Op0) {
374 if (RetVT.SimpleTy != MVT::f64)
375 return Register();
376 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
377}
378
379Register fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
380 if (RetVT.SimpleTy != MVT::v8f16)
381 return Register();
382 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
383 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
384 }
385 return Register();
386}
387
388Register fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
389 if (RetVT.SimpleTy != MVT::v4f32)
390 return Register();
391 if ((Subtarget->hasSIMD128())) {
392 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
393 }
394 return Register();
395}
396
397Register fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
398 if (RetVT.SimpleTy != MVT::v2f64)
399 return Register();
400 if ((Subtarget->hasSIMD128())) {
401 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
402 }
403 return Register();
404}
405
406Register fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, Register Op0) {
407 switch (VT.SimpleTy) {
408 case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0);
409 case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0);
410 case MVT::v8f16: return fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(RetVT, Op0);
411 case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0);
412 case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0);
413 default: return Register();
414 }
415}
416
417// FastEmit functions for ISD::FNEG.
418
419Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
420 if (RetVT.SimpleTy != MVT::f32)
421 return Register();
422 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F32, RC: &WebAssembly::F32RegClass, Op0);
423}
424
425Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
426 if (RetVT.SimpleTy != MVT::f64)
427 return Register();
428 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F64, RC: &WebAssembly::F64RegClass, Op0);
429}
430
431Register fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, Register Op0) {
432 if (RetVT.SimpleTy != MVT::v8f16)
433 return Register();
434 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
435 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F16x8, RC: &WebAssembly::V128RegClass, Op0);
436 }
437 return Register();
438}
439
440Register fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, Register Op0) {
441 if (RetVT.SimpleTy != MVT::v4f32)
442 return Register();
443 if ((Subtarget->hasSIMD128())) {
444 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F32x4, RC: &WebAssembly::V128RegClass, Op0);
445 }
446 return Register();
447}
448
449Register fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, Register Op0) {
450 if (RetVT.SimpleTy != MVT::v2f64)
451 return Register();
452 if ((Subtarget->hasSIMD128())) {
453 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F64x2, RC: &WebAssembly::V128RegClass, Op0);
454 }
455 return Register();
456}
457
458Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
459 switch (VT.SimpleTy) {
460 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
461 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
462 case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0);
463 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0);
464 case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0);
465 default: return Register();
466 }
467}
468
469// FastEmit functions for ISD::FP_EXTEND.
470
471Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
472 if (RetVT.SimpleTy != MVT::f64)
473 return Register();
474 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_PROMOTE_F32, RC: &WebAssembly::F64RegClass, Op0);
475}
476
477Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
478 switch (VT.SimpleTy) {
479 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
480 default: return Register();
481 }
482}
483
484// FastEmit functions for ISD::FP_ROUND.
485
486Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
487 if (RetVT.SimpleTy != MVT::f32)
488 return Register();
489 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_DEMOTE_F64, RC: &WebAssembly::F32RegClass, Op0);
490}
491
492Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
493 switch (VT.SimpleTy) {
494 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
495 default: return Register();
496 }
497}
498
499// FastEmit functions for ISD::FP_TO_SINT.
500
501Register fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Register Op0) {
502 if ((!Subtarget->hasNontrappingFPToInt())) {
503 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I32_F32, RC: &WebAssembly::I32RegClass, Op0);
504 }
505 if ((Subtarget->hasNontrappingFPToInt())) {
506 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_S_SAT_F32, RC: &WebAssembly::I32RegClass, Op0);
507 }
508 return Register();
509}
510
511Register fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Register Op0) {
512 if ((!Subtarget->hasNontrappingFPToInt())) {
513 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I64_F32, RC: &WebAssembly::I64RegClass, Op0);
514 }
515 if ((Subtarget->hasNontrappingFPToInt())) {
516 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_S_SAT_F32, RC: &WebAssembly::I64RegClass, Op0);
517 }
518 return Register();
519}
520
521Register fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, Register Op0) {
522switch (RetVT.SimpleTy) {
523 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0);
524 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0);
525 default: return Register();
526}
527}
528
529Register fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Register Op0) {
530 if ((!Subtarget->hasNontrappingFPToInt())) {
531 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I32_F64, RC: &WebAssembly::I32RegClass, Op0);
532 }
533 if ((Subtarget->hasNontrappingFPToInt())) {
534 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_S_SAT_F64, RC: &WebAssembly::I32RegClass, Op0);
535 }
536 return Register();
537}
538
539Register fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Register Op0) {
540 if ((!Subtarget->hasNontrappingFPToInt())) {
541 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I64_F64, RC: &WebAssembly::I64RegClass, Op0);
542 }
543 if ((Subtarget->hasNontrappingFPToInt())) {
544 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_S_SAT_F64, RC: &WebAssembly::I64RegClass, Op0);
545 }
546 return Register();
547}
548
549Register fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, Register Op0) {
550switch (RetVT.SimpleTy) {
551 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0);
552 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0);
553 default: return Register();
554}
555}
556
557Register fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
558 if (RetVT.SimpleTy != MVT::v8i16)
559 return Register();
560 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
561 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_sint_I16x8, RC: &WebAssembly::V128RegClass, Op0);
562 }
563 return Register();
564}
565
566Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
567 if (RetVT.SimpleTy != MVT::v4i32)
568 return Register();
569 if ((Subtarget->hasRelaxedSIMD())) {
570 return fastEmitInst_r(MachineInstOpcode: WebAssembly::int_wasm_relaxed_trunc_signed_I32x4, RC: &WebAssembly::V128RegClass, Op0);
571 }
572 if ((Subtarget->hasSIMD128())) {
573 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_sint_I32x4, RC: &WebAssembly::V128RegClass, Op0);
574 }
575 return Register();
576}
577
578Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
579 switch (VT.SimpleTy) {
580 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
581 case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
582 case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0);
583 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
584 default: return Register();
585 }
586}
587
588// FastEmit functions for ISD::FP_TO_UINT.
589
590Register fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Register Op0) {
591 if ((!Subtarget->hasNontrappingFPToInt())) {
592 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I32_F32, RC: &WebAssembly::I32RegClass, Op0);
593 }
594 if ((Subtarget->hasNontrappingFPToInt())) {
595 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_U_SAT_F32, RC: &WebAssembly::I32RegClass, Op0);
596 }
597 return Register();
598}
599
600Register fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Register Op0) {
601 if ((!Subtarget->hasNontrappingFPToInt())) {
602 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I64_F32, RC: &WebAssembly::I64RegClass, Op0);
603 }
604 if ((Subtarget->hasNontrappingFPToInt())) {
605 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_U_SAT_F32, RC: &WebAssembly::I64RegClass, Op0);
606 }
607 return Register();
608}
609
610Register fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, Register Op0) {
611switch (RetVT.SimpleTy) {
612 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0);
613 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0);
614 default: return Register();
615}
616}
617
618Register fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Register Op0) {
619 if ((!Subtarget->hasNontrappingFPToInt())) {
620 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I32_F64, RC: &WebAssembly::I32RegClass, Op0);
621 }
622 if ((Subtarget->hasNontrappingFPToInt())) {
623 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_U_SAT_F64, RC: &WebAssembly::I32RegClass, Op0);
624 }
625 return Register();
626}
627
628Register fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Register Op0) {
629 if ((!Subtarget->hasNontrappingFPToInt())) {
630 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I64_F64, RC: &WebAssembly::I64RegClass, Op0);
631 }
632 if ((Subtarget->hasNontrappingFPToInt())) {
633 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_U_SAT_F64, RC: &WebAssembly::I64RegClass, Op0);
634 }
635 return Register();
636}
637
638Register fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, Register Op0) {
639switch (RetVT.SimpleTy) {
640 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0);
641 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0);
642 default: return Register();
643}
644}
645
646Register fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
647 if (RetVT.SimpleTy != MVT::v8i16)
648 return Register();
649 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
650 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_uint_I16x8, RC: &WebAssembly::V128RegClass, Op0);
651 }
652 return Register();
653}
654
655Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
656 if (RetVT.SimpleTy != MVT::v4i32)
657 return Register();
658 if ((Subtarget->hasRelaxedSIMD())) {
659 return fastEmitInst_r(MachineInstOpcode: WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4, RC: &WebAssembly::V128RegClass, Op0);
660 }
661 if ((Subtarget->hasSIMD128())) {
662 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_uint_I32x4, RC: &WebAssembly::V128RegClass, Op0);
663 }
664 return Register();
665}
666
667Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
668 switch (VT.SimpleTy) {
669 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
670 case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
671 case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0);
672 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
673 default: return Register();
674 }
675}
676
677// FastEmit functions for ISD::FRINT.
678
679Register fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, Register Op0) {
680 if (RetVT.SimpleTy != MVT::f32)
681 return Register();
682 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
683}
684
685Register fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, Register Op0) {
686 if (RetVT.SimpleTy != MVT::f64)
687 return Register();
688 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
689}
690
691Register fastEmit_ISD_FRINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
692 if (RetVT.SimpleTy != MVT::v8f16)
693 return Register();
694 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
695}
696
697Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
698 if (RetVT.SimpleTy != MVT::v4f32)
699 return Register();
700 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
701}
702
703Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
704 if (RetVT.SimpleTy != MVT::v2f64)
705 return Register();
706 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
707}
708
709Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
710 switch (VT.SimpleTy) {
711 case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0);
712 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0);
713 case MVT::v8f16: return fastEmit_ISD_FRINT_MVT_v8f16_r(RetVT, Op0);
714 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
715 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
716 default: return Register();
717 }
718}
719
720// FastEmit functions for ISD::FROUNDEVEN.
721
722Register fastEmit_ISD_FROUNDEVEN_MVT_f32_r(MVT RetVT, Register Op0) {
723 if (RetVT.SimpleTy != MVT::f32)
724 return Register();
725 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
726}
727
728Register fastEmit_ISD_FROUNDEVEN_MVT_f64_r(MVT RetVT, Register Op0) {
729 if (RetVT.SimpleTy != MVT::f64)
730 return Register();
731 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
732}
733
734Register fastEmit_ISD_FROUNDEVEN_MVT_v8f16_r(MVT RetVT, Register Op0) {
735 if (RetVT.SimpleTy != MVT::v8f16)
736 return Register();
737 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
738}
739
740Register fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(MVT RetVT, Register Op0) {
741 if (RetVT.SimpleTy != MVT::v4f32)
742 return Register();
743 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
744}
745
746Register fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(MVT RetVT, Register Op0) {
747 if (RetVT.SimpleTy != MVT::v2f64)
748 return Register();
749 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
750}
751
752Register fastEmit_ISD_FROUNDEVEN_r(MVT VT, MVT RetVT, Register Op0) {
753 switch (VT.SimpleTy) {
754 case MVT::f32: return fastEmit_ISD_FROUNDEVEN_MVT_f32_r(RetVT, Op0);
755 case MVT::f64: return fastEmit_ISD_FROUNDEVEN_MVT_f64_r(RetVT, Op0);
756 case MVT::v8f16: return fastEmit_ISD_FROUNDEVEN_MVT_v8f16_r(RetVT, Op0);
757 case MVT::v4f32: return fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(RetVT, Op0);
758 case MVT::v2f64: return fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(RetVT, Op0);
759 default: return Register();
760 }
761}
762
763// FastEmit functions for ISD::FSQRT.
764
765Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
766 if (RetVT.SimpleTy != MVT::f32)
767 return Register();
768 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F32, RC: &WebAssembly::F32RegClass, Op0);
769}
770
771Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
772 if (RetVT.SimpleTy != MVT::f64)
773 return Register();
774 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F64, RC: &WebAssembly::F64RegClass, Op0);
775}
776
777Register fastEmit_ISD_FSQRT_MVT_v8f16_r(MVT RetVT, Register Op0) {
778 if (RetVT.SimpleTy != MVT::v8f16)
779 return Register();
780 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
781 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F16x8, RC: &WebAssembly::V128RegClass, Op0);
782 }
783 return Register();
784}
785
786Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
787 if (RetVT.SimpleTy != MVT::v4f32)
788 return Register();
789 if ((Subtarget->hasSIMD128())) {
790 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
791 }
792 return Register();
793}
794
795Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
796 if (RetVT.SimpleTy != MVT::v2f64)
797 return Register();
798 if ((Subtarget->hasSIMD128())) {
799 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
800 }
801 return Register();
802}
803
804Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
805 switch (VT.SimpleTy) {
806 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
807 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
808 case MVT::v8f16: return fastEmit_ISD_FSQRT_MVT_v8f16_r(RetVT, Op0);
809 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
810 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
811 default: return Register();
812 }
813}
814
815// FastEmit functions for ISD::FTRUNC.
816
817Register fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, Register Op0) {
818 if (RetVT.SimpleTy != MVT::f32)
819 return Register();
820 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F32, RC: &WebAssembly::F32RegClass, Op0);
821}
822
823Register fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, Register Op0) {
824 if (RetVT.SimpleTy != MVT::f64)
825 return Register();
826 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F64, RC: &WebAssembly::F64RegClass, Op0);
827}
828
829Register fastEmit_ISD_FTRUNC_MVT_v8f16_r(MVT RetVT, Register Op0) {
830 if (RetVT.SimpleTy != MVT::v8f16)
831 return Register();
832 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
833 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F16x8, RC: &WebAssembly::V128RegClass, Op0);
834 }
835 return Register();
836}
837
838Register fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, Register Op0) {
839 if (RetVT.SimpleTy != MVT::v4f32)
840 return Register();
841 if ((Subtarget->hasSIMD128())) {
842 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F32x4, RC: &WebAssembly::V128RegClass, Op0);
843 }
844 return Register();
845}
846
847Register fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, Register Op0) {
848 if (RetVT.SimpleTy != MVT::v2f64)
849 return Register();
850 if ((Subtarget->hasSIMD128())) {
851 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F64x2, RC: &WebAssembly::V128RegClass, Op0);
852 }
853 return Register();
854}
855
856Register fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, Register Op0) {
857 switch (VT.SimpleTy) {
858 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0);
859 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0);
860 case MVT::v8f16: return fastEmit_ISD_FTRUNC_MVT_v8f16_r(RetVT, Op0);
861 case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0);
862 case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0);
863 default: return Register();
864 }
865}
866
867// FastEmit functions for ISD::SCALAR_TO_VECTOR.
868
869Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v16i8_r(Register Op0) {
870 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
871}
872
873Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v8i16_r(Register Op0) {
874 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I16x8, RC: &WebAssembly::V128RegClass, Op0);
875}
876
877Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(Register Op0) {
878 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I32x4, RC: &WebAssembly::V128RegClass, Op0);
879}
880
881Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, Register Op0) {
882switch (RetVT.SimpleTy) {
883 case MVT::v16i8: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v16i8_r(Op0);
884 case MVT::v8i16: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v8i16_r(Op0);
885 case MVT::v4i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(Op0);
886 default: return Register();
887}
888}
889
890Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(MVT RetVT, Register Op0) {
891 if (RetVT.SimpleTy != MVT::v2i64)
892 return Register();
893 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I64x2, RC: &WebAssembly::V128RegClass, Op0);
894}
895
896Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, Register Op0) {
897 if (RetVT.SimpleTy != MVT::v4f32)
898 return Register();
899 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
900}
901
902Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(MVT RetVT, Register Op0) {
903 if (RetVT.SimpleTy != MVT::v2f64)
904 return Register();
905 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
906}
907
908Register fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, Register Op0) {
909 switch (VT.SimpleTy) {
910 case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0);
911 case MVT::i64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(RetVT, Op0);
912 case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0);
913 case MVT::f64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(RetVT, Op0);
914 default: return Register();
915 }
916}
917
918// FastEmit functions for ISD::SIGN_EXTEND.
919
920Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
921 if (RetVT.SimpleTy != MVT::i64)
922 return Register();
923 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_S_I32, RC: &WebAssembly::I64RegClass, Op0);
924}
925
926Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
927 switch (VT.SimpleTy) {
928 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
929 default: return Register();
930 }
931}
932
933// FastEmit functions for ISD::SINT_TO_FP.
934
935Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
936 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_S_I32, RC: &WebAssembly::F32RegClass, Op0);
937}
938
939Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
940 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_S_I32, RC: &WebAssembly::F64RegClass, Op0);
941}
942
943Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
944switch (RetVT.SimpleTy) {
945 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
946 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
947 default: return Register();
948}
949}
950
951Register fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Register Op0) {
952 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_S_I64, RC: &WebAssembly::F32RegClass, Op0);
953}
954
955Register fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Register Op0) {
956 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_S_I64, RC: &WebAssembly::F64RegClass, Op0);
957}
958
959Register fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
960switch (RetVT.SimpleTy) {
961 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0);
962 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0);
963 default: return Register();
964}
965}
966
967Register fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, Register Op0) {
968 if (RetVT.SimpleTy != MVT::v8f16)
969 return Register();
970 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
971 return fastEmitInst_r(MachineInstOpcode: WebAssembly::sint_to_fp_F16x8, RC: &WebAssembly::V128RegClass, Op0);
972 }
973 return Register();
974}
975
976Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
977 if (RetVT.SimpleTy != MVT::v4f32)
978 return Register();
979 if ((Subtarget->hasSIMD128())) {
980 return fastEmitInst_r(MachineInstOpcode: WebAssembly::sint_to_fp_F32x4, RC: &WebAssembly::V128RegClass, Op0);
981 }
982 return Register();
983}
984
985Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
986 switch (VT.SimpleTy) {
987 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
988 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
989 case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0);
990 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
991 default: return Register();
992 }
993}
994
995// FastEmit functions for ISD::SPLAT_VECTOR.
996
997Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v16i8_r(Register Op0) {
998 if ((Subtarget->hasSIMD128())) {
999 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
1000 }
1001 return Register();
1002}
1003
1004Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v8i16_r(Register Op0) {
1005 if ((Subtarget->hasSIMD128())) {
1006 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1007 }
1008 return Register();
1009}
1010
1011Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v4i32_r(Register Op0) {
1012 if ((Subtarget->hasSIMD128())) {
1013 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1014 }
1015 return Register();
1016}
1017
1018Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(MVT RetVT, Register Op0) {
1019switch (RetVT.SimpleTy) {
1020 case MVT::v16i8: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v16i8_r(Op0);
1021 case MVT::v8i16: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v8i16_r(Op0);
1022 case MVT::v4i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v4i32_r(Op0);
1023 default: return Register();
1024}
1025}
1026
1027Register fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(MVT RetVT, Register Op0) {
1028 if (RetVT.SimpleTy != MVT::v2i64)
1029 return Register();
1030 if ((Subtarget->hasSIMD128())) {
1031 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1032 }
1033 return Register();
1034}
1035
1036Register fastEmit_ISD_SPLAT_VECTOR_MVT_f32_r(MVT RetVT, Register Op0) {
1037 if (RetVT.SimpleTy != MVT::v4f32)
1038 return Register();
1039 if ((Subtarget->hasSIMD128())) {
1040 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1041 }
1042 return Register();
1043}
1044
1045Register fastEmit_ISD_SPLAT_VECTOR_MVT_f64_r(MVT RetVT, Register Op0) {
1046 if (RetVT.SimpleTy != MVT::v2f64)
1047 return Register();
1048 if ((Subtarget->hasSIMD128())) {
1049 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1050 }
1051 return Register();
1052}
1053
1054Register fastEmit_ISD_SPLAT_VECTOR_r(MVT VT, MVT RetVT, Register Op0) {
1055 switch (VT.SimpleTy) {
1056 case MVT::i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(RetVT, Op0);
1057 case MVT::i64: return fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(RetVT, Op0);
1058 case MVT::f32: return fastEmit_ISD_SPLAT_VECTOR_MVT_f32_r(RetVT, Op0);
1059 case MVT::f64: return fastEmit_ISD_SPLAT_VECTOR_MVT_f64_r(RetVT, Op0);
1060 default: return Register();
1061 }
1062}
1063
1064// FastEmit functions for ISD::TRUNCATE.
1065
1066Register fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, Register Op0) {
1067 if (RetVT.SimpleTy != MVT::i32)
1068 return Register();
1069 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_WRAP_I64, RC: &WebAssembly::I32RegClass, Op0);
1070}
1071
1072Register fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, Register Op0) {
1073 switch (VT.SimpleTy) {
1074 case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0);
1075 default: return Register();
1076 }
1077}
1078
1079// FastEmit functions for ISD::UINT_TO_FP.
1080
1081Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1082 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_U_I32, RC: &WebAssembly::F32RegClass, Op0);
1083}
1084
1085Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1086 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_U_I32, RC: &WebAssembly::F64RegClass, Op0);
1087}
1088
1089Register fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1090switch (RetVT.SimpleTy) {
1091 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1092 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1093 default: return Register();
1094}
1095}
1096
1097Register fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Register Op0) {
1098 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_U_I64, RC: &WebAssembly::F32RegClass, Op0);
1099}
1100
1101Register fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Register Op0) {
1102 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_U_I64, RC: &WebAssembly::F64RegClass, Op0);
1103}
1104
1105Register fastEmit_ISD_UINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
1106switch (RetVT.SimpleTy) {
1107 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0);
1108 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Op0);
1109 default: return Register();
1110}
1111}
1112
1113Register fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, Register Op0) {
1114 if (RetVT.SimpleTy != MVT::v8f16)
1115 return Register();
1116 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1117 return fastEmitInst_r(MachineInstOpcode: WebAssembly::uint_to_fp_F16x8, RC: &WebAssembly::V128RegClass, Op0);
1118 }
1119 return Register();
1120}
1121
1122Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1123 if (RetVT.SimpleTy != MVT::v4f32)
1124 return Register();
1125 if ((Subtarget->hasSIMD128())) {
1126 return fastEmitInst_r(MachineInstOpcode: WebAssembly::uint_to_fp_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1127 }
1128 return Register();
1129}
1130
1131Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1132 switch (VT.SimpleTy) {
1133 case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1134 case MVT::i64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_r(RetVT, Op0);
1135 case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0);
1136 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1137 default: return Register();
1138 }
1139}
1140
1141// FastEmit functions for ISD::ZERO_EXTEND.
1142
1143Register fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
1144 if (RetVT.SimpleTy != MVT::i64)
1145 return Register();
1146 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_U_I32, RC: &WebAssembly::I64RegClass, Op0);
1147}
1148
1149Register fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
1150 switch (VT.SimpleTy) {
1151 case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(RetVT, Op0);
1152 default: return Register();
1153 }
1154}
1155
1156// FastEmit functions for WebAssemblyISD::CONVERT_LOW_S.
1157
1158Register fastEmit_WebAssemblyISD_CONVERT_LOW_S_MVT_v4i32_r(MVT RetVT, Register Op0) {
1159 if (RetVT.SimpleTy != MVT::v2f64)
1160 return Register();
1161 if ((Subtarget->hasSIMD128())) {
1162 return fastEmitInst_r(MachineInstOpcode: WebAssembly::convert_low_s_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1163 }
1164 return Register();
1165}
1166
1167Register fastEmit_WebAssemblyISD_CONVERT_LOW_S_r(MVT VT, MVT RetVT, Register Op0) {
1168 switch (VT.SimpleTy) {
1169 case MVT::v4i32: return fastEmit_WebAssemblyISD_CONVERT_LOW_S_MVT_v4i32_r(RetVT, Op0);
1170 default: return Register();
1171 }
1172}
1173
1174// FastEmit functions for WebAssemblyISD::CONVERT_LOW_U.
1175
1176Register fastEmit_WebAssemblyISD_CONVERT_LOW_U_MVT_v4i32_r(MVT RetVT, Register Op0) {
1177 if (RetVT.SimpleTy != MVT::v2f64)
1178 return Register();
1179 if ((Subtarget->hasSIMD128())) {
1180 return fastEmitInst_r(MachineInstOpcode: WebAssembly::convert_low_u_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1181 }
1182 return Register();
1183}
1184
1185Register fastEmit_WebAssemblyISD_CONVERT_LOW_U_r(MVT VT, MVT RetVT, Register Op0) {
1186 switch (VT.SimpleTy) {
1187 case MVT::v4i32: return fastEmit_WebAssemblyISD_CONVERT_LOW_U_MVT_v4i32_r(RetVT, Op0);
1188 default: return Register();
1189 }
1190}
1191
1192// FastEmit functions for WebAssemblyISD::DEMOTE_ZERO.
1193
1194Register fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v4f32_r(MVT RetVT, Register Op0) {
1195 if (RetVT.SimpleTy != MVT::v8f16)
1196 return Register();
1197 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1198 return fastEmitInst_r(MachineInstOpcode: WebAssembly::demote_zero_F16x8, RC: &WebAssembly::V128RegClass, Op0);
1199 }
1200 return Register();
1201}
1202
1203Register fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v2f64_r(MVT RetVT, Register Op0) {
1204 if (RetVT.SimpleTy != MVT::v4f32)
1205 return Register();
1206 if ((Subtarget->hasSIMD128())) {
1207 return fastEmitInst_r(MachineInstOpcode: WebAssembly::demote_zero_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1208 }
1209 return Register();
1210}
1211
1212Register fastEmit_WebAssemblyISD_DEMOTE_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1213 switch (VT.SimpleTy) {
1214 case MVT::v4f32: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v4f32_r(RetVT, Op0);
1215 case MVT::v2f64: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v2f64_r(RetVT, Op0);
1216 default: return Register();
1217 }
1218}
1219
1220// FastEmit functions for WebAssemblyISD::EXTEND_HIGH_S.
1221
1222Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v16i8_r(MVT RetVT, Register Op0) {
1223 if (RetVT.SimpleTy != MVT::v8i16)
1224 return Register();
1225 if ((Subtarget->hasSIMD128())) {
1226 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1227 }
1228 return Register();
1229}
1230
1231Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v8i16_r(MVT RetVT, Register Op0) {
1232 if (RetVT.SimpleTy != MVT::v4i32)
1233 return Register();
1234 if ((Subtarget->hasSIMD128())) {
1235 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1236 }
1237 return Register();
1238}
1239
1240Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v4i32_r(MVT RetVT, Register Op0) {
1241 if (RetVT.SimpleTy != MVT::v2i64)
1242 return Register();
1243 if ((Subtarget->hasSIMD128())) {
1244 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1245 }
1246 return Register();
1247}
1248
1249Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_r(MVT VT, MVT RetVT, Register Op0) {
1250 switch (VT.SimpleTy) {
1251 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v16i8_r(RetVT, Op0);
1252 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v8i16_r(RetVT, Op0);
1253 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v4i32_r(RetVT, Op0);
1254 default: return Register();
1255 }
1256}
1257
1258// FastEmit functions for WebAssemblyISD::EXTEND_HIGH_U.
1259
1260Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v16i8_r(MVT RetVT, Register Op0) {
1261 if (RetVT.SimpleTy != MVT::v8i16)
1262 return Register();
1263 if ((Subtarget->hasSIMD128())) {
1264 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1265 }
1266 return Register();
1267}
1268
1269Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v8i16_r(MVT RetVT, Register Op0) {
1270 if (RetVT.SimpleTy != MVT::v4i32)
1271 return Register();
1272 if ((Subtarget->hasSIMD128())) {
1273 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1274 }
1275 return Register();
1276}
1277
1278Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v4i32_r(MVT RetVT, Register Op0) {
1279 if (RetVT.SimpleTy != MVT::v2i64)
1280 return Register();
1281 if ((Subtarget->hasSIMD128())) {
1282 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1283 }
1284 return Register();
1285}
1286
1287Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_r(MVT VT, MVT RetVT, Register Op0) {
1288 switch (VT.SimpleTy) {
1289 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v16i8_r(RetVT, Op0);
1290 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v8i16_r(RetVT, Op0);
1291 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v4i32_r(RetVT, Op0);
1292 default: return Register();
1293 }
1294}
1295
1296// FastEmit functions for WebAssemblyISD::EXTEND_LOW_S.
1297
1298Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v16i8_r(MVT RetVT, Register Op0) {
1299 if (RetVT.SimpleTy != MVT::v8i16)
1300 return Register();
1301 if ((Subtarget->hasSIMD128())) {
1302 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1303 }
1304 return Register();
1305}
1306
1307Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v8i16_r(MVT RetVT, Register Op0) {
1308 if (RetVT.SimpleTy != MVT::v4i32)
1309 return Register();
1310 if ((Subtarget->hasSIMD128())) {
1311 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1312 }
1313 return Register();
1314}
1315
1316Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v4i32_r(MVT RetVT, Register Op0) {
1317 if (RetVT.SimpleTy != MVT::v2i64)
1318 return Register();
1319 if ((Subtarget->hasSIMD128())) {
1320 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1321 }
1322 return Register();
1323}
1324
1325Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_r(MVT VT, MVT RetVT, Register Op0) {
1326 switch (VT.SimpleTy) {
1327 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v16i8_r(RetVT, Op0);
1328 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v8i16_r(RetVT, Op0);
1329 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v4i32_r(RetVT, Op0);
1330 default: return Register();
1331 }
1332}
1333
1334// FastEmit functions for WebAssemblyISD::EXTEND_LOW_U.
1335
1336Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v16i8_r(MVT RetVT, Register Op0) {
1337 if (RetVT.SimpleTy != MVT::v8i16)
1338 return Register();
1339 if ((Subtarget->hasSIMD128())) {
1340 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1341 }
1342 return Register();
1343}
1344
1345Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v8i16_r(MVT RetVT, Register Op0) {
1346 if (RetVT.SimpleTy != MVT::v4i32)
1347 return Register();
1348 if ((Subtarget->hasSIMD128())) {
1349 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1350 }
1351 return Register();
1352}
1353
1354Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v4i32_r(MVT RetVT, Register Op0) {
1355 if (RetVT.SimpleTy != MVT::v2i64)
1356 return Register();
1357 if ((Subtarget->hasSIMD128())) {
1358 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1359 }
1360 return Register();
1361}
1362
1363Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_r(MVT VT, MVT RetVT, Register Op0) {
1364 switch (VT.SimpleTy) {
1365 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v16i8_r(RetVT, Op0);
1366 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v8i16_r(RetVT, Op0);
1367 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v4i32_r(RetVT, Op0);
1368 default: return Register();
1369 }
1370}
1371
1372// FastEmit functions for WebAssemblyISD::EXT_ADD_PAIRWISE_S.
1373
1374Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v16i8_r(MVT RetVT, Register Op0) {
1375 if (RetVT.SimpleTy != MVT::v8i16)
1376 return Register();
1377 if ((Subtarget->hasSIMD128())) {
1378 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1379 }
1380 return Register();
1381}
1382
1383Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v8i16_r(MVT RetVT, Register Op0) {
1384 if (RetVT.SimpleTy != MVT::v4i32)
1385 return Register();
1386 if ((Subtarget->hasSIMD128())) {
1387 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1388 }
1389 return Register();
1390}
1391
1392Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_r(MVT VT, MVT RetVT, Register Op0) {
1393 switch (VT.SimpleTy) {
1394 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v16i8_r(RetVT, Op0);
1395 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v8i16_r(RetVT, Op0);
1396 default: return Register();
1397 }
1398}
1399
1400// FastEmit functions for WebAssemblyISD::EXT_ADD_PAIRWISE_U.
1401
1402Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v16i8_r(MVT RetVT, Register Op0) {
1403 if (RetVT.SimpleTy != MVT::v8i16)
1404 return Register();
1405 if ((Subtarget->hasSIMD128())) {
1406 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1407 }
1408 return Register();
1409}
1410
1411Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v8i16_r(MVT RetVT, Register Op0) {
1412 if (RetVT.SimpleTy != MVT::v4i32)
1413 return Register();
1414 if ((Subtarget->hasSIMD128())) {
1415 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1416 }
1417 return Register();
1418}
1419
1420Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_r(MVT VT, MVT RetVT, Register Op0) {
1421 switch (VT.SimpleTy) {
1422 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v16i8_r(RetVT, Op0);
1423 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v8i16_r(RetVT, Op0);
1424 default: return Register();
1425 }
1426}
1427
1428// FastEmit functions for WebAssemblyISD::PROMOTE_LOW.
1429
1430Register fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v8i16_r(MVT RetVT, Register Op0) {
1431 if (RetVT.SimpleTy != MVT::v4f32)
1432 return Register();
1433 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1434 return fastEmitInst_r(MachineInstOpcode: WebAssembly::promote_low_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1435 }
1436 return Register();
1437}
1438
1439Register fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v4f32_r(MVT RetVT, Register Op0) {
1440 if (RetVT.SimpleTy != MVT::v2f64)
1441 return Register();
1442 if ((Subtarget->hasSIMD128())) {
1443 return fastEmitInst_r(MachineInstOpcode: WebAssembly::promote_low_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1444 }
1445 return Register();
1446}
1447
1448Register fastEmit_WebAssemblyISD_PROMOTE_LOW_r(MVT VT, MVT RetVT, Register Op0) {
1449 switch (VT.SimpleTy) {
1450 case MVT::v8i16: return fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v8i16_r(RetVT, Op0);
1451 case MVT::v4f32: return fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v4f32_r(RetVT, Op0);
1452 default: return Register();
1453 }
1454}
1455
1456// FastEmit functions for WebAssemblyISD::TRUNC_SAT_ZERO_S.
1457
1458Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_MVT_v2f64_r(MVT RetVT, Register Op0) {
1459 if (RetVT.SimpleTy != MVT::v4i32)
1460 return Register();
1461 if ((Subtarget->hasSIMD128())) {
1462 return fastEmitInst_r(MachineInstOpcode: WebAssembly::trunc_sat_zero_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1463 }
1464 return Register();
1465}
1466
1467Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_r(MVT VT, MVT RetVT, Register Op0) {
1468 switch (VT.SimpleTy) {
1469 case MVT::v2f64: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_MVT_v2f64_r(RetVT, Op0);
1470 default: return Register();
1471 }
1472}
1473
1474// FastEmit functions for WebAssemblyISD::TRUNC_SAT_ZERO_U.
1475
1476Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_MVT_v2f64_r(MVT RetVT, Register Op0) {
1477 if (RetVT.SimpleTy != MVT::v4i32)
1478 return Register();
1479 if ((Subtarget->hasSIMD128())) {
1480 return fastEmitInst_r(MachineInstOpcode: WebAssembly::trunc_sat_zero_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1481 }
1482 return Register();
1483}
1484
1485Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_r(MVT VT, MVT RetVT, Register Op0) {
1486 switch (VT.SimpleTy) {
1487 case MVT::v2f64: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_MVT_v2f64_r(RetVT, Op0);
1488 default: return Register();
1489 }
1490}
1491
1492// Top-level FastEmit function.
1493
1494Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
1495 switch (Opcode) {
1496 case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0);
1497 case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0);
1498 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1499 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1500 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1501 case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0);
1502 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1503 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0);
1504 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0);
1505 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0);
1506 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1507 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1508 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1509 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1510 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1511 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1512 case ISD::FROUNDEVEN: return fastEmit_ISD_FROUNDEVEN_r(VT, RetVT, Op0);
1513 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1514 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0);
1515 case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0);
1516 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1517 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1518 case ISD::SPLAT_VECTOR: return fastEmit_ISD_SPLAT_VECTOR_r(VT, RetVT, Op0);
1519 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0);
1520 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1521 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0);
1522 case WebAssemblyISD::CONVERT_LOW_S: return fastEmit_WebAssemblyISD_CONVERT_LOW_S_r(VT, RetVT, Op0);
1523 case WebAssemblyISD::CONVERT_LOW_U: return fastEmit_WebAssemblyISD_CONVERT_LOW_U_r(VT, RetVT, Op0);
1524 case WebAssemblyISD::DEMOTE_ZERO: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_r(VT, RetVT, Op0);
1525 case WebAssemblyISD::EXTEND_HIGH_S: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_r(VT, RetVT, Op0);
1526 case WebAssemblyISD::EXTEND_HIGH_U: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_r(VT, RetVT, Op0);
1527 case WebAssemblyISD::EXTEND_LOW_S: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_r(VT, RetVT, Op0);
1528 case WebAssemblyISD::EXTEND_LOW_U: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_r(VT, RetVT, Op0);
1529 case WebAssemblyISD::EXT_ADD_PAIRWISE_S: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_r(VT, RetVT, Op0);
1530 case WebAssemblyISD::EXT_ADD_PAIRWISE_U: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_r(VT, RetVT, Op0);
1531 case WebAssemblyISD::PROMOTE_LOW: return fastEmit_WebAssemblyISD_PROMOTE_LOW_r(VT, RetVT, Op0);
1532 case WebAssemblyISD::TRUNC_SAT_ZERO_S: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_r(VT, RetVT, Op0);
1533 case WebAssemblyISD::TRUNC_SAT_ZERO_U: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_r(VT, RetVT, Op0);
1534 default: return Register();
1535 }
1536}
1537
1538// FastEmit functions for ISD::ADD.
1539
1540Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1541 if (RetVT.SimpleTy != MVT::i32)
1542 return Register();
1543 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
1544}
1545
1546Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1547 if (RetVT.SimpleTy != MVT::i64)
1548 return Register();
1549 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
1550}
1551
1552Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1553 if (RetVT.SimpleTy != MVT::v16i8)
1554 return Register();
1555 if ((Subtarget->hasSIMD128())) {
1556 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
1557 }
1558 return Register();
1559}
1560
1561Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1562 if (RetVT.SimpleTy != MVT::v8i16)
1563 return Register();
1564 if ((Subtarget->hasSIMD128())) {
1565 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1566 }
1567 return Register();
1568}
1569
1570Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1571 if (RetVT.SimpleTy != MVT::v4i32)
1572 return Register();
1573 if ((Subtarget->hasSIMD128())) {
1574 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1575 }
1576 return Register();
1577}
1578
1579Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1580 if (RetVT.SimpleTy != MVT::v2i64)
1581 return Register();
1582 if ((Subtarget->hasSIMD128())) {
1583 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1584 }
1585 return Register();
1586}
1587
1588Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1589 switch (VT.SimpleTy) {
1590 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1591 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1592 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1593 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1594 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1595 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1596 default: return Register();
1597 }
1598}
1599
1600// FastEmit functions for ISD::AND.
1601
1602Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1603 if (RetVT.SimpleTy != MVT::i32)
1604 return Register();
1605 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
1606}
1607
1608Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1609 if (RetVT.SimpleTy != MVT::i64)
1610 return Register();
1611 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
1612}
1613
1614Register fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1615 if (RetVT.SimpleTy != MVT::v16i8)
1616 return Register();
1617 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1618}
1619
1620Register fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1621 if (RetVT.SimpleTy != MVT::v8i16)
1622 return Register();
1623 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1624}
1625
1626Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1627 if (RetVT.SimpleTy != MVT::v4i32)
1628 return Register();
1629 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1630}
1631
1632Register fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1633 if (RetVT.SimpleTy != MVT::v2i64)
1634 return Register();
1635 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1636}
1637
1638Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1639 switch (VT.SimpleTy) {
1640 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1641 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1642 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1643 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1644 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1645 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1646 default: return Register();
1647 }
1648}
1649
1650// FastEmit functions for ISD::AVGCEILU.
1651
1652Register fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1653 if (RetVT.SimpleTy != MVT::v16i8)
1654 return Register();
1655 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AVGR_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
1656}
1657
1658Register fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1659 if (RetVT.SimpleTy != MVT::v8i16)
1660 return Register();
1661 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AVGR_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1662}
1663
1664Register fastEmit_ISD_AVGCEILU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1665 switch (VT.SimpleTy) {
1666 case MVT::v16i8: return fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(RetVT, Op0, Op1);
1667 case MVT::v8i16: return fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(RetVT, Op0, Op1);
1668 default: return Register();
1669 }
1670}
1671
1672// FastEmit functions for ISD::FADD.
1673
1674Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1675 if (RetVT.SimpleTy != MVT::f32)
1676 return Register();
1677 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1678}
1679
1680Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1681 if (RetVT.SimpleTy != MVT::f64)
1682 return Register();
1683 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1684}
1685
1686Register fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1687 if (RetVT.SimpleTy != MVT::v8f16)
1688 return Register();
1689 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1690 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1691 }
1692 return Register();
1693}
1694
1695Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1696 if (RetVT.SimpleTy != MVT::v4f32)
1697 return Register();
1698 if ((Subtarget->hasSIMD128())) {
1699 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1700 }
1701 return Register();
1702}
1703
1704Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1705 if (RetVT.SimpleTy != MVT::v2f64)
1706 return Register();
1707 if ((Subtarget->hasSIMD128())) {
1708 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1709 }
1710 return Register();
1711}
1712
1713Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1714 switch (VT.SimpleTy) {
1715 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1716 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1717 case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op1);
1718 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1719 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1720 default: return Register();
1721 }
1722}
1723
1724// FastEmit functions for ISD::FCOPYSIGN.
1725
1726Register fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1727 if (RetVT.SimpleTy != MVT::f32)
1728 return Register();
1729 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::COPYSIGN_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1730}
1731
1732Register fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1733 if (RetVT.SimpleTy != MVT::f64)
1734 return Register();
1735 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::COPYSIGN_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1736}
1737
1738Register fastEmit_ISD_FCOPYSIGN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1739 switch (VT.SimpleTy) {
1740 case MVT::f32: return fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(RetVT, Op0, Op1);
1741 case MVT::f64: return fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(RetVT, Op0, Op1);
1742 default: return Register();
1743 }
1744}
1745
1746// FastEmit functions for ISD::FDIV.
1747
1748Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1749 if (RetVT.SimpleTy != MVT::f32)
1750 return Register();
1751 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1752}
1753
1754Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1755 if (RetVT.SimpleTy != MVT::f64)
1756 return Register();
1757 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1758}
1759
1760Register fastEmit_ISD_FDIV_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1761 if (RetVT.SimpleTy != MVT::v8f16)
1762 return Register();
1763 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1764 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1765 }
1766 return Register();
1767}
1768
1769Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1770 if (RetVT.SimpleTy != MVT::v4f32)
1771 return Register();
1772 if ((Subtarget->hasSIMD128())) {
1773 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1774 }
1775 return Register();
1776}
1777
1778Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1779 if (RetVT.SimpleTy != MVT::v2f64)
1780 return Register();
1781 if ((Subtarget->hasSIMD128())) {
1782 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1783 }
1784 return Register();
1785}
1786
1787Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1788 switch (VT.SimpleTy) {
1789 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1790 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1791 case MVT::v8f16: return fastEmit_ISD_FDIV_MVT_v8f16_rr(RetVT, Op0, Op1);
1792 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1793 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1794 default: return Register();
1795 }
1796}
1797
1798// FastEmit functions for ISD::FMAXIMUM.
1799
1800Register fastEmit_ISD_FMAXIMUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1801 if (RetVT.SimpleTy != MVT::f32)
1802 return Register();
1803 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1804}
1805
1806Register fastEmit_ISD_FMAXIMUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1807 if (RetVT.SimpleTy != MVT::f64)
1808 return Register();
1809 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1810}
1811
1812Register fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1813 if (RetVT.SimpleTy != MVT::v8f16)
1814 return Register();
1815 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1816 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1817 }
1818 return Register();
1819}
1820
1821Register fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1822 if (RetVT.SimpleTy != MVT::v4f32)
1823 return Register();
1824 if ((Subtarget->hasSIMD128())) {
1825 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1826 }
1827 return Register();
1828}
1829
1830Register fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1831 if (RetVT.SimpleTy != MVT::v2f64)
1832 return Register();
1833 if ((Subtarget->hasSIMD128())) {
1834 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1835 }
1836 return Register();
1837}
1838
1839Register fastEmit_ISD_FMAXIMUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1840 switch (VT.SimpleTy) {
1841 case MVT::f32: return fastEmit_ISD_FMAXIMUM_MVT_f32_rr(RetVT, Op0, Op1);
1842 case MVT::f64: return fastEmit_ISD_FMAXIMUM_MVT_f64_rr(RetVT, Op0, Op1);
1843 case MVT::v8f16: return fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(RetVT, Op0, Op1);
1844 case MVT::v4f32: return fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(RetVT, Op0, Op1);
1845 case MVT::v2f64: return fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(RetVT, Op0, Op1);
1846 default: return Register();
1847 }
1848}
1849
1850// FastEmit functions for ISD::FMINIMUM.
1851
1852Register fastEmit_ISD_FMINIMUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1853 if (RetVT.SimpleTy != MVT::f32)
1854 return Register();
1855 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1856}
1857
1858Register fastEmit_ISD_FMINIMUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1859 if (RetVT.SimpleTy != MVT::f64)
1860 return Register();
1861 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1862}
1863
1864Register fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1865 if (RetVT.SimpleTy != MVT::v8f16)
1866 return Register();
1867 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1868 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1869 }
1870 return Register();
1871}
1872
1873Register fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1874 if (RetVT.SimpleTy != MVT::v4f32)
1875 return Register();
1876 if ((Subtarget->hasSIMD128())) {
1877 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1878 }
1879 return Register();
1880}
1881
1882Register fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1883 if (RetVT.SimpleTy != MVT::v2f64)
1884 return Register();
1885 if ((Subtarget->hasSIMD128())) {
1886 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1887 }
1888 return Register();
1889}
1890
1891Register fastEmit_ISD_FMINIMUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1892 switch (VT.SimpleTy) {
1893 case MVT::f32: return fastEmit_ISD_FMINIMUM_MVT_f32_rr(RetVT, Op0, Op1);
1894 case MVT::f64: return fastEmit_ISD_FMINIMUM_MVT_f64_rr(RetVT, Op0, Op1);
1895 case MVT::v8f16: return fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(RetVT, Op0, Op1);
1896 case MVT::v4f32: return fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(RetVT, Op0, Op1);
1897 case MVT::v2f64: return fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(RetVT, Op0, Op1);
1898 default: return Register();
1899 }
1900}
1901
1902// FastEmit functions for ISD::FMUL.
1903
1904Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1905 if (RetVT.SimpleTy != MVT::f32)
1906 return Register();
1907 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1908}
1909
1910Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1911 if (RetVT.SimpleTy != MVT::f64)
1912 return Register();
1913 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1914}
1915
1916Register fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1917 if (RetVT.SimpleTy != MVT::v8f16)
1918 return Register();
1919 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1920 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1921 }
1922 return Register();
1923}
1924
1925Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1926 if (RetVT.SimpleTy != MVT::v4f32)
1927 return Register();
1928 if ((Subtarget->hasSIMD128())) {
1929 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1930 }
1931 return Register();
1932}
1933
1934Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1935 if (RetVT.SimpleTy != MVT::v2f64)
1936 return Register();
1937 if ((Subtarget->hasSIMD128())) {
1938 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1939 }
1940 return Register();
1941}
1942
1943Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1944 switch (VT.SimpleTy) {
1945 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1946 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1947 case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op1);
1948 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1949 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1950 default: return Register();
1951 }
1952}
1953
1954// FastEmit functions for ISD::FSUB.
1955
1956Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1957 if (RetVT.SimpleTy != MVT::f32)
1958 return Register();
1959 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1960}
1961
1962Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1963 if (RetVT.SimpleTy != MVT::f64)
1964 return Register();
1965 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1966}
1967
1968Register fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1969 if (RetVT.SimpleTy != MVT::v8f16)
1970 return Register();
1971 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1972 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1973 }
1974 return Register();
1975}
1976
1977Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1978 if (RetVT.SimpleTy != MVT::v4f32)
1979 return Register();
1980 if ((Subtarget->hasSIMD128())) {
1981 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1982 }
1983 return Register();
1984}
1985
1986Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1987 if (RetVT.SimpleTy != MVT::v2f64)
1988 return Register();
1989 if ((Subtarget->hasSIMD128())) {
1990 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1991 }
1992 return Register();
1993}
1994
1995Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1996 switch (VT.SimpleTy) {
1997 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
1998 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
1999 case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op1);
2000 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
2001 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
2002 default: return Register();
2003 }
2004}
2005
2006// FastEmit functions for ISD::MUL.
2007
2008Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2009 if (RetVT.SimpleTy != MVT::i32)
2010 return Register();
2011 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2012}
2013
2014Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2015 if (RetVT.SimpleTy != MVT::i64)
2016 return Register();
2017 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2018}
2019
2020Register fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2021 if (RetVT.SimpleTy != MVT::v8i16)
2022 return Register();
2023 if ((Subtarget->hasSIMD128())) {
2024 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2025 }
2026 return Register();
2027}
2028
2029Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2030 if (RetVT.SimpleTy != MVT::v4i32)
2031 return Register();
2032 if ((Subtarget->hasSIMD128())) {
2033 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2034 }
2035 return Register();
2036}
2037
2038Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2039 if (RetVT.SimpleTy != MVT::v2i64)
2040 return Register();
2041 if ((Subtarget->hasSIMD128())) {
2042 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2043 }
2044 return Register();
2045}
2046
2047Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2048 switch (VT.SimpleTy) {
2049 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
2050 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
2051 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
2052 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
2053 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
2054 default: return Register();
2055 }
2056}
2057
2058// FastEmit functions for ISD::OR.
2059
2060Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2061 if (RetVT.SimpleTy != MVT::i32)
2062 return Register();
2063 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2064}
2065
2066Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2067 if (RetVT.SimpleTy != MVT::i64)
2068 return Register();
2069 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2070}
2071
2072Register fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2073 if (RetVT.SimpleTy != MVT::v16i8)
2074 return Register();
2075 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2076}
2077
2078Register fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2079 if (RetVT.SimpleTy != MVT::v8i16)
2080 return Register();
2081 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2082}
2083
2084Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2085 if (RetVT.SimpleTy != MVT::v4i32)
2086 return Register();
2087 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2088}
2089
2090Register fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2091 if (RetVT.SimpleTy != MVT::v2i64)
2092 return Register();
2093 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2094}
2095
2096Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2097 switch (VT.SimpleTy) {
2098 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
2099 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
2100 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
2101 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
2102 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
2103 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
2104 default: return Register();
2105 }
2106}
2107
2108// FastEmit functions for ISD::ROTL.
2109
2110Register fastEmit_ISD_ROTL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2111 if (RetVT.SimpleTy != MVT::i32)
2112 return Register();
2113 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2114}
2115
2116Register fastEmit_ISD_ROTL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2117 if (RetVT.SimpleTy != MVT::i64)
2118 return Register();
2119 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2120}
2121
2122Register fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2123 switch (VT.SimpleTy) {
2124 case MVT::i32: return fastEmit_ISD_ROTL_MVT_i32_rr(RetVT, Op0, Op1);
2125 case MVT::i64: return fastEmit_ISD_ROTL_MVT_i64_rr(RetVT, Op0, Op1);
2126 default: return Register();
2127 }
2128}
2129
2130// FastEmit functions for ISD::ROTR.
2131
2132Register fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2133 if (RetVT.SimpleTy != MVT::i32)
2134 return Register();
2135 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2136}
2137
2138Register fastEmit_ISD_ROTR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2139 if (RetVT.SimpleTy != MVT::i64)
2140 return Register();
2141 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2142}
2143
2144Register fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2145 switch (VT.SimpleTy) {
2146 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
2147 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_rr(RetVT, Op0, Op1);
2148 default: return Register();
2149 }
2150}
2151
2152// FastEmit functions for ISD::SADDSAT.
2153
2154Register fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2155 if (RetVT.SimpleTy != MVT::v16i8)
2156 return Register();
2157 if ((Subtarget->hasSIMD128())) {
2158 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2159 }
2160 return Register();
2161}
2162
2163Register fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2164 if (RetVT.SimpleTy != MVT::v8i16)
2165 return Register();
2166 if ((Subtarget->hasSIMD128())) {
2167 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2168 }
2169 return Register();
2170}
2171
2172Register fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2173 switch (VT.SimpleTy) {
2174 case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2175 case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2176 default: return Register();
2177 }
2178}
2179
2180// FastEmit functions for ISD::SDIV.
2181
2182Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2183 if (RetVT.SimpleTy != MVT::i32)
2184 return Register();
2185 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2186}
2187
2188Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2189 if (RetVT.SimpleTy != MVT::i64)
2190 return Register();
2191 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2192}
2193
2194Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2195 switch (VT.SimpleTy) {
2196 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
2197 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
2198 default: return Register();
2199 }
2200}
2201
2202// FastEmit functions for ISD::SHL.
2203
2204Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2205 if (RetVT.SimpleTy != MVT::i32)
2206 return Register();
2207 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2208}
2209
2210Register fastEmit_ISD_SHL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2211 if (RetVT.SimpleTy != MVT::i64)
2212 return Register();
2213 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2214}
2215
2216Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2217 switch (VT.SimpleTy) {
2218 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
2219 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_rr(RetVT, Op0, Op1);
2220 default: return Register();
2221 }
2222}
2223
2224// FastEmit functions for ISD::SMAX.
2225
2226Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2227 if (RetVT.SimpleTy != MVT::v16i8)
2228 return Register();
2229 if ((Subtarget->hasSIMD128())) {
2230 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2231 }
2232 return Register();
2233}
2234
2235Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2236 if (RetVT.SimpleTy != MVT::v8i16)
2237 return Register();
2238 if ((Subtarget->hasSIMD128())) {
2239 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2240 }
2241 return Register();
2242}
2243
2244Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2245 if (RetVT.SimpleTy != MVT::v4i32)
2246 return Register();
2247 if ((Subtarget->hasSIMD128())) {
2248 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2249 }
2250 return Register();
2251}
2252
2253Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2254 switch (VT.SimpleTy) {
2255 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2256 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2257 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2258 default: return Register();
2259 }
2260}
2261
2262// FastEmit functions for ISD::SMIN.
2263
2264Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2265 if (RetVT.SimpleTy != MVT::v16i8)
2266 return Register();
2267 if ((Subtarget->hasSIMD128())) {
2268 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2269 }
2270 return Register();
2271}
2272
2273Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2274 if (RetVT.SimpleTy != MVT::v8i16)
2275 return Register();
2276 if ((Subtarget->hasSIMD128())) {
2277 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2278 }
2279 return Register();
2280}
2281
2282Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2283 if (RetVT.SimpleTy != MVT::v4i32)
2284 return Register();
2285 if ((Subtarget->hasSIMD128())) {
2286 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2287 }
2288 return Register();
2289}
2290
2291Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2292 switch (VT.SimpleTy) {
2293 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2294 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2295 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2296 default: return Register();
2297 }
2298}
2299
2300// FastEmit functions for ISD::SRA.
2301
2302Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2303 if (RetVT.SimpleTy != MVT::i32)
2304 return Register();
2305 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2306}
2307
2308Register fastEmit_ISD_SRA_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2309 if (RetVT.SimpleTy != MVT::i64)
2310 return Register();
2311 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2312}
2313
2314Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2315 switch (VT.SimpleTy) {
2316 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2317 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_rr(RetVT, Op0, Op1);
2318 default: return Register();
2319 }
2320}
2321
2322// FastEmit functions for ISD::SREM.
2323
2324Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2325 if (RetVT.SimpleTy != MVT::i32)
2326 return Register();
2327 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2328}
2329
2330Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2331 if (RetVT.SimpleTy != MVT::i64)
2332 return Register();
2333 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2334}
2335
2336Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2337 switch (VT.SimpleTy) {
2338 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2339 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2340 default: return Register();
2341 }
2342}
2343
2344// FastEmit functions for ISD::SRL.
2345
2346Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2347 if (RetVT.SimpleTy != MVT::i32)
2348 return Register();
2349 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2350}
2351
2352Register fastEmit_ISD_SRL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2353 if (RetVT.SimpleTy != MVT::i64)
2354 return Register();
2355 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2356}
2357
2358Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2359 switch (VT.SimpleTy) {
2360 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2361 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_rr(RetVT, Op0, Op1);
2362 default: return Register();
2363 }
2364}
2365
2366// FastEmit functions for ISD::SSUBSAT.
2367
2368Register fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2369 if (RetVT.SimpleTy != MVT::v16i8)
2370 return Register();
2371 if ((Subtarget->hasSIMD128())) {
2372 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2373 }
2374 return Register();
2375}
2376
2377Register fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2378 if (RetVT.SimpleTy != MVT::v8i16)
2379 return Register();
2380 if ((Subtarget->hasSIMD128())) {
2381 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2382 }
2383 return Register();
2384}
2385
2386Register fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2387 switch (VT.SimpleTy) {
2388 case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2389 case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2390 default: return Register();
2391 }
2392}
2393
2394// FastEmit functions for ISD::SUB.
2395
2396Register fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2397 if (RetVT.SimpleTy != MVT::i32)
2398 return Register();
2399 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2400}
2401
2402Register fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2403 if (RetVT.SimpleTy != MVT::i64)
2404 return Register();
2405 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2406}
2407
2408Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2409 if (RetVT.SimpleTy != MVT::v16i8)
2410 return Register();
2411 if ((Subtarget->hasSIMD128())) {
2412 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2413 }
2414 return Register();
2415}
2416
2417Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2418 if (RetVT.SimpleTy != MVT::v8i16)
2419 return Register();
2420 if ((Subtarget->hasSIMD128())) {
2421 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2422 }
2423 return Register();
2424}
2425
2426Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2427 if (RetVT.SimpleTy != MVT::v4i32)
2428 return Register();
2429 if ((Subtarget->hasSIMD128())) {
2430 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2431 }
2432 return Register();
2433}
2434
2435Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2436 if (RetVT.SimpleTy != MVT::v2i64)
2437 return Register();
2438 if ((Subtarget->hasSIMD128())) {
2439 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2440 }
2441 return Register();
2442}
2443
2444Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2445 switch (VT.SimpleTy) {
2446 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2447 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2448 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2449 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2450 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2451 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2452 default: return Register();
2453 }
2454}
2455
2456// FastEmit functions for ISD::UADDSAT.
2457
2458Register fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2459 if (RetVT.SimpleTy != MVT::v16i8)
2460 return Register();
2461 if ((Subtarget->hasSIMD128())) {
2462 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2463 }
2464 return Register();
2465}
2466
2467Register fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2468 if (RetVT.SimpleTy != MVT::v8i16)
2469 return Register();
2470 if ((Subtarget->hasSIMD128())) {
2471 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2472 }
2473 return Register();
2474}
2475
2476Register fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2477 switch (VT.SimpleTy) {
2478 case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2479 case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2480 default: return Register();
2481 }
2482}
2483
2484// FastEmit functions for ISD::UDIV.
2485
2486Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2487 if (RetVT.SimpleTy != MVT::i32)
2488 return Register();
2489 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2490}
2491
2492Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2493 if (RetVT.SimpleTy != MVT::i64)
2494 return Register();
2495 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2496}
2497
2498Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2499 switch (VT.SimpleTy) {
2500 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2501 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2502 default: return Register();
2503 }
2504}
2505
2506// FastEmit functions for ISD::UMAX.
2507
2508Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2509 if (RetVT.SimpleTy != MVT::v16i8)
2510 return Register();
2511 if ((Subtarget->hasSIMD128())) {
2512 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2513 }
2514 return Register();
2515}
2516
2517Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2518 if (RetVT.SimpleTy != MVT::v8i16)
2519 return Register();
2520 if ((Subtarget->hasSIMD128())) {
2521 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2522 }
2523 return Register();
2524}
2525
2526Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2527 if (RetVT.SimpleTy != MVT::v4i32)
2528 return Register();
2529 if ((Subtarget->hasSIMD128())) {
2530 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2531 }
2532 return Register();
2533}
2534
2535Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2536 switch (VT.SimpleTy) {
2537 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2538 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2539 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2540 default: return Register();
2541 }
2542}
2543
2544// FastEmit functions for ISD::UMIN.
2545
2546Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2547 if (RetVT.SimpleTy != MVT::v16i8)
2548 return Register();
2549 if ((Subtarget->hasSIMD128())) {
2550 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2551 }
2552 return Register();
2553}
2554
2555Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2556 if (RetVT.SimpleTy != MVT::v8i16)
2557 return Register();
2558 if ((Subtarget->hasSIMD128())) {
2559 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2560 }
2561 return Register();
2562}
2563
2564Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2565 if (RetVT.SimpleTy != MVT::v4i32)
2566 return Register();
2567 if ((Subtarget->hasSIMD128())) {
2568 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2569 }
2570 return Register();
2571}
2572
2573Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2574 switch (VT.SimpleTy) {
2575 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2576 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2577 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2578 default: return Register();
2579 }
2580}
2581
2582// FastEmit functions for ISD::UREM.
2583
2584Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2585 if (RetVT.SimpleTy != MVT::i32)
2586 return Register();
2587 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2588}
2589
2590Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2591 if (RetVT.SimpleTy != MVT::i64)
2592 return Register();
2593 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2594}
2595
2596Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2597 switch (VT.SimpleTy) {
2598 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
2599 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
2600 default: return Register();
2601 }
2602}
2603
2604// FastEmit functions for ISD::USUBSAT.
2605
2606Register fastEmit_ISD_USUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2607 if (RetVT.SimpleTy != MVT::v16i8)
2608 return Register();
2609 if ((Subtarget->hasSIMD128())) {
2610 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2611 }
2612 return Register();
2613}
2614
2615Register fastEmit_ISD_USUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2616 if (RetVT.SimpleTy != MVT::v8i16)
2617 return Register();
2618 if ((Subtarget->hasSIMD128())) {
2619 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2620 }
2621 return Register();
2622}
2623
2624Register fastEmit_ISD_USUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2625 switch (VT.SimpleTy) {
2626 case MVT::v16i8: return fastEmit_ISD_USUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2627 case MVT::v8i16: return fastEmit_ISD_USUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2628 default: return Register();
2629 }
2630}
2631
2632// FastEmit functions for ISD::XOR.
2633
2634Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2635 if (RetVT.SimpleTy != MVT::i32)
2636 return Register();
2637 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2638}
2639
2640Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2641 if (RetVT.SimpleTy != MVT::i64)
2642 return Register();
2643 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2644}
2645
2646Register fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2647 if (RetVT.SimpleTy != MVT::v16i8)
2648 return Register();
2649 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2650}
2651
2652Register fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2653 if (RetVT.SimpleTy != MVT::v8i16)
2654 return Register();
2655 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2656}
2657
2658Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2659 if (RetVT.SimpleTy != MVT::v4i32)
2660 return Register();
2661 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2662}
2663
2664Register fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2665 if (RetVT.SimpleTy != MVT::v2i64)
2666 return Register();
2667 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2668}
2669
2670Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2671 switch (VT.SimpleTy) {
2672 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
2673 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
2674 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
2675 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
2676 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
2677 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
2678 default: return Register();
2679 }
2680}
2681
2682// FastEmit functions for WebAssemblyISD::DOT.
2683
2684Register fastEmit_WebAssemblyISD_DOT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2685 if (RetVT.SimpleTy != MVT::v4i32)
2686 return Register();
2687 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DOT, RC: &WebAssembly::V128RegClass, Op0, Op1);
2688}
2689
2690Register fastEmit_WebAssemblyISD_DOT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2691 switch (VT.SimpleTy) {
2692 case MVT::v8i16: return fastEmit_WebAssemblyISD_DOT_MVT_v8i16_rr(RetVT, Op0, Op1);
2693 default: return Register();
2694 }
2695}
2696
2697// FastEmit functions for WebAssemblyISD::NARROW_U.
2698
2699Register fastEmit_WebAssemblyISD_NARROW_U_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2700 if (RetVT.SimpleTy != MVT::v16i8)
2701 return Register();
2702 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::NARROW_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2703}
2704
2705Register fastEmit_WebAssemblyISD_NARROW_U_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2706 if (RetVT.SimpleTy != MVT::v8i16)
2707 return Register();
2708 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::NARROW_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2709}
2710
2711Register fastEmit_WebAssemblyISD_NARROW_U_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2712 switch (VT.SimpleTy) {
2713 case MVT::v8i16: return fastEmit_WebAssemblyISD_NARROW_U_MVT_v8i16_rr(RetVT, Op0, Op1);
2714 case MVT::v4i32: return fastEmit_WebAssemblyISD_NARROW_U_MVT_v4i32_rr(RetVT, Op0, Op1);
2715 default: return Register();
2716 }
2717}
2718
2719// FastEmit functions for WebAssemblyISD::RELAXED_FMAX.
2720
2721Register fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
2722 if (RetVT.SimpleTy != MVT::v4f32)
2723 return Register();
2724 if ((Subtarget->hasRelaxedSIMD())) {
2725 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMAX_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2726 }
2727 return Register();
2728}
2729
2730Register fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
2731 if (RetVT.SimpleTy != MVT::v2f64)
2732 return Register();
2733 if ((Subtarget->hasRelaxedSIMD())) {
2734 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMAX_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2735 }
2736 return Register();
2737}
2738
2739Register fastEmit_WebAssemblyISD_RELAXED_FMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2740 switch (VT.SimpleTy) {
2741 case MVT::v4f32: return fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v4f32_rr(RetVT, Op0, Op1);
2742 case MVT::v2f64: return fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v2f64_rr(RetVT, Op0, Op1);
2743 default: return Register();
2744 }
2745}
2746
2747// FastEmit functions for WebAssemblyISD::RELAXED_FMIN.
2748
2749Register fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
2750 if (RetVT.SimpleTy != MVT::v4f32)
2751 return Register();
2752 if ((Subtarget->hasRelaxedSIMD())) {
2753 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMIN_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2754 }
2755 return Register();
2756}
2757
2758Register fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
2759 if (RetVT.SimpleTy != MVT::v2f64)
2760 return Register();
2761 if ((Subtarget->hasRelaxedSIMD())) {
2762 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMIN_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2763 }
2764 return Register();
2765}
2766
2767Register fastEmit_WebAssemblyISD_RELAXED_FMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2768 switch (VT.SimpleTy) {
2769 case MVT::v4f32: return fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v4f32_rr(RetVT, Op0, Op1);
2770 case MVT::v2f64: return fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v2f64_rr(RetVT, Op0, Op1);
2771 default: return Register();
2772 }
2773}
2774
2775// FastEmit functions for WebAssemblyISD::SWIZZLE.
2776
2777Register fastEmit_WebAssemblyISD_SWIZZLE_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2778 if (RetVT.SimpleTy != MVT::v16i8)
2779 return Register();
2780 if ((Subtarget->hasSIMD128())) {
2781 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SWIZZLE, RC: &WebAssembly::V128RegClass, Op0, Op1);
2782 }
2783 return Register();
2784}
2785
2786Register fastEmit_WebAssemblyISD_SWIZZLE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2787 switch (VT.SimpleTy) {
2788 case MVT::v16i8: return fastEmit_WebAssemblyISD_SWIZZLE_MVT_v16i8_rr(RetVT, Op0, Op1);
2789 default: return Register();
2790 }
2791}
2792
2793// Top-level FastEmit function.
2794
2795Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
2796 switch (Opcode) {
2797 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
2798 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
2799 case ISD::AVGCEILU: return fastEmit_ISD_AVGCEILU_rr(VT, RetVT, Op0, Op1);
2800 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
2801 case ISD::FCOPYSIGN: return fastEmit_ISD_FCOPYSIGN_rr(VT, RetVT, Op0, Op1);
2802 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
2803 case ISD::FMAXIMUM: return fastEmit_ISD_FMAXIMUM_rr(VT, RetVT, Op0, Op1);
2804 case ISD::FMINIMUM: return fastEmit_ISD_FMINIMUM_rr(VT, RetVT, Op0, Op1);
2805 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
2806 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
2807 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
2808 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
2809 case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op1);
2810 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
2811 case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op1);
2812 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
2813 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
2814 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
2815 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
2816 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
2817 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
2818 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
2819 case ISD::SSUBSAT: return fastEmit_ISD_SSUBSAT_rr(VT, RetVT, Op0, Op1);
2820 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
2821 case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op1);
2822 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
2823 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
2824 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
2825 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
2826 case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op1);
2827 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
2828 case WebAssemblyISD::DOT: return fastEmit_WebAssemblyISD_DOT_rr(VT, RetVT, Op0, Op1);
2829 case WebAssemblyISD::NARROW_U: return fastEmit_WebAssemblyISD_NARROW_U_rr(VT, RetVT, Op0, Op1);
2830 case WebAssemblyISD::RELAXED_FMAX: return fastEmit_WebAssemblyISD_RELAXED_FMAX_rr(VT, RetVT, Op0, Op1);
2831 case WebAssemblyISD::RELAXED_FMIN: return fastEmit_WebAssemblyISD_RELAXED_FMIN_rr(VT, RetVT, Op0, Op1);
2832 case WebAssemblyISD::SWIZZLE: return fastEmit_WebAssemblyISD_SWIZZLE_rr(VT, RetVT, Op0, Op1);
2833 default: return Register();
2834 }
2835}
2836
2837// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2838
2839Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(MVT RetVT, Register Op0, uint64_t imm1) {
2840 if (RetVT.SimpleTy != MVT::i32)
2841 return Register();
2842 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I8x16_u, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2843}
2844
2845Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2846 switch (VT.SimpleTy) {
2847 case MVT::v16i8: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(RetVT, Op0, imm1);
2848 default: return Register();
2849 }
2850}
2851
2852// Top-level FastEmit function.
2853
2854Register fastEmit_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2855 switch (Opcode) {
2856 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(VT, RetVT, Op0, imm1);
2857 default: return Register();
2858 }
2859}
2860
2861// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2862
2863Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(MVT RetVT, Register Op0, uint64_t imm1) {
2864 if (RetVT.SimpleTy != MVT::i32)
2865 return Register();
2866 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I16x8_u, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2867}
2868
2869Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2870 switch (VT.SimpleTy) {
2871 case MVT::v8i16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(RetVT, Op0, imm1);
2872 default: return Register();
2873 }
2874}
2875
2876// Top-level FastEmit function.
2877
2878Register fastEmit_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2879 switch (Opcode) {
2880 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(VT, RetVT, Op0, imm1);
2881 default: return Register();
2882 }
2883}
2884
2885// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2886
2887Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(MVT RetVT, Register Op0, uint64_t imm1) {
2888 if (RetVT.SimpleTy != MVT::i32)
2889 return Register();
2890 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I32x4, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2891}
2892
2893Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(MVT RetVT, Register Op0, uint64_t imm1) {
2894 if (RetVT.SimpleTy != MVT::f32)
2895 return Register();
2896 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_F32x4, RC: &WebAssembly::F32RegClass, Op0, Imm: imm1);
2897}
2898
2899Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2900 switch (VT.SimpleTy) {
2901 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(RetVT, Op0, imm1);
2902 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(RetVT, Op0, imm1);
2903 default: return Register();
2904 }
2905}
2906
2907// Top-level FastEmit function.
2908
2909Register fastEmit_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2910 switch (Opcode) {
2911 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(VT, RetVT, Op0, imm1);
2912 default: return Register();
2913 }
2914}
2915
2916// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2917
2918Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(MVT RetVT, Register Op0, uint64_t imm1) {
2919 if (RetVT.SimpleTy != MVT::i64)
2920 return Register();
2921 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I64x2, RC: &WebAssembly::I64RegClass, Op0, Imm: imm1);
2922}
2923
2924Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(MVT RetVT, Register Op0, uint64_t imm1) {
2925 if (RetVT.SimpleTy != MVT::f64)
2926 return Register();
2927 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_F64x2, RC: &WebAssembly::F64RegClass, Op0, Imm: imm1);
2928}
2929
2930Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2931 switch (VT.SimpleTy) {
2932 case MVT::v2i64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(RetVT, Op0, imm1);
2933 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(RetVT, Op0, imm1);
2934 default: return Register();
2935 }
2936}
2937
2938// Top-level FastEmit function.
2939
2940Register fastEmit_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2941 switch (Opcode) {
2942 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(VT, RetVT, Op0, imm1);
2943 default: return Register();
2944 }
2945}
2946
2947// FastEmit functions for ISD::ConstantFP.
2948
2949Register fastEmit_ISD_ConstantFP_MVT_f32_f(MVT RetVT, const ConstantFP *f0) {
2950 if (RetVT.SimpleTy != MVT::f32)
2951 return Register();
2952 return fastEmitInst_f(MachineInstOpcode: WebAssembly::CONST_F32, RC: &WebAssembly::F32RegClass, FPImm: f0);
2953}
2954
2955Register fastEmit_ISD_ConstantFP_MVT_f64_f(MVT RetVT, const ConstantFP *f0) {
2956 if (RetVT.SimpleTy != MVT::f64)
2957 return Register();
2958 return fastEmitInst_f(MachineInstOpcode: WebAssembly::CONST_F64, RC: &WebAssembly::F64RegClass, FPImm: f0);
2959}
2960
2961Register fastEmit_ISD_ConstantFP_f(MVT VT, MVT RetVT, const ConstantFP *f0) {
2962 switch (VT.SimpleTy) {
2963 case MVT::f32: return fastEmit_ISD_ConstantFP_MVT_f32_f(RetVT, f0);
2964 case MVT::f64: return fastEmit_ISD_ConstantFP_MVT_f64_f(RetVT, f0);
2965 default: return Register();
2966 }
2967}
2968
2969// Top-level FastEmit function.
2970
2971Register fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *f0) override {
2972 switch (Opcode) {
2973 case ISD::ConstantFP: return fastEmit_ISD_ConstantFP_f(VT, RetVT, f0);
2974 default: return Register();
2975 }
2976}
2977
2978// FastEmit functions for ISD::Constant.
2979
2980Register fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
2981 if (RetVT.SimpleTy != MVT::i32)
2982 return Register();
2983 return fastEmitInst_i(MachineInstOpcode: WebAssembly::CONST_I32, RC: &WebAssembly::I32RegClass, Imm: imm0);
2984}
2985
2986Register fastEmit_ISD_Constant_MVT_i64_i(MVT RetVT, uint64_t imm0) {
2987 if (RetVT.SimpleTy != MVT::i64)
2988 return Register();
2989 return fastEmitInst_i(MachineInstOpcode: WebAssembly::CONST_I64, RC: &WebAssembly::I64RegClass, Imm: imm0);
2990}
2991
2992Register fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
2993 switch (VT.SimpleTy) {
2994 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
2995 case MVT::i64: return fastEmit_ISD_Constant_MVT_i64_i(RetVT, imm0);
2996 default: return Register();
2997 }
2998}
2999
3000// Top-level FastEmit function.
3001
3002Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
3003 switch (Opcode) {
3004 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
3005 default: return Register();
3006 }
3007}
3008
3009