1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the WebAssembly target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_ImmI8(int64_t Imm) {
12return -(1 << (8 - 1)) <= Imm && Imm < (1 << 8);
13}
14static bool Predicate_ImmI16(int64_t Imm) {
15return -(1 << (16 - 1)) <= Imm && Imm < (1 << 16);
16}
17static bool Predicate_LaneIdx32(int64_t Imm) {
18return 0 <= Imm && Imm < 32;
19}
20static bool Predicate_LaneIdx16(int64_t Imm) {
21return 0 <= Imm && Imm < 16;
22}
23static bool Predicate_LaneIdx8(int64_t Imm) {
24return 0 <= Imm && Imm < 8;
25}
26static bool Predicate_LaneIdx4(int64_t Imm) {
27return 0 <= Imm && Imm < 4;
28}
29static bool Predicate_LaneIdx2(int64_t Imm) {
30return 0 <= Imm && Imm < 2;
31}
32
33
34// FastEmit functions for ISD::ABS.
35
36Register fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, Register Op0) {
37 if (RetVT.SimpleTy != MVT::v16i8)
38 return Register();
39 if ((Subtarget->hasSIMD128())) {
40 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I8x16, RC: &WebAssembly::V128RegClass, Op0);
41 }
42 return Register();
43}
44
45Register fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, Register Op0) {
46 if (RetVT.SimpleTy != MVT::v8i16)
47 return Register();
48 if ((Subtarget->hasSIMD128())) {
49 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I16x8, RC: &WebAssembly::V128RegClass, Op0);
50 }
51 return Register();
52}
53
54Register fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, Register Op0) {
55 if (RetVT.SimpleTy != MVT::v4i32)
56 return Register();
57 if ((Subtarget->hasSIMD128())) {
58 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I32x4, RC: &WebAssembly::V128RegClass, Op0);
59 }
60 return Register();
61}
62
63Register fastEmit_ISD_ABS_MVT_v2i64_r(MVT RetVT, Register Op0) {
64 if (RetVT.SimpleTy != MVT::v2i64)
65 return Register();
66 if ((Subtarget->hasSIMD128())) {
67 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I64x2, RC: &WebAssembly::V128RegClass, Op0);
68 }
69 return Register();
70}
71
72Register fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, Register Op0) {
73 switch (VT.SimpleTy) {
74 case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0);
75 case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0);
76 case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0);
77 case MVT::v2i64: return fastEmit_ISD_ABS_MVT_v2i64_r(RetVT, Op0);
78 default: return Register();
79 }
80}
81
82// FastEmit functions for ISD::ANY_EXTEND.
83
84Register fastEmit_ISD_ANY_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
85 if (RetVT.SimpleTy != MVT::i64)
86 return Register();
87 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_U_I32, RC: &WebAssembly::I64RegClass, Op0);
88}
89
90Register fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
91 switch (VT.SimpleTy) {
92 case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i32_r(RetVT, Op0);
93 default: return Register();
94 }
95}
96
97// FastEmit functions for ISD::BITCAST.
98
99Register fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, Register Op0) {
100 if (RetVT.SimpleTy != MVT::f32)
101 return Register();
102 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_REINTERPRET_I32, RC: &WebAssembly::F32RegClass, Op0);
103}
104
105Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
106 if (RetVT.SimpleTy != MVT::f64)
107 return Register();
108 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_REINTERPRET_I64, RC: &WebAssembly::F64RegClass, Op0);
109}
110
111Register fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, Register Op0) {
112 if (RetVT.SimpleTy != MVT::i32)
113 return Register();
114 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_REINTERPRET_F32, RC: &WebAssembly::I32RegClass, Op0);
115}
116
117Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
118 if (RetVT.SimpleTy != MVT::i64)
119 return Register();
120 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_REINTERPRET_F64, RC: &WebAssembly::I64RegClass, Op0);
121}
122
123Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
124 switch (VT.SimpleTy) {
125 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
126 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
127 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
128 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
129 default: return Register();
130 }
131}
132
133// FastEmit functions for ISD::CTLZ.
134
135Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
136 if (RetVT.SimpleTy != MVT::i32)
137 return Register();
138 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CLZ_I32, RC: &WebAssembly::I32RegClass, Op0);
139}
140
141Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
142 if (RetVT.SimpleTy != MVT::i64)
143 return Register();
144 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CLZ_I64, RC: &WebAssembly::I64RegClass, Op0);
145}
146
147Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
148 switch (VT.SimpleTy) {
149 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
150 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
151 default: return Register();
152 }
153}
154
155// FastEmit functions for ISD::CTPOP.
156
157Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
158 if (RetVT.SimpleTy != MVT::i32)
159 return Register();
160 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I32, RC: &WebAssembly::I32RegClass, Op0);
161}
162
163Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
164 if (RetVT.SimpleTy != MVT::i64)
165 return Register();
166 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I64, RC: &WebAssembly::I64RegClass, Op0);
167}
168
169Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
170 if (RetVT.SimpleTy != MVT::v16i8)
171 return Register();
172 if ((Subtarget->hasSIMD128())) {
173 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
174 }
175 return Register();
176}
177
178Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
179 switch (VT.SimpleTy) {
180 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
181 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
182 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
183 default: return Register();
184 }
185}
186
187// FastEmit functions for ISD::CTTZ.
188
189Register fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, Register Op0) {
190 if (RetVT.SimpleTy != MVT::i32)
191 return Register();
192 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CTZ_I32, RC: &WebAssembly::I32RegClass, Op0);
193}
194
195Register fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, Register Op0) {
196 if (RetVT.SimpleTy != MVT::i64)
197 return Register();
198 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CTZ_I64, RC: &WebAssembly::I64RegClass, Op0);
199}
200
201Register fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, Register Op0) {
202 switch (VT.SimpleTy) {
203 case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0);
204 case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0);
205 default: return Register();
206 }
207}
208
209// FastEmit functions for ISD::FABS.
210
211Register fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, Register Op0) {
212 if (RetVT.SimpleTy != MVT::f32)
213 return Register();
214 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F32, RC: &WebAssembly::F32RegClass, Op0);
215}
216
217Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
218 if (RetVT.SimpleTy != MVT::f64)
219 return Register();
220 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F64, RC: &WebAssembly::F64RegClass, Op0);
221}
222
223Register fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, Register Op0) {
224 if (RetVT.SimpleTy != MVT::v8f16)
225 return Register();
226 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
227 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F16x8, RC: &WebAssembly::V128RegClass, Op0);
228 }
229 return Register();
230}
231
232Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
233 if (RetVT.SimpleTy != MVT::v4f32)
234 return Register();
235 if ((Subtarget->hasSIMD128())) {
236 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F32x4, RC: &WebAssembly::V128RegClass, Op0);
237 }
238 return Register();
239}
240
241Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
242 if (RetVT.SimpleTy != MVT::v2f64)
243 return Register();
244 if ((Subtarget->hasSIMD128())) {
245 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F64x2, RC: &WebAssembly::V128RegClass, Op0);
246 }
247 return Register();
248}
249
250Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
251 switch (VT.SimpleTy) {
252 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
253 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
254 case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0);
255 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
256 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
257 default: return Register();
258 }
259}
260
261// FastEmit functions for ISD::FCEIL.
262
263Register fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, Register Op0) {
264 if (RetVT.SimpleTy != MVT::f32)
265 return Register();
266 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F32, RC: &WebAssembly::F32RegClass, Op0);
267}
268
269Register fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, Register Op0) {
270 if (RetVT.SimpleTy != MVT::f64)
271 return Register();
272 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F64, RC: &WebAssembly::F64RegClass, Op0);
273}
274
275Register fastEmit_ISD_FCEIL_MVT_v8f16_r(MVT RetVT, Register Op0) {
276 if (RetVT.SimpleTy != MVT::v8f16)
277 return Register();
278 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
279 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F16x8, RC: &WebAssembly::V128RegClass, Op0);
280 }
281 return Register();
282}
283
284Register fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, Register Op0) {
285 if (RetVT.SimpleTy != MVT::v4f32)
286 return Register();
287 if ((Subtarget->hasSIMD128())) {
288 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F32x4, RC: &WebAssembly::V128RegClass, Op0);
289 }
290 return Register();
291}
292
293Register fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, Register Op0) {
294 if (RetVT.SimpleTy != MVT::v2f64)
295 return Register();
296 if ((Subtarget->hasSIMD128())) {
297 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F64x2, RC: &WebAssembly::V128RegClass, Op0);
298 }
299 return Register();
300}
301
302Register fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, Register Op0) {
303 switch (VT.SimpleTy) {
304 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0);
305 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0);
306 case MVT::v8f16: return fastEmit_ISD_FCEIL_MVT_v8f16_r(RetVT, Op0);
307 case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0);
308 case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0);
309 default: return Register();
310 }
311}
312
313// FastEmit functions for ISD::FFLOOR.
314
315Register fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, Register Op0) {
316 if (RetVT.SimpleTy != MVT::f32)
317 return Register();
318 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F32, RC: &WebAssembly::F32RegClass, Op0);
319}
320
321Register fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, Register Op0) {
322 if (RetVT.SimpleTy != MVT::f64)
323 return Register();
324 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F64, RC: &WebAssembly::F64RegClass, Op0);
325}
326
327Register fastEmit_ISD_FFLOOR_MVT_v8f16_r(MVT RetVT, Register Op0) {
328 if (RetVT.SimpleTy != MVT::v8f16)
329 return Register();
330 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
331 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F16x8, RC: &WebAssembly::V128RegClass, Op0);
332 }
333 return Register();
334}
335
336Register fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, Register Op0) {
337 if (RetVT.SimpleTy != MVT::v4f32)
338 return Register();
339 if ((Subtarget->hasSIMD128())) {
340 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F32x4, RC: &WebAssembly::V128RegClass, Op0);
341 }
342 return Register();
343}
344
345Register fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, Register Op0) {
346 if (RetVT.SimpleTy != MVT::v2f64)
347 return Register();
348 if ((Subtarget->hasSIMD128())) {
349 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F64x2, RC: &WebAssembly::V128RegClass, Op0);
350 }
351 return Register();
352}
353
354Register fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, Register Op0) {
355 switch (VT.SimpleTy) {
356 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0);
357 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0);
358 case MVT::v8f16: return fastEmit_ISD_FFLOOR_MVT_v8f16_r(RetVT, Op0);
359 case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0);
360 case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0);
361 default: return Register();
362 }
363}
364
365// FastEmit functions for ISD::FNEARBYINT.
366
367Register fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, Register Op0) {
368 if (RetVT.SimpleTy != MVT::f32)
369 return Register();
370 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
371}
372
373Register fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, Register Op0) {
374 if (RetVT.SimpleTy != MVT::f64)
375 return Register();
376 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
377}
378
379Register fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
380 if (RetVT.SimpleTy != MVT::v8f16)
381 return Register();
382 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
383 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
384 }
385 return Register();
386}
387
388Register fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
389 if (RetVT.SimpleTy != MVT::v4f32)
390 return Register();
391 if ((Subtarget->hasSIMD128())) {
392 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
393 }
394 return Register();
395}
396
397Register fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
398 if (RetVT.SimpleTy != MVT::v2f64)
399 return Register();
400 if ((Subtarget->hasSIMD128())) {
401 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
402 }
403 return Register();
404}
405
406Register fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, Register Op0) {
407 switch (VT.SimpleTy) {
408 case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0);
409 case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0);
410 case MVT::v8f16: return fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(RetVT, Op0);
411 case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0);
412 case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0);
413 default: return Register();
414 }
415}
416
417// FastEmit functions for ISD::FNEG.
418
419Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
420 if (RetVT.SimpleTy != MVT::f32)
421 return Register();
422 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F32, RC: &WebAssembly::F32RegClass, Op0);
423}
424
425Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
426 if (RetVT.SimpleTy != MVT::f64)
427 return Register();
428 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F64, RC: &WebAssembly::F64RegClass, Op0);
429}
430
431Register fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, Register Op0) {
432 if (RetVT.SimpleTy != MVT::v8f16)
433 return Register();
434 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
435 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F16x8, RC: &WebAssembly::V128RegClass, Op0);
436 }
437 return Register();
438}
439
440Register fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, Register Op0) {
441 if (RetVT.SimpleTy != MVT::v4f32)
442 return Register();
443 if ((Subtarget->hasSIMD128())) {
444 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F32x4, RC: &WebAssembly::V128RegClass, Op0);
445 }
446 return Register();
447}
448
449Register fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, Register Op0) {
450 if (RetVT.SimpleTy != MVT::v2f64)
451 return Register();
452 if ((Subtarget->hasSIMD128())) {
453 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F64x2, RC: &WebAssembly::V128RegClass, Op0);
454 }
455 return Register();
456}
457
458Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
459 switch (VT.SimpleTy) {
460 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
461 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
462 case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0);
463 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0);
464 case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0);
465 default: return Register();
466 }
467}
468
469// FastEmit functions for ISD::FP_EXTEND.
470
471Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
472 if (RetVT.SimpleTy != MVT::f64)
473 return Register();
474 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_PROMOTE_F32, RC: &WebAssembly::F64RegClass, Op0);
475}
476
477Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
478 switch (VT.SimpleTy) {
479 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
480 default: return Register();
481 }
482}
483
484// FastEmit functions for ISD::FP_ROUND.
485
486Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
487 if (RetVT.SimpleTy != MVT::f32)
488 return Register();
489 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_DEMOTE_F64, RC: &WebAssembly::F32RegClass, Op0);
490}
491
492Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
493 switch (VT.SimpleTy) {
494 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
495 default: return Register();
496 }
497}
498
499// FastEmit functions for ISD::FP_TO_SINT.
500
501Register fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Register Op0) {
502 if ((!Subtarget->hasNontrappingFPToInt())) {
503 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I32_F32, RC: &WebAssembly::I32RegClass, Op0);
504 }
505 if ((Subtarget->hasNontrappingFPToInt())) {
506 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_S_SAT_F32, RC: &WebAssembly::I32RegClass, Op0);
507 }
508 return Register();
509}
510
511Register fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Register Op0) {
512 if ((!Subtarget->hasNontrappingFPToInt())) {
513 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I64_F32, RC: &WebAssembly::I64RegClass, Op0);
514 }
515 if ((Subtarget->hasNontrappingFPToInt())) {
516 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_S_SAT_F32, RC: &WebAssembly::I64RegClass, Op0);
517 }
518 return Register();
519}
520
521Register fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, Register Op0) {
522switch (RetVT.SimpleTy) {
523 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0);
524 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0);
525 default: return Register();
526}
527}
528
529Register fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Register Op0) {
530 if ((!Subtarget->hasNontrappingFPToInt())) {
531 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I32_F64, RC: &WebAssembly::I32RegClass, Op0);
532 }
533 if ((Subtarget->hasNontrappingFPToInt())) {
534 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_S_SAT_F64, RC: &WebAssembly::I32RegClass, Op0);
535 }
536 return Register();
537}
538
539Register fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Register Op0) {
540 if ((!Subtarget->hasNontrappingFPToInt())) {
541 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I64_F64, RC: &WebAssembly::I64RegClass, Op0);
542 }
543 if ((Subtarget->hasNontrappingFPToInt())) {
544 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_S_SAT_F64, RC: &WebAssembly::I64RegClass, Op0);
545 }
546 return Register();
547}
548
549Register fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, Register Op0) {
550switch (RetVT.SimpleTy) {
551 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0);
552 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0);
553 default: return Register();
554}
555}
556
557Register fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
558 if (RetVT.SimpleTy != MVT::v8i16)
559 return Register();
560 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
561 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_sint_I16x8, RC: &WebAssembly::V128RegClass, Op0);
562 }
563 return Register();
564}
565
566Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
567 if (RetVT.SimpleTy != MVT::v4i32)
568 return Register();
569 if ((Subtarget->hasSIMD128())) {
570 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_sint_I32x4, RC: &WebAssembly::V128RegClass, Op0);
571 }
572 return Register();
573}
574
575Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
576 switch (VT.SimpleTy) {
577 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
578 case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
579 case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0);
580 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
581 default: return Register();
582 }
583}
584
585// FastEmit functions for ISD::FP_TO_UINT.
586
587Register fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Register Op0) {
588 if ((!Subtarget->hasNontrappingFPToInt())) {
589 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I32_F32, RC: &WebAssembly::I32RegClass, Op0);
590 }
591 if ((Subtarget->hasNontrappingFPToInt())) {
592 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_U_SAT_F32, RC: &WebAssembly::I32RegClass, Op0);
593 }
594 return Register();
595}
596
597Register fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Register Op0) {
598 if ((!Subtarget->hasNontrappingFPToInt())) {
599 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I64_F32, RC: &WebAssembly::I64RegClass, Op0);
600 }
601 if ((Subtarget->hasNontrappingFPToInt())) {
602 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_U_SAT_F32, RC: &WebAssembly::I64RegClass, Op0);
603 }
604 return Register();
605}
606
607Register fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, Register Op0) {
608switch (RetVT.SimpleTy) {
609 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0);
610 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0);
611 default: return Register();
612}
613}
614
615Register fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Register Op0) {
616 if ((!Subtarget->hasNontrappingFPToInt())) {
617 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I32_F64, RC: &WebAssembly::I32RegClass, Op0);
618 }
619 if ((Subtarget->hasNontrappingFPToInt())) {
620 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_U_SAT_F64, RC: &WebAssembly::I32RegClass, Op0);
621 }
622 return Register();
623}
624
625Register fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Register Op0) {
626 if ((!Subtarget->hasNontrappingFPToInt())) {
627 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I64_F64, RC: &WebAssembly::I64RegClass, Op0);
628 }
629 if ((Subtarget->hasNontrappingFPToInt())) {
630 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_U_SAT_F64, RC: &WebAssembly::I64RegClass, Op0);
631 }
632 return Register();
633}
634
635Register fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, Register Op0) {
636switch (RetVT.SimpleTy) {
637 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0);
638 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0);
639 default: return Register();
640}
641}
642
643Register fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
644 if (RetVT.SimpleTy != MVT::v8i16)
645 return Register();
646 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
647 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_uint_I16x8, RC: &WebAssembly::V128RegClass, Op0);
648 }
649 return Register();
650}
651
652Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
653 if (RetVT.SimpleTy != MVT::v4i32)
654 return Register();
655 if ((Subtarget->hasSIMD128())) {
656 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_uint_I32x4, RC: &WebAssembly::V128RegClass, Op0);
657 }
658 return Register();
659}
660
661Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
662 switch (VT.SimpleTy) {
663 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
664 case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
665 case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0);
666 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
667 default: return Register();
668 }
669}
670
671// FastEmit functions for ISD::FRINT.
672
673Register fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, Register Op0) {
674 if (RetVT.SimpleTy != MVT::f32)
675 return Register();
676 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
677}
678
679Register fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, Register Op0) {
680 if (RetVT.SimpleTy != MVT::f64)
681 return Register();
682 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
683}
684
685Register fastEmit_ISD_FRINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
686 if (RetVT.SimpleTy != MVT::v8f16)
687 return Register();
688 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
689}
690
691Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
692 if (RetVT.SimpleTy != MVT::v4f32)
693 return Register();
694 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
695}
696
697Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
698 if (RetVT.SimpleTy != MVT::v2f64)
699 return Register();
700 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
701}
702
703Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
704 switch (VT.SimpleTy) {
705 case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0);
706 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0);
707 case MVT::v8f16: return fastEmit_ISD_FRINT_MVT_v8f16_r(RetVT, Op0);
708 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
709 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
710 default: return Register();
711 }
712}
713
714// FastEmit functions for ISD::FROUNDEVEN.
715
716Register fastEmit_ISD_FROUNDEVEN_MVT_f32_r(MVT RetVT, Register Op0) {
717 if (RetVT.SimpleTy != MVT::f32)
718 return Register();
719 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
720}
721
722Register fastEmit_ISD_FROUNDEVEN_MVT_f64_r(MVT RetVT, Register Op0) {
723 if (RetVT.SimpleTy != MVT::f64)
724 return Register();
725 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
726}
727
728Register fastEmit_ISD_FROUNDEVEN_MVT_v8f16_r(MVT RetVT, Register Op0) {
729 if (RetVT.SimpleTy != MVT::v8f16)
730 return Register();
731 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
732}
733
734Register fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(MVT RetVT, Register Op0) {
735 if (RetVT.SimpleTy != MVT::v4f32)
736 return Register();
737 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
738}
739
740Register fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(MVT RetVT, Register Op0) {
741 if (RetVT.SimpleTy != MVT::v2f64)
742 return Register();
743 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
744}
745
746Register fastEmit_ISD_FROUNDEVEN_r(MVT VT, MVT RetVT, Register Op0) {
747 switch (VT.SimpleTy) {
748 case MVT::f32: return fastEmit_ISD_FROUNDEVEN_MVT_f32_r(RetVT, Op0);
749 case MVT::f64: return fastEmit_ISD_FROUNDEVEN_MVT_f64_r(RetVT, Op0);
750 case MVT::v8f16: return fastEmit_ISD_FROUNDEVEN_MVT_v8f16_r(RetVT, Op0);
751 case MVT::v4f32: return fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(RetVT, Op0);
752 case MVT::v2f64: return fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(RetVT, Op0);
753 default: return Register();
754 }
755}
756
757// FastEmit functions for ISD::FSQRT.
758
759Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
760 if (RetVT.SimpleTy != MVT::f32)
761 return Register();
762 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F32, RC: &WebAssembly::F32RegClass, Op0);
763}
764
765Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
766 if (RetVT.SimpleTy != MVT::f64)
767 return Register();
768 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F64, RC: &WebAssembly::F64RegClass, Op0);
769}
770
771Register fastEmit_ISD_FSQRT_MVT_v8f16_r(MVT RetVT, Register Op0) {
772 if (RetVT.SimpleTy != MVT::v8f16)
773 return Register();
774 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
775 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F16x8, RC: &WebAssembly::V128RegClass, Op0);
776 }
777 return Register();
778}
779
780Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
781 if (RetVT.SimpleTy != MVT::v4f32)
782 return Register();
783 if ((Subtarget->hasSIMD128())) {
784 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
785 }
786 return Register();
787}
788
789Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
790 if (RetVT.SimpleTy != MVT::v2f64)
791 return Register();
792 if ((Subtarget->hasSIMD128())) {
793 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
794 }
795 return Register();
796}
797
798Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
799 switch (VT.SimpleTy) {
800 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
801 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
802 case MVT::v8f16: return fastEmit_ISD_FSQRT_MVT_v8f16_r(RetVT, Op0);
803 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
804 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
805 default: return Register();
806 }
807}
808
809// FastEmit functions for ISD::FTRUNC.
810
811Register fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, Register Op0) {
812 if (RetVT.SimpleTy != MVT::f32)
813 return Register();
814 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F32, RC: &WebAssembly::F32RegClass, Op0);
815}
816
817Register fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, Register Op0) {
818 if (RetVT.SimpleTy != MVT::f64)
819 return Register();
820 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F64, RC: &WebAssembly::F64RegClass, Op0);
821}
822
823Register fastEmit_ISD_FTRUNC_MVT_v8f16_r(MVT RetVT, Register Op0) {
824 if (RetVT.SimpleTy != MVT::v8f16)
825 return Register();
826 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
827 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F16x8, RC: &WebAssembly::V128RegClass, Op0);
828 }
829 return Register();
830}
831
832Register fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, Register Op0) {
833 if (RetVT.SimpleTy != MVT::v4f32)
834 return Register();
835 if ((Subtarget->hasSIMD128())) {
836 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F32x4, RC: &WebAssembly::V128RegClass, Op0);
837 }
838 return Register();
839}
840
841Register fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, Register Op0) {
842 if (RetVT.SimpleTy != MVT::v2f64)
843 return Register();
844 if ((Subtarget->hasSIMD128())) {
845 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F64x2, RC: &WebAssembly::V128RegClass, Op0);
846 }
847 return Register();
848}
849
850Register fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, Register Op0) {
851 switch (VT.SimpleTy) {
852 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0);
853 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0);
854 case MVT::v8f16: return fastEmit_ISD_FTRUNC_MVT_v8f16_r(RetVT, Op0);
855 case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0);
856 case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0);
857 default: return Register();
858 }
859}
860
861// FastEmit functions for ISD::SCALAR_TO_VECTOR.
862
863Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v16i8_r(Register Op0) {
864 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
865}
866
867Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v8i16_r(Register Op0) {
868 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I16x8, RC: &WebAssembly::V128RegClass, Op0);
869}
870
871Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(Register Op0) {
872 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I32x4, RC: &WebAssembly::V128RegClass, Op0);
873}
874
875Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, Register Op0) {
876switch (RetVT.SimpleTy) {
877 case MVT::v16i8: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v16i8_r(Op0);
878 case MVT::v8i16: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v8i16_r(Op0);
879 case MVT::v4i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(Op0);
880 default: return Register();
881}
882}
883
884Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(MVT RetVT, Register Op0) {
885 if (RetVT.SimpleTy != MVT::v2i64)
886 return Register();
887 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I64x2, RC: &WebAssembly::V128RegClass, Op0);
888}
889
890Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, Register Op0) {
891 if (RetVT.SimpleTy != MVT::v4f32)
892 return Register();
893 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
894}
895
896Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(MVT RetVT, Register Op0) {
897 if (RetVT.SimpleTy != MVT::v2f64)
898 return Register();
899 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
900}
901
902Register fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, Register Op0) {
903 switch (VT.SimpleTy) {
904 case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0);
905 case MVT::i64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(RetVT, Op0);
906 case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0);
907 case MVT::f64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(RetVT, Op0);
908 default: return Register();
909 }
910}
911
912// FastEmit functions for ISD::SIGN_EXTEND.
913
914Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
915 if (RetVT.SimpleTy != MVT::i64)
916 return Register();
917 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_S_I32, RC: &WebAssembly::I64RegClass, Op0);
918}
919
920Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
921 switch (VT.SimpleTy) {
922 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
923 default: return Register();
924 }
925}
926
927// FastEmit functions for ISD::SINT_TO_FP.
928
929Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
930 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_S_I32, RC: &WebAssembly::F32RegClass, Op0);
931}
932
933Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
934 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_S_I32, RC: &WebAssembly::F64RegClass, Op0);
935}
936
937Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
938switch (RetVT.SimpleTy) {
939 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
940 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
941 default: return Register();
942}
943}
944
945Register fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Register Op0) {
946 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_S_I64, RC: &WebAssembly::F32RegClass, Op0);
947}
948
949Register fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Register Op0) {
950 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_S_I64, RC: &WebAssembly::F64RegClass, Op0);
951}
952
953Register fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
954switch (RetVT.SimpleTy) {
955 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0);
956 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0);
957 default: return Register();
958}
959}
960
961Register fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, Register Op0) {
962 if (RetVT.SimpleTy != MVT::v8f16)
963 return Register();
964 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
965 return fastEmitInst_r(MachineInstOpcode: WebAssembly::sint_to_fp_F16x8, RC: &WebAssembly::V128RegClass, Op0);
966 }
967 return Register();
968}
969
970Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
971 if (RetVT.SimpleTy != MVT::v4f32)
972 return Register();
973 if ((Subtarget->hasSIMD128())) {
974 return fastEmitInst_r(MachineInstOpcode: WebAssembly::sint_to_fp_F32x4, RC: &WebAssembly::V128RegClass, Op0);
975 }
976 return Register();
977}
978
979Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
980 switch (VT.SimpleTy) {
981 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
982 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
983 case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0);
984 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
985 default: return Register();
986 }
987}
988
989// FastEmit functions for ISD::SPLAT_VECTOR.
990
991Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v16i8_r(Register Op0) {
992 if ((Subtarget->hasSIMD128())) {
993 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
994 }
995 return Register();
996}
997
998Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v8i16_r(Register Op0) {
999 if ((Subtarget->hasSIMD128())) {
1000 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1001 }
1002 return Register();
1003}
1004
1005Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v4i32_r(Register Op0) {
1006 if ((Subtarget->hasSIMD128())) {
1007 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1008 }
1009 return Register();
1010}
1011
1012Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(MVT RetVT, Register Op0) {
1013switch (RetVT.SimpleTy) {
1014 case MVT::v16i8: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v16i8_r(Op0);
1015 case MVT::v8i16: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v8i16_r(Op0);
1016 case MVT::v4i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v4i32_r(Op0);
1017 default: return Register();
1018}
1019}
1020
1021Register fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(MVT RetVT, Register Op0) {
1022 if (RetVT.SimpleTy != MVT::v2i64)
1023 return Register();
1024 if ((Subtarget->hasSIMD128())) {
1025 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1026 }
1027 return Register();
1028}
1029
1030Register fastEmit_ISD_SPLAT_VECTOR_MVT_f32_r(MVT RetVT, Register Op0) {
1031 if (RetVT.SimpleTy != MVT::v4f32)
1032 return Register();
1033 if ((Subtarget->hasSIMD128())) {
1034 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1035 }
1036 return Register();
1037}
1038
1039Register fastEmit_ISD_SPLAT_VECTOR_MVT_f64_r(MVT RetVT, Register Op0) {
1040 if (RetVT.SimpleTy != MVT::v2f64)
1041 return Register();
1042 if ((Subtarget->hasSIMD128())) {
1043 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1044 }
1045 return Register();
1046}
1047
1048Register fastEmit_ISD_SPLAT_VECTOR_r(MVT VT, MVT RetVT, Register Op0) {
1049 switch (VT.SimpleTy) {
1050 case MVT::i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(RetVT, Op0);
1051 case MVT::i64: return fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(RetVT, Op0);
1052 case MVT::f32: return fastEmit_ISD_SPLAT_VECTOR_MVT_f32_r(RetVT, Op0);
1053 case MVT::f64: return fastEmit_ISD_SPLAT_VECTOR_MVT_f64_r(RetVT, Op0);
1054 default: return Register();
1055 }
1056}
1057
1058// FastEmit functions for ISD::TRUNCATE.
1059
1060Register fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, Register Op0) {
1061 if (RetVT.SimpleTy != MVT::i32)
1062 return Register();
1063 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_WRAP_I64, RC: &WebAssembly::I32RegClass, Op0);
1064}
1065
1066Register fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, Register Op0) {
1067 switch (VT.SimpleTy) {
1068 case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0);
1069 default: return Register();
1070 }
1071}
1072
1073// FastEmit functions for ISD::UINT_TO_FP.
1074
1075Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1076 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_U_I32, RC: &WebAssembly::F32RegClass, Op0);
1077}
1078
1079Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1080 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_U_I32, RC: &WebAssembly::F64RegClass, Op0);
1081}
1082
1083Register fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1084switch (RetVT.SimpleTy) {
1085 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1086 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1087 default: return Register();
1088}
1089}
1090
1091Register fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Register Op0) {
1092 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_U_I64, RC: &WebAssembly::F32RegClass, Op0);
1093}
1094
1095Register fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Register Op0) {
1096 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_U_I64, RC: &WebAssembly::F64RegClass, Op0);
1097}
1098
1099Register fastEmit_ISD_UINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
1100switch (RetVT.SimpleTy) {
1101 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0);
1102 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Op0);
1103 default: return Register();
1104}
1105}
1106
1107Register fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, Register Op0) {
1108 if (RetVT.SimpleTy != MVT::v8f16)
1109 return Register();
1110 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1111 return fastEmitInst_r(MachineInstOpcode: WebAssembly::uint_to_fp_F16x8, RC: &WebAssembly::V128RegClass, Op0);
1112 }
1113 return Register();
1114}
1115
1116Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1117 if (RetVT.SimpleTy != MVT::v4f32)
1118 return Register();
1119 if ((Subtarget->hasSIMD128())) {
1120 return fastEmitInst_r(MachineInstOpcode: WebAssembly::uint_to_fp_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1121 }
1122 return Register();
1123}
1124
1125Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1126 switch (VT.SimpleTy) {
1127 case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1128 case MVT::i64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_r(RetVT, Op0);
1129 case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0);
1130 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1131 default: return Register();
1132 }
1133}
1134
1135// FastEmit functions for ISD::ZERO_EXTEND.
1136
1137Register fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
1138 if (RetVT.SimpleTy != MVT::i64)
1139 return Register();
1140 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_U_I32, RC: &WebAssembly::I64RegClass, Op0);
1141}
1142
1143Register fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
1144 switch (VT.SimpleTy) {
1145 case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(RetVT, Op0);
1146 default: return Register();
1147 }
1148}
1149
1150// FastEmit functions for WebAssemblyISD::BR_TABLE.
1151
1152Register fastEmit_WebAssemblyISD_BR_TABLE_MVT_i32_r(MVT RetVT, Register Op0) {
1153 if (RetVT.SimpleTy != MVT::isVoid)
1154 return Register();
1155 return fastEmitInst_r(MachineInstOpcode: WebAssembly::BR_TABLE_I32, RC: &WebAssembly::I32RegClass, Op0);
1156}
1157
1158Register fastEmit_WebAssemblyISD_BR_TABLE_MVT_i64_r(MVT RetVT, Register Op0) {
1159 if (RetVT.SimpleTy != MVT::isVoid)
1160 return Register();
1161 return fastEmitInst_r(MachineInstOpcode: WebAssembly::BR_TABLE_I64, RC: &WebAssembly::I64RegClass, Op0);
1162}
1163
1164Register fastEmit_WebAssemblyISD_BR_TABLE_r(MVT VT, MVT RetVT, Register Op0) {
1165 switch (VT.SimpleTy) {
1166 case MVT::i32: return fastEmit_WebAssemblyISD_BR_TABLE_MVT_i32_r(RetVT, Op0);
1167 case MVT::i64: return fastEmit_WebAssemblyISD_BR_TABLE_MVT_i64_r(RetVT, Op0);
1168 default: return Register();
1169 }
1170}
1171
1172// FastEmit functions for WebAssemblyISD::CONVERT_LOW_S.
1173
1174Register fastEmit_WebAssemblyISD_CONVERT_LOW_S_MVT_v4i32_r(MVT RetVT, Register Op0) {
1175 if (RetVT.SimpleTy != MVT::v2f64)
1176 return Register();
1177 if ((Subtarget->hasSIMD128())) {
1178 return fastEmitInst_r(MachineInstOpcode: WebAssembly::convert_low_s_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1179 }
1180 return Register();
1181}
1182
1183Register fastEmit_WebAssemblyISD_CONVERT_LOW_S_r(MVT VT, MVT RetVT, Register Op0) {
1184 switch (VT.SimpleTy) {
1185 case MVT::v4i32: return fastEmit_WebAssemblyISD_CONVERT_LOW_S_MVT_v4i32_r(RetVT, Op0);
1186 default: return Register();
1187 }
1188}
1189
1190// FastEmit functions for WebAssemblyISD::CONVERT_LOW_U.
1191
1192Register fastEmit_WebAssemblyISD_CONVERT_LOW_U_MVT_v4i32_r(MVT RetVT, Register Op0) {
1193 if (RetVT.SimpleTy != MVT::v2f64)
1194 return Register();
1195 if ((Subtarget->hasSIMD128())) {
1196 return fastEmitInst_r(MachineInstOpcode: WebAssembly::convert_low_u_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1197 }
1198 return Register();
1199}
1200
1201Register fastEmit_WebAssemblyISD_CONVERT_LOW_U_r(MVT VT, MVT RetVT, Register Op0) {
1202 switch (VT.SimpleTy) {
1203 case MVT::v4i32: return fastEmit_WebAssemblyISD_CONVERT_LOW_U_MVT_v4i32_r(RetVT, Op0);
1204 default: return Register();
1205 }
1206}
1207
1208// FastEmit functions for WebAssemblyISD::DEMOTE_ZERO.
1209
1210Register fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v4f32_r(MVT RetVT, Register Op0) {
1211 if (RetVT.SimpleTy != MVT::v8f16)
1212 return Register();
1213 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1214 return fastEmitInst_r(MachineInstOpcode: WebAssembly::demote_zero_F16x8, RC: &WebAssembly::V128RegClass, Op0);
1215 }
1216 return Register();
1217}
1218
1219Register fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v2f64_r(MVT RetVT, Register Op0) {
1220 if (RetVT.SimpleTy != MVT::v4f32)
1221 return Register();
1222 if ((Subtarget->hasSIMD128())) {
1223 return fastEmitInst_r(MachineInstOpcode: WebAssembly::demote_zero_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1224 }
1225 return Register();
1226}
1227
1228Register fastEmit_WebAssemblyISD_DEMOTE_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1229 switch (VT.SimpleTy) {
1230 case MVT::v4f32: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v4f32_r(RetVT, Op0);
1231 case MVT::v2f64: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v2f64_r(RetVT, Op0);
1232 default: return Register();
1233 }
1234}
1235
1236// FastEmit functions for WebAssemblyISD::EXTEND_HIGH_S.
1237
1238Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v16i8_r(MVT RetVT, Register Op0) {
1239 if (RetVT.SimpleTy != MVT::v8i16)
1240 return Register();
1241 if ((Subtarget->hasSIMD128())) {
1242 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1243 }
1244 return Register();
1245}
1246
1247Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v8i16_r(MVT RetVT, Register Op0) {
1248 if (RetVT.SimpleTy != MVT::v4i32)
1249 return Register();
1250 if ((Subtarget->hasSIMD128())) {
1251 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1252 }
1253 return Register();
1254}
1255
1256Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v4i32_r(MVT RetVT, Register Op0) {
1257 if (RetVT.SimpleTy != MVT::v2i64)
1258 return Register();
1259 if ((Subtarget->hasSIMD128())) {
1260 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1261 }
1262 return Register();
1263}
1264
1265Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_r(MVT VT, MVT RetVT, Register Op0) {
1266 switch (VT.SimpleTy) {
1267 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v16i8_r(RetVT, Op0);
1268 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v8i16_r(RetVT, Op0);
1269 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v4i32_r(RetVT, Op0);
1270 default: return Register();
1271 }
1272}
1273
1274// FastEmit functions for WebAssemblyISD::EXTEND_HIGH_U.
1275
1276Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v16i8_r(MVT RetVT, Register Op0) {
1277 if (RetVT.SimpleTy != MVT::v8i16)
1278 return Register();
1279 if ((Subtarget->hasSIMD128())) {
1280 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1281 }
1282 return Register();
1283}
1284
1285Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v8i16_r(MVT RetVT, Register Op0) {
1286 if (RetVT.SimpleTy != MVT::v4i32)
1287 return Register();
1288 if ((Subtarget->hasSIMD128())) {
1289 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1290 }
1291 return Register();
1292}
1293
1294Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v4i32_r(MVT RetVT, Register Op0) {
1295 if (RetVT.SimpleTy != MVT::v2i64)
1296 return Register();
1297 if ((Subtarget->hasSIMD128())) {
1298 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1299 }
1300 return Register();
1301}
1302
1303Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_r(MVT VT, MVT RetVT, Register Op0) {
1304 switch (VT.SimpleTy) {
1305 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v16i8_r(RetVT, Op0);
1306 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v8i16_r(RetVT, Op0);
1307 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v4i32_r(RetVT, Op0);
1308 default: return Register();
1309 }
1310}
1311
1312// FastEmit functions for WebAssemblyISD::EXTEND_LOW_S.
1313
1314Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v16i8_r(MVT RetVT, Register Op0) {
1315 if (RetVT.SimpleTy != MVT::v8i16)
1316 return Register();
1317 if ((Subtarget->hasSIMD128())) {
1318 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1319 }
1320 return Register();
1321}
1322
1323Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v8i16_r(MVT RetVT, Register Op0) {
1324 if (RetVT.SimpleTy != MVT::v4i32)
1325 return Register();
1326 if ((Subtarget->hasSIMD128())) {
1327 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1328 }
1329 return Register();
1330}
1331
1332Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v4i32_r(MVT RetVT, Register Op0) {
1333 if (RetVT.SimpleTy != MVT::v2i64)
1334 return Register();
1335 if ((Subtarget->hasSIMD128())) {
1336 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1337 }
1338 return Register();
1339}
1340
1341Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_r(MVT VT, MVT RetVT, Register Op0) {
1342 switch (VT.SimpleTy) {
1343 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v16i8_r(RetVT, Op0);
1344 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v8i16_r(RetVT, Op0);
1345 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v4i32_r(RetVT, Op0);
1346 default: return Register();
1347 }
1348}
1349
1350// FastEmit functions for WebAssemblyISD::EXTEND_LOW_U.
1351
1352Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v16i8_r(MVT RetVT, Register Op0) {
1353 if (RetVT.SimpleTy != MVT::v8i16)
1354 return Register();
1355 if ((Subtarget->hasSIMD128())) {
1356 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1357 }
1358 return Register();
1359}
1360
1361Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v8i16_r(MVT RetVT, Register Op0) {
1362 if (RetVT.SimpleTy != MVT::v4i32)
1363 return Register();
1364 if ((Subtarget->hasSIMD128())) {
1365 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1366 }
1367 return Register();
1368}
1369
1370Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v4i32_r(MVT RetVT, Register Op0) {
1371 if (RetVT.SimpleTy != MVT::v2i64)
1372 return Register();
1373 if ((Subtarget->hasSIMD128())) {
1374 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1375 }
1376 return Register();
1377}
1378
1379Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_r(MVT VT, MVT RetVT, Register Op0) {
1380 switch (VT.SimpleTy) {
1381 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v16i8_r(RetVT, Op0);
1382 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v8i16_r(RetVT, Op0);
1383 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v4i32_r(RetVT, Op0);
1384 default: return Register();
1385 }
1386}
1387
1388// FastEmit functions for WebAssemblyISD::EXT_ADD_PAIRWISE_S.
1389
1390Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v16i8_r(MVT RetVT, Register Op0) {
1391 if (RetVT.SimpleTy != MVT::v8i16)
1392 return Register();
1393 if ((Subtarget->hasSIMD128())) {
1394 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1395 }
1396 return Register();
1397}
1398
1399Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v8i16_r(MVT RetVT, Register Op0) {
1400 if (RetVT.SimpleTy != MVT::v4i32)
1401 return Register();
1402 if ((Subtarget->hasSIMD128())) {
1403 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1404 }
1405 return Register();
1406}
1407
1408Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_r(MVT VT, MVT RetVT, Register Op0) {
1409 switch (VT.SimpleTy) {
1410 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v16i8_r(RetVT, Op0);
1411 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v8i16_r(RetVT, Op0);
1412 default: return Register();
1413 }
1414}
1415
1416// FastEmit functions for WebAssemblyISD::EXT_ADD_PAIRWISE_U.
1417
1418Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v16i8_r(MVT RetVT, Register Op0) {
1419 if (RetVT.SimpleTy != MVT::v8i16)
1420 return Register();
1421 if ((Subtarget->hasSIMD128())) {
1422 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1423 }
1424 return Register();
1425}
1426
1427Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v8i16_r(MVT RetVT, Register Op0) {
1428 if (RetVT.SimpleTy != MVT::v4i32)
1429 return Register();
1430 if ((Subtarget->hasSIMD128())) {
1431 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1432 }
1433 return Register();
1434}
1435
1436Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_r(MVT VT, MVT RetVT, Register Op0) {
1437 switch (VT.SimpleTy) {
1438 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v16i8_r(RetVT, Op0);
1439 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v8i16_r(RetVT, Op0);
1440 default: return Register();
1441 }
1442}
1443
1444// FastEmit functions for WebAssemblyISD::PROMOTE_LOW.
1445
1446Register fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v8i16_r(MVT RetVT, Register Op0) {
1447 if (RetVT.SimpleTy != MVT::v4f32)
1448 return Register();
1449 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1450 return fastEmitInst_r(MachineInstOpcode: WebAssembly::promote_low_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1451 }
1452 return Register();
1453}
1454
1455Register fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v4f32_r(MVT RetVT, Register Op0) {
1456 if (RetVT.SimpleTy != MVT::v2f64)
1457 return Register();
1458 if ((Subtarget->hasSIMD128())) {
1459 return fastEmitInst_r(MachineInstOpcode: WebAssembly::promote_low_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1460 }
1461 return Register();
1462}
1463
1464Register fastEmit_WebAssemblyISD_PROMOTE_LOW_r(MVT VT, MVT RetVT, Register Op0) {
1465 switch (VT.SimpleTy) {
1466 case MVT::v8i16: return fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v8i16_r(RetVT, Op0);
1467 case MVT::v4f32: return fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v4f32_r(RetVT, Op0);
1468 default: return Register();
1469 }
1470}
1471
1472// FastEmit functions for WebAssemblyISD::TRUNC_SAT_ZERO_S.
1473
1474Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_MVT_v2f64_r(MVT RetVT, Register Op0) {
1475 if (RetVT.SimpleTy != MVT::v4i32)
1476 return Register();
1477 if ((Subtarget->hasSIMD128())) {
1478 return fastEmitInst_r(MachineInstOpcode: WebAssembly::trunc_sat_zero_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1479 }
1480 return Register();
1481}
1482
1483Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_r(MVT VT, MVT RetVT, Register Op0) {
1484 switch (VT.SimpleTy) {
1485 case MVT::v2f64: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_MVT_v2f64_r(RetVT, Op0);
1486 default: return Register();
1487 }
1488}
1489
1490// FastEmit functions for WebAssemblyISD::TRUNC_SAT_ZERO_U.
1491
1492Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_MVT_v2f64_r(MVT RetVT, Register Op0) {
1493 if (RetVT.SimpleTy != MVT::v4i32)
1494 return Register();
1495 if ((Subtarget->hasSIMD128())) {
1496 return fastEmitInst_r(MachineInstOpcode: WebAssembly::trunc_sat_zero_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1497 }
1498 return Register();
1499}
1500
1501Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_r(MVT VT, MVT RetVT, Register Op0) {
1502 switch (VT.SimpleTy) {
1503 case MVT::v2f64: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_MVT_v2f64_r(RetVT, Op0);
1504 default: return Register();
1505 }
1506}
1507
1508// Top-level FastEmit function.
1509
1510Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
1511 switch (Opcode) {
1512 case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0);
1513 case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0);
1514 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1515 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1516 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1517 case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0);
1518 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1519 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0);
1520 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0);
1521 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0);
1522 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1523 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1524 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1525 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1526 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1527 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1528 case ISD::FROUNDEVEN: return fastEmit_ISD_FROUNDEVEN_r(VT, RetVT, Op0);
1529 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1530 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0);
1531 case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0);
1532 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1533 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1534 case ISD::SPLAT_VECTOR: return fastEmit_ISD_SPLAT_VECTOR_r(VT, RetVT, Op0);
1535 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0);
1536 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1537 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0);
1538 case WebAssemblyISD::BR_TABLE: return fastEmit_WebAssemblyISD_BR_TABLE_r(VT, RetVT, Op0);
1539 case WebAssemblyISD::CONVERT_LOW_S: return fastEmit_WebAssemblyISD_CONVERT_LOW_S_r(VT, RetVT, Op0);
1540 case WebAssemblyISD::CONVERT_LOW_U: return fastEmit_WebAssemblyISD_CONVERT_LOW_U_r(VT, RetVT, Op0);
1541 case WebAssemblyISD::DEMOTE_ZERO: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_r(VT, RetVT, Op0);
1542 case WebAssemblyISD::EXTEND_HIGH_S: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_r(VT, RetVT, Op0);
1543 case WebAssemblyISD::EXTEND_HIGH_U: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_r(VT, RetVT, Op0);
1544 case WebAssemblyISD::EXTEND_LOW_S: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_r(VT, RetVT, Op0);
1545 case WebAssemblyISD::EXTEND_LOW_U: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_r(VT, RetVT, Op0);
1546 case WebAssemblyISD::EXT_ADD_PAIRWISE_S: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_r(VT, RetVT, Op0);
1547 case WebAssemblyISD::EXT_ADD_PAIRWISE_U: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_r(VT, RetVT, Op0);
1548 case WebAssemblyISD::PROMOTE_LOW: return fastEmit_WebAssemblyISD_PROMOTE_LOW_r(VT, RetVT, Op0);
1549 case WebAssemblyISD::TRUNC_SAT_ZERO_S: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_r(VT, RetVT, Op0);
1550 case WebAssemblyISD::TRUNC_SAT_ZERO_U: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_r(VT, RetVT, Op0);
1551 default: return Register();
1552 }
1553}
1554
1555// FastEmit functions for ISD::ADD.
1556
1557Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1558 if (RetVT.SimpleTy != MVT::i32)
1559 return Register();
1560 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
1561}
1562
1563Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1564 if (RetVT.SimpleTy != MVT::i64)
1565 return Register();
1566 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
1567}
1568
1569Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1570 if (RetVT.SimpleTy != MVT::v16i8)
1571 return Register();
1572 if ((Subtarget->hasSIMD128())) {
1573 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
1574 }
1575 return Register();
1576}
1577
1578Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1579 if (RetVT.SimpleTy != MVT::v8i16)
1580 return Register();
1581 if ((Subtarget->hasSIMD128())) {
1582 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1583 }
1584 return Register();
1585}
1586
1587Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1588 if (RetVT.SimpleTy != MVT::v4i32)
1589 return Register();
1590 if ((Subtarget->hasSIMD128())) {
1591 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1592 }
1593 return Register();
1594}
1595
1596Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1597 if (RetVT.SimpleTy != MVT::v2i64)
1598 return Register();
1599 if ((Subtarget->hasSIMD128())) {
1600 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1601 }
1602 return Register();
1603}
1604
1605Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1606 switch (VT.SimpleTy) {
1607 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1608 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1609 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1610 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1611 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1612 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1613 default: return Register();
1614 }
1615}
1616
1617// FastEmit functions for ISD::AND.
1618
1619Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1620 if (RetVT.SimpleTy != MVT::i32)
1621 return Register();
1622 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
1623}
1624
1625Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1626 if (RetVT.SimpleTy != MVT::i64)
1627 return Register();
1628 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
1629}
1630
1631Register fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1632 if (RetVT.SimpleTy != MVT::v16i8)
1633 return Register();
1634 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1635}
1636
1637Register fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1638 if (RetVT.SimpleTy != MVT::v8i16)
1639 return Register();
1640 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1641}
1642
1643Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1644 if (RetVT.SimpleTy != MVT::v4i32)
1645 return Register();
1646 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1647}
1648
1649Register fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1650 if (RetVT.SimpleTy != MVT::v2i64)
1651 return Register();
1652 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1653}
1654
1655Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1656 switch (VT.SimpleTy) {
1657 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1658 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1659 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1660 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1661 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1662 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1663 default: return Register();
1664 }
1665}
1666
1667// FastEmit functions for ISD::AVGCEILU.
1668
1669Register fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1670 if (RetVT.SimpleTy != MVT::v16i8)
1671 return Register();
1672 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AVGR_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
1673}
1674
1675Register fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1676 if (RetVT.SimpleTy != MVT::v8i16)
1677 return Register();
1678 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AVGR_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1679}
1680
1681Register fastEmit_ISD_AVGCEILU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1682 switch (VT.SimpleTy) {
1683 case MVT::v16i8: return fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(RetVT, Op0, Op1);
1684 case MVT::v8i16: return fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(RetVT, Op0, Op1);
1685 default: return Register();
1686 }
1687}
1688
1689// FastEmit functions for ISD::FADD.
1690
1691Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1692 if (RetVT.SimpleTy != MVT::f32)
1693 return Register();
1694 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1695}
1696
1697Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1698 if (RetVT.SimpleTy != MVT::f64)
1699 return Register();
1700 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1701}
1702
1703Register fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1704 if (RetVT.SimpleTy != MVT::v8f16)
1705 return Register();
1706 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1707 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1708 }
1709 return Register();
1710}
1711
1712Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1713 if (RetVT.SimpleTy != MVT::v4f32)
1714 return Register();
1715 if ((Subtarget->hasSIMD128())) {
1716 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1717 }
1718 return Register();
1719}
1720
1721Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1722 if (RetVT.SimpleTy != MVT::v2f64)
1723 return Register();
1724 if ((Subtarget->hasSIMD128())) {
1725 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1726 }
1727 return Register();
1728}
1729
1730Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1731 switch (VT.SimpleTy) {
1732 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1733 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1734 case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op1);
1735 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1736 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1737 default: return Register();
1738 }
1739}
1740
1741// FastEmit functions for ISD::FCOPYSIGN.
1742
1743Register fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1744 if (RetVT.SimpleTy != MVT::f32)
1745 return Register();
1746 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::COPYSIGN_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1747}
1748
1749Register fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1750 if (RetVT.SimpleTy != MVT::f64)
1751 return Register();
1752 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::COPYSIGN_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1753}
1754
1755Register fastEmit_ISD_FCOPYSIGN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1756 switch (VT.SimpleTy) {
1757 case MVT::f32: return fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(RetVT, Op0, Op1);
1758 case MVT::f64: return fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(RetVT, Op0, Op1);
1759 default: return Register();
1760 }
1761}
1762
1763// FastEmit functions for ISD::FDIV.
1764
1765Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1766 if (RetVT.SimpleTy != MVT::f32)
1767 return Register();
1768 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1769}
1770
1771Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1772 if (RetVT.SimpleTy != MVT::f64)
1773 return Register();
1774 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1775}
1776
1777Register fastEmit_ISD_FDIV_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1778 if (RetVT.SimpleTy != MVT::v8f16)
1779 return Register();
1780 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1781 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1782 }
1783 return Register();
1784}
1785
1786Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1787 if (RetVT.SimpleTy != MVT::v4f32)
1788 return Register();
1789 if ((Subtarget->hasSIMD128())) {
1790 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1791 }
1792 return Register();
1793}
1794
1795Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1796 if (RetVT.SimpleTy != MVT::v2f64)
1797 return Register();
1798 if ((Subtarget->hasSIMD128())) {
1799 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1800 }
1801 return Register();
1802}
1803
1804Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1805 switch (VT.SimpleTy) {
1806 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1807 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1808 case MVT::v8f16: return fastEmit_ISD_FDIV_MVT_v8f16_rr(RetVT, Op0, Op1);
1809 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1810 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1811 default: return Register();
1812 }
1813}
1814
1815// FastEmit functions for ISD::FMAXIMUM.
1816
1817Register fastEmit_ISD_FMAXIMUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1818 if (RetVT.SimpleTy != MVT::f32)
1819 return Register();
1820 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1821}
1822
1823Register fastEmit_ISD_FMAXIMUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1824 if (RetVT.SimpleTy != MVT::f64)
1825 return Register();
1826 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1827}
1828
1829Register fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1830 if (RetVT.SimpleTy != MVT::v8f16)
1831 return Register();
1832 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1833 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1834 }
1835 return Register();
1836}
1837
1838Register fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1839 if (RetVT.SimpleTy != MVT::v4f32)
1840 return Register();
1841 if ((Subtarget->hasSIMD128())) {
1842 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1843 }
1844 return Register();
1845}
1846
1847Register fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1848 if (RetVT.SimpleTy != MVT::v2f64)
1849 return Register();
1850 if ((Subtarget->hasSIMD128())) {
1851 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1852 }
1853 return Register();
1854}
1855
1856Register fastEmit_ISD_FMAXIMUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1857 switch (VT.SimpleTy) {
1858 case MVT::f32: return fastEmit_ISD_FMAXIMUM_MVT_f32_rr(RetVT, Op0, Op1);
1859 case MVT::f64: return fastEmit_ISD_FMAXIMUM_MVT_f64_rr(RetVT, Op0, Op1);
1860 case MVT::v8f16: return fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(RetVT, Op0, Op1);
1861 case MVT::v4f32: return fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(RetVT, Op0, Op1);
1862 case MVT::v2f64: return fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(RetVT, Op0, Op1);
1863 default: return Register();
1864 }
1865}
1866
1867// FastEmit functions for ISD::FMINIMUM.
1868
1869Register fastEmit_ISD_FMINIMUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1870 if (RetVT.SimpleTy != MVT::f32)
1871 return Register();
1872 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1873}
1874
1875Register fastEmit_ISD_FMINIMUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1876 if (RetVT.SimpleTy != MVT::f64)
1877 return Register();
1878 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1879}
1880
1881Register fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1882 if (RetVT.SimpleTy != MVT::v8f16)
1883 return Register();
1884 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1885 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1886 }
1887 return Register();
1888}
1889
1890Register fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1891 if (RetVT.SimpleTy != MVT::v4f32)
1892 return Register();
1893 if ((Subtarget->hasSIMD128())) {
1894 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1895 }
1896 return Register();
1897}
1898
1899Register fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1900 if (RetVT.SimpleTy != MVT::v2f64)
1901 return Register();
1902 if ((Subtarget->hasSIMD128())) {
1903 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1904 }
1905 return Register();
1906}
1907
1908Register fastEmit_ISD_FMINIMUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1909 switch (VT.SimpleTy) {
1910 case MVT::f32: return fastEmit_ISD_FMINIMUM_MVT_f32_rr(RetVT, Op0, Op1);
1911 case MVT::f64: return fastEmit_ISD_FMINIMUM_MVT_f64_rr(RetVT, Op0, Op1);
1912 case MVT::v8f16: return fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(RetVT, Op0, Op1);
1913 case MVT::v4f32: return fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(RetVT, Op0, Op1);
1914 case MVT::v2f64: return fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(RetVT, Op0, Op1);
1915 default: return Register();
1916 }
1917}
1918
1919// FastEmit functions for ISD::FMUL.
1920
1921Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1922 if (RetVT.SimpleTy != MVT::f32)
1923 return Register();
1924 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1925}
1926
1927Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1928 if (RetVT.SimpleTy != MVT::f64)
1929 return Register();
1930 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1931}
1932
1933Register fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1934 if (RetVT.SimpleTy != MVT::v8f16)
1935 return Register();
1936 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1937 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1938 }
1939 return Register();
1940}
1941
1942Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1943 if (RetVT.SimpleTy != MVT::v4f32)
1944 return Register();
1945 if ((Subtarget->hasSIMD128())) {
1946 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1947 }
1948 return Register();
1949}
1950
1951Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1952 if (RetVT.SimpleTy != MVT::v2f64)
1953 return Register();
1954 if ((Subtarget->hasSIMD128())) {
1955 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1956 }
1957 return Register();
1958}
1959
1960Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1961 switch (VT.SimpleTy) {
1962 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1963 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1964 case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op1);
1965 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1966 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1967 default: return Register();
1968 }
1969}
1970
1971// FastEmit functions for ISD::FSUB.
1972
1973Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1974 if (RetVT.SimpleTy != MVT::f32)
1975 return Register();
1976 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1977}
1978
1979Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1980 if (RetVT.SimpleTy != MVT::f64)
1981 return Register();
1982 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1983}
1984
1985Register fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1986 if (RetVT.SimpleTy != MVT::v8f16)
1987 return Register();
1988 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1989 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1990 }
1991 return Register();
1992}
1993
1994Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1995 if (RetVT.SimpleTy != MVT::v4f32)
1996 return Register();
1997 if ((Subtarget->hasSIMD128())) {
1998 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1999 }
2000 return Register();
2001}
2002
2003Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
2004 if (RetVT.SimpleTy != MVT::v2f64)
2005 return Register();
2006 if ((Subtarget->hasSIMD128())) {
2007 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2008 }
2009 return Register();
2010}
2011
2012Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2013 switch (VT.SimpleTy) {
2014 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
2015 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
2016 case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op1);
2017 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
2018 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
2019 default: return Register();
2020 }
2021}
2022
2023// FastEmit functions for ISD::MUL.
2024
2025Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2026 if (RetVT.SimpleTy != MVT::i32)
2027 return Register();
2028 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2029}
2030
2031Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2032 if (RetVT.SimpleTy != MVT::i64)
2033 return Register();
2034 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2035}
2036
2037Register fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2038 if (RetVT.SimpleTy != MVT::v8i16)
2039 return Register();
2040 if ((Subtarget->hasSIMD128())) {
2041 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2042 }
2043 return Register();
2044}
2045
2046Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2047 if (RetVT.SimpleTy != MVT::v4i32)
2048 return Register();
2049 if ((Subtarget->hasSIMD128())) {
2050 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2051 }
2052 return Register();
2053}
2054
2055Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2056 if (RetVT.SimpleTy != MVT::v2i64)
2057 return Register();
2058 if ((Subtarget->hasSIMD128())) {
2059 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2060 }
2061 return Register();
2062}
2063
2064Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2065 switch (VT.SimpleTy) {
2066 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
2067 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
2068 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
2069 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
2070 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
2071 default: return Register();
2072 }
2073}
2074
2075// FastEmit functions for ISD::OR.
2076
2077Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2078 if (RetVT.SimpleTy != MVT::i32)
2079 return Register();
2080 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2081}
2082
2083Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2084 if (RetVT.SimpleTy != MVT::i64)
2085 return Register();
2086 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2087}
2088
2089Register fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2090 if (RetVT.SimpleTy != MVT::v16i8)
2091 return Register();
2092 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2093}
2094
2095Register fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2096 if (RetVT.SimpleTy != MVT::v8i16)
2097 return Register();
2098 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2099}
2100
2101Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2102 if (RetVT.SimpleTy != MVT::v4i32)
2103 return Register();
2104 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2105}
2106
2107Register fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2108 if (RetVT.SimpleTy != MVT::v2i64)
2109 return Register();
2110 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2111}
2112
2113Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2114 switch (VT.SimpleTy) {
2115 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
2116 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
2117 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
2118 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
2119 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
2120 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
2121 default: return Register();
2122 }
2123}
2124
2125// FastEmit functions for ISD::ROTL.
2126
2127Register fastEmit_ISD_ROTL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2128 if (RetVT.SimpleTy != MVT::i32)
2129 return Register();
2130 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2131}
2132
2133Register fastEmit_ISD_ROTL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2134 if (RetVT.SimpleTy != MVT::i64)
2135 return Register();
2136 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2137}
2138
2139Register fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2140 switch (VT.SimpleTy) {
2141 case MVT::i32: return fastEmit_ISD_ROTL_MVT_i32_rr(RetVT, Op0, Op1);
2142 case MVT::i64: return fastEmit_ISD_ROTL_MVT_i64_rr(RetVT, Op0, Op1);
2143 default: return Register();
2144 }
2145}
2146
2147// FastEmit functions for ISD::ROTR.
2148
2149Register fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2150 if (RetVT.SimpleTy != MVT::i32)
2151 return Register();
2152 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2153}
2154
2155Register fastEmit_ISD_ROTR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2156 if (RetVT.SimpleTy != MVT::i64)
2157 return Register();
2158 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2159}
2160
2161Register fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2162 switch (VT.SimpleTy) {
2163 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
2164 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_rr(RetVT, Op0, Op1);
2165 default: return Register();
2166 }
2167}
2168
2169// FastEmit functions for ISD::SADDSAT.
2170
2171Register fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2172 if (RetVT.SimpleTy != MVT::v16i8)
2173 return Register();
2174 if ((Subtarget->hasSIMD128())) {
2175 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2176 }
2177 return Register();
2178}
2179
2180Register fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2181 if (RetVT.SimpleTy != MVT::v8i16)
2182 return Register();
2183 if ((Subtarget->hasSIMD128())) {
2184 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2185 }
2186 return Register();
2187}
2188
2189Register fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2190 switch (VT.SimpleTy) {
2191 case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2192 case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2193 default: return Register();
2194 }
2195}
2196
2197// FastEmit functions for ISD::SDIV.
2198
2199Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2200 if (RetVT.SimpleTy != MVT::i32)
2201 return Register();
2202 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2203}
2204
2205Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2206 if (RetVT.SimpleTy != MVT::i64)
2207 return Register();
2208 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2209}
2210
2211Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2212 switch (VT.SimpleTy) {
2213 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
2214 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
2215 default: return Register();
2216 }
2217}
2218
2219// FastEmit functions for ISD::SHL.
2220
2221Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2222 if (RetVT.SimpleTy != MVT::i32)
2223 return Register();
2224 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2225}
2226
2227Register fastEmit_ISD_SHL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2228 if (RetVT.SimpleTy != MVT::i64)
2229 return Register();
2230 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2231}
2232
2233Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2234 switch (VT.SimpleTy) {
2235 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
2236 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_rr(RetVT, Op0, Op1);
2237 default: return Register();
2238 }
2239}
2240
2241// FastEmit functions for ISD::SMAX.
2242
2243Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2244 if (RetVT.SimpleTy != MVT::v16i8)
2245 return Register();
2246 if ((Subtarget->hasSIMD128())) {
2247 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2248 }
2249 return Register();
2250}
2251
2252Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2253 if (RetVT.SimpleTy != MVT::v8i16)
2254 return Register();
2255 if ((Subtarget->hasSIMD128())) {
2256 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2257 }
2258 return Register();
2259}
2260
2261Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2262 if (RetVT.SimpleTy != MVT::v4i32)
2263 return Register();
2264 if ((Subtarget->hasSIMD128())) {
2265 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2266 }
2267 return Register();
2268}
2269
2270Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2271 switch (VT.SimpleTy) {
2272 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2273 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2274 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2275 default: return Register();
2276 }
2277}
2278
2279// FastEmit functions for ISD::SMIN.
2280
2281Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2282 if (RetVT.SimpleTy != MVT::v16i8)
2283 return Register();
2284 if ((Subtarget->hasSIMD128())) {
2285 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2286 }
2287 return Register();
2288}
2289
2290Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2291 if (RetVT.SimpleTy != MVT::v8i16)
2292 return Register();
2293 if ((Subtarget->hasSIMD128())) {
2294 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2295 }
2296 return Register();
2297}
2298
2299Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2300 if (RetVT.SimpleTy != MVT::v4i32)
2301 return Register();
2302 if ((Subtarget->hasSIMD128())) {
2303 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2304 }
2305 return Register();
2306}
2307
2308Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2309 switch (VT.SimpleTy) {
2310 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2311 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2312 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2313 default: return Register();
2314 }
2315}
2316
2317// FastEmit functions for ISD::SRA.
2318
2319Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2320 if (RetVT.SimpleTy != MVT::i32)
2321 return Register();
2322 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2323}
2324
2325Register fastEmit_ISD_SRA_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2326 if (RetVT.SimpleTy != MVT::i64)
2327 return Register();
2328 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2329}
2330
2331Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2332 switch (VT.SimpleTy) {
2333 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2334 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_rr(RetVT, Op0, Op1);
2335 default: return Register();
2336 }
2337}
2338
2339// FastEmit functions for ISD::SREM.
2340
2341Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2342 if (RetVT.SimpleTy != MVT::i32)
2343 return Register();
2344 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2345}
2346
2347Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2348 if (RetVT.SimpleTy != MVT::i64)
2349 return Register();
2350 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2351}
2352
2353Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2354 switch (VT.SimpleTy) {
2355 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2356 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2357 default: return Register();
2358 }
2359}
2360
2361// FastEmit functions for ISD::SRL.
2362
2363Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2364 if (RetVT.SimpleTy != MVT::i32)
2365 return Register();
2366 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2367}
2368
2369Register fastEmit_ISD_SRL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2370 if (RetVT.SimpleTy != MVT::i64)
2371 return Register();
2372 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2373}
2374
2375Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2376 switch (VT.SimpleTy) {
2377 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2378 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_rr(RetVT, Op0, Op1);
2379 default: return Register();
2380 }
2381}
2382
2383// FastEmit functions for ISD::SSUBSAT.
2384
2385Register fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2386 if (RetVT.SimpleTy != MVT::v16i8)
2387 return Register();
2388 if ((Subtarget->hasSIMD128())) {
2389 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2390 }
2391 return Register();
2392}
2393
2394Register fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2395 if (RetVT.SimpleTy != MVT::v8i16)
2396 return Register();
2397 if ((Subtarget->hasSIMD128())) {
2398 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2399 }
2400 return Register();
2401}
2402
2403Register fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2404 switch (VT.SimpleTy) {
2405 case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2406 case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2407 default: return Register();
2408 }
2409}
2410
2411// FastEmit functions for ISD::SUB.
2412
2413Register fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2414 if (RetVT.SimpleTy != MVT::i32)
2415 return Register();
2416 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2417}
2418
2419Register fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2420 if (RetVT.SimpleTy != MVT::i64)
2421 return Register();
2422 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2423}
2424
2425Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2426 if (RetVT.SimpleTy != MVT::v16i8)
2427 return Register();
2428 if ((Subtarget->hasSIMD128())) {
2429 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2430 }
2431 return Register();
2432}
2433
2434Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2435 if (RetVT.SimpleTy != MVT::v8i16)
2436 return Register();
2437 if ((Subtarget->hasSIMD128())) {
2438 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2439 }
2440 return Register();
2441}
2442
2443Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2444 if (RetVT.SimpleTy != MVT::v4i32)
2445 return Register();
2446 if ((Subtarget->hasSIMD128())) {
2447 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2448 }
2449 return Register();
2450}
2451
2452Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2453 if (RetVT.SimpleTy != MVT::v2i64)
2454 return Register();
2455 if ((Subtarget->hasSIMD128())) {
2456 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2457 }
2458 return Register();
2459}
2460
2461Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2462 switch (VT.SimpleTy) {
2463 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2464 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2465 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2466 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2467 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2468 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2469 default: return Register();
2470 }
2471}
2472
2473// FastEmit functions for ISD::UADDSAT.
2474
2475Register fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2476 if (RetVT.SimpleTy != MVT::v16i8)
2477 return Register();
2478 if ((Subtarget->hasSIMD128())) {
2479 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2480 }
2481 return Register();
2482}
2483
2484Register fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2485 if (RetVT.SimpleTy != MVT::v8i16)
2486 return Register();
2487 if ((Subtarget->hasSIMD128())) {
2488 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2489 }
2490 return Register();
2491}
2492
2493Register fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2494 switch (VT.SimpleTy) {
2495 case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2496 case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2497 default: return Register();
2498 }
2499}
2500
2501// FastEmit functions for ISD::UDIV.
2502
2503Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2504 if (RetVT.SimpleTy != MVT::i32)
2505 return Register();
2506 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2507}
2508
2509Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2510 if (RetVT.SimpleTy != MVT::i64)
2511 return Register();
2512 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2513}
2514
2515Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2516 switch (VT.SimpleTy) {
2517 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2518 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2519 default: return Register();
2520 }
2521}
2522
2523// FastEmit functions for ISD::UMAX.
2524
2525Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2526 if (RetVT.SimpleTy != MVT::v16i8)
2527 return Register();
2528 if ((Subtarget->hasSIMD128())) {
2529 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2530 }
2531 return Register();
2532}
2533
2534Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2535 if (RetVT.SimpleTy != MVT::v8i16)
2536 return Register();
2537 if ((Subtarget->hasSIMD128())) {
2538 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2539 }
2540 return Register();
2541}
2542
2543Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2544 if (RetVT.SimpleTy != MVT::v4i32)
2545 return Register();
2546 if ((Subtarget->hasSIMD128())) {
2547 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2548 }
2549 return Register();
2550}
2551
2552Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2553 switch (VT.SimpleTy) {
2554 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2555 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2556 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2557 default: return Register();
2558 }
2559}
2560
2561// FastEmit functions for ISD::UMIN.
2562
2563Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2564 if (RetVT.SimpleTy != MVT::v16i8)
2565 return Register();
2566 if ((Subtarget->hasSIMD128())) {
2567 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2568 }
2569 return Register();
2570}
2571
2572Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2573 if (RetVT.SimpleTy != MVT::v8i16)
2574 return Register();
2575 if ((Subtarget->hasSIMD128())) {
2576 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2577 }
2578 return Register();
2579}
2580
2581Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2582 if (RetVT.SimpleTy != MVT::v4i32)
2583 return Register();
2584 if ((Subtarget->hasSIMD128())) {
2585 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2586 }
2587 return Register();
2588}
2589
2590Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2591 switch (VT.SimpleTy) {
2592 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2593 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2594 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2595 default: return Register();
2596 }
2597}
2598
2599// FastEmit functions for ISD::UREM.
2600
2601Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2602 if (RetVT.SimpleTy != MVT::i32)
2603 return Register();
2604 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2605}
2606
2607Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2608 if (RetVT.SimpleTy != MVT::i64)
2609 return Register();
2610 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2611}
2612
2613Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2614 switch (VT.SimpleTy) {
2615 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
2616 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
2617 default: return Register();
2618 }
2619}
2620
2621// FastEmit functions for ISD::USUBSAT.
2622
2623Register fastEmit_ISD_USUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2624 if (RetVT.SimpleTy != MVT::v16i8)
2625 return Register();
2626 if ((Subtarget->hasSIMD128())) {
2627 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2628 }
2629 return Register();
2630}
2631
2632Register fastEmit_ISD_USUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2633 if (RetVT.SimpleTy != MVT::v8i16)
2634 return Register();
2635 if ((Subtarget->hasSIMD128())) {
2636 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2637 }
2638 return Register();
2639}
2640
2641Register fastEmit_ISD_USUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2642 switch (VT.SimpleTy) {
2643 case MVT::v16i8: return fastEmit_ISD_USUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2644 case MVT::v8i16: return fastEmit_ISD_USUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2645 default: return Register();
2646 }
2647}
2648
2649// FastEmit functions for ISD::XOR.
2650
2651Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2652 if (RetVT.SimpleTy != MVT::i32)
2653 return Register();
2654 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2655}
2656
2657Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2658 if (RetVT.SimpleTy != MVT::i64)
2659 return Register();
2660 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2661}
2662
2663Register fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2664 if (RetVT.SimpleTy != MVT::v16i8)
2665 return Register();
2666 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2667}
2668
2669Register fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2670 if (RetVT.SimpleTy != MVT::v8i16)
2671 return Register();
2672 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2673}
2674
2675Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2676 if (RetVT.SimpleTy != MVT::v4i32)
2677 return Register();
2678 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2679}
2680
2681Register fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2682 if (RetVT.SimpleTy != MVT::v2i64)
2683 return Register();
2684 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2685}
2686
2687Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2688 switch (VT.SimpleTy) {
2689 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
2690 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
2691 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
2692 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
2693 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
2694 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
2695 default: return Register();
2696 }
2697}
2698
2699// FastEmit functions for WebAssemblyISD::DOT.
2700
2701Register fastEmit_WebAssemblyISD_DOT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2702 if (RetVT.SimpleTy != MVT::v4i32)
2703 return Register();
2704 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DOT, RC: &WebAssembly::V128RegClass, Op0, Op1);
2705}
2706
2707Register fastEmit_WebAssemblyISD_DOT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2708 switch (VT.SimpleTy) {
2709 case MVT::v8i16: return fastEmit_WebAssemblyISD_DOT_MVT_v8i16_rr(RetVT, Op0, Op1);
2710 default: return Register();
2711 }
2712}
2713
2714// FastEmit functions for WebAssemblyISD::NARROW_U.
2715
2716Register fastEmit_WebAssemblyISD_NARROW_U_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2717 if (RetVT.SimpleTy != MVT::v16i8)
2718 return Register();
2719 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::NARROW_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2720}
2721
2722Register fastEmit_WebAssemblyISD_NARROW_U_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2723 if (RetVT.SimpleTy != MVT::v8i16)
2724 return Register();
2725 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::NARROW_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2726}
2727
2728Register fastEmit_WebAssemblyISD_NARROW_U_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2729 switch (VT.SimpleTy) {
2730 case MVT::v8i16: return fastEmit_WebAssemblyISD_NARROW_U_MVT_v8i16_rr(RetVT, Op0, Op1);
2731 case MVT::v4i32: return fastEmit_WebAssemblyISD_NARROW_U_MVT_v4i32_rr(RetVT, Op0, Op1);
2732 default: return Register();
2733 }
2734}
2735
2736// FastEmit functions for WebAssemblyISD::RELAXED_FMAX.
2737
2738Register fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
2739 if (RetVT.SimpleTy != MVT::v4f32)
2740 return Register();
2741 if ((Subtarget->hasRelaxedSIMD())) {
2742 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMAX_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2743 }
2744 return Register();
2745}
2746
2747Register fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
2748 if (RetVT.SimpleTy != MVT::v2f64)
2749 return Register();
2750 if ((Subtarget->hasRelaxedSIMD())) {
2751 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMAX_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2752 }
2753 return Register();
2754}
2755
2756Register fastEmit_WebAssemblyISD_RELAXED_FMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2757 switch (VT.SimpleTy) {
2758 case MVT::v4f32: return fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v4f32_rr(RetVT, Op0, Op1);
2759 case MVT::v2f64: return fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v2f64_rr(RetVT, Op0, Op1);
2760 default: return Register();
2761 }
2762}
2763
2764// FastEmit functions for WebAssemblyISD::RELAXED_FMIN.
2765
2766Register fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
2767 if (RetVT.SimpleTy != MVT::v4f32)
2768 return Register();
2769 if ((Subtarget->hasRelaxedSIMD())) {
2770 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMIN_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2771 }
2772 return Register();
2773}
2774
2775Register fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
2776 if (RetVT.SimpleTy != MVT::v2f64)
2777 return Register();
2778 if ((Subtarget->hasRelaxedSIMD())) {
2779 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMIN_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2780 }
2781 return Register();
2782}
2783
2784Register fastEmit_WebAssemblyISD_RELAXED_FMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2785 switch (VT.SimpleTy) {
2786 case MVT::v4f32: return fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v4f32_rr(RetVT, Op0, Op1);
2787 case MVT::v2f64: return fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v2f64_rr(RetVT, Op0, Op1);
2788 default: return Register();
2789 }
2790}
2791
2792// FastEmit functions for WebAssemblyISD::SWIZZLE.
2793
2794Register fastEmit_WebAssemblyISD_SWIZZLE_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2795 if (RetVT.SimpleTy != MVT::v16i8)
2796 return Register();
2797 if ((Subtarget->hasSIMD128())) {
2798 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SWIZZLE, RC: &WebAssembly::V128RegClass, Op0, Op1);
2799 }
2800 return Register();
2801}
2802
2803Register fastEmit_WebAssemblyISD_SWIZZLE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2804 switch (VT.SimpleTy) {
2805 case MVT::v16i8: return fastEmit_WebAssemblyISD_SWIZZLE_MVT_v16i8_rr(RetVT, Op0, Op1);
2806 default: return Register();
2807 }
2808}
2809
2810// Top-level FastEmit function.
2811
2812Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
2813 switch (Opcode) {
2814 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
2815 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
2816 case ISD::AVGCEILU: return fastEmit_ISD_AVGCEILU_rr(VT, RetVT, Op0, Op1);
2817 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
2818 case ISD::FCOPYSIGN: return fastEmit_ISD_FCOPYSIGN_rr(VT, RetVT, Op0, Op1);
2819 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
2820 case ISD::FMAXIMUM: return fastEmit_ISD_FMAXIMUM_rr(VT, RetVT, Op0, Op1);
2821 case ISD::FMINIMUM: return fastEmit_ISD_FMINIMUM_rr(VT, RetVT, Op0, Op1);
2822 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
2823 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
2824 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
2825 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
2826 case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op1);
2827 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
2828 case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op1);
2829 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
2830 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
2831 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
2832 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
2833 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
2834 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
2835 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
2836 case ISD::SSUBSAT: return fastEmit_ISD_SSUBSAT_rr(VT, RetVT, Op0, Op1);
2837 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
2838 case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op1);
2839 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
2840 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
2841 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
2842 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
2843 case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op1);
2844 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
2845 case WebAssemblyISD::DOT: return fastEmit_WebAssemblyISD_DOT_rr(VT, RetVT, Op0, Op1);
2846 case WebAssemblyISD::NARROW_U: return fastEmit_WebAssemblyISD_NARROW_U_rr(VT, RetVT, Op0, Op1);
2847 case WebAssemblyISD::RELAXED_FMAX: return fastEmit_WebAssemblyISD_RELAXED_FMAX_rr(VT, RetVT, Op0, Op1);
2848 case WebAssemblyISD::RELAXED_FMIN: return fastEmit_WebAssemblyISD_RELAXED_FMIN_rr(VT, RetVT, Op0, Op1);
2849 case WebAssemblyISD::SWIZZLE: return fastEmit_WebAssemblyISD_SWIZZLE_rr(VT, RetVT, Op0, Op1);
2850 default: return Register();
2851 }
2852}
2853
2854// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2855
2856Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(MVT RetVT, Register Op0, uint64_t imm1) {
2857 if (RetVT.SimpleTy != MVT::i32)
2858 return Register();
2859 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I8x16_u, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2860}
2861
2862Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2863 switch (VT.SimpleTy) {
2864 case MVT::v16i8: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(RetVT, Op0, imm1);
2865 default: return Register();
2866 }
2867}
2868
2869// Top-level FastEmit function.
2870
2871Register fastEmit_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2872 switch (Opcode) {
2873 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(VT, RetVT, Op0, imm1);
2874 default: return Register();
2875 }
2876}
2877
2878// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2879
2880Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(MVT RetVT, Register Op0, uint64_t imm1) {
2881 if (RetVT.SimpleTy != MVT::i32)
2882 return Register();
2883 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I16x8_u, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2884}
2885
2886Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2887 switch (VT.SimpleTy) {
2888 case MVT::v8i16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(RetVT, Op0, imm1);
2889 default: return Register();
2890 }
2891}
2892
2893// Top-level FastEmit function.
2894
2895Register fastEmit_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2896 switch (Opcode) {
2897 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(VT, RetVT, Op0, imm1);
2898 default: return Register();
2899 }
2900}
2901
2902// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2903
2904Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(MVT RetVT, Register Op0, uint64_t imm1) {
2905 if (RetVT.SimpleTy != MVT::i32)
2906 return Register();
2907 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I32x4, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2908}
2909
2910Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(MVT RetVT, Register Op0, uint64_t imm1) {
2911 if (RetVT.SimpleTy != MVT::f32)
2912 return Register();
2913 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_F32x4, RC: &WebAssembly::F32RegClass, Op0, Imm: imm1);
2914}
2915
2916Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2917 switch (VT.SimpleTy) {
2918 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(RetVT, Op0, imm1);
2919 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(RetVT, Op0, imm1);
2920 default: return Register();
2921 }
2922}
2923
2924// Top-level FastEmit function.
2925
2926Register fastEmit_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2927 switch (Opcode) {
2928 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(VT, RetVT, Op0, imm1);
2929 default: return Register();
2930 }
2931}
2932
2933// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2934
2935Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(MVT RetVT, Register Op0, uint64_t imm1) {
2936 if (RetVT.SimpleTy != MVT::i64)
2937 return Register();
2938 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I64x2, RC: &WebAssembly::I64RegClass, Op0, Imm: imm1);
2939}
2940
2941Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(MVT RetVT, Register Op0, uint64_t imm1) {
2942 if (RetVT.SimpleTy != MVT::f64)
2943 return Register();
2944 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_F64x2, RC: &WebAssembly::F64RegClass, Op0, Imm: imm1);
2945}
2946
2947Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2948 switch (VT.SimpleTy) {
2949 case MVT::v2i64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(RetVT, Op0, imm1);
2950 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(RetVT, Op0, imm1);
2951 default: return Register();
2952 }
2953}
2954
2955// Top-level FastEmit function.
2956
2957Register fastEmit_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2958 switch (Opcode) {
2959 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(VT, RetVT, Op0, imm1);
2960 default: return Register();
2961 }
2962}
2963
2964// FastEmit functions for ISD::ConstantFP.
2965
2966Register fastEmit_ISD_ConstantFP_MVT_f32_f(MVT RetVT, const ConstantFP *f0) {
2967 if (RetVT.SimpleTy != MVT::f32)
2968 return Register();
2969 return fastEmitInst_f(MachineInstOpcode: WebAssembly::CONST_F32, RC: &WebAssembly::F32RegClass, FPImm: f0);
2970}
2971
2972Register fastEmit_ISD_ConstantFP_MVT_f64_f(MVT RetVT, const ConstantFP *f0) {
2973 if (RetVT.SimpleTy != MVT::f64)
2974 return Register();
2975 return fastEmitInst_f(MachineInstOpcode: WebAssembly::CONST_F64, RC: &WebAssembly::F64RegClass, FPImm: f0);
2976}
2977
2978Register fastEmit_ISD_ConstantFP_f(MVT VT, MVT RetVT, const ConstantFP *f0) {
2979 switch (VT.SimpleTy) {
2980 case MVT::f32: return fastEmit_ISD_ConstantFP_MVT_f32_f(RetVT, f0);
2981 case MVT::f64: return fastEmit_ISD_ConstantFP_MVT_f64_f(RetVT, f0);
2982 default: return Register();
2983 }
2984}
2985
2986// Top-level FastEmit function.
2987
2988Register fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *f0) override {
2989 switch (Opcode) {
2990 case ISD::ConstantFP: return fastEmit_ISD_ConstantFP_f(VT, RetVT, f0);
2991 default: return Register();
2992 }
2993}
2994
2995// FastEmit functions for ISD::Constant.
2996
2997Register fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
2998 if (RetVT.SimpleTy != MVT::i32)
2999 return Register();
3000 return fastEmitInst_i(MachineInstOpcode: WebAssembly::CONST_I32, RC: &WebAssembly::I32RegClass, Imm: imm0);
3001}
3002
3003Register fastEmit_ISD_Constant_MVT_i64_i(MVT RetVT, uint64_t imm0) {
3004 if (RetVT.SimpleTy != MVT::i64)
3005 return Register();
3006 return fastEmitInst_i(MachineInstOpcode: WebAssembly::CONST_I64, RC: &WebAssembly::I64RegClass, Imm: imm0);
3007}
3008
3009Register fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
3010 switch (VT.SimpleTy) {
3011 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
3012 case MVT::i64: return fastEmit_ISD_Constant_MVT_i64_i(RetVT, imm0);
3013 default: return Register();
3014 }
3015}
3016
3017// Top-level FastEmit function.
3018
3019Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
3020 switch (Opcode) {
3021 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
3022 default: return Register();
3023 }
3024}
3025
3026