1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the WebAssembly target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_ImmI8(int64_t Imm) {
12return -(1 << (8 - 1)) <= Imm && Imm < (1 << 8);
13}
14static bool Predicate_ImmI16(int64_t Imm) {
15return -(1 << (16 - 1)) <= Imm && Imm < (1 << 16);
16}
17static bool Predicate_LaneIdx32(int64_t Imm) {
18return 0 <= Imm && Imm < 32;
19}
20static bool Predicate_LaneIdx16(int64_t Imm) {
21return 0 <= Imm && Imm < 16;
22}
23static bool Predicate_LaneIdx8(int64_t Imm) {
24return 0 <= Imm && Imm < 8;
25}
26static bool Predicate_LaneIdx4(int64_t Imm) {
27return 0 <= Imm && Imm < 4;
28}
29static bool Predicate_LaneIdx2(int64_t Imm) {
30return 0 <= Imm && Imm < 2;
31}
32
33
34// FastEmit functions for ISD::ABS.
35
36Register fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, Register Op0) {
37 if (RetVT.SimpleTy != MVT::v16i8)
38 return Register();
39 if ((Subtarget->hasSIMD128())) {
40 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I8x16, RC: &WebAssembly::V128RegClass, Op0);
41 }
42 return Register();
43}
44
45Register fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, Register Op0) {
46 if (RetVT.SimpleTy != MVT::v8i16)
47 return Register();
48 if ((Subtarget->hasSIMD128())) {
49 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I16x8, RC: &WebAssembly::V128RegClass, Op0);
50 }
51 return Register();
52}
53
54Register fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, Register Op0) {
55 if (RetVT.SimpleTy != MVT::v4i32)
56 return Register();
57 if ((Subtarget->hasSIMD128())) {
58 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I32x4, RC: &WebAssembly::V128RegClass, Op0);
59 }
60 return Register();
61}
62
63Register fastEmit_ISD_ABS_MVT_v2i64_r(MVT RetVT, Register Op0) {
64 if (RetVT.SimpleTy != MVT::v2i64)
65 return Register();
66 if ((Subtarget->hasSIMD128())) {
67 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I64x2, RC: &WebAssembly::V128RegClass, Op0);
68 }
69 return Register();
70}
71
72Register fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, Register Op0) {
73 switch (VT.SimpleTy) {
74 case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0);
75 case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0);
76 case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0);
77 case MVT::v2i64: return fastEmit_ISD_ABS_MVT_v2i64_r(RetVT, Op0);
78 default: return Register();
79 }
80}
81
82// FastEmit functions for ISD::ANY_EXTEND.
83
84Register fastEmit_ISD_ANY_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
85 if (RetVT.SimpleTy != MVT::i64)
86 return Register();
87 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_U_I32, RC: &WebAssembly::I64RegClass, Op0);
88}
89
90Register fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
91 switch (VT.SimpleTy) {
92 case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i32_r(RetVT, Op0);
93 default: return Register();
94 }
95}
96
97// FastEmit functions for ISD::BITCAST.
98
99Register fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, Register Op0) {
100 if (RetVT.SimpleTy != MVT::f32)
101 return Register();
102 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_REINTERPRET_I32, RC: &WebAssembly::F32RegClass, Op0);
103}
104
105Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
106 if (RetVT.SimpleTy != MVT::f64)
107 return Register();
108 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_REINTERPRET_I64, RC: &WebAssembly::F64RegClass, Op0);
109}
110
111Register fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, Register Op0) {
112 if (RetVT.SimpleTy != MVT::i32)
113 return Register();
114 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_REINTERPRET_F32, RC: &WebAssembly::I32RegClass, Op0);
115}
116
117Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
118 if (RetVT.SimpleTy != MVT::i64)
119 return Register();
120 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_REINTERPRET_F64, RC: &WebAssembly::I64RegClass, Op0);
121}
122
123Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
124 switch (VT.SimpleTy) {
125 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
126 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
127 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
128 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
129 default: return Register();
130 }
131}
132
133// FastEmit functions for ISD::CTLZ.
134
135Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
136 if (RetVT.SimpleTy != MVT::i32)
137 return Register();
138 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CLZ_I32, RC: &WebAssembly::I32RegClass, Op0);
139}
140
141Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
142 if (RetVT.SimpleTy != MVT::i64)
143 return Register();
144 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CLZ_I64, RC: &WebAssembly::I64RegClass, Op0);
145}
146
147Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
148 switch (VT.SimpleTy) {
149 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
150 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
151 default: return Register();
152 }
153}
154
155// FastEmit functions for ISD::CTPOP.
156
157Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
158 if (RetVT.SimpleTy != MVT::i32)
159 return Register();
160 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I32, RC: &WebAssembly::I32RegClass, Op0);
161}
162
163Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
164 if (RetVT.SimpleTy != MVT::i64)
165 return Register();
166 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I64, RC: &WebAssembly::I64RegClass, Op0);
167}
168
169Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
170 if (RetVT.SimpleTy != MVT::v16i8)
171 return Register();
172 if ((Subtarget->hasSIMD128())) {
173 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
174 }
175 return Register();
176}
177
178Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
179 switch (VT.SimpleTy) {
180 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
181 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
182 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
183 default: return Register();
184 }
185}
186
187// FastEmit functions for ISD::CTTZ.
188
189Register fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, Register Op0) {
190 if (RetVT.SimpleTy != MVT::i32)
191 return Register();
192 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CTZ_I32, RC: &WebAssembly::I32RegClass, Op0);
193}
194
195Register fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, Register Op0) {
196 if (RetVT.SimpleTy != MVT::i64)
197 return Register();
198 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CTZ_I64, RC: &WebAssembly::I64RegClass, Op0);
199}
200
201Register fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, Register Op0) {
202 switch (VT.SimpleTy) {
203 case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0);
204 case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0);
205 default: return Register();
206 }
207}
208
209// FastEmit functions for ISD::FABS.
210
211Register fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, Register Op0) {
212 if (RetVT.SimpleTy != MVT::f32)
213 return Register();
214 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F32, RC: &WebAssembly::F32RegClass, Op0);
215}
216
217Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
218 if (RetVT.SimpleTy != MVT::f64)
219 return Register();
220 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F64, RC: &WebAssembly::F64RegClass, Op0);
221}
222
223Register fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, Register Op0) {
224 if (RetVT.SimpleTy != MVT::v8f16)
225 return Register();
226 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
227 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F16x8, RC: &WebAssembly::V128RegClass, Op0);
228 }
229 return Register();
230}
231
232Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
233 if (RetVT.SimpleTy != MVT::v4f32)
234 return Register();
235 if ((Subtarget->hasSIMD128())) {
236 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F32x4, RC: &WebAssembly::V128RegClass, Op0);
237 }
238 return Register();
239}
240
241Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
242 if (RetVT.SimpleTy != MVT::v2f64)
243 return Register();
244 if ((Subtarget->hasSIMD128())) {
245 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F64x2, RC: &WebAssembly::V128RegClass, Op0);
246 }
247 return Register();
248}
249
250Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
251 switch (VT.SimpleTy) {
252 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
253 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
254 case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0);
255 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
256 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
257 default: return Register();
258 }
259}
260
261// FastEmit functions for ISD::FCEIL.
262
263Register fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, Register Op0) {
264 if (RetVT.SimpleTy != MVT::f32)
265 return Register();
266 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F32, RC: &WebAssembly::F32RegClass, Op0);
267}
268
269Register fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, Register Op0) {
270 if (RetVT.SimpleTy != MVT::f64)
271 return Register();
272 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F64, RC: &WebAssembly::F64RegClass, Op0);
273}
274
275Register fastEmit_ISD_FCEIL_MVT_v8f16_r(MVT RetVT, Register Op0) {
276 if (RetVT.SimpleTy != MVT::v8f16)
277 return Register();
278 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
279 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F16x8, RC: &WebAssembly::V128RegClass, Op0);
280 }
281 return Register();
282}
283
284Register fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, Register Op0) {
285 if (RetVT.SimpleTy != MVT::v4f32)
286 return Register();
287 if ((Subtarget->hasSIMD128())) {
288 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F32x4, RC: &WebAssembly::V128RegClass, Op0);
289 }
290 return Register();
291}
292
293Register fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, Register Op0) {
294 if (RetVT.SimpleTy != MVT::v2f64)
295 return Register();
296 if ((Subtarget->hasSIMD128())) {
297 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F64x2, RC: &WebAssembly::V128RegClass, Op0);
298 }
299 return Register();
300}
301
302Register fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, Register Op0) {
303 switch (VT.SimpleTy) {
304 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0);
305 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0);
306 case MVT::v8f16: return fastEmit_ISD_FCEIL_MVT_v8f16_r(RetVT, Op0);
307 case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0);
308 case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0);
309 default: return Register();
310 }
311}
312
313// FastEmit functions for ISD::FFLOOR.
314
315Register fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, Register Op0) {
316 if (RetVT.SimpleTy != MVT::f32)
317 return Register();
318 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F32, RC: &WebAssembly::F32RegClass, Op0);
319}
320
321Register fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, Register Op0) {
322 if (RetVT.SimpleTy != MVT::f64)
323 return Register();
324 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F64, RC: &WebAssembly::F64RegClass, Op0);
325}
326
327Register fastEmit_ISD_FFLOOR_MVT_v8f16_r(MVT RetVT, Register Op0) {
328 if (RetVT.SimpleTy != MVT::v8f16)
329 return Register();
330 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
331 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F16x8, RC: &WebAssembly::V128RegClass, Op0);
332 }
333 return Register();
334}
335
336Register fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, Register Op0) {
337 if (RetVT.SimpleTy != MVT::v4f32)
338 return Register();
339 if ((Subtarget->hasSIMD128())) {
340 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F32x4, RC: &WebAssembly::V128RegClass, Op0);
341 }
342 return Register();
343}
344
345Register fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, Register Op0) {
346 if (RetVT.SimpleTy != MVT::v2f64)
347 return Register();
348 if ((Subtarget->hasSIMD128())) {
349 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F64x2, RC: &WebAssembly::V128RegClass, Op0);
350 }
351 return Register();
352}
353
354Register fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, Register Op0) {
355 switch (VT.SimpleTy) {
356 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0);
357 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0);
358 case MVT::v8f16: return fastEmit_ISD_FFLOOR_MVT_v8f16_r(RetVT, Op0);
359 case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0);
360 case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0);
361 default: return Register();
362 }
363}
364
365// FastEmit functions for ISD::FNEARBYINT.
366
367Register fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, Register Op0) {
368 if (RetVT.SimpleTy != MVT::f32)
369 return Register();
370 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
371}
372
373Register fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, Register Op0) {
374 if (RetVT.SimpleTy != MVT::f64)
375 return Register();
376 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
377}
378
379Register fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
380 if (RetVT.SimpleTy != MVT::v8f16)
381 return Register();
382 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
383 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
384 }
385 return Register();
386}
387
388Register fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
389 if (RetVT.SimpleTy != MVT::v4f32)
390 return Register();
391 if ((Subtarget->hasSIMD128())) {
392 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
393 }
394 return Register();
395}
396
397Register fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
398 if (RetVT.SimpleTy != MVT::v2f64)
399 return Register();
400 if ((Subtarget->hasSIMD128())) {
401 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
402 }
403 return Register();
404}
405
406Register fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, Register Op0) {
407 switch (VT.SimpleTy) {
408 case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0);
409 case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0);
410 case MVT::v8f16: return fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(RetVT, Op0);
411 case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0);
412 case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0);
413 default: return Register();
414 }
415}
416
417// FastEmit functions for ISD::FNEG.
418
419Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
420 if (RetVT.SimpleTy != MVT::f32)
421 return Register();
422 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F32, RC: &WebAssembly::F32RegClass, Op0);
423}
424
425Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
426 if (RetVT.SimpleTy != MVT::f64)
427 return Register();
428 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F64, RC: &WebAssembly::F64RegClass, Op0);
429}
430
431Register fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, Register Op0) {
432 if (RetVT.SimpleTy != MVT::v8f16)
433 return Register();
434 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
435 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F16x8, RC: &WebAssembly::V128RegClass, Op0);
436 }
437 return Register();
438}
439
440Register fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, Register Op0) {
441 if (RetVT.SimpleTy != MVT::v4f32)
442 return Register();
443 if ((Subtarget->hasSIMD128())) {
444 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F32x4, RC: &WebAssembly::V128RegClass, Op0);
445 }
446 return Register();
447}
448
449Register fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, Register Op0) {
450 if (RetVT.SimpleTy != MVT::v2f64)
451 return Register();
452 if ((Subtarget->hasSIMD128())) {
453 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F64x2, RC: &WebAssembly::V128RegClass, Op0);
454 }
455 return Register();
456}
457
458Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
459 switch (VT.SimpleTy) {
460 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
461 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
462 case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0);
463 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0);
464 case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0);
465 default: return Register();
466 }
467}
468
469// FastEmit functions for ISD::FP_EXTEND.
470
471Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
472 if (RetVT.SimpleTy != MVT::f64)
473 return Register();
474 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_PROMOTE_F32, RC: &WebAssembly::F64RegClass, Op0);
475}
476
477Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
478 switch (VT.SimpleTy) {
479 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
480 default: return Register();
481 }
482}
483
484// FastEmit functions for ISD::FP_ROUND.
485
486Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
487 if (RetVT.SimpleTy != MVT::f32)
488 return Register();
489 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_DEMOTE_F64, RC: &WebAssembly::F32RegClass, Op0);
490}
491
492Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
493 switch (VT.SimpleTy) {
494 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
495 default: return Register();
496 }
497}
498
499// FastEmit functions for ISD::FP_TO_SINT.
500
501Register fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Register Op0) {
502 if ((!Subtarget->hasNontrappingFPToInt())) {
503 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I32_F32, RC: &WebAssembly::I32RegClass, Op0);
504 }
505 if ((Subtarget->hasNontrappingFPToInt())) {
506 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_S_SAT_F32, RC: &WebAssembly::I32RegClass, Op0);
507 }
508 return Register();
509}
510
511Register fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Register Op0) {
512 if ((!Subtarget->hasNontrappingFPToInt())) {
513 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I64_F32, RC: &WebAssembly::I64RegClass, Op0);
514 }
515 if ((Subtarget->hasNontrappingFPToInt())) {
516 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_S_SAT_F32, RC: &WebAssembly::I64RegClass, Op0);
517 }
518 return Register();
519}
520
521Register fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, Register Op0) {
522switch (RetVT.SimpleTy) {
523 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0);
524 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0);
525 default: return Register();
526}
527}
528
529Register fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Register Op0) {
530 if ((!Subtarget->hasNontrappingFPToInt())) {
531 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I32_F64, RC: &WebAssembly::I32RegClass, Op0);
532 }
533 if ((Subtarget->hasNontrappingFPToInt())) {
534 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_S_SAT_F64, RC: &WebAssembly::I32RegClass, Op0);
535 }
536 return Register();
537}
538
539Register fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Register Op0) {
540 if ((!Subtarget->hasNontrappingFPToInt())) {
541 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I64_F64, RC: &WebAssembly::I64RegClass, Op0);
542 }
543 if ((Subtarget->hasNontrappingFPToInt())) {
544 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_S_SAT_F64, RC: &WebAssembly::I64RegClass, Op0);
545 }
546 return Register();
547}
548
549Register fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, Register Op0) {
550switch (RetVT.SimpleTy) {
551 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0);
552 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0);
553 default: return Register();
554}
555}
556
557Register fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
558 if (RetVT.SimpleTy != MVT::v8i16)
559 return Register();
560 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
561 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_sint_I16x8, RC: &WebAssembly::V128RegClass, Op0);
562 }
563 return Register();
564}
565
566Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
567 if (RetVT.SimpleTy != MVT::v4i32)
568 return Register();
569 if ((Subtarget->hasRelaxedSIMD())) {
570 return fastEmitInst_r(MachineInstOpcode: WebAssembly::int_wasm_relaxed_trunc_signed_I32x4, RC: &WebAssembly::V128RegClass, Op0);
571 }
572 if ((Subtarget->hasSIMD128())) {
573 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_sint_I32x4, RC: &WebAssembly::V128RegClass, Op0);
574 }
575 return Register();
576}
577
578Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
579 switch (VT.SimpleTy) {
580 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
581 case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
582 case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0);
583 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
584 default: return Register();
585 }
586}
587
588// FastEmit functions for ISD::FP_TO_UINT.
589
590Register fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Register Op0) {
591 if ((!Subtarget->hasNontrappingFPToInt())) {
592 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I32_F32, RC: &WebAssembly::I32RegClass, Op0);
593 }
594 if ((Subtarget->hasNontrappingFPToInt())) {
595 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_U_SAT_F32, RC: &WebAssembly::I32RegClass, Op0);
596 }
597 return Register();
598}
599
600Register fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Register Op0) {
601 if ((!Subtarget->hasNontrappingFPToInt())) {
602 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I64_F32, RC: &WebAssembly::I64RegClass, Op0);
603 }
604 if ((Subtarget->hasNontrappingFPToInt())) {
605 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_U_SAT_F32, RC: &WebAssembly::I64RegClass, Op0);
606 }
607 return Register();
608}
609
610Register fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, Register Op0) {
611switch (RetVT.SimpleTy) {
612 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0);
613 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0);
614 default: return Register();
615}
616}
617
618Register fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Register Op0) {
619 if ((!Subtarget->hasNontrappingFPToInt())) {
620 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I32_F64, RC: &WebAssembly::I32RegClass, Op0);
621 }
622 if ((Subtarget->hasNontrappingFPToInt())) {
623 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_U_SAT_F64, RC: &WebAssembly::I32RegClass, Op0);
624 }
625 return Register();
626}
627
628Register fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Register Op0) {
629 if ((!Subtarget->hasNontrappingFPToInt())) {
630 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I64_F64, RC: &WebAssembly::I64RegClass, Op0);
631 }
632 if ((Subtarget->hasNontrappingFPToInt())) {
633 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_U_SAT_F64, RC: &WebAssembly::I64RegClass, Op0);
634 }
635 return Register();
636}
637
638Register fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, Register Op0) {
639switch (RetVT.SimpleTy) {
640 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0);
641 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0);
642 default: return Register();
643}
644}
645
646Register fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
647 if (RetVT.SimpleTy != MVT::v8i16)
648 return Register();
649 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
650 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_uint_I16x8, RC: &WebAssembly::V128RegClass, Op0);
651 }
652 return Register();
653}
654
655Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
656 if (RetVT.SimpleTy != MVT::v4i32)
657 return Register();
658 if ((Subtarget->hasRelaxedSIMD())) {
659 return fastEmitInst_r(MachineInstOpcode: WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4, RC: &WebAssembly::V128RegClass, Op0);
660 }
661 if ((Subtarget->hasSIMD128())) {
662 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_uint_I32x4, RC: &WebAssembly::V128RegClass, Op0);
663 }
664 return Register();
665}
666
667Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
668 switch (VT.SimpleTy) {
669 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
670 case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
671 case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0);
672 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
673 default: return Register();
674 }
675}
676
677// FastEmit functions for ISD::FRINT.
678
679Register fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, Register Op0) {
680 if (RetVT.SimpleTy != MVT::f32)
681 return Register();
682 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
683}
684
685Register fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, Register Op0) {
686 if (RetVT.SimpleTy != MVT::f64)
687 return Register();
688 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
689}
690
691Register fastEmit_ISD_FRINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
692 if (RetVT.SimpleTy != MVT::v8f16)
693 return Register();
694 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
695}
696
697Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
698 if (RetVT.SimpleTy != MVT::v4f32)
699 return Register();
700 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
701}
702
703Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
704 if (RetVT.SimpleTy != MVT::v2f64)
705 return Register();
706 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
707}
708
709Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
710 switch (VT.SimpleTy) {
711 case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0);
712 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0);
713 case MVT::v8f16: return fastEmit_ISD_FRINT_MVT_v8f16_r(RetVT, Op0);
714 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
715 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
716 default: return Register();
717 }
718}
719
720// FastEmit functions for ISD::FROUNDEVEN.
721
722Register fastEmit_ISD_FROUNDEVEN_MVT_f32_r(MVT RetVT, Register Op0) {
723 if (RetVT.SimpleTy != MVT::f32)
724 return Register();
725 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
726}
727
728Register fastEmit_ISD_FROUNDEVEN_MVT_f64_r(MVT RetVT, Register Op0) {
729 if (RetVT.SimpleTy != MVT::f64)
730 return Register();
731 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
732}
733
734Register fastEmit_ISD_FROUNDEVEN_MVT_v8f16_r(MVT RetVT, Register Op0) {
735 if (RetVT.SimpleTy != MVT::v8f16)
736 return Register();
737 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
738}
739
740Register fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(MVT RetVT, Register Op0) {
741 if (RetVT.SimpleTy != MVT::v4f32)
742 return Register();
743 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
744}
745
746Register fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(MVT RetVT, Register Op0) {
747 if (RetVT.SimpleTy != MVT::v2f64)
748 return Register();
749 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
750}
751
752Register fastEmit_ISD_FROUNDEVEN_r(MVT VT, MVT RetVT, Register Op0) {
753 switch (VT.SimpleTy) {
754 case MVT::f32: return fastEmit_ISD_FROUNDEVEN_MVT_f32_r(RetVT, Op0);
755 case MVT::f64: return fastEmit_ISD_FROUNDEVEN_MVT_f64_r(RetVT, Op0);
756 case MVT::v8f16: return fastEmit_ISD_FROUNDEVEN_MVT_v8f16_r(RetVT, Op0);
757 case MVT::v4f32: return fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(RetVT, Op0);
758 case MVT::v2f64: return fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(RetVT, Op0);
759 default: return Register();
760 }
761}
762
763// FastEmit functions for ISD::FSQRT.
764
765Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
766 if (RetVT.SimpleTy != MVT::f32)
767 return Register();
768 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F32, RC: &WebAssembly::F32RegClass, Op0);
769}
770
771Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
772 if (RetVT.SimpleTy != MVT::f64)
773 return Register();
774 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F64, RC: &WebAssembly::F64RegClass, Op0);
775}
776
777Register fastEmit_ISD_FSQRT_MVT_v8f16_r(MVT RetVT, Register Op0) {
778 if (RetVT.SimpleTy != MVT::v8f16)
779 return Register();
780 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
781 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F16x8, RC: &WebAssembly::V128RegClass, Op0);
782 }
783 return Register();
784}
785
786Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
787 if (RetVT.SimpleTy != MVT::v4f32)
788 return Register();
789 if ((Subtarget->hasSIMD128())) {
790 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
791 }
792 return Register();
793}
794
795Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
796 if (RetVT.SimpleTy != MVT::v2f64)
797 return Register();
798 if ((Subtarget->hasSIMD128())) {
799 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
800 }
801 return Register();
802}
803
804Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
805 switch (VT.SimpleTy) {
806 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
807 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
808 case MVT::v8f16: return fastEmit_ISD_FSQRT_MVT_v8f16_r(RetVT, Op0);
809 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
810 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
811 default: return Register();
812 }
813}
814
815// FastEmit functions for ISD::FTRUNC.
816
817Register fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, Register Op0) {
818 if (RetVT.SimpleTy != MVT::f32)
819 return Register();
820 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F32, RC: &WebAssembly::F32RegClass, Op0);
821}
822
823Register fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, Register Op0) {
824 if (RetVT.SimpleTy != MVT::f64)
825 return Register();
826 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F64, RC: &WebAssembly::F64RegClass, Op0);
827}
828
829Register fastEmit_ISD_FTRUNC_MVT_v8f16_r(MVT RetVT, Register Op0) {
830 if (RetVT.SimpleTy != MVT::v8f16)
831 return Register();
832 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
833 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F16x8, RC: &WebAssembly::V128RegClass, Op0);
834 }
835 return Register();
836}
837
838Register fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, Register Op0) {
839 if (RetVT.SimpleTy != MVT::v4f32)
840 return Register();
841 if ((Subtarget->hasSIMD128())) {
842 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F32x4, RC: &WebAssembly::V128RegClass, Op0);
843 }
844 return Register();
845}
846
847Register fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, Register Op0) {
848 if (RetVT.SimpleTy != MVT::v2f64)
849 return Register();
850 if ((Subtarget->hasSIMD128())) {
851 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F64x2, RC: &WebAssembly::V128RegClass, Op0);
852 }
853 return Register();
854}
855
856Register fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, Register Op0) {
857 switch (VT.SimpleTy) {
858 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0);
859 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0);
860 case MVT::v8f16: return fastEmit_ISD_FTRUNC_MVT_v8f16_r(RetVT, Op0);
861 case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0);
862 case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0);
863 default: return Register();
864 }
865}
866
867// FastEmit functions for ISD::SCALAR_TO_VECTOR.
868
869Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v16i8_r(Register Op0) {
870 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
871}
872
873Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v8i16_r(Register Op0) {
874 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I16x8, RC: &WebAssembly::V128RegClass, Op0);
875}
876
877Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(Register Op0) {
878 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I32x4, RC: &WebAssembly::V128RegClass, Op0);
879}
880
881Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, Register Op0) {
882switch (RetVT.SimpleTy) {
883 case MVT::v16i8: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v16i8_r(Op0);
884 case MVT::v8i16: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v8i16_r(Op0);
885 case MVT::v4i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(Op0);
886 default: return Register();
887}
888}
889
890Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(MVT RetVT, Register Op0) {
891 if (RetVT.SimpleTy != MVT::v2i64)
892 return Register();
893 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I64x2, RC: &WebAssembly::V128RegClass, Op0);
894}
895
896Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, Register Op0) {
897 if (RetVT.SimpleTy != MVT::v4f32)
898 return Register();
899 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
900}
901
902Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(MVT RetVT, Register Op0) {
903 if (RetVT.SimpleTy != MVT::v2f64)
904 return Register();
905 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
906}
907
908Register fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, Register Op0) {
909 switch (VT.SimpleTy) {
910 case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0);
911 case MVT::i64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(RetVT, Op0);
912 case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0);
913 case MVT::f64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(RetVT, Op0);
914 default: return Register();
915 }
916}
917
918// FastEmit functions for ISD::SIGN_EXTEND.
919
920Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
921 if (RetVT.SimpleTy != MVT::i64)
922 return Register();
923 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_S_I32, RC: &WebAssembly::I64RegClass, Op0);
924}
925
926Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
927 switch (VT.SimpleTy) {
928 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
929 default: return Register();
930 }
931}
932
933// FastEmit functions for ISD::SINT_TO_FP.
934
935Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
936 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_S_I32, RC: &WebAssembly::F32RegClass, Op0);
937}
938
939Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
940 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_S_I32, RC: &WebAssembly::F64RegClass, Op0);
941}
942
943Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
944switch (RetVT.SimpleTy) {
945 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
946 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
947 default: return Register();
948}
949}
950
951Register fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Register Op0) {
952 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_S_I64, RC: &WebAssembly::F32RegClass, Op0);
953}
954
955Register fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Register Op0) {
956 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_S_I64, RC: &WebAssembly::F64RegClass, Op0);
957}
958
959Register fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
960switch (RetVT.SimpleTy) {
961 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0);
962 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0);
963 default: return Register();
964}
965}
966
967Register fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, Register Op0) {
968 if (RetVT.SimpleTy != MVT::v8f16)
969 return Register();
970 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
971 return fastEmitInst_r(MachineInstOpcode: WebAssembly::sint_to_fp_F16x8, RC: &WebAssembly::V128RegClass, Op0);
972 }
973 return Register();
974}
975
976Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
977 if (RetVT.SimpleTy != MVT::v4f32)
978 return Register();
979 if ((Subtarget->hasSIMD128())) {
980 return fastEmitInst_r(MachineInstOpcode: WebAssembly::sint_to_fp_F32x4, RC: &WebAssembly::V128RegClass, Op0);
981 }
982 return Register();
983}
984
985Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
986 switch (VT.SimpleTy) {
987 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
988 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
989 case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0);
990 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
991 default: return Register();
992 }
993}
994
995// FastEmit functions for ISD::SPLAT_VECTOR.
996
997Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v16i8_r(Register Op0) {
998 if ((Subtarget->hasSIMD128())) {
999 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
1000 }
1001 return Register();
1002}
1003
1004Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v8i16_r(Register Op0) {
1005 if ((Subtarget->hasSIMD128())) {
1006 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1007 }
1008 return Register();
1009}
1010
1011Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v4i32_r(Register Op0) {
1012 if ((Subtarget->hasSIMD128())) {
1013 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1014 }
1015 return Register();
1016}
1017
1018Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(MVT RetVT, Register Op0) {
1019switch (RetVT.SimpleTy) {
1020 case MVT::v16i8: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v16i8_r(Op0);
1021 case MVT::v8i16: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v8i16_r(Op0);
1022 case MVT::v4i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v4i32_r(Op0);
1023 default: return Register();
1024}
1025}
1026
1027Register fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(MVT RetVT, Register Op0) {
1028 if (RetVT.SimpleTy != MVT::v2i64)
1029 return Register();
1030 if ((Subtarget->hasSIMD128())) {
1031 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1032 }
1033 return Register();
1034}
1035
1036Register fastEmit_ISD_SPLAT_VECTOR_MVT_f32_r(MVT RetVT, Register Op0) {
1037 if (RetVT.SimpleTy != MVT::v4f32)
1038 return Register();
1039 if ((Subtarget->hasSIMD128())) {
1040 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1041 }
1042 return Register();
1043}
1044
1045Register fastEmit_ISD_SPLAT_VECTOR_MVT_f64_r(MVT RetVT, Register Op0) {
1046 if (RetVT.SimpleTy != MVT::v2f64)
1047 return Register();
1048 if ((Subtarget->hasSIMD128())) {
1049 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1050 }
1051 return Register();
1052}
1053
1054Register fastEmit_ISD_SPLAT_VECTOR_r(MVT VT, MVT RetVT, Register Op0) {
1055 switch (VT.SimpleTy) {
1056 case MVT::i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(RetVT, Op0);
1057 case MVT::i64: return fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(RetVT, Op0);
1058 case MVT::f32: return fastEmit_ISD_SPLAT_VECTOR_MVT_f32_r(RetVT, Op0);
1059 case MVT::f64: return fastEmit_ISD_SPLAT_VECTOR_MVT_f64_r(RetVT, Op0);
1060 default: return Register();
1061 }
1062}
1063
1064// FastEmit functions for ISD::TRUNCATE.
1065
1066Register fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, Register Op0) {
1067 if (RetVT.SimpleTy != MVT::i32)
1068 return Register();
1069 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_WRAP_I64, RC: &WebAssembly::I32RegClass, Op0);
1070}
1071
1072Register fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, Register Op0) {
1073 switch (VT.SimpleTy) {
1074 case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0);
1075 default: return Register();
1076 }
1077}
1078
1079// FastEmit functions for ISD::UINT_TO_FP.
1080
1081Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1082 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_U_I32, RC: &WebAssembly::F32RegClass, Op0);
1083}
1084
1085Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1086 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_U_I32, RC: &WebAssembly::F64RegClass, Op0);
1087}
1088
1089Register fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1090switch (RetVT.SimpleTy) {
1091 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1092 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1093 default: return Register();
1094}
1095}
1096
1097Register fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Register Op0) {
1098 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_U_I64, RC: &WebAssembly::F32RegClass, Op0);
1099}
1100
1101Register fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Register Op0) {
1102 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_U_I64, RC: &WebAssembly::F64RegClass, Op0);
1103}
1104
1105Register fastEmit_ISD_UINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
1106switch (RetVT.SimpleTy) {
1107 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0);
1108 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Op0);
1109 default: return Register();
1110}
1111}
1112
1113Register fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, Register Op0) {
1114 if (RetVT.SimpleTy != MVT::v8f16)
1115 return Register();
1116 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1117 return fastEmitInst_r(MachineInstOpcode: WebAssembly::uint_to_fp_F16x8, RC: &WebAssembly::V128RegClass, Op0);
1118 }
1119 return Register();
1120}
1121
1122Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1123 if (RetVT.SimpleTy != MVT::v4f32)
1124 return Register();
1125 if ((Subtarget->hasSIMD128())) {
1126 return fastEmitInst_r(MachineInstOpcode: WebAssembly::uint_to_fp_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1127 }
1128 return Register();
1129}
1130
1131Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1132 switch (VT.SimpleTy) {
1133 case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1134 case MVT::i64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_r(RetVT, Op0);
1135 case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0);
1136 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1137 default: return Register();
1138 }
1139}
1140
1141// FastEmit functions for ISD::ZERO_EXTEND.
1142
1143Register fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
1144 if (RetVT.SimpleTy != MVT::i64)
1145 return Register();
1146 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_U_I32, RC: &WebAssembly::I64RegClass, Op0);
1147}
1148
1149Register fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
1150 switch (VT.SimpleTy) {
1151 case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(RetVT, Op0);
1152 default: return Register();
1153 }
1154}
1155
1156// FastEmit functions for WebAssemblyISD::BR_TABLE.
1157
1158Register fastEmit_WebAssemblyISD_BR_TABLE_MVT_i32_r(MVT RetVT, Register Op0) {
1159 if (RetVT.SimpleTy != MVT::isVoid)
1160 return Register();
1161 return fastEmitInst_r(MachineInstOpcode: WebAssembly::BR_TABLE_I32, RC: &WebAssembly::I32RegClass, Op0);
1162}
1163
1164Register fastEmit_WebAssemblyISD_BR_TABLE_MVT_i64_r(MVT RetVT, Register Op0) {
1165 if (RetVT.SimpleTy != MVT::isVoid)
1166 return Register();
1167 return fastEmitInst_r(MachineInstOpcode: WebAssembly::BR_TABLE_I64, RC: &WebAssembly::I64RegClass, Op0);
1168}
1169
1170Register fastEmit_WebAssemblyISD_BR_TABLE_r(MVT VT, MVT RetVT, Register Op0) {
1171 switch (VT.SimpleTy) {
1172 case MVT::i32: return fastEmit_WebAssemblyISD_BR_TABLE_MVT_i32_r(RetVT, Op0);
1173 case MVT::i64: return fastEmit_WebAssemblyISD_BR_TABLE_MVT_i64_r(RetVT, Op0);
1174 default: return Register();
1175 }
1176}
1177
1178// FastEmit functions for WebAssemblyISD::CONVERT_LOW_S.
1179
1180Register fastEmit_WebAssemblyISD_CONVERT_LOW_S_MVT_v4i32_r(MVT RetVT, Register Op0) {
1181 if (RetVT.SimpleTy != MVT::v2f64)
1182 return Register();
1183 if ((Subtarget->hasSIMD128())) {
1184 return fastEmitInst_r(MachineInstOpcode: WebAssembly::convert_low_s_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1185 }
1186 return Register();
1187}
1188
1189Register fastEmit_WebAssemblyISD_CONVERT_LOW_S_r(MVT VT, MVT RetVT, Register Op0) {
1190 switch (VT.SimpleTy) {
1191 case MVT::v4i32: return fastEmit_WebAssemblyISD_CONVERT_LOW_S_MVT_v4i32_r(RetVT, Op0);
1192 default: return Register();
1193 }
1194}
1195
1196// FastEmit functions for WebAssemblyISD::CONVERT_LOW_U.
1197
1198Register fastEmit_WebAssemblyISD_CONVERT_LOW_U_MVT_v4i32_r(MVT RetVT, Register Op0) {
1199 if (RetVT.SimpleTy != MVT::v2f64)
1200 return Register();
1201 if ((Subtarget->hasSIMD128())) {
1202 return fastEmitInst_r(MachineInstOpcode: WebAssembly::convert_low_u_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1203 }
1204 return Register();
1205}
1206
1207Register fastEmit_WebAssemblyISD_CONVERT_LOW_U_r(MVT VT, MVT RetVT, Register Op0) {
1208 switch (VT.SimpleTy) {
1209 case MVT::v4i32: return fastEmit_WebAssemblyISD_CONVERT_LOW_U_MVT_v4i32_r(RetVT, Op0);
1210 default: return Register();
1211 }
1212}
1213
1214// FastEmit functions for WebAssemblyISD::DEMOTE_ZERO.
1215
1216Register fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v4f32_r(MVT RetVT, Register Op0) {
1217 if (RetVT.SimpleTy != MVT::v8f16)
1218 return Register();
1219 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1220 return fastEmitInst_r(MachineInstOpcode: WebAssembly::demote_zero_F16x8, RC: &WebAssembly::V128RegClass, Op0);
1221 }
1222 return Register();
1223}
1224
1225Register fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v2f64_r(MVT RetVT, Register Op0) {
1226 if (RetVT.SimpleTy != MVT::v4f32)
1227 return Register();
1228 if ((Subtarget->hasSIMD128())) {
1229 return fastEmitInst_r(MachineInstOpcode: WebAssembly::demote_zero_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1230 }
1231 return Register();
1232}
1233
1234Register fastEmit_WebAssemblyISD_DEMOTE_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1235 switch (VT.SimpleTy) {
1236 case MVT::v4f32: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v4f32_r(RetVT, Op0);
1237 case MVT::v2f64: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v2f64_r(RetVT, Op0);
1238 default: return Register();
1239 }
1240}
1241
1242// FastEmit functions for WebAssemblyISD::EXTEND_HIGH_S.
1243
1244Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v16i8_r(MVT RetVT, Register Op0) {
1245 if (RetVT.SimpleTy != MVT::v8i16)
1246 return Register();
1247 if ((Subtarget->hasSIMD128())) {
1248 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1249 }
1250 return Register();
1251}
1252
1253Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v8i16_r(MVT RetVT, Register Op0) {
1254 if (RetVT.SimpleTy != MVT::v4i32)
1255 return Register();
1256 if ((Subtarget->hasSIMD128())) {
1257 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1258 }
1259 return Register();
1260}
1261
1262Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v4i32_r(MVT RetVT, Register Op0) {
1263 if (RetVT.SimpleTy != MVT::v2i64)
1264 return Register();
1265 if ((Subtarget->hasSIMD128())) {
1266 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1267 }
1268 return Register();
1269}
1270
1271Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_r(MVT VT, MVT RetVT, Register Op0) {
1272 switch (VT.SimpleTy) {
1273 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v16i8_r(RetVT, Op0);
1274 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v8i16_r(RetVT, Op0);
1275 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v4i32_r(RetVT, Op0);
1276 default: return Register();
1277 }
1278}
1279
1280// FastEmit functions for WebAssemblyISD::EXTEND_HIGH_U.
1281
1282Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v16i8_r(MVT RetVT, Register Op0) {
1283 if (RetVT.SimpleTy != MVT::v8i16)
1284 return Register();
1285 if ((Subtarget->hasSIMD128())) {
1286 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1287 }
1288 return Register();
1289}
1290
1291Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v8i16_r(MVT RetVT, Register Op0) {
1292 if (RetVT.SimpleTy != MVT::v4i32)
1293 return Register();
1294 if ((Subtarget->hasSIMD128())) {
1295 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1296 }
1297 return Register();
1298}
1299
1300Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v4i32_r(MVT RetVT, Register Op0) {
1301 if (RetVT.SimpleTy != MVT::v2i64)
1302 return Register();
1303 if ((Subtarget->hasSIMD128())) {
1304 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1305 }
1306 return Register();
1307}
1308
1309Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_r(MVT VT, MVT RetVT, Register Op0) {
1310 switch (VT.SimpleTy) {
1311 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v16i8_r(RetVT, Op0);
1312 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v8i16_r(RetVT, Op0);
1313 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v4i32_r(RetVT, Op0);
1314 default: return Register();
1315 }
1316}
1317
1318// FastEmit functions for WebAssemblyISD::EXTEND_LOW_S.
1319
1320Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v16i8_r(MVT RetVT, Register Op0) {
1321 if (RetVT.SimpleTy != MVT::v8i16)
1322 return Register();
1323 if ((Subtarget->hasSIMD128())) {
1324 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1325 }
1326 return Register();
1327}
1328
1329Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v8i16_r(MVT RetVT, Register Op0) {
1330 if (RetVT.SimpleTy != MVT::v4i32)
1331 return Register();
1332 if ((Subtarget->hasSIMD128())) {
1333 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1334 }
1335 return Register();
1336}
1337
1338Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v4i32_r(MVT RetVT, Register Op0) {
1339 if (RetVT.SimpleTy != MVT::v2i64)
1340 return Register();
1341 if ((Subtarget->hasSIMD128())) {
1342 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1343 }
1344 return Register();
1345}
1346
1347Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_r(MVT VT, MVT RetVT, Register Op0) {
1348 switch (VT.SimpleTy) {
1349 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v16i8_r(RetVT, Op0);
1350 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v8i16_r(RetVT, Op0);
1351 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v4i32_r(RetVT, Op0);
1352 default: return Register();
1353 }
1354}
1355
1356// FastEmit functions for WebAssemblyISD::EXTEND_LOW_U.
1357
1358Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v16i8_r(MVT RetVT, Register Op0) {
1359 if (RetVT.SimpleTy != MVT::v8i16)
1360 return Register();
1361 if ((Subtarget->hasSIMD128())) {
1362 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1363 }
1364 return Register();
1365}
1366
1367Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v8i16_r(MVT RetVT, Register Op0) {
1368 if (RetVT.SimpleTy != MVT::v4i32)
1369 return Register();
1370 if ((Subtarget->hasSIMD128())) {
1371 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1372 }
1373 return Register();
1374}
1375
1376Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v4i32_r(MVT RetVT, Register Op0) {
1377 if (RetVT.SimpleTy != MVT::v2i64)
1378 return Register();
1379 if ((Subtarget->hasSIMD128())) {
1380 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1381 }
1382 return Register();
1383}
1384
1385Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_r(MVT VT, MVT RetVT, Register Op0) {
1386 switch (VT.SimpleTy) {
1387 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v16i8_r(RetVT, Op0);
1388 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v8i16_r(RetVT, Op0);
1389 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v4i32_r(RetVT, Op0);
1390 default: return Register();
1391 }
1392}
1393
1394// FastEmit functions for WebAssemblyISD::EXT_ADD_PAIRWISE_S.
1395
1396Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v16i8_r(MVT RetVT, Register Op0) {
1397 if (RetVT.SimpleTy != MVT::v8i16)
1398 return Register();
1399 if ((Subtarget->hasSIMD128())) {
1400 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1401 }
1402 return Register();
1403}
1404
1405Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v8i16_r(MVT RetVT, Register Op0) {
1406 if (RetVT.SimpleTy != MVT::v4i32)
1407 return Register();
1408 if ((Subtarget->hasSIMD128())) {
1409 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1410 }
1411 return Register();
1412}
1413
1414Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_r(MVT VT, MVT RetVT, Register Op0) {
1415 switch (VT.SimpleTy) {
1416 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v16i8_r(RetVT, Op0);
1417 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v8i16_r(RetVT, Op0);
1418 default: return Register();
1419 }
1420}
1421
1422// FastEmit functions for WebAssemblyISD::EXT_ADD_PAIRWISE_U.
1423
1424Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v16i8_r(MVT RetVT, Register Op0) {
1425 if (RetVT.SimpleTy != MVT::v8i16)
1426 return Register();
1427 if ((Subtarget->hasSIMD128())) {
1428 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1429 }
1430 return Register();
1431}
1432
1433Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v8i16_r(MVT RetVT, Register Op0) {
1434 if (RetVT.SimpleTy != MVT::v4i32)
1435 return Register();
1436 if ((Subtarget->hasSIMD128())) {
1437 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1438 }
1439 return Register();
1440}
1441
1442Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_r(MVT VT, MVT RetVT, Register Op0) {
1443 switch (VT.SimpleTy) {
1444 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v16i8_r(RetVT, Op0);
1445 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v8i16_r(RetVT, Op0);
1446 default: return Register();
1447 }
1448}
1449
1450// FastEmit functions for WebAssemblyISD::PROMOTE_LOW.
1451
1452Register fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v8i16_r(MVT RetVT, Register Op0) {
1453 if (RetVT.SimpleTy != MVT::v4f32)
1454 return Register();
1455 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1456 return fastEmitInst_r(MachineInstOpcode: WebAssembly::promote_low_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1457 }
1458 return Register();
1459}
1460
1461Register fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v4f32_r(MVT RetVT, Register Op0) {
1462 if (RetVT.SimpleTy != MVT::v2f64)
1463 return Register();
1464 if ((Subtarget->hasSIMD128())) {
1465 return fastEmitInst_r(MachineInstOpcode: WebAssembly::promote_low_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1466 }
1467 return Register();
1468}
1469
1470Register fastEmit_WebAssemblyISD_PROMOTE_LOW_r(MVT VT, MVT RetVT, Register Op0) {
1471 switch (VT.SimpleTy) {
1472 case MVT::v8i16: return fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v8i16_r(RetVT, Op0);
1473 case MVT::v4f32: return fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v4f32_r(RetVT, Op0);
1474 default: return Register();
1475 }
1476}
1477
1478// FastEmit functions for WebAssemblyISD::TRUNC_SAT_ZERO_S.
1479
1480Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_MVT_v2f64_r(MVT RetVT, Register Op0) {
1481 if (RetVT.SimpleTy != MVT::v4i32)
1482 return Register();
1483 if ((Subtarget->hasSIMD128())) {
1484 return fastEmitInst_r(MachineInstOpcode: WebAssembly::trunc_sat_zero_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1485 }
1486 return Register();
1487}
1488
1489Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_r(MVT VT, MVT RetVT, Register Op0) {
1490 switch (VT.SimpleTy) {
1491 case MVT::v2f64: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_MVT_v2f64_r(RetVT, Op0);
1492 default: return Register();
1493 }
1494}
1495
1496// FastEmit functions for WebAssemblyISD::TRUNC_SAT_ZERO_U.
1497
1498Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_MVT_v2f64_r(MVT RetVT, Register Op0) {
1499 if (RetVT.SimpleTy != MVT::v4i32)
1500 return Register();
1501 if ((Subtarget->hasSIMD128())) {
1502 return fastEmitInst_r(MachineInstOpcode: WebAssembly::trunc_sat_zero_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1503 }
1504 return Register();
1505}
1506
1507Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_r(MVT VT, MVT RetVT, Register Op0) {
1508 switch (VT.SimpleTy) {
1509 case MVT::v2f64: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_MVT_v2f64_r(RetVT, Op0);
1510 default: return Register();
1511 }
1512}
1513
1514// Top-level FastEmit function.
1515
1516Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
1517 switch (Opcode) {
1518 case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0);
1519 case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0);
1520 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1521 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1522 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1523 case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0);
1524 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1525 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0);
1526 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0);
1527 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0);
1528 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1529 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1530 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1531 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1532 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1533 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1534 case ISD::FROUNDEVEN: return fastEmit_ISD_FROUNDEVEN_r(VT, RetVT, Op0);
1535 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1536 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0);
1537 case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0);
1538 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1539 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1540 case ISD::SPLAT_VECTOR: return fastEmit_ISD_SPLAT_VECTOR_r(VT, RetVT, Op0);
1541 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0);
1542 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1543 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0);
1544 case WebAssemblyISD::BR_TABLE: return fastEmit_WebAssemblyISD_BR_TABLE_r(VT, RetVT, Op0);
1545 case WebAssemblyISD::CONVERT_LOW_S: return fastEmit_WebAssemblyISD_CONVERT_LOW_S_r(VT, RetVT, Op0);
1546 case WebAssemblyISD::CONVERT_LOW_U: return fastEmit_WebAssemblyISD_CONVERT_LOW_U_r(VT, RetVT, Op0);
1547 case WebAssemblyISD::DEMOTE_ZERO: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_r(VT, RetVT, Op0);
1548 case WebAssemblyISD::EXTEND_HIGH_S: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_r(VT, RetVT, Op0);
1549 case WebAssemblyISD::EXTEND_HIGH_U: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_r(VT, RetVT, Op0);
1550 case WebAssemblyISD::EXTEND_LOW_S: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_r(VT, RetVT, Op0);
1551 case WebAssemblyISD::EXTEND_LOW_U: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_r(VT, RetVT, Op0);
1552 case WebAssemblyISD::EXT_ADD_PAIRWISE_S: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_r(VT, RetVT, Op0);
1553 case WebAssemblyISD::EXT_ADD_PAIRWISE_U: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_r(VT, RetVT, Op0);
1554 case WebAssemblyISD::PROMOTE_LOW: return fastEmit_WebAssemblyISD_PROMOTE_LOW_r(VT, RetVT, Op0);
1555 case WebAssemblyISD::TRUNC_SAT_ZERO_S: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_r(VT, RetVT, Op0);
1556 case WebAssemblyISD::TRUNC_SAT_ZERO_U: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_r(VT, RetVT, Op0);
1557 default: return Register();
1558 }
1559}
1560
1561// FastEmit functions for ISD::ADD.
1562
1563Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1564 if (RetVT.SimpleTy != MVT::i32)
1565 return Register();
1566 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
1567}
1568
1569Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1570 if (RetVT.SimpleTy != MVT::i64)
1571 return Register();
1572 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
1573}
1574
1575Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1576 if (RetVT.SimpleTy != MVT::v16i8)
1577 return Register();
1578 if ((Subtarget->hasSIMD128())) {
1579 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
1580 }
1581 return Register();
1582}
1583
1584Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1585 if (RetVT.SimpleTy != MVT::v8i16)
1586 return Register();
1587 if ((Subtarget->hasSIMD128())) {
1588 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1589 }
1590 return Register();
1591}
1592
1593Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1594 if (RetVT.SimpleTy != MVT::v4i32)
1595 return Register();
1596 if ((Subtarget->hasSIMD128())) {
1597 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1598 }
1599 return Register();
1600}
1601
1602Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1603 if (RetVT.SimpleTy != MVT::v2i64)
1604 return Register();
1605 if ((Subtarget->hasSIMD128())) {
1606 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1607 }
1608 return Register();
1609}
1610
1611Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1612 switch (VT.SimpleTy) {
1613 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1614 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1615 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1616 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1617 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1618 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1619 default: return Register();
1620 }
1621}
1622
1623// FastEmit functions for ISD::AND.
1624
1625Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1626 if (RetVT.SimpleTy != MVT::i32)
1627 return Register();
1628 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
1629}
1630
1631Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1632 if (RetVT.SimpleTy != MVT::i64)
1633 return Register();
1634 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
1635}
1636
1637Register fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1638 if (RetVT.SimpleTy != MVT::v16i8)
1639 return Register();
1640 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1641}
1642
1643Register fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1644 if (RetVT.SimpleTy != MVT::v8i16)
1645 return Register();
1646 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1647}
1648
1649Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1650 if (RetVT.SimpleTy != MVT::v4i32)
1651 return Register();
1652 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1653}
1654
1655Register fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1656 if (RetVT.SimpleTy != MVT::v2i64)
1657 return Register();
1658 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1659}
1660
1661Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1662 switch (VT.SimpleTy) {
1663 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1664 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1665 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1666 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1667 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1668 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1669 default: return Register();
1670 }
1671}
1672
1673// FastEmit functions for ISD::AVGCEILU.
1674
1675Register fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1676 if (RetVT.SimpleTy != MVT::v16i8)
1677 return Register();
1678 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AVGR_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
1679}
1680
1681Register fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1682 if (RetVT.SimpleTy != MVT::v8i16)
1683 return Register();
1684 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AVGR_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1685}
1686
1687Register fastEmit_ISD_AVGCEILU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1688 switch (VT.SimpleTy) {
1689 case MVT::v16i8: return fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(RetVT, Op0, Op1);
1690 case MVT::v8i16: return fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(RetVT, Op0, Op1);
1691 default: return Register();
1692 }
1693}
1694
1695// FastEmit functions for ISD::FADD.
1696
1697Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1698 if (RetVT.SimpleTy != MVT::f32)
1699 return Register();
1700 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1701}
1702
1703Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1704 if (RetVT.SimpleTy != MVT::f64)
1705 return Register();
1706 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1707}
1708
1709Register fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1710 if (RetVT.SimpleTy != MVT::v8f16)
1711 return Register();
1712 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1713 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1714 }
1715 return Register();
1716}
1717
1718Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1719 if (RetVT.SimpleTy != MVT::v4f32)
1720 return Register();
1721 if ((Subtarget->hasSIMD128())) {
1722 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1723 }
1724 return Register();
1725}
1726
1727Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1728 if (RetVT.SimpleTy != MVT::v2f64)
1729 return Register();
1730 if ((Subtarget->hasSIMD128())) {
1731 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1732 }
1733 return Register();
1734}
1735
1736Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1737 switch (VT.SimpleTy) {
1738 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1739 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1740 case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op1);
1741 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1742 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1743 default: return Register();
1744 }
1745}
1746
1747// FastEmit functions for ISD::FCOPYSIGN.
1748
1749Register fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1750 if (RetVT.SimpleTy != MVT::f32)
1751 return Register();
1752 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::COPYSIGN_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1753}
1754
1755Register fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1756 if (RetVT.SimpleTy != MVT::f64)
1757 return Register();
1758 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::COPYSIGN_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1759}
1760
1761Register fastEmit_ISD_FCOPYSIGN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1762 switch (VT.SimpleTy) {
1763 case MVT::f32: return fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(RetVT, Op0, Op1);
1764 case MVT::f64: return fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(RetVT, Op0, Op1);
1765 default: return Register();
1766 }
1767}
1768
1769// FastEmit functions for ISD::FDIV.
1770
1771Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1772 if (RetVT.SimpleTy != MVT::f32)
1773 return Register();
1774 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1775}
1776
1777Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1778 if (RetVT.SimpleTy != MVT::f64)
1779 return Register();
1780 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1781}
1782
1783Register fastEmit_ISD_FDIV_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1784 if (RetVT.SimpleTy != MVT::v8f16)
1785 return Register();
1786 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1787 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1788 }
1789 return Register();
1790}
1791
1792Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1793 if (RetVT.SimpleTy != MVT::v4f32)
1794 return Register();
1795 if ((Subtarget->hasSIMD128())) {
1796 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1797 }
1798 return Register();
1799}
1800
1801Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1802 if (RetVT.SimpleTy != MVT::v2f64)
1803 return Register();
1804 if ((Subtarget->hasSIMD128())) {
1805 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1806 }
1807 return Register();
1808}
1809
1810Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1811 switch (VT.SimpleTy) {
1812 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1813 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1814 case MVT::v8f16: return fastEmit_ISD_FDIV_MVT_v8f16_rr(RetVT, Op0, Op1);
1815 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1816 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1817 default: return Register();
1818 }
1819}
1820
1821// FastEmit functions for ISD::FMAXIMUM.
1822
1823Register fastEmit_ISD_FMAXIMUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1824 if (RetVT.SimpleTy != MVT::f32)
1825 return Register();
1826 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1827}
1828
1829Register fastEmit_ISD_FMAXIMUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1830 if (RetVT.SimpleTy != MVT::f64)
1831 return Register();
1832 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1833}
1834
1835Register fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1836 if (RetVT.SimpleTy != MVT::v8f16)
1837 return Register();
1838 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1839 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1840 }
1841 return Register();
1842}
1843
1844Register fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1845 if (RetVT.SimpleTy != MVT::v4f32)
1846 return Register();
1847 if ((Subtarget->hasSIMD128())) {
1848 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1849 }
1850 return Register();
1851}
1852
1853Register fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1854 if (RetVT.SimpleTy != MVT::v2f64)
1855 return Register();
1856 if ((Subtarget->hasSIMD128())) {
1857 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1858 }
1859 return Register();
1860}
1861
1862Register fastEmit_ISD_FMAXIMUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1863 switch (VT.SimpleTy) {
1864 case MVT::f32: return fastEmit_ISD_FMAXIMUM_MVT_f32_rr(RetVT, Op0, Op1);
1865 case MVT::f64: return fastEmit_ISD_FMAXIMUM_MVT_f64_rr(RetVT, Op0, Op1);
1866 case MVT::v8f16: return fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(RetVT, Op0, Op1);
1867 case MVT::v4f32: return fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(RetVT, Op0, Op1);
1868 case MVT::v2f64: return fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(RetVT, Op0, Op1);
1869 default: return Register();
1870 }
1871}
1872
1873// FastEmit functions for ISD::FMINIMUM.
1874
1875Register fastEmit_ISD_FMINIMUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1876 if (RetVT.SimpleTy != MVT::f32)
1877 return Register();
1878 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1879}
1880
1881Register fastEmit_ISD_FMINIMUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1882 if (RetVT.SimpleTy != MVT::f64)
1883 return Register();
1884 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1885}
1886
1887Register fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1888 if (RetVT.SimpleTy != MVT::v8f16)
1889 return Register();
1890 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1891 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1892 }
1893 return Register();
1894}
1895
1896Register fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1897 if (RetVT.SimpleTy != MVT::v4f32)
1898 return Register();
1899 if ((Subtarget->hasSIMD128())) {
1900 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1901 }
1902 return Register();
1903}
1904
1905Register fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1906 if (RetVT.SimpleTy != MVT::v2f64)
1907 return Register();
1908 if ((Subtarget->hasSIMD128())) {
1909 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1910 }
1911 return Register();
1912}
1913
1914Register fastEmit_ISD_FMINIMUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1915 switch (VT.SimpleTy) {
1916 case MVT::f32: return fastEmit_ISD_FMINIMUM_MVT_f32_rr(RetVT, Op0, Op1);
1917 case MVT::f64: return fastEmit_ISD_FMINIMUM_MVT_f64_rr(RetVT, Op0, Op1);
1918 case MVT::v8f16: return fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(RetVT, Op0, Op1);
1919 case MVT::v4f32: return fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(RetVT, Op0, Op1);
1920 case MVT::v2f64: return fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(RetVT, Op0, Op1);
1921 default: return Register();
1922 }
1923}
1924
1925// FastEmit functions for ISD::FMUL.
1926
1927Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1928 if (RetVT.SimpleTy != MVT::f32)
1929 return Register();
1930 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1931}
1932
1933Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1934 if (RetVT.SimpleTy != MVT::f64)
1935 return Register();
1936 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1937}
1938
1939Register fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1940 if (RetVT.SimpleTy != MVT::v8f16)
1941 return Register();
1942 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1943 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1944 }
1945 return Register();
1946}
1947
1948Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1949 if (RetVT.SimpleTy != MVT::v4f32)
1950 return Register();
1951 if ((Subtarget->hasSIMD128())) {
1952 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1953 }
1954 return Register();
1955}
1956
1957Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1958 if (RetVT.SimpleTy != MVT::v2f64)
1959 return Register();
1960 if ((Subtarget->hasSIMD128())) {
1961 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1962 }
1963 return Register();
1964}
1965
1966Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1967 switch (VT.SimpleTy) {
1968 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1969 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1970 case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op1);
1971 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1972 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1973 default: return Register();
1974 }
1975}
1976
1977// FastEmit functions for ISD::FSUB.
1978
1979Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1980 if (RetVT.SimpleTy != MVT::f32)
1981 return Register();
1982 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1983}
1984
1985Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1986 if (RetVT.SimpleTy != MVT::f64)
1987 return Register();
1988 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1989}
1990
1991Register fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1992 if (RetVT.SimpleTy != MVT::v8f16)
1993 return Register();
1994 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1995 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1996 }
1997 return Register();
1998}
1999
2000Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
2001 if (RetVT.SimpleTy != MVT::v4f32)
2002 return Register();
2003 if ((Subtarget->hasSIMD128())) {
2004 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2005 }
2006 return Register();
2007}
2008
2009Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
2010 if (RetVT.SimpleTy != MVT::v2f64)
2011 return Register();
2012 if ((Subtarget->hasSIMD128())) {
2013 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2014 }
2015 return Register();
2016}
2017
2018Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2019 switch (VT.SimpleTy) {
2020 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
2021 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
2022 case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op1);
2023 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
2024 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
2025 default: return Register();
2026 }
2027}
2028
2029// FastEmit functions for ISD::MUL.
2030
2031Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2032 if (RetVT.SimpleTy != MVT::i32)
2033 return Register();
2034 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2035}
2036
2037Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2038 if (RetVT.SimpleTy != MVT::i64)
2039 return Register();
2040 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2041}
2042
2043Register fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2044 if (RetVT.SimpleTy != MVT::v8i16)
2045 return Register();
2046 if ((Subtarget->hasSIMD128())) {
2047 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2048 }
2049 return Register();
2050}
2051
2052Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2053 if (RetVT.SimpleTy != MVT::v4i32)
2054 return Register();
2055 if ((Subtarget->hasSIMD128())) {
2056 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2057 }
2058 return Register();
2059}
2060
2061Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2062 if (RetVT.SimpleTy != MVT::v2i64)
2063 return Register();
2064 if ((Subtarget->hasSIMD128())) {
2065 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2066 }
2067 return Register();
2068}
2069
2070Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2071 switch (VT.SimpleTy) {
2072 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
2073 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
2074 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
2075 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
2076 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
2077 default: return Register();
2078 }
2079}
2080
2081// FastEmit functions for ISD::OR.
2082
2083Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2084 if (RetVT.SimpleTy != MVT::i32)
2085 return Register();
2086 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2087}
2088
2089Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2090 if (RetVT.SimpleTy != MVT::i64)
2091 return Register();
2092 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2093}
2094
2095Register fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2096 if (RetVT.SimpleTy != MVT::v16i8)
2097 return Register();
2098 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2099}
2100
2101Register fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2102 if (RetVT.SimpleTy != MVT::v8i16)
2103 return Register();
2104 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2105}
2106
2107Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2108 if (RetVT.SimpleTy != MVT::v4i32)
2109 return Register();
2110 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2111}
2112
2113Register fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2114 if (RetVT.SimpleTy != MVT::v2i64)
2115 return Register();
2116 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2117}
2118
2119Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2120 switch (VT.SimpleTy) {
2121 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
2122 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
2123 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
2124 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
2125 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
2126 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
2127 default: return Register();
2128 }
2129}
2130
2131// FastEmit functions for ISD::ROTL.
2132
2133Register fastEmit_ISD_ROTL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2134 if (RetVT.SimpleTy != MVT::i32)
2135 return Register();
2136 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2137}
2138
2139Register fastEmit_ISD_ROTL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2140 if (RetVT.SimpleTy != MVT::i64)
2141 return Register();
2142 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2143}
2144
2145Register fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2146 switch (VT.SimpleTy) {
2147 case MVT::i32: return fastEmit_ISD_ROTL_MVT_i32_rr(RetVT, Op0, Op1);
2148 case MVT::i64: return fastEmit_ISD_ROTL_MVT_i64_rr(RetVT, Op0, Op1);
2149 default: return Register();
2150 }
2151}
2152
2153// FastEmit functions for ISD::ROTR.
2154
2155Register fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2156 if (RetVT.SimpleTy != MVT::i32)
2157 return Register();
2158 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2159}
2160
2161Register fastEmit_ISD_ROTR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2162 if (RetVT.SimpleTy != MVT::i64)
2163 return Register();
2164 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2165}
2166
2167Register fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2168 switch (VT.SimpleTy) {
2169 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
2170 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_rr(RetVT, Op0, Op1);
2171 default: return Register();
2172 }
2173}
2174
2175// FastEmit functions for ISD::SADDSAT.
2176
2177Register fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2178 if (RetVT.SimpleTy != MVT::v16i8)
2179 return Register();
2180 if ((Subtarget->hasSIMD128())) {
2181 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2182 }
2183 return Register();
2184}
2185
2186Register fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2187 if (RetVT.SimpleTy != MVT::v8i16)
2188 return Register();
2189 if ((Subtarget->hasSIMD128())) {
2190 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2191 }
2192 return Register();
2193}
2194
2195Register fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2196 switch (VT.SimpleTy) {
2197 case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2198 case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2199 default: return Register();
2200 }
2201}
2202
2203// FastEmit functions for ISD::SDIV.
2204
2205Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2206 if (RetVT.SimpleTy != MVT::i32)
2207 return Register();
2208 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2209}
2210
2211Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2212 if (RetVT.SimpleTy != MVT::i64)
2213 return Register();
2214 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2215}
2216
2217Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2218 switch (VT.SimpleTy) {
2219 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
2220 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
2221 default: return Register();
2222 }
2223}
2224
2225// FastEmit functions for ISD::SHL.
2226
2227Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2228 if (RetVT.SimpleTy != MVT::i32)
2229 return Register();
2230 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2231}
2232
2233Register fastEmit_ISD_SHL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2234 if (RetVT.SimpleTy != MVT::i64)
2235 return Register();
2236 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2237}
2238
2239Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2240 switch (VT.SimpleTy) {
2241 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
2242 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_rr(RetVT, Op0, Op1);
2243 default: return Register();
2244 }
2245}
2246
2247// FastEmit functions for ISD::SMAX.
2248
2249Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2250 if (RetVT.SimpleTy != MVT::v16i8)
2251 return Register();
2252 if ((Subtarget->hasSIMD128())) {
2253 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2254 }
2255 return Register();
2256}
2257
2258Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2259 if (RetVT.SimpleTy != MVT::v8i16)
2260 return Register();
2261 if ((Subtarget->hasSIMD128())) {
2262 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2263 }
2264 return Register();
2265}
2266
2267Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2268 if (RetVT.SimpleTy != MVT::v4i32)
2269 return Register();
2270 if ((Subtarget->hasSIMD128())) {
2271 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2272 }
2273 return Register();
2274}
2275
2276Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2277 switch (VT.SimpleTy) {
2278 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2279 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2280 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2281 default: return Register();
2282 }
2283}
2284
2285// FastEmit functions for ISD::SMIN.
2286
2287Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2288 if (RetVT.SimpleTy != MVT::v16i8)
2289 return Register();
2290 if ((Subtarget->hasSIMD128())) {
2291 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2292 }
2293 return Register();
2294}
2295
2296Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2297 if (RetVT.SimpleTy != MVT::v8i16)
2298 return Register();
2299 if ((Subtarget->hasSIMD128())) {
2300 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2301 }
2302 return Register();
2303}
2304
2305Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2306 if (RetVT.SimpleTy != MVT::v4i32)
2307 return Register();
2308 if ((Subtarget->hasSIMD128())) {
2309 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2310 }
2311 return Register();
2312}
2313
2314Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2315 switch (VT.SimpleTy) {
2316 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2317 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2318 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2319 default: return Register();
2320 }
2321}
2322
2323// FastEmit functions for ISD::SRA.
2324
2325Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2326 if (RetVT.SimpleTy != MVT::i32)
2327 return Register();
2328 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2329}
2330
2331Register fastEmit_ISD_SRA_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2332 if (RetVT.SimpleTy != MVT::i64)
2333 return Register();
2334 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2335}
2336
2337Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2338 switch (VT.SimpleTy) {
2339 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2340 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_rr(RetVT, Op0, Op1);
2341 default: return Register();
2342 }
2343}
2344
2345// FastEmit functions for ISD::SREM.
2346
2347Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2348 if (RetVT.SimpleTy != MVT::i32)
2349 return Register();
2350 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2351}
2352
2353Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2354 if (RetVT.SimpleTy != MVT::i64)
2355 return Register();
2356 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2357}
2358
2359Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2360 switch (VT.SimpleTy) {
2361 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2362 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2363 default: return Register();
2364 }
2365}
2366
2367// FastEmit functions for ISD::SRL.
2368
2369Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2370 if (RetVT.SimpleTy != MVT::i32)
2371 return Register();
2372 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2373}
2374
2375Register fastEmit_ISD_SRL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2376 if (RetVT.SimpleTy != MVT::i64)
2377 return Register();
2378 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2379}
2380
2381Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2382 switch (VT.SimpleTy) {
2383 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2384 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_rr(RetVT, Op0, Op1);
2385 default: return Register();
2386 }
2387}
2388
2389// FastEmit functions for ISD::SSUBSAT.
2390
2391Register fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2392 if (RetVT.SimpleTy != MVT::v16i8)
2393 return Register();
2394 if ((Subtarget->hasSIMD128())) {
2395 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2396 }
2397 return Register();
2398}
2399
2400Register fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2401 if (RetVT.SimpleTy != MVT::v8i16)
2402 return Register();
2403 if ((Subtarget->hasSIMD128())) {
2404 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2405 }
2406 return Register();
2407}
2408
2409Register fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2410 switch (VT.SimpleTy) {
2411 case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2412 case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2413 default: return Register();
2414 }
2415}
2416
2417// FastEmit functions for ISD::SUB.
2418
2419Register fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2420 if (RetVT.SimpleTy != MVT::i32)
2421 return Register();
2422 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2423}
2424
2425Register fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2426 if (RetVT.SimpleTy != MVT::i64)
2427 return Register();
2428 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2429}
2430
2431Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2432 if (RetVT.SimpleTy != MVT::v16i8)
2433 return Register();
2434 if ((Subtarget->hasSIMD128())) {
2435 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2436 }
2437 return Register();
2438}
2439
2440Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2441 if (RetVT.SimpleTy != MVT::v8i16)
2442 return Register();
2443 if ((Subtarget->hasSIMD128())) {
2444 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2445 }
2446 return Register();
2447}
2448
2449Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2450 if (RetVT.SimpleTy != MVT::v4i32)
2451 return Register();
2452 if ((Subtarget->hasSIMD128())) {
2453 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2454 }
2455 return Register();
2456}
2457
2458Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2459 if (RetVT.SimpleTy != MVT::v2i64)
2460 return Register();
2461 if ((Subtarget->hasSIMD128())) {
2462 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2463 }
2464 return Register();
2465}
2466
2467Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2468 switch (VT.SimpleTy) {
2469 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2470 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2471 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2472 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2473 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2474 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2475 default: return Register();
2476 }
2477}
2478
2479// FastEmit functions for ISD::UADDSAT.
2480
2481Register fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2482 if (RetVT.SimpleTy != MVT::v16i8)
2483 return Register();
2484 if ((Subtarget->hasSIMD128())) {
2485 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2486 }
2487 return Register();
2488}
2489
2490Register fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2491 if (RetVT.SimpleTy != MVT::v8i16)
2492 return Register();
2493 if ((Subtarget->hasSIMD128())) {
2494 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2495 }
2496 return Register();
2497}
2498
2499Register fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2500 switch (VT.SimpleTy) {
2501 case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2502 case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2503 default: return Register();
2504 }
2505}
2506
2507// FastEmit functions for ISD::UDIV.
2508
2509Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2510 if (RetVT.SimpleTy != MVT::i32)
2511 return Register();
2512 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2513}
2514
2515Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2516 if (RetVT.SimpleTy != MVT::i64)
2517 return Register();
2518 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2519}
2520
2521Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2522 switch (VT.SimpleTy) {
2523 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2524 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2525 default: return Register();
2526 }
2527}
2528
2529// FastEmit functions for ISD::UMAX.
2530
2531Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2532 if (RetVT.SimpleTy != MVT::v16i8)
2533 return Register();
2534 if ((Subtarget->hasSIMD128())) {
2535 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2536 }
2537 return Register();
2538}
2539
2540Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2541 if (RetVT.SimpleTy != MVT::v8i16)
2542 return Register();
2543 if ((Subtarget->hasSIMD128())) {
2544 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2545 }
2546 return Register();
2547}
2548
2549Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2550 if (RetVT.SimpleTy != MVT::v4i32)
2551 return Register();
2552 if ((Subtarget->hasSIMD128())) {
2553 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2554 }
2555 return Register();
2556}
2557
2558Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2559 switch (VT.SimpleTy) {
2560 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2561 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2562 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2563 default: return Register();
2564 }
2565}
2566
2567// FastEmit functions for ISD::UMIN.
2568
2569Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2570 if (RetVT.SimpleTy != MVT::v16i8)
2571 return Register();
2572 if ((Subtarget->hasSIMD128())) {
2573 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2574 }
2575 return Register();
2576}
2577
2578Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2579 if (RetVT.SimpleTy != MVT::v8i16)
2580 return Register();
2581 if ((Subtarget->hasSIMD128())) {
2582 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2583 }
2584 return Register();
2585}
2586
2587Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2588 if (RetVT.SimpleTy != MVT::v4i32)
2589 return Register();
2590 if ((Subtarget->hasSIMD128())) {
2591 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2592 }
2593 return Register();
2594}
2595
2596Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2597 switch (VT.SimpleTy) {
2598 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2599 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2600 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2601 default: return Register();
2602 }
2603}
2604
2605// FastEmit functions for ISD::UREM.
2606
2607Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2608 if (RetVT.SimpleTy != MVT::i32)
2609 return Register();
2610 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2611}
2612
2613Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2614 if (RetVT.SimpleTy != MVT::i64)
2615 return Register();
2616 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2617}
2618
2619Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2620 switch (VT.SimpleTy) {
2621 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
2622 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
2623 default: return Register();
2624 }
2625}
2626
2627// FastEmit functions for ISD::USUBSAT.
2628
2629Register fastEmit_ISD_USUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2630 if (RetVT.SimpleTy != MVT::v16i8)
2631 return Register();
2632 if ((Subtarget->hasSIMD128())) {
2633 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2634 }
2635 return Register();
2636}
2637
2638Register fastEmit_ISD_USUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2639 if (RetVT.SimpleTy != MVT::v8i16)
2640 return Register();
2641 if ((Subtarget->hasSIMD128())) {
2642 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2643 }
2644 return Register();
2645}
2646
2647Register fastEmit_ISD_USUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2648 switch (VT.SimpleTy) {
2649 case MVT::v16i8: return fastEmit_ISD_USUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2650 case MVT::v8i16: return fastEmit_ISD_USUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2651 default: return Register();
2652 }
2653}
2654
2655// FastEmit functions for ISD::XOR.
2656
2657Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2658 if (RetVT.SimpleTy != MVT::i32)
2659 return Register();
2660 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2661}
2662
2663Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2664 if (RetVT.SimpleTy != MVT::i64)
2665 return Register();
2666 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2667}
2668
2669Register fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2670 if (RetVT.SimpleTy != MVT::v16i8)
2671 return Register();
2672 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2673}
2674
2675Register fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2676 if (RetVT.SimpleTy != MVT::v8i16)
2677 return Register();
2678 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2679}
2680
2681Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2682 if (RetVT.SimpleTy != MVT::v4i32)
2683 return Register();
2684 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2685}
2686
2687Register fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2688 if (RetVT.SimpleTy != MVT::v2i64)
2689 return Register();
2690 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2691}
2692
2693Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2694 switch (VT.SimpleTy) {
2695 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
2696 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
2697 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
2698 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
2699 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
2700 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
2701 default: return Register();
2702 }
2703}
2704
2705// FastEmit functions for WebAssemblyISD::DOT.
2706
2707Register fastEmit_WebAssemblyISD_DOT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2708 if (RetVT.SimpleTy != MVT::v4i32)
2709 return Register();
2710 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DOT, RC: &WebAssembly::V128RegClass, Op0, Op1);
2711}
2712
2713Register fastEmit_WebAssemblyISD_DOT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2714 switch (VT.SimpleTy) {
2715 case MVT::v8i16: return fastEmit_WebAssemblyISD_DOT_MVT_v8i16_rr(RetVT, Op0, Op1);
2716 default: return Register();
2717 }
2718}
2719
2720// FastEmit functions for WebAssemblyISD::NARROW_U.
2721
2722Register fastEmit_WebAssemblyISD_NARROW_U_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2723 if (RetVT.SimpleTy != MVT::v16i8)
2724 return Register();
2725 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::NARROW_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2726}
2727
2728Register fastEmit_WebAssemblyISD_NARROW_U_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2729 if (RetVT.SimpleTy != MVT::v8i16)
2730 return Register();
2731 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::NARROW_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2732}
2733
2734Register fastEmit_WebAssemblyISD_NARROW_U_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2735 switch (VT.SimpleTy) {
2736 case MVT::v8i16: return fastEmit_WebAssemblyISD_NARROW_U_MVT_v8i16_rr(RetVT, Op0, Op1);
2737 case MVT::v4i32: return fastEmit_WebAssemblyISD_NARROW_U_MVT_v4i32_rr(RetVT, Op0, Op1);
2738 default: return Register();
2739 }
2740}
2741
2742// FastEmit functions for WebAssemblyISD::RELAXED_FMAX.
2743
2744Register fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
2745 if (RetVT.SimpleTy != MVT::v4f32)
2746 return Register();
2747 if ((Subtarget->hasRelaxedSIMD())) {
2748 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMAX_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2749 }
2750 return Register();
2751}
2752
2753Register fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
2754 if (RetVT.SimpleTy != MVT::v2f64)
2755 return Register();
2756 if ((Subtarget->hasRelaxedSIMD())) {
2757 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMAX_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2758 }
2759 return Register();
2760}
2761
2762Register fastEmit_WebAssemblyISD_RELAXED_FMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2763 switch (VT.SimpleTy) {
2764 case MVT::v4f32: return fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v4f32_rr(RetVT, Op0, Op1);
2765 case MVT::v2f64: return fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v2f64_rr(RetVT, Op0, Op1);
2766 default: return Register();
2767 }
2768}
2769
2770// FastEmit functions for WebAssemblyISD::RELAXED_FMIN.
2771
2772Register fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
2773 if (RetVT.SimpleTy != MVT::v4f32)
2774 return Register();
2775 if ((Subtarget->hasRelaxedSIMD())) {
2776 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMIN_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2777 }
2778 return Register();
2779}
2780
2781Register fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
2782 if (RetVT.SimpleTy != MVT::v2f64)
2783 return Register();
2784 if ((Subtarget->hasRelaxedSIMD())) {
2785 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMIN_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2786 }
2787 return Register();
2788}
2789
2790Register fastEmit_WebAssemblyISD_RELAXED_FMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2791 switch (VT.SimpleTy) {
2792 case MVT::v4f32: return fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v4f32_rr(RetVT, Op0, Op1);
2793 case MVT::v2f64: return fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v2f64_rr(RetVT, Op0, Op1);
2794 default: return Register();
2795 }
2796}
2797
2798// FastEmit functions for WebAssemblyISD::SWIZZLE.
2799
2800Register fastEmit_WebAssemblyISD_SWIZZLE_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2801 if (RetVT.SimpleTy != MVT::v16i8)
2802 return Register();
2803 if ((Subtarget->hasSIMD128())) {
2804 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SWIZZLE, RC: &WebAssembly::V128RegClass, Op0, Op1);
2805 }
2806 return Register();
2807}
2808
2809Register fastEmit_WebAssemblyISD_SWIZZLE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2810 switch (VT.SimpleTy) {
2811 case MVT::v16i8: return fastEmit_WebAssemblyISD_SWIZZLE_MVT_v16i8_rr(RetVT, Op0, Op1);
2812 default: return Register();
2813 }
2814}
2815
2816// Top-level FastEmit function.
2817
2818Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
2819 switch (Opcode) {
2820 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
2821 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
2822 case ISD::AVGCEILU: return fastEmit_ISD_AVGCEILU_rr(VT, RetVT, Op0, Op1);
2823 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
2824 case ISD::FCOPYSIGN: return fastEmit_ISD_FCOPYSIGN_rr(VT, RetVT, Op0, Op1);
2825 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
2826 case ISD::FMAXIMUM: return fastEmit_ISD_FMAXIMUM_rr(VT, RetVT, Op0, Op1);
2827 case ISD::FMINIMUM: return fastEmit_ISD_FMINIMUM_rr(VT, RetVT, Op0, Op1);
2828 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
2829 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
2830 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
2831 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
2832 case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op1);
2833 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
2834 case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op1);
2835 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
2836 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
2837 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
2838 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
2839 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
2840 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
2841 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
2842 case ISD::SSUBSAT: return fastEmit_ISD_SSUBSAT_rr(VT, RetVT, Op0, Op1);
2843 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
2844 case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op1);
2845 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
2846 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
2847 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
2848 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
2849 case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op1);
2850 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
2851 case WebAssemblyISD::DOT: return fastEmit_WebAssemblyISD_DOT_rr(VT, RetVT, Op0, Op1);
2852 case WebAssemblyISD::NARROW_U: return fastEmit_WebAssemblyISD_NARROW_U_rr(VT, RetVT, Op0, Op1);
2853 case WebAssemblyISD::RELAXED_FMAX: return fastEmit_WebAssemblyISD_RELAXED_FMAX_rr(VT, RetVT, Op0, Op1);
2854 case WebAssemblyISD::RELAXED_FMIN: return fastEmit_WebAssemblyISD_RELAXED_FMIN_rr(VT, RetVT, Op0, Op1);
2855 case WebAssemblyISD::SWIZZLE: return fastEmit_WebAssemblyISD_SWIZZLE_rr(VT, RetVT, Op0, Op1);
2856 default: return Register();
2857 }
2858}
2859
2860// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2861
2862Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(MVT RetVT, Register Op0, uint64_t imm1) {
2863 if (RetVT.SimpleTy != MVT::i32)
2864 return Register();
2865 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I8x16_u, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2866}
2867
2868Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2869 switch (VT.SimpleTy) {
2870 case MVT::v16i8: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(RetVT, Op0, imm1);
2871 default: return Register();
2872 }
2873}
2874
2875// Top-level FastEmit function.
2876
2877Register fastEmit_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2878 switch (Opcode) {
2879 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(VT, RetVT, Op0, imm1);
2880 default: return Register();
2881 }
2882}
2883
2884// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2885
2886Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(MVT RetVT, Register Op0, uint64_t imm1) {
2887 if (RetVT.SimpleTy != MVT::i32)
2888 return Register();
2889 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I16x8_u, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2890}
2891
2892Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2893 switch (VT.SimpleTy) {
2894 case MVT::v8i16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(RetVT, Op0, imm1);
2895 default: return Register();
2896 }
2897}
2898
2899// Top-level FastEmit function.
2900
2901Register fastEmit_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2902 switch (Opcode) {
2903 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(VT, RetVT, Op0, imm1);
2904 default: return Register();
2905 }
2906}
2907
2908// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2909
2910Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(MVT RetVT, Register Op0, uint64_t imm1) {
2911 if (RetVT.SimpleTy != MVT::i32)
2912 return Register();
2913 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I32x4, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2914}
2915
2916Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(MVT RetVT, Register Op0, uint64_t imm1) {
2917 if (RetVT.SimpleTy != MVT::f32)
2918 return Register();
2919 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_F32x4, RC: &WebAssembly::F32RegClass, Op0, Imm: imm1);
2920}
2921
2922Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2923 switch (VT.SimpleTy) {
2924 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(RetVT, Op0, imm1);
2925 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(RetVT, Op0, imm1);
2926 default: return Register();
2927 }
2928}
2929
2930// Top-level FastEmit function.
2931
2932Register fastEmit_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2933 switch (Opcode) {
2934 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(VT, RetVT, Op0, imm1);
2935 default: return Register();
2936 }
2937}
2938
2939// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2940
2941Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(MVT RetVT, Register Op0, uint64_t imm1) {
2942 if (RetVT.SimpleTy != MVT::i64)
2943 return Register();
2944 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I64x2, RC: &WebAssembly::I64RegClass, Op0, Imm: imm1);
2945}
2946
2947Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(MVT RetVT, Register Op0, uint64_t imm1) {
2948 if (RetVT.SimpleTy != MVT::f64)
2949 return Register();
2950 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_F64x2, RC: &WebAssembly::F64RegClass, Op0, Imm: imm1);
2951}
2952
2953Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2954 switch (VT.SimpleTy) {
2955 case MVT::v2i64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(RetVT, Op0, imm1);
2956 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(RetVT, Op0, imm1);
2957 default: return Register();
2958 }
2959}
2960
2961// Top-level FastEmit function.
2962
2963Register fastEmit_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2964 switch (Opcode) {
2965 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(VT, RetVT, Op0, imm1);
2966 default: return Register();
2967 }
2968}
2969
2970// FastEmit functions for ISD::ConstantFP.
2971
2972Register fastEmit_ISD_ConstantFP_MVT_f32_f(MVT RetVT, const ConstantFP *f0) {
2973 if (RetVT.SimpleTy != MVT::f32)
2974 return Register();
2975 return fastEmitInst_f(MachineInstOpcode: WebAssembly::CONST_F32, RC: &WebAssembly::F32RegClass, FPImm: f0);
2976}
2977
2978Register fastEmit_ISD_ConstantFP_MVT_f64_f(MVT RetVT, const ConstantFP *f0) {
2979 if (RetVT.SimpleTy != MVT::f64)
2980 return Register();
2981 return fastEmitInst_f(MachineInstOpcode: WebAssembly::CONST_F64, RC: &WebAssembly::F64RegClass, FPImm: f0);
2982}
2983
2984Register fastEmit_ISD_ConstantFP_f(MVT VT, MVT RetVT, const ConstantFP *f0) {
2985 switch (VT.SimpleTy) {
2986 case MVT::f32: return fastEmit_ISD_ConstantFP_MVT_f32_f(RetVT, f0);
2987 case MVT::f64: return fastEmit_ISD_ConstantFP_MVT_f64_f(RetVT, f0);
2988 default: return Register();
2989 }
2990}
2991
2992// Top-level FastEmit function.
2993
2994Register fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *f0) override {
2995 switch (Opcode) {
2996 case ISD::ConstantFP: return fastEmit_ISD_ConstantFP_f(VT, RetVT, f0);
2997 default: return Register();
2998 }
2999}
3000
3001// FastEmit functions for ISD::Constant.
3002
3003Register fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
3004 if (RetVT.SimpleTy != MVT::i32)
3005 return Register();
3006 return fastEmitInst_i(MachineInstOpcode: WebAssembly::CONST_I32, RC: &WebAssembly::I32RegClass, Imm: imm0);
3007}
3008
3009Register fastEmit_ISD_Constant_MVT_i64_i(MVT RetVT, uint64_t imm0) {
3010 if (RetVT.SimpleTy != MVT::i64)
3011 return Register();
3012 return fastEmitInst_i(MachineInstOpcode: WebAssembly::CONST_I64, RC: &WebAssembly::I64RegClass, Imm: imm0);
3013}
3014
3015Register fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
3016 switch (VT.SimpleTy) {
3017 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
3018 case MVT::i64: return fastEmit_ISD_Constant_MVT_i64_i(RetVT, imm0);
3019 default: return Register();
3020 }
3021}
3022
3023// Top-level FastEmit function.
3024
3025Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
3026 switch (Opcode) {
3027 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
3028 default: return Register();
3029 }
3030}
3031
3032