1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the WebAssembly target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_ImmI8(int64_t Imm) {
12return -(1 << (8 - 1)) <= Imm && Imm < (1 << 8);
13}
14static bool Predicate_ImmI16(int64_t Imm) {
15return -(1 << (16 - 1)) <= Imm && Imm < (1 << 16);
16}
17static bool Predicate_LaneIdx32(int64_t Imm) {
18return 0 <= Imm && Imm < 32;
19}
20static bool Predicate_LaneIdx16(int64_t Imm) {
21return 0 <= Imm && Imm < 16;
22}
23static bool Predicate_LaneIdx8(int64_t Imm) {
24return 0 <= Imm && Imm < 8;
25}
26static bool Predicate_LaneIdx4(int64_t Imm) {
27return 0 <= Imm && Imm < 4;
28}
29static bool Predicate_LaneIdx2(int64_t Imm) {
30return 0 <= Imm && Imm < 2;
31}
32
33
34// FastEmit functions for ISD::ABS.
35
36Register fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, Register Op0) {
37 if (RetVT.SimpleTy != MVT::v16i8)
38 return Register();
39 if ((Subtarget->hasSIMD128())) {
40 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I8x16, RC: &WebAssembly::V128RegClass, Op0);
41 }
42 return Register();
43}
44
45Register fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, Register Op0) {
46 if (RetVT.SimpleTy != MVT::v8i16)
47 return Register();
48 if ((Subtarget->hasSIMD128())) {
49 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I16x8, RC: &WebAssembly::V128RegClass, Op0);
50 }
51 return Register();
52}
53
54Register fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, Register Op0) {
55 if (RetVT.SimpleTy != MVT::v4i32)
56 return Register();
57 if ((Subtarget->hasSIMD128())) {
58 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I32x4, RC: &WebAssembly::V128RegClass, Op0);
59 }
60 return Register();
61}
62
63Register fastEmit_ISD_ABS_MVT_v2i64_r(MVT RetVT, Register Op0) {
64 if (RetVT.SimpleTy != MVT::v2i64)
65 return Register();
66 if ((Subtarget->hasSIMD128())) {
67 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_I64x2, RC: &WebAssembly::V128RegClass, Op0);
68 }
69 return Register();
70}
71
72Register fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, Register Op0) {
73 switch (VT.SimpleTy) {
74 case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0);
75 case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0);
76 case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0);
77 case MVT::v2i64: return fastEmit_ISD_ABS_MVT_v2i64_r(RetVT, Op0);
78 default: return Register();
79 }
80}
81
82// FastEmit functions for ISD::ANY_EXTEND.
83
84Register fastEmit_ISD_ANY_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
85 if (RetVT.SimpleTy != MVT::i64)
86 return Register();
87 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_U_I32, RC: &WebAssembly::I64RegClass, Op0);
88}
89
90Register fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
91 switch (VT.SimpleTy) {
92 case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i32_r(RetVT, Op0);
93 default: return Register();
94 }
95}
96
97// FastEmit functions for ISD::BITCAST.
98
99Register fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, Register Op0) {
100 if (RetVT.SimpleTy != MVT::f32)
101 return Register();
102 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_REINTERPRET_I32, RC: &WebAssembly::F32RegClass, Op0);
103}
104
105Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
106 if (RetVT.SimpleTy != MVT::f64)
107 return Register();
108 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_REINTERPRET_I64, RC: &WebAssembly::F64RegClass, Op0);
109}
110
111Register fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, Register Op0) {
112 if (RetVT.SimpleTy != MVT::i32)
113 return Register();
114 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_REINTERPRET_F32, RC: &WebAssembly::I32RegClass, Op0);
115}
116
117Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
118 if (RetVT.SimpleTy != MVT::i64)
119 return Register();
120 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_REINTERPRET_F64, RC: &WebAssembly::I64RegClass, Op0);
121}
122
123Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
124 switch (VT.SimpleTy) {
125 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
126 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
127 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
128 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
129 default: return Register();
130 }
131}
132
133// FastEmit functions for ISD::CTLZ.
134
135Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
136 if (RetVT.SimpleTy != MVT::i32)
137 return Register();
138 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CLZ_I32, RC: &WebAssembly::I32RegClass, Op0);
139}
140
141Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
142 if (RetVT.SimpleTy != MVT::i64)
143 return Register();
144 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CLZ_I64, RC: &WebAssembly::I64RegClass, Op0);
145}
146
147Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
148 switch (VT.SimpleTy) {
149 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
150 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
151 default: return Register();
152 }
153}
154
155// FastEmit functions for ISD::CTPOP.
156
157Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
158 if (RetVT.SimpleTy != MVT::i32)
159 return Register();
160 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I32, RC: &WebAssembly::I32RegClass, Op0);
161}
162
163Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
164 if (RetVT.SimpleTy != MVT::i64)
165 return Register();
166 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I64, RC: &WebAssembly::I64RegClass, Op0);
167}
168
169Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
170 if (RetVT.SimpleTy != MVT::v16i8)
171 return Register();
172 if ((Subtarget->hasSIMD128())) {
173 return fastEmitInst_r(MachineInstOpcode: WebAssembly::POPCNT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
174 }
175 return Register();
176}
177
178Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
179 switch (VT.SimpleTy) {
180 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
181 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
182 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
183 default: return Register();
184 }
185}
186
187// FastEmit functions for ISD::CTTZ.
188
189Register fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, Register Op0) {
190 if (RetVT.SimpleTy != MVT::i32)
191 return Register();
192 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CTZ_I32, RC: &WebAssembly::I32RegClass, Op0);
193}
194
195Register fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, Register Op0) {
196 if (RetVT.SimpleTy != MVT::i64)
197 return Register();
198 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CTZ_I64, RC: &WebAssembly::I64RegClass, Op0);
199}
200
201Register fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, Register Op0) {
202 switch (VT.SimpleTy) {
203 case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0);
204 case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0);
205 default: return Register();
206 }
207}
208
209// FastEmit functions for ISD::FABS.
210
211Register fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, Register Op0) {
212 if (RetVT.SimpleTy != MVT::f32)
213 return Register();
214 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F32, RC: &WebAssembly::F32RegClass, Op0);
215}
216
217Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
218 if (RetVT.SimpleTy != MVT::f64)
219 return Register();
220 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F64, RC: &WebAssembly::F64RegClass, Op0);
221}
222
223Register fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, Register Op0) {
224 if (RetVT.SimpleTy != MVT::v8f16)
225 return Register();
226 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
227 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F16x8, RC: &WebAssembly::V128RegClass, Op0);
228 }
229 return Register();
230}
231
232Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
233 if (RetVT.SimpleTy != MVT::v4f32)
234 return Register();
235 if ((Subtarget->hasSIMD128())) {
236 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F32x4, RC: &WebAssembly::V128RegClass, Op0);
237 }
238 return Register();
239}
240
241Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
242 if (RetVT.SimpleTy != MVT::v2f64)
243 return Register();
244 if ((Subtarget->hasSIMD128())) {
245 return fastEmitInst_r(MachineInstOpcode: WebAssembly::ABS_F64x2, RC: &WebAssembly::V128RegClass, Op0);
246 }
247 return Register();
248}
249
250Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
251 switch (VT.SimpleTy) {
252 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
253 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
254 case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0);
255 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
256 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
257 default: return Register();
258 }
259}
260
261// FastEmit functions for ISD::FCEIL.
262
263Register fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, Register Op0) {
264 if (RetVT.SimpleTy != MVT::f32)
265 return Register();
266 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F32, RC: &WebAssembly::F32RegClass, Op0);
267}
268
269Register fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, Register Op0) {
270 if (RetVT.SimpleTy != MVT::f64)
271 return Register();
272 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F64, RC: &WebAssembly::F64RegClass, Op0);
273}
274
275Register fastEmit_ISD_FCEIL_MVT_v8f16_r(MVT RetVT, Register Op0) {
276 if (RetVT.SimpleTy != MVT::v8f16)
277 return Register();
278 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
279 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F16x8, RC: &WebAssembly::V128RegClass, Op0);
280 }
281 return Register();
282}
283
284Register fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, Register Op0) {
285 if (RetVT.SimpleTy != MVT::v4f32)
286 return Register();
287 if ((Subtarget->hasSIMD128())) {
288 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F32x4, RC: &WebAssembly::V128RegClass, Op0);
289 }
290 return Register();
291}
292
293Register fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, Register Op0) {
294 if (RetVT.SimpleTy != MVT::v2f64)
295 return Register();
296 if ((Subtarget->hasSIMD128())) {
297 return fastEmitInst_r(MachineInstOpcode: WebAssembly::CEIL_F64x2, RC: &WebAssembly::V128RegClass, Op0);
298 }
299 return Register();
300}
301
302Register fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, Register Op0) {
303 switch (VT.SimpleTy) {
304 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0);
305 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0);
306 case MVT::v8f16: return fastEmit_ISD_FCEIL_MVT_v8f16_r(RetVT, Op0);
307 case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0);
308 case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0);
309 default: return Register();
310 }
311}
312
313// FastEmit functions for ISD::FFLOOR.
314
315Register fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, Register Op0) {
316 if (RetVT.SimpleTy != MVT::f32)
317 return Register();
318 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F32, RC: &WebAssembly::F32RegClass, Op0);
319}
320
321Register fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, Register Op0) {
322 if (RetVT.SimpleTy != MVT::f64)
323 return Register();
324 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F64, RC: &WebAssembly::F64RegClass, Op0);
325}
326
327Register fastEmit_ISD_FFLOOR_MVT_v8f16_r(MVT RetVT, Register Op0) {
328 if (RetVT.SimpleTy != MVT::v8f16)
329 return Register();
330 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
331 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F16x8, RC: &WebAssembly::V128RegClass, Op0);
332 }
333 return Register();
334}
335
336Register fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, Register Op0) {
337 if (RetVT.SimpleTy != MVT::v4f32)
338 return Register();
339 if ((Subtarget->hasSIMD128())) {
340 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F32x4, RC: &WebAssembly::V128RegClass, Op0);
341 }
342 return Register();
343}
344
345Register fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, Register Op0) {
346 if (RetVT.SimpleTy != MVT::v2f64)
347 return Register();
348 if ((Subtarget->hasSIMD128())) {
349 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FLOOR_F64x2, RC: &WebAssembly::V128RegClass, Op0);
350 }
351 return Register();
352}
353
354Register fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, Register Op0) {
355 switch (VT.SimpleTy) {
356 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0);
357 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0);
358 case MVT::v8f16: return fastEmit_ISD_FFLOOR_MVT_v8f16_r(RetVT, Op0);
359 case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0);
360 case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0);
361 default: return Register();
362 }
363}
364
365// FastEmit functions for ISD::FNEARBYINT.
366
367Register fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, Register Op0) {
368 if (RetVT.SimpleTy != MVT::f32)
369 return Register();
370 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
371}
372
373Register fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, Register Op0) {
374 if (RetVT.SimpleTy != MVT::f64)
375 return Register();
376 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
377}
378
379Register fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
380 if (RetVT.SimpleTy != MVT::v8f16)
381 return Register();
382 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
383 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
384 }
385 return Register();
386}
387
388Register fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
389 if (RetVT.SimpleTy != MVT::v4f32)
390 return Register();
391 if ((Subtarget->hasSIMD128())) {
392 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
393 }
394 return Register();
395}
396
397Register fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
398 if (RetVT.SimpleTy != MVT::v2f64)
399 return Register();
400 if ((Subtarget->hasSIMD128())) {
401 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
402 }
403 return Register();
404}
405
406Register fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, Register Op0) {
407 switch (VT.SimpleTy) {
408 case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0);
409 case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0);
410 case MVT::v8f16: return fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(RetVT, Op0);
411 case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0);
412 case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0);
413 default: return Register();
414 }
415}
416
417// FastEmit functions for ISD::FNEG.
418
419Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
420 if (RetVT.SimpleTy != MVT::f32)
421 return Register();
422 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F32, RC: &WebAssembly::F32RegClass, Op0);
423}
424
425Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
426 if (RetVT.SimpleTy != MVT::f64)
427 return Register();
428 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F64, RC: &WebAssembly::F64RegClass, Op0);
429}
430
431Register fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, Register Op0) {
432 if (RetVT.SimpleTy != MVT::v8f16)
433 return Register();
434 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
435 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F16x8, RC: &WebAssembly::V128RegClass, Op0);
436 }
437 return Register();
438}
439
440Register fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, Register Op0) {
441 if (RetVT.SimpleTy != MVT::v4f32)
442 return Register();
443 if ((Subtarget->hasSIMD128())) {
444 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F32x4, RC: &WebAssembly::V128RegClass, Op0);
445 }
446 return Register();
447}
448
449Register fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, Register Op0) {
450 if (RetVT.SimpleTy != MVT::v2f64)
451 return Register();
452 if ((Subtarget->hasSIMD128())) {
453 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEG_F64x2, RC: &WebAssembly::V128RegClass, Op0);
454 }
455 return Register();
456}
457
458Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
459 switch (VT.SimpleTy) {
460 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
461 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
462 case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0);
463 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0);
464 case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0);
465 default: return Register();
466 }
467}
468
469// FastEmit functions for ISD::FP_EXTEND.
470
471Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
472 if (RetVT.SimpleTy != MVT::f64)
473 return Register();
474 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_PROMOTE_F32, RC: &WebAssembly::F64RegClass, Op0);
475}
476
477Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
478 switch (VT.SimpleTy) {
479 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
480 default: return Register();
481 }
482}
483
484// FastEmit functions for ISD::FP_ROUND.
485
486Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
487 if (RetVT.SimpleTy != MVT::f32)
488 return Register();
489 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_DEMOTE_F64, RC: &WebAssembly::F32RegClass, Op0);
490}
491
492Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
493 switch (VT.SimpleTy) {
494 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
495 default: return Register();
496 }
497}
498
499// FastEmit functions for ISD::FP_TO_SINT.
500
501Register fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Register Op0) {
502 if ((!Subtarget->hasNontrappingFPToInt())) {
503 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I32_F32, RC: &WebAssembly::I32RegClass, Op0);
504 }
505 if ((Subtarget->hasNontrappingFPToInt())) {
506 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_S_SAT_F32, RC: &WebAssembly::I32RegClass, Op0);
507 }
508 return Register();
509}
510
511Register fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Register Op0) {
512 if ((!Subtarget->hasNontrappingFPToInt())) {
513 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I64_F32, RC: &WebAssembly::I64RegClass, Op0);
514 }
515 if ((Subtarget->hasNontrappingFPToInt())) {
516 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_S_SAT_F32, RC: &WebAssembly::I64RegClass, Op0);
517 }
518 return Register();
519}
520
521Register fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, Register Op0) {
522switch (RetVT.SimpleTy) {
523 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0);
524 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0);
525 default: return Register();
526}
527}
528
529Register fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Register Op0) {
530 if ((!Subtarget->hasNontrappingFPToInt())) {
531 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I32_F64, RC: &WebAssembly::I32RegClass, Op0);
532 }
533 if ((Subtarget->hasNontrappingFPToInt())) {
534 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_S_SAT_F64, RC: &WebAssembly::I32RegClass, Op0);
535 }
536 return Register();
537}
538
539Register fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Register Op0) {
540 if ((!Subtarget->hasNontrappingFPToInt())) {
541 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_SINT_I64_F64, RC: &WebAssembly::I64RegClass, Op0);
542 }
543 if ((Subtarget->hasNontrappingFPToInt())) {
544 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_S_SAT_F64, RC: &WebAssembly::I64RegClass, Op0);
545 }
546 return Register();
547}
548
549Register fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, Register Op0) {
550switch (RetVT.SimpleTy) {
551 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0);
552 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0);
553 default: return Register();
554}
555}
556
557Register fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
558 if (RetVT.SimpleTy != MVT::v8i16)
559 return Register();
560 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
561 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_sint_I16x8, RC: &WebAssembly::V128RegClass, Op0);
562 }
563 return Register();
564}
565
566Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
567 if (RetVT.SimpleTy != MVT::v4i32)
568 return Register();
569 if ((Subtarget->hasSIMD128())) {
570 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_sint_I32x4, RC: &WebAssembly::V128RegClass, Op0);
571 }
572 return Register();
573}
574
575Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
576 switch (VT.SimpleTy) {
577 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
578 case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
579 case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0);
580 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
581 default: return Register();
582 }
583}
584
585// FastEmit functions for ISD::FP_TO_UINT.
586
587Register fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Register Op0) {
588 if ((!Subtarget->hasNontrappingFPToInt())) {
589 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I32_F32, RC: &WebAssembly::I32RegClass, Op0);
590 }
591 if ((Subtarget->hasNontrappingFPToInt())) {
592 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_U_SAT_F32, RC: &WebAssembly::I32RegClass, Op0);
593 }
594 return Register();
595}
596
597Register fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Register Op0) {
598 if ((!Subtarget->hasNontrappingFPToInt())) {
599 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I64_F32, RC: &WebAssembly::I64RegClass, Op0);
600 }
601 if ((Subtarget->hasNontrappingFPToInt())) {
602 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_U_SAT_F32, RC: &WebAssembly::I64RegClass, Op0);
603 }
604 return Register();
605}
606
607Register fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, Register Op0) {
608switch (RetVT.SimpleTy) {
609 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0);
610 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0);
611 default: return Register();
612}
613}
614
615Register fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Register Op0) {
616 if ((!Subtarget->hasNontrappingFPToInt())) {
617 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I32_F64, RC: &WebAssembly::I32RegClass, Op0);
618 }
619 if ((Subtarget->hasNontrappingFPToInt())) {
620 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_TRUNC_U_SAT_F64, RC: &WebAssembly::I32RegClass, Op0);
621 }
622 return Register();
623}
624
625Register fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Register Op0) {
626 if ((!Subtarget->hasNontrappingFPToInt())) {
627 return fastEmitInst_r(MachineInstOpcode: WebAssembly::FP_TO_UINT_I64_F64, RC: &WebAssembly::I64RegClass, Op0);
628 }
629 if ((Subtarget->hasNontrappingFPToInt())) {
630 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_TRUNC_U_SAT_F64, RC: &WebAssembly::I64RegClass, Op0);
631 }
632 return Register();
633}
634
635Register fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, Register Op0) {
636switch (RetVT.SimpleTy) {
637 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0);
638 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0);
639 default: return Register();
640}
641}
642
643Register fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
644 if (RetVT.SimpleTy != MVT::v8i16)
645 return Register();
646 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
647 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_uint_I16x8, RC: &WebAssembly::V128RegClass, Op0);
648 }
649 return Register();
650}
651
652Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
653 if (RetVT.SimpleTy != MVT::v4i32)
654 return Register();
655 if ((Subtarget->hasSIMD128())) {
656 return fastEmitInst_r(MachineInstOpcode: WebAssembly::fp_to_uint_I32x4, RC: &WebAssembly::V128RegClass, Op0);
657 }
658 return Register();
659}
660
661Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
662 switch (VT.SimpleTy) {
663 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
664 case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
665 case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0);
666 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
667 default: return Register();
668 }
669}
670
671// FastEmit functions for ISD::FRINT.
672
673Register fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, Register Op0) {
674 if (RetVT.SimpleTy != MVT::f32)
675 return Register();
676 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
677}
678
679Register fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, Register Op0) {
680 if (RetVT.SimpleTy != MVT::f64)
681 return Register();
682 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
683}
684
685Register fastEmit_ISD_FRINT_MVT_v8f16_r(MVT RetVT, Register Op0) {
686 if (RetVT.SimpleTy != MVT::v8f16)
687 return Register();
688 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
689}
690
691Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
692 if (RetVT.SimpleTy != MVT::v4f32)
693 return Register();
694 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
695}
696
697Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
698 if (RetVT.SimpleTy != MVT::v2f64)
699 return Register();
700 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
701}
702
703Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
704 switch (VT.SimpleTy) {
705 case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0);
706 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0);
707 case MVT::v8f16: return fastEmit_ISD_FRINT_MVT_v8f16_r(RetVT, Op0);
708 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
709 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
710 default: return Register();
711 }
712}
713
714// FastEmit functions for ISD::FROUNDEVEN.
715
716Register fastEmit_ISD_FROUNDEVEN_MVT_f32_r(MVT RetVT, Register Op0) {
717 if (RetVT.SimpleTy != MVT::f32)
718 return Register();
719 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32, RC: &WebAssembly::F32RegClass, Op0);
720}
721
722Register fastEmit_ISD_FROUNDEVEN_MVT_f64_r(MVT RetVT, Register Op0) {
723 if (RetVT.SimpleTy != MVT::f64)
724 return Register();
725 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64, RC: &WebAssembly::F64RegClass, Op0);
726}
727
728Register fastEmit_ISD_FROUNDEVEN_MVT_v8f16_r(MVT RetVT, Register Op0) {
729 if (RetVT.SimpleTy != MVT::v8f16)
730 return Register();
731 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F16x8, RC: &WebAssembly::V128RegClass, Op0);
732}
733
734Register fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(MVT RetVT, Register Op0) {
735 if (RetVT.SimpleTy != MVT::v4f32)
736 return Register();
737 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F32x4, RC: &WebAssembly::V128RegClass, Op0);
738}
739
740Register fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(MVT RetVT, Register Op0) {
741 if (RetVT.SimpleTy != MVT::v2f64)
742 return Register();
743 return fastEmitInst_r(MachineInstOpcode: WebAssembly::NEAREST_F64x2, RC: &WebAssembly::V128RegClass, Op0);
744}
745
746Register fastEmit_ISD_FROUNDEVEN_r(MVT VT, MVT RetVT, Register Op0) {
747 switch (VT.SimpleTy) {
748 case MVT::f32: return fastEmit_ISD_FROUNDEVEN_MVT_f32_r(RetVT, Op0);
749 case MVT::f64: return fastEmit_ISD_FROUNDEVEN_MVT_f64_r(RetVT, Op0);
750 case MVT::v8f16: return fastEmit_ISD_FROUNDEVEN_MVT_v8f16_r(RetVT, Op0);
751 case MVT::v4f32: return fastEmit_ISD_FROUNDEVEN_MVT_v4f32_r(RetVT, Op0);
752 case MVT::v2f64: return fastEmit_ISD_FROUNDEVEN_MVT_v2f64_r(RetVT, Op0);
753 default: return Register();
754 }
755}
756
757// FastEmit functions for ISD::FSQRT.
758
759Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
760 if (RetVT.SimpleTy != MVT::f32)
761 return Register();
762 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F32, RC: &WebAssembly::F32RegClass, Op0);
763}
764
765Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
766 if (RetVT.SimpleTy != MVT::f64)
767 return Register();
768 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F64, RC: &WebAssembly::F64RegClass, Op0);
769}
770
771Register fastEmit_ISD_FSQRT_MVT_v8f16_r(MVT RetVT, Register Op0) {
772 if (RetVT.SimpleTy != MVT::v8f16)
773 return Register();
774 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
775 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F16x8, RC: &WebAssembly::V128RegClass, Op0);
776 }
777 return Register();
778}
779
780Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
781 if (RetVT.SimpleTy != MVT::v4f32)
782 return Register();
783 if ((Subtarget->hasSIMD128())) {
784 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
785 }
786 return Register();
787}
788
789Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
790 if (RetVT.SimpleTy != MVT::v2f64)
791 return Register();
792 if ((Subtarget->hasSIMD128())) {
793 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SQRT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
794 }
795 return Register();
796}
797
798Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
799 switch (VT.SimpleTy) {
800 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
801 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
802 case MVT::v8f16: return fastEmit_ISD_FSQRT_MVT_v8f16_r(RetVT, Op0);
803 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
804 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
805 default: return Register();
806 }
807}
808
809// FastEmit functions for ISD::FTRUNC.
810
811Register fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, Register Op0) {
812 if (RetVT.SimpleTy != MVT::f32)
813 return Register();
814 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F32, RC: &WebAssembly::F32RegClass, Op0);
815}
816
817Register fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, Register Op0) {
818 if (RetVT.SimpleTy != MVT::f64)
819 return Register();
820 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F64, RC: &WebAssembly::F64RegClass, Op0);
821}
822
823Register fastEmit_ISD_FTRUNC_MVT_v8f16_r(MVT RetVT, Register Op0) {
824 if (RetVT.SimpleTy != MVT::v8f16)
825 return Register();
826 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
827 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F16x8, RC: &WebAssembly::V128RegClass, Op0);
828 }
829 return Register();
830}
831
832Register fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, Register Op0) {
833 if (RetVT.SimpleTy != MVT::v4f32)
834 return Register();
835 if ((Subtarget->hasSIMD128())) {
836 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F32x4, RC: &WebAssembly::V128RegClass, Op0);
837 }
838 return Register();
839}
840
841Register fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, Register Op0) {
842 if (RetVT.SimpleTy != MVT::v2f64)
843 return Register();
844 if ((Subtarget->hasSIMD128())) {
845 return fastEmitInst_r(MachineInstOpcode: WebAssembly::TRUNC_F64x2, RC: &WebAssembly::V128RegClass, Op0);
846 }
847 return Register();
848}
849
850Register fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, Register Op0) {
851 switch (VT.SimpleTy) {
852 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0);
853 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0);
854 case MVT::v8f16: return fastEmit_ISD_FTRUNC_MVT_v8f16_r(RetVT, Op0);
855 case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0);
856 case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0);
857 default: return Register();
858 }
859}
860
861// FastEmit functions for ISD::SCALAR_TO_VECTOR.
862
863Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v16i8_r(Register Op0) {
864 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
865}
866
867Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v8i16_r(Register Op0) {
868 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I16x8, RC: &WebAssembly::V128RegClass, Op0);
869}
870
871Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(Register Op0) {
872 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I32x4, RC: &WebAssembly::V128RegClass, Op0);
873}
874
875Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, Register Op0) {
876switch (RetVT.SimpleTy) {
877 case MVT::v16i8: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v16i8_r(Op0);
878 case MVT::v8i16: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v8i16_r(Op0);
879 case MVT::v4i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(Op0);
880 default: return Register();
881}
882}
883
884Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(MVT RetVT, Register Op0) {
885 if (RetVT.SimpleTy != MVT::v2i64)
886 return Register();
887 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I64x2, RC: &WebAssembly::V128RegClass, Op0);
888}
889
890Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, Register Op0) {
891 if (RetVT.SimpleTy != MVT::v4f32)
892 return Register();
893 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
894}
895
896Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(MVT RetVT, Register Op0) {
897 if (RetVT.SimpleTy != MVT::v2f64)
898 return Register();
899 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
900}
901
902Register fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, Register Op0) {
903 switch (VT.SimpleTy) {
904 case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0);
905 case MVT::i64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(RetVT, Op0);
906 case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0);
907 case MVT::f64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(RetVT, Op0);
908 default: return Register();
909 }
910}
911
912// FastEmit functions for ISD::SIGN_EXTEND.
913
914Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
915 if (RetVT.SimpleTy != MVT::i64)
916 return Register();
917 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_S_I32, RC: &WebAssembly::I64RegClass, Op0);
918}
919
920Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
921 switch (VT.SimpleTy) {
922 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
923 default: return Register();
924 }
925}
926
927// FastEmit functions for ISD::SINT_TO_FP.
928
929Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
930 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_S_I32, RC: &WebAssembly::F32RegClass, Op0);
931}
932
933Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
934 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_S_I32, RC: &WebAssembly::F64RegClass, Op0);
935}
936
937Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
938switch (RetVT.SimpleTy) {
939 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
940 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
941 default: return Register();
942}
943}
944
945Register fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Register Op0) {
946 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_S_I64, RC: &WebAssembly::F32RegClass, Op0);
947}
948
949Register fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Register Op0) {
950 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_S_I64, RC: &WebAssembly::F64RegClass, Op0);
951}
952
953Register fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
954switch (RetVT.SimpleTy) {
955 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0);
956 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0);
957 default: return Register();
958}
959}
960
961Register fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, Register Op0) {
962 if (RetVT.SimpleTy != MVT::v8f16)
963 return Register();
964 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
965 return fastEmitInst_r(MachineInstOpcode: WebAssembly::sint_to_fp_F16x8, RC: &WebAssembly::V128RegClass, Op0);
966 }
967 return Register();
968}
969
970Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
971 if (RetVT.SimpleTy != MVT::v4f32)
972 return Register();
973 if ((Subtarget->hasSIMD128())) {
974 return fastEmitInst_r(MachineInstOpcode: WebAssembly::sint_to_fp_F32x4, RC: &WebAssembly::V128RegClass, Op0);
975 }
976 return Register();
977}
978
979Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
980 switch (VT.SimpleTy) {
981 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
982 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
983 case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0);
984 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
985 default: return Register();
986 }
987}
988
989// FastEmit functions for ISD::SPLAT_VECTOR.
990
991Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v16i8_r(Register Op0) {
992 if ((Subtarget->hasSIMD128())) {
993 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I8x16, RC: &WebAssembly::V128RegClass, Op0);
994 }
995 return Register();
996}
997
998Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v8i16_r(Register Op0) {
999 if ((Subtarget->hasSIMD128())) {
1000 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1001 }
1002 return Register();
1003}
1004
1005Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v4i32_r(Register Op0) {
1006 if ((Subtarget->hasSIMD128())) {
1007 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1008 }
1009 return Register();
1010}
1011
1012Register fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(MVT RetVT, Register Op0) {
1013switch (RetVT.SimpleTy) {
1014 case MVT::v16i8: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v16i8_r(Op0);
1015 case MVT::v8i16: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v8i16_r(Op0);
1016 case MVT::v4i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_MVT_v4i32_r(Op0);
1017 default: return Register();
1018}
1019}
1020
1021Register fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(MVT RetVT, Register Op0) {
1022 if (RetVT.SimpleTy != MVT::v2i64)
1023 return Register();
1024 if ((Subtarget->hasSIMD128())) {
1025 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1026 }
1027 return Register();
1028}
1029
1030Register fastEmit_ISD_SPLAT_VECTOR_MVT_f32_r(MVT RetVT, Register Op0) {
1031 if (RetVT.SimpleTy != MVT::v4f32)
1032 return Register();
1033 if ((Subtarget->hasSIMD128())) {
1034 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1035 }
1036 return Register();
1037}
1038
1039Register fastEmit_ISD_SPLAT_VECTOR_MVT_f64_r(MVT RetVT, Register Op0) {
1040 if (RetVT.SimpleTy != MVT::v2f64)
1041 return Register();
1042 if ((Subtarget->hasSIMD128())) {
1043 return fastEmitInst_r(MachineInstOpcode: WebAssembly::SPLAT_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1044 }
1045 return Register();
1046}
1047
1048Register fastEmit_ISD_SPLAT_VECTOR_r(MVT VT, MVT RetVT, Register Op0) {
1049 switch (VT.SimpleTy) {
1050 case MVT::i32: return fastEmit_ISD_SPLAT_VECTOR_MVT_i32_r(RetVT, Op0);
1051 case MVT::i64: return fastEmit_ISD_SPLAT_VECTOR_MVT_i64_r(RetVT, Op0);
1052 case MVT::f32: return fastEmit_ISD_SPLAT_VECTOR_MVT_f32_r(RetVT, Op0);
1053 case MVT::f64: return fastEmit_ISD_SPLAT_VECTOR_MVT_f64_r(RetVT, Op0);
1054 default: return Register();
1055 }
1056}
1057
1058// FastEmit functions for ISD::TRUNCATE.
1059
1060Register fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, Register Op0) {
1061 if (RetVT.SimpleTy != MVT::i32)
1062 return Register();
1063 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I32_WRAP_I64, RC: &WebAssembly::I32RegClass, Op0);
1064}
1065
1066Register fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, Register Op0) {
1067 switch (VT.SimpleTy) {
1068 case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0);
1069 default: return Register();
1070 }
1071}
1072
1073// FastEmit functions for ISD::UINT_TO_FP.
1074
1075Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1076 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_U_I32, RC: &WebAssembly::F32RegClass, Op0);
1077}
1078
1079Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1080 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_U_I32, RC: &WebAssembly::F64RegClass, Op0);
1081}
1082
1083Register fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1084switch (RetVT.SimpleTy) {
1085 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1086 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1087 default: return Register();
1088}
1089}
1090
1091Register fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Register Op0) {
1092 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F32_CONVERT_U_I64, RC: &WebAssembly::F32RegClass, Op0);
1093}
1094
1095Register fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Register Op0) {
1096 return fastEmitInst_r(MachineInstOpcode: WebAssembly::F64_CONVERT_U_I64, RC: &WebAssembly::F64RegClass, Op0);
1097}
1098
1099Register fastEmit_ISD_UINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
1100switch (RetVT.SimpleTy) {
1101 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0);
1102 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Op0);
1103 default: return Register();
1104}
1105}
1106
1107Register fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, Register Op0) {
1108 if (RetVT.SimpleTy != MVT::v8f16)
1109 return Register();
1110 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1111 return fastEmitInst_r(MachineInstOpcode: WebAssembly::uint_to_fp_F16x8, RC: &WebAssembly::V128RegClass, Op0);
1112 }
1113 return Register();
1114}
1115
1116Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1117 if (RetVT.SimpleTy != MVT::v4f32)
1118 return Register();
1119 if ((Subtarget->hasSIMD128())) {
1120 return fastEmitInst_r(MachineInstOpcode: WebAssembly::uint_to_fp_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1121 }
1122 return Register();
1123}
1124
1125Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1126 switch (VT.SimpleTy) {
1127 case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1128 case MVT::i64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_r(RetVT, Op0);
1129 case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0);
1130 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1131 default: return Register();
1132 }
1133}
1134
1135// FastEmit functions for ISD::ZERO_EXTEND.
1136
1137Register fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
1138 if (RetVT.SimpleTy != MVT::i64)
1139 return Register();
1140 return fastEmitInst_r(MachineInstOpcode: WebAssembly::I64_EXTEND_U_I32, RC: &WebAssembly::I64RegClass, Op0);
1141}
1142
1143Register fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
1144 switch (VT.SimpleTy) {
1145 case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(RetVT, Op0);
1146 default: return Register();
1147 }
1148}
1149
1150// FastEmit functions for WebAssemblyISD::BR_TABLE.
1151
1152Register fastEmit_WebAssemblyISD_BR_TABLE_MVT_i32_r(MVT RetVT, Register Op0) {
1153 if (RetVT.SimpleTy != MVT::isVoid)
1154 return Register();
1155 return fastEmitInst_r(MachineInstOpcode: WebAssembly::BR_TABLE_I32, RC: &WebAssembly::I32RegClass, Op0);
1156}
1157
1158Register fastEmit_WebAssemblyISD_BR_TABLE_MVT_i64_r(MVT RetVT, Register Op0) {
1159 if (RetVT.SimpleTy != MVT::isVoid)
1160 return Register();
1161 return fastEmitInst_r(MachineInstOpcode: WebAssembly::BR_TABLE_I64, RC: &WebAssembly::I64RegClass, Op0);
1162}
1163
1164Register fastEmit_WebAssemblyISD_BR_TABLE_r(MVT VT, MVT RetVT, Register Op0) {
1165 switch (VT.SimpleTy) {
1166 case MVT::i32: return fastEmit_WebAssemblyISD_BR_TABLE_MVT_i32_r(RetVT, Op0);
1167 case MVT::i64: return fastEmit_WebAssemblyISD_BR_TABLE_MVT_i64_r(RetVT, Op0);
1168 default: return Register();
1169 }
1170}
1171
1172// FastEmit functions for WebAssemblyISD::CONVERT_LOW_S.
1173
1174Register fastEmit_WebAssemblyISD_CONVERT_LOW_S_MVT_v4i32_r(MVT RetVT, Register Op0) {
1175 if (RetVT.SimpleTy != MVT::v2f64)
1176 return Register();
1177 if ((Subtarget->hasSIMD128())) {
1178 return fastEmitInst_r(MachineInstOpcode: WebAssembly::convert_low_s_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1179 }
1180 return Register();
1181}
1182
1183Register fastEmit_WebAssemblyISD_CONVERT_LOW_S_r(MVT VT, MVT RetVT, Register Op0) {
1184 switch (VT.SimpleTy) {
1185 case MVT::v4i32: return fastEmit_WebAssemblyISD_CONVERT_LOW_S_MVT_v4i32_r(RetVT, Op0);
1186 default: return Register();
1187 }
1188}
1189
1190// FastEmit functions for WebAssemblyISD::CONVERT_LOW_U.
1191
1192Register fastEmit_WebAssemblyISD_CONVERT_LOW_U_MVT_v4i32_r(MVT RetVT, Register Op0) {
1193 if (RetVT.SimpleTy != MVT::v2f64)
1194 return Register();
1195 if ((Subtarget->hasSIMD128())) {
1196 return fastEmitInst_r(MachineInstOpcode: WebAssembly::convert_low_u_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1197 }
1198 return Register();
1199}
1200
1201Register fastEmit_WebAssemblyISD_CONVERT_LOW_U_r(MVT VT, MVT RetVT, Register Op0) {
1202 switch (VT.SimpleTy) {
1203 case MVT::v4i32: return fastEmit_WebAssemblyISD_CONVERT_LOW_U_MVT_v4i32_r(RetVT, Op0);
1204 default: return Register();
1205 }
1206}
1207
1208// FastEmit functions for WebAssemblyISD::DEMOTE_ZERO.
1209
1210Register fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v2f64_r(MVT RetVT, Register Op0) {
1211 if (RetVT.SimpleTy != MVT::v4f32)
1212 return Register();
1213 if ((Subtarget->hasSIMD128())) {
1214 return fastEmitInst_r(MachineInstOpcode: WebAssembly::demote_zero_F32x4, RC: &WebAssembly::V128RegClass, Op0);
1215 }
1216 return Register();
1217}
1218
1219Register fastEmit_WebAssemblyISD_DEMOTE_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1220 switch (VT.SimpleTy) {
1221 case MVT::v2f64: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_MVT_v2f64_r(RetVT, Op0);
1222 default: return Register();
1223 }
1224}
1225
1226// FastEmit functions for WebAssemblyISD::EXTEND_HIGH_S.
1227
1228Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v16i8_r(MVT RetVT, Register Op0) {
1229 if (RetVT.SimpleTy != MVT::v8i16)
1230 return Register();
1231 if ((Subtarget->hasSIMD128())) {
1232 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1233 }
1234 return Register();
1235}
1236
1237Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v8i16_r(MVT RetVT, Register Op0) {
1238 if (RetVT.SimpleTy != MVT::v4i32)
1239 return Register();
1240 if ((Subtarget->hasSIMD128())) {
1241 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1242 }
1243 return Register();
1244}
1245
1246Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v4i32_r(MVT RetVT, Register Op0) {
1247 if (RetVT.SimpleTy != MVT::v2i64)
1248 return Register();
1249 if ((Subtarget->hasSIMD128())) {
1250 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_s_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1251 }
1252 return Register();
1253}
1254
1255Register fastEmit_WebAssemblyISD_EXTEND_HIGH_S_r(MVT VT, MVT RetVT, Register Op0) {
1256 switch (VT.SimpleTy) {
1257 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v16i8_r(RetVT, Op0);
1258 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v8i16_r(RetVT, Op0);
1259 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_MVT_v4i32_r(RetVT, Op0);
1260 default: return Register();
1261 }
1262}
1263
1264// FastEmit functions for WebAssemblyISD::EXTEND_HIGH_U.
1265
1266Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v16i8_r(MVT RetVT, Register Op0) {
1267 if (RetVT.SimpleTy != MVT::v8i16)
1268 return Register();
1269 if ((Subtarget->hasSIMD128())) {
1270 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1271 }
1272 return Register();
1273}
1274
1275Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v8i16_r(MVT RetVT, Register Op0) {
1276 if (RetVT.SimpleTy != MVT::v4i32)
1277 return Register();
1278 if ((Subtarget->hasSIMD128())) {
1279 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1280 }
1281 return Register();
1282}
1283
1284Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v4i32_r(MVT RetVT, Register Op0) {
1285 if (RetVT.SimpleTy != MVT::v2i64)
1286 return Register();
1287 if ((Subtarget->hasSIMD128())) {
1288 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_high_u_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1289 }
1290 return Register();
1291}
1292
1293Register fastEmit_WebAssemblyISD_EXTEND_HIGH_U_r(MVT VT, MVT RetVT, Register Op0) {
1294 switch (VT.SimpleTy) {
1295 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v16i8_r(RetVT, Op0);
1296 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v8i16_r(RetVT, Op0);
1297 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_MVT_v4i32_r(RetVT, Op0);
1298 default: return Register();
1299 }
1300}
1301
1302// FastEmit functions for WebAssemblyISD::EXTEND_LOW_S.
1303
1304Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v16i8_r(MVT RetVT, Register Op0) {
1305 if (RetVT.SimpleTy != MVT::v8i16)
1306 return Register();
1307 if ((Subtarget->hasSIMD128())) {
1308 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1309 }
1310 return Register();
1311}
1312
1313Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v8i16_r(MVT RetVT, Register Op0) {
1314 if (RetVT.SimpleTy != MVT::v4i32)
1315 return Register();
1316 if ((Subtarget->hasSIMD128())) {
1317 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1318 }
1319 return Register();
1320}
1321
1322Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v4i32_r(MVT RetVT, Register Op0) {
1323 if (RetVT.SimpleTy != MVT::v2i64)
1324 return Register();
1325 if ((Subtarget->hasSIMD128())) {
1326 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_s_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1327 }
1328 return Register();
1329}
1330
1331Register fastEmit_WebAssemblyISD_EXTEND_LOW_S_r(MVT VT, MVT RetVT, Register Op0) {
1332 switch (VT.SimpleTy) {
1333 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v16i8_r(RetVT, Op0);
1334 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v8i16_r(RetVT, Op0);
1335 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_MVT_v4i32_r(RetVT, Op0);
1336 default: return Register();
1337 }
1338}
1339
1340// FastEmit functions for WebAssemblyISD::EXTEND_LOW_U.
1341
1342Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v16i8_r(MVT RetVT, Register Op0) {
1343 if (RetVT.SimpleTy != MVT::v8i16)
1344 return Register();
1345 if ((Subtarget->hasSIMD128())) {
1346 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1347 }
1348 return Register();
1349}
1350
1351Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v8i16_r(MVT RetVT, Register Op0) {
1352 if (RetVT.SimpleTy != MVT::v4i32)
1353 return Register();
1354 if ((Subtarget->hasSIMD128())) {
1355 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1356 }
1357 return Register();
1358}
1359
1360Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v4i32_r(MVT RetVT, Register Op0) {
1361 if (RetVT.SimpleTy != MVT::v2i64)
1362 return Register();
1363 if ((Subtarget->hasSIMD128())) {
1364 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extend_low_u_I64x2, RC: &WebAssembly::V128RegClass, Op0);
1365 }
1366 return Register();
1367}
1368
1369Register fastEmit_WebAssemblyISD_EXTEND_LOW_U_r(MVT VT, MVT RetVT, Register Op0) {
1370 switch (VT.SimpleTy) {
1371 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v16i8_r(RetVT, Op0);
1372 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v8i16_r(RetVT, Op0);
1373 case MVT::v4i32: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_MVT_v4i32_r(RetVT, Op0);
1374 default: return Register();
1375 }
1376}
1377
1378// FastEmit functions for WebAssemblyISD::EXT_ADD_PAIRWISE_S.
1379
1380Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v16i8_r(MVT RetVT, Register Op0) {
1381 if (RetVT.SimpleTy != MVT::v8i16)
1382 return Register();
1383 if ((Subtarget->hasSIMD128())) {
1384 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_s_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1385 }
1386 return Register();
1387}
1388
1389Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v8i16_r(MVT RetVT, Register Op0) {
1390 if (RetVT.SimpleTy != MVT::v4i32)
1391 return Register();
1392 if ((Subtarget->hasSIMD128())) {
1393 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1394 }
1395 return Register();
1396}
1397
1398Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_r(MVT VT, MVT RetVT, Register Op0) {
1399 switch (VT.SimpleTy) {
1400 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v16i8_r(RetVT, Op0);
1401 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_MVT_v8i16_r(RetVT, Op0);
1402 default: return Register();
1403 }
1404}
1405
1406// FastEmit functions for WebAssemblyISD::EXT_ADD_PAIRWISE_U.
1407
1408Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v16i8_r(MVT RetVT, Register Op0) {
1409 if (RetVT.SimpleTy != MVT::v8i16)
1410 return Register();
1411 if ((Subtarget->hasSIMD128())) {
1412 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_u_I16x8, RC: &WebAssembly::V128RegClass, Op0);
1413 }
1414 return Register();
1415}
1416
1417Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v8i16_r(MVT RetVT, Register Op0) {
1418 if (RetVT.SimpleTy != MVT::v4i32)
1419 return Register();
1420 if ((Subtarget->hasSIMD128())) {
1421 return fastEmitInst_r(MachineInstOpcode: WebAssembly::extadd_pairwise_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1422 }
1423 return Register();
1424}
1425
1426Register fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_r(MVT VT, MVT RetVT, Register Op0) {
1427 switch (VT.SimpleTy) {
1428 case MVT::v16i8: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v16i8_r(RetVT, Op0);
1429 case MVT::v8i16: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_MVT_v8i16_r(RetVT, Op0);
1430 default: return Register();
1431 }
1432}
1433
1434// FastEmit functions for WebAssemblyISD::PROMOTE_LOW.
1435
1436Register fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v4f32_r(MVT RetVT, Register Op0) {
1437 if (RetVT.SimpleTy != MVT::v2f64)
1438 return Register();
1439 if ((Subtarget->hasSIMD128())) {
1440 return fastEmitInst_r(MachineInstOpcode: WebAssembly::promote_low_F64x2, RC: &WebAssembly::V128RegClass, Op0);
1441 }
1442 return Register();
1443}
1444
1445Register fastEmit_WebAssemblyISD_PROMOTE_LOW_r(MVT VT, MVT RetVT, Register Op0) {
1446 switch (VT.SimpleTy) {
1447 case MVT::v4f32: return fastEmit_WebAssemblyISD_PROMOTE_LOW_MVT_v4f32_r(RetVT, Op0);
1448 default: return Register();
1449 }
1450}
1451
1452// FastEmit functions for WebAssemblyISD::TRUNC_SAT_ZERO_S.
1453
1454Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_MVT_v2f64_r(MVT RetVT, Register Op0) {
1455 if (RetVT.SimpleTy != MVT::v4i32)
1456 return Register();
1457 if ((Subtarget->hasSIMD128())) {
1458 return fastEmitInst_r(MachineInstOpcode: WebAssembly::trunc_sat_zero_s_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1459 }
1460 return Register();
1461}
1462
1463Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_r(MVT VT, MVT RetVT, Register Op0) {
1464 switch (VT.SimpleTy) {
1465 case MVT::v2f64: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_MVT_v2f64_r(RetVT, Op0);
1466 default: return Register();
1467 }
1468}
1469
1470// FastEmit functions for WebAssemblyISD::TRUNC_SAT_ZERO_U.
1471
1472Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_MVT_v2f64_r(MVT RetVT, Register Op0) {
1473 if (RetVT.SimpleTy != MVT::v4i32)
1474 return Register();
1475 if ((Subtarget->hasSIMD128())) {
1476 return fastEmitInst_r(MachineInstOpcode: WebAssembly::trunc_sat_zero_u_I32x4, RC: &WebAssembly::V128RegClass, Op0);
1477 }
1478 return Register();
1479}
1480
1481Register fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_r(MVT VT, MVT RetVT, Register Op0) {
1482 switch (VT.SimpleTy) {
1483 case MVT::v2f64: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_MVT_v2f64_r(RetVT, Op0);
1484 default: return Register();
1485 }
1486}
1487
1488// Top-level FastEmit function.
1489
1490Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
1491 switch (Opcode) {
1492 case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0);
1493 case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0);
1494 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1495 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1496 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1497 case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0);
1498 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1499 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0);
1500 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0);
1501 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0);
1502 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1503 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1504 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1505 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1506 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1507 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1508 case ISD::FROUNDEVEN: return fastEmit_ISD_FROUNDEVEN_r(VT, RetVT, Op0);
1509 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1510 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0);
1511 case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0);
1512 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1513 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1514 case ISD::SPLAT_VECTOR: return fastEmit_ISD_SPLAT_VECTOR_r(VT, RetVT, Op0);
1515 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0);
1516 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1517 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0);
1518 case WebAssemblyISD::BR_TABLE: return fastEmit_WebAssemblyISD_BR_TABLE_r(VT, RetVT, Op0);
1519 case WebAssemblyISD::CONVERT_LOW_S: return fastEmit_WebAssemblyISD_CONVERT_LOW_S_r(VT, RetVT, Op0);
1520 case WebAssemblyISD::CONVERT_LOW_U: return fastEmit_WebAssemblyISD_CONVERT_LOW_U_r(VT, RetVT, Op0);
1521 case WebAssemblyISD::DEMOTE_ZERO: return fastEmit_WebAssemblyISD_DEMOTE_ZERO_r(VT, RetVT, Op0);
1522 case WebAssemblyISD::EXTEND_HIGH_S: return fastEmit_WebAssemblyISD_EXTEND_HIGH_S_r(VT, RetVT, Op0);
1523 case WebAssemblyISD::EXTEND_HIGH_U: return fastEmit_WebAssemblyISD_EXTEND_HIGH_U_r(VT, RetVT, Op0);
1524 case WebAssemblyISD::EXTEND_LOW_S: return fastEmit_WebAssemblyISD_EXTEND_LOW_S_r(VT, RetVT, Op0);
1525 case WebAssemblyISD::EXTEND_LOW_U: return fastEmit_WebAssemblyISD_EXTEND_LOW_U_r(VT, RetVT, Op0);
1526 case WebAssemblyISD::EXT_ADD_PAIRWISE_S: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_S_r(VT, RetVT, Op0);
1527 case WebAssemblyISD::EXT_ADD_PAIRWISE_U: return fastEmit_WebAssemblyISD_EXT_ADD_PAIRWISE_U_r(VT, RetVT, Op0);
1528 case WebAssemblyISD::PROMOTE_LOW: return fastEmit_WebAssemblyISD_PROMOTE_LOW_r(VT, RetVT, Op0);
1529 case WebAssemblyISD::TRUNC_SAT_ZERO_S: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_S_r(VT, RetVT, Op0);
1530 case WebAssemblyISD::TRUNC_SAT_ZERO_U: return fastEmit_WebAssemblyISD_TRUNC_SAT_ZERO_U_r(VT, RetVT, Op0);
1531 default: return Register();
1532 }
1533}
1534
1535// FastEmit functions for ISD::ADD.
1536
1537Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1538 if (RetVT.SimpleTy != MVT::i32)
1539 return Register();
1540 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
1541}
1542
1543Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1544 if (RetVT.SimpleTy != MVT::i64)
1545 return Register();
1546 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
1547}
1548
1549Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1550 if (RetVT.SimpleTy != MVT::v16i8)
1551 return Register();
1552 if ((Subtarget->hasSIMD128())) {
1553 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
1554 }
1555 return Register();
1556}
1557
1558Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1559 if (RetVT.SimpleTy != MVT::v8i16)
1560 return Register();
1561 if ((Subtarget->hasSIMD128())) {
1562 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1563 }
1564 return Register();
1565}
1566
1567Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1568 if (RetVT.SimpleTy != MVT::v4i32)
1569 return Register();
1570 if ((Subtarget->hasSIMD128())) {
1571 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1572 }
1573 return Register();
1574}
1575
1576Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1577 if (RetVT.SimpleTy != MVT::v2i64)
1578 return Register();
1579 if ((Subtarget->hasSIMD128())) {
1580 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1581 }
1582 return Register();
1583}
1584
1585Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1586 switch (VT.SimpleTy) {
1587 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1588 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1589 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1590 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1591 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1592 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1593 default: return Register();
1594 }
1595}
1596
1597// FastEmit functions for ISD::AND.
1598
1599Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1600 if (RetVT.SimpleTy != MVT::i32)
1601 return Register();
1602 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
1603}
1604
1605Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1606 if (RetVT.SimpleTy != MVT::i64)
1607 return Register();
1608 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
1609}
1610
1611Register fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1612 if (RetVT.SimpleTy != MVT::v16i8)
1613 return Register();
1614 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1615}
1616
1617Register fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1618 if (RetVT.SimpleTy != MVT::v8i16)
1619 return Register();
1620 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1621}
1622
1623Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1624 if (RetVT.SimpleTy != MVT::v4i32)
1625 return Register();
1626 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1627}
1628
1629Register fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1630 if (RetVT.SimpleTy != MVT::v2i64)
1631 return Register();
1632 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AND, RC: &WebAssembly::V128RegClass, Op0, Op1);
1633}
1634
1635Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1636 switch (VT.SimpleTy) {
1637 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1638 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1639 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1640 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1641 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1642 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1643 default: return Register();
1644 }
1645}
1646
1647// FastEmit functions for ISD::AVGCEILU.
1648
1649Register fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1650 if (RetVT.SimpleTy != MVT::v16i8)
1651 return Register();
1652 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AVGR_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
1653}
1654
1655Register fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1656 if (RetVT.SimpleTy != MVT::v8i16)
1657 return Register();
1658 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::AVGR_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1659}
1660
1661Register fastEmit_ISD_AVGCEILU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1662 switch (VT.SimpleTy) {
1663 case MVT::v16i8: return fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(RetVT, Op0, Op1);
1664 case MVT::v8i16: return fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(RetVT, Op0, Op1);
1665 default: return Register();
1666 }
1667}
1668
1669// FastEmit functions for ISD::FADD.
1670
1671Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1672 if (RetVT.SimpleTy != MVT::f32)
1673 return Register();
1674 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1675}
1676
1677Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1678 if (RetVT.SimpleTy != MVT::f64)
1679 return Register();
1680 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1681}
1682
1683Register fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1684 if (RetVT.SimpleTy != MVT::v8f16)
1685 return Register();
1686 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1687 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1688 }
1689 return Register();
1690}
1691
1692Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1693 if (RetVT.SimpleTy != MVT::v4f32)
1694 return Register();
1695 if ((Subtarget->hasSIMD128())) {
1696 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1697 }
1698 return Register();
1699}
1700
1701Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1702 if (RetVT.SimpleTy != MVT::v2f64)
1703 return Register();
1704 if ((Subtarget->hasSIMD128())) {
1705 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1706 }
1707 return Register();
1708}
1709
1710Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1711 switch (VT.SimpleTy) {
1712 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1713 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1714 case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op1);
1715 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1716 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1717 default: return Register();
1718 }
1719}
1720
1721// FastEmit functions for ISD::FCOPYSIGN.
1722
1723Register fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1724 if (RetVT.SimpleTy != MVT::f32)
1725 return Register();
1726 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::COPYSIGN_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1727}
1728
1729Register fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1730 if (RetVT.SimpleTy != MVT::f64)
1731 return Register();
1732 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::COPYSIGN_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1733}
1734
1735Register fastEmit_ISD_FCOPYSIGN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1736 switch (VT.SimpleTy) {
1737 case MVT::f32: return fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(RetVT, Op0, Op1);
1738 case MVT::f64: return fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(RetVT, Op0, Op1);
1739 default: return Register();
1740 }
1741}
1742
1743// FastEmit functions for ISD::FDIV.
1744
1745Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1746 if (RetVT.SimpleTy != MVT::f32)
1747 return Register();
1748 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1749}
1750
1751Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1752 if (RetVT.SimpleTy != MVT::f64)
1753 return Register();
1754 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1755}
1756
1757Register fastEmit_ISD_FDIV_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1758 if (RetVT.SimpleTy != MVT::v8f16)
1759 return Register();
1760 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1761 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1762 }
1763 return Register();
1764}
1765
1766Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1767 if (RetVT.SimpleTy != MVT::v4f32)
1768 return Register();
1769 if ((Subtarget->hasSIMD128())) {
1770 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1771 }
1772 return Register();
1773}
1774
1775Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1776 if (RetVT.SimpleTy != MVT::v2f64)
1777 return Register();
1778 if ((Subtarget->hasSIMD128())) {
1779 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1780 }
1781 return Register();
1782}
1783
1784Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1785 switch (VT.SimpleTy) {
1786 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1787 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1788 case MVT::v8f16: return fastEmit_ISD_FDIV_MVT_v8f16_rr(RetVT, Op0, Op1);
1789 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1790 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1791 default: return Register();
1792 }
1793}
1794
1795// FastEmit functions for ISD::FMAXIMUM.
1796
1797Register fastEmit_ISD_FMAXIMUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1798 if (RetVT.SimpleTy != MVT::f32)
1799 return Register();
1800 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1801}
1802
1803Register fastEmit_ISD_FMAXIMUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1804 if (RetVT.SimpleTy != MVT::f64)
1805 return Register();
1806 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1807}
1808
1809Register fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1810 if (RetVT.SimpleTy != MVT::v8f16)
1811 return Register();
1812 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1813 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1814 }
1815 return Register();
1816}
1817
1818Register fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1819 if (RetVT.SimpleTy != MVT::v4f32)
1820 return Register();
1821 if ((Subtarget->hasSIMD128())) {
1822 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1823 }
1824 return Register();
1825}
1826
1827Register fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1828 if (RetVT.SimpleTy != MVT::v2f64)
1829 return Register();
1830 if ((Subtarget->hasSIMD128())) {
1831 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1832 }
1833 return Register();
1834}
1835
1836Register fastEmit_ISD_FMAXIMUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1837 switch (VT.SimpleTy) {
1838 case MVT::f32: return fastEmit_ISD_FMAXIMUM_MVT_f32_rr(RetVT, Op0, Op1);
1839 case MVT::f64: return fastEmit_ISD_FMAXIMUM_MVT_f64_rr(RetVT, Op0, Op1);
1840 case MVT::v8f16: return fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(RetVT, Op0, Op1);
1841 case MVT::v4f32: return fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(RetVT, Op0, Op1);
1842 case MVT::v2f64: return fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(RetVT, Op0, Op1);
1843 default: return Register();
1844 }
1845}
1846
1847// FastEmit functions for ISD::FMINIMUM.
1848
1849Register fastEmit_ISD_FMINIMUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1850 if (RetVT.SimpleTy != MVT::f32)
1851 return Register();
1852 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1853}
1854
1855Register fastEmit_ISD_FMINIMUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1856 if (RetVT.SimpleTy != MVT::f64)
1857 return Register();
1858 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1859}
1860
1861Register fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1862 if (RetVT.SimpleTy != MVT::v8f16)
1863 return Register();
1864 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1865 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1866 }
1867 return Register();
1868}
1869
1870Register fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1871 if (RetVT.SimpleTy != MVT::v4f32)
1872 return Register();
1873 if ((Subtarget->hasSIMD128())) {
1874 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1875 }
1876 return Register();
1877}
1878
1879Register fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1880 if (RetVT.SimpleTy != MVT::v2f64)
1881 return Register();
1882 if ((Subtarget->hasSIMD128())) {
1883 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1884 }
1885 return Register();
1886}
1887
1888Register fastEmit_ISD_FMINIMUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1889 switch (VT.SimpleTy) {
1890 case MVT::f32: return fastEmit_ISD_FMINIMUM_MVT_f32_rr(RetVT, Op0, Op1);
1891 case MVT::f64: return fastEmit_ISD_FMINIMUM_MVT_f64_rr(RetVT, Op0, Op1);
1892 case MVT::v8f16: return fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(RetVT, Op0, Op1);
1893 case MVT::v4f32: return fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(RetVT, Op0, Op1);
1894 case MVT::v2f64: return fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(RetVT, Op0, Op1);
1895 default: return Register();
1896 }
1897}
1898
1899// FastEmit functions for ISD::FMUL.
1900
1901Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1902 if (RetVT.SimpleTy != MVT::f32)
1903 return Register();
1904 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1905}
1906
1907Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1908 if (RetVT.SimpleTy != MVT::f64)
1909 return Register();
1910 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1911}
1912
1913Register fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1914 if (RetVT.SimpleTy != MVT::v8f16)
1915 return Register();
1916 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1917 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1918 }
1919 return Register();
1920}
1921
1922Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1923 if (RetVT.SimpleTy != MVT::v4f32)
1924 return Register();
1925 if ((Subtarget->hasSIMD128())) {
1926 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1927 }
1928 return Register();
1929}
1930
1931Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1932 if (RetVT.SimpleTy != MVT::v2f64)
1933 return Register();
1934 if ((Subtarget->hasSIMD128())) {
1935 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1936 }
1937 return Register();
1938}
1939
1940Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1941 switch (VT.SimpleTy) {
1942 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1943 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1944 case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op1);
1945 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1946 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1947 default: return Register();
1948 }
1949}
1950
1951// FastEmit functions for ISD::FSUB.
1952
1953Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1954 if (RetVT.SimpleTy != MVT::f32)
1955 return Register();
1956 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F32, RC: &WebAssembly::F32RegClass, Op0, Op1);
1957}
1958
1959Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1960 if (RetVT.SimpleTy != MVT::f64)
1961 return Register();
1962 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F64, RC: &WebAssembly::F64RegClass, Op0, Op1);
1963}
1964
1965Register fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, Register Op0, Register Op1) {
1966 if (RetVT.SimpleTy != MVT::v8f16)
1967 return Register();
1968 if ((Subtarget->hasFP16()) && (Subtarget->hasSIMD128())) {
1969 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
1970 }
1971 return Register();
1972}
1973
1974Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1975 if (RetVT.SimpleTy != MVT::v4f32)
1976 return Register();
1977 if ((Subtarget->hasSIMD128())) {
1978 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
1979 }
1980 return Register();
1981}
1982
1983Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1984 if (RetVT.SimpleTy != MVT::v2f64)
1985 return Register();
1986 if ((Subtarget->hasSIMD128())) {
1987 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
1988 }
1989 return Register();
1990}
1991
1992Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1993 switch (VT.SimpleTy) {
1994 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
1995 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
1996 case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op1);
1997 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
1998 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
1999 default: return Register();
2000 }
2001}
2002
2003// FastEmit functions for ISD::MUL.
2004
2005Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2006 if (RetVT.SimpleTy != MVT::i32)
2007 return Register();
2008 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2009}
2010
2011Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2012 if (RetVT.SimpleTy != MVT::i64)
2013 return Register();
2014 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2015}
2016
2017Register fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2018 if (RetVT.SimpleTy != MVT::v8i16)
2019 return Register();
2020 if ((Subtarget->hasSIMD128())) {
2021 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2022 }
2023 return Register();
2024}
2025
2026Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2027 if (RetVT.SimpleTy != MVT::v4i32)
2028 return Register();
2029 if ((Subtarget->hasSIMD128())) {
2030 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2031 }
2032 return Register();
2033}
2034
2035Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2036 if (RetVT.SimpleTy != MVT::v2i64)
2037 return Register();
2038 if ((Subtarget->hasSIMD128())) {
2039 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MUL_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2040 }
2041 return Register();
2042}
2043
2044Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2045 switch (VT.SimpleTy) {
2046 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
2047 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
2048 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
2049 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
2050 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
2051 default: return Register();
2052 }
2053}
2054
2055// FastEmit functions for ISD::OR.
2056
2057Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2058 if (RetVT.SimpleTy != MVT::i32)
2059 return Register();
2060 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2061}
2062
2063Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2064 if (RetVT.SimpleTy != MVT::i64)
2065 return Register();
2066 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2067}
2068
2069Register fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2070 if (RetVT.SimpleTy != MVT::v16i8)
2071 return Register();
2072 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2073}
2074
2075Register fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2076 if (RetVT.SimpleTy != MVT::v8i16)
2077 return Register();
2078 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2079}
2080
2081Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2082 if (RetVT.SimpleTy != MVT::v4i32)
2083 return Register();
2084 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2085}
2086
2087Register fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2088 if (RetVT.SimpleTy != MVT::v2i64)
2089 return Register();
2090 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::OR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2091}
2092
2093Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2094 switch (VT.SimpleTy) {
2095 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
2096 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
2097 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
2098 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
2099 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
2100 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
2101 default: return Register();
2102 }
2103}
2104
2105// FastEmit functions for ISD::ROTL.
2106
2107Register fastEmit_ISD_ROTL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2108 if (RetVT.SimpleTy != MVT::i32)
2109 return Register();
2110 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2111}
2112
2113Register fastEmit_ISD_ROTL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2114 if (RetVT.SimpleTy != MVT::i64)
2115 return Register();
2116 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2117}
2118
2119Register fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2120 switch (VT.SimpleTy) {
2121 case MVT::i32: return fastEmit_ISD_ROTL_MVT_i32_rr(RetVT, Op0, Op1);
2122 case MVT::i64: return fastEmit_ISD_ROTL_MVT_i64_rr(RetVT, Op0, Op1);
2123 default: return Register();
2124 }
2125}
2126
2127// FastEmit functions for ISD::ROTR.
2128
2129Register fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2130 if (RetVT.SimpleTy != MVT::i32)
2131 return Register();
2132 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2133}
2134
2135Register fastEmit_ISD_ROTR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2136 if (RetVT.SimpleTy != MVT::i64)
2137 return Register();
2138 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ROTR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2139}
2140
2141Register fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2142 switch (VT.SimpleTy) {
2143 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
2144 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_rr(RetVT, Op0, Op1);
2145 default: return Register();
2146 }
2147}
2148
2149// FastEmit functions for ISD::SADDSAT.
2150
2151Register fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2152 if (RetVT.SimpleTy != MVT::v16i8)
2153 return Register();
2154 if ((Subtarget->hasSIMD128())) {
2155 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2156 }
2157 return Register();
2158}
2159
2160Register fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2161 if (RetVT.SimpleTy != MVT::v8i16)
2162 return Register();
2163 if ((Subtarget->hasSIMD128())) {
2164 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2165 }
2166 return Register();
2167}
2168
2169Register fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2170 switch (VT.SimpleTy) {
2171 case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2172 case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2173 default: return Register();
2174 }
2175}
2176
2177// FastEmit functions for ISD::SDIV.
2178
2179Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2180 if (RetVT.SimpleTy != MVT::i32)
2181 return Register();
2182 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2183}
2184
2185Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2186 if (RetVT.SimpleTy != MVT::i64)
2187 return Register();
2188 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2189}
2190
2191Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2192 switch (VT.SimpleTy) {
2193 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
2194 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
2195 default: return Register();
2196 }
2197}
2198
2199// FastEmit functions for ISD::SHL.
2200
2201Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2202 if (RetVT.SimpleTy != MVT::i32)
2203 return Register();
2204 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHL_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2205}
2206
2207Register fastEmit_ISD_SHL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2208 if (RetVT.SimpleTy != MVT::i64)
2209 return Register();
2210 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHL_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2211}
2212
2213Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2214 switch (VT.SimpleTy) {
2215 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
2216 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_rr(RetVT, Op0, Op1);
2217 default: return Register();
2218 }
2219}
2220
2221// FastEmit functions for ISD::SMAX.
2222
2223Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2224 if (RetVT.SimpleTy != MVT::v16i8)
2225 return Register();
2226 if ((Subtarget->hasSIMD128())) {
2227 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2228 }
2229 return Register();
2230}
2231
2232Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2233 if (RetVT.SimpleTy != MVT::v8i16)
2234 return Register();
2235 if ((Subtarget->hasSIMD128())) {
2236 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2237 }
2238 return Register();
2239}
2240
2241Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2242 if (RetVT.SimpleTy != MVT::v4i32)
2243 return Register();
2244 if ((Subtarget->hasSIMD128())) {
2245 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_S_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2246 }
2247 return Register();
2248}
2249
2250Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2251 switch (VT.SimpleTy) {
2252 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2253 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2254 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2255 default: return Register();
2256 }
2257}
2258
2259// FastEmit functions for ISD::SMIN.
2260
2261Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2262 if (RetVT.SimpleTy != MVT::v16i8)
2263 return Register();
2264 if ((Subtarget->hasSIMD128())) {
2265 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2266 }
2267 return Register();
2268}
2269
2270Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2271 if (RetVT.SimpleTy != MVT::v8i16)
2272 return Register();
2273 if ((Subtarget->hasSIMD128())) {
2274 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2275 }
2276 return Register();
2277}
2278
2279Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2280 if (RetVT.SimpleTy != MVT::v4i32)
2281 return Register();
2282 if ((Subtarget->hasSIMD128())) {
2283 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_S_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2284 }
2285 return Register();
2286}
2287
2288Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2289 switch (VT.SimpleTy) {
2290 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2291 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2292 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2293 default: return Register();
2294 }
2295}
2296
2297// FastEmit functions for ISD::SRA.
2298
2299Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2300 if (RetVT.SimpleTy != MVT::i32)
2301 return Register();
2302 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2303}
2304
2305Register fastEmit_ISD_SRA_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2306 if (RetVT.SimpleTy != MVT::i64)
2307 return Register();
2308 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2309}
2310
2311Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2312 switch (VT.SimpleTy) {
2313 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2314 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_rr(RetVT, Op0, Op1);
2315 default: return Register();
2316 }
2317}
2318
2319// FastEmit functions for ISD::SREM.
2320
2321Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2322 if (RetVT.SimpleTy != MVT::i32)
2323 return Register();
2324 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_S_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2325}
2326
2327Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2328 if (RetVT.SimpleTy != MVT::i64)
2329 return Register();
2330 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_S_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2331}
2332
2333Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2334 switch (VT.SimpleTy) {
2335 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2336 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2337 default: return Register();
2338 }
2339}
2340
2341// FastEmit functions for ISD::SRL.
2342
2343Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2344 if (RetVT.SimpleTy != MVT::i32)
2345 return Register();
2346 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2347}
2348
2349Register fastEmit_ISD_SRL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2350 if (RetVT.SimpleTy != MVT::i64)
2351 return Register();
2352 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SHR_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2353}
2354
2355Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2356 switch (VT.SimpleTy) {
2357 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2358 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_rr(RetVT, Op0, Op1);
2359 default: return Register();
2360 }
2361}
2362
2363// FastEmit functions for ISD::SSUBSAT.
2364
2365Register fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2366 if (RetVT.SimpleTy != MVT::v16i8)
2367 return Register();
2368 if ((Subtarget->hasSIMD128())) {
2369 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_S_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2370 }
2371 return Register();
2372}
2373
2374Register fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2375 if (RetVT.SimpleTy != MVT::v8i16)
2376 return Register();
2377 if ((Subtarget->hasSIMD128())) {
2378 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_S_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2379 }
2380 return Register();
2381}
2382
2383Register fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2384 switch (VT.SimpleTy) {
2385 case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2386 case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2387 default: return Register();
2388 }
2389}
2390
2391// FastEmit functions for ISD::SUB.
2392
2393Register fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2394 if (RetVT.SimpleTy != MVT::i32)
2395 return Register();
2396 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2397}
2398
2399Register fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2400 if (RetVT.SimpleTy != MVT::i64)
2401 return Register();
2402 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2403}
2404
2405Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2406 if (RetVT.SimpleTy != MVT::v16i8)
2407 return Register();
2408 if ((Subtarget->hasSIMD128())) {
2409 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2410 }
2411 return Register();
2412}
2413
2414Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2415 if (RetVT.SimpleTy != MVT::v8i16)
2416 return Register();
2417 if ((Subtarget->hasSIMD128())) {
2418 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2419 }
2420 return Register();
2421}
2422
2423Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2424 if (RetVT.SimpleTy != MVT::v4i32)
2425 return Register();
2426 if ((Subtarget->hasSIMD128())) {
2427 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2428 }
2429 return Register();
2430}
2431
2432Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2433 if (RetVT.SimpleTy != MVT::v2i64)
2434 return Register();
2435 if ((Subtarget->hasSIMD128())) {
2436 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_I64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2437 }
2438 return Register();
2439}
2440
2441Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2442 switch (VT.SimpleTy) {
2443 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2444 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2445 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2446 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2447 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2448 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2449 default: return Register();
2450 }
2451}
2452
2453// FastEmit functions for ISD::UADDSAT.
2454
2455Register fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2456 if (RetVT.SimpleTy != MVT::v16i8)
2457 return Register();
2458 if ((Subtarget->hasSIMD128())) {
2459 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2460 }
2461 return Register();
2462}
2463
2464Register fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2465 if (RetVT.SimpleTy != MVT::v8i16)
2466 return Register();
2467 if ((Subtarget->hasSIMD128())) {
2468 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::ADD_SAT_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2469 }
2470 return Register();
2471}
2472
2473Register fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2474 switch (VT.SimpleTy) {
2475 case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2476 case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2477 default: return Register();
2478 }
2479}
2480
2481// FastEmit functions for ISD::UDIV.
2482
2483Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2484 if (RetVT.SimpleTy != MVT::i32)
2485 return Register();
2486 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2487}
2488
2489Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2490 if (RetVT.SimpleTy != MVT::i64)
2491 return Register();
2492 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DIV_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2493}
2494
2495Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2496 switch (VT.SimpleTy) {
2497 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2498 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2499 default: return Register();
2500 }
2501}
2502
2503// FastEmit functions for ISD::UMAX.
2504
2505Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2506 if (RetVT.SimpleTy != MVT::v16i8)
2507 return Register();
2508 if ((Subtarget->hasSIMD128())) {
2509 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2510 }
2511 return Register();
2512}
2513
2514Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2515 if (RetVT.SimpleTy != MVT::v8i16)
2516 return Register();
2517 if ((Subtarget->hasSIMD128())) {
2518 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2519 }
2520 return Register();
2521}
2522
2523Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2524 if (RetVT.SimpleTy != MVT::v4i32)
2525 return Register();
2526 if ((Subtarget->hasSIMD128())) {
2527 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MAX_U_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2528 }
2529 return Register();
2530}
2531
2532Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2533 switch (VT.SimpleTy) {
2534 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2535 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2536 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2537 default: return Register();
2538 }
2539}
2540
2541// FastEmit functions for ISD::UMIN.
2542
2543Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2544 if (RetVT.SimpleTy != MVT::v16i8)
2545 return Register();
2546 if ((Subtarget->hasSIMD128())) {
2547 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2548 }
2549 return Register();
2550}
2551
2552Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2553 if (RetVT.SimpleTy != MVT::v8i16)
2554 return Register();
2555 if ((Subtarget->hasSIMD128())) {
2556 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2557 }
2558 return Register();
2559}
2560
2561Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2562 if (RetVT.SimpleTy != MVT::v4i32)
2563 return Register();
2564 if ((Subtarget->hasSIMD128())) {
2565 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::MIN_U_I32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2566 }
2567 return Register();
2568}
2569
2570Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2571 switch (VT.SimpleTy) {
2572 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2573 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2574 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2575 default: return Register();
2576 }
2577}
2578
2579// FastEmit functions for ISD::UREM.
2580
2581Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2582 if (RetVT.SimpleTy != MVT::i32)
2583 return Register();
2584 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_U_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2585}
2586
2587Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2588 if (RetVT.SimpleTy != MVT::i64)
2589 return Register();
2590 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::REM_U_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2591}
2592
2593Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2594 switch (VT.SimpleTy) {
2595 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
2596 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
2597 default: return Register();
2598 }
2599}
2600
2601// FastEmit functions for ISD::USUBSAT.
2602
2603Register fastEmit_ISD_USUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2604 if (RetVT.SimpleTy != MVT::v16i8)
2605 return Register();
2606 if ((Subtarget->hasSIMD128())) {
2607 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2608 }
2609 return Register();
2610}
2611
2612Register fastEmit_ISD_USUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2613 if (RetVT.SimpleTy != MVT::v8i16)
2614 return Register();
2615 if ((Subtarget->hasSIMD128())) {
2616 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SUB_SAT_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2617 }
2618 return Register();
2619}
2620
2621Register fastEmit_ISD_USUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2622 switch (VT.SimpleTy) {
2623 case MVT::v16i8: return fastEmit_ISD_USUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
2624 case MVT::v8i16: return fastEmit_ISD_USUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
2625 default: return Register();
2626 }
2627}
2628
2629// FastEmit functions for ISD::XOR.
2630
2631Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2632 if (RetVT.SimpleTy != MVT::i32)
2633 return Register();
2634 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR_I32, RC: &WebAssembly::I32RegClass, Op0, Op1);
2635}
2636
2637Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2638 if (RetVT.SimpleTy != MVT::i64)
2639 return Register();
2640 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR_I64, RC: &WebAssembly::I64RegClass, Op0, Op1);
2641}
2642
2643Register fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2644 if (RetVT.SimpleTy != MVT::v16i8)
2645 return Register();
2646 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2647}
2648
2649Register fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2650 if (RetVT.SimpleTy != MVT::v8i16)
2651 return Register();
2652 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2653}
2654
2655Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2656 if (RetVT.SimpleTy != MVT::v4i32)
2657 return Register();
2658 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2659}
2660
2661Register fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2662 if (RetVT.SimpleTy != MVT::v2i64)
2663 return Register();
2664 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::XOR, RC: &WebAssembly::V128RegClass, Op0, Op1);
2665}
2666
2667Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2668 switch (VT.SimpleTy) {
2669 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
2670 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
2671 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
2672 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
2673 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
2674 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
2675 default: return Register();
2676 }
2677}
2678
2679// FastEmit functions for WebAssemblyISD::DOT.
2680
2681Register fastEmit_WebAssemblyISD_DOT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2682 if (RetVT.SimpleTy != MVT::v4i32)
2683 return Register();
2684 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::DOT, RC: &WebAssembly::V128RegClass, Op0, Op1);
2685}
2686
2687Register fastEmit_WebAssemblyISD_DOT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2688 switch (VT.SimpleTy) {
2689 case MVT::v8i16: return fastEmit_WebAssemblyISD_DOT_MVT_v8i16_rr(RetVT, Op0, Op1);
2690 default: return Register();
2691 }
2692}
2693
2694// FastEmit functions for WebAssemblyISD::NARROW_U.
2695
2696Register fastEmit_WebAssemblyISD_NARROW_U_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2697 if (RetVT.SimpleTy != MVT::v16i8)
2698 return Register();
2699 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::NARROW_U_I8x16, RC: &WebAssembly::V128RegClass, Op0, Op1);
2700}
2701
2702Register fastEmit_WebAssemblyISD_NARROW_U_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2703 if (RetVT.SimpleTy != MVT::v8i16)
2704 return Register();
2705 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::NARROW_U_I16x8, RC: &WebAssembly::V128RegClass, Op0, Op1);
2706}
2707
2708Register fastEmit_WebAssemblyISD_NARROW_U_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2709 switch (VT.SimpleTy) {
2710 case MVT::v8i16: return fastEmit_WebAssemblyISD_NARROW_U_MVT_v8i16_rr(RetVT, Op0, Op1);
2711 case MVT::v4i32: return fastEmit_WebAssemblyISD_NARROW_U_MVT_v4i32_rr(RetVT, Op0, Op1);
2712 default: return Register();
2713 }
2714}
2715
2716// FastEmit functions for WebAssemblyISD::RELAXED_FMAX.
2717
2718Register fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
2719 if (RetVT.SimpleTy != MVT::v4f32)
2720 return Register();
2721 if ((Subtarget->hasRelaxedSIMD())) {
2722 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMAX_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2723 }
2724 return Register();
2725}
2726
2727Register fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
2728 if (RetVT.SimpleTy != MVT::v2f64)
2729 return Register();
2730 if ((Subtarget->hasRelaxedSIMD())) {
2731 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMAX_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2732 }
2733 return Register();
2734}
2735
2736Register fastEmit_WebAssemblyISD_RELAXED_FMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2737 switch (VT.SimpleTy) {
2738 case MVT::v4f32: return fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v4f32_rr(RetVT, Op0, Op1);
2739 case MVT::v2f64: return fastEmit_WebAssemblyISD_RELAXED_FMAX_MVT_v2f64_rr(RetVT, Op0, Op1);
2740 default: return Register();
2741 }
2742}
2743
2744// FastEmit functions for WebAssemblyISD::RELAXED_FMIN.
2745
2746Register fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
2747 if (RetVT.SimpleTy != MVT::v4f32)
2748 return Register();
2749 if ((Subtarget->hasRelaxedSIMD())) {
2750 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMIN_F32x4, RC: &WebAssembly::V128RegClass, Op0, Op1);
2751 }
2752 return Register();
2753}
2754
2755Register fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
2756 if (RetVT.SimpleTy != MVT::v2f64)
2757 return Register();
2758 if ((Subtarget->hasRelaxedSIMD())) {
2759 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SIMD_RELAXED_FMIN_F64x2, RC: &WebAssembly::V128RegClass, Op0, Op1);
2760 }
2761 return Register();
2762}
2763
2764Register fastEmit_WebAssemblyISD_RELAXED_FMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2765 switch (VT.SimpleTy) {
2766 case MVT::v4f32: return fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v4f32_rr(RetVT, Op0, Op1);
2767 case MVT::v2f64: return fastEmit_WebAssemblyISD_RELAXED_FMIN_MVT_v2f64_rr(RetVT, Op0, Op1);
2768 default: return Register();
2769 }
2770}
2771
2772// FastEmit functions for WebAssemblyISD::SWIZZLE.
2773
2774Register fastEmit_WebAssemblyISD_SWIZZLE_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2775 if (RetVT.SimpleTy != MVT::v16i8)
2776 return Register();
2777 if ((Subtarget->hasSIMD128())) {
2778 return fastEmitInst_rr(MachineInstOpcode: WebAssembly::SWIZZLE, RC: &WebAssembly::V128RegClass, Op0, Op1);
2779 }
2780 return Register();
2781}
2782
2783Register fastEmit_WebAssemblyISD_SWIZZLE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2784 switch (VT.SimpleTy) {
2785 case MVT::v16i8: return fastEmit_WebAssemblyISD_SWIZZLE_MVT_v16i8_rr(RetVT, Op0, Op1);
2786 default: return Register();
2787 }
2788}
2789
2790// Top-level FastEmit function.
2791
2792Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
2793 switch (Opcode) {
2794 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
2795 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
2796 case ISD::AVGCEILU: return fastEmit_ISD_AVGCEILU_rr(VT, RetVT, Op0, Op1);
2797 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
2798 case ISD::FCOPYSIGN: return fastEmit_ISD_FCOPYSIGN_rr(VT, RetVT, Op0, Op1);
2799 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
2800 case ISD::FMAXIMUM: return fastEmit_ISD_FMAXIMUM_rr(VT, RetVT, Op0, Op1);
2801 case ISD::FMINIMUM: return fastEmit_ISD_FMINIMUM_rr(VT, RetVT, Op0, Op1);
2802 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
2803 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
2804 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
2805 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
2806 case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op1);
2807 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
2808 case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op1);
2809 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
2810 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
2811 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
2812 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
2813 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
2814 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
2815 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
2816 case ISD::SSUBSAT: return fastEmit_ISD_SSUBSAT_rr(VT, RetVT, Op0, Op1);
2817 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
2818 case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op1);
2819 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
2820 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
2821 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
2822 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
2823 case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op1);
2824 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
2825 case WebAssemblyISD::DOT: return fastEmit_WebAssemblyISD_DOT_rr(VT, RetVT, Op0, Op1);
2826 case WebAssemblyISD::NARROW_U: return fastEmit_WebAssemblyISD_NARROW_U_rr(VT, RetVT, Op0, Op1);
2827 case WebAssemblyISD::RELAXED_FMAX: return fastEmit_WebAssemblyISD_RELAXED_FMAX_rr(VT, RetVT, Op0, Op1);
2828 case WebAssemblyISD::RELAXED_FMIN: return fastEmit_WebAssemblyISD_RELAXED_FMIN_rr(VT, RetVT, Op0, Op1);
2829 case WebAssemblyISD::SWIZZLE: return fastEmit_WebAssemblyISD_SWIZZLE_rr(VT, RetVT, Op0, Op1);
2830 default: return Register();
2831 }
2832}
2833
2834// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2835
2836Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(MVT RetVT, Register Op0, uint64_t imm1) {
2837 if (RetVT.SimpleTy != MVT::i32)
2838 return Register();
2839 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I8x16_u, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2840}
2841
2842Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2843 switch (VT.SimpleTy) {
2844 case MVT::v16i8: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(RetVT, Op0, imm1);
2845 default: return Register();
2846 }
2847}
2848
2849// Top-level FastEmit function.
2850
2851Register fastEmit_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2852 switch (Opcode) {
2853 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(VT, RetVT, Op0, imm1);
2854 default: return Register();
2855 }
2856}
2857
2858// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2859
2860Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(MVT RetVT, Register Op0, uint64_t imm1) {
2861 if (RetVT.SimpleTy != MVT::i32)
2862 return Register();
2863 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I16x8_u, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2864}
2865
2866Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2867 switch (VT.SimpleTy) {
2868 case MVT::v8i16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(RetVT, Op0, imm1);
2869 default: return Register();
2870 }
2871}
2872
2873// Top-level FastEmit function.
2874
2875Register fastEmit_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2876 switch (Opcode) {
2877 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(VT, RetVT, Op0, imm1);
2878 default: return Register();
2879 }
2880}
2881
2882// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2883
2884Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(MVT RetVT, Register Op0, uint64_t imm1) {
2885 if (RetVT.SimpleTy != MVT::i32)
2886 return Register();
2887 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I32x4, RC: &WebAssembly::I32RegClass, Op0, Imm: imm1);
2888}
2889
2890Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(MVT RetVT, Register Op0, uint64_t imm1) {
2891 if (RetVT.SimpleTy != MVT::f32)
2892 return Register();
2893 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_F32x4, RC: &WebAssembly::F32RegClass, Op0, Imm: imm1);
2894}
2895
2896Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2897 switch (VT.SimpleTy) {
2898 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(RetVT, Op0, imm1);
2899 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(RetVT, Op0, imm1);
2900 default: return Register();
2901 }
2902}
2903
2904// Top-level FastEmit function.
2905
2906Register fastEmit_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2907 switch (Opcode) {
2908 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(VT, RetVT, Op0, imm1);
2909 default: return Register();
2910 }
2911}
2912
2913// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
2914
2915Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(MVT RetVT, Register Op0, uint64_t imm1) {
2916 if (RetVT.SimpleTy != MVT::i64)
2917 return Register();
2918 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_I64x2, RC: &WebAssembly::I64RegClass, Op0, Imm: imm1);
2919}
2920
2921Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(MVT RetVT, Register Op0, uint64_t imm1) {
2922 if (RetVT.SimpleTy != MVT::f64)
2923 return Register();
2924 return fastEmitInst_ri(MachineInstOpcode: WebAssembly::EXTRACT_LANE_F64x2, RC: &WebAssembly::F64RegClass, Op0, Imm: imm1);
2925}
2926
2927Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
2928 switch (VT.SimpleTy) {
2929 case MVT::v2i64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(RetVT, Op0, imm1);
2930 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(RetVT, Op0, imm1);
2931 default: return Register();
2932 }
2933}
2934
2935// Top-level FastEmit function.
2936
2937Register fastEmit_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
2938 switch (Opcode) {
2939 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(VT, RetVT, Op0, imm1);
2940 default: return Register();
2941 }
2942}
2943
2944// FastEmit functions for ISD::ConstantFP.
2945
2946Register fastEmit_ISD_ConstantFP_MVT_f32_f(MVT RetVT, const ConstantFP *f0) {
2947 if (RetVT.SimpleTy != MVT::f32)
2948 return Register();
2949 return fastEmitInst_f(MachineInstOpcode: WebAssembly::CONST_F32, RC: &WebAssembly::F32RegClass, FPImm: f0);
2950}
2951
2952Register fastEmit_ISD_ConstantFP_MVT_f64_f(MVT RetVT, const ConstantFP *f0) {
2953 if (RetVT.SimpleTy != MVT::f64)
2954 return Register();
2955 return fastEmitInst_f(MachineInstOpcode: WebAssembly::CONST_F64, RC: &WebAssembly::F64RegClass, FPImm: f0);
2956}
2957
2958Register fastEmit_ISD_ConstantFP_f(MVT VT, MVT RetVT, const ConstantFP *f0) {
2959 switch (VT.SimpleTy) {
2960 case MVT::f32: return fastEmit_ISD_ConstantFP_MVT_f32_f(RetVT, f0);
2961 case MVT::f64: return fastEmit_ISD_ConstantFP_MVT_f64_f(RetVT, f0);
2962 default: return Register();
2963 }
2964}
2965
2966// Top-level FastEmit function.
2967
2968Register fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *f0) override {
2969 switch (Opcode) {
2970 case ISD::ConstantFP: return fastEmit_ISD_ConstantFP_f(VT, RetVT, f0);
2971 default: return Register();
2972 }
2973}
2974
2975// FastEmit functions for ISD::Constant.
2976
2977Register fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
2978 if (RetVT.SimpleTy != MVT::i32)
2979 return Register();
2980 return fastEmitInst_i(MachineInstOpcode: WebAssembly::CONST_I32, RC: &WebAssembly::I32RegClass, Imm: imm0);
2981}
2982
2983Register fastEmit_ISD_Constant_MVT_i64_i(MVT RetVT, uint64_t imm0) {
2984 if (RetVT.SimpleTy != MVT::i64)
2985 return Register();
2986 return fastEmitInst_i(MachineInstOpcode: WebAssembly::CONST_I64, RC: &WebAssembly::I64RegClass, Imm: imm0);
2987}
2988
2989Register fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
2990 switch (VT.SimpleTy) {
2991 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
2992 case MVT::i64: return fastEmit_ISD_Constant_MVT_i64_i(RetVT, imm0);
2993 default: return Register();
2994 }
2995}
2996
2997// Top-level FastEmit function.
2998
2999Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
3000 switch (Opcode) {
3001 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
3002 default: return Register();
3003 }
3004}
3005
3006