1//===-- WebAssemblyFastISel.cpp - WebAssembly FastISel implementation -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file defines the WebAssembly-specific support for the FastISel
11/// class. Some of the target-specific code is generated by tablegen in the file
12/// WebAssemblyGenFastISel.inc, which is #included here.
13///
14/// TODO: kill flags
15///
16//===----------------------------------------------------------------------===//
17
18#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
19#include "Utils/WasmAddressSpaces.h"
20#include "Utils/WebAssemblyTypeUtilities.h"
21#include "WebAssemblyMachineFunctionInfo.h"
22#include "WebAssemblySubtarget.h"
23#include "WebAssemblyUtilities.h"
24#include "llvm/Analysis/BranchProbabilityInfo.h"
25#include "llvm/CodeGen/FastISel.h"
26#include "llvm/CodeGen/FunctionLoweringInfo.h"
27#include "llvm/CodeGen/MachineConstantPool.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineModuleInfo.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/IR/DataLayout.h"
33#include "llvm/IR/DerivedTypes.h"
34#include "llvm/IR/Function.h"
35#include "llvm/IR/GetElementPtrTypeIterator.h"
36#include "llvm/IR/GlobalVariable.h"
37#include "llvm/IR/Instructions.h"
38#include "llvm/IR/IntrinsicsWebAssembly.h"
39#include "llvm/IR/Operator.h"
40
41using namespace llvm;
42
43#define DEBUG_TYPE "wasm-fastisel"
44
45namespace {
46
47class WebAssemblyFastISel final : public FastISel {
48 // All possible address modes.
49 class Address {
50 public:
51 enum BaseKind { RegBase, FrameIndexBase };
52
53 private:
54 BaseKind Kind = RegBase;
55 union {
56 unsigned Reg;
57 int FI;
58 } Base;
59
60 // Whether the base has been determined yet
61 bool IsBaseSet = false;
62
63 int64_t Offset = 0;
64
65 const GlobalValue *GV = nullptr;
66
67 public:
68 // Innocuous defaults for our address.
69 Address() { Base.Reg = 0; }
70 void setKind(BaseKind K) {
71 assert(!isSet() && "Can't change kind with non-zero base");
72 Kind = K;
73 }
74 BaseKind getKind() const { return Kind; }
75 bool isRegBase() const { return Kind == RegBase; }
76 bool isFIBase() const { return Kind == FrameIndexBase; }
77 void setReg(unsigned Reg) {
78 assert(isRegBase() && "Invalid base register access!");
79 assert(!IsBaseSet && "Base cannot be reset");
80 Base.Reg = Reg;
81 IsBaseSet = true;
82 }
83 unsigned getReg() const {
84 assert(isRegBase() && "Invalid base register access!");
85 return Base.Reg;
86 }
87 void setFI(unsigned FI) {
88 assert(isFIBase() && "Invalid base frame index access!");
89 assert(!IsBaseSet && "Base cannot be reset");
90 Base.FI = FI;
91 IsBaseSet = true;
92 }
93 unsigned getFI() const {
94 assert(isFIBase() && "Invalid base frame index access!");
95 return Base.FI;
96 }
97
98 void setOffset(int64_t NewOffset) {
99 assert(NewOffset >= 0 && "Offsets must be non-negative");
100 Offset = NewOffset;
101 }
102 int64_t getOffset() const { return Offset; }
103 void setGlobalValue(const GlobalValue *G) { GV = G; }
104 const GlobalValue *getGlobalValue() const { return GV; }
105 bool isSet() const { return IsBaseSet; }
106 };
107
108 /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
109 /// right decision when generating code for different targets.
110 const WebAssemblySubtarget *Subtarget;
111 LLVMContext *Context;
112
113private:
114 // Utility helper routines
115 MVT::SimpleValueType getSimpleType(Type *Ty) {
116 EVT VT = TLI.getValueType(DL, Ty, /*AllowUnknown=*/true);
117 return VT.isSimple() ? VT.getSimpleVT().SimpleTy
118 : MVT::INVALID_SIMPLE_VALUE_TYPE;
119 }
120 MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) {
121 switch (VT) {
122 case MVT::i1:
123 case MVT::i8:
124 case MVT::i16:
125 return MVT::i32;
126 case MVT::i32:
127 case MVT::i64:
128 case MVT::f32:
129 case MVT::f64:
130 return VT;
131 case MVT::funcref:
132 case MVT::externref:
133 if (Subtarget->hasReferenceTypes())
134 return VT;
135 break;
136 case MVT::exnref:
137 if (Subtarget->hasReferenceTypes() && Subtarget->hasExceptionHandling())
138 return VT;
139 break;
140 case MVT::f16:
141 return MVT::f32;
142 case MVT::v16i8:
143 case MVT::v8i16:
144 case MVT::v4i32:
145 case MVT::v4f32:
146 case MVT::v2i64:
147 case MVT::v2f64:
148 if (Subtarget->hasSIMD128())
149 return VT;
150 break;
151 default:
152 break;
153 }
154 return MVT::INVALID_SIMPLE_VALUE_TYPE;
155 }
156 bool computeAddress(const Value *Obj, Address &Addr);
157 void materializeLoadStoreOperands(Address &Addr);
158 void addLoadStoreOperands(const Address &Addr, const MachineInstrBuilder &MIB,
159 MachineMemOperand *MMO);
160 bool emitLoad(Register ResultReg, unsigned Opc, const LoadInst *LoadInst);
161 unsigned maskI1Value(unsigned Reg, const Value *V);
162 unsigned getRegForI1Value(const Value *V, const BasicBlock *BB, bool &Not);
163 unsigned zeroExtendToI32(unsigned Reg, const Value *V,
164 MVT::SimpleValueType From);
165 unsigned signExtendToI32(unsigned Reg, const Value *V,
166 MVT::SimpleValueType From);
167 unsigned zeroExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
168 MVT::SimpleValueType To);
169 unsigned signExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
170 MVT::SimpleValueType To);
171 unsigned getRegForUnsignedValue(const Value *V);
172 unsigned getRegForSignedValue(const Value *V);
173 unsigned getRegForPromotedValue(const Value *V, bool IsSigned);
174 unsigned notValue(unsigned Reg);
175 unsigned copyValue(unsigned Reg);
176
177 // Backend specific FastISel code.
178 Register fastMaterializeAlloca(const AllocaInst *AI) override;
179 Register fastMaterializeConstant(const Constant *C) override;
180 bool fastLowerArguments() override;
181
182 // Selection routines.
183 bool selectCall(const Instruction *I);
184 bool selectSelect(const Instruction *I);
185 bool selectTrunc(const Instruction *I);
186 bool selectZExt(const Instruction *I);
187 bool selectSExt(const Instruction *I);
188 bool selectICmp(const Instruction *I);
189 bool selectFCmp(const Instruction *I);
190 bool selectBitCast(const Instruction *I);
191 bool selectLoad(const Instruction *I);
192 bool selectStore(const Instruction *I);
193 bool selectCondBr(const Instruction *I);
194 bool selectRet(const Instruction *I);
195 bool selectUnreachable(const Instruction *I);
196
197public:
198 // Backend specific FastISel code.
199 WebAssemblyFastISel(FunctionLoweringInfo &FuncInfo,
200 const TargetLibraryInfo *LibInfo,
201 const LibcallLoweringInfo *LibcallLowering)
202 : FastISel(FuncInfo, LibInfo, LibcallLowering,
203 /*SkipTargetIndependentISel=*/true) {
204 Subtarget = &FuncInfo.MF->getSubtarget<WebAssemblySubtarget>();
205 Context = &FuncInfo.Fn->getContext();
206 }
207
208 bool fastSelectInstruction(const Instruction *I) override;
209 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
210 const LoadInst *LI) override;
211
212#include "WebAssemblyGenFastISel.inc"
213};
214
215} // end anonymous namespace
216
217bool WebAssemblyFastISel::computeAddress(const Value *Obj, Address &Addr) {
218 const User *U = nullptr;
219 unsigned Opcode = Instruction::UserOp1;
220 if (const auto *I = dyn_cast<Instruction>(Val: Obj)) {
221 // Don't walk into other basic blocks unless the object is an alloca from
222 // another block, otherwise it may not have a virtual register assigned.
223 if (FuncInfo.StaticAllocaMap.count(Val: static_cast<const AllocaInst *>(Obj)) ||
224 FuncInfo.getMBB(BB: I->getParent()) == FuncInfo.MBB) {
225 Opcode = I->getOpcode();
226 U = I;
227 }
228 } else if (const auto *C = dyn_cast<ConstantExpr>(Val: Obj)) {
229 Opcode = C->getOpcode();
230 U = C;
231 }
232
233 if (auto *Ty = dyn_cast<PointerType>(Val: Obj->getType()))
234 if (Ty->getAddressSpace() > 255)
235 // Fast instruction selection doesn't support the special
236 // address spaces.
237 return false;
238
239 if (const auto *GV = dyn_cast<GlobalValue>(Val: Obj)) {
240 if (TLI.isPositionIndependent())
241 return false;
242 if (Addr.getGlobalValue())
243 return false;
244 if (GV->isThreadLocal())
245 return false;
246 Addr.setGlobalValue(GV);
247 return true;
248 }
249
250 switch (Opcode) {
251 default:
252 break;
253 case Instruction::BitCast: {
254 // Look through bitcasts.
255 return computeAddress(Obj: U->getOperand(i: 0), Addr);
256 }
257 case Instruction::IntToPtr: {
258 // Look past no-op inttoptrs.
259 if (TLI.getValueType(DL, Ty: U->getOperand(i: 0)->getType()) ==
260 TLI.getPointerTy(DL))
261 return computeAddress(Obj: U->getOperand(i: 0), Addr);
262 break;
263 }
264 case Instruction::PtrToInt: {
265 // Look past no-op ptrtoints.
266 if (TLI.getValueType(DL, Ty: U->getType()) == TLI.getPointerTy(DL))
267 return computeAddress(Obj: U->getOperand(i: 0), Addr);
268 break;
269 }
270 case Instruction::GetElementPtr: {
271 Address SavedAddr = Addr;
272 uint64_t TmpOffset = Addr.getOffset();
273 // Non-inbounds geps can wrap; wasm's offsets can't.
274 if (!cast<GEPOperator>(Val: U)->isInBounds())
275 goto unsupported_gep;
276 // Iterate through the GEP folding the constants into offsets where
277 // we can.
278 for (gep_type_iterator GTI = gep_type_begin(GEP: U), E = gep_type_end(GEP: U);
279 GTI != E; ++GTI) {
280 const Value *Op = GTI.getOperand();
281 if (StructType *STy = GTI.getStructTypeOrNull()) {
282 const StructLayout *SL = DL.getStructLayout(Ty: STy);
283 unsigned Idx = cast<ConstantInt>(Val: Op)->getZExtValue();
284 TmpOffset += SL->getElementOffset(Idx);
285 } else {
286 uint64_t S = GTI.getSequentialElementStride(DL);
287 for (;;) {
288 if (const auto *CI = dyn_cast<ConstantInt>(Val: Op)) {
289 // Constant-offset addressing.
290 TmpOffset += CI->getSExtValue() * S;
291 break;
292 }
293 if (S == 1 && Addr.isRegBase() && Addr.getReg() == 0) {
294 // An unscaled add of a register. Set it as the new base.
295 Register Reg = getRegForValue(V: Op);
296 if (Reg == 0)
297 return false;
298 Addr.setReg(Reg);
299 break;
300 }
301 if (canFoldAddIntoGEP(GEP: U, Add: Op)) {
302 // A compatible add with a constant operand. Fold the constant.
303 auto *CI = cast<ConstantInt>(Val: cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 1));
304 TmpOffset += CI->getSExtValue() * S;
305 // Iterate on the other operand.
306 Op = cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 0);
307 continue;
308 }
309 // Unsupported
310 goto unsupported_gep;
311 }
312 }
313 }
314 // Don't fold in negative offsets.
315 if (int64_t(TmpOffset) >= 0) {
316 // Try to grab the base operand now.
317 Addr.setOffset(TmpOffset);
318 if (computeAddress(Obj: U->getOperand(i: 0), Addr))
319 return true;
320 }
321 // We failed, restore everything and try the other options.
322 Addr = SavedAddr;
323 unsupported_gep:
324 break;
325 }
326 case Instruction::Alloca: {
327 const auto *AI = cast<AllocaInst>(Val: Obj);
328 auto SI = FuncInfo.StaticAllocaMap.find(Val: AI);
329 if (SI != FuncInfo.StaticAllocaMap.end()) {
330 if (Addr.isSet()) {
331 return false;
332 }
333 Addr.setKind(Address::FrameIndexBase);
334 Addr.setFI(SI->second);
335 return true;
336 }
337 break;
338 }
339 case Instruction::Add: {
340 // We should not fold operands into an offset when 'nuw' (no unsigned wrap)
341 // is not present, because the address calculation does not wrap.
342 if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(Val: U))
343 if (!OFBinOp->hasNoUnsignedWrap())
344 break;
345
346 // Adds of constants are common and easy enough.
347 const Value *LHS = U->getOperand(i: 0);
348 const Value *RHS = U->getOperand(i: 1);
349
350 if (isa<ConstantInt>(Val: LHS))
351 std::swap(a&: LHS, b&: RHS);
352
353 if (const auto *CI = dyn_cast<ConstantInt>(Val: RHS)) {
354 uint64_t TmpOffset = Addr.getOffset() + CI->getSExtValue();
355 if (int64_t(TmpOffset) >= 0) {
356 Addr.setOffset(TmpOffset);
357 return computeAddress(Obj: LHS, Addr);
358 }
359 }
360
361 Address Backup = Addr;
362 if (computeAddress(Obj: LHS, Addr) && computeAddress(Obj: RHS, Addr))
363 return true;
364 Addr = Backup;
365
366 break;
367 }
368 case Instruction::Sub: {
369 // We should not fold operands into an offset when 'nuw' (no unsigned wrap)
370 // is not present, because the address calculation does not wrap.
371 if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(Val: U))
372 if (!OFBinOp->hasNoUnsignedWrap())
373 break;
374
375 // Subs of constants are common and easy enough.
376 const Value *LHS = U->getOperand(i: 0);
377 const Value *RHS = U->getOperand(i: 1);
378
379 if (const auto *CI = dyn_cast<ConstantInt>(Val: RHS)) {
380 int64_t TmpOffset = Addr.getOffset() - CI->getSExtValue();
381 if (TmpOffset >= 0) {
382 Addr.setOffset(TmpOffset);
383 return computeAddress(Obj: LHS, Addr);
384 }
385 }
386 break;
387 }
388 }
389 if (Addr.isSet()) {
390 return false;
391 }
392 Register Reg = getRegForValue(V: Obj);
393 if (Reg == 0)
394 return false;
395 Addr.setReg(Reg);
396 return Addr.getReg() != 0;
397}
398
399void WebAssemblyFastISel::materializeLoadStoreOperands(Address &Addr) {
400 if (Addr.isRegBase()) {
401 unsigned Reg = Addr.getReg();
402 if (Reg == 0) {
403 Reg = createResultReg(RC: Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
404 : &WebAssembly::I32RegClass);
405 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
406 : WebAssembly::CONST_I32;
407 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: Reg)
408 .addImm(Val: 0);
409 Addr.setReg(Reg);
410 }
411 }
412}
413
414void WebAssemblyFastISel::addLoadStoreOperands(const Address &Addr,
415 const MachineInstrBuilder &MIB,
416 MachineMemOperand *MMO) {
417 // Set the alignment operand (this is rewritten in SetP2AlignOperands).
418 // TODO: Disable SetP2AlignOperands for FastISel and just do it here.
419 MIB.addImm(Val: 0);
420
421 if (const GlobalValue *GV = Addr.getGlobalValue())
422 MIB.addGlobalAddress(GV, Offset: Addr.getOffset());
423 else
424 MIB.addImm(Val: Addr.getOffset());
425
426 if (Addr.isRegBase())
427 MIB.addReg(RegNo: Addr.getReg());
428 else
429 MIB.addFrameIndex(Idx: Addr.getFI());
430
431 MIB.addMemOperand(MMO);
432}
433
434bool WebAssemblyFastISel::emitLoad(Register ResultReg, unsigned Opc,
435 const LoadInst *Load) {
436 Address Addr;
437 if (!computeAddress(Obj: Load->getPointerOperand(), Addr))
438 return false;
439
440 materializeLoadStoreOperands(Addr);
441 auto MIB =
442 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg);
443 addLoadStoreOperands(Addr, MIB, MMO: createMachineMemOperandFor(I: Load));
444
445 return true;
446}
447
448unsigned WebAssemblyFastISel::maskI1Value(unsigned Reg, const Value *V) {
449 return zeroExtendToI32(Reg, V, From: MVT::i1);
450}
451
452unsigned WebAssemblyFastISel::getRegForI1Value(const Value *V,
453 const BasicBlock *BB,
454 bool &Not) {
455 if (const auto *ICmp = dyn_cast<ICmpInst>(Val: V))
456 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: ICmp->getOperand(i_nocapture: 1)))
457 if (ICmp->isEquality() && C->isZero() && C->getType()->isIntegerTy(BitWidth: 32) &&
458 ICmp->getParent() == BB) {
459 Not = ICmp->isTrueWhenEqual();
460 return getRegForValue(V: ICmp->getOperand(i_nocapture: 0));
461 }
462
463 Not = false;
464 Register Reg = getRegForValue(V);
465 if (Reg == 0)
466 return 0;
467 return maskI1Value(Reg, V);
468}
469
470unsigned WebAssemblyFastISel::zeroExtendToI32(unsigned Reg, const Value *V,
471 MVT::SimpleValueType From) {
472 if (Reg == 0)
473 return 0;
474
475 switch (From) {
476 case MVT::i1:
477 // If the value is naturally an i1, we don't need to mask it. We only know
478 // if a value is naturally an i1 if it is definitely lowered by FastISel,
479 // not a DAG ISel fallback.
480 if (V != nullptr && isa<Argument>(Val: V) && cast<Argument>(Val: V)->hasZExtAttr())
481 return copyValue(Reg);
482 break;
483 case MVT::i8:
484 case MVT::i16:
485 break;
486 case MVT::i32:
487 return copyValue(Reg);
488 default:
489 return 0;
490 }
491
492 Register Imm = createResultReg(RC: &WebAssembly::I32RegClass);
493 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
494 MCID: TII.get(Opcode: WebAssembly::CONST_I32), DestReg: Imm)
495 .addImm(Val: ~(~uint64_t(0) << MVT(From).getSizeInBits()));
496
497 Register Result = createResultReg(RC: &WebAssembly::I32RegClass);
498 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: WebAssembly::AND_I32),
499 DestReg: Result)
500 .addReg(RegNo: Reg)
501 .addReg(RegNo: Imm);
502
503 return Result;
504}
505
506unsigned WebAssemblyFastISel::signExtendToI32(unsigned Reg, const Value *V,
507 MVT::SimpleValueType From) {
508 if (Reg == 0)
509 return 0;
510
511 switch (From) {
512 case MVT::i1:
513 case MVT::i8:
514 case MVT::i16:
515 break;
516 case MVT::i32:
517 return copyValue(Reg);
518 default:
519 return 0;
520 }
521
522 if (Subtarget->hasSignExt()) {
523 if (From == MVT::i8 || From == MVT::i16) {
524 Register Result = createResultReg(RC: &WebAssembly::I32RegClass);
525 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
526 MCID: TII.get(Opcode: From == MVT::i16 ? WebAssembly::I32_EXTEND16_S_I32
527 : WebAssembly::I32_EXTEND8_S_I32),
528 DestReg: Result)
529 .addReg(RegNo: Reg);
530 return Result;
531 }
532 }
533
534 Register Imm = createResultReg(RC: &WebAssembly::I32RegClass);
535 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
536 MCID: TII.get(Opcode: WebAssembly::CONST_I32), DestReg: Imm)
537 .addImm(Val: 32 - MVT(From).getSizeInBits());
538
539 Register Left = createResultReg(RC: &WebAssembly::I32RegClass);
540 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: WebAssembly::SHL_I32),
541 DestReg: Left)
542 .addReg(RegNo: Reg)
543 .addReg(RegNo: Imm);
544
545 Register Right = createResultReg(RC: &WebAssembly::I32RegClass);
546 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
547 MCID: TII.get(Opcode: WebAssembly::SHR_S_I32), DestReg: Right)
548 .addReg(RegNo: Left)
549 .addReg(RegNo: Imm);
550
551 return Right;
552}
553
554unsigned WebAssemblyFastISel::zeroExtend(unsigned Reg, const Value *V,
555 MVT::SimpleValueType From,
556 MVT::SimpleValueType To) {
557 if (To == MVT::i64) {
558 if (From == MVT::i64)
559 return copyValue(Reg);
560
561 Reg = zeroExtendToI32(Reg, V, From);
562
563 Register Result = createResultReg(RC: &WebAssembly::I64RegClass);
564 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
565 MCID: TII.get(Opcode: WebAssembly::I64_EXTEND_U_I32), DestReg: Result)
566 .addReg(RegNo: Reg);
567 return Result;
568 }
569
570 if (To == MVT::i32)
571 return zeroExtendToI32(Reg, V, From);
572
573 return 0;
574}
575
576unsigned WebAssemblyFastISel::signExtend(unsigned Reg, const Value *V,
577 MVT::SimpleValueType From,
578 MVT::SimpleValueType To) {
579 if (To == MVT::i64) {
580 if (From == MVT::i64)
581 return copyValue(Reg);
582
583 Register Result = createResultReg(RC: &WebAssembly::I64RegClass);
584
585 if (Subtarget->hasSignExt()) {
586 if (From != MVT::i32) {
587 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
588 MCID: TII.get(Opcode: WebAssembly::I64_EXTEND_U_I32), DestReg: Result)
589 .addReg(RegNo: Reg);
590
591 Reg = Result;
592 Result = createResultReg(RC: &WebAssembly::I64RegClass);
593 }
594
595 switch (From) {
596 case MVT::i8:
597 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
598 MCID: TII.get(Opcode: WebAssembly::I64_EXTEND8_S_I64), DestReg: Result)
599 .addReg(RegNo: Reg);
600 return Result;
601 case MVT::i16:
602 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
603 MCID: TII.get(Opcode: WebAssembly::I64_EXTEND16_S_I64), DestReg: Result)
604 .addReg(RegNo: Reg);
605 return Result;
606 case MVT::i32:
607 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
608 MCID: TII.get(Opcode: WebAssembly::I64_EXTEND_S_I32), DestReg: Result)
609 .addReg(RegNo: Reg);
610 return Result;
611 default:
612 break;
613 }
614 } else {
615 Reg = signExtendToI32(Reg, V, From);
616
617 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
618 MCID: TII.get(Opcode: WebAssembly::I64_EXTEND_S_I32), DestReg: Result)
619 .addReg(RegNo: Reg);
620 }
621
622 return Result;
623 }
624
625 if (To == MVT::i32)
626 return signExtendToI32(Reg, V, From);
627
628 return 0;
629}
630
631unsigned WebAssemblyFastISel::getRegForUnsignedValue(const Value *V) {
632 MVT::SimpleValueType From = getSimpleType(Ty: V->getType());
633 MVT::SimpleValueType To = getLegalType(VT: From);
634 Register VReg = getRegForValue(V);
635 if (VReg == 0)
636 return 0;
637 if (From == To)
638 return VReg;
639 return zeroExtend(Reg: VReg, V, From, To);
640}
641
642unsigned WebAssemblyFastISel::getRegForSignedValue(const Value *V) {
643 MVT::SimpleValueType From = getSimpleType(Ty: V->getType());
644 MVT::SimpleValueType To = getLegalType(VT: From);
645 Register VReg = getRegForValue(V);
646 if (VReg == 0)
647 return 0;
648 if (From == To)
649 return VReg;
650 return signExtend(Reg: VReg, V, From, To);
651}
652
653unsigned WebAssemblyFastISel::getRegForPromotedValue(const Value *V,
654 bool IsSigned) {
655 return IsSigned ? getRegForSignedValue(V) : getRegForUnsignedValue(V);
656}
657
658unsigned WebAssemblyFastISel::notValue(unsigned Reg) {
659 assert(MRI.getRegClass(Reg) == &WebAssembly::I32RegClass);
660
661 Register NotReg = createResultReg(RC: &WebAssembly::I32RegClass);
662 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: WebAssembly::EQZ_I32),
663 DestReg: NotReg)
664 .addReg(RegNo: Reg);
665 return NotReg;
666}
667
668unsigned WebAssemblyFastISel::copyValue(unsigned Reg) {
669 Register ResultReg = createResultReg(RC: MRI.getRegClass(Reg));
670 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: WebAssembly::COPY),
671 DestReg: ResultReg)
672 .addReg(RegNo: Reg);
673 return ResultReg;
674}
675
676Register WebAssemblyFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
677 auto SI = FuncInfo.StaticAllocaMap.find(Val: AI);
678
679 if (SI != FuncInfo.StaticAllocaMap.end()) {
680 Register ResultReg =
681 createResultReg(RC: Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
682 : &WebAssembly::I32RegClass);
683 unsigned Opc =
684 Subtarget->hasAddr64() ? WebAssembly::COPY_I64 : WebAssembly::COPY_I32;
685 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
686 .addFrameIndex(Idx: SI->second);
687 return ResultReg;
688 }
689
690 return Register();
691}
692
693Register WebAssemblyFastISel::fastMaterializeConstant(const Constant *C) {
694 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Val: C)) {
695 if (TLI.isPositionIndependent())
696 return Register();
697 if (GV->isThreadLocal())
698 return Register();
699 Register ResultReg =
700 createResultReg(RC: Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
701 : &WebAssembly::I32RegClass);
702 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
703 : WebAssembly::CONST_I32;
704 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
705 .addGlobalAddress(GV);
706 return ResultReg;
707 }
708
709 // Let target-independent code handle it.
710 return Register();
711}
712
713bool WebAssemblyFastISel::fastLowerArguments() {
714 if (!FuncInfo.CanLowerReturn)
715 return false;
716
717 const Function *F = FuncInfo.Fn;
718 if (F->isVarArg())
719 return false;
720
721 if (FuncInfo.Fn->getCallingConv() == CallingConv::Swift)
722 return false;
723
724 unsigned I = 0;
725 for (auto const &Arg : F->args()) {
726 const AttributeList &Attrs = F->getAttributes();
727 if (Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::ByVal) ||
728 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::SwiftSelf) ||
729 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::SwiftError) ||
730 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::InAlloca) ||
731 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::Nest))
732 return false;
733
734 Type *ArgTy = Arg.getType();
735 if (ArgTy->isStructTy() || ArgTy->isArrayTy())
736 return false;
737 if (!Subtarget->hasSIMD128() && ArgTy->isVectorTy())
738 return false;
739
740 unsigned Opc;
741 const TargetRegisterClass *RC;
742 switch (getSimpleType(Ty: ArgTy)) {
743 case MVT::i1:
744 case MVT::i8:
745 case MVT::i16:
746 case MVT::i32:
747 Opc = WebAssembly::ARGUMENT_i32;
748 RC = &WebAssembly::I32RegClass;
749 break;
750 case MVT::i64:
751 Opc = WebAssembly::ARGUMENT_i64;
752 RC = &WebAssembly::I64RegClass;
753 break;
754 case MVT::f32:
755 Opc = WebAssembly::ARGUMENT_f32;
756 RC = &WebAssembly::F32RegClass;
757 break;
758 case MVT::f64:
759 Opc = WebAssembly::ARGUMENT_f64;
760 RC = &WebAssembly::F64RegClass;
761 break;
762 case MVT::v16i8:
763 Opc = WebAssembly::ARGUMENT_v16i8;
764 RC = &WebAssembly::V128RegClass;
765 break;
766 case MVT::v8i16:
767 Opc = WebAssembly::ARGUMENT_v8i16;
768 RC = &WebAssembly::V128RegClass;
769 break;
770 case MVT::v4i32:
771 Opc = WebAssembly::ARGUMENT_v4i32;
772 RC = &WebAssembly::V128RegClass;
773 break;
774 case MVT::v2i64:
775 Opc = WebAssembly::ARGUMENT_v2i64;
776 RC = &WebAssembly::V128RegClass;
777 break;
778 case MVT::v4f32:
779 Opc = WebAssembly::ARGUMENT_v4f32;
780 RC = &WebAssembly::V128RegClass;
781 break;
782 case MVT::v2f64:
783 Opc = WebAssembly::ARGUMENT_v2f64;
784 RC = &WebAssembly::V128RegClass;
785 break;
786 case MVT::funcref:
787 Opc = WebAssembly::ARGUMENT_funcref;
788 RC = &WebAssembly::FUNCREFRegClass;
789 break;
790 case MVT::externref:
791 Opc = WebAssembly::ARGUMENT_externref;
792 RC = &WebAssembly::EXTERNREFRegClass;
793 break;
794 case MVT::exnref:
795 Opc = WebAssembly::ARGUMENT_exnref;
796 RC = &WebAssembly::EXNREFRegClass;
797 break;
798 default:
799 return false;
800 }
801 Register ResultReg = createResultReg(RC);
802 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
803 .addImm(Val: I);
804 updateValueMap(I: &Arg, Reg: ResultReg);
805
806 ++I;
807 }
808
809 MRI.addLiveIn(Reg: WebAssembly::ARGUMENTS);
810
811 auto *MFI = MF->getInfo<WebAssemblyFunctionInfo>();
812 for (auto const &Arg : F->args()) {
813 MVT::SimpleValueType ArgTy = getLegalType(VT: getSimpleType(Ty: Arg.getType()));
814 if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
815 MFI->clearParamsAndResults();
816 return false;
817 }
818 MFI->addParam(VT: ArgTy);
819 }
820
821 if (!F->getReturnType()->isVoidTy()) {
822 MVT::SimpleValueType RetTy =
823 getLegalType(VT: getSimpleType(Ty: F->getReturnType()));
824 if (RetTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
825 MFI->clearParamsAndResults();
826 return false;
827 }
828 MFI->addResult(VT: RetTy);
829 }
830
831 return true;
832}
833
834bool WebAssemblyFastISel::selectCall(const Instruction *I) {
835 const auto *Call = cast<CallInst>(Val: I);
836
837 // TODO: Support tail calls in FastISel
838 if (Call->isMustTailCall() || Call->isInlineAsm() ||
839 Call->getFunctionType()->isVarArg())
840 return false;
841
842 Function *Func = Call->getCalledFunction();
843 if (Func && Func->isIntrinsic())
844 return false;
845
846 if (Call->getCallingConv() == CallingConv::Swift)
847 return false;
848
849 bool IsDirect = Func != nullptr;
850 if (!IsDirect && isa<ConstantExpr>(Val: Call->getCalledOperand()))
851 return false;
852
853 FunctionType *FuncTy = Call->getFunctionType();
854 unsigned Opc = IsDirect ? WebAssembly::CALL : WebAssembly::CALL_INDIRECT;
855 bool IsVoid = FuncTy->getReturnType()->isVoidTy();
856 unsigned ResultReg;
857 if (!IsVoid) {
858 if (!Subtarget->hasSIMD128() && Call->getType()->isVectorTy())
859 return false;
860
861 MVT::SimpleValueType RetTy = getSimpleType(Ty: Call->getType());
862 switch (RetTy) {
863 case MVT::i1:
864 case MVT::i8:
865 case MVT::i16:
866 case MVT::i32:
867 ResultReg = createResultReg(RC: &WebAssembly::I32RegClass);
868 break;
869 case MVT::i64:
870 ResultReg = createResultReg(RC: &WebAssembly::I64RegClass);
871 break;
872 case MVT::f32:
873 ResultReg = createResultReg(RC: &WebAssembly::F32RegClass);
874 break;
875 case MVT::f64:
876 ResultReg = createResultReg(RC: &WebAssembly::F64RegClass);
877 break;
878 case MVT::v16i8:
879 ResultReg = createResultReg(RC: &WebAssembly::V128RegClass);
880 break;
881 case MVT::v8i16:
882 ResultReg = createResultReg(RC: &WebAssembly::V128RegClass);
883 break;
884 case MVT::v4i32:
885 ResultReg = createResultReg(RC: &WebAssembly::V128RegClass);
886 break;
887 case MVT::v2i64:
888 ResultReg = createResultReg(RC: &WebAssembly::V128RegClass);
889 break;
890 case MVT::v4f32:
891 ResultReg = createResultReg(RC: &WebAssembly::V128RegClass);
892 break;
893 case MVT::v2f64:
894 ResultReg = createResultReg(RC: &WebAssembly::V128RegClass);
895 break;
896 case MVT::funcref:
897 ResultReg = createResultReg(RC: &WebAssembly::FUNCREFRegClass);
898 break;
899 case MVT::externref:
900 ResultReg = createResultReg(RC: &WebAssembly::EXTERNREFRegClass);
901 break;
902 case MVT::exnref:
903 ResultReg = createResultReg(RC: &WebAssembly::EXNREFRegClass);
904 break;
905 default:
906 return false;
907 }
908 }
909
910 SmallVector<unsigned, 8> Args;
911 for (unsigned I = 0, E = Call->arg_size(); I < E; ++I) {
912 Value *V = Call->getArgOperand(i: I);
913 MVT::SimpleValueType ArgTy = getSimpleType(Ty: V->getType());
914 if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
915 return false;
916
917 const AttributeList &Attrs = Call->getAttributes();
918 if (Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::ByVal) ||
919 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::SwiftSelf) ||
920 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::SwiftError) ||
921 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::InAlloca) ||
922 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::Nest))
923 return false;
924
925 unsigned Reg;
926
927 if (Call->paramHasAttr(ArgNo: I, Kind: Attribute::SExt))
928 Reg = getRegForSignedValue(V);
929 else if (Call->paramHasAttr(ArgNo: I, Kind: Attribute::ZExt))
930 Reg = getRegForUnsignedValue(V);
931 else
932 Reg = getRegForValue(V);
933
934 if (Reg == 0)
935 return false;
936
937 Args.push_back(Elt: Reg);
938 }
939
940 unsigned CalleeReg = 0;
941 // A call through a funcref is expressed as a call through the pointer
942 // produced by llvm.wasm.funcref.to_ptr. Recover the funcref operand, place it
943 // into __funcref_call_table, and call it.
944 //
945 // TODO: Use call_ref if wasm-gc feature is available, would lead to simpler
946 // code here.
947 const Value *FuncrefArg = nullptr;
948 if (const auto *Conv = dyn_cast<CallInst>(Val: Call->getCalledOperand()))
949 if (Conv->getIntrinsicID() == Intrinsic::wasm_funcref_to_ptr)
950 FuncrefArg = Conv->getArgOperand(i: 0);
951
952 const bool IsFuncrefCall = FuncrefArg != nullptr;
953 MCSymbolWasm *Table = nullptr;
954
955 if (!IsDirect) {
956 if (!IsFuncrefCall) {
957 // Table is ___indirect_function_table
958 Table = WebAssembly::getOrCreateFunctionTableSymbol(Ctx&: MF->getContext(),
959 Subtarget);
960 CalleeReg = getRegForValue(V: Call->getCalledOperand());
961 if (!CalleeReg)
962 return false;
963 } else {
964 // Table is __funcref_call_table
965 Table = WebAssembly::getOrCreateFuncrefCallTableSymbol(Ctx&: MF->getContext(),
966 Subtarget);
967 CalleeReg = getRegForValue(V: FuncrefArg);
968 // Put the funcref in slot 0 of __funcref_call_table
969 unsigned ZeroReg = createResultReg(RC: &WebAssembly::I32RegClass);
970 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
971 MCID: TII.get(Opcode: WebAssembly::CONST_I32), DestReg: ZeroReg)
972 .addImm(Val: 0);
973 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
974 MCID: TII.get(Opcode: WebAssembly::TABLE_SET_FUNCREF))
975 .addSym(Sym: Table)
976 .addReg(RegNo: ZeroReg)
977 .addReg(RegNo: CalleeReg);
978 // Set CalleeReg to an immediate 0
979 CalleeReg = createResultReg(RC: &WebAssembly::I32RegClass);
980 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
981 MCID: TII.get(Opcode: WebAssembly::CONST_I32), DestReg: CalleeReg)
982 .addImm(Val: 0);
983 }
984 }
985
986 auto MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc));
987
988 if (!IsVoid)
989 MIB.addReg(RegNo: ResultReg, Flags: RegState::Define);
990
991 if (IsDirect) {
992 MIB.addGlobalAddress(GV: Func);
993 } else {
994 // Placeholder for the type index.
995 MIB.addImm(Val: 0);
996 if (Subtarget->hasCallIndirectOverlong()) {
997 MIB.addSym(Sym: Table);
998 } else {
999 // Otherwise for the MVP there is at most one table whose number is 0, but
1000 // we can't write a table symbol or issue relocations. Instead we just
1001 // ensure the table is live.
1002 Table->setNoStrip();
1003 MIB.addImm(Val: 0);
1004 }
1005 }
1006
1007 for (unsigned ArgReg : Args)
1008 MIB.addReg(RegNo: ArgReg);
1009
1010 if (!IsDirect)
1011 MIB.addReg(RegNo: CalleeReg);
1012
1013 if (IsFuncrefCall) {
1014 // Clear slot 0 of the funcref call table after the call.
1015 unsigned ZeroReg = createResultReg(RC: &WebAssembly::I32RegClass);
1016 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1017 MCID: TII.get(Opcode: WebAssembly::CONST_I32), DestReg: ZeroReg)
1018 .addImm(Val: 0);
1019 unsigned NullReg = createResultReg(RC: &WebAssembly::FUNCREFRegClass);
1020 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1021 MCID: TII.get(Opcode: WebAssembly::REF_NULL_FUNCREF), DestReg: NullReg);
1022 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1023 MCID: TII.get(Opcode: WebAssembly::TABLE_SET_FUNCREF))
1024 .addSym(Sym: Table)
1025 .addReg(RegNo: ZeroReg)
1026 .addReg(RegNo: NullReg);
1027 }
1028
1029 if (!IsVoid)
1030 updateValueMap(I: Call, Reg: ResultReg);
1031
1032 diagnoseDontCall(CI: *Call);
1033 return true;
1034}
1035
1036bool WebAssemblyFastISel::selectSelect(const Instruction *I) {
1037 const auto *Select = cast<SelectInst>(Val: I);
1038
1039 bool Not;
1040 unsigned CondReg =
1041 getRegForI1Value(V: Select->getCondition(), BB: I->getParent(), Not);
1042 if (CondReg == 0)
1043 return false;
1044
1045 Register TrueReg = getRegForValue(V: Select->getTrueValue());
1046 if (TrueReg == 0)
1047 return false;
1048
1049 Register FalseReg = getRegForValue(V: Select->getFalseValue());
1050 if (FalseReg == 0)
1051 return false;
1052
1053 if (Not)
1054 std::swap(a&: TrueReg, b&: FalseReg);
1055
1056 unsigned Opc;
1057 const TargetRegisterClass *RC;
1058 switch (getSimpleType(Ty: Select->getType())) {
1059 case MVT::i1:
1060 case MVT::i8:
1061 case MVT::i16:
1062 case MVT::i32:
1063 Opc = WebAssembly::SELECT_I32;
1064 RC = &WebAssembly::I32RegClass;
1065 break;
1066 case MVT::i64:
1067 Opc = WebAssembly::SELECT_I64;
1068 RC = &WebAssembly::I64RegClass;
1069 break;
1070 case MVT::f32:
1071 Opc = WebAssembly::SELECT_F32;
1072 RC = &WebAssembly::F32RegClass;
1073 break;
1074 case MVT::f64:
1075 Opc = WebAssembly::SELECT_F64;
1076 RC = &WebAssembly::F64RegClass;
1077 break;
1078 case MVT::funcref:
1079 Opc = WebAssembly::SELECT_FUNCREF;
1080 RC = &WebAssembly::FUNCREFRegClass;
1081 break;
1082 case MVT::externref:
1083 Opc = WebAssembly::SELECT_EXTERNREF;
1084 RC = &WebAssembly::EXTERNREFRegClass;
1085 break;
1086 case MVT::exnref:
1087 Opc = WebAssembly::SELECT_EXNREF;
1088 RC = &WebAssembly::EXNREFRegClass;
1089 break;
1090 default:
1091 return false;
1092 }
1093
1094 Register ResultReg = createResultReg(RC);
1095 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
1096 .addReg(RegNo: TrueReg)
1097 .addReg(RegNo: FalseReg)
1098 .addReg(RegNo: CondReg);
1099
1100 updateValueMap(I: Select, Reg: ResultReg);
1101 return true;
1102}
1103
1104bool WebAssemblyFastISel::selectTrunc(const Instruction *I) {
1105 const auto *Trunc = cast<TruncInst>(Val: I);
1106
1107 const Value *Op = Trunc->getOperand(i_nocapture: 0);
1108 MVT::SimpleValueType From = getSimpleType(Ty: Op->getType());
1109 MVT::SimpleValueType To = getLegalType(VT: getSimpleType(Ty: Trunc->getType()));
1110 Register In = getRegForValue(V: Op);
1111 if (In == 0)
1112 return false;
1113
1114 auto Truncate = [&](Register Reg) -> unsigned {
1115 if (From == MVT::i64) {
1116 if (To == MVT::i64)
1117 return copyValue(Reg);
1118
1119 if (To == MVT::i1 || To == MVT::i8 || To == MVT::i16 || To == MVT::i32) {
1120 Register Result = createResultReg(RC: &WebAssembly::I32RegClass);
1121 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1122 MCID: TII.get(Opcode: WebAssembly::I32_WRAP_I64), DestReg: Result)
1123 .addReg(RegNo: Reg);
1124 return Result;
1125 }
1126 }
1127
1128 if (From == MVT::i32)
1129 return copyValue(Reg);
1130
1131 return 0;
1132 };
1133
1134 unsigned Reg = Truncate(In);
1135 if (Reg == 0)
1136 return false;
1137
1138 updateValueMap(I: Trunc, Reg);
1139 return true;
1140}
1141
1142bool WebAssemblyFastISel::selectZExt(const Instruction *I) {
1143 const auto *ZExt = cast<ZExtInst>(Val: I);
1144
1145 const Value *Op = ZExt->getOperand(i_nocapture: 0);
1146 MVT::SimpleValueType From = getSimpleType(Ty: Op->getType());
1147 MVT::SimpleValueType To = getLegalType(VT: getSimpleType(Ty: ZExt->getType()));
1148 Register In = getRegForValue(V: Op);
1149 if (In == 0)
1150 return false;
1151 unsigned Reg = zeroExtend(Reg: In, V: Op, From, To);
1152 if (Reg == 0)
1153 return false;
1154
1155 updateValueMap(I: ZExt, Reg);
1156 return true;
1157}
1158
1159bool WebAssemblyFastISel::selectSExt(const Instruction *I) {
1160 const auto *SExt = cast<SExtInst>(Val: I);
1161
1162 const Value *Op = SExt->getOperand(i_nocapture: 0);
1163 MVT::SimpleValueType From = getSimpleType(Ty: Op->getType());
1164 MVT::SimpleValueType To = getLegalType(VT: getSimpleType(Ty: SExt->getType()));
1165 Register In = getRegForValue(V: Op);
1166 if (In == 0)
1167 return false;
1168 unsigned Reg = signExtend(Reg: In, V: Op, From, To);
1169 if (Reg == 0)
1170 return false;
1171
1172 updateValueMap(I: SExt, Reg);
1173 return true;
1174}
1175
1176bool WebAssemblyFastISel::selectICmp(const Instruction *I) {
1177 const auto *ICmp = cast<ICmpInst>(Val: I);
1178
1179 bool I32 = getSimpleType(Ty: ICmp->getOperand(i_nocapture: 0)->getType()) != MVT::i64;
1180 unsigned Opc;
1181 bool IsSigned = false;
1182 switch (ICmp->getPredicate()) {
1183 case ICmpInst::ICMP_EQ:
1184 Opc = I32 ? WebAssembly::EQ_I32 : WebAssembly::EQ_I64;
1185 break;
1186 case ICmpInst::ICMP_NE:
1187 Opc = I32 ? WebAssembly::NE_I32 : WebAssembly::NE_I64;
1188 break;
1189 case ICmpInst::ICMP_UGT:
1190 Opc = I32 ? WebAssembly::GT_U_I32 : WebAssembly::GT_U_I64;
1191 break;
1192 case ICmpInst::ICMP_UGE:
1193 Opc = I32 ? WebAssembly::GE_U_I32 : WebAssembly::GE_U_I64;
1194 break;
1195 case ICmpInst::ICMP_ULT:
1196 Opc = I32 ? WebAssembly::LT_U_I32 : WebAssembly::LT_U_I64;
1197 break;
1198 case ICmpInst::ICMP_ULE:
1199 Opc = I32 ? WebAssembly::LE_U_I32 : WebAssembly::LE_U_I64;
1200 break;
1201 case ICmpInst::ICMP_SGT:
1202 Opc = I32 ? WebAssembly::GT_S_I32 : WebAssembly::GT_S_I64;
1203 IsSigned = true;
1204 break;
1205 case ICmpInst::ICMP_SGE:
1206 Opc = I32 ? WebAssembly::GE_S_I32 : WebAssembly::GE_S_I64;
1207 IsSigned = true;
1208 break;
1209 case ICmpInst::ICMP_SLT:
1210 Opc = I32 ? WebAssembly::LT_S_I32 : WebAssembly::LT_S_I64;
1211 IsSigned = true;
1212 break;
1213 case ICmpInst::ICMP_SLE:
1214 Opc = I32 ? WebAssembly::LE_S_I32 : WebAssembly::LE_S_I64;
1215 IsSigned = true;
1216 break;
1217 default:
1218 return false;
1219 }
1220
1221 unsigned LHS = getRegForPromotedValue(V: ICmp->getOperand(i_nocapture: 0), IsSigned);
1222 if (LHS == 0)
1223 return false;
1224
1225 unsigned RHS = getRegForPromotedValue(V: ICmp->getOperand(i_nocapture: 1), IsSigned);
1226 if (RHS == 0)
1227 return false;
1228
1229 Register ResultReg = createResultReg(RC: &WebAssembly::I32RegClass);
1230 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
1231 .addReg(RegNo: LHS)
1232 .addReg(RegNo: RHS);
1233 updateValueMap(I: ICmp, Reg: ResultReg);
1234 return true;
1235}
1236
1237bool WebAssemblyFastISel::selectFCmp(const Instruction *I) {
1238 const auto *FCmp = cast<FCmpInst>(Val: I);
1239
1240 Register LHS = getRegForValue(V: FCmp->getOperand(i_nocapture: 0));
1241 if (LHS == 0)
1242 return false;
1243
1244 Register RHS = getRegForValue(V: FCmp->getOperand(i_nocapture: 1));
1245 if (RHS == 0)
1246 return false;
1247
1248 bool F32 = getSimpleType(Ty: FCmp->getOperand(i_nocapture: 0)->getType()) != MVT::f64;
1249 unsigned Opc;
1250 bool Not = false;
1251 switch (FCmp->getPredicate()) {
1252 case FCmpInst::FCMP_OEQ:
1253 Opc = F32 ? WebAssembly::EQ_F32 : WebAssembly::EQ_F64;
1254 break;
1255 case FCmpInst::FCMP_UNE:
1256 Opc = F32 ? WebAssembly::NE_F32 : WebAssembly::NE_F64;
1257 break;
1258 case FCmpInst::FCMP_OGT:
1259 Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
1260 break;
1261 case FCmpInst::FCMP_OGE:
1262 Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
1263 break;
1264 case FCmpInst::FCMP_OLT:
1265 Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
1266 break;
1267 case FCmpInst::FCMP_OLE:
1268 Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
1269 break;
1270 case FCmpInst::FCMP_UGT:
1271 Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
1272 Not = true;
1273 break;
1274 case FCmpInst::FCMP_UGE:
1275 Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
1276 Not = true;
1277 break;
1278 case FCmpInst::FCMP_ULT:
1279 Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
1280 Not = true;
1281 break;
1282 case FCmpInst::FCMP_ULE:
1283 Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
1284 Not = true;
1285 break;
1286 default:
1287 return false;
1288 }
1289
1290 Register ResultReg = createResultReg(RC: &WebAssembly::I32RegClass);
1291 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
1292 .addReg(RegNo: LHS)
1293 .addReg(RegNo: RHS);
1294
1295 if (Not)
1296 ResultReg = notValue(Reg: ResultReg);
1297
1298 updateValueMap(I: FCmp, Reg: ResultReg);
1299 return true;
1300}
1301
1302bool WebAssemblyFastISel::selectBitCast(const Instruction *I) {
1303 // Target-independent code can handle this, except it doesn't set the dead
1304 // flag on the ARGUMENTS clobber, so we have to do that manually in order
1305 // to satisfy code that expects this of isBitcast() instructions.
1306 EVT VT = TLI.getValueType(DL, Ty: I->getOperand(i: 0)->getType());
1307 EVT RetVT = TLI.getValueType(DL, Ty: I->getType());
1308 if (!VT.isSimple() || !RetVT.isSimple())
1309 return false;
1310
1311 Register In = getRegForValue(V: I->getOperand(i: 0));
1312 if (In == 0)
1313 return false;
1314
1315 if (VT == RetVT) {
1316 // No-op bitcast.
1317 updateValueMap(I, Reg: In);
1318 return true;
1319 }
1320
1321 Register Reg =
1322 fastEmit_ISD_BITCAST_r(VT: VT.getSimpleVT(), RetVT: RetVT.getSimpleVT(), Op0: In);
1323 if (!Reg)
1324 return false;
1325 MachineBasicBlock::iterator Iter = FuncInfo.InsertPt;
1326 --Iter;
1327 assert(Iter->isBitcast());
1328 Iter->setPhysRegsDeadExcept(UsedRegs: ArrayRef<Register>(), TRI);
1329 updateValueMap(I, Reg);
1330 return true;
1331}
1332
1333static unsigned getSExtLoadOpcode(unsigned LoadSize, bool I64Result, bool A64) {
1334 if (I64Result) {
1335 switch (LoadSize) {
1336 default:
1337 return WebAssembly::INSTRUCTION_LIST_END;
1338 case 8:
1339 return A64 ? WebAssembly::LOAD8_S_I64_A64 : WebAssembly::LOAD8_S_I64_A32;
1340 case 16:
1341 return A64 ? WebAssembly::LOAD16_S_I64_A64
1342 : WebAssembly::LOAD16_S_I64_A32;
1343 case 32:
1344 return A64 ? WebAssembly::LOAD32_S_I64_A64
1345 : WebAssembly::LOAD32_S_I64_A32;
1346 }
1347 }
1348
1349 switch (LoadSize) {
1350 default:
1351 return WebAssembly::INSTRUCTION_LIST_END;
1352 case 8:
1353 return A64 ? WebAssembly::LOAD8_S_I32_A64 : WebAssembly::LOAD8_S_I32_A32;
1354 case 16:
1355 return A64 ? WebAssembly::LOAD16_S_I32_A64 : WebAssembly::LOAD16_S_I32_A32;
1356 }
1357}
1358
1359static unsigned getZExtLoadOpcode(unsigned LoadSize, bool I64Result, bool A64) {
1360 if (I64Result) {
1361 switch (LoadSize) {
1362 default:
1363 return WebAssembly::INSTRUCTION_LIST_END;
1364 case 8:
1365 return A64 ? WebAssembly::LOAD8_U_I64_A64 : WebAssembly::LOAD8_U_I64_A32;
1366 case 16:
1367 return A64 ? WebAssembly::LOAD16_U_I64_A64
1368 : WebAssembly::LOAD16_U_I64_A32;
1369 case 32:
1370 return A64 ? WebAssembly::LOAD32_U_I64_A64
1371 : WebAssembly::LOAD32_U_I64_A32;
1372 }
1373 }
1374
1375 switch (LoadSize) {
1376 default:
1377 return WebAssembly::INSTRUCTION_LIST_END;
1378 case 8:
1379 return A64 ? WebAssembly::LOAD8_U_I32_A64 : WebAssembly::LOAD8_U_I32_A32;
1380 case 16:
1381 return A64 ? WebAssembly::LOAD16_U_I32_A64 : WebAssembly::LOAD16_U_I32_A32;
1382 }
1383}
1384
1385static bool isFoldableSExtOpcode(unsigned Opc) {
1386 switch (Opc) {
1387 default:
1388 return false;
1389 case WebAssembly::I32_EXTEND8_S_I32:
1390 case WebAssembly::I32_EXTEND16_S_I32:
1391 case WebAssembly::I64_EXTEND8_S_I64:
1392 case WebAssembly::I64_EXTEND16_S_I64:
1393 case WebAssembly::I64_EXTEND32_S_I64:
1394 case WebAssembly::I64_EXTEND_S_I32:
1395 return true;
1396 }
1397}
1398
1399static bool isI64SExtResult(unsigned Opc) {
1400 switch (Opc) {
1401 default:
1402 llvm_unreachable("unexpected opcode");
1403 case WebAssembly::I32_EXTEND8_S_I32:
1404 case WebAssembly::I32_EXTEND16_S_I32:
1405 return false;
1406 case WebAssembly::I64_EXTEND8_S_I64:
1407 case WebAssembly::I64_EXTEND16_S_I64:
1408 case WebAssembly::I64_EXTEND32_S_I64:
1409 case WebAssembly::I64_EXTEND_S_I32:
1410 return true;
1411 }
1412}
1413
1414static unsigned getFoldedLoadOpcode(MachineInstr *MI, MachineRegisterInfo &MRI,
1415 const LoadInst *LI, bool A64) {
1416 unsigned Opc = MI->getOpcode();
1417
1418 if (isFoldableSExtOpcode(Opc)) {
1419 unsigned LoadSize = LI->getType()->getPrimitiveSizeInBits();
1420 return getSExtLoadOpcode(LoadSize, I64Result: isI64SExtResult(Opc), A64);
1421 }
1422
1423 return WebAssembly::INSTRUCTION_LIST_END;
1424}
1425
1426static unsigned getFoldedI64LoadOpcode(Register DestReg, const LoadInst *LI,
1427 MachineRegisterInfo &MRI, bool A64,
1428 MachineInstr *&OuterUserMI,
1429 unsigned NarrowOpc) {
1430 if (!MRI.hasOneNonDBGUse(RegNo: DestReg))
1431 return NarrowOpc;
1432
1433 MachineInstr *UserMI = &*MRI.use_instr_nodbg_begin(RegNo: DestReg);
1434 unsigned LoadSize = LI->getType()->getPrimitiveSizeInBits();
1435 switch (UserMI->getOpcode()) {
1436 case WebAssembly::I64_EXTEND_U_I32:
1437 OuterUserMI = UserMI;
1438 return getZExtLoadOpcode(LoadSize, /*I64Result=*/true, A64);
1439 case WebAssembly::I64_EXTEND_S_I32:
1440 OuterUserMI = UserMI;
1441 return getSExtLoadOpcode(LoadSize, /*I64Result=*/true, A64);
1442 default:
1443 return NarrowOpc;
1444 }
1445}
1446
1447/// Matches a sign-extension pattern (shl + shr_s) to fold it into a signed
1448/// load. FastISel assumes that 'sext' from i8 or i16 will first be lowered to a
1449/// 32-bit zero-extending load (i32.load8_u / i32.load16_u) followed by 32-bit
1450/// shifts, even when extending to i64. Therefore, this function only matches
1451/// 32-bit shifts (SHL_I32 / SHR_S_I32) and specifically checks if both shift
1452/// amounts are identical, compile-time constants that match the exact extension
1453/// size (32 - LoadBitWidth).
1454static unsigned matchFoldableShift(MachineInstr *MI, const LoadInst *LI,
1455 MachineRegisterInfo &MRI, bool A64,
1456 MachineInstr *&UserMI,
1457 MachineInstr *&OuterUserMI) {
1458 unsigned Opc = MI->getOpcode();
1459 unsigned NewOpc = WebAssembly::INSTRUCTION_LIST_END;
1460 if (Opc != WebAssembly::SHL_I32)
1461 return NewOpc;
1462
1463 Register DestReg = MI->getOperand(i: 0).getReg();
1464 if (!MRI.hasOneNonDBGUse(RegNo: DestReg))
1465 return NewOpc;
1466
1467 UserMI = &*MRI.use_instr_nodbg_begin(RegNo: DestReg);
1468 unsigned UserOpc = UserMI->getOpcode();
1469 if (UserOpc != WebAssembly::SHR_S_I32)
1470 return NewOpc;
1471
1472 Type *LoadTy = LI->getType();
1473 if (!LoadTy->isIntegerTy(BitWidth: 8) && !LoadTy->isIntegerTy(BitWidth: 16))
1474 return NewOpc;
1475
1476 int64_t ExpectedShiftAmt = 32 - LoadTy->getIntegerBitWidth();
1477 Register ShlAmtReg = MI->getOperand(i: 2).getReg();
1478 Register ShrAmtReg = UserMI->getOperand(i: 2).getReg();
1479 MachineInstr *ShlAmtDef = MRI.getUniqueVRegDef(Reg: ShlAmtReg);
1480 MachineInstr *ShrAmtDef = MRI.getUniqueVRegDef(Reg: ShrAmtReg);
1481 auto IsExpectedConst = [ExpectedShiftAmt](MachineInstr *MI) {
1482 return MI && MI->getOpcode() == WebAssembly::CONST_I32 &&
1483 MI->getOperand(i: 1).getImm() == ExpectedShiftAmt;
1484 };
1485 if (!IsExpectedConst(ShlAmtDef) || !IsExpectedConst(ShrAmtDef))
1486 return NewOpc;
1487
1488 unsigned LoadSize = LoadTy->getIntegerBitWidth();
1489 unsigned NarrowOpc = getSExtLoadOpcode(LoadSize, /*I64Result=*/false, A64);
1490 if (NarrowOpc == WebAssembly::INSTRUCTION_LIST_END)
1491 return WebAssembly::INSTRUCTION_LIST_END;
1492
1493 return getFoldedI64LoadOpcode(DestReg: UserMI->getOperand(i: 0).getReg(), LI, MRI, A64,
1494 OuterUserMI, NarrowOpc);
1495}
1496
1497static unsigned matchFoldableSExtFromPromotedI32(MachineInstr *MI,
1498 const LoadInst *LI,
1499 MachineRegisterInfo &MRI,
1500 bool A64,
1501 MachineInstr *&UserMI) {
1502 if (MI->getOpcode() != WebAssembly::I64_EXTEND_U_I32)
1503 return WebAssembly::INSTRUCTION_LIST_END;
1504
1505 unsigned LoadSize = LI->getType()->getPrimitiveSizeInBits();
1506 Register DestReg = MI->getOperand(i: 0).getReg();
1507 if (!MRI.hasOneNonDBGUse(RegNo: DestReg))
1508 return WebAssembly::INSTRUCTION_LIST_END;
1509
1510 UserMI = &*MRI.use_instr_nodbg_begin(RegNo: DestReg);
1511 switch (UserMI->getOpcode()) {
1512 default:
1513 return WebAssembly::INSTRUCTION_LIST_END;
1514 case WebAssembly::I64_EXTEND8_S_I64:
1515 if (LoadSize != 8)
1516 return WebAssembly::INSTRUCTION_LIST_END;
1517 return getSExtLoadOpcode(LoadSize, I64Result: true, A64);
1518 case WebAssembly::I64_EXTEND16_S_I64:
1519 if (LoadSize != 16)
1520 return WebAssembly::INSTRUCTION_LIST_END;
1521 return getSExtLoadOpcode(LoadSize, I64Result: true, A64);
1522 }
1523}
1524
1525static unsigned matchFoldableCopyToI64Ext(MachineInstr *MI, const LoadInst *LI,
1526 MachineRegisterInfo &MRI, bool A64,
1527 MachineInstr *&OuterUserMI) {
1528 if (MI->getOpcode() != WebAssembly::COPY)
1529 return WebAssembly::INSTRUCTION_LIST_END;
1530
1531 unsigned LoadSize = LI->getType()->getPrimitiveSizeInBits();
1532 if (LoadSize != 32)
1533 return WebAssembly::INSTRUCTION_LIST_END;
1534
1535 Register CopyDst = MI->getOperand(i: 0).getReg();
1536 if (!MRI.hasOneNonDBGUse(RegNo: CopyDst))
1537 return WebAssembly::INSTRUCTION_LIST_END;
1538
1539 OuterUserMI = &*MRI.use_instr_nodbg_begin(RegNo: CopyDst);
1540 switch (OuterUserMI->getOpcode()) {
1541 default:
1542 return WebAssembly::INSTRUCTION_LIST_END;
1543 case WebAssembly::I64_EXTEND_U_I32:
1544 return getZExtLoadOpcode(LoadSize, I64Result: true, A64);
1545 case WebAssembly::I64_EXTEND_S_I32:
1546 return getSExtLoadOpcode(LoadSize, I64Result: true, A64);
1547 }
1548}
1549
1550static unsigned matchFoldableAnd(MachineInstr *MI, const LoadInst *LI,
1551 MachineRegisterInfo &MRI, bool A64,
1552 MachineInstr *&OuterUserMI) {
1553 if (MI->getOpcode() != WebAssembly::AND_I32 &&
1554 MI->getOpcode() != WebAssembly::AND_I64)
1555 return WebAssembly::INSTRUCTION_LIST_END;
1556
1557 uint64_t Mask = 0;
1558 bool IsConstant = false;
1559 for (unsigned I = 1; I <= 2; ++I) {
1560 Register Reg = MI->getOperand(i: I).getReg();
1561 MachineInstr *DefMI = MRI.getUniqueVRegDef(Reg);
1562 if (DefMI && (DefMI->getOpcode() == WebAssembly::CONST_I32 ||
1563 DefMI->getOpcode() == WebAssembly::CONST_I64)) {
1564 Mask = DefMI->getOperand(i: 1).getImm();
1565 IsConstant = true;
1566 break;
1567 }
1568 }
1569
1570 if (!IsConstant)
1571 return WebAssembly::INSTRUCTION_LIST_END;
1572
1573 unsigned LoadSize = LI->getType()->getPrimitiveSizeInBits();
1574 if (Mask != llvm::maskTrailingOnes<uint64_t>(N: LoadSize))
1575 return WebAssembly::INSTRUCTION_LIST_END;
1576
1577 if (MI->getOpcode() == WebAssembly::AND_I64)
1578 return getZExtLoadOpcode(LoadSize, /*I64Result=*/true, A64);
1579
1580 unsigned NarrowOpc = getZExtLoadOpcode(LoadSize, /*I64Result=*/false, A64);
1581 if (NarrowOpc == WebAssembly::INSTRUCTION_LIST_END)
1582 return WebAssembly::INSTRUCTION_LIST_END;
1583
1584 return getFoldedI64LoadOpcode(DestReg: MI->getOperand(i: 0).getReg(), LI, MRI, A64,
1585 OuterUserMI, NarrowOpc);
1586}
1587
1588bool WebAssemblyFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
1589 const LoadInst *LI) {
1590 bool A64 = Subtarget->hasAddr64();
1591 MachineRegisterInfo &MRI = FuncInfo.MF->getRegInfo();
1592 Register ResultReg;
1593 MachineInstr *UserMI = nullptr;
1594 MachineInstr *OuterUserMI = nullptr;
1595 unsigned NewOpc = WebAssembly::INSTRUCTION_LIST_END;
1596 if ((NewOpc = matchFoldableSExtFromPromotedI32(MI, LI, MRI, A64, UserMI)) !=
1597 WebAssembly::INSTRUCTION_LIST_END) {
1598 ResultReg = UserMI->getOperand(i: 0).getReg();
1599 } else if ((NewOpc =
1600 matchFoldableCopyToI64Ext(MI, LI, MRI, A64, OuterUserMI)) !=
1601 WebAssembly::INSTRUCTION_LIST_END) {
1602 ResultReg = OuterUserMI->getOperand(i: 0).getReg();
1603 } else if ((NewOpc = matchFoldableAnd(MI, LI, MRI, A64, OuterUserMI)) !=
1604 WebAssembly::INSTRUCTION_LIST_END) {
1605 ResultReg = OuterUserMI ? OuterUserMI->getOperand(i: 0).getReg()
1606 : MI->getOperand(i: 0).getReg();
1607 } else if ((NewOpc = getFoldedLoadOpcode(MI, MRI, LI, A64)) !=
1608 WebAssembly::INSTRUCTION_LIST_END) {
1609 ResultReg = MI->getOperand(i: 0).getReg();
1610 } else if ((NewOpc =
1611 matchFoldableShift(MI, LI, MRI, A64, UserMI, OuterUserMI)) !=
1612 WebAssembly::INSTRUCTION_LIST_END) {
1613 ResultReg = OuterUserMI ? OuterUserMI->getOperand(i: 0).getReg()
1614 : UserMI->getOperand(i: 0).getReg();
1615 } else {
1616 return false;
1617 }
1618
1619 if (!emitLoad(ResultReg, Opc: NewOpc, Load: LI))
1620 return false;
1621
1622 if (OuterUserMI) {
1623 MachineBasicBlock::iterator OuterIter(OuterUserMI);
1624 removeDeadCode(I: OuterIter, E: std::next(x: OuterIter));
1625 }
1626
1627 if (UserMI) {
1628 MachineBasicBlock::iterator UserIter(UserMI);
1629 removeDeadCode(I: UserIter, E: std::next(x: UserIter));
1630 }
1631
1632 MachineBasicBlock::iterator Iter(MI);
1633 removeDeadCode(I: Iter, E: std::next(x: Iter));
1634 return true;
1635}
1636
1637bool WebAssemblyFastISel::selectLoad(const Instruction *I) {
1638 const auto *Load = cast<LoadInst>(Val: I);
1639 if (Load->isAtomic())
1640 return false;
1641 if (!WebAssembly::isDefaultAddressSpace(AS: Load->getPointerAddressSpace()))
1642 return false;
1643 if (!Subtarget->hasSIMD128() && Load->getType()->isVectorTy())
1644 return false;
1645
1646 // TODO: Fold a following sign-/zero-extend into the load instruction.
1647
1648 unsigned Opc;
1649 const TargetRegisterClass *RC;
1650 bool A64 = Subtarget->hasAddr64();
1651 switch (getSimpleType(Ty: Load->getType())) {
1652 case MVT::i1:
1653 case MVT::i8:
1654 Opc = A64 ? WebAssembly::LOAD8_U_I32_A64 : WebAssembly::LOAD8_U_I32_A32;
1655 RC = &WebAssembly::I32RegClass;
1656 break;
1657 case MVT::i16:
1658 Opc = A64 ? WebAssembly::LOAD16_U_I32_A64 : WebAssembly::LOAD16_U_I32_A32;
1659 RC = &WebAssembly::I32RegClass;
1660 break;
1661 case MVT::i32:
1662 Opc = A64 ? WebAssembly::LOAD_I32_A64 : WebAssembly::LOAD_I32_A32;
1663 RC = &WebAssembly::I32RegClass;
1664 break;
1665 case MVT::i64:
1666 Opc = A64 ? WebAssembly::LOAD_I64_A64 : WebAssembly::LOAD_I64_A32;
1667 RC = &WebAssembly::I64RegClass;
1668 break;
1669 case MVT::f32:
1670 Opc = A64 ? WebAssembly::LOAD_F32_A64 : WebAssembly::LOAD_F32_A32;
1671 RC = &WebAssembly::F32RegClass;
1672 break;
1673 case MVT::f64:
1674 Opc = A64 ? WebAssembly::LOAD_F64_A64 : WebAssembly::LOAD_F64_A32;
1675 RC = &WebAssembly::F64RegClass;
1676 break;
1677 default:
1678 return false;
1679 }
1680
1681 Register ResultReg = createResultReg(RC);
1682 if (!emitLoad(ResultReg, Opc, Load))
1683 return false;
1684
1685 updateValueMap(I: Load, Reg: ResultReg);
1686 return true;
1687}
1688
1689bool WebAssemblyFastISel::selectStore(const Instruction *I) {
1690 const auto *Store = cast<StoreInst>(Val: I);
1691 if (Store->isAtomic())
1692 return false;
1693 if (!WebAssembly::isDefaultAddressSpace(AS: Store->getPointerAddressSpace()))
1694 return false;
1695 if (!Subtarget->hasSIMD128() &&
1696 Store->getValueOperand()->getType()->isVectorTy())
1697 return false;
1698
1699 Address Addr;
1700 if (!computeAddress(Obj: Store->getPointerOperand(), Addr))
1701 return false;
1702
1703 unsigned Opc;
1704 bool VTIsi1 = false;
1705 bool A64 = Subtarget->hasAddr64();
1706 switch (getSimpleType(Ty: Store->getValueOperand()->getType())) {
1707 case MVT::i1:
1708 VTIsi1 = true;
1709 [[fallthrough]];
1710 case MVT::i8:
1711 Opc = A64 ? WebAssembly::STORE8_I32_A64 : WebAssembly::STORE8_I32_A32;
1712 break;
1713 case MVT::i16:
1714 Opc = A64 ? WebAssembly::STORE16_I32_A64 : WebAssembly::STORE16_I32_A32;
1715 break;
1716 case MVT::i32:
1717 Opc = A64 ? WebAssembly::STORE_I32_A64 : WebAssembly::STORE_I32_A32;
1718 break;
1719 case MVT::i64:
1720 Opc = A64 ? WebAssembly::STORE_I64_A64 : WebAssembly::STORE_I64_A32;
1721 break;
1722 case MVT::f32:
1723 Opc = A64 ? WebAssembly::STORE_F32_A64 : WebAssembly::STORE_F32_A32;
1724 break;
1725 case MVT::f64:
1726 Opc = A64 ? WebAssembly::STORE_F64_A64 : WebAssembly::STORE_F64_A32;
1727 break;
1728 default:
1729 return false;
1730 }
1731
1732 materializeLoadStoreOperands(Addr);
1733
1734 Register ValueReg = getRegForValue(V: Store->getValueOperand());
1735 if (ValueReg == 0)
1736 return false;
1737 if (VTIsi1)
1738 ValueReg = maskI1Value(Reg: ValueReg, V: Store->getValueOperand());
1739
1740 auto MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc));
1741
1742 addLoadStoreOperands(Addr, MIB, MMO: createMachineMemOperandFor(I: Store));
1743
1744 MIB.addReg(RegNo: ValueReg);
1745 return true;
1746}
1747
1748bool WebAssemblyFastISel::selectCondBr(const Instruction *I) {
1749 const auto *Br = cast<CondBrInst>(Val: I);
1750
1751 MachineBasicBlock *TBB = FuncInfo.getMBB(BB: Br->getSuccessor(i: 0));
1752 MachineBasicBlock *FBB = FuncInfo.getMBB(BB: Br->getSuccessor(i: 1));
1753
1754 bool Not;
1755 unsigned CondReg = getRegForI1Value(V: Br->getCondition(), BB: Br->getParent(), Not);
1756 if (CondReg == 0)
1757 return false;
1758
1759 unsigned Opc = WebAssembly::BR_IF;
1760 if (Not)
1761 Opc = WebAssembly::BR_UNLESS;
1762
1763 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc))
1764 .addMBB(MBB: TBB)
1765 .addReg(RegNo: CondReg);
1766
1767 finishCondBranch(BranchBB: Br->getParent(), TrueMBB: TBB, FalseMBB: FBB);
1768 return true;
1769}
1770
1771bool WebAssemblyFastISel::selectRet(const Instruction *I) {
1772 if (!FuncInfo.CanLowerReturn)
1773 return false;
1774
1775 const auto *Ret = cast<ReturnInst>(Val: I);
1776
1777 if (Ret->getNumOperands() == 0) {
1778 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1779 MCID: TII.get(Opcode: WebAssembly::RETURN));
1780 return true;
1781 }
1782
1783 // TODO: support multiple return in FastISel
1784 if (Ret->getNumOperands() > 1)
1785 return false;
1786
1787 Value *RV = Ret->getOperand(i_nocapture: 0);
1788 if (!Subtarget->hasSIMD128() && RV->getType()->isVectorTy())
1789 return false;
1790
1791 switch (getSimpleType(Ty: RV->getType())) {
1792 case MVT::i1:
1793 case MVT::i8:
1794 case MVT::i16:
1795 case MVT::i32:
1796 case MVT::i64:
1797 case MVT::f32:
1798 case MVT::f64:
1799 case MVT::v16i8:
1800 case MVT::v8i16:
1801 case MVT::v4i32:
1802 case MVT::v2i64:
1803 case MVT::v4f32:
1804 case MVT::v2f64:
1805 case MVT::funcref:
1806 case MVT::externref:
1807 case MVT::exnref:
1808 break;
1809 default:
1810 return false;
1811 }
1812
1813 unsigned Reg;
1814 if (FuncInfo.Fn->getAttributes().hasRetAttr(Kind: Attribute::SExt))
1815 Reg = getRegForSignedValue(V: RV);
1816 else if (FuncInfo.Fn->getAttributes().hasRetAttr(Kind: Attribute::ZExt))
1817 Reg = getRegForUnsignedValue(V: RV);
1818 else
1819 Reg = getRegForValue(V: RV);
1820
1821 if (Reg == 0)
1822 return false;
1823
1824 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: WebAssembly::RETURN))
1825 .addReg(RegNo: Reg);
1826 return true;
1827}
1828
1829bool WebAssemblyFastISel::selectUnreachable(const Instruction *I) {
1830 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1831 MCID: TII.get(Opcode: WebAssembly::UNREACHABLE));
1832 return true;
1833}
1834
1835bool WebAssemblyFastISel::fastSelectInstruction(const Instruction *I) {
1836 switch (I->getOpcode()) {
1837 case Instruction::Call:
1838 if (selectCall(I))
1839 return true;
1840 break;
1841 case Instruction::Select:
1842 return selectSelect(I);
1843 case Instruction::Trunc:
1844 return selectTrunc(I);
1845 case Instruction::ZExt:
1846 return selectZExt(I);
1847 case Instruction::SExt:
1848 return selectSExt(I);
1849 case Instruction::ICmp:
1850 return selectICmp(I);
1851 case Instruction::FCmp:
1852 return selectFCmp(I);
1853 case Instruction::BitCast:
1854 return selectBitCast(I);
1855 case Instruction::Load:
1856 return selectLoad(I);
1857 case Instruction::Store:
1858 return selectStore(I);
1859 case Instruction::CondBr:
1860 return selectCondBr(I);
1861 case Instruction::Ret:
1862 return selectRet(I);
1863 case Instruction::Unreachable:
1864 return selectUnreachable(I);
1865 default:
1866 break;
1867 }
1868
1869 // Fall back to target-independent instruction selection.
1870 return selectOperator(I, Opcode: I->getOpcode());
1871}
1872
1873FastISel *
1874WebAssembly::createFastISel(FunctionLoweringInfo &FuncInfo,
1875 const TargetLibraryInfo *LibInfo,
1876 const LibcallLoweringInfo *LibcallLowering) {
1877 return new WebAssemblyFastISel(FuncInfo, LibInfo, LibcallLowering);
1878}
1879