1//===-- WebAssemblyFastISel.cpp - WebAssembly FastISel implementation -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file defines the WebAssembly-specific support for the FastISel
11/// class. Some of the target-specific code is generated by tablegen in the file
12/// WebAssemblyGenFastISel.inc, which is #included here.
13///
14/// TODO: kill flags
15///
16//===----------------------------------------------------------------------===//
17
18#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
19#include "Utils/WasmAddressSpaces.h"
20#include "Utils/WebAssemblyTypeUtilities.h"
21#include "WebAssemblyMachineFunctionInfo.h"
22#include "WebAssemblySubtarget.h"
23#include "WebAssemblyUtilities.h"
24#include "llvm/Analysis/BranchProbabilityInfo.h"
25#include "llvm/CodeGen/FastISel.h"
26#include "llvm/CodeGen/FunctionLoweringInfo.h"
27#include "llvm/CodeGen/MachineConstantPool.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineModuleInfo.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/IR/DataLayout.h"
33#include "llvm/IR/DerivedTypes.h"
34#include "llvm/IR/Function.h"
35#include "llvm/IR/GetElementPtrTypeIterator.h"
36#include "llvm/IR/GlobalVariable.h"
37#include "llvm/IR/Instructions.h"
38#include "llvm/IR/IntrinsicsWebAssembly.h"
39#include "llvm/IR/Operator.h"
40
41using namespace llvm;
42
43#define DEBUG_TYPE "wasm-fastisel"
44
45namespace {
46
47class WebAssemblyFastISel final : public FastISel {
48 // All possible address modes.
49 class Address {
50 public:
51 enum BaseKind { RegBase, FrameIndexBase };
52
53 private:
54 BaseKind Kind = RegBase;
55 union {
56 unsigned Reg;
57 int FI;
58 } Base;
59
60 // Whether the base has been determined yet
61 bool IsBaseSet = false;
62
63 int64_t Offset = 0;
64
65 const GlobalValue *GV = nullptr;
66
67 public:
68 // Innocuous defaults for our address.
69 Address() { Base.Reg = 0; }
70 void setKind(BaseKind K) {
71 assert(!isSet() && "Can't change kind with non-zero base");
72 Kind = K;
73 }
74 BaseKind getKind() const { return Kind; }
75 bool isRegBase() const { return Kind == RegBase; }
76 bool isFIBase() const { return Kind == FrameIndexBase; }
77 void setReg(unsigned Reg) {
78 assert(isRegBase() && "Invalid base register access!");
79 assert(!IsBaseSet && "Base cannot be reset");
80 Base.Reg = Reg;
81 IsBaseSet = true;
82 }
83 unsigned getReg() const {
84 assert(isRegBase() && "Invalid base register access!");
85 return Base.Reg;
86 }
87 void setFI(unsigned FI) {
88 assert(isFIBase() && "Invalid base frame index access!");
89 assert(!IsBaseSet && "Base cannot be reset");
90 Base.FI = FI;
91 IsBaseSet = true;
92 }
93 unsigned getFI() const {
94 assert(isFIBase() && "Invalid base frame index access!");
95 return Base.FI;
96 }
97
98 void setOffset(int64_t NewOffset) {
99 assert(NewOffset >= 0 && "Offsets must be non-negative");
100 Offset = NewOffset;
101 }
102 int64_t getOffset() const { return Offset; }
103 void setGlobalValue(const GlobalValue *G) { GV = G; }
104 const GlobalValue *getGlobalValue() const { return GV; }
105 bool isSet() const { return IsBaseSet; }
106 };
107
108 /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
109 /// right decision when generating code for different targets.
110 const WebAssemblySubtarget *Subtarget;
111 LLVMContext *Context;
112
113private:
114 // Utility helper routines
115 MVT::SimpleValueType getSimpleType(Type *Ty) {
116 EVT VT = TLI.getValueType(DL, Ty, /*AllowUnknown=*/true);
117 return VT.isSimple() ? VT.getSimpleVT().SimpleTy
118 : MVT::INVALID_SIMPLE_VALUE_TYPE;
119 }
120 MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) {
121 switch (VT) {
122 case MVT::i1:
123 case MVT::i8:
124 case MVT::i16:
125 return MVT::i32;
126 case MVT::i32:
127 case MVT::i64:
128 case MVT::f32:
129 case MVT::f64:
130 return VT;
131 case MVT::funcref:
132 case MVT::externref:
133 if (Subtarget->hasReferenceTypes())
134 return VT;
135 break;
136 case MVT::exnref:
137 if (Subtarget->hasReferenceTypes() && Subtarget->hasExceptionHandling())
138 return VT;
139 break;
140 case MVT::f16:
141 return MVT::f32;
142 case MVT::v16i8:
143 case MVT::v8i16:
144 case MVT::v4i32:
145 case MVT::v4f32:
146 case MVT::v2i64:
147 case MVT::v2f64:
148 if (Subtarget->hasSIMD128())
149 return VT;
150 break;
151 default:
152 break;
153 }
154 return MVT::INVALID_SIMPLE_VALUE_TYPE;
155 }
156 bool computeAddress(const Value *Obj, Address &Addr);
157 void materializeLoadStoreOperands(Address &Addr);
158 void addLoadStoreOperands(const Address &Addr, const MachineInstrBuilder &MIB,
159 MachineMemOperand *MMO);
160 bool emitLoad(Register ResultReg, unsigned Opc, const LoadInst *LoadInst);
161 unsigned maskI1Value(unsigned Reg, const Value *V);
162 unsigned getRegForI1Value(const Value *V, const BasicBlock *BB, bool &Not);
163 unsigned zeroExtendToI32(unsigned Reg, const Value *V,
164 MVT::SimpleValueType From);
165 unsigned signExtendToI32(unsigned Reg, const Value *V,
166 MVT::SimpleValueType From);
167 unsigned zeroExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
168 MVT::SimpleValueType To);
169 unsigned signExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
170 MVT::SimpleValueType To);
171 unsigned getRegForUnsignedValue(const Value *V);
172 unsigned getRegForSignedValue(const Value *V);
173 unsigned getRegForPromotedValue(const Value *V, bool IsSigned);
174 unsigned notValue(unsigned Reg);
175 unsigned copyValue(unsigned Reg);
176
177 // Backend specific FastISel code.
178 Register fastMaterializeAlloca(const AllocaInst *AI) override;
179 Register fastMaterializeConstant(const Constant *C) override;
180 bool fastLowerArguments() override;
181
182 // Selection routines.
183 bool selectCall(const Instruction *I);
184 bool selectSelect(const Instruction *I);
185 bool selectTrunc(const Instruction *I);
186 bool selectZExt(const Instruction *I);
187 bool selectSExt(const Instruction *I);
188 bool selectICmp(const Instruction *I);
189 bool selectFCmp(const Instruction *I);
190 bool selectBitCast(const Instruction *I);
191 bool selectLoad(const Instruction *I);
192 bool selectStore(const Instruction *I);
193 bool selectCondBr(const Instruction *I);
194 bool selectRet(const Instruction *I);
195 bool selectUnreachable(const Instruction *I);
196
197public:
198 // Backend specific FastISel code.
199 WebAssemblyFastISel(FunctionLoweringInfo &FuncInfo,
200 const TargetLibraryInfo *LibInfo,
201 const LibcallLoweringInfo *LibcallLowering)
202 : FastISel(FuncInfo, LibInfo, LibcallLowering,
203 /*SkipTargetIndependentISel=*/true) {
204 Subtarget = &FuncInfo.MF->getSubtarget<WebAssemblySubtarget>();
205 Context = &FuncInfo.Fn->getContext();
206 }
207
208 bool fastSelectInstruction(const Instruction *I) override;
209 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
210 const LoadInst *LI) override;
211
212#include "WebAssemblyGenFastISel.inc"
213};
214
215} // end anonymous namespace
216
217bool WebAssemblyFastISel::computeAddress(const Value *Obj, Address &Addr) {
218 const User *U = nullptr;
219 unsigned Opcode = Instruction::UserOp1;
220 if (const auto *I = dyn_cast<Instruction>(Val: Obj)) {
221 // Don't walk into other basic blocks unless the object is an alloca from
222 // another block, otherwise it may not have a virtual register assigned.
223 if (FuncInfo.StaticAllocaMap.count(Val: static_cast<const AllocaInst *>(Obj)) ||
224 FuncInfo.getMBB(BB: I->getParent()) == FuncInfo.MBB) {
225 Opcode = I->getOpcode();
226 U = I;
227 }
228 } else if (const auto *C = dyn_cast<ConstantExpr>(Val: Obj)) {
229 Opcode = C->getOpcode();
230 U = C;
231 }
232
233 if (auto *Ty = dyn_cast<PointerType>(Val: Obj->getType()))
234 if (Ty->getAddressSpace() > 255)
235 // Fast instruction selection doesn't support the special
236 // address spaces.
237 return false;
238
239 if (const auto *GV = dyn_cast<GlobalValue>(Val: Obj)) {
240 if (TLI.isPositionIndependent())
241 return false;
242 if (Addr.getGlobalValue())
243 return false;
244 if (GV->isThreadLocal())
245 return false;
246 Addr.setGlobalValue(GV);
247 return true;
248 }
249
250 switch (Opcode) {
251 default:
252 break;
253 case Instruction::BitCast: {
254 // Look through bitcasts.
255 return computeAddress(Obj: U->getOperand(i: 0), Addr);
256 }
257 case Instruction::IntToPtr: {
258 // Look past no-op inttoptrs.
259 if (TLI.getValueType(DL, Ty: U->getOperand(i: 0)->getType()) ==
260 TLI.getPointerTy(DL))
261 return computeAddress(Obj: U->getOperand(i: 0), Addr);
262 break;
263 }
264 case Instruction::PtrToInt: {
265 // Look past no-op ptrtoints.
266 if (TLI.getValueType(DL, Ty: U->getType()) == TLI.getPointerTy(DL))
267 return computeAddress(Obj: U->getOperand(i: 0), Addr);
268 break;
269 }
270 case Instruction::GetElementPtr: {
271 Address SavedAddr = Addr;
272 uint64_t TmpOffset = Addr.getOffset();
273 // Non-inbounds geps can wrap; wasm's offsets can't.
274 if (!cast<GEPOperator>(Val: U)->isInBounds())
275 goto unsupported_gep;
276 // Iterate through the GEP folding the constants into offsets where
277 // we can.
278 for (gep_type_iterator GTI = gep_type_begin(GEP: U), E = gep_type_end(GEP: U);
279 GTI != E; ++GTI) {
280 const Value *Op = GTI.getOperand();
281 if (StructType *STy = GTI.getStructTypeOrNull()) {
282 const StructLayout *SL = DL.getStructLayout(Ty: STy);
283 unsigned Idx = cast<ConstantInt>(Val: Op)->getZExtValue();
284 TmpOffset += SL->getElementOffset(Idx);
285 } else {
286 uint64_t S = GTI.getSequentialElementStride(DL);
287 for (;;) {
288 if (const auto *CI = dyn_cast<ConstantInt>(Val: Op)) {
289 // Constant-offset addressing.
290 TmpOffset += CI->getSExtValue() * S;
291 break;
292 }
293 if (S == 1 && Addr.isRegBase() && Addr.getReg() == 0) {
294 // An unscaled add of a register. Set it as the new base.
295 Register Reg = getRegForValue(V: Op);
296 if (Reg == 0)
297 return false;
298 Addr.setReg(Reg);
299 break;
300 }
301 if (canFoldAddIntoGEP(GEP: U, Add: Op)) {
302 // A compatible add with a constant operand. Fold the constant.
303 auto *CI = cast<ConstantInt>(Val: cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 1));
304 TmpOffset += CI->getSExtValue() * S;
305 // Iterate on the other operand.
306 Op = cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 0);
307 continue;
308 }
309 // Unsupported
310 goto unsupported_gep;
311 }
312 }
313 }
314 // Don't fold in negative offsets.
315 if (int64_t(TmpOffset) >= 0) {
316 // Try to grab the base operand now.
317 Addr.setOffset(TmpOffset);
318 if (computeAddress(Obj: U->getOperand(i: 0), Addr))
319 return true;
320 }
321 // We failed, restore everything and try the other options.
322 Addr = SavedAddr;
323 unsupported_gep:
324 break;
325 }
326 case Instruction::Alloca: {
327 const auto *AI = cast<AllocaInst>(Val: Obj);
328 auto SI = FuncInfo.StaticAllocaMap.find(Val: AI);
329 if (SI != FuncInfo.StaticAllocaMap.end()) {
330 if (Addr.isSet()) {
331 return false;
332 }
333 Addr.setKind(Address::FrameIndexBase);
334 Addr.setFI(SI->second);
335 return true;
336 }
337 break;
338 }
339 case Instruction::Add: {
340 // We should not fold operands into an offset when 'nuw' (no unsigned wrap)
341 // is not present, because the address calculation does not wrap.
342 if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(Val: U))
343 if (!OFBinOp->hasNoUnsignedWrap())
344 break;
345
346 // Adds of constants are common and easy enough.
347 const Value *LHS = U->getOperand(i: 0);
348 const Value *RHS = U->getOperand(i: 1);
349
350 if (isa<ConstantInt>(Val: LHS))
351 std::swap(a&: LHS, b&: RHS);
352
353 if (const auto *CI = dyn_cast<ConstantInt>(Val: RHS)) {
354 uint64_t TmpOffset = Addr.getOffset() + CI->getSExtValue();
355 if (int64_t(TmpOffset) >= 0) {
356 Addr.setOffset(TmpOffset);
357 return computeAddress(Obj: LHS, Addr);
358 }
359 }
360
361 Address Backup = Addr;
362 if (computeAddress(Obj: LHS, Addr) && computeAddress(Obj: RHS, Addr))
363 return true;
364 Addr = Backup;
365
366 break;
367 }
368 case Instruction::Sub: {
369 // We should not fold operands into an offset when 'nuw' (no unsigned wrap)
370 // is not present, because the address calculation does not wrap.
371 if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(Val: U))
372 if (!OFBinOp->hasNoUnsignedWrap())
373 break;
374
375 // Subs of constants are common and easy enough.
376 const Value *LHS = U->getOperand(i: 0);
377 const Value *RHS = U->getOperand(i: 1);
378
379 if (const auto *CI = dyn_cast<ConstantInt>(Val: RHS)) {
380 int64_t TmpOffset = Addr.getOffset() - CI->getSExtValue();
381 if (TmpOffset >= 0) {
382 Addr.setOffset(TmpOffset);
383 return computeAddress(Obj: LHS, Addr);
384 }
385 }
386 break;
387 }
388 }
389 if (Addr.isSet()) {
390 return false;
391 }
392 Register Reg = getRegForValue(V: Obj);
393 if (Reg == 0)
394 return false;
395 Addr.setReg(Reg);
396 return Addr.getReg() != 0;
397}
398
399void WebAssemblyFastISel::materializeLoadStoreOperands(Address &Addr) {
400 if (Addr.isRegBase()) {
401 unsigned Reg = Addr.getReg();
402 if (Reg == 0) {
403 Reg = createResultReg(RC: Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
404 : &WebAssembly::I32RegClass);
405 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
406 : WebAssembly::CONST_I32;
407 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: Reg)
408 .addImm(Val: 0);
409 Addr.setReg(Reg);
410 }
411 }
412}
413
414void WebAssemblyFastISel::addLoadStoreOperands(const Address &Addr,
415 const MachineInstrBuilder &MIB,
416 MachineMemOperand *MMO) {
417 // Set the alignment operand (this is rewritten in SetP2AlignOperands).
418 // TODO: Disable SetP2AlignOperands for FastISel and just do it here.
419 MIB.addImm(Val: 0);
420
421 if (const GlobalValue *GV = Addr.getGlobalValue())
422 MIB.addGlobalAddress(GV, Offset: Addr.getOffset());
423 else
424 MIB.addImm(Val: Addr.getOffset());
425
426 if (Addr.isRegBase())
427 MIB.addReg(RegNo: Addr.getReg());
428 else
429 MIB.addFrameIndex(Idx: Addr.getFI());
430
431 MIB.addMemOperand(MMO);
432}
433
434bool WebAssemblyFastISel::emitLoad(Register ResultReg, unsigned Opc,
435 const LoadInst *Load) {
436 Address Addr;
437 if (!computeAddress(Obj: Load->getPointerOperand(), Addr))
438 return false;
439
440 materializeLoadStoreOperands(Addr);
441 auto MIB =
442 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg);
443 addLoadStoreOperands(Addr, MIB, MMO: createMachineMemOperandFor(I: Load));
444
445 return true;
446}
447
448unsigned WebAssemblyFastISel::maskI1Value(unsigned Reg, const Value *V) {
449 return zeroExtendToI32(Reg, V, From: MVT::i1);
450}
451
452unsigned WebAssemblyFastISel::getRegForI1Value(const Value *V,
453 const BasicBlock *BB,
454 bool &Not) {
455 if (const auto *ICmp = dyn_cast<ICmpInst>(Val: V))
456 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: ICmp->getOperand(i_nocapture: 1)))
457 if (ICmp->isEquality() && C->isZero() && C->getType()->isIntegerTy(BitWidth: 32) &&
458 ICmp->getParent() == BB) {
459 Not = ICmp->isTrueWhenEqual();
460 return getRegForValue(V: ICmp->getOperand(i_nocapture: 0));
461 }
462
463 Not = false;
464 Register Reg = getRegForValue(V);
465 if (Reg == 0)
466 return 0;
467 return maskI1Value(Reg, V);
468}
469
470unsigned WebAssemblyFastISel::zeroExtendToI32(unsigned Reg, const Value *V,
471 MVT::SimpleValueType From) {
472 if (Reg == 0)
473 return 0;
474
475 switch (From) {
476 case MVT::i1:
477 // If the value is naturally an i1, we don't need to mask it. We only know
478 // if a value is naturally an i1 if it is definitely lowered by FastISel,
479 // not a DAG ISel fallback.
480 if (V != nullptr && isa<Argument>(Val: V) && cast<Argument>(Val: V)->hasZExtAttr())
481 return copyValue(Reg);
482 break;
483 case MVT::i8:
484 case MVT::i16:
485 break;
486 case MVT::i32:
487 return copyValue(Reg);
488 default:
489 return 0;
490 }
491
492 Register Imm = createResultReg(RC: &WebAssembly::I32RegClass);
493 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
494 MCID: TII.get(Opcode: WebAssembly::CONST_I32), DestReg: Imm)
495 .addImm(Val: ~(~uint64_t(0) << MVT(From).getSizeInBits()));
496
497 Register Result = createResultReg(RC: &WebAssembly::I32RegClass);
498 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: WebAssembly::AND_I32),
499 DestReg: Result)
500 .addReg(RegNo: Reg)
501 .addReg(RegNo: Imm);
502
503 return Result;
504}
505
506unsigned WebAssemblyFastISel::signExtendToI32(unsigned Reg, const Value *V,
507 MVT::SimpleValueType From) {
508 if (Reg == 0)
509 return 0;
510
511 switch (From) {
512 case MVT::i1:
513 case MVT::i8:
514 case MVT::i16:
515 break;
516 case MVT::i32:
517 return copyValue(Reg);
518 default:
519 return 0;
520 }
521
522 if (Subtarget->hasSignExt()) {
523 if (From == MVT::i8 || From == MVT::i16) {
524 Register Result = createResultReg(RC: &WebAssembly::I32RegClass);
525 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
526 MCID: TII.get(Opcode: From == MVT::i16 ? WebAssembly::I32_EXTEND16_S_I32
527 : WebAssembly::I32_EXTEND8_S_I32),
528 DestReg: Result)
529 .addReg(RegNo: Reg);
530 return Result;
531 }
532 }
533
534 Register Imm = createResultReg(RC: &WebAssembly::I32RegClass);
535 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
536 MCID: TII.get(Opcode: WebAssembly::CONST_I32), DestReg: Imm)
537 .addImm(Val: 32 - MVT(From).getSizeInBits());
538
539 Register Left = createResultReg(RC: &WebAssembly::I32RegClass);
540 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: WebAssembly::SHL_I32),
541 DestReg: Left)
542 .addReg(RegNo: Reg)
543 .addReg(RegNo: Imm);
544
545 Register Right = createResultReg(RC: &WebAssembly::I32RegClass);
546 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
547 MCID: TII.get(Opcode: WebAssembly::SHR_S_I32), DestReg: Right)
548 .addReg(RegNo: Left)
549 .addReg(RegNo: Imm);
550
551 return Right;
552}
553
554unsigned WebAssemblyFastISel::zeroExtend(unsigned Reg, const Value *V,
555 MVT::SimpleValueType From,
556 MVT::SimpleValueType To) {
557 if (To == MVT::i64) {
558 if (From == MVT::i64)
559 return copyValue(Reg);
560
561 Reg = zeroExtendToI32(Reg, V, From);
562
563 Register Result = createResultReg(RC: &WebAssembly::I64RegClass);
564 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
565 MCID: TII.get(Opcode: WebAssembly::I64_EXTEND_U_I32), DestReg: Result)
566 .addReg(RegNo: Reg);
567 return Result;
568 }
569
570 if (To == MVT::i32)
571 return zeroExtendToI32(Reg, V, From);
572
573 return 0;
574}
575
576unsigned WebAssemblyFastISel::signExtend(unsigned Reg, const Value *V,
577 MVT::SimpleValueType From,
578 MVT::SimpleValueType To) {
579 if (To == MVT::i64) {
580 if (From == MVT::i64)
581 return copyValue(Reg);
582
583 Register Result = createResultReg(RC: &WebAssembly::I64RegClass);
584
585 if (Subtarget->hasSignExt()) {
586 switch (From) {
587 case MVT::i8:
588 case MVT::i16: {
589 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
590 MCID: TII.get(Opcode: WebAssembly::I64_EXTEND_U_I32), DestReg: Result)
591 .addReg(RegNo: Reg);
592
593 Reg = Result;
594 Result = createResultReg(RC: &WebAssembly::I64RegClass);
595
596 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
597 MCID: TII.get(Opcode: From == MVT::i8 ? WebAssembly::I64_EXTEND8_S_I64
598 : WebAssembly::I64_EXTEND16_S_I64),
599 DestReg: Result)
600 .addReg(RegNo: Reg);
601 return Result;
602 }
603 case MVT::i32:
604 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
605 MCID: TII.get(Opcode: WebAssembly::I64_EXTEND_S_I32), DestReg: Result)
606 .addReg(RegNo: Reg);
607 return Result;
608 default:
609 break;
610 }
611 }
612
613 Reg = signExtendToI32(Reg, V, From);
614 if (Reg == 0)
615 return 0;
616
617 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
618 MCID: TII.get(Opcode: WebAssembly::I64_EXTEND_S_I32), DestReg: Result)
619 .addReg(RegNo: Reg);
620 return Result;
621 }
622
623 if (To == MVT::i32)
624 return signExtendToI32(Reg, V, From);
625
626 return 0;
627}
628
629unsigned WebAssemblyFastISel::getRegForUnsignedValue(const Value *V) {
630 MVT::SimpleValueType From = getSimpleType(Ty: V->getType());
631 MVT::SimpleValueType To = getLegalType(VT: From);
632 Register VReg = getRegForValue(V);
633 if (VReg == 0)
634 return 0;
635 if (From == To)
636 return VReg;
637 return zeroExtend(Reg: VReg, V, From, To);
638}
639
640unsigned WebAssemblyFastISel::getRegForSignedValue(const Value *V) {
641 MVT::SimpleValueType From = getSimpleType(Ty: V->getType());
642 MVT::SimpleValueType To = getLegalType(VT: From);
643 Register VReg = getRegForValue(V);
644 if (VReg == 0)
645 return 0;
646 if (From == To)
647 return VReg;
648 return signExtend(Reg: VReg, V, From, To);
649}
650
651unsigned WebAssemblyFastISel::getRegForPromotedValue(const Value *V,
652 bool IsSigned) {
653 return IsSigned ? getRegForSignedValue(V) : getRegForUnsignedValue(V);
654}
655
656unsigned WebAssemblyFastISel::notValue(unsigned Reg) {
657 assert(MRI.getRegClass(Reg) == &WebAssembly::I32RegClass);
658
659 Register NotReg = createResultReg(RC: &WebAssembly::I32RegClass);
660 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: WebAssembly::EQZ_I32),
661 DestReg: NotReg)
662 .addReg(RegNo: Reg);
663 return NotReg;
664}
665
666unsigned WebAssemblyFastISel::copyValue(unsigned Reg) {
667 Register ResultReg = createResultReg(RC: MRI.getRegClass(Reg));
668 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: WebAssembly::COPY),
669 DestReg: ResultReg)
670 .addReg(RegNo: Reg);
671 return ResultReg;
672}
673
674Register WebAssemblyFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
675 auto SI = FuncInfo.StaticAllocaMap.find(Val: AI);
676
677 if (SI != FuncInfo.StaticAllocaMap.end()) {
678 Register ResultReg =
679 createResultReg(RC: Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
680 : &WebAssembly::I32RegClass);
681 unsigned Opc =
682 Subtarget->hasAddr64() ? WebAssembly::COPY_I64 : WebAssembly::COPY_I32;
683 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
684 .addFrameIndex(Idx: SI->second);
685 return ResultReg;
686 }
687
688 return Register();
689}
690
691Register WebAssemblyFastISel::fastMaterializeConstant(const Constant *C) {
692 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Val: C)) {
693 if (TLI.isPositionIndependent())
694 return Register();
695 if (GV->isThreadLocal())
696 return Register();
697 Register ResultReg =
698 createResultReg(RC: Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
699 : &WebAssembly::I32RegClass);
700 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
701 : WebAssembly::CONST_I32;
702 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
703 .addGlobalAddress(GV);
704 return ResultReg;
705 }
706
707 // Let target-independent code handle it.
708 return Register();
709}
710
711bool WebAssemblyFastISel::fastLowerArguments() {
712 if (!FuncInfo.CanLowerReturn)
713 return false;
714
715 const Function *F = FuncInfo.Fn;
716 if (F->isVarArg())
717 return false;
718
719 if (FuncInfo.Fn->getCallingConv() == CallingConv::Swift)
720 return false;
721
722 unsigned I = 0;
723 for (auto const &Arg : F->args()) {
724 const AttributeList &Attrs = F->getAttributes();
725 if (Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::ByVal) ||
726 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::SwiftSelf) ||
727 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::SwiftError) ||
728 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::InAlloca) ||
729 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::Nest))
730 return false;
731
732 Type *ArgTy = Arg.getType();
733 if (ArgTy->isStructTy() || ArgTy->isArrayTy())
734 return false;
735 if (!Subtarget->hasSIMD128() && ArgTy->isVectorTy())
736 return false;
737
738 unsigned Opc;
739 const TargetRegisterClass *RC;
740 switch (getSimpleType(Ty: ArgTy)) {
741 case MVT::i1:
742 case MVT::i8:
743 case MVT::i16:
744 case MVT::i32:
745 Opc = WebAssembly::ARGUMENT_i32;
746 RC = &WebAssembly::I32RegClass;
747 break;
748 case MVT::i64:
749 Opc = WebAssembly::ARGUMENT_i64;
750 RC = &WebAssembly::I64RegClass;
751 break;
752 case MVT::f32:
753 Opc = WebAssembly::ARGUMENT_f32;
754 RC = &WebAssembly::F32RegClass;
755 break;
756 case MVT::f64:
757 Opc = WebAssembly::ARGUMENT_f64;
758 RC = &WebAssembly::F64RegClass;
759 break;
760 case MVT::v16i8:
761 Opc = WebAssembly::ARGUMENT_v16i8;
762 RC = &WebAssembly::V128RegClass;
763 break;
764 case MVT::v8i16:
765 Opc = WebAssembly::ARGUMENT_v8i16;
766 RC = &WebAssembly::V128RegClass;
767 break;
768 case MVT::v4i32:
769 Opc = WebAssembly::ARGUMENT_v4i32;
770 RC = &WebAssembly::V128RegClass;
771 break;
772 case MVT::v2i64:
773 Opc = WebAssembly::ARGUMENT_v2i64;
774 RC = &WebAssembly::V128RegClass;
775 break;
776 case MVT::v4f32:
777 Opc = WebAssembly::ARGUMENT_v4f32;
778 RC = &WebAssembly::V128RegClass;
779 break;
780 case MVT::v2f64:
781 Opc = WebAssembly::ARGUMENT_v2f64;
782 RC = &WebAssembly::V128RegClass;
783 break;
784 case MVT::funcref:
785 Opc = WebAssembly::ARGUMENT_funcref;
786 RC = &WebAssembly::FUNCREFRegClass;
787 break;
788 case MVT::externref:
789 Opc = WebAssembly::ARGUMENT_externref;
790 RC = &WebAssembly::EXTERNREFRegClass;
791 break;
792 case MVT::exnref:
793 Opc = WebAssembly::ARGUMENT_exnref;
794 RC = &WebAssembly::EXNREFRegClass;
795 break;
796 default:
797 return false;
798 }
799 Register ResultReg = createResultReg(RC);
800 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
801 .addImm(Val: I);
802 updateValueMap(I: &Arg, Reg: ResultReg);
803
804 ++I;
805 }
806
807 MRI.addLiveIn(Reg: WebAssembly::ARGUMENTS);
808
809 auto *MFI = MF->getInfo<WebAssemblyFunctionInfo>();
810 for (auto const &Arg : F->args()) {
811 MVT::SimpleValueType ArgTy = getLegalType(VT: getSimpleType(Ty: Arg.getType()));
812 if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
813 MFI->clearParamsAndResults();
814 return false;
815 }
816 MFI->addParam(VT: ArgTy);
817 }
818
819 if (!F->getReturnType()->isVoidTy()) {
820 MVT::SimpleValueType RetTy =
821 getLegalType(VT: getSimpleType(Ty: F->getReturnType()));
822 if (RetTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
823 MFI->clearParamsAndResults();
824 return false;
825 }
826 MFI->addResult(VT: RetTy);
827 }
828
829 return true;
830}
831
832bool WebAssemblyFastISel::selectCall(const Instruction *I) {
833 const auto *Call = cast<CallInst>(Val: I);
834
835 // TODO: Support tail calls in FastISel
836 if (Call->isMustTailCall() || Call->isInlineAsm() ||
837 Call->getFunctionType()->isVarArg())
838 return false;
839
840 Function *Func = Call->getCalledFunction();
841 if (Func && Func->isIntrinsic())
842 return false;
843
844 if (Call->getCallingConv() == CallingConv::Swift)
845 return false;
846
847 bool IsDirect = Func != nullptr;
848 if (!IsDirect && isa<ConstantExpr>(Val: Call->getCalledOperand()))
849 return false;
850
851 FunctionType *FuncTy = Call->getFunctionType();
852 unsigned Opc = IsDirect ? WebAssembly::CALL : WebAssembly::CALL_INDIRECT;
853 bool IsVoid = FuncTy->getReturnType()->isVoidTy();
854 unsigned ResultReg;
855 if (!IsVoid) {
856 if (!Subtarget->hasSIMD128() && Call->getType()->isVectorTy())
857 return false;
858
859 MVT::SimpleValueType RetTy = getSimpleType(Ty: Call->getType());
860 switch (RetTy) {
861 case MVT::i1:
862 case MVT::i8:
863 case MVT::i16:
864 case MVT::i32:
865 ResultReg = createResultReg(RC: &WebAssembly::I32RegClass);
866 break;
867 case MVT::i64:
868 ResultReg = createResultReg(RC: &WebAssembly::I64RegClass);
869 break;
870 case MVT::f32:
871 ResultReg = createResultReg(RC: &WebAssembly::F32RegClass);
872 break;
873 case MVT::f64:
874 ResultReg = createResultReg(RC: &WebAssembly::F64RegClass);
875 break;
876 case MVT::v16i8:
877 ResultReg = createResultReg(RC: &WebAssembly::V128RegClass);
878 break;
879 case MVT::v8i16:
880 ResultReg = createResultReg(RC: &WebAssembly::V128RegClass);
881 break;
882 case MVT::v4i32:
883 ResultReg = createResultReg(RC: &WebAssembly::V128RegClass);
884 break;
885 case MVT::v2i64:
886 ResultReg = createResultReg(RC: &WebAssembly::V128RegClass);
887 break;
888 case MVT::v4f32:
889 ResultReg = createResultReg(RC: &WebAssembly::V128RegClass);
890 break;
891 case MVT::v2f64:
892 ResultReg = createResultReg(RC: &WebAssembly::V128RegClass);
893 break;
894 case MVT::funcref:
895 ResultReg = createResultReg(RC: &WebAssembly::FUNCREFRegClass);
896 break;
897 case MVT::externref:
898 ResultReg = createResultReg(RC: &WebAssembly::EXTERNREFRegClass);
899 break;
900 case MVT::exnref:
901 ResultReg = createResultReg(RC: &WebAssembly::EXNREFRegClass);
902 break;
903 default:
904 return false;
905 }
906 }
907
908 SmallVector<unsigned, 8> Args;
909 for (unsigned I = 0, E = Call->arg_size(); I < E; ++I) {
910 Value *V = Call->getArgOperand(i: I);
911 MVT::SimpleValueType ArgTy = getSimpleType(Ty: V->getType());
912 if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
913 return false;
914
915 const AttributeList &Attrs = Call->getAttributes();
916 if (Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::ByVal) ||
917 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::SwiftSelf) ||
918 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::SwiftError) ||
919 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::InAlloca) ||
920 Attrs.hasParamAttr(ArgNo: I, Kind: Attribute::Nest))
921 return false;
922
923 unsigned Reg;
924
925 if (Call->paramHasAttr(ArgNo: I, Kind: Attribute::SExt))
926 Reg = getRegForSignedValue(V);
927 else if (Call->paramHasAttr(ArgNo: I, Kind: Attribute::ZExt))
928 Reg = getRegForUnsignedValue(V);
929 else
930 Reg = getRegForValue(V);
931
932 if (Reg == 0)
933 return false;
934
935 Args.push_back(Elt: Reg);
936 }
937
938 unsigned CalleeReg = 0;
939 // A call through a funcref is expressed as a call through the pointer
940 // produced by llvm.wasm.funcref.to_ptr. Recover the funcref operand, place it
941 // into __funcref_call_table, and call it.
942 //
943 // TODO: Use call_ref if wasm-gc feature is available, would lead to simpler
944 // code here.
945 const Value *FuncrefArg = nullptr;
946 if (const auto *Conv = dyn_cast<CallInst>(Val: Call->getCalledOperand()))
947 if (Conv->getIntrinsicID() == Intrinsic::wasm_funcref_to_ptr)
948 FuncrefArg = Conv->getArgOperand(i: 0);
949
950 const bool IsFuncrefCall = FuncrefArg != nullptr;
951 MCSymbolWasm *Table = nullptr;
952
953 if (!IsDirect) {
954 if (!IsFuncrefCall) {
955 // Table is ___indirect_function_table
956 Table = WebAssembly::getOrCreateFunctionTableSymbol(Ctx&: MF->getContext(),
957 Subtarget);
958 CalleeReg = getRegForValue(V: Call->getCalledOperand());
959 if (!CalleeReg)
960 return false;
961 } else {
962 // Table is __funcref_call_table
963 Table = WebAssembly::getOrCreateFuncrefCallTableSymbol(Ctx&: MF->getContext(),
964 Subtarget);
965 CalleeReg = getRegForValue(V: FuncrefArg);
966 // Put the funcref in slot 0 of __funcref_call_table
967 unsigned ZeroReg = createResultReg(RC: &WebAssembly::I32RegClass);
968 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
969 MCID: TII.get(Opcode: WebAssembly::CONST_I32), DestReg: ZeroReg)
970 .addImm(Val: 0);
971 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
972 MCID: TII.get(Opcode: WebAssembly::TABLE_SET_FUNCREF))
973 .addSym(Sym: Table)
974 .addReg(RegNo: ZeroReg)
975 .addReg(RegNo: CalleeReg);
976 // Set CalleeReg to an immediate 0
977 CalleeReg = createResultReg(RC: &WebAssembly::I32RegClass);
978 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
979 MCID: TII.get(Opcode: WebAssembly::CONST_I32), DestReg: CalleeReg)
980 .addImm(Val: 0);
981 }
982 }
983
984 auto MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc));
985
986 if (!IsVoid)
987 MIB.addReg(RegNo: ResultReg, Flags: RegState::Define);
988
989 if (IsDirect) {
990 MIB.addGlobalAddress(GV: Func);
991 } else {
992 // Placeholder for the type index.
993 MIB.addImm(Val: 0);
994 if (Subtarget->hasCallIndirectOverlong()) {
995 MIB.addSym(Sym: Table);
996 } else {
997 // Otherwise for the MVP there is at most one table whose number is 0, but
998 // we can't write a table symbol or issue relocations. Instead we just
999 // ensure the table is live.
1000 Table->setNoStrip();
1001 MIB.addImm(Val: 0);
1002 }
1003 }
1004
1005 for (unsigned ArgReg : Args)
1006 MIB.addReg(RegNo: ArgReg);
1007
1008 if (!IsDirect)
1009 MIB.addReg(RegNo: CalleeReg);
1010
1011 if (IsFuncrefCall) {
1012 // Clear slot 0 of the funcref call table after the call.
1013 unsigned ZeroReg = createResultReg(RC: &WebAssembly::I32RegClass);
1014 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1015 MCID: TII.get(Opcode: WebAssembly::CONST_I32), DestReg: ZeroReg)
1016 .addImm(Val: 0);
1017 unsigned NullReg = createResultReg(RC: &WebAssembly::FUNCREFRegClass);
1018 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1019 MCID: TII.get(Opcode: WebAssembly::REF_NULL_FUNCREF), DestReg: NullReg);
1020 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1021 MCID: TII.get(Opcode: WebAssembly::TABLE_SET_FUNCREF))
1022 .addSym(Sym: Table)
1023 .addReg(RegNo: ZeroReg)
1024 .addReg(RegNo: NullReg);
1025 }
1026
1027 if (!IsVoid)
1028 updateValueMap(I: Call, Reg: ResultReg);
1029
1030 diagnoseDontCall(CI: *Call);
1031 return true;
1032}
1033
1034bool WebAssemblyFastISel::selectSelect(const Instruction *I) {
1035 const auto *Select = cast<SelectInst>(Val: I);
1036
1037 bool Not;
1038 unsigned CondReg =
1039 getRegForI1Value(V: Select->getCondition(), BB: I->getParent(), Not);
1040 if (CondReg == 0)
1041 return false;
1042
1043 Register TrueReg = getRegForValue(V: Select->getTrueValue());
1044 if (TrueReg == 0)
1045 return false;
1046
1047 Register FalseReg = getRegForValue(V: Select->getFalseValue());
1048 if (FalseReg == 0)
1049 return false;
1050
1051 if (Not)
1052 std::swap(a&: TrueReg, b&: FalseReg);
1053
1054 unsigned Opc;
1055 const TargetRegisterClass *RC;
1056 switch (getSimpleType(Ty: Select->getType())) {
1057 case MVT::i1:
1058 case MVT::i8:
1059 case MVT::i16:
1060 case MVT::i32:
1061 Opc = WebAssembly::SELECT_I32;
1062 RC = &WebAssembly::I32RegClass;
1063 break;
1064 case MVT::i64:
1065 Opc = WebAssembly::SELECT_I64;
1066 RC = &WebAssembly::I64RegClass;
1067 break;
1068 case MVT::f32:
1069 Opc = WebAssembly::SELECT_F32;
1070 RC = &WebAssembly::F32RegClass;
1071 break;
1072 case MVT::f64:
1073 Opc = WebAssembly::SELECT_F64;
1074 RC = &WebAssembly::F64RegClass;
1075 break;
1076 case MVT::funcref:
1077 Opc = WebAssembly::SELECT_FUNCREF;
1078 RC = &WebAssembly::FUNCREFRegClass;
1079 break;
1080 case MVT::externref:
1081 Opc = WebAssembly::SELECT_EXTERNREF;
1082 RC = &WebAssembly::EXTERNREFRegClass;
1083 break;
1084 case MVT::exnref:
1085 Opc = WebAssembly::SELECT_EXNREF;
1086 RC = &WebAssembly::EXNREFRegClass;
1087 break;
1088 default:
1089 return false;
1090 }
1091
1092 Register ResultReg = createResultReg(RC);
1093 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
1094 .addReg(RegNo: TrueReg)
1095 .addReg(RegNo: FalseReg)
1096 .addReg(RegNo: CondReg);
1097
1098 updateValueMap(I: Select, Reg: ResultReg);
1099 return true;
1100}
1101
1102bool WebAssemblyFastISel::selectTrunc(const Instruction *I) {
1103 const auto *Trunc = cast<TruncInst>(Val: I);
1104
1105 const Value *Op = Trunc->getOperand(i_nocapture: 0);
1106 MVT::SimpleValueType From = getSimpleType(Ty: Op->getType());
1107 MVT::SimpleValueType To = getLegalType(VT: getSimpleType(Ty: Trunc->getType()));
1108 Register In = getRegForValue(V: Op);
1109 if (In == 0)
1110 return false;
1111
1112 auto Truncate = [&](Register Reg) -> unsigned {
1113 if (From == MVT::i64) {
1114 if (To == MVT::i64)
1115 return copyValue(Reg);
1116
1117 if (To == MVT::i1 || To == MVT::i8 || To == MVT::i16 || To == MVT::i32) {
1118 Register Result = createResultReg(RC: &WebAssembly::I32RegClass);
1119 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1120 MCID: TII.get(Opcode: WebAssembly::I32_WRAP_I64), DestReg: Result)
1121 .addReg(RegNo: Reg);
1122 return Result;
1123 }
1124 }
1125
1126 if (From == MVT::i32)
1127 return copyValue(Reg);
1128
1129 return 0;
1130 };
1131
1132 unsigned Reg = Truncate(In);
1133 if (Reg == 0)
1134 return false;
1135
1136 updateValueMap(I: Trunc, Reg);
1137 return true;
1138}
1139
1140bool WebAssemblyFastISel::selectZExt(const Instruction *I) {
1141 const auto *ZExt = cast<ZExtInst>(Val: I);
1142
1143 const Value *Op = ZExt->getOperand(i_nocapture: 0);
1144 MVT::SimpleValueType From = getSimpleType(Ty: Op->getType());
1145 MVT::SimpleValueType To = getLegalType(VT: getSimpleType(Ty: ZExt->getType()));
1146 Register In = getRegForValue(V: Op);
1147 if (In == 0)
1148 return false;
1149 unsigned Reg = zeroExtend(Reg: In, V: Op, From, To);
1150 if (Reg == 0)
1151 return false;
1152
1153 updateValueMap(I: ZExt, Reg);
1154 return true;
1155}
1156
1157bool WebAssemblyFastISel::selectSExt(const Instruction *I) {
1158 const auto *SExt = cast<SExtInst>(Val: I);
1159
1160 const Value *Op = SExt->getOperand(i_nocapture: 0);
1161 MVT::SimpleValueType From = getSimpleType(Ty: Op->getType());
1162 MVT::SimpleValueType To = getLegalType(VT: getSimpleType(Ty: SExt->getType()));
1163 Register In = getRegForValue(V: Op);
1164 if (In == 0)
1165 return false;
1166 unsigned Reg = signExtend(Reg: In, V: Op, From, To);
1167 if (Reg == 0)
1168 return false;
1169
1170 updateValueMap(I: SExt, Reg);
1171 return true;
1172}
1173
1174bool WebAssemblyFastISel::selectICmp(const Instruction *I) {
1175 const auto *ICmp = cast<ICmpInst>(Val: I);
1176
1177 bool I32 = getSimpleType(Ty: ICmp->getOperand(i_nocapture: 0)->getType()) != MVT::i64;
1178 unsigned Opc;
1179 bool IsSigned = false;
1180 switch (ICmp->getPredicate()) {
1181 case ICmpInst::ICMP_EQ:
1182 Opc = I32 ? WebAssembly::EQ_I32 : WebAssembly::EQ_I64;
1183 break;
1184 case ICmpInst::ICMP_NE:
1185 Opc = I32 ? WebAssembly::NE_I32 : WebAssembly::NE_I64;
1186 break;
1187 case ICmpInst::ICMP_UGT:
1188 Opc = I32 ? WebAssembly::GT_U_I32 : WebAssembly::GT_U_I64;
1189 break;
1190 case ICmpInst::ICMP_UGE:
1191 Opc = I32 ? WebAssembly::GE_U_I32 : WebAssembly::GE_U_I64;
1192 break;
1193 case ICmpInst::ICMP_ULT:
1194 Opc = I32 ? WebAssembly::LT_U_I32 : WebAssembly::LT_U_I64;
1195 break;
1196 case ICmpInst::ICMP_ULE:
1197 Opc = I32 ? WebAssembly::LE_U_I32 : WebAssembly::LE_U_I64;
1198 break;
1199 case ICmpInst::ICMP_SGT:
1200 Opc = I32 ? WebAssembly::GT_S_I32 : WebAssembly::GT_S_I64;
1201 IsSigned = true;
1202 break;
1203 case ICmpInst::ICMP_SGE:
1204 Opc = I32 ? WebAssembly::GE_S_I32 : WebAssembly::GE_S_I64;
1205 IsSigned = true;
1206 break;
1207 case ICmpInst::ICMP_SLT:
1208 Opc = I32 ? WebAssembly::LT_S_I32 : WebAssembly::LT_S_I64;
1209 IsSigned = true;
1210 break;
1211 case ICmpInst::ICMP_SLE:
1212 Opc = I32 ? WebAssembly::LE_S_I32 : WebAssembly::LE_S_I64;
1213 IsSigned = true;
1214 break;
1215 default:
1216 return false;
1217 }
1218
1219 unsigned LHS = getRegForPromotedValue(V: ICmp->getOperand(i_nocapture: 0), IsSigned);
1220 if (LHS == 0)
1221 return false;
1222
1223 unsigned RHS = getRegForPromotedValue(V: ICmp->getOperand(i_nocapture: 1), IsSigned);
1224 if (RHS == 0)
1225 return false;
1226
1227 Register ResultReg = createResultReg(RC: &WebAssembly::I32RegClass);
1228 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
1229 .addReg(RegNo: LHS)
1230 .addReg(RegNo: RHS);
1231 updateValueMap(I: ICmp, Reg: ResultReg);
1232 return true;
1233}
1234
1235bool WebAssemblyFastISel::selectFCmp(const Instruction *I) {
1236 const auto *FCmp = cast<FCmpInst>(Val: I);
1237
1238 Register LHS = getRegForValue(V: FCmp->getOperand(i_nocapture: 0));
1239 if (LHS == 0)
1240 return false;
1241
1242 Register RHS = getRegForValue(V: FCmp->getOperand(i_nocapture: 1));
1243 if (RHS == 0)
1244 return false;
1245
1246 bool F32 = getSimpleType(Ty: FCmp->getOperand(i_nocapture: 0)->getType()) != MVT::f64;
1247 unsigned Opc;
1248 bool Not = false;
1249 switch (FCmp->getPredicate()) {
1250 case FCmpInst::FCMP_OEQ:
1251 Opc = F32 ? WebAssembly::EQ_F32 : WebAssembly::EQ_F64;
1252 break;
1253 case FCmpInst::FCMP_UNE:
1254 Opc = F32 ? WebAssembly::NE_F32 : WebAssembly::NE_F64;
1255 break;
1256 case FCmpInst::FCMP_OGT:
1257 Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
1258 break;
1259 case FCmpInst::FCMP_OGE:
1260 Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
1261 break;
1262 case FCmpInst::FCMP_OLT:
1263 Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
1264 break;
1265 case FCmpInst::FCMP_OLE:
1266 Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
1267 break;
1268 case FCmpInst::FCMP_UGT:
1269 Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
1270 Not = true;
1271 break;
1272 case FCmpInst::FCMP_UGE:
1273 Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
1274 Not = true;
1275 break;
1276 case FCmpInst::FCMP_ULT:
1277 Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
1278 Not = true;
1279 break;
1280 case FCmpInst::FCMP_ULE:
1281 Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
1282 Not = true;
1283 break;
1284 default:
1285 return false;
1286 }
1287
1288 Register ResultReg = createResultReg(RC: &WebAssembly::I32RegClass);
1289 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
1290 .addReg(RegNo: LHS)
1291 .addReg(RegNo: RHS);
1292
1293 if (Not)
1294 ResultReg = notValue(Reg: ResultReg);
1295
1296 updateValueMap(I: FCmp, Reg: ResultReg);
1297 return true;
1298}
1299
1300bool WebAssemblyFastISel::selectBitCast(const Instruction *I) {
1301 // Target-independent code can handle this, except it doesn't set the dead
1302 // flag on the ARGUMENTS clobber, so we have to do that manually in order
1303 // to satisfy code that expects this of isBitcast() instructions.
1304 EVT VT = TLI.getValueType(DL, Ty: I->getOperand(i: 0)->getType());
1305 EVT RetVT = TLI.getValueType(DL, Ty: I->getType());
1306 if (!VT.isSimple() || !RetVT.isSimple())
1307 return false;
1308
1309 Register In = getRegForValue(V: I->getOperand(i: 0));
1310 if (In == 0)
1311 return false;
1312
1313 if (VT == RetVT) {
1314 // No-op bitcast.
1315 updateValueMap(I, Reg: In);
1316 return true;
1317 }
1318
1319 Register Reg =
1320 fastEmit_ISD_BITCAST_r(VT: VT.getSimpleVT(), RetVT: RetVT.getSimpleVT(), Op0: In);
1321 if (!Reg)
1322 return false;
1323 MachineBasicBlock::iterator Iter = FuncInfo.InsertPt;
1324 --Iter;
1325 assert(Iter->isBitcast());
1326 Iter->setPhysRegsDeadExcept(UsedRegs: ArrayRef<Register>(), TRI);
1327 updateValueMap(I, Reg);
1328 return true;
1329}
1330
1331static unsigned getSExtLoadOpcode(unsigned LoadSize, bool I64Result, bool A64) {
1332 if (I64Result) {
1333 switch (LoadSize) {
1334 default:
1335 return WebAssembly::INSTRUCTION_LIST_END;
1336 case 8:
1337 return A64 ? WebAssembly::LOAD8_S_I64_A64 : WebAssembly::LOAD8_S_I64_A32;
1338 case 16:
1339 return A64 ? WebAssembly::LOAD16_S_I64_A64
1340 : WebAssembly::LOAD16_S_I64_A32;
1341 case 32:
1342 return A64 ? WebAssembly::LOAD32_S_I64_A64
1343 : WebAssembly::LOAD32_S_I64_A32;
1344 }
1345 }
1346
1347 switch (LoadSize) {
1348 default:
1349 return WebAssembly::INSTRUCTION_LIST_END;
1350 case 8:
1351 return A64 ? WebAssembly::LOAD8_S_I32_A64 : WebAssembly::LOAD8_S_I32_A32;
1352 case 16:
1353 return A64 ? WebAssembly::LOAD16_S_I32_A64 : WebAssembly::LOAD16_S_I32_A32;
1354 }
1355}
1356
1357static unsigned getZExtLoadOpcode(unsigned LoadSize, bool I64Result, bool A64) {
1358 if (I64Result) {
1359 switch (LoadSize) {
1360 default:
1361 return WebAssembly::INSTRUCTION_LIST_END;
1362 case 8:
1363 return A64 ? WebAssembly::LOAD8_U_I64_A64 : WebAssembly::LOAD8_U_I64_A32;
1364 case 16:
1365 return A64 ? WebAssembly::LOAD16_U_I64_A64
1366 : WebAssembly::LOAD16_U_I64_A32;
1367 case 32:
1368 return A64 ? WebAssembly::LOAD32_U_I64_A64
1369 : WebAssembly::LOAD32_U_I64_A32;
1370 }
1371 }
1372
1373 switch (LoadSize) {
1374 default:
1375 return WebAssembly::INSTRUCTION_LIST_END;
1376 case 8:
1377 return A64 ? WebAssembly::LOAD8_U_I32_A64 : WebAssembly::LOAD8_U_I32_A32;
1378 case 16:
1379 return A64 ? WebAssembly::LOAD16_U_I32_A64 : WebAssembly::LOAD16_U_I32_A32;
1380 }
1381}
1382
1383static bool isFoldableSExtOpcode(unsigned Opc) {
1384 switch (Opc) {
1385 default:
1386 return false;
1387 case WebAssembly::I32_EXTEND8_S_I32:
1388 case WebAssembly::I32_EXTEND16_S_I32:
1389 case WebAssembly::I64_EXTEND8_S_I64:
1390 case WebAssembly::I64_EXTEND16_S_I64:
1391 case WebAssembly::I64_EXTEND32_S_I64:
1392 case WebAssembly::I64_EXTEND_S_I32:
1393 return true;
1394 }
1395}
1396
1397static bool isI64SExtResult(unsigned Opc) {
1398 switch (Opc) {
1399 default:
1400 llvm_unreachable("unexpected opcode");
1401 case WebAssembly::I32_EXTEND8_S_I32:
1402 case WebAssembly::I32_EXTEND16_S_I32:
1403 return false;
1404 case WebAssembly::I64_EXTEND8_S_I64:
1405 case WebAssembly::I64_EXTEND16_S_I64:
1406 case WebAssembly::I64_EXTEND32_S_I64:
1407 case WebAssembly::I64_EXTEND_S_I32:
1408 return true;
1409 }
1410}
1411
1412static unsigned getFoldedLoadOpcode(MachineInstr *MI, MachineRegisterInfo &MRI,
1413 const LoadInst *LI, bool A64) {
1414 unsigned Opc = MI->getOpcode();
1415
1416 if (isFoldableSExtOpcode(Opc)) {
1417 unsigned LoadSize = LI->getType()->getPrimitiveSizeInBits();
1418 return getSExtLoadOpcode(LoadSize, I64Result: isI64SExtResult(Opc), A64);
1419 }
1420
1421 return WebAssembly::INSTRUCTION_LIST_END;
1422}
1423
1424static unsigned getFoldedI64LoadOpcode(Register DestReg, const LoadInst *LI,
1425 MachineRegisterInfo &MRI, bool A64,
1426 MachineInstr *&OuterUserMI,
1427 unsigned NarrowOpc) {
1428 if (!MRI.hasOneNonDBGUse(RegNo: DestReg))
1429 return NarrowOpc;
1430
1431 MachineInstr *UserMI = &*MRI.use_instr_nodbg_begin(RegNo: DestReg);
1432 unsigned LoadSize = LI->getType()->getPrimitiveSizeInBits();
1433 switch (UserMI->getOpcode()) {
1434 case WebAssembly::I64_EXTEND_U_I32:
1435 OuterUserMI = UserMI;
1436 return getZExtLoadOpcode(LoadSize, /*I64Result=*/true, A64);
1437 case WebAssembly::I64_EXTEND_S_I32:
1438 OuterUserMI = UserMI;
1439 return getSExtLoadOpcode(LoadSize, /*I64Result=*/true, A64);
1440 default:
1441 return NarrowOpc;
1442 }
1443}
1444
1445/// Matches a sign-extension pattern (shl + shr_s) to fold it into a signed
1446/// load. FastISel assumes that 'sext' from i8 or i16 will first be lowered to a
1447/// 32-bit zero-extending load (i32.load8_u / i32.load16_u) followed by 32-bit
1448/// shifts, even when extending to i64. Therefore, this function only matches
1449/// 32-bit shifts (SHL_I32 / SHR_S_I32) and specifically checks if both shift
1450/// amounts are identical, compile-time constants that match the exact extension
1451/// size (32 - LoadBitWidth).
1452static unsigned matchFoldableShift(MachineInstr *MI, const LoadInst *LI,
1453 MachineRegisterInfo &MRI, bool A64,
1454 MachineInstr *&UserMI,
1455 MachineInstr *&OuterUserMI) {
1456 unsigned Opc = MI->getOpcode();
1457 unsigned NewOpc = WebAssembly::INSTRUCTION_LIST_END;
1458 if (Opc != WebAssembly::SHL_I32)
1459 return NewOpc;
1460
1461 Register DestReg = MI->getOperand(i: 0).getReg();
1462 if (!MRI.hasOneNonDBGUse(RegNo: DestReg))
1463 return NewOpc;
1464
1465 UserMI = &*MRI.use_instr_nodbg_begin(RegNo: DestReg);
1466 unsigned UserOpc = UserMI->getOpcode();
1467 if (UserOpc != WebAssembly::SHR_S_I32)
1468 return NewOpc;
1469
1470 Type *LoadTy = LI->getType();
1471 if (!LoadTy->isIntegerTy(BitWidth: 8) && !LoadTy->isIntegerTy(BitWidth: 16))
1472 return NewOpc;
1473
1474 int64_t ExpectedShiftAmt = 32 - LoadTy->getIntegerBitWidth();
1475 Register ShlAmtReg = MI->getOperand(i: 2).getReg();
1476 Register ShrAmtReg = UserMI->getOperand(i: 2).getReg();
1477 MachineInstr *ShlAmtDef = MRI.getUniqueVRegDef(Reg: ShlAmtReg);
1478 MachineInstr *ShrAmtDef = MRI.getUniqueVRegDef(Reg: ShrAmtReg);
1479 auto IsExpectedConst = [ExpectedShiftAmt](MachineInstr *MI) {
1480 return MI && MI->getOpcode() == WebAssembly::CONST_I32 &&
1481 MI->getOperand(i: 1).getImm() == ExpectedShiftAmt;
1482 };
1483 if (!IsExpectedConst(ShlAmtDef) || !IsExpectedConst(ShrAmtDef))
1484 return NewOpc;
1485
1486 unsigned LoadSize = LoadTy->getIntegerBitWidth();
1487 unsigned NarrowOpc = getSExtLoadOpcode(LoadSize, /*I64Result=*/false, A64);
1488 if (NarrowOpc == WebAssembly::INSTRUCTION_LIST_END)
1489 return WebAssembly::INSTRUCTION_LIST_END;
1490
1491 return getFoldedI64LoadOpcode(DestReg: UserMI->getOperand(i: 0).getReg(), LI, MRI, A64,
1492 OuterUserMI, NarrowOpc);
1493}
1494
1495static unsigned matchFoldableSExtFromPromotedI32(MachineInstr *MI,
1496 const LoadInst *LI,
1497 MachineRegisterInfo &MRI,
1498 bool A64,
1499 MachineInstr *&UserMI) {
1500 if (MI->getOpcode() != WebAssembly::I64_EXTEND_U_I32)
1501 return WebAssembly::INSTRUCTION_LIST_END;
1502
1503 unsigned LoadSize = LI->getType()->getPrimitiveSizeInBits();
1504 Register DestReg = MI->getOperand(i: 0).getReg();
1505 if (!MRI.hasOneNonDBGUse(RegNo: DestReg))
1506 return WebAssembly::INSTRUCTION_LIST_END;
1507
1508 UserMI = &*MRI.use_instr_nodbg_begin(RegNo: DestReg);
1509 switch (UserMI->getOpcode()) {
1510 default:
1511 return WebAssembly::INSTRUCTION_LIST_END;
1512 case WebAssembly::I64_EXTEND8_S_I64:
1513 if (LoadSize != 8)
1514 return WebAssembly::INSTRUCTION_LIST_END;
1515 return getSExtLoadOpcode(LoadSize, I64Result: true, A64);
1516 case WebAssembly::I64_EXTEND16_S_I64:
1517 if (LoadSize != 16)
1518 return WebAssembly::INSTRUCTION_LIST_END;
1519 return getSExtLoadOpcode(LoadSize, I64Result: true, A64);
1520 }
1521}
1522
1523static unsigned matchFoldableCopyToI64Ext(MachineInstr *MI, const LoadInst *LI,
1524 MachineRegisterInfo &MRI, bool A64,
1525 MachineInstr *&OuterUserMI) {
1526 if (MI->getOpcode() != WebAssembly::COPY)
1527 return WebAssembly::INSTRUCTION_LIST_END;
1528
1529 unsigned LoadSize = LI->getType()->getPrimitiveSizeInBits();
1530 if (LoadSize != 32)
1531 return WebAssembly::INSTRUCTION_LIST_END;
1532
1533 Register CopyDst = MI->getOperand(i: 0).getReg();
1534 if (!MRI.hasOneNonDBGUse(RegNo: CopyDst))
1535 return WebAssembly::INSTRUCTION_LIST_END;
1536
1537 OuterUserMI = &*MRI.use_instr_nodbg_begin(RegNo: CopyDst);
1538 switch (OuterUserMI->getOpcode()) {
1539 default:
1540 return WebAssembly::INSTRUCTION_LIST_END;
1541 case WebAssembly::I64_EXTEND_U_I32:
1542 return getZExtLoadOpcode(LoadSize, I64Result: true, A64);
1543 case WebAssembly::I64_EXTEND_S_I32:
1544 return getSExtLoadOpcode(LoadSize, I64Result: true, A64);
1545 }
1546}
1547
1548static unsigned matchFoldableAnd(MachineInstr *MI, const LoadInst *LI,
1549 MachineRegisterInfo &MRI, bool A64,
1550 MachineInstr *&OuterUserMI) {
1551 if (MI->getOpcode() != WebAssembly::AND_I32 &&
1552 MI->getOpcode() != WebAssembly::AND_I64)
1553 return WebAssembly::INSTRUCTION_LIST_END;
1554
1555 uint64_t Mask = 0;
1556 bool IsConstant = false;
1557 for (unsigned I = 1; I <= 2; ++I) {
1558 Register Reg = MI->getOperand(i: I).getReg();
1559 MachineInstr *DefMI = MRI.getUniqueVRegDef(Reg);
1560 if (DefMI && (DefMI->getOpcode() == WebAssembly::CONST_I32 ||
1561 DefMI->getOpcode() == WebAssembly::CONST_I64)) {
1562 Mask = DefMI->getOperand(i: 1).getImm();
1563 IsConstant = true;
1564 break;
1565 }
1566 }
1567
1568 if (!IsConstant)
1569 return WebAssembly::INSTRUCTION_LIST_END;
1570
1571 unsigned LoadSize = LI->getType()->getPrimitiveSizeInBits();
1572 if (Mask != llvm::maskTrailingOnes<uint64_t>(N: LoadSize))
1573 return WebAssembly::INSTRUCTION_LIST_END;
1574
1575 if (MI->getOpcode() == WebAssembly::AND_I64)
1576 return getZExtLoadOpcode(LoadSize, /*I64Result=*/true, A64);
1577
1578 unsigned NarrowOpc = getZExtLoadOpcode(LoadSize, /*I64Result=*/false, A64);
1579 if (NarrowOpc == WebAssembly::INSTRUCTION_LIST_END)
1580 return WebAssembly::INSTRUCTION_LIST_END;
1581
1582 return getFoldedI64LoadOpcode(DestReg: MI->getOperand(i: 0).getReg(), LI, MRI, A64,
1583 OuterUserMI, NarrowOpc);
1584}
1585
1586bool WebAssemblyFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
1587 const LoadInst *LI) {
1588 bool A64 = Subtarget->hasAddr64();
1589 MachineRegisterInfo &MRI = FuncInfo.MF->getRegInfo();
1590 Register ResultReg;
1591 MachineInstr *UserMI = nullptr;
1592 MachineInstr *OuterUserMI = nullptr;
1593 unsigned NewOpc = WebAssembly::INSTRUCTION_LIST_END;
1594 if ((NewOpc = matchFoldableSExtFromPromotedI32(MI, LI, MRI, A64, UserMI)) !=
1595 WebAssembly::INSTRUCTION_LIST_END) {
1596 ResultReg = UserMI->getOperand(i: 0).getReg();
1597 } else if ((NewOpc =
1598 matchFoldableCopyToI64Ext(MI, LI, MRI, A64, OuterUserMI)) !=
1599 WebAssembly::INSTRUCTION_LIST_END) {
1600 ResultReg = OuterUserMI->getOperand(i: 0).getReg();
1601 } else if ((NewOpc = matchFoldableAnd(MI, LI, MRI, A64, OuterUserMI)) !=
1602 WebAssembly::INSTRUCTION_LIST_END) {
1603 ResultReg = OuterUserMI ? OuterUserMI->getOperand(i: 0).getReg()
1604 : MI->getOperand(i: 0).getReg();
1605 } else if ((NewOpc = getFoldedLoadOpcode(MI, MRI, LI, A64)) !=
1606 WebAssembly::INSTRUCTION_LIST_END) {
1607 ResultReg = MI->getOperand(i: 0).getReg();
1608 } else if ((NewOpc =
1609 matchFoldableShift(MI, LI, MRI, A64, UserMI, OuterUserMI)) !=
1610 WebAssembly::INSTRUCTION_LIST_END) {
1611 ResultReg = OuterUserMI ? OuterUserMI->getOperand(i: 0).getReg()
1612 : UserMI->getOperand(i: 0).getReg();
1613 } else {
1614 return false;
1615 }
1616
1617 if (!emitLoad(ResultReg, Opc: NewOpc, Load: LI))
1618 return false;
1619
1620 if (OuterUserMI) {
1621 MachineBasicBlock::iterator OuterIter(OuterUserMI);
1622 removeDeadCode(I: OuterIter, E: std::next(x: OuterIter));
1623 }
1624
1625 if (UserMI) {
1626 MachineBasicBlock::iterator UserIter(UserMI);
1627 removeDeadCode(I: UserIter, E: std::next(x: UserIter));
1628 }
1629
1630 MachineBasicBlock::iterator Iter(MI);
1631 removeDeadCode(I: Iter, E: std::next(x: Iter));
1632 return true;
1633}
1634
1635bool WebAssemblyFastISel::selectLoad(const Instruction *I) {
1636 const auto *Load = cast<LoadInst>(Val: I);
1637 if (Load->isAtomic())
1638 return false;
1639 if (!WebAssembly::isDefaultAddressSpace(AS: Load->getPointerAddressSpace()))
1640 return false;
1641 if (!Subtarget->hasSIMD128() && Load->getType()->isVectorTy())
1642 return false;
1643
1644 // TODO: Fold a following sign-/zero-extend into the load instruction.
1645
1646 unsigned Opc;
1647 const TargetRegisterClass *RC;
1648 bool A64 = Subtarget->hasAddr64();
1649 switch (getSimpleType(Ty: Load->getType())) {
1650 case MVT::i1:
1651 case MVT::i8:
1652 Opc = A64 ? WebAssembly::LOAD8_U_I32_A64 : WebAssembly::LOAD8_U_I32_A32;
1653 RC = &WebAssembly::I32RegClass;
1654 break;
1655 case MVT::i16:
1656 Opc = A64 ? WebAssembly::LOAD16_U_I32_A64 : WebAssembly::LOAD16_U_I32_A32;
1657 RC = &WebAssembly::I32RegClass;
1658 break;
1659 case MVT::i32:
1660 Opc = A64 ? WebAssembly::LOAD_I32_A64 : WebAssembly::LOAD_I32_A32;
1661 RC = &WebAssembly::I32RegClass;
1662 break;
1663 case MVT::i64:
1664 Opc = A64 ? WebAssembly::LOAD_I64_A64 : WebAssembly::LOAD_I64_A32;
1665 RC = &WebAssembly::I64RegClass;
1666 break;
1667 case MVT::f32:
1668 Opc = A64 ? WebAssembly::LOAD_F32_A64 : WebAssembly::LOAD_F32_A32;
1669 RC = &WebAssembly::F32RegClass;
1670 break;
1671 case MVT::f64:
1672 Opc = A64 ? WebAssembly::LOAD_F64_A64 : WebAssembly::LOAD_F64_A32;
1673 RC = &WebAssembly::F64RegClass;
1674 break;
1675 default:
1676 return false;
1677 }
1678
1679 Register ResultReg = createResultReg(RC);
1680 if (!emitLoad(ResultReg, Opc, Load))
1681 return false;
1682
1683 updateValueMap(I: Load, Reg: ResultReg);
1684 return true;
1685}
1686
1687bool WebAssemblyFastISel::selectStore(const Instruction *I) {
1688 const auto *Store = cast<StoreInst>(Val: I);
1689 if (Store->isAtomic())
1690 return false;
1691 if (!WebAssembly::isDefaultAddressSpace(AS: Store->getPointerAddressSpace()))
1692 return false;
1693 if (!Subtarget->hasSIMD128() &&
1694 Store->getValueOperand()->getType()->isVectorTy())
1695 return false;
1696
1697 Address Addr;
1698 if (!computeAddress(Obj: Store->getPointerOperand(), Addr))
1699 return false;
1700
1701 unsigned Opc;
1702 bool VTIsi1 = false;
1703 bool A64 = Subtarget->hasAddr64();
1704 switch (getSimpleType(Ty: Store->getValueOperand()->getType())) {
1705 case MVT::i1:
1706 VTIsi1 = true;
1707 [[fallthrough]];
1708 case MVT::i8:
1709 Opc = A64 ? WebAssembly::STORE8_I32_A64 : WebAssembly::STORE8_I32_A32;
1710 break;
1711 case MVT::i16:
1712 Opc = A64 ? WebAssembly::STORE16_I32_A64 : WebAssembly::STORE16_I32_A32;
1713 break;
1714 case MVT::i32:
1715 Opc = A64 ? WebAssembly::STORE_I32_A64 : WebAssembly::STORE_I32_A32;
1716 break;
1717 case MVT::i64:
1718 Opc = A64 ? WebAssembly::STORE_I64_A64 : WebAssembly::STORE_I64_A32;
1719 break;
1720 case MVT::f32:
1721 Opc = A64 ? WebAssembly::STORE_F32_A64 : WebAssembly::STORE_F32_A32;
1722 break;
1723 case MVT::f64:
1724 Opc = A64 ? WebAssembly::STORE_F64_A64 : WebAssembly::STORE_F64_A32;
1725 break;
1726 default:
1727 return false;
1728 }
1729
1730 materializeLoadStoreOperands(Addr);
1731
1732 Register ValueReg = getRegForValue(V: Store->getValueOperand());
1733 if (ValueReg == 0)
1734 return false;
1735 if (VTIsi1)
1736 ValueReg = maskI1Value(Reg: ValueReg, V: Store->getValueOperand());
1737
1738 auto MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc));
1739
1740 addLoadStoreOperands(Addr, MIB, MMO: createMachineMemOperandFor(I: Store));
1741
1742 MIB.addReg(RegNo: ValueReg);
1743 return true;
1744}
1745
1746bool WebAssemblyFastISel::selectCondBr(const Instruction *I) {
1747 const auto *Br = cast<CondBrInst>(Val: I);
1748
1749 MachineBasicBlock *TBB = FuncInfo.getMBB(BB: Br->getSuccessor(i: 0));
1750 MachineBasicBlock *FBB = FuncInfo.getMBB(BB: Br->getSuccessor(i: 1));
1751
1752 bool Not;
1753 unsigned CondReg = getRegForI1Value(V: Br->getCondition(), BB: Br->getParent(), Not);
1754 if (CondReg == 0)
1755 return false;
1756
1757 unsigned Opc = WebAssembly::BR_IF;
1758 if (Not)
1759 Opc = WebAssembly::BR_UNLESS;
1760
1761 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc))
1762 .addMBB(MBB: TBB)
1763 .addReg(RegNo: CondReg);
1764
1765 finishCondBranch(BranchBB: Br->getParent(), TrueMBB: TBB, FalseMBB: FBB);
1766 return true;
1767}
1768
1769bool WebAssemblyFastISel::selectRet(const Instruction *I) {
1770 if (!FuncInfo.CanLowerReturn)
1771 return false;
1772
1773 const auto *Ret = cast<ReturnInst>(Val: I);
1774
1775 if (Ret->getNumOperands() == 0) {
1776 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1777 MCID: TII.get(Opcode: WebAssembly::RETURN));
1778 return true;
1779 }
1780
1781 // TODO: support multiple return in FastISel
1782 if (Ret->getNumOperands() > 1)
1783 return false;
1784
1785 Value *RV = Ret->getOperand(i_nocapture: 0);
1786 if (!Subtarget->hasSIMD128() && RV->getType()->isVectorTy())
1787 return false;
1788
1789 switch (getSimpleType(Ty: RV->getType())) {
1790 case MVT::i1:
1791 case MVT::i8:
1792 case MVT::i16:
1793 case MVT::i32:
1794 case MVT::i64:
1795 case MVT::f32:
1796 case MVT::f64:
1797 case MVT::v16i8:
1798 case MVT::v8i16:
1799 case MVT::v4i32:
1800 case MVT::v2i64:
1801 case MVT::v4f32:
1802 case MVT::v2f64:
1803 case MVT::funcref:
1804 case MVT::externref:
1805 case MVT::exnref:
1806 break;
1807 default:
1808 return false;
1809 }
1810
1811 unsigned Reg;
1812 if (FuncInfo.Fn->getAttributes().hasRetAttr(Kind: Attribute::SExt))
1813 Reg = getRegForSignedValue(V: RV);
1814 else if (FuncInfo.Fn->getAttributes().hasRetAttr(Kind: Attribute::ZExt))
1815 Reg = getRegForUnsignedValue(V: RV);
1816 else
1817 Reg = getRegForValue(V: RV);
1818
1819 if (Reg == 0)
1820 return false;
1821
1822 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: WebAssembly::RETURN))
1823 .addReg(RegNo: Reg);
1824 return true;
1825}
1826
1827bool WebAssemblyFastISel::selectUnreachable(const Instruction *I) {
1828 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1829 MCID: TII.get(Opcode: WebAssembly::UNREACHABLE));
1830 return true;
1831}
1832
1833bool WebAssemblyFastISel::fastSelectInstruction(const Instruction *I) {
1834 switch (I->getOpcode()) {
1835 case Instruction::Call:
1836 if (selectCall(I))
1837 return true;
1838 break;
1839 case Instruction::Select:
1840 return selectSelect(I);
1841 case Instruction::Trunc:
1842 return selectTrunc(I);
1843 case Instruction::ZExt:
1844 return selectZExt(I);
1845 case Instruction::SExt:
1846 return selectSExt(I);
1847 case Instruction::ICmp:
1848 return selectICmp(I);
1849 case Instruction::FCmp:
1850 return selectFCmp(I);
1851 case Instruction::BitCast:
1852 return selectBitCast(I);
1853 case Instruction::Load:
1854 return selectLoad(I);
1855 case Instruction::Store:
1856 return selectStore(I);
1857 case Instruction::CondBr:
1858 return selectCondBr(I);
1859 case Instruction::Ret:
1860 return selectRet(I);
1861 case Instruction::Unreachable:
1862 return selectUnreachable(I);
1863 default:
1864 break;
1865 }
1866
1867 // Fall back to target-independent instruction selection.
1868 return selectOperator(I, Opcode: I->getOpcode());
1869}
1870
1871FastISel *
1872WebAssembly::createFastISel(FunctionLoweringInfo &FuncInfo,
1873 const TargetLibraryInfo *LibInfo,
1874 const LibcallLoweringInfo *LibcallLowering) {
1875 return new WebAssemblyFastISel(FuncInfo, LibInfo, LibcallLowering);
1876}
1877