1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#if !defined(GET_CC_REGISTER_LISTS)
10
11static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
14bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
17static bool CC_X86_32(unsigned ValNo, MVT ValVT,
18 MVT LocVT, CCValAssign::LocInfo LocInfo,
19 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
20static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
23static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
24 MVT LocVT, CCValAssign::LocInfo LocInfo,
25 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
26static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
27 MVT LocVT, CCValAssign::LocInfo LocInfo,
28 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
29static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
30 MVT LocVT, CCValAssign::LocInfo LocInfo,
31 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
32static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
33 MVT LocVT, CCValAssign::LocInfo LocInfo,
34 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
35static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
36 MVT LocVT, CCValAssign::LocInfo LocInfo,
37 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
38static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
39 MVT LocVT, CCValAssign::LocInfo LocInfo,
40 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
41static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
42 MVT LocVT, CCValAssign::LocInfo LocInfo,
43 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
44static bool CC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
45 MVT LocVT, CCValAssign::LocInfo LocInfo,
46 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
47static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
48 MVT LocVT, CCValAssign::LocInfo LocInfo,
49 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
50static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
51 MVT LocVT, CCValAssign::LocInfo LocInfo,
52 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
53static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
54 MVT LocVT, CCValAssign::LocInfo LocInfo,
55 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
56static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
57 MVT LocVT, CCValAssign::LocInfo LocInfo,
58 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
59static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
60 MVT LocVT, CCValAssign::LocInfo LocInfo,
61 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
62static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
63 MVT LocVT, CCValAssign::LocInfo LocInfo,
64 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
65static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
66 MVT LocVT, CCValAssign::LocInfo LocInfo,
67 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
68static bool CC_X86_64(unsigned ValNo, MVT ValVT,
69 MVT LocVT, CCValAssign::LocInfo LocInfo,
70 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
71static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
72 MVT LocVT, CCValAssign::LocInfo LocInfo,
73 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
74static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
75 MVT LocVT, CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
77static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
78 MVT LocVT, CCValAssign::LocInfo LocInfo,
79 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
80static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
81 MVT LocVT, CCValAssign::LocInfo LocInfo,
82 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
83static bool CC_X86_64_Preserve_None(unsigned ValNo, MVT ValVT,
84 MVT LocVT, CCValAssign::LocInfo LocInfo,
85 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
86static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
87 MVT LocVT, CCValAssign::LocInfo LocInfo,
88 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
89static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
90 MVT LocVT, CCValAssign::LocInfo LocInfo,
91 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
92static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT,
93 MVT LocVT, CCValAssign::LocInfo LocInfo,
94 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
95static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
96 MVT LocVT, CCValAssign::LocInfo LocInfo,
97 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
98static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
99 MVT LocVT, CCValAssign::LocInfo LocInfo,
100 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
101static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
102 MVT LocVT, CCValAssign::LocInfo LocInfo,
103 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
104static bool CC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
105 MVT LocVT, CCValAssign::LocInfo LocInfo,
106 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
107static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
108 MVT LocVT, CCValAssign::LocInfo LocInfo,
109 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
110static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
111 MVT LocVT, CCValAssign::LocInfo LocInfo,
112 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
113bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
114 MVT LocVT, CCValAssign::LocInfo LocInfo,
115 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
116static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
117 MVT LocVT, CCValAssign::LocInfo LocInfo,
118 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
119static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
120 MVT LocVT, CCValAssign::LocInfo LocInfo,
121 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
122static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
123 MVT LocVT, CCValAssign::LocInfo LocInfo,
124 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
125static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
126 MVT LocVT, CCValAssign::LocInfo LocInfo,
127 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
128static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
129 MVT LocVT, CCValAssign::LocInfo LocInfo,
130 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
131static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
132 MVT LocVT, CCValAssign::LocInfo LocInfo,
133 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
134static bool RetCC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
135 MVT LocVT, CCValAssign::LocInfo LocInfo,
136 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
137static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
138 MVT LocVT, CCValAssign::LocInfo LocInfo,
139 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
140static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
141 MVT LocVT, CCValAssign::LocInfo LocInfo,
142 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
143static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
144 MVT LocVT, CCValAssign::LocInfo LocInfo,
145 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
146static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
147 MVT LocVT, CCValAssign::LocInfo LocInfo,
148 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
149static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
150 MVT LocVT, CCValAssign::LocInfo LocInfo,
151 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
152static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
153 MVT LocVT, CCValAssign::LocInfo LocInfo,
154 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
155static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
156 MVT LocVT, CCValAssign::LocInfo LocInfo,
157 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
158static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
159 MVT LocVT, CCValAssign::LocInfo LocInfo,
160 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
161static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
162 MVT LocVT, CCValAssign::LocInfo LocInfo,
163 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
164static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
165 MVT LocVT, CCValAssign::LocInfo LocInfo,
166 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
167static bool RetCC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
168 MVT LocVT, CCValAssign::LocInfo LocInfo,
169 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
170
171
172static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
173 MVT LocVT, CCValAssign::LocInfo LocInfo,
174 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
175
176 if (LocVT == MVT::i32) {
177 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
178 static const MCPhysReg RegList1[] = {
179 X86::ECX, X86::EDX, X86::R8D, X86::R9D
180 };
181 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
182 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
183 return false;
184 }
185 }
186 }
187
188 if (LocVT == MVT::i64) {
189 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
190 static const MCPhysReg RegList2[] = {
191 X86::RCX, X86::RDX, X86::R8, X86::R9
192 };
193 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
194 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
195 return false;
196 }
197 }
198 }
199
200 if (LocVT == MVT::i32) {
201 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
202 static const MCPhysReg RegList3[] = {
203 X86::EDI, X86::ESI, X86::EDX, X86::ECX
204 };
205 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
206 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
207 return false;
208 }
209 }
210 }
211
212 if (LocVT == MVT::i64) {
213 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
214 static const MCPhysReg RegList4[] = {
215 X86::RDI, X86::RSI, X86::RDX, X86::RCX
216 };
217 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
218 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
219 return false;
220 }
221 }
222 }
223
224 if (LocVT == MVT::i32) {
225 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(4));
226 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
227 return false;
228 }
229
230 if (LocVT == MVT::f32 ||
231 LocVT == MVT::f64 ||
232 LocVT == MVT::v4i32 ||
233 LocVT == MVT::v2i64 ||
234 LocVT == MVT::v4f32 ||
235 LocVT == MVT::v2f64) {
236 static const MCPhysReg RegList6[] = {
237 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
238 };
239 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
240 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
241 return false;
242 }
243 }
244
245 if (LocVT == MVT::v8f32 ||
246 LocVT == MVT::v4f64 ||
247 LocVT == MVT::v8i32 ||
248 LocVT == MVT::v4i64) {
249 static const MCPhysReg RegList7[] = {
250 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
251 };
252 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
253 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
254 return false;
255 }
256 }
257
258 if (LocVT == MVT::v16f32 ||
259 LocVT == MVT::v8f64 ||
260 LocVT == MVT::v16i32 ||
261 LocVT == MVT::v8i64) {
262 static const MCPhysReg RegList8[] = {
263 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
264 };
265 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
266 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
267 return false;
268 }
269 }
270
271 if (LocVT == MVT::v16i1 ||
272 LocVT == MVT::v8i1) {
273 if (MCRegister Reg = State.AllocateReg(Reg: X86::K1)) {
274 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
275 return false;
276 }
277 }
278
279 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
280 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
281 return false;
282 }
283
284 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
285 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
286 return false;
287 }
288
289 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
290 return false;
291
292 return true; // CC didn't match.
293}
294
295
296bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
297 MVT LocVT, CCValAssign::LocInfo LocInfo,
298 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
299
300 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
301 if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
302 return false;
303 }
304
305 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
306 if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
307 return false;
308 }
309
310 if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
311 return false;
312
313 return true; // CC didn't match.
314}
315
316
317static bool CC_X86_32(unsigned ValNo, MVT ValVT,
318 MVT LocVT, CCValAssign::LocInfo LocInfo,
319 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
320
321 if (State.getCallingConv() == CallingConv::X86_INTR) {
322 if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
323 return false;
324 }
325
326 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetMCU()) {
327 if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
328 return false;
329 }
330
331 if (State.getCallingConv() == CallingConv::X86_FastCall) {
332 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
333 return false;
334 }
335
336 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
337 if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
338 return false;
339 }
340
341 if (State.getCallingConv() == CallingConv::X86_ThisCall) {
342 if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
343 return false;
344 }
345
346 if (State.getCallingConv() == CallingConv::CFGuard_Check) {
347 if (!CC_X86_Win32_CFGuard_Check(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
348 return false;
349 }
350
351 if (State.getCallingConv() == CallingConv::Fast) {
352 if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
353 return false;
354 }
355
356 if (State.getCallingConv() == CallingConv::Tail) {
357 if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
358 return false;
359 }
360
361 if (State.getCallingConv() == CallingConv::GHC) {
362 if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
363 return false;
364 }
365
366 if (State.getCallingConv() == CallingConv::HiPE) {
367 if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
368 return false;
369 }
370
371 if (State.getCallingConv() == CallingConv::X86_RegCall) {
372 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin32()) {
373 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
374 if (!CC_X86_32_RegCallv4_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
375 return false;
376 }
377 }
378 }
379
380 if (State.getCallingConv() == CallingConv::X86_RegCall) {
381 if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
382 return false;
383 }
384
385 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
386 return false;
387
388 return true; // CC didn't match.
389}
390
391
392static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
393 MVT LocVT, CCValAssign::LocInfo LocInfo,
394 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
395
396 if (LocVT == MVT::i1 ||
397 LocVT == MVT::i8 ||
398 LocVT == MVT::i16 ||
399 LocVT == MVT::v1i1) {
400 LocVT = MVT::i32;
401 if (ArgFlags.isSExt())
402 LocInfo = CCValAssign::SExt;
403 else if (ArgFlags.isZExt())
404 LocInfo = CCValAssign::ZExt;
405 else
406 LocInfo = CCValAssign::AExt;
407 }
408
409 if (ArgFlags.isNest()) {
410 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
411 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
412 return false;
413 }
414 }
415
416 if (LocVT == MVT::i32) {
417 if (ArgFlags.isInConsecutiveRegs()) {
418 if (CC_X86_32_I128_FP128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
419 return false;
420 }
421 }
422
423 if (State.getCallingConv() == CallingConv::SwiftTail) {
424 if (ArgFlags.isSwiftSelf()) {
425 if (LocVT == MVT::i32) {
426 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
427 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
428 return false;
429 }
430 }
431 }
432 }
433
434 if (!State.isVarArg()) {
435 if (ArgFlags.isInReg()) {
436 if (LocVT == MVT::i32) {
437 static const MCPhysReg RegList1[] = {
438 X86::EAX, X86::EDX, X86::ECX
439 };
440 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
441 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
442 return false;
443 }
444 }
445 }
446 }
447
448 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
449 return false;
450
451 return true; // CC didn't match.
452}
453
454
455static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
456 MVT LocVT, CCValAssign::LocInfo LocInfo,
457 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
458
459 if (ArgFlags.isByVal()) {
460 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
461 return false;
462 }
463
464 if (ArgFlags.isPreallocated()) {
465 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
466 return false;
467 }
468
469 if (!State.isVarArg()) {
470 if (ArgFlags.isInReg()) {
471 if (LocVT == MVT::f32 ||
472 LocVT == MVT::f64) {
473 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
474 static const MCPhysReg RegList1[] = {
475 X86::XMM0, X86::XMM1, X86::XMM2
476 };
477 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
478 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
479 return false;
480 }
481 }
482 }
483 }
484 }
485
486 if (!State.isVarArg()) {
487 if (ArgFlags.isInReg()) {
488 if (LocVT == MVT::f16) {
489 static const MCPhysReg RegList2[] = {
490 X86::XMM0, X86::XMM1, X86::XMM2
491 };
492 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
493 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
494 return false;
495 }
496 }
497 }
498 }
499
500 if (LocVT == MVT::f16) {
501 int64_t Offset3 = State.AllocateStack(Size: 4, Alignment: Align(4));
502 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
503 return false;
504 }
505
506 if (LocVT == MVT::i32 ||
507 LocVT == MVT::f32) {
508 int64_t Offset4 = State.AllocateStack(Size: 4, Alignment: Align(4));
509 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
510 return false;
511 }
512
513 if (LocVT == MVT::f64) {
514 int64_t Offset5 = State.AllocateStack(Size: 8, Alignment: Align(4));
515 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
516 return false;
517 }
518
519 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetDarwin()) {
520 if (LocVT == MVT::f80) {
521 int64_t Offset6 = State.AllocateStack(
522 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())), Alignment: Align(4));
523 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
524 return false;
525 }
526 }
527
528 if (LocVT == MVT::f80) {
529 int64_t Offset7 = State.AllocateStack(
530 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
531 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
532 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
533 return false;
534 }
535
536 if (LocVT == MVT::v2i1) {
537 LocVT = MVT::v2i64;
538 if (ArgFlags.isSExt())
539 LocInfo = CCValAssign::SExt;
540 else if (ArgFlags.isZExt())
541 LocInfo = CCValAssign::ZExt;
542 else
543 LocInfo = CCValAssign::AExt;
544 }
545
546 if (LocVT == MVT::v4i1) {
547 LocVT = MVT::v4i32;
548 if (ArgFlags.isSExt())
549 LocInfo = CCValAssign::SExt;
550 else if (ArgFlags.isZExt())
551 LocInfo = CCValAssign::ZExt;
552 else
553 LocInfo = CCValAssign::AExt;
554 }
555
556 if (LocVT == MVT::v8i1) {
557 LocVT = MVT::v8i16;
558 if (ArgFlags.isSExt())
559 LocInfo = CCValAssign::SExt;
560 else if (ArgFlags.isZExt())
561 LocInfo = CCValAssign::ZExt;
562 else
563 LocInfo = CCValAssign::AExt;
564 }
565
566 if (LocVT == MVT::v16i1) {
567 LocVT = MVT::v16i8;
568 if (ArgFlags.isSExt())
569 LocInfo = CCValAssign::SExt;
570 else if (ArgFlags.isZExt())
571 LocInfo = CCValAssign::ZExt;
572 else
573 LocInfo = CCValAssign::AExt;
574 }
575
576 if (LocVT == MVT::v32i1) {
577 LocVT = MVT::v32i8;
578 if (ArgFlags.isSExt())
579 LocInfo = CCValAssign::SExt;
580 else if (ArgFlags.isZExt())
581 LocInfo = CCValAssign::ZExt;
582 else
583 LocInfo = CCValAssign::AExt;
584 }
585
586 if (LocVT == MVT::v64i1) {
587 LocVT = MVT::v64i8;
588 if (ArgFlags.isSExt())
589 LocInfo = CCValAssign::SExt;
590 else if (ArgFlags.isZExt())
591 LocInfo = CCValAssign::ZExt;
592 else
593 LocInfo = CCValAssign::AExt;
594 }
595
596 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetDarwin()) {
597 if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
598 return false;
599 }
600
601 if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
602 return false;
603
604 return true; // CC didn't match.
605}
606
607
608static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
609 MVT LocVT, CCValAssign::LocInfo LocInfo,
610 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
611
612 if (ArgFlags.isByVal()) {
613 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
614 return false;
615 }
616
617 if (LocVT == MVT::i1 ||
618 LocVT == MVT::i8 ||
619 LocVT == MVT::i16 ||
620 LocVT == MVT::v1i1) {
621 LocVT = MVT::i32;
622 if (ArgFlags.isSExt())
623 LocInfo = CCValAssign::SExt;
624 else if (ArgFlags.isZExt())
625 LocInfo = CCValAssign::ZExt;
626 else
627 LocInfo = CCValAssign::AExt;
628 }
629
630 if (ArgFlags.isNest()) {
631 if (MCRegister Reg = State.AllocateReg(Reg: X86::EAX)) {
632 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
633 return false;
634 }
635 }
636
637 if (LocVT == MVT::i32) {
638 static const MCPhysReg RegList1[] = {
639 X86::ECX, X86::EDX
640 };
641 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
642 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
643 return false;
644 }
645 }
646
647 if (!State.isVarArg()) {
648 if (LocVT == MVT::f32 ||
649 LocVT == MVT::f64) {
650 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
651 static const MCPhysReg RegList2[] = {
652 X86::XMM0, X86::XMM1, X86::XMM2
653 };
654 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
655 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
656 return false;
657 }
658 }
659 }
660 }
661
662 if (LocVT == MVT::f64) {
663 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(8));
664 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
665 return false;
666 }
667
668 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
669 return false;
670
671 return true; // CC didn't match.
672}
673
674
675static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
676 MVT LocVT, CCValAssign::LocInfo LocInfo,
677 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
678
679 if (LocVT == MVT::i1) {
680 LocVT = MVT::i8;
681 if (ArgFlags.isSExt())
682 LocInfo = CCValAssign::SExt;
683 else if (ArgFlags.isZExt())
684 LocInfo = CCValAssign::ZExt;
685 else
686 LocInfo = CCValAssign::AExt;
687 }
688
689 if (ArgFlags.isNest()) {
690 if (MCRegister Reg = State.AllocateReg(Reg: X86::EAX)) {
691 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
692 return false;
693 }
694 }
695
696 if (ArgFlags.isInReg()) {
697 if (LocVT == MVT::i8) {
698 static const MCPhysReg RegList1[] = {
699 X86::CL, X86::DL
700 };
701 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
702 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
703 return false;
704 }
705 }
706 }
707
708 if (ArgFlags.isInReg()) {
709 if (LocVT == MVT::i16) {
710 static const MCPhysReg RegList2[] = {
711 X86::CX, X86::DX
712 };
713 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
714 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
715 return false;
716 }
717 }
718 }
719
720 if (ArgFlags.isInReg()) {
721 if (LocVT == MVT::i32) {
722 static const MCPhysReg RegList3[] = {
723 X86::ECX, X86::EDX
724 };
725 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
726 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
727 return false;
728 }
729 }
730 }
731
732 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
733 return false;
734
735 return true; // CC didn't match.
736}
737
738
739static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
740 MVT LocVT, CCValAssign::LocInfo LocInfo,
741 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
742
743 if (LocVT == MVT::i8 ||
744 LocVT == MVT::i16) {
745 LocVT = MVT::i32;
746 if (ArgFlags.isSExt())
747 LocInfo = CCValAssign::SExt;
748 else if (ArgFlags.isZExt())
749 LocInfo = CCValAssign::ZExt;
750 else
751 LocInfo = CCValAssign::AExt;
752 }
753
754 if (LocVT == MVT::i32) {
755 static const MCPhysReg RegList1[] = {
756 X86::EBX, X86::EBP, X86::EDI, X86::ESI
757 };
758 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
759 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
760 return false;
761 }
762 }
763
764 return true; // CC didn't match.
765}
766
767
768static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
769 MVT LocVT, CCValAssign::LocInfo LocInfo,
770 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
771
772 if (LocVT == MVT::i8 ||
773 LocVT == MVT::i16) {
774 LocVT = MVT::i32;
775 if (ArgFlags.isSExt())
776 LocInfo = CCValAssign::SExt;
777 else if (ArgFlags.isZExt())
778 LocInfo = CCValAssign::ZExt;
779 else
780 LocInfo = CCValAssign::AExt;
781 }
782
783 if (LocVT == MVT::i32) {
784 static const MCPhysReg RegList1[] = {
785 X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
786 };
787 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
788 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
789 return false;
790 }
791 }
792
793 if (LocVT == MVT::i32 ||
794 LocVT == MVT::f32) {
795 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
796 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
797 return false;
798 }
799
800 return true; // CC didn't match.
801}
802
803
804static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
805 MVT LocVT, CCValAssign::LocInfo LocInfo,
806 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
807
808 if (ArgFlags.isByVal()) {
809 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
810 return false;
811 }
812
813 if (LocVT == MVT::i1 ||
814 LocVT == MVT::i8 ||
815 LocVT == MVT::i16 ||
816 LocVT == MVT::v1i1) {
817 LocVT = MVT::i32;
818 if (ArgFlags.isSExt())
819 LocInfo = CCValAssign::SExt;
820 else if (ArgFlags.isZExt())
821 LocInfo = CCValAssign::ZExt;
822 else
823 LocInfo = CCValAssign::AExt;
824 }
825
826 if (!State.isVarArg()) {
827 if (LocVT == MVT::i32) {
828 if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
829 return false;
830 }
831 }
832
833 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
834 return false;
835
836 return true; // CC didn't match.
837}
838
839
840static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
841 MVT LocVT, CCValAssign::LocInfo LocInfo,
842 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
843
844 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
845 if (ArgFlags.isByVal()) {
846 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
847 return false;
848 }
849 }
850
851 if (ArgFlags.isByVal()) {
852 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
853 return false;
854 }
855
856 if (LocVT == MVT::i1 ||
857 LocVT == MVT::i8 ||
858 LocVT == MVT::i16 ||
859 LocVT == MVT::v1i1) {
860 LocVT = MVT::i32;
861 if (ArgFlags.isSExt())
862 LocInfo = CCValAssign::SExt;
863 else if (ArgFlags.isZExt())
864 LocInfo = CCValAssign::ZExt;
865 else
866 LocInfo = CCValAssign::AExt;
867 }
868
869 if (LocVT == MVT::v8i1 ||
870 LocVT == MVT::v16i1 ||
871 LocVT == MVT::v32i1) {
872 LocVT = MVT::i32;
873 if (ArgFlags.isSExt())
874 LocInfo = CCValAssign::SExt;
875 else if (ArgFlags.isZExt())
876 LocInfo = CCValAssign::ZExt;
877 else
878 LocInfo = CCValAssign::AExt;
879 }
880
881 if (LocVT == MVT::i32) {
882 static const MCPhysReg RegList1[] = {
883 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
884 };
885 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
886 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
887 return false;
888 }
889 }
890
891 if (LocVT == MVT::i64) {
892 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
893 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
894 return false;
895 }
896 }
897
898 if (LocVT == MVT::v64i1) {
899 LocVT = MVT::i64;
900 if (ArgFlags.isSExt())
901 LocInfo = CCValAssign::SExt;
902 else if (ArgFlags.isZExt())
903 LocInfo = CCValAssign::ZExt;
904 else
905 LocInfo = CCValAssign::AExt;
906 }
907
908 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
909 if (LocVT == MVT::i64) {
910 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
911 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
912 return false;
913 }
914 }
915 }
916
917 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
918 if (LocVT == MVT::i64) {
919 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
920 return false;
921 }
922 }
923
924 if (LocVT == MVT::f32 ||
925 LocVT == MVT::f64 ||
926 LocVT == MVT::f128) {
927 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
928 static const MCPhysReg RegList2[] = {
929 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
930 };
931 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
932 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
933 return false;
934 }
935 }
936 }
937
938 if (LocVT == MVT::f80) {
939 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
940 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
941 return false;
942 }
943 }
944
945 if (LocVT == MVT::v16i8 ||
946 LocVT == MVT::v8i16 ||
947 LocVT == MVT::v4i32 ||
948 LocVT == MVT::v2i64 ||
949 LocVT == MVT::v4f32 ||
950 LocVT == MVT::v2f64) {
951 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
952 static const MCPhysReg RegList3[] = {
953 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
954 };
955 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
956 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
957 return false;
958 }
959 }
960 }
961
962 if (LocVT == MVT::v32i8 ||
963 LocVT == MVT::v16i16 ||
964 LocVT == MVT::v8i32 ||
965 LocVT == MVT::v4i64 ||
966 LocVT == MVT::v8f32 ||
967 LocVT == MVT::v4f64) {
968 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
969 static const MCPhysReg RegList4[] = {
970 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
971 };
972 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
973 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
974 return false;
975 }
976 }
977 }
978
979 if (LocVT == MVT::v64i8 ||
980 LocVT == MVT::v32i16 ||
981 LocVT == MVT::v16i32 ||
982 LocVT == MVT::v8i64 ||
983 LocVT == MVT::v16f32 ||
984 LocVT == MVT::v8f64) {
985 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
986 static const MCPhysReg RegList5[] = {
987 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
988 };
989 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
990 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
991 return false;
992 }
993 }
994 }
995
996 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
997 if (LocVT == MVT::i32 ||
998 LocVT == MVT::i64 ||
999 LocVT == MVT::f32 ||
1000 LocVT == MVT::f64) {
1001 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
1002 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1003 return false;
1004 }
1005 }
1006
1007 if (LocVT == MVT::i32 ||
1008 LocVT == MVT::f32) {
1009 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(4));
1010 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
1011 return false;
1012 }
1013
1014 if (LocVT == MVT::i64 ||
1015 LocVT == MVT::f64) {
1016 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(4));
1017 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1018 return false;
1019 }
1020
1021 if (LocVT == MVT::f80 ||
1022 LocVT == MVT::f128) {
1023 int64_t Offset9 = State.AllocateStack(
1024 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1025 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1026 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1027 return false;
1028 }
1029
1030 if (LocVT == MVT::v16i8 ||
1031 LocVT == MVT::v8i16 ||
1032 LocVT == MVT::v4i32 ||
1033 LocVT == MVT::v2i64 ||
1034 LocVT == MVT::v4f32 ||
1035 LocVT == MVT::v2f64) {
1036 int64_t Offset10 = State.AllocateStack(Size: 16, Alignment: Align(16));
1037 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1038 return false;
1039 }
1040
1041 if (LocVT == MVT::v32i8 ||
1042 LocVT == MVT::v16i16 ||
1043 LocVT == MVT::v8i32 ||
1044 LocVT == MVT::v4i64 ||
1045 LocVT == MVT::v8f32 ||
1046 LocVT == MVT::v4f64) {
1047 int64_t Offset11 = State.AllocateStack(Size: 32, Alignment: Align(32));
1048 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
1049 return false;
1050 }
1051
1052 if (LocVT == MVT::v64i8 ||
1053 LocVT == MVT::v32i16 ||
1054 LocVT == MVT::v16i32 ||
1055 LocVT == MVT::v8i64 ||
1056 LocVT == MVT::v16f32 ||
1057 LocVT == MVT::v8f64) {
1058 int64_t Offset12 = State.AllocateStack(Size: 64, Alignment: Align(64));
1059 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
1060 return false;
1061 }
1062
1063 return true; // CC didn't match.
1064}
1065
1066
1067static bool CC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
1068 MVT LocVT, CCValAssign::LocInfo LocInfo,
1069 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1070
1071 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
1072 if (ArgFlags.isByVal()) {
1073 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1074 return false;
1075 }
1076 }
1077
1078 if (ArgFlags.isByVal()) {
1079 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
1080 return false;
1081 }
1082
1083 if (LocVT == MVT::i1 ||
1084 LocVT == MVT::i8 ||
1085 LocVT == MVT::i16 ||
1086 LocVT == MVT::v1i1) {
1087 LocVT = MVT::i32;
1088 if (ArgFlags.isSExt())
1089 LocInfo = CCValAssign::SExt;
1090 else if (ArgFlags.isZExt())
1091 LocInfo = CCValAssign::ZExt;
1092 else
1093 LocInfo = CCValAssign::AExt;
1094 }
1095
1096 if (LocVT == MVT::v8i1 ||
1097 LocVT == MVT::v16i1 ||
1098 LocVT == MVT::v32i1) {
1099 LocVT = MVT::i32;
1100 if (ArgFlags.isSExt())
1101 LocInfo = CCValAssign::SExt;
1102 else if (ArgFlags.isZExt())
1103 LocInfo = CCValAssign::ZExt;
1104 else
1105 LocInfo = CCValAssign::AExt;
1106 }
1107
1108 if (LocVT == MVT::i32) {
1109 static const MCPhysReg RegList1[] = {
1110 X86::ECX, X86::EDX, X86::EDI, X86::ESI
1111 };
1112 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1113 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1114 return false;
1115 }
1116 }
1117
1118 if (LocVT == MVT::i64) {
1119 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1120 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1121 return false;
1122 }
1123 }
1124
1125 if (LocVT == MVT::v64i1) {
1126 LocVT = MVT::i64;
1127 if (ArgFlags.isSExt())
1128 LocInfo = CCValAssign::SExt;
1129 else if (ArgFlags.isZExt())
1130 LocInfo = CCValAssign::ZExt;
1131 else
1132 LocInfo = CCValAssign::AExt;
1133 }
1134
1135 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
1136 if (LocVT == MVT::i64) {
1137 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1138 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1139 return false;
1140 }
1141 }
1142 }
1143
1144 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
1145 if (LocVT == MVT::i64) {
1146 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1147 return false;
1148 }
1149 }
1150
1151 if (LocVT == MVT::f32 ||
1152 LocVT == MVT::f64 ||
1153 LocVT == MVT::f128) {
1154 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
1155 static const MCPhysReg RegList2[] = {
1156 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1157 };
1158 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1159 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1160 return false;
1161 }
1162 }
1163 }
1164
1165 if (LocVT == MVT::f80) {
1166 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
1167 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1168 return false;
1169 }
1170 }
1171
1172 if (LocVT == MVT::v16i8 ||
1173 LocVT == MVT::v8i16 ||
1174 LocVT == MVT::v4i32 ||
1175 LocVT == MVT::v2i64 ||
1176 LocVT == MVT::v4f32 ||
1177 LocVT == MVT::v2f64) {
1178 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
1179 static const MCPhysReg RegList3[] = {
1180 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1181 };
1182 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1183 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1184 return false;
1185 }
1186 }
1187 }
1188
1189 if (LocVT == MVT::v32i8 ||
1190 LocVT == MVT::v16i16 ||
1191 LocVT == MVT::v8i32 ||
1192 LocVT == MVT::v4i64 ||
1193 LocVT == MVT::v8f32 ||
1194 LocVT == MVT::v4f64) {
1195 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1196 static const MCPhysReg RegList4[] = {
1197 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1198 };
1199 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1200 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1201 return false;
1202 }
1203 }
1204 }
1205
1206 if (LocVT == MVT::v64i8 ||
1207 LocVT == MVT::v32i16 ||
1208 LocVT == MVT::v16i32 ||
1209 LocVT == MVT::v8i64 ||
1210 LocVT == MVT::v16f32 ||
1211 LocVT == MVT::v8f64) {
1212 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
1213 static const MCPhysReg RegList5[] = {
1214 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1215 };
1216 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
1217 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1218 return false;
1219 }
1220 }
1221 }
1222
1223 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
1224 if (LocVT == MVT::i32 ||
1225 LocVT == MVT::i64 ||
1226 LocVT == MVT::f32 ||
1227 LocVT == MVT::f64) {
1228 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
1229 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1230 return false;
1231 }
1232 }
1233
1234 if (LocVT == MVT::i32 ||
1235 LocVT == MVT::f32) {
1236 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(4));
1237 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
1238 return false;
1239 }
1240
1241 if (LocVT == MVT::i64 ||
1242 LocVT == MVT::f64) {
1243 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(4));
1244 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1245 return false;
1246 }
1247
1248 if (LocVT == MVT::f80 ||
1249 LocVT == MVT::f128) {
1250 int64_t Offset9 = State.AllocateStack(
1251 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1252 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1253 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1254 return false;
1255 }
1256
1257 if (LocVT == MVT::v16i8 ||
1258 LocVT == MVT::v8i16 ||
1259 LocVT == MVT::v4i32 ||
1260 LocVT == MVT::v2i64 ||
1261 LocVT == MVT::v4f32 ||
1262 LocVT == MVT::v2f64) {
1263 int64_t Offset10 = State.AllocateStack(Size: 16, Alignment: Align(16));
1264 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1265 return false;
1266 }
1267
1268 if (LocVT == MVT::v32i8 ||
1269 LocVT == MVT::v16i16 ||
1270 LocVT == MVT::v8i32 ||
1271 LocVT == MVT::v4i64 ||
1272 LocVT == MVT::v8f32 ||
1273 LocVT == MVT::v4f64) {
1274 int64_t Offset11 = State.AllocateStack(Size: 32, Alignment: Align(32));
1275 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
1276 return false;
1277 }
1278
1279 if (LocVT == MVT::v64i8 ||
1280 LocVT == MVT::v32i16 ||
1281 LocVT == MVT::v16i32 ||
1282 LocVT == MVT::v8i64 ||
1283 LocVT == MVT::v16f32 ||
1284 LocVT == MVT::v8f64) {
1285 int64_t Offset12 = State.AllocateStack(Size: 64, Alignment: Align(64));
1286 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
1287 return false;
1288 }
1289
1290 return true; // CC didn't match.
1291}
1292
1293
1294static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
1295 MVT LocVT, CCValAssign::LocInfo LocInfo,
1296 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1297
1298 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetCygMing()) {
1299 if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1300 return false;
1301 }
1302
1303 if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1304 return false;
1305
1306 return true; // CC didn't match.
1307}
1308
1309
1310static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
1311 MVT LocVT, CCValAssign::LocInfo LocInfo,
1312 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1313
1314 if (LocVT == MVT::i32) {
1315 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
1316 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1317 return false;
1318 }
1319 }
1320
1321 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1322 return false;
1323
1324 return true; // CC didn't match.
1325}
1326
1327
1328static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
1329 MVT LocVT, CCValAssign::LocInfo LocInfo,
1330 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1331
1332 if (LocVT == MVT::i1 ||
1333 LocVT == MVT::i8 ||
1334 LocVT == MVT::i16 ||
1335 LocVT == MVT::v1i1) {
1336 LocVT = MVT::i32;
1337 if (ArgFlags.isSExt())
1338 LocInfo = CCValAssign::SExt;
1339 else if (ArgFlags.isZExt())
1340 LocInfo = CCValAssign::ZExt;
1341 else
1342 LocInfo = CCValAssign::AExt;
1343 }
1344
1345 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1346 return false;
1347
1348 return true; // CC didn't match.
1349}
1350
1351
1352static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
1353 MVT LocVT, CCValAssign::LocInfo LocInfo,
1354 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1355
1356 if (LocVT == MVT::i1 ||
1357 LocVT == MVT::i8 ||
1358 LocVT == MVT::i16 ||
1359 LocVT == MVT::v1i1) {
1360 LocVT = MVT::i32;
1361 if (ArgFlags.isSExt())
1362 LocInfo = CCValAssign::SExt;
1363 else if (ArgFlags.isZExt())
1364 LocInfo = CCValAssign::ZExt;
1365 else
1366 LocInfo = CCValAssign::AExt;
1367 }
1368
1369 if (ArgFlags.isSRet()) {
1370 int64_t Offset1 = State.AllocateStack(Size: 4, Alignment: Align(4));
1371 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1372 return false;
1373 }
1374
1375 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1376 return false;
1377
1378 return true; // CC didn't match.
1379}
1380
1381
1382static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
1383 MVT LocVT, CCValAssign::LocInfo LocInfo,
1384 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1385
1386 if (LocVT == MVT::v16i8 ||
1387 LocVT == MVT::v8i16 ||
1388 LocVT == MVT::v4i32 ||
1389 LocVT == MVT::v2i64 ||
1390 LocVT == MVT::v8f16 ||
1391 LocVT == MVT::v8bf16 ||
1392 LocVT == MVT::v4f32 ||
1393 LocVT == MVT::v2f64) {
1394 int64_t Offset1 = State.AllocateStack(Size: 16, Alignment: Align(16));
1395 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1396 return false;
1397 }
1398
1399 if (LocVT == MVT::v32i8 ||
1400 LocVT == MVT::v16i16 ||
1401 LocVT == MVT::v8i32 ||
1402 LocVT == MVT::v4i64 ||
1403 LocVT == MVT::v16f16 ||
1404 LocVT == MVT::v16bf16 ||
1405 LocVT == MVT::v8f32 ||
1406 LocVT == MVT::v4f64) {
1407 int64_t Offset2 = State.AllocateStack(Size: 32, Alignment: Align(32));
1408 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1409 return false;
1410 }
1411
1412 if (LocVT == MVT::v64i8 ||
1413 LocVT == MVT::v32i16 ||
1414 LocVT == MVT::v16i32 ||
1415 LocVT == MVT::v8i64 ||
1416 LocVT == MVT::v32f16 ||
1417 LocVT == MVT::v32bf16 ||
1418 LocVT == MVT::v16f32 ||
1419 LocVT == MVT::v8f64) {
1420 int64_t Offset3 = State.AllocateStack(Size: 64, Alignment: Align(64));
1421 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1422 return false;
1423 }
1424
1425 return true; // CC didn't match.
1426}
1427
1428
1429static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
1430 MVT LocVT, CCValAssign::LocInfo LocInfo,
1431 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1432
1433 if (!State.isVarArg()) {
1434 if (LocVT == MVT::v16i8 ||
1435 LocVT == MVT::v8i16 ||
1436 LocVT == MVT::v4i32 ||
1437 LocVT == MVT::v2i64 ||
1438 LocVT == MVT::v8f16 ||
1439 LocVT == MVT::v8bf16 ||
1440 LocVT == MVT::v4f32 ||
1441 LocVT == MVT::v2f64) {
1442 static const MCPhysReg RegList1[] = {
1443 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1444 };
1445 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1446 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1447 return false;
1448 }
1449 }
1450 }
1451
1452 if (!State.isVarArg()) {
1453 if (LocVT == MVT::v32i8 ||
1454 LocVT == MVT::v16i16 ||
1455 LocVT == MVT::v8i32 ||
1456 LocVT == MVT::v4i64 ||
1457 LocVT == MVT::v16f16 ||
1458 LocVT == MVT::v16bf16 ||
1459 LocVT == MVT::v8f32 ||
1460 LocVT == MVT::v4f64) {
1461 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1462 static const MCPhysReg RegList2[] = {
1463 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1464 };
1465 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1466 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1467 return false;
1468 }
1469 }
1470 }
1471 }
1472
1473 if (!State.isVarArg()) {
1474 if (LocVT == MVT::v64i8 ||
1475 LocVT == MVT::v32i16 ||
1476 LocVT == MVT::v16i32 ||
1477 LocVT == MVT::v8i64 ||
1478 LocVT == MVT::v32f16 ||
1479 LocVT == MVT::v32bf16 ||
1480 LocVT == MVT::v16f32 ||
1481 LocVT == MVT::v8f64) {
1482 static const MCPhysReg RegList3[] = {
1483 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1484 };
1485 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1486 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1487 return false;
1488 }
1489 }
1490 }
1491
1492 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1493 return false;
1494
1495 return true; // CC didn't match.
1496}
1497
1498
1499static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
1500 MVT LocVT, CCValAssign::LocInfo LocInfo,
1501 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1502
1503 if (!State.isVarArg()) {
1504 if (LocVT == MVT::v16i8 ||
1505 LocVT == MVT::v8i16 ||
1506 LocVT == MVT::v4i32 ||
1507 LocVT == MVT::v2i64 ||
1508 LocVT == MVT::v8f16 ||
1509 LocVT == MVT::v8bf16 ||
1510 LocVT == MVT::v4f32 ||
1511 LocVT == MVT::v2f64) {
1512 static const MCPhysReg RegList1[] = {
1513 X86::XMM0, X86::XMM1, X86::XMM2
1514 };
1515 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1516 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1517 return false;
1518 }
1519 }
1520 }
1521
1522 if (!State.isVarArg()) {
1523 if (LocVT == MVT::v32i8 ||
1524 LocVT == MVT::v16i16 ||
1525 LocVT == MVT::v8i32 ||
1526 LocVT == MVT::v4i64 ||
1527 LocVT == MVT::v16f16 ||
1528 LocVT == MVT::v16bf16 ||
1529 LocVT == MVT::v8f32 ||
1530 LocVT == MVT::v4f64) {
1531 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1532 static const MCPhysReg RegList2[] = {
1533 X86::YMM0, X86::YMM1, X86::YMM2
1534 };
1535 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1536 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1537 return false;
1538 }
1539 }
1540 }
1541 }
1542
1543 if (!State.isVarArg()) {
1544 if (LocVT == MVT::v64i8 ||
1545 LocVT == MVT::v32i16 ||
1546 LocVT == MVT::v16i32 ||
1547 LocVT == MVT::v8i64 ||
1548 LocVT == MVT::v32f16 ||
1549 LocVT == MVT::v32bf16 ||
1550 LocVT == MVT::v16f32 ||
1551 LocVT == MVT::v8f64) {
1552 static const MCPhysReg RegList3[] = {
1553 X86::ZMM0, X86::ZMM1, X86::ZMM2
1554 };
1555 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1556 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1557 return false;
1558 }
1559 }
1560 }
1561
1562 if (State.isVarArg() && State.getMachineFunction().getSubtarget().getTargetTriple().isWindowsMSVCEnvironment()) {
1563 if (!CC_X86_Win32_Vector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1564 return false;
1565 }
1566
1567 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1568 return false;
1569
1570 return true; // CC didn't match.
1571}
1572
1573
1574static bool CC_X86_64(unsigned ValNo, MVT ValVT,
1575 MVT LocVT, CCValAssign::LocInfo LocInfo,
1576 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1577
1578 if (State.getCallingConv() == CallingConv::GHC) {
1579 if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1580 return false;
1581 }
1582
1583 if (State.getCallingConv() == CallingConv::HiPE) {
1584 if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1585 return false;
1586 }
1587
1588 if (State.getCallingConv() == CallingConv::AnyReg) {
1589 if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1590 return false;
1591 }
1592
1593 if (State.getCallingConv() == CallingConv::Win64) {
1594 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1595 return false;
1596 }
1597
1598 if (State.getCallingConv() == CallingConv::X86_64_SysV) {
1599 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1600 return false;
1601 }
1602
1603 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
1604 if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1605 return false;
1606 }
1607
1608 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1609 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
1610 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
1611 if (!CC_X86_Win64_RegCallv4(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1612 return false;
1613 }
1614 }
1615 }
1616
1617 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1618 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
1619 if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1620 return false;
1621 }
1622 }
1623
1624 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1625 if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1626 return false;
1627 }
1628
1629 if (State.getCallingConv() == CallingConv::PreserveNone) {
1630 if (!CC_X86_64_Preserve_None(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1631 return false;
1632 }
1633
1634 if (State.getCallingConv() == CallingConv::X86_INTR) {
1635 if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1636 return false;
1637 }
1638
1639 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
1640 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1641 return false;
1642 }
1643
1644 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetUEFI64()) {
1645 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1646 return false;
1647 }
1648
1649 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1650 return false;
1651
1652 return true; // CC didn't match.
1653}
1654
1655
1656static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
1657 MVT LocVT, CCValAssign::LocInfo LocInfo,
1658 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1659
1660 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1661 return false;
1662
1663 return true; // CC didn't match.
1664}
1665
1666
1667static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
1668 MVT LocVT, CCValAssign::LocInfo LocInfo,
1669 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1670
1671 if (ArgFlags.isByVal()) {
1672 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1673 return false;
1674 }
1675
1676 if (LocVT == MVT::i1 ||
1677 LocVT == MVT::i8 ||
1678 LocVT == MVT::i16 ||
1679 LocVT == MVT::v1i1) {
1680 LocVT = MVT::i32;
1681 if (ArgFlags.isSExt())
1682 LocInfo = CCValAssign::SExt;
1683 else if (ArgFlags.isZExt())
1684 LocInfo = CCValAssign::ZExt;
1685 else
1686 LocInfo = CCValAssign::AExt;
1687 }
1688
1689 if (ArgFlags.isNest()) {
1690 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTarget64BitILP32()) {
1691 if (MCRegister Reg = State.AllocateReg(Reg: X86::R10D)) {
1692 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1693 return false;
1694 }
1695 }
1696 }
1697
1698 if (ArgFlags.isNest()) {
1699 if (MCRegister Reg = State.AllocateReg(Reg: X86::R10)) {
1700 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1701 return false;
1702 }
1703 }
1704
1705 if (ArgFlags.isSwiftSelf()) {
1706 if (LocVT == MVT::i64) {
1707 if (MCRegister Reg = State.AllocateReg(Reg: X86::R13)) {
1708 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1709 return false;
1710 }
1711 }
1712 }
1713
1714 if (ArgFlags.isSwiftError()) {
1715 if (LocVT == MVT::i64) {
1716 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
1717 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1718 return false;
1719 }
1720 }
1721 }
1722
1723 if (ArgFlags.isSwiftAsync()) {
1724 if (LocVT == MVT::i64) {
1725 if (MCRegister Reg = State.AllocateReg(Reg: X86::R14)) {
1726 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1727 return false;
1728 }
1729 }
1730 }
1731
1732 if (State.getCallingConv() == CallingConv::Swift) {
1733 if (ArgFlags.isSRet()) {
1734 if (LocVT == MVT::i64) {
1735 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1736 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1737 return false;
1738 }
1739 }
1740 }
1741 }
1742
1743 if (State.getCallingConv() == CallingConv::SwiftTail) {
1744 if (ArgFlags.isSRet()) {
1745 if (LocVT == MVT::i64) {
1746 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1747 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1748 return false;
1749 }
1750 }
1751 }
1752 }
1753
1754 if (ArgFlags.isPointer()) {
1755 if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1756 return false;
1757 }
1758
1759 if (LocVT == MVT::i32) {
1760 static const MCPhysReg RegList1[] = {
1761 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1762 };
1763 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1764 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1765 return false;
1766 }
1767 }
1768
1769 if (LocVT == MVT::i64) {
1770 if (ArgFlags.isInConsecutiveRegs()) {
1771 if (CC_X86_64_I128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1772 return false;
1773 }
1774 }
1775
1776 if (LocVT == MVT::i64) {
1777 static const MCPhysReg RegList2[] = {
1778 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1779 };
1780 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1781 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1782 return false;
1783 }
1784 }
1785
1786 if (LocVT == MVT::v2i1) {
1787 LocVT = MVT::v2i64;
1788 if (ArgFlags.isSExt())
1789 LocInfo = CCValAssign::SExt;
1790 else if (ArgFlags.isZExt())
1791 LocInfo = CCValAssign::ZExt;
1792 else
1793 LocInfo = CCValAssign::AExt;
1794 }
1795
1796 if (LocVT == MVT::v4i1) {
1797 LocVT = MVT::v4i32;
1798 if (ArgFlags.isSExt())
1799 LocInfo = CCValAssign::SExt;
1800 else if (ArgFlags.isZExt())
1801 LocInfo = CCValAssign::ZExt;
1802 else
1803 LocInfo = CCValAssign::AExt;
1804 }
1805
1806 if (LocVT == MVT::v8i1) {
1807 LocVT = MVT::v8i16;
1808 if (ArgFlags.isSExt())
1809 LocInfo = CCValAssign::SExt;
1810 else if (ArgFlags.isZExt())
1811 LocInfo = CCValAssign::ZExt;
1812 else
1813 LocInfo = CCValAssign::AExt;
1814 }
1815
1816 if (LocVT == MVT::v16i1) {
1817 LocVT = MVT::v16i8;
1818 if (ArgFlags.isSExt())
1819 LocInfo = CCValAssign::SExt;
1820 else if (ArgFlags.isZExt())
1821 LocInfo = CCValAssign::ZExt;
1822 else
1823 LocInfo = CCValAssign::AExt;
1824 }
1825
1826 if (LocVT == MVT::v32i1) {
1827 LocVT = MVT::v32i8;
1828 if (ArgFlags.isSExt())
1829 LocInfo = CCValAssign::SExt;
1830 else if (ArgFlags.isZExt())
1831 LocInfo = CCValAssign::ZExt;
1832 else
1833 LocInfo = CCValAssign::AExt;
1834 }
1835
1836 if (LocVT == MVT::v64i1) {
1837 LocVT = MVT::v64i8;
1838 if (ArgFlags.isSExt())
1839 LocInfo = CCValAssign::SExt;
1840 else if (ArgFlags.isZExt())
1841 LocInfo = CCValAssign::ZExt;
1842 else
1843 LocInfo = CCValAssign::AExt;
1844 }
1845
1846 if (LocVT == MVT::f16 ||
1847 LocVT == MVT::f32 ||
1848 LocVT == MVT::f64 ||
1849 LocVT == MVT::f128 ||
1850 LocVT == MVT::v16i8 ||
1851 LocVT == MVT::v8i16 ||
1852 LocVT == MVT::v4i32 ||
1853 LocVT == MVT::v2i64 ||
1854 LocVT == MVT::v8f16 ||
1855 LocVT == MVT::v8bf16 ||
1856 LocVT == MVT::v4f32 ||
1857 LocVT == MVT::v2f64) {
1858 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
1859 static const MCPhysReg RegList3[] = {
1860 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1861 };
1862 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1863 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1864 return false;
1865 }
1866 }
1867 }
1868
1869 if (!State.isVarArg()) {
1870 if (LocVT == MVT::v32i8 ||
1871 LocVT == MVT::v16i16 ||
1872 LocVT == MVT::v8i32 ||
1873 LocVT == MVT::v4i64 ||
1874 LocVT == MVT::v16f16 ||
1875 LocVT == MVT::v16bf16 ||
1876 LocVT == MVT::v8f32 ||
1877 LocVT == MVT::v4f64) {
1878 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1879 static const MCPhysReg RegList4[] = {
1880 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1881 };
1882 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1883 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1884 return false;
1885 }
1886 }
1887 }
1888 }
1889
1890 if (!State.isVarArg()) {
1891 if (LocVT == MVT::v64i8 ||
1892 LocVT == MVT::v32i16 ||
1893 LocVT == MVT::v16i32 ||
1894 LocVT == MVT::v8i64 ||
1895 LocVT == MVT::v32f16 ||
1896 LocVT == MVT::v32bf16 ||
1897 LocVT == MVT::v16f32 ||
1898 LocVT == MVT::v8f64) {
1899 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
1900 static const MCPhysReg RegList5[] = {
1901 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1902 };
1903 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
1904 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1905 return false;
1906 }
1907 }
1908 }
1909 }
1910
1911 if (LocVT == MVT::i32 ||
1912 LocVT == MVT::i64 ||
1913 LocVT == MVT::f16 ||
1914 LocVT == MVT::f32 ||
1915 LocVT == MVT::f64) {
1916 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
1917 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1918 return false;
1919 }
1920
1921 if (LocVT == MVT::f80 ||
1922 LocVT == MVT::f128) {
1923 int64_t Offset7 = State.AllocateStack(
1924 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1925 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1926 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
1927 return false;
1928 }
1929
1930 if (LocVT == MVT::v16i8 ||
1931 LocVT == MVT::v8i16 ||
1932 LocVT == MVT::v4i32 ||
1933 LocVT == MVT::v2i64 ||
1934 LocVT == MVT::v8f16 ||
1935 LocVT == MVT::v8bf16 ||
1936 LocVT == MVT::v4f32 ||
1937 LocVT == MVT::v2f64) {
1938 int64_t Offset8 = State.AllocateStack(Size: 16, Alignment: Align(16));
1939 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1940 return false;
1941 }
1942
1943 if (LocVT == MVT::v32i8 ||
1944 LocVT == MVT::v16i16 ||
1945 LocVT == MVT::v8i32 ||
1946 LocVT == MVT::v4i64 ||
1947 LocVT == MVT::v16f16 ||
1948 LocVT == MVT::v16bf16 ||
1949 LocVT == MVT::v8f32 ||
1950 LocVT == MVT::v4f64) {
1951 int64_t Offset9 = State.AllocateStack(Size: 32, Alignment: Align(32));
1952 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1953 return false;
1954 }
1955
1956 if (LocVT == MVT::v64i8 ||
1957 LocVT == MVT::v32i16 ||
1958 LocVT == MVT::v16i32 ||
1959 LocVT == MVT::v8i64 ||
1960 LocVT == MVT::v32f16 ||
1961 LocVT == MVT::v32bf16 ||
1962 LocVT == MVT::v16f32 ||
1963 LocVT == MVT::v8f64) {
1964 int64_t Offset10 = State.AllocateStack(Size: 64, Alignment: Align(64));
1965 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1966 return false;
1967 }
1968
1969 return true; // CC didn't match.
1970}
1971
1972
1973static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
1974 MVT LocVT, CCValAssign::LocInfo LocInfo,
1975 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1976
1977 if (LocVT == MVT::i8 ||
1978 LocVT == MVT::i16 ||
1979 LocVT == MVT::i32) {
1980 LocVT = MVT::i64;
1981 if (ArgFlags.isSExt())
1982 LocInfo = CCValAssign::SExt;
1983 else if (ArgFlags.isZExt())
1984 LocInfo = CCValAssign::ZExt;
1985 else
1986 LocInfo = CCValAssign::AExt;
1987 }
1988
1989 if (LocVT == MVT::i64) {
1990 static const MCPhysReg RegList1[] = {
1991 X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
1992 };
1993 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1994 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1995 return false;
1996 }
1997 }
1998
1999 if (LocVT == MVT::f32 ||
2000 LocVT == MVT::f64 ||
2001 LocVT == MVT::v16i8 ||
2002 LocVT == MVT::v8i16 ||
2003 LocVT == MVT::v4i32 ||
2004 LocVT == MVT::v2i64 ||
2005 LocVT == MVT::v4f32 ||
2006 LocVT == MVT::v2f64) {
2007 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2008 static const MCPhysReg RegList2[] = {
2009 X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
2010 };
2011 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2012 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2013 return false;
2014 }
2015 }
2016 }
2017
2018 if (LocVT == MVT::v32i8 ||
2019 LocVT == MVT::v16i16 ||
2020 LocVT == MVT::v8i32 ||
2021 LocVT == MVT::v4i64 ||
2022 LocVT == MVT::v8f32 ||
2023 LocVT == MVT::v4f64) {
2024 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
2025 static const MCPhysReg RegList3[] = {
2026 X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6
2027 };
2028 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2029 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2030 return false;
2031 }
2032 }
2033 }
2034
2035 if (LocVT == MVT::v64i8 ||
2036 LocVT == MVT::v32i16 ||
2037 LocVT == MVT::v16i32 ||
2038 LocVT == MVT::v8i64 ||
2039 LocVT == MVT::v16f32 ||
2040 LocVT == MVT::v8f64) {
2041 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
2042 static const MCPhysReg RegList4[] = {
2043 X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6
2044 };
2045 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2046 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2047 return false;
2048 }
2049 }
2050 }
2051
2052 return true; // CC didn't match.
2053}
2054
2055
2056static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
2057 MVT LocVT, CCValAssign::LocInfo LocInfo,
2058 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2059
2060 if (LocVT == MVT::i8 ||
2061 LocVT == MVT::i16 ||
2062 LocVT == MVT::i32) {
2063 LocVT = MVT::i64;
2064 if (ArgFlags.isSExt())
2065 LocInfo = CCValAssign::SExt;
2066 else if (ArgFlags.isZExt())
2067 LocInfo = CCValAssign::ZExt;
2068 else
2069 LocInfo = CCValAssign::AExt;
2070 }
2071
2072 if (LocVT == MVT::i64) {
2073 static const MCPhysReg RegList1[] = {
2074 X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8
2075 };
2076 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2077 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2078 return false;
2079 }
2080 }
2081
2082 if (LocVT == MVT::i32 ||
2083 LocVT == MVT::i64 ||
2084 LocVT == MVT::f32 ||
2085 LocVT == MVT::f64) {
2086 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(8));
2087 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
2088 return false;
2089 }
2090
2091 return true; // CC didn't match.
2092}
2093
2094
2095static bool CC_X86_64_Preserve_None(unsigned ValNo, MVT ValVT,
2096 MVT LocVT, CCValAssign::LocInfo LocInfo,
2097 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2098
2099 if (LocVT == MVT::i32) {
2100 static const MCPhysReg RegList1[] = {
2101 X86::R12D, X86::R13D, X86::R14D, X86::R15D, X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D, X86::R11D, X86::EAX
2102 };
2103 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2104 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2105 return false;
2106 }
2107 }
2108
2109 if (LocVT == MVT::i64) {
2110 static const MCPhysReg RegList2[] = {
2111 X86::R12, X86::R13, X86::R14, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::R11, X86::RAX
2112 };
2113 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2114 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2115 return false;
2116 }
2117 }
2118
2119 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
2120 return false;
2121
2122 return true; // CC didn't match.
2123}
2124
2125
2126static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
2127 MVT LocVT, CCValAssign::LocInfo LocInfo,
2128 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2129
2130 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2131 if (ArgFlags.isByVal()) {
2132 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2133 return false;
2134 }
2135 }
2136
2137 if (ArgFlags.isByVal()) {
2138 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2139 return false;
2140 }
2141
2142 if (LocVT == MVT::i1 ||
2143 LocVT == MVT::i8 ||
2144 LocVT == MVT::i16 ||
2145 LocVT == MVT::v1i1) {
2146 LocVT = MVT::i32;
2147 if (ArgFlags.isSExt())
2148 LocInfo = CCValAssign::SExt;
2149 else if (ArgFlags.isZExt())
2150 LocInfo = CCValAssign::ZExt;
2151 else
2152 LocInfo = CCValAssign::AExt;
2153 }
2154
2155 if (LocVT == MVT::v8i1 ||
2156 LocVT == MVT::v16i1 ||
2157 LocVT == MVT::v32i1) {
2158 LocVT = MVT::i32;
2159 if (ArgFlags.isSExt())
2160 LocInfo = CCValAssign::SExt;
2161 else if (ArgFlags.isZExt())
2162 LocInfo = CCValAssign::ZExt;
2163 else
2164 LocInfo = CCValAssign::AExt;
2165 }
2166
2167 if (LocVT == MVT::i32) {
2168 static const MCPhysReg RegList1[] = {
2169 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
2170 };
2171 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2172 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2173 return false;
2174 }
2175 }
2176
2177 if (LocVT == MVT::i64) {
2178 static const MCPhysReg RegList2[] = {
2179 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2180 };
2181 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2182 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2183 return false;
2184 }
2185 }
2186
2187 if (LocVT == MVT::v64i1) {
2188 LocVT = MVT::i64;
2189 if (ArgFlags.isSExt())
2190 LocInfo = CCValAssign::SExt;
2191 else if (ArgFlags.isZExt())
2192 LocInfo = CCValAssign::ZExt;
2193 else
2194 LocInfo = CCValAssign::AExt;
2195 }
2196
2197 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2198 if (LocVT == MVT::i64) {
2199 static const MCPhysReg RegList3[] = {
2200 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2201 };
2202 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2203 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2204 return false;
2205 }
2206 }
2207 }
2208
2209 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
2210 if (LocVT == MVT::i64) {
2211 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2212 return false;
2213 }
2214 }
2215
2216 if (LocVT == MVT::f32 ||
2217 LocVT == MVT::f64 ||
2218 LocVT == MVT::f128) {
2219 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2220 static const MCPhysReg RegList4[] = {
2221 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2222 };
2223 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2224 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2225 return false;
2226 }
2227 }
2228 }
2229
2230 if (LocVT == MVT::f80) {
2231 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
2232 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2233 return false;
2234 }
2235 }
2236
2237 if (LocVT == MVT::v16i8 ||
2238 LocVT == MVT::v8i16 ||
2239 LocVT == MVT::v4i32 ||
2240 LocVT == MVT::v2i64 ||
2241 LocVT == MVT::v4f32 ||
2242 LocVT == MVT::v2f64) {
2243 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2244 static const MCPhysReg RegList5[] = {
2245 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2246 };
2247 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2248 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2249 return false;
2250 }
2251 }
2252 }
2253
2254 if (LocVT == MVT::v32i8 ||
2255 LocVT == MVT::v16i16 ||
2256 LocVT == MVT::v8i32 ||
2257 LocVT == MVT::v4i64 ||
2258 LocVT == MVT::v8f32 ||
2259 LocVT == MVT::v4f64) {
2260 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
2261 static const MCPhysReg RegList6[] = {
2262 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2263 };
2264 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2265 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2266 return false;
2267 }
2268 }
2269 }
2270
2271 if (LocVT == MVT::v64i8 ||
2272 LocVT == MVT::v32i16 ||
2273 LocVT == MVT::v16i32 ||
2274 LocVT == MVT::v8i64 ||
2275 LocVT == MVT::v16f32 ||
2276 LocVT == MVT::v8f64) {
2277 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
2278 static const MCPhysReg RegList7[] = {
2279 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2280 };
2281 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2282 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2283 return false;
2284 }
2285 }
2286 }
2287
2288 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2289 if (LocVT == MVT::i32 ||
2290 LocVT == MVT::i64 ||
2291 LocVT == MVT::f32 ||
2292 LocVT == MVT::f64) {
2293 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
2294 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
2295 return false;
2296 }
2297 }
2298
2299 if (LocVT == MVT::i32 ||
2300 LocVT == MVT::f32) {
2301 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
2302 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
2303 return false;
2304 }
2305
2306 if (LocVT == MVT::i64 ||
2307 LocVT == MVT::f64) {
2308 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
2309 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
2310 return false;
2311 }
2312
2313 if (LocVT == MVT::f80 ||
2314 LocVT == MVT::f128) {
2315 int64_t Offset11 = State.AllocateStack(
2316 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
2317 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
2318 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
2319 return false;
2320 }
2321
2322 if (LocVT == MVT::v16i8 ||
2323 LocVT == MVT::v8i16 ||
2324 LocVT == MVT::v4i32 ||
2325 LocVT == MVT::v2i64 ||
2326 LocVT == MVT::v4f32 ||
2327 LocVT == MVT::v2f64) {
2328 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
2329 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
2330 return false;
2331 }
2332
2333 if (LocVT == MVT::v32i8 ||
2334 LocVT == MVT::v16i16 ||
2335 LocVT == MVT::v8i32 ||
2336 LocVT == MVT::v4i64 ||
2337 LocVT == MVT::v8f32 ||
2338 LocVT == MVT::v4f64) {
2339 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
2340 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2341 return false;
2342 }
2343
2344 if (LocVT == MVT::v64i8 ||
2345 LocVT == MVT::v32i16 ||
2346 LocVT == MVT::v16i32 ||
2347 LocVT == MVT::v8i64 ||
2348 LocVT == MVT::v16f32 ||
2349 LocVT == MVT::v8f64) {
2350 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
2351 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
2352 return false;
2353 }
2354
2355 return true; // CC didn't match.
2356}
2357
2358
2359static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
2360 MVT LocVT, CCValAssign::LocInfo LocInfo,
2361 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2362
2363 if (LocVT == MVT::i32) {
2364 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
2365 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2366 return false;
2367 }
2368 }
2369
2370 return true; // CC didn't match.
2371}
2372
2373
2374static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT,
2375 MVT LocVT, CCValAssign::LocInfo LocInfo,
2376 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2377
2378 if (LocVT == MVT::v16i8 ||
2379 LocVT == MVT::v8i16 ||
2380 LocVT == MVT::v4i32 ||
2381 LocVT == MVT::v2i64 ||
2382 LocVT == MVT::v8f16 ||
2383 LocVT == MVT::v8bf16 ||
2384 LocVT == MVT::v4f32 ||
2385 LocVT == MVT::v2f64) {
2386 int64_t Offset1 = State.AllocateStack(Size: 16, Alignment: Align(4));
2387 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
2388 return false;
2389 }
2390
2391 if (LocVT == MVT::v32i8 ||
2392 LocVT == MVT::v16i16 ||
2393 LocVT == MVT::v8i32 ||
2394 LocVT == MVT::v4i64 ||
2395 LocVT == MVT::v16f16 ||
2396 LocVT == MVT::v16bf16 ||
2397 LocVT == MVT::v8f32 ||
2398 LocVT == MVT::v4f64) {
2399 int64_t Offset2 = State.AllocateStack(Size: 32, Alignment: Align(4));
2400 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
2401 return false;
2402 }
2403
2404 if (LocVT == MVT::v64i8 ||
2405 LocVT == MVT::v32i16 ||
2406 LocVT == MVT::v16i32 ||
2407 LocVT == MVT::v8i64 ||
2408 LocVT == MVT::v32f16 ||
2409 LocVT == MVT::v32bf16 ||
2410 LocVT == MVT::v16f32 ||
2411 LocVT == MVT::v8f64) {
2412 int64_t Offset3 = State.AllocateStack(Size: 64, Alignment: Align(4));
2413 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
2414 return false;
2415 }
2416
2417 return true; // CC didn't match.
2418}
2419
2420
2421static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
2422 MVT LocVT, CCValAssign::LocInfo LocInfo,
2423 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2424
2425 if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2426 return false;
2427
2428 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
2429 return false;
2430
2431 return true; // CC didn't match.
2432}
2433
2434
2435static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
2436 MVT LocVT, CCValAssign::LocInfo LocInfo,
2437 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2438
2439 if (ArgFlags.isByVal()) {
2440 LocVT = MVT::i64;
2441 LocInfo = CCValAssign::Indirect;
2442 }
2443
2444 if (LocVT == MVT::i1 ||
2445 LocVT == MVT::v1i1) {
2446 LocVT = MVT::i8;
2447 if (ArgFlags.isSExt())
2448 LocInfo = CCValAssign::SExt;
2449 else if (ArgFlags.isZExt())
2450 LocInfo = CCValAssign::ZExt;
2451 else
2452 LocInfo = CCValAssign::AExt;
2453 }
2454
2455 if (ArgFlags.isNest()) {
2456 if (MCRegister Reg = State.AllocateReg(Reg: X86::R10)) {
2457 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2458 return false;
2459 }
2460 }
2461
2462 if (ArgFlags.isSwiftError()) {
2463 if (LocVT == MVT::i64) {
2464 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
2465 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2466 return false;
2467 }
2468 }
2469 }
2470
2471 if (ArgFlags.isSwiftSelf()) {
2472 if (LocVT == MVT::i64) {
2473 if (MCRegister Reg = State.AllocateReg(Reg: X86::R13)) {
2474 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2475 return false;
2476 }
2477 }
2478 }
2479
2480 if (ArgFlags.isSwiftAsync()) {
2481 if (LocVT == MVT::i64) {
2482 if (MCRegister Reg = State.AllocateReg(Reg: X86::R14)) {
2483 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2484 return false;
2485 }
2486 }
2487 }
2488
2489 if (ArgFlags.isCFGuardTarget()) {
2490 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
2491 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2492 return false;
2493 }
2494 }
2495
2496 if (LocVT == MVT::v16i8 ||
2497 LocVT == MVT::v8i16 ||
2498 LocVT == MVT::v4i32 ||
2499 LocVT == MVT::v2i64 ||
2500 LocVT == MVT::v8f16 ||
2501 LocVT == MVT::v8bf16 ||
2502 LocVT == MVT::v4f32 ||
2503 LocVT == MVT::v2f64) {
2504 LocVT = MVT::i64;
2505 LocInfo = CCValAssign::Indirect;
2506 }
2507
2508 if (LocVT == MVT::v32i8 ||
2509 LocVT == MVT::v16i16 ||
2510 LocVT == MVT::v8i32 ||
2511 LocVT == MVT::v4i64 ||
2512 LocVT == MVT::v16f16 ||
2513 LocVT == MVT::v16bf16 ||
2514 LocVT == MVT::v8f32 ||
2515 LocVT == MVT::v4f64) {
2516 LocVT = MVT::i64;
2517 LocInfo = CCValAssign::Indirect;
2518 }
2519
2520 if (LocVT == MVT::v64i8 ||
2521 LocVT == MVT::v32i16 ||
2522 LocVT == MVT::v16i32 ||
2523 LocVT == MVT::v32f16 ||
2524 LocVT == MVT::v32bf16 ||
2525 LocVT == MVT::v16f32 ||
2526 LocVT == MVT::v8f64 ||
2527 LocVT == MVT::v8i64) {
2528 LocVT = MVT::i64;
2529 LocInfo = CCValAssign::Indirect;
2530 }
2531
2532 if (LocVT == MVT::f80) {
2533 LocVT = MVT::i64;
2534 LocInfo = CCValAssign::Indirect;
2535 }
2536
2537 if (LocVT == MVT::f128) {
2538 LocVT = MVT::i64;
2539 LocInfo = CCValAssign::Indirect;
2540 }
2541
2542 if (LocVT == MVT::f32) {
2543 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2544 LocVT = MVT::i32;
2545 LocInfo = CCValAssign::BCvt;
2546 }
2547 }
2548
2549 if (LocVT == MVT::f64) {
2550 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2551 LocVT = MVT::i64;
2552 LocInfo = CCValAssign::BCvt;
2553 }
2554 }
2555
2556 if (LocVT == MVT::f16 ||
2557 LocVT == MVT::f32 ||
2558 LocVT == MVT::f64) {
2559 static const MCPhysReg RegList1[] = {
2560 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2561 };
2562 static const MCPhysReg RegList2[] = {
2563 X86::RCX, X86::RDX, X86::R8, X86::R9
2564 };
2565 if (MCRegister Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
2566 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2567 return false;
2568 }
2569 }
2570
2571 if (LocVT == MVT::i8) {
2572 static const MCPhysReg RegList3[] = {
2573 X86::CL, X86::DL, X86::R8B, X86::R9B
2574 };
2575 static const MCPhysReg RegList4[] = {
2576 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2577 };
2578 if (MCRegister Reg = State.AllocateReg(Regs: RegList3, ShadowRegs: RegList4)) {
2579 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2580 return false;
2581 }
2582 }
2583
2584 if (LocVT == MVT::i16) {
2585 static const MCPhysReg RegList5[] = {
2586 X86::CX, X86::DX, X86::R8W, X86::R9W
2587 };
2588 static const MCPhysReg RegList6[] = {
2589 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2590 };
2591 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
2592 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2593 return false;
2594 }
2595 }
2596
2597 if (LocVT == MVT::i32) {
2598 static const MCPhysReg RegList7[] = {
2599 X86::ECX, X86::EDX, X86::R8D, X86::R9D
2600 };
2601 static const MCPhysReg RegList8[] = {
2602 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2603 };
2604 if (MCRegister Reg = State.AllocateReg(Regs: RegList7, ShadowRegs: RegList8)) {
2605 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2606 return false;
2607 }
2608 }
2609
2610 if (State.getCallingConv() == CallingConv::X86_ThisCall) {
2611 if (ArgFlags.isSRet()) {
2612 if (LocVT == MVT::i64) {
2613 static const MCPhysReg RegList9[] = {
2614 X86::RDX, X86::R8, X86::R9
2615 };
2616 static const MCPhysReg RegList10[] = {
2617 X86::XMM1, X86::XMM2, X86::XMM3
2618 };
2619 if (MCRegister Reg = State.AllocateReg(Regs: RegList9, ShadowRegs: RegList10)) {
2620 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2621 return false;
2622 }
2623 }
2624 }
2625 }
2626
2627 if (LocVT == MVT::i64) {
2628 static const MCPhysReg RegList11[] = {
2629 X86::RCX, X86::RDX, X86::R8, X86::R9
2630 };
2631 static const MCPhysReg RegList12[] = {
2632 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2633 };
2634 if (MCRegister Reg = State.AllocateReg(Regs: RegList11, ShadowRegs: RegList12)) {
2635 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2636 return false;
2637 }
2638 }
2639
2640 if (LocVT == MVT::i8 ||
2641 LocVT == MVT::i16 ||
2642 LocVT == MVT::i32 ||
2643 LocVT == MVT::i64 ||
2644 LocVT == MVT::f16 ||
2645 LocVT == MVT::f32 ||
2646 LocVT == MVT::f64) {
2647 int64_t Offset13 = State.AllocateStack(Size: 8, Alignment: Align(8));
2648 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2649 return false;
2650 }
2651
2652 return true; // CC didn't match.
2653}
2654
2655
2656static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
2657 MVT LocVT, CCValAssign::LocInfo LocInfo,
2658 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2659
2660 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2661 if (ArgFlags.isByVal()) {
2662 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2663 return false;
2664 }
2665 }
2666
2667 if (ArgFlags.isByVal()) {
2668 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2669 return false;
2670 }
2671
2672 if (LocVT == MVT::i1 ||
2673 LocVT == MVT::i8 ||
2674 LocVT == MVT::i16 ||
2675 LocVT == MVT::v1i1) {
2676 LocVT = MVT::i32;
2677 if (ArgFlags.isSExt())
2678 LocInfo = CCValAssign::SExt;
2679 else if (ArgFlags.isZExt())
2680 LocInfo = CCValAssign::ZExt;
2681 else
2682 LocInfo = CCValAssign::AExt;
2683 }
2684
2685 if (LocVT == MVT::v8i1 ||
2686 LocVT == MVT::v16i1 ||
2687 LocVT == MVT::v32i1) {
2688 LocVT = MVT::i32;
2689 if (ArgFlags.isSExt())
2690 LocInfo = CCValAssign::SExt;
2691 else if (ArgFlags.isZExt())
2692 LocInfo = CCValAssign::ZExt;
2693 else
2694 LocInfo = CCValAssign::AExt;
2695 }
2696
2697 if (LocVT == MVT::i32) {
2698 static const MCPhysReg RegList1[] = {
2699 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2700 };
2701 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2702 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2703 return false;
2704 }
2705 }
2706
2707 if (LocVT == MVT::i64) {
2708 static const MCPhysReg RegList2[] = {
2709 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2710 };
2711 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2712 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2713 return false;
2714 }
2715 }
2716
2717 if (LocVT == MVT::v64i1) {
2718 LocVT = MVT::i64;
2719 if (ArgFlags.isSExt())
2720 LocInfo = CCValAssign::SExt;
2721 else if (ArgFlags.isZExt())
2722 LocInfo = CCValAssign::ZExt;
2723 else
2724 LocInfo = CCValAssign::AExt;
2725 }
2726
2727 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2728 if (LocVT == MVT::i64) {
2729 static const MCPhysReg RegList3[] = {
2730 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2731 };
2732 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2733 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2734 return false;
2735 }
2736 }
2737 }
2738
2739 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
2740 if (LocVT == MVT::i64) {
2741 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2742 return false;
2743 }
2744 }
2745
2746 if (LocVT == MVT::f32 ||
2747 LocVT == MVT::f64 ||
2748 LocVT == MVT::f128) {
2749 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2750 static const MCPhysReg RegList4[] = {
2751 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2752 };
2753 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2754 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2755 return false;
2756 }
2757 }
2758 }
2759
2760 if (LocVT == MVT::f80) {
2761 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
2762 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2763 return false;
2764 }
2765 }
2766
2767 if (LocVT == MVT::v16i8 ||
2768 LocVT == MVT::v8i16 ||
2769 LocVT == MVT::v4i32 ||
2770 LocVT == MVT::v2i64 ||
2771 LocVT == MVT::v4f32 ||
2772 LocVT == MVT::v2f64) {
2773 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2774 static const MCPhysReg RegList5[] = {
2775 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2776 };
2777 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2778 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2779 return false;
2780 }
2781 }
2782 }
2783
2784 if (LocVT == MVT::v32i8 ||
2785 LocVT == MVT::v16i16 ||
2786 LocVT == MVT::v8i32 ||
2787 LocVT == MVT::v4i64 ||
2788 LocVT == MVT::v8f32 ||
2789 LocVT == MVT::v4f64) {
2790 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
2791 static const MCPhysReg RegList6[] = {
2792 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2793 };
2794 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2795 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2796 return false;
2797 }
2798 }
2799 }
2800
2801 if (LocVT == MVT::v64i8 ||
2802 LocVT == MVT::v32i16 ||
2803 LocVT == MVT::v16i32 ||
2804 LocVT == MVT::v8i64 ||
2805 LocVT == MVT::v16f32 ||
2806 LocVT == MVT::v8f64) {
2807 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
2808 static const MCPhysReg RegList7[] = {
2809 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2810 };
2811 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2812 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2813 return false;
2814 }
2815 }
2816 }
2817
2818 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2819 if (LocVT == MVT::i32 ||
2820 LocVT == MVT::i64 ||
2821 LocVT == MVT::f32 ||
2822 LocVT == MVT::f64) {
2823 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
2824 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
2825 return false;
2826 }
2827 }
2828
2829 if (LocVT == MVT::i32 ||
2830 LocVT == MVT::f32) {
2831 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
2832 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
2833 return false;
2834 }
2835
2836 if (LocVT == MVT::i64 ||
2837 LocVT == MVT::f64) {
2838 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
2839 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
2840 return false;
2841 }
2842
2843 if (LocVT == MVT::f80 ||
2844 LocVT == MVT::f128) {
2845 int64_t Offset11 = State.AllocateStack(
2846 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
2847 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
2848 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
2849 return false;
2850 }
2851
2852 if (LocVT == MVT::v16i8 ||
2853 LocVT == MVT::v8i16 ||
2854 LocVT == MVT::v4i32 ||
2855 LocVT == MVT::v2i64 ||
2856 LocVT == MVT::v4f32 ||
2857 LocVT == MVT::v2f64) {
2858 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
2859 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
2860 return false;
2861 }
2862
2863 if (LocVT == MVT::v32i8 ||
2864 LocVT == MVT::v16i16 ||
2865 LocVT == MVT::v8i32 ||
2866 LocVT == MVT::v4i64 ||
2867 LocVT == MVT::v8f32 ||
2868 LocVT == MVT::v4f64) {
2869 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
2870 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2871 return false;
2872 }
2873
2874 if (LocVT == MVT::v64i8 ||
2875 LocVT == MVT::v32i16 ||
2876 LocVT == MVT::v16i32 ||
2877 LocVT == MVT::v8i64 ||
2878 LocVT == MVT::v16f32 ||
2879 LocVT == MVT::v8f64) {
2880 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
2881 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
2882 return false;
2883 }
2884
2885 return true; // CC didn't match.
2886}
2887
2888
2889static bool CC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
2890 MVT LocVT, CCValAssign::LocInfo LocInfo,
2891 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2892
2893 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2894 if (ArgFlags.isByVal()) {
2895 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2896 return false;
2897 }
2898 }
2899
2900 if (ArgFlags.isByVal()) {
2901 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2902 return false;
2903 }
2904
2905 if (LocVT == MVT::i1 ||
2906 LocVT == MVT::i8 ||
2907 LocVT == MVT::i16 ||
2908 LocVT == MVT::v1i1) {
2909 LocVT = MVT::i32;
2910 if (ArgFlags.isSExt())
2911 LocInfo = CCValAssign::SExt;
2912 else if (ArgFlags.isZExt())
2913 LocInfo = CCValAssign::ZExt;
2914 else
2915 LocInfo = CCValAssign::AExt;
2916 }
2917
2918 if (LocVT == MVT::v8i1 ||
2919 LocVT == MVT::v16i1 ||
2920 LocVT == MVT::v32i1) {
2921 LocVT = MVT::i32;
2922 if (ArgFlags.isSExt())
2923 LocInfo = CCValAssign::SExt;
2924 else if (ArgFlags.isZExt())
2925 LocInfo = CCValAssign::ZExt;
2926 else
2927 LocInfo = CCValAssign::AExt;
2928 }
2929
2930 if (LocVT == MVT::i32) {
2931 static const MCPhysReg RegList1[] = {
2932 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2933 };
2934 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2935 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2936 return false;
2937 }
2938 }
2939
2940 if (LocVT == MVT::i64) {
2941 static const MCPhysReg RegList2[] = {
2942 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
2943 };
2944 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2945 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2946 return false;
2947 }
2948 }
2949
2950 if (LocVT == MVT::v64i1) {
2951 LocVT = MVT::i64;
2952 if (ArgFlags.isSExt())
2953 LocInfo = CCValAssign::SExt;
2954 else if (ArgFlags.isZExt())
2955 LocInfo = CCValAssign::ZExt;
2956 else
2957 LocInfo = CCValAssign::AExt;
2958 }
2959
2960 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2961 if (LocVT == MVT::i64) {
2962 static const MCPhysReg RegList3[] = {
2963 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
2964 };
2965 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2966 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2967 return false;
2968 }
2969 }
2970 }
2971
2972 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
2973 if (LocVT == MVT::i64) {
2974 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2975 return false;
2976 }
2977 }
2978
2979 if (LocVT == MVT::f32 ||
2980 LocVT == MVT::f64 ||
2981 LocVT == MVT::f128) {
2982 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2983 static const MCPhysReg RegList4[] = {
2984 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2985 };
2986 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2987 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2988 return false;
2989 }
2990 }
2991 }
2992
2993 if (LocVT == MVT::f80) {
2994 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
2995 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2996 return false;
2997 }
2998 }
2999
3000 if (LocVT == MVT::v16i8 ||
3001 LocVT == MVT::v8i16 ||
3002 LocVT == MVT::v4i32 ||
3003 LocVT == MVT::v2i64 ||
3004 LocVT == MVT::v4f32 ||
3005 LocVT == MVT::v2f64) {
3006 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3007 static const MCPhysReg RegList5[] = {
3008 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3009 };
3010 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3011 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3012 return false;
3013 }
3014 }
3015 }
3016
3017 if (LocVT == MVT::v32i8 ||
3018 LocVT == MVT::v16i16 ||
3019 LocVT == MVT::v8i32 ||
3020 LocVT == MVT::v4i64 ||
3021 LocVT == MVT::v8f32 ||
3022 LocVT == MVT::v4f64) {
3023 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
3024 static const MCPhysReg RegList6[] = {
3025 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3026 };
3027 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3028 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3029 return false;
3030 }
3031 }
3032 }
3033
3034 if (LocVT == MVT::v64i8 ||
3035 LocVT == MVT::v32i16 ||
3036 LocVT == MVT::v16i32 ||
3037 LocVT == MVT::v8i64 ||
3038 LocVT == MVT::v16f32 ||
3039 LocVT == MVT::v8f64) {
3040 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
3041 static const MCPhysReg RegList7[] = {
3042 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3043 };
3044 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3045 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3046 return false;
3047 }
3048 }
3049 }
3050
3051 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3052 if (LocVT == MVT::i32 ||
3053 LocVT == MVT::i64 ||
3054 LocVT == MVT::f32 ||
3055 LocVT == MVT::f64) {
3056 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
3057 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
3058 return false;
3059 }
3060 }
3061
3062 if (LocVT == MVT::i32 ||
3063 LocVT == MVT::f32) {
3064 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
3065 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
3066 return false;
3067 }
3068
3069 if (LocVT == MVT::i64 ||
3070 LocVT == MVT::f64) {
3071 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
3072 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
3073 return false;
3074 }
3075
3076 if (LocVT == MVT::f80 ||
3077 LocVT == MVT::f128) {
3078 int64_t Offset11 = State.AllocateStack(
3079 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
3080 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
3081 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
3082 return false;
3083 }
3084
3085 if (LocVT == MVT::v16i8 ||
3086 LocVT == MVT::v8i16 ||
3087 LocVT == MVT::v4i32 ||
3088 LocVT == MVT::v2i64 ||
3089 LocVT == MVT::v4f32 ||
3090 LocVT == MVT::v2f64) {
3091 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
3092 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
3093 return false;
3094 }
3095
3096 if (LocVT == MVT::v32i8 ||
3097 LocVT == MVT::v16i16 ||
3098 LocVT == MVT::v8i32 ||
3099 LocVT == MVT::v4i64 ||
3100 LocVT == MVT::v8f32 ||
3101 LocVT == MVT::v4f64) {
3102 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
3103 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
3104 return false;
3105 }
3106
3107 if (LocVT == MVT::v64i8 ||
3108 LocVT == MVT::v32i16 ||
3109 LocVT == MVT::v16i32 ||
3110 LocVT == MVT::v8i64 ||
3111 LocVT == MVT::v16f32 ||
3112 LocVT == MVT::v8f64) {
3113 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
3114 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
3115 return false;
3116 }
3117
3118 return true; // CC didn't match.
3119}
3120
3121
3122static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
3123 MVT LocVT, CCValAssign::LocInfo LocInfo,
3124 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3125
3126 if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3127 return false;
3128
3129 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3130 return false;
3131
3132 return true; // CC didn't match.
3133}
3134
3135
3136static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
3137 MVT LocVT, CCValAssign::LocInfo LocInfo,
3138 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3139
3140 if (LocVT == MVT::f32 ||
3141 LocVT == MVT::f64 ||
3142 LocVT == MVT::v4i32 ||
3143 LocVT == MVT::v2i64 ||
3144 LocVT == MVT::v4f32 ||
3145 LocVT == MVT::v2f64) {
3146 static const MCPhysReg RegList1[] = {
3147 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3148 };
3149 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3150 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3151 return false;
3152 }
3153 }
3154
3155 if (LocVT == MVT::v8f32 ||
3156 LocVT == MVT::v4f64 ||
3157 LocVT == MVT::v8i32 ||
3158 LocVT == MVT::v4i64) {
3159 static const MCPhysReg RegList2[] = {
3160 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
3161 };
3162 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3163 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3164 return false;
3165 }
3166 }
3167
3168 if (LocVT == MVT::v16f32 ||
3169 LocVT == MVT::v8f64 ||
3170 LocVT == MVT::v16i32 ||
3171 LocVT == MVT::v8i64) {
3172 static const MCPhysReg RegList3[] = {
3173 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
3174 };
3175 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3176 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3177 return false;
3178 }
3179 }
3180
3181 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3182 return false;
3183
3184 return true; // CC didn't match.
3185}
3186
3187
3188bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
3189 MVT LocVT, CCValAssign::LocInfo LocInfo,
3190 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3191
3192 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
3193 if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3194 return false;
3195 }
3196
3197 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3198 if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3199 return false;
3200 }
3201
3202 if (!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3203 return false;
3204
3205 return true; // CC didn't match.
3206}
3207
3208
3209static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
3210 MVT LocVT, CCValAssign::LocInfo LocInfo,
3211 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3212
3213 if (LocVT == MVT::v1i1) {
3214 LocVT = MVT::i8;
3215 if (ArgFlags.isSExt())
3216 LocInfo = CCValAssign::SExt;
3217 else if (ArgFlags.isZExt())
3218 LocInfo = CCValAssign::ZExt;
3219 else
3220 LocInfo = CCValAssign::AExt;
3221 }
3222
3223 if (LocVT == MVT::i1) {
3224 LocVT = MVT::i8;
3225 if (ArgFlags.isSExt())
3226 LocInfo = CCValAssign::SExt;
3227 else if (ArgFlags.isZExt())
3228 LocInfo = CCValAssign::ZExt;
3229 else
3230 LocInfo = CCValAssign::AExt;
3231 }
3232
3233 if (LocVT == MVT::i8) {
3234 static const MCPhysReg RegList1[] = {
3235 X86::AL, X86::DL, X86::CL
3236 };
3237 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3238 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3239 return false;
3240 }
3241 }
3242
3243 if (LocVT == MVT::i16) {
3244 static const MCPhysReg RegList2[] = {
3245 X86::AX, X86::DX, X86::CX
3246 };
3247 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3248 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3249 return false;
3250 }
3251 }
3252
3253 if (LocVT == MVT::i32) {
3254 static const MCPhysReg RegList3[] = {
3255 X86::EAX, X86::EDX, X86::ECX
3256 };
3257 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3258 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3259 return false;
3260 }
3261 }
3262
3263 if (LocVT == MVT::i64) {
3264 static const MCPhysReg RegList4[] = {
3265 X86::RAX, X86::RDX, X86::RCX
3266 };
3267 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3268 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3269 return false;
3270 }
3271 }
3272
3273 if (LocVT == MVT::v2i1) {
3274 LocVT = MVT::v2i64;
3275 if (ArgFlags.isSExt())
3276 LocInfo = CCValAssign::SExt;
3277 else if (ArgFlags.isZExt())
3278 LocInfo = CCValAssign::ZExt;
3279 else
3280 LocInfo = CCValAssign::AExt;
3281 }
3282
3283 if (LocVT == MVT::v4i1) {
3284 LocVT = MVT::v4i32;
3285 if (ArgFlags.isSExt())
3286 LocInfo = CCValAssign::SExt;
3287 else if (ArgFlags.isZExt())
3288 LocInfo = CCValAssign::ZExt;
3289 else
3290 LocInfo = CCValAssign::AExt;
3291 }
3292
3293 if (LocVT == MVT::v8i1) {
3294 LocVT = MVT::v8i16;
3295 if (ArgFlags.isSExt())
3296 LocInfo = CCValAssign::SExt;
3297 else if (ArgFlags.isZExt())
3298 LocInfo = CCValAssign::ZExt;
3299 else
3300 LocInfo = CCValAssign::AExt;
3301 }
3302
3303 if (LocVT == MVT::v16i1) {
3304 LocVT = MVT::v16i8;
3305 if (ArgFlags.isSExt())
3306 LocInfo = CCValAssign::SExt;
3307 else if (ArgFlags.isZExt())
3308 LocInfo = CCValAssign::ZExt;
3309 else
3310 LocInfo = CCValAssign::AExt;
3311 }
3312
3313 if (LocVT == MVT::v32i1) {
3314 LocVT = MVT::v32i8;
3315 if (ArgFlags.isSExt())
3316 LocInfo = CCValAssign::SExt;
3317 else if (ArgFlags.isZExt())
3318 LocInfo = CCValAssign::ZExt;
3319 else
3320 LocInfo = CCValAssign::AExt;
3321 }
3322
3323 if (LocVT == MVT::v64i1) {
3324 LocVT = MVT::v64i8;
3325 if (ArgFlags.isSExt())
3326 LocInfo = CCValAssign::SExt;
3327 else if (ArgFlags.isZExt())
3328 LocInfo = CCValAssign::ZExt;
3329 else
3330 LocInfo = CCValAssign::AExt;
3331 }
3332
3333 if (LocVT == MVT::v16i8 ||
3334 LocVT == MVT::v8i16 ||
3335 LocVT == MVT::v4i32 ||
3336 LocVT == MVT::v2i64 ||
3337 LocVT == MVT::v8f16 ||
3338 LocVT == MVT::v8bf16 ||
3339 LocVT == MVT::v4f32 ||
3340 LocVT == MVT::v2f64) {
3341 static const MCPhysReg RegList5[] = {
3342 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3343 };
3344 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3345 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3346 return false;
3347 }
3348 }
3349
3350 if (LocVT == MVT::v32i8 ||
3351 LocVT == MVT::v16i16 ||
3352 LocVT == MVT::v8i32 ||
3353 LocVT == MVT::v4i64 ||
3354 LocVT == MVT::v16f16 ||
3355 LocVT == MVT::v16bf16 ||
3356 LocVT == MVT::v8f32 ||
3357 LocVT == MVT::v4f64) {
3358 static const MCPhysReg RegList6[] = {
3359 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
3360 };
3361 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3362 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3363 return false;
3364 }
3365 }
3366
3367 if (LocVT == MVT::v64i8 ||
3368 LocVT == MVT::v32i16 ||
3369 LocVT == MVT::v16i32 ||
3370 LocVT == MVT::v8i64 ||
3371 LocVT == MVT::v32f16 ||
3372 LocVT == MVT::v32bf16 ||
3373 LocVT == MVT::v16f32 ||
3374 LocVT == MVT::v8f64) {
3375 static const MCPhysReg RegList7[] = {
3376 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
3377 };
3378 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3379 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3380 return false;
3381 }
3382 }
3383
3384 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
3385 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetUEFI64()) {
3386 if (LocVT == MVT::f80) {
3387 static const MCPhysReg RegList8[] = {
3388 X86::FP0, X86::FP1
3389 };
3390 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
3391 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3392 return false;
3393 }
3394 }
3395 }
3396 }
3397
3398 return true; // CC didn't match.
3399}
3400
3401
3402static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
3403 MVT LocVT, CCValAssign::LocInfo LocInfo,
3404 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3405
3406 if (State.getCallingConv() == CallingConv::Fast) {
3407 if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3408 return false;
3409 }
3410
3411 if (State.getCallingConv() == CallingConv::Tail) {
3412 if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3413 return false;
3414 }
3415
3416 if (State.getCallingConv() == CallingConv::HiPE) {
3417 if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3418 return false;
3419 }
3420
3421 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
3422 if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3423 return false;
3424 }
3425
3426 if (State.getCallingConv() == CallingConv::X86_RegCall) {
3427 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin32()) {
3428 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
3429 if (!RetCC_X86_32_RegCallv4_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3430 return false;
3431 }
3432 }
3433 }
3434
3435 if (State.getCallingConv() == CallingConv::X86_RegCall) {
3436 if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3437 return false;
3438 }
3439
3440 if (!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3441 return false;
3442
3443 return true; // CC didn't match.
3444}
3445
3446
3447static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
3448 MVT LocVT, CCValAssign::LocInfo LocInfo,
3449 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3450
3451 if (ArgFlags.isInReg()) {
3452 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
3453 if (LocVT == MVT::f32 ||
3454 LocVT == MVT::f64) {
3455 static const MCPhysReg RegList1[] = {
3456 X86::XMM0, X86::XMM1, X86::XMM2
3457 };
3458 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3459 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3460 return false;
3461 }
3462 }
3463 }
3464 }
3465
3466 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasX87()) {
3467 if (LocVT == MVT::f32 ||
3468 LocVT == MVT::f64) {
3469 static const MCPhysReg RegList2[] = {
3470 X86::FP0, X86::FP1
3471 };
3472 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3473 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3474 return false;
3475 }
3476 }
3477 }
3478
3479 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasX87()) {
3480 if (LocVT == MVT::f32) {
3481 static const MCPhysReg RegList3[] = {
3482 X86::EAX, X86::EDX, X86::ECX
3483 };
3484 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3485 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3486 return false;
3487 }
3488 }
3489 }
3490
3491 if (LocVT == MVT::f16) {
3492 static const MCPhysReg RegList4[] = {
3493 X86::XMM0, X86::XMM1, X86::XMM2
3494 };
3495 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3496 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3497 return false;
3498 }
3499 }
3500
3501 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3502 return false;
3503
3504 return true; // CC didn't match.
3505}
3506
3507
3508static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
3509 MVT LocVT, CCValAssign::LocInfo LocInfo,
3510 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3511
3512 if (LocVT == MVT::f32) {
3513 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
3514 static const MCPhysReg RegList1[] = {
3515 X86::XMM0, X86::XMM1, X86::XMM2
3516 };
3517 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3518 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3519 return false;
3520 }
3521 }
3522 }
3523
3524 if (LocVT == MVT::f64) {
3525 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
3526 static const MCPhysReg RegList2[] = {
3527 X86::XMM0, X86::XMM1, X86::XMM2
3528 };
3529 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3530 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3531 return false;
3532 }
3533 }
3534 }
3535
3536 if (LocVT == MVT::i8) {
3537 static const MCPhysReg RegList3[] = {
3538 X86::AL, X86::DL, X86::CL
3539 };
3540 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3541 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3542 return false;
3543 }
3544 }
3545
3546 if (LocVT == MVT::i16) {
3547 static const MCPhysReg RegList4[] = {
3548 X86::AX, X86::DX, X86::CX
3549 };
3550 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3551 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3552 return false;
3553 }
3554 }
3555
3556 if (LocVT == MVT::i32) {
3557 static const MCPhysReg RegList5[] = {
3558 X86::EAX, X86::EDX, X86::ECX
3559 };
3560 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3561 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3562 return false;
3563 }
3564 }
3565
3566 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3567 return false;
3568
3569 return true; // CC didn't match.
3570}
3571
3572
3573static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
3574 MVT LocVT, CCValAssign::LocInfo LocInfo,
3575 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3576
3577 if (LocVT == MVT::i8 ||
3578 LocVT == MVT::i16) {
3579 LocVT = MVT::i32;
3580 if (ArgFlags.isSExt())
3581 LocInfo = CCValAssign::SExt;
3582 else if (ArgFlags.isZExt())
3583 LocInfo = CCValAssign::ZExt;
3584 else
3585 LocInfo = CCValAssign::AExt;
3586 }
3587
3588 if (LocVT == MVT::i32) {
3589 static const MCPhysReg RegList1[] = {
3590 X86::ESI, X86::EBP, X86::EAX, X86::EDX
3591 };
3592 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3593 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3594 return false;
3595 }
3596 }
3597
3598 return true; // CC didn't match.
3599}
3600
3601
3602static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
3603 MVT LocVT, CCValAssign::LocInfo LocInfo,
3604 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3605
3606 if (LocVT == MVT::i1 ||
3607 LocVT == MVT::v1i1 ||
3608 LocVT == MVT::v8i1) {
3609 LocVT = MVT::i8;
3610 if (ArgFlags.isSExt())
3611 LocInfo = CCValAssign::SExt;
3612 else if (ArgFlags.isZExt())
3613 LocInfo = CCValAssign::ZExt;
3614 else
3615 LocInfo = CCValAssign::AExt;
3616 }
3617
3618 if (LocVT == MVT::v16i1) {
3619 LocVT = MVT::i16;
3620 if (ArgFlags.isSExt())
3621 LocInfo = CCValAssign::SExt;
3622 else if (ArgFlags.isZExt())
3623 LocInfo = CCValAssign::ZExt;
3624 else
3625 LocInfo = CCValAssign::AExt;
3626 }
3627
3628 if (LocVT == MVT::v32i1) {
3629 LocVT = MVT::i32;
3630 if (ArgFlags.isSExt())
3631 LocInfo = CCValAssign::SExt;
3632 else if (ArgFlags.isZExt())
3633 LocInfo = CCValAssign::ZExt;
3634 else
3635 LocInfo = CCValAssign::AExt;
3636 }
3637
3638 if (LocVT == MVT::i8) {
3639 static const MCPhysReg RegList1[] = {
3640 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL
3641 };
3642 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3643 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3644 return false;
3645 }
3646 }
3647
3648 if (LocVT == MVT::i16) {
3649 static const MCPhysReg RegList2[] = {
3650 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI
3651 };
3652 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3653 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3654 return false;
3655 }
3656 }
3657
3658 if (LocVT == MVT::i32) {
3659 static const MCPhysReg RegList3[] = {
3660 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
3661 };
3662 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3663 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3664 return false;
3665 }
3666 }
3667
3668 if (LocVT == MVT::i64) {
3669 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3670 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3671 return false;
3672 }
3673 }
3674
3675 if (LocVT == MVT::v64i1) {
3676 LocVT = MVT::i64;
3677 if (ArgFlags.isSExt())
3678 LocInfo = CCValAssign::SExt;
3679 else if (ArgFlags.isZExt())
3680 LocInfo = CCValAssign::ZExt;
3681 else
3682 LocInfo = CCValAssign::AExt;
3683 }
3684
3685 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3686 if (LocVT == MVT::i64) {
3687 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3688 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3689 return false;
3690 }
3691 }
3692 }
3693
3694 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
3695 if (LocVT == MVT::i64) {
3696 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3697 return false;
3698 }
3699 }
3700
3701 if (LocVT == MVT::f80) {
3702 static const MCPhysReg RegList4[] = {
3703 X86::FP0, X86::FP1
3704 };
3705 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3706 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3707 return false;
3708 }
3709 }
3710
3711 if (LocVT == MVT::f32 ||
3712 LocVT == MVT::f64 ||
3713 LocVT == MVT::f128) {
3714 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3715 static const MCPhysReg RegList5[] = {
3716 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3717 };
3718 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3719 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3720 return false;
3721 }
3722 }
3723 }
3724
3725 if (LocVT == MVT::v16i8 ||
3726 LocVT == MVT::v8i16 ||
3727 LocVT == MVT::v4i32 ||
3728 LocVT == MVT::v2i64 ||
3729 LocVT == MVT::v4f32 ||
3730 LocVT == MVT::v2f64) {
3731 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3732 static const MCPhysReg RegList6[] = {
3733 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3734 };
3735 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3736 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3737 return false;
3738 }
3739 }
3740 }
3741
3742 if (LocVT == MVT::v32i8 ||
3743 LocVT == MVT::v16i16 ||
3744 LocVT == MVT::v8i32 ||
3745 LocVT == MVT::v4i64 ||
3746 LocVT == MVT::v8f32 ||
3747 LocVT == MVT::v4f64) {
3748 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
3749 static const MCPhysReg RegList7[] = {
3750 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3751 };
3752 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3753 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3754 return false;
3755 }
3756 }
3757 }
3758
3759 if (LocVT == MVT::v64i8 ||
3760 LocVT == MVT::v32i16 ||
3761 LocVT == MVT::v16i32 ||
3762 LocVT == MVT::v8i64 ||
3763 LocVT == MVT::v16f32 ||
3764 LocVT == MVT::v8f64) {
3765 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
3766 static const MCPhysReg RegList8[] = {
3767 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3768 };
3769 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
3770 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3771 return false;
3772 }
3773 }
3774 }
3775
3776 return true; // CC didn't match.
3777}
3778
3779
3780static bool RetCC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
3781 MVT LocVT, CCValAssign::LocInfo LocInfo,
3782 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3783
3784 if (LocVT == MVT::i1 ||
3785 LocVT == MVT::v1i1 ||
3786 LocVT == MVT::v8i1) {
3787 LocVT = MVT::i8;
3788 if (ArgFlags.isSExt())
3789 LocInfo = CCValAssign::SExt;
3790 else if (ArgFlags.isZExt())
3791 LocInfo = CCValAssign::ZExt;
3792 else
3793 LocInfo = CCValAssign::AExt;
3794 }
3795
3796 if (LocVT == MVT::v16i1) {
3797 LocVT = MVT::i16;
3798 if (ArgFlags.isSExt())
3799 LocInfo = CCValAssign::SExt;
3800 else if (ArgFlags.isZExt())
3801 LocInfo = CCValAssign::ZExt;
3802 else
3803 LocInfo = CCValAssign::AExt;
3804 }
3805
3806 if (LocVT == MVT::v32i1) {
3807 LocVT = MVT::i32;
3808 if (ArgFlags.isSExt())
3809 LocInfo = CCValAssign::SExt;
3810 else if (ArgFlags.isZExt())
3811 LocInfo = CCValAssign::ZExt;
3812 else
3813 LocInfo = CCValAssign::AExt;
3814 }
3815
3816 if (LocVT == MVT::i8) {
3817 static const MCPhysReg RegList1[] = {
3818 X86::CL, X86::DL, X86::DIL, X86::SIL
3819 };
3820 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3821 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3822 return false;
3823 }
3824 }
3825
3826 if (LocVT == MVT::i16) {
3827 static const MCPhysReg RegList2[] = {
3828 X86::CX, X86::DX, X86::DI, X86::SI
3829 };
3830 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3831 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3832 return false;
3833 }
3834 }
3835
3836 if (LocVT == MVT::i32) {
3837 static const MCPhysReg RegList3[] = {
3838 X86::ECX, X86::EDX, X86::EDI, X86::ESI
3839 };
3840 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3841 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3842 return false;
3843 }
3844 }
3845
3846 if (LocVT == MVT::i64) {
3847 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3848 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3849 return false;
3850 }
3851 }
3852
3853 if (LocVT == MVT::v64i1) {
3854 LocVT = MVT::i64;
3855 if (ArgFlags.isSExt())
3856 LocInfo = CCValAssign::SExt;
3857 else if (ArgFlags.isZExt())
3858 LocInfo = CCValAssign::ZExt;
3859 else
3860 LocInfo = CCValAssign::AExt;
3861 }
3862
3863 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3864 if (LocVT == MVT::i64) {
3865 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3866 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3867 return false;
3868 }
3869 }
3870 }
3871
3872 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
3873 if (LocVT == MVT::i64) {
3874 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3875 return false;
3876 }
3877 }
3878
3879 if (LocVT == MVT::f80) {
3880 static const MCPhysReg RegList4[] = {
3881 X86::FP0, X86::FP1
3882 };
3883 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3884 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3885 return false;
3886 }
3887 }
3888
3889 if (LocVT == MVT::f32 ||
3890 LocVT == MVT::f64 ||
3891 LocVT == MVT::f128) {
3892 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3893 static const MCPhysReg RegList5[] = {
3894 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3895 };
3896 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3897 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3898 return false;
3899 }
3900 }
3901 }
3902
3903 if (LocVT == MVT::v16i8 ||
3904 LocVT == MVT::v8i16 ||
3905 LocVT == MVT::v4i32 ||
3906 LocVT == MVT::v2i64 ||
3907 LocVT == MVT::v4f32 ||
3908 LocVT == MVT::v2f64) {
3909 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3910 static const MCPhysReg RegList6[] = {
3911 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3912 };
3913 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3914 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3915 return false;
3916 }
3917 }
3918 }
3919
3920 if (LocVT == MVT::v32i8 ||
3921 LocVT == MVT::v16i16 ||
3922 LocVT == MVT::v8i32 ||
3923 LocVT == MVT::v4i64 ||
3924 LocVT == MVT::v8f32 ||
3925 LocVT == MVT::v4f64) {
3926 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
3927 static const MCPhysReg RegList7[] = {
3928 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3929 };
3930 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3931 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3932 return false;
3933 }
3934 }
3935 }
3936
3937 if (LocVT == MVT::v64i8 ||
3938 LocVT == MVT::v32i16 ||
3939 LocVT == MVT::v16i32 ||
3940 LocVT == MVT::v8i64 ||
3941 LocVT == MVT::v16f32 ||
3942 LocVT == MVT::v8f64) {
3943 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
3944 static const MCPhysReg RegList8[] = {
3945 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3946 };
3947 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
3948 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3949 return false;
3950 }
3951 }
3952 }
3953
3954 return true; // CC didn't match.
3955}
3956
3957
3958static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
3959 MVT LocVT, CCValAssign::LocInfo LocInfo,
3960 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3961
3962 if (LocVT == MVT::f32 ||
3963 LocVT == MVT::f64 ||
3964 LocVT == MVT::f128) {
3965 static const MCPhysReg RegList1[] = {
3966 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3967 };
3968 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3969 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3970 return false;
3971 }
3972 }
3973
3974 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3975 return false;
3976
3977 return true; // CC didn't match.
3978}
3979
3980
3981static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
3982 MVT LocVT, CCValAssign::LocInfo LocInfo,
3983 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3984
3985 if (State.getCallingConv() == CallingConv::HiPE) {
3986 if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3987 return false;
3988 }
3989
3990 if (State.getCallingConv() == CallingConv::AnyReg) {
3991 if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3992 return false;
3993 }
3994
3995 if (State.getCallingConv() == CallingConv::Swift) {
3996 if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3997 return false;
3998 }
3999
4000 if (State.getCallingConv() == CallingConv::SwiftTail) {
4001 if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4002 return false;
4003 }
4004
4005 if (State.getCallingConv() == CallingConv::Win64) {
4006 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4007 return false;
4008 }
4009
4010 if (State.getCallingConv() == CallingConv::X86_64_SysV) {
4011 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4012 return false;
4013 }
4014
4015 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
4016 if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4017 return false;
4018 }
4019
4020 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4021 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
4022 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
4023 if (!RetCC_X86_Win64_RegCallv4(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4024 return false;
4025 }
4026 }
4027 }
4028
4029 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4030 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
4031 if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4032 return false;
4033 }
4034 }
4035
4036 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4037 if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4038 return false;
4039 }
4040
4041 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
4042 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4043 return false;
4044 }
4045
4046 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetUEFI64()) {
4047 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4048 return false;
4049 }
4050
4051 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4052 return false;
4053
4054 return true; // CC didn't match.
4055}
4056
4057
4058static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
4059 MVT LocVT, CCValAssign::LocInfo LocInfo,
4060 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4061
4062 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4063 return false;
4064
4065 return true; // CC didn't match.
4066}
4067
4068
4069static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
4070 MVT LocVT, CCValAssign::LocInfo LocInfo,
4071 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4072
4073 if (LocVT == MVT::f16) {
4074 static const MCPhysReg RegList1[] = {
4075 X86::XMM0, X86::XMM1
4076 };
4077 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4078 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4079 return false;
4080 }
4081 }
4082
4083 if (LocVT == MVT::f32) {
4084 static const MCPhysReg RegList2[] = {
4085 X86::XMM0, X86::XMM1
4086 };
4087 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4088 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4089 return false;
4090 }
4091 }
4092
4093 if (LocVT == MVT::f64) {
4094 static const MCPhysReg RegList3[] = {
4095 X86::XMM0, X86::XMM1
4096 };
4097 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4098 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4099 return false;
4100 }
4101 }
4102
4103 if (LocVT == MVT::f128) {
4104 static const MCPhysReg RegList4[] = {
4105 X86::XMM0, X86::XMM1
4106 };
4107 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4108 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4109 return false;
4110 }
4111 }
4112
4113 if (ArgFlags.isPointer()) {
4114 if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4115 return false;
4116 }
4117
4118 if (ArgFlags.isSwiftError()) {
4119 if (LocVT == MVT::i64) {
4120 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
4121 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4122 return false;
4123 }
4124 }
4125 }
4126
4127 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4128 return false;
4129
4130 return true; // CC didn't match.
4131}
4132
4133
4134static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
4135 MVT LocVT, CCValAssign::LocInfo LocInfo,
4136 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4137
4138 if (LocVT == MVT::i8 ||
4139 LocVT == MVT::i16 ||
4140 LocVT == MVT::i32) {
4141 LocVT = MVT::i64;
4142 if (ArgFlags.isSExt())
4143 LocInfo = CCValAssign::SExt;
4144 else if (ArgFlags.isZExt())
4145 LocInfo = CCValAssign::ZExt;
4146 else
4147 LocInfo = CCValAssign::AExt;
4148 }
4149
4150 if (LocVT == MVT::i64) {
4151 static const MCPhysReg RegList1[] = {
4152 X86::R15, X86::RBP, X86::RAX, X86::RDX
4153 };
4154 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4155 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4156 return false;
4157 }
4158 }
4159
4160 return true; // CC didn't match.
4161}
4162
4163
4164static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
4165 MVT LocVT, CCValAssign::LocInfo LocInfo,
4166 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4167
4168 if (ArgFlags.isSwiftError()) {
4169 if (LocVT == MVT::i64) {
4170 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
4171 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4172 return false;
4173 }
4174 }
4175 }
4176
4177 if (LocVT == MVT::v1i1) {
4178 LocVT = MVT::i8;
4179 if (ArgFlags.isSExt())
4180 LocInfo = CCValAssign::SExt;
4181 else if (ArgFlags.isZExt())
4182 LocInfo = CCValAssign::ZExt;
4183 else
4184 LocInfo = CCValAssign::AExt;
4185 }
4186
4187 if (LocVT == MVT::i1) {
4188 LocVT = MVT::i8;
4189 if (ArgFlags.isSExt())
4190 LocInfo = CCValAssign::SExt;
4191 else if (ArgFlags.isZExt())
4192 LocInfo = CCValAssign::ZExt;
4193 else
4194 LocInfo = CCValAssign::AExt;
4195 }
4196
4197 if (LocVT == MVT::i8) {
4198 static const MCPhysReg RegList1[] = {
4199 X86::AL, X86::DL, X86::CL, X86::R8B
4200 };
4201 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4202 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4203 return false;
4204 }
4205 }
4206
4207 if (LocVT == MVT::i16) {
4208 static const MCPhysReg RegList2[] = {
4209 X86::AX, X86::DX, X86::CX, X86::R8W
4210 };
4211 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4212 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4213 return false;
4214 }
4215 }
4216
4217 if (LocVT == MVT::i32) {
4218 static const MCPhysReg RegList3[] = {
4219 X86::EAX, X86::EDX, X86::ECX, X86::R8D
4220 };
4221 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4222 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4223 return false;
4224 }
4225 }
4226
4227 if (LocVT == MVT::i64) {
4228 static const MCPhysReg RegList4[] = {
4229 X86::RAX, X86::RDX, X86::RCX, X86::R8
4230 };
4231 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4232 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4233 return false;
4234 }
4235 }
4236
4237 if (LocVT == MVT::f32) {
4238 static const MCPhysReg RegList5[] = {
4239 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4240 };
4241 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4242 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4243 return false;
4244 }
4245 }
4246
4247 if (LocVT == MVT::f64) {
4248 static const MCPhysReg RegList6[] = {
4249 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4250 };
4251 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4252 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4253 return false;
4254 }
4255 }
4256
4257 if (LocVT == MVT::f128) {
4258 static const MCPhysReg RegList7[] = {
4259 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4260 };
4261 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4262 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4263 return false;
4264 }
4265 }
4266
4267 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4268 return false;
4269
4270 return true; // CC didn't match.
4271}
4272
4273
4274static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
4275 MVT LocVT, CCValAssign::LocInfo LocInfo,
4276 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4277
4278 if (LocVT == MVT::f32 ||
4279 LocVT == MVT::f64 ||
4280 LocVT == MVT::f128) {
4281 static const MCPhysReg RegList1[] = {
4282 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4283 };
4284 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4285 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4286 return false;
4287 }
4288 }
4289
4290 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4291 return false;
4292
4293 return true; // CC didn't match.
4294}
4295
4296
4297static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
4298 MVT LocVT, CCValAssign::LocInfo LocInfo,
4299 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4300
4301 if (LocVT == MVT::i1 ||
4302 LocVT == MVT::v1i1 ||
4303 LocVT == MVT::v8i1) {
4304 LocVT = MVT::i8;
4305 if (ArgFlags.isSExt())
4306 LocInfo = CCValAssign::SExt;
4307 else if (ArgFlags.isZExt())
4308 LocInfo = CCValAssign::ZExt;
4309 else
4310 LocInfo = CCValAssign::AExt;
4311 }
4312
4313 if (LocVT == MVT::v16i1) {
4314 LocVT = MVT::i16;
4315 if (ArgFlags.isSExt())
4316 LocInfo = CCValAssign::SExt;
4317 else if (ArgFlags.isZExt())
4318 LocInfo = CCValAssign::ZExt;
4319 else
4320 LocInfo = CCValAssign::AExt;
4321 }
4322
4323 if (LocVT == MVT::v32i1) {
4324 LocVT = MVT::i32;
4325 if (ArgFlags.isSExt())
4326 LocInfo = CCValAssign::SExt;
4327 else if (ArgFlags.isZExt())
4328 LocInfo = CCValAssign::ZExt;
4329 else
4330 LocInfo = CCValAssign::AExt;
4331 }
4332
4333 if (LocVT == MVT::i8) {
4334 static const MCPhysReg RegList1[] = {
4335 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B
4336 };
4337 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4338 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4339 return false;
4340 }
4341 }
4342
4343 if (LocVT == MVT::i16) {
4344 static const MCPhysReg RegList2[] = {
4345 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W
4346 };
4347 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4348 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4349 return false;
4350 }
4351 }
4352
4353 if (LocVT == MVT::i32) {
4354 static const MCPhysReg RegList3[] = {
4355 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
4356 };
4357 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4358 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4359 return false;
4360 }
4361 }
4362
4363 if (LocVT == MVT::i64) {
4364 static const MCPhysReg RegList4[] = {
4365 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
4366 };
4367 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4368 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4369 return false;
4370 }
4371 }
4372
4373 if (LocVT == MVT::v64i1) {
4374 LocVT = MVT::i64;
4375 if (ArgFlags.isSExt())
4376 LocInfo = CCValAssign::SExt;
4377 else if (ArgFlags.isZExt())
4378 LocInfo = CCValAssign::ZExt;
4379 else
4380 LocInfo = CCValAssign::AExt;
4381 }
4382
4383 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
4384 if (LocVT == MVT::i64) {
4385 static const MCPhysReg RegList5[] = {
4386 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
4387 };
4388 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4389 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4390 return false;
4391 }
4392 }
4393 }
4394
4395 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
4396 if (LocVT == MVT::i64) {
4397 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4398 return false;
4399 }
4400 }
4401
4402 if (LocVT == MVT::f80) {
4403 static const MCPhysReg RegList6[] = {
4404 X86::FP0, X86::FP1
4405 };
4406 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4407 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4408 return false;
4409 }
4410 }
4411
4412 if (LocVT == MVT::f32 ||
4413 LocVT == MVT::f64 ||
4414 LocVT == MVT::f128) {
4415 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4416 static const MCPhysReg RegList7[] = {
4417 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4418 };
4419 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4420 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4421 return false;
4422 }
4423 }
4424 }
4425
4426 if (LocVT == MVT::v16i8 ||
4427 LocVT == MVT::v8i16 ||
4428 LocVT == MVT::v4i32 ||
4429 LocVT == MVT::v2i64 ||
4430 LocVT == MVT::v4f32 ||
4431 LocVT == MVT::v2f64) {
4432 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4433 static const MCPhysReg RegList8[] = {
4434 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4435 };
4436 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
4437 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4438 return false;
4439 }
4440 }
4441 }
4442
4443 if (LocVT == MVT::v32i8 ||
4444 LocVT == MVT::v16i16 ||
4445 LocVT == MVT::v8i32 ||
4446 LocVT == MVT::v4i64 ||
4447 LocVT == MVT::v8f32 ||
4448 LocVT == MVT::v4f64) {
4449 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
4450 static const MCPhysReg RegList9[] = {
4451 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4452 };
4453 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
4454 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4455 return false;
4456 }
4457 }
4458 }
4459
4460 if (LocVT == MVT::v64i8 ||
4461 LocVT == MVT::v32i16 ||
4462 LocVT == MVT::v16i32 ||
4463 LocVT == MVT::v8i64 ||
4464 LocVT == MVT::v16f32 ||
4465 LocVT == MVT::v8f64) {
4466 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
4467 static const MCPhysReg RegList10[] = {
4468 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4469 };
4470 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
4471 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4472 return false;
4473 }
4474 }
4475 }
4476
4477 return true; // CC didn't match.
4478}
4479
4480
4481static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
4482 MVT LocVT, CCValAssign::LocInfo LocInfo,
4483 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4484
4485 if (LocVT == MVT::f32) {
4486 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4487 LocVT = MVT::i32;
4488 LocInfo = CCValAssign::BCvt;
4489 }
4490 }
4491
4492 if (LocVT == MVT::f64) {
4493 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4494 LocVT = MVT::i64;
4495 LocInfo = CCValAssign::BCvt;
4496 }
4497 }
4498
4499 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4500 return false;
4501
4502 return true; // CC didn't match.
4503}
4504
4505
4506static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
4507 MVT LocVT, CCValAssign::LocInfo LocInfo,
4508 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4509
4510 if (LocVT == MVT::i1 ||
4511 LocVT == MVT::v1i1 ||
4512 LocVT == MVT::v8i1) {
4513 LocVT = MVT::i8;
4514 if (ArgFlags.isSExt())
4515 LocInfo = CCValAssign::SExt;
4516 else if (ArgFlags.isZExt())
4517 LocInfo = CCValAssign::ZExt;
4518 else
4519 LocInfo = CCValAssign::AExt;
4520 }
4521
4522 if (LocVT == MVT::v16i1) {
4523 LocVT = MVT::i16;
4524 if (ArgFlags.isSExt())
4525 LocInfo = CCValAssign::SExt;
4526 else if (ArgFlags.isZExt())
4527 LocInfo = CCValAssign::ZExt;
4528 else
4529 LocInfo = CCValAssign::AExt;
4530 }
4531
4532 if (LocVT == MVT::v32i1) {
4533 LocVT = MVT::i32;
4534 if (ArgFlags.isSExt())
4535 LocInfo = CCValAssign::SExt;
4536 else if (ArgFlags.isZExt())
4537 LocInfo = CCValAssign::ZExt;
4538 else
4539 LocInfo = CCValAssign::AExt;
4540 }
4541
4542 if (LocVT == MVT::i8) {
4543 static const MCPhysReg RegList1[] = {
4544 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
4545 };
4546 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4547 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4548 return false;
4549 }
4550 }
4551
4552 if (LocVT == MVT::i16) {
4553 static const MCPhysReg RegList2[] = {
4554 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
4555 };
4556 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4557 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4558 return false;
4559 }
4560 }
4561
4562 if (LocVT == MVT::i32) {
4563 static const MCPhysReg RegList3[] = {
4564 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
4565 };
4566 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4567 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4568 return false;
4569 }
4570 }
4571
4572 if (LocVT == MVT::i64) {
4573 static const MCPhysReg RegList4[] = {
4574 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
4575 };
4576 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4577 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4578 return false;
4579 }
4580 }
4581
4582 if (LocVT == MVT::v64i1) {
4583 LocVT = MVT::i64;
4584 if (ArgFlags.isSExt())
4585 LocInfo = CCValAssign::SExt;
4586 else if (ArgFlags.isZExt())
4587 LocInfo = CCValAssign::ZExt;
4588 else
4589 LocInfo = CCValAssign::AExt;
4590 }
4591
4592 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
4593 if (LocVT == MVT::i64) {
4594 static const MCPhysReg RegList5[] = {
4595 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
4596 };
4597 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4598 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4599 return false;
4600 }
4601 }
4602 }
4603
4604 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
4605 if (LocVT == MVT::i64) {
4606 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4607 return false;
4608 }
4609 }
4610
4611 if (LocVT == MVT::f80) {
4612 static const MCPhysReg RegList6[] = {
4613 X86::FP0, X86::FP1
4614 };
4615 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4616 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4617 return false;
4618 }
4619 }
4620
4621 if (LocVT == MVT::f32 ||
4622 LocVT == MVT::f64 ||
4623 LocVT == MVT::f128) {
4624 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4625 static const MCPhysReg RegList7[] = {
4626 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4627 };
4628 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4629 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4630 return false;
4631 }
4632 }
4633 }
4634
4635 if (LocVT == MVT::v16i8 ||
4636 LocVT == MVT::v8i16 ||
4637 LocVT == MVT::v4i32 ||
4638 LocVT == MVT::v2i64 ||
4639 LocVT == MVT::v4f32 ||
4640 LocVT == MVT::v2f64) {
4641 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4642 static const MCPhysReg RegList8[] = {
4643 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4644 };
4645 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
4646 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4647 return false;
4648 }
4649 }
4650 }
4651
4652 if (LocVT == MVT::v32i8 ||
4653 LocVT == MVT::v16i16 ||
4654 LocVT == MVT::v8i32 ||
4655 LocVT == MVT::v4i64 ||
4656 LocVT == MVT::v8f32 ||
4657 LocVT == MVT::v4f64) {
4658 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
4659 static const MCPhysReg RegList9[] = {
4660 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4661 };
4662 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
4663 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4664 return false;
4665 }
4666 }
4667 }
4668
4669 if (LocVT == MVT::v64i8 ||
4670 LocVT == MVT::v32i16 ||
4671 LocVT == MVT::v16i32 ||
4672 LocVT == MVT::v8i64 ||
4673 LocVT == MVT::v16f32 ||
4674 LocVT == MVT::v8f64) {
4675 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
4676 static const MCPhysReg RegList10[] = {
4677 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4678 };
4679 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
4680 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4681 return false;
4682 }
4683 }
4684 }
4685
4686 return true; // CC didn't match.
4687}
4688
4689
4690static bool RetCC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
4691 MVT LocVT, CCValAssign::LocInfo LocInfo,
4692 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4693
4694 if (LocVT == MVT::i1 ||
4695 LocVT == MVT::v1i1 ||
4696 LocVT == MVT::v8i1) {
4697 LocVT = MVT::i8;
4698 if (ArgFlags.isSExt())
4699 LocInfo = CCValAssign::SExt;
4700 else if (ArgFlags.isZExt())
4701 LocInfo = CCValAssign::ZExt;
4702 else
4703 LocInfo = CCValAssign::AExt;
4704 }
4705
4706 if (LocVT == MVT::v16i1) {
4707 LocVT = MVT::i16;
4708 if (ArgFlags.isSExt())
4709 LocInfo = CCValAssign::SExt;
4710 else if (ArgFlags.isZExt())
4711 LocInfo = CCValAssign::ZExt;
4712 else
4713 LocInfo = CCValAssign::AExt;
4714 }
4715
4716 if (LocVT == MVT::v32i1) {
4717 LocVT = MVT::i32;
4718 if (ArgFlags.isSExt())
4719 LocInfo = CCValAssign::SExt;
4720 else if (ArgFlags.isZExt())
4721 LocInfo = CCValAssign::ZExt;
4722 else
4723 LocInfo = CCValAssign::AExt;
4724 }
4725
4726 if (LocVT == MVT::i8) {
4727 static const MCPhysReg RegList1[] = {
4728 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
4729 };
4730 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4731 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4732 return false;
4733 }
4734 }
4735
4736 if (LocVT == MVT::i16) {
4737 static const MCPhysReg RegList2[] = {
4738 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
4739 };
4740 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4741 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4742 return false;
4743 }
4744 }
4745
4746 if (LocVT == MVT::i32) {
4747 static const MCPhysReg RegList3[] = {
4748 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
4749 };
4750 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4751 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4752 return false;
4753 }
4754 }
4755
4756 if (LocVT == MVT::i64) {
4757 static const MCPhysReg RegList4[] = {
4758 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
4759 };
4760 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4761 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4762 return false;
4763 }
4764 }
4765
4766 if (LocVT == MVT::v64i1) {
4767 LocVT = MVT::i64;
4768 if (ArgFlags.isSExt())
4769 LocInfo = CCValAssign::SExt;
4770 else if (ArgFlags.isZExt())
4771 LocInfo = CCValAssign::ZExt;
4772 else
4773 LocInfo = CCValAssign::AExt;
4774 }
4775
4776 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
4777 if (LocVT == MVT::i64) {
4778 static const MCPhysReg RegList5[] = {
4779 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
4780 };
4781 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4782 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4783 return false;
4784 }
4785 }
4786 }
4787
4788 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
4789 if (LocVT == MVT::i64) {
4790 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4791 return false;
4792 }
4793 }
4794
4795 if (LocVT == MVT::f80) {
4796 static const MCPhysReg RegList6[] = {
4797 X86::FP0, X86::FP1
4798 };
4799 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4800 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4801 return false;
4802 }
4803 }
4804
4805 if (LocVT == MVT::f32 ||
4806 LocVT == MVT::f64 ||
4807 LocVT == MVT::f128) {
4808 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4809 static const MCPhysReg RegList7[] = {
4810 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4811 };
4812 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4813 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4814 return false;
4815 }
4816 }
4817 }
4818
4819 if (LocVT == MVT::v16i8 ||
4820 LocVT == MVT::v8i16 ||
4821 LocVT == MVT::v4i32 ||
4822 LocVT == MVT::v2i64 ||
4823 LocVT == MVT::v4f32 ||
4824 LocVT == MVT::v2f64) {
4825 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4826 static const MCPhysReg RegList8[] = {
4827 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4828 };
4829 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
4830 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4831 return false;
4832 }
4833 }
4834 }
4835
4836 if (LocVT == MVT::v32i8 ||
4837 LocVT == MVT::v16i16 ||
4838 LocVT == MVT::v8i32 ||
4839 LocVT == MVT::v4i64 ||
4840 LocVT == MVT::v8f32 ||
4841 LocVT == MVT::v4f64) {
4842 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
4843 static const MCPhysReg RegList9[] = {
4844 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4845 };
4846 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
4847 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4848 return false;
4849 }
4850 }
4851 }
4852
4853 if (LocVT == MVT::v64i8 ||
4854 LocVT == MVT::v32i16 ||
4855 LocVT == MVT::v16i32 ||
4856 LocVT == MVT::v8i64 ||
4857 LocVT == MVT::v16f32 ||
4858 LocVT == MVT::v8f64) {
4859 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
4860 static const MCPhysReg RegList10[] = {
4861 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4862 };
4863 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
4864 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4865 return false;
4866 }
4867 }
4868 }
4869
4870 return true; // CC didn't match.
4871}
4872
4873#else
4874
4875const MCRegister CC_Intel_OCL_BI_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::K1, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4876const MCRegister CC_X86_ArgRegs[] = { 0 };
4877const MCRegister CC_X86_32_ArgRegs[] = { 0 };
4878const MCRegister CC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX };
4879const MCRegister CC_X86_32_Common_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2 };
4880const MCRegister CC_X86_32_FastCC_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 };
4881const MCRegister CC_X86_32_FastCall_ArgRegs[] = { X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX };
4882const MCRegister CC_X86_32_GHC_ArgRegs[] = { X86::EBP, X86::EBX, X86::EDI, X86::ESI };
4883const MCRegister CC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::ECX, X86::EDX, X86::ESI };
4884const MCRegister CC_X86_32_MCU_ArgRegs[] = { 0 };
4885const MCRegister CC_X86_32_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::RAX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4886const MCRegister CC_X86_32_RegCallv4_Win_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::RAX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4887const MCRegister CC_X86_32_ThisCall_ArgRegs[] = { 0 };
4888const MCRegister CC_X86_32_ThisCall_Common_ArgRegs[] = { X86::ECX };
4889const MCRegister CC_X86_32_ThisCall_Mingw_ArgRegs[] = { 0 };
4890const MCRegister CC_X86_32_ThisCall_Win_ArgRegs[] = { 0 };
4891const MCRegister CC_X86_32_Vector_Common_ArgRegs[] = { 0 };
4892const MCRegister CC_X86_32_Vector_Darwin_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4893const MCRegister CC_X86_32_Vector_Standard_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::YMM0, X86::YMM1, X86::YMM2, X86::ZMM0, X86::ZMM1, X86::ZMM2 };
4894const MCRegister CC_X86_64_ArgRegs[] = { 0 };
4895const MCRegister CC_X86_64_AnyReg_ArgRegs[] = { 0 };
4896const MCRegister CC_X86_64_C_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::R10, X86::R10D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4897const MCRegister CC_X86_64_GHC_ArgRegs[] = { X86::R12, X86::R13, X86::R14, X86::R15, X86::R8, X86::R9, X86::RBP, X86::RBX, X86::RDI, X86::RSI, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6 };
4898const MCRegister CC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::R8, X86::RBP, X86::RCX, X86::RDX, X86::RSI };
4899const MCRegister CC_X86_64_Preserve_None_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R13, X86::R13D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI };
4900const MCRegister CC_X86_SysV64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R12, X86::R12D, X86::R13, X86::R13D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4901const MCRegister CC_X86_Win32_CFGuard_Check_ArgRegs[] = { X86::ECX };
4902const MCRegister CC_X86_Win32_Vector_ArgRegs[] = { 0 };
4903const MCRegister CC_X86_Win32_VectorCall_ArgRegs[] = { 0 };
4904const MCRegister CC_X86_Win64_C_ArgRegs[] = { X86::R10, X86::RAX };
4905const MCRegister CC_X86_Win64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R10, X86::R10D, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4906const MCRegister CC_X86_Win64_RegCallv4_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4907const MCRegister CC_X86_Win64_VectorCall_ArgRegs[] = { 0 };
4908const MCRegister RetCC_Intel_OCL_BI_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4909const MCRegister RetCC_X86_ArgRegs[] = { 0 };
4910const MCRegister RetCC_X86Common_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4911const MCRegister RetCC_X86_32_ArgRegs[] = { 0 };
4912const MCRegister RetCC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::XMM0, X86::XMM1, X86::XMM2 };
4913const MCRegister RetCC_X86_32_Fast_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 };
4914const MCRegister RetCC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::EDX, X86::ESI };
4915const MCRegister RetCC_X86_32_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::RAX, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4916const MCRegister RetCC_X86_32_RegCallv4_Win_ArgRegs[] = { X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::RAX, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4917const MCRegister RetCC_X86_32_VectorCall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4918const MCRegister RetCC_X86_64_ArgRegs[] = { 0 };
4919const MCRegister RetCC_X86_64_AnyReg_ArgRegs[] = { 0 };
4920const MCRegister RetCC_X86_64_C_ArgRegs[] = { X86::XMM0, X86::XMM1 };
4921const MCRegister RetCC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::RAX, X86::RBP, X86::RDX };
4922const MCRegister RetCC_X86_64_Swift_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4923const MCRegister RetCC_X86_64_Vectorcall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4924const MCRegister RetCC_X86_SysV64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R13, X86::R13B, X86::R13D, X86::R13W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4925const MCRegister RetCC_X86_Win64_C_ArgRegs[] = { 0 };
4926const MCRegister RetCC_X86_Win64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R10, X86::R10B, X86::R10D, X86::R10W, X86::R11, X86::R11B, X86::R11D, X86::R11W, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4927const MCRegister RetCC_X86_Win64_RegCallv4_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R11, X86::R11B, X86::R11D, X86::R11W, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4928
4929// Registers used by Swift.
4930const MCRegister CC_X86_64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 };
4931const MCRegister CC_X86_Win64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 };
4932const MCRegister RetCC_X86_64_C_Swift_ArgRegs[] = { X86::R12 };
4933const MCRegister RetCC_X86_64_Swift_Swift_ArgRegs[] = { X86::R12 };
4934
4935#endif // !defined(GET_CC_REGISTER_LISTS)
4936
4937