1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_CALLING_CONV_IMPL
10#undef GET_CALLING_CONV_IMPL
11
12static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
13 MVT LocVT, CCValAssign::LocInfo LocInfo,
14 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
15bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
16 MVT LocVT, CCValAssign::LocInfo LocInfo,
17 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
18static bool CC_X86_32(unsigned ValNo, MVT ValVT,
19 MVT LocVT, CCValAssign::LocInfo LocInfo,
20 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
21static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
22 MVT LocVT, CCValAssign::LocInfo LocInfo,
23 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
24static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
25 MVT LocVT, CCValAssign::LocInfo LocInfo,
26 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
27static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
28 MVT LocVT, CCValAssign::LocInfo LocInfo,
29 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
30static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
31 MVT LocVT, CCValAssign::LocInfo LocInfo,
32 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
33static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
34 MVT LocVT, CCValAssign::LocInfo LocInfo,
35 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
36static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
37 MVT LocVT, CCValAssign::LocInfo LocInfo,
38 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
39static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
40 MVT LocVT, CCValAssign::LocInfo LocInfo,
41 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
42static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
43 MVT LocVT, CCValAssign::LocInfo LocInfo,
44 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
45static bool CC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
46 MVT LocVT, CCValAssign::LocInfo LocInfo,
47 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
48static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
49 MVT LocVT, CCValAssign::LocInfo LocInfo,
50 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
51static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
52 MVT LocVT, CCValAssign::LocInfo LocInfo,
53 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
54static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
55 MVT LocVT, CCValAssign::LocInfo LocInfo,
56 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
57static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
58 MVT LocVT, CCValAssign::LocInfo LocInfo,
59 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
60static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
61 MVT LocVT, CCValAssign::LocInfo LocInfo,
62 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
63static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
64 MVT LocVT, CCValAssign::LocInfo LocInfo,
65 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
66static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
67 MVT LocVT, CCValAssign::LocInfo LocInfo,
68 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
69static bool CC_X86_64(unsigned ValNo, MVT ValVT,
70 MVT LocVT, CCValAssign::LocInfo LocInfo,
71 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
72static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
73 MVT LocVT, CCValAssign::LocInfo LocInfo,
74 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
75static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
76 MVT LocVT, CCValAssign::LocInfo LocInfo,
77 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
78static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
79 MVT LocVT, CCValAssign::LocInfo LocInfo,
80 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
81static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
82 MVT LocVT, CCValAssign::LocInfo LocInfo,
83 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
84static bool CC_X86_64_Preserve_None(unsigned ValNo, MVT ValVT,
85 MVT LocVT, CCValAssign::LocInfo LocInfo,
86 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
87static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
88 MVT LocVT, CCValAssign::LocInfo LocInfo,
89 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
90static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
91 MVT LocVT, CCValAssign::LocInfo LocInfo,
92 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
93static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT,
94 MVT LocVT, CCValAssign::LocInfo LocInfo,
95 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
96static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
97 MVT LocVT, CCValAssign::LocInfo LocInfo,
98 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
99static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
100 MVT LocVT, CCValAssign::LocInfo LocInfo,
101 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
102static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
103 MVT LocVT, CCValAssign::LocInfo LocInfo,
104 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
105static bool CC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
106 MVT LocVT, CCValAssign::LocInfo LocInfo,
107 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
108static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
109 MVT LocVT, CCValAssign::LocInfo LocInfo,
110 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
111static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
112 MVT LocVT, CCValAssign::LocInfo LocInfo,
113 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
114bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
115 MVT LocVT, CCValAssign::LocInfo LocInfo,
116 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
117static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
118 MVT LocVT, CCValAssign::LocInfo LocInfo,
119 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
120static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
121 MVT LocVT, CCValAssign::LocInfo LocInfo,
122 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
123static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
124 MVT LocVT, CCValAssign::LocInfo LocInfo,
125 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
126static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
127 MVT LocVT, CCValAssign::LocInfo LocInfo,
128 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
129static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
130 MVT LocVT, CCValAssign::LocInfo LocInfo,
131 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
132static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
133 MVT LocVT, CCValAssign::LocInfo LocInfo,
134 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
135static bool RetCC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
136 MVT LocVT, CCValAssign::LocInfo LocInfo,
137 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
138static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
139 MVT LocVT, CCValAssign::LocInfo LocInfo,
140 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
141static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
142 MVT LocVT, CCValAssign::LocInfo LocInfo,
143 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
144static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
145 MVT LocVT, CCValAssign::LocInfo LocInfo,
146 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
147static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
148 MVT LocVT, CCValAssign::LocInfo LocInfo,
149 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
150static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
151 MVT LocVT, CCValAssign::LocInfo LocInfo,
152 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
153static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
154 MVT LocVT, CCValAssign::LocInfo LocInfo,
155 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
156static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
157 MVT LocVT, CCValAssign::LocInfo LocInfo,
158 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
159static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
160 MVT LocVT, CCValAssign::LocInfo LocInfo,
161 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
162static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
163 MVT LocVT, CCValAssign::LocInfo LocInfo,
164 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
165static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
166 MVT LocVT, CCValAssign::LocInfo LocInfo,
167 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
168static bool RetCC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
169 MVT LocVT, CCValAssign::LocInfo LocInfo,
170 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
171
172
173static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
174 MVT LocVT, CCValAssign::LocInfo LocInfo,
175 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
176
177 if (LocVT == MVT::i32) {
178 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
179 static const MCPhysReg RegList1[] = {
180 X86::ECX, X86::EDX, X86::R8D, X86::R9D
181 };
182 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
183 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
184 return false;
185 }
186 }
187 }
188
189 if (LocVT == MVT::i64) {
190 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
191 static const MCPhysReg RegList2[] = {
192 X86::RCX, X86::RDX, X86::R8, X86::R9
193 };
194 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
195 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
196 return false;
197 }
198 }
199 }
200
201 if (LocVT == MVT::i32) {
202 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
203 static const MCPhysReg RegList3[] = {
204 X86::EDI, X86::ESI, X86::EDX, X86::ECX
205 };
206 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
207 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
208 return false;
209 }
210 }
211 }
212
213 if (LocVT == MVT::i64) {
214 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
215 static const MCPhysReg RegList4[] = {
216 X86::RDI, X86::RSI, X86::RDX, X86::RCX
217 };
218 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
219 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
220 return false;
221 }
222 }
223 }
224
225 if (LocVT == MVT::i32) {
226 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(4));
227 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
228 return false;
229 }
230
231 if (LocVT == MVT::f32 ||
232 LocVT == MVT::f64 ||
233 LocVT == MVT::v4i32 ||
234 LocVT == MVT::v2i64 ||
235 LocVT == MVT::v4f32 ||
236 LocVT == MVT::v2f64) {
237 static const MCPhysReg RegList6[] = {
238 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
239 };
240 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
241 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
242 return false;
243 }
244 }
245
246 if (LocVT == MVT::v8f32 ||
247 LocVT == MVT::v4f64 ||
248 LocVT == MVT::v8i32 ||
249 LocVT == MVT::v4i64) {
250 static const MCPhysReg RegList7[] = {
251 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
252 };
253 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
254 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
255 return false;
256 }
257 }
258
259 if (LocVT == MVT::v16f32 ||
260 LocVT == MVT::v8f64 ||
261 LocVT == MVT::v16i32 ||
262 LocVT == MVT::v8i64) {
263 static const MCPhysReg RegList8[] = {
264 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
265 };
266 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
267 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
268 return false;
269 }
270 }
271
272 if (LocVT == MVT::v16i1 ||
273 LocVT == MVT::v8i1) {
274 if (MCRegister Reg = State.AllocateReg(Reg: X86::K1)) {
275 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
276 return false;
277 }
278 }
279
280 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
281 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
282 return false;
283 }
284
285 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
286 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
287 return false;
288 }
289
290 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
291 return false;
292
293 return true; // CC didn't match.
294}
295
296
297bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
298 MVT LocVT, CCValAssign::LocInfo LocInfo,
299 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
300
301 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
302 if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
303 return false;
304 }
305
306 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
307 if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
308 return false;
309 }
310
311 if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
312 return false;
313
314 return true; // CC didn't match.
315}
316
317
318static bool CC_X86_32(unsigned ValNo, MVT ValVT,
319 MVT LocVT, CCValAssign::LocInfo LocInfo,
320 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
321
322 if (State.getCallingConv() == CallingConv::X86_INTR) {
323 if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
324 return false;
325 }
326
327 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetMCU()) {
328 if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
329 return false;
330 }
331
332 if (State.getCallingConv() == CallingConv::X86_FastCall) {
333 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
334 return false;
335 }
336
337 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
338 if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
339 return false;
340 }
341
342 if (State.getCallingConv() == CallingConv::X86_ThisCall) {
343 if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
344 return false;
345 }
346
347 if (State.getCallingConv() == CallingConv::CFGuard_Check) {
348 if (!CC_X86_Win32_CFGuard_Check(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
349 return false;
350 }
351
352 if (State.getCallingConv() == CallingConv::Fast) {
353 if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
354 return false;
355 }
356
357 if (State.getCallingConv() == CallingConv::Tail) {
358 if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
359 return false;
360 }
361
362 if (State.getCallingConv() == CallingConv::GHC) {
363 if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
364 return false;
365 }
366
367 if (State.getCallingConv() == CallingConv::HiPE) {
368 if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
369 return false;
370 }
371
372 if (State.getCallingConv() == CallingConv::X86_RegCall) {
373 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin32()) {
374 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
375 if (!CC_X86_32_RegCallv4_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
376 return false;
377 }
378 }
379 }
380
381 if (State.getCallingConv() == CallingConv::X86_RegCall) {
382 if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
383 return false;
384 }
385
386 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
387 return false;
388
389 return true; // CC didn't match.
390}
391
392
393static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
394 MVT LocVT, CCValAssign::LocInfo LocInfo,
395 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
396
397 if (LocVT == MVT::i1 ||
398 LocVT == MVT::i8 ||
399 LocVT == MVT::i16 ||
400 LocVT == MVT::v1i1) {
401 LocVT = MVT::i32;
402 if (ArgFlags.isSExt())
403 LocInfo = CCValAssign::SExt;
404 else if (ArgFlags.isZExt())
405 LocInfo = CCValAssign::ZExt;
406 else
407 LocInfo = CCValAssign::AExt;
408 }
409
410 if (ArgFlags.isNest()) {
411 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
412 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
413 return false;
414 }
415 }
416
417 if (LocVT == MVT::i32) {
418 if (ArgFlags.isInConsecutiveRegs()) {
419 if (CC_X86_32_I128_FP128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
420 return false;
421 }
422 }
423
424 if (State.getCallingConv() == CallingConv::SwiftTail) {
425 if (ArgFlags.isSwiftSelf()) {
426 if (LocVT == MVT::i32) {
427 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
428 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
429 return false;
430 }
431 }
432 }
433 }
434
435 if (!State.isVarArg()) {
436 if (ArgFlags.isInReg()) {
437 if (LocVT == MVT::i32) {
438 static const MCPhysReg RegList1[] = {
439 X86::EAX, X86::EDX, X86::ECX
440 };
441 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
442 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
443 return false;
444 }
445 }
446 }
447 }
448
449 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
450 return false;
451
452 return true; // CC didn't match.
453}
454
455
456static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
457 MVT LocVT, CCValAssign::LocInfo LocInfo,
458 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
459
460 if (ArgFlags.isByVal()) {
461 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
462 return false;
463 }
464
465 if (ArgFlags.isPreallocated()) {
466 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
467 return false;
468 }
469
470 if (!State.isVarArg()) {
471 if (ArgFlags.isInReg()) {
472 if (LocVT == MVT::f32 ||
473 LocVT == MVT::f64) {
474 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
475 static const MCPhysReg RegList1[] = {
476 X86::XMM0, X86::XMM1, X86::XMM2
477 };
478 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
479 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
480 return false;
481 }
482 }
483 }
484 }
485 }
486
487 if (!State.isVarArg()) {
488 if (ArgFlags.isInReg()) {
489 if (LocVT == MVT::f16) {
490 static const MCPhysReg RegList2[] = {
491 X86::XMM0, X86::XMM1, X86::XMM2
492 };
493 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
494 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
495 return false;
496 }
497 }
498 }
499 }
500
501 if (LocVT == MVT::f16) {
502 int64_t Offset3 = State.AllocateStack(Size: 4, Alignment: Align(4));
503 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
504 return false;
505 }
506
507 if (LocVT == MVT::i32 ||
508 LocVT == MVT::f32) {
509 int64_t Offset4 = State.AllocateStack(Size: 4, Alignment: Align(4));
510 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
511 return false;
512 }
513
514 if (LocVT == MVT::f64) {
515 int64_t Offset5 = State.AllocateStack(Size: 8, Alignment: Align(4));
516 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
517 return false;
518 }
519
520 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetDarwin()) {
521 if (LocVT == MVT::f80) {
522 int64_t Offset6 = State.AllocateStack(
523 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())), Alignment: Align(4));
524 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
525 return false;
526 }
527 }
528
529 if (LocVT == MVT::f80) {
530 int64_t Offset7 = State.AllocateStack(
531 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
532 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
533 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
534 return false;
535 }
536
537 if (LocVT == MVT::v2i1) {
538 LocVT = MVT::v2i64;
539 if (ArgFlags.isSExt())
540 LocInfo = CCValAssign::SExt;
541 else if (ArgFlags.isZExt())
542 LocInfo = CCValAssign::ZExt;
543 else
544 LocInfo = CCValAssign::AExt;
545 }
546
547 if (LocVT == MVT::v4i1) {
548 LocVT = MVT::v4i32;
549 if (ArgFlags.isSExt())
550 LocInfo = CCValAssign::SExt;
551 else if (ArgFlags.isZExt())
552 LocInfo = CCValAssign::ZExt;
553 else
554 LocInfo = CCValAssign::AExt;
555 }
556
557 if (LocVT == MVT::v8i1) {
558 LocVT = MVT::v8i16;
559 if (ArgFlags.isSExt())
560 LocInfo = CCValAssign::SExt;
561 else if (ArgFlags.isZExt())
562 LocInfo = CCValAssign::ZExt;
563 else
564 LocInfo = CCValAssign::AExt;
565 }
566
567 if (LocVT == MVT::v16i1) {
568 LocVT = MVT::v16i8;
569 if (ArgFlags.isSExt())
570 LocInfo = CCValAssign::SExt;
571 else if (ArgFlags.isZExt())
572 LocInfo = CCValAssign::ZExt;
573 else
574 LocInfo = CCValAssign::AExt;
575 }
576
577 if (LocVT == MVT::v32i1) {
578 LocVT = MVT::v32i8;
579 if (ArgFlags.isSExt())
580 LocInfo = CCValAssign::SExt;
581 else if (ArgFlags.isZExt())
582 LocInfo = CCValAssign::ZExt;
583 else
584 LocInfo = CCValAssign::AExt;
585 }
586
587 if (LocVT == MVT::v64i1) {
588 LocVT = MVT::v64i8;
589 if (ArgFlags.isSExt())
590 LocInfo = CCValAssign::SExt;
591 else if (ArgFlags.isZExt())
592 LocInfo = CCValAssign::ZExt;
593 else
594 LocInfo = CCValAssign::AExt;
595 }
596
597 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetDarwin()) {
598 if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
599 return false;
600 }
601
602 if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
603 return false;
604
605 return true; // CC didn't match.
606}
607
608
609static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
610 MVT LocVT, CCValAssign::LocInfo LocInfo,
611 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
612
613 if (ArgFlags.isByVal()) {
614 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
615 return false;
616 }
617
618 if (LocVT == MVT::i1 ||
619 LocVT == MVT::i8 ||
620 LocVT == MVT::i16 ||
621 LocVT == MVT::v1i1) {
622 LocVT = MVT::i32;
623 if (ArgFlags.isSExt())
624 LocInfo = CCValAssign::SExt;
625 else if (ArgFlags.isZExt())
626 LocInfo = CCValAssign::ZExt;
627 else
628 LocInfo = CCValAssign::AExt;
629 }
630
631 if (ArgFlags.isNest()) {
632 if (MCRegister Reg = State.AllocateReg(Reg: X86::EAX)) {
633 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
634 return false;
635 }
636 }
637
638 if (LocVT == MVT::i32) {
639 static const MCPhysReg RegList1[] = {
640 X86::ECX, X86::EDX
641 };
642 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
643 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
644 return false;
645 }
646 }
647
648 if (!State.isVarArg()) {
649 if (LocVT == MVT::f32 ||
650 LocVT == MVT::f64) {
651 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
652 static const MCPhysReg RegList2[] = {
653 X86::XMM0, X86::XMM1, X86::XMM2
654 };
655 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
656 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
657 return false;
658 }
659 }
660 }
661 }
662
663 if (LocVT == MVT::f64) {
664 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(8));
665 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
666 return false;
667 }
668
669 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
670 return false;
671
672 return true; // CC didn't match.
673}
674
675
676static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
677 MVT LocVT, CCValAssign::LocInfo LocInfo,
678 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
679
680 if (LocVT == MVT::i1) {
681 LocVT = MVT::i8;
682 if (ArgFlags.isSExt())
683 LocInfo = CCValAssign::SExt;
684 else if (ArgFlags.isZExt())
685 LocInfo = CCValAssign::ZExt;
686 else
687 LocInfo = CCValAssign::AExt;
688 }
689
690 if (ArgFlags.isNest()) {
691 if (MCRegister Reg = State.AllocateReg(Reg: X86::EAX)) {
692 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
693 return false;
694 }
695 }
696
697 if (ArgFlags.isInReg()) {
698 if (LocVT == MVT::i8) {
699 static const MCPhysReg RegList1[] = {
700 X86::CL, X86::DL
701 };
702 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
703 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
704 return false;
705 }
706 }
707 }
708
709 if (ArgFlags.isInReg()) {
710 if (LocVT == MVT::i16) {
711 static const MCPhysReg RegList2[] = {
712 X86::CX, X86::DX
713 };
714 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
715 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
716 return false;
717 }
718 }
719 }
720
721 if (ArgFlags.isInReg()) {
722 if (LocVT == MVT::i32) {
723 static const MCPhysReg RegList3[] = {
724 X86::ECX, X86::EDX
725 };
726 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
727 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
728 return false;
729 }
730 }
731 }
732
733 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
734 return false;
735
736 return true; // CC didn't match.
737}
738
739
740static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
741 MVT LocVT, CCValAssign::LocInfo LocInfo,
742 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
743
744 if (LocVT == MVT::i8 ||
745 LocVT == MVT::i16) {
746 LocVT = MVT::i32;
747 if (ArgFlags.isSExt())
748 LocInfo = CCValAssign::SExt;
749 else if (ArgFlags.isZExt())
750 LocInfo = CCValAssign::ZExt;
751 else
752 LocInfo = CCValAssign::AExt;
753 }
754
755 if (LocVT == MVT::i32) {
756 static const MCPhysReg RegList1[] = {
757 X86::EBX, X86::EBP, X86::EDI, X86::ESI
758 };
759 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
760 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
761 return false;
762 }
763 }
764
765 return true; // CC didn't match.
766}
767
768
769static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
770 MVT LocVT, CCValAssign::LocInfo LocInfo,
771 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
772
773 if (LocVT == MVT::i8 ||
774 LocVT == MVT::i16) {
775 LocVT = MVT::i32;
776 if (ArgFlags.isSExt())
777 LocInfo = CCValAssign::SExt;
778 else if (ArgFlags.isZExt())
779 LocInfo = CCValAssign::ZExt;
780 else
781 LocInfo = CCValAssign::AExt;
782 }
783
784 if (LocVT == MVT::i32) {
785 static const MCPhysReg RegList1[] = {
786 X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
787 };
788 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
789 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
790 return false;
791 }
792 }
793
794 if (LocVT == MVT::i32 ||
795 LocVT == MVT::f32) {
796 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
797 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
798 return false;
799 }
800
801 return true; // CC didn't match.
802}
803
804
805static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
806 MVT LocVT, CCValAssign::LocInfo LocInfo,
807 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
808
809 if (ArgFlags.isByVal()) {
810 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
811 return false;
812 }
813
814 if (LocVT == MVT::i1 ||
815 LocVT == MVT::i8 ||
816 LocVT == MVT::i16 ||
817 LocVT == MVT::v1i1) {
818 LocVT = MVT::i32;
819 if (ArgFlags.isSExt())
820 LocInfo = CCValAssign::SExt;
821 else if (ArgFlags.isZExt())
822 LocInfo = CCValAssign::ZExt;
823 else
824 LocInfo = CCValAssign::AExt;
825 }
826
827 if (!State.isVarArg()) {
828 if (LocVT == MVT::i32) {
829 if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
830 return false;
831 }
832 }
833
834 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
835 return false;
836
837 return true; // CC didn't match.
838}
839
840
841static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
842 MVT LocVT, CCValAssign::LocInfo LocInfo,
843 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
844
845 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
846 if (ArgFlags.isByVal()) {
847 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
848 return false;
849 }
850 }
851
852 if (ArgFlags.isByVal()) {
853 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
854 return false;
855 }
856
857 if (LocVT == MVT::i1 ||
858 LocVT == MVT::i8 ||
859 LocVT == MVT::i16 ||
860 LocVT == MVT::v1i1) {
861 LocVT = MVT::i32;
862 if (ArgFlags.isSExt())
863 LocInfo = CCValAssign::SExt;
864 else if (ArgFlags.isZExt())
865 LocInfo = CCValAssign::ZExt;
866 else
867 LocInfo = CCValAssign::AExt;
868 }
869
870 if (LocVT == MVT::v8i1 ||
871 LocVT == MVT::v16i1 ||
872 LocVT == MVT::v32i1) {
873 LocVT = MVT::i32;
874 if (ArgFlags.isSExt())
875 LocInfo = CCValAssign::SExt;
876 else if (ArgFlags.isZExt())
877 LocInfo = CCValAssign::ZExt;
878 else
879 LocInfo = CCValAssign::AExt;
880 }
881
882 if (LocVT == MVT::i32) {
883 static const MCPhysReg RegList1[] = {
884 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
885 };
886 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
887 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
888 return false;
889 }
890 }
891
892 if (LocVT == MVT::i64) {
893 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
894 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
895 return false;
896 }
897 }
898
899 if (LocVT == MVT::v64i1) {
900 LocVT = MVT::i64;
901 if (ArgFlags.isSExt())
902 LocInfo = CCValAssign::SExt;
903 else if (ArgFlags.isZExt())
904 LocInfo = CCValAssign::ZExt;
905 else
906 LocInfo = CCValAssign::AExt;
907 }
908
909 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
910 if (LocVT == MVT::i64) {
911 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
912 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
913 return false;
914 }
915 }
916 }
917
918 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
919 if (LocVT == MVT::i64) {
920 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
921 return false;
922 }
923 }
924
925 if (LocVT == MVT::f32 ||
926 LocVT == MVT::f64 ||
927 LocVT == MVT::f128) {
928 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
929 static const MCPhysReg RegList2[] = {
930 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
931 };
932 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
933 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
934 return false;
935 }
936 }
937 }
938
939 if (LocVT == MVT::f80) {
940 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
941 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
942 return false;
943 }
944 }
945
946 if (LocVT == MVT::v16i8 ||
947 LocVT == MVT::v8i16 ||
948 LocVT == MVT::v4i32 ||
949 LocVT == MVT::v2i64 ||
950 LocVT == MVT::v4f32 ||
951 LocVT == MVT::v2f64) {
952 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
953 static const MCPhysReg RegList3[] = {
954 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
955 };
956 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
957 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
958 return false;
959 }
960 }
961 }
962
963 if (LocVT == MVT::v32i8 ||
964 LocVT == MVT::v16i16 ||
965 LocVT == MVT::v8i32 ||
966 LocVT == MVT::v4i64 ||
967 LocVT == MVT::v8f32 ||
968 LocVT == MVT::v4f64) {
969 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
970 static const MCPhysReg RegList4[] = {
971 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
972 };
973 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
974 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
975 return false;
976 }
977 }
978 }
979
980 if (LocVT == MVT::v64i8 ||
981 LocVT == MVT::v32i16 ||
982 LocVT == MVT::v16i32 ||
983 LocVT == MVT::v8i64 ||
984 LocVT == MVT::v16f32 ||
985 LocVT == MVT::v8f64) {
986 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
987 static const MCPhysReg RegList5[] = {
988 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
989 };
990 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
991 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
992 return false;
993 }
994 }
995 }
996
997 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
998 if (LocVT == MVT::i32 ||
999 LocVT == MVT::i64 ||
1000 LocVT == MVT::f32 ||
1001 LocVT == MVT::f64) {
1002 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
1003 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1004 return false;
1005 }
1006 }
1007
1008 if (LocVT == MVT::i32 ||
1009 LocVT == MVT::f32) {
1010 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(4));
1011 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
1012 return false;
1013 }
1014
1015 if (LocVT == MVT::i64 ||
1016 LocVT == MVT::f64) {
1017 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(4));
1018 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1019 return false;
1020 }
1021
1022 if (LocVT == MVT::f80 ||
1023 LocVT == MVT::f128) {
1024 int64_t Offset9 = State.AllocateStack(
1025 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1026 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1027 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1028 return false;
1029 }
1030
1031 if (LocVT == MVT::v16i8 ||
1032 LocVT == MVT::v8i16 ||
1033 LocVT == MVT::v4i32 ||
1034 LocVT == MVT::v2i64 ||
1035 LocVT == MVT::v4f32 ||
1036 LocVT == MVT::v2f64) {
1037 int64_t Offset10 = State.AllocateStack(Size: 16, Alignment: Align(16));
1038 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1039 return false;
1040 }
1041
1042 if (LocVT == MVT::v32i8 ||
1043 LocVT == MVT::v16i16 ||
1044 LocVT == MVT::v8i32 ||
1045 LocVT == MVT::v4i64 ||
1046 LocVT == MVT::v8f32 ||
1047 LocVT == MVT::v4f64) {
1048 int64_t Offset11 = State.AllocateStack(Size: 32, Alignment: Align(32));
1049 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
1050 return false;
1051 }
1052
1053 if (LocVT == MVT::v64i8 ||
1054 LocVT == MVT::v32i16 ||
1055 LocVT == MVT::v16i32 ||
1056 LocVT == MVT::v8i64 ||
1057 LocVT == MVT::v16f32 ||
1058 LocVT == MVT::v8f64) {
1059 int64_t Offset12 = State.AllocateStack(Size: 64, Alignment: Align(64));
1060 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
1061 return false;
1062 }
1063
1064 return true; // CC didn't match.
1065}
1066
1067
1068static bool CC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
1069 MVT LocVT, CCValAssign::LocInfo LocInfo,
1070 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1071
1072 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
1073 if (ArgFlags.isByVal()) {
1074 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1075 return false;
1076 }
1077 }
1078
1079 if (ArgFlags.isByVal()) {
1080 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
1081 return false;
1082 }
1083
1084 if (LocVT == MVT::i1 ||
1085 LocVT == MVT::i8 ||
1086 LocVT == MVT::i16 ||
1087 LocVT == MVT::v1i1) {
1088 LocVT = MVT::i32;
1089 if (ArgFlags.isSExt())
1090 LocInfo = CCValAssign::SExt;
1091 else if (ArgFlags.isZExt())
1092 LocInfo = CCValAssign::ZExt;
1093 else
1094 LocInfo = CCValAssign::AExt;
1095 }
1096
1097 if (LocVT == MVT::v8i1 ||
1098 LocVT == MVT::v16i1 ||
1099 LocVT == MVT::v32i1) {
1100 LocVT = MVT::i32;
1101 if (ArgFlags.isSExt())
1102 LocInfo = CCValAssign::SExt;
1103 else if (ArgFlags.isZExt())
1104 LocInfo = CCValAssign::ZExt;
1105 else
1106 LocInfo = CCValAssign::AExt;
1107 }
1108
1109 if (LocVT == MVT::i32) {
1110 static const MCPhysReg RegList1[] = {
1111 X86::ECX, X86::EDX, X86::EDI, X86::ESI
1112 };
1113 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1114 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1115 return false;
1116 }
1117 }
1118
1119 if (LocVT == MVT::i64) {
1120 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1121 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1122 return false;
1123 }
1124 }
1125
1126 if (LocVT == MVT::v64i1) {
1127 LocVT = MVT::i64;
1128 if (ArgFlags.isSExt())
1129 LocInfo = CCValAssign::SExt;
1130 else if (ArgFlags.isZExt())
1131 LocInfo = CCValAssign::ZExt;
1132 else
1133 LocInfo = CCValAssign::AExt;
1134 }
1135
1136 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
1137 if (LocVT == MVT::i64) {
1138 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1139 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1140 return false;
1141 }
1142 }
1143 }
1144
1145 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
1146 if (LocVT == MVT::i64) {
1147 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1148 return false;
1149 }
1150 }
1151
1152 if (LocVT == MVT::f32 ||
1153 LocVT == MVT::f64 ||
1154 LocVT == MVT::f128) {
1155 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
1156 static const MCPhysReg RegList2[] = {
1157 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1158 };
1159 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1160 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1161 return false;
1162 }
1163 }
1164 }
1165
1166 if (LocVT == MVT::f80) {
1167 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
1168 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1169 return false;
1170 }
1171 }
1172
1173 if (LocVT == MVT::v16i8 ||
1174 LocVT == MVT::v8i16 ||
1175 LocVT == MVT::v4i32 ||
1176 LocVT == MVT::v2i64 ||
1177 LocVT == MVT::v4f32 ||
1178 LocVT == MVT::v2f64) {
1179 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
1180 static const MCPhysReg RegList3[] = {
1181 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1182 };
1183 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1184 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1185 return false;
1186 }
1187 }
1188 }
1189
1190 if (LocVT == MVT::v32i8 ||
1191 LocVT == MVT::v16i16 ||
1192 LocVT == MVT::v8i32 ||
1193 LocVT == MVT::v4i64 ||
1194 LocVT == MVT::v8f32 ||
1195 LocVT == MVT::v4f64) {
1196 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1197 static const MCPhysReg RegList4[] = {
1198 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1199 };
1200 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1201 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1202 return false;
1203 }
1204 }
1205 }
1206
1207 if (LocVT == MVT::v64i8 ||
1208 LocVT == MVT::v32i16 ||
1209 LocVT == MVT::v16i32 ||
1210 LocVT == MVT::v8i64 ||
1211 LocVT == MVT::v16f32 ||
1212 LocVT == MVT::v8f64) {
1213 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
1214 static const MCPhysReg RegList5[] = {
1215 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1216 };
1217 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
1218 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1219 return false;
1220 }
1221 }
1222 }
1223
1224 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
1225 if (LocVT == MVT::i32 ||
1226 LocVT == MVT::i64 ||
1227 LocVT == MVT::f32 ||
1228 LocVT == MVT::f64) {
1229 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
1230 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1231 return false;
1232 }
1233 }
1234
1235 if (LocVT == MVT::i32 ||
1236 LocVT == MVT::f32) {
1237 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(4));
1238 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
1239 return false;
1240 }
1241
1242 if (LocVT == MVT::i64 ||
1243 LocVT == MVT::f64) {
1244 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(4));
1245 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1246 return false;
1247 }
1248
1249 if (LocVT == MVT::f80 ||
1250 LocVT == MVT::f128) {
1251 int64_t Offset9 = State.AllocateStack(
1252 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1253 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1254 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1255 return false;
1256 }
1257
1258 if (LocVT == MVT::v16i8 ||
1259 LocVT == MVT::v8i16 ||
1260 LocVT == MVT::v4i32 ||
1261 LocVT == MVT::v2i64 ||
1262 LocVT == MVT::v4f32 ||
1263 LocVT == MVT::v2f64) {
1264 int64_t Offset10 = State.AllocateStack(Size: 16, Alignment: Align(16));
1265 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1266 return false;
1267 }
1268
1269 if (LocVT == MVT::v32i8 ||
1270 LocVT == MVT::v16i16 ||
1271 LocVT == MVT::v8i32 ||
1272 LocVT == MVT::v4i64 ||
1273 LocVT == MVT::v8f32 ||
1274 LocVT == MVT::v4f64) {
1275 int64_t Offset11 = State.AllocateStack(Size: 32, Alignment: Align(32));
1276 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
1277 return false;
1278 }
1279
1280 if (LocVT == MVT::v64i8 ||
1281 LocVT == MVT::v32i16 ||
1282 LocVT == MVT::v16i32 ||
1283 LocVT == MVT::v8i64 ||
1284 LocVT == MVT::v16f32 ||
1285 LocVT == MVT::v8f64) {
1286 int64_t Offset12 = State.AllocateStack(Size: 64, Alignment: Align(64));
1287 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
1288 return false;
1289 }
1290
1291 return true; // CC didn't match.
1292}
1293
1294
1295static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
1296 MVT LocVT, CCValAssign::LocInfo LocInfo,
1297 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1298
1299 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetCygMing()) {
1300 if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1301 return false;
1302 }
1303
1304 if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1305 return false;
1306
1307 return true; // CC didn't match.
1308}
1309
1310
1311static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
1312 MVT LocVT, CCValAssign::LocInfo LocInfo,
1313 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1314
1315 if (LocVT == MVT::i32) {
1316 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
1317 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1318 return false;
1319 }
1320 }
1321
1322 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1323 return false;
1324
1325 return true; // CC didn't match.
1326}
1327
1328
1329static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
1330 MVT LocVT, CCValAssign::LocInfo LocInfo,
1331 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1332
1333 if (LocVT == MVT::i1 ||
1334 LocVT == MVT::i8 ||
1335 LocVT == MVT::i16 ||
1336 LocVT == MVT::v1i1) {
1337 LocVT = MVT::i32;
1338 if (ArgFlags.isSExt())
1339 LocInfo = CCValAssign::SExt;
1340 else if (ArgFlags.isZExt())
1341 LocInfo = CCValAssign::ZExt;
1342 else
1343 LocInfo = CCValAssign::AExt;
1344 }
1345
1346 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1347 return false;
1348
1349 return true; // CC didn't match.
1350}
1351
1352
1353static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
1354 MVT LocVT, CCValAssign::LocInfo LocInfo,
1355 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1356
1357 if (LocVT == MVT::i1 ||
1358 LocVT == MVT::i8 ||
1359 LocVT == MVT::i16 ||
1360 LocVT == MVT::v1i1) {
1361 LocVT = MVT::i32;
1362 if (ArgFlags.isSExt())
1363 LocInfo = CCValAssign::SExt;
1364 else if (ArgFlags.isZExt())
1365 LocInfo = CCValAssign::ZExt;
1366 else
1367 LocInfo = CCValAssign::AExt;
1368 }
1369
1370 if (ArgFlags.isSRet()) {
1371 int64_t Offset1 = State.AllocateStack(Size: 4, Alignment: Align(4));
1372 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1373 return false;
1374 }
1375
1376 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1377 return false;
1378
1379 return true; // CC didn't match.
1380}
1381
1382
1383static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
1384 MVT LocVT, CCValAssign::LocInfo LocInfo,
1385 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1386
1387 if (LocVT == MVT::v16i8 ||
1388 LocVT == MVT::v8i16 ||
1389 LocVT == MVT::v4i32 ||
1390 LocVT == MVT::v2i64 ||
1391 LocVT == MVT::v8f16 ||
1392 LocVT == MVT::v8bf16 ||
1393 LocVT == MVT::v4f32 ||
1394 LocVT == MVT::v2f64) {
1395 int64_t Offset1 = State.AllocateStack(Size: 16, Alignment: Align(16));
1396 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1397 return false;
1398 }
1399
1400 if (LocVT == MVT::v32i8 ||
1401 LocVT == MVT::v16i16 ||
1402 LocVT == MVT::v8i32 ||
1403 LocVT == MVT::v4i64 ||
1404 LocVT == MVT::v16f16 ||
1405 LocVT == MVT::v16bf16 ||
1406 LocVT == MVT::v8f32 ||
1407 LocVT == MVT::v4f64) {
1408 int64_t Offset2 = State.AllocateStack(Size: 32, Alignment: Align(32));
1409 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1410 return false;
1411 }
1412
1413 if (LocVT == MVT::v64i8 ||
1414 LocVT == MVT::v32i16 ||
1415 LocVT == MVT::v16i32 ||
1416 LocVT == MVT::v8i64 ||
1417 LocVT == MVT::v32f16 ||
1418 LocVT == MVT::v32bf16 ||
1419 LocVT == MVT::v16f32 ||
1420 LocVT == MVT::v8f64) {
1421 int64_t Offset3 = State.AllocateStack(Size: 64, Alignment: Align(64));
1422 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1423 return false;
1424 }
1425
1426 return true; // CC didn't match.
1427}
1428
1429
1430static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
1431 MVT LocVT, CCValAssign::LocInfo LocInfo,
1432 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1433
1434 if (!State.isVarArg()) {
1435 if (LocVT == MVT::v16i8 ||
1436 LocVT == MVT::v8i16 ||
1437 LocVT == MVT::v4i32 ||
1438 LocVT == MVT::v2i64 ||
1439 LocVT == MVT::v8f16 ||
1440 LocVT == MVT::v8bf16 ||
1441 LocVT == MVT::v4f32 ||
1442 LocVT == MVT::v2f64) {
1443 static const MCPhysReg RegList1[] = {
1444 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1445 };
1446 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1447 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1448 return false;
1449 }
1450 }
1451 }
1452
1453 if (!State.isVarArg()) {
1454 if (LocVT == MVT::v32i8 ||
1455 LocVT == MVT::v16i16 ||
1456 LocVT == MVT::v8i32 ||
1457 LocVT == MVT::v4i64 ||
1458 LocVT == MVT::v16f16 ||
1459 LocVT == MVT::v16bf16 ||
1460 LocVT == MVT::v8f32 ||
1461 LocVT == MVT::v4f64) {
1462 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1463 static const MCPhysReg RegList2[] = {
1464 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1465 };
1466 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1467 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1468 return false;
1469 }
1470 }
1471 }
1472 }
1473
1474 if (!State.isVarArg()) {
1475 if (LocVT == MVT::v64i8 ||
1476 LocVT == MVT::v32i16 ||
1477 LocVT == MVT::v16i32 ||
1478 LocVT == MVT::v8i64 ||
1479 LocVT == MVT::v32f16 ||
1480 LocVT == MVT::v32bf16 ||
1481 LocVT == MVT::v16f32 ||
1482 LocVT == MVT::v8f64) {
1483 static const MCPhysReg RegList3[] = {
1484 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1485 };
1486 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1487 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1488 return false;
1489 }
1490 }
1491 }
1492
1493 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1494 return false;
1495
1496 return true; // CC didn't match.
1497}
1498
1499
1500static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
1501 MVT LocVT, CCValAssign::LocInfo LocInfo,
1502 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1503
1504 if (!State.isVarArg()) {
1505 if (LocVT == MVT::v16i8 ||
1506 LocVT == MVT::v8i16 ||
1507 LocVT == MVT::v4i32 ||
1508 LocVT == MVT::v2i64 ||
1509 LocVT == MVT::v8f16 ||
1510 LocVT == MVT::v8bf16 ||
1511 LocVT == MVT::v4f32 ||
1512 LocVT == MVT::v2f64) {
1513 static const MCPhysReg RegList1[] = {
1514 X86::XMM0, X86::XMM1, X86::XMM2
1515 };
1516 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1517 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1518 return false;
1519 }
1520 }
1521 }
1522
1523 if (!State.isVarArg()) {
1524 if (LocVT == MVT::v32i8 ||
1525 LocVT == MVT::v16i16 ||
1526 LocVT == MVT::v8i32 ||
1527 LocVT == MVT::v4i64 ||
1528 LocVT == MVT::v16f16 ||
1529 LocVT == MVT::v16bf16 ||
1530 LocVT == MVT::v8f32 ||
1531 LocVT == MVT::v4f64) {
1532 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1533 static const MCPhysReg RegList2[] = {
1534 X86::YMM0, X86::YMM1, X86::YMM2
1535 };
1536 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1537 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1538 return false;
1539 }
1540 }
1541 }
1542 }
1543
1544 if (!State.isVarArg()) {
1545 if (LocVT == MVT::v64i8 ||
1546 LocVT == MVT::v32i16 ||
1547 LocVT == MVT::v16i32 ||
1548 LocVT == MVT::v8i64 ||
1549 LocVT == MVT::v32f16 ||
1550 LocVT == MVT::v32bf16 ||
1551 LocVT == MVT::v16f32 ||
1552 LocVT == MVT::v8f64) {
1553 static const MCPhysReg RegList3[] = {
1554 X86::ZMM0, X86::ZMM1, X86::ZMM2
1555 };
1556 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1557 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1558 return false;
1559 }
1560 }
1561 }
1562
1563 if (State.isVarArg() && State.getMachineFunction().getSubtarget().getTargetTriple().isWindowsMSVCEnvironment()) {
1564 if (!CC_X86_Win32_Vector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1565 return false;
1566 }
1567
1568 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1569 return false;
1570
1571 return true; // CC didn't match.
1572}
1573
1574
1575static bool CC_X86_64(unsigned ValNo, MVT ValVT,
1576 MVT LocVT, CCValAssign::LocInfo LocInfo,
1577 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1578
1579 if (State.getCallingConv() == CallingConv::GHC) {
1580 if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1581 return false;
1582 }
1583
1584 if (State.getCallingConv() == CallingConv::HiPE) {
1585 if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1586 return false;
1587 }
1588
1589 if (State.getCallingConv() == CallingConv::AnyReg) {
1590 if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1591 return false;
1592 }
1593
1594 if (State.getCallingConv() == CallingConv::Win64) {
1595 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1596 return false;
1597 }
1598
1599 if (State.getCallingConv() == CallingConv::X86_64_SysV) {
1600 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1601 return false;
1602 }
1603
1604 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
1605 if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1606 return false;
1607 }
1608
1609 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1610 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
1611 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
1612 if (!CC_X86_Win64_RegCallv4(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1613 return false;
1614 }
1615 }
1616 }
1617
1618 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1619 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
1620 if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1621 return false;
1622 }
1623 }
1624
1625 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1626 if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1627 return false;
1628 }
1629
1630 if (State.getCallingConv() == CallingConv::PreserveNone) {
1631 if (!CC_X86_64_Preserve_None(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1632 return false;
1633 }
1634
1635 if (State.getCallingConv() == CallingConv::X86_INTR) {
1636 if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1637 return false;
1638 }
1639
1640 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
1641 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1642 return false;
1643 }
1644
1645 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetUEFI64()) {
1646 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1647 return false;
1648 }
1649
1650 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1651 return false;
1652
1653 return true; // CC didn't match.
1654}
1655
1656
1657static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
1658 MVT LocVT, CCValAssign::LocInfo LocInfo,
1659 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1660
1661 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1662 return false;
1663
1664 return true; // CC didn't match.
1665}
1666
1667
1668static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
1669 MVT LocVT, CCValAssign::LocInfo LocInfo,
1670 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1671
1672 if (ArgFlags.isByVal()) {
1673 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1674 return false;
1675 }
1676
1677 if (LocVT == MVT::i1 ||
1678 LocVT == MVT::i8 ||
1679 LocVT == MVT::i16 ||
1680 LocVT == MVT::v1i1) {
1681 LocVT = MVT::i32;
1682 if (ArgFlags.isSExt())
1683 LocInfo = CCValAssign::SExt;
1684 else if (ArgFlags.isZExt())
1685 LocInfo = CCValAssign::ZExt;
1686 else
1687 LocInfo = CCValAssign::AExt;
1688 }
1689
1690 if (ArgFlags.isNest()) {
1691 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTarget64BitILP32()) {
1692 if (MCRegister Reg = State.AllocateReg(Reg: X86::R10D)) {
1693 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1694 return false;
1695 }
1696 }
1697 }
1698
1699 if (ArgFlags.isNest()) {
1700 if (MCRegister Reg = State.AllocateReg(Reg: X86::R10)) {
1701 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1702 return false;
1703 }
1704 }
1705
1706 if (ArgFlags.isSwiftSelf()) {
1707 if (LocVT == MVT::i64) {
1708 if (MCRegister Reg = State.AllocateReg(Reg: X86::R13)) {
1709 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1710 return false;
1711 }
1712 }
1713 }
1714
1715 if (ArgFlags.isSwiftError()) {
1716 if (LocVT == MVT::i64) {
1717 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
1718 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1719 return false;
1720 }
1721 }
1722 }
1723
1724 if (ArgFlags.isSwiftAsync()) {
1725 if (LocVT == MVT::i64) {
1726 if (MCRegister Reg = State.AllocateReg(Reg: X86::R14)) {
1727 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1728 return false;
1729 }
1730 }
1731 }
1732
1733 if (State.getCallingConv() == CallingConv::Swift) {
1734 if (ArgFlags.isSRet()) {
1735 if (LocVT == MVT::i64) {
1736 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1737 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1738 return false;
1739 }
1740 }
1741 }
1742 }
1743
1744 if (State.getCallingConv() == CallingConv::SwiftTail) {
1745 if (ArgFlags.isSRet()) {
1746 if (LocVT == MVT::i64) {
1747 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1748 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1749 return false;
1750 }
1751 }
1752 }
1753 }
1754
1755 if (ArgFlags.isPointer()) {
1756 if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1757 return false;
1758 }
1759
1760 if (LocVT == MVT::i32) {
1761 static const MCPhysReg RegList1[] = {
1762 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1763 };
1764 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1765 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1766 return false;
1767 }
1768 }
1769
1770 if (LocVT == MVT::i64) {
1771 if (ArgFlags.isInConsecutiveRegs()) {
1772 if (CC_X86_64_I128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1773 return false;
1774 }
1775 }
1776
1777 if (LocVT == MVT::i64) {
1778 static const MCPhysReg RegList2[] = {
1779 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1780 };
1781 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1782 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1783 return false;
1784 }
1785 }
1786
1787 if (LocVT == MVT::v2i1) {
1788 LocVT = MVT::v2i64;
1789 if (ArgFlags.isSExt())
1790 LocInfo = CCValAssign::SExt;
1791 else if (ArgFlags.isZExt())
1792 LocInfo = CCValAssign::ZExt;
1793 else
1794 LocInfo = CCValAssign::AExt;
1795 }
1796
1797 if (LocVT == MVT::v4i1) {
1798 LocVT = MVT::v4i32;
1799 if (ArgFlags.isSExt())
1800 LocInfo = CCValAssign::SExt;
1801 else if (ArgFlags.isZExt())
1802 LocInfo = CCValAssign::ZExt;
1803 else
1804 LocInfo = CCValAssign::AExt;
1805 }
1806
1807 if (LocVT == MVT::v8i1) {
1808 LocVT = MVT::v8i16;
1809 if (ArgFlags.isSExt())
1810 LocInfo = CCValAssign::SExt;
1811 else if (ArgFlags.isZExt())
1812 LocInfo = CCValAssign::ZExt;
1813 else
1814 LocInfo = CCValAssign::AExt;
1815 }
1816
1817 if (LocVT == MVT::v16i1) {
1818 LocVT = MVT::v16i8;
1819 if (ArgFlags.isSExt())
1820 LocInfo = CCValAssign::SExt;
1821 else if (ArgFlags.isZExt())
1822 LocInfo = CCValAssign::ZExt;
1823 else
1824 LocInfo = CCValAssign::AExt;
1825 }
1826
1827 if (LocVT == MVT::v32i1) {
1828 LocVT = MVT::v32i8;
1829 if (ArgFlags.isSExt())
1830 LocInfo = CCValAssign::SExt;
1831 else if (ArgFlags.isZExt())
1832 LocInfo = CCValAssign::ZExt;
1833 else
1834 LocInfo = CCValAssign::AExt;
1835 }
1836
1837 if (LocVT == MVT::v64i1) {
1838 LocVT = MVT::v64i8;
1839 if (ArgFlags.isSExt())
1840 LocInfo = CCValAssign::SExt;
1841 else if (ArgFlags.isZExt())
1842 LocInfo = CCValAssign::ZExt;
1843 else
1844 LocInfo = CCValAssign::AExt;
1845 }
1846
1847 if (LocVT == MVT::f16 ||
1848 LocVT == MVT::f32 ||
1849 LocVT == MVT::f64 ||
1850 LocVT == MVT::f128 ||
1851 LocVT == MVT::v16i8 ||
1852 LocVT == MVT::v8i16 ||
1853 LocVT == MVT::v4i32 ||
1854 LocVT == MVT::v2i64 ||
1855 LocVT == MVT::v8f16 ||
1856 LocVT == MVT::v8bf16 ||
1857 LocVT == MVT::v4f32 ||
1858 LocVT == MVT::v2f64) {
1859 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
1860 static const MCPhysReg RegList3[] = {
1861 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1862 };
1863 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1864 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1865 return false;
1866 }
1867 }
1868 }
1869
1870 if (!State.isVarArg()) {
1871 if (LocVT == MVT::v32i8 ||
1872 LocVT == MVT::v16i16 ||
1873 LocVT == MVT::v8i32 ||
1874 LocVT == MVT::v4i64 ||
1875 LocVT == MVT::v16f16 ||
1876 LocVT == MVT::v16bf16 ||
1877 LocVT == MVT::v8f32 ||
1878 LocVT == MVT::v4f64) {
1879 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1880 static const MCPhysReg RegList4[] = {
1881 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1882 };
1883 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1884 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1885 return false;
1886 }
1887 }
1888 }
1889 }
1890
1891 if (!State.isVarArg()) {
1892 if (LocVT == MVT::v64i8 ||
1893 LocVT == MVT::v32i16 ||
1894 LocVT == MVT::v16i32 ||
1895 LocVT == MVT::v8i64 ||
1896 LocVT == MVT::v32f16 ||
1897 LocVT == MVT::v32bf16 ||
1898 LocVT == MVT::v16f32 ||
1899 LocVT == MVT::v8f64) {
1900 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
1901 static const MCPhysReg RegList5[] = {
1902 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1903 };
1904 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
1905 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1906 return false;
1907 }
1908 }
1909 }
1910 }
1911
1912 if (LocVT == MVT::i32 ||
1913 LocVT == MVT::i64 ||
1914 LocVT == MVT::f16 ||
1915 LocVT == MVT::f32 ||
1916 LocVT == MVT::f64) {
1917 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
1918 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1919 return false;
1920 }
1921
1922 if (LocVT == MVT::f80 ||
1923 LocVT == MVT::f128) {
1924 int64_t Offset7 = State.AllocateStack(
1925 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1926 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1927 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
1928 return false;
1929 }
1930
1931 if (LocVT == MVT::v16i8 ||
1932 LocVT == MVT::v8i16 ||
1933 LocVT == MVT::v4i32 ||
1934 LocVT == MVT::v2i64 ||
1935 LocVT == MVT::v8f16 ||
1936 LocVT == MVT::v8bf16 ||
1937 LocVT == MVT::v4f32 ||
1938 LocVT == MVT::v2f64) {
1939 int64_t Offset8 = State.AllocateStack(Size: 16, Alignment: Align(16));
1940 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1941 return false;
1942 }
1943
1944 if (LocVT == MVT::v32i8 ||
1945 LocVT == MVT::v16i16 ||
1946 LocVT == MVT::v8i32 ||
1947 LocVT == MVT::v4i64 ||
1948 LocVT == MVT::v16f16 ||
1949 LocVT == MVT::v16bf16 ||
1950 LocVT == MVT::v8f32 ||
1951 LocVT == MVT::v4f64) {
1952 int64_t Offset9 = State.AllocateStack(Size: 32, Alignment: Align(32));
1953 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1954 return false;
1955 }
1956
1957 if (LocVT == MVT::v64i8 ||
1958 LocVT == MVT::v32i16 ||
1959 LocVT == MVT::v16i32 ||
1960 LocVT == MVT::v8i64 ||
1961 LocVT == MVT::v32f16 ||
1962 LocVT == MVT::v32bf16 ||
1963 LocVT == MVT::v16f32 ||
1964 LocVT == MVT::v8f64) {
1965 int64_t Offset10 = State.AllocateStack(Size: 64, Alignment: Align(64));
1966 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1967 return false;
1968 }
1969
1970 return true; // CC didn't match.
1971}
1972
1973
1974static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
1975 MVT LocVT, CCValAssign::LocInfo LocInfo,
1976 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1977
1978 if (LocVT == MVT::i8 ||
1979 LocVT == MVT::i16 ||
1980 LocVT == MVT::i32) {
1981 LocVT = MVT::i64;
1982 if (ArgFlags.isSExt())
1983 LocInfo = CCValAssign::SExt;
1984 else if (ArgFlags.isZExt())
1985 LocInfo = CCValAssign::ZExt;
1986 else
1987 LocInfo = CCValAssign::AExt;
1988 }
1989
1990 if (LocVT == MVT::i64) {
1991 static const MCPhysReg RegList1[] = {
1992 X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
1993 };
1994 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1995 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1996 return false;
1997 }
1998 }
1999
2000 if (LocVT == MVT::f32 ||
2001 LocVT == MVT::f64 ||
2002 LocVT == MVT::v16i8 ||
2003 LocVT == MVT::v8i16 ||
2004 LocVT == MVT::v4i32 ||
2005 LocVT == MVT::v2i64 ||
2006 LocVT == MVT::v4f32 ||
2007 LocVT == MVT::v2f64) {
2008 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2009 static const MCPhysReg RegList2[] = {
2010 X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
2011 };
2012 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2013 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2014 return false;
2015 }
2016 }
2017 }
2018
2019 if (LocVT == MVT::v32i8 ||
2020 LocVT == MVT::v16i16 ||
2021 LocVT == MVT::v8i32 ||
2022 LocVT == MVT::v4i64 ||
2023 LocVT == MVT::v8f32 ||
2024 LocVT == MVT::v4f64) {
2025 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
2026 static const MCPhysReg RegList3[] = {
2027 X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6
2028 };
2029 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2030 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2031 return false;
2032 }
2033 }
2034 }
2035
2036 if (LocVT == MVT::v64i8 ||
2037 LocVT == MVT::v32i16 ||
2038 LocVT == MVT::v16i32 ||
2039 LocVT == MVT::v8i64 ||
2040 LocVT == MVT::v16f32 ||
2041 LocVT == MVT::v8f64) {
2042 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
2043 static const MCPhysReg RegList4[] = {
2044 X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6
2045 };
2046 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2047 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2048 return false;
2049 }
2050 }
2051 }
2052
2053 return true; // CC didn't match.
2054}
2055
2056
2057static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
2058 MVT LocVT, CCValAssign::LocInfo LocInfo,
2059 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2060
2061 if (LocVT == MVT::i8 ||
2062 LocVT == MVT::i16 ||
2063 LocVT == MVT::i32) {
2064 LocVT = MVT::i64;
2065 if (ArgFlags.isSExt())
2066 LocInfo = CCValAssign::SExt;
2067 else if (ArgFlags.isZExt())
2068 LocInfo = CCValAssign::ZExt;
2069 else
2070 LocInfo = CCValAssign::AExt;
2071 }
2072
2073 if (LocVT == MVT::i64) {
2074 static const MCPhysReg RegList1[] = {
2075 X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8
2076 };
2077 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2078 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2079 return false;
2080 }
2081 }
2082
2083 if (LocVT == MVT::i32 ||
2084 LocVT == MVT::i64 ||
2085 LocVT == MVT::f32 ||
2086 LocVT == MVT::f64) {
2087 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(8));
2088 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
2089 return false;
2090 }
2091
2092 return true; // CC didn't match.
2093}
2094
2095
2096static bool CC_X86_64_Preserve_None(unsigned ValNo, MVT ValVT,
2097 MVT LocVT, CCValAssign::LocInfo LocInfo,
2098 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2099
2100 if (ArgFlags.isByVal()) {
2101 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2102 return false;
2103 }
2104
2105 if (LocVT == MVT::i32) {
2106 static const MCPhysReg RegList1[] = {
2107 X86::R12D, X86::R13D, X86::R14D, X86::R15D, X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D, X86::R11D, X86::EAX
2108 };
2109 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2110 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2111 return false;
2112 }
2113 }
2114
2115 if (LocVT == MVT::i64) {
2116 static const MCPhysReg RegList2[] = {
2117 X86::R12, X86::R13, X86::R14, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::R11, X86::RAX
2118 };
2119 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2120 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2121 return false;
2122 }
2123 }
2124
2125 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
2126 return false;
2127
2128 return true; // CC didn't match.
2129}
2130
2131
2132static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
2133 MVT LocVT, CCValAssign::LocInfo LocInfo,
2134 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2135
2136 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2137 if (ArgFlags.isByVal()) {
2138 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2139 return false;
2140 }
2141 }
2142
2143 if (ArgFlags.isByVal()) {
2144 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2145 return false;
2146 }
2147
2148 if (LocVT == MVT::i1 ||
2149 LocVT == MVT::i8 ||
2150 LocVT == MVT::i16 ||
2151 LocVT == MVT::v1i1) {
2152 LocVT = MVT::i32;
2153 if (ArgFlags.isSExt())
2154 LocInfo = CCValAssign::SExt;
2155 else if (ArgFlags.isZExt())
2156 LocInfo = CCValAssign::ZExt;
2157 else
2158 LocInfo = CCValAssign::AExt;
2159 }
2160
2161 if (LocVT == MVT::v8i1 ||
2162 LocVT == MVT::v16i1 ||
2163 LocVT == MVT::v32i1) {
2164 LocVT = MVT::i32;
2165 if (ArgFlags.isSExt())
2166 LocInfo = CCValAssign::SExt;
2167 else if (ArgFlags.isZExt())
2168 LocInfo = CCValAssign::ZExt;
2169 else
2170 LocInfo = CCValAssign::AExt;
2171 }
2172
2173 if (LocVT == MVT::i32) {
2174 static const MCPhysReg RegList1[] = {
2175 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
2176 };
2177 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2178 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2179 return false;
2180 }
2181 }
2182
2183 if (LocVT == MVT::i64) {
2184 static const MCPhysReg RegList2[] = {
2185 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2186 };
2187 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2188 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2189 return false;
2190 }
2191 }
2192
2193 if (LocVT == MVT::v64i1) {
2194 LocVT = MVT::i64;
2195 if (ArgFlags.isSExt())
2196 LocInfo = CCValAssign::SExt;
2197 else if (ArgFlags.isZExt())
2198 LocInfo = CCValAssign::ZExt;
2199 else
2200 LocInfo = CCValAssign::AExt;
2201 }
2202
2203 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2204 if (LocVT == MVT::i64) {
2205 static const MCPhysReg RegList3[] = {
2206 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2207 };
2208 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2209 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2210 return false;
2211 }
2212 }
2213 }
2214
2215 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
2216 if (LocVT == MVT::i64) {
2217 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2218 return false;
2219 }
2220 }
2221
2222 if (LocVT == MVT::f32 ||
2223 LocVT == MVT::f64 ||
2224 LocVT == MVT::f128) {
2225 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2226 static const MCPhysReg RegList4[] = {
2227 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2228 };
2229 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2230 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2231 return false;
2232 }
2233 }
2234 }
2235
2236 if (LocVT == MVT::f80) {
2237 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
2238 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2239 return false;
2240 }
2241 }
2242
2243 if (LocVT == MVT::v16i8 ||
2244 LocVT == MVT::v8i16 ||
2245 LocVT == MVT::v4i32 ||
2246 LocVT == MVT::v2i64 ||
2247 LocVT == MVT::v4f32 ||
2248 LocVT == MVT::v2f64) {
2249 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2250 static const MCPhysReg RegList5[] = {
2251 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2252 };
2253 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2254 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2255 return false;
2256 }
2257 }
2258 }
2259
2260 if (LocVT == MVT::v32i8 ||
2261 LocVT == MVT::v16i16 ||
2262 LocVT == MVT::v8i32 ||
2263 LocVT == MVT::v4i64 ||
2264 LocVT == MVT::v8f32 ||
2265 LocVT == MVT::v4f64) {
2266 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
2267 static const MCPhysReg RegList6[] = {
2268 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2269 };
2270 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2271 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2272 return false;
2273 }
2274 }
2275 }
2276
2277 if (LocVT == MVT::v64i8 ||
2278 LocVT == MVT::v32i16 ||
2279 LocVT == MVT::v16i32 ||
2280 LocVT == MVT::v8i64 ||
2281 LocVT == MVT::v16f32 ||
2282 LocVT == MVT::v8f64) {
2283 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
2284 static const MCPhysReg RegList7[] = {
2285 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2286 };
2287 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2288 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2289 return false;
2290 }
2291 }
2292 }
2293
2294 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2295 if (LocVT == MVT::i32 ||
2296 LocVT == MVT::i64 ||
2297 LocVT == MVT::f32 ||
2298 LocVT == MVT::f64) {
2299 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
2300 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
2301 return false;
2302 }
2303 }
2304
2305 if (LocVT == MVT::i32 ||
2306 LocVT == MVT::f32) {
2307 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
2308 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
2309 return false;
2310 }
2311
2312 if (LocVT == MVT::i64 ||
2313 LocVT == MVT::f64) {
2314 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
2315 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
2316 return false;
2317 }
2318
2319 if (LocVT == MVT::f80 ||
2320 LocVT == MVT::f128) {
2321 int64_t Offset11 = State.AllocateStack(
2322 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
2323 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
2324 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
2325 return false;
2326 }
2327
2328 if (LocVT == MVT::v16i8 ||
2329 LocVT == MVT::v8i16 ||
2330 LocVT == MVT::v4i32 ||
2331 LocVT == MVT::v2i64 ||
2332 LocVT == MVT::v4f32 ||
2333 LocVT == MVT::v2f64) {
2334 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
2335 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
2336 return false;
2337 }
2338
2339 if (LocVT == MVT::v32i8 ||
2340 LocVT == MVT::v16i16 ||
2341 LocVT == MVT::v8i32 ||
2342 LocVT == MVT::v4i64 ||
2343 LocVT == MVT::v8f32 ||
2344 LocVT == MVT::v4f64) {
2345 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
2346 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2347 return false;
2348 }
2349
2350 if (LocVT == MVT::v64i8 ||
2351 LocVT == MVT::v32i16 ||
2352 LocVT == MVT::v16i32 ||
2353 LocVT == MVT::v8i64 ||
2354 LocVT == MVT::v16f32 ||
2355 LocVT == MVT::v8f64) {
2356 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
2357 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
2358 return false;
2359 }
2360
2361 return true; // CC didn't match.
2362}
2363
2364
2365static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
2366 MVT LocVT, CCValAssign::LocInfo LocInfo,
2367 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2368
2369 if (LocVT == MVT::i32) {
2370 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
2371 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2372 return false;
2373 }
2374 }
2375
2376 return true; // CC didn't match.
2377}
2378
2379
2380static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT,
2381 MVT LocVT, CCValAssign::LocInfo LocInfo,
2382 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2383
2384 if (LocVT == MVT::v16i8 ||
2385 LocVT == MVT::v8i16 ||
2386 LocVT == MVT::v4i32 ||
2387 LocVT == MVT::v2i64 ||
2388 LocVT == MVT::v8f16 ||
2389 LocVT == MVT::v8bf16 ||
2390 LocVT == MVT::v4f32 ||
2391 LocVT == MVT::v2f64) {
2392 int64_t Offset1 = State.AllocateStack(Size: 16, Alignment: Align(4));
2393 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
2394 return false;
2395 }
2396
2397 if (LocVT == MVT::v32i8 ||
2398 LocVT == MVT::v16i16 ||
2399 LocVT == MVT::v8i32 ||
2400 LocVT == MVT::v4i64 ||
2401 LocVT == MVT::v16f16 ||
2402 LocVT == MVT::v16bf16 ||
2403 LocVT == MVT::v8f32 ||
2404 LocVT == MVT::v4f64) {
2405 int64_t Offset2 = State.AllocateStack(Size: 32, Alignment: Align(4));
2406 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
2407 return false;
2408 }
2409
2410 if (LocVT == MVT::v64i8 ||
2411 LocVT == MVT::v32i16 ||
2412 LocVT == MVT::v16i32 ||
2413 LocVT == MVT::v8i64 ||
2414 LocVT == MVT::v32f16 ||
2415 LocVT == MVT::v32bf16 ||
2416 LocVT == MVT::v16f32 ||
2417 LocVT == MVT::v8f64) {
2418 int64_t Offset3 = State.AllocateStack(Size: 64, Alignment: Align(4));
2419 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
2420 return false;
2421 }
2422
2423 return true; // CC didn't match.
2424}
2425
2426
2427static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
2428 MVT LocVT, CCValAssign::LocInfo LocInfo,
2429 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2430
2431 if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2432 return false;
2433
2434 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
2435 return false;
2436
2437 return true; // CC didn't match.
2438}
2439
2440
2441static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
2442 MVT LocVT, CCValAssign::LocInfo LocInfo,
2443 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2444
2445 if (ArgFlags.isByVal()) {
2446 LocVT = MVT::i64;
2447 LocInfo = CCValAssign::Indirect;
2448 }
2449
2450 if (LocVT == MVT::i1 ||
2451 LocVT == MVT::v1i1) {
2452 LocVT = MVT::i8;
2453 if (ArgFlags.isSExt())
2454 LocInfo = CCValAssign::SExt;
2455 else if (ArgFlags.isZExt())
2456 LocInfo = CCValAssign::ZExt;
2457 else
2458 LocInfo = CCValAssign::AExt;
2459 }
2460
2461 if (ArgFlags.isNest()) {
2462 if (MCRegister Reg = State.AllocateReg(Reg: X86::R10)) {
2463 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2464 return false;
2465 }
2466 }
2467
2468 if (ArgFlags.isSwiftError()) {
2469 if (LocVT == MVT::i64) {
2470 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
2471 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2472 return false;
2473 }
2474 }
2475 }
2476
2477 if (ArgFlags.isSwiftSelf()) {
2478 if (LocVT == MVT::i64) {
2479 if (MCRegister Reg = State.AllocateReg(Reg: X86::R13)) {
2480 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2481 return false;
2482 }
2483 }
2484 }
2485
2486 if (ArgFlags.isSwiftAsync()) {
2487 if (LocVT == MVT::i64) {
2488 if (MCRegister Reg = State.AllocateReg(Reg: X86::R14)) {
2489 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2490 return false;
2491 }
2492 }
2493 }
2494
2495 if (ArgFlags.isCFGuardTarget()) {
2496 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
2497 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2498 return false;
2499 }
2500 }
2501
2502 if (LocVT == MVT::v16i8 ||
2503 LocVT == MVT::v8i16 ||
2504 LocVT == MVT::v4i32 ||
2505 LocVT == MVT::v2i64 ||
2506 LocVT == MVT::v8f16 ||
2507 LocVT == MVT::v8bf16 ||
2508 LocVT == MVT::v4f32 ||
2509 LocVT == MVT::v2f64) {
2510 LocVT = MVT::i64;
2511 LocInfo = CCValAssign::Indirect;
2512 }
2513
2514 if (LocVT == MVT::v32i8 ||
2515 LocVT == MVT::v16i16 ||
2516 LocVT == MVT::v8i32 ||
2517 LocVT == MVT::v4i64 ||
2518 LocVT == MVT::v16f16 ||
2519 LocVT == MVT::v16bf16 ||
2520 LocVT == MVT::v8f32 ||
2521 LocVT == MVT::v4f64) {
2522 LocVT = MVT::i64;
2523 LocInfo = CCValAssign::Indirect;
2524 }
2525
2526 if (LocVT == MVT::v64i8 ||
2527 LocVT == MVT::v32i16 ||
2528 LocVT == MVT::v16i32 ||
2529 LocVT == MVT::v32f16 ||
2530 LocVT == MVT::v32bf16 ||
2531 LocVT == MVT::v16f32 ||
2532 LocVT == MVT::v8f64 ||
2533 LocVT == MVT::v8i64) {
2534 LocVT = MVT::i64;
2535 LocInfo = CCValAssign::Indirect;
2536 }
2537
2538 if (LocVT == MVT::f80) {
2539 LocVT = MVT::i64;
2540 LocInfo = CCValAssign::Indirect;
2541 }
2542
2543 if (LocVT == MVT::f128) {
2544 LocVT = MVT::i64;
2545 LocInfo = CCValAssign::Indirect;
2546 }
2547
2548 if (LocVT == MVT::f32) {
2549 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2550 LocVT = MVT::i32;
2551 LocInfo = CCValAssign::BCvt;
2552 }
2553 }
2554
2555 if (LocVT == MVT::f64) {
2556 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2557 LocVT = MVT::i64;
2558 LocInfo = CCValAssign::BCvt;
2559 }
2560 }
2561
2562 if (LocVT == MVT::f16 ||
2563 LocVT == MVT::f32 ||
2564 LocVT == MVT::f64) {
2565 static const MCPhysReg RegList1[] = {
2566 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2567 };
2568 static const MCPhysReg RegList2[] = {
2569 X86::RCX, X86::RDX, X86::R8, X86::R9
2570 };
2571 if (MCRegister Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
2572 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2573 return false;
2574 }
2575 }
2576
2577 if (LocVT == MVT::i8) {
2578 static const MCPhysReg RegList3[] = {
2579 X86::CL, X86::DL, X86::R8B, X86::R9B
2580 };
2581 static const MCPhysReg RegList4[] = {
2582 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2583 };
2584 if (MCRegister Reg = State.AllocateReg(Regs: RegList3, ShadowRegs: RegList4)) {
2585 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2586 return false;
2587 }
2588 }
2589
2590 if (LocVT == MVT::i16) {
2591 static const MCPhysReg RegList5[] = {
2592 X86::CX, X86::DX, X86::R8W, X86::R9W
2593 };
2594 static const MCPhysReg RegList6[] = {
2595 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2596 };
2597 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
2598 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2599 return false;
2600 }
2601 }
2602
2603 if (LocVT == MVT::i32) {
2604 static const MCPhysReg RegList7[] = {
2605 X86::ECX, X86::EDX, X86::R8D, X86::R9D
2606 };
2607 static const MCPhysReg RegList8[] = {
2608 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2609 };
2610 if (MCRegister Reg = State.AllocateReg(Regs: RegList7, ShadowRegs: RegList8)) {
2611 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2612 return false;
2613 }
2614 }
2615
2616 if (State.getCallingConv() == CallingConv::X86_ThisCall) {
2617 if (ArgFlags.isSRet()) {
2618 if (LocVT == MVT::i64) {
2619 static const MCPhysReg RegList9[] = {
2620 X86::RDX, X86::R8, X86::R9
2621 };
2622 static const MCPhysReg RegList10[] = {
2623 X86::XMM1, X86::XMM2, X86::XMM3
2624 };
2625 if (MCRegister Reg = State.AllocateReg(Regs: RegList9, ShadowRegs: RegList10)) {
2626 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2627 return false;
2628 }
2629 }
2630 }
2631 }
2632
2633 if (LocVT == MVT::i64) {
2634 static const MCPhysReg RegList11[] = {
2635 X86::RCX, X86::RDX, X86::R8, X86::R9
2636 };
2637 static const MCPhysReg RegList12[] = {
2638 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2639 };
2640 if (MCRegister Reg = State.AllocateReg(Regs: RegList11, ShadowRegs: RegList12)) {
2641 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2642 return false;
2643 }
2644 }
2645
2646 if (LocVT == MVT::i8 ||
2647 LocVT == MVT::i16 ||
2648 LocVT == MVT::i32 ||
2649 LocVT == MVT::i64 ||
2650 LocVT == MVT::f16 ||
2651 LocVT == MVT::f32 ||
2652 LocVT == MVT::f64) {
2653 int64_t Offset13 = State.AllocateStack(Size: 8, Alignment: Align(8));
2654 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2655 return false;
2656 }
2657
2658 return true; // CC didn't match.
2659}
2660
2661
2662static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
2663 MVT LocVT, CCValAssign::LocInfo LocInfo,
2664 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2665
2666 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2667 if (ArgFlags.isByVal()) {
2668 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2669 return false;
2670 }
2671 }
2672
2673 if (ArgFlags.isByVal()) {
2674 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2675 return false;
2676 }
2677
2678 if (LocVT == MVT::i1 ||
2679 LocVT == MVT::i8 ||
2680 LocVT == MVT::i16 ||
2681 LocVT == MVT::v1i1) {
2682 LocVT = MVT::i32;
2683 if (ArgFlags.isSExt())
2684 LocInfo = CCValAssign::SExt;
2685 else if (ArgFlags.isZExt())
2686 LocInfo = CCValAssign::ZExt;
2687 else
2688 LocInfo = CCValAssign::AExt;
2689 }
2690
2691 if (LocVT == MVT::v8i1 ||
2692 LocVT == MVT::v16i1 ||
2693 LocVT == MVT::v32i1) {
2694 LocVT = MVT::i32;
2695 if (ArgFlags.isSExt())
2696 LocInfo = CCValAssign::SExt;
2697 else if (ArgFlags.isZExt())
2698 LocInfo = CCValAssign::ZExt;
2699 else
2700 LocInfo = CCValAssign::AExt;
2701 }
2702
2703 if (LocVT == MVT::i32) {
2704 static const MCPhysReg RegList1[] = {
2705 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2706 };
2707 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2708 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2709 return false;
2710 }
2711 }
2712
2713 if (LocVT == MVT::i64) {
2714 static const MCPhysReg RegList2[] = {
2715 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2716 };
2717 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2718 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2719 return false;
2720 }
2721 }
2722
2723 if (LocVT == MVT::v64i1) {
2724 LocVT = MVT::i64;
2725 if (ArgFlags.isSExt())
2726 LocInfo = CCValAssign::SExt;
2727 else if (ArgFlags.isZExt())
2728 LocInfo = CCValAssign::ZExt;
2729 else
2730 LocInfo = CCValAssign::AExt;
2731 }
2732
2733 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2734 if (LocVT == MVT::i64) {
2735 static const MCPhysReg RegList3[] = {
2736 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2737 };
2738 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2739 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2740 return false;
2741 }
2742 }
2743 }
2744
2745 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
2746 if (LocVT == MVT::i64) {
2747 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2748 return false;
2749 }
2750 }
2751
2752 if (LocVT == MVT::f32 ||
2753 LocVT == MVT::f64 ||
2754 LocVT == MVT::f128) {
2755 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2756 static const MCPhysReg RegList4[] = {
2757 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2758 };
2759 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2760 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2761 return false;
2762 }
2763 }
2764 }
2765
2766 if (LocVT == MVT::f80) {
2767 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
2768 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2769 return false;
2770 }
2771 }
2772
2773 if (LocVT == MVT::v16i8 ||
2774 LocVT == MVT::v8i16 ||
2775 LocVT == MVT::v4i32 ||
2776 LocVT == MVT::v2i64 ||
2777 LocVT == MVT::v4f32 ||
2778 LocVT == MVT::v2f64) {
2779 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2780 static const MCPhysReg RegList5[] = {
2781 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2782 };
2783 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2784 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2785 return false;
2786 }
2787 }
2788 }
2789
2790 if (LocVT == MVT::v32i8 ||
2791 LocVT == MVT::v16i16 ||
2792 LocVT == MVT::v8i32 ||
2793 LocVT == MVT::v4i64 ||
2794 LocVT == MVT::v8f32 ||
2795 LocVT == MVT::v4f64) {
2796 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
2797 static const MCPhysReg RegList6[] = {
2798 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2799 };
2800 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2801 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2802 return false;
2803 }
2804 }
2805 }
2806
2807 if (LocVT == MVT::v64i8 ||
2808 LocVT == MVT::v32i16 ||
2809 LocVT == MVT::v16i32 ||
2810 LocVT == MVT::v8i64 ||
2811 LocVT == MVT::v16f32 ||
2812 LocVT == MVT::v8f64) {
2813 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
2814 static const MCPhysReg RegList7[] = {
2815 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2816 };
2817 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2818 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2819 return false;
2820 }
2821 }
2822 }
2823
2824 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2825 if (LocVT == MVT::i32 ||
2826 LocVT == MVT::i64 ||
2827 LocVT == MVT::f32 ||
2828 LocVT == MVT::f64) {
2829 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
2830 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
2831 return false;
2832 }
2833 }
2834
2835 if (LocVT == MVT::i32 ||
2836 LocVT == MVT::f32) {
2837 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
2838 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
2839 return false;
2840 }
2841
2842 if (LocVT == MVT::i64 ||
2843 LocVT == MVT::f64) {
2844 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
2845 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
2846 return false;
2847 }
2848
2849 if (LocVT == MVT::f80 ||
2850 LocVT == MVT::f128) {
2851 int64_t Offset11 = State.AllocateStack(
2852 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
2853 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
2854 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
2855 return false;
2856 }
2857
2858 if (LocVT == MVT::v16i8 ||
2859 LocVT == MVT::v8i16 ||
2860 LocVT == MVT::v4i32 ||
2861 LocVT == MVT::v2i64 ||
2862 LocVT == MVT::v4f32 ||
2863 LocVT == MVT::v2f64) {
2864 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
2865 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
2866 return false;
2867 }
2868
2869 if (LocVT == MVT::v32i8 ||
2870 LocVT == MVT::v16i16 ||
2871 LocVT == MVT::v8i32 ||
2872 LocVT == MVT::v4i64 ||
2873 LocVT == MVT::v8f32 ||
2874 LocVT == MVT::v4f64) {
2875 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
2876 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2877 return false;
2878 }
2879
2880 if (LocVT == MVT::v64i8 ||
2881 LocVT == MVT::v32i16 ||
2882 LocVT == MVT::v16i32 ||
2883 LocVT == MVT::v8i64 ||
2884 LocVT == MVT::v16f32 ||
2885 LocVT == MVT::v8f64) {
2886 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
2887 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
2888 return false;
2889 }
2890
2891 return true; // CC didn't match.
2892}
2893
2894
2895static bool CC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
2896 MVT LocVT, CCValAssign::LocInfo LocInfo,
2897 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2898
2899 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2900 if (ArgFlags.isByVal()) {
2901 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2902 return false;
2903 }
2904 }
2905
2906 if (ArgFlags.isByVal()) {
2907 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2908 return false;
2909 }
2910
2911 if (LocVT == MVT::i1 ||
2912 LocVT == MVT::i8 ||
2913 LocVT == MVT::i16 ||
2914 LocVT == MVT::v1i1) {
2915 LocVT = MVT::i32;
2916 if (ArgFlags.isSExt())
2917 LocInfo = CCValAssign::SExt;
2918 else if (ArgFlags.isZExt())
2919 LocInfo = CCValAssign::ZExt;
2920 else
2921 LocInfo = CCValAssign::AExt;
2922 }
2923
2924 if (LocVT == MVT::v8i1 ||
2925 LocVT == MVT::v16i1 ||
2926 LocVT == MVT::v32i1) {
2927 LocVT = MVT::i32;
2928 if (ArgFlags.isSExt())
2929 LocInfo = CCValAssign::SExt;
2930 else if (ArgFlags.isZExt())
2931 LocInfo = CCValAssign::ZExt;
2932 else
2933 LocInfo = CCValAssign::AExt;
2934 }
2935
2936 if (LocVT == MVT::i32) {
2937 static const MCPhysReg RegList1[] = {
2938 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2939 };
2940 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2941 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2942 return false;
2943 }
2944 }
2945
2946 if (LocVT == MVT::i64) {
2947 static const MCPhysReg RegList2[] = {
2948 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
2949 };
2950 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2951 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2952 return false;
2953 }
2954 }
2955
2956 if (LocVT == MVT::v64i1) {
2957 LocVT = MVT::i64;
2958 if (ArgFlags.isSExt())
2959 LocInfo = CCValAssign::SExt;
2960 else if (ArgFlags.isZExt())
2961 LocInfo = CCValAssign::ZExt;
2962 else
2963 LocInfo = CCValAssign::AExt;
2964 }
2965
2966 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2967 if (LocVT == MVT::i64) {
2968 static const MCPhysReg RegList3[] = {
2969 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
2970 };
2971 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2972 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2973 return false;
2974 }
2975 }
2976 }
2977
2978 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
2979 if (LocVT == MVT::i64) {
2980 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2981 return false;
2982 }
2983 }
2984
2985 if (LocVT == MVT::f32 ||
2986 LocVT == MVT::f64 ||
2987 LocVT == MVT::f128) {
2988 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2989 static const MCPhysReg RegList4[] = {
2990 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2991 };
2992 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2993 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2994 return false;
2995 }
2996 }
2997 }
2998
2999 if (LocVT == MVT::f80) {
3000 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
3001 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3002 return false;
3003 }
3004 }
3005
3006 if (LocVT == MVT::v16i8 ||
3007 LocVT == MVT::v8i16 ||
3008 LocVT == MVT::v4i32 ||
3009 LocVT == MVT::v2i64 ||
3010 LocVT == MVT::v4f32 ||
3011 LocVT == MVT::v2f64) {
3012 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3013 static const MCPhysReg RegList5[] = {
3014 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3015 };
3016 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3017 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3018 return false;
3019 }
3020 }
3021 }
3022
3023 if (LocVT == MVT::v32i8 ||
3024 LocVT == MVT::v16i16 ||
3025 LocVT == MVT::v8i32 ||
3026 LocVT == MVT::v4i64 ||
3027 LocVT == MVT::v8f32 ||
3028 LocVT == MVT::v4f64) {
3029 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
3030 static const MCPhysReg RegList6[] = {
3031 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3032 };
3033 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3034 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3035 return false;
3036 }
3037 }
3038 }
3039
3040 if (LocVT == MVT::v64i8 ||
3041 LocVT == MVT::v32i16 ||
3042 LocVT == MVT::v16i32 ||
3043 LocVT == MVT::v8i64 ||
3044 LocVT == MVT::v16f32 ||
3045 LocVT == MVT::v8f64) {
3046 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
3047 static const MCPhysReg RegList7[] = {
3048 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3049 };
3050 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3051 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3052 return false;
3053 }
3054 }
3055 }
3056
3057 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3058 if (LocVT == MVT::i32 ||
3059 LocVT == MVT::i64 ||
3060 LocVT == MVT::f32 ||
3061 LocVT == MVT::f64) {
3062 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
3063 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
3064 return false;
3065 }
3066 }
3067
3068 if (LocVT == MVT::i32 ||
3069 LocVT == MVT::f32) {
3070 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
3071 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
3072 return false;
3073 }
3074
3075 if (LocVT == MVT::i64 ||
3076 LocVT == MVT::f64) {
3077 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
3078 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
3079 return false;
3080 }
3081
3082 if (LocVT == MVT::f80 ||
3083 LocVT == MVT::f128) {
3084 int64_t Offset11 = State.AllocateStack(
3085 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
3086 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
3087 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
3088 return false;
3089 }
3090
3091 if (LocVT == MVT::v16i8 ||
3092 LocVT == MVT::v8i16 ||
3093 LocVT == MVT::v4i32 ||
3094 LocVT == MVT::v2i64 ||
3095 LocVT == MVT::v4f32 ||
3096 LocVT == MVT::v2f64) {
3097 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
3098 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
3099 return false;
3100 }
3101
3102 if (LocVT == MVT::v32i8 ||
3103 LocVT == MVT::v16i16 ||
3104 LocVT == MVT::v8i32 ||
3105 LocVT == MVT::v4i64 ||
3106 LocVT == MVT::v8f32 ||
3107 LocVT == MVT::v4f64) {
3108 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
3109 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
3110 return false;
3111 }
3112
3113 if (LocVT == MVT::v64i8 ||
3114 LocVT == MVT::v32i16 ||
3115 LocVT == MVT::v16i32 ||
3116 LocVT == MVT::v8i64 ||
3117 LocVT == MVT::v16f32 ||
3118 LocVT == MVT::v8f64) {
3119 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
3120 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
3121 return false;
3122 }
3123
3124 return true; // CC didn't match.
3125}
3126
3127
3128static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
3129 MVT LocVT, CCValAssign::LocInfo LocInfo,
3130 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3131
3132 if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3133 return false;
3134
3135 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3136 return false;
3137
3138 return true; // CC didn't match.
3139}
3140
3141
3142static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
3143 MVT LocVT, CCValAssign::LocInfo LocInfo,
3144 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3145
3146 if (LocVT == MVT::f32 ||
3147 LocVT == MVT::f64 ||
3148 LocVT == MVT::v4i32 ||
3149 LocVT == MVT::v2i64 ||
3150 LocVT == MVT::v4f32 ||
3151 LocVT == MVT::v2f64) {
3152 static const MCPhysReg RegList1[] = {
3153 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3154 };
3155 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3156 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3157 return false;
3158 }
3159 }
3160
3161 if (LocVT == MVT::v8f32 ||
3162 LocVT == MVT::v4f64 ||
3163 LocVT == MVT::v8i32 ||
3164 LocVT == MVT::v4i64) {
3165 static const MCPhysReg RegList2[] = {
3166 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
3167 };
3168 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3169 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3170 return false;
3171 }
3172 }
3173
3174 if (LocVT == MVT::v16f32 ||
3175 LocVT == MVT::v8f64 ||
3176 LocVT == MVT::v16i32 ||
3177 LocVT == MVT::v8i64) {
3178 static const MCPhysReg RegList3[] = {
3179 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
3180 };
3181 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3182 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3183 return false;
3184 }
3185 }
3186
3187 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3188 return false;
3189
3190 return true; // CC didn't match.
3191}
3192
3193
3194bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
3195 MVT LocVT, CCValAssign::LocInfo LocInfo,
3196 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3197
3198 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
3199 if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3200 return false;
3201 }
3202
3203 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3204 if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3205 return false;
3206 }
3207
3208 if (!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3209 return false;
3210
3211 return true; // CC didn't match.
3212}
3213
3214
3215static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
3216 MVT LocVT, CCValAssign::LocInfo LocInfo,
3217 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3218
3219 if (LocVT == MVT::v1i1) {
3220 LocVT = MVT::i8;
3221 if (ArgFlags.isSExt())
3222 LocInfo = CCValAssign::SExt;
3223 else if (ArgFlags.isZExt())
3224 LocInfo = CCValAssign::ZExt;
3225 else
3226 LocInfo = CCValAssign::AExt;
3227 }
3228
3229 if (LocVT == MVT::i1) {
3230 LocVT = MVT::i8;
3231 if (ArgFlags.isSExt())
3232 LocInfo = CCValAssign::SExt;
3233 else if (ArgFlags.isZExt())
3234 LocInfo = CCValAssign::ZExt;
3235 else
3236 LocInfo = CCValAssign::AExt;
3237 }
3238
3239 if (LocVT == MVT::i8) {
3240 static const MCPhysReg RegList1[] = {
3241 X86::AL, X86::DL, X86::CL
3242 };
3243 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3244 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3245 return false;
3246 }
3247 }
3248
3249 if (LocVT == MVT::i16) {
3250 static const MCPhysReg RegList2[] = {
3251 X86::AX, X86::DX, X86::CX
3252 };
3253 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3254 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3255 return false;
3256 }
3257 }
3258
3259 if (LocVT == MVT::i32) {
3260 static const MCPhysReg RegList3[] = {
3261 X86::EAX, X86::EDX, X86::ECX
3262 };
3263 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3264 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3265 return false;
3266 }
3267 }
3268
3269 if (LocVT == MVT::i64) {
3270 static const MCPhysReg RegList4[] = {
3271 X86::RAX, X86::RDX, X86::RCX
3272 };
3273 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3274 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3275 return false;
3276 }
3277 }
3278
3279 if (LocVT == MVT::v2i1) {
3280 LocVT = MVT::v2i64;
3281 if (ArgFlags.isSExt())
3282 LocInfo = CCValAssign::SExt;
3283 else if (ArgFlags.isZExt())
3284 LocInfo = CCValAssign::ZExt;
3285 else
3286 LocInfo = CCValAssign::AExt;
3287 }
3288
3289 if (LocVT == MVT::v4i1) {
3290 LocVT = MVT::v4i32;
3291 if (ArgFlags.isSExt())
3292 LocInfo = CCValAssign::SExt;
3293 else if (ArgFlags.isZExt())
3294 LocInfo = CCValAssign::ZExt;
3295 else
3296 LocInfo = CCValAssign::AExt;
3297 }
3298
3299 if (LocVT == MVT::v8i1) {
3300 LocVT = MVT::v8i16;
3301 if (ArgFlags.isSExt())
3302 LocInfo = CCValAssign::SExt;
3303 else if (ArgFlags.isZExt())
3304 LocInfo = CCValAssign::ZExt;
3305 else
3306 LocInfo = CCValAssign::AExt;
3307 }
3308
3309 if (LocVT == MVT::v16i1) {
3310 LocVT = MVT::v16i8;
3311 if (ArgFlags.isSExt())
3312 LocInfo = CCValAssign::SExt;
3313 else if (ArgFlags.isZExt())
3314 LocInfo = CCValAssign::ZExt;
3315 else
3316 LocInfo = CCValAssign::AExt;
3317 }
3318
3319 if (LocVT == MVT::v32i1) {
3320 LocVT = MVT::v32i8;
3321 if (ArgFlags.isSExt())
3322 LocInfo = CCValAssign::SExt;
3323 else if (ArgFlags.isZExt())
3324 LocInfo = CCValAssign::ZExt;
3325 else
3326 LocInfo = CCValAssign::AExt;
3327 }
3328
3329 if (LocVT == MVT::v64i1) {
3330 LocVT = MVT::v64i8;
3331 if (ArgFlags.isSExt())
3332 LocInfo = CCValAssign::SExt;
3333 else if (ArgFlags.isZExt())
3334 LocInfo = CCValAssign::ZExt;
3335 else
3336 LocInfo = CCValAssign::AExt;
3337 }
3338
3339 if (LocVT == MVT::v16i8 ||
3340 LocVT == MVT::v8i16 ||
3341 LocVT == MVT::v4i32 ||
3342 LocVT == MVT::v2i64 ||
3343 LocVT == MVT::v8f16 ||
3344 LocVT == MVT::v8bf16 ||
3345 LocVT == MVT::v4f32 ||
3346 LocVT == MVT::v2f64) {
3347 static const MCPhysReg RegList5[] = {
3348 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3349 };
3350 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3351 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3352 return false;
3353 }
3354 }
3355
3356 if (LocVT == MVT::v32i8 ||
3357 LocVT == MVT::v16i16 ||
3358 LocVT == MVT::v8i32 ||
3359 LocVT == MVT::v4i64 ||
3360 LocVT == MVT::v16f16 ||
3361 LocVT == MVT::v16bf16 ||
3362 LocVT == MVT::v8f32 ||
3363 LocVT == MVT::v4f64) {
3364 static const MCPhysReg RegList6[] = {
3365 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
3366 };
3367 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3368 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3369 return false;
3370 }
3371 }
3372
3373 if (LocVT == MVT::v64i8 ||
3374 LocVT == MVT::v32i16 ||
3375 LocVT == MVT::v16i32 ||
3376 LocVT == MVT::v8i64 ||
3377 LocVT == MVT::v32f16 ||
3378 LocVT == MVT::v32bf16 ||
3379 LocVT == MVT::v16f32 ||
3380 LocVT == MVT::v8f64) {
3381 static const MCPhysReg RegList7[] = {
3382 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
3383 };
3384 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3385 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3386 return false;
3387 }
3388 }
3389
3390 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
3391 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetUEFI64()) {
3392 if (LocVT == MVT::f80) {
3393 static const MCPhysReg RegList8[] = {
3394 X86::FP0, X86::FP1
3395 };
3396 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
3397 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3398 return false;
3399 }
3400 }
3401 }
3402 }
3403
3404 return true; // CC didn't match.
3405}
3406
3407
3408static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
3409 MVT LocVT, CCValAssign::LocInfo LocInfo,
3410 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3411
3412 if (State.getCallingConv() == CallingConv::Fast) {
3413 if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3414 return false;
3415 }
3416
3417 if (State.getCallingConv() == CallingConv::Tail) {
3418 if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3419 return false;
3420 }
3421
3422 if (State.getCallingConv() == CallingConv::HiPE) {
3423 if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3424 return false;
3425 }
3426
3427 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
3428 if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3429 return false;
3430 }
3431
3432 if (State.getCallingConv() == CallingConv::X86_RegCall) {
3433 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin32()) {
3434 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
3435 if (!RetCC_X86_32_RegCallv4_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3436 return false;
3437 }
3438 }
3439 }
3440
3441 if (State.getCallingConv() == CallingConv::X86_RegCall) {
3442 if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3443 return false;
3444 }
3445
3446 if (!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3447 return false;
3448
3449 return true; // CC didn't match.
3450}
3451
3452
3453static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
3454 MVT LocVT, CCValAssign::LocInfo LocInfo,
3455 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3456
3457 if (ArgFlags.isInReg()) {
3458 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
3459 if (LocVT == MVT::f32 ||
3460 LocVT == MVT::f64) {
3461 static const MCPhysReg RegList1[] = {
3462 X86::XMM0, X86::XMM1, X86::XMM2
3463 };
3464 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3465 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3466 return false;
3467 }
3468 }
3469 }
3470 }
3471
3472 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasX87()) {
3473 if (LocVT == MVT::f32 ||
3474 LocVT == MVT::f64) {
3475 static const MCPhysReg RegList2[] = {
3476 X86::FP0, X86::FP1
3477 };
3478 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3479 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3480 return false;
3481 }
3482 }
3483 }
3484
3485 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasX87()) {
3486 if (LocVT == MVT::f32) {
3487 static const MCPhysReg RegList3[] = {
3488 X86::EAX, X86::EDX, X86::ECX
3489 };
3490 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3491 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3492 return false;
3493 }
3494 }
3495 }
3496
3497 if (LocVT == MVT::f16) {
3498 static const MCPhysReg RegList4[] = {
3499 X86::XMM0, X86::XMM1, X86::XMM2
3500 };
3501 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3502 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3503 return false;
3504 }
3505 }
3506
3507 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3508 return false;
3509
3510 return true; // CC didn't match.
3511}
3512
3513
3514static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
3515 MVT LocVT, CCValAssign::LocInfo LocInfo,
3516 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3517
3518 if (LocVT == MVT::f32) {
3519 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
3520 static const MCPhysReg RegList1[] = {
3521 X86::XMM0, X86::XMM1, X86::XMM2
3522 };
3523 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3524 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3525 return false;
3526 }
3527 }
3528 }
3529
3530 if (LocVT == MVT::f64) {
3531 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
3532 static const MCPhysReg RegList2[] = {
3533 X86::XMM0, X86::XMM1, X86::XMM2
3534 };
3535 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3536 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3537 return false;
3538 }
3539 }
3540 }
3541
3542 if (LocVT == MVT::i8) {
3543 static const MCPhysReg RegList3[] = {
3544 X86::AL, X86::DL, X86::CL
3545 };
3546 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3547 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3548 return false;
3549 }
3550 }
3551
3552 if (LocVT == MVT::i16) {
3553 static const MCPhysReg RegList4[] = {
3554 X86::AX, X86::DX, X86::CX
3555 };
3556 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3557 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3558 return false;
3559 }
3560 }
3561
3562 if (LocVT == MVT::i32) {
3563 static const MCPhysReg RegList5[] = {
3564 X86::EAX, X86::EDX, X86::ECX
3565 };
3566 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3567 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3568 return false;
3569 }
3570 }
3571
3572 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3573 return false;
3574
3575 return true; // CC didn't match.
3576}
3577
3578
3579static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
3580 MVT LocVT, CCValAssign::LocInfo LocInfo,
3581 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3582
3583 if (LocVT == MVT::i8 ||
3584 LocVT == MVT::i16) {
3585 LocVT = MVT::i32;
3586 if (ArgFlags.isSExt())
3587 LocInfo = CCValAssign::SExt;
3588 else if (ArgFlags.isZExt())
3589 LocInfo = CCValAssign::ZExt;
3590 else
3591 LocInfo = CCValAssign::AExt;
3592 }
3593
3594 if (LocVT == MVT::i32) {
3595 static const MCPhysReg RegList1[] = {
3596 X86::ESI, X86::EBP, X86::EAX, X86::EDX
3597 };
3598 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3599 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3600 return false;
3601 }
3602 }
3603
3604 return true; // CC didn't match.
3605}
3606
3607
3608static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
3609 MVT LocVT, CCValAssign::LocInfo LocInfo,
3610 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3611
3612 if (LocVT == MVT::i1 ||
3613 LocVT == MVT::v1i1 ||
3614 LocVT == MVT::v8i1) {
3615 LocVT = MVT::i8;
3616 if (ArgFlags.isSExt())
3617 LocInfo = CCValAssign::SExt;
3618 else if (ArgFlags.isZExt())
3619 LocInfo = CCValAssign::ZExt;
3620 else
3621 LocInfo = CCValAssign::AExt;
3622 }
3623
3624 if (LocVT == MVT::v16i1) {
3625 LocVT = MVT::i16;
3626 if (ArgFlags.isSExt())
3627 LocInfo = CCValAssign::SExt;
3628 else if (ArgFlags.isZExt())
3629 LocInfo = CCValAssign::ZExt;
3630 else
3631 LocInfo = CCValAssign::AExt;
3632 }
3633
3634 if (LocVT == MVT::v32i1) {
3635 LocVT = MVT::i32;
3636 if (ArgFlags.isSExt())
3637 LocInfo = CCValAssign::SExt;
3638 else if (ArgFlags.isZExt())
3639 LocInfo = CCValAssign::ZExt;
3640 else
3641 LocInfo = CCValAssign::AExt;
3642 }
3643
3644 if (LocVT == MVT::i8) {
3645 static const MCPhysReg RegList1[] = {
3646 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL
3647 };
3648 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3649 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3650 return false;
3651 }
3652 }
3653
3654 if (LocVT == MVT::i16) {
3655 static const MCPhysReg RegList2[] = {
3656 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI
3657 };
3658 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3659 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3660 return false;
3661 }
3662 }
3663
3664 if (LocVT == MVT::i32) {
3665 static const MCPhysReg RegList3[] = {
3666 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
3667 };
3668 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3669 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3670 return false;
3671 }
3672 }
3673
3674 if (LocVT == MVT::i64) {
3675 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3676 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3677 return false;
3678 }
3679 }
3680
3681 if (LocVT == MVT::v64i1) {
3682 LocVT = MVT::i64;
3683 if (ArgFlags.isSExt())
3684 LocInfo = CCValAssign::SExt;
3685 else if (ArgFlags.isZExt())
3686 LocInfo = CCValAssign::ZExt;
3687 else
3688 LocInfo = CCValAssign::AExt;
3689 }
3690
3691 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3692 if (LocVT == MVT::i64) {
3693 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3694 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3695 return false;
3696 }
3697 }
3698 }
3699
3700 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
3701 if (LocVT == MVT::i64) {
3702 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3703 return false;
3704 }
3705 }
3706
3707 if (LocVT == MVT::f80) {
3708 static const MCPhysReg RegList4[] = {
3709 X86::FP0, X86::FP1
3710 };
3711 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3712 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3713 return false;
3714 }
3715 }
3716
3717 if (LocVT == MVT::f32 ||
3718 LocVT == MVT::f64 ||
3719 LocVT == MVT::f128) {
3720 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3721 static const MCPhysReg RegList5[] = {
3722 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3723 };
3724 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3725 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3726 return false;
3727 }
3728 }
3729 }
3730
3731 if (LocVT == MVT::v16i8 ||
3732 LocVT == MVT::v8i16 ||
3733 LocVT == MVT::v4i32 ||
3734 LocVT == MVT::v2i64 ||
3735 LocVT == MVT::v4f32 ||
3736 LocVT == MVT::v2f64) {
3737 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3738 static const MCPhysReg RegList6[] = {
3739 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3740 };
3741 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3742 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3743 return false;
3744 }
3745 }
3746 }
3747
3748 if (LocVT == MVT::v32i8 ||
3749 LocVT == MVT::v16i16 ||
3750 LocVT == MVT::v8i32 ||
3751 LocVT == MVT::v4i64 ||
3752 LocVT == MVT::v8f32 ||
3753 LocVT == MVT::v4f64) {
3754 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
3755 static const MCPhysReg RegList7[] = {
3756 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3757 };
3758 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3759 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3760 return false;
3761 }
3762 }
3763 }
3764
3765 if (LocVT == MVT::v64i8 ||
3766 LocVT == MVT::v32i16 ||
3767 LocVT == MVT::v16i32 ||
3768 LocVT == MVT::v8i64 ||
3769 LocVT == MVT::v16f32 ||
3770 LocVT == MVT::v8f64) {
3771 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
3772 static const MCPhysReg RegList8[] = {
3773 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3774 };
3775 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
3776 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3777 return false;
3778 }
3779 }
3780 }
3781
3782 return true; // CC didn't match.
3783}
3784
3785
3786static bool RetCC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
3787 MVT LocVT, CCValAssign::LocInfo LocInfo,
3788 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3789
3790 if (LocVT == MVT::i1 ||
3791 LocVT == MVT::v1i1 ||
3792 LocVT == MVT::v8i1) {
3793 LocVT = MVT::i8;
3794 if (ArgFlags.isSExt())
3795 LocInfo = CCValAssign::SExt;
3796 else if (ArgFlags.isZExt())
3797 LocInfo = CCValAssign::ZExt;
3798 else
3799 LocInfo = CCValAssign::AExt;
3800 }
3801
3802 if (LocVT == MVT::v16i1) {
3803 LocVT = MVT::i16;
3804 if (ArgFlags.isSExt())
3805 LocInfo = CCValAssign::SExt;
3806 else if (ArgFlags.isZExt())
3807 LocInfo = CCValAssign::ZExt;
3808 else
3809 LocInfo = CCValAssign::AExt;
3810 }
3811
3812 if (LocVT == MVT::v32i1) {
3813 LocVT = MVT::i32;
3814 if (ArgFlags.isSExt())
3815 LocInfo = CCValAssign::SExt;
3816 else if (ArgFlags.isZExt())
3817 LocInfo = CCValAssign::ZExt;
3818 else
3819 LocInfo = CCValAssign::AExt;
3820 }
3821
3822 if (LocVT == MVT::i8) {
3823 static const MCPhysReg RegList1[] = {
3824 X86::CL, X86::DL, X86::DIL, X86::SIL
3825 };
3826 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3827 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3828 return false;
3829 }
3830 }
3831
3832 if (LocVT == MVT::i16) {
3833 static const MCPhysReg RegList2[] = {
3834 X86::CX, X86::DX, X86::DI, X86::SI
3835 };
3836 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3837 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3838 return false;
3839 }
3840 }
3841
3842 if (LocVT == MVT::i32) {
3843 static const MCPhysReg RegList3[] = {
3844 X86::ECX, X86::EDX, X86::EDI, X86::ESI
3845 };
3846 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3847 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3848 return false;
3849 }
3850 }
3851
3852 if (LocVT == MVT::i64) {
3853 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3854 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3855 return false;
3856 }
3857 }
3858
3859 if (LocVT == MVT::v64i1) {
3860 LocVT = MVT::i64;
3861 if (ArgFlags.isSExt())
3862 LocInfo = CCValAssign::SExt;
3863 else if (ArgFlags.isZExt())
3864 LocInfo = CCValAssign::ZExt;
3865 else
3866 LocInfo = CCValAssign::AExt;
3867 }
3868
3869 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3870 if (LocVT == MVT::i64) {
3871 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3872 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3873 return false;
3874 }
3875 }
3876 }
3877
3878 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
3879 if (LocVT == MVT::i64) {
3880 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3881 return false;
3882 }
3883 }
3884
3885 if (LocVT == MVT::f80) {
3886 static const MCPhysReg RegList4[] = {
3887 X86::FP0, X86::FP1
3888 };
3889 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3890 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3891 return false;
3892 }
3893 }
3894
3895 if (LocVT == MVT::f32 ||
3896 LocVT == MVT::f64 ||
3897 LocVT == MVT::f128) {
3898 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3899 static const MCPhysReg RegList5[] = {
3900 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3901 };
3902 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3903 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3904 return false;
3905 }
3906 }
3907 }
3908
3909 if (LocVT == MVT::v16i8 ||
3910 LocVT == MVT::v8i16 ||
3911 LocVT == MVT::v4i32 ||
3912 LocVT == MVT::v2i64 ||
3913 LocVT == MVT::v4f32 ||
3914 LocVT == MVT::v2f64) {
3915 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3916 static const MCPhysReg RegList6[] = {
3917 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3918 };
3919 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3920 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3921 return false;
3922 }
3923 }
3924 }
3925
3926 if (LocVT == MVT::v32i8 ||
3927 LocVT == MVT::v16i16 ||
3928 LocVT == MVT::v8i32 ||
3929 LocVT == MVT::v4i64 ||
3930 LocVT == MVT::v8f32 ||
3931 LocVT == MVT::v4f64) {
3932 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
3933 static const MCPhysReg RegList7[] = {
3934 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3935 };
3936 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3937 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3938 return false;
3939 }
3940 }
3941 }
3942
3943 if (LocVT == MVT::v64i8 ||
3944 LocVT == MVT::v32i16 ||
3945 LocVT == MVT::v16i32 ||
3946 LocVT == MVT::v8i64 ||
3947 LocVT == MVT::v16f32 ||
3948 LocVT == MVT::v8f64) {
3949 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
3950 static const MCPhysReg RegList8[] = {
3951 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3952 };
3953 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
3954 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3955 return false;
3956 }
3957 }
3958 }
3959
3960 return true; // CC didn't match.
3961}
3962
3963
3964static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
3965 MVT LocVT, CCValAssign::LocInfo LocInfo,
3966 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3967
3968 if (LocVT == MVT::f32 ||
3969 LocVT == MVT::f64 ||
3970 LocVT == MVT::f128) {
3971 static const MCPhysReg RegList1[] = {
3972 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3973 };
3974 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3975 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3976 return false;
3977 }
3978 }
3979
3980 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3981 return false;
3982
3983 return true; // CC didn't match.
3984}
3985
3986
3987static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
3988 MVT LocVT, CCValAssign::LocInfo LocInfo,
3989 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3990
3991 if (State.getCallingConv() == CallingConv::HiPE) {
3992 if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3993 return false;
3994 }
3995
3996 if (State.getCallingConv() == CallingConv::AnyReg) {
3997 if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3998 return false;
3999 }
4000
4001 if (State.getCallingConv() == CallingConv::Swift) {
4002 if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4003 return false;
4004 }
4005
4006 if (State.getCallingConv() == CallingConv::SwiftTail) {
4007 if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4008 return false;
4009 }
4010
4011 if (State.getCallingConv() == CallingConv::Win64) {
4012 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4013 return false;
4014 }
4015
4016 if (State.getCallingConv() == CallingConv::X86_64_SysV) {
4017 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4018 return false;
4019 }
4020
4021 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
4022 if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4023 return false;
4024 }
4025
4026 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4027 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
4028 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
4029 if (!RetCC_X86_Win64_RegCallv4(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4030 return false;
4031 }
4032 }
4033 }
4034
4035 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4036 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
4037 if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4038 return false;
4039 }
4040 }
4041
4042 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4043 if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4044 return false;
4045 }
4046
4047 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
4048 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4049 return false;
4050 }
4051
4052 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetUEFI64()) {
4053 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4054 return false;
4055 }
4056
4057 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4058 return false;
4059
4060 return true; // CC didn't match.
4061}
4062
4063
4064static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
4065 MVT LocVT, CCValAssign::LocInfo LocInfo,
4066 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4067
4068 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4069 return false;
4070
4071 return true; // CC didn't match.
4072}
4073
4074
4075static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
4076 MVT LocVT, CCValAssign::LocInfo LocInfo,
4077 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4078
4079 if (LocVT == MVT::f16) {
4080 static const MCPhysReg RegList1[] = {
4081 X86::XMM0, X86::XMM1
4082 };
4083 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4084 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4085 return false;
4086 }
4087 }
4088
4089 if (LocVT == MVT::f32) {
4090 static const MCPhysReg RegList2[] = {
4091 X86::XMM0, X86::XMM1
4092 };
4093 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4094 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4095 return false;
4096 }
4097 }
4098
4099 if (LocVT == MVT::f64) {
4100 static const MCPhysReg RegList3[] = {
4101 X86::XMM0, X86::XMM1
4102 };
4103 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4104 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4105 return false;
4106 }
4107 }
4108
4109 if (LocVT == MVT::f128) {
4110 static const MCPhysReg RegList4[] = {
4111 X86::XMM0, X86::XMM1
4112 };
4113 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4114 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4115 return false;
4116 }
4117 }
4118
4119 if (ArgFlags.isPointer()) {
4120 if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4121 return false;
4122 }
4123
4124 if (ArgFlags.isSwiftError()) {
4125 if (LocVT == MVT::i64) {
4126 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
4127 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4128 return false;
4129 }
4130 }
4131 }
4132
4133 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4134 return false;
4135
4136 return true; // CC didn't match.
4137}
4138
4139
4140static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
4141 MVT LocVT, CCValAssign::LocInfo LocInfo,
4142 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4143
4144 if (LocVT == MVT::i8 ||
4145 LocVT == MVT::i16 ||
4146 LocVT == MVT::i32) {
4147 LocVT = MVT::i64;
4148 if (ArgFlags.isSExt())
4149 LocInfo = CCValAssign::SExt;
4150 else if (ArgFlags.isZExt())
4151 LocInfo = CCValAssign::ZExt;
4152 else
4153 LocInfo = CCValAssign::AExt;
4154 }
4155
4156 if (LocVT == MVT::i64) {
4157 static const MCPhysReg RegList1[] = {
4158 X86::R15, X86::RBP, X86::RAX, X86::RDX
4159 };
4160 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4161 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4162 return false;
4163 }
4164 }
4165
4166 return true; // CC didn't match.
4167}
4168
4169
4170static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
4171 MVT LocVT, CCValAssign::LocInfo LocInfo,
4172 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4173
4174 if (ArgFlags.isSwiftError()) {
4175 if (LocVT == MVT::i64) {
4176 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
4177 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4178 return false;
4179 }
4180 }
4181 }
4182
4183 if (LocVT == MVT::v1i1) {
4184 LocVT = MVT::i8;
4185 if (ArgFlags.isSExt())
4186 LocInfo = CCValAssign::SExt;
4187 else if (ArgFlags.isZExt())
4188 LocInfo = CCValAssign::ZExt;
4189 else
4190 LocInfo = CCValAssign::AExt;
4191 }
4192
4193 if (LocVT == MVT::i1) {
4194 LocVT = MVT::i8;
4195 if (ArgFlags.isSExt())
4196 LocInfo = CCValAssign::SExt;
4197 else if (ArgFlags.isZExt())
4198 LocInfo = CCValAssign::ZExt;
4199 else
4200 LocInfo = CCValAssign::AExt;
4201 }
4202
4203 if (LocVT == MVT::i8) {
4204 static const MCPhysReg RegList1[] = {
4205 X86::AL, X86::DL, X86::CL, X86::R8B
4206 };
4207 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4208 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4209 return false;
4210 }
4211 }
4212
4213 if (LocVT == MVT::i16) {
4214 static const MCPhysReg RegList2[] = {
4215 X86::AX, X86::DX, X86::CX, X86::R8W
4216 };
4217 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4218 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4219 return false;
4220 }
4221 }
4222
4223 if (LocVT == MVT::i32) {
4224 static const MCPhysReg RegList3[] = {
4225 X86::EAX, X86::EDX, X86::ECX, X86::R8D
4226 };
4227 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4228 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4229 return false;
4230 }
4231 }
4232
4233 if (LocVT == MVT::i64) {
4234 static const MCPhysReg RegList4[] = {
4235 X86::RAX, X86::RDX, X86::RCX, X86::R8
4236 };
4237 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4238 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4239 return false;
4240 }
4241 }
4242
4243 if (LocVT == MVT::f32) {
4244 static const MCPhysReg RegList5[] = {
4245 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4246 };
4247 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4248 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4249 return false;
4250 }
4251 }
4252
4253 if (LocVT == MVT::f64) {
4254 static const MCPhysReg RegList6[] = {
4255 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4256 };
4257 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4258 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4259 return false;
4260 }
4261 }
4262
4263 if (LocVT == MVT::f128) {
4264 static const MCPhysReg RegList7[] = {
4265 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4266 };
4267 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4268 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4269 return false;
4270 }
4271 }
4272
4273 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4274 return false;
4275
4276 return true; // CC didn't match.
4277}
4278
4279
4280static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
4281 MVT LocVT, CCValAssign::LocInfo LocInfo,
4282 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4283
4284 if (LocVT == MVT::f32 ||
4285 LocVT == MVT::f64 ||
4286 LocVT == MVT::f128) {
4287 static const MCPhysReg RegList1[] = {
4288 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4289 };
4290 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4291 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4292 return false;
4293 }
4294 }
4295
4296 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4297 return false;
4298
4299 return true; // CC didn't match.
4300}
4301
4302
4303static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
4304 MVT LocVT, CCValAssign::LocInfo LocInfo,
4305 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4306
4307 if (LocVT == MVT::i1 ||
4308 LocVT == MVT::v1i1 ||
4309 LocVT == MVT::v8i1) {
4310 LocVT = MVT::i8;
4311 if (ArgFlags.isSExt())
4312 LocInfo = CCValAssign::SExt;
4313 else if (ArgFlags.isZExt())
4314 LocInfo = CCValAssign::ZExt;
4315 else
4316 LocInfo = CCValAssign::AExt;
4317 }
4318
4319 if (LocVT == MVT::v16i1) {
4320 LocVT = MVT::i16;
4321 if (ArgFlags.isSExt())
4322 LocInfo = CCValAssign::SExt;
4323 else if (ArgFlags.isZExt())
4324 LocInfo = CCValAssign::ZExt;
4325 else
4326 LocInfo = CCValAssign::AExt;
4327 }
4328
4329 if (LocVT == MVT::v32i1) {
4330 LocVT = MVT::i32;
4331 if (ArgFlags.isSExt())
4332 LocInfo = CCValAssign::SExt;
4333 else if (ArgFlags.isZExt())
4334 LocInfo = CCValAssign::ZExt;
4335 else
4336 LocInfo = CCValAssign::AExt;
4337 }
4338
4339 if (LocVT == MVT::i8) {
4340 static const MCPhysReg RegList1[] = {
4341 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B
4342 };
4343 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4344 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4345 return false;
4346 }
4347 }
4348
4349 if (LocVT == MVT::i16) {
4350 static const MCPhysReg RegList2[] = {
4351 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W
4352 };
4353 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4354 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4355 return false;
4356 }
4357 }
4358
4359 if (LocVT == MVT::i32) {
4360 static const MCPhysReg RegList3[] = {
4361 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
4362 };
4363 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4364 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4365 return false;
4366 }
4367 }
4368
4369 if (LocVT == MVT::i64) {
4370 static const MCPhysReg RegList4[] = {
4371 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
4372 };
4373 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4374 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4375 return false;
4376 }
4377 }
4378
4379 if (LocVT == MVT::v64i1) {
4380 LocVT = MVT::i64;
4381 if (ArgFlags.isSExt())
4382 LocInfo = CCValAssign::SExt;
4383 else if (ArgFlags.isZExt())
4384 LocInfo = CCValAssign::ZExt;
4385 else
4386 LocInfo = CCValAssign::AExt;
4387 }
4388
4389 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
4390 if (LocVT == MVT::i64) {
4391 static const MCPhysReg RegList5[] = {
4392 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
4393 };
4394 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4395 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4396 return false;
4397 }
4398 }
4399 }
4400
4401 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
4402 if (LocVT == MVT::i64) {
4403 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4404 return false;
4405 }
4406 }
4407
4408 if (LocVT == MVT::f80) {
4409 static const MCPhysReg RegList6[] = {
4410 X86::FP0, X86::FP1
4411 };
4412 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4413 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4414 return false;
4415 }
4416 }
4417
4418 if (LocVT == MVT::f32 ||
4419 LocVT == MVT::f64 ||
4420 LocVT == MVT::f128) {
4421 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4422 static const MCPhysReg RegList7[] = {
4423 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4424 };
4425 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4426 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4427 return false;
4428 }
4429 }
4430 }
4431
4432 if (LocVT == MVT::v16i8 ||
4433 LocVT == MVT::v8i16 ||
4434 LocVT == MVT::v4i32 ||
4435 LocVT == MVT::v2i64 ||
4436 LocVT == MVT::v4f32 ||
4437 LocVT == MVT::v2f64) {
4438 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4439 static const MCPhysReg RegList8[] = {
4440 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4441 };
4442 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
4443 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4444 return false;
4445 }
4446 }
4447 }
4448
4449 if (LocVT == MVT::v32i8 ||
4450 LocVT == MVT::v16i16 ||
4451 LocVT == MVT::v8i32 ||
4452 LocVT == MVT::v4i64 ||
4453 LocVT == MVT::v8f32 ||
4454 LocVT == MVT::v4f64) {
4455 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
4456 static const MCPhysReg RegList9[] = {
4457 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4458 };
4459 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
4460 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4461 return false;
4462 }
4463 }
4464 }
4465
4466 if (LocVT == MVT::v64i8 ||
4467 LocVT == MVT::v32i16 ||
4468 LocVT == MVT::v16i32 ||
4469 LocVT == MVT::v8i64 ||
4470 LocVT == MVT::v16f32 ||
4471 LocVT == MVT::v8f64) {
4472 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
4473 static const MCPhysReg RegList10[] = {
4474 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4475 };
4476 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
4477 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4478 return false;
4479 }
4480 }
4481 }
4482
4483 return true; // CC didn't match.
4484}
4485
4486
4487static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
4488 MVT LocVT, CCValAssign::LocInfo LocInfo,
4489 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4490
4491 if (LocVT == MVT::f32) {
4492 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4493 LocVT = MVT::i32;
4494 LocInfo = CCValAssign::BCvt;
4495 }
4496 }
4497
4498 if (LocVT == MVT::f64) {
4499 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4500 LocVT = MVT::i64;
4501 LocInfo = CCValAssign::BCvt;
4502 }
4503 }
4504
4505 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4506 return false;
4507
4508 return true; // CC didn't match.
4509}
4510
4511
4512static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
4513 MVT LocVT, CCValAssign::LocInfo LocInfo,
4514 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4515
4516 if (LocVT == MVT::i1 ||
4517 LocVT == MVT::v1i1 ||
4518 LocVT == MVT::v8i1) {
4519 LocVT = MVT::i8;
4520 if (ArgFlags.isSExt())
4521 LocInfo = CCValAssign::SExt;
4522 else if (ArgFlags.isZExt())
4523 LocInfo = CCValAssign::ZExt;
4524 else
4525 LocInfo = CCValAssign::AExt;
4526 }
4527
4528 if (LocVT == MVT::v16i1) {
4529 LocVT = MVT::i16;
4530 if (ArgFlags.isSExt())
4531 LocInfo = CCValAssign::SExt;
4532 else if (ArgFlags.isZExt())
4533 LocInfo = CCValAssign::ZExt;
4534 else
4535 LocInfo = CCValAssign::AExt;
4536 }
4537
4538 if (LocVT == MVT::v32i1) {
4539 LocVT = MVT::i32;
4540 if (ArgFlags.isSExt())
4541 LocInfo = CCValAssign::SExt;
4542 else if (ArgFlags.isZExt())
4543 LocInfo = CCValAssign::ZExt;
4544 else
4545 LocInfo = CCValAssign::AExt;
4546 }
4547
4548 if (LocVT == MVT::i8) {
4549 static const MCPhysReg RegList1[] = {
4550 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
4551 };
4552 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4553 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4554 return false;
4555 }
4556 }
4557
4558 if (LocVT == MVT::i16) {
4559 static const MCPhysReg RegList2[] = {
4560 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
4561 };
4562 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4563 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4564 return false;
4565 }
4566 }
4567
4568 if (LocVT == MVT::i32) {
4569 static const MCPhysReg RegList3[] = {
4570 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
4571 };
4572 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4573 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4574 return false;
4575 }
4576 }
4577
4578 if (LocVT == MVT::i64) {
4579 static const MCPhysReg RegList4[] = {
4580 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
4581 };
4582 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4583 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4584 return false;
4585 }
4586 }
4587
4588 if (LocVT == MVT::v64i1) {
4589 LocVT = MVT::i64;
4590 if (ArgFlags.isSExt())
4591 LocInfo = CCValAssign::SExt;
4592 else if (ArgFlags.isZExt())
4593 LocInfo = CCValAssign::ZExt;
4594 else
4595 LocInfo = CCValAssign::AExt;
4596 }
4597
4598 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
4599 if (LocVT == MVT::i64) {
4600 static const MCPhysReg RegList5[] = {
4601 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
4602 };
4603 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4604 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4605 return false;
4606 }
4607 }
4608 }
4609
4610 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
4611 if (LocVT == MVT::i64) {
4612 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4613 return false;
4614 }
4615 }
4616
4617 if (LocVT == MVT::f80) {
4618 static const MCPhysReg RegList6[] = {
4619 X86::FP0, X86::FP1
4620 };
4621 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4622 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4623 return false;
4624 }
4625 }
4626
4627 if (LocVT == MVT::f32 ||
4628 LocVT == MVT::f64 ||
4629 LocVT == MVT::f128) {
4630 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4631 static const MCPhysReg RegList7[] = {
4632 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4633 };
4634 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4635 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4636 return false;
4637 }
4638 }
4639 }
4640
4641 if (LocVT == MVT::v16i8 ||
4642 LocVT == MVT::v8i16 ||
4643 LocVT == MVT::v4i32 ||
4644 LocVT == MVT::v2i64 ||
4645 LocVT == MVT::v4f32 ||
4646 LocVT == MVT::v2f64) {
4647 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4648 static const MCPhysReg RegList8[] = {
4649 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4650 };
4651 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
4652 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4653 return false;
4654 }
4655 }
4656 }
4657
4658 if (LocVT == MVT::v32i8 ||
4659 LocVT == MVT::v16i16 ||
4660 LocVT == MVT::v8i32 ||
4661 LocVT == MVT::v4i64 ||
4662 LocVT == MVT::v8f32 ||
4663 LocVT == MVT::v4f64) {
4664 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
4665 static const MCPhysReg RegList9[] = {
4666 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4667 };
4668 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
4669 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4670 return false;
4671 }
4672 }
4673 }
4674
4675 if (LocVT == MVT::v64i8 ||
4676 LocVT == MVT::v32i16 ||
4677 LocVT == MVT::v16i32 ||
4678 LocVT == MVT::v8i64 ||
4679 LocVT == MVT::v16f32 ||
4680 LocVT == MVT::v8f64) {
4681 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
4682 static const MCPhysReg RegList10[] = {
4683 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4684 };
4685 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
4686 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4687 return false;
4688 }
4689 }
4690 }
4691
4692 return true; // CC didn't match.
4693}
4694
4695
4696static bool RetCC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
4697 MVT LocVT, CCValAssign::LocInfo LocInfo,
4698 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4699
4700 if (LocVT == MVT::i1 ||
4701 LocVT == MVT::v1i1 ||
4702 LocVT == MVT::v8i1) {
4703 LocVT = MVT::i8;
4704 if (ArgFlags.isSExt())
4705 LocInfo = CCValAssign::SExt;
4706 else if (ArgFlags.isZExt())
4707 LocInfo = CCValAssign::ZExt;
4708 else
4709 LocInfo = CCValAssign::AExt;
4710 }
4711
4712 if (LocVT == MVT::v16i1) {
4713 LocVT = MVT::i16;
4714 if (ArgFlags.isSExt())
4715 LocInfo = CCValAssign::SExt;
4716 else if (ArgFlags.isZExt())
4717 LocInfo = CCValAssign::ZExt;
4718 else
4719 LocInfo = CCValAssign::AExt;
4720 }
4721
4722 if (LocVT == MVT::v32i1) {
4723 LocVT = MVT::i32;
4724 if (ArgFlags.isSExt())
4725 LocInfo = CCValAssign::SExt;
4726 else if (ArgFlags.isZExt())
4727 LocInfo = CCValAssign::ZExt;
4728 else
4729 LocInfo = CCValAssign::AExt;
4730 }
4731
4732 if (LocVT == MVT::i8) {
4733 static const MCPhysReg RegList1[] = {
4734 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
4735 };
4736 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4737 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4738 return false;
4739 }
4740 }
4741
4742 if (LocVT == MVT::i16) {
4743 static const MCPhysReg RegList2[] = {
4744 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
4745 };
4746 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4747 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4748 return false;
4749 }
4750 }
4751
4752 if (LocVT == MVT::i32) {
4753 static const MCPhysReg RegList3[] = {
4754 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
4755 };
4756 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4757 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4758 return false;
4759 }
4760 }
4761
4762 if (LocVT == MVT::i64) {
4763 static const MCPhysReg RegList4[] = {
4764 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
4765 };
4766 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4767 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4768 return false;
4769 }
4770 }
4771
4772 if (LocVT == MVT::v64i1) {
4773 LocVT = MVT::i64;
4774 if (ArgFlags.isSExt())
4775 LocInfo = CCValAssign::SExt;
4776 else if (ArgFlags.isZExt())
4777 LocInfo = CCValAssign::ZExt;
4778 else
4779 LocInfo = CCValAssign::AExt;
4780 }
4781
4782 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
4783 if (LocVT == MVT::i64) {
4784 static const MCPhysReg RegList5[] = {
4785 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
4786 };
4787 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4788 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4789 return false;
4790 }
4791 }
4792 }
4793
4794 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
4795 if (LocVT == MVT::i64) {
4796 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4797 return false;
4798 }
4799 }
4800
4801 if (LocVT == MVT::f80) {
4802 static const MCPhysReg RegList6[] = {
4803 X86::FP0, X86::FP1
4804 };
4805 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4806 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4807 return false;
4808 }
4809 }
4810
4811 if (LocVT == MVT::f32 ||
4812 LocVT == MVT::f64 ||
4813 LocVT == MVT::f128) {
4814 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4815 static const MCPhysReg RegList7[] = {
4816 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4817 };
4818 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4819 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4820 return false;
4821 }
4822 }
4823 }
4824
4825 if (LocVT == MVT::v16i8 ||
4826 LocVT == MVT::v8i16 ||
4827 LocVT == MVT::v4i32 ||
4828 LocVT == MVT::v2i64 ||
4829 LocVT == MVT::v4f32 ||
4830 LocVT == MVT::v2f64) {
4831 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4832 static const MCPhysReg RegList8[] = {
4833 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4834 };
4835 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
4836 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4837 return false;
4838 }
4839 }
4840 }
4841
4842 if (LocVT == MVT::v32i8 ||
4843 LocVT == MVT::v16i16 ||
4844 LocVT == MVT::v8i32 ||
4845 LocVT == MVT::v4i64 ||
4846 LocVT == MVT::v8f32 ||
4847 LocVT == MVT::v4f64) {
4848 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
4849 static const MCPhysReg RegList9[] = {
4850 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4851 };
4852 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
4853 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4854 return false;
4855 }
4856 }
4857 }
4858
4859 if (LocVT == MVT::v64i8 ||
4860 LocVT == MVT::v32i16 ||
4861 LocVT == MVT::v16i32 ||
4862 LocVT == MVT::v8i64 ||
4863 LocVT == MVT::v16f32 ||
4864 LocVT == MVT::v8f64) {
4865 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
4866 static const MCPhysReg RegList10[] = {
4867 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4868 };
4869 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
4870 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4871 return false;
4872 }
4873 }
4874 }
4875
4876 return true; // CC didn't match.
4877}
4878
4879#endif // GET_CALLING_CONV_IMPL
4880
4881#ifdef GET_CC_REGISTER_LISTS
4882#undef GET_CC_REGISTER_LISTS
4883
4884const MCRegister CC_Intel_OCL_BI_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::K1, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4885const MCRegister CC_X86_ArgRegs[] = { 0 };
4886const MCRegister CC_X86_32_ArgRegs[] = { 0 };
4887const MCRegister CC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX };
4888const MCRegister CC_X86_32_Common_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2 };
4889const MCRegister CC_X86_32_FastCC_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 };
4890const MCRegister CC_X86_32_FastCall_ArgRegs[] = { X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX };
4891const MCRegister CC_X86_32_GHC_ArgRegs[] = { X86::EBP, X86::EBX, X86::EDI, X86::ESI };
4892const MCRegister CC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::ECX, X86::EDX, X86::ESI };
4893const MCRegister CC_X86_32_MCU_ArgRegs[] = { 0 };
4894const MCRegister CC_X86_32_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::RAX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4895const MCRegister CC_X86_32_RegCallv4_Win_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::RAX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4896const MCRegister CC_X86_32_ThisCall_ArgRegs[] = { 0 };
4897const MCRegister CC_X86_32_ThisCall_Common_ArgRegs[] = { X86::ECX };
4898const MCRegister CC_X86_32_ThisCall_Mingw_ArgRegs[] = { 0 };
4899const MCRegister CC_X86_32_ThisCall_Win_ArgRegs[] = { 0 };
4900const MCRegister CC_X86_32_Vector_Common_ArgRegs[] = { 0 };
4901const MCRegister CC_X86_32_Vector_Darwin_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4902const MCRegister CC_X86_32_Vector_Standard_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::YMM0, X86::YMM1, X86::YMM2, X86::ZMM0, X86::ZMM1, X86::ZMM2 };
4903const MCRegister CC_X86_64_ArgRegs[] = { 0 };
4904const MCRegister CC_X86_64_AnyReg_ArgRegs[] = { 0 };
4905const MCRegister CC_X86_64_C_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::R10, X86::R10D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4906const MCRegister CC_X86_64_GHC_ArgRegs[] = { X86::R12, X86::R13, X86::R14, X86::R15, X86::R8, X86::R9, X86::RBP, X86::RBX, X86::RDI, X86::RSI, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6 };
4907const MCRegister CC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::R8, X86::RBP, X86::RCX, X86::RDX, X86::RSI };
4908const MCRegister CC_X86_64_Preserve_None_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R13, X86::R13D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI };
4909const MCRegister CC_X86_SysV64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R12, X86::R12D, X86::R13, X86::R13D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4910const MCRegister CC_X86_Win32_CFGuard_Check_ArgRegs[] = { X86::ECX };
4911const MCRegister CC_X86_Win32_Vector_ArgRegs[] = { 0 };
4912const MCRegister CC_X86_Win32_VectorCall_ArgRegs[] = { 0 };
4913const MCRegister CC_X86_Win64_C_ArgRegs[] = { X86::R10, X86::RAX };
4914const MCRegister CC_X86_Win64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R10, X86::R10D, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4915const MCRegister CC_X86_Win64_RegCallv4_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4916const MCRegister CC_X86_Win64_VectorCall_ArgRegs[] = { 0 };
4917const MCRegister RetCC_Intel_OCL_BI_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4918const MCRegister RetCC_X86_ArgRegs[] = { 0 };
4919const MCRegister RetCC_X86Common_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4920const MCRegister RetCC_X86_32_ArgRegs[] = { 0 };
4921const MCRegister RetCC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::XMM0, X86::XMM1, X86::XMM2 };
4922const MCRegister RetCC_X86_32_Fast_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 };
4923const MCRegister RetCC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::EDX, X86::ESI };
4924const MCRegister RetCC_X86_32_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::RAX, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4925const MCRegister RetCC_X86_32_RegCallv4_Win_ArgRegs[] = { X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::RAX, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4926const MCRegister RetCC_X86_32_VectorCall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4927const MCRegister RetCC_X86_64_ArgRegs[] = { 0 };
4928const MCRegister RetCC_X86_64_AnyReg_ArgRegs[] = { 0 };
4929const MCRegister RetCC_X86_64_C_ArgRegs[] = { X86::XMM0, X86::XMM1 };
4930const MCRegister RetCC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::RAX, X86::RBP, X86::RDX };
4931const MCRegister RetCC_X86_64_Swift_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4932const MCRegister RetCC_X86_64_Vectorcall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4933const MCRegister RetCC_X86_SysV64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R13, X86::R13B, X86::R13D, X86::R13W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4934const MCRegister RetCC_X86_Win64_C_ArgRegs[] = { 0 };
4935const MCRegister RetCC_X86_Win64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R10, X86::R10B, X86::R10D, X86::R10W, X86::R11, X86::R11B, X86::R11D, X86::R11W, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4936const MCRegister RetCC_X86_Win64_RegCallv4_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R11, X86::R11B, X86::R11D, X86::R11W, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4937
4938// Registers used by Swift.
4939const MCRegister CC_X86_64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 };
4940const MCRegister CC_X86_Win64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 };
4941const MCRegister RetCC_X86_64_C_Swift_ArgRegs[] = { X86::R12 };
4942const MCRegister RetCC_X86_64_Swift_Swift_ArgRegs[] = { X86::R12 };
4943
4944#endif // GET_CC_REGISTER_LISTS
4945
4946