1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#if !defined(GET_CC_REGISTER_LISTS)
10
11static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
14bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
17static bool CC_X86_32(unsigned ValNo, MVT ValVT,
18 MVT LocVT, CCValAssign::LocInfo LocInfo,
19 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
20static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
23static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
24 MVT LocVT, CCValAssign::LocInfo LocInfo,
25 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
26static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
27 MVT LocVT, CCValAssign::LocInfo LocInfo,
28 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
29static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
30 MVT LocVT, CCValAssign::LocInfo LocInfo,
31 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
32static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
33 MVT LocVT, CCValAssign::LocInfo LocInfo,
34 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
35static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
36 MVT LocVT, CCValAssign::LocInfo LocInfo,
37 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
38static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
39 MVT LocVT, CCValAssign::LocInfo LocInfo,
40 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
41static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
42 MVT LocVT, CCValAssign::LocInfo LocInfo,
43 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
44static bool CC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
45 MVT LocVT, CCValAssign::LocInfo LocInfo,
46 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
47static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
48 MVT LocVT, CCValAssign::LocInfo LocInfo,
49 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
50static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
51 MVT LocVT, CCValAssign::LocInfo LocInfo,
52 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
53static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
54 MVT LocVT, CCValAssign::LocInfo LocInfo,
55 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
56static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
57 MVT LocVT, CCValAssign::LocInfo LocInfo,
58 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
59static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
60 MVT LocVT, CCValAssign::LocInfo LocInfo,
61 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
62static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
63 MVT LocVT, CCValAssign::LocInfo LocInfo,
64 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
65static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
66 MVT LocVT, CCValAssign::LocInfo LocInfo,
67 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
68static bool CC_X86_64(unsigned ValNo, MVT ValVT,
69 MVT LocVT, CCValAssign::LocInfo LocInfo,
70 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
71static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
72 MVT LocVT, CCValAssign::LocInfo LocInfo,
73 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
74static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
75 MVT LocVT, CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
77static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
78 MVT LocVT, CCValAssign::LocInfo LocInfo,
79 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
80static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
81 MVT LocVT, CCValAssign::LocInfo LocInfo,
82 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
83static bool CC_X86_64_Preserve_None(unsigned ValNo, MVT ValVT,
84 MVT LocVT, CCValAssign::LocInfo LocInfo,
85 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
86static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
87 MVT LocVT, CCValAssign::LocInfo LocInfo,
88 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
89static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
90 MVT LocVT, CCValAssign::LocInfo LocInfo,
91 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
92static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT,
93 MVT LocVT, CCValAssign::LocInfo LocInfo,
94 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
95static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
96 MVT LocVT, CCValAssign::LocInfo LocInfo,
97 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
98static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
99 MVT LocVT, CCValAssign::LocInfo LocInfo,
100 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
101static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
102 MVT LocVT, CCValAssign::LocInfo LocInfo,
103 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
104static bool CC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
105 MVT LocVT, CCValAssign::LocInfo LocInfo,
106 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
107static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
108 MVT LocVT, CCValAssign::LocInfo LocInfo,
109 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
110static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
111 MVT LocVT, CCValAssign::LocInfo LocInfo,
112 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
113bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
114 MVT LocVT, CCValAssign::LocInfo LocInfo,
115 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
116static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
117 MVT LocVT, CCValAssign::LocInfo LocInfo,
118 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
119static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
120 MVT LocVT, CCValAssign::LocInfo LocInfo,
121 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
122static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
123 MVT LocVT, CCValAssign::LocInfo LocInfo,
124 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
125static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
126 MVT LocVT, CCValAssign::LocInfo LocInfo,
127 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
128static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
129 MVT LocVT, CCValAssign::LocInfo LocInfo,
130 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
131static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
132 MVT LocVT, CCValAssign::LocInfo LocInfo,
133 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
134static bool RetCC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
135 MVT LocVT, CCValAssign::LocInfo LocInfo,
136 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
137static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
138 MVT LocVT, CCValAssign::LocInfo LocInfo,
139 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
140static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
141 MVT LocVT, CCValAssign::LocInfo LocInfo,
142 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
143static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
144 MVT LocVT, CCValAssign::LocInfo LocInfo,
145 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
146static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
147 MVT LocVT, CCValAssign::LocInfo LocInfo,
148 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
149static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
150 MVT LocVT, CCValAssign::LocInfo LocInfo,
151 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
152static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
153 MVT LocVT, CCValAssign::LocInfo LocInfo,
154 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
155static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
156 MVT LocVT, CCValAssign::LocInfo LocInfo,
157 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
158static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
159 MVT LocVT, CCValAssign::LocInfo LocInfo,
160 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
161static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
162 MVT LocVT, CCValAssign::LocInfo LocInfo,
163 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
164static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
165 MVT LocVT, CCValAssign::LocInfo LocInfo,
166 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
167static bool RetCC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
168 MVT LocVT, CCValAssign::LocInfo LocInfo,
169 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
170
171
172static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
173 MVT LocVT, CCValAssign::LocInfo LocInfo,
174 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
175
176 if (LocVT == MVT::i32) {
177 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
178 static const MCPhysReg RegList1[] = {
179 X86::ECX, X86::EDX, X86::R8D, X86::R9D
180 };
181 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
182 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
183 return false;
184 }
185 }
186 }
187
188 if (LocVT == MVT::i64) {
189 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
190 static const MCPhysReg RegList2[] = {
191 X86::RCX, X86::RDX, X86::R8, X86::R9
192 };
193 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
194 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
195 return false;
196 }
197 }
198 }
199
200 if (LocVT == MVT::i32) {
201 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
202 static const MCPhysReg RegList3[] = {
203 X86::EDI, X86::ESI, X86::EDX, X86::ECX
204 };
205 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
206 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
207 return false;
208 }
209 }
210 }
211
212 if (LocVT == MVT::i64) {
213 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
214 static const MCPhysReg RegList4[] = {
215 X86::RDI, X86::RSI, X86::RDX, X86::RCX
216 };
217 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
218 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
219 return false;
220 }
221 }
222 }
223
224 if (LocVT == MVT::i32) {
225 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(4));
226 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
227 return false;
228 }
229
230 if (LocVT == MVT::f32 ||
231 LocVT == MVT::f64 ||
232 LocVT == MVT::v4i32 ||
233 LocVT == MVT::v2i64 ||
234 LocVT == MVT::v4f32 ||
235 LocVT == MVT::v2f64) {
236 static const MCPhysReg RegList6[] = {
237 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
238 };
239 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
240 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
241 return false;
242 }
243 }
244
245 if (LocVT == MVT::v8f32 ||
246 LocVT == MVT::v4f64 ||
247 LocVT == MVT::v8i32 ||
248 LocVT == MVT::v4i64) {
249 static const MCPhysReg RegList7[] = {
250 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
251 };
252 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
253 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
254 return false;
255 }
256 }
257
258 if (LocVT == MVT::v16f32 ||
259 LocVT == MVT::v8f64 ||
260 LocVT == MVT::v16i32 ||
261 LocVT == MVT::v8i64) {
262 static const MCPhysReg RegList8[] = {
263 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
264 };
265 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
266 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
267 return false;
268 }
269 }
270
271 if (LocVT == MVT::v16i1 ||
272 LocVT == MVT::v8i1) {
273 if (MCRegister Reg = State.AllocateReg(Reg: X86::K1)) {
274 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
275 return false;
276 }
277 }
278
279 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
280 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
281 return false;
282 }
283
284 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
285 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
286 return false;
287 }
288
289 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
290 return false;
291
292 return true; // CC didn't match.
293}
294
295
296bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
297 MVT LocVT, CCValAssign::LocInfo LocInfo,
298 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
299
300 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
301 if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
302 return false;
303 }
304
305 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
306 if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
307 return false;
308 }
309
310 if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
311 return false;
312
313 return true; // CC didn't match.
314}
315
316
317static bool CC_X86_32(unsigned ValNo, MVT ValVT,
318 MVT LocVT, CCValAssign::LocInfo LocInfo,
319 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
320
321 if (State.getCallingConv() == CallingConv::X86_INTR) {
322 if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
323 return false;
324 }
325
326 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetMCU()) {
327 if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
328 return false;
329 }
330
331 if (State.getCallingConv() == CallingConv::X86_FastCall) {
332 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
333 return false;
334 }
335
336 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
337 if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
338 return false;
339 }
340
341 if (State.getCallingConv() == CallingConv::X86_ThisCall) {
342 if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
343 return false;
344 }
345
346 if (State.getCallingConv() == CallingConv::CFGuard_Check) {
347 if (!CC_X86_Win32_CFGuard_Check(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
348 return false;
349 }
350
351 if (State.getCallingConv() == CallingConv::Fast) {
352 if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
353 return false;
354 }
355
356 if (State.getCallingConv() == CallingConv::Tail) {
357 if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
358 return false;
359 }
360
361 if (State.getCallingConv() == CallingConv::GHC) {
362 if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
363 return false;
364 }
365
366 if (State.getCallingConv() == CallingConv::HiPE) {
367 if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
368 return false;
369 }
370
371 if (State.getCallingConv() == CallingConv::X86_RegCall) {
372 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin32()) {
373 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
374 if (!CC_X86_32_RegCallv4_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
375 return false;
376 }
377 }
378 }
379
380 if (State.getCallingConv() == CallingConv::X86_RegCall) {
381 if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
382 return false;
383 }
384
385 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
386 return false;
387
388 return true; // CC didn't match.
389}
390
391
392static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
393 MVT LocVT, CCValAssign::LocInfo LocInfo,
394 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
395
396 if (LocVT == MVT::i1 ||
397 LocVT == MVT::i8 ||
398 LocVT == MVT::i16 ||
399 LocVT == MVT::v1i1) {
400 LocVT = MVT::i32;
401 if (ArgFlags.isSExt())
402 LocInfo = CCValAssign::SExt;
403 else if (ArgFlags.isZExt())
404 LocInfo = CCValAssign::ZExt;
405 else
406 LocInfo = CCValAssign::AExt;
407 }
408
409 if (ArgFlags.isNest()) {
410 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
411 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
412 return false;
413 }
414 }
415
416 if (LocVT == MVT::i32) {
417 if (ArgFlags.isInConsecutiveRegs()) {
418 if (CC_X86_32_I128_FP128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
419 return false;
420 }
421 }
422
423 if (State.getCallingConv() == CallingConv::SwiftTail) {
424 if (ArgFlags.isSwiftSelf()) {
425 if (LocVT == MVT::i32) {
426 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
427 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
428 return false;
429 }
430 }
431 }
432 }
433
434 if (!State.isVarArg()) {
435 if (ArgFlags.isInReg()) {
436 if (LocVT == MVT::i32) {
437 static const MCPhysReg RegList1[] = {
438 X86::EAX, X86::EDX, X86::ECX
439 };
440 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
441 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
442 return false;
443 }
444 }
445 }
446 }
447
448 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
449 return false;
450
451 return true; // CC didn't match.
452}
453
454
455static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
456 MVT LocVT, CCValAssign::LocInfo LocInfo,
457 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
458
459 if (ArgFlags.isByVal()) {
460 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
461 return false;
462 }
463
464 if (ArgFlags.isPreallocated()) {
465 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
466 return false;
467 }
468
469 if (!State.isVarArg()) {
470 if (ArgFlags.isInReg()) {
471 if (LocVT == MVT::f32 ||
472 LocVT == MVT::f64) {
473 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
474 static const MCPhysReg RegList1[] = {
475 X86::XMM0, X86::XMM1, X86::XMM2
476 };
477 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
478 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
479 return false;
480 }
481 }
482 }
483 }
484 }
485
486 if (!State.isVarArg()) {
487 if (ArgFlags.isInReg()) {
488 if (LocVT == MVT::f16) {
489 static const MCPhysReg RegList2[] = {
490 X86::XMM0, X86::XMM1, X86::XMM2
491 };
492 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
493 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
494 return false;
495 }
496 }
497 }
498 }
499
500 if (LocVT == MVT::f16) {
501 int64_t Offset3 = State.AllocateStack(Size: 4, Alignment: Align(4));
502 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
503 return false;
504 }
505
506 if (LocVT == MVT::i32 ||
507 LocVT == MVT::f32) {
508 int64_t Offset4 = State.AllocateStack(Size: 4, Alignment: Align(4));
509 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
510 return false;
511 }
512
513 if (LocVT == MVT::f64) {
514 int64_t Offset5 = State.AllocateStack(Size: 8, Alignment: Align(4));
515 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
516 return false;
517 }
518
519 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetDarwin()) {
520 if (LocVT == MVT::f80) {
521 int64_t Offset6 = State.AllocateStack(
522 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())), Alignment: Align(4));
523 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
524 return false;
525 }
526 }
527
528 if (LocVT == MVT::f80) {
529 int64_t Offset7 = State.AllocateStack(
530 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
531 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
532 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
533 return false;
534 }
535
536 if (LocVT == MVT::v2i1) {
537 LocVT = MVT::v2i64;
538 if (ArgFlags.isSExt())
539 LocInfo = CCValAssign::SExt;
540 else if (ArgFlags.isZExt())
541 LocInfo = CCValAssign::ZExt;
542 else
543 LocInfo = CCValAssign::AExt;
544 }
545
546 if (LocVT == MVT::v4i1) {
547 LocVT = MVT::v4i32;
548 if (ArgFlags.isSExt())
549 LocInfo = CCValAssign::SExt;
550 else if (ArgFlags.isZExt())
551 LocInfo = CCValAssign::ZExt;
552 else
553 LocInfo = CCValAssign::AExt;
554 }
555
556 if (LocVT == MVT::v8i1) {
557 LocVT = MVT::v8i16;
558 if (ArgFlags.isSExt())
559 LocInfo = CCValAssign::SExt;
560 else if (ArgFlags.isZExt())
561 LocInfo = CCValAssign::ZExt;
562 else
563 LocInfo = CCValAssign::AExt;
564 }
565
566 if (LocVT == MVT::v16i1) {
567 LocVT = MVT::v16i8;
568 if (ArgFlags.isSExt())
569 LocInfo = CCValAssign::SExt;
570 else if (ArgFlags.isZExt())
571 LocInfo = CCValAssign::ZExt;
572 else
573 LocInfo = CCValAssign::AExt;
574 }
575
576 if (LocVT == MVT::v32i1) {
577 LocVT = MVT::v32i8;
578 if (ArgFlags.isSExt())
579 LocInfo = CCValAssign::SExt;
580 else if (ArgFlags.isZExt())
581 LocInfo = CCValAssign::ZExt;
582 else
583 LocInfo = CCValAssign::AExt;
584 }
585
586 if (LocVT == MVT::v64i1) {
587 LocVT = MVT::v64i8;
588 if (ArgFlags.isSExt())
589 LocInfo = CCValAssign::SExt;
590 else if (ArgFlags.isZExt())
591 LocInfo = CCValAssign::ZExt;
592 else
593 LocInfo = CCValAssign::AExt;
594 }
595
596 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetDarwin()) {
597 if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
598 return false;
599 }
600
601 if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
602 return false;
603
604 return true; // CC didn't match.
605}
606
607
608static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
609 MVT LocVT, CCValAssign::LocInfo LocInfo,
610 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
611
612 if (ArgFlags.isByVal()) {
613 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
614 return false;
615 }
616
617 if (LocVT == MVT::i1 ||
618 LocVT == MVT::i8 ||
619 LocVT == MVT::i16 ||
620 LocVT == MVT::v1i1) {
621 LocVT = MVT::i32;
622 if (ArgFlags.isSExt())
623 LocInfo = CCValAssign::SExt;
624 else if (ArgFlags.isZExt())
625 LocInfo = CCValAssign::ZExt;
626 else
627 LocInfo = CCValAssign::AExt;
628 }
629
630 if (ArgFlags.isNest()) {
631 if (MCRegister Reg = State.AllocateReg(Reg: X86::EAX)) {
632 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
633 return false;
634 }
635 }
636
637 if (LocVT == MVT::i32) {
638 static const MCPhysReg RegList1[] = {
639 X86::ECX, X86::EDX
640 };
641 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
642 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
643 return false;
644 }
645 }
646
647 if (!State.isVarArg()) {
648 if (LocVT == MVT::f32 ||
649 LocVT == MVT::f64) {
650 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
651 static const MCPhysReg RegList2[] = {
652 X86::XMM0, X86::XMM1, X86::XMM2
653 };
654 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
655 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
656 return false;
657 }
658 }
659 }
660 }
661
662 if (LocVT == MVT::f64) {
663 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(8));
664 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
665 return false;
666 }
667
668 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
669 return false;
670
671 return true; // CC didn't match.
672}
673
674
675static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
676 MVT LocVT, CCValAssign::LocInfo LocInfo,
677 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
678
679 if (LocVT == MVT::i1) {
680 LocVT = MVT::i8;
681 if (ArgFlags.isSExt())
682 LocInfo = CCValAssign::SExt;
683 else if (ArgFlags.isZExt())
684 LocInfo = CCValAssign::ZExt;
685 else
686 LocInfo = CCValAssign::AExt;
687 }
688
689 if (ArgFlags.isNest()) {
690 if (MCRegister Reg = State.AllocateReg(Reg: X86::EAX)) {
691 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
692 return false;
693 }
694 }
695
696 if (ArgFlags.isInReg()) {
697 if (LocVT == MVT::i8) {
698 static const MCPhysReg RegList1[] = {
699 X86::CL, X86::DL
700 };
701 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
702 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
703 return false;
704 }
705 }
706 }
707
708 if (ArgFlags.isInReg()) {
709 if (LocVT == MVT::i16) {
710 static const MCPhysReg RegList2[] = {
711 X86::CX, X86::DX
712 };
713 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
714 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
715 return false;
716 }
717 }
718 }
719
720 if (ArgFlags.isInReg()) {
721 if (LocVT == MVT::i32) {
722 static const MCPhysReg RegList3[] = {
723 X86::ECX, X86::EDX
724 };
725 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
726 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
727 return false;
728 }
729 }
730 }
731
732 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
733 return false;
734
735 return true; // CC didn't match.
736}
737
738
739static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
740 MVT LocVT, CCValAssign::LocInfo LocInfo,
741 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
742
743 if (LocVT == MVT::i8 ||
744 LocVT == MVT::i16) {
745 LocVT = MVT::i32;
746 if (ArgFlags.isSExt())
747 LocInfo = CCValAssign::SExt;
748 else if (ArgFlags.isZExt())
749 LocInfo = CCValAssign::ZExt;
750 else
751 LocInfo = CCValAssign::AExt;
752 }
753
754 if (LocVT == MVT::i32) {
755 static const MCPhysReg RegList1[] = {
756 X86::EBX, X86::EBP, X86::EDI, X86::ESI
757 };
758 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
759 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
760 return false;
761 }
762 }
763
764 return true; // CC didn't match.
765}
766
767
768static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
769 MVT LocVT, CCValAssign::LocInfo LocInfo,
770 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
771
772 if (LocVT == MVT::i8 ||
773 LocVT == MVT::i16) {
774 LocVT = MVT::i32;
775 if (ArgFlags.isSExt())
776 LocInfo = CCValAssign::SExt;
777 else if (ArgFlags.isZExt())
778 LocInfo = CCValAssign::ZExt;
779 else
780 LocInfo = CCValAssign::AExt;
781 }
782
783 if (LocVT == MVT::i32) {
784 static const MCPhysReg RegList1[] = {
785 X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
786 };
787 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
788 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
789 return false;
790 }
791 }
792
793 if (LocVT == MVT::i32 ||
794 LocVT == MVT::f32) {
795 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
796 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
797 return false;
798 }
799
800 return true; // CC didn't match.
801}
802
803
804static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
805 MVT LocVT, CCValAssign::LocInfo LocInfo,
806 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
807
808 if (ArgFlags.isByVal()) {
809 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
810 return false;
811 }
812
813 if (LocVT == MVT::i1 ||
814 LocVT == MVT::i8 ||
815 LocVT == MVT::i16 ||
816 LocVT == MVT::v1i1) {
817 LocVT = MVT::i32;
818 if (ArgFlags.isSExt())
819 LocInfo = CCValAssign::SExt;
820 else if (ArgFlags.isZExt())
821 LocInfo = CCValAssign::ZExt;
822 else
823 LocInfo = CCValAssign::AExt;
824 }
825
826 if (!State.isVarArg()) {
827 if (LocVT == MVT::i32) {
828 if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
829 return false;
830 }
831 }
832
833 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
834 return false;
835
836 return true; // CC didn't match.
837}
838
839
840static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
841 MVT LocVT, CCValAssign::LocInfo LocInfo,
842 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
843
844 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
845 if (ArgFlags.isByVal()) {
846 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
847 return false;
848 }
849 }
850
851 if (ArgFlags.isByVal()) {
852 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
853 return false;
854 }
855
856 if (LocVT == MVT::i1 ||
857 LocVT == MVT::i8 ||
858 LocVT == MVT::i16 ||
859 LocVT == MVT::v1i1) {
860 LocVT = MVT::i32;
861 if (ArgFlags.isSExt())
862 LocInfo = CCValAssign::SExt;
863 else if (ArgFlags.isZExt())
864 LocInfo = CCValAssign::ZExt;
865 else
866 LocInfo = CCValAssign::AExt;
867 }
868
869 if (LocVT == MVT::v8i1 ||
870 LocVT == MVT::v16i1 ||
871 LocVT == MVT::v32i1) {
872 LocVT = MVT::i32;
873 if (ArgFlags.isSExt())
874 LocInfo = CCValAssign::SExt;
875 else if (ArgFlags.isZExt())
876 LocInfo = CCValAssign::ZExt;
877 else
878 LocInfo = CCValAssign::AExt;
879 }
880
881 if (LocVT == MVT::i32) {
882 static const MCPhysReg RegList1[] = {
883 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
884 };
885 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
886 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
887 return false;
888 }
889 }
890
891 if (LocVT == MVT::i64) {
892 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
893 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
894 return false;
895 }
896 }
897
898 if (LocVT == MVT::v64i1) {
899 LocVT = MVT::i64;
900 if (ArgFlags.isSExt())
901 LocInfo = CCValAssign::SExt;
902 else if (ArgFlags.isZExt())
903 LocInfo = CCValAssign::ZExt;
904 else
905 LocInfo = CCValAssign::AExt;
906 }
907
908 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
909 if (LocVT == MVT::i64) {
910 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
911 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
912 return false;
913 }
914 }
915 }
916
917 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
918 if (LocVT == MVT::i64) {
919 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
920 return false;
921 }
922 }
923
924 if (LocVT == MVT::f32 ||
925 LocVT == MVT::f64 ||
926 LocVT == MVT::f128) {
927 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
928 static const MCPhysReg RegList2[] = {
929 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
930 };
931 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
932 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
933 return false;
934 }
935 }
936 }
937
938 if (LocVT == MVT::f80) {
939 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
940 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
941 return false;
942 }
943 }
944
945 if (LocVT == MVT::v16i8 ||
946 LocVT == MVT::v8i16 ||
947 LocVT == MVT::v4i32 ||
948 LocVT == MVT::v2i64 ||
949 LocVT == MVT::v4f32 ||
950 LocVT == MVT::v2f64) {
951 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
952 static const MCPhysReg RegList3[] = {
953 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
954 };
955 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
956 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
957 return false;
958 }
959 }
960 }
961
962 if (LocVT == MVT::v32i8 ||
963 LocVT == MVT::v16i16 ||
964 LocVT == MVT::v8i32 ||
965 LocVT == MVT::v4i64 ||
966 LocVT == MVT::v8f32 ||
967 LocVT == MVT::v4f64) {
968 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
969 static const MCPhysReg RegList4[] = {
970 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
971 };
972 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
973 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
974 return false;
975 }
976 }
977 }
978
979 if (LocVT == MVT::v64i8 ||
980 LocVT == MVT::v32i16 ||
981 LocVT == MVT::v16i32 ||
982 LocVT == MVT::v8i64 ||
983 LocVT == MVT::v16f32 ||
984 LocVT == MVT::v8f64) {
985 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
986 static const MCPhysReg RegList5[] = {
987 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
988 };
989 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
990 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
991 return false;
992 }
993 }
994 }
995
996 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
997 if (LocVT == MVT::i32 ||
998 LocVT == MVT::i64 ||
999 LocVT == MVT::f32 ||
1000 LocVT == MVT::f64) {
1001 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
1002 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1003 return false;
1004 }
1005 }
1006
1007 if (LocVT == MVT::i32 ||
1008 LocVT == MVT::f32) {
1009 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(4));
1010 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
1011 return false;
1012 }
1013
1014 if (LocVT == MVT::i64 ||
1015 LocVT == MVT::f64) {
1016 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(4));
1017 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1018 return false;
1019 }
1020
1021 if (LocVT == MVT::f80 ||
1022 LocVT == MVT::f128) {
1023 int64_t Offset9 = State.AllocateStack(
1024 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1025 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1026 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1027 return false;
1028 }
1029
1030 if (LocVT == MVT::v16i8 ||
1031 LocVT == MVT::v8i16 ||
1032 LocVT == MVT::v4i32 ||
1033 LocVT == MVT::v2i64 ||
1034 LocVT == MVT::v4f32 ||
1035 LocVT == MVT::v2f64) {
1036 int64_t Offset10 = State.AllocateStack(Size: 16, Alignment: Align(16));
1037 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1038 return false;
1039 }
1040
1041 if (LocVT == MVT::v32i8 ||
1042 LocVT == MVT::v16i16 ||
1043 LocVT == MVT::v8i32 ||
1044 LocVT == MVT::v4i64 ||
1045 LocVT == MVT::v8f32 ||
1046 LocVT == MVT::v4f64) {
1047 int64_t Offset11 = State.AllocateStack(Size: 32, Alignment: Align(32));
1048 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
1049 return false;
1050 }
1051
1052 if (LocVT == MVT::v64i8 ||
1053 LocVT == MVT::v32i16 ||
1054 LocVT == MVT::v16i32 ||
1055 LocVT == MVT::v8i64 ||
1056 LocVT == MVT::v16f32 ||
1057 LocVT == MVT::v8f64) {
1058 int64_t Offset12 = State.AllocateStack(Size: 64, Alignment: Align(64));
1059 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
1060 return false;
1061 }
1062
1063 return true; // CC didn't match.
1064}
1065
1066
1067static bool CC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
1068 MVT LocVT, CCValAssign::LocInfo LocInfo,
1069 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1070
1071 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
1072 if (ArgFlags.isByVal()) {
1073 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1074 return false;
1075 }
1076 }
1077
1078 if (ArgFlags.isByVal()) {
1079 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
1080 return false;
1081 }
1082
1083 if (LocVT == MVT::i1 ||
1084 LocVT == MVT::i8 ||
1085 LocVT == MVT::i16 ||
1086 LocVT == MVT::v1i1) {
1087 LocVT = MVT::i32;
1088 if (ArgFlags.isSExt())
1089 LocInfo = CCValAssign::SExt;
1090 else if (ArgFlags.isZExt())
1091 LocInfo = CCValAssign::ZExt;
1092 else
1093 LocInfo = CCValAssign::AExt;
1094 }
1095
1096 if (LocVT == MVT::v8i1 ||
1097 LocVT == MVT::v16i1 ||
1098 LocVT == MVT::v32i1) {
1099 LocVT = MVT::i32;
1100 if (ArgFlags.isSExt())
1101 LocInfo = CCValAssign::SExt;
1102 else if (ArgFlags.isZExt())
1103 LocInfo = CCValAssign::ZExt;
1104 else
1105 LocInfo = CCValAssign::AExt;
1106 }
1107
1108 if (LocVT == MVT::i32) {
1109 static const MCPhysReg RegList1[] = {
1110 X86::ECX, X86::EDX, X86::EDI, X86::ESI
1111 };
1112 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1113 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1114 return false;
1115 }
1116 }
1117
1118 if (LocVT == MVT::i64) {
1119 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1120 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1121 return false;
1122 }
1123 }
1124
1125 if (LocVT == MVT::v64i1) {
1126 LocVT = MVT::i64;
1127 if (ArgFlags.isSExt())
1128 LocInfo = CCValAssign::SExt;
1129 else if (ArgFlags.isZExt())
1130 LocInfo = CCValAssign::ZExt;
1131 else
1132 LocInfo = CCValAssign::AExt;
1133 }
1134
1135 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
1136 if (LocVT == MVT::i64) {
1137 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1138 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1139 return false;
1140 }
1141 }
1142 }
1143
1144 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
1145 if (LocVT == MVT::i64) {
1146 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1147 return false;
1148 }
1149 }
1150
1151 if (LocVT == MVT::f32 ||
1152 LocVT == MVT::f64 ||
1153 LocVT == MVT::f128) {
1154 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
1155 static const MCPhysReg RegList2[] = {
1156 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1157 };
1158 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1159 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1160 return false;
1161 }
1162 }
1163 }
1164
1165 if (LocVT == MVT::f80) {
1166 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
1167 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1168 return false;
1169 }
1170 }
1171
1172 if (LocVT == MVT::v16i8 ||
1173 LocVT == MVT::v8i16 ||
1174 LocVT == MVT::v4i32 ||
1175 LocVT == MVT::v2i64 ||
1176 LocVT == MVT::v4f32 ||
1177 LocVT == MVT::v2f64) {
1178 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
1179 static const MCPhysReg RegList3[] = {
1180 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1181 };
1182 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1183 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1184 return false;
1185 }
1186 }
1187 }
1188
1189 if (LocVT == MVT::v32i8 ||
1190 LocVT == MVT::v16i16 ||
1191 LocVT == MVT::v8i32 ||
1192 LocVT == MVT::v4i64 ||
1193 LocVT == MVT::v8f32 ||
1194 LocVT == MVT::v4f64) {
1195 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1196 static const MCPhysReg RegList4[] = {
1197 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1198 };
1199 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1200 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1201 return false;
1202 }
1203 }
1204 }
1205
1206 if (LocVT == MVT::v64i8 ||
1207 LocVT == MVT::v32i16 ||
1208 LocVT == MVT::v16i32 ||
1209 LocVT == MVT::v8i64 ||
1210 LocVT == MVT::v16f32 ||
1211 LocVT == MVT::v8f64) {
1212 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
1213 static const MCPhysReg RegList5[] = {
1214 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1215 };
1216 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
1217 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1218 return false;
1219 }
1220 }
1221 }
1222
1223 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
1224 if (LocVT == MVT::i32 ||
1225 LocVT == MVT::i64 ||
1226 LocVT == MVT::f32 ||
1227 LocVT == MVT::f64) {
1228 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
1229 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1230 return false;
1231 }
1232 }
1233
1234 if (LocVT == MVT::i32 ||
1235 LocVT == MVT::f32) {
1236 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(4));
1237 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
1238 return false;
1239 }
1240
1241 if (LocVT == MVT::i64 ||
1242 LocVT == MVT::f64) {
1243 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(4));
1244 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1245 return false;
1246 }
1247
1248 if (LocVT == MVT::f80 ||
1249 LocVT == MVT::f128) {
1250 int64_t Offset9 = State.AllocateStack(
1251 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1252 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1253 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1254 return false;
1255 }
1256
1257 if (LocVT == MVT::v16i8 ||
1258 LocVT == MVT::v8i16 ||
1259 LocVT == MVT::v4i32 ||
1260 LocVT == MVT::v2i64 ||
1261 LocVT == MVT::v4f32 ||
1262 LocVT == MVT::v2f64) {
1263 int64_t Offset10 = State.AllocateStack(Size: 16, Alignment: Align(16));
1264 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1265 return false;
1266 }
1267
1268 if (LocVT == MVT::v32i8 ||
1269 LocVT == MVT::v16i16 ||
1270 LocVT == MVT::v8i32 ||
1271 LocVT == MVT::v4i64 ||
1272 LocVT == MVT::v8f32 ||
1273 LocVT == MVT::v4f64) {
1274 int64_t Offset11 = State.AllocateStack(Size: 32, Alignment: Align(32));
1275 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
1276 return false;
1277 }
1278
1279 if (LocVT == MVT::v64i8 ||
1280 LocVT == MVT::v32i16 ||
1281 LocVT == MVT::v16i32 ||
1282 LocVT == MVT::v8i64 ||
1283 LocVT == MVT::v16f32 ||
1284 LocVT == MVT::v8f64) {
1285 int64_t Offset12 = State.AllocateStack(Size: 64, Alignment: Align(64));
1286 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
1287 return false;
1288 }
1289
1290 return true; // CC didn't match.
1291}
1292
1293
1294static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
1295 MVT LocVT, CCValAssign::LocInfo LocInfo,
1296 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1297
1298 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetCygMing()) {
1299 if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1300 return false;
1301 }
1302
1303 if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1304 return false;
1305
1306 return true; // CC didn't match.
1307}
1308
1309
1310static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
1311 MVT LocVT, CCValAssign::LocInfo LocInfo,
1312 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1313
1314 if (LocVT == MVT::i32) {
1315 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
1316 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1317 return false;
1318 }
1319 }
1320
1321 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1322 return false;
1323
1324 return true; // CC didn't match.
1325}
1326
1327
1328static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
1329 MVT LocVT, CCValAssign::LocInfo LocInfo,
1330 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1331
1332 if (LocVT == MVT::i1 ||
1333 LocVT == MVT::i8 ||
1334 LocVT == MVT::i16 ||
1335 LocVT == MVT::v1i1) {
1336 LocVT = MVT::i32;
1337 if (ArgFlags.isSExt())
1338 LocInfo = CCValAssign::SExt;
1339 else if (ArgFlags.isZExt())
1340 LocInfo = CCValAssign::ZExt;
1341 else
1342 LocInfo = CCValAssign::AExt;
1343 }
1344
1345 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1346 return false;
1347
1348 return true; // CC didn't match.
1349}
1350
1351
1352static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
1353 MVT LocVT, CCValAssign::LocInfo LocInfo,
1354 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1355
1356 if (LocVT == MVT::i1 ||
1357 LocVT == MVT::i8 ||
1358 LocVT == MVT::i16 ||
1359 LocVT == MVT::v1i1) {
1360 LocVT = MVT::i32;
1361 if (ArgFlags.isSExt())
1362 LocInfo = CCValAssign::SExt;
1363 else if (ArgFlags.isZExt())
1364 LocInfo = CCValAssign::ZExt;
1365 else
1366 LocInfo = CCValAssign::AExt;
1367 }
1368
1369 if (ArgFlags.isSRet()) {
1370 int64_t Offset1 = State.AllocateStack(Size: 4, Alignment: Align(4));
1371 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1372 return false;
1373 }
1374
1375 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1376 return false;
1377
1378 return true; // CC didn't match.
1379}
1380
1381
1382static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
1383 MVT LocVT, CCValAssign::LocInfo LocInfo,
1384 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1385
1386 if (LocVT == MVT::v16i8 ||
1387 LocVT == MVT::v8i16 ||
1388 LocVT == MVT::v4i32 ||
1389 LocVT == MVT::v2i64 ||
1390 LocVT == MVT::v8f16 ||
1391 LocVT == MVT::v8bf16 ||
1392 LocVT == MVT::v4f32 ||
1393 LocVT == MVT::v2f64) {
1394 int64_t Offset1 = State.AllocateStack(Size: 16, Alignment: Align(16));
1395 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1396 return false;
1397 }
1398
1399 if (LocVT == MVT::v32i8 ||
1400 LocVT == MVT::v16i16 ||
1401 LocVT == MVT::v8i32 ||
1402 LocVT == MVT::v4i64 ||
1403 LocVT == MVT::v16f16 ||
1404 LocVT == MVT::v16bf16 ||
1405 LocVT == MVT::v8f32 ||
1406 LocVT == MVT::v4f64) {
1407 int64_t Offset2 = State.AllocateStack(Size: 32, Alignment: Align(32));
1408 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1409 return false;
1410 }
1411
1412 if (LocVT == MVT::v64i8 ||
1413 LocVT == MVT::v32i16 ||
1414 LocVT == MVT::v16i32 ||
1415 LocVT == MVT::v8i64 ||
1416 LocVT == MVT::v32f16 ||
1417 LocVT == MVT::v32bf16 ||
1418 LocVT == MVT::v16f32 ||
1419 LocVT == MVT::v8f64) {
1420 int64_t Offset3 = State.AllocateStack(Size: 64, Alignment: Align(64));
1421 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1422 return false;
1423 }
1424
1425 return true; // CC didn't match.
1426}
1427
1428
1429static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
1430 MVT LocVT, CCValAssign::LocInfo LocInfo,
1431 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1432
1433 if (!State.isVarArg()) {
1434 if (LocVT == MVT::v16i8 ||
1435 LocVT == MVT::v8i16 ||
1436 LocVT == MVT::v4i32 ||
1437 LocVT == MVT::v2i64 ||
1438 LocVT == MVT::v8f16 ||
1439 LocVT == MVT::v8bf16 ||
1440 LocVT == MVT::v4f32 ||
1441 LocVT == MVT::v2f64) {
1442 static const MCPhysReg RegList1[] = {
1443 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1444 };
1445 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1446 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1447 return false;
1448 }
1449 }
1450 }
1451
1452 if (!State.isVarArg()) {
1453 if (LocVT == MVT::v32i8 ||
1454 LocVT == MVT::v16i16 ||
1455 LocVT == MVT::v8i32 ||
1456 LocVT == MVT::v4i64 ||
1457 LocVT == MVT::v16f16 ||
1458 LocVT == MVT::v16bf16 ||
1459 LocVT == MVT::v8f32 ||
1460 LocVT == MVT::v4f64) {
1461 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1462 static const MCPhysReg RegList2[] = {
1463 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1464 };
1465 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1466 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1467 return false;
1468 }
1469 }
1470 }
1471 }
1472
1473 if (!State.isVarArg()) {
1474 if (LocVT == MVT::v64i8 ||
1475 LocVT == MVT::v32i16 ||
1476 LocVT == MVT::v16i32 ||
1477 LocVT == MVT::v8i64 ||
1478 LocVT == MVT::v32f16 ||
1479 LocVT == MVT::v32bf16 ||
1480 LocVT == MVT::v16f32 ||
1481 LocVT == MVT::v8f64) {
1482 static const MCPhysReg RegList3[] = {
1483 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1484 };
1485 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1486 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1487 return false;
1488 }
1489 }
1490 }
1491
1492 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1493 return false;
1494
1495 return true; // CC didn't match.
1496}
1497
1498
1499static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
1500 MVT LocVT, CCValAssign::LocInfo LocInfo,
1501 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1502
1503 if (!State.isVarArg()) {
1504 if (LocVT == MVT::v16i8 ||
1505 LocVT == MVT::v8i16 ||
1506 LocVT == MVT::v4i32 ||
1507 LocVT == MVT::v2i64 ||
1508 LocVT == MVT::v8f16 ||
1509 LocVT == MVT::v8bf16 ||
1510 LocVT == MVT::v4f32 ||
1511 LocVT == MVT::v2f64) {
1512 static const MCPhysReg RegList1[] = {
1513 X86::XMM0, X86::XMM1, X86::XMM2
1514 };
1515 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1516 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1517 return false;
1518 }
1519 }
1520 }
1521
1522 if (!State.isVarArg()) {
1523 if (LocVT == MVT::v32i8 ||
1524 LocVT == MVT::v16i16 ||
1525 LocVT == MVT::v8i32 ||
1526 LocVT == MVT::v4i64 ||
1527 LocVT == MVT::v16f16 ||
1528 LocVT == MVT::v16bf16 ||
1529 LocVT == MVT::v8f32 ||
1530 LocVT == MVT::v4f64) {
1531 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1532 static const MCPhysReg RegList2[] = {
1533 X86::YMM0, X86::YMM1, X86::YMM2
1534 };
1535 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1536 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1537 return false;
1538 }
1539 }
1540 }
1541 }
1542
1543 if (!State.isVarArg()) {
1544 if (LocVT == MVT::v64i8 ||
1545 LocVT == MVT::v32i16 ||
1546 LocVT == MVT::v16i32 ||
1547 LocVT == MVT::v8i64 ||
1548 LocVT == MVT::v32f16 ||
1549 LocVT == MVT::v32bf16 ||
1550 LocVT == MVT::v16f32 ||
1551 LocVT == MVT::v8f64) {
1552 static const MCPhysReg RegList3[] = {
1553 X86::ZMM0, X86::ZMM1, X86::ZMM2
1554 };
1555 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1556 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1557 return false;
1558 }
1559 }
1560 }
1561
1562 if (State.isVarArg() && State.getMachineFunction().getSubtarget().getTargetTriple().isWindowsMSVCEnvironment()) {
1563 if (!CC_X86_Win32_Vector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1564 return false;
1565 }
1566
1567 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1568 return false;
1569
1570 return true; // CC didn't match.
1571}
1572
1573
1574static bool CC_X86_64(unsigned ValNo, MVT ValVT,
1575 MVT LocVT, CCValAssign::LocInfo LocInfo,
1576 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1577
1578 if (State.getCallingConv() == CallingConv::GHC) {
1579 if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1580 return false;
1581 }
1582
1583 if (State.getCallingConv() == CallingConv::HiPE) {
1584 if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1585 return false;
1586 }
1587
1588 if (State.getCallingConv() == CallingConv::AnyReg) {
1589 if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1590 return false;
1591 }
1592
1593 if (State.getCallingConv() == CallingConv::Win64) {
1594 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1595 return false;
1596 }
1597
1598 if (State.getCallingConv() == CallingConv::X86_64_SysV) {
1599 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1600 return false;
1601 }
1602
1603 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
1604 if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1605 return false;
1606 }
1607
1608 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1609 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
1610 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
1611 if (!CC_X86_Win64_RegCallv4(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1612 return false;
1613 }
1614 }
1615 }
1616
1617 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1618 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
1619 if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1620 return false;
1621 }
1622 }
1623
1624 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1625 if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1626 return false;
1627 }
1628
1629 if (State.getCallingConv() == CallingConv::PreserveNone) {
1630 if (!CC_X86_64_Preserve_None(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1631 return false;
1632 }
1633
1634 if (State.getCallingConv() == CallingConv::X86_INTR) {
1635 if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1636 return false;
1637 }
1638
1639 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
1640 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1641 return false;
1642 }
1643
1644 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetUEFI64()) {
1645 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1646 return false;
1647 }
1648
1649 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1650 return false;
1651
1652 return true; // CC didn't match.
1653}
1654
1655
1656static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
1657 MVT LocVT, CCValAssign::LocInfo LocInfo,
1658 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1659
1660 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1661 return false;
1662
1663 return true; // CC didn't match.
1664}
1665
1666
1667static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
1668 MVT LocVT, CCValAssign::LocInfo LocInfo,
1669 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1670
1671 if (ArgFlags.isByVal()) {
1672 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1673 return false;
1674 }
1675
1676 if (LocVT == MVT::i1 ||
1677 LocVT == MVT::i8 ||
1678 LocVT == MVT::i16 ||
1679 LocVT == MVT::v1i1) {
1680 LocVT = MVT::i32;
1681 if (ArgFlags.isSExt())
1682 LocInfo = CCValAssign::SExt;
1683 else if (ArgFlags.isZExt())
1684 LocInfo = CCValAssign::ZExt;
1685 else
1686 LocInfo = CCValAssign::AExt;
1687 }
1688
1689 if (ArgFlags.isNest()) {
1690 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTarget64BitILP32()) {
1691 if (MCRegister Reg = State.AllocateReg(Reg: X86::R10D)) {
1692 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1693 return false;
1694 }
1695 }
1696 }
1697
1698 if (ArgFlags.isNest()) {
1699 if (MCRegister Reg = State.AllocateReg(Reg: X86::R10)) {
1700 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1701 return false;
1702 }
1703 }
1704
1705 if (ArgFlags.isSwiftSelf()) {
1706 if (LocVT == MVT::i64) {
1707 if (MCRegister Reg = State.AllocateReg(Reg: X86::R13)) {
1708 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1709 return false;
1710 }
1711 }
1712 }
1713
1714 if (ArgFlags.isSwiftError()) {
1715 if (LocVT == MVT::i64) {
1716 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
1717 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1718 return false;
1719 }
1720 }
1721 }
1722
1723 if (ArgFlags.isSwiftAsync()) {
1724 if (LocVT == MVT::i64) {
1725 if (MCRegister Reg = State.AllocateReg(Reg: X86::R14)) {
1726 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1727 return false;
1728 }
1729 }
1730 }
1731
1732 if (State.getCallingConv() == CallingConv::Swift) {
1733 if (ArgFlags.isSRet()) {
1734 if (LocVT == MVT::i64) {
1735 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1736 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1737 return false;
1738 }
1739 }
1740 }
1741 }
1742
1743 if (State.getCallingConv() == CallingConv::SwiftTail) {
1744 if (ArgFlags.isSRet()) {
1745 if (LocVT == MVT::i64) {
1746 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1747 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1748 return false;
1749 }
1750 }
1751 }
1752 }
1753
1754 if (ArgFlags.isPointer()) {
1755 if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1756 return false;
1757 }
1758
1759 if (LocVT == MVT::i32) {
1760 static const MCPhysReg RegList1[] = {
1761 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1762 };
1763 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1764 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1765 return false;
1766 }
1767 }
1768
1769 if (LocVT == MVT::i64) {
1770 if (ArgFlags.isInConsecutiveRegs()) {
1771 if (CC_X86_64_I128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1772 return false;
1773 }
1774 }
1775
1776 if (LocVT == MVT::i64) {
1777 static const MCPhysReg RegList2[] = {
1778 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1779 };
1780 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1781 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1782 return false;
1783 }
1784 }
1785
1786 if (LocVT == MVT::v2i1) {
1787 LocVT = MVT::v2i64;
1788 if (ArgFlags.isSExt())
1789 LocInfo = CCValAssign::SExt;
1790 else if (ArgFlags.isZExt())
1791 LocInfo = CCValAssign::ZExt;
1792 else
1793 LocInfo = CCValAssign::AExt;
1794 }
1795
1796 if (LocVT == MVT::v4i1) {
1797 LocVT = MVT::v4i32;
1798 if (ArgFlags.isSExt())
1799 LocInfo = CCValAssign::SExt;
1800 else if (ArgFlags.isZExt())
1801 LocInfo = CCValAssign::ZExt;
1802 else
1803 LocInfo = CCValAssign::AExt;
1804 }
1805
1806 if (LocVT == MVT::v8i1) {
1807 LocVT = MVT::v8i16;
1808 if (ArgFlags.isSExt())
1809 LocInfo = CCValAssign::SExt;
1810 else if (ArgFlags.isZExt())
1811 LocInfo = CCValAssign::ZExt;
1812 else
1813 LocInfo = CCValAssign::AExt;
1814 }
1815
1816 if (LocVT == MVT::v16i1) {
1817 LocVT = MVT::v16i8;
1818 if (ArgFlags.isSExt())
1819 LocInfo = CCValAssign::SExt;
1820 else if (ArgFlags.isZExt())
1821 LocInfo = CCValAssign::ZExt;
1822 else
1823 LocInfo = CCValAssign::AExt;
1824 }
1825
1826 if (LocVT == MVT::v32i1) {
1827 LocVT = MVT::v32i8;
1828 if (ArgFlags.isSExt())
1829 LocInfo = CCValAssign::SExt;
1830 else if (ArgFlags.isZExt())
1831 LocInfo = CCValAssign::ZExt;
1832 else
1833 LocInfo = CCValAssign::AExt;
1834 }
1835
1836 if (LocVT == MVT::v64i1) {
1837 LocVT = MVT::v64i8;
1838 if (ArgFlags.isSExt())
1839 LocInfo = CCValAssign::SExt;
1840 else if (ArgFlags.isZExt())
1841 LocInfo = CCValAssign::ZExt;
1842 else
1843 LocInfo = CCValAssign::AExt;
1844 }
1845
1846 if (LocVT == MVT::f16 ||
1847 LocVT == MVT::f32 ||
1848 LocVT == MVT::f64 ||
1849 LocVT == MVT::f128 ||
1850 LocVT == MVT::v16i8 ||
1851 LocVT == MVT::v8i16 ||
1852 LocVT == MVT::v4i32 ||
1853 LocVT == MVT::v2i64 ||
1854 LocVT == MVT::v8f16 ||
1855 LocVT == MVT::v8bf16 ||
1856 LocVT == MVT::v4f32 ||
1857 LocVT == MVT::v2f64) {
1858 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
1859 static const MCPhysReg RegList3[] = {
1860 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1861 };
1862 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1863 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1864 return false;
1865 }
1866 }
1867 }
1868
1869 if (!State.isVarArg()) {
1870 if (LocVT == MVT::v32i8 ||
1871 LocVT == MVT::v16i16 ||
1872 LocVT == MVT::v8i32 ||
1873 LocVT == MVT::v4i64 ||
1874 LocVT == MVT::v16f16 ||
1875 LocVT == MVT::v16bf16 ||
1876 LocVT == MVT::v8f32 ||
1877 LocVT == MVT::v4f64) {
1878 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1879 static const MCPhysReg RegList4[] = {
1880 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1881 };
1882 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1883 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1884 return false;
1885 }
1886 }
1887 }
1888 }
1889
1890 if (!State.isVarArg()) {
1891 if (LocVT == MVT::v64i8 ||
1892 LocVT == MVT::v32i16 ||
1893 LocVT == MVT::v16i32 ||
1894 LocVT == MVT::v8i64 ||
1895 LocVT == MVT::v32f16 ||
1896 LocVT == MVT::v32bf16 ||
1897 LocVT == MVT::v16f32 ||
1898 LocVT == MVT::v8f64) {
1899 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
1900 static const MCPhysReg RegList5[] = {
1901 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1902 };
1903 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
1904 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1905 return false;
1906 }
1907 }
1908 }
1909 }
1910
1911 if (LocVT == MVT::i32 ||
1912 LocVT == MVT::i64 ||
1913 LocVT == MVT::f16 ||
1914 LocVT == MVT::f32 ||
1915 LocVT == MVT::f64) {
1916 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
1917 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1918 return false;
1919 }
1920
1921 if (LocVT == MVT::f80 ||
1922 LocVT == MVT::f128) {
1923 int64_t Offset7 = State.AllocateStack(
1924 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1925 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1926 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
1927 return false;
1928 }
1929
1930 if (LocVT == MVT::v16i8 ||
1931 LocVT == MVT::v8i16 ||
1932 LocVT == MVT::v4i32 ||
1933 LocVT == MVT::v2i64 ||
1934 LocVT == MVT::v8f16 ||
1935 LocVT == MVT::v8bf16 ||
1936 LocVT == MVT::v4f32 ||
1937 LocVT == MVT::v2f64) {
1938 int64_t Offset8 = State.AllocateStack(Size: 16, Alignment: Align(16));
1939 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1940 return false;
1941 }
1942
1943 if (LocVT == MVT::v32i8 ||
1944 LocVT == MVT::v16i16 ||
1945 LocVT == MVT::v8i32 ||
1946 LocVT == MVT::v4i64 ||
1947 LocVT == MVT::v16f16 ||
1948 LocVT == MVT::v16bf16 ||
1949 LocVT == MVT::v8f32 ||
1950 LocVT == MVT::v4f64) {
1951 int64_t Offset9 = State.AllocateStack(Size: 32, Alignment: Align(32));
1952 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1953 return false;
1954 }
1955
1956 if (LocVT == MVT::v64i8 ||
1957 LocVT == MVT::v32i16 ||
1958 LocVT == MVT::v16i32 ||
1959 LocVT == MVT::v8i64 ||
1960 LocVT == MVT::v32f16 ||
1961 LocVT == MVT::v32bf16 ||
1962 LocVT == MVT::v16f32 ||
1963 LocVT == MVT::v8f64) {
1964 int64_t Offset10 = State.AllocateStack(Size: 64, Alignment: Align(64));
1965 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1966 return false;
1967 }
1968
1969 return true; // CC didn't match.
1970}
1971
1972
1973static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
1974 MVT LocVT, CCValAssign::LocInfo LocInfo,
1975 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1976
1977 if (LocVT == MVT::i8 ||
1978 LocVT == MVT::i16 ||
1979 LocVT == MVT::i32) {
1980 LocVT = MVT::i64;
1981 if (ArgFlags.isSExt())
1982 LocInfo = CCValAssign::SExt;
1983 else if (ArgFlags.isZExt())
1984 LocInfo = CCValAssign::ZExt;
1985 else
1986 LocInfo = CCValAssign::AExt;
1987 }
1988
1989 if (LocVT == MVT::i64) {
1990 static const MCPhysReg RegList1[] = {
1991 X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
1992 };
1993 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1994 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1995 return false;
1996 }
1997 }
1998
1999 if (LocVT == MVT::f32 ||
2000 LocVT == MVT::f64 ||
2001 LocVT == MVT::v16i8 ||
2002 LocVT == MVT::v8i16 ||
2003 LocVT == MVT::v4i32 ||
2004 LocVT == MVT::v2i64 ||
2005 LocVT == MVT::v4f32 ||
2006 LocVT == MVT::v2f64) {
2007 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2008 static const MCPhysReg RegList2[] = {
2009 X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
2010 };
2011 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2012 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2013 return false;
2014 }
2015 }
2016 }
2017
2018 if (LocVT == MVT::v32i8 ||
2019 LocVT == MVT::v16i16 ||
2020 LocVT == MVT::v8i32 ||
2021 LocVT == MVT::v4i64 ||
2022 LocVT == MVT::v8f32 ||
2023 LocVT == MVT::v4f64) {
2024 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
2025 static const MCPhysReg RegList3[] = {
2026 X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6
2027 };
2028 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2029 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2030 return false;
2031 }
2032 }
2033 }
2034
2035 if (LocVT == MVT::v64i8 ||
2036 LocVT == MVT::v32i16 ||
2037 LocVT == MVT::v16i32 ||
2038 LocVT == MVT::v8i64 ||
2039 LocVT == MVT::v16f32 ||
2040 LocVT == MVT::v8f64) {
2041 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
2042 static const MCPhysReg RegList4[] = {
2043 X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6
2044 };
2045 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2046 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2047 return false;
2048 }
2049 }
2050 }
2051
2052 return true; // CC didn't match.
2053}
2054
2055
2056static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
2057 MVT LocVT, CCValAssign::LocInfo LocInfo,
2058 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2059
2060 if (LocVT == MVT::i8 ||
2061 LocVT == MVT::i16 ||
2062 LocVT == MVT::i32) {
2063 LocVT = MVT::i64;
2064 if (ArgFlags.isSExt())
2065 LocInfo = CCValAssign::SExt;
2066 else if (ArgFlags.isZExt())
2067 LocInfo = CCValAssign::ZExt;
2068 else
2069 LocInfo = CCValAssign::AExt;
2070 }
2071
2072 if (LocVT == MVT::i64) {
2073 static const MCPhysReg RegList1[] = {
2074 X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8
2075 };
2076 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2077 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2078 return false;
2079 }
2080 }
2081
2082 if (LocVT == MVT::i32 ||
2083 LocVT == MVT::i64 ||
2084 LocVT == MVT::f32 ||
2085 LocVT == MVT::f64) {
2086 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(8));
2087 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
2088 return false;
2089 }
2090
2091 return true; // CC didn't match.
2092}
2093
2094
2095static bool CC_X86_64_Preserve_None(unsigned ValNo, MVT ValVT,
2096 MVT LocVT, CCValAssign::LocInfo LocInfo,
2097 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2098
2099 if (ArgFlags.isByVal()) {
2100 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2101 return false;
2102 }
2103
2104 if (LocVT == MVT::i32) {
2105 static const MCPhysReg RegList1[] = {
2106 X86::R12D, X86::R13D, X86::R14D, X86::R15D, X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D, X86::R11D, X86::EAX
2107 };
2108 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2109 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2110 return false;
2111 }
2112 }
2113
2114 if (LocVT == MVT::i64) {
2115 static const MCPhysReg RegList2[] = {
2116 X86::R12, X86::R13, X86::R14, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::R11, X86::RAX
2117 };
2118 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2119 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2120 return false;
2121 }
2122 }
2123
2124 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
2125 return false;
2126
2127 return true; // CC didn't match.
2128}
2129
2130
2131static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
2132 MVT LocVT, CCValAssign::LocInfo LocInfo,
2133 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2134
2135 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2136 if (ArgFlags.isByVal()) {
2137 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2138 return false;
2139 }
2140 }
2141
2142 if (ArgFlags.isByVal()) {
2143 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2144 return false;
2145 }
2146
2147 if (LocVT == MVT::i1 ||
2148 LocVT == MVT::i8 ||
2149 LocVT == MVT::i16 ||
2150 LocVT == MVT::v1i1) {
2151 LocVT = MVT::i32;
2152 if (ArgFlags.isSExt())
2153 LocInfo = CCValAssign::SExt;
2154 else if (ArgFlags.isZExt())
2155 LocInfo = CCValAssign::ZExt;
2156 else
2157 LocInfo = CCValAssign::AExt;
2158 }
2159
2160 if (LocVT == MVT::v8i1 ||
2161 LocVT == MVT::v16i1 ||
2162 LocVT == MVT::v32i1) {
2163 LocVT = MVT::i32;
2164 if (ArgFlags.isSExt())
2165 LocInfo = CCValAssign::SExt;
2166 else if (ArgFlags.isZExt())
2167 LocInfo = CCValAssign::ZExt;
2168 else
2169 LocInfo = CCValAssign::AExt;
2170 }
2171
2172 if (LocVT == MVT::i32) {
2173 static const MCPhysReg RegList1[] = {
2174 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
2175 };
2176 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2177 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2178 return false;
2179 }
2180 }
2181
2182 if (LocVT == MVT::i64) {
2183 static const MCPhysReg RegList2[] = {
2184 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2185 };
2186 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2187 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2188 return false;
2189 }
2190 }
2191
2192 if (LocVT == MVT::v64i1) {
2193 LocVT = MVT::i64;
2194 if (ArgFlags.isSExt())
2195 LocInfo = CCValAssign::SExt;
2196 else if (ArgFlags.isZExt())
2197 LocInfo = CCValAssign::ZExt;
2198 else
2199 LocInfo = CCValAssign::AExt;
2200 }
2201
2202 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2203 if (LocVT == MVT::i64) {
2204 static const MCPhysReg RegList3[] = {
2205 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2206 };
2207 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2208 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2209 return false;
2210 }
2211 }
2212 }
2213
2214 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
2215 if (LocVT == MVT::i64) {
2216 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2217 return false;
2218 }
2219 }
2220
2221 if (LocVT == MVT::f32 ||
2222 LocVT == MVT::f64 ||
2223 LocVT == MVT::f128) {
2224 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2225 static const MCPhysReg RegList4[] = {
2226 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2227 };
2228 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2229 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2230 return false;
2231 }
2232 }
2233 }
2234
2235 if (LocVT == MVT::f80) {
2236 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
2237 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2238 return false;
2239 }
2240 }
2241
2242 if (LocVT == MVT::v16i8 ||
2243 LocVT == MVT::v8i16 ||
2244 LocVT == MVT::v4i32 ||
2245 LocVT == MVT::v2i64 ||
2246 LocVT == MVT::v4f32 ||
2247 LocVT == MVT::v2f64) {
2248 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2249 static const MCPhysReg RegList5[] = {
2250 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2251 };
2252 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2253 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2254 return false;
2255 }
2256 }
2257 }
2258
2259 if (LocVT == MVT::v32i8 ||
2260 LocVT == MVT::v16i16 ||
2261 LocVT == MVT::v8i32 ||
2262 LocVT == MVT::v4i64 ||
2263 LocVT == MVT::v8f32 ||
2264 LocVT == MVT::v4f64) {
2265 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
2266 static const MCPhysReg RegList6[] = {
2267 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2268 };
2269 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2270 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2271 return false;
2272 }
2273 }
2274 }
2275
2276 if (LocVT == MVT::v64i8 ||
2277 LocVT == MVT::v32i16 ||
2278 LocVT == MVT::v16i32 ||
2279 LocVT == MVT::v8i64 ||
2280 LocVT == MVT::v16f32 ||
2281 LocVT == MVT::v8f64) {
2282 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
2283 static const MCPhysReg RegList7[] = {
2284 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2285 };
2286 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2287 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2288 return false;
2289 }
2290 }
2291 }
2292
2293 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2294 if (LocVT == MVT::i32 ||
2295 LocVT == MVT::i64 ||
2296 LocVT == MVT::f32 ||
2297 LocVT == MVT::f64) {
2298 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
2299 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
2300 return false;
2301 }
2302 }
2303
2304 if (LocVT == MVT::i32 ||
2305 LocVT == MVT::f32) {
2306 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
2307 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
2308 return false;
2309 }
2310
2311 if (LocVT == MVT::i64 ||
2312 LocVT == MVT::f64) {
2313 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
2314 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
2315 return false;
2316 }
2317
2318 if (LocVT == MVT::f80 ||
2319 LocVT == MVT::f128) {
2320 int64_t Offset11 = State.AllocateStack(
2321 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
2322 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
2323 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
2324 return false;
2325 }
2326
2327 if (LocVT == MVT::v16i8 ||
2328 LocVT == MVT::v8i16 ||
2329 LocVT == MVT::v4i32 ||
2330 LocVT == MVT::v2i64 ||
2331 LocVT == MVT::v4f32 ||
2332 LocVT == MVT::v2f64) {
2333 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
2334 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
2335 return false;
2336 }
2337
2338 if (LocVT == MVT::v32i8 ||
2339 LocVT == MVT::v16i16 ||
2340 LocVT == MVT::v8i32 ||
2341 LocVT == MVT::v4i64 ||
2342 LocVT == MVT::v8f32 ||
2343 LocVT == MVT::v4f64) {
2344 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
2345 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2346 return false;
2347 }
2348
2349 if (LocVT == MVT::v64i8 ||
2350 LocVT == MVT::v32i16 ||
2351 LocVT == MVT::v16i32 ||
2352 LocVT == MVT::v8i64 ||
2353 LocVT == MVT::v16f32 ||
2354 LocVT == MVT::v8f64) {
2355 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
2356 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
2357 return false;
2358 }
2359
2360 return true; // CC didn't match.
2361}
2362
2363
2364static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
2365 MVT LocVT, CCValAssign::LocInfo LocInfo,
2366 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2367
2368 if (LocVT == MVT::i32) {
2369 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
2370 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2371 return false;
2372 }
2373 }
2374
2375 return true; // CC didn't match.
2376}
2377
2378
2379static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT,
2380 MVT LocVT, CCValAssign::LocInfo LocInfo,
2381 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2382
2383 if (LocVT == MVT::v16i8 ||
2384 LocVT == MVT::v8i16 ||
2385 LocVT == MVT::v4i32 ||
2386 LocVT == MVT::v2i64 ||
2387 LocVT == MVT::v8f16 ||
2388 LocVT == MVT::v8bf16 ||
2389 LocVT == MVT::v4f32 ||
2390 LocVT == MVT::v2f64) {
2391 int64_t Offset1 = State.AllocateStack(Size: 16, Alignment: Align(4));
2392 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
2393 return false;
2394 }
2395
2396 if (LocVT == MVT::v32i8 ||
2397 LocVT == MVT::v16i16 ||
2398 LocVT == MVT::v8i32 ||
2399 LocVT == MVT::v4i64 ||
2400 LocVT == MVT::v16f16 ||
2401 LocVT == MVT::v16bf16 ||
2402 LocVT == MVT::v8f32 ||
2403 LocVT == MVT::v4f64) {
2404 int64_t Offset2 = State.AllocateStack(Size: 32, Alignment: Align(4));
2405 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
2406 return false;
2407 }
2408
2409 if (LocVT == MVT::v64i8 ||
2410 LocVT == MVT::v32i16 ||
2411 LocVT == MVT::v16i32 ||
2412 LocVT == MVT::v8i64 ||
2413 LocVT == MVT::v32f16 ||
2414 LocVT == MVT::v32bf16 ||
2415 LocVT == MVT::v16f32 ||
2416 LocVT == MVT::v8f64) {
2417 int64_t Offset3 = State.AllocateStack(Size: 64, Alignment: Align(4));
2418 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
2419 return false;
2420 }
2421
2422 return true; // CC didn't match.
2423}
2424
2425
2426static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
2427 MVT LocVT, CCValAssign::LocInfo LocInfo,
2428 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2429
2430 if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2431 return false;
2432
2433 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
2434 return false;
2435
2436 return true; // CC didn't match.
2437}
2438
2439
2440static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
2441 MVT LocVT, CCValAssign::LocInfo LocInfo,
2442 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2443
2444 if (ArgFlags.isByVal()) {
2445 LocVT = MVT::i64;
2446 LocInfo = CCValAssign::Indirect;
2447 }
2448
2449 if (LocVT == MVT::i1 ||
2450 LocVT == MVT::v1i1) {
2451 LocVT = MVT::i8;
2452 if (ArgFlags.isSExt())
2453 LocInfo = CCValAssign::SExt;
2454 else if (ArgFlags.isZExt())
2455 LocInfo = CCValAssign::ZExt;
2456 else
2457 LocInfo = CCValAssign::AExt;
2458 }
2459
2460 if (ArgFlags.isNest()) {
2461 if (MCRegister Reg = State.AllocateReg(Reg: X86::R10)) {
2462 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2463 return false;
2464 }
2465 }
2466
2467 if (ArgFlags.isSwiftError()) {
2468 if (LocVT == MVT::i64) {
2469 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
2470 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2471 return false;
2472 }
2473 }
2474 }
2475
2476 if (ArgFlags.isSwiftSelf()) {
2477 if (LocVT == MVT::i64) {
2478 if (MCRegister Reg = State.AllocateReg(Reg: X86::R13)) {
2479 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2480 return false;
2481 }
2482 }
2483 }
2484
2485 if (ArgFlags.isSwiftAsync()) {
2486 if (LocVT == MVT::i64) {
2487 if (MCRegister Reg = State.AllocateReg(Reg: X86::R14)) {
2488 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2489 return false;
2490 }
2491 }
2492 }
2493
2494 if (ArgFlags.isCFGuardTarget()) {
2495 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
2496 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2497 return false;
2498 }
2499 }
2500
2501 if (LocVT == MVT::v16i8 ||
2502 LocVT == MVT::v8i16 ||
2503 LocVT == MVT::v4i32 ||
2504 LocVT == MVT::v2i64 ||
2505 LocVT == MVT::v8f16 ||
2506 LocVT == MVT::v8bf16 ||
2507 LocVT == MVT::v4f32 ||
2508 LocVT == MVT::v2f64) {
2509 LocVT = MVT::i64;
2510 LocInfo = CCValAssign::Indirect;
2511 }
2512
2513 if (LocVT == MVT::v32i8 ||
2514 LocVT == MVT::v16i16 ||
2515 LocVT == MVT::v8i32 ||
2516 LocVT == MVT::v4i64 ||
2517 LocVT == MVT::v16f16 ||
2518 LocVT == MVT::v16bf16 ||
2519 LocVT == MVT::v8f32 ||
2520 LocVT == MVT::v4f64) {
2521 LocVT = MVT::i64;
2522 LocInfo = CCValAssign::Indirect;
2523 }
2524
2525 if (LocVT == MVT::v64i8 ||
2526 LocVT == MVT::v32i16 ||
2527 LocVT == MVT::v16i32 ||
2528 LocVT == MVT::v32f16 ||
2529 LocVT == MVT::v32bf16 ||
2530 LocVT == MVT::v16f32 ||
2531 LocVT == MVT::v8f64 ||
2532 LocVT == MVT::v8i64) {
2533 LocVT = MVT::i64;
2534 LocInfo = CCValAssign::Indirect;
2535 }
2536
2537 if (LocVT == MVT::f80) {
2538 LocVT = MVT::i64;
2539 LocInfo = CCValAssign::Indirect;
2540 }
2541
2542 if (LocVT == MVT::f128) {
2543 LocVT = MVT::i64;
2544 LocInfo = CCValAssign::Indirect;
2545 }
2546
2547 if (LocVT == MVT::f32) {
2548 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2549 LocVT = MVT::i32;
2550 LocInfo = CCValAssign::BCvt;
2551 }
2552 }
2553
2554 if (LocVT == MVT::f64) {
2555 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2556 LocVT = MVT::i64;
2557 LocInfo = CCValAssign::BCvt;
2558 }
2559 }
2560
2561 if (LocVT == MVT::f16 ||
2562 LocVT == MVT::f32 ||
2563 LocVT == MVT::f64) {
2564 static const MCPhysReg RegList1[] = {
2565 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2566 };
2567 static const MCPhysReg RegList2[] = {
2568 X86::RCX, X86::RDX, X86::R8, X86::R9
2569 };
2570 if (MCRegister Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
2571 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2572 return false;
2573 }
2574 }
2575
2576 if (LocVT == MVT::i8) {
2577 static const MCPhysReg RegList3[] = {
2578 X86::CL, X86::DL, X86::R8B, X86::R9B
2579 };
2580 static const MCPhysReg RegList4[] = {
2581 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2582 };
2583 if (MCRegister Reg = State.AllocateReg(Regs: RegList3, ShadowRegs: RegList4)) {
2584 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2585 return false;
2586 }
2587 }
2588
2589 if (LocVT == MVT::i16) {
2590 static const MCPhysReg RegList5[] = {
2591 X86::CX, X86::DX, X86::R8W, X86::R9W
2592 };
2593 static const MCPhysReg RegList6[] = {
2594 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2595 };
2596 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
2597 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2598 return false;
2599 }
2600 }
2601
2602 if (LocVT == MVT::i32) {
2603 static const MCPhysReg RegList7[] = {
2604 X86::ECX, X86::EDX, X86::R8D, X86::R9D
2605 };
2606 static const MCPhysReg RegList8[] = {
2607 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2608 };
2609 if (MCRegister Reg = State.AllocateReg(Regs: RegList7, ShadowRegs: RegList8)) {
2610 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2611 return false;
2612 }
2613 }
2614
2615 if (State.getCallingConv() == CallingConv::X86_ThisCall) {
2616 if (ArgFlags.isSRet()) {
2617 if (LocVT == MVT::i64) {
2618 static const MCPhysReg RegList9[] = {
2619 X86::RDX, X86::R8, X86::R9
2620 };
2621 static const MCPhysReg RegList10[] = {
2622 X86::XMM1, X86::XMM2, X86::XMM3
2623 };
2624 if (MCRegister Reg = State.AllocateReg(Regs: RegList9, ShadowRegs: RegList10)) {
2625 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2626 return false;
2627 }
2628 }
2629 }
2630 }
2631
2632 if (LocVT == MVT::i64) {
2633 static const MCPhysReg RegList11[] = {
2634 X86::RCX, X86::RDX, X86::R8, X86::R9
2635 };
2636 static const MCPhysReg RegList12[] = {
2637 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2638 };
2639 if (MCRegister Reg = State.AllocateReg(Regs: RegList11, ShadowRegs: RegList12)) {
2640 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2641 return false;
2642 }
2643 }
2644
2645 if (LocVT == MVT::i8 ||
2646 LocVT == MVT::i16 ||
2647 LocVT == MVT::i32 ||
2648 LocVT == MVT::i64 ||
2649 LocVT == MVT::f16 ||
2650 LocVT == MVT::f32 ||
2651 LocVT == MVT::f64) {
2652 int64_t Offset13 = State.AllocateStack(Size: 8, Alignment: Align(8));
2653 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2654 return false;
2655 }
2656
2657 return true; // CC didn't match.
2658}
2659
2660
2661static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
2662 MVT LocVT, CCValAssign::LocInfo LocInfo,
2663 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2664
2665 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2666 if (ArgFlags.isByVal()) {
2667 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2668 return false;
2669 }
2670 }
2671
2672 if (ArgFlags.isByVal()) {
2673 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2674 return false;
2675 }
2676
2677 if (LocVT == MVT::i1 ||
2678 LocVT == MVT::i8 ||
2679 LocVT == MVT::i16 ||
2680 LocVT == MVT::v1i1) {
2681 LocVT = MVT::i32;
2682 if (ArgFlags.isSExt())
2683 LocInfo = CCValAssign::SExt;
2684 else if (ArgFlags.isZExt())
2685 LocInfo = CCValAssign::ZExt;
2686 else
2687 LocInfo = CCValAssign::AExt;
2688 }
2689
2690 if (LocVT == MVT::v8i1 ||
2691 LocVT == MVT::v16i1 ||
2692 LocVT == MVT::v32i1) {
2693 LocVT = MVT::i32;
2694 if (ArgFlags.isSExt())
2695 LocInfo = CCValAssign::SExt;
2696 else if (ArgFlags.isZExt())
2697 LocInfo = CCValAssign::ZExt;
2698 else
2699 LocInfo = CCValAssign::AExt;
2700 }
2701
2702 if (LocVT == MVT::i32) {
2703 static const MCPhysReg RegList1[] = {
2704 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2705 };
2706 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2707 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2708 return false;
2709 }
2710 }
2711
2712 if (LocVT == MVT::i64) {
2713 static const MCPhysReg RegList2[] = {
2714 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2715 };
2716 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2717 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2718 return false;
2719 }
2720 }
2721
2722 if (LocVT == MVT::v64i1) {
2723 LocVT = MVT::i64;
2724 if (ArgFlags.isSExt())
2725 LocInfo = CCValAssign::SExt;
2726 else if (ArgFlags.isZExt())
2727 LocInfo = CCValAssign::ZExt;
2728 else
2729 LocInfo = CCValAssign::AExt;
2730 }
2731
2732 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2733 if (LocVT == MVT::i64) {
2734 static const MCPhysReg RegList3[] = {
2735 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2736 };
2737 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2738 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2739 return false;
2740 }
2741 }
2742 }
2743
2744 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
2745 if (LocVT == MVT::i64) {
2746 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2747 return false;
2748 }
2749 }
2750
2751 if (LocVT == MVT::f32 ||
2752 LocVT == MVT::f64 ||
2753 LocVT == MVT::f128) {
2754 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2755 static const MCPhysReg RegList4[] = {
2756 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2757 };
2758 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2759 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2760 return false;
2761 }
2762 }
2763 }
2764
2765 if (LocVT == MVT::f80) {
2766 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
2767 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2768 return false;
2769 }
2770 }
2771
2772 if (LocVT == MVT::v16i8 ||
2773 LocVT == MVT::v8i16 ||
2774 LocVT == MVT::v4i32 ||
2775 LocVT == MVT::v2i64 ||
2776 LocVT == MVT::v4f32 ||
2777 LocVT == MVT::v2f64) {
2778 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2779 static const MCPhysReg RegList5[] = {
2780 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2781 };
2782 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2783 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2784 return false;
2785 }
2786 }
2787 }
2788
2789 if (LocVT == MVT::v32i8 ||
2790 LocVT == MVT::v16i16 ||
2791 LocVT == MVT::v8i32 ||
2792 LocVT == MVT::v4i64 ||
2793 LocVT == MVT::v8f32 ||
2794 LocVT == MVT::v4f64) {
2795 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
2796 static const MCPhysReg RegList6[] = {
2797 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2798 };
2799 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2800 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2801 return false;
2802 }
2803 }
2804 }
2805
2806 if (LocVT == MVT::v64i8 ||
2807 LocVT == MVT::v32i16 ||
2808 LocVT == MVT::v16i32 ||
2809 LocVT == MVT::v8i64 ||
2810 LocVT == MVT::v16f32 ||
2811 LocVT == MVT::v8f64) {
2812 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
2813 static const MCPhysReg RegList7[] = {
2814 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2815 };
2816 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2817 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2818 return false;
2819 }
2820 }
2821 }
2822
2823 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2824 if (LocVT == MVT::i32 ||
2825 LocVT == MVT::i64 ||
2826 LocVT == MVT::f32 ||
2827 LocVT == MVT::f64) {
2828 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
2829 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
2830 return false;
2831 }
2832 }
2833
2834 if (LocVT == MVT::i32 ||
2835 LocVT == MVT::f32) {
2836 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
2837 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
2838 return false;
2839 }
2840
2841 if (LocVT == MVT::i64 ||
2842 LocVT == MVT::f64) {
2843 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
2844 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
2845 return false;
2846 }
2847
2848 if (LocVT == MVT::f80 ||
2849 LocVT == MVT::f128) {
2850 int64_t Offset11 = State.AllocateStack(
2851 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
2852 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
2853 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
2854 return false;
2855 }
2856
2857 if (LocVT == MVT::v16i8 ||
2858 LocVT == MVT::v8i16 ||
2859 LocVT == MVT::v4i32 ||
2860 LocVT == MVT::v2i64 ||
2861 LocVT == MVT::v4f32 ||
2862 LocVT == MVT::v2f64) {
2863 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
2864 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
2865 return false;
2866 }
2867
2868 if (LocVT == MVT::v32i8 ||
2869 LocVT == MVT::v16i16 ||
2870 LocVT == MVT::v8i32 ||
2871 LocVT == MVT::v4i64 ||
2872 LocVT == MVT::v8f32 ||
2873 LocVT == MVT::v4f64) {
2874 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
2875 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2876 return false;
2877 }
2878
2879 if (LocVT == MVT::v64i8 ||
2880 LocVT == MVT::v32i16 ||
2881 LocVT == MVT::v16i32 ||
2882 LocVT == MVT::v8i64 ||
2883 LocVT == MVT::v16f32 ||
2884 LocVT == MVT::v8f64) {
2885 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
2886 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
2887 return false;
2888 }
2889
2890 return true; // CC didn't match.
2891}
2892
2893
2894static bool CC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
2895 MVT LocVT, CCValAssign::LocInfo LocInfo,
2896 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2897
2898 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2899 if (ArgFlags.isByVal()) {
2900 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2901 return false;
2902 }
2903 }
2904
2905 if (ArgFlags.isByVal()) {
2906 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2907 return false;
2908 }
2909
2910 if (LocVT == MVT::i1 ||
2911 LocVT == MVT::i8 ||
2912 LocVT == MVT::i16 ||
2913 LocVT == MVT::v1i1) {
2914 LocVT = MVT::i32;
2915 if (ArgFlags.isSExt())
2916 LocInfo = CCValAssign::SExt;
2917 else if (ArgFlags.isZExt())
2918 LocInfo = CCValAssign::ZExt;
2919 else
2920 LocInfo = CCValAssign::AExt;
2921 }
2922
2923 if (LocVT == MVT::v8i1 ||
2924 LocVT == MVT::v16i1 ||
2925 LocVT == MVT::v32i1) {
2926 LocVT = MVT::i32;
2927 if (ArgFlags.isSExt())
2928 LocInfo = CCValAssign::SExt;
2929 else if (ArgFlags.isZExt())
2930 LocInfo = CCValAssign::ZExt;
2931 else
2932 LocInfo = CCValAssign::AExt;
2933 }
2934
2935 if (LocVT == MVT::i32) {
2936 static const MCPhysReg RegList1[] = {
2937 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2938 };
2939 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2940 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2941 return false;
2942 }
2943 }
2944
2945 if (LocVT == MVT::i64) {
2946 static const MCPhysReg RegList2[] = {
2947 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
2948 };
2949 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2950 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2951 return false;
2952 }
2953 }
2954
2955 if (LocVT == MVT::v64i1) {
2956 LocVT = MVT::i64;
2957 if (ArgFlags.isSExt())
2958 LocInfo = CCValAssign::SExt;
2959 else if (ArgFlags.isZExt())
2960 LocInfo = CCValAssign::ZExt;
2961 else
2962 LocInfo = CCValAssign::AExt;
2963 }
2964
2965 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2966 if (LocVT == MVT::i64) {
2967 static const MCPhysReg RegList3[] = {
2968 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
2969 };
2970 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2971 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2972 return false;
2973 }
2974 }
2975 }
2976
2977 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
2978 if (LocVT == MVT::i64) {
2979 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2980 return false;
2981 }
2982 }
2983
2984 if (LocVT == MVT::f32 ||
2985 LocVT == MVT::f64 ||
2986 LocVT == MVT::f128) {
2987 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2988 static const MCPhysReg RegList4[] = {
2989 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2990 };
2991 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2992 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2993 return false;
2994 }
2995 }
2996 }
2997
2998 if (LocVT == MVT::f80) {
2999 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
3000 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3001 return false;
3002 }
3003 }
3004
3005 if (LocVT == MVT::v16i8 ||
3006 LocVT == MVT::v8i16 ||
3007 LocVT == MVT::v4i32 ||
3008 LocVT == MVT::v2i64 ||
3009 LocVT == MVT::v4f32 ||
3010 LocVT == MVT::v2f64) {
3011 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3012 static const MCPhysReg RegList5[] = {
3013 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3014 };
3015 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3016 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3017 return false;
3018 }
3019 }
3020 }
3021
3022 if (LocVT == MVT::v32i8 ||
3023 LocVT == MVT::v16i16 ||
3024 LocVT == MVT::v8i32 ||
3025 LocVT == MVT::v4i64 ||
3026 LocVT == MVT::v8f32 ||
3027 LocVT == MVT::v4f64) {
3028 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
3029 static const MCPhysReg RegList6[] = {
3030 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3031 };
3032 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3033 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3034 return false;
3035 }
3036 }
3037 }
3038
3039 if (LocVT == MVT::v64i8 ||
3040 LocVT == MVT::v32i16 ||
3041 LocVT == MVT::v16i32 ||
3042 LocVT == MVT::v8i64 ||
3043 LocVT == MVT::v16f32 ||
3044 LocVT == MVT::v8f64) {
3045 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
3046 static const MCPhysReg RegList7[] = {
3047 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3048 };
3049 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3050 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3051 return false;
3052 }
3053 }
3054 }
3055
3056 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3057 if (LocVT == MVT::i32 ||
3058 LocVT == MVT::i64 ||
3059 LocVT == MVT::f32 ||
3060 LocVT == MVT::f64) {
3061 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
3062 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
3063 return false;
3064 }
3065 }
3066
3067 if (LocVT == MVT::i32 ||
3068 LocVT == MVT::f32) {
3069 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
3070 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
3071 return false;
3072 }
3073
3074 if (LocVT == MVT::i64 ||
3075 LocVT == MVT::f64) {
3076 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
3077 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
3078 return false;
3079 }
3080
3081 if (LocVT == MVT::f80 ||
3082 LocVT == MVT::f128) {
3083 int64_t Offset11 = State.AllocateStack(
3084 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
3085 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
3086 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
3087 return false;
3088 }
3089
3090 if (LocVT == MVT::v16i8 ||
3091 LocVT == MVT::v8i16 ||
3092 LocVT == MVT::v4i32 ||
3093 LocVT == MVT::v2i64 ||
3094 LocVT == MVT::v4f32 ||
3095 LocVT == MVT::v2f64) {
3096 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
3097 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
3098 return false;
3099 }
3100
3101 if (LocVT == MVT::v32i8 ||
3102 LocVT == MVT::v16i16 ||
3103 LocVT == MVT::v8i32 ||
3104 LocVT == MVT::v4i64 ||
3105 LocVT == MVT::v8f32 ||
3106 LocVT == MVT::v4f64) {
3107 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
3108 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
3109 return false;
3110 }
3111
3112 if (LocVT == MVT::v64i8 ||
3113 LocVT == MVT::v32i16 ||
3114 LocVT == MVT::v16i32 ||
3115 LocVT == MVT::v8i64 ||
3116 LocVT == MVT::v16f32 ||
3117 LocVT == MVT::v8f64) {
3118 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
3119 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
3120 return false;
3121 }
3122
3123 return true; // CC didn't match.
3124}
3125
3126
3127static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
3128 MVT LocVT, CCValAssign::LocInfo LocInfo,
3129 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3130
3131 if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3132 return false;
3133
3134 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3135 return false;
3136
3137 return true; // CC didn't match.
3138}
3139
3140
3141static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
3142 MVT LocVT, CCValAssign::LocInfo LocInfo,
3143 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3144
3145 if (LocVT == MVT::f32 ||
3146 LocVT == MVT::f64 ||
3147 LocVT == MVT::v4i32 ||
3148 LocVT == MVT::v2i64 ||
3149 LocVT == MVT::v4f32 ||
3150 LocVT == MVT::v2f64) {
3151 static const MCPhysReg RegList1[] = {
3152 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3153 };
3154 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3155 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3156 return false;
3157 }
3158 }
3159
3160 if (LocVT == MVT::v8f32 ||
3161 LocVT == MVT::v4f64 ||
3162 LocVT == MVT::v8i32 ||
3163 LocVT == MVT::v4i64) {
3164 static const MCPhysReg RegList2[] = {
3165 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
3166 };
3167 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3168 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3169 return false;
3170 }
3171 }
3172
3173 if (LocVT == MVT::v16f32 ||
3174 LocVT == MVT::v8f64 ||
3175 LocVT == MVT::v16i32 ||
3176 LocVT == MVT::v8i64) {
3177 static const MCPhysReg RegList3[] = {
3178 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
3179 };
3180 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3181 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3182 return false;
3183 }
3184 }
3185
3186 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3187 return false;
3188
3189 return true; // CC didn't match.
3190}
3191
3192
3193bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
3194 MVT LocVT, CCValAssign::LocInfo LocInfo,
3195 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3196
3197 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
3198 if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3199 return false;
3200 }
3201
3202 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3203 if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3204 return false;
3205 }
3206
3207 if (!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3208 return false;
3209
3210 return true; // CC didn't match.
3211}
3212
3213
3214static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
3215 MVT LocVT, CCValAssign::LocInfo LocInfo,
3216 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3217
3218 if (LocVT == MVT::v1i1) {
3219 LocVT = MVT::i8;
3220 if (ArgFlags.isSExt())
3221 LocInfo = CCValAssign::SExt;
3222 else if (ArgFlags.isZExt())
3223 LocInfo = CCValAssign::ZExt;
3224 else
3225 LocInfo = CCValAssign::AExt;
3226 }
3227
3228 if (LocVT == MVT::i1) {
3229 LocVT = MVT::i8;
3230 if (ArgFlags.isSExt())
3231 LocInfo = CCValAssign::SExt;
3232 else if (ArgFlags.isZExt())
3233 LocInfo = CCValAssign::ZExt;
3234 else
3235 LocInfo = CCValAssign::AExt;
3236 }
3237
3238 if (LocVT == MVT::i8) {
3239 static const MCPhysReg RegList1[] = {
3240 X86::AL, X86::DL, X86::CL
3241 };
3242 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3243 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3244 return false;
3245 }
3246 }
3247
3248 if (LocVT == MVT::i16) {
3249 static const MCPhysReg RegList2[] = {
3250 X86::AX, X86::DX, X86::CX
3251 };
3252 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3253 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3254 return false;
3255 }
3256 }
3257
3258 if (LocVT == MVT::i32) {
3259 static const MCPhysReg RegList3[] = {
3260 X86::EAX, X86::EDX, X86::ECX
3261 };
3262 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3263 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3264 return false;
3265 }
3266 }
3267
3268 if (LocVT == MVT::i64) {
3269 static const MCPhysReg RegList4[] = {
3270 X86::RAX, X86::RDX, X86::RCX
3271 };
3272 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3273 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3274 return false;
3275 }
3276 }
3277
3278 if (LocVT == MVT::v2i1) {
3279 LocVT = MVT::v2i64;
3280 if (ArgFlags.isSExt())
3281 LocInfo = CCValAssign::SExt;
3282 else if (ArgFlags.isZExt())
3283 LocInfo = CCValAssign::ZExt;
3284 else
3285 LocInfo = CCValAssign::AExt;
3286 }
3287
3288 if (LocVT == MVT::v4i1) {
3289 LocVT = MVT::v4i32;
3290 if (ArgFlags.isSExt())
3291 LocInfo = CCValAssign::SExt;
3292 else if (ArgFlags.isZExt())
3293 LocInfo = CCValAssign::ZExt;
3294 else
3295 LocInfo = CCValAssign::AExt;
3296 }
3297
3298 if (LocVT == MVT::v8i1) {
3299 LocVT = MVT::v8i16;
3300 if (ArgFlags.isSExt())
3301 LocInfo = CCValAssign::SExt;
3302 else if (ArgFlags.isZExt())
3303 LocInfo = CCValAssign::ZExt;
3304 else
3305 LocInfo = CCValAssign::AExt;
3306 }
3307
3308 if (LocVT == MVT::v16i1) {
3309 LocVT = MVT::v16i8;
3310 if (ArgFlags.isSExt())
3311 LocInfo = CCValAssign::SExt;
3312 else if (ArgFlags.isZExt())
3313 LocInfo = CCValAssign::ZExt;
3314 else
3315 LocInfo = CCValAssign::AExt;
3316 }
3317
3318 if (LocVT == MVT::v32i1) {
3319 LocVT = MVT::v32i8;
3320 if (ArgFlags.isSExt())
3321 LocInfo = CCValAssign::SExt;
3322 else if (ArgFlags.isZExt())
3323 LocInfo = CCValAssign::ZExt;
3324 else
3325 LocInfo = CCValAssign::AExt;
3326 }
3327
3328 if (LocVT == MVT::v64i1) {
3329 LocVT = MVT::v64i8;
3330 if (ArgFlags.isSExt())
3331 LocInfo = CCValAssign::SExt;
3332 else if (ArgFlags.isZExt())
3333 LocInfo = CCValAssign::ZExt;
3334 else
3335 LocInfo = CCValAssign::AExt;
3336 }
3337
3338 if (LocVT == MVT::v16i8 ||
3339 LocVT == MVT::v8i16 ||
3340 LocVT == MVT::v4i32 ||
3341 LocVT == MVT::v2i64 ||
3342 LocVT == MVT::v8f16 ||
3343 LocVT == MVT::v8bf16 ||
3344 LocVT == MVT::v4f32 ||
3345 LocVT == MVT::v2f64) {
3346 static const MCPhysReg RegList5[] = {
3347 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3348 };
3349 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3350 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3351 return false;
3352 }
3353 }
3354
3355 if (LocVT == MVT::v32i8 ||
3356 LocVT == MVT::v16i16 ||
3357 LocVT == MVT::v8i32 ||
3358 LocVT == MVT::v4i64 ||
3359 LocVT == MVT::v16f16 ||
3360 LocVT == MVT::v16bf16 ||
3361 LocVT == MVT::v8f32 ||
3362 LocVT == MVT::v4f64) {
3363 static const MCPhysReg RegList6[] = {
3364 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
3365 };
3366 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3367 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3368 return false;
3369 }
3370 }
3371
3372 if (LocVT == MVT::v64i8 ||
3373 LocVT == MVT::v32i16 ||
3374 LocVT == MVT::v16i32 ||
3375 LocVT == MVT::v8i64 ||
3376 LocVT == MVT::v32f16 ||
3377 LocVT == MVT::v32bf16 ||
3378 LocVT == MVT::v16f32 ||
3379 LocVT == MVT::v8f64) {
3380 static const MCPhysReg RegList7[] = {
3381 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
3382 };
3383 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3384 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3385 return false;
3386 }
3387 }
3388
3389 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
3390 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetUEFI64()) {
3391 if (LocVT == MVT::f80) {
3392 static const MCPhysReg RegList8[] = {
3393 X86::FP0, X86::FP1
3394 };
3395 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
3396 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3397 return false;
3398 }
3399 }
3400 }
3401 }
3402
3403 return true; // CC didn't match.
3404}
3405
3406
3407static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
3408 MVT LocVT, CCValAssign::LocInfo LocInfo,
3409 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3410
3411 if (State.getCallingConv() == CallingConv::Fast) {
3412 if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3413 return false;
3414 }
3415
3416 if (State.getCallingConv() == CallingConv::Tail) {
3417 if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3418 return false;
3419 }
3420
3421 if (State.getCallingConv() == CallingConv::HiPE) {
3422 if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3423 return false;
3424 }
3425
3426 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
3427 if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3428 return false;
3429 }
3430
3431 if (State.getCallingConv() == CallingConv::X86_RegCall) {
3432 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin32()) {
3433 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
3434 if (!RetCC_X86_32_RegCallv4_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3435 return false;
3436 }
3437 }
3438 }
3439
3440 if (State.getCallingConv() == CallingConv::X86_RegCall) {
3441 if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3442 return false;
3443 }
3444
3445 if (!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3446 return false;
3447
3448 return true; // CC didn't match.
3449}
3450
3451
3452static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
3453 MVT LocVT, CCValAssign::LocInfo LocInfo,
3454 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3455
3456 if (ArgFlags.isInReg()) {
3457 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
3458 if (LocVT == MVT::f32 ||
3459 LocVT == MVT::f64) {
3460 static const MCPhysReg RegList1[] = {
3461 X86::XMM0, X86::XMM1, X86::XMM2
3462 };
3463 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3464 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3465 return false;
3466 }
3467 }
3468 }
3469 }
3470
3471 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasX87()) {
3472 if (LocVT == MVT::f32 ||
3473 LocVT == MVT::f64) {
3474 static const MCPhysReg RegList2[] = {
3475 X86::FP0, X86::FP1
3476 };
3477 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3478 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3479 return false;
3480 }
3481 }
3482 }
3483
3484 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasX87()) {
3485 if (LocVT == MVT::f32) {
3486 static const MCPhysReg RegList3[] = {
3487 X86::EAX, X86::EDX, X86::ECX
3488 };
3489 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3490 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3491 return false;
3492 }
3493 }
3494 }
3495
3496 if (LocVT == MVT::f16) {
3497 static const MCPhysReg RegList4[] = {
3498 X86::XMM0, X86::XMM1, X86::XMM2
3499 };
3500 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3501 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3502 return false;
3503 }
3504 }
3505
3506 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3507 return false;
3508
3509 return true; // CC didn't match.
3510}
3511
3512
3513static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
3514 MVT LocVT, CCValAssign::LocInfo LocInfo,
3515 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3516
3517 if (LocVT == MVT::f32) {
3518 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
3519 static const MCPhysReg RegList1[] = {
3520 X86::XMM0, X86::XMM1, X86::XMM2
3521 };
3522 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3523 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3524 return false;
3525 }
3526 }
3527 }
3528
3529 if (LocVT == MVT::f64) {
3530 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
3531 static const MCPhysReg RegList2[] = {
3532 X86::XMM0, X86::XMM1, X86::XMM2
3533 };
3534 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3535 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3536 return false;
3537 }
3538 }
3539 }
3540
3541 if (LocVT == MVT::i8) {
3542 static const MCPhysReg RegList3[] = {
3543 X86::AL, X86::DL, X86::CL
3544 };
3545 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3546 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3547 return false;
3548 }
3549 }
3550
3551 if (LocVT == MVT::i16) {
3552 static const MCPhysReg RegList4[] = {
3553 X86::AX, X86::DX, X86::CX
3554 };
3555 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3556 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3557 return false;
3558 }
3559 }
3560
3561 if (LocVT == MVT::i32) {
3562 static const MCPhysReg RegList5[] = {
3563 X86::EAX, X86::EDX, X86::ECX
3564 };
3565 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3566 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3567 return false;
3568 }
3569 }
3570
3571 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3572 return false;
3573
3574 return true; // CC didn't match.
3575}
3576
3577
3578static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
3579 MVT LocVT, CCValAssign::LocInfo LocInfo,
3580 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3581
3582 if (LocVT == MVT::i8 ||
3583 LocVT == MVT::i16) {
3584 LocVT = MVT::i32;
3585 if (ArgFlags.isSExt())
3586 LocInfo = CCValAssign::SExt;
3587 else if (ArgFlags.isZExt())
3588 LocInfo = CCValAssign::ZExt;
3589 else
3590 LocInfo = CCValAssign::AExt;
3591 }
3592
3593 if (LocVT == MVT::i32) {
3594 static const MCPhysReg RegList1[] = {
3595 X86::ESI, X86::EBP, X86::EAX, X86::EDX
3596 };
3597 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3598 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3599 return false;
3600 }
3601 }
3602
3603 return true; // CC didn't match.
3604}
3605
3606
3607static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
3608 MVT LocVT, CCValAssign::LocInfo LocInfo,
3609 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3610
3611 if (LocVT == MVT::i1 ||
3612 LocVT == MVT::v1i1 ||
3613 LocVT == MVT::v8i1) {
3614 LocVT = MVT::i8;
3615 if (ArgFlags.isSExt())
3616 LocInfo = CCValAssign::SExt;
3617 else if (ArgFlags.isZExt())
3618 LocInfo = CCValAssign::ZExt;
3619 else
3620 LocInfo = CCValAssign::AExt;
3621 }
3622
3623 if (LocVT == MVT::v16i1) {
3624 LocVT = MVT::i16;
3625 if (ArgFlags.isSExt())
3626 LocInfo = CCValAssign::SExt;
3627 else if (ArgFlags.isZExt())
3628 LocInfo = CCValAssign::ZExt;
3629 else
3630 LocInfo = CCValAssign::AExt;
3631 }
3632
3633 if (LocVT == MVT::v32i1) {
3634 LocVT = MVT::i32;
3635 if (ArgFlags.isSExt())
3636 LocInfo = CCValAssign::SExt;
3637 else if (ArgFlags.isZExt())
3638 LocInfo = CCValAssign::ZExt;
3639 else
3640 LocInfo = CCValAssign::AExt;
3641 }
3642
3643 if (LocVT == MVT::i8) {
3644 static const MCPhysReg RegList1[] = {
3645 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL
3646 };
3647 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3648 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3649 return false;
3650 }
3651 }
3652
3653 if (LocVT == MVT::i16) {
3654 static const MCPhysReg RegList2[] = {
3655 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI
3656 };
3657 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3658 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3659 return false;
3660 }
3661 }
3662
3663 if (LocVT == MVT::i32) {
3664 static const MCPhysReg RegList3[] = {
3665 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
3666 };
3667 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3668 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3669 return false;
3670 }
3671 }
3672
3673 if (LocVT == MVT::i64) {
3674 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3675 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3676 return false;
3677 }
3678 }
3679
3680 if (LocVT == MVT::v64i1) {
3681 LocVT = MVT::i64;
3682 if (ArgFlags.isSExt())
3683 LocInfo = CCValAssign::SExt;
3684 else if (ArgFlags.isZExt())
3685 LocInfo = CCValAssign::ZExt;
3686 else
3687 LocInfo = CCValAssign::AExt;
3688 }
3689
3690 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3691 if (LocVT == MVT::i64) {
3692 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3693 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3694 return false;
3695 }
3696 }
3697 }
3698
3699 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
3700 if (LocVT == MVT::i64) {
3701 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3702 return false;
3703 }
3704 }
3705
3706 if (LocVT == MVT::f80) {
3707 static const MCPhysReg RegList4[] = {
3708 X86::FP0, X86::FP1
3709 };
3710 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3711 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3712 return false;
3713 }
3714 }
3715
3716 if (LocVT == MVT::f32 ||
3717 LocVT == MVT::f64 ||
3718 LocVT == MVT::f128) {
3719 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3720 static const MCPhysReg RegList5[] = {
3721 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3722 };
3723 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3724 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3725 return false;
3726 }
3727 }
3728 }
3729
3730 if (LocVT == MVT::v16i8 ||
3731 LocVT == MVT::v8i16 ||
3732 LocVT == MVT::v4i32 ||
3733 LocVT == MVT::v2i64 ||
3734 LocVT == MVT::v4f32 ||
3735 LocVT == MVT::v2f64) {
3736 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3737 static const MCPhysReg RegList6[] = {
3738 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3739 };
3740 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3741 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3742 return false;
3743 }
3744 }
3745 }
3746
3747 if (LocVT == MVT::v32i8 ||
3748 LocVT == MVT::v16i16 ||
3749 LocVT == MVT::v8i32 ||
3750 LocVT == MVT::v4i64 ||
3751 LocVT == MVT::v8f32 ||
3752 LocVT == MVT::v4f64) {
3753 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
3754 static const MCPhysReg RegList7[] = {
3755 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3756 };
3757 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3758 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3759 return false;
3760 }
3761 }
3762 }
3763
3764 if (LocVT == MVT::v64i8 ||
3765 LocVT == MVT::v32i16 ||
3766 LocVT == MVT::v16i32 ||
3767 LocVT == MVT::v8i64 ||
3768 LocVT == MVT::v16f32 ||
3769 LocVT == MVT::v8f64) {
3770 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
3771 static const MCPhysReg RegList8[] = {
3772 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3773 };
3774 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
3775 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3776 return false;
3777 }
3778 }
3779 }
3780
3781 return true; // CC didn't match.
3782}
3783
3784
3785static bool RetCC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
3786 MVT LocVT, CCValAssign::LocInfo LocInfo,
3787 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3788
3789 if (LocVT == MVT::i1 ||
3790 LocVT == MVT::v1i1 ||
3791 LocVT == MVT::v8i1) {
3792 LocVT = MVT::i8;
3793 if (ArgFlags.isSExt())
3794 LocInfo = CCValAssign::SExt;
3795 else if (ArgFlags.isZExt())
3796 LocInfo = CCValAssign::ZExt;
3797 else
3798 LocInfo = CCValAssign::AExt;
3799 }
3800
3801 if (LocVT == MVT::v16i1) {
3802 LocVT = MVT::i16;
3803 if (ArgFlags.isSExt())
3804 LocInfo = CCValAssign::SExt;
3805 else if (ArgFlags.isZExt())
3806 LocInfo = CCValAssign::ZExt;
3807 else
3808 LocInfo = CCValAssign::AExt;
3809 }
3810
3811 if (LocVT == MVT::v32i1) {
3812 LocVT = MVT::i32;
3813 if (ArgFlags.isSExt())
3814 LocInfo = CCValAssign::SExt;
3815 else if (ArgFlags.isZExt())
3816 LocInfo = CCValAssign::ZExt;
3817 else
3818 LocInfo = CCValAssign::AExt;
3819 }
3820
3821 if (LocVT == MVT::i8) {
3822 static const MCPhysReg RegList1[] = {
3823 X86::CL, X86::DL, X86::DIL, X86::SIL
3824 };
3825 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3826 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3827 return false;
3828 }
3829 }
3830
3831 if (LocVT == MVT::i16) {
3832 static const MCPhysReg RegList2[] = {
3833 X86::CX, X86::DX, X86::DI, X86::SI
3834 };
3835 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3836 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3837 return false;
3838 }
3839 }
3840
3841 if (LocVT == MVT::i32) {
3842 static const MCPhysReg RegList3[] = {
3843 X86::ECX, X86::EDX, X86::EDI, X86::ESI
3844 };
3845 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3846 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3847 return false;
3848 }
3849 }
3850
3851 if (LocVT == MVT::i64) {
3852 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3853 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3854 return false;
3855 }
3856 }
3857
3858 if (LocVT == MVT::v64i1) {
3859 LocVT = MVT::i64;
3860 if (ArgFlags.isSExt())
3861 LocInfo = CCValAssign::SExt;
3862 else if (ArgFlags.isZExt())
3863 LocInfo = CCValAssign::ZExt;
3864 else
3865 LocInfo = CCValAssign::AExt;
3866 }
3867
3868 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3869 if (LocVT == MVT::i64) {
3870 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3871 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3872 return false;
3873 }
3874 }
3875 }
3876
3877 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
3878 if (LocVT == MVT::i64) {
3879 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3880 return false;
3881 }
3882 }
3883
3884 if (LocVT == MVT::f80) {
3885 static const MCPhysReg RegList4[] = {
3886 X86::FP0, X86::FP1
3887 };
3888 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3889 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3890 return false;
3891 }
3892 }
3893
3894 if (LocVT == MVT::f32 ||
3895 LocVT == MVT::f64 ||
3896 LocVT == MVT::f128) {
3897 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3898 static const MCPhysReg RegList5[] = {
3899 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3900 };
3901 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3902 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3903 return false;
3904 }
3905 }
3906 }
3907
3908 if (LocVT == MVT::v16i8 ||
3909 LocVT == MVT::v8i16 ||
3910 LocVT == MVT::v4i32 ||
3911 LocVT == MVT::v2i64 ||
3912 LocVT == MVT::v4f32 ||
3913 LocVT == MVT::v2f64) {
3914 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3915 static const MCPhysReg RegList6[] = {
3916 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3917 };
3918 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3919 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3920 return false;
3921 }
3922 }
3923 }
3924
3925 if (LocVT == MVT::v32i8 ||
3926 LocVT == MVT::v16i16 ||
3927 LocVT == MVT::v8i32 ||
3928 LocVT == MVT::v4i64 ||
3929 LocVT == MVT::v8f32 ||
3930 LocVT == MVT::v4f64) {
3931 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
3932 static const MCPhysReg RegList7[] = {
3933 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3934 };
3935 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3936 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3937 return false;
3938 }
3939 }
3940 }
3941
3942 if (LocVT == MVT::v64i8 ||
3943 LocVT == MVT::v32i16 ||
3944 LocVT == MVT::v16i32 ||
3945 LocVT == MVT::v8i64 ||
3946 LocVT == MVT::v16f32 ||
3947 LocVT == MVT::v8f64) {
3948 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
3949 static const MCPhysReg RegList8[] = {
3950 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3951 };
3952 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
3953 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3954 return false;
3955 }
3956 }
3957 }
3958
3959 return true; // CC didn't match.
3960}
3961
3962
3963static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
3964 MVT LocVT, CCValAssign::LocInfo LocInfo,
3965 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3966
3967 if (LocVT == MVT::f32 ||
3968 LocVT == MVT::f64 ||
3969 LocVT == MVT::f128) {
3970 static const MCPhysReg RegList1[] = {
3971 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3972 };
3973 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3974 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3975 return false;
3976 }
3977 }
3978
3979 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3980 return false;
3981
3982 return true; // CC didn't match.
3983}
3984
3985
3986static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
3987 MVT LocVT, CCValAssign::LocInfo LocInfo,
3988 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
3989
3990 if (State.getCallingConv() == CallingConv::HiPE) {
3991 if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3992 return false;
3993 }
3994
3995 if (State.getCallingConv() == CallingConv::AnyReg) {
3996 if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
3997 return false;
3998 }
3999
4000 if (State.getCallingConv() == CallingConv::Swift) {
4001 if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4002 return false;
4003 }
4004
4005 if (State.getCallingConv() == CallingConv::SwiftTail) {
4006 if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4007 return false;
4008 }
4009
4010 if (State.getCallingConv() == CallingConv::Win64) {
4011 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4012 return false;
4013 }
4014
4015 if (State.getCallingConv() == CallingConv::X86_64_SysV) {
4016 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4017 return false;
4018 }
4019
4020 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
4021 if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4022 return false;
4023 }
4024
4025 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4026 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
4027 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
4028 if (!RetCC_X86_Win64_RegCallv4(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4029 return false;
4030 }
4031 }
4032 }
4033
4034 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4035 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
4036 if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4037 return false;
4038 }
4039 }
4040
4041 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4042 if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4043 return false;
4044 }
4045
4046 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
4047 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4048 return false;
4049 }
4050
4051 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetUEFI64()) {
4052 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4053 return false;
4054 }
4055
4056 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4057 return false;
4058
4059 return true; // CC didn't match.
4060}
4061
4062
4063static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
4064 MVT LocVT, CCValAssign::LocInfo LocInfo,
4065 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4066
4067 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4068 return false;
4069
4070 return true; // CC didn't match.
4071}
4072
4073
4074static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
4075 MVT LocVT, CCValAssign::LocInfo LocInfo,
4076 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4077
4078 if (LocVT == MVT::f16) {
4079 static const MCPhysReg RegList1[] = {
4080 X86::XMM0, X86::XMM1
4081 };
4082 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4083 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4084 return false;
4085 }
4086 }
4087
4088 if (LocVT == MVT::f32) {
4089 static const MCPhysReg RegList2[] = {
4090 X86::XMM0, X86::XMM1
4091 };
4092 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4093 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4094 return false;
4095 }
4096 }
4097
4098 if (LocVT == MVT::f64) {
4099 static const MCPhysReg RegList3[] = {
4100 X86::XMM0, X86::XMM1
4101 };
4102 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4103 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4104 return false;
4105 }
4106 }
4107
4108 if (LocVT == MVT::f128) {
4109 static const MCPhysReg RegList4[] = {
4110 X86::XMM0, X86::XMM1
4111 };
4112 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4113 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4114 return false;
4115 }
4116 }
4117
4118 if (ArgFlags.isPointer()) {
4119 if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4120 return false;
4121 }
4122
4123 if (ArgFlags.isSwiftError()) {
4124 if (LocVT == MVT::i64) {
4125 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
4126 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4127 return false;
4128 }
4129 }
4130 }
4131
4132 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4133 return false;
4134
4135 return true; // CC didn't match.
4136}
4137
4138
4139static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
4140 MVT LocVT, CCValAssign::LocInfo LocInfo,
4141 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4142
4143 if (LocVT == MVT::i8 ||
4144 LocVT == MVT::i16 ||
4145 LocVT == MVT::i32) {
4146 LocVT = MVT::i64;
4147 if (ArgFlags.isSExt())
4148 LocInfo = CCValAssign::SExt;
4149 else if (ArgFlags.isZExt())
4150 LocInfo = CCValAssign::ZExt;
4151 else
4152 LocInfo = CCValAssign::AExt;
4153 }
4154
4155 if (LocVT == MVT::i64) {
4156 static const MCPhysReg RegList1[] = {
4157 X86::R15, X86::RBP, X86::RAX, X86::RDX
4158 };
4159 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4160 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4161 return false;
4162 }
4163 }
4164
4165 return true; // CC didn't match.
4166}
4167
4168
4169static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
4170 MVT LocVT, CCValAssign::LocInfo LocInfo,
4171 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4172
4173 if (ArgFlags.isSwiftError()) {
4174 if (LocVT == MVT::i64) {
4175 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
4176 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4177 return false;
4178 }
4179 }
4180 }
4181
4182 if (LocVT == MVT::v1i1) {
4183 LocVT = MVT::i8;
4184 if (ArgFlags.isSExt())
4185 LocInfo = CCValAssign::SExt;
4186 else if (ArgFlags.isZExt())
4187 LocInfo = CCValAssign::ZExt;
4188 else
4189 LocInfo = CCValAssign::AExt;
4190 }
4191
4192 if (LocVT == MVT::i1) {
4193 LocVT = MVT::i8;
4194 if (ArgFlags.isSExt())
4195 LocInfo = CCValAssign::SExt;
4196 else if (ArgFlags.isZExt())
4197 LocInfo = CCValAssign::ZExt;
4198 else
4199 LocInfo = CCValAssign::AExt;
4200 }
4201
4202 if (LocVT == MVT::i8) {
4203 static const MCPhysReg RegList1[] = {
4204 X86::AL, X86::DL, X86::CL, X86::R8B
4205 };
4206 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4207 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4208 return false;
4209 }
4210 }
4211
4212 if (LocVT == MVT::i16) {
4213 static const MCPhysReg RegList2[] = {
4214 X86::AX, X86::DX, X86::CX, X86::R8W
4215 };
4216 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4217 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4218 return false;
4219 }
4220 }
4221
4222 if (LocVT == MVT::i32) {
4223 static const MCPhysReg RegList3[] = {
4224 X86::EAX, X86::EDX, X86::ECX, X86::R8D
4225 };
4226 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4227 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4228 return false;
4229 }
4230 }
4231
4232 if (LocVT == MVT::i64) {
4233 static const MCPhysReg RegList4[] = {
4234 X86::RAX, X86::RDX, X86::RCX, X86::R8
4235 };
4236 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4237 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4238 return false;
4239 }
4240 }
4241
4242 if (LocVT == MVT::f32) {
4243 static const MCPhysReg RegList5[] = {
4244 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4245 };
4246 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4247 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4248 return false;
4249 }
4250 }
4251
4252 if (LocVT == MVT::f64) {
4253 static const MCPhysReg RegList6[] = {
4254 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4255 };
4256 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4257 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4258 return false;
4259 }
4260 }
4261
4262 if (LocVT == MVT::f128) {
4263 static const MCPhysReg RegList7[] = {
4264 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4265 };
4266 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4267 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4268 return false;
4269 }
4270 }
4271
4272 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4273 return false;
4274
4275 return true; // CC didn't match.
4276}
4277
4278
4279static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
4280 MVT LocVT, CCValAssign::LocInfo LocInfo,
4281 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4282
4283 if (LocVT == MVT::f32 ||
4284 LocVT == MVT::f64 ||
4285 LocVT == MVT::f128) {
4286 static const MCPhysReg RegList1[] = {
4287 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4288 };
4289 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4290 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4291 return false;
4292 }
4293 }
4294
4295 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4296 return false;
4297
4298 return true; // CC didn't match.
4299}
4300
4301
4302static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
4303 MVT LocVT, CCValAssign::LocInfo LocInfo,
4304 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4305
4306 if (LocVT == MVT::i1 ||
4307 LocVT == MVT::v1i1 ||
4308 LocVT == MVT::v8i1) {
4309 LocVT = MVT::i8;
4310 if (ArgFlags.isSExt())
4311 LocInfo = CCValAssign::SExt;
4312 else if (ArgFlags.isZExt())
4313 LocInfo = CCValAssign::ZExt;
4314 else
4315 LocInfo = CCValAssign::AExt;
4316 }
4317
4318 if (LocVT == MVT::v16i1) {
4319 LocVT = MVT::i16;
4320 if (ArgFlags.isSExt())
4321 LocInfo = CCValAssign::SExt;
4322 else if (ArgFlags.isZExt())
4323 LocInfo = CCValAssign::ZExt;
4324 else
4325 LocInfo = CCValAssign::AExt;
4326 }
4327
4328 if (LocVT == MVT::v32i1) {
4329 LocVT = MVT::i32;
4330 if (ArgFlags.isSExt())
4331 LocInfo = CCValAssign::SExt;
4332 else if (ArgFlags.isZExt())
4333 LocInfo = CCValAssign::ZExt;
4334 else
4335 LocInfo = CCValAssign::AExt;
4336 }
4337
4338 if (LocVT == MVT::i8) {
4339 static const MCPhysReg RegList1[] = {
4340 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B
4341 };
4342 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4343 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4344 return false;
4345 }
4346 }
4347
4348 if (LocVT == MVT::i16) {
4349 static const MCPhysReg RegList2[] = {
4350 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W
4351 };
4352 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4353 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4354 return false;
4355 }
4356 }
4357
4358 if (LocVT == MVT::i32) {
4359 static const MCPhysReg RegList3[] = {
4360 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
4361 };
4362 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4363 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4364 return false;
4365 }
4366 }
4367
4368 if (LocVT == MVT::i64) {
4369 static const MCPhysReg RegList4[] = {
4370 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
4371 };
4372 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4373 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4374 return false;
4375 }
4376 }
4377
4378 if (LocVT == MVT::v64i1) {
4379 LocVT = MVT::i64;
4380 if (ArgFlags.isSExt())
4381 LocInfo = CCValAssign::SExt;
4382 else if (ArgFlags.isZExt())
4383 LocInfo = CCValAssign::ZExt;
4384 else
4385 LocInfo = CCValAssign::AExt;
4386 }
4387
4388 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
4389 if (LocVT == MVT::i64) {
4390 static const MCPhysReg RegList5[] = {
4391 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
4392 };
4393 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4394 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4395 return false;
4396 }
4397 }
4398 }
4399
4400 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
4401 if (LocVT == MVT::i64) {
4402 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4403 return false;
4404 }
4405 }
4406
4407 if (LocVT == MVT::f80) {
4408 static const MCPhysReg RegList6[] = {
4409 X86::FP0, X86::FP1
4410 };
4411 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4412 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4413 return false;
4414 }
4415 }
4416
4417 if (LocVT == MVT::f32 ||
4418 LocVT == MVT::f64 ||
4419 LocVT == MVT::f128) {
4420 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4421 static const MCPhysReg RegList7[] = {
4422 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4423 };
4424 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4425 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4426 return false;
4427 }
4428 }
4429 }
4430
4431 if (LocVT == MVT::v16i8 ||
4432 LocVT == MVT::v8i16 ||
4433 LocVT == MVT::v4i32 ||
4434 LocVT == MVT::v2i64 ||
4435 LocVT == MVT::v4f32 ||
4436 LocVT == MVT::v2f64) {
4437 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4438 static const MCPhysReg RegList8[] = {
4439 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4440 };
4441 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
4442 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4443 return false;
4444 }
4445 }
4446 }
4447
4448 if (LocVT == MVT::v32i8 ||
4449 LocVT == MVT::v16i16 ||
4450 LocVT == MVT::v8i32 ||
4451 LocVT == MVT::v4i64 ||
4452 LocVT == MVT::v8f32 ||
4453 LocVT == MVT::v4f64) {
4454 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
4455 static const MCPhysReg RegList9[] = {
4456 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4457 };
4458 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
4459 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4460 return false;
4461 }
4462 }
4463 }
4464
4465 if (LocVT == MVT::v64i8 ||
4466 LocVT == MVT::v32i16 ||
4467 LocVT == MVT::v16i32 ||
4468 LocVT == MVT::v8i64 ||
4469 LocVT == MVT::v16f32 ||
4470 LocVT == MVT::v8f64) {
4471 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
4472 static const MCPhysReg RegList10[] = {
4473 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4474 };
4475 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
4476 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4477 return false;
4478 }
4479 }
4480 }
4481
4482 return true; // CC didn't match.
4483}
4484
4485
4486static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
4487 MVT LocVT, CCValAssign::LocInfo LocInfo,
4488 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4489
4490 if (LocVT == MVT::f32) {
4491 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4492 LocVT = MVT::i32;
4493 LocInfo = CCValAssign::BCvt;
4494 }
4495 }
4496
4497 if (LocVT == MVT::f64) {
4498 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4499 LocVT = MVT::i64;
4500 LocInfo = CCValAssign::BCvt;
4501 }
4502 }
4503
4504 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
4505 return false;
4506
4507 return true; // CC didn't match.
4508}
4509
4510
4511static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
4512 MVT LocVT, CCValAssign::LocInfo LocInfo,
4513 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4514
4515 if (LocVT == MVT::i1 ||
4516 LocVT == MVT::v1i1 ||
4517 LocVT == MVT::v8i1) {
4518 LocVT = MVT::i8;
4519 if (ArgFlags.isSExt())
4520 LocInfo = CCValAssign::SExt;
4521 else if (ArgFlags.isZExt())
4522 LocInfo = CCValAssign::ZExt;
4523 else
4524 LocInfo = CCValAssign::AExt;
4525 }
4526
4527 if (LocVT == MVT::v16i1) {
4528 LocVT = MVT::i16;
4529 if (ArgFlags.isSExt())
4530 LocInfo = CCValAssign::SExt;
4531 else if (ArgFlags.isZExt())
4532 LocInfo = CCValAssign::ZExt;
4533 else
4534 LocInfo = CCValAssign::AExt;
4535 }
4536
4537 if (LocVT == MVT::v32i1) {
4538 LocVT = MVT::i32;
4539 if (ArgFlags.isSExt())
4540 LocInfo = CCValAssign::SExt;
4541 else if (ArgFlags.isZExt())
4542 LocInfo = CCValAssign::ZExt;
4543 else
4544 LocInfo = CCValAssign::AExt;
4545 }
4546
4547 if (LocVT == MVT::i8) {
4548 static const MCPhysReg RegList1[] = {
4549 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
4550 };
4551 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4552 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4553 return false;
4554 }
4555 }
4556
4557 if (LocVT == MVT::i16) {
4558 static const MCPhysReg RegList2[] = {
4559 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
4560 };
4561 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4562 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4563 return false;
4564 }
4565 }
4566
4567 if (LocVT == MVT::i32) {
4568 static const MCPhysReg RegList3[] = {
4569 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
4570 };
4571 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4572 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4573 return false;
4574 }
4575 }
4576
4577 if (LocVT == MVT::i64) {
4578 static const MCPhysReg RegList4[] = {
4579 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
4580 };
4581 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4582 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4583 return false;
4584 }
4585 }
4586
4587 if (LocVT == MVT::v64i1) {
4588 LocVT = MVT::i64;
4589 if (ArgFlags.isSExt())
4590 LocInfo = CCValAssign::SExt;
4591 else if (ArgFlags.isZExt())
4592 LocInfo = CCValAssign::ZExt;
4593 else
4594 LocInfo = CCValAssign::AExt;
4595 }
4596
4597 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
4598 if (LocVT == MVT::i64) {
4599 static const MCPhysReg RegList5[] = {
4600 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
4601 };
4602 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4603 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4604 return false;
4605 }
4606 }
4607 }
4608
4609 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
4610 if (LocVT == MVT::i64) {
4611 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4612 return false;
4613 }
4614 }
4615
4616 if (LocVT == MVT::f80) {
4617 static const MCPhysReg RegList6[] = {
4618 X86::FP0, X86::FP1
4619 };
4620 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4621 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4622 return false;
4623 }
4624 }
4625
4626 if (LocVT == MVT::f32 ||
4627 LocVT == MVT::f64 ||
4628 LocVT == MVT::f128) {
4629 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4630 static const MCPhysReg RegList7[] = {
4631 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4632 };
4633 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4634 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4635 return false;
4636 }
4637 }
4638 }
4639
4640 if (LocVT == MVT::v16i8 ||
4641 LocVT == MVT::v8i16 ||
4642 LocVT == MVT::v4i32 ||
4643 LocVT == MVT::v2i64 ||
4644 LocVT == MVT::v4f32 ||
4645 LocVT == MVT::v2f64) {
4646 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4647 static const MCPhysReg RegList8[] = {
4648 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4649 };
4650 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
4651 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4652 return false;
4653 }
4654 }
4655 }
4656
4657 if (LocVT == MVT::v32i8 ||
4658 LocVT == MVT::v16i16 ||
4659 LocVT == MVT::v8i32 ||
4660 LocVT == MVT::v4i64 ||
4661 LocVT == MVT::v8f32 ||
4662 LocVT == MVT::v4f64) {
4663 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
4664 static const MCPhysReg RegList9[] = {
4665 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4666 };
4667 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
4668 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4669 return false;
4670 }
4671 }
4672 }
4673
4674 if (LocVT == MVT::v64i8 ||
4675 LocVT == MVT::v32i16 ||
4676 LocVT == MVT::v16i32 ||
4677 LocVT == MVT::v8i64 ||
4678 LocVT == MVT::v16f32 ||
4679 LocVT == MVT::v8f64) {
4680 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
4681 static const MCPhysReg RegList10[] = {
4682 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4683 };
4684 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
4685 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4686 return false;
4687 }
4688 }
4689 }
4690
4691 return true; // CC didn't match.
4692}
4693
4694
4695static bool RetCC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
4696 MVT LocVT, CCValAssign::LocInfo LocInfo,
4697 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
4698
4699 if (LocVT == MVT::i1 ||
4700 LocVT == MVT::v1i1 ||
4701 LocVT == MVT::v8i1) {
4702 LocVT = MVT::i8;
4703 if (ArgFlags.isSExt())
4704 LocInfo = CCValAssign::SExt;
4705 else if (ArgFlags.isZExt())
4706 LocInfo = CCValAssign::ZExt;
4707 else
4708 LocInfo = CCValAssign::AExt;
4709 }
4710
4711 if (LocVT == MVT::v16i1) {
4712 LocVT = MVT::i16;
4713 if (ArgFlags.isSExt())
4714 LocInfo = CCValAssign::SExt;
4715 else if (ArgFlags.isZExt())
4716 LocInfo = CCValAssign::ZExt;
4717 else
4718 LocInfo = CCValAssign::AExt;
4719 }
4720
4721 if (LocVT == MVT::v32i1) {
4722 LocVT = MVT::i32;
4723 if (ArgFlags.isSExt())
4724 LocInfo = CCValAssign::SExt;
4725 else if (ArgFlags.isZExt())
4726 LocInfo = CCValAssign::ZExt;
4727 else
4728 LocInfo = CCValAssign::AExt;
4729 }
4730
4731 if (LocVT == MVT::i8) {
4732 static const MCPhysReg RegList1[] = {
4733 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
4734 };
4735 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4736 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4737 return false;
4738 }
4739 }
4740
4741 if (LocVT == MVT::i16) {
4742 static const MCPhysReg RegList2[] = {
4743 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
4744 };
4745 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4746 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4747 return false;
4748 }
4749 }
4750
4751 if (LocVT == MVT::i32) {
4752 static const MCPhysReg RegList3[] = {
4753 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
4754 };
4755 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4756 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4757 return false;
4758 }
4759 }
4760
4761 if (LocVT == MVT::i64) {
4762 static const MCPhysReg RegList4[] = {
4763 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
4764 };
4765 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4766 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4767 return false;
4768 }
4769 }
4770
4771 if (LocVT == MVT::v64i1) {
4772 LocVT = MVT::i64;
4773 if (ArgFlags.isSExt())
4774 LocInfo = CCValAssign::SExt;
4775 else if (ArgFlags.isZExt())
4776 LocInfo = CCValAssign::ZExt;
4777 else
4778 LocInfo = CCValAssign::AExt;
4779 }
4780
4781 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
4782 if (LocVT == MVT::i64) {
4783 static const MCPhysReg RegList5[] = {
4784 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
4785 };
4786 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4787 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4788 return false;
4789 }
4790 }
4791 }
4792
4793 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
4794 if (LocVT == MVT::i64) {
4795 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4796 return false;
4797 }
4798 }
4799
4800 if (LocVT == MVT::f80) {
4801 static const MCPhysReg RegList6[] = {
4802 X86::FP0, X86::FP1
4803 };
4804 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4805 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4806 return false;
4807 }
4808 }
4809
4810 if (LocVT == MVT::f32 ||
4811 LocVT == MVT::f64 ||
4812 LocVT == MVT::f128) {
4813 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4814 static const MCPhysReg RegList7[] = {
4815 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4816 };
4817 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4818 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4819 return false;
4820 }
4821 }
4822 }
4823
4824 if (LocVT == MVT::v16i8 ||
4825 LocVT == MVT::v8i16 ||
4826 LocVT == MVT::v4i32 ||
4827 LocVT == MVT::v2i64 ||
4828 LocVT == MVT::v4f32 ||
4829 LocVT == MVT::v2f64) {
4830 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4831 static const MCPhysReg RegList8[] = {
4832 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4833 };
4834 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
4835 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4836 return false;
4837 }
4838 }
4839 }
4840
4841 if (LocVT == MVT::v32i8 ||
4842 LocVT == MVT::v16i16 ||
4843 LocVT == MVT::v8i32 ||
4844 LocVT == MVT::v4i64 ||
4845 LocVT == MVT::v8f32 ||
4846 LocVT == MVT::v4f64) {
4847 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
4848 static const MCPhysReg RegList9[] = {
4849 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4850 };
4851 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
4852 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4853 return false;
4854 }
4855 }
4856 }
4857
4858 if (LocVT == MVT::v64i8 ||
4859 LocVT == MVT::v32i16 ||
4860 LocVT == MVT::v16i32 ||
4861 LocVT == MVT::v8i64 ||
4862 LocVT == MVT::v16f32 ||
4863 LocVT == MVT::v8f64) {
4864 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
4865 static const MCPhysReg RegList10[] = {
4866 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4867 };
4868 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
4869 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4870 return false;
4871 }
4872 }
4873 }
4874
4875 return true; // CC didn't match.
4876}
4877
4878#else
4879
4880const MCRegister CC_Intel_OCL_BI_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::K1, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4881const MCRegister CC_X86_ArgRegs[] = { 0 };
4882const MCRegister CC_X86_32_ArgRegs[] = { 0 };
4883const MCRegister CC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX };
4884const MCRegister CC_X86_32_Common_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2 };
4885const MCRegister CC_X86_32_FastCC_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 };
4886const MCRegister CC_X86_32_FastCall_ArgRegs[] = { X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX };
4887const MCRegister CC_X86_32_GHC_ArgRegs[] = { X86::EBP, X86::EBX, X86::EDI, X86::ESI };
4888const MCRegister CC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::ECX, X86::EDX, X86::ESI };
4889const MCRegister CC_X86_32_MCU_ArgRegs[] = { 0 };
4890const MCRegister CC_X86_32_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::RAX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4891const MCRegister CC_X86_32_RegCallv4_Win_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::RAX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4892const MCRegister CC_X86_32_ThisCall_ArgRegs[] = { 0 };
4893const MCRegister CC_X86_32_ThisCall_Common_ArgRegs[] = { X86::ECX };
4894const MCRegister CC_X86_32_ThisCall_Mingw_ArgRegs[] = { 0 };
4895const MCRegister CC_X86_32_ThisCall_Win_ArgRegs[] = { 0 };
4896const MCRegister CC_X86_32_Vector_Common_ArgRegs[] = { 0 };
4897const MCRegister CC_X86_32_Vector_Darwin_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4898const MCRegister CC_X86_32_Vector_Standard_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::YMM0, X86::YMM1, X86::YMM2, X86::ZMM0, X86::ZMM1, X86::ZMM2 };
4899const MCRegister CC_X86_64_ArgRegs[] = { 0 };
4900const MCRegister CC_X86_64_AnyReg_ArgRegs[] = { 0 };
4901const MCRegister CC_X86_64_C_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::R10, X86::R10D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4902const MCRegister CC_X86_64_GHC_ArgRegs[] = { X86::R12, X86::R13, X86::R14, X86::R15, X86::R8, X86::R9, X86::RBP, X86::RBX, X86::RDI, X86::RSI, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6 };
4903const MCRegister CC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::R8, X86::RBP, X86::RCX, X86::RDX, X86::RSI };
4904const MCRegister CC_X86_64_Preserve_None_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R13, X86::R13D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI };
4905const MCRegister CC_X86_SysV64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R12, X86::R12D, X86::R13, X86::R13D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4906const MCRegister CC_X86_Win32_CFGuard_Check_ArgRegs[] = { X86::ECX };
4907const MCRegister CC_X86_Win32_Vector_ArgRegs[] = { 0 };
4908const MCRegister CC_X86_Win32_VectorCall_ArgRegs[] = { 0 };
4909const MCRegister CC_X86_Win64_C_ArgRegs[] = { X86::R10, X86::RAX };
4910const MCRegister CC_X86_Win64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R10, X86::R10D, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4911const MCRegister CC_X86_Win64_RegCallv4_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4912const MCRegister CC_X86_Win64_VectorCall_ArgRegs[] = { 0 };
4913const MCRegister RetCC_Intel_OCL_BI_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4914const MCRegister RetCC_X86_ArgRegs[] = { 0 };
4915const MCRegister RetCC_X86Common_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4916const MCRegister RetCC_X86_32_ArgRegs[] = { 0 };
4917const MCRegister RetCC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::XMM0, X86::XMM1, X86::XMM2 };
4918const MCRegister RetCC_X86_32_Fast_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 };
4919const MCRegister RetCC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::EDX, X86::ESI };
4920const MCRegister RetCC_X86_32_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::RAX, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4921const MCRegister RetCC_X86_32_RegCallv4_Win_ArgRegs[] = { X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::RAX, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4922const MCRegister RetCC_X86_32_VectorCall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4923const MCRegister RetCC_X86_64_ArgRegs[] = { 0 };
4924const MCRegister RetCC_X86_64_AnyReg_ArgRegs[] = { 0 };
4925const MCRegister RetCC_X86_64_C_ArgRegs[] = { X86::XMM0, X86::XMM1 };
4926const MCRegister RetCC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::RAX, X86::RBP, X86::RDX };
4927const MCRegister RetCC_X86_64_Swift_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4928const MCRegister RetCC_X86_64_Vectorcall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4929const MCRegister RetCC_X86_SysV64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R13, X86::R13B, X86::R13D, X86::R13W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4930const MCRegister RetCC_X86_Win64_C_ArgRegs[] = { 0 };
4931const MCRegister RetCC_X86_Win64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R10, X86::R10B, X86::R10D, X86::R10W, X86::R11, X86::R11B, X86::R11D, X86::R11W, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4932const MCRegister RetCC_X86_Win64_RegCallv4_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R11, X86::R11B, X86::R11D, X86::R11W, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4933
4934// Registers used by Swift.
4935const MCRegister CC_X86_64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 };
4936const MCRegister CC_X86_Win64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 };
4937const MCRegister RetCC_X86_64_C_Swift_ArgRegs[] = { X86::R12 };
4938const MCRegister RetCC_X86_64_Swift_Swift_ArgRegs[] = { X86::R12 };
4939
4940#endif // !defined(GET_CC_REGISTER_LISTS)
4941
4942