1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t X86RegDiffLists[] = {
12 /* 0 */ -56, -56, 0,
13 /* 3 */ -32, -48, 0,
14 /* 6 */ 32, -16, -48, 0,
15 /* 10 */ 48, -16, -48, 0,
16 /* 14 */ 16, -8, -48, 0,
17 /* 18 */ 24, -8, -48, 0,
18 /* 22 */ -28, 32, 2, -1, -18, 0,
19 /* 28 */ -32, -16, 0,
20 /* 31 */ -28, 30, 2, -1, -16, 0,
21 /* 37 */ -2, -4, 0,
22 /* 40 */ -29, 20, -3, 0,
23 /* 44 */ -4, -1, 0,
24 /* 47 */ -2, -1, 0,
25 /* 50 */ -1, -1, 0,
26 /* 53 */ 2, -1, 0,
27 /* 56 */ -72, 1, 0,
28 /* 59 */ -71, 1, 0,
29 /* 62 */ -70, 1, 0,
30 /* 65 */ -69, 1, 0,
31 /* 68 */ 1, 1, 0,
32 /* 71 */ 3, 0,
33 /* 73 */ 1, 7, 0,
34 /* 76 */ 3, 7, 0,
35 /* 79 */ -24, 8, 0,
36 /* 82 */ 1, 11, 0,
37 /* 85 */ 1, 14, 0,
38 /* 88 */ -48, 16, 0,
39 /* 91 */ 48, 8, -24, 8, 24, 0,
40 /* 97 */ -29, -10, 2, -1, 27, 0,
41 /* 103 */ -2, -32, 28, 0,
42 /* 107 */ -1, -32, 28, 0,
43 /* 111 */ -2, -30, 28, 0,
44 /* 115 */ -1, -30, 28, 0,
45 /* 119 */ -15, 28, 0,
46 /* 122 */ -20, 29, 0,
47 /* 125 */ -18, 29, 0,
48 /* 128 */ -17, 29, 0,
49 /* 131 */ 2, 6, 29, 0,
50 /* 135 */ 6, 6, 29, 0,
51 /* 139 */ -2, 10, 29, 0,
52 /* 143 */ -1, 10, 29, 0,
53 /* 147 */ 2, 12, 29, 0,
54 /* 151 */ 3, 12, 29, 0,
55 /* 155 */ 4, 15, 29, 0,
56 /* 159 */ 5, 15, 29, 0,
57 /* 163 */ -2, 17, 29, 0,
58 /* 167 */ -1, 17, 29, 0,
59 /* 171 */ 1, 19, 29, 0,
60 /* 175 */ 2, 19, 29, 0,
61 /* 179 */ -29, -6, -2, -4, 30, 0,
62 /* 185 */ 16, 32, 0,
63 /* 188 */ -29, -12, -2, -1, 33, 0,
64 /* 194 */ -29, -17, 2, -1, 34, 0,
65 /* 200 */ -29, -15, -4, -1, 38, 0,
66 /* 206 */ -29, -19, -1, -1, 39, 0,
67 /* 212 */ 48, 16, -48, 16, 48, 0,
68 /* 218 */ 56, 56, 0,
69 /* 221 */ 68, 0,
70 /* 223 */ 69, 0,
71 /* 225 */ 70, 0,
72 /* 227 */ 71, 0,
73 /* 229 */ 72, 0,
74};
75
76extern const LaneBitmask X86LaneMaskLists[] = {
77 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
78 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004),
79 /* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000008),
80 /* 7 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
81 /* 10 */ LaneBitmask(0x0000000000000007), LaneBitmask(0x0000000000000008),
82 /* 12 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020),
83 /* 14 */ LaneBitmask(0x0000000000000040),
84 /* 15 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
85};
86
87extern const uint16_t X86SubRegIdxLists[] = {
88 /* 0 */ 1, 2,
89 /* 2 */ 1, 3,
90 /* 4 */ 6, 4, 1, 2, 5,
91 /* 9 */ 6, 4, 1, 3, 5,
92 /* 14 */ 6, 4, 5,
93 /* 17 */ 7, 8,
94 /* 19 */ 10, 9,
95};
96
97
98#ifdef __GNUC__
99#pragma GCC diagnostic push
100#pragma GCC diagnostic ignored "-Woverlength-strings"
101#endif
102extern const char X86RegStrings[] = {
103 /* 0 */ "XMM10\000"
104 /* 6 */ "YMM10\000"
105 /* 12 */ "ZMM10\000"
106 /* 18 */ "CR10\000"
107 /* 23 */ "DR10\000"
108 /* 28 */ "XMM20\000"
109 /* 34 */ "YMM20\000"
110 /* 40 */ "ZMM20\000"
111 /* 46 */ "R20\000"
112 /* 50 */ "XMM30\000"
113 /* 56 */ "YMM30\000"
114 /* 62 */ "ZMM30\000"
115 /* 68 */ "R30\000"
116 /* 72 */ "K0\000"
117 /* 75 */ "TMM0\000"
118 /* 80 */ "XMM0\000"
119 /* 85 */ "YMM0\000"
120 /* 90 */ "ZMM0\000"
121 /* 95 */ "FP0\000"
122 /* 99 */ "CR0\000"
123 /* 103 */ "DR0\000"
124 /* 107 */ "ST0\000"
125 /* 111 */ "XMM11\000"
126 /* 117 */ "YMM11\000"
127 /* 123 */ "ZMM11\000"
128 /* 129 */ "CR11\000"
129 /* 134 */ "DR11\000"
130 /* 139 */ "XMM21\000"
131 /* 145 */ "YMM21\000"
132 /* 151 */ "ZMM21\000"
133 /* 157 */ "R21\000"
134 /* 161 */ "XMM31\000"
135 /* 167 */ "YMM31\000"
136 /* 173 */ "ZMM31\000"
137 /* 179 */ "R31\000"
138 /* 183 */ "K0_K1\000"
139 /* 189 */ "TMM1\000"
140 /* 194 */ "XMM1\000"
141 /* 199 */ "YMM1\000"
142 /* 204 */ "ZMM1\000"
143 /* 209 */ "FP1\000"
144 /* 213 */ "CR1\000"
145 /* 217 */ "DR1\000"
146 /* 221 */ "ST1\000"
147 /* 225 */ "XMM12\000"
148 /* 231 */ "YMM12\000"
149 /* 237 */ "ZMM12\000"
150 /* 243 */ "CR12\000"
151 /* 248 */ "DR12\000"
152 /* 253 */ "XMM22\000"
153 /* 259 */ "YMM22\000"
154 /* 265 */ "ZMM22\000"
155 /* 271 */ "R22\000"
156 /* 275 */ "K2\000"
157 /* 278 */ "TMM2\000"
158 /* 283 */ "XMM2\000"
159 /* 288 */ "YMM2\000"
160 /* 293 */ "ZMM2\000"
161 /* 298 */ "FP2\000"
162 /* 302 */ "CR2\000"
163 /* 306 */ "DR2\000"
164 /* 310 */ "ST2\000"
165 /* 314 */ "XMM13\000"
166 /* 320 */ "YMM13\000"
167 /* 326 */ "ZMM13\000"
168 /* 332 */ "CR13\000"
169 /* 337 */ "DR13\000"
170 /* 342 */ "XMM23\000"
171 /* 348 */ "YMM23\000"
172 /* 354 */ "ZMM23\000"
173 /* 360 */ "R23\000"
174 /* 364 */ "K2_K3\000"
175 /* 370 */ "TMM3\000"
176 /* 375 */ "XMM3\000"
177 /* 380 */ "YMM3\000"
178 /* 385 */ "ZMM3\000"
179 /* 390 */ "FP3\000"
180 /* 394 */ "CR3\000"
181 /* 398 */ "DR3\000"
182 /* 402 */ "ST3\000"
183 /* 406 */ "XMM14\000"
184 /* 412 */ "YMM14\000"
185 /* 418 */ "ZMM14\000"
186 /* 424 */ "CR14\000"
187 /* 429 */ "DR14\000"
188 /* 434 */ "XMM24\000"
189 /* 440 */ "YMM24\000"
190 /* 446 */ "ZMM24\000"
191 /* 452 */ "R24\000"
192 /* 456 */ "K4\000"
193 /* 459 */ "TMM4\000"
194 /* 464 */ "XMM4\000"
195 /* 469 */ "YMM4\000"
196 /* 474 */ "ZMM4\000"
197 /* 479 */ "FP4\000"
198 /* 483 */ "CR4\000"
199 /* 487 */ "DR4\000"
200 /* 491 */ "ST4\000"
201 /* 495 */ "XMM15\000"
202 /* 501 */ "YMM15\000"
203 /* 507 */ "ZMM15\000"
204 /* 513 */ "CR15\000"
205 /* 518 */ "DR15\000"
206 /* 523 */ "XMM25\000"
207 /* 529 */ "YMM25\000"
208 /* 535 */ "ZMM25\000"
209 /* 541 */ "R25\000"
210 /* 545 */ "K4_K5\000"
211 /* 551 */ "TMM5\000"
212 /* 556 */ "XMM5\000"
213 /* 561 */ "YMM5\000"
214 /* 566 */ "ZMM5\000"
215 /* 571 */ "FP5\000"
216 /* 575 */ "CR5\000"
217 /* 579 */ "DR5\000"
218 /* 583 */ "ST5\000"
219 /* 587 */ "XMM16\000"
220 /* 593 */ "YMM16\000"
221 /* 599 */ "ZMM16\000"
222 /* 605 */ "R16\000"
223 /* 609 */ "XMM26\000"
224 /* 615 */ "YMM26\000"
225 /* 621 */ "ZMM26\000"
226 /* 627 */ "R26\000"
227 /* 631 */ "K6\000"
228 /* 634 */ "TMM6\000"
229 /* 639 */ "XMM6\000"
230 /* 644 */ "YMM6\000"
231 /* 649 */ "ZMM6\000"
232 /* 654 */ "FP6\000"
233 /* 658 */ "CR6\000"
234 /* 662 */ "DR6\000"
235 /* 666 */ "ST6\000"
236 /* 670 */ "XMM17\000"
237 /* 676 */ "YMM17\000"
238 /* 682 */ "ZMM17\000"
239 /* 688 */ "R17\000"
240 /* 692 */ "XMM27\000"
241 /* 698 */ "YMM27\000"
242 /* 704 */ "ZMM27\000"
243 /* 710 */ "R27\000"
244 /* 714 */ "K6_K7\000"
245 /* 720 */ "TMM7\000"
246 /* 725 */ "XMM7\000"
247 /* 730 */ "YMM7\000"
248 /* 735 */ "ZMM7\000"
249 /* 740 */ "FP7\000"
250 /* 744 */ "CR7\000"
251 /* 748 */ "DR7\000"
252 /* 752 */ "ST7\000"
253 /* 756 */ "XMM18\000"
254 /* 762 */ "YMM18\000"
255 /* 768 */ "ZMM18\000"
256 /* 774 */ "R18\000"
257 /* 778 */ "XMM28\000"
258 /* 784 */ "YMM28\000"
259 /* 790 */ "ZMM28\000"
260 /* 796 */ "R28\000"
261 /* 800 */ "XMM8\000"
262 /* 805 */ "YMM8\000"
263 /* 810 */ "ZMM8\000"
264 /* 815 */ "CR8\000"
265 /* 819 */ "DR8\000"
266 /* 823 */ "XMM19\000"
267 /* 829 */ "YMM19\000"
268 /* 835 */ "ZMM19\000"
269 /* 841 */ "R19\000"
270 /* 845 */ "XMM29\000"
271 /* 851 */ "YMM29\000"
272 /* 857 */ "ZMM29\000"
273 /* 863 */ "R29\000"
274 /* 867 */ "XMM9\000"
275 /* 872 */ "YMM9\000"
276 /* 877 */ "ZMM9\000"
277 /* 882 */ "CR9\000"
278 /* 886 */ "DR9\000"
279 /* 890 */ "R10B\000"
280 /* 895 */ "R20B\000"
281 /* 900 */ "R30B\000"
282 /* 905 */ "R11B\000"
283 /* 910 */ "R21B\000"
284 /* 915 */ "R31B\000"
285 /* 920 */ "R12B\000"
286 /* 925 */ "R22B\000"
287 /* 930 */ "R13B\000"
288 /* 935 */ "R23B\000"
289 /* 940 */ "R14B\000"
290 /* 945 */ "R24B\000"
291 /* 950 */ "R15B\000"
292 /* 955 */ "R25B\000"
293 /* 960 */ "R16B\000"
294 /* 965 */ "R26B\000"
295 /* 970 */ "R17B\000"
296 /* 975 */ "R27B\000"
297 /* 980 */ "R18B\000"
298 /* 985 */ "R28B\000"
299 /* 990 */ "R8B\000"
300 /* 994 */ "R19B\000"
301 /* 999 */ "R29B\000"
302 /* 1004 */ "R9B\000"
303 /* 1008 */ "R10D\000"
304 /* 1013 */ "R20D\000"
305 /* 1018 */ "R30D\000"
306 /* 1023 */ "R11D\000"
307 /* 1028 */ "R21D\000"
308 /* 1033 */ "R31D\000"
309 /* 1038 */ "R12D\000"
310 /* 1043 */ "R22D\000"
311 /* 1048 */ "R13D\000"
312 /* 1053 */ "R23D\000"
313 /* 1058 */ "R14D\000"
314 /* 1063 */ "R24D\000"
315 /* 1068 */ "R15D\000"
316 /* 1073 */ "R25D\000"
317 /* 1078 */ "R16D\000"
318 /* 1083 */ "R26D\000"
319 /* 1088 */ "R17D\000"
320 /* 1093 */ "R27D\000"
321 /* 1098 */ "R18D\000"
322 /* 1103 */ "R28D\000"
323 /* 1108 */ "R8D\000"
324 /* 1112 */ "R19D\000"
325 /* 1117 */ "R29D\000"
326 /* 1122 */ "R9D\000"
327 /* 1126 */ "FS_BASE\000"
328 /* 1134 */ "GS_BASE\000"
329 /* 1142 */ "DF\000"
330 /* 1145 */ "TMMCFG\000"
331 /* 1152 */ "AH\000"
332 /* 1155 */ "R10BH\000"
333 /* 1161 */ "R20BH\000"
334 /* 1167 */ "R30BH\000"
335 /* 1173 */ "R11BH\000"
336 /* 1179 */ "R21BH\000"
337 /* 1185 */ "R31BH\000"
338 /* 1191 */ "R12BH\000"
339 /* 1197 */ "R22BH\000"
340 /* 1203 */ "R13BH\000"
341 /* 1209 */ "R23BH\000"
342 /* 1215 */ "R14BH\000"
343 /* 1221 */ "R24BH\000"
344 /* 1227 */ "R15BH\000"
345 /* 1233 */ "R25BH\000"
346 /* 1239 */ "R16BH\000"
347 /* 1245 */ "R26BH\000"
348 /* 1251 */ "R17BH\000"
349 /* 1257 */ "R27BH\000"
350 /* 1263 */ "R18BH\000"
351 /* 1269 */ "R28BH\000"
352 /* 1275 */ "R8BH\000"
353 /* 1280 */ "R19BH\000"
354 /* 1286 */ "R29BH\000"
355 /* 1292 */ "R9BH\000"
356 /* 1297 */ "CH\000"
357 /* 1300 */ "DH\000"
358 /* 1303 */ "DIH\000"
359 /* 1307 */ "SIH\000"
360 /* 1311 */ "BPH\000"
361 /* 1315 */ "SPH\000"
362 /* 1319 */ "R10WH\000"
363 /* 1325 */ "R20WH\000"
364 /* 1331 */ "R30WH\000"
365 /* 1337 */ "R11WH\000"
366 /* 1343 */ "R21WH\000"
367 /* 1349 */ "R31WH\000"
368 /* 1355 */ "R12WH\000"
369 /* 1361 */ "R22WH\000"
370 /* 1367 */ "R13WH\000"
371 /* 1373 */ "R23WH\000"
372 /* 1379 */ "R14WH\000"
373 /* 1385 */ "R24WH\000"
374 /* 1391 */ "R15WH\000"
375 /* 1397 */ "R25WH\000"
376 /* 1403 */ "R16WH\000"
377 /* 1409 */ "R26WH\000"
378 /* 1415 */ "R17WH\000"
379 /* 1421 */ "R27WH\000"
380 /* 1427 */ "R18WH\000"
381 /* 1433 */ "R28WH\000"
382 /* 1439 */ "R8WH\000"
383 /* 1444 */ "R19WH\000"
384 /* 1450 */ "R29WH\000"
385 /* 1456 */ "R9WH\000"
386 /* 1461 */ "EDI\000"
387 /* 1465 */ "HDI\000"
388 /* 1469 */ "RDI\000"
389 /* 1473 */ "ESI\000"
390 /* 1477 */ "HSI\000"
391 /* 1481 */ "RSI\000"
392 /* 1485 */ "AL\000"
393 /* 1488 */ "BL\000"
394 /* 1491 */ "CL\000"
395 /* 1494 */ "DL\000"
396 /* 1497 */ "DIL\000"
397 /* 1501 */ "SIL\000"
398 /* 1505 */ "BPL\000"
399 /* 1509 */ "SPL\000"
400 /* 1513 */ "EBP\000"
401 /* 1517 */ "HBP\000"
402 /* 1521 */ "RBP\000"
403 /* 1525 */ "EIP\000"
404 /* 1529 */ "HIP\000"
405 /* 1533 */ "RIP\000"
406 /* 1537 */ "ESP\000"
407 /* 1541 */ "HSP\000"
408 /* 1545 */ "RSP\000"
409 /* 1549 */ "SSP\000"
410 /* 1553 */ "MXCSR\000"
411 /* 1559 */ "CS\000"
412 /* 1562 */ "DS\000"
413 /* 1565 */ "ES\000"
414 /* 1568 */ "FS\000"
415 /* 1571 */ "_EFLAGS\000"
416 /* 1579 */ "RFLAGS\000"
417 /* 1586 */ "SS\000"
418 /* 1589 */ "R10W\000"
419 /* 1594 */ "R20W\000"
420 /* 1599 */ "R30W\000"
421 /* 1604 */ "R11W\000"
422 /* 1609 */ "R21W\000"
423 /* 1614 */ "R31W\000"
424 /* 1619 */ "R12W\000"
425 /* 1624 */ "R22W\000"
426 /* 1629 */ "R13W\000"
427 /* 1634 */ "R23W\000"
428 /* 1639 */ "R14W\000"
429 /* 1644 */ "R24W\000"
430 /* 1649 */ "R15W\000"
431 /* 1654 */ "R25W\000"
432 /* 1659 */ "R16W\000"
433 /* 1664 */ "R26W\000"
434 /* 1669 */ "R17W\000"
435 /* 1674 */ "R27W\000"
436 /* 1679 */ "R18W\000"
437 /* 1684 */ "R28W\000"
438 /* 1689 */ "R8W\000"
439 /* 1693 */ "R19W\000"
440 /* 1698 */ "R29W\000"
441 /* 1703 */ "R9W\000"
442 /* 1707 */ "FPCW\000"
443 /* 1712 */ "FPSW\000"
444 /* 1717 */ "EAX\000"
445 /* 1721 */ "HAX\000"
446 /* 1725 */ "RAX\000"
447 /* 1729 */ "EBX\000"
448 /* 1733 */ "HBX\000"
449 /* 1737 */ "RBX\000"
450 /* 1741 */ "ECX\000"
451 /* 1745 */ "HCX\000"
452 /* 1749 */ "RCX\000"
453 /* 1753 */ "EDX\000"
454 /* 1757 */ "HDX\000"
455 /* 1761 */ "RDX\000"
456 /* 1765 */ "EIZ\000"
457 /* 1769 */ "RIZ\000"
458};
459#ifdef __GNUC__
460#pragma GCC diagnostic pop
461#endif
462
463extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
464 { .Name: 5, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
465 { .Name: 1152, .SubRegs: 2, .SuperRegs: 175, .SubRegIndices: 2, .RegUnits: 8192, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
466 { .Name: 1485, .SubRegs: 2, .SuperRegs: 171, .SubRegIndices: 2, .RegUnits: 8193, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
467 { .Name: 1718, .SubRegs: 50, .SuperRegs: 172, .SubRegIndices: 0, .RegUnits: 233472, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
468 { .Name: 1158, .SubRegs: 2, .SuperRegs: 159, .SubRegIndices: 2, .RegUnits: 8194, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
469 { .Name: 1488, .SubRegs: 2, .SuperRegs: 155, .SubRegIndices: 2, .RegUnits: 8195, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
470 { .Name: 1514, .SubRegs: 53, .SuperRegs: 164, .SubRegIndices: 2, .RegUnits: 233476, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
471 { .Name: 1311, .SubRegs: 2, .SuperRegs: 167, .SubRegIndices: 2, .RegUnits: 8197, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
472 { .Name: 1505, .SubRegs: 2, .SuperRegs: 163, .SubRegIndices: 2, .RegUnits: 8196, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
473 { .Name: 1730, .SubRegs: 44, .SuperRegs: 156, .SubRegIndices: 0, .RegUnits: 233474, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
474 { .Name: 1297, .SubRegs: 2, .SuperRegs: 151, .SubRegIndices: 2, .RegUnits: 8198, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
475 { .Name: 1491, .SubRegs: 2, .SuperRegs: 147, .SubRegIndices: 2, .RegUnits: 8199, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
476 { .Name: 1559, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8200, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
477 { .Name: 1742, .SubRegs: 47, .SuperRegs: 148, .SubRegIndices: 0, .RegUnits: 233478, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
478 { .Name: 1142, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8201, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
479 { .Name: 1300, .SubRegs: 2, .SuperRegs: 135, .SubRegIndices: 2, .RegUnits: 8202, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
480 { .Name: 1462, .SubRegs: 53, .SuperRegs: 140, .SubRegIndices: 2, .RegUnits: 233483, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
481 { .Name: 1303, .SubRegs: 2, .SuperRegs: 143, .SubRegIndices: 2, .RegUnits: 8204, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
482 { .Name: 1497, .SubRegs: 2, .SuperRegs: 139, .SubRegIndices: 2, .RegUnits: 8203, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
483 { .Name: 1494, .SubRegs: 2, .SuperRegs: 131, .SubRegIndices: 2, .RegUnits: 8205, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
484 { .Name: 1562, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8206, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
485 { .Name: 1754, .SubRegs: 37, .SuperRegs: 132, .SubRegIndices: 0, .RegUnits: 290826, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
486 { .Name: 1717, .SubRegs: 207, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 348160, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
487 { .Name: 1513, .SubRegs: 195, .SuperRegs: 123, .SubRegIndices: 10, .RegUnits: 335876, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
488 { .Name: 1729, .SubRegs: 201, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 348162, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
489 { .Name: 1741, .SubRegs: 189, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 335878, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
490 { .Name: 1461, .SubRegs: 98, .SuperRegs: 123, .SubRegIndices: 10, .RegUnits: 299019, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
491 { .Name: 1753, .SubRegs: 180, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 311306, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
492 { .Name: 1572, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8213, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
493 { .Name: 1525, .SubRegs: 41, .SuperRegs: 123, .SubRegIndices: 15, .RegUnits: 233494, .RegUnitLaneMasks: 10, .IsConstant: 0, .IsArtificial: 0 },
494 { .Name: 1765, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8216, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
495 { .Name: 1565, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8217, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
496 { .Name: 1473, .SubRegs: 32, .SuperRegs: 105, .SubRegIndices: 10, .RegUnits: 278554, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
497 { .Name: 1537, .SubRegs: 23, .SuperRegs: 105, .SubRegIndices: 10, .RegUnits: 278557, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
498 { .Name: 1707, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8224, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
499 { .Name: 1712, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8225, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
500 { .Name: 1568, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8226, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
501 { .Name: 1126, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8227, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
502 { .Name: 1576, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8228, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
503 { .Name: 1134, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8229, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
504 { .Name: 1721, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8207, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
505 { .Name: 1517, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8208, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
506 { .Name: 1733, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8209, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
507 { .Name: 1745, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8210, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
508 { .Name: 1465, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8211, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
509 { .Name: 1757, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8212, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
510 { .Name: 1529, .SubRegs: 2, .SuperRegs: 128, .SubRegIndices: 2, .RegUnits: 8215, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
511 { .Name: 1477, .SubRegs: 2, .SuperRegs: 119, .SubRegIndices: 2, .RegUnits: 8220, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
512 { .Name: 1541, .SubRegs: 2, .SuperRegs: 119, .SubRegIndices: 2, .RegUnits: 8223, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
513 { .Name: 1526, .SubRegs: 2, .SuperRegs: 122, .SubRegIndices: 2, .RegUnits: 8214, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
514 { .Name: 1553, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8230, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
515 { .Name: 1725, .SubRegs: 206, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 348160, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
516 { .Name: 1521, .SubRegs: 194, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 335876, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
517 { .Name: 1737, .SubRegs: 200, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 348162, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
518 { .Name: 1749, .SubRegs: 188, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 335878, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
519 { .Name: 1469, .SubRegs: 97, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 299019, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
520 { .Name: 1761, .SubRegs: 179, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 311306, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
521 { .Name: 1579, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8231, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
522 { .Name: 1533, .SubRegs: 40, .SuperRegs: 2, .SubRegIndices: 14, .RegUnits: 233494, .RegUnitLaneMasks: 10, .IsConstant: 0, .IsArtificial: 0 },
523 { .Name: 1769, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8232, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
524 { .Name: 1481, .SubRegs: 31, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278554, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
525 { .Name: 1545, .SubRegs: 22, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278557, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
526 { .Name: 1474, .SubRegs: 53, .SuperRegs: 112, .SubRegIndices: 2, .RegUnits: 233498, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
527 { .Name: 1307, .SubRegs: 2, .SuperRegs: 115, .SubRegIndices: 2, .RegUnits: 8219, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
528 { .Name: 1501, .SubRegs: 2, .SuperRegs: 111, .SubRegIndices: 2, .RegUnits: 8218, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
529 { .Name: 1538, .SubRegs: 53, .SuperRegs: 104, .SubRegIndices: 2, .RegUnits: 233501, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
530 { .Name: 1315, .SubRegs: 2, .SuperRegs: 107, .SubRegIndices: 2, .RegUnits: 8222, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
531 { .Name: 1509, .SubRegs: 2, .SuperRegs: 103, .SubRegIndices: 2, .RegUnits: 8221, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
532 { .Name: 1586, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8233, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
533 { .Name: 1549, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8234, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
534 { .Name: 1571, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8235, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
535 { .Name: 99, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8236, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
536 { .Name: 213, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8237, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
537 { .Name: 302, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8238, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
538 { .Name: 394, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8239, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
539 { .Name: 483, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8240, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
540 { .Name: 575, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8241, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
541 { .Name: 658, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8242, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
542 { .Name: 744, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8243, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
543 { .Name: 815, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8244, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
544 { .Name: 882, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8245, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
545 { .Name: 18, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8246, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
546 { .Name: 129, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8247, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
547 { .Name: 243, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8248, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
548 { .Name: 332, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8249, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
549 { .Name: 424, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8250, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
550 { .Name: 513, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8251, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
551 { .Name: 103, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8252, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
552 { .Name: 217, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8253, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
553 { .Name: 306, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8254, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
554 { .Name: 398, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8255, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
555 { .Name: 487, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8256, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
556 { .Name: 579, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8257, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
557 { .Name: 662, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8258, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
558 { .Name: 748, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8259, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
559 { .Name: 819, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8260, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
560 { .Name: 886, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8261, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
561 { .Name: 23, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8262, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
562 { .Name: 134, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8263, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
563 { .Name: 248, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8264, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
564 { .Name: 337, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8265, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
565 { .Name: 429, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8266, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
566 { .Name: 518, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8267, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
567 { .Name: 95, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8268, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
568 { .Name: 209, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8269, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
569 { .Name: 298, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8270, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
570 { .Name: 390, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8271, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
571 { .Name: 479, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8272, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
572 { .Name: 571, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8273, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
573 { .Name: 654, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8274, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
574 { .Name: 740, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8275, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
575 { .Name: 76, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8276, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
576 { .Name: 190, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8277, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
577 { .Name: 279, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8278, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
578 { .Name: 371, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8279, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
579 { .Name: 460, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8280, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
580 { .Name: 552, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8281, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
581 { .Name: 635, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8282, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
582 { .Name: 721, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8283, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
583 { .Name: 816, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278620, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
584 { .Name: 883, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278623, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
585 { .Name: 19, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278626, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
586 { .Name: 130, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278629, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
587 { .Name: 244, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278632, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
588 { .Name: 333, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278635, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
589 { .Name: 425, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278638, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
590 { .Name: 514, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278641, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
591 { .Name: 107, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8308, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
592 { .Name: 221, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8309, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
593 { .Name: 310, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8310, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
594 { .Name: 402, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8311, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
595 { .Name: 491, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8312, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
596 { .Name: 583, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8313, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
597 { .Name: 666, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8314, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
598 { .Name: 752, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8315, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
599 { .Name: 80, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8316, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
600 { .Name: 194, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8317, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
601 { .Name: 283, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8318, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
602 { .Name: 375, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8319, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
603 { .Name: 464, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8320, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
604 { .Name: 556, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8321, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
605 { .Name: 639, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8322, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
606 { .Name: 725, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8323, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
607 { .Name: 800, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8324, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
608 { .Name: 867, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8325, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
609 { .Name: 0, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8326, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
610 { .Name: 111, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8327, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
611 { .Name: 225, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8328, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
612 { .Name: 314, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8329, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
613 { .Name: 406, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8330, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
614 { .Name: 495, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8331, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
615 { .Name: 990, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8284, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
616 { .Name: 1004, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8287, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
617 { .Name: 890, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8290, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
618 { .Name: 905, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8293, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
619 { .Name: 920, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8296, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
620 { .Name: 930, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8299, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
621 { .Name: 940, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8302, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
622 { .Name: 950, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8305, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
623 { .Name: 1275, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8285, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
624 { .Name: 1292, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8288, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
625 { .Name: 1155, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8291, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
626 { .Name: 1173, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8294, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
627 { .Name: 1191, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8297, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
628 { .Name: 1203, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8300, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
629 { .Name: 1215, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8303, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
630 { .Name: 1227, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8306, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
631 { .Name: 1108, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278620, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
632 { .Name: 1122, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278623, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
633 { .Name: 1008, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278626, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
634 { .Name: 1023, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278629, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
635 { .Name: 1038, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278632, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
636 { .Name: 1048, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278635, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
637 { .Name: 1058, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278638, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
638 { .Name: 1068, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278641, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
639 { .Name: 1689, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233564, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
640 { .Name: 1703, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233567, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
641 { .Name: 1589, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233570, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
642 { .Name: 1604, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233573, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
643 { .Name: 1619, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233576, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
644 { .Name: 1629, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233579, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
645 { .Name: 1639, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233582, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
646 { .Name: 1649, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233585, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
647 { .Name: 1439, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8286, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
648 { .Name: 1456, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8289, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
649 { .Name: 1319, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8292, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
650 { .Name: 1337, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8295, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
651 { .Name: 1355, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8298, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
652 { .Name: 1367, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8301, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
653 { .Name: 1379, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8304, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
654 { .Name: 1391, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8307, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
655 { .Name: 85, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8316, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
656 { .Name: 199, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8317, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
657 { .Name: 288, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8318, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
658 { .Name: 380, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8319, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
659 { .Name: 469, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8320, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
660 { .Name: 561, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8321, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
661 { .Name: 644, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8322, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
662 { .Name: 730, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8323, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
663 { .Name: 805, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8324, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
664 { .Name: 872, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8325, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
665 { .Name: 6, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8326, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
666 { .Name: 117, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8327, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
667 { .Name: 231, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8328, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
668 { .Name: 320, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8329, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
669 { .Name: 412, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8330, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
670 { .Name: 501, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8331, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
671 { .Name: 72, .SubRegs: 2, .SuperRegs: 229, .SubRegIndices: 2, .RegUnits: 8332, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
672 { .Name: 186, .SubRegs: 2, .SuperRegs: 227, .SubRegIndices: 2, .RegUnits: 8333, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
673 { .Name: 275, .SubRegs: 2, .SuperRegs: 227, .SubRegIndices: 2, .RegUnits: 8334, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
674 { .Name: 367, .SubRegs: 2, .SuperRegs: 225, .SubRegIndices: 2, .RegUnits: 8335, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
675 { .Name: 456, .SubRegs: 2, .SuperRegs: 225, .SubRegIndices: 2, .RegUnits: 8336, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
676 { .Name: 548, .SubRegs: 2, .SuperRegs: 223, .SubRegIndices: 2, .RegUnits: 8337, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
677 { .Name: 631, .SubRegs: 2, .SuperRegs: 223, .SubRegIndices: 2, .RegUnits: 8338, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
678 { .Name: 717, .SubRegs: 2, .SuperRegs: 221, .SubRegIndices: 2, .RegUnits: 8339, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
679 { .Name: 587, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8340, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
680 { .Name: 670, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8341, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
681 { .Name: 756, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8342, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
682 { .Name: 823, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8343, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
683 { .Name: 28, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8344, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
684 { .Name: 139, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8345, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
685 { .Name: 253, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8346, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
686 { .Name: 342, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8347, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
687 { .Name: 434, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8348, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
688 { .Name: 523, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8349, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
689 { .Name: 609, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8350, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
690 { .Name: 692, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8351, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
691 { .Name: 778, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8352, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
692 { .Name: 845, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8353, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
693 { .Name: 50, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8354, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
694 { .Name: 161, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8355, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
695 { .Name: 593, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8340, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
696 { .Name: 676, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8341, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
697 { .Name: 762, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8342, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
698 { .Name: 829, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8343, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
699 { .Name: 34, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8344, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
700 { .Name: 145, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8345, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
701 { .Name: 259, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8346, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
702 { .Name: 348, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8347, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
703 { .Name: 440, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8348, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
704 { .Name: 529, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8349, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
705 { .Name: 615, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8350, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
706 { .Name: 698, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8351, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
707 { .Name: 784, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8352, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
708 { .Name: 851, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8353, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
709 { .Name: 56, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8354, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
710 { .Name: 167, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8355, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
711 { .Name: 90, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8316, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
712 { .Name: 204, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8317, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
713 { .Name: 293, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8318, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
714 { .Name: 385, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8319, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
715 { .Name: 474, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8320, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
716 { .Name: 566, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8321, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
717 { .Name: 649, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8322, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
718 { .Name: 735, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8323, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
719 { .Name: 810, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8324, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
720 { .Name: 877, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8325, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
721 { .Name: 12, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8326, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
722 { .Name: 123, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8327, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
723 { .Name: 237, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8328, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
724 { .Name: 326, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8329, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
725 { .Name: 418, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8330, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
726 { .Name: 507, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8331, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
727 { .Name: 599, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8340, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
728 { .Name: 682, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8341, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
729 { .Name: 768, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8342, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
730 { .Name: 835, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8343, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
731 { .Name: 40, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8344, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
732 { .Name: 151, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8345, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
733 { .Name: 265, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8346, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
734 { .Name: 354, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8347, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
735 { .Name: 446, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8348, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
736 { .Name: 535, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8349, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
737 { .Name: 621, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8350, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
738 { .Name: 704, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8351, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
739 { .Name: 790, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8352, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
740 { .Name: 857, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8353, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
741 { .Name: 62, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8354, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
742 { .Name: 173, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8355, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
743 { .Name: 183, .SubRegs: 56, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233612, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
744 { .Name: 364, .SubRegs: 59, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233614, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
745 { .Name: 545, .SubRegs: 62, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233616, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
746 { .Name: 714, .SubRegs: 65, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233618, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
747 { .Name: 1145, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8356, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
748 { .Name: 75, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8357, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
749 { .Name: 189, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8358, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
750 { .Name: 278, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8359, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
751 { .Name: 370, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8360, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
752 { .Name: 459, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8361, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
753 { .Name: 551, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8362, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
754 { .Name: 634, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8363, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
755 { .Name: 720, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8364, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
756 { .Name: 605, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278701, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
757 { .Name: 688, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278704, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
758 { .Name: 774, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278707, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
759 { .Name: 841, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278710, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
760 { .Name: 46, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278713, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
761 { .Name: 157, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278716, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
762 { .Name: 271, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278719, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
763 { .Name: 360, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278722, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
764 { .Name: 452, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278725, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
765 { .Name: 541, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278728, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
766 { .Name: 627, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278731, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
767 { .Name: 710, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278734, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
768 { .Name: 796, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278737, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
769 { .Name: 863, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278740, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
770 { .Name: 68, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278743, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
771 { .Name: 179, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278746, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
772 { .Name: 960, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8365, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
773 { .Name: 970, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8368, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
774 { .Name: 980, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8371, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
775 { .Name: 994, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8374, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
776 { .Name: 895, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8377, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
777 { .Name: 910, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8380, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
778 { .Name: 925, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8383, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
779 { .Name: 935, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8386, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
780 { .Name: 945, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8389, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
781 { .Name: 955, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8392, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
782 { .Name: 965, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8395, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
783 { .Name: 975, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8398, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
784 { .Name: 985, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8401, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
785 { .Name: 999, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8404, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
786 { .Name: 900, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8407, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
787 { .Name: 915, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8410, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
788 { .Name: 1239, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8366, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
789 { .Name: 1251, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8369, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
790 { .Name: 1263, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8372, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
791 { .Name: 1280, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8375, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
792 { .Name: 1161, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8378, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
793 { .Name: 1179, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8381, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
794 { .Name: 1197, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8384, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
795 { .Name: 1209, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8387, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
796 { .Name: 1221, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8390, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
797 { .Name: 1233, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8393, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
798 { .Name: 1245, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8396, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
799 { .Name: 1257, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8399, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
800 { .Name: 1269, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8402, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
801 { .Name: 1286, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8405, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
802 { .Name: 1167, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8408, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
803 { .Name: 1185, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8411, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
804 { .Name: 1078, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278701, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
805 { .Name: 1088, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278704, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
806 { .Name: 1098, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278707, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
807 { .Name: 1112, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278710, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
808 { .Name: 1013, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278713, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
809 { .Name: 1028, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278716, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
810 { .Name: 1043, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278719, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
811 { .Name: 1053, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278722, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
812 { .Name: 1063, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278725, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
813 { .Name: 1073, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278728, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
814 { .Name: 1083, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278731, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
815 { .Name: 1093, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278734, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
816 { .Name: 1103, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278737, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
817 { .Name: 1117, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278740, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
818 { .Name: 1018, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278743, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
819 { .Name: 1033, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278746, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
820 { .Name: 1659, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233645, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
821 { .Name: 1669, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233648, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
822 { .Name: 1679, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233651, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
823 { .Name: 1693, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233654, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
824 { .Name: 1594, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233657, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
825 { .Name: 1609, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233660, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
826 { .Name: 1624, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233663, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
827 { .Name: 1634, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233666, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
828 { .Name: 1644, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233669, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
829 { .Name: 1654, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233672, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
830 { .Name: 1664, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233675, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
831 { .Name: 1674, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233678, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
832 { .Name: 1684, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233681, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
833 { .Name: 1698, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233684, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
834 { .Name: 1599, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233687, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
835 { .Name: 1614, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233690, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
836 { .Name: 1403, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8367, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
837 { .Name: 1415, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8370, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
838 { .Name: 1427, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8373, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
839 { .Name: 1444, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8376, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
840 { .Name: 1325, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8379, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
841 { .Name: 1343, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8382, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
842 { .Name: 1361, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8385, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
843 { .Name: 1373, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8388, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
844 { .Name: 1385, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8391, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
845 { .Name: 1397, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8394, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
846 { .Name: 1409, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8397, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
847 { .Name: 1421, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8400, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
848 { .Name: 1433, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8403, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
849 { .Name: 1450, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8406, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
850 { .Name: 1331, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8409, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
851 { .Name: 1349, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8412, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
852};
853
854extern const MCPhysReg X86RegUnitRoots[][2] = {
855 { X86::AH },
856 { X86::AL },
857 { X86::BH },
858 { X86::BL },
859 { X86::BPL },
860 { X86::BPH },
861 { X86::CH },
862 { X86::CL },
863 { X86::CS },
864 { X86::DF },
865 { X86::DH },
866 { X86::DIL },
867 { X86::DIH },
868 { X86::DL },
869 { X86::DS },
870 { X86::HAX },
871 { X86::HBP },
872 { X86::HBX },
873 { X86::HCX },
874 { X86::HDI },
875 { X86::HDX },
876 { X86::EFLAGS },
877 { X86::IP },
878 { X86::HIP },
879 { X86::EIZ },
880 { X86::ES },
881 { X86::SIL },
882 { X86::SIH },
883 { X86::HSI },
884 { X86::SPL },
885 { X86::SPH },
886 { X86::HSP },
887 { X86::FPCW },
888 { X86::FPSW },
889 { X86::FS },
890 { X86::FS_BASE },
891 { X86::GS },
892 { X86::GS_BASE },
893 { X86::MXCSR },
894 { X86::RFLAGS },
895 { X86::RIZ },
896 { X86::SS },
897 { X86::SSP },
898 { X86::_EFLAGS },
899 { X86::CR0 },
900 { X86::CR1 },
901 { X86::CR2 },
902 { X86::CR3 },
903 { X86::CR4 },
904 { X86::CR5 },
905 { X86::CR6 },
906 { X86::CR7 },
907 { X86::CR8 },
908 { X86::CR9 },
909 { X86::CR10 },
910 { X86::CR11 },
911 { X86::CR12 },
912 { X86::CR13 },
913 { X86::CR14 },
914 { X86::CR15 },
915 { X86::DR0 },
916 { X86::DR1 },
917 { X86::DR2 },
918 { X86::DR3 },
919 { X86::DR4 },
920 { X86::DR5 },
921 { X86::DR6 },
922 { X86::DR7 },
923 { X86::DR8 },
924 { X86::DR9 },
925 { X86::DR10 },
926 { X86::DR11 },
927 { X86::DR12 },
928 { X86::DR13 },
929 { X86::DR14 },
930 { X86::DR15 },
931 { X86::FP0 },
932 { X86::FP1 },
933 { X86::FP2 },
934 { X86::FP3 },
935 { X86::FP4 },
936 { X86::FP5 },
937 { X86::FP6 },
938 { X86::FP7 },
939 { X86::MM0 },
940 { X86::MM1 },
941 { X86::MM2 },
942 { X86::MM3 },
943 { X86::MM4 },
944 { X86::MM5 },
945 { X86::MM6 },
946 { X86::MM7 },
947 { X86::R8B },
948 { X86::R8BH },
949 { X86::R8WH },
950 { X86::R9B },
951 { X86::R9BH },
952 { X86::R9WH },
953 { X86::R10B },
954 { X86::R10BH },
955 { X86::R10WH },
956 { X86::R11B },
957 { X86::R11BH },
958 { X86::R11WH },
959 { X86::R12B },
960 { X86::R12BH },
961 { X86::R12WH },
962 { X86::R13B },
963 { X86::R13BH },
964 { X86::R13WH },
965 { X86::R14B },
966 { X86::R14BH },
967 { X86::R14WH },
968 { X86::R15B },
969 { X86::R15BH },
970 { X86::R15WH },
971 { X86::ST0 },
972 { X86::ST1 },
973 { X86::ST2 },
974 { X86::ST3 },
975 { X86::ST4 },
976 { X86::ST5 },
977 { X86::ST6 },
978 { X86::ST7 },
979 { X86::XMM0 },
980 { X86::XMM1 },
981 { X86::XMM2 },
982 { X86::XMM3 },
983 { X86::XMM4 },
984 { X86::XMM5 },
985 { X86::XMM6 },
986 { X86::XMM7 },
987 { X86::XMM8 },
988 { X86::XMM9 },
989 { X86::XMM10 },
990 { X86::XMM11 },
991 { X86::XMM12 },
992 { X86::XMM13 },
993 { X86::XMM14 },
994 { X86::XMM15 },
995 { X86::K0 },
996 { X86::K1 },
997 { X86::K2 },
998 { X86::K3 },
999 { X86::K4 },
1000 { X86::K5 },
1001 { X86::K6 },
1002 { X86::K7 },
1003 { X86::XMM16 },
1004 { X86::XMM17 },
1005 { X86::XMM18 },
1006 { X86::XMM19 },
1007 { X86::XMM20 },
1008 { X86::XMM21 },
1009 { X86::XMM22 },
1010 { X86::XMM23 },
1011 { X86::XMM24 },
1012 { X86::XMM25 },
1013 { X86::XMM26 },
1014 { X86::XMM27 },
1015 { X86::XMM28 },
1016 { X86::XMM29 },
1017 { X86::XMM30 },
1018 { X86::XMM31 },
1019 { X86::TMMCFG },
1020 { X86::TMM0 },
1021 { X86::TMM1 },
1022 { X86::TMM2 },
1023 { X86::TMM3 },
1024 { X86::TMM4 },
1025 { X86::TMM5 },
1026 { X86::TMM6 },
1027 { X86::TMM7 },
1028 { X86::R16B },
1029 { X86::R16BH },
1030 { X86::R16WH },
1031 { X86::R17B },
1032 { X86::R17BH },
1033 { X86::R17WH },
1034 { X86::R18B },
1035 { X86::R18BH },
1036 { X86::R18WH },
1037 { X86::R19B },
1038 { X86::R19BH },
1039 { X86::R19WH },
1040 { X86::R20B },
1041 { X86::R20BH },
1042 { X86::R20WH },
1043 { X86::R21B },
1044 { X86::R21BH },
1045 { X86::R21WH },
1046 { X86::R22B },
1047 { X86::R22BH },
1048 { X86::R22WH },
1049 { X86::R23B },
1050 { X86::R23BH },
1051 { X86::R23WH },
1052 { X86::R24B },
1053 { X86::R24BH },
1054 { X86::R24WH },
1055 { X86::R25B },
1056 { X86::R25BH },
1057 { X86::R25WH },
1058 { X86::R26B },
1059 { X86::R26BH },
1060 { X86::R26WH },
1061 { X86::R27B },
1062 { X86::R27BH },
1063 { X86::R27WH },
1064 { X86::R28B },
1065 { X86::R28BH },
1066 { X86::R28WH },
1067 { X86::R29B },
1068 { X86::R29BH },
1069 { X86::R29WH },
1070 { X86::R30B },
1071 { X86::R30BH },
1072 { X86::R30WH },
1073 { X86::R31B },
1074 { X86::R31BH },
1075 { X86::R31WH },
1076};
1077
1078namespace {
1079
1080// Register classes...
1081 // GR8 Register Class...
1082 const MCPhysReg GR8[] = {
1083 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R30B, X86::R31B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::R20B, X86::R21B, X86::R28B, X86::R29B,
1084 };
1085
1086 // GR8 Bit set.
1087 const uint8_t GR8Bits[] = {
1088 0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1089 };
1090
1091 // GRH8 Register Class...
1092 const MCPhysReg GRH8[] = {
1093 X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH, X86::R16BH, X86::R17BH, X86::R18BH, X86::R19BH, X86::R20BH, X86::R21BH, X86::R22BH, X86::R23BH, X86::R24BH, X86::R25BH, X86::R26BH, X86::R27BH, X86::R28BH, X86::R29BH, X86::R30BH, X86::R31BH,
1094 };
1095
1096 // GRH8 Bit set.
1097 const uint8_t GRH8Bits[] = {
1098 0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1099 };
1100
1101 // GR8_NOREX2 Register Class...
1102 const MCPhysReg GR8_NOREX2[] = {
1103 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
1104 };
1105
1106 // GR8_NOREX2 Bit set.
1107 const uint8_t GR8_NOREX2Bits[] = {
1108 0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1109 };
1110
1111 // GR8_NOREX Register Class...
1112 const MCPhysReg GR8_NOREX[] = {
1113 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
1114 };
1115
1116 // GR8_NOREX Bit set.
1117 const uint8_t GR8_NOREXBits[] = {
1118 0x36, 0x8c, 0x08,
1119 };
1120
1121 // GR8_ABCD_H Register Class...
1122 const MCPhysReg GR8_ABCD_H[] = {
1123 X86::AH, X86::CH, X86::DH, X86::BH,
1124 };
1125
1126 // GR8_ABCD_H Bit set.
1127 const uint8_t GR8_ABCD_HBits[] = {
1128 0x12, 0x84,
1129 };
1130
1131 // GR8_ABCD_L Register Class...
1132 const MCPhysReg GR8_ABCD_L[] = {
1133 X86::AL, X86::CL, X86::DL, X86::BL,
1134 };
1135
1136 // GR8_ABCD_L Bit set.
1137 const uint8_t GR8_ABCD_LBits[] = {
1138 0x24, 0x08, 0x08,
1139 };
1140
1141 // GRH16 Register Class...
1142 const MCPhysReg GRH16[] = {
1143 X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH, X86::R16WH, X86::R17WH, X86::R18WH, X86::R19WH, X86::R20WH, X86::R21WH, X86::R22WH, X86::R23WH, X86::R24WH, X86::R25WH, X86::R26WH, X86::R27WH, X86::R28WH, X86::R29WH, X86::R30WH, X86::R31WH,
1144 };
1145
1146 // GRH16 Bit set.
1147 const uint8_t GRH16Bits[] = {
1148 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1149 };
1150
1151 // GR16 Register Class...
1152 const MCPhysReg GR16[] = {
1153 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R16W, X86::R17W, X86::R18W, X86::R19W, X86::R22W, X86::R23W, X86::R24W, X86::R25W, X86::R26W, X86::R27W, X86::R30W, X86::R31W, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::R20W, X86::R21W, X86::R28W, X86::R29W,
1154 };
1155
1156 // GR16 Bit set.
1157 const uint8_t GR16Bits[] = {
1158 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1159 };
1160
1161 // GR16_NOREX2 Register Class...
1162 const MCPhysReg GR16_NOREX2[] = {
1163 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
1164 };
1165
1166 // GR16_NOREX2 Bit set.
1167 const uint8_t GR16_NOREX2Bits[] = {
1168 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1169 };
1170
1171 // GR16_NOREX Register Class...
1172 const MCPhysReg GR16_NOREX[] = {
1173 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP,
1174 };
1175
1176 // GR16_NOREX Bit set.
1177 const uint8_t GR16_NOREXBits[] = {
1178 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02,
1179 };
1180
1181 // VK1 Register Class...
1182 const MCPhysReg VK1[] = {
1183 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1184 };
1185
1186 // VK1 Bit set.
1187 const uint8_t VK1Bits[] = {
1188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1189 };
1190
1191 // VK16 Register Class...
1192 const MCPhysReg VK16[] = {
1193 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1194 };
1195
1196 // VK16 Bit set.
1197 const uint8_t VK16Bits[] = {
1198 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1199 };
1200
1201 // VK2 Register Class...
1202 const MCPhysReg VK2[] = {
1203 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1204 };
1205
1206 // VK2 Bit set.
1207 const uint8_t VK2Bits[] = {
1208 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1209 };
1210
1211 // VK4 Register Class...
1212 const MCPhysReg VK4[] = {
1213 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1214 };
1215
1216 // VK4 Bit set.
1217 const uint8_t VK4Bits[] = {
1218 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1219 };
1220
1221 // VK8 Register Class...
1222 const MCPhysReg VK8[] = {
1223 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1224 };
1225
1226 // VK8 Bit set.
1227 const uint8_t VK8Bits[] = {
1228 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1229 };
1230
1231 // VK16WM Register Class...
1232 const MCPhysReg VK16WM[] = {
1233 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1234 };
1235
1236 // VK16WM Bit set.
1237 const uint8_t VK16WMBits[] = {
1238 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1239 };
1240
1241 // VK1WM Register Class...
1242 const MCPhysReg VK1WM[] = {
1243 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1244 };
1245
1246 // VK1WM Bit set.
1247 const uint8_t VK1WMBits[] = {
1248 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1249 };
1250
1251 // VK2WM Register Class...
1252 const MCPhysReg VK2WM[] = {
1253 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1254 };
1255
1256 // VK2WM Bit set.
1257 const uint8_t VK2WMBits[] = {
1258 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1259 };
1260
1261 // VK4WM Register Class...
1262 const MCPhysReg VK4WM[] = {
1263 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1264 };
1265
1266 // VK4WM Bit set.
1267 const uint8_t VK4WMBits[] = {
1268 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1269 };
1270
1271 // VK8WM Register Class...
1272 const MCPhysReg VK8WM[] = {
1273 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1274 };
1275
1276 // VK8WM Bit set.
1277 const uint8_t VK8WMBits[] = {
1278 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1279 };
1280
1281 // SEGMENT_REG Register Class...
1282 const MCPhysReg SEGMENT_REG[] = {
1283 X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS,
1284 };
1285
1286 // SEGMENT_REG Bit set.
1287 const uint8_t SEGMENT_REGBits[] = {
1288 0x00, 0x10, 0x10, 0x80, 0x50, 0x00, 0x00, 0x00, 0x10,
1289 };
1290
1291 // GR16_ABCD Register Class...
1292 const MCPhysReg GR16_ABCD[] = {
1293 X86::AX, X86::CX, X86::DX, X86::BX,
1294 };
1295
1296 // GR16_ABCD Bit set.
1297 const uint8_t GR16_ABCDBits[] = {
1298 0x08, 0x22, 0x20,
1299 };
1300
1301 // FPCCR Register Class...
1302 const MCPhysReg FPCCR[] = {
1303 X86::FPSW,
1304 };
1305
1306 // FPCCR Bit set.
1307 const uint8_t FPCCRBits[] = {
1308 0x00, 0x00, 0x00, 0x00, 0x08,
1309 };
1310
1311 // FR16X Register Class...
1312 const MCPhysReg FR16X[] = {
1313 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
1314 };
1315
1316 // FR16X Bit set.
1317 const uint8_t FR16XBits[] = {
1318 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1319 };
1320
1321 // FR16 Register Class...
1322 const MCPhysReg FR16[] = {
1323 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
1324 };
1325
1326 // FR16 Bit set.
1327 const uint8_t FR16Bits[] = {
1328 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1329 };
1330
1331 // VK16PAIR Register Class...
1332 const MCPhysReg VK16PAIR[] = {
1333 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1334 };
1335
1336 // VK16PAIR Bit set.
1337 const uint8_t VK16PAIRBits[] = {
1338 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1339 };
1340
1341 // VK1PAIR Register Class...
1342 const MCPhysReg VK1PAIR[] = {
1343 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1344 };
1345
1346 // VK1PAIR Bit set.
1347 const uint8_t VK1PAIRBits[] = {
1348 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1349 };
1350
1351 // VK2PAIR Register Class...
1352 const MCPhysReg VK2PAIR[] = {
1353 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1354 };
1355
1356 // VK2PAIR Bit set.
1357 const uint8_t VK2PAIRBits[] = {
1358 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1359 };
1360
1361 // VK4PAIR Register Class...
1362 const MCPhysReg VK4PAIR[] = {
1363 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1364 };
1365
1366 // VK4PAIR Bit set.
1367 const uint8_t VK4PAIRBits[] = {
1368 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1369 };
1370
1371 // VK8PAIR Register Class...
1372 const MCPhysReg VK8PAIR[] = {
1373 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1374 };
1375
1376 // VK8PAIR Bit set.
1377 const uint8_t VK8PAIRBits[] = {
1378 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1379 };
1380
1381 // VK1PAIR_with_sub_mask_0_in_VK1WM Register Class...
1382 const MCPhysReg VK1PAIR_with_sub_mask_0_in_VK1WM[] = {
1383 X86::K2_K3, X86::K4_K5, X86::K6_K7,
1384 };
1385
1386 // VK1PAIR_with_sub_mask_0_in_VK1WM Bit set.
1387 const uint8_t VK1PAIR_with_sub_mask_0_in_VK1WMBits[] = {
1388 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
1389 };
1390
1391 // LOW32_ADDR_ACCESS_RBP Register Class...
1392 const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
1393 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::RIP, X86::RBP,
1394 };
1395
1396 // LOW32_ADDR_ACCESS_RBP Bit set.
1397 const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
1398 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1399 };
1400
1401 // LOW32_ADDR_ACCESS Register Class...
1402 const MCPhysReg LOW32_ADDR_ACCESS[] = {
1403 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::RIP,
1404 };
1405
1406 // LOW32_ADDR_ACCESS Bit set.
1407 const uint8_t LOW32_ADDR_ACCESSBits[] = {
1408 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1409 };
1410
1411 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
1412 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
1413 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::RBP,
1414 };
1415
1416 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
1417 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
1418 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1419 };
1420
1421 // FR32X Register Class...
1422 const MCPhysReg FR32X[] = {
1423 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
1424 };
1425
1426 // FR32X Bit set.
1427 const uint8_t FR32XBits[] = {
1428 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1429 };
1430
1431 // GR32 Register Class...
1432 const MCPhysReg GR32[] = {
1433 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D,
1434 };
1435
1436 // GR32 Bit set.
1437 const uint8_t GR32Bits[] = {
1438 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1439 };
1440
1441 // GR32_NOSP Register Class...
1442 const MCPhysReg GR32_NOSP[] = {
1443 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D,
1444 };
1445
1446 // GR32_NOSP Bit set.
1447 const uint8_t GR32_NOSPBits[] = {
1448 0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1449 };
1450
1451 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 Register Class...
1452 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2[] = {
1453 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP,
1454 };
1455
1456 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 Bit set.
1457 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits[] = {
1458 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1459 };
1460
1461 // DEBUG_REG Register Class...
1462 const MCPhysReg DEBUG_REG[] = {
1463 X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15,
1464 };
1465
1466 // DEBUG_REG Bit set.
1467 const uint8_t DEBUG_REGBits[] = {
1468 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1469 };
1470
1471 // FR32 Register Class...
1472 const MCPhysReg FR32[] = {
1473 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
1474 };
1475
1476 // FR32 Bit set.
1477 const uint8_t FR32Bits[] = {
1478 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1479 };
1480
1481 // GR32_NOREX2 Register Class...
1482 const MCPhysReg GR32_NOREX2[] = {
1483 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
1484 };
1485
1486 // GR32_NOREX2 Bit set.
1487 const uint8_t GR32_NOREX2Bits[] = {
1488 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1489 };
1490
1491 // GR32_NOREX2_NOSP Register Class...
1492 const MCPhysReg GR32_NOREX2_NOSP[] = {
1493 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
1494 };
1495
1496 // GR32_NOREX2_NOSP Bit set.
1497 const uint8_t GR32_NOREX2_NOSPBits[] = {
1498 0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1499 };
1500
1501 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
1502 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
1503 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP,
1504 };
1505
1506 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
1507 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
1508 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10,
1509 };
1510
1511 // GR32_NOREX Register Class...
1512 const MCPhysReg GR32_NOREX[] = {
1513 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP,
1514 };
1515
1516 // GR32_NOREX Bit set.
1517 const uint8_t GR32_NOREXBits[] = {
1518 0x00, 0x00, 0xc0, 0x0f, 0x03,
1519 };
1520
1521 // VK32 Register Class...
1522 const MCPhysReg VK32[] = {
1523 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1524 };
1525
1526 // VK32 Bit set.
1527 const uint8_t VK32Bits[] = {
1528 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1529 };
1530
1531 // GR32_NOREX_NOSP Register Class...
1532 const MCPhysReg GR32_NOREX_NOSP[] = {
1533 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,
1534 };
1535
1536 // GR32_NOREX_NOSP Bit set.
1537 const uint8_t GR32_NOREX_NOSPBits[] = {
1538 0x00, 0x00, 0xc0, 0x0f, 0x01,
1539 };
1540
1541 // RFP32 Register Class...
1542 const MCPhysReg RFP32[] = {
1543 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
1544 };
1545
1546 // RFP32 Bit set.
1547 const uint8_t RFP32Bits[] = {
1548 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
1549 };
1550
1551 // VK32WM Register Class...
1552 const MCPhysReg VK32WM[] = {
1553 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1554 };
1555
1556 // VK32WM Bit set.
1557 const uint8_t VK32WMBits[] = {
1558 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1559 };
1560
1561 // GR32_ABCD Register Class...
1562 const MCPhysReg GR32_ABCD[] = {
1563 X86::EAX, X86::ECX, X86::EDX, X86::EBX,
1564 };
1565
1566 // GR32_ABCD Bit set.
1567 const uint8_t GR32_ABCDBits[] = {
1568 0x00, 0x00, 0x40, 0x0b,
1569 };
1570
1571 // GR32_TC Register Class...
1572 const MCPhysReg GR32_TC[] = {
1573 X86::EAX, X86::ECX, X86::EDX, X86::ESP,
1574 };
1575
1576 // GR32_TC Bit set.
1577 const uint8_t GR32_TCBits[] = {
1578 0x00, 0x00, 0x40, 0x0a, 0x02,
1579 };
1580
1581 // GR32_ABCD_and_GR32_TC Register Class...
1582 const MCPhysReg GR32_ABCD_and_GR32_TC[] = {
1583 X86::EAX, X86::ECX, X86::EDX,
1584 };
1585
1586 // GR32_ABCD_and_GR32_TC Bit set.
1587 const uint8_t GR32_ABCD_and_GR32_TCBits[] = {
1588 0x00, 0x00, 0x40, 0x0a,
1589 };
1590
1591 // GR32_AD Register Class...
1592 const MCPhysReg GR32_AD[] = {
1593 X86::EAX, X86::EDX,
1594 };
1595
1596 // GR32_AD Bit set.
1597 const uint8_t GR32_ADBits[] = {
1598 0x00, 0x00, 0x40, 0x08,
1599 };
1600
1601 // GR32_ArgRef Register Class...
1602 const MCPhysReg GR32_ArgRef[] = {
1603 X86::ECX, X86::EDX,
1604 };
1605
1606 // GR32_ArgRef Bit set.
1607 const uint8_t GR32_ArgRefBits[] = {
1608 0x00, 0x00, 0x00, 0x0a,
1609 };
1610
1611 // GR32_BPSP Register Class...
1612 const MCPhysReg GR32_BPSP[] = {
1613 X86::EBP, X86::ESP,
1614 };
1615
1616 // GR32_BPSP Bit set.
1617 const uint8_t GR32_BPSPBits[] = {
1618 0x00, 0x00, 0x80, 0x00, 0x02,
1619 };
1620
1621 // GR32_BSI Register Class...
1622 const MCPhysReg GR32_BSI[] = {
1623 X86::EBX, X86::ESI,
1624 };
1625
1626 // GR32_BSI Bit set.
1627 const uint8_t GR32_BSIBits[] = {
1628 0x00, 0x00, 0x00, 0x01, 0x01,
1629 };
1630
1631 // GR32_CB Register Class...
1632 const MCPhysReg GR32_CB[] = {
1633 X86::ECX, X86::EBX,
1634 };
1635
1636 // GR32_CB Bit set.
1637 const uint8_t GR32_CBBits[] = {
1638 0x00, 0x00, 0x00, 0x03,
1639 };
1640
1641 // GR32_DC Register Class...
1642 const MCPhysReg GR32_DC[] = {
1643 X86::EDX, X86::ECX,
1644 };
1645
1646 // GR32_DC Bit set.
1647 const uint8_t GR32_DCBits[] = {
1648 0x00, 0x00, 0x00, 0x0a,
1649 };
1650
1651 // GR32_DIBP Register Class...
1652 const MCPhysReg GR32_DIBP[] = {
1653 X86::EDI, X86::EBP,
1654 };
1655
1656 // GR32_DIBP Bit set.
1657 const uint8_t GR32_DIBPBits[] = {
1658 0x00, 0x00, 0x80, 0x04,
1659 };
1660
1661 // GR32_SIDI Register Class...
1662 const MCPhysReg GR32_SIDI[] = {
1663 X86::ESI, X86::EDI,
1664 };
1665
1666 // GR32_SIDI Bit set.
1667 const uint8_t GR32_SIDIBits[] = {
1668 0x00, 0x00, 0x00, 0x04, 0x01,
1669 };
1670
1671 // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
1672 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
1673 X86::RIP, X86::RBP,
1674 };
1675
1676 // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
1677 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
1678 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
1679 };
1680
1681 // CCR Register Class...
1682 const MCPhysReg CCR[] = {
1683 X86::EFLAGS,
1684 };
1685
1686 // CCR Bit set.
1687 const uint8_t CCRBits[] = {
1688 0x00, 0x00, 0x00, 0x10,
1689 };
1690
1691 // DFCCR Register Class...
1692 const MCPhysReg DFCCR[] = {
1693 X86::DF,
1694 };
1695
1696 // DFCCR Bit set.
1697 const uint8_t DFCCRBits[] = {
1698 0x00, 0x40,
1699 };
1700
1701 // GR32_ABCD_and_GR32_BSI Register Class...
1702 const MCPhysReg GR32_ABCD_and_GR32_BSI[] = {
1703 X86::EBX,
1704 };
1705
1706 // GR32_ABCD_and_GR32_BSI Bit set.
1707 const uint8_t GR32_ABCD_and_GR32_BSIBits[] = {
1708 0x00, 0x00, 0x00, 0x01,
1709 };
1710
1711 // GR32_AD_and_GR32_ArgRef Register Class...
1712 const MCPhysReg GR32_AD_and_GR32_ArgRef[] = {
1713 X86::EDX,
1714 };
1715
1716 // GR32_AD_and_GR32_ArgRef Bit set.
1717 const uint8_t GR32_AD_and_GR32_ArgRefBits[] = {
1718 0x00, 0x00, 0x00, 0x08,
1719 };
1720
1721 // GR32_ArgRef_and_GR32_CB Register Class...
1722 const MCPhysReg GR32_ArgRef_and_GR32_CB[] = {
1723 X86::ECX,
1724 };
1725
1726 // GR32_ArgRef_and_GR32_CB Bit set.
1727 const uint8_t GR32_ArgRef_and_GR32_CBBits[] = {
1728 0x00, 0x00, 0x00, 0x02,
1729 };
1730
1731 // GR32_BPSP_and_GR32_DIBP Register Class...
1732 const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = {
1733 X86::EBP,
1734 };
1735
1736 // GR32_BPSP_and_GR32_DIBP Bit set.
1737 const uint8_t GR32_BPSP_and_GR32_DIBPBits[] = {
1738 0x00, 0x00, 0x80,
1739 };
1740
1741 // GR32_BPSP_and_GR32_TC Register Class...
1742 const MCPhysReg GR32_BPSP_and_GR32_TC[] = {
1743 X86::ESP,
1744 };
1745
1746 // GR32_BPSP_and_GR32_TC Bit set.
1747 const uint8_t GR32_BPSP_and_GR32_TCBits[] = {
1748 0x00, 0x00, 0x00, 0x00, 0x02,
1749 };
1750
1751 // GR32_BSI_and_GR32_SIDI Register Class...
1752 const MCPhysReg GR32_BSI_and_GR32_SIDI[] = {
1753 X86::ESI,
1754 };
1755
1756 // GR32_BSI_and_GR32_SIDI Bit set.
1757 const uint8_t GR32_BSI_and_GR32_SIDIBits[] = {
1758 0x00, 0x00, 0x00, 0x00, 0x01,
1759 };
1760
1761 // GR32_DIBP_and_GR32_SIDI Register Class...
1762 const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = {
1763 X86::EDI,
1764 };
1765
1766 // GR32_DIBP_and_GR32_SIDI Bit set.
1767 const uint8_t GR32_DIBP_and_GR32_SIDIBits[] = {
1768 0x00, 0x00, 0x00, 0x04,
1769 };
1770
1771 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
1772 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
1773 X86::RBP,
1774 };
1775
1776 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
1777 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
1778 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
1779 };
1780
1781 // LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
1782 const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
1783 X86::RIP,
1784 };
1785
1786 // LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
1787 const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
1788 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
1789 };
1790
1791 // RFP64 Register Class...
1792 const MCPhysReg RFP64[] = {
1793 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
1794 };
1795
1796 // RFP64 Bit set.
1797 const uint8_t RFP64Bits[] = {
1798 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
1799 };
1800
1801 // GR64 Register Class...
1802 const MCPhysReg GR64[] = {
1803 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::RBP, X86::RSP, X86::RIP,
1804 };
1805
1806 // GR64 Bit set.
1807 const uint8_t GR64Bits[] = {
1808 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1809 };
1810
1811 // FR64X Register Class...
1812 const MCPhysReg FR64X[] = {
1813 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
1814 };
1815
1816 // FR64X Bit set.
1817 const uint8_t FR64XBits[] = {
1818 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1819 };
1820
1821 // GR64_with_sub_8bit Register Class...
1822 const MCPhysReg GR64_with_sub_8bit[] = {
1823 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::RBP, X86::RSP,
1824 };
1825
1826 // GR64_with_sub_8bit Bit set.
1827 const uint8_t GR64_with_sub_8bitBits[] = {
1828 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1829 };
1830
1831 // GR64_NOSP Register Class...
1832 const MCPhysReg GR64_NOSP[] = {
1833 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::RBP,
1834 };
1835
1836 // GR64_NOSP Bit set.
1837 const uint8_t GR64_NOSPBits[] = {
1838 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1839 };
1840
1841 // GR64_NOREX2 Register Class...
1842 const MCPhysReg GR64_NOREX2[] = {
1843 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
1844 };
1845
1846 // GR64_NOREX2 Bit set.
1847 const uint8_t GR64_NOREX2Bits[] = {
1848 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1849 };
1850
1851 // CONTROL_REG Register Class...
1852 const MCPhysReg CONTROL_REG[] = {
1853 X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15,
1854 };
1855
1856 // CONTROL_REG Bit set.
1857 const uint8_t CONTROL_REGBits[] = {
1858 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1859 };
1860
1861 // FR64 Register Class...
1862 const MCPhysReg FR64[] = {
1863 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
1864 };
1865
1866 // FR64 Bit set.
1867 const uint8_t FR64Bits[] = {
1868 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1869 };
1870
1871 // GR64_with_sub_16bit_in_GR16_NOREX2 Register Class...
1872 const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX2[] = {
1873 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
1874 };
1875
1876 // GR64_with_sub_16bit_in_GR16_NOREX2 Bit set.
1877 const uint8_t GR64_with_sub_16bit_in_GR16_NOREX2Bits[] = {
1878 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1879 };
1880
1881 // GR64_NOREX2_NOSP Register Class...
1882 const MCPhysReg GR64_NOREX2_NOSP[] = {
1883 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
1884 };
1885
1886 // GR64_NOREX2_NOSP Bit set.
1887 const uint8_t GR64_NOREX2_NOSPBits[] = {
1888 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1889 };
1890
1891 // GR64PLTSafe Register Class...
1892 const MCPhysReg GR64PLTSafe[] = {
1893 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
1894 };
1895
1896 // GR64PLTSafe Bit set.
1897 const uint8_t GR64PLTSafeBits[] = {
1898 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x79,
1899 };
1900
1901 // GR64_TC Register Class...
1902 const MCPhysReg GR64_TC[] = {
1903 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
1904 };
1905
1906 // GR64_TC Bit set.
1907 const uint8_t GR64_TCBits[] = {
1908 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
1909 };
1910
1911 // GR64_NOREX Register Class...
1912 const MCPhysReg GR64_NOREX[] = {
1913 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
1914 };
1915
1916 // GR64_NOREX Bit set.
1917 const uint8_t GR64_NOREXBits[] = {
1918 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35,
1919 };
1920
1921 // GR64_TCW64 Register Class...
1922 const MCPhysReg GR64_TCW64[] = {
1923 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP,
1924 };
1925
1926 // GR64_TCW64 Bit set.
1927 const uint8_t GR64_TCW64Bits[] = {
1928 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1929 };
1930
1931 // GR64_TC_with_sub_8bit Register Class...
1932 const MCPhysReg GR64_TC_with_sub_8bit[] = {
1933 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP,
1934 };
1935
1936 // GR64_TC_with_sub_8bit Bit set.
1937 const uint8_t GR64_TC_with_sub_8bitBits[] = {
1938 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
1939 };
1940
1941 // GR64_NOREX2_NOSP_and_GR64_TC Register Class...
1942 const MCPhysReg GR64_NOREX2_NOSP_and_GR64_TC[] = {
1943 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11,
1944 };
1945
1946 // GR64_NOREX2_NOSP_and_GR64_TC Bit set.
1947 const uint8_t GR64_NOREX2_NOSP_and_GR64_TCBits[] = {
1948 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
1949 };
1950
1951 // GR64_TCW64_with_sub_8bit Register Class...
1952 const MCPhysReg GR64_TCW64_with_sub_8bit[] = {
1953 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP,
1954 };
1955
1956 // GR64_TCW64_with_sub_8bit Bit set.
1957 const uint8_t GR64_TCW64_with_sub_8bitBits[] = {
1958 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1959 };
1960
1961 // GR64_TC_and_GR64_TCW64 Register Class...
1962 const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
1963 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
1964 };
1965
1966 // GR64_TC_and_GR64_TCW64 Bit set.
1967 const uint8_t GR64_TC_and_GR64_TCW64Bits[] = {
1968 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
1969 };
1970
1971 // GR64_with_sub_16bit_in_GR16_NOREX Register Class...
1972 const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
1973 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP,
1974 };
1975
1976 // GR64_with_sub_16bit_in_GR16_NOREX Bit set.
1977 const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
1978 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31,
1979 };
1980
1981 // VK64 Register Class...
1982 const MCPhysReg VK64[] = {
1983 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1984 };
1985
1986 // VK64 Bit set.
1987 const uint8_t VK64Bits[] = {
1988 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1989 };
1990
1991 // VR64 Register Class...
1992 const MCPhysReg VR64[] = {
1993 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
1994 };
1995
1996 // VR64 Bit set.
1997 const uint8_t VR64Bits[] = {
1998 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1999 };
2000
2001 // GR64PLTSafe_and_GR64_TC Register Class...
2002 const MCPhysReg GR64PLTSafe_and_GR64_TC[] = {
2003 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9,
2004 };
2005
2006 // GR64PLTSafe_and_GR64_TC Bit set.
2007 const uint8_t GR64PLTSafe_and_GR64_TCBits[] = {
2008 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
2009 };
2010
2011 // GR64_NOREX2_NOSP_and_GR64_TCW64 Register Class...
2012 const MCPhysReg GR64_NOREX2_NOSP_and_GR64_TCW64[] = {
2013 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11,
2014 };
2015
2016 // GR64_NOREX2_NOSP_and_GR64_TCW64 Bit set.
2017 const uint8_t GR64_NOREX2_NOSP_and_GR64_TCW64Bits[] = {
2018 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
2019 };
2020
2021 // GR64_NOREX_NOSP Register Class...
2022 const MCPhysReg GR64_NOREX_NOSP[] = {
2023 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP,
2024 };
2025
2026 // GR64_NOREX_NOSP Bit set.
2027 const uint8_t GR64_NOREX_NOSPBits[] = {
2028 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11,
2029 };
2030
2031 // GR64_NOREX_and_GR64_TC Register Class...
2032 const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
2033 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP,
2034 };
2035
2036 // GR64_NOREX_and_GR64_TC Bit set.
2037 const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
2038 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35,
2039 };
2040
2041 // GR64_TCW64_and_GR64_TC_with_sub_8bit Register Class...
2042 const MCPhysReg GR64_TCW64_and_GR64_TC_with_sub_8bit[] = {
2043 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP,
2044 };
2045
2046 // GR64_TCW64_and_GR64_TC_with_sub_8bit Bit set.
2047 const uint8_t GR64_TCW64_and_GR64_TC_with_sub_8bitBits[] = {
2048 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2049 };
2050
2051 // VK64WM Register Class...
2052 const MCPhysReg VK64WM[] = {
2053 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
2054 };
2055
2056 // VK64WM Bit set.
2057 const uint8_t VK64WMBits[] = {
2058 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
2059 };
2060
2061 // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 Register Class...
2062 const MCPhysReg GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64[] = {
2063 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11,
2064 };
2065
2066 // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 Bit set.
2067 const uint8_t GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits[] = {
2068 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2069 };
2070
2071 // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Register Class...
2072 const MCPhysReg GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX[] = {
2073 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP,
2074 };
2075
2076 // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Bit set.
2077 const uint8_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
2078 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31,
2079 };
2080
2081 // GR64PLTSafe_and_GR64_TCW64 Register Class...
2082 const MCPhysReg GR64PLTSafe_and_GR64_TCW64[] = {
2083 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9,
2084 };
2085
2086 // GR64PLTSafe_and_GR64_TCW64 Bit set.
2087 const uint8_t GR64PLTSafe_and_GR64_TCW64Bits[] = {
2088 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
2089 };
2090
2091 // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Register Class...
2092 const MCPhysReg GR64_NOREX_and_GR64PLTSafe_and_GR64_TC[] = {
2093 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI,
2094 };
2095
2096 // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Bit set.
2097 const uint8_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits[] = {
2098 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11,
2099 };
2100
2101 // GR64_NOREX_and_GR64_TCW64 Register Class...
2102 const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
2103 X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP,
2104 };
2105
2106 // GR64_NOREX_and_GR64_TCW64 Bit set.
2107 const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = {
2108 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25,
2109 };
2110
2111 // GR64_ABCD Register Class...
2112 const MCPhysReg GR64_ABCD[] = {
2113 X86::RAX, X86::RCX, X86::RDX, X86::RBX,
2114 };
2115
2116 // GR64_ABCD Bit set.
2117 const uint8_t GR64_ABCDBits[] = {
2118 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0x01,
2119 };
2120
2121 // GR64_with_sub_32bit_in_GR32_TC Register Class...
2122 const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
2123 X86::RAX, X86::RCX, X86::RDX, X86::RSP,
2124 };
2125
2126 // GR64_with_sub_32bit_in_GR32_TC Bit set.
2127 const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
2128 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21,
2129 };
2130
2131 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Register Class...
2132 const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC[] = {
2133 X86::RAX, X86::RCX, X86::RDX,
2134 };
2135
2136 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Bit set.
2137 const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits[] = {
2138 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01,
2139 };
2140
2141 // GR64_AD Register Class...
2142 const MCPhysReg GR64_AD[] = {
2143 X86::RAX, X86::RDX,
2144 };
2145
2146 // GR64_AD Bit set.
2147 const uint8_t GR64_ADBits[] = {
2148 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01,
2149 };
2150
2151 // GR64_ArgRef Register Class...
2152 const MCPhysReg GR64_ArgRef[] = {
2153 X86::R10, X86::R11,
2154 };
2155
2156 // GR64_ArgRef Bit set.
2157 const uint8_t GR64_ArgRefBits[] = {
2158 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,
2159 };
2160
2161 // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class...
2162 const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
2163 X86::RBP, X86::RIP,
2164 };
2165
2166 // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set.
2167 const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = {
2168 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
2169 };
2170
2171 // GR64_with_sub_32bit_in_GR32_ArgRef Register Class...
2172 const MCPhysReg GR64_with_sub_32bit_in_GR32_ArgRef[] = {
2173 X86::RCX, X86::RDX,
2174 };
2175
2176 // GR64_with_sub_32bit_in_GR32_ArgRef Bit set.
2177 const uint8_t GR64_with_sub_32bit_in_GR32_ArgRefBits[] = {
2178 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01,
2179 };
2180
2181 // GR64_with_sub_32bit_in_GR32_BPSP Register Class...
2182 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP[] = {
2183 X86::RBP, X86::RSP,
2184 };
2185
2186 // GR64_with_sub_32bit_in_GR32_BPSP Bit set.
2187 const uint8_t GR64_with_sub_32bit_in_GR32_BPSPBits[] = {
2188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x20,
2189 };
2190
2191 // GR64_with_sub_32bit_in_GR32_BSI Register Class...
2192 const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI[] = {
2193 X86::RSI, X86::RBX,
2194 };
2195
2196 // GR64_with_sub_32bit_in_GR32_BSI Bit set.
2197 const uint8_t GR64_with_sub_32bit_in_GR32_BSIBits[] = {
2198 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x10,
2199 };
2200
2201 // GR64_with_sub_32bit_in_GR32_CB Register Class...
2202 const MCPhysReg GR64_with_sub_32bit_in_GR32_CB[] = {
2203 X86::RCX, X86::RBX,
2204 };
2205
2206 // GR64_with_sub_32bit_in_GR32_CB Bit set.
2207 const uint8_t GR64_with_sub_32bit_in_GR32_CBBits[] = {
2208 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
2209 };
2210
2211 // GR64_with_sub_32bit_in_GR32_DIBP Register Class...
2212 const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP[] = {
2213 X86::RDI, X86::RBP,
2214 };
2215
2216 // GR64_with_sub_32bit_in_GR32_DIBP Bit set.
2217 const uint8_t GR64_with_sub_32bit_in_GR32_DIBPBits[] = {
2218 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90,
2219 };
2220
2221 // GR64_with_sub_32bit_in_GR32_SIDI Register Class...
2222 const MCPhysReg GR64_with_sub_32bit_in_GR32_SIDI[] = {
2223 X86::RSI, X86::RDI,
2224 };
2225
2226 // GR64_with_sub_32bit_in_GR32_SIDI Bit set.
2227 const uint8_t GR64_with_sub_32bit_in_GR32_SIDIBits[] = {
2228 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10,
2229 };
2230
2231 // GR64_A Register Class...
2232 const MCPhysReg GR64_A[] = {
2233 X86::RAX,
2234 };
2235
2236 // GR64_A Bit set.
2237 const uint8_t GR64_ABits[] = {
2238 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2239 };
2240
2241 // GR64_ArgRef_and_GR64_TC Register Class...
2242 const MCPhysReg GR64_ArgRef_and_GR64_TC[] = {
2243 X86::R11,
2244 };
2245
2246 // GR64_ArgRef_and_GR64_TC Bit set.
2247 const uint8_t GR64_ArgRef_and_GR64_TCBits[] = {
2248 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2249 };
2250
2251 // GR64_and_LOW32_ADDR_ACCESS Register Class...
2252 const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
2253 X86::RIP,
2254 };
2255
2256 // GR64_and_LOW32_ADDR_ACCESS Bit set.
2257 const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = {
2258 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2259 };
2260
2261 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Register Class...
2262 const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI[] = {
2263 X86::RBX,
2264 };
2265
2266 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Bit set.
2267 const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits[] = {
2268 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2269 };
2270
2271 // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef Register Class...
2272 const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef[] = {
2273 X86::RDX,
2274 };
2275
2276 // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef Bit set.
2277 const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits[] = {
2278 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
2279 };
2280
2281 // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB Register Class...
2282 const MCPhysReg GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB[] = {
2283 X86::RCX,
2284 };
2285
2286 // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB Bit set.
2287 const uint8_t GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits[] = {
2288 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2289 };
2290
2291 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Register Class...
2292 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP[] = {
2293 X86::RBP,
2294 };
2295
2296 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Bit set.
2297 const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits[] = {
2298 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2299 };
2300
2301 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Register Class...
2302 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC[] = {
2303 X86::RSP,
2304 };
2305
2306 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Bit set.
2307 const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits[] = {
2308 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2309 };
2310
2311 // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Register Class...
2312 const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI[] = {
2313 X86::RSI,
2314 };
2315
2316 // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Bit set.
2317 const uint8_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits[] = {
2318 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2319 };
2320
2321 // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Register Class...
2322 const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI[] = {
2323 X86::RDI,
2324 };
2325
2326 // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Bit set.
2327 const uint8_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits[] = {
2328 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
2329 };
2330
2331 // RST Register Class...
2332 const MCPhysReg RST[] = {
2333 X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
2334 };
2335
2336 // RST Bit set.
2337 const uint8_t RSTBits[] = {
2338 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2339 };
2340
2341 // RFP80 Register Class...
2342 const MCPhysReg RFP80[] = {
2343 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
2344 };
2345
2346 // RFP80 Bit set.
2347 const uint8_t RFP80Bits[] = {
2348 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
2349 };
2350
2351 // RFP80_7 Register Class...
2352 const MCPhysReg RFP80_7[] = {
2353 X86::FP7,
2354 };
2355
2356 // RFP80_7 Bit set.
2357 const uint8_t RFP80_7Bits[] = {
2358 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2359 };
2360
2361 // VR128X Register Class...
2362 const MCPhysReg VR128X[] = {
2363 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
2364 };
2365
2366 // VR128X Bit set.
2367 const uint8_t VR128XBits[] = {
2368 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2369 };
2370
2371 // VR128 Register Class...
2372 const MCPhysReg VR128[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
2374 };
2375
2376 // VR128 Bit set.
2377 const uint8_t VR128Bits[] = {
2378 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2379 };
2380
2381 // VR256X Register Class...
2382 const MCPhysReg VR256X[] = {
2383 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31,
2384 };
2385
2386 // VR256X Bit set.
2387 const uint8_t VR256XBits[] = {
2388 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x80, 0xff, 0x7f,
2389 };
2390
2391 // VR256 Register Class...
2392 const MCPhysReg VR256[] = {
2393 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15,
2394 };
2395
2396 // VR256 Bit set.
2397 const uint8_t VR256Bits[] = {
2398 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2399 };
2400
2401 // VR512 Register Class...
2402 const MCPhysReg VR512[] = {
2403 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31,
2404 };
2405
2406 // VR512 Bit set.
2407 const uint8_t VR512Bits[] = {
2408 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
2409 };
2410
2411 // VR512_0_15 Register Class...
2412 const MCPhysReg VR512_0_15[] = {
2413 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15,
2414 };
2415
2416 // VR512_0_15 Bit set.
2417 const uint8_t VR512_0_15Bits[] = {
2418 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2419 };
2420
2421 // TILE Register Class...
2422 const MCPhysReg TILE[] = {
2423 X86::TMM0, X86::TMM1, X86::TMM2, X86::TMM3, X86::TMM4, X86::TMM5, X86::TMM6, X86::TMM7,
2424 };
2425
2426 // TILE Bit set.
2427 const uint8_t TILEBits[] = {
2428 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
2429 };
2430
2431} // namespace
2432
2433#ifdef __GNUC__
2434#pragma GCC diagnostic push
2435#pragma GCC diagnostic ignored "-Woverlength-strings"
2436#endif
2437extern const char X86RegClassStrings[] = {
2438 /* 0 */ "RFP80\000"
2439 /* 6 */ "VK1\000"
2440 /* 10 */ "VR512\000"
2441 /* 16 */ "VK32\000"
2442 /* 21 */ "RFP32\000"
2443 /* 27 */ "FR32\000"
2444 /* 32 */ "GR32\000"
2445 /* 37 */ "VK2\000"
2446 /* 41 */ "GR32_NOREX2\000"
2447 /* 53 */ "GR64_NOREX2\000"
2448 /* 65 */ "GR64_with_sub_16bit_in_GR16_NOREX2\000"
2449 /* 100 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2\000"
2450 /* 152 */ "GR8_NOREX2\000"
2451 /* 163 */ "VK64\000"
2452 /* 168 */ "RFP64\000"
2453 /* 174 */ "FR64\000"
2454 /* 179 */ "GR64\000"
2455 /* 184 */ "VR64\000"
2456 /* 189 */ "GR64_TC_and_GR64_TCW64\000"
2457 /* 212 */ "GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64\000"
2458 /* 256 */ "GR64_NOREX_and_GR64_TCW64\000"
2459 /* 282 */ "GR64PLTSafe_and_GR64_TCW64\000"
2460 /* 309 */ "VK4\000"
2461 /* 313 */ "VR512_0_15\000"
2462 /* 324 */ "GRH16\000"
2463 /* 330 */ "VK16\000"
2464 /* 335 */ "FR16\000"
2465 /* 340 */ "GR16\000"
2466 /* 345 */ "VR256\000"
2467 /* 351 */ "RFP80_7\000"
2468 /* 359 */ "VR128\000"
2469 /* 365 */ "GRH8\000"
2470 /* 370 */ "VK8\000"
2471 /* 374 */ "GR8\000"
2472 /* 378 */ "GR64_A\000"
2473 /* 385 */ "GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB\000"
2474 /* 432 */ "GR64_with_sub_32bit_in_GR32_CB\000"
2475 /* 463 */ "GR32_DC\000"
2476 /* 471 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC\000"
2477 /* 516 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC\000"
2478 /* 561 */ "GR64_with_sub_32bit_in_GR32_TC\000"
2479 /* 592 */ "GR64_NOREX2_NOSP_and_GR64_TC\000"
2480 /* 621 */ "GR64_NOREX_and_GR64_TC\000"
2481 /* 644 */ "GR64_NOREX_and_GR64PLTSafe_and_GR64_TC\000"
2482 /* 683 */ "GR64_ArgRef_and_GR64_TC\000"
2483 /* 707 */ "GR32_AD\000"
2484 /* 715 */ "GR64_AD\000"
2485 /* 723 */ "GR32_ABCD\000"
2486 /* 733 */ "GR64_ABCD\000"
2487 /* 743 */ "GR16_ABCD\000"
2488 /* 753 */ "TILE\000"
2489 /* 758 */ "DEBUG_REG\000"
2490 /* 768 */ "CONTROL_REG\000"
2491 /* 780 */ "SEGMENT_REG\000"
2492 /* 792 */ "GR8_ABCD_H\000"
2493 /* 803 */ "GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI\000"
2494 /* 849 */ "GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI\000"
2495 /* 896 */ "GR64_with_sub_32bit_in_GR32_SIDI\000"
2496 /* 929 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI\000"
2497 /* 975 */ "GR64_with_sub_32bit_in_GR32_BSI\000"
2498 /* 1007 */ "GR8_ABCD_L\000"
2499 /* 1018 */ "VK1PAIR_with_sub_mask_0_in_VK1WM\000"
2500 /* 1051 */ "VK32WM\000"
2501 /* 1058 */ "VK2WM\000"
2502 /* 1064 */ "VK64WM\000"
2503 /* 1071 */ "VK4WM\000"
2504 /* 1077 */ "VK16WM\000"
2505 /* 1084 */ "VK8WM\000"
2506 /* 1090 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP\000"
2507 /* 1137 */ "GR64_with_sub_32bit_in_GR32_DIBP\000"
2508 /* 1170 */ "GR64_and_LOW32_ADDR_ACCESS_RBP\000"
2509 /* 1201 */ "GR32_NOSP\000"
2510 /* 1211 */ "GR32_NOREX2_NOSP\000"
2511 /* 1228 */ "GR64_NOREX2_NOSP\000"
2512 /* 1245 */ "GR64_NOSP\000"
2513 /* 1255 */ "GR32_NOREX_NOSP\000"
2514 /* 1271 */ "GR64_NOREX_NOSP\000"
2515 /* 1287 */ "GR64_with_sub_32bit_in_GR32_BPSP\000"
2516 /* 1320 */ "DFCCR\000"
2517 /* 1326 */ "FPCCR\000"
2518 /* 1332 */ "VK1PAIR\000"
2519 /* 1340 */ "VK2PAIR\000"
2520 /* 1348 */ "VK4PAIR\000"
2521 /* 1356 */ "VK16PAIR\000"
2522 /* 1365 */ "VK8PAIR\000"
2523 /* 1373 */ "GR64_and_LOW32_ADDR_ACCESS\000"
2524 /* 1400 */ "RST\000"
2525 /* 1404 */ "FR32X\000"
2526 /* 1410 */ "FR64X\000"
2527 /* 1416 */ "FR16X\000"
2528 /* 1422 */ "VR256X\000"
2529 /* 1429 */ "VR128X\000"
2530 /* 1436 */ "GR32_NOREX\000"
2531 /* 1447 */ "GR64_NOREX\000"
2532 /* 1458 */ "GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX\000"
2533 /* 1504 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX\000"
2534 /* 1555 */ "GR8_NOREX\000"
2535 /* 1565 */ "GR64PLTSafe\000"
2536 /* 1577 */ "GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef\000"
2537 /* 1624 */ "GR64_with_sub_32bit_in_GR32_ArgRef\000"
2538 /* 1659 */ "GR64_ArgRef\000"
2539 /* 1671 */ "LOW32_ADDR_ACCESS_RBP_with_sub_32bit\000"
2540 /* 1708 */ "LOW32_ADDR_ACCESS_with_sub_32bit\000"
2541 /* 1741 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit\000"
2542 /* 1792 */ "GR64_with_sub_8bit\000"
2543 /* 1811 */ "GR64_TCW64_with_sub_8bit\000"
2544 /* 1836 */ "GR64_TCW64_and_GR64_TC_with_sub_8bit\000"
2545 /* 1873 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit\000"
2546};
2547#ifdef __GNUC__
2548#pragma GCC diagnostic pop
2549#endif
2550
2551extern const MCRegisterClass X86MCRegisterClasses[] = {
2552 { .RegsBegin: GR8, .RegSet: GR8Bits, .NameIdx: 374, .RegsSize: 36, .RegSetSize: sizeof(GR8Bits), .ID: X86::GR8RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2553 { .RegsBegin: GRH8, .RegSet: GRH8Bits, .NameIdx: 365, .RegsSize: 28, .RegSetSize: sizeof(GRH8Bits), .ID: X86::GRH8RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2554 { .RegsBegin: GR8_NOREX2, .RegSet: GR8_NOREX2Bits, .NameIdx: 152, .RegsSize: 20, .RegSetSize: sizeof(GR8_NOREX2Bits), .ID: X86::GR8_NOREX2RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2555 { .RegsBegin: GR8_NOREX, .RegSet: GR8_NOREXBits, .NameIdx: 1555, .RegsSize: 8, .RegSetSize: sizeof(GR8_NOREXBits), .ID: X86::GR8_NOREXRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2556 { .RegsBegin: GR8_ABCD_H, .RegSet: GR8_ABCD_HBits, .NameIdx: 792, .RegsSize: 4, .RegSetSize: sizeof(GR8_ABCD_HBits), .ID: X86::GR8_ABCD_HRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2557 { .RegsBegin: GR8_ABCD_L, .RegSet: GR8_ABCD_LBits, .NameIdx: 1007, .RegsSize: 4, .RegSetSize: sizeof(GR8_ABCD_LBits), .ID: X86::GR8_ABCD_LRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2558 { .RegsBegin: GRH16, .RegSet: GRH16Bits, .NameIdx: 324, .RegsSize: 33, .RegSetSize: sizeof(GRH16Bits), .ID: X86::GRH16RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2559 { .RegsBegin: GR16, .RegSet: GR16Bits, .NameIdx: 340, .RegsSize: 32, .RegSetSize: sizeof(GR16Bits), .ID: X86::GR16RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2560 { .RegsBegin: GR16_NOREX2, .RegSet: GR16_NOREX2Bits, .NameIdx: 88, .RegsSize: 16, .RegSetSize: sizeof(GR16_NOREX2Bits), .ID: X86::GR16_NOREX2RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2561 { .RegsBegin: GR16_NOREX, .RegSet: GR16_NOREXBits, .NameIdx: 1493, .RegsSize: 8, .RegSetSize: sizeof(GR16_NOREXBits), .ID: X86::GR16_NOREXRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2562 { .RegsBegin: VK1, .RegSet: VK1Bits, .NameIdx: 6, .RegsSize: 8, .RegSetSize: sizeof(VK1Bits), .ID: X86::VK1RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2563 { .RegsBegin: VK16, .RegSet: VK16Bits, .NameIdx: 330, .RegsSize: 8, .RegSetSize: sizeof(VK16Bits), .ID: X86::VK16RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2564 { .RegsBegin: VK2, .RegSet: VK2Bits, .NameIdx: 37, .RegsSize: 8, .RegSetSize: sizeof(VK2Bits), .ID: X86::VK2RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2565 { .RegsBegin: VK4, .RegSet: VK4Bits, .NameIdx: 309, .RegsSize: 8, .RegSetSize: sizeof(VK4Bits), .ID: X86::VK4RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2566 { .RegsBegin: VK8, .RegSet: VK8Bits, .NameIdx: 370, .RegsSize: 8, .RegSetSize: sizeof(VK8Bits), .ID: X86::VK8RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2567 { .RegsBegin: VK16WM, .RegSet: VK16WMBits, .NameIdx: 1077, .RegsSize: 7, .RegSetSize: sizeof(VK16WMBits), .ID: X86::VK16WMRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2568 { .RegsBegin: VK1WM, .RegSet: VK1WMBits, .NameIdx: 1045, .RegsSize: 7, .RegSetSize: sizeof(VK1WMBits), .ID: X86::VK1WMRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2569 { .RegsBegin: VK2WM, .RegSet: VK2WMBits, .NameIdx: 1058, .RegsSize: 7, .RegSetSize: sizeof(VK2WMBits), .ID: X86::VK2WMRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2570 { .RegsBegin: VK4WM, .RegSet: VK4WMBits, .NameIdx: 1071, .RegsSize: 7, .RegSetSize: sizeof(VK4WMBits), .ID: X86::VK4WMRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2571 { .RegsBegin: VK8WM, .RegSet: VK8WMBits, .NameIdx: 1084, .RegsSize: 7, .RegSetSize: sizeof(VK8WMBits), .ID: X86::VK8WMRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2572 { .RegsBegin: SEGMENT_REG, .RegSet: SEGMENT_REGBits, .NameIdx: 780, .RegsSize: 6, .RegSetSize: sizeof(SEGMENT_REGBits), .ID: X86::SEGMENT_REGRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2573 { .RegsBegin: GR16_ABCD, .RegSet: GR16_ABCDBits, .NameIdx: 743, .RegsSize: 4, .RegSetSize: sizeof(GR16_ABCDBits), .ID: X86::GR16_ABCDRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2574 { .RegsBegin: FPCCR, .RegSet: FPCCRBits, .NameIdx: 1326, .RegsSize: 1, .RegSetSize: sizeof(FPCCRBits), .ID: X86::FPCCRRegClassID, .RegSizeInBits: 16, .CopyCost: 255, .Allocatable: false, .BaseClass: false },
2575 { .RegsBegin: FR16X, .RegSet: FR16XBits, .NameIdx: 1416, .RegsSize: 32, .RegSetSize: sizeof(FR16XBits), .ID: X86::FR16XRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2576 { .RegsBegin: FR16, .RegSet: FR16Bits, .NameIdx: 335, .RegsSize: 16, .RegSetSize: sizeof(FR16Bits), .ID: X86::FR16RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2577 { .RegsBegin: VK16PAIR, .RegSet: VK16PAIRBits, .NameIdx: 1356, .RegsSize: 4, .RegSetSize: sizeof(VK16PAIRBits), .ID: X86::VK16PAIRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2578 { .RegsBegin: VK1PAIR, .RegSet: VK1PAIRBits, .NameIdx: 1332, .RegsSize: 4, .RegSetSize: sizeof(VK1PAIRBits), .ID: X86::VK1PAIRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2579 { .RegsBegin: VK2PAIR, .RegSet: VK2PAIRBits, .NameIdx: 1340, .RegsSize: 4, .RegSetSize: sizeof(VK2PAIRBits), .ID: X86::VK2PAIRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2580 { .RegsBegin: VK4PAIR, .RegSet: VK4PAIRBits, .NameIdx: 1348, .RegsSize: 4, .RegSetSize: sizeof(VK4PAIRBits), .ID: X86::VK4PAIRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2581 { .RegsBegin: VK8PAIR, .RegSet: VK8PAIRBits, .NameIdx: 1365, .RegsSize: 4, .RegSetSize: sizeof(VK8PAIRBits), .ID: X86::VK8PAIRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2582 { .RegsBegin: VK1PAIR_with_sub_mask_0_in_VK1WM, .RegSet: VK1PAIR_with_sub_mask_0_in_VK1WMBits, .NameIdx: 1018, .RegsSize: 3, .RegSetSize: sizeof(VK1PAIR_with_sub_mask_0_in_VK1WMBits), .ID: X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2583 { .RegsBegin: LOW32_ADDR_ACCESS_RBP, .RegSet: LOW32_ADDR_ACCESS_RBPBits, .NameIdx: 1179, .RegsSize: 34, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_RBPBits), .ID: X86::LOW32_ADDR_ACCESS_RBPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2584 { .RegsBegin: LOW32_ADDR_ACCESS, .RegSet: LOW32_ADDR_ACCESSBits, .NameIdx: 1382, .RegsSize: 33, .RegSetSize: sizeof(LOW32_ADDR_ACCESSBits), .ID: X86::LOW32_ADDR_ACCESSRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2585 { .RegsBegin: LOW32_ADDR_ACCESS_RBP_with_sub_8bit, .RegSet: LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, .NameIdx: 1873, .RegsSize: 33, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits), .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2586 { .RegsBegin: FR32X, .RegSet: FR32XBits, .NameIdx: 1404, .RegsSize: 32, .RegSetSize: sizeof(FR32XBits), .ID: X86::FR32XRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2587 { .RegsBegin: GR32, .RegSet: GR32Bits, .NameIdx: 32, .RegsSize: 32, .RegSetSize: sizeof(GR32Bits), .ID: X86::GR32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2588 { .RegsBegin: GR32_NOSP, .RegSet: GR32_NOSPBits, .NameIdx: 1201, .RegsSize: 31, .RegSetSize: sizeof(GR32_NOSPBits), .ID: X86::GR32_NOSPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2589 { .RegsBegin: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2, .RegSet: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits, .NameIdx: 100, .RegsSize: 17, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits), .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2590 { .RegsBegin: DEBUG_REG, .RegSet: DEBUG_REGBits, .NameIdx: 758, .RegsSize: 16, .RegSetSize: sizeof(DEBUG_REGBits), .ID: X86::DEBUG_REGRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2591 { .RegsBegin: FR32, .RegSet: FR32Bits, .NameIdx: 27, .RegsSize: 16, .RegSetSize: sizeof(FR32Bits), .ID: X86::FR32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2592 { .RegsBegin: GR32_NOREX2, .RegSet: GR32_NOREX2Bits, .NameIdx: 41, .RegsSize: 16, .RegSetSize: sizeof(GR32_NOREX2Bits), .ID: X86::GR32_NOREX2RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2593 { .RegsBegin: GR32_NOREX2_NOSP, .RegSet: GR32_NOREX2_NOSPBits, .NameIdx: 1211, .RegsSize: 15, .RegSetSize: sizeof(GR32_NOREX2_NOSPBits), .ID: X86::GR32_NOREX2_NOSPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2594 { .RegsBegin: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, .RegSet: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, .NameIdx: 1504, .RegsSize: 9, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits), .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2595 { .RegsBegin: GR32_NOREX, .RegSet: GR32_NOREXBits, .NameIdx: 1436, .RegsSize: 8, .RegSetSize: sizeof(GR32_NOREXBits), .ID: X86::GR32_NOREXRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2596 { .RegsBegin: VK32, .RegSet: VK32Bits, .NameIdx: 16, .RegsSize: 8, .RegSetSize: sizeof(VK32Bits), .ID: X86::VK32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2597 { .RegsBegin: GR32_NOREX_NOSP, .RegSet: GR32_NOREX_NOSPBits, .NameIdx: 1255, .RegsSize: 7, .RegSetSize: sizeof(GR32_NOREX_NOSPBits), .ID: X86::GR32_NOREX_NOSPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2598 { .RegsBegin: RFP32, .RegSet: RFP32Bits, .NameIdx: 21, .RegsSize: 7, .RegSetSize: sizeof(RFP32Bits), .ID: X86::RFP32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2599 { .RegsBegin: VK32WM, .RegSet: VK32WMBits, .NameIdx: 1051, .RegsSize: 7, .RegSetSize: sizeof(VK32WMBits), .ID: X86::VK32WMRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2600 { .RegsBegin: GR32_ABCD, .RegSet: GR32_ABCDBits, .NameIdx: 723, .RegsSize: 4, .RegSetSize: sizeof(GR32_ABCDBits), .ID: X86::GR32_ABCDRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2601 { .RegsBegin: GR32_TC, .RegSet: GR32_TCBits, .NameIdx: 508, .RegsSize: 4, .RegSetSize: sizeof(GR32_TCBits), .ID: X86::GR32_TCRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2602 { .RegsBegin: GR32_ABCD_and_GR32_TC, .RegSet: GR32_ABCD_and_GR32_TCBits, .NameIdx: 494, .RegsSize: 3, .RegSetSize: sizeof(GR32_ABCD_and_GR32_TCBits), .ID: X86::GR32_ABCD_and_GR32_TCRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2603 { .RegsBegin: GR32_AD, .RegSet: GR32_ADBits, .NameIdx: 707, .RegsSize: 2, .RegSetSize: sizeof(GR32_ADBits), .ID: X86::GR32_ADRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2604 { .RegsBegin: GR32_ArgRef, .RegSet: GR32_ArgRefBits, .NameIdx: 1612, .RegsSize: 2, .RegSetSize: sizeof(GR32_ArgRefBits), .ID: X86::GR32_ArgRefRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2605 { .RegsBegin: GR32_BPSP, .RegSet: GR32_BPSPBits, .NameIdx: 1310, .RegsSize: 2, .RegSetSize: sizeof(GR32_BPSPBits), .ID: X86::GR32_BPSPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2606 { .RegsBegin: GR32_BSI, .RegSet: GR32_BSIBits, .NameIdx: 966, .RegsSize: 2, .RegSetSize: sizeof(GR32_BSIBits), .ID: X86::GR32_BSIRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2607 { .RegsBegin: GR32_CB, .RegSet: GR32_CBBits, .NameIdx: 424, .RegsSize: 2, .RegSetSize: sizeof(GR32_CBBits), .ID: X86::GR32_CBRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2608 { .RegsBegin: GR32_DC, .RegSet: GR32_DCBits, .NameIdx: 463, .RegsSize: 2, .RegSetSize: sizeof(GR32_DCBits), .ID: X86::GR32_DCRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2609 { .RegsBegin: GR32_DIBP, .RegSet: GR32_DIBPBits, .NameIdx: 1127, .RegsSize: 2, .RegSetSize: sizeof(GR32_DIBPBits), .ID: X86::GR32_DIBPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2610 { .RegsBegin: GR32_SIDI, .RegSet: GR32_SIDIBits, .NameIdx: 839, .RegsSize: 2, .RegSetSize: sizeof(GR32_SIDIBits), .ID: X86::GR32_SIDIRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2611 { .RegsBegin: LOW32_ADDR_ACCESS_RBP_with_sub_32bit, .RegSet: LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, .NameIdx: 1671, .RegsSize: 2, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits), .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2612 { .RegsBegin: CCR, .RegSet: CCRBits, .NameIdx: 1322, .RegsSize: 1, .RegSetSize: sizeof(CCRBits), .ID: X86::CCRRegClassID, .RegSizeInBits: 32, .CopyCost: 255, .Allocatable: false, .BaseClass: false },
2613 { .RegsBegin: DFCCR, .RegSet: DFCCRBits, .NameIdx: 1320, .RegsSize: 1, .RegSetSize: sizeof(DFCCRBits), .ID: X86::DFCCRRegClassID, .RegSizeInBits: 32, .CopyCost: 255, .Allocatable: false, .BaseClass: false },
2614 { .RegsBegin: GR32_ABCD_and_GR32_BSI, .RegSet: GR32_ABCD_and_GR32_BSIBits, .NameIdx: 952, .RegsSize: 1, .RegSetSize: sizeof(GR32_ABCD_and_GR32_BSIBits), .ID: X86::GR32_ABCD_and_GR32_BSIRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2615 { .RegsBegin: GR32_AD_and_GR32_ArgRef, .RegSet: GR32_AD_and_GR32_ArgRefBits, .NameIdx: 1600, .RegsSize: 1, .RegSetSize: sizeof(GR32_AD_and_GR32_ArgRefBits), .ID: X86::GR32_AD_and_GR32_ArgRefRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2616 { .RegsBegin: GR32_ArgRef_and_GR32_CB, .RegSet: GR32_ArgRef_and_GR32_CBBits, .NameIdx: 408, .RegsSize: 1, .RegSetSize: sizeof(GR32_ArgRef_and_GR32_CBBits), .ID: X86::GR32_ArgRef_and_GR32_CBRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2617 { .RegsBegin: GR32_BPSP_and_GR32_DIBP, .RegSet: GR32_BPSP_and_GR32_DIBPBits, .NameIdx: 1113, .RegsSize: 1, .RegSetSize: sizeof(GR32_BPSP_and_GR32_DIBPBits), .ID: X86::GR32_BPSP_and_GR32_DIBPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2618 { .RegsBegin: GR32_BPSP_and_GR32_TC, .RegSet: GR32_BPSP_and_GR32_TCBits, .NameIdx: 539, .RegsSize: 1, .RegSetSize: sizeof(GR32_BPSP_and_GR32_TCBits), .ID: X86::GR32_BPSP_and_GR32_TCRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2619 { .RegsBegin: GR32_BSI_and_GR32_SIDI, .RegSet: GR32_BSI_and_GR32_SIDIBits, .NameIdx: 826, .RegsSize: 1, .RegSetSize: sizeof(GR32_BSI_and_GR32_SIDIBits), .ID: X86::GR32_BSI_and_GR32_SIDIRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2620 { .RegsBegin: GR32_DIBP_and_GR32_SIDI, .RegSet: GR32_DIBP_and_GR32_SIDIBits, .NameIdx: 872, .RegsSize: 1, .RegSetSize: sizeof(GR32_DIBP_and_GR32_SIDIBits), .ID: X86::GR32_DIBP_and_GR32_SIDIRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2621 { .RegsBegin: LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, .RegSet: LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, .NameIdx: 1741, .RegsSize: 1, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits), .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2622 { .RegsBegin: LOW32_ADDR_ACCESS_with_sub_32bit, .RegSet: LOW32_ADDR_ACCESS_with_sub_32bitBits, .NameIdx: 1708, .RegsSize: 1, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits), .ID: X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2623 { .RegsBegin: RFP64, .RegSet: RFP64Bits, .NameIdx: 168, .RegsSize: 7, .RegSetSize: sizeof(RFP64Bits), .ID: X86::RFP64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2624 { .RegsBegin: GR64, .RegSet: GR64Bits, .NameIdx: 179, .RegsSize: 33, .RegSetSize: sizeof(GR64Bits), .ID: X86::GR64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2625 { .RegsBegin: FR64X, .RegSet: FR64XBits, .NameIdx: 1410, .RegsSize: 32, .RegSetSize: sizeof(FR64XBits), .ID: X86::FR64XRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2626 { .RegsBegin: GR64_with_sub_8bit, .RegSet: GR64_with_sub_8bitBits, .NameIdx: 1792, .RegsSize: 32, .RegSetSize: sizeof(GR64_with_sub_8bitBits), .ID: X86::GR64_with_sub_8bitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2627 { .RegsBegin: GR64_NOSP, .RegSet: GR64_NOSPBits, .NameIdx: 1245, .RegsSize: 31, .RegSetSize: sizeof(GR64_NOSPBits), .ID: X86::GR64_NOSPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2628 { .RegsBegin: GR64_NOREX2, .RegSet: GR64_NOREX2Bits, .NameIdx: 53, .RegsSize: 17, .RegSetSize: sizeof(GR64_NOREX2Bits), .ID: X86::GR64_NOREX2RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2629 { .RegsBegin: CONTROL_REG, .RegSet: CONTROL_REGBits, .NameIdx: 768, .RegsSize: 16, .RegSetSize: sizeof(CONTROL_REGBits), .ID: X86::CONTROL_REGRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2630 { .RegsBegin: FR64, .RegSet: FR64Bits, .NameIdx: 174, .RegsSize: 16, .RegSetSize: sizeof(FR64Bits), .ID: X86::FR64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2631 { .RegsBegin: GR64_with_sub_16bit_in_GR16_NOREX2, .RegSet: GR64_with_sub_16bit_in_GR16_NOREX2Bits, .NameIdx: 65, .RegsSize: 16, .RegSetSize: sizeof(GR64_with_sub_16bit_in_GR16_NOREX2Bits), .ID: X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2632 { .RegsBegin: GR64_NOREX2_NOSP, .RegSet: GR64_NOREX2_NOSPBits, .NameIdx: 1228, .RegsSize: 15, .RegSetSize: sizeof(GR64_NOREX2_NOSPBits), .ID: X86::GR64_NOREX2_NOSPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2633 { .RegsBegin: GR64PLTSafe, .RegSet: GR64PLTSafeBits, .NameIdx: 1565, .RegsSize: 13, .RegSetSize: sizeof(GR64PLTSafeBits), .ID: X86::GR64PLTSafeRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2634 { .RegsBegin: GR64_TC, .RegSet: GR64_TCBits, .NameIdx: 613, .RegsSize: 10, .RegSetSize: sizeof(GR64_TCBits), .ID: X86::GR64_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2635 { .RegsBegin: GR64_NOREX, .RegSet: GR64_NOREXBits, .NameIdx: 1447, .RegsSize: 9, .RegSetSize: sizeof(GR64_NOREXBits), .ID: X86::GR64_NOREXRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2636 { .RegsBegin: GR64_TCW64, .RegSet: GR64_TCW64Bits, .NameIdx: 201, .RegsSize: 9, .RegSetSize: sizeof(GR64_TCW64Bits), .ID: X86::GR64_TCW64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2637 { .RegsBegin: GR64_TC_with_sub_8bit, .RegSet: GR64_TC_with_sub_8bitBits, .NameIdx: 1851, .RegsSize: 9, .RegSetSize: sizeof(GR64_TC_with_sub_8bitBits), .ID: X86::GR64_TC_with_sub_8bitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2638 { .RegsBegin: GR64_NOREX2_NOSP_and_GR64_TC, .RegSet: GR64_NOREX2_NOSP_and_GR64_TCBits, .NameIdx: 592, .RegsSize: 8, .RegSetSize: sizeof(GR64_NOREX2_NOSP_and_GR64_TCBits), .ID: X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2639 { .RegsBegin: GR64_TCW64_with_sub_8bit, .RegSet: GR64_TCW64_with_sub_8bitBits, .NameIdx: 1811, .RegsSize: 8, .RegSetSize: sizeof(GR64_TCW64_with_sub_8bitBits), .ID: X86::GR64_TCW64_with_sub_8bitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2640 { .RegsBegin: GR64_TC_and_GR64_TCW64, .RegSet: GR64_TC_and_GR64_TCW64Bits, .NameIdx: 189, .RegsSize: 8, .RegSetSize: sizeof(GR64_TC_and_GR64_TCW64Bits), .ID: X86::GR64_TC_and_GR64_TCW64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2641 { .RegsBegin: GR64_with_sub_16bit_in_GR16_NOREX, .RegSet: GR64_with_sub_16bit_in_GR16_NOREXBits, .NameIdx: 1470, .RegsSize: 8, .RegSetSize: sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits), .ID: X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2642 { .RegsBegin: VK64, .RegSet: VK64Bits, .NameIdx: 163, .RegsSize: 8, .RegSetSize: sizeof(VK64Bits), .ID: X86::VK64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2643 { .RegsBegin: VR64, .RegSet: VR64Bits, .NameIdx: 184, .RegsSize: 8, .RegSetSize: sizeof(VR64Bits), .ID: X86::VR64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2644 { .RegsBegin: GR64PLTSafe_and_GR64_TC, .RegSet: GR64PLTSafe_and_GR64_TCBits, .NameIdx: 659, .RegsSize: 7, .RegSetSize: sizeof(GR64PLTSafe_and_GR64_TCBits), .ID: X86::GR64PLTSafe_and_GR64_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2645 { .RegsBegin: GR64_NOREX2_NOSP_and_GR64_TCW64, .RegSet: GR64_NOREX2_NOSP_and_GR64_TCW64Bits, .NameIdx: 224, .RegsSize: 7, .RegSetSize: sizeof(GR64_NOREX2_NOSP_and_GR64_TCW64Bits), .ID: X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2646 { .RegsBegin: GR64_NOREX_NOSP, .RegSet: GR64_NOREX_NOSPBits, .NameIdx: 1271, .RegsSize: 7, .RegSetSize: sizeof(GR64_NOREX_NOSPBits), .ID: X86::GR64_NOREX_NOSPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2647 { .RegsBegin: GR64_NOREX_and_GR64_TC, .RegSet: GR64_NOREX_and_GR64_TCBits, .NameIdx: 621, .RegsSize: 7, .RegSetSize: sizeof(GR64_NOREX_and_GR64_TCBits), .ID: X86::GR64_NOREX_and_GR64_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2648 { .RegsBegin: GR64_TCW64_and_GR64_TC_with_sub_8bit, .RegSet: GR64_TCW64_and_GR64_TC_with_sub_8bitBits, .NameIdx: 1836, .RegsSize: 7, .RegSetSize: sizeof(GR64_TCW64_and_GR64_TC_with_sub_8bitBits), .ID: X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2649 { .RegsBegin: VK64WM, .RegSet: VK64WMBits, .NameIdx: 1064, .RegsSize: 7, .RegSetSize: sizeof(VK64WMBits), .ID: X86::VK64WMRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2650 { .RegsBegin: GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64, .RegSet: GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits, .NameIdx: 212, .RegsSize: 6, .RegSetSize: sizeof(GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits), .ID: X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2651 { .RegsBegin: GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX, .RegSet: GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits, .NameIdx: 1458, .RegsSize: 6, .RegSetSize: sizeof(GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits), .ID: X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2652 { .RegsBegin: GR64PLTSafe_and_GR64_TCW64, .RegSet: GR64PLTSafe_and_GR64_TCW64Bits, .NameIdx: 282, .RegsSize: 5, .RegSetSize: sizeof(GR64PLTSafe_and_GR64_TCW64Bits), .ID: X86::GR64PLTSafe_and_GR64_TCW64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2653 { .RegsBegin: GR64_NOREX_and_GR64PLTSafe_and_GR64_TC, .RegSet: GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits, .NameIdx: 644, .RegsSize: 5, .RegSetSize: sizeof(GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits), .ID: X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2654 { .RegsBegin: GR64_NOREX_and_GR64_TCW64, .RegSet: GR64_NOREX_and_GR64_TCW64Bits, .NameIdx: 256, .RegsSize: 5, .RegSetSize: sizeof(GR64_NOREX_and_GR64_TCW64Bits), .ID: X86::GR64_NOREX_and_GR64_TCW64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2655 { .RegsBegin: GR64_ABCD, .RegSet: GR64_ABCDBits, .NameIdx: 733, .RegsSize: 4, .RegSetSize: sizeof(GR64_ABCDBits), .ID: X86::GR64_ABCDRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2656 { .RegsBegin: GR64_with_sub_32bit_in_GR32_TC, .RegSet: GR64_with_sub_32bit_in_GR32_TCBits, .NameIdx: 561, .RegsSize: 4, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_TCBits), .ID: X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2657 { .RegsBegin: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC, .RegSet: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits, .NameIdx: 471, .RegsSize: 3, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits), .ID: X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2658 { .RegsBegin: GR64_AD, .RegSet: GR64_ADBits, .NameIdx: 715, .RegsSize: 2, .RegSetSize: sizeof(GR64_ADBits), .ID: X86::GR64_ADRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2659 { .RegsBegin: GR64_ArgRef, .RegSet: GR64_ArgRefBits, .NameIdx: 1659, .RegsSize: 2, .RegSetSize: sizeof(GR64_ArgRefBits), .ID: X86::GR64_ArgRefRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2660 { .RegsBegin: GR64_and_LOW32_ADDR_ACCESS_RBP, .RegSet: GR64_and_LOW32_ADDR_ACCESS_RBPBits, .NameIdx: 1170, .RegsSize: 2, .RegSetSize: sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits), .ID: X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2661 { .RegsBegin: GR64_with_sub_32bit_in_GR32_ArgRef, .RegSet: GR64_with_sub_32bit_in_GR32_ArgRefBits, .NameIdx: 1624, .RegsSize: 2, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_ArgRefBits), .ID: X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2662 { .RegsBegin: GR64_with_sub_32bit_in_GR32_BPSP, .RegSet: GR64_with_sub_32bit_in_GR32_BPSPBits, .NameIdx: 1287, .RegsSize: 2, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_BPSPBits), .ID: X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2663 { .RegsBegin: GR64_with_sub_32bit_in_GR32_BSI, .RegSet: GR64_with_sub_32bit_in_GR32_BSIBits, .NameIdx: 975, .RegsSize: 2, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_BSIBits), .ID: X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2664 { .RegsBegin: GR64_with_sub_32bit_in_GR32_CB, .RegSet: GR64_with_sub_32bit_in_GR32_CBBits, .NameIdx: 432, .RegsSize: 2, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_CBBits), .ID: X86::GR64_with_sub_32bit_in_GR32_CBRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2665 { .RegsBegin: GR64_with_sub_32bit_in_GR32_DIBP, .RegSet: GR64_with_sub_32bit_in_GR32_DIBPBits, .NameIdx: 1137, .RegsSize: 2, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_DIBPBits), .ID: X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2666 { .RegsBegin: GR64_with_sub_32bit_in_GR32_SIDI, .RegSet: GR64_with_sub_32bit_in_GR32_SIDIBits, .NameIdx: 896, .RegsSize: 2, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_SIDIBits), .ID: X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2667 { .RegsBegin: GR64_A, .RegSet: GR64_ABits, .NameIdx: 378, .RegsSize: 1, .RegSetSize: sizeof(GR64_ABits), .ID: X86::GR64_ARegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2668 { .RegsBegin: GR64_ArgRef_and_GR64_TC, .RegSet: GR64_ArgRef_and_GR64_TCBits, .NameIdx: 683, .RegsSize: 1, .RegSetSize: sizeof(GR64_ArgRef_and_GR64_TCBits), .ID: X86::GR64_ArgRef_and_GR64_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2669 { .RegsBegin: GR64_and_LOW32_ADDR_ACCESS, .RegSet: GR64_and_LOW32_ADDR_ACCESSBits, .NameIdx: 1373, .RegsSize: 1, .RegSetSize: sizeof(GR64_and_LOW32_ADDR_ACCESSBits), .ID: X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2670 { .RegsBegin: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI, .RegSet: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits, .NameIdx: 929, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits), .ID: X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2671 { .RegsBegin: GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef, .RegSet: GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits, .NameIdx: 1577, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits), .ID: X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2672 { .RegsBegin: GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB, .RegSet: GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits, .NameIdx: 385, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits), .ID: X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2673 { .RegsBegin: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP, .RegSet: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits, .NameIdx: 1090, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits), .ID: X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2674 { .RegsBegin: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC, .RegSet: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits, .NameIdx: 516, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits), .ID: X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2675 { .RegsBegin: GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI, .RegSet: GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits, .NameIdx: 803, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits), .ID: X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2676 { .RegsBegin: GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI, .RegSet: GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits, .NameIdx: 849, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits), .ID: X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2677 { .RegsBegin: RST, .RegSet: RSTBits, .NameIdx: 1400, .RegsSize: 8, .RegSetSize: sizeof(RSTBits), .ID: X86::RSTRegClassID, .RegSizeInBits: 80, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2678 { .RegsBegin: RFP80, .RegSet: RFP80Bits, .NameIdx: 0, .RegsSize: 7, .RegSetSize: sizeof(RFP80Bits), .ID: X86::RFP80RegClassID, .RegSizeInBits: 80, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2679 { .RegsBegin: RFP80_7, .RegSet: RFP80_7Bits, .NameIdx: 351, .RegsSize: 1, .RegSetSize: sizeof(RFP80_7Bits), .ID: X86::RFP80_7RegClassID, .RegSizeInBits: 80, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2680 { .RegsBegin: VR128X, .RegSet: VR128XBits, .NameIdx: 1429, .RegsSize: 32, .RegSetSize: sizeof(VR128XBits), .ID: X86::VR128XRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2681 { .RegsBegin: VR128, .RegSet: VR128Bits, .NameIdx: 359, .RegsSize: 16, .RegSetSize: sizeof(VR128Bits), .ID: X86::VR128RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2682 { .RegsBegin: VR256X, .RegSet: VR256XBits, .NameIdx: 1422, .RegsSize: 32, .RegSetSize: sizeof(VR256XBits), .ID: X86::VR256XRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2683 { .RegsBegin: VR256, .RegSet: VR256Bits, .NameIdx: 345, .RegsSize: 16, .RegSetSize: sizeof(VR256Bits), .ID: X86::VR256RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2684 { .RegsBegin: VR512, .RegSet: VR512Bits, .NameIdx: 10, .RegsSize: 32, .RegSetSize: sizeof(VR512Bits), .ID: X86::VR512RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2685 { .RegsBegin: VR512_0_15, .RegSet: VR512_0_15Bits, .NameIdx: 313, .RegsSize: 16, .RegSetSize: sizeof(VR512_0_15Bits), .ID: X86::VR512_0_15RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2686 { .RegsBegin: TILE, .RegSet: TILEBits, .NameIdx: 753, .RegsSize: 8, .RegSetSize: sizeof(TILEBits), .ID: X86::TILERegClassID, .RegSizeInBits: 8192, .CopyCost: 255, .Allocatable: true, .BaseClass: false },
2687};
2688
2689// X86 Dwarf<->LLVM register mappings.
2690extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
2691 { .FromReg: 0U, .ToReg: X86::RAX },
2692 { .FromReg: 1U, .ToReg: X86::RDX },
2693 { .FromReg: 2U, .ToReg: X86::RCX },
2694 { .FromReg: 3U, .ToReg: X86::RBX },
2695 { .FromReg: 4U, .ToReg: X86::RSI },
2696 { .FromReg: 5U, .ToReg: X86::RDI },
2697 { .FromReg: 6U, .ToReg: X86::RBP },
2698 { .FromReg: 7U, .ToReg: X86::RSP },
2699 { .FromReg: 8U, .ToReg: X86::R8 },
2700 { .FromReg: 9U, .ToReg: X86::R9 },
2701 { .FromReg: 10U, .ToReg: X86::R10 },
2702 { .FromReg: 11U, .ToReg: X86::R11 },
2703 { .FromReg: 12U, .ToReg: X86::R12 },
2704 { .FromReg: 13U, .ToReg: X86::R13 },
2705 { .FromReg: 14U, .ToReg: X86::R14 },
2706 { .FromReg: 15U, .ToReg: X86::R15 },
2707 { .FromReg: 16U, .ToReg: X86::RIP },
2708 { .FromReg: 17U, .ToReg: X86::XMM0 },
2709 { .FromReg: 18U, .ToReg: X86::XMM1 },
2710 { .FromReg: 19U, .ToReg: X86::XMM2 },
2711 { .FromReg: 20U, .ToReg: X86::XMM3 },
2712 { .FromReg: 21U, .ToReg: X86::XMM4 },
2713 { .FromReg: 22U, .ToReg: X86::XMM5 },
2714 { .FromReg: 23U, .ToReg: X86::XMM6 },
2715 { .FromReg: 24U, .ToReg: X86::XMM7 },
2716 { .FromReg: 25U, .ToReg: X86::XMM8 },
2717 { .FromReg: 26U, .ToReg: X86::XMM9 },
2718 { .FromReg: 27U, .ToReg: X86::XMM10 },
2719 { .FromReg: 28U, .ToReg: X86::XMM11 },
2720 { .FromReg: 29U, .ToReg: X86::XMM12 },
2721 { .FromReg: 30U, .ToReg: X86::XMM13 },
2722 { .FromReg: 31U, .ToReg: X86::XMM14 },
2723 { .FromReg: 32U, .ToReg: X86::XMM15 },
2724 { .FromReg: 33U, .ToReg: X86::ST0 },
2725 { .FromReg: 34U, .ToReg: X86::ST1 },
2726 { .FromReg: 35U, .ToReg: X86::ST2 },
2727 { .FromReg: 36U, .ToReg: X86::ST3 },
2728 { .FromReg: 37U, .ToReg: X86::ST4 },
2729 { .FromReg: 38U, .ToReg: X86::ST5 },
2730 { .FromReg: 39U, .ToReg: X86::ST6 },
2731 { .FromReg: 40U, .ToReg: X86::ST7 },
2732 { .FromReg: 41U, .ToReg: X86::MM0 },
2733 { .FromReg: 42U, .ToReg: X86::MM1 },
2734 { .FromReg: 43U, .ToReg: X86::MM2 },
2735 { .FromReg: 44U, .ToReg: X86::MM3 },
2736 { .FromReg: 45U, .ToReg: X86::MM4 },
2737 { .FromReg: 46U, .ToReg: X86::MM5 },
2738 { .FromReg: 47U, .ToReg: X86::MM6 },
2739 { .FromReg: 48U, .ToReg: X86::MM7 },
2740 { .FromReg: 49U, .ToReg: X86::RFLAGS },
2741 { .FromReg: 50U, .ToReg: X86::ES },
2742 { .FromReg: 51U, .ToReg: X86::CS },
2743 { .FromReg: 52U, .ToReg: X86::SS },
2744 { .FromReg: 53U, .ToReg: X86::DS },
2745 { .FromReg: 54U, .ToReg: X86::FS },
2746 { .FromReg: 55U, .ToReg: X86::GS },
2747 { .FromReg: 58U, .ToReg: X86::FS_BASE },
2748 { .FromReg: 59U, .ToReg: X86::GS_BASE },
2749 { .FromReg: 67U, .ToReg: X86::XMM16 },
2750 { .FromReg: 68U, .ToReg: X86::XMM17 },
2751 { .FromReg: 69U, .ToReg: X86::XMM18 },
2752 { .FromReg: 70U, .ToReg: X86::XMM19 },
2753 { .FromReg: 71U, .ToReg: X86::XMM20 },
2754 { .FromReg: 72U, .ToReg: X86::XMM21 },
2755 { .FromReg: 73U, .ToReg: X86::XMM22 },
2756 { .FromReg: 74U, .ToReg: X86::XMM23 },
2757 { .FromReg: 75U, .ToReg: X86::XMM24 },
2758 { .FromReg: 76U, .ToReg: X86::XMM25 },
2759 { .FromReg: 77U, .ToReg: X86::XMM26 },
2760 { .FromReg: 78U, .ToReg: X86::XMM27 },
2761 { .FromReg: 79U, .ToReg: X86::XMM28 },
2762 { .FromReg: 80U, .ToReg: X86::XMM29 },
2763 { .FromReg: 81U, .ToReg: X86::XMM30 },
2764 { .FromReg: 82U, .ToReg: X86::XMM31 },
2765 { .FromReg: 118U, .ToReg: X86::K0 },
2766 { .FromReg: 119U, .ToReg: X86::K1 },
2767 { .FromReg: 120U, .ToReg: X86::K2 },
2768 { .FromReg: 121U, .ToReg: X86::K3 },
2769 { .FromReg: 122U, .ToReg: X86::K4 },
2770 { .FromReg: 123U, .ToReg: X86::K5 },
2771 { .FromReg: 124U, .ToReg: X86::K6 },
2772 { .FromReg: 125U, .ToReg: X86::K7 },
2773 { .FromReg: 130U, .ToReg: X86::R16 },
2774 { .FromReg: 131U, .ToReg: X86::R17 },
2775 { .FromReg: 132U, .ToReg: X86::R18 },
2776 { .FromReg: 133U, .ToReg: X86::R19 },
2777 { .FromReg: 134U, .ToReg: X86::R20 },
2778 { .FromReg: 135U, .ToReg: X86::R21 },
2779 { .FromReg: 136U, .ToReg: X86::R22 },
2780 { .FromReg: 137U, .ToReg: X86::R23 },
2781 { .FromReg: 138U, .ToReg: X86::R24 },
2782 { .FromReg: 139U, .ToReg: X86::R25 },
2783 { .FromReg: 140U, .ToReg: X86::R26 },
2784 { .FromReg: 141U, .ToReg: X86::R27 },
2785 { .FromReg: 142U, .ToReg: X86::R28 },
2786 { .FromReg: 143U, .ToReg: X86::R29 },
2787 { .FromReg: 144U, .ToReg: X86::R30 },
2788 { .FromReg: 145U, .ToReg: X86::R31 },
2789};
2790extern const unsigned X86DwarfFlavour0Dwarf2LSize = std::size(X86DwarfFlavour0Dwarf2L);
2791
2792extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
2793 { .FromReg: 0U, .ToReg: X86::EAX },
2794 { .FromReg: 1U, .ToReg: X86::ECX },
2795 { .FromReg: 2U, .ToReg: X86::EDX },
2796 { .FromReg: 3U, .ToReg: X86::EBX },
2797 { .FromReg: 4U, .ToReg: X86::EBP },
2798 { .FromReg: 5U, .ToReg: X86::ESP },
2799 { .FromReg: 6U, .ToReg: X86::ESI },
2800 { .FromReg: 7U, .ToReg: X86::EDI },
2801 { .FromReg: 8U, .ToReg: X86::EIP },
2802 { .FromReg: 9U, .ToReg: X86::EFLAGS },
2803 { .FromReg: 12U, .ToReg: X86::ST0 },
2804 { .FromReg: 13U, .ToReg: X86::ST1 },
2805 { .FromReg: 14U, .ToReg: X86::ST2 },
2806 { .FromReg: 15U, .ToReg: X86::ST3 },
2807 { .FromReg: 16U, .ToReg: X86::ST4 },
2808 { .FromReg: 17U, .ToReg: X86::ST5 },
2809 { .FromReg: 18U, .ToReg: X86::ST6 },
2810 { .FromReg: 19U, .ToReg: X86::ST7 },
2811 { .FromReg: 21U, .ToReg: X86::XMM0 },
2812 { .FromReg: 22U, .ToReg: X86::XMM1 },
2813 { .FromReg: 23U, .ToReg: X86::XMM2 },
2814 { .FromReg: 24U, .ToReg: X86::XMM3 },
2815 { .FromReg: 25U, .ToReg: X86::XMM4 },
2816 { .FromReg: 26U, .ToReg: X86::XMM5 },
2817 { .FromReg: 27U, .ToReg: X86::XMM6 },
2818 { .FromReg: 28U, .ToReg: X86::XMM7 },
2819 { .FromReg: 29U, .ToReg: X86::MM0 },
2820 { .FromReg: 30U, .ToReg: X86::MM1 },
2821 { .FromReg: 31U, .ToReg: X86::MM2 },
2822 { .FromReg: 32U, .ToReg: X86::MM3 },
2823 { .FromReg: 33U, .ToReg: X86::MM4 },
2824 { .FromReg: 34U, .ToReg: X86::MM5 },
2825 { .FromReg: 35U, .ToReg: X86::MM6 },
2826 { .FromReg: 36U, .ToReg: X86::MM7 },
2827 { .FromReg: 93U, .ToReg: X86::K0 },
2828 { .FromReg: 94U, .ToReg: X86::K1 },
2829 { .FromReg: 95U, .ToReg: X86::K2 },
2830 { .FromReg: 96U, .ToReg: X86::K3 },
2831 { .FromReg: 97U, .ToReg: X86::K4 },
2832 { .FromReg: 98U, .ToReg: X86::K5 },
2833 { .FromReg: 99U, .ToReg: X86::K6 },
2834 { .FromReg: 100U, .ToReg: X86::K7 },
2835};
2836extern const unsigned X86DwarfFlavour1Dwarf2LSize = std::size(X86DwarfFlavour1Dwarf2L);
2837
2838extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
2839 { .FromReg: 0U, .ToReg: X86::EAX },
2840 { .FromReg: 1U, .ToReg: X86::ECX },
2841 { .FromReg: 2U, .ToReg: X86::EDX },
2842 { .FromReg: 3U, .ToReg: X86::EBX },
2843 { .FromReg: 4U, .ToReg: X86::ESP },
2844 { .FromReg: 5U, .ToReg: X86::EBP },
2845 { .FromReg: 6U, .ToReg: X86::ESI },
2846 { .FromReg: 7U, .ToReg: X86::EDI },
2847 { .FromReg: 8U, .ToReg: X86::EIP },
2848 { .FromReg: 9U, .ToReg: X86::EFLAGS },
2849 { .FromReg: 11U, .ToReg: X86::ST0 },
2850 { .FromReg: 12U, .ToReg: X86::ST1 },
2851 { .FromReg: 13U, .ToReg: X86::ST2 },
2852 { .FromReg: 14U, .ToReg: X86::ST3 },
2853 { .FromReg: 15U, .ToReg: X86::ST4 },
2854 { .FromReg: 16U, .ToReg: X86::ST5 },
2855 { .FromReg: 17U, .ToReg: X86::ST6 },
2856 { .FromReg: 18U, .ToReg: X86::ST7 },
2857 { .FromReg: 21U, .ToReg: X86::XMM0 },
2858 { .FromReg: 22U, .ToReg: X86::XMM1 },
2859 { .FromReg: 23U, .ToReg: X86::XMM2 },
2860 { .FromReg: 24U, .ToReg: X86::XMM3 },
2861 { .FromReg: 25U, .ToReg: X86::XMM4 },
2862 { .FromReg: 26U, .ToReg: X86::XMM5 },
2863 { .FromReg: 27U, .ToReg: X86::XMM6 },
2864 { .FromReg: 28U, .ToReg: X86::XMM7 },
2865 { .FromReg: 29U, .ToReg: X86::MM0 },
2866 { .FromReg: 30U, .ToReg: X86::MM1 },
2867 { .FromReg: 31U, .ToReg: X86::MM2 },
2868 { .FromReg: 32U, .ToReg: X86::MM3 },
2869 { .FromReg: 33U, .ToReg: X86::MM4 },
2870 { .FromReg: 34U, .ToReg: X86::MM5 },
2871 { .FromReg: 35U, .ToReg: X86::MM6 },
2872 { .FromReg: 36U, .ToReg: X86::MM7 },
2873 { .FromReg: 40U, .ToReg: X86::ES },
2874 { .FromReg: 41U, .ToReg: X86::CS },
2875 { .FromReg: 42U, .ToReg: X86::SS },
2876 { .FromReg: 43U, .ToReg: X86::DS },
2877 { .FromReg: 44U, .ToReg: X86::FS },
2878 { .FromReg: 45U, .ToReg: X86::GS },
2879 { .FromReg: 93U, .ToReg: X86::K0 },
2880 { .FromReg: 94U, .ToReg: X86::K1 },
2881 { .FromReg: 95U, .ToReg: X86::K2 },
2882 { .FromReg: 96U, .ToReg: X86::K3 },
2883 { .FromReg: 97U, .ToReg: X86::K4 },
2884 { .FromReg: 98U, .ToReg: X86::K5 },
2885 { .FromReg: 99U, .ToReg: X86::K6 },
2886 { .FromReg: 100U, .ToReg: X86::K7 },
2887};
2888extern const unsigned X86DwarfFlavour2Dwarf2LSize = std::size(X86DwarfFlavour2Dwarf2L);
2889
2890extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
2891 { .FromReg: 0U, .ToReg: X86::RAX },
2892 { .FromReg: 1U, .ToReg: X86::RDX },
2893 { .FromReg: 2U, .ToReg: X86::RCX },
2894 { .FromReg: 3U, .ToReg: X86::RBX },
2895 { .FromReg: 4U, .ToReg: X86::RSI },
2896 { .FromReg: 5U, .ToReg: X86::RDI },
2897 { .FromReg: 6U, .ToReg: X86::RBP },
2898 { .FromReg: 7U, .ToReg: X86::RSP },
2899 { .FromReg: 8U, .ToReg: X86::R8 },
2900 { .FromReg: 9U, .ToReg: X86::R9 },
2901 { .FromReg: 10U, .ToReg: X86::R10 },
2902 { .FromReg: 11U, .ToReg: X86::R11 },
2903 { .FromReg: 12U, .ToReg: X86::R12 },
2904 { .FromReg: 13U, .ToReg: X86::R13 },
2905 { .FromReg: 14U, .ToReg: X86::R14 },
2906 { .FromReg: 15U, .ToReg: X86::R15 },
2907 { .FromReg: 16U, .ToReg: X86::RIP },
2908 { .FromReg: 17U, .ToReg: X86::XMM0 },
2909 { .FromReg: 18U, .ToReg: X86::XMM1 },
2910 { .FromReg: 19U, .ToReg: X86::XMM2 },
2911 { .FromReg: 20U, .ToReg: X86::XMM3 },
2912 { .FromReg: 21U, .ToReg: X86::XMM4 },
2913 { .FromReg: 22U, .ToReg: X86::XMM5 },
2914 { .FromReg: 23U, .ToReg: X86::XMM6 },
2915 { .FromReg: 24U, .ToReg: X86::XMM7 },
2916 { .FromReg: 25U, .ToReg: X86::XMM8 },
2917 { .FromReg: 26U, .ToReg: X86::XMM9 },
2918 { .FromReg: 27U, .ToReg: X86::XMM10 },
2919 { .FromReg: 28U, .ToReg: X86::XMM11 },
2920 { .FromReg: 29U, .ToReg: X86::XMM12 },
2921 { .FromReg: 30U, .ToReg: X86::XMM13 },
2922 { .FromReg: 31U, .ToReg: X86::XMM14 },
2923 { .FromReg: 32U, .ToReg: X86::XMM15 },
2924 { .FromReg: 33U, .ToReg: X86::ST0 },
2925 { .FromReg: 34U, .ToReg: X86::ST1 },
2926 { .FromReg: 35U, .ToReg: X86::ST2 },
2927 { .FromReg: 36U, .ToReg: X86::ST3 },
2928 { .FromReg: 37U, .ToReg: X86::ST4 },
2929 { .FromReg: 38U, .ToReg: X86::ST5 },
2930 { .FromReg: 39U, .ToReg: X86::ST6 },
2931 { .FromReg: 40U, .ToReg: X86::ST7 },
2932 { .FromReg: 41U, .ToReg: X86::MM0 },
2933 { .FromReg: 42U, .ToReg: X86::MM1 },
2934 { .FromReg: 43U, .ToReg: X86::MM2 },
2935 { .FromReg: 44U, .ToReg: X86::MM3 },
2936 { .FromReg: 45U, .ToReg: X86::MM4 },
2937 { .FromReg: 46U, .ToReg: X86::MM5 },
2938 { .FromReg: 47U, .ToReg: X86::MM6 },
2939 { .FromReg: 48U, .ToReg: X86::MM7 },
2940 { .FromReg: 49U, .ToReg: X86::RFLAGS },
2941 { .FromReg: 50U, .ToReg: X86::ES },
2942 { .FromReg: 51U, .ToReg: X86::CS },
2943 { .FromReg: 52U, .ToReg: X86::SS },
2944 { .FromReg: 53U, .ToReg: X86::DS },
2945 { .FromReg: 54U, .ToReg: X86::FS },
2946 { .FromReg: 55U, .ToReg: X86::GS },
2947 { .FromReg: 58U, .ToReg: X86::FS_BASE },
2948 { .FromReg: 59U, .ToReg: X86::GS_BASE },
2949 { .FromReg: 67U, .ToReg: X86::XMM16 },
2950 { .FromReg: 68U, .ToReg: X86::XMM17 },
2951 { .FromReg: 69U, .ToReg: X86::XMM18 },
2952 { .FromReg: 70U, .ToReg: X86::XMM19 },
2953 { .FromReg: 71U, .ToReg: X86::XMM20 },
2954 { .FromReg: 72U, .ToReg: X86::XMM21 },
2955 { .FromReg: 73U, .ToReg: X86::XMM22 },
2956 { .FromReg: 74U, .ToReg: X86::XMM23 },
2957 { .FromReg: 75U, .ToReg: X86::XMM24 },
2958 { .FromReg: 76U, .ToReg: X86::XMM25 },
2959 { .FromReg: 77U, .ToReg: X86::XMM26 },
2960 { .FromReg: 78U, .ToReg: X86::XMM27 },
2961 { .FromReg: 79U, .ToReg: X86::XMM28 },
2962 { .FromReg: 80U, .ToReg: X86::XMM29 },
2963 { .FromReg: 81U, .ToReg: X86::XMM30 },
2964 { .FromReg: 82U, .ToReg: X86::XMM31 },
2965 { .FromReg: 118U, .ToReg: X86::K0 },
2966 { .FromReg: 119U, .ToReg: X86::K1 },
2967 { .FromReg: 120U, .ToReg: X86::K2 },
2968 { .FromReg: 121U, .ToReg: X86::K3 },
2969 { .FromReg: 122U, .ToReg: X86::K4 },
2970 { .FromReg: 123U, .ToReg: X86::K5 },
2971 { .FromReg: 124U, .ToReg: X86::K6 },
2972 { .FromReg: 125U, .ToReg: X86::K7 },
2973 { .FromReg: 130U, .ToReg: X86::R16 },
2974 { .FromReg: 131U, .ToReg: X86::R17 },
2975 { .FromReg: 132U, .ToReg: X86::R18 },
2976 { .FromReg: 133U, .ToReg: X86::R19 },
2977 { .FromReg: 134U, .ToReg: X86::R20 },
2978 { .FromReg: 135U, .ToReg: X86::R21 },
2979 { .FromReg: 136U, .ToReg: X86::R22 },
2980 { .FromReg: 137U, .ToReg: X86::R23 },
2981 { .FromReg: 138U, .ToReg: X86::R24 },
2982 { .FromReg: 139U, .ToReg: X86::R25 },
2983 { .FromReg: 140U, .ToReg: X86::R26 },
2984 { .FromReg: 141U, .ToReg: X86::R27 },
2985 { .FromReg: 142U, .ToReg: X86::R28 },
2986 { .FromReg: 143U, .ToReg: X86::R29 },
2987 { .FromReg: 144U, .ToReg: X86::R30 },
2988 { .FromReg: 145U, .ToReg: X86::R31 },
2989};
2990extern const unsigned X86EHFlavour0Dwarf2LSize = std::size(X86EHFlavour0Dwarf2L);
2991
2992extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
2993 { .FromReg: 0U, .ToReg: X86::EAX },
2994 { .FromReg: 1U, .ToReg: X86::ECX },
2995 { .FromReg: 2U, .ToReg: X86::EDX },
2996 { .FromReg: 3U, .ToReg: X86::EBX },
2997 { .FromReg: 4U, .ToReg: X86::EBP },
2998 { .FromReg: 5U, .ToReg: X86::ESP },
2999 { .FromReg: 6U, .ToReg: X86::ESI },
3000 { .FromReg: 7U, .ToReg: X86::EDI },
3001 { .FromReg: 8U, .ToReg: X86::EIP },
3002 { .FromReg: 9U, .ToReg: X86::EFLAGS },
3003 { .FromReg: 12U, .ToReg: X86::ST0 },
3004 { .FromReg: 13U, .ToReg: X86::ST1 },
3005 { .FromReg: 14U, .ToReg: X86::ST2 },
3006 { .FromReg: 15U, .ToReg: X86::ST3 },
3007 { .FromReg: 16U, .ToReg: X86::ST4 },
3008 { .FromReg: 17U, .ToReg: X86::ST5 },
3009 { .FromReg: 18U, .ToReg: X86::ST6 },
3010 { .FromReg: 19U, .ToReg: X86::ST7 },
3011 { .FromReg: 21U, .ToReg: X86::XMM0 },
3012 { .FromReg: 22U, .ToReg: X86::XMM1 },
3013 { .FromReg: 23U, .ToReg: X86::XMM2 },
3014 { .FromReg: 24U, .ToReg: X86::XMM3 },
3015 { .FromReg: 25U, .ToReg: X86::XMM4 },
3016 { .FromReg: 26U, .ToReg: X86::XMM5 },
3017 { .FromReg: 27U, .ToReg: X86::XMM6 },
3018 { .FromReg: 28U, .ToReg: X86::XMM7 },
3019 { .FromReg: 29U, .ToReg: X86::MM0 },
3020 { .FromReg: 30U, .ToReg: X86::MM1 },
3021 { .FromReg: 31U, .ToReg: X86::MM2 },
3022 { .FromReg: 32U, .ToReg: X86::MM3 },
3023 { .FromReg: 33U, .ToReg: X86::MM4 },
3024 { .FromReg: 34U, .ToReg: X86::MM5 },
3025 { .FromReg: 35U, .ToReg: X86::MM6 },
3026 { .FromReg: 36U, .ToReg: X86::MM7 },
3027 { .FromReg: 93U, .ToReg: X86::K0 },
3028 { .FromReg: 94U, .ToReg: X86::K1 },
3029 { .FromReg: 95U, .ToReg: X86::K2 },
3030 { .FromReg: 96U, .ToReg: X86::K3 },
3031 { .FromReg: 97U, .ToReg: X86::K4 },
3032 { .FromReg: 98U, .ToReg: X86::K5 },
3033 { .FromReg: 99U, .ToReg: X86::K6 },
3034 { .FromReg: 100U, .ToReg: X86::K7 },
3035};
3036extern const unsigned X86EHFlavour1Dwarf2LSize = std::size(X86EHFlavour1Dwarf2L);
3037
3038extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
3039 { .FromReg: 0U, .ToReg: X86::EAX },
3040 { .FromReg: 1U, .ToReg: X86::ECX },
3041 { .FromReg: 2U, .ToReg: X86::EDX },
3042 { .FromReg: 3U, .ToReg: X86::EBX },
3043 { .FromReg: 4U, .ToReg: X86::ESP },
3044 { .FromReg: 5U, .ToReg: X86::EBP },
3045 { .FromReg: 6U, .ToReg: X86::ESI },
3046 { .FromReg: 7U, .ToReg: X86::EDI },
3047 { .FromReg: 8U, .ToReg: X86::EIP },
3048 { .FromReg: 9U, .ToReg: X86::EFLAGS },
3049 { .FromReg: 11U, .ToReg: X86::ST0 },
3050 { .FromReg: 12U, .ToReg: X86::ST1 },
3051 { .FromReg: 13U, .ToReg: X86::ST2 },
3052 { .FromReg: 14U, .ToReg: X86::ST3 },
3053 { .FromReg: 15U, .ToReg: X86::ST4 },
3054 { .FromReg: 16U, .ToReg: X86::ST5 },
3055 { .FromReg: 17U, .ToReg: X86::ST6 },
3056 { .FromReg: 18U, .ToReg: X86::ST7 },
3057 { .FromReg: 21U, .ToReg: X86::XMM0 },
3058 { .FromReg: 22U, .ToReg: X86::XMM1 },
3059 { .FromReg: 23U, .ToReg: X86::XMM2 },
3060 { .FromReg: 24U, .ToReg: X86::XMM3 },
3061 { .FromReg: 25U, .ToReg: X86::XMM4 },
3062 { .FromReg: 26U, .ToReg: X86::XMM5 },
3063 { .FromReg: 27U, .ToReg: X86::XMM6 },
3064 { .FromReg: 28U, .ToReg: X86::XMM7 },
3065 { .FromReg: 29U, .ToReg: X86::MM0 },
3066 { .FromReg: 30U, .ToReg: X86::MM1 },
3067 { .FromReg: 31U, .ToReg: X86::MM2 },
3068 { .FromReg: 32U, .ToReg: X86::MM3 },
3069 { .FromReg: 33U, .ToReg: X86::MM4 },
3070 { .FromReg: 34U, .ToReg: X86::MM5 },
3071 { .FromReg: 35U, .ToReg: X86::MM6 },
3072 { .FromReg: 36U, .ToReg: X86::MM7 },
3073 { .FromReg: 40U, .ToReg: X86::ES },
3074 { .FromReg: 41U, .ToReg: X86::CS },
3075 { .FromReg: 42U, .ToReg: X86::SS },
3076 { .FromReg: 43U, .ToReg: X86::DS },
3077 { .FromReg: 44U, .ToReg: X86::FS },
3078 { .FromReg: 45U, .ToReg: X86::GS },
3079 { .FromReg: 93U, .ToReg: X86::K0 },
3080 { .FromReg: 94U, .ToReg: X86::K1 },
3081 { .FromReg: 95U, .ToReg: X86::K2 },
3082 { .FromReg: 96U, .ToReg: X86::K3 },
3083 { .FromReg: 97U, .ToReg: X86::K4 },
3084 { .FromReg: 98U, .ToReg: X86::K5 },
3085 { .FromReg: 99U, .ToReg: X86::K6 },
3086 { .FromReg: 100U, .ToReg: X86::K7 },
3087};
3088extern const unsigned X86EHFlavour2Dwarf2LSize = std::size(X86EHFlavour2Dwarf2L);
3089
3090extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
3091 { .FromReg: X86::CS, .ToReg: 51U },
3092 { .FromReg: X86::DS, .ToReg: 53U },
3093 { .FromReg: X86::EAX, .ToReg: -2U },
3094 { .FromReg: X86::EBP, .ToReg: -2U },
3095 { .FromReg: X86::EBX, .ToReg: -2U },
3096 { .FromReg: X86::ECX, .ToReg: -2U },
3097 { .FromReg: X86::EDI, .ToReg: -2U },
3098 { .FromReg: X86::EDX, .ToReg: -2U },
3099 { .FromReg: X86::EFLAGS, .ToReg: 49U },
3100 { .FromReg: X86::EIP, .ToReg: -2U },
3101 { .FromReg: X86::ES, .ToReg: 50U },
3102 { .FromReg: X86::ESI, .ToReg: -2U },
3103 { .FromReg: X86::ESP, .ToReg: -2U },
3104 { .FromReg: X86::FS, .ToReg: 54U },
3105 { .FromReg: X86::FS_BASE, .ToReg: 58U },
3106 { .FromReg: X86::GS, .ToReg: 55U },
3107 { .FromReg: X86::GS_BASE, .ToReg: 59U },
3108 { .FromReg: X86::RAX, .ToReg: 0U },
3109 { .FromReg: X86::RBP, .ToReg: 6U },
3110 { .FromReg: X86::RBX, .ToReg: 3U },
3111 { .FromReg: X86::RCX, .ToReg: 2U },
3112 { .FromReg: X86::RDI, .ToReg: 5U },
3113 { .FromReg: X86::RDX, .ToReg: 1U },
3114 { .FromReg: X86::RFLAGS, .ToReg: 49U },
3115 { .FromReg: X86::RIP, .ToReg: 16U },
3116 { .FromReg: X86::RSI, .ToReg: 4U },
3117 { .FromReg: X86::RSP, .ToReg: 7U },
3118 { .FromReg: X86::SS, .ToReg: 52U },
3119 { .FromReg: X86::_EFLAGS, .ToReg: 49U },
3120 { .FromReg: X86::MM0, .ToReg: 41U },
3121 { .FromReg: X86::MM1, .ToReg: 42U },
3122 { .FromReg: X86::MM2, .ToReg: 43U },
3123 { .FromReg: X86::MM3, .ToReg: 44U },
3124 { .FromReg: X86::MM4, .ToReg: 45U },
3125 { .FromReg: X86::MM5, .ToReg: 46U },
3126 { .FromReg: X86::MM6, .ToReg: 47U },
3127 { .FromReg: X86::MM7, .ToReg: 48U },
3128 { .FromReg: X86::R8, .ToReg: 8U },
3129 { .FromReg: X86::R9, .ToReg: 9U },
3130 { .FromReg: X86::R10, .ToReg: 10U },
3131 { .FromReg: X86::R11, .ToReg: 11U },
3132 { .FromReg: X86::R12, .ToReg: 12U },
3133 { .FromReg: X86::R13, .ToReg: 13U },
3134 { .FromReg: X86::R14, .ToReg: 14U },
3135 { .FromReg: X86::R15, .ToReg: 15U },
3136 { .FromReg: X86::ST0, .ToReg: 33U },
3137 { .FromReg: X86::ST1, .ToReg: 34U },
3138 { .FromReg: X86::ST2, .ToReg: 35U },
3139 { .FromReg: X86::ST3, .ToReg: 36U },
3140 { .FromReg: X86::ST4, .ToReg: 37U },
3141 { .FromReg: X86::ST5, .ToReg: 38U },
3142 { .FromReg: X86::ST6, .ToReg: 39U },
3143 { .FromReg: X86::ST7, .ToReg: 40U },
3144 { .FromReg: X86::XMM0, .ToReg: 17U },
3145 { .FromReg: X86::XMM1, .ToReg: 18U },
3146 { .FromReg: X86::XMM2, .ToReg: 19U },
3147 { .FromReg: X86::XMM3, .ToReg: 20U },
3148 { .FromReg: X86::XMM4, .ToReg: 21U },
3149 { .FromReg: X86::XMM5, .ToReg: 22U },
3150 { .FromReg: X86::XMM6, .ToReg: 23U },
3151 { .FromReg: X86::XMM7, .ToReg: 24U },
3152 { .FromReg: X86::XMM8, .ToReg: 25U },
3153 { .FromReg: X86::XMM9, .ToReg: 26U },
3154 { .FromReg: X86::XMM10, .ToReg: 27U },
3155 { .FromReg: X86::XMM11, .ToReg: 28U },
3156 { .FromReg: X86::XMM12, .ToReg: 29U },
3157 { .FromReg: X86::XMM13, .ToReg: 30U },
3158 { .FromReg: X86::XMM14, .ToReg: 31U },
3159 { .FromReg: X86::XMM15, .ToReg: 32U },
3160 { .FromReg: X86::YMM0, .ToReg: 17U },
3161 { .FromReg: X86::YMM1, .ToReg: 18U },
3162 { .FromReg: X86::YMM2, .ToReg: 19U },
3163 { .FromReg: X86::YMM3, .ToReg: 20U },
3164 { .FromReg: X86::YMM4, .ToReg: 21U },
3165 { .FromReg: X86::YMM5, .ToReg: 22U },
3166 { .FromReg: X86::YMM6, .ToReg: 23U },
3167 { .FromReg: X86::YMM7, .ToReg: 24U },
3168 { .FromReg: X86::YMM8, .ToReg: 25U },
3169 { .FromReg: X86::YMM9, .ToReg: 26U },
3170 { .FromReg: X86::YMM10, .ToReg: 27U },
3171 { .FromReg: X86::YMM11, .ToReg: 28U },
3172 { .FromReg: X86::YMM12, .ToReg: 29U },
3173 { .FromReg: X86::YMM13, .ToReg: 30U },
3174 { .FromReg: X86::YMM14, .ToReg: 31U },
3175 { .FromReg: X86::YMM15, .ToReg: 32U },
3176 { .FromReg: X86::K0, .ToReg: 118U },
3177 { .FromReg: X86::K1, .ToReg: 119U },
3178 { .FromReg: X86::K2, .ToReg: 120U },
3179 { .FromReg: X86::K3, .ToReg: 121U },
3180 { .FromReg: X86::K4, .ToReg: 122U },
3181 { .FromReg: X86::K5, .ToReg: 123U },
3182 { .FromReg: X86::K6, .ToReg: 124U },
3183 { .FromReg: X86::K7, .ToReg: 125U },
3184 { .FromReg: X86::XMM16, .ToReg: 67U },
3185 { .FromReg: X86::XMM17, .ToReg: 68U },
3186 { .FromReg: X86::XMM18, .ToReg: 69U },
3187 { .FromReg: X86::XMM19, .ToReg: 70U },
3188 { .FromReg: X86::XMM20, .ToReg: 71U },
3189 { .FromReg: X86::XMM21, .ToReg: 72U },
3190 { .FromReg: X86::XMM22, .ToReg: 73U },
3191 { .FromReg: X86::XMM23, .ToReg: 74U },
3192 { .FromReg: X86::XMM24, .ToReg: 75U },
3193 { .FromReg: X86::XMM25, .ToReg: 76U },
3194 { .FromReg: X86::XMM26, .ToReg: 77U },
3195 { .FromReg: X86::XMM27, .ToReg: 78U },
3196 { .FromReg: X86::XMM28, .ToReg: 79U },
3197 { .FromReg: X86::XMM29, .ToReg: 80U },
3198 { .FromReg: X86::XMM30, .ToReg: 81U },
3199 { .FromReg: X86::XMM31, .ToReg: 82U },
3200 { .FromReg: X86::YMM16, .ToReg: 67U },
3201 { .FromReg: X86::YMM17, .ToReg: 68U },
3202 { .FromReg: X86::YMM18, .ToReg: 69U },
3203 { .FromReg: X86::YMM19, .ToReg: 70U },
3204 { .FromReg: X86::YMM20, .ToReg: 71U },
3205 { .FromReg: X86::YMM21, .ToReg: 72U },
3206 { .FromReg: X86::YMM22, .ToReg: 73U },
3207 { .FromReg: X86::YMM23, .ToReg: 74U },
3208 { .FromReg: X86::YMM24, .ToReg: 75U },
3209 { .FromReg: X86::YMM25, .ToReg: 76U },
3210 { .FromReg: X86::YMM26, .ToReg: 77U },
3211 { .FromReg: X86::YMM27, .ToReg: 78U },
3212 { .FromReg: X86::YMM28, .ToReg: 79U },
3213 { .FromReg: X86::YMM29, .ToReg: 80U },
3214 { .FromReg: X86::YMM30, .ToReg: 81U },
3215 { .FromReg: X86::YMM31, .ToReg: 82U },
3216 { .FromReg: X86::ZMM0, .ToReg: 17U },
3217 { .FromReg: X86::ZMM1, .ToReg: 18U },
3218 { .FromReg: X86::ZMM2, .ToReg: 19U },
3219 { .FromReg: X86::ZMM3, .ToReg: 20U },
3220 { .FromReg: X86::ZMM4, .ToReg: 21U },
3221 { .FromReg: X86::ZMM5, .ToReg: 22U },
3222 { .FromReg: X86::ZMM6, .ToReg: 23U },
3223 { .FromReg: X86::ZMM7, .ToReg: 24U },
3224 { .FromReg: X86::ZMM8, .ToReg: 25U },
3225 { .FromReg: X86::ZMM9, .ToReg: 26U },
3226 { .FromReg: X86::ZMM10, .ToReg: 27U },
3227 { .FromReg: X86::ZMM11, .ToReg: 28U },
3228 { .FromReg: X86::ZMM12, .ToReg: 29U },
3229 { .FromReg: X86::ZMM13, .ToReg: 30U },
3230 { .FromReg: X86::ZMM14, .ToReg: 31U },
3231 { .FromReg: X86::ZMM15, .ToReg: 32U },
3232 { .FromReg: X86::ZMM16, .ToReg: 67U },
3233 { .FromReg: X86::ZMM17, .ToReg: 68U },
3234 { .FromReg: X86::ZMM18, .ToReg: 69U },
3235 { .FromReg: X86::ZMM19, .ToReg: 70U },
3236 { .FromReg: X86::ZMM20, .ToReg: 71U },
3237 { .FromReg: X86::ZMM21, .ToReg: 72U },
3238 { .FromReg: X86::ZMM22, .ToReg: 73U },
3239 { .FromReg: X86::ZMM23, .ToReg: 74U },
3240 { .FromReg: X86::ZMM24, .ToReg: 75U },
3241 { .FromReg: X86::ZMM25, .ToReg: 76U },
3242 { .FromReg: X86::ZMM26, .ToReg: 77U },
3243 { .FromReg: X86::ZMM27, .ToReg: 78U },
3244 { .FromReg: X86::ZMM28, .ToReg: 79U },
3245 { .FromReg: X86::ZMM29, .ToReg: 80U },
3246 { .FromReg: X86::ZMM30, .ToReg: 81U },
3247 { .FromReg: X86::ZMM31, .ToReg: 82U },
3248 { .FromReg: X86::R16, .ToReg: 130U },
3249 { .FromReg: X86::R17, .ToReg: 131U },
3250 { .FromReg: X86::R18, .ToReg: 132U },
3251 { .FromReg: X86::R19, .ToReg: 133U },
3252 { .FromReg: X86::R20, .ToReg: 134U },
3253 { .FromReg: X86::R21, .ToReg: 135U },
3254 { .FromReg: X86::R22, .ToReg: 136U },
3255 { .FromReg: X86::R23, .ToReg: 137U },
3256 { .FromReg: X86::R24, .ToReg: 138U },
3257 { .FromReg: X86::R25, .ToReg: 139U },
3258 { .FromReg: X86::R26, .ToReg: 140U },
3259 { .FromReg: X86::R27, .ToReg: 141U },
3260 { .FromReg: X86::R28, .ToReg: 142U },
3261 { .FromReg: X86::R29, .ToReg: 143U },
3262 { .FromReg: X86::R30, .ToReg: 144U },
3263 { .FromReg: X86::R31, .ToReg: 145U },
3264};
3265extern const unsigned X86DwarfFlavour0L2DwarfSize = std::size(X86DwarfFlavour0L2Dwarf);
3266
3267extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
3268 { .FromReg: X86::CS, .ToReg: -2U },
3269 { .FromReg: X86::DS, .ToReg: -2U },
3270 { .FromReg: X86::EAX, .ToReg: 0U },
3271 { .FromReg: X86::EBP, .ToReg: 4U },
3272 { .FromReg: X86::EBX, .ToReg: 3U },
3273 { .FromReg: X86::ECX, .ToReg: 1U },
3274 { .FromReg: X86::EDI, .ToReg: 7U },
3275 { .FromReg: X86::EDX, .ToReg: 2U },
3276 { .FromReg: X86::EFLAGS, .ToReg: 9U },
3277 { .FromReg: X86::EIP, .ToReg: 8U },
3278 { .FromReg: X86::ES, .ToReg: -2U },
3279 { .FromReg: X86::ESI, .ToReg: 6U },
3280 { .FromReg: X86::ESP, .ToReg: 5U },
3281 { .FromReg: X86::FS, .ToReg: -2U },
3282 { .FromReg: X86::FS_BASE, .ToReg: -2U },
3283 { .FromReg: X86::GS, .ToReg: -2U },
3284 { .FromReg: X86::GS_BASE, .ToReg: -2U },
3285 { .FromReg: X86::RAX, .ToReg: -2U },
3286 { .FromReg: X86::RBP, .ToReg: -2U },
3287 { .FromReg: X86::RBX, .ToReg: -2U },
3288 { .FromReg: X86::RCX, .ToReg: -2U },
3289 { .FromReg: X86::RDI, .ToReg: -2U },
3290 { .FromReg: X86::RDX, .ToReg: -2U },
3291 { .FromReg: X86::RFLAGS, .ToReg: -2U },
3292 { .FromReg: X86::RIP, .ToReg: -2U },
3293 { .FromReg: X86::RSI, .ToReg: -2U },
3294 { .FromReg: X86::RSP, .ToReg: -2U },
3295 { .FromReg: X86::SS, .ToReg: -2U },
3296 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
3297 { .FromReg: X86::MM0, .ToReg: 29U },
3298 { .FromReg: X86::MM1, .ToReg: 30U },
3299 { .FromReg: X86::MM2, .ToReg: 31U },
3300 { .FromReg: X86::MM3, .ToReg: 32U },
3301 { .FromReg: X86::MM4, .ToReg: 33U },
3302 { .FromReg: X86::MM5, .ToReg: 34U },
3303 { .FromReg: X86::MM6, .ToReg: 35U },
3304 { .FromReg: X86::MM7, .ToReg: 36U },
3305 { .FromReg: X86::R8, .ToReg: -2U },
3306 { .FromReg: X86::R9, .ToReg: -2U },
3307 { .FromReg: X86::R10, .ToReg: -2U },
3308 { .FromReg: X86::R11, .ToReg: -2U },
3309 { .FromReg: X86::R12, .ToReg: -2U },
3310 { .FromReg: X86::R13, .ToReg: -2U },
3311 { .FromReg: X86::R14, .ToReg: -2U },
3312 { .FromReg: X86::R15, .ToReg: -2U },
3313 { .FromReg: X86::ST0, .ToReg: 12U },
3314 { .FromReg: X86::ST1, .ToReg: 13U },
3315 { .FromReg: X86::ST2, .ToReg: 14U },
3316 { .FromReg: X86::ST3, .ToReg: 15U },
3317 { .FromReg: X86::ST4, .ToReg: 16U },
3318 { .FromReg: X86::ST5, .ToReg: 17U },
3319 { .FromReg: X86::ST6, .ToReg: 18U },
3320 { .FromReg: X86::ST7, .ToReg: 19U },
3321 { .FromReg: X86::XMM0, .ToReg: 21U },
3322 { .FromReg: X86::XMM1, .ToReg: 22U },
3323 { .FromReg: X86::XMM2, .ToReg: 23U },
3324 { .FromReg: X86::XMM3, .ToReg: 24U },
3325 { .FromReg: X86::XMM4, .ToReg: 25U },
3326 { .FromReg: X86::XMM5, .ToReg: 26U },
3327 { .FromReg: X86::XMM6, .ToReg: 27U },
3328 { .FromReg: X86::XMM7, .ToReg: 28U },
3329 { .FromReg: X86::XMM8, .ToReg: -2U },
3330 { .FromReg: X86::XMM9, .ToReg: -2U },
3331 { .FromReg: X86::XMM10, .ToReg: -2U },
3332 { .FromReg: X86::XMM11, .ToReg: -2U },
3333 { .FromReg: X86::XMM12, .ToReg: -2U },
3334 { .FromReg: X86::XMM13, .ToReg: -2U },
3335 { .FromReg: X86::XMM14, .ToReg: -2U },
3336 { .FromReg: X86::XMM15, .ToReg: -2U },
3337 { .FromReg: X86::YMM0, .ToReg: 21U },
3338 { .FromReg: X86::YMM1, .ToReg: 22U },
3339 { .FromReg: X86::YMM2, .ToReg: 23U },
3340 { .FromReg: X86::YMM3, .ToReg: 24U },
3341 { .FromReg: X86::YMM4, .ToReg: 25U },
3342 { .FromReg: X86::YMM5, .ToReg: 26U },
3343 { .FromReg: X86::YMM6, .ToReg: 27U },
3344 { .FromReg: X86::YMM7, .ToReg: 28U },
3345 { .FromReg: X86::YMM8, .ToReg: -2U },
3346 { .FromReg: X86::YMM9, .ToReg: -2U },
3347 { .FromReg: X86::YMM10, .ToReg: -2U },
3348 { .FromReg: X86::YMM11, .ToReg: -2U },
3349 { .FromReg: X86::YMM12, .ToReg: -2U },
3350 { .FromReg: X86::YMM13, .ToReg: -2U },
3351 { .FromReg: X86::YMM14, .ToReg: -2U },
3352 { .FromReg: X86::YMM15, .ToReg: -2U },
3353 { .FromReg: X86::K0, .ToReg: 93U },
3354 { .FromReg: X86::K1, .ToReg: 94U },
3355 { .FromReg: X86::K2, .ToReg: 95U },
3356 { .FromReg: X86::K3, .ToReg: 96U },
3357 { .FromReg: X86::K4, .ToReg: 97U },
3358 { .FromReg: X86::K5, .ToReg: 98U },
3359 { .FromReg: X86::K6, .ToReg: 99U },
3360 { .FromReg: X86::K7, .ToReg: 100U },
3361 { .FromReg: X86::XMM16, .ToReg: -2U },
3362 { .FromReg: X86::XMM17, .ToReg: -2U },
3363 { .FromReg: X86::XMM18, .ToReg: -2U },
3364 { .FromReg: X86::XMM19, .ToReg: -2U },
3365 { .FromReg: X86::XMM20, .ToReg: -2U },
3366 { .FromReg: X86::XMM21, .ToReg: -2U },
3367 { .FromReg: X86::XMM22, .ToReg: -2U },
3368 { .FromReg: X86::XMM23, .ToReg: -2U },
3369 { .FromReg: X86::XMM24, .ToReg: -2U },
3370 { .FromReg: X86::XMM25, .ToReg: -2U },
3371 { .FromReg: X86::XMM26, .ToReg: -2U },
3372 { .FromReg: X86::XMM27, .ToReg: -2U },
3373 { .FromReg: X86::XMM28, .ToReg: -2U },
3374 { .FromReg: X86::XMM29, .ToReg: -2U },
3375 { .FromReg: X86::XMM30, .ToReg: -2U },
3376 { .FromReg: X86::XMM31, .ToReg: -2U },
3377 { .FromReg: X86::YMM16, .ToReg: -2U },
3378 { .FromReg: X86::YMM17, .ToReg: -2U },
3379 { .FromReg: X86::YMM18, .ToReg: -2U },
3380 { .FromReg: X86::YMM19, .ToReg: -2U },
3381 { .FromReg: X86::YMM20, .ToReg: -2U },
3382 { .FromReg: X86::YMM21, .ToReg: -2U },
3383 { .FromReg: X86::YMM22, .ToReg: -2U },
3384 { .FromReg: X86::YMM23, .ToReg: -2U },
3385 { .FromReg: X86::YMM24, .ToReg: -2U },
3386 { .FromReg: X86::YMM25, .ToReg: -2U },
3387 { .FromReg: X86::YMM26, .ToReg: -2U },
3388 { .FromReg: X86::YMM27, .ToReg: -2U },
3389 { .FromReg: X86::YMM28, .ToReg: -2U },
3390 { .FromReg: X86::YMM29, .ToReg: -2U },
3391 { .FromReg: X86::YMM30, .ToReg: -2U },
3392 { .FromReg: X86::YMM31, .ToReg: -2U },
3393 { .FromReg: X86::ZMM0, .ToReg: 21U },
3394 { .FromReg: X86::ZMM1, .ToReg: 22U },
3395 { .FromReg: X86::ZMM2, .ToReg: 23U },
3396 { .FromReg: X86::ZMM3, .ToReg: 24U },
3397 { .FromReg: X86::ZMM4, .ToReg: 25U },
3398 { .FromReg: X86::ZMM5, .ToReg: 26U },
3399 { .FromReg: X86::ZMM6, .ToReg: 27U },
3400 { .FromReg: X86::ZMM7, .ToReg: 28U },
3401 { .FromReg: X86::ZMM8, .ToReg: -2U },
3402 { .FromReg: X86::ZMM9, .ToReg: -2U },
3403 { .FromReg: X86::ZMM10, .ToReg: -2U },
3404 { .FromReg: X86::ZMM11, .ToReg: -2U },
3405 { .FromReg: X86::ZMM12, .ToReg: -2U },
3406 { .FromReg: X86::ZMM13, .ToReg: -2U },
3407 { .FromReg: X86::ZMM14, .ToReg: -2U },
3408 { .FromReg: X86::ZMM15, .ToReg: -2U },
3409 { .FromReg: X86::ZMM16, .ToReg: -2U },
3410 { .FromReg: X86::ZMM17, .ToReg: -2U },
3411 { .FromReg: X86::ZMM18, .ToReg: -2U },
3412 { .FromReg: X86::ZMM19, .ToReg: -2U },
3413 { .FromReg: X86::ZMM20, .ToReg: -2U },
3414 { .FromReg: X86::ZMM21, .ToReg: -2U },
3415 { .FromReg: X86::ZMM22, .ToReg: -2U },
3416 { .FromReg: X86::ZMM23, .ToReg: -2U },
3417 { .FromReg: X86::ZMM24, .ToReg: -2U },
3418 { .FromReg: X86::ZMM25, .ToReg: -2U },
3419 { .FromReg: X86::ZMM26, .ToReg: -2U },
3420 { .FromReg: X86::ZMM27, .ToReg: -2U },
3421 { .FromReg: X86::ZMM28, .ToReg: -2U },
3422 { .FromReg: X86::ZMM29, .ToReg: -2U },
3423 { .FromReg: X86::ZMM30, .ToReg: -2U },
3424 { .FromReg: X86::ZMM31, .ToReg: -2U },
3425 { .FromReg: X86::R16, .ToReg: -2U },
3426 { .FromReg: X86::R17, .ToReg: -2U },
3427 { .FromReg: X86::R18, .ToReg: -2U },
3428 { .FromReg: X86::R19, .ToReg: -2U },
3429 { .FromReg: X86::R20, .ToReg: -2U },
3430 { .FromReg: X86::R21, .ToReg: -2U },
3431 { .FromReg: X86::R22, .ToReg: -2U },
3432 { .FromReg: X86::R23, .ToReg: -2U },
3433 { .FromReg: X86::R24, .ToReg: -2U },
3434 { .FromReg: X86::R25, .ToReg: -2U },
3435 { .FromReg: X86::R26, .ToReg: -2U },
3436 { .FromReg: X86::R27, .ToReg: -2U },
3437 { .FromReg: X86::R28, .ToReg: -2U },
3438 { .FromReg: X86::R29, .ToReg: -2U },
3439 { .FromReg: X86::R30, .ToReg: -2U },
3440 { .FromReg: X86::R31, .ToReg: -2U },
3441};
3442extern const unsigned X86DwarfFlavour1L2DwarfSize = std::size(X86DwarfFlavour1L2Dwarf);
3443
3444extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
3445 { .FromReg: X86::CS, .ToReg: 41U },
3446 { .FromReg: X86::DS, .ToReg: 43U },
3447 { .FromReg: X86::EAX, .ToReg: 0U },
3448 { .FromReg: X86::EBP, .ToReg: 5U },
3449 { .FromReg: X86::EBX, .ToReg: 3U },
3450 { .FromReg: X86::ECX, .ToReg: 1U },
3451 { .FromReg: X86::EDI, .ToReg: 7U },
3452 { .FromReg: X86::EDX, .ToReg: 2U },
3453 { .FromReg: X86::EFLAGS, .ToReg: 9U },
3454 { .FromReg: X86::EIP, .ToReg: 8U },
3455 { .FromReg: X86::ES, .ToReg: 40U },
3456 { .FromReg: X86::ESI, .ToReg: 6U },
3457 { .FromReg: X86::ESP, .ToReg: 4U },
3458 { .FromReg: X86::FS, .ToReg: 44U },
3459 { .FromReg: X86::FS_BASE, .ToReg: -2U },
3460 { .FromReg: X86::GS, .ToReg: 45U },
3461 { .FromReg: X86::GS_BASE, .ToReg: -2U },
3462 { .FromReg: X86::RAX, .ToReg: -2U },
3463 { .FromReg: X86::RBP, .ToReg: -2U },
3464 { .FromReg: X86::RBX, .ToReg: -2U },
3465 { .FromReg: X86::RCX, .ToReg: -2U },
3466 { .FromReg: X86::RDI, .ToReg: -2U },
3467 { .FromReg: X86::RDX, .ToReg: -2U },
3468 { .FromReg: X86::RFLAGS, .ToReg: -2U },
3469 { .FromReg: X86::RIP, .ToReg: -2U },
3470 { .FromReg: X86::RSI, .ToReg: -2U },
3471 { .FromReg: X86::RSP, .ToReg: -2U },
3472 { .FromReg: X86::SS, .ToReg: 42U },
3473 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
3474 { .FromReg: X86::MM0, .ToReg: 29U },
3475 { .FromReg: X86::MM1, .ToReg: 30U },
3476 { .FromReg: X86::MM2, .ToReg: 31U },
3477 { .FromReg: X86::MM3, .ToReg: 32U },
3478 { .FromReg: X86::MM4, .ToReg: 33U },
3479 { .FromReg: X86::MM5, .ToReg: 34U },
3480 { .FromReg: X86::MM6, .ToReg: 35U },
3481 { .FromReg: X86::MM7, .ToReg: 36U },
3482 { .FromReg: X86::R8, .ToReg: -2U },
3483 { .FromReg: X86::R9, .ToReg: -2U },
3484 { .FromReg: X86::R10, .ToReg: -2U },
3485 { .FromReg: X86::R11, .ToReg: -2U },
3486 { .FromReg: X86::R12, .ToReg: -2U },
3487 { .FromReg: X86::R13, .ToReg: -2U },
3488 { .FromReg: X86::R14, .ToReg: -2U },
3489 { .FromReg: X86::R15, .ToReg: -2U },
3490 { .FromReg: X86::ST0, .ToReg: 11U },
3491 { .FromReg: X86::ST1, .ToReg: 12U },
3492 { .FromReg: X86::ST2, .ToReg: 13U },
3493 { .FromReg: X86::ST3, .ToReg: 14U },
3494 { .FromReg: X86::ST4, .ToReg: 15U },
3495 { .FromReg: X86::ST5, .ToReg: 16U },
3496 { .FromReg: X86::ST6, .ToReg: 17U },
3497 { .FromReg: X86::ST7, .ToReg: 18U },
3498 { .FromReg: X86::XMM0, .ToReg: 21U },
3499 { .FromReg: X86::XMM1, .ToReg: 22U },
3500 { .FromReg: X86::XMM2, .ToReg: 23U },
3501 { .FromReg: X86::XMM3, .ToReg: 24U },
3502 { .FromReg: X86::XMM4, .ToReg: 25U },
3503 { .FromReg: X86::XMM5, .ToReg: 26U },
3504 { .FromReg: X86::XMM6, .ToReg: 27U },
3505 { .FromReg: X86::XMM7, .ToReg: 28U },
3506 { .FromReg: X86::XMM8, .ToReg: -2U },
3507 { .FromReg: X86::XMM9, .ToReg: -2U },
3508 { .FromReg: X86::XMM10, .ToReg: -2U },
3509 { .FromReg: X86::XMM11, .ToReg: -2U },
3510 { .FromReg: X86::XMM12, .ToReg: -2U },
3511 { .FromReg: X86::XMM13, .ToReg: -2U },
3512 { .FromReg: X86::XMM14, .ToReg: -2U },
3513 { .FromReg: X86::XMM15, .ToReg: -2U },
3514 { .FromReg: X86::YMM0, .ToReg: 21U },
3515 { .FromReg: X86::YMM1, .ToReg: 22U },
3516 { .FromReg: X86::YMM2, .ToReg: 23U },
3517 { .FromReg: X86::YMM3, .ToReg: 24U },
3518 { .FromReg: X86::YMM4, .ToReg: 25U },
3519 { .FromReg: X86::YMM5, .ToReg: 26U },
3520 { .FromReg: X86::YMM6, .ToReg: 27U },
3521 { .FromReg: X86::YMM7, .ToReg: 28U },
3522 { .FromReg: X86::YMM8, .ToReg: -2U },
3523 { .FromReg: X86::YMM9, .ToReg: -2U },
3524 { .FromReg: X86::YMM10, .ToReg: -2U },
3525 { .FromReg: X86::YMM11, .ToReg: -2U },
3526 { .FromReg: X86::YMM12, .ToReg: -2U },
3527 { .FromReg: X86::YMM13, .ToReg: -2U },
3528 { .FromReg: X86::YMM14, .ToReg: -2U },
3529 { .FromReg: X86::YMM15, .ToReg: -2U },
3530 { .FromReg: X86::K0, .ToReg: 93U },
3531 { .FromReg: X86::K1, .ToReg: 94U },
3532 { .FromReg: X86::K2, .ToReg: 95U },
3533 { .FromReg: X86::K3, .ToReg: 96U },
3534 { .FromReg: X86::K4, .ToReg: 97U },
3535 { .FromReg: X86::K5, .ToReg: 98U },
3536 { .FromReg: X86::K6, .ToReg: 99U },
3537 { .FromReg: X86::K7, .ToReg: 100U },
3538 { .FromReg: X86::XMM16, .ToReg: -2U },
3539 { .FromReg: X86::XMM17, .ToReg: -2U },
3540 { .FromReg: X86::XMM18, .ToReg: -2U },
3541 { .FromReg: X86::XMM19, .ToReg: -2U },
3542 { .FromReg: X86::XMM20, .ToReg: -2U },
3543 { .FromReg: X86::XMM21, .ToReg: -2U },
3544 { .FromReg: X86::XMM22, .ToReg: -2U },
3545 { .FromReg: X86::XMM23, .ToReg: -2U },
3546 { .FromReg: X86::XMM24, .ToReg: -2U },
3547 { .FromReg: X86::XMM25, .ToReg: -2U },
3548 { .FromReg: X86::XMM26, .ToReg: -2U },
3549 { .FromReg: X86::XMM27, .ToReg: -2U },
3550 { .FromReg: X86::XMM28, .ToReg: -2U },
3551 { .FromReg: X86::XMM29, .ToReg: -2U },
3552 { .FromReg: X86::XMM30, .ToReg: -2U },
3553 { .FromReg: X86::XMM31, .ToReg: -2U },
3554 { .FromReg: X86::YMM16, .ToReg: -2U },
3555 { .FromReg: X86::YMM17, .ToReg: -2U },
3556 { .FromReg: X86::YMM18, .ToReg: -2U },
3557 { .FromReg: X86::YMM19, .ToReg: -2U },
3558 { .FromReg: X86::YMM20, .ToReg: -2U },
3559 { .FromReg: X86::YMM21, .ToReg: -2U },
3560 { .FromReg: X86::YMM22, .ToReg: -2U },
3561 { .FromReg: X86::YMM23, .ToReg: -2U },
3562 { .FromReg: X86::YMM24, .ToReg: -2U },
3563 { .FromReg: X86::YMM25, .ToReg: -2U },
3564 { .FromReg: X86::YMM26, .ToReg: -2U },
3565 { .FromReg: X86::YMM27, .ToReg: -2U },
3566 { .FromReg: X86::YMM28, .ToReg: -2U },
3567 { .FromReg: X86::YMM29, .ToReg: -2U },
3568 { .FromReg: X86::YMM30, .ToReg: -2U },
3569 { .FromReg: X86::YMM31, .ToReg: -2U },
3570 { .FromReg: X86::ZMM0, .ToReg: 21U },
3571 { .FromReg: X86::ZMM1, .ToReg: 22U },
3572 { .FromReg: X86::ZMM2, .ToReg: 23U },
3573 { .FromReg: X86::ZMM3, .ToReg: 24U },
3574 { .FromReg: X86::ZMM4, .ToReg: 25U },
3575 { .FromReg: X86::ZMM5, .ToReg: 26U },
3576 { .FromReg: X86::ZMM6, .ToReg: 27U },
3577 { .FromReg: X86::ZMM7, .ToReg: 28U },
3578 { .FromReg: X86::ZMM8, .ToReg: -2U },
3579 { .FromReg: X86::ZMM9, .ToReg: -2U },
3580 { .FromReg: X86::ZMM10, .ToReg: -2U },
3581 { .FromReg: X86::ZMM11, .ToReg: -2U },
3582 { .FromReg: X86::ZMM12, .ToReg: -2U },
3583 { .FromReg: X86::ZMM13, .ToReg: -2U },
3584 { .FromReg: X86::ZMM14, .ToReg: -2U },
3585 { .FromReg: X86::ZMM15, .ToReg: -2U },
3586 { .FromReg: X86::ZMM16, .ToReg: -2U },
3587 { .FromReg: X86::ZMM17, .ToReg: -2U },
3588 { .FromReg: X86::ZMM18, .ToReg: -2U },
3589 { .FromReg: X86::ZMM19, .ToReg: -2U },
3590 { .FromReg: X86::ZMM20, .ToReg: -2U },
3591 { .FromReg: X86::ZMM21, .ToReg: -2U },
3592 { .FromReg: X86::ZMM22, .ToReg: -2U },
3593 { .FromReg: X86::ZMM23, .ToReg: -2U },
3594 { .FromReg: X86::ZMM24, .ToReg: -2U },
3595 { .FromReg: X86::ZMM25, .ToReg: -2U },
3596 { .FromReg: X86::ZMM26, .ToReg: -2U },
3597 { .FromReg: X86::ZMM27, .ToReg: -2U },
3598 { .FromReg: X86::ZMM28, .ToReg: -2U },
3599 { .FromReg: X86::ZMM29, .ToReg: -2U },
3600 { .FromReg: X86::ZMM30, .ToReg: -2U },
3601 { .FromReg: X86::ZMM31, .ToReg: -2U },
3602 { .FromReg: X86::R16, .ToReg: -2U },
3603 { .FromReg: X86::R17, .ToReg: -2U },
3604 { .FromReg: X86::R18, .ToReg: -2U },
3605 { .FromReg: X86::R19, .ToReg: -2U },
3606 { .FromReg: X86::R20, .ToReg: -2U },
3607 { .FromReg: X86::R21, .ToReg: -2U },
3608 { .FromReg: X86::R22, .ToReg: -2U },
3609 { .FromReg: X86::R23, .ToReg: -2U },
3610 { .FromReg: X86::R24, .ToReg: -2U },
3611 { .FromReg: X86::R25, .ToReg: -2U },
3612 { .FromReg: X86::R26, .ToReg: -2U },
3613 { .FromReg: X86::R27, .ToReg: -2U },
3614 { .FromReg: X86::R28, .ToReg: -2U },
3615 { .FromReg: X86::R29, .ToReg: -2U },
3616 { .FromReg: X86::R30, .ToReg: -2U },
3617 { .FromReg: X86::R31, .ToReg: -2U },
3618};
3619extern const unsigned X86DwarfFlavour2L2DwarfSize = std::size(X86DwarfFlavour2L2Dwarf);
3620
3621extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
3622 { .FromReg: X86::CS, .ToReg: 51U },
3623 { .FromReg: X86::DS, .ToReg: 53U },
3624 { .FromReg: X86::EAX, .ToReg: -2U },
3625 { .FromReg: X86::EBP, .ToReg: -2U },
3626 { .FromReg: X86::EBX, .ToReg: -2U },
3627 { .FromReg: X86::ECX, .ToReg: -2U },
3628 { .FromReg: X86::EDI, .ToReg: -2U },
3629 { .FromReg: X86::EDX, .ToReg: -2U },
3630 { .FromReg: X86::EFLAGS, .ToReg: 49U },
3631 { .FromReg: X86::EIP, .ToReg: -2U },
3632 { .FromReg: X86::ES, .ToReg: 50U },
3633 { .FromReg: X86::ESI, .ToReg: -2U },
3634 { .FromReg: X86::ESP, .ToReg: -2U },
3635 { .FromReg: X86::FS, .ToReg: 54U },
3636 { .FromReg: X86::FS_BASE, .ToReg: 58U },
3637 { .FromReg: X86::GS, .ToReg: 55U },
3638 { .FromReg: X86::GS_BASE, .ToReg: 59U },
3639 { .FromReg: X86::RAX, .ToReg: 0U },
3640 { .FromReg: X86::RBP, .ToReg: 6U },
3641 { .FromReg: X86::RBX, .ToReg: 3U },
3642 { .FromReg: X86::RCX, .ToReg: 2U },
3643 { .FromReg: X86::RDI, .ToReg: 5U },
3644 { .FromReg: X86::RDX, .ToReg: 1U },
3645 { .FromReg: X86::RFLAGS, .ToReg: 49U },
3646 { .FromReg: X86::RIP, .ToReg: 16U },
3647 { .FromReg: X86::RSI, .ToReg: 4U },
3648 { .FromReg: X86::RSP, .ToReg: 7U },
3649 { .FromReg: X86::SS, .ToReg: 52U },
3650 { .FromReg: X86::_EFLAGS, .ToReg: 49U },
3651 { .FromReg: X86::MM0, .ToReg: 41U },
3652 { .FromReg: X86::MM1, .ToReg: 42U },
3653 { .FromReg: X86::MM2, .ToReg: 43U },
3654 { .FromReg: X86::MM3, .ToReg: 44U },
3655 { .FromReg: X86::MM4, .ToReg: 45U },
3656 { .FromReg: X86::MM5, .ToReg: 46U },
3657 { .FromReg: X86::MM6, .ToReg: 47U },
3658 { .FromReg: X86::MM7, .ToReg: 48U },
3659 { .FromReg: X86::R8, .ToReg: 8U },
3660 { .FromReg: X86::R9, .ToReg: 9U },
3661 { .FromReg: X86::R10, .ToReg: 10U },
3662 { .FromReg: X86::R11, .ToReg: 11U },
3663 { .FromReg: X86::R12, .ToReg: 12U },
3664 { .FromReg: X86::R13, .ToReg: 13U },
3665 { .FromReg: X86::R14, .ToReg: 14U },
3666 { .FromReg: X86::R15, .ToReg: 15U },
3667 { .FromReg: X86::ST0, .ToReg: 33U },
3668 { .FromReg: X86::ST1, .ToReg: 34U },
3669 { .FromReg: X86::ST2, .ToReg: 35U },
3670 { .FromReg: X86::ST3, .ToReg: 36U },
3671 { .FromReg: X86::ST4, .ToReg: 37U },
3672 { .FromReg: X86::ST5, .ToReg: 38U },
3673 { .FromReg: X86::ST6, .ToReg: 39U },
3674 { .FromReg: X86::ST7, .ToReg: 40U },
3675 { .FromReg: X86::XMM0, .ToReg: 17U },
3676 { .FromReg: X86::XMM1, .ToReg: 18U },
3677 { .FromReg: X86::XMM2, .ToReg: 19U },
3678 { .FromReg: X86::XMM3, .ToReg: 20U },
3679 { .FromReg: X86::XMM4, .ToReg: 21U },
3680 { .FromReg: X86::XMM5, .ToReg: 22U },
3681 { .FromReg: X86::XMM6, .ToReg: 23U },
3682 { .FromReg: X86::XMM7, .ToReg: 24U },
3683 { .FromReg: X86::XMM8, .ToReg: 25U },
3684 { .FromReg: X86::XMM9, .ToReg: 26U },
3685 { .FromReg: X86::XMM10, .ToReg: 27U },
3686 { .FromReg: X86::XMM11, .ToReg: 28U },
3687 { .FromReg: X86::XMM12, .ToReg: 29U },
3688 { .FromReg: X86::XMM13, .ToReg: 30U },
3689 { .FromReg: X86::XMM14, .ToReg: 31U },
3690 { .FromReg: X86::XMM15, .ToReg: 32U },
3691 { .FromReg: X86::YMM0, .ToReg: 17U },
3692 { .FromReg: X86::YMM1, .ToReg: 18U },
3693 { .FromReg: X86::YMM2, .ToReg: 19U },
3694 { .FromReg: X86::YMM3, .ToReg: 20U },
3695 { .FromReg: X86::YMM4, .ToReg: 21U },
3696 { .FromReg: X86::YMM5, .ToReg: 22U },
3697 { .FromReg: X86::YMM6, .ToReg: 23U },
3698 { .FromReg: X86::YMM7, .ToReg: 24U },
3699 { .FromReg: X86::YMM8, .ToReg: 25U },
3700 { .FromReg: X86::YMM9, .ToReg: 26U },
3701 { .FromReg: X86::YMM10, .ToReg: 27U },
3702 { .FromReg: X86::YMM11, .ToReg: 28U },
3703 { .FromReg: X86::YMM12, .ToReg: 29U },
3704 { .FromReg: X86::YMM13, .ToReg: 30U },
3705 { .FromReg: X86::YMM14, .ToReg: 31U },
3706 { .FromReg: X86::YMM15, .ToReg: 32U },
3707 { .FromReg: X86::K0, .ToReg: 118U },
3708 { .FromReg: X86::K1, .ToReg: 119U },
3709 { .FromReg: X86::K2, .ToReg: 120U },
3710 { .FromReg: X86::K3, .ToReg: 121U },
3711 { .FromReg: X86::K4, .ToReg: 122U },
3712 { .FromReg: X86::K5, .ToReg: 123U },
3713 { .FromReg: X86::K6, .ToReg: 124U },
3714 { .FromReg: X86::K7, .ToReg: 125U },
3715 { .FromReg: X86::XMM16, .ToReg: 67U },
3716 { .FromReg: X86::XMM17, .ToReg: 68U },
3717 { .FromReg: X86::XMM18, .ToReg: 69U },
3718 { .FromReg: X86::XMM19, .ToReg: 70U },
3719 { .FromReg: X86::XMM20, .ToReg: 71U },
3720 { .FromReg: X86::XMM21, .ToReg: 72U },
3721 { .FromReg: X86::XMM22, .ToReg: 73U },
3722 { .FromReg: X86::XMM23, .ToReg: 74U },
3723 { .FromReg: X86::XMM24, .ToReg: 75U },
3724 { .FromReg: X86::XMM25, .ToReg: 76U },
3725 { .FromReg: X86::XMM26, .ToReg: 77U },
3726 { .FromReg: X86::XMM27, .ToReg: 78U },
3727 { .FromReg: X86::XMM28, .ToReg: 79U },
3728 { .FromReg: X86::XMM29, .ToReg: 80U },
3729 { .FromReg: X86::XMM30, .ToReg: 81U },
3730 { .FromReg: X86::XMM31, .ToReg: 82U },
3731 { .FromReg: X86::YMM16, .ToReg: 67U },
3732 { .FromReg: X86::YMM17, .ToReg: 68U },
3733 { .FromReg: X86::YMM18, .ToReg: 69U },
3734 { .FromReg: X86::YMM19, .ToReg: 70U },
3735 { .FromReg: X86::YMM20, .ToReg: 71U },
3736 { .FromReg: X86::YMM21, .ToReg: 72U },
3737 { .FromReg: X86::YMM22, .ToReg: 73U },
3738 { .FromReg: X86::YMM23, .ToReg: 74U },
3739 { .FromReg: X86::YMM24, .ToReg: 75U },
3740 { .FromReg: X86::YMM25, .ToReg: 76U },
3741 { .FromReg: X86::YMM26, .ToReg: 77U },
3742 { .FromReg: X86::YMM27, .ToReg: 78U },
3743 { .FromReg: X86::YMM28, .ToReg: 79U },
3744 { .FromReg: X86::YMM29, .ToReg: 80U },
3745 { .FromReg: X86::YMM30, .ToReg: 81U },
3746 { .FromReg: X86::YMM31, .ToReg: 82U },
3747 { .FromReg: X86::ZMM0, .ToReg: 17U },
3748 { .FromReg: X86::ZMM1, .ToReg: 18U },
3749 { .FromReg: X86::ZMM2, .ToReg: 19U },
3750 { .FromReg: X86::ZMM3, .ToReg: 20U },
3751 { .FromReg: X86::ZMM4, .ToReg: 21U },
3752 { .FromReg: X86::ZMM5, .ToReg: 22U },
3753 { .FromReg: X86::ZMM6, .ToReg: 23U },
3754 { .FromReg: X86::ZMM7, .ToReg: 24U },
3755 { .FromReg: X86::ZMM8, .ToReg: 25U },
3756 { .FromReg: X86::ZMM9, .ToReg: 26U },
3757 { .FromReg: X86::ZMM10, .ToReg: 27U },
3758 { .FromReg: X86::ZMM11, .ToReg: 28U },
3759 { .FromReg: X86::ZMM12, .ToReg: 29U },
3760 { .FromReg: X86::ZMM13, .ToReg: 30U },
3761 { .FromReg: X86::ZMM14, .ToReg: 31U },
3762 { .FromReg: X86::ZMM15, .ToReg: 32U },
3763 { .FromReg: X86::ZMM16, .ToReg: 67U },
3764 { .FromReg: X86::ZMM17, .ToReg: 68U },
3765 { .FromReg: X86::ZMM18, .ToReg: 69U },
3766 { .FromReg: X86::ZMM19, .ToReg: 70U },
3767 { .FromReg: X86::ZMM20, .ToReg: 71U },
3768 { .FromReg: X86::ZMM21, .ToReg: 72U },
3769 { .FromReg: X86::ZMM22, .ToReg: 73U },
3770 { .FromReg: X86::ZMM23, .ToReg: 74U },
3771 { .FromReg: X86::ZMM24, .ToReg: 75U },
3772 { .FromReg: X86::ZMM25, .ToReg: 76U },
3773 { .FromReg: X86::ZMM26, .ToReg: 77U },
3774 { .FromReg: X86::ZMM27, .ToReg: 78U },
3775 { .FromReg: X86::ZMM28, .ToReg: 79U },
3776 { .FromReg: X86::ZMM29, .ToReg: 80U },
3777 { .FromReg: X86::ZMM30, .ToReg: 81U },
3778 { .FromReg: X86::ZMM31, .ToReg: 82U },
3779 { .FromReg: X86::R16, .ToReg: 130U },
3780 { .FromReg: X86::R17, .ToReg: 131U },
3781 { .FromReg: X86::R18, .ToReg: 132U },
3782 { .FromReg: X86::R19, .ToReg: 133U },
3783 { .FromReg: X86::R20, .ToReg: 134U },
3784 { .FromReg: X86::R21, .ToReg: 135U },
3785 { .FromReg: X86::R22, .ToReg: 136U },
3786 { .FromReg: X86::R23, .ToReg: 137U },
3787 { .FromReg: X86::R24, .ToReg: 138U },
3788 { .FromReg: X86::R25, .ToReg: 139U },
3789 { .FromReg: X86::R26, .ToReg: 140U },
3790 { .FromReg: X86::R27, .ToReg: 141U },
3791 { .FromReg: X86::R28, .ToReg: 142U },
3792 { .FromReg: X86::R29, .ToReg: 143U },
3793 { .FromReg: X86::R30, .ToReg: 144U },
3794 { .FromReg: X86::R31, .ToReg: 145U },
3795};
3796extern const unsigned X86EHFlavour0L2DwarfSize = std::size(X86EHFlavour0L2Dwarf);
3797
3798extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
3799 { .FromReg: X86::CS, .ToReg: -2U },
3800 { .FromReg: X86::DS, .ToReg: -2U },
3801 { .FromReg: X86::EAX, .ToReg: 0U },
3802 { .FromReg: X86::EBP, .ToReg: 4U },
3803 { .FromReg: X86::EBX, .ToReg: 3U },
3804 { .FromReg: X86::ECX, .ToReg: 1U },
3805 { .FromReg: X86::EDI, .ToReg: 7U },
3806 { .FromReg: X86::EDX, .ToReg: 2U },
3807 { .FromReg: X86::EFLAGS, .ToReg: 9U },
3808 { .FromReg: X86::EIP, .ToReg: 8U },
3809 { .FromReg: X86::ES, .ToReg: -2U },
3810 { .FromReg: X86::ESI, .ToReg: 6U },
3811 { .FromReg: X86::ESP, .ToReg: 5U },
3812 { .FromReg: X86::FS, .ToReg: -2U },
3813 { .FromReg: X86::FS_BASE, .ToReg: -2U },
3814 { .FromReg: X86::GS, .ToReg: -2U },
3815 { .FromReg: X86::GS_BASE, .ToReg: -2U },
3816 { .FromReg: X86::RAX, .ToReg: -2U },
3817 { .FromReg: X86::RBP, .ToReg: -2U },
3818 { .FromReg: X86::RBX, .ToReg: -2U },
3819 { .FromReg: X86::RCX, .ToReg: -2U },
3820 { .FromReg: X86::RDI, .ToReg: -2U },
3821 { .FromReg: X86::RDX, .ToReg: -2U },
3822 { .FromReg: X86::RFLAGS, .ToReg: -2U },
3823 { .FromReg: X86::RIP, .ToReg: -2U },
3824 { .FromReg: X86::RSI, .ToReg: -2U },
3825 { .FromReg: X86::RSP, .ToReg: -2U },
3826 { .FromReg: X86::SS, .ToReg: -2U },
3827 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
3828 { .FromReg: X86::MM0, .ToReg: 29U },
3829 { .FromReg: X86::MM1, .ToReg: 30U },
3830 { .FromReg: X86::MM2, .ToReg: 31U },
3831 { .FromReg: X86::MM3, .ToReg: 32U },
3832 { .FromReg: X86::MM4, .ToReg: 33U },
3833 { .FromReg: X86::MM5, .ToReg: 34U },
3834 { .FromReg: X86::MM6, .ToReg: 35U },
3835 { .FromReg: X86::MM7, .ToReg: 36U },
3836 { .FromReg: X86::R8, .ToReg: -2U },
3837 { .FromReg: X86::R9, .ToReg: -2U },
3838 { .FromReg: X86::R10, .ToReg: -2U },
3839 { .FromReg: X86::R11, .ToReg: -2U },
3840 { .FromReg: X86::R12, .ToReg: -2U },
3841 { .FromReg: X86::R13, .ToReg: -2U },
3842 { .FromReg: X86::R14, .ToReg: -2U },
3843 { .FromReg: X86::R15, .ToReg: -2U },
3844 { .FromReg: X86::ST0, .ToReg: 12U },
3845 { .FromReg: X86::ST1, .ToReg: 13U },
3846 { .FromReg: X86::ST2, .ToReg: 14U },
3847 { .FromReg: X86::ST3, .ToReg: 15U },
3848 { .FromReg: X86::ST4, .ToReg: 16U },
3849 { .FromReg: X86::ST5, .ToReg: 17U },
3850 { .FromReg: X86::ST6, .ToReg: 18U },
3851 { .FromReg: X86::ST7, .ToReg: 19U },
3852 { .FromReg: X86::XMM0, .ToReg: 21U },
3853 { .FromReg: X86::XMM1, .ToReg: 22U },
3854 { .FromReg: X86::XMM2, .ToReg: 23U },
3855 { .FromReg: X86::XMM3, .ToReg: 24U },
3856 { .FromReg: X86::XMM4, .ToReg: 25U },
3857 { .FromReg: X86::XMM5, .ToReg: 26U },
3858 { .FromReg: X86::XMM6, .ToReg: 27U },
3859 { .FromReg: X86::XMM7, .ToReg: 28U },
3860 { .FromReg: X86::XMM8, .ToReg: -2U },
3861 { .FromReg: X86::XMM9, .ToReg: -2U },
3862 { .FromReg: X86::XMM10, .ToReg: -2U },
3863 { .FromReg: X86::XMM11, .ToReg: -2U },
3864 { .FromReg: X86::XMM12, .ToReg: -2U },
3865 { .FromReg: X86::XMM13, .ToReg: -2U },
3866 { .FromReg: X86::XMM14, .ToReg: -2U },
3867 { .FromReg: X86::XMM15, .ToReg: -2U },
3868 { .FromReg: X86::YMM0, .ToReg: 21U },
3869 { .FromReg: X86::YMM1, .ToReg: 22U },
3870 { .FromReg: X86::YMM2, .ToReg: 23U },
3871 { .FromReg: X86::YMM3, .ToReg: 24U },
3872 { .FromReg: X86::YMM4, .ToReg: 25U },
3873 { .FromReg: X86::YMM5, .ToReg: 26U },
3874 { .FromReg: X86::YMM6, .ToReg: 27U },
3875 { .FromReg: X86::YMM7, .ToReg: 28U },
3876 { .FromReg: X86::YMM8, .ToReg: -2U },
3877 { .FromReg: X86::YMM9, .ToReg: -2U },
3878 { .FromReg: X86::YMM10, .ToReg: -2U },
3879 { .FromReg: X86::YMM11, .ToReg: -2U },
3880 { .FromReg: X86::YMM12, .ToReg: -2U },
3881 { .FromReg: X86::YMM13, .ToReg: -2U },
3882 { .FromReg: X86::YMM14, .ToReg: -2U },
3883 { .FromReg: X86::YMM15, .ToReg: -2U },
3884 { .FromReg: X86::K0, .ToReg: 93U },
3885 { .FromReg: X86::K1, .ToReg: 94U },
3886 { .FromReg: X86::K2, .ToReg: 95U },
3887 { .FromReg: X86::K3, .ToReg: 96U },
3888 { .FromReg: X86::K4, .ToReg: 97U },
3889 { .FromReg: X86::K5, .ToReg: 98U },
3890 { .FromReg: X86::K6, .ToReg: 99U },
3891 { .FromReg: X86::K7, .ToReg: 100U },
3892 { .FromReg: X86::XMM16, .ToReg: -2U },
3893 { .FromReg: X86::XMM17, .ToReg: -2U },
3894 { .FromReg: X86::XMM18, .ToReg: -2U },
3895 { .FromReg: X86::XMM19, .ToReg: -2U },
3896 { .FromReg: X86::XMM20, .ToReg: -2U },
3897 { .FromReg: X86::XMM21, .ToReg: -2U },
3898 { .FromReg: X86::XMM22, .ToReg: -2U },
3899 { .FromReg: X86::XMM23, .ToReg: -2U },
3900 { .FromReg: X86::XMM24, .ToReg: -2U },
3901 { .FromReg: X86::XMM25, .ToReg: -2U },
3902 { .FromReg: X86::XMM26, .ToReg: -2U },
3903 { .FromReg: X86::XMM27, .ToReg: -2U },
3904 { .FromReg: X86::XMM28, .ToReg: -2U },
3905 { .FromReg: X86::XMM29, .ToReg: -2U },
3906 { .FromReg: X86::XMM30, .ToReg: -2U },
3907 { .FromReg: X86::XMM31, .ToReg: -2U },
3908 { .FromReg: X86::YMM16, .ToReg: -2U },
3909 { .FromReg: X86::YMM17, .ToReg: -2U },
3910 { .FromReg: X86::YMM18, .ToReg: -2U },
3911 { .FromReg: X86::YMM19, .ToReg: -2U },
3912 { .FromReg: X86::YMM20, .ToReg: -2U },
3913 { .FromReg: X86::YMM21, .ToReg: -2U },
3914 { .FromReg: X86::YMM22, .ToReg: -2U },
3915 { .FromReg: X86::YMM23, .ToReg: -2U },
3916 { .FromReg: X86::YMM24, .ToReg: -2U },
3917 { .FromReg: X86::YMM25, .ToReg: -2U },
3918 { .FromReg: X86::YMM26, .ToReg: -2U },
3919 { .FromReg: X86::YMM27, .ToReg: -2U },
3920 { .FromReg: X86::YMM28, .ToReg: -2U },
3921 { .FromReg: X86::YMM29, .ToReg: -2U },
3922 { .FromReg: X86::YMM30, .ToReg: -2U },
3923 { .FromReg: X86::YMM31, .ToReg: -2U },
3924 { .FromReg: X86::ZMM0, .ToReg: 21U },
3925 { .FromReg: X86::ZMM1, .ToReg: 22U },
3926 { .FromReg: X86::ZMM2, .ToReg: 23U },
3927 { .FromReg: X86::ZMM3, .ToReg: 24U },
3928 { .FromReg: X86::ZMM4, .ToReg: 25U },
3929 { .FromReg: X86::ZMM5, .ToReg: 26U },
3930 { .FromReg: X86::ZMM6, .ToReg: 27U },
3931 { .FromReg: X86::ZMM7, .ToReg: 28U },
3932 { .FromReg: X86::ZMM8, .ToReg: -2U },
3933 { .FromReg: X86::ZMM9, .ToReg: -2U },
3934 { .FromReg: X86::ZMM10, .ToReg: -2U },
3935 { .FromReg: X86::ZMM11, .ToReg: -2U },
3936 { .FromReg: X86::ZMM12, .ToReg: -2U },
3937 { .FromReg: X86::ZMM13, .ToReg: -2U },
3938 { .FromReg: X86::ZMM14, .ToReg: -2U },
3939 { .FromReg: X86::ZMM15, .ToReg: -2U },
3940 { .FromReg: X86::ZMM16, .ToReg: -2U },
3941 { .FromReg: X86::ZMM17, .ToReg: -2U },
3942 { .FromReg: X86::ZMM18, .ToReg: -2U },
3943 { .FromReg: X86::ZMM19, .ToReg: -2U },
3944 { .FromReg: X86::ZMM20, .ToReg: -2U },
3945 { .FromReg: X86::ZMM21, .ToReg: -2U },
3946 { .FromReg: X86::ZMM22, .ToReg: -2U },
3947 { .FromReg: X86::ZMM23, .ToReg: -2U },
3948 { .FromReg: X86::ZMM24, .ToReg: -2U },
3949 { .FromReg: X86::ZMM25, .ToReg: -2U },
3950 { .FromReg: X86::ZMM26, .ToReg: -2U },
3951 { .FromReg: X86::ZMM27, .ToReg: -2U },
3952 { .FromReg: X86::ZMM28, .ToReg: -2U },
3953 { .FromReg: X86::ZMM29, .ToReg: -2U },
3954 { .FromReg: X86::ZMM30, .ToReg: -2U },
3955 { .FromReg: X86::ZMM31, .ToReg: -2U },
3956 { .FromReg: X86::R16, .ToReg: -2U },
3957 { .FromReg: X86::R17, .ToReg: -2U },
3958 { .FromReg: X86::R18, .ToReg: -2U },
3959 { .FromReg: X86::R19, .ToReg: -2U },
3960 { .FromReg: X86::R20, .ToReg: -2U },
3961 { .FromReg: X86::R21, .ToReg: -2U },
3962 { .FromReg: X86::R22, .ToReg: -2U },
3963 { .FromReg: X86::R23, .ToReg: -2U },
3964 { .FromReg: X86::R24, .ToReg: -2U },
3965 { .FromReg: X86::R25, .ToReg: -2U },
3966 { .FromReg: X86::R26, .ToReg: -2U },
3967 { .FromReg: X86::R27, .ToReg: -2U },
3968 { .FromReg: X86::R28, .ToReg: -2U },
3969 { .FromReg: X86::R29, .ToReg: -2U },
3970 { .FromReg: X86::R30, .ToReg: -2U },
3971 { .FromReg: X86::R31, .ToReg: -2U },
3972};
3973extern const unsigned X86EHFlavour1L2DwarfSize = std::size(X86EHFlavour1L2Dwarf);
3974
3975extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
3976 { .FromReg: X86::CS, .ToReg: 41U },
3977 { .FromReg: X86::DS, .ToReg: 43U },
3978 { .FromReg: X86::EAX, .ToReg: 0U },
3979 { .FromReg: X86::EBP, .ToReg: 5U },
3980 { .FromReg: X86::EBX, .ToReg: 3U },
3981 { .FromReg: X86::ECX, .ToReg: 1U },
3982 { .FromReg: X86::EDI, .ToReg: 7U },
3983 { .FromReg: X86::EDX, .ToReg: 2U },
3984 { .FromReg: X86::EFLAGS, .ToReg: 9U },
3985 { .FromReg: X86::EIP, .ToReg: 8U },
3986 { .FromReg: X86::ES, .ToReg: 40U },
3987 { .FromReg: X86::ESI, .ToReg: 6U },
3988 { .FromReg: X86::ESP, .ToReg: 4U },
3989 { .FromReg: X86::FS, .ToReg: 44U },
3990 { .FromReg: X86::FS_BASE, .ToReg: -2U },
3991 { .FromReg: X86::GS, .ToReg: 45U },
3992 { .FromReg: X86::GS_BASE, .ToReg: -2U },
3993 { .FromReg: X86::RAX, .ToReg: -2U },
3994 { .FromReg: X86::RBP, .ToReg: -2U },
3995 { .FromReg: X86::RBX, .ToReg: -2U },
3996 { .FromReg: X86::RCX, .ToReg: -2U },
3997 { .FromReg: X86::RDI, .ToReg: -2U },
3998 { .FromReg: X86::RDX, .ToReg: -2U },
3999 { .FromReg: X86::RFLAGS, .ToReg: -2U },
4000 { .FromReg: X86::RIP, .ToReg: -2U },
4001 { .FromReg: X86::RSI, .ToReg: -2U },
4002 { .FromReg: X86::RSP, .ToReg: -2U },
4003 { .FromReg: X86::SS, .ToReg: 42U },
4004 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
4005 { .FromReg: X86::MM0, .ToReg: 29U },
4006 { .FromReg: X86::MM1, .ToReg: 30U },
4007 { .FromReg: X86::MM2, .ToReg: 31U },
4008 { .FromReg: X86::MM3, .ToReg: 32U },
4009 { .FromReg: X86::MM4, .ToReg: 33U },
4010 { .FromReg: X86::MM5, .ToReg: 34U },
4011 { .FromReg: X86::MM6, .ToReg: 35U },
4012 { .FromReg: X86::MM7, .ToReg: 36U },
4013 { .FromReg: X86::R8, .ToReg: -2U },
4014 { .FromReg: X86::R9, .ToReg: -2U },
4015 { .FromReg: X86::R10, .ToReg: -2U },
4016 { .FromReg: X86::R11, .ToReg: -2U },
4017 { .FromReg: X86::R12, .ToReg: -2U },
4018 { .FromReg: X86::R13, .ToReg: -2U },
4019 { .FromReg: X86::R14, .ToReg: -2U },
4020 { .FromReg: X86::R15, .ToReg: -2U },
4021 { .FromReg: X86::ST0, .ToReg: 11U },
4022 { .FromReg: X86::ST1, .ToReg: 12U },
4023 { .FromReg: X86::ST2, .ToReg: 13U },
4024 { .FromReg: X86::ST3, .ToReg: 14U },
4025 { .FromReg: X86::ST4, .ToReg: 15U },
4026 { .FromReg: X86::ST5, .ToReg: 16U },
4027 { .FromReg: X86::ST6, .ToReg: 17U },
4028 { .FromReg: X86::ST7, .ToReg: 18U },
4029 { .FromReg: X86::XMM0, .ToReg: 21U },
4030 { .FromReg: X86::XMM1, .ToReg: 22U },
4031 { .FromReg: X86::XMM2, .ToReg: 23U },
4032 { .FromReg: X86::XMM3, .ToReg: 24U },
4033 { .FromReg: X86::XMM4, .ToReg: 25U },
4034 { .FromReg: X86::XMM5, .ToReg: 26U },
4035 { .FromReg: X86::XMM6, .ToReg: 27U },
4036 { .FromReg: X86::XMM7, .ToReg: 28U },
4037 { .FromReg: X86::XMM8, .ToReg: -2U },
4038 { .FromReg: X86::XMM9, .ToReg: -2U },
4039 { .FromReg: X86::XMM10, .ToReg: -2U },
4040 { .FromReg: X86::XMM11, .ToReg: -2U },
4041 { .FromReg: X86::XMM12, .ToReg: -2U },
4042 { .FromReg: X86::XMM13, .ToReg: -2U },
4043 { .FromReg: X86::XMM14, .ToReg: -2U },
4044 { .FromReg: X86::XMM15, .ToReg: -2U },
4045 { .FromReg: X86::YMM0, .ToReg: 21U },
4046 { .FromReg: X86::YMM1, .ToReg: 22U },
4047 { .FromReg: X86::YMM2, .ToReg: 23U },
4048 { .FromReg: X86::YMM3, .ToReg: 24U },
4049 { .FromReg: X86::YMM4, .ToReg: 25U },
4050 { .FromReg: X86::YMM5, .ToReg: 26U },
4051 { .FromReg: X86::YMM6, .ToReg: 27U },
4052 { .FromReg: X86::YMM7, .ToReg: 28U },
4053 { .FromReg: X86::YMM8, .ToReg: -2U },
4054 { .FromReg: X86::YMM9, .ToReg: -2U },
4055 { .FromReg: X86::YMM10, .ToReg: -2U },
4056 { .FromReg: X86::YMM11, .ToReg: -2U },
4057 { .FromReg: X86::YMM12, .ToReg: -2U },
4058 { .FromReg: X86::YMM13, .ToReg: -2U },
4059 { .FromReg: X86::YMM14, .ToReg: -2U },
4060 { .FromReg: X86::YMM15, .ToReg: -2U },
4061 { .FromReg: X86::K0, .ToReg: 93U },
4062 { .FromReg: X86::K1, .ToReg: 94U },
4063 { .FromReg: X86::K2, .ToReg: 95U },
4064 { .FromReg: X86::K3, .ToReg: 96U },
4065 { .FromReg: X86::K4, .ToReg: 97U },
4066 { .FromReg: X86::K5, .ToReg: 98U },
4067 { .FromReg: X86::K6, .ToReg: 99U },
4068 { .FromReg: X86::K7, .ToReg: 100U },
4069 { .FromReg: X86::XMM16, .ToReg: -2U },
4070 { .FromReg: X86::XMM17, .ToReg: -2U },
4071 { .FromReg: X86::XMM18, .ToReg: -2U },
4072 { .FromReg: X86::XMM19, .ToReg: -2U },
4073 { .FromReg: X86::XMM20, .ToReg: -2U },
4074 { .FromReg: X86::XMM21, .ToReg: -2U },
4075 { .FromReg: X86::XMM22, .ToReg: -2U },
4076 { .FromReg: X86::XMM23, .ToReg: -2U },
4077 { .FromReg: X86::XMM24, .ToReg: -2U },
4078 { .FromReg: X86::XMM25, .ToReg: -2U },
4079 { .FromReg: X86::XMM26, .ToReg: -2U },
4080 { .FromReg: X86::XMM27, .ToReg: -2U },
4081 { .FromReg: X86::XMM28, .ToReg: -2U },
4082 { .FromReg: X86::XMM29, .ToReg: -2U },
4083 { .FromReg: X86::XMM30, .ToReg: -2U },
4084 { .FromReg: X86::XMM31, .ToReg: -2U },
4085 { .FromReg: X86::YMM16, .ToReg: -2U },
4086 { .FromReg: X86::YMM17, .ToReg: -2U },
4087 { .FromReg: X86::YMM18, .ToReg: -2U },
4088 { .FromReg: X86::YMM19, .ToReg: -2U },
4089 { .FromReg: X86::YMM20, .ToReg: -2U },
4090 { .FromReg: X86::YMM21, .ToReg: -2U },
4091 { .FromReg: X86::YMM22, .ToReg: -2U },
4092 { .FromReg: X86::YMM23, .ToReg: -2U },
4093 { .FromReg: X86::YMM24, .ToReg: -2U },
4094 { .FromReg: X86::YMM25, .ToReg: -2U },
4095 { .FromReg: X86::YMM26, .ToReg: -2U },
4096 { .FromReg: X86::YMM27, .ToReg: -2U },
4097 { .FromReg: X86::YMM28, .ToReg: -2U },
4098 { .FromReg: X86::YMM29, .ToReg: -2U },
4099 { .FromReg: X86::YMM30, .ToReg: -2U },
4100 { .FromReg: X86::YMM31, .ToReg: -2U },
4101 { .FromReg: X86::ZMM0, .ToReg: 21U },
4102 { .FromReg: X86::ZMM1, .ToReg: 22U },
4103 { .FromReg: X86::ZMM2, .ToReg: 23U },
4104 { .FromReg: X86::ZMM3, .ToReg: 24U },
4105 { .FromReg: X86::ZMM4, .ToReg: 25U },
4106 { .FromReg: X86::ZMM5, .ToReg: 26U },
4107 { .FromReg: X86::ZMM6, .ToReg: 27U },
4108 { .FromReg: X86::ZMM7, .ToReg: 28U },
4109 { .FromReg: X86::ZMM8, .ToReg: -2U },
4110 { .FromReg: X86::ZMM9, .ToReg: -2U },
4111 { .FromReg: X86::ZMM10, .ToReg: -2U },
4112 { .FromReg: X86::ZMM11, .ToReg: -2U },
4113 { .FromReg: X86::ZMM12, .ToReg: -2U },
4114 { .FromReg: X86::ZMM13, .ToReg: -2U },
4115 { .FromReg: X86::ZMM14, .ToReg: -2U },
4116 { .FromReg: X86::ZMM15, .ToReg: -2U },
4117 { .FromReg: X86::ZMM16, .ToReg: -2U },
4118 { .FromReg: X86::ZMM17, .ToReg: -2U },
4119 { .FromReg: X86::ZMM18, .ToReg: -2U },
4120 { .FromReg: X86::ZMM19, .ToReg: -2U },
4121 { .FromReg: X86::ZMM20, .ToReg: -2U },
4122 { .FromReg: X86::ZMM21, .ToReg: -2U },
4123 { .FromReg: X86::ZMM22, .ToReg: -2U },
4124 { .FromReg: X86::ZMM23, .ToReg: -2U },
4125 { .FromReg: X86::ZMM24, .ToReg: -2U },
4126 { .FromReg: X86::ZMM25, .ToReg: -2U },
4127 { .FromReg: X86::ZMM26, .ToReg: -2U },
4128 { .FromReg: X86::ZMM27, .ToReg: -2U },
4129 { .FromReg: X86::ZMM28, .ToReg: -2U },
4130 { .FromReg: X86::ZMM29, .ToReg: -2U },
4131 { .FromReg: X86::ZMM30, .ToReg: -2U },
4132 { .FromReg: X86::ZMM31, .ToReg: -2U },
4133 { .FromReg: X86::R16, .ToReg: -2U },
4134 { .FromReg: X86::R17, .ToReg: -2U },
4135 { .FromReg: X86::R18, .ToReg: -2U },
4136 { .FromReg: X86::R19, .ToReg: -2U },
4137 { .FromReg: X86::R20, .ToReg: -2U },
4138 { .FromReg: X86::R21, .ToReg: -2U },
4139 { .FromReg: X86::R22, .ToReg: -2U },
4140 { .FromReg: X86::R23, .ToReg: -2U },
4141 { .FromReg: X86::R24, .ToReg: -2U },
4142 { .FromReg: X86::R25, .ToReg: -2U },
4143 { .FromReg: X86::R26, .ToReg: -2U },
4144 { .FromReg: X86::R27, .ToReg: -2U },
4145 { .FromReg: X86::R28, .ToReg: -2U },
4146 { .FromReg: X86::R29, .ToReg: -2U },
4147 { .FromReg: X86::R30, .ToReg: -2U },
4148 { .FromReg: X86::R31, .ToReg: -2U },
4149};
4150extern const unsigned X86EHFlavour2L2DwarfSize = std::size(X86EHFlavour2L2Dwarf);
4151
4152extern const uint16_t X86RegEncodingTable[] = {
4153 0,
4154 4,
4155 0,
4156 0,
4157 7,
4158 3,
4159 5,
4160 65535,
4161 5,
4162 3,
4163 5,
4164 1,
4165 1,
4166 1,
4167 0,
4168 6,
4169 7,
4170 65535,
4171 7,
4172 2,
4173 3,
4174 2,
4175 0,
4176 5,
4177 3,
4178 1,
4179 7,
4180 2,
4181 0,
4182 0,
4183 4,
4184 0,
4185 6,
4186 4,
4187 0,
4188 0,
4189 4,
4190 0,
4191 5,
4192 0,
4193 65535,
4194 65535,
4195 65535,
4196 65535,
4197 65535,
4198 65535,
4199 65535,
4200 65535,
4201 65535,
4202 0,
4203 0,
4204 0,
4205 5,
4206 3,
4207 1,
4208 7,
4209 2,
4210 0,
4211 0,
4212 4,
4213 6,
4214 4,
4215 6,
4216 65535,
4217 6,
4218 4,
4219 65535,
4220 4,
4221 2,
4222 0,
4223 0,
4224 0,
4225 1,
4226 2,
4227 3,
4228 4,
4229 5,
4230 6,
4231 7,
4232 8,
4233 9,
4234 10,
4235 11,
4236 12,
4237 13,
4238 14,
4239 15,
4240 0,
4241 1,
4242 2,
4243 3,
4244 4,
4245 5,
4246 6,
4247 7,
4248 8,
4249 9,
4250 10,
4251 11,
4252 12,
4253 13,
4254 14,
4255 15,
4256 0,
4257 0,
4258 0,
4259 0,
4260 0,
4261 0,
4262 0,
4263 0,
4264 0,
4265 1,
4266 2,
4267 3,
4268 4,
4269 5,
4270 6,
4271 7,
4272 8,
4273 9,
4274 10,
4275 11,
4276 12,
4277 13,
4278 14,
4279 15,
4280 0,
4281 1,
4282 2,
4283 3,
4284 4,
4285 5,
4286 6,
4287 7,
4288 0,
4289 1,
4290 2,
4291 3,
4292 4,
4293 5,
4294 6,
4295 7,
4296 8,
4297 9,
4298 10,
4299 11,
4300 12,
4301 13,
4302 14,
4303 15,
4304 8,
4305 9,
4306 10,
4307 11,
4308 12,
4309 13,
4310 14,
4311 15,
4312 65535,
4313 65535,
4314 65535,
4315 65535,
4316 65535,
4317 65535,
4318 65535,
4319 65535,
4320 8,
4321 9,
4322 10,
4323 11,
4324 12,
4325 13,
4326 14,
4327 15,
4328 8,
4329 9,
4330 10,
4331 11,
4332 12,
4333 13,
4334 14,
4335 15,
4336 65535,
4337 65535,
4338 65535,
4339 65535,
4340 65535,
4341 65535,
4342 65535,
4343 65535,
4344 0,
4345 1,
4346 2,
4347 3,
4348 4,
4349 5,
4350 6,
4351 7,
4352 8,
4353 9,
4354 10,
4355 11,
4356 12,
4357 13,
4358 14,
4359 15,
4360 0,
4361 1,
4362 2,
4363 3,
4364 4,
4365 5,
4366 6,
4367 7,
4368 16,
4369 17,
4370 18,
4371 19,
4372 20,
4373 21,
4374 22,
4375 23,
4376 24,
4377 25,
4378 26,
4379 27,
4380 28,
4381 29,
4382 30,
4383 31,
4384 16,
4385 17,
4386 18,
4387 19,
4388 20,
4389 21,
4390 22,
4391 23,
4392 24,
4393 25,
4394 26,
4395 27,
4396 28,
4397 29,
4398 30,
4399 31,
4400 0,
4401 1,
4402 2,
4403 3,
4404 4,
4405 5,
4406 6,
4407 7,
4408 8,
4409 9,
4410 10,
4411 11,
4412 12,
4413 13,
4414 14,
4415 15,
4416 16,
4417 17,
4418 18,
4419 19,
4420 20,
4421 21,
4422 22,
4423 23,
4424 24,
4425 25,
4426 26,
4427 27,
4428 28,
4429 29,
4430 30,
4431 31,
4432 0,
4433 2,
4434 4,
4435 6,
4436 0,
4437 0,
4438 1,
4439 2,
4440 3,
4441 4,
4442 5,
4443 6,
4444 7,
4445 16,
4446 17,
4447 18,
4448 19,
4449 20,
4450 21,
4451 22,
4452 23,
4453 24,
4454 25,
4455 26,
4456 27,
4457 28,
4458 29,
4459 30,
4460 31,
4461 16,
4462 17,
4463 18,
4464 19,
4465 20,
4466 21,
4467 22,
4468 23,
4469 24,
4470 25,
4471 26,
4472 27,
4473 28,
4474 29,
4475 30,
4476 31,
4477 65535,
4478 65535,
4479 65535,
4480 65535,
4481 65535,
4482 65535,
4483 65535,
4484 65535,
4485 65535,
4486 65535,
4487 65535,
4488 65535,
4489 65535,
4490 65535,
4491 65535,
4492 65535,
4493 16,
4494 17,
4495 18,
4496 19,
4497 20,
4498 21,
4499 22,
4500 23,
4501 24,
4502 25,
4503 26,
4504 27,
4505 28,
4506 29,
4507 30,
4508 31,
4509 16,
4510 17,
4511 18,
4512 19,
4513 20,
4514 21,
4515 22,
4516 23,
4517 24,
4518 25,
4519 26,
4520 27,
4521 28,
4522 29,
4523 30,
4524 31,
4525 65535,
4526 65535,
4527 65535,
4528 65535,
4529 65535,
4530 65535,
4531 65535,
4532 65535,
4533 65535,
4534 65535,
4535 65535,
4536 65535,
4537 65535,
4538 65535,
4539 65535,
4540 65535,
4541};
4542static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
4543 RI->InitMCRegisterInfo(D: X86RegDesc, NR: 388, RA, PC, C: X86MCRegisterClasses, NC: 135, RURoots: X86RegUnitRoots, NRU: 221, DL: X86RegDiffLists, RUMS: X86LaneMaskLists, Strings: X86RegStrings, ClassStrings: X86RegClassStrings, SubIndices: X86SubRegIdxLists, NumIndices: 11,
4544RET: X86RegEncodingTable, RUI: nullptr);
4545
4546 switch (DwarfFlavour) {
4547 default:
4548 llvm_unreachable("Unknown DWARF flavour");
4549 case 0:
4550 RI->mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour0Dwarf2L, Size: X86DwarfFlavour0Dwarf2LSize, isEH: false);
4551 break;
4552 case 1:
4553 RI->mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour1Dwarf2L, Size: X86DwarfFlavour1Dwarf2LSize, isEH: false);
4554 break;
4555 case 2:
4556 RI->mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour2Dwarf2L, Size: X86DwarfFlavour2Dwarf2LSize, isEH: false);
4557 break;
4558 }
4559 switch (EHFlavour) {
4560 default:
4561 llvm_unreachable("Unknown DWARF flavour");
4562 case 0:
4563 RI->mapDwarfRegsToLLVMRegs(Map: X86EHFlavour0Dwarf2L, Size: X86EHFlavour0Dwarf2LSize, isEH: true);
4564 break;
4565 case 1:
4566 RI->mapDwarfRegsToLLVMRegs(Map: X86EHFlavour1Dwarf2L, Size: X86EHFlavour1Dwarf2LSize, isEH: true);
4567 break;
4568 case 2:
4569 RI->mapDwarfRegsToLLVMRegs(Map: X86EHFlavour2Dwarf2L, Size: X86EHFlavour2Dwarf2LSize, isEH: true);
4570 break;
4571 }
4572 switch (DwarfFlavour) {
4573 default:
4574 llvm_unreachable("Unknown DWARF flavour");
4575 case 0:
4576 RI->mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour0L2Dwarf, Size: X86DwarfFlavour0L2DwarfSize, isEH: false);
4577 break;
4578 case 1:
4579 RI->mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour1L2Dwarf, Size: X86DwarfFlavour1L2DwarfSize, isEH: false);
4580 break;
4581 case 2:
4582 RI->mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour2L2Dwarf, Size: X86DwarfFlavour2L2DwarfSize, isEH: false);
4583 break;
4584 }
4585 switch (EHFlavour) {
4586 default:
4587 llvm_unreachable("Unknown DWARF flavour");
4588 case 0:
4589 RI->mapLLVMRegsToDwarfRegs(Map: X86EHFlavour0L2Dwarf, Size: X86EHFlavour0L2DwarfSize, isEH: true);
4590 break;
4591 case 1:
4592 RI->mapLLVMRegsToDwarfRegs(Map: X86EHFlavour1L2Dwarf, Size: X86EHFlavour1L2DwarfSize, isEH: true);
4593 break;
4594 case 2:
4595 RI->mapLLVMRegsToDwarfRegs(Map: X86EHFlavour2L2Dwarf, Size: X86EHFlavour2L2DwarfSize, isEH: true);
4596 break;
4597 }
4598}
4599
4600
4601} // namespace llvm
4602