1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t X86RegDiffLists[] = {
12 /* 0 */ -56, -56, 0,
13 /* 3 */ -32, -48, 0,
14 /* 6 */ 32, -16, -48, 0,
15 /* 10 */ 48, -16, -48, 0,
16 /* 14 */ 16, -8, -48, 0,
17 /* 18 */ 24, -8, -48, 0,
18 /* 22 */ -28, 32, 2, -1, -18, 0,
19 /* 28 */ -32, -16, 0,
20 /* 31 */ -28, 30, 2, -1, -16, 0,
21 /* 37 */ -2, -4, 0,
22 /* 40 */ -29, 20, -3, 0,
23 /* 44 */ -4, -1, 0,
24 /* 47 */ -2, -1, 0,
25 /* 50 */ -1, -1, 0,
26 /* 53 */ 2, -1, 0,
27 /* 56 */ -72, 1, 0,
28 /* 59 */ -71, 1, 0,
29 /* 62 */ -70, 1, 0,
30 /* 65 */ -69, 1, 0,
31 /* 68 */ 1, 1, 0,
32 /* 71 */ 3, 0,
33 /* 73 */ 1, 7, 0,
34 /* 76 */ 3, 7, 0,
35 /* 79 */ -24, 8, 0,
36 /* 82 */ 1, 11, 0,
37 /* 85 */ 1, 14, 0,
38 /* 88 */ -48, 16, 0,
39 /* 91 */ 48, 8, -24, 8, 24, 0,
40 /* 97 */ -29, -10, 2, -1, 27, 0,
41 /* 103 */ -2, -32, 28, 0,
42 /* 107 */ -1, -32, 28, 0,
43 /* 111 */ -2, -30, 28, 0,
44 /* 115 */ -1, -30, 28, 0,
45 /* 119 */ -15, 28, 0,
46 /* 122 */ -20, 29, 0,
47 /* 125 */ -18, 29, 0,
48 /* 128 */ -17, 29, 0,
49 /* 131 */ 2, 6, 29, 0,
50 /* 135 */ 6, 6, 29, 0,
51 /* 139 */ -2, 10, 29, 0,
52 /* 143 */ -1, 10, 29, 0,
53 /* 147 */ 2, 12, 29, 0,
54 /* 151 */ 3, 12, 29, 0,
55 /* 155 */ 4, 15, 29, 0,
56 /* 159 */ 5, 15, 29, 0,
57 /* 163 */ -2, 17, 29, 0,
58 /* 167 */ -1, 17, 29, 0,
59 /* 171 */ 1, 19, 29, 0,
60 /* 175 */ 2, 19, 29, 0,
61 /* 179 */ -29, -6, -2, -4, 30, 0,
62 /* 185 */ 16, 32, 0,
63 /* 188 */ -29, -12, -2, -1, 33, 0,
64 /* 194 */ -29, -17, 2, -1, 34, 0,
65 /* 200 */ -29, -15, -4, -1, 38, 0,
66 /* 206 */ -29, -19, -1, -1, 39, 0,
67 /* 212 */ 48, 16, -48, 16, 48, 0,
68 /* 218 */ 56, 56, 0,
69 /* 221 */ 68, 0,
70 /* 223 */ 69, 0,
71 /* 225 */ 70, 0,
72 /* 227 */ 71, 0,
73 /* 229 */ 72, 0,
74};
75
76extern const LaneBitmask X86LaneMaskLists[] = {
77 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
78 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004),
79 /* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000008),
80 /* 7 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
81 /* 10 */ LaneBitmask(0x0000000000000007), LaneBitmask(0x0000000000000008),
82 /* 12 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020),
83 /* 14 */ LaneBitmask(0x0000000000000040),
84 /* 15 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
85};
86
87extern const uint16_t X86SubRegIdxLists[] = {
88 /* 0 */ 1, 2,
89 /* 2 */ 1, 3,
90 /* 4 */ 6, 4, 1, 2, 5,
91 /* 9 */ 6, 4, 1, 3, 5,
92 /* 14 */ 6, 4, 5,
93 /* 17 */ 7, 8,
94 /* 19 */ 10, 9,
95};
96
97
98#ifdef __GNUC__
99#pragma GCC diagnostic push
100#pragma GCC diagnostic ignored "-Woverlength-strings"
101#endif
102extern const char X86RegStrings[] = {
103 /* 0 */ "XMM10\000"
104 /* 6 */ "YMM10\000"
105 /* 12 */ "ZMM10\000"
106 /* 18 */ "CR10\000"
107 /* 23 */ "DR10\000"
108 /* 28 */ "XMM20\000"
109 /* 34 */ "YMM20\000"
110 /* 40 */ "ZMM20\000"
111 /* 46 */ "R20\000"
112 /* 50 */ "XMM30\000"
113 /* 56 */ "YMM30\000"
114 /* 62 */ "ZMM30\000"
115 /* 68 */ "R30\000"
116 /* 72 */ "K0\000"
117 /* 75 */ "TMM0\000"
118 /* 80 */ "XMM0\000"
119 /* 85 */ "YMM0\000"
120 /* 90 */ "ZMM0\000"
121 /* 95 */ "FP0\000"
122 /* 99 */ "CR0\000"
123 /* 103 */ "DR0\000"
124 /* 107 */ "ST0\000"
125 /* 111 */ "XMM11\000"
126 /* 117 */ "YMM11\000"
127 /* 123 */ "ZMM11\000"
128 /* 129 */ "CR11\000"
129 /* 134 */ "DR11\000"
130 /* 139 */ "XMM21\000"
131 /* 145 */ "YMM21\000"
132 /* 151 */ "ZMM21\000"
133 /* 157 */ "R21\000"
134 /* 161 */ "XMM31\000"
135 /* 167 */ "YMM31\000"
136 /* 173 */ "ZMM31\000"
137 /* 179 */ "R31\000"
138 /* 183 */ "K0_K1\000"
139 /* 189 */ "TMM1\000"
140 /* 194 */ "XMM1\000"
141 /* 199 */ "YMM1\000"
142 /* 204 */ "ZMM1\000"
143 /* 209 */ "FP1\000"
144 /* 213 */ "CR1\000"
145 /* 217 */ "DR1\000"
146 /* 221 */ "ST1\000"
147 /* 225 */ "XMM12\000"
148 /* 231 */ "YMM12\000"
149 /* 237 */ "ZMM12\000"
150 /* 243 */ "CR12\000"
151 /* 248 */ "DR12\000"
152 /* 253 */ "XMM22\000"
153 /* 259 */ "YMM22\000"
154 /* 265 */ "ZMM22\000"
155 /* 271 */ "R22\000"
156 /* 275 */ "K2\000"
157 /* 278 */ "TMM2\000"
158 /* 283 */ "XMM2\000"
159 /* 288 */ "YMM2\000"
160 /* 293 */ "ZMM2\000"
161 /* 298 */ "FP2\000"
162 /* 302 */ "CR2\000"
163 /* 306 */ "DR2\000"
164 /* 310 */ "ST2\000"
165 /* 314 */ "XMM13\000"
166 /* 320 */ "YMM13\000"
167 /* 326 */ "ZMM13\000"
168 /* 332 */ "CR13\000"
169 /* 337 */ "DR13\000"
170 /* 342 */ "XMM23\000"
171 /* 348 */ "YMM23\000"
172 /* 354 */ "ZMM23\000"
173 /* 360 */ "R23\000"
174 /* 364 */ "K2_K3\000"
175 /* 370 */ "TMM3\000"
176 /* 375 */ "XMM3\000"
177 /* 380 */ "YMM3\000"
178 /* 385 */ "ZMM3\000"
179 /* 390 */ "FP3\000"
180 /* 394 */ "CR3\000"
181 /* 398 */ "DR3\000"
182 /* 402 */ "ST3\000"
183 /* 406 */ "XMM14\000"
184 /* 412 */ "YMM14\000"
185 /* 418 */ "ZMM14\000"
186 /* 424 */ "CR14\000"
187 /* 429 */ "DR14\000"
188 /* 434 */ "XMM24\000"
189 /* 440 */ "YMM24\000"
190 /* 446 */ "ZMM24\000"
191 /* 452 */ "R24\000"
192 /* 456 */ "K4\000"
193 /* 459 */ "TMM4\000"
194 /* 464 */ "XMM4\000"
195 /* 469 */ "YMM4\000"
196 /* 474 */ "ZMM4\000"
197 /* 479 */ "FP4\000"
198 /* 483 */ "CR4\000"
199 /* 487 */ "DR4\000"
200 /* 491 */ "ST4\000"
201 /* 495 */ "XMM15\000"
202 /* 501 */ "YMM15\000"
203 /* 507 */ "ZMM15\000"
204 /* 513 */ "CR15\000"
205 /* 518 */ "DR15\000"
206 /* 523 */ "XMM25\000"
207 /* 529 */ "YMM25\000"
208 /* 535 */ "ZMM25\000"
209 /* 541 */ "R25\000"
210 /* 545 */ "K4_K5\000"
211 /* 551 */ "TMM5\000"
212 /* 556 */ "XMM5\000"
213 /* 561 */ "YMM5\000"
214 /* 566 */ "ZMM5\000"
215 /* 571 */ "FP5\000"
216 /* 575 */ "CR5\000"
217 /* 579 */ "DR5\000"
218 /* 583 */ "ST5\000"
219 /* 587 */ "XMM16\000"
220 /* 593 */ "YMM16\000"
221 /* 599 */ "ZMM16\000"
222 /* 605 */ "R16\000"
223 /* 609 */ "XMM26\000"
224 /* 615 */ "YMM26\000"
225 /* 621 */ "ZMM26\000"
226 /* 627 */ "R26\000"
227 /* 631 */ "K6\000"
228 /* 634 */ "TMM6\000"
229 /* 639 */ "XMM6\000"
230 /* 644 */ "YMM6\000"
231 /* 649 */ "ZMM6\000"
232 /* 654 */ "FP6\000"
233 /* 658 */ "CR6\000"
234 /* 662 */ "DR6\000"
235 /* 666 */ "ST6\000"
236 /* 670 */ "XMM17\000"
237 /* 676 */ "YMM17\000"
238 /* 682 */ "ZMM17\000"
239 /* 688 */ "R17\000"
240 /* 692 */ "XMM27\000"
241 /* 698 */ "YMM27\000"
242 /* 704 */ "ZMM27\000"
243 /* 710 */ "R27\000"
244 /* 714 */ "K6_K7\000"
245 /* 720 */ "TMM7\000"
246 /* 725 */ "XMM7\000"
247 /* 730 */ "YMM7\000"
248 /* 735 */ "ZMM7\000"
249 /* 740 */ "FP7\000"
250 /* 744 */ "CR7\000"
251 /* 748 */ "DR7\000"
252 /* 752 */ "ST7\000"
253 /* 756 */ "XMM18\000"
254 /* 762 */ "YMM18\000"
255 /* 768 */ "ZMM18\000"
256 /* 774 */ "R18\000"
257 /* 778 */ "XMM28\000"
258 /* 784 */ "YMM28\000"
259 /* 790 */ "ZMM28\000"
260 /* 796 */ "R28\000"
261 /* 800 */ "XMM8\000"
262 /* 805 */ "YMM8\000"
263 /* 810 */ "ZMM8\000"
264 /* 815 */ "CR8\000"
265 /* 819 */ "DR8\000"
266 /* 823 */ "XMM19\000"
267 /* 829 */ "YMM19\000"
268 /* 835 */ "ZMM19\000"
269 /* 841 */ "R19\000"
270 /* 845 */ "XMM29\000"
271 /* 851 */ "YMM29\000"
272 /* 857 */ "ZMM29\000"
273 /* 863 */ "R29\000"
274 /* 867 */ "XMM9\000"
275 /* 872 */ "YMM9\000"
276 /* 877 */ "ZMM9\000"
277 /* 882 */ "CR9\000"
278 /* 886 */ "DR9\000"
279 /* 890 */ "R10B\000"
280 /* 895 */ "R20B\000"
281 /* 900 */ "R30B\000"
282 /* 905 */ "R11B\000"
283 /* 910 */ "R21B\000"
284 /* 915 */ "R31B\000"
285 /* 920 */ "R12B\000"
286 /* 925 */ "R22B\000"
287 /* 930 */ "R13B\000"
288 /* 935 */ "R23B\000"
289 /* 940 */ "R14B\000"
290 /* 945 */ "R24B\000"
291 /* 950 */ "R15B\000"
292 /* 955 */ "R25B\000"
293 /* 960 */ "R16B\000"
294 /* 965 */ "R26B\000"
295 /* 970 */ "R17B\000"
296 /* 975 */ "R27B\000"
297 /* 980 */ "R18B\000"
298 /* 985 */ "R28B\000"
299 /* 990 */ "R8B\000"
300 /* 994 */ "R19B\000"
301 /* 999 */ "R29B\000"
302 /* 1004 */ "R9B\000"
303 /* 1008 */ "R10D\000"
304 /* 1013 */ "R20D\000"
305 /* 1018 */ "R30D\000"
306 /* 1023 */ "R11D\000"
307 /* 1028 */ "R21D\000"
308 /* 1033 */ "R31D\000"
309 /* 1038 */ "R12D\000"
310 /* 1043 */ "R22D\000"
311 /* 1048 */ "R13D\000"
312 /* 1053 */ "R23D\000"
313 /* 1058 */ "R14D\000"
314 /* 1063 */ "R24D\000"
315 /* 1068 */ "R15D\000"
316 /* 1073 */ "R25D\000"
317 /* 1078 */ "R16D\000"
318 /* 1083 */ "R26D\000"
319 /* 1088 */ "R17D\000"
320 /* 1093 */ "R27D\000"
321 /* 1098 */ "R18D\000"
322 /* 1103 */ "R28D\000"
323 /* 1108 */ "R8D\000"
324 /* 1112 */ "R19D\000"
325 /* 1117 */ "R29D\000"
326 /* 1122 */ "R9D\000"
327 /* 1126 */ "FS_BASE\000"
328 /* 1134 */ "GS_BASE\000"
329 /* 1142 */ "DF\000"
330 /* 1145 */ "TMMCFG\000"
331 /* 1152 */ "AH\000"
332 /* 1155 */ "R10BH\000"
333 /* 1161 */ "R20BH\000"
334 /* 1167 */ "R30BH\000"
335 /* 1173 */ "R11BH\000"
336 /* 1179 */ "R21BH\000"
337 /* 1185 */ "R31BH\000"
338 /* 1191 */ "R12BH\000"
339 /* 1197 */ "R22BH\000"
340 /* 1203 */ "R13BH\000"
341 /* 1209 */ "R23BH\000"
342 /* 1215 */ "R14BH\000"
343 /* 1221 */ "R24BH\000"
344 /* 1227 */ "R15BH\000"
345 /* 1233 */ "R25BH\000"
346 /* 1239 */ "R16BH\000"
347 /* 1245 */ "R26BH\000"
348 /* 1251 */ "R17BH\000"
349 /* 1257 */ "R27BH\000"
350 /* 1263 */ "R18BH\000"
351 /* 1269 */ "R28BH\000"
352 /* 1275 */ "R8BH\000"
353 /* 1280 */ "R19BH\000"
354 /* 1286 */ "R29BH\000"
355 /* 1292 */ "R9BH\000"
356 /* 1297 */ "CH\000"
357 /* 1300 */ "DH\000"
358 /* 1303 */ "DIH\000"
359 /* 1307 */ "SIH\000"
360 /* 1311 */ "BPH\000"
361 /* 1315 */ "SPH\000"
362 /* 1319 */ "R10WH\000"
363 /* 1325 */ "R20WH\000"
364 /* 1331 */ "R30WH\000"
365 /* 1337 */ "R11WH\000"
366 /* 1343 */ "R21WH\000"
367 /* 1349 */ "R31WH\000"
368 /* 1355 */ "R12WH\000"
369 /* 1361 */ "R22WH\000"
370 /* 1367 */ "R13WH\000"
371 /* 1373 */ "R23WH\000"
372 /* 1379 */ "R14WH\000"
373 /* 1385 */ "R24WH\000"
374 /* 1391 */ "R15WH\000"
375 /* 1397 */ "R25WH\000"
376 /* 1403 */ "R16WH\000"
377 /* 1409 */ "R26WH\000"
378 /* 1415 */ "R17WH\000"
379 /* 1421 */ "R27WH\000"
380 /* 1427 */ "R18WH\000"
381 /* 1433 */ "R28WH\000"
382 /* 1439 */ "R8WH\000"
383 /* 1444 */ "R19WH\000"
384 /* 1450 */ "R29WH\000"
385 /* 1456 */ "R9WH\000"
386 /* 1461 */ "EDI\000"
387 /* 1465 */ "HDI\000"
388 /* 1469 */ "RDI\000"
389 /* 1473 */ "ESI\000"
390 /* 1477 */ "HSI\000"
391 /* 1481 */ "RSI\000"
392 /* 1485 */ "AL\000"
393 /* 1488 */ "BL\000"
394 /* 1491 */ "CL\000"
395 /* 1494 */ "DL\000"
396 /* 1497 */ "DIL\000"
397 /* 1501 */ "SIL\000"
398 /* 1505 */ "BPL\000"
399 /* 1509 */ "SPL\000"
400 /* 1513 */ "EBP\000"
401 /* 1517 */ "HBP\000"
402 /* 1521 */ "RBP\000"
403 /* 1525 */ "EIP\000"
404 /* 1529 */ "HIP\000"
405 /* 1533 */ "RIP\000"
406 /* 1537 */ "ESP\000"
407 /* 1541 */ "HSP\000"
408 /* 1545 */ "RSP\000"
409 /* 1549 */ "SSP\000"
410 /* 1553 */ "MXCSR\000"
411 /* 1559 */ "CS\000"
412 /* 1562 */ "DS\000"
413 /* 1565 */ "ES\000"
414 /* 1568 */ "FS\000"
415 /* 1571 */ "_EFLAGS\000"
416 /* 1579 */ "RFLAGS\000"
417 /* 1586 */ "SS\000"
418 /* 1589 */ "R10W\000"
419 /* 1594 */ "R20W\000"
420 /* 1599 */ "R30W\000"
421 /* 1604 */ "R11W\000"
422 /* 1609 */ "R21W\000"
423 /* 1614 */ "R31W\000"
424 /* 1619 */ "R12W\000"
425 /* 1624 */ "R22W\000"
426 /* 1629 */ "R13W\000"
427 /* 1634 */ "R23W\000"
428 /* 1639 */ "R14W\000"
429 /* 1644 */ "R24W\000"
430 /* 1649 */ "R15W\000"
431 /* 1654 */ "R25W\000"
432 /* 1659 */ "R16W\000"
433 /* 1664 */ "R26W\000"
434 /* 1669 */ "R17W\000"
435 /* 1674 */ "R27W\000"
436 /* 1679 */ "R18W\000"
437 /* 1684 */ "R28W\000"
438 /* 1689 */ "R8W\000"
439 /* 1693 */ "R19W\000"
440 /* 1698 */ "R29W\000"
441 /* 1703 */ "R9W\000"
442 /* 1707 */ "FPCW\000"
443 /* 1712 */ "FPSW\000"
444 /* 1717 */ "EAX\000"
445 /* 1721 */ "HAX\000"
446 /* 1725 */ "RAX\000"
447 /* 1729 */ "EBX\000"
448 /* 1733 */ "HBX\000"
449 /* 1737 */ "RBX\000"
450 /* 1741 */ "ECX\000"
451 /* 1745 */ "HCX\000"
452 /* 1749 */ "RCX\000"
453 /* 1753 */ "EDX\000"
454 /* 1757 */ "HDX\000"
455 /* 1761 */ "RDX\000"
456 /* 1765 */ "EIZ\000"
457 /* 1769 */ "RIZ\000"
458};
459#ifdef __GNUC__
460#pragma GCC diagnostic pop
461#endif
462
463extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
464 { .Name: 5, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
465 { .Name: 1152, .SubRegs: 2, .SuperRegs: 175, .SubRegIndices: 2, .RegUnits: 8192, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
466 { .Name: 1485, .SubRegs: 2, .SuperRegs: 171, .SubRegIndices: 2, .RegUnits: 8193, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
467 { .Name: 1718, .SubRegs: 50, .SuperRegs: 172, .SubRegIndices: 0, .RegUnits: 233472, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
468 { .Name: 1158, .SubRegs: 2, .SuperRegs: 159, .SubRegIndices: 2, .RegUnits: 8194, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
469 { .Name: 1488, .SubRegs: 2, .SuperRegs: 155, .SubRegIndices: 2, .RegUnits: 8195, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
470 { .Name: 1514, .SubRegs: 53, .SuperRegs: 164, .SubRegIndices: 2, .RegUnits: 233476, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
471 { .Name: 1311, .SubRegs: 2, .SuperRegs: 167, .SubRegIndices: 2, .RegUnits: 8197, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
472 { .Name: 1505, .SubRegs: 2, .SuperRegs: 163, .SubRegIndices: 2, .RegUnits: 8196, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
473 { .Name: 1730, .SubRegs: 44, .SuperRegs: 156, .SubRegIndices: 0, .RegUnits: 233474, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
474 { .Name: 1297, .SubRegs: 2, .SuperRegs: 151, .SubRegIndices: 2, .RegUnits: 8198, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
475 { .Name: 1491, .SubRegs: 2, .SuperRegs: 147, .SubRegIndices: 2, .RegUnits: 8199, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
476 { .Name: 1559, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8200, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
477 { .Name: 1742, .SubRegs: 47, .SuperRegs: 148, .SubRegIndices: 0, .RegUnits: 233478, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
478 { .Name: 1142, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8201, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
479 { .Name: 1300, .SubRegs: 2, .SuperRegs: 135, .SubRegIndices: 2, .RegUnits: 8202, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
480 { .Name: 1462, .SubRegs: 53, .SuperRegs: 140, .SubRegIndices: 2, .RegUnits: 233483, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
481 { .Name: 1303, .SubRegs: 2, .SuperRegs: 143, .SubRegIndices: 2, .RegUnits: 8204, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
482 { .Name: 1497, .SubRegs: 2, .SuperRegs: 139, .SubRegIndices: 2, .RegUnits: 8203, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
483 { .Name: 1494, .SubRegs: 2, .SuperRegs: 131, .SubRegIndices: 2, .RegUnits: 8205, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
484 { .Name: 1562, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8206, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
485 { .Name: 1754, .SubRegs: 37, .SuperRegs: 132, .SubRegIndices: 0, .RegUnits: 290826, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
486 { .Name: 1717, .SubRegs: 207, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 348160, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
487 { .Name: 1513, .SubRegs: 195, .SuperRegs: 123, .SubRegIndices: 10, .RegUnits: 335876, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
488 { .Name: 1729, .SubRegs: 201, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 348162, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
489 { .Name: 1741, .SubRegs: 189, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 335878, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
490 { .Name: 1461, .SubRegs: 98, .SuperRegs: 123, .SubRegIndices: 10, .RegUnits: 299019, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
491 { .Name: 1753, .SubRegs: 180, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 311306, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
492 { .Name: 1572, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8213, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
493 { .Name: 1525, .SubRegs: 41, .SuperRegs: 123, .SubRegIndices: 15, .RegUnits: 233494, .RegUnitLaneMasks: 10, .IsConstant: 0, .IsArtificial: 0 },
494 { .Name: 1765, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8216, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
495 { .Name: 1565, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8217, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
496 { .Name: 1473, .SubRegs: 32, .SuperRegs: 105, .SubRegIndices: 10, .RegUnits: 278554, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
497 { .Name: 1537, .SubRegs: 23, .SuperRegs: 105, .SubRegIndices: 10, .RegUnits: 278557, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
498 { .Name: 1707, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8224, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
499 { .Name: 1712, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8225, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
500 { .Name: 1568, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8226, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
501 { .Name: 1126, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8227, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
502 { .Name: 1576, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8228, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
503 { .Name: 1134, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8229, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
504 { .Name: 1721, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8207, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
505 { .Name: 1517, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8208, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
506 { .Name: 1733, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8209, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
507 { .Name: 1745, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8210, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
508 { .Name: 1465, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8211, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
509 { .Name: 1757, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8212, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
510 { .Name: 1529, .SubRegs: 2, .SuperRegs: 128, .SubRegIndices: 2, .RegUnits: 8215, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
511 { .Name: 1477, .SubRegs: 2, .SuperRegs: 119, .SubRegIndices: 2, .RegUnits: 8220, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
512 { .Name: 1541, .SubRegs: 2, .SuperRegs: 119, .SubRegIndices: 2, .RegUnits: 8223, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
513 { .Name: 1526, .SubRegs: 2, .SuperRegs: 122, .SubRegIndices: 2, .RegUnits: 8214, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
514 { .Name: 1553, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8230, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
515 { .Name: 1725, .SubRegs: 206, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 348160, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
516 { .Name: 1521, .SubRegs: 194, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 335876, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
517 { .Name: 1737, .SubRegs: 200, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 348162, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
518 { .Name: 1749, .SubRegs: 188, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 335878, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
519 { .Name: 1469, .SubRegs: 97, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 299019, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
520 { .Name: 1761, .SubRegs: 179, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 311306, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
521 { .Name: 1579, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8231, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
522 { .Name: 1533, .SubRegs: 40, .SuperRegs: 2, .SubRegIndices: 14, .RegUnits: 233494, .RegUnitLaneMasks: 10, .IsConstant: 0, .IsArtificial: 0 },
523 { .Name: 1769, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8232, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
524 { .Name: 1481, .SubRegs: 31, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278554, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
525 { .Name: 1545, .SubRegs: 22, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278557, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
526 { .Name: 1474, .SubRegs: 53, .SuperRegs: 112, .SubRegIndices: 2, .RegUnits: 233498, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
527 { .Name: 1307, .SubRegs: 2, .SuperRegs: 115, .SubRegIndices: 2, .RegUnits: 8219, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
528 { .Name: 1501, .SubRegs: 2, .SuperRegs: 111, .SubRegIndices: 2, .RegUnits: 8218, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
529 { .Name: 1538, .SubRegs: 53, .SuperRegs: 104, .SubRegIndices: 2, .RegUnits: 233501, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
530 { .Name: 1315, .SubRegs: 2, .SuperRegs: 107, .SubRegIndices: 2, .RegUnits: 8222, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
531 { .Name: 1509, .SubRegs: 2, .SuperRegs: 103, .SubRegIndices: 2, .RegUnits: 8221, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
532 { .Name: 1586, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8233, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
533 { .Name: 1549, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8234, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
534 { .Name: 1571, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8235, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
535 { .Name: 99, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8236, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
536 { .Name: 213, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8237, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
537 { .Name: 302, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8238, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
538 { .Name: 394, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8239, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
539 { .Name: 483, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8240, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
540 { .Name: 575, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8241, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
541 { .Name: 658, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8242, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
542 { .Name: 744, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8243, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
543 { .Name: 815, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8244, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
544 { .Name: 882, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8245, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
545 { .Name: 18, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8246, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
546 { .Name: 129, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8247, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
547 { .Name: 243, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8248, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
548 { .Name: 332, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8249, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
549 { .Name: 424, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8250, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
550 { .Name: 513, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8251, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
551 { .Name: 103, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8252, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
552 { .Name: 217, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8253, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
553 { .Name: 306, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8254, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
554 { .Name: 398, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8255, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
555 { .Name: 487, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8256, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
556 { .Name: 579, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8257, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
557 { .Name: 662, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8258, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
558 { .Name: 748, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8259, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
559 { .Name: 819, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8260, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
560 { .Name: 886, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8261, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
561 { .Name: 23, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8262, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
562 { .Name: 134, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8263, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
563 { .Name: 248, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8264, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
564 { .Name: 337, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8265, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
565 { .Name: 429, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8266, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
566 { .Name: 518, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8267, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
567 { .Name: 95, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8268, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
568 { .Name: 209, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8269, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
569 { .Name: 298, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8270, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
570 { .Name: 390, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8271, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
571 { .Name: 479, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8272, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
572 { .Name: 571, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8273, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
573 { .Name: 654, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8274, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
574 { .Name: 740, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8275, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
575 { .Name: 76, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8276, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
576 { .Name: 190, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8277, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
577 { .Name: 279, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8278, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
578 { .Name: 371, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8279, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
579 { .Name: 460, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8280, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
580 { .Name: 552, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8281, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
581 { .Name: 635, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8282, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
582 { .Name: 721, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8283, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
583 { .Name: 816, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278620, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
584 { .Name: 883, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278623, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
585 { .Name: 19, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278626, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
586 { .Name: 130, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278629, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
587 { .Name: 244, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278632, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
588 { .Name: 333, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278635, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
589 { .Name: 425, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278638, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
590 { .Name: 514, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278641, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
591 { .Name: 107, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8308, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
592 { .Name: 221, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8309, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
593 { .Name: 310, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8310, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
594 { .Name: 402, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8311, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
595 { .Name: 491, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8312, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
596 { .Name: 583, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8313, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
597 { .Name: 666, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8314, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
598 { .Name: 752, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8315, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
599 { .Name: 80, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8316, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
600 { .Name: 194, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8317, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
601 { .Name: 283, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8318, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
602 { .Name: 375, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8319, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
603 { .Name: 464, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8320, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
604 { .Name: 556, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8321, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
605 { .Name: 639, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8322, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
606 { .Name: 725, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8323, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
607 { .Name: 800, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8324, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
608 { .Name: 867, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8325, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
609 { .Name: 0, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8326, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
610 { .Name: 111, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8327, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
611 { .Name: 225, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8328, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
612 { .Name: 314, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8329, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
613 { .Name: 406, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8330, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
614 { .Name: 495, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8331, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
615 { .Name: 990, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8284, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
616 { .Name: 1004, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8287, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
617 { .Name: 890, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8290, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
618 { .Name: 905, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8293, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
619 { .Name: 920, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8296, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
620 { .Name: 930, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8299, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
621 { .Name: 940, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8302, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
622 { .Name: 950, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8305, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
623 { .Name: 1275, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8285, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
624 { .Name: 1292, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8288, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
625 { .Name: 1155, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8291, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
626 { .Name: 1173, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8294, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
627 { .Name: 1191, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8297, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
628 { .Name: 1203, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8300, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
629 { .Name: 1215, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8303, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
630 { .Name: 1227, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8306, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
631 { .Name: 1108, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278620, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
632 { .Name: 1122, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278623, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
633 { .Name: 1008, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278626, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
634 { .Name: 1023, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278629, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
635 { .Name: 1038, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278632, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
636 { .Name: 1048, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278635, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
637 { .Name: 1058, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278638, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
638 { .Name: 1068, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278641, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
639 { .Name: 1689, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233564, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
640 { .Name: 1703, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233567, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
641 { .Name: 1589, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233570, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
642 { .Name: 1604, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233573, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
643 { .Name: 1619, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233576, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
644 { .Name: 1629, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233579, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
645 { .Name: 1639, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233582, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
646 { .Name: 1649, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233585, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
647 { .Name: 1439, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8286, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
648 { .Name: 1456, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8289, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
649 { .Name: 1319, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8292, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
650 { .Name: 1337, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8295, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
651 { .Name: 1355, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8298, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
652 { .Name: 1367, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8301, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
653 { .Name: 1379, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8304, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
654 { .Name: 1391, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8307, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
655 { .Name: 85, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8316, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
656 { .Name: 199, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8317, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
657 { .Name: 288, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8318, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
658 { .Name: 380, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8319, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
659 { .Name: 469, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8320, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
660 { .Name: 561, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8321, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
661 { .Name: 644, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8322, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
662 { .Name: 730, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8323, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
663 { .Name: 805, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8324, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
664 { .Name: 872, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8325, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
665 { .Name: 6, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8326, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
666 { .Name: 117, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8327, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
667 { .Name: 231, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8328, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
668 { .Name: 320, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8329, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
669 { .Name: 412, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8330, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
670 { .Name: 501, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8331, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
671 { .Name: 72, .SubRegs: 2, .SuperRegs: 229, .SubRegIndices: 2, .RegUnits: 8332, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
672 { .Name: 186, .SubRegs: 2, .SuperRegs: 227, .SubRegIndices: 2, .RegUnits: 8333, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
673 { .Name: 275, .SubRegs: 2, .SuperRegs: 227, .SubRegIndices: 2, .RegUnits: 8334, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
674 { .Name: 367, .SubRegs: 2, .SuperRegs: 225, .SubRegIndices: 2, .RegUnits: 8335, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
675 { .Name: 456, .SubRegs: 2, .SuperRegs: 225, .SubRegIndices: 2, .RegUnits: 8336, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
676 { .Name: 548, .SubRegs: 2, .SuperRegs: 223, .SubRegIndices: 2, .RegUnits: 8337, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
677 { .Name: 631, .SubRegs: 2, .SuperRegs: 223, .SubRegIndices: 2, .RegUnits: 8338, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
678 { .Name: 717, .SubRegs: 2, .SuperRegs: 221, .SubRegIndices: 2, .RegUnits: 8339, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
679 { .Name: 587, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8340, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
680 { .Name: 670, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8341, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
681 { .Name: 756, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8342, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
682 { .Name: 823, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8343, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
683 { .Name: 28, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8344, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
684 { .Name: 139, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8345, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
685 { .Name: 253, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8346, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
686 { .Name: 342, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8347, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
687 { .Name: 434, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8348, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
688 { .Name: 523, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8349, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
689 { .Name: 609, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8350, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
690 { .Name: 692, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8351, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
691 { .Name: 778, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8352, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
692 { .Name: 845, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8353, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
693 { .Name: 50, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8354, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
694 { .Name: 161, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8355, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
695 { .Name: 593, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8340, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
696 { .Name: 676, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8341, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
697 { .Name: 762, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8342, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
698 { .Name: 829, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8343, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
699 { .Name: 34, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8344, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
700 { .Name: 145, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8345, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
701 { .Name: 259, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8346, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
702 { .Name: 348, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8347, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
703 { .Name: 440, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8348, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
704 { .Name: 529, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8349, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
705 { .Name: 615, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8350, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
706 { .Name: 698, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8351, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
707 { .Name: 784, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8352, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
708 { .Name: 851, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8353, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
709 { .Name: 56, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8354, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
710 { .Name: 167, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8355, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
711 { .Name: 90, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8316, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
712 { .Name: 204, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8317, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
713 { .Name: 293, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8318, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
714 { .Name: 385, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8319, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
715 { .Name: 474, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8320, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
716 { .Name: 566, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8321, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
717 { .Name: 649, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8322, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
718 { .Name: 735, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8323, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
719 { .Name: 810, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8324, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
720 { .Name: 877, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8325, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
721 { .Name: 12, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8326, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
722 { .Name: 123, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8327, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
723 { .Name: 237, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8328, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
724 { .Name: 326, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8329, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
725 { .Name: 418, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8330, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
726 { .Name: 507, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8331, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
727 { .Name: 599, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8340, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
728 { .Name: 682, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8341, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
729 { .Name: 768, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8342, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
730 { .Name: 835, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8343, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
731 { .Name: 40, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8344, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
732 { .Name: 151, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8345, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
733 { .Name: 265, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8346, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
734 { .Name: 354, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8347, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
735 { .Name: 446, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8348, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
736 { .Name: 535, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8349, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
737 { .Name: 621, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8350, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
738 { .Name: 704, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8351, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
739 { .Name: 790, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8352, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
740 { .Name: 857, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8353, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
741 { .Name: 62, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8354, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
742 { .Name: 173, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8355, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
743 { .Name: 183, .SubRegs: 56, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233612, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
744 { .Name: 364, .SubRegs: 59, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233614, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
745 { .Name: 545, .SubRegs: 62, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233616, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
746 { .Name: 714, .SubRegs: 65, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233618, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
747 { .Name: 1145, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8356, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
748 { .Name: 75, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8357, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
749 { .Name: 189, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8358, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
750 { .Name: 278, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8359, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
751 { .Name: 370, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8360, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
752 { .Name: 459, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8361, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
753 { .Name: 551, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8362, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
754 { .Name: 634, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8363, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
755 { .Name: 720, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8364, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
756 { .Name: 605, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278701, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
757 { .Name: 688, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278704, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
758 { .Name: 774, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278707, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
759 { .Name: 841, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278710, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
760 { .Name: 46, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278713, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
761 { .Name: 157, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278716, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
762 { .Name: 271, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278719, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
763 { .Name: 360, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278722, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
764 { .Name: 452, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278725, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
765 { .Name: 541, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278728, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
766 { .Name: 627, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278731, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
767 { .Name: 710, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278734, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
768 { .Name: 796, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278737, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
769 { .Name: 863, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278740, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
770 { .Name: 68, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278743, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
771 { .Name: 179, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278746, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
772 { .Name: 960, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8365, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
773 { .Name: 970, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8368, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
774 { .Name: 980, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8371, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
775 { .Name: 994, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8374, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
776 { .Name: 895, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8377, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
777 { .Name: 910, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8380, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
778 { .Name: 925, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8383, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
779 { .Name: 935, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8386, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
780 { .Name: 945, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8389, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
781 { .Name: 955, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8392, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
782 { .Name: 965, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8395, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
783 { .Name: 975, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8398, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
784 { .Name: 985, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8401, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
785 { .Name: 999, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8404, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
786 { .Name: 900, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8407, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
787 { .Name: 915, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8410, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
788 { .Name: 1239, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8366, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
789 { .Name: 1251, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8369, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
790 { .Name: 1263, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8372, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
791 { .Name: 1280, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8375, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
792 { .Name: 1161, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8378, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
793 { .Name: 1179, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8381, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
794 { .Name: 1197, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8384, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
795 { .Name: 1209, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8387, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
796 { .Name: 1221, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8390, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
797 { .Name: 1233, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8393, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
798 { .Name: 1245, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8396, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
799 { .Name: 1257, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8399, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
800 { .Name: 1269, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8402, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
801 { .Name: 1286, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8405, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
802 { .Name: 1167, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8408, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
803 { .Name: 1185, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8411, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
804 { .Name: 1078, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278701, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
805 { .Name: 1088, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278704, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
806 { .Name: 1098, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278707, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
807 { .Name: 1112, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278710, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
808 { .Name: 1013, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278713, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
809 { .Name: 1028, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278716, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
810 { .Name: 1043, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278719, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
811 { .Name: 1053, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278722, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
812 { .Name: 1063, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278725, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
813 { .Name: 1073, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278728, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
814 { .Name: 1083, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278731, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
815 { .Name: 1093, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278734, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
816 { .Name: 1103, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278737, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
817 { .Name: 1117, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278740, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
818 { .Name: 1018, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278743, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
819 { .Name: 1033, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278746, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
820 { .Name: 1659, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233645, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
821 { .Name: 1669, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233648, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
822 { .Name: 1679, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233651, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
823 { .Name: 1693, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233654, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
824 { .Name: 1594, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233657, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
825 { .Name: 1609, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233660, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
826 { .Name: 1624, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233663, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
827 { .Name: 1634, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233666, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
828 { .Name: 1644, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233669, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
829 { .Name: 1654, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233672, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
830 { .Name: 1664, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233675, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
831 { .Name: 1674, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233678, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
832 { .Name: 1684, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233681, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
833 { .Name: 1698, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233684, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
834 { .Name: 1599, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233687, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
835 { .Name: 1614, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233690, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
836 { .Name: 1403, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8367, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
837 { .Name: 1415, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8370, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
838 { .Name: 1427, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8373, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
839 { .Name: 1444, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8376, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
840 { .Name: 1325, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8379, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
841 { .Name: 1343, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8382, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
842 { .Name: 1361, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8385, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
843 { .Name: 1373, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8388, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
844 { .Name: 1385, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8391, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
845 { .Name: 1397, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8394, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
846 { .Name: 1409, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8397, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
847 { .Name: 1421, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8400, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
848 { .Name: 1433, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8403, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
849 { .Name: 1450, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8406, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
850 { .Name: 1331, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8409, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
851 { .Name: 1349, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8412, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
852};
853
854extern const MCPhysReg X86RegUnitRoots[][2] = {
855 { X86::AH },
856 { X86::AL },
857 { X86::BH },
858 { X86::BL },
859 { X86::BPL },
860 { X86::BPH },
861 { X86::CH },
862 { X86::CL },
863 { X86::CS },
864 { X86::DF },
865 { X86::DH },
866 { X86::DIL },
867 { X86::DIH },
868 { X86::DL },
869 { X86::DS },
870 { X86::HAX },
871 { X86::HBP },
872 { X86::HBX },
873 { X86::HCX },
874 { X86::HDI },
875 { X86::HDX },
876 { X86::EFLAGS },
877 { X86::IP },
878 { X86::HIP },
879 { X86::EIZ },
880 { X86::ES },
881 { X86::SIL },
882 { X86::SIH },
883 { X86::HSI },
884 { X86::SPL },
885 { X86::SPH },
886 { X86::HSP },
887 { X86::FPCW },
888 { X86::FPSW },
889 { X86::FS },
890 { X86::FS_BASE },
891 { X86::GS },
892 { X86::GS_BASE },
893 { X86::MXCSR },
894 { X86::RFLAGS },
895 { X86::RIZ },
896 { X86::SS },
897 { X86::SSP },
898 { X86::_EFLAGS },
899 { X86::CR0 },
900 { X86::CR1 },
901 { X86::CR2 },
902 { X86::CR3 },
903 { X86::CR4 },
904 { X86::CR5 },
905 { X86::CR6 },
906 { X86::CR7 },
907 { X86::CR8 },
908 { X86::CR9 },
909 { X86::CR10 },
910 { X86::CR11 },
911 { X86::CR12 },
912 { X86::CR13 },
913 { X86::CR14 },
914 { X86::CR15 },
915 { X86::DR0 },
916 { X86::DR1 },
917 { X86::DR2 },
918 { X86::DR3 },
919 { X86::DR4 },
920 { X86::DR5 },
921 { X86::DR6 },
922 { X86::DR7 },
923 { X86::DR8 },
924 { X86::DR9 },
925 { X86::DR10 },
926 { X86::DR11 },
927 { X86::DR12 },
928 { X86::DR13 },
929 { X86::DR14 },
930 { X86::DR15 },
931 { X86::FP0 },
932 { X86::FP1 },
933 { X86::FP2 },
934 { X86::FP3 },
935 { X86::FP4 },
936 { X86::FP5 },
937 { X86::FP6 },
938 { X86::FP7 },
939 { X86::MM0 },
940 { X86::MM1 },
941 { X86::MM2 },
942 { X86::MM3 },
943 { X86::MM4 },
944 { X86::MM5 },
945 { X86::MM6 },
946 { X86::MM7 },
947 { X86::R8B },
948 { X86::R8BH },
949 { X86::R8WH },
950 { X86::R9B },
951 { X86::R9BH },
952 { X86::R9WH },
953 { X86::R10B },
954 { X86::R10BH },
955 { X86::R10WH },
956 { X86::R11B },
957 { X86::R11BH },
958 { X86::R11WH },
959 { X86::R12B },
960 { X86::R12BH },
961 { X86::R12WH },
962 { X86::R13B },
963 { X86::R13BH },
964 { X86::R13WH },
965 { X86::R14B },
966 { X86::R14BH },
967 { X86::R14WH },
968 { X86::R15B },
969 { X86::R15BH },
970 { X86::R15WH },
971 { X86::ST0 },
972 { X86::ST1 },
973 { X86::ST2 },
974 { X86::ST3 },
975 { X86::ST4 },
976 { X86::ST5 },
977 { X86::ST6 },
978 { X86::ST7 },
979 { X86::XMM0 },
980 { X86::XMM1 },
981 { X86::XMM2 },
982 { X86::XMM3 },
983 { X86::XMM4 },
984 { X86::XMM5 },
985 { X86::XMM6 },
986 { X86::XMM7 },
987 { X86::XMM8 },
988 { X86::XMM9 },
989 { X86::XMM10 },
990 { X86::XMM11 },
991 { X86::XMM12 },
992 { X86::XMM13 },
993 { X86::XMM14 },
994 { X86::XMM15 },
995 { X86::K0 },
996 { X86::K1 },
997 { X86::K2 },
998 { X86::K3 },
999 { X86::K4 },
1000 { X86::K5 },
1001 { X86::K6 },
1002 { X86::K7 },
1003 { X86::XMM16 },
1004 { X86::XMM17 },
1005 { X86::XMM18 },
1006 { X86::XMM19 },
1007 { X86::XMM20 },
1008 { X86::XMM21 },
1009 { X86::XMM22 },
1010 { X86::XMM23 },
1011 { X86::XMM24 },
1012 { X86::XMM25 },
1013 { X86::XMM26 },
1014 { X86::XMM27 },
1015 { X86::XMM28 },
1016 { X86::XMM29 },
1017 { X86::XMM30 },
1018 { X86::XMM31 },
1019 { X86::TMMCFG },
1020 { X86::TMM0 },
1021 { X86::TMM1 },
1022 { X86::TMM2 },
1023 { X86::TMM3 },
1024 { X86::TMM4 },
1025 { X86::TMM5 },
1026 { X86::TMM6 },
1027 { X86::TMM7 },
1028 { X86::R16B },
1029 { X86::R16BH },
1030 { X86::R16WH },
1031 { X86::R17B },
1032 { X86::R17BH },
1033 { X86::R17WH },
1034 { X86::R18B },
1035 { X86::R18BH },
1036 { X86::R18WH },
1037 { X86::R19B },
1038 { X86::R19BH },
1039 { X86::R19WH },
1040 { X86::R20B },
1041 { X86::R20BH },
1042 { X86::R20WH },
1043 { X86::R21B },
1044 { X86::R21BH },
1045 { X86::R21WH },
1046 { X86::R22B },
1047 { X86::R22BH },
1048 { X86::R22WH },
1049 { X86::R23B },
1050 { X86::R23BH },
1051 { X86::R23WH },
1052 { X86::R24B },
1053 { X86::R24BH },
1054 { X86::R24WH },
1055 { X86::R25B },
1056 { X86::R25BH },
1057 { X86::R25WH },
1058 { X86::R26B },
1059 { X86::R26BH },
1060 { X86::R26WH },
1061 { X86::R27B },
1062 { X86::R27BH },
1063 { X86::R27WH },
1064 { X86::R28B },
1065 { X86::R28BH },
1066 { X86::R28WH },
1067 { X86::R29B },
1068 { X86::R29BH },
1069 { X86::R29WH },
1070 { X86::R30B },
1071 { X86::R30BH },
1072 { X86::R30WH },
1073 { X86::R31B },
1074 { X86::R31BH },
1075 { X86::R31WH },
1076};
1077
1078// Register classes...
1079
1080#ifdef __GNUC__
1081#pragma GCC diagnostic push
1082#pragma GCC diagnostic ignored "-Woverlength-strings"
1083#endif
1084extern const char X86RegClassStrings[] = {
1085 /* 0 */ "RFP80\000"
1086 /* 6 */ "VK1\000"
1087 /* 10 */ "VR512\000"
1088 /* 16 */ "VK32\000"
1089 /* 21 */ "RFP32\000"
1090 /* 27 */ "FR32\000"
1091 /* 32 */ "GR32\000"
1092 /* 37 */ "VK2\000"
1093 /* 41 */ "GR32_NOREX2\000"
1094 /* 53 */ "GR64_NOREX2\000"
1095 /* 65 */ "GR64_with_sub_16bit_in_GR16_NOREX2\000"
1096 /* 100 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2\000"
1097 /* 152 */ "GR8_NOREX2\000"
1098 /* 163 */ "VK64\000"
1099 /* 168 */ "RFP64\000"
1100 /* 174 */ "FR64\000"
1101 /* 179 */ "GR64\000"
1102 /* 184 */ "VR64\000"
1103 /* 189 */ "GR64_TC_and_GR64_TCW64\000"
1104 /* 212 */ "GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64\000"
1105 /* 256 */ "GR64_NOREX_and_GR64_TCW64\000"
1106 /* 282 */ "GR64PLTSafe_and_GR64_TCW64\000"
1107 /* 309 */ "VK4\000"
1108 /* 313 */ "VR512_0_15\000"
1109 /* 324 */ "GRH16\000"
1110 /* 330 */ "VK16\000"
1111 /* 335 */ "FR16\000"
1112 /* 340 */ "GR16\000"
1113 /* 345 */ "VR256\000"
1114 /* 351 */ "RFP80_7\000"
1115 /* 359 */ "VR128\000"
1116 /* 365 */ "GRH8\000"
1117 /* 370 */ "VK8\000"
1118 /* 374 */ "GR8\000"
1119 /* 378 */ "GR64_A\000"
1120 /* 385 */ "GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB\000"
1121 /* 432 */ "GR64_with_sub_32bit_in_GR32_CB\000"
1122 /* 463 */ "GR32_DC\000"
1123 /* 471 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC\000"
1124 /* 516 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC\000"
1125 /* 561 */ "GR64_with_sub_32bit_in_GR32_TC\000"
1126 /* 592 */ "GR64_NOREX2_NOSP_and_GR64_TC\000"
1127 /* 621 */ "GR64_NOREX_and_GR64_TC\000"
1128 /* 644 */ "GR64_NOREX_and_GR64PLTSafe_and_GR64_TC\000"
1129 /* 683 */ "GR64_ArgRef_and_GR64_TC\000"
1130 /* 707 */ "GR32_AD\000"
1131 /* 715 */ "GR64_AD\000"
1132 /* 723 */ "GR32_ABCD\000"
1133 /* 733 */ "GR64_ABCD\000"
1134 /* 743 */ "GR16_ABCD\000"
1135 /* 753 */ "TILE\000"
1136 /* 758 */ "DEBUG_REG\000"
1137 /* 768 */ "CONTROL_REG\000"
1138 /* 780 */ "SEGMENT_REG\000"
1139 /* 792 */ "GR8_ABCD_H\000"
1140 /* 803 */ "GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI\000"
1141 /* 849 */ "GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI\000"
1142 /* 896 */ "GR64_with_sub_32bit_in_GR32_SIDI\000"
1143 /* 929 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI\000"
1144 /* 975 */ "GR64_with_sub_32bit_in_GR32_BSI\000"
1145 /* 1007 */ "GR8_ABCD_L\000"
1146 /* 1018 */ "VK1PAIR_with_sub_mask_0_in_VK1WM\000"
1147 /* 1051 */ "VK32WM\000"
1148 /* 1058 */ "VK2WM\000"
1149 /* 1064 */ "VK64WM\000"
1150 /* 1071 */ "VK4WM\000"
1151 /* 1077 */ "VK16WM\000"
1152 /* 1084 */ "VK8WM\000"
1153 /* 1090 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP\000"
1154 /* 1137 */ "GR64_with_sub_32bit_in_GR32_DIBP\000"
1155 /* 1170 */ "GR64_and_LOW32_ADDR_ACCESS_RBP\000"
1156 /* 1201 */ "GR32_NOSP\000"
1157 /* 1211 */ "GR32_NOREX2_NOSP\000"
1158 /* 1228 */ "GR64_NOREX2_NOSP\000"
1159 /* 1245 */ "GR64_NOSP\000"
1160 /* 1255 */ "GR32_NOREX_NOSP\000"
1161 /* 1271 */ "GR64_NOREX_NOSP\000"
1162 /* 1287 */ "GR64_with_sub_32bit_in_GR32_BPSP\000"
1163 /* 1320 */ "DFCCR\000"
1164 /* 1326 */ "FPCCR\000"
1165 /* 1332 */ "VK1PAIR\000"
1166 /* 1340 */ "VK2PAIR\000"
1167 /* 1348 */ "VK4PAIR\000"
1168 /* 1356 */ "VK16PAIR\000"
1169 /* 1365 */ "VK8PAIR\000"
1170 /* 1373 */ "GR64_and_LOW32_ADDR_ACCESS\000"
1171 /* 1400 */ "RST\000"
1172 /* 1404 */ "FR32X\000"
1173 /* 1410 */ "FR64X\000"
1174 /* 1416 */ "FR16X\000"
1175 /* 1422 */ "VR256X\000"
1176 /* 1429 */ "VR128X\000"
1177 /* 1436 */ "GR32_NOREX\000"
1178 /* 1447 */ "GR64_NOREX\000"
1179 /* 1458 */ "GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX\000"
1180 /* 1504 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX\000"
1181 /* 1555 */ "GR8_NOREX\000"
1182 /* 1565 */ "GR64PLTSafe\000"
1183 /* 1577 */ "GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef\000"
1184 /* 1624 */ "GR64_with_sub_32bit_in_GR32_ArgRef\000"
1185 /* 1659 */ "GR64_ArgRef\000"
1186 /* 1671 */ "LOW32_ADDR_ACCESS_RBP_with_sub_32bit\000"
1187 /* 1708 */ "LOW32_ADDR_ACCESS_with_sub_32bit\000"
1188 /* 1741 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit\000"
1189 /* 1792 */ "GR64_with_sub_8bit\000"
1190 /* 1811 */ "GR64_TCW64_with_sub_8bit\000"
1191 /* 1836 */ "GR64_TCW64_and_GR64_TC_with_sub_8bit\000"
1192 /* 1873 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit\000"
1193};
1194#ifdef __GNUC__
1195#pragma GCC diagnostic pop
1196#endif
1197
1198using X86RegisterClassStorage = MCRegisterClassStorage<135, 1296, 2329, 1070, 16, 979>;
1199extern const MCRegisterClassStorage<135, 1296, 2329, 1070, 16, 979> X86MCRegisterClassStorage = {
1200 .Classes: {
1201 {
1202 offsetof(X86RegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
1203 offsetof(X86RegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
1204 .NameIdx: 374,
1205 .RegSizeInBits: 8,
1206 .RegsSize: 36,
1207 .RegSetSize: 41,
1208 .ID: X86::GR8RegClassID,
1209 .CopyCost: 1, /* CopyCost */
1210 .Allocatable: true, /* Allocatable */
1211 .BaseClass: false,
1212 offsetof(X86RegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
1213 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[2]) - 0 * sizeof(MCRegisterClass),
1214 .LaneMask: LaneBitmask(0x0000000000000001),
1215 .AllocationPriority: 0,
1216 .GlobalPriority: false,
1217 .TSFlags: 0x00, /* TSFlags */
1218 .SpillStackID: 0, /* SpillStackID */
1219 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1220 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1221 offsetof(X86RegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
1222 .SuperClassesSize: 0
1223 },
1224 {
1225 offsetof(X86RegisterClassStorage, Regs[36]) - 1 * sizeof(MCRegisterClass),
1226 offsetof(X86RegisterClassStorage, BitSets[41]) - 1 * sizeof(MCRegisterClass),
1227 .NameIdx: 365,
1228 .RegSizeInBits: 8,
1229 .RegsSize: 28,
1230 .RegSetSize: 43,
1231 .ID: X86::GRH8RegClassID,
1232 .CopyCost: 1, /* CopyCost */
1233 .Allocatable: false, /* Allocatable */
1234 .BaseClass: false,
1235 offsetof(X86RegisterClassStorage, SubClassMasks[15]) - 1 * sizeof(MCRegisterClass),
1236 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 1 * sizeof(MCRegisterClass),
1237 .LaneMask: LaneBitmask(0x0000000000000001),
1238 .AllocationPriority: 0,
1239 .GlobalPriority: false,
1240 .TSFlags: 0x00, /* TSFlags */
1241 .SpillStackID: 0, /* SpillStackID */
1242 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1243 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1244 offsetof(X86RegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
1245 .SuperClassesSize: 0
1246 },
1247 {
1248 offsetof(X86RegisterClassStorage, Regs[64]) - 2 * sizeof(MCRegisterClass),
1249 offsetof(X86RegisterClassStorage, BitSets[84]) - 2 * sizeof(MCRegisterClass),
1250 .NameIdx: 152,
1251 .RegSizeInBits: 8,
1252 .RegsSize: 20,
1253 .RegSetSize: 20,
1254 .ID: X86::GR8_NOREX2RegClassID,
1255 .CopyCost: 1, /* CopyCost */
1256 .Allocatable: true, /* Allocatable */
1257 .BaseClass: false,
1258 offsetof(X86RegisterClassStorage, SubClassMasks[20]) - 2 * sizeof(MCRegisterClass),
1259 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[2]) - 2 * sizeof(MCRegisterClass),
1260 .LaneMask: LaneBitmask(0x0000000000000001),
1261 .AllocationPriority: 0,
1262 .GlobalPriority: false,
1263 .TSFlags: 0x00, /* TSFlags */
1264 .SpillStackID: 0, /* SpillStackID */
1265 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1266 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1267 offsetof(X86RegisterClassStorage, SuperClasses[0]) - 2 * sizeof(MCRegisterClass),
1268 .SuperClassesSize: 1
1269 },
1270 {
1271 offsetof(X86RegisterClassStorage, Regs[84]) - 3 * sizeof(MCRegisterClass),
1272 offsetof(X86RegisterClassStorage, BitSets[104]) - 3 * sizeof(MCRegisterClass),
1273 .NameIdx: 1555,
1274 .RegSizeInBits: 8,
1275 .RegsSize: 8,
1276 .RegSetSize: 3,
1277 .ID: X86::GR8_NOREXRegClassID,
1278 .CopyCost: 1, /* CopyCost */
1279 .Allocatable: true, /* Allocatable */
1280 .BaseClass: false,
1281 offsetof(X86RegisterClassStorage, SubClassMasks[35]) - 3 * sizeof(MCRegisterClass),
1282 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[2]) - 3 * sizeof(MCRegisterClass),
1283 .LaneMask: LaneBitmask(0x0000000000000001),
1284 .AllocationPriority: 0,
1285 .GlobalPriority: false,
1286 .TSFlags: 0x00, /* TSFlags */
1287 .SpillStackID: 0, /* SpillStackID */
1288 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1289 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1290 offsetof(X86RegisterClassStorage, SuperClasses[1]) - 3 * sizeof(MCRegisterClass),
1291 .SuperClassesSize: 2
1292 },
1293 {
1294 offsetof(X86RegisterClassStorage, Regs[92]) - 4 * sizeof(MCRegisterClass),
1295 offsetof(X86RegisterClassStorage, BitSets[107]) - 4 * sizeof(MCRegisterClass),
1296 .NameIdx: 792,
1297 .RegSizeInBits: 8,
1298 .RegsSize: 4,
1299 .RegSetSize: 2,
1300 .ID: X86::GR8_ABCD_HRegClassID,
1301 .CopyCost: 1, /* CopyCost */
1302 .Allocatable: true, /* Allocatable */
1303 .BaseClass: false,
1304 offsetof(X86RegisterClassStorage, SubClassMasks[50]) - 4 * sizeof(MCRegisterClass),
1305 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[3]) - 4 * sizeof(MCRegisterClass),
1306 .LaneMask: LaneBitmask(0x0000000000000001),
1307 .AllocationPriority: 0,
1308 .GlobalPriority: false,
1309 .TSFlags: 0x00, /* TSFlags */
1310 .SpillStackID: 0, /* SpillStackID */
1311 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1312 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1313 offsetof(X86RegisterClassStorage, SuperClasses[3]) - 4 * sizeof(MCRegisterClass),
1314 .SuperClassesSize: 3
1315 },
1316 {
1317 offsetof(X86RegisterClassStorage, Regs[96]) - 5 * sizeof(MCRegisterClass),
1318 offsetof(X86RegisterClassStorage, BitSets[109]) - 5 * sizeof(MCRegisterClass),
1319 .NameIdx: 1007,
1320 .RegSizeInBits: 8,
1321 .RegsSize: 4,
1322 .RegSetSize: 3,
1323 .ID: X86::GR8_ABCD_LRegClassID,
1324 .CopyCost: 1, /* CopyCost */
1325 .Allocatable: true, /* Allocatable */
1326 .BaseClass: false,
1327 offsetof(X86RegisterClassStorage, SubClassMasks[60]) - 5 * sizeof(MCRegisterClass),
1328 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[0]) - 5 * sizeof(MCRegisterClass),
1329 .LaneMask: LaneBitmask(0x0000000000000001),
1330 .AllocationPriority: 0,
1331 .GlobalPriority: false,
1332 .TSFlags: 0x00, /* TSFlags */
1333 .SpillStackID: 0, /* SpillStackID */
1334 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1335 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1336 offsetof(X86RegisterClassStorage, SuperClasses[6]) - 5 * sizeof(MCRegisterClass),
1337 .SuperClassesSize: 3
1338 },
1339 {
1340 offsetof(X86RegisterClassStorage, Regs[100]) - 6 * sizeof(MCRegisterClass),
1341 offsetof(X86RegisterClassStorage, BitSets[112]) - 6 * sizeof(MCRegisterClass),
1342 .NameIdx: 324,
1343 .RegSizeInBits: 16,
1344 .RegsSize: 33,
1345 .RegSetSize: 49,
1346 .ID: X86::GRH16RegClassID,
1347 .CopyCost: 1, /* CopyCost */
1348 .Allocatable: false, /* Allocatable */
1349 .BaseClass: false,
1350 offsetof(X86RegisterClassStorage, SubClassMasks[70]) - 6 * sizeof(MCRegisterClass),
1351 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 6 * sizeof(MCRegisterClass),
1352 .LaneMask: LaneBitmask(0x0000000000000001),
1353 .AllocationPriority: 0,
1354 .GlobalPriority: false,
1355 .TSFlags: 0x00, /* TSFlags */
1356 .SpillStackID: 0, /* SpillStackID */
1357 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1358 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1359 offsetof(X86RegisterClassStorage, SuperClasses[9]) - 6 * sizeof(MCRegisterClass),
1360 .SuperClassesSize: 0
1361 },
1362 {
1363 offsetof(X86RegisterClassStorage, Regs[133]) - 7 * sizeof(MCRegisterClass),
1364 offsetof(X86RegisterClassStorage, BitSets[161]) - 7 * sizeof(MCRegisterClass),
1365 .NameIdx: 340,
1366 .RegSizeInBits: 16,
1367 .RegsSize: 32,
1368 .RegSetSize: 47,
1369 .ID: X86::GR16RegClassID,
1370 .CopyCost: 1, /* CopyCost */
1371 .Allocatable: true, /* Allocatable */
1372 .BaseClass: false,
1373 offsetof(X86RegisterClassStorage, SubClassMasks[75]) - 7 * sizeof(MCRegisterClass),
1374 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[5]) - 7 * sizeof(MCRegisterClass),
1375 .LaneMask: LaneBitmask(0x0000000000000003),
1376 .AllocationPriority: 0,
1377 .GlobalPriority: false,
1378 .TSFlags: 0x00, /* TSFlags */
1379 .SpillStackID: 0, /* SpillStackID */
1380 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1381 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1382 offsetof(X86RegisterClassStorage, SuperClasses[9]) - 7 * sizeof(MCRegisterClass),
1383 .SuperClassesSize: 0
1384 },
1385 {
1386 offsetof(X86RegisterClassStorage, Regs[165]) - 8 * sizeof(MCRegisterClass),
1387 offsetof(X86RegisterClassStorage, BitSets[208]) - 8 * sizeof(MCRegisterClass),
1388 .NameIdx: 88,
1389 .RegSizeInBits: 16,
1390 .RegsSize: 16,
1391 .RegSetSize: 23,
1392 .ID: X86::GR16_NOREX2RegClassID,
1393 .CopyCost: 1, /* CopyCost */
1394 .Allocatable: true, /* Allocatable */
1395 .BaseClass: false,
1396 offsetof(X86RegisterClassStorage, SubClassMasks[85]) - 8 * sizeof(MCRegisterClass),
1397 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[5]) - 8 * sizeof(MCRegisterClass),
1398 .LaneMask: LaneBitmask(0x0000000000000003),
1399 .AllocationPriority: 0,
1400 .GlobalPriority: false,
1401 .TSFlags: 0x00, /* TSFlags */
1402 .SpillStackID: 0, /* SpillStackID */
1403 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1404 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1405 offsetof(X86RegisterClassStorage, SuperClasses[9]) - 8 * sizeof(MCRegisterClass),
1406 .SuperClassesSize: 1
1407 },
1408 {
1409 offsetof(X86RegisterClassStorage, Regs[181]) - 9 * sizeof(MCRegisterClass),
1410 offsetof(X86RegisterClassStorage, BitSets[231]) - 9 * sizeof(MCRegisterClass),
1411 .NameIdx: 1493,
1412 .RegSizeInBits: 16,
1413 .RegsSize: 8,
1414 .RegSetSize: 9,
1415 .ID: X86::GR16_NOREXRegClassID,
1416 .CopyCost: 1, /* CopyCost */
1417 .Allocatable: true, /* Allocatable */
1418 .BaseClass: false,
1419 offsetof(X86RegisterClassStorage, SubClassMasks[95]) - 9 * sizeof(MCRegisterClass),
1420 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[5]) - 9 * sizeof(MCRegisterClass),
1421 .LaneMask: LaneBitmask(0x0000000000000003),
1422 .AllocationPriority: 0,
1423 .GlobalPriority: false,
1424 .TSFlags: 0x00, /* TSFlags */
1425 .SpillStackID: 0, /* SpillStackID */
1426 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1427 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1428 offsetof(X86RegisterClassStorage, SuperClasses[10]) - 9 * sizeof(MCRegisterClass),
1429 .SuperClassesSize: 2
1430 },
1431 {
1432 offsetof(X86RegisterClassStorage, Regs[189]) - 10 * sizeof(MCRegisterClass),
1433 offsetof(X86RegisterClassStorage, BitSets[240]) - 10 * sizeof(MCRegisterClass),
1434 .NameIdx: 6,
1435 .RegSizeInBits: 16,
1436 .RegsSize: 8,
1437 .RegSetSize: 27,
1438 .ID: X86::VK1RegClassID,
1439 .CopyCost: 1, /* CopyCost */
1440 .Allocatable: true, /* Allocatable */
1441 .BaseClass: false,
1442 offsetof(X86RegisterClassStorage, SubClassMasks[105]) - 10 * sizeof(MCRegisterClass),
1443 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 10 * sizeof(MCRegisterClass),
1444 .LaneMask: LaneBitmask(0x0000000000000001),
1445 .AllocationPriority: 0,
1446 .GlobalPriority: false,
1447 .TSFlags: 0x00, /* TSFlags */
1448 .SpillStackID: 0, /* SpillStackID */
1449 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1450 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1451 offsetof(X86RegisterClassStorage, SuperClasses[12]) - 10 * sizeof(MCRegisterClass),
1452 .SuperClassesSize: 4
1453 },
1454 {
1455 offsetof(X86RegisterClassStorage, Regs[197]) - 11 * sizeof(MCRegisterClass),
1456 offsetof(X86RegisterClassStorage, BitSets[267]) - 11 * sizeof(MCRegisterClass),
1457 .NameIdx: 330,
1458 .RegSizeInBits: 16,
1459 .RegsSize: 8,
1460 .RegSetSize: 27,
1461 .ID: X86::VK16RegClassID,
1462 .CopyCost: 1, /* CopyCost */
1463 .Allocatable: true, /* Allocatable */
1464 .BaseClass: false,
1465 offsetof(X86RegisterClassStorage, SubClassMasks[120]) - 11 * sizeof(MCRegisterClass),
1466 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 11 * sizeof(MCRegisterClass),
1467 .LaneMask: LaneBitmask(0x0000000000000001),
1468 .AllocationPriority: 0,
1469 .GlobalPriority: false,
1470 .TSFlags: 0x00, /* TSFlags */
1471 .SpillStackID: 0, /* SpillStackID */
1472 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1473 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1474 offsetof(X86RegisterClassStorage, SuperClasses[16]) - 11 * sizeof(MCRegisterClass),
1475 .SuperClassesSize: 4
1476 },
1477 {
1478 offsetof(X86RegisterClassStorage, Regs[205]) - 12 * sizeof(MCRegisterClass),
1479 offsetof(X86RegisterClassStorage, BitSets[294]) - 12 * sizeof(MCRegisterClass),
1480 .NameIdx: 37,
1481 .RegSizeInBits: 16,
1482 .RegsSize: 8,
1483 .RegSetSize: 27,
1484 .ID: X86::VK2RegClassID,
1485 .CopyCost: 1, /* CopyCost */
1486 .Allocatable: true, /* Allocatable */
1487 .BaseClass: false,
1488 offsetof(X86RegisterClassStorage, SubClassMasks[135]) - 12 * sizeof(MCRegisterClass),
1489 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 12 * sizeof(MCRegisterClass),
1490 .LaneMask: LaneBitmask(0x0000000000000001),
1491 .AllocationPriority: 0,
1492 .GlobalPriority: false,
1493 .TSFlags: 0x00, /* TSFlags */
1494 .SpillStackID: 0, /* SpillStackID */
1495 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1496 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1497 offsetof(X86RegisterClassStorage, SuperClasses[20]) - 12 * sizeof(MCRegisterClass),
1498 .SuperClassesSize: 4
1499 },
1500 {
1501 offsetof(X86RegisterClassStorage, Regs[213]) - 13 * sizeof(MCRegisterClass),
1502 offsetof(X86RegisterClassStorage, BitSets[321]) - 13 * sizeof(MCRegisterClass),
1503 .NameIdx: 309,
1504 .RegSizeInBits: 16,
1505 .RegsSize: 8,
1506 .RegSetSize: 27,
1507 .ID: X86::VK4RegClassID,
1508 .CopyCost: 1, /* CopyCost */
1509 .Allocatable: true, /* Allocatable */
1510 .BaseClass: false,
1511 offsetof(X86RegisterClassStorage, SubClassMasks[150]) - 13 * sizeof(MCRegisterClass),
1512 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 13 * sizeof(MCRegisterClass),
1513 .LaneMask: LaneBitmask(0x0000000000000001),
1514 .AllocationPriority: 0,
1515 .GlobalPriority: false,
1516 .TSFlags: 0x00, /* TSFlags */
1517 .SpillStackID: 0, /* SpillStackID */
1518 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1519 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1520 offsetof(X86RegisterClassStorage, SuperClasses[24]) - 13 * sizeof(MCRegisterClass),
1521 .SuperClassesSize: 4
1522 },
1523 {
1524 offsetof(X86RegisterClassStorage, Regs[221]) - 14 * sizeof(MCRegisterClass),
1525 offsetof(X86RegisterClassStorage, BitSets[348]) - 14 * sizeof(MCRegisterClass),
1526 .NameIdx: 370,
1527 .RegSizeInBits: 16,
1528 .RegsSize: 8,
1529 .RegSetSize: 27,
1530 .ID: X86::VK8RegClassID,
1531 .CopyCost: 1, /* CopyCost */
1532 .Allocatable: true, /* Allocatable */
1533 .BaseClass: false,
1534 offsetof(X86RegisterClassStorage, SubClassMasks[165]) - 14 * sizeof(MCRegisterClass),
1535 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 14 * sizeof(MCRegisterClass),
1536 .LaneMask: LaneBitmask(0x0000000000000001),
1537 .AllocationPriority: 0,
1538 .GlobalPriority: false,
1539 .TSFlags: 0x00, /* TSFlags */
1540 .SpillStackID: 0, /* SpillStackID */
1541 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1542 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1543 offsetof(X86RegisterClassStorage, SuperClasses[28]) - 14 * sizeof(MCRegisterClass),
1544 .SuperClassesSize: 4
1545 },
1546 {
1547 offsetof(X86RegisterClassStorage, Regs[229]) - 15 * sizeof(MCRegisterClass),
1548 offsetof(X86RegisterClassStorage, BitSets[375]) - 15 * sizeof(MCRegisterClass),
1549 .NameIdx: 1077,
1550 .RegSizeInBits: 16,
1551 .RegsSize: 7,
1552 .RegSetSize: 27,
1553 .ID: X86::VK16WMRegClassID,
1554 .CopyCost: 1, /* CopyCost */
1555 .Allocatable: true, /* Allocatable */
1556 .BaseClass: false,
1557 offsetof(X86RegisterClassStorage, SubClassMasks[180]) - 15 * sizeof(MCRegisterClass),
1558 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 15 * sizeof(MCRegisterClass),
1559 .LaneMask: LaneBitmask(0x0000000000000001),
1560 .AllocationPriority: 0,
1561 .GlobalPriority: false,
1562 .TSFlags: 0x00, /* TSFlags */
1563 .SpillStackID: 0, /* SpillStackID */
1564 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1565 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1566 offsetof(X86RegisterClassStorage, SuperClasses[32]) - 15 * sizeof(MCRegisterClass),
1567 .SuperClassesSize: 9
1568 },
1569 {
1570 offsetof(X86RegisterClassStorage, Regs[236]) - 16 * sizeof(MCRegisterClass),
1571 offsetof(X86RegisterClassStorage, BitSets[402]) - 16 * sizeof(MCRegisterClass),
1572 .NameIdx: 1045,
1573 .RegSizeInBits: 16,
1574 .RegsSize: 7,
1575 .RegSetSize: 27,
1576 .ID: X86::VK1WMRegClassID,
1577 .CopyCost: 1, /* CopyCost */
1578 .Allocatable: true, /* Allocatable */
1579 .BaseClass: false,
1580 offsetof(X86RegisterClassStorage, SubClassMasks[195]) - 16 * sizeof(MCRegisterClass),
1581 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 16 * sizeof(MCRegisterClass),
1582 .LaneMask: LaneBitmask(0x0000000000000001),
1583 .AllocationPriority: 0,
1584 .GlobalPriority: false,
1585 .TSFlags: 0x00, /* TSFlags */
1586 .SpillStackID: 0, /* SpillStackID */
1587 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1588 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1589 offsetof(X86RegisterClassStorage, SuperClasses[41]) - 16 * sizeof(MCRegisterClass),
1590 .SuperClassesSize: 9
1591 },
1592 {
1593 offsetof(X86RegisterClassStorage, Regs[243]) - 17 * sizeof(MCRegisterClass),
1594 offsetof(X86RegisterClassStorage, BitSets[429]) - 17 * sizeof(MCRegisterClass),
1595 .NameIdx: 1058,
1596 .RegSizeInBits: 16,
1597 .RegsSize: 7,
1598 .RegSetSize: 27,
1599 .ID: X86::VK2WMRegClassID,
1600 .CopyCost: 1, /* CopyCost */
1601 .Allocatable: true, /* Allocatable */
1602 .BaseClass: false,
1603 offsetof(X86RegisterClassStorage, SubClassMasks[210]) - 17 * sizeof(MCRegisterClass),
1604 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 17 * sizeof(MCRegisterClass),
1605 .LaneMask: LaneBitmask(0x0000000000000001),
1606 .AllocationPriority: 0,
1607 .GlobalPriority: false,
1608 .TSFlags: 0x00, /* TSFlags */
1609 .SpillStackID: 0, /* SpillStackID */
1610 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1611 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1612 offsetof(X86RegisterClassStorage, SuperClasses[50]) - 17 * sizeof(MCRegisterClass),
1613 .SuperClassesSize: 9
1614 },
1615 {
1616 offsetof(X86RegisterClassStorage, Regs[250]) - 18 * sizeof(MCRegisterClass),
1617 offsetof(X86RegisterClassStorage, BitSets[456]) - 18 * sizeof(MCRegisterClass),
1618 .NameIdx: 1071,
1619 .RegSizeInBits: 16,
1620 .RegsSize: 7,
1621 .RegSetSize: 27,
1622 .ID: X86::VK4WMRegClassID,
1623 .CopyCost: 1, /* CopyCost */
1624 .Allocatable: true, /* Allocatable */
1625 .BaseClass: false,
1626 offsetof(X86RegisterClassStorage, SubClassMasks[225]) - 18 * sizeof(MCRegisterClass),
1627 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 18 * sizeof(MCRegisterClass),
1628 .LaneMask: LaneBitmask(0x0000000000000001),
1629 .AllocationPriority: 0,
1630 .GlobalPriority: false,
1631 .TSFlags: 0x00, /* TSFlags */
1632 .SpillStackID: 0, /* SpillStackID */
1633 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1634 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1635 offsetof(X86RegisterClassStorage, SuperClasses[59]) - 18 * sizeof(MCRegisterClass),
1636 .SuperClassesSize: 9
1637 },
1638 {
1639 offsetof(X86RegisterClassStorage, Regs[257]) - 19 * sizeof(MCRegisterClass),
1640 offsetof(X86RegisterClassStorage, BitSets[483]) - 19 * sizeof(MCRegisterClass),
1641 .NameIdx: 1084,
1642 .RegSizeInBits: 16,
1643 .RegsSize: 7,
1644 .RegSetSize: 27,
1645 .ID: X86::VK8WMRegClassID,
1646 .CopyCost: 1, /* CopyCost */
1647 .Allocatable: true, /* Allocatable */
1648 .BaseClass: false,
1649 offsetof(X86RegisterClassStorage, SubClassMasks[240]) - 19 * sizeof(MCRegisterClass),
1650 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 19 * sizeof(MCRegisterClass),
1651 .LaneMask: LaneBitmask(0x0000000000000001),
1652 .AllocationPriority: 0,
1653 .GlobalPriority: false,
1654 .TSFlags: 0x00, /* TSFlags */
1655 .SpillStackID: 0, /* SpillStackID */
1656 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1657 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1658 offsetof(X86RegisterClassStorage, SuperClasses[68]) - 19 * sizeof(MCRegisterClass),
1659 .SuperClassesSize: 9
1660 },
1661 {
1662 offsetof(X86RegisterClassStorage, Regs[264]) - 20 * sizeof(MCRegisterClass),
1663 offsetof(X86RegisterClassStorage, BitSets[510]) - 20 * sizeof(MCRegisterClass),
1664 .NameIdx: 780,
1665 .RegSizeInBits: 16,
1666 .RegsSize: 6,
1667 .RegSetSize: 9,
1668 .ID: X86::SEGMENT_REGRegClassID,
1669 .CopyCost: 1, /* CopyCost */
1670 .Allocatable: true, /* Allocatable */
1671 .BaseClass: false,
1672 offsetof(X86RegisterClassStorage, SubClassMasks[255]) - 20 * sizeof(MCRegisterClass),
1673 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 20 * sizeof(MCRegisterClass),
1674 .LaneMask: LaneBitmask(0x0000000000000001),
1675 .AllocationPriority: 0,
1676 .GlobalPriority: false,
1677 .TSFlags: 0x00, /* TSFlags */
1678 .SpillStackID: 0, /* SpillStackID */
1679 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1680 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1681 offsetof(X86RegisterClassStorage, SuperClasses[77]) - 20 * sizeof(MCRegisterClass),
1682 .SuperClassesSize: 0
1683 },
1684 {
1685 offsetof(X86RegisterClassStorage, Regs[270]) - 21 * sizeof(MCRegisterClass),
1686 offsetof(X86RegisterClassStorage, BitSets[519]) - 21 * sizeof(MCRegisterClass),
1687 .NameIdx: 743,
1688 .RegSizeInBits: 16,
1689 .RegsSize: 4,
1690 .RegSetSize: 3,
1691 .ID: X86::GR16_ABCDRegClassID,
1692 .CopyCost: 1, /* CopyCost */
1693 .Allocatable: true, /* Allocatable */
1694 .BaseClass: false,
1695 offsetof(X86RegisterClassStorage, SubClassMasks[260]) - 21 * sizeof(MCRegisterClass),
1696 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[5]) - 21 * sizeof(MCRegisterClass),
1697 .LaneMask: LaneBitmask(0x0000000000000003),
1698 .AllocationPriority: 0,
1699 .GlobalPriority: false,
1700 .TSFlags: 0x00, /* TSFlags */
1701 .SpillStackID: 0, /* SpillStackID */
1702 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1703 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1704 offsetof(X86RegisterClassStorage, SuperClasses[77]) - 21 * sizeof(MCRegisterClass),
1705 .SuperClassesSize: 3
1706 },
1707 {
1708 offsetof(X86RegisterClassStorage, Regs[274]) - 22 * sizeof(MCRegisterClass),
1709 offsetof(X86RegisterClassStorage, BitSets[522]) - 22 * sizeof(MCRegisterClass),
1710 .NameIdx: 1326,
1711 .RegSizeInBits: 16,
1712 .RegsSize: 1,
1713 .RegSetSize: 5,
1714 .ID: X86::FPCCRRegClassID,
1715 .CopyCost: 255, /* CopyCost */
1716 .Allocatable: false, /* Allocatable */
1717 .BaseClass: false,
1718 offsetof(X86RegisterClassStorage, SubClassMasks[270]) - 22 * sizeof(MCRegisterClass),
1719 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 22 * sizeof(MCRegisterClass),
1720 .LaneMask: LaneBitmask(0x0000000000000001),
1721 .AllocationPriority: 0,
1722 .GlobalPriority: false,
1723 .TSFlags: 0x00, /* TSFlags */
1724 .SpillStackID: 0, /* SpillStackID */
1725 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1726 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1727 offsetof(X86RegisterClassStorage, SuperClasses[80]) - 22 * sizeof(MCRegisterClass),
1728 .SuperClassesSize: 0
1729 },
1730 {
1731 offsetof(X86RegisterClassStorage, Regs[275]) - 23 * sizeof(MCRegisterClass),
1732 offsetof(X86RegisterClassStorage, BitSets[527]) - 23 * sizeof(MCRegisterClass),
1733 .NameIdx: 1416,
1734 .RegSizeInBits: 32,
1735 .RegsSize: 32,
1736 .RegSetSize: 29,
1737 .ID: X86::FR16XRegClassID,
1738 .CopyCost: 1, /* CopyCost */
1739 .Allocatable: true, /* Allocatable */
1740 .BaseClass: false,
1741 offsetof(X86RegisterClassStorage, SubClassMasks[275]) - 23 * sizeof(MCRegisterClass),
1742 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 23 * sizeof(MCRegisterClass),
1743 .LaneMask: LaneBitmask(0x0000000000000001),
1744 .AllocationPriority: 0,
1745 .GlobalPriority: false,
1746 .TSFlags: 0x00, /* TSFlags */
1747 .SpillStackID: 0, /* SpillStackID */
1748 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1749 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1750 offsetof(X86RegisterClassStorage, SuperClasses[80]) - 23 * sizeof(MCRegisterClass),
1751 .SuperClassesSize: 0
1752 },
1753 {
1754 offsetof(X86RegisterClassStorage, Regs[307]) - 24 * sizeof(MCRegisterClass),
1755 offsetof(X86RegisterClassStorage, BitSets[556]) - 24 * sizeof(MCRegisterClass),
1756 .NameIdx: 335,
1757 .RegSizeInBits: 32,
1758 .RegsSize: 16,
1759 .RegSetSize: 19,
1760 .ID: X86::FR16RegClassID,
1761 .CopyCost: 1, /* CopyCost */
1762 .Allocatable: true, /* Allocatable */
1763 .BaseClass: false,
1764 offsetof(X86RegisterClassStorage, SubClassMasks[285]) - 24 * sizeof(MCRegisterClass),
1765 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 24 * sizeof(MCRegisterClass),
1766 .LaneMask: LaneBitmask(0x0000000000000001),
1767 .AllocationPriority: 0,
1768 .GlobalPriority: false,
1769 .TSFlags: 0x00, /* TSFlags */
1770 .SpillStackID: 0, /* SpillStackID */
1771 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1772 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1773 offsetof(X86RegisterClassStorage, SuperClasses[80]) - 24 * sizeof(MCRegisterClass),
1774 .SuperClassesSize: 1
1775 },
1776 {
1777 offsetof(X86RegisterClassStorage, Regs[323]) - 25 * sizeof(MCRegisterClass),
1778 offsetof(X86RegisterClassStorage, BitSets[575]) - 25 * sizeof(MCRegisterClass),
1779 .NameIdx: 1356,
1780 .RegSizeInBits: 32,
1781 .RegsSize: 4,
1782 .RegSetSize: 36,
1783 .ID: X86::VK16PAIRRegClassID,
1784 .CopyCost: 1, /* CopyCost */
1785 .Allocatable: true, /* Allocatable */
1786 .BaseClass: false,
1787 offsetof(X86RegisterClassStorage, SubClassMasks[295]) - 25 * sizeof(MCRegisterClass),
1788 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 25 * sizeof(MCRegisterClass),
1789 .LaneMask: LaneBitmask(0x0000000000000030),
1790 .AllocationPriority: 0,
1791 .GlobalPriority: false,
1792 .TSFlags: 0x00, /* TSFlags */
1793 .SpillStackID: 0, /* SpillStackID */
1794 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1795 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1796 offsetof(X86RegisterClassStorage, SuperClasses[81]) - 25 * sizeof(MCRegisterClass),
1797 .SuperClassesSize: 4
1798 },
1799 {
1800 offsetof(X86RegisterClassStorage, Regs[327]) - 26 * sizeof(MCRegisterClass),
1801 offsetof(X86RegisterClassStorage, BitSets[611]) - 26 * sizeof(MCRegisterClass),
1802 .NameIdx: 1332,
1803 .RegSizeInBits: 32,
1804 .RegsSize: 4,
1805 .RegSetSize: 36,
1806 .ID: X86::VK1PAIRRegClassID,
1807 .CopyCost: 1, /* CopyCost */
1808 .Allocatable: true, /* Allocatable */
1809 .BaseClass: false,
1810 offsetof(X86RegisterClassStorage, SubClassMasks[300]) - 26 * sizeof(MCRegisterClass),
1811 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 26 * sizeof(MCRegisterClass),
1812 .LaneMask: LaneBitmask(0x0000000000000030),
1813 .AllocationPriority: 0,
1814 .GlobalPriority: false,
1815 .TSFlags: 0x00, /* TSFlags */
1816 .SpillStackID: 0, /* SpillStackID */
1817 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1818 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1819 offsetof(X86RegisterClassStorage, SuperClasses[85]) - 26 * sizeof(MCRegisterClass),
1820 .SuperClassesSize: 4
1821 },
1822 {
1823 offsetof(X86RegisterClassStorage, Regs[331]) - 27 * sizeof(MCRegisterClass),
1824 offsetof(X86RegisterClassStorage, BitSets[647]) - 27 * sizeof(MCRegisterClass),
1825 .NameIdx: 1340,
1826 .RegSizeInBits: 32,
1827 .RegsSize: 4,
1828 .RegSetSize: 36,
1829 .ID: X86::VK2PAIRRegClassID,
1830 .CopyCost: 1, /* CopyCost */
1831 .Allocatable: true, /* Allocatable */
1832 .BaseClass: false,
1833 offsetof(X86RegisterClassStorage, SubClassMasks[305]) - 27 * sizeof(MCRegisterClass),
1834 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 27 * sizeof(MCRegisterClass),
1835 .LaneMask: LaneBitmask(0x0000000000000030),
1836 .AllocationPriority: 0,
1837 .GlobalPriority: false,
1838 .TSFlags: 0x00, /* TSFlags */
1839 .SpillStackID: 0, /* SpillStackID */
1840 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1841 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1842 offsetof(X86RegisterClassStorage, SuperClasses[89]) - 27 * sizeof(MCRegisterClass),
1843 .SuperClassesSize: 4
1844 },
1845 {
1846 offsetof(X86RegisterClassStorage, Regs[335]) - 28 * sizeof(MCRegisterClass),
1847 offsetof(X86RegisterClassStorage, BitSets[683]) - 28 * sizeof(MCRegisterClass),
1848 .NameIdx: 1348,
1849 .RegSizeInBits: 32,
1850 .RegsSize: 4,
1851 .RegSetSize: 36,
1852 .ID: X86::VK4PAIRRegClassID,
1853 .CopyCost: 1, /* CopyCost */
1854 .Allocatable: true, /* Allocatable */
1855 .BaseClass: false,
1856 offsetof(X86RegisterClassStorage, SubClassMasks[310]) - 28 * sizeof(MCRegisterClass),
1857 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 28 * sizeof(MCRegisterClass),
1858 .LaneMask: LaneBitmask(0x0000000000000030),
1859 .AllocationPriority: 0,
1860 .GlobalPriority: false,
1861 .TSFlags: 0x00, /* TSFlags */
1862 .SpillStackID: 0, /* SpillStackID */
1863 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1864 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1865 offsetof(X86RegisterClassStorage, SuperClasses[93]) - 28 * sizeof(MCRegisterClass),
1866 .SuperClassesSize: 4
1867 },
1868 {
1869 offsetof(X86RegisterClassStorage, Regs[339]) - 29 * sizeof(MCRegisterClass),
1870 offsetof(X86RegisterClassStorage, BitSets[719]) - 29 * sizeof(MCRegisterClass),
1871 .NameIdx: 1365,
1872 .RegSizeInBits: 32,
1873 .RegsSize: 4,
1874 .RegSetSize: 36,
1875 .ID: X86::VK8PAIRRegClassID,
1876 .CopyCost: 1, /* CopyCost */
1877 .Allocatable: true, /* Allocatable */
1878 .BaseClass: false,
1879 offsetof(X86RegisterClassStorage, SubClassMasks[315]) - 29 * sizeof(MCRegisterClass),
1880 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 29 * sizeof(MCRegisterClass),
1881 .LaneMask: LaneBitmask(0x0000000000000030),
1882 .AllocationPriority: 0,
1883 .GlobalPriority: false,
1884 .TSFlags: 0x00, /* TSFlags */
1885 .SpillStackID: 0, /* SpillStackID */
1886 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1887 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1888 offsetof(X86RegisterClassStorage, SuperClasses[97]) - 29 * sizeof(MCRegisterClass),
1889 .SuperClassesSize: 4
1890 },
1891 {
1892 offsetof(X86RegisterClassStorage, Regs[343]) - 30 * sizeof(MCRegisterClass),
1893 offsetof(X86RegisterClassStorage, BitSets[755]) - 30 * sizeof(MCRegisterClass),
1894 .NameIdx: 1018,
1895 .RegSizeInBits: 32,
1896 .RegsSize: 3,
1897 .RegSetSize: 36,
1898 .ID: X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID,
1899 .CopyCost: 1, /* CopyCost */
1900 .Allocatable: true, /* Allocatable */
1901 .BaseClass: false,
1902 offsetof(X86RegisterClassStorage, SubClassMasks[320]) - 30 * sizeof(MCRegisterClass),
1903 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 30 * sizeof(MCRegisterClass),
1904 .LaneMask: LaneBitmask(0x0000000000000030),
1905 .AllocationPriority: 0,
1906 .GlobalPriority: false,
1907 .TSFlags: 0x00, /* TSFlags */
1908 .SpillStackID: 0, /* SpillStackID */
1909 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1910 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1911 offsetof(X86RegisterClassStorage, SuperClasses[101]) - 30 * sizeof(MCRegisterClass),
1912 .SuperClassesSize: 5
1913 },
1914 {
1915 offsetof(X86RegisterClassStorage, Regs[346]) - 31 * sizeof(MCRegisterClass),
1916 offsetof(X86RegisterClassStorage, BitSets[791]) - 31 * sizeof(MCRegisterClass),
1917 .NameIdx: 1179,
1918 .RegSizeInBits: 32,
1919 .RegsSize: 34,
1920 .RegSetSize: 45,
1921 .ID: X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1922 .CopyCost: 1, /* CopyCost */
1923 .Allocatable: true, /* Allocatable */
1924 .BaseClass: false,
1925 offsetof(X86RegisterClassStorage, SubClassMasks[325]) - 31 * sizeof(MCRegisterClass),
1926 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 31 * sizeof(MCRegisterClass),
1927 .LaneMask: LaneBitmask(0x000000000000000F),
1928 .AllocationPriority: 0,
1929 .GlobalPriority: false,
1930 .TSFlags: 0x00, /* TSFlags */
1931 .SpillStackID: 0, /* SpillStackID */
1932 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1933 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1934 offsetof(X86RegisterClassStorage, SuperClasses[106]) - 31 * sizeof(MCRegisterClass),
1935 .SuperClassesSize: 0
1936 },
1937 {
1938 offsetof(X86RegisterClassStorage, Regs[380]) - 32 * sizeof(MCRegisterClass),
1939 offsetof(X86RegisterClassStorage, BitSets[836]) - 32 * sizeof(MCRegisterClass),
1940 .NameIdx: 1382,
1941 .RegSizeInBits: 32,
1942 .RegsSize: 33,
1943 .RegSetSize: 45,
1944 .ID: X86::LOW32_ADDR_ACCESSRegClassID,
1945 .CopyCost: 1, /* CopyCost */
1946 .Allocatable: true, /* Allocatable */
1947 .BaseClass: false,
1948 offsetof(X86RegisterClassStorage, SubClassMasks[335]) - 32 * sizeof(MCRegisterClass),
1949 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 32 * sizeof(MCRegisterClass),
1950 .LaneMask: LaneBitmask(0x000000000000000F),
1951 .AllocationPriority: 0,
1952 .GlobalPriority: false,
1953 .TSFlags: 0x00, /* TSFlags */
1954 .SpillStackID: 0, /* SpillStackID */
1955 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1956 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1957 offsetof(X86RegisterClassStorage, SuperClasses[106]) - 32 * sizeof(MCRegisterClass),
1958 .SuperClassesSize: 1
1959 },
1960 {
1961 offsetof(X86RegisterClassStorage, Regs[413]) - 33 * sizeof(MCRegisterClass),
1962 offsetof(X86RegisterClassStorage, BitSets[881]) - 33 * sizeof(MCRegisterClass),
1963 .NameIdx: 1873,
1964 .RegSizeInBits: 32,
1965 .RegsSize: 33,
1966 .RegSetSize: 45,
1967 .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1968 .CopyCost: 1, /* CopyCost */
1969 .Allocatable: true, /* Allocatable */
1970 .BaseClass: false,
1971 offsetof(X86RegisterClassStorage, SubClassMasks[345]) - 33 * sizeof(MCRegisterClass),
1972 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 33 * sizeof(MCRegisterClass),
1973 .LaneMask: LaneBitmask(0x000000000000000F),
1974 .AllocationPriority: 0,
1975 .GlobalPriority: false,
1976 .TSFlags: 0x00, /* TSFlags */
1977 .SpillStackID: 0, /* SpillStackID */
1978 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1979 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1980 offsetof(X86RegisterClassStorage, SuperClasses[107]) - 33 * sizeof(MCRegisterClass),
1981 .SuperClassesSize: 1
1982 },
1983 {
1984 offsetof(X86RegisterClassStorage, Regs[446]) - 34 * sizeof(MCRegisterClass),
1985 offsetof(X86RegisterClassStorage, BitSets[926]) - 34 * sizeof(MCRegisterClass),
1986 .NameIdx: 1404,
1987 .RegSizeInBits: 32,
1988 .RegsSize: 32,
1989 .RegSetSize: 29,
1990 .ID: X86::FR32XRegClassID,
1991 .CopyCost: 1, /* CopyCost */
1992 .Allocatable: true, /* Allocatable */
1993 .BaseClass: false,
1994 offsetof(X86RegisterClassStorage, SubClassMasks[355]) - 34 * sizeof(MCRegisterClass),
1995 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 34 * sizeof(MCRegisterClass),
1996 .LaneMask: LaneBitmask(0x0000000000000001),
1997 .AllocationPriority: 0,
1998 .GlobalPriority: false,
1999 .TSFlags: 0x00, /* TSFlags */
2000 .SpillStackID: 0, /* SpillStackID */
2001 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2002 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2003 offsetof(X86RegisterClassStorage, SuperClasses[108]) - 34 * sizeof(MCRegisterClass),
2004 .SuperClassesSize: 1
2005 },
2006 {
2007 offsetof(X86RegisterClassStorage, Regs[478]) - 35 * sizeof(MCRegisterClass),
2008 offsetof(X86RegisterClassStorage, BitSets[955]) - 35 * sizeof(MCRegisterClass),
2009 .NameIdx: 32,
2010 .RegSizeInBits: 32,
2011 .RegsSize: 32,
2012 .RegSetSize: 45,
2013 .ID: X86::GR32RegClassID,
2014 .CopyCost: 1, /* CopyCost */
2015 .Allocatable: true, /* Allocatable */
2016 .BaseClass: false,
2017 offsetof(X86RegisterClassStorage, SubClassMasks[365]) - 35 * sizeof(MCRegisterClass),
2018 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 35 * sizeof(MCRegisterClass),
2019 .LaneMask: LaneBitmask(0x000000000000000F),
2020 .AllocationPriority: 0,
2021 .GlobalPriority: false,
2022 .TSFlags: 0x00, /* TSFlags */
2023 .SpillStackID: 0, /* SpillStackID */
2024 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2025 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2026 offsetof(X86RegisterClassStorage, SuperClasses[109]) - 35 * sizeof(MCRegisterClass),
2027 .SuperClassesSize: 3
2028 },
2029 {
2030 offsetof(X86RegisterClassStorage, Regs[510]) - 36 * sizeof(MCRegisterClass),
2031 offsetof(X86RegisterClassStorage, BitSets[1000]) - 36 * sizeof(MCRegisterClass),
2032 .NameIdx: 1201,
2033 .RegSizeInBits: 32,
2034 .RegsSize: 31,
2035 .RegSetSize: 45,
2036 .ID: X86::GR32_NOSPRegClassID,
2037 .CopyCost: 1, /* CopyCost */
2038 .Allocatable: true, /* Allocatable */
2039 .BaseClass: false,
2040 offsetof(X86RegisterClassStorage, SubClassMasks[375]) - 36 * sizeof(MCRegisterClass),
2041 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 36 * sizeof(MCRegisterClass),
2042 .LaneMask: LaneBitmask(0x000000000000000F),
2043 .AllocationPriority: 0,
2044 .GlobalPriority: false,
2045 .TSFlags: 0x00, /* TSFlags */
2046 .SpillStackID: 0, /* SpillStackID */
2047 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2048 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2049 offsetof(X86RegisterClassStorage, SuperClasses[112]) - 36 * sizeof(MCRegisterClass),
2050 .SuperClassesSize: 4
2051 },
2052 {
2053 offsetof(X86RegisterClassStorage, Regs[541]) - 37 * sizeof(MCRegisterClass),
2054 offsetof(X86RegisterClassStorage, BitSets[1045]) - 37 * sizeof(MCRegisterClass),
2055 .NameIdx: 100,
2056 .RegSizeInBits: 32,
2057 .RegsSize: 17,
2058 .RegSetSize: 22,
2059 .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
2060 .CopyCost: 1, /* CopyCost */
2061 .Allocatable: true, /* Allocatable */
2062 .BaseClass: false,
2063 offsetof(X86RegisterClassStorage, SubClassMasks[385]) - 37 * sizeof(MCRegisterClass),
2064 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 37 * sizeof(MCRegisterClass),
2065 .LaneMask: LaneBitmask(0x000000000000000F),
2066 .AllocationPriority: 0,
2067 .GlobalPriority: false,
2068 .TSFlags: 0x00, /* TSFlags */
2069 .SpillStackID: 0, /* SpillStackID */
2070 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2071 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2072 offsetof(X86RegisterClassStorage, SuperClasses[116]) - 37 * sizeof(MCRegisterClass),
2073 .SuperClassesSize: 2
2074 },
2075 {
2076 offsetof(X86RegisterClassStorage, Regs[558]) - 38 * sizeof(MCRegisterClass),
2077 offsetof(X86RegisterClassStorage, BitSets[1067]) - 38 * sizeof(MCRegisterClass),
2078 .NameIdx: 758,
2079 .RegSizeInBits: 32,
2080 .RegsSize: 16,
2081 .RegSetSize: 13,
2082 .ID: X86::DEBUG_REGRegClassID,
2083 .CopyCost: 1, /* CopyCost */
2084 .Allocatable: true, /* Allocatable */
2085 .BaseClass: false,
2086 offsetof(X86RegisterClassStorage, SubClassMasks[395]) - 38 * sizeof(MCRegisterClass),
2087 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 38 * sizeof(MCRegisterClass),
2088 .LaneMask: LaneBitmask(0x0000000000000001),
2089 .AllocationPriority: 0,
2090 .GlobalPriority: false,
2091 .TSFlags: 0x00, /* TSFlags */
2092 .SpillStackID: 0, /* SpillStackID */
2093 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2094 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2095 offsetof(X86RegisterClassStorage, SuperClasses[118]) - 38 * sizeof(MCRegisterClass),
2096 .SuperClassesSize: 0
2097 },
2098 {
2099 offsetof(X86RegisterClassStorage, Regs[574]) - 39 * sizeof(MCRegisterClass),
2100 offsetof(X86RegisterClassStorage, BitSets[1080]) - 39 * sizeof(MCRegisterClass),
2101 .NameIdx: 27,
2102 .RegSizeInBits: 32,
2103 .RegsSize: 16,
2104 .RegSetSize: 19,
2105 .ID: X86::FR32RegClassID,
2106 .CopyCost: 1, /* CopyCost */
2107 .Allocatable: true, /* Allocatable */
2108 .BaseClass: false,
2109 offsetof(X86RegisterClassStorage, SubClassMasks[400]) - 39 * sizeof(MCRegisterClass),
2110 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 39 * sizeof(MCRegisterClass),
2111 .LaneMask: LaneBitmask(0x0000000000000001),
2112 .AllocationPriority: 0,
2113 .GlobalPriority: false,
2114 .TSFlags: 0x00, /* TSFlags */
2115 .SpillStackID: 0, /* SpillStackID */
2116 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2117 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2118 offsetof(X86RegisterClassStorage, SuperClasses[118]) - 39 * sizeof(MCRegisterClass),
2119 .SuperClassesSize: 3
2120 },
2121 {
2122 offsetof(X86RegisterClassStorage, Regs[590]) - 40 * sizeof(MCRegisterClass),
2123 offsetof(X86RegisterClassStorage, BitSets[1099]) - 40 * sizeof(MCRegisterClass),
2124 .NameIdx: 41,
2125 .RegSizeInBits: 32,
2126 .RegsSize: 16,
2127 .RegSetSize: 22,
2128 .ID: X86::GR32_NOREX2RegClassID,
2129 .CopyCost: 1, /* CopyCost */
2130 .Allocatable: true, /* Allocatable */
2131 .BaseClass: false,
2132 offsetof(X86RegisterClassStorage, SubClassMasks[410]) - 40 * sizeof(MCRegisterClass),
2133 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 40 * sizeof(MCRegisterClass),
2134 .LaneMask: LaneBitmask(0x000000000000000F),
2135 .AllocationPriority: 0,
2136 .GlobalPriority: false,
2137 .TSFlags: 0x00, /* TSFlags */
2138 .SpillStackID: 0, /* SpillStackID */
2139 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2140 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2141 offsetof(X86RegisterClassStorage, SuperClasses[121]) - 40 * sizeof(MCRegisterClass),
2142 .SuperClassesSize: 5
2143 },
2144 {
2145 offsetof(X86RegisterClassStorage, Regs[606]) - 41 * sizeof(MCRegisterClass),
2146 offsetof(X86RegisterClassStorage, BitSets[1121]) - 41 * sizeof(MCRegisterClass),
2147 .NameIdx: 1211,
2148 .RegSizeInBits: 32,
2149 .RegsSize: 15,
2150 .RegSetSize: 22,
2151 .ID: X86::GR32_NOREX2_NOSPRegClassID,
2152 .CopyCost: 1, /* CopyCost */
2153 .Allocatable: true, /* Allocatable */
2154 .BaseClass: false,
2155 offsetof(X86RegisterClassStorage, SubClassMasks[420]) - 41 * sizeof(MCRegisterClass),
2156 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 41 * sizeof(MCRegisterClass),
2157 .LaneMask: LaneBitmask(0x000000000000000F),
2158 .AllocationPriority: 0,
2159 .GlobalPriority: false,
2160 .TSFlags: 0x00, /* TSFlags */
2161 .SpillStackID: 0, /* SpillStackID */
2162 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2163 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2164 offsetof(X86RegisterClassStorage, SuperClasses[126]) - 41 * sizeof(MCRegisterClass),
2165 .SuperClassesSize: 7
2166 },
2167 {
2168 offsetof(X86RegisterClassStorage, Regs[621]) - 42 * sizeof(MCRegisterClass),
2169 offsetof(X86RegisterClassStorage, BitSets[1143]) - 42 * sizeof(MCRegisterClass),
2170 .NameIdx: 1504,
2171 .RegSizeInBits: 32,
2172 .RegsSize: 9,
2173 .RegSetSize: 7,
2174 .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
2175 .CopyCost: 1, /* CopyCost */
2176 .Allocatable: true, /* Allocatable */
2177 .BaseClass: false,
2178 offsetof(X86RegisterClassStorage, SubClassMasks[430]) - 42 * sizeof(MCRegisterClass),
2179 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 42 * sizeof(MCRegisterClass),
2180 .LaneMask: LaneBitmask(0x000000000000000F),
2181 .AllocationPriority: 0,
2182 .GlobalPriority: false,
2183 .TSFlags: 0x00, /* TSFlags */
2184 .SpillStackID: 0, /* SpillStackID */
2185 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2186 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2187 offsetof(X86RegisterClassStorage, SuperClasses[133]) - 42 * sizeof(MCRegisterClass),
2188 .SuperClassesSize: 3
2189 },
2190 {
2191 offsetof(X86RegisterClassStorage, Regs[630]) - 43 * sizeof(MCRegisterClass),
2192 offsetof(X86RegisterClassStorage, BitSets[1150]) - 43 * sizeof(MCRegisterClass),
2193 .NameIdx: 1436,
2194 .RegSizeInBits: 32,
2195 .RegsSize: 8,
2196 .RegSetSize: 5,
2197 .ID: X86::GR32_NOREXRegClassID,
2198 .CopyCost: 1, /* CopyCost */
2199 .Allocatable: true, /* Allocatable */
2200 .BaseClass: false,
2201 offsetof(X86RegisterClassStorage, SubClassMasks[440]) - 43 * sizeof(MCRegisterClass),
2202 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 43 * sizeof(MCRegisterClass),
2203 .LaneMask: LaneBitmask(0x000000000000000F),
2204 .AllocationPriority: 0,
2205 .GlobalPriority: false,
2206 .TSFlags: 0x00, /* TSFlags */
2207 .SpillStackID: 0, /* SpillStackID */
2208 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2209 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2210 offsetof(X86RegisterClassStorage, SuperClasses[136]) - 43 * sizeof(MCRegisterClass),
2211 .SuperClassesSize: 7
2212 },
2213 {
2214 offsetof(X86RegisterClassStorage, Regs[638]) - 44 * sizeof(MCRegisterClass),
2215 offsetof(X86RegisterClassStorage, BitSets[1155]) - 44 * sizeof(MCRegisterClass),
2216 .NameIdx: 16,
2217 .RegSizeInBits: 32,
2218 .RegsSize: 8,
2219 .RegSetSize: 27,
2220 .ID: X86::VK32RegClassID,
2221 .CopyCost: 1, /* CopyCost */
2222 .Allocatable: true, /* Allocatable */
2223 .BaseClass: false,
2224 offsetof(X86RegisterClassStorage, SubClassMasks[450]) - 44 * sizeof(MCRegisterClass),
2225 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 44 * sizeof(MCRegisterClass),
2226 .LaneMask: LaneBitmask(0x0000000000000001),
2227 .AllocationPriority: 0,
2228 .GlobalPriority: false,
2229 .TSFlags: 0x00, /* TSFlags */
2230 .SpillStackID: 0, /* SpillStackID */
2231 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2232 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2233 offsetof(X86RegisterClassStorage, SuperClasses[143]) - 44 * sizeof(MCRegisterClass),
2234 .SuperClassesSize: 5
2235 },
2236 {
2237 offsetof(X86RegisterClassStorage, Regs[646]) - 45 * sizeof(MCRegisterClass),
2238 offsetof(X86RegisterClassStorage, BitSets[1182]) - 45 * sizeof(MCRegisterClass),
2239 .NameIdx: 1255,
2240 .RegSizeInBits: 32,
2241 .RegsSize: 7,
2242 .RegSetSize: 5,
2243 .ID: X86::GR32_NOREX_NOSPRegClassID,
2244 .CopyCost: 1, /* CopyCost */
2245 .Allocatable: true, /* Allocatable */
2246 .BaseClass: false,
2247 offsetof(X86RegisterClassStorage, SubClassMasks[465]) - 45 * sizeof(MCRegisterClass),
2248 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 45 * sizeof(MCRegisterClass),
2249 .LaneMask: LaneBitmask(0x000000000000000F),
2250 .AllocationPriority: 0,
2251 .GlobalPriority: false,
2252 .TSFlags: 0x00, /* TSFlags */
2253 .SpillStackID: 0, /* SpillStackID */
2254 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2255 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2256 offsetof(X86RegisterClassStorage, SuperClasses[148]) - 45 * sizeof(MCRegisterClass),
2257 .SuperClassesSize: 10
2258 },
2259 {
2260 offsetof(X86RegisterClassStorage, Regs[653]) - 46 * sizeof(MCRegisterClass),
2261 offsetof(X86RegisterClassStorage, BitSets[1187]) - 46 * sizeof(MCRegisterClass),
2262 .NameIdx: 21,
2263 .RegSizeInBits: 32,
2264 .RegsSize: 7,
2265 .RegSetSize: 14,
2266 .ID: X86::RFP32RegClassID,
2267 .CopyCost: 1, /* CopyCost */
2268 .Allocatable: true, /* Allocatable */
2269 .BaseClass: false,
2270 offsetof(X86RegisterClassStorage, SubClassMasks[475]) - 46 * sizeof(MCRegisterClass),
2271 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 46 * sizeof(MCRegisterClass),
2272 .LaneMask: LaneBitmask(0x0000000000000001),
2273 .AllocationPriority: 0,
2274 .GlobalPriority: false,
2275 .TSFlags: 0x00, /* TSFlags */
2276 .SpillStackID: 0, /* SpillStackID */
2277 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2278 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2279 offsetof(X86RegisterClassStorage, SuperClasses[158]) - 46 * sizeof(MCRegisterClass),
2280 .SuperClassesSize: 0
2281 },
2282 {
2283 offsetof(X86RegisterClassStorage, Regs[660]) - 47 * sizeof(MCRegisterClass),
2284 offsetof(X86RegisterClassStorage, BitSets[1201]) - 47 * sizeof(MCRegisterClass),
2285 .NameIdx: 1051,
2286 .RegSizeInBits: 32,
2287 .RegsSize: 7,
2288 .RegSetSize: 27,
2289 .ID: X86::VK32WMRegClassID,
2290 .CopyCost: 1, /* CopyCost */
2291 .Allocatable: true, /* Allocatable */
2292 .BaseClass: false,
2293 offsetof(X86RegisterClassStorage, SubClassMasks[480]) - 47 * sizeof(MCRegisterClass),
2294 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 47 * sizeof(MCRegisterClass),
2295 .LaneMask: LaneBitmask(0x0000000000000001),
2296 .AllocationPriority: 0,
2297 .GlobalPriority: false,
2298 .TSFlags: 0x00, /* TSFlags */
2299 .SpillStackID: 0, /* SpillStackID */
2300 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2301 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2302 offsetof(X86RegisterClassStorage, SuperClasses[158]) - 47 * sizeof(MCRegisterClass),
2303 .SuperClassesSize: 11
2304 },
2305 {
2306 offsetof(X86RegisterClassStorage, Regs[667]) - 48 * sizeof(MCRegisterClass),
2307 offsetof(X86RegisterClassStorage, BitSets[1228]) - 48 * sizeof(MCRegisterClass),
2308 .NameIdx: 723,
2309 .RegSizeInBits: 32,
2310 .RegsSize: 4,
2311 .RegSetSize: 4,
2312 .ID: X86::GR32_ABCDRegClassID,
2313 .CopyCost: 1, /* CopyCost */
2314 .Allocatable: true, /* Allocatable */
2315 .BaseClass: false,
2316 offsetof(X86RegisterClassStorage, SubClassMasks[495]) - 48 * sizeof(MCRegisterClass),
2317 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 48 * sizeof(MCRegisterClass),
2318 .LaneMask: LaneBitmask(0x000000000000000F),
2319 .AllocationPriority: 0,
2320 .GlobalPriority: false,
2321 .TSFlags: 0x00, /* TSFlags */
2322 .SpillStackID: 0, /* SpillStackID */
2323 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2324 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2325 offsetof(X86RegisterClassStorage, SuperClasses[169]) - 48 * sizeof(MCRegisterClass),
2326 .SuperClassesSize: 11
2327 },
2328 {
2329 offsetof(X86RegisterClassStorage, Regs[671]) - 49 * sizeof(MCRegisterClass),
2330 offsetof(X86RegisterClassStorage, BitSets[1232]) - 49 * sizeof(MCRegisterClass),
2331 .NameIdx: 508,
2332 .RegSizeInBits: 32,
2333 .RegsSize: 4,
2334 .RegSetSize: 5,
2335 .ID: X86::GR32_TCRegClassID,
2336 .CopyCost: 1, /* CopyCost */
2337 .Allocatable: true, /* Allocatable */
2338 .BaseClass: false,
2339 offsetof(X86RegisterClassStorage, SubClassMasks[505]) - 49 * sizeof(MCRegisterClass),
2340 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 49 * sizeof(MCRegisterClass),
2341 .LaneMask: LaneBitmask(0x000000000000000F),
2342 .AllocationPriority: 0,
2343 .GlobalPriority: false,
2344 .TSFlags: 0x00, /* TSFlags */
2345 .SpillStackID: 0, /* SpillStackID */
2346 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2347 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2348 offsetof(X86RegisterClassStorage, SuperClasses[180]) - 49 * sizeof(MCRegisterClass),
2349 .SuperClassesSize: 8
2350 },
2351 {
2352 offsetof(X86RegisterClassStorage, Regs[675]) - 50 * sizeof(MCRegisterClass),
2353 offsetof(X86RegisterClassStorage, BitSets[1237]) - 50 * sizeof(MCRegisterClass),
2354 .NameIdx: 494,
2355 .RegSizeInBits: 32,
2356 .RegsSize: 3,
2357 .RegSetSize: 4,
2358 .ID: X86::GR32_ABCD_and_GR32_TCRegClassID,
2359 .CopyCost: 1, /* CopyCost */
2360 .Allocatable: true, /* Allocatable */
2361 .BaseClass: false,
2362 offsetof(X86RegisterClassStorage, SubClassMasks[515]) - 50 * sizeof(MCRegisterClass),
2363 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 50 * sizeof(MCRegisterClass),
2364 .LaneMask: LaneBitmask(0x000000000000000F),
2365 .AllocationPriority: 0,
2366 .GlobalPriority: false,
2367 .TSFlags: 0x00, /* TSFlags */
2368 .SpillStackID: 0, /* SpillStackID */
2369 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2370 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2371 offsetof(X86RegisterClassStorage, SuperClasses[188]) - 50 * sizeof(MCRegisterClass),
2372 .SuperClassesSize: 13
2373 },
2374 {
2375 offsetof(X86RegisterClassStorage, Regs[678]) - 51 * sizeof(MCRegisterClass),
2376 offsetof(X86RegisterClassStorage, BitSets[1241]) - 51 * sizeof(MCRegisterClass),
2377 .NameIdx: 707,
2378 .RegSizeInBits: 32,
2379 .RegsSize: 2,
2380 .RegSetSize: 4,
2381 .ID: X86::GR32_ADRegClassID,
2382 .CopyCost: 1, /* CopyCost */
2383 .Allocatable: true, /* Allocatable */
2384 .BaseClass: false,
2385 offsetof(X86RegisterClassStorage, SubClassMasks[525]) - 51 * sizeof(MCRegisterClass),
2386 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 51 * sizeof(MCRegisterClass),
2387 .LaneMask: LaneBitmask(0x000000000000000F),
2388 .AllocationPriority: 0,
2389 .GlobalPriority: false,
2390 .TSFlags: 0x00, /* TSFlags */
2391 .SpillStackID: 0, /* SpillStackID */
2392 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2393 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2394 offsetof(X86RegisterClassStorage, SuperClasses[201]) - 51 * sizeof(MCRegisterClass),
2395 .SuperClassesSize: 14
2396 },
2397 {
2398 offsetof(X86RegisterClassStorage, Regs[680]) - 52 * sizeof(MCRegisterClass),
2399 offsetof(X86RegisterClassStorage, BitSets[1245]) - 52 * sizeof(MCRegisterClass),
2400 .NameIdx: 1612,
2401 .RegSizeInBits: 32,
2402 .RegsSize: 2,
2403 .RegSetSize: 4,
2404 .ID: X86::GR32_ArgRefRegClassID,
2405 .CopyCost: 1, /* CopyCost */
2406 .Allocatable: true, /* Allocatable */
2407 .BaseClass: false,
2408 offsetof(X86RegisterClassStorage, SubClassMasks[535]) - 52 * sizeof(MCRegisterClass),
2409 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 52 * sizeof(MCRegisterClass),
2410 .LaneMask: LaneBitmask(0x000000000000000F),
2411 .AllocationPriority: 0,
2412 .GlobalPriority: false,
2413 .TSFlags: 0x00, /* TSFlags */
2414 .SpillStackID: 0, /* SpillStackID */
2415 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2416 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2417 offsetof(X86RegisterClassStorage, SuperClasses[215]) - 52 * sizeof(MCRegisterClass),
2418 .SuperClassesSize: 14
2419 },
2420 {
2421 offsetof(X86RegisterClassStorage, Regs[682]) - 53 * sizeof(MCRegisterClass),
2422 offsetof(X86RegisterClassStorage, BitSets[1249]) - 53 * sizeof(MCRegisterClass),
2423 .NameIdx: 1310,
2424 .RegSizeInBits: 32,
2425 .RegsSize: 2,
2426 .RegSetSize: 5,
2427 .ID: X86::GR32_BPSPRegClassID,
2428 .CopyCost: 1, /* CopyCost */
2429 .Allocatable: true, /* Allocatable */
2430 .BaseClass: false,
2431 offsetof(X86RegisterClassStorage, SubClassMasks[545]) - 53 * sizeof(MCRegisterClass),
2432 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 53 * sizeof(MCRegisterClass),
2433 .LaneMask: LaneBitmask(0x000000000000000F),
2434 .AllocationPriority: 0,
2435 .GlobalPriority: false,
2436 .TSFlags: 0x00, /* TSFlags */
2437 .SpillStackID: 0, /* SpillStackID */
2438 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2439 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2440 offsetof(X86RegisterClassStorage, SuperClasses[229]) - 53 * sizeof(MCRegisterClass),
2441 .SuperClassesSize: 8
2442 },
2443 {
2444 offsetof(X86RegisterClassStorage, Regs[684]) - 54 * sizeof(MCRegisterClass),
2445 offsetof(X86RegisterClassStorage, BitSets[1254]) - 54 * sizeof(MCRegisterClass),
2446 .NameIdx: 966,
2447 .RegSizeInBits: 32,
2448 .RegsSize: 2,
2449 .RegSetSize: 5,
2450 .ID: X86::GR32_BSIRegClassID,
2451 .CopyCost: 1, /* CopyCost */
2452 .Allocatable: true, /* Allocatable */
2453 .BaseClass: false,
2454 offsetof(X86RegisterClassStorage, SubClassMasks[555]) - 54 * sizeof(MCRegisterClass),
2455 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 54 * sizeof(MCRegisterClass),
2456 .LaneMask: LaneBitmask(0x000000000000000F),
2457 .AllocationPriority: 0,
2458 .GlobalPriority: false,
2459 .TSFlags: 0x00, /* TSFlags */
2460 .SpillStackID: 0, /* SpillStackID */
2461 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2462 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2463 offsetof(X86RegisterClassStorage, SuperClasses[237]) - 54 * sizeof(MCRegisterClass),
2464 .SuperClassesSize: 11
2465 },
2466 {
2467 offsetof(X86RegisterClassStorage, Regs[686]) - 55 * sizeof(MCRegisterClass),
2468 offsetof(X86RegisterClassStorage, BitSets[1259]) - 55 * sizeof(MCRegisterClass),
2469 .NameIdx: 424,
2470 .RegSizeInBits: 32,
2471 .RegsSize: 2,
2472 .RegSetSize: 4,
2473 .ID: X86::GR32_CBRegClassID,
2474 .CopyCost: 1, /* CopyCost */
2475 .Allocatable: true, /* Allocatable */
2476 .BaseClass: false,
2477 offsetof(X86RegisterClassStorage, SubClassMasks[565]) - 55 * sizeof(MCRegisterClass),
2478 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 55 * sizeof(MCRegisterClass),
2479 .LaneMask: LaneBitmask(0x000000000000000F),
2480 .AllocationPriority: 0,
2481 .GlobalPriority: false,
2482 .TSFlags: 0x00, /* TSFlags */
2483 .SpillStackID: 0, /* SpillStackID */
2484 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2485 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2486 offsetof(X86RegisterClassStorage, SuperClasses[248]) - 55 * sizeof(MCRegisterClass),
2487 .SuperClassesSize: 12
2488 },
2489 {
2490 offsetof(X86RegisterClassStorage, Regs[688]) - 56 * sizeof(MCRegisterClass),
2491 offsetof(X86RegisterClassStorage, BitSets[1263]) - 56 * sizeof(MCRegisterClass),
2492 .NameIdx: 463,
2493 .RegSizeInBits: 32,
2494 .RegsSize: 2,
2495 .RegSetSize: 4,
2496 .ID: X86::GR32_DCRegClassID,
2497 .CopyCost: 1, /* CopyCost */
2498 .Allocatable: true, /* Allocatable */
2499 .BaseClass: false,
2500 offsetof(X86RegisterClassStorage, SubClassMasks[575]) - 56 * sizeof(MCRegisterClass),
2501 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 56 * sizeof(MCRegisterClass),
2502 .LaneMask: LaneBitmask(0x000000000000000F),
2503 .AllocationPriority: 0,
2504 .GlobalPriority: false,
2505 .TSFlags: 0x00, /* TSFlags */
2506 .SpillStackID: 0, /* SpillStackID */
2507 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2508 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2509 offsetof(X86RegisterClassStorage, SuperClasses[260]) - 56 * sizeof(MCRegisterClass),
2510 .SuperClassesSize: 15
2511 },
2512 {
2513 offsetof(X86RegisterClassStorage, Regs[690]) - 57 * sizeof(MCRegisterClass),
2514 offsetof(X86RegisterClassStorage, BitSets[1267]) - 57 * sizeof(MCRegisterClass),
2515 .NameIdx: 1127,
2516 .RegSizeInBits: 32,
2517 .RegsSize: 2,
2518 .RegSetSize: 4,
2519 .ID: X86::GR32_DIBPRegClassID,
2520 .CopyCost: 1, /* CopyCost */
2521 .Allocatable: true, /* Allocatable */
2522 .BaseClass: false,
2523 offsetof(X86RegisterClassStorage, SubClassMasks[585]) - 57 * sizeof(MCRegisterClass),
2524 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 57 * sizeof(MCRegisterClass),
2525 .LaneMask: LaneBitmask(0x000000000000000F),
2526 .AllocationPriority: 0,
2527 .GlobalPriority: false,
2528 .TSFlags: 0x00, /* TSFlags */
2529 .SpillStackID: 0, /* SpillStackID */
2530 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2531 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2532 offsetof(X86RegisterClassStorage, SuperClasses[275]) - 57 * sizeof(MCRegisterClass),
2533 .SuperClassesSize: 11
2534 },
2535 {
2536 offsetof(X86RegisterClassStorage, Regs[692]) - 58 * sizeof(MCRegisterClass),
2537 offsetof(X86RegisterClassStorage, BitSets[1271]) - 58 * sizeof(MCRegisterClass),
2538 .NameIdx: 839,
2539 .RegSizeInBits: 32,
2540 .RegsSize: 2,
2541 .RegSetSize: 5,
2542 .ID: X86::GR32_SIDIRegClassID,
2543 .CopyCost: 1, /* CopyCost */
2544 .Allocatable: true, /* Allocatable */
2545 .BaseClass: false,
2546 offsetof(X86RegisterClassStorage, SubClassMasks[595]) - 58 * sizeof(MCRegisterClass),
2547 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 58 * sizeof(MCRegisterClass),
2548 .LaneMask: LaneBitmask(0x000000000000000F),
2549 .AllocationPriority: 0,
2550 .GlobalPriority: false,
2551 .TSFlags: 0x00, /* TSFlags */
2552 .SpillStackID: 0, /* SpillStackID */
2553 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2554 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2555 offsetof(X86RegisterClassStorage, SuperClasses[286]) - 58 * sizeof(MCRegisterClass),
2556 .SuperClassesSize: 11
2557 },
2558 {
2559 offsetof(X86RegisterClassStorage, Regs[694]) - 59 * sizeof(MCRegisterClass),
2560 offsetof(X86RegisterClassStorage, BitSets[1276]) - 59 * sizeof(MCRegisterClass),
2561 .NameIdx: 1671,
2562 .RegSizeInBits: 32,
2563 .RegsSize: 2,
2564 .RegSetSize: 8,
2565 .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
2566 .CopyCost: 1, /* CopyCost */
2567 .Allocatable: true, /* Allocatable */
2568 .BaseClass: false,
2569 offsetof(X86RegisterClassStorage, SubClassMasks[605]) - 59 * sizeof(MCRegisterClass),
2570 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 59 * sizeof(MCRegisterClass),
2571 .LaneMask: LaneBitmask(0x000000000000000F),
2572 .AllocationPriority: 0,
2573 .GlobalPriority: false,
2574 .TSFlags: 0x00, /* TSFlags */
2575 .SpillStackID: 0, /* SpillStackID */
2576 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2577 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2578 offsetof(X86RegisterClassStorage, SuperClasses[297]) - 59 * sizeof(MCRegisterClass),
2579 .SuperClassesSize: 1
2580 },
2581 {
2582 offsetof(X86RegisterClassStorage, Regs[696]) - 60 * sizeof(MCRegisterClass),
2583 offsetof(X86RegisterClassStorage, BitSets[1284]) - 60 * sizeof(MCRegisterClass),
2584 .NameIdx: 1322,
2585 .RegSizeInBits: 32,
2586 .RegsSize: 1,
2587 .RegSetSize: 4,
2588 .ID: X86::CCRRegClassID,
2589 .CopyCost: 255, /* CopyCost */
2590 .Allocatable: false, /* Allocatable */
2591 .BaseClass: false,
2592 offsetof(X86RegisterClassStorage, SubClassMasks[610]) - 60 * sizeof(MCRegisterClass),
2593 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 60 * sizeof(MCRegisterClass),
2594 .LaneMask: LaneBitmask(0x0000000000000001),
2595 .AllocationPriority: 0,
2596 .GlobalPriority: false,
2597 .TSFlags: 0x00, /* TSFlags */
2598 .SpillStackID: 0, /* SpillStackID */
2599 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2600 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2601 offsetof(X86RegisterClassStorage, SuperClasses[298]) - 60 * sizeof(MCRegisterClass),
2602 .SuperClassesSize: 0
2603 },
2604 {
2605 offsetof(X86RegisterClassStorage, Regs[697]) - 61 * sizeof(MCRegisterClass),
2606 offsetof(X86RegisterClassStorage, BitSets[1288]) - 61 * sizeof(MCRegisterClass),
2607 .NameIdx: 1320,
2608 .RegSizeInBits: 32,
2609 .RegsSize: 1,
2610 .RegSetSize: 2,
2611 .ID: X86::DFCCRRegClassID,
2612 .CopyCost: 255, /* CopyCost */
2613 .Allocatable: false, /* Allocatable */
2614 .BaseClass: false,
2615 offsetof(X86RegisterClassStorage, SubClassMasks[615]) - 61 * sizeof(MCRegisterClass),
2616 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 61 * sizeof(MCRegisterClass),
2617 .LaneMask: LaneBitmask(0x0000000000000001),
2618 .AllocationPriority: 0,
2619 .GlobalPriority: false,
2620 .TSFlags: 0x00, /* TSFlags */
2621 .SpillStackID: 0, /* SpillStackID */
2622 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2623 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2624 offsetof(X86RegisterClassStorage, SuperClasses[298]) - 61 * sizeof(MCRegisterClass),
2625 .SuperClassesSize: 0
2626 },
2627 {
2628 offsetof(X86RegisterClassStorage, Regs[698]) - 62 * sizeof(MCRegisterClass),
2629 offsetof(X86RegisterClassStorage, BitSets[1290]) - 62 * sizeof(MCRegisterClass),
2630 .NameIdx: 952,
2631 .RegSizeInBits: 32,
2632 .RegsSize: 1,
2633 .RegSetSize: 4,
2634 .ID: X86::GR32_ABCD_and_GR32_BSIRegClassID,
2635 .CopyCost: 1, /* CopyCost */
2636 .Allocatable: true, /* Allocatable */
2637 .BaseClass: false,
2638 offsetof(X86RegisterClassStorage, SubClassMasks[620]) - 62 * sizeof(MCRegisterClass),
2639 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 62 * sizeof(MCRegisterClass),
2640 .LaneMask: LaneBitmask(0x000000000000000F),
2641 .AllocationPriority: 0,
2642 .GlobalPriority: false,
2643 .TSFlags: 0x00, /* TSFlags */
2644 .SpillStackID: 0, /* SpillStackID */
2645 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2646 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2647 offsetof(X86RegisterClassStorage, SuperClasses[298]) - 62 * sizeof(MCRegisterClass),
2648 .SuperClassesSize: 14
2649 },
2650 {
2651 offsetof(X86RegisterClassStorage, Regs[699]) - 63 * sizeof(MCRegisterClass),
2652 offsetof(X86RegisterClassStorage, BitSets[1294]) - 63 * sizeof(MCRegisterClass),
2653 .NameIdx: 1600,
2654 .RegSizeInBits: 32,
2655 .RegsSize: 1,
2656 .RegSetSize: 4,
2657 .ID: X86::GR32_AD_and_GR32_ArgRefRegClassID,
2658 .CopyCost: 1, /* CopyCost */
2659 .Allocatable: true, /* Allocatable */
2660 .BaseClass: false,
2661 offsetof(X86RegisterClassStorage, SubClassMasks[630]) - 63 * sizeof(MCRegisterClass),
2662 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 63 * sizeof(MCRegisterClass),
2663 .LaneMask: LaneBitmask(0x000000000000000F),
2664 .AllocationPriority: 0,
2665 .GlobalPriority: false,
2666 .TSFlags: 0x00, /* TSFlags */
2667 .SpillStackID: 0, /* SpillStackID */
2668 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2669 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2670 offsetof(X86RegisterClassStorage, SuperClasses[312]) - 63 * sizeof(MCRegisterClass),
2671 .SuperClassesSize: 17
2672 },
2673 {
2674 offsetof(X86RegisterClassStorage, Regs[700]) - 64 * sizeof(MCRegisterClass),
2675 offsetof(X86RegisterClassStorage, BitSets[1298]) - 64 * sizeof(MCRegisterClass),
2676 .NameIdx: 408,
2677 .RegSizeInBits: 32,
2678 .RegsSize: 1,
2679 .RegSetSize: 4,
2680 .ID: X86::GR32_ArgRef_and_GR32_CBRegClassID,
2681 .CopyCost: 1, /* CopyCost */
2682 .Allocatable: true, /* Allocatable */
2683 .BaseClass: false,
2684 offsetof(X86RegisterClassStorage, SubClassMasks[640]) - 64 * sizeof(MCRegisterClass),
2685 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 64 * sizeof(MCRegisterClass),
2686 .LaneMask: LaneBitmask(0x000000000000000F),
2687 .AllocationPriority: 0,
2688 .GlobalPriority: false,
2689 .TSFlags: 0x00, /* TSFlags */
2690 .SpillStackID: 0, /* SpillStackID */
2691 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2692 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2693 offsetof(X86RegisterClassStorage, SuperClasses[329]) - 64 * sizeof(MCRegisterClass),
2694 .SuperClassesSize: 17
2695 },
2696 {
2697 offsetof(X86RegisterClassStorage, Regs[701]) - 65 * sizeof(MCRegisterClass),
2698 offsetof(X86RegisterClassStorage, BitSets[1302]) - 65 * sizeof(MCRegisterClass),
2699 .NameIdx: 1113,
2700 .RegSizeInBits: 32,
2701 .RegsSize: 1,
2702 .RegSetSize: 3,
2703 .ID: X86::GR32_BPSP_and_GR32_DIBPRegClassID,
2704 .CopyCost: 1, /* CopyCost */
2705 .Allocatable: true, /* Allocatable */
2706 .BaseClass: false,
2707 offsetof(X86RegisterClassStorage, SubClassMasks[650]) - 65 * sizeof(MCRegisterClass),
2708 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 65 * sizeof(MCRegisterClass),
2709 .LaneMask: LaneBitmask(0x000000000000000F),
2710 .AllocationPriority: 0,
2711 .GlobalPriority: false,
2712 .TSFlags: 0x00, /* TSFlags */
2713 .SpillStackID: 0, /* SpillStackID */
2714 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2715 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2716 offsetof(X86RegisterClassStorage, SuperClasses[346]) - 65 * sizeof(MCRegisterClass),
2717 .SuperClassesSize: 13
2718 },
2719 {
2720 offsetof(X86RegisterClassStorage, Regs[702]) - 66 * sizeof(MCRegisterClass),
2721 offsetof(X86RegisterClassStorage, BitSets[1305]) - 66 * sizeof(MCRegisterClass),
2722 .NameIdx: 539,
2723 .RegSizeInBits: 32,
2724 .RegsSize: 1,
2725 .RegSetSize: 5,
2726 .ID: X86::GR32_BPSP_and_GR32_TCRegClassID,
2727 .CopyCost: 1, /* CopyCost */
2728 .Allocatable: true, /* Allocatable */
2729 .BaseClass: false,
2730 offsetof(X86RegisterClassStorage, SubClassMasks[660]) - 66 * sizeof(MCRegisterClass),
2731 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 66 * sizeof(MCRegisterClass),
2732 .LaneMask: LaneBitmask(0x000000000000000F),
2733 .AllocationPriority: 0,
2734 .GlobalPriority: false,
2735 .TSFlags: 0x00, /* TSFlags */
2736 .SpillStackID: 0, /* SpillStackID */
2737 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2738 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2739 offsetof(X86RegisterClassStorage, SuperClasses[359]) - 66 * sizeof(MCRegisterClass),
2740 .SuperClassesSize: 10
2741 },
2742 {
2743 offsetof(X86RegisterClassStorage, Regs[703]) - 67 * sizeof(MCRegisterClass),
2744 offsetof(X86RegisterClassStorage, BitSets[1310]) - 67 * sizeof(MCRegisterClass),
2745 .NameIdx: 826,
2746 .RegSizeInBits: 32,
2747 .RegsSize: 1,
2748 .RegSetSize: 5,
2749 .ID: X86::GR32_BSI_and_GR32_SIDIRegClassID,
2750 .CopyCost: 1, /* CopyCost */
2751 .Allocatable: true, /* Allocatable */
2752 .BaseClass: false,
2753 offsetof(X86RegisterClassStorage, SubClassMasks[670]) - 67 * sizeof(MCRegisterClass),
2754 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 67 * sizeof(MCRegisterClass),
2755 .LaneMask: LaneBitmask(0x000000000000000F),
2756 .AllocationPriority: 0,
2757 .GlobalPriority: false,
2758 .TSFlags: 0x00, /* TSFlags */
2759 .SpillStackID: 0, /* SpillStackID */
2760 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2761 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2762 offsetof(X86RegisterClassStorage, SuperClasses[369]) - 67 * sizeof(MCRegisterClass),
2763 .SuperClassesSize: 13
2764 },
2765 {
2766 offsetof(X86RegisterClassStorage, Regs[704]) - 68 * sizeof(MCRegisterClass),
2767 offsetof(X86RegisterClassStorage, BitSets[1315]) - 68 * sizeof(MCRegisterClass),
2768 .NameIdx: 872,
2769 .RegSizeInBits: 32,
2770 .RegsSize: 1,
2771 .RegSetSize: 4,
2772 .ID: X86::GR32_DIBP_and_GR32_SIDIRegClassID,
2773 .CopyCost: 1, /* CopyCost */
2774 .Allocatable: true, /* Allocatable */
2775 .BaseClass: false,
2776 offsetof(X86RegisterClassStorage, SubClassMasks[680]) - 68 * sizeof(MCRegisterClass),
2777 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 68 * sizeof(MCRegisterClass),
2778 .LaneMask: LaneBitmask(0x000000000000000F),
2779 .AllocationPriority: 0,
2780 .GlobalPriority: false,
2781 .TSFlags: 0x00, /* TSFlags */
2782 .SpillStackID: 0, /* SpillStackID */
2783 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2784 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2785 offsetof(X86RegisterClassStorage, SuperClasses[382]) - 68 * sizeof(MCRegisterClass),
2786 .SuperClassesSize: 13
2787 },
2788 {
2789 offsetof(X86RegisterClassStorage, Regs[705]) - 69 * sizeof(MCRegisterClass),
2790 offsetof(X86RegisterClassStorage, BitSets[1319]) - 69 * sizeof(MCRegisterClass),
2791 .NameIdx: 1741,
2792 .RegSizeInBits: 32,
2793 .RegsSize: 1,
2794 .RegSetSize: 7,
2795 .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID,
2796 .CopyCost: 1, /* CopyCost */
2797 .Allocatable: true, /* Allocatable */
2798 .BaseClass: false,
2799 offsetof(X86RegisterClassStorage, SubClassMasks[690]) - 69 * sizeof(MCRegisterClass),
2800 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 69 * sizeof(MCRegisterClass),
2801 .LaneMask: LaneBitmask(0x000000000000000F),
2802 .AllocationPriority: 0,
2803 .GlobalPriority: false,
2804 .TSFlags: 0x00, /* TSFlags */
2805 .SpillStackID: 0, /* SpillStackID */
2806 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2807 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2808 offsetof(X86RegisterClassStorage, SuperClasses[395]) - 69 * sizeof(MCRegisterClass),
2809 .SuperClassesSize: 5
2810 },
2811 {
2812 offsetof(X86RegisterClassStorage, Regs[706]) - 70 * sizeof(MCRegisterClass),
2813 offsetof(X86RegisterClassStorage, BitSets[1326]) - 70 * sizeof(MCRegisterClass),
2814 .NameIdx: 1708,
2815 .RegSizeInBits: 32,
2816 .RegsSize: 1,
2817 .RegSetSize: 8,
2818 .ID: X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID,
2819 .CopyCost: 1, /* CopyCost */
2820 .Allocatable: true, /* Allocatable */
2821 .BaseClass: false,
2822 offsetof(X86RegisterClassStorage, SubClassMasks[695]) - 70 * sizeof(MCRegisterClass),
2823 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 70 * sizeof(MCRegisterClass),
2824 .LaneMask: LaneBitmask(0x000000000000000F),
2825 .AllocationPriority: 0,
2826 .GlobalPriority: false,
2827 .TSFlags: 0x00, /* TSFlags */
2828 .SpillStackID: 0, /* SpillStackID */
2829 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2830 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2831 offsetof(X86RegisterClassStorage, SuperClasses[400]) - 70 * sizeof(MCRegisterClass),
2832 .SuperClassesSize: 3
2833 },
2834 {
2835 offsetof(X86RegisterClassStorage, Regs[707]) - 71 * sizeof(MCRegisterClass),
2836 offsetof(X86RegisterClassStorage, BitSets[1334]) - 71 * sizeof(MCRegisterClass),
2837 .NameIdx: 168,
2838 .RegSizeInBits: 64,
2839 .RegsSize: 7,
2840 .RegSetSize: 14,
2841 .ID: X86::RFP64RegClassID,
2842 .CopyCost: 1, /* CopyCost */
2843 .Allocatable: true, /* Allocatable */
2844 .BaseClass: false,
2845 offsetof(X86RegisterClassStorage, SubClassMasks[700]) - 71 * sizeof(MCRegisterClass),
2846 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 71 * sizeof(MCRegisterClass),
2847 .LaneMask: LaneBitmask(0x0000000000000001),
2848 .AllocationPriority: 0,
2849 .GlobalPriority: false,
2850 .TSFlags: 0x00, /* TSFlags */
2851 .SpillStackID: 0, /* SpillStackID */
2852 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2853 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2854 offsetof(X86RegisterClassStorage, SuperClasses[403]) - 71 * sizeof(MCRegisterClass),
2855 .SuperClassesSize: 1
2856 },
2857 {
2858 offsetof(X86RegisterClassStorage, Regs[714]) - 72 * sizeof(MCRegisterClass),
2859 offsetof(X86RegisterClassStorage, BitSets[1348]) - 72 * sizeof(MCRegisterClass),
2860 .NameIdx: 179,
2861 .RegSizeInBits: 64,
2862 .RegsSize: 33,
2863 .RegSetSize: 39,
2864 .ID: X86::GR64RegClassID,
2865 .CopyCost: 1, /* CopyCost */
2866 .Allocatable: true, /* Allocatable */
2867 .BaseClass: false,
2868 offsetof(X86RegisterClassStorage, SubClassMasks[705]) - 72 * sizeof(MCRegisterClass),
2869 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 72 * sizeof(MCRegisterClass),
2870 .LaneMask: LaneBitmask(0x000000000000000F),
2871 .AllocationPriority: 0,
2872 .GlobalPriority: false,
2873 .TSFlags: 0x00, /* TSFlags */
2874 .SpillStackID: 0, /* SpillStackID */
2875 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2876 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2877 offsetof(X86RegisterClassStorage, SuperClasses[404]) - 72 * sizeof(MCRegisterClass),
2878 .SuperClassesSize: 0
2879 },
2880 {
2881 offsetof(X86RegisterClassStorage, Regs[747]) - 73 * sizeof(MCRegisterClass),
2882 offsetof(X86RegisterClassStorage, BitSets[1387]) - 73 * sizeof(MCRegisterClass),
2883 .NameIdx: 1410,
2884 .RegSizeInBits: 64,
2885 .RegsSize: 32,
2886 .RegSetSize: 29,
2887 .ID: X86::FR64XRegClassID,
2888 .CopyCost: 1, /* CopyCost */
2889 .Allocatable: true, /* Allocatable */
2890 .BaseClass: false,
2891 offsetof(X86RegisterClassStorage, SubClassMasks[710]) - 73 * sizeof(MCRegisterClass),
2892 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 73 * sizeof(MCRegisterClass),
2893 .LaneMask: LaneBitmask(0x0000000000000001),
2894 .AllocationPriority: 0,
2895 .GlobalPriority: false,
2896 .TSFlags: 0x00, /* TSFlags */
2897 .SpillStackID: 0, /* SpillStackID */
2898 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2899 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2900 offsetof(X86RegisterClassStorage, SuperClasses[404]) - 73 * sizeof(MCRegisterClass),
2901 .SuperClassesSize: 2
2902 },
2903 {
2904 offsetof(X86RegisterClassStorage, Regs[779]) - 74 * sizeof(MCRegisterClass),
2905 offsetof(X86RegisterClassStorage, BitSets[1416]) - 74 * sizeof(MCRegisterClass),
2906 .NameIdx: 1792,
2907 .RegSizeInBits: 64,
2908 .RegsSize: 32,
2909 .RegSetSize: 39,
2910 .ID: X86::GR64_with_sub_8bitRegClassID,
2911 .CopyCost: 1, /* CopyCost */
2912 .Allocatable: true, /* Allocatable */
2913 .BaseClass: false,
2914 offsetof(X86RegisterClassStorage, SubClassMasks[720]) - 74 * sizeof(MCRegisterClass),
2915 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 74 * sizeof(MCRegisterClass),
2916 .LaneMask: LaneBitmask(0x000000000000000F),
2917 .AllocationPriority: 0,
2918 .GlobalPriority: false,
2919 .TSFlags: 0x00, /* TSFlags */
2920 .SpillStackID: 0, /* SpillStackID */
2921 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2922 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2923 offsetof(X86RegisterClassStorage, SuperClasses[406]) - 74 * sizeof(MCRegisterClass),
2924 .SuperClassesSize: 1
2925 },
2926 {
2927 offsetof(X86RegisterClassStorage, Regs[811]) - 75 * sizeof(MCRegisterClass),
2928 offsetof(X86RegisterClassStorage, BitSets[1455]) - 75 * sizeof(MCRegisterClass),
2929 .NameIdx: 1245,
2930 .RegSizeInBits: 64,
2931 .RegsSize: 31,
2932 .RegSetSize: 39,
2933 .ID: X86::GR64_NOSPRegClassID,
2934 .CopyCost: 1, /* CopyCost */
2935 .Allocatable: true, /* Allocatable */
2936 .BaseClass: false,
2937 offsetof(X86RegisterClassStorage, SubClassMasks[725]) - 75 * sizeof(MCRegisterClass),
2938 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 75 * sizeof(MCRegisterClass),
2939 .LaneMask: LaneBitmask(0x000000000000000F),
2940 .AllocationPriority: 0,
2941 .GlobalPriority: false,
2942 .TSFlags: 0x00, /* TSFlags */
2943 .SpillStackID: 0, /* SpillStackID */
2944 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2945 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2946 offsetof(X86RegisterClassStorage, SuperClasses[407]) - 75 * sizeof(MCRegisterClass),
2947 .SuperClassesSize: 2
2948 },
2949 {
2950 offsetof(X86RegisterClassStorage, Regs[842]) - 76 * sizeof(MCRegisterClass),
2951 offsetof(X86RegisterClassStorage, BitSets[1494]) - 76 * sizeof(MCRegisterClass),
2952 .NameIdx: 53,
2953 .RegSizeInBits: 64,
2954 .RegsSize: 17,
2955 .RegSetSize: 16,
2956 .ID: X86::GR64_NOREX2RegClassID,
2957 .CopyCost: 1, /* CopyCost */
2958 .Allocatable: true, /* Allocatable */
2959 .BaseClass: false,
2960 offsetof(X86RegisterClassStorage, SubClassMasks[730]) - 76 * sizeof(MCRegisterClass),
2961 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 76 * sizeof(MCRegisterClass),
2962 .LaneMask: LaneBitmask(0x000000000000000F),
2963 .AllocationPriority: 0,
2964 .GlobalPriority: false,
2965 .TSFlags: 0x00, /* TSFlags */
2966 .SpillStackID: 0, /* SpillStackID */
2967 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2968 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2969 offsetof(X86RegisterClassStorage, SuperClasses[409]) - 76 * sizeof(MCRegisterClass),
2970 .SuperClassesSize: 1
2971 },
2972 {
2973 offsetof(X86RegisterClassStorage, Regs[859]) - 77 * sizeof(MCRegisterClass),
2974 offsetof(X86RegisterClassStorage, BitSets[1510]) - 77 * sizeof(MCRegisterClass),
2975 .NameIdx: 768,
2976 .RegSizeInBits: 64,
2977 .RegsSize: 16,
2978 .RegSetSize: 11,
2979 .ID: X86::CONTROL_REGRegClassID,
2980 .CopyCost: 1, /* CopyCost */
2981 .Allocatable: true, /* Allocatable */
2982 .BaseClass: false,
2983 offsetof(X86RegisterClassStorage, SubClassMasks[735]) - 77 * sizeof(MCRegisterClass),
2984 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 77 * sizeof(MCRegisterClass),
2985 .LaneMask: LaneBitmask(0x0000000000000001),
2986 .AllocationPriority: 0,
2987 .GlobalPriority: false,
2988 .TSFlags: 0x00, /* TSFlags */
2989 .SpillStackID: 0, /* SpillStackID */
2990 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2991 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2992 offsetof(X86RegisterClassStorage, SuperClasses[410]) - 77 * sizeof(MCRegisterClass),
2993 .SuperClassesSize: 0
2994 },
2995 {
2996 offsetof(X86RegisterClassStorage, Regs[875]) - 78 * sizeof(MCRegisterClass),
2997 offsetof(X86RegisterClassStorage, BitSets[1521]) - 78 * sizeof(MCRegisterClass),
2998 .NameIdx: 174,
2999 .RegSizeInBits: 64,
3000 .RegsSize: 16,
3001 .RegSetSize: 19,
3002 .ID: X86::FR64RegClassID,
3003 .CopyCost: 1, /* CopyCost */
3004 .Allocatable: true, /* Allocatable */
3005 .BaseClass: false,
3006 offsetof(X86RegisterClassStorage, SubClassMasks[740]) - 78 * sizeof(MCRegisterClass),
3007 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 78 * sizeof(MCRegisterClass),
3008 .LaneMask: LaneBitmask(0x0000000000000001),
3009 .AllocationPriority: 0,
3010 .GlobalPriority: false,
3011 .TSFlags: 0x00, /* TSFlags */
3012 .SpillStackID: 0, /* SpillStackID */
3013 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3014 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3015 offsetof(X86RegisterClassStorage, SuperClasses[410]) - 78 * sizeof(MCRegisterClass),
3016 .SuperClassesSize: 5
3017 },
3018 {
3019 offsetof(X86RegisterClassStorage, Regs[891]) - 79 * sizeof(MCRegisterClass),
3020 offsetof(X86RegisterClassStorage, BitSets[1540]) - 79 * sizeof(MCRegisterClass),
3021 .NameIdx: 65,
3022 .RegSizeInBits: 64,
3023 .RegsSize: 16,
3024 .RegSetSize: 16,
3025 .ID: X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
3026 .CopyCost: 1, /* CopyCost */
3027 .Allocatable: true, /* Allocatable */
3028 .BaseClass: false,
3029 offsetof(X86RegisterClassStorage, SubClassMasks[750]) - 79 * sizeof(MCRegisterClass),
3030 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 79 * sizeof(MCRegisterClass),
3031 .LaneMask: LaneBitmask(0x000000000000000F),
3032 .AllocationPriority: 0,
3033 .GlobalPriority: false,
3034 .TSFlags: 0x00, /* TSFlags */
3035 .SpillStackID: 0, /* SpillStackID */
3036 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3037 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3038 offsetof(X86RegisterClassStorage, SuperClasses[415]) - 79 * sizeof(MCRegisterClass),
3039 .SuperClassesSize: 3
3040 },
3041 {
3042 offsetof(X86RegisterClassStorage, Regs[907]) - 80 * sizeof(MCRegisterClass),
3043 offsetof(X86RegisterClassStorage, BitSets[1556]) - 80 * sizeof(MCRegisterClass),
3044 .NameIdx: 1228,
3045 .RegSizeInBits: 64,
3046 .RegsSize: 15,
3047 .RegSetSize: 16,
3048 .ID: X86::GR64_NOREX2_NOSPRegClassID,
3049 .CopyCost: 1, /* CopyCost */
3050 .Allocatable: true, /* Allocatable */
3051 .BaseClass: false,
3052 offsetof(X86RegisterClassStorage, SubClassMasks[755]) - 80 * sizeof(MCRegisterClass),
3053 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 80 * sizeof(MCRegisterClass),
3054 .LaneMask: LaneBitmask(0x000000000000000F),
3055 .AllocationPriority: 0,
3056 .GlobalPriority: false,
3057 .TSFlags: 0x00, /* TSFlags */
3058 .SpillStackID: 0, /* SpillStackID */
3059 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3060 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3061 offsetof(X86RegisterClassStorage, SuperClasses[418]) - 80 * sizeof(MCRegisterClass),
3062 .SuperClassesSize: 5
3063 },
3064 {
3065 offsetof(X86RegisterClassStorage, Regs[922]) - 81 * sizeof(MCRegisterClass),
3066 offsetof(X86RegisterClassStorage, BitSets[1572]) - 81 * sizeof(MCRegisterClass),
3067 .NameIdx: 1565,
3068 .RegSizeInBits: 64,
3069 .RegsSize: 13,
3070 .RegSetSize: 16,
3071 .ID: X86::GR64PLTSafeRegClassID,
3072 .CopyCost: 1, /* CopyCost */
3073 .Allocatable: true, /* Allocatable */
3074 .BaseClass: false,
3075 offsetof(X86RegisterClassStorage, SubClassMasks[760]) - 81 * sizeof(MCRegisterClass),
3076 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 81 * sizeof(MCRegisterClass),
3077 .LaneMask: LaneBitmask(0x000000000000000F),
3078 .AllocationPriority: 0,
3079 .GlobalPriority: false,
3080 .TSFlags: 0x00, /* TSFlags */
3081 .SpillStackID: 0, /* SpillStackID */
3082 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3083 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3084 offsetof(X86RegisterClassStorage, SuperClasses[423]) - 81 * sizeof(MCRegisterClass),
3085 .SuperClassesSize: 6
3086 },
3087 {
3088 offsetof(X86RegisterClassStorage, Regs[935]) - 82 * sizeof(MCRegisterClass),
3089 offsetof(X86RegisterClassStorage, BitSets[1588]) - 82 * sizeof(MCRegisterClass),
3090 .NameIdx: 613,
3091 .RegSizeInBits: 64,
3092 .RegsSize: 10,
3093 .RegSetSize: 16,
3094 .ID: X86::GR64_TCRegClassID,
3095 .CopyCost: 1, /* CopyCost */
3096 .Allocatable: true, /* Allocatable */
3097 .BaseClass: false,
3098 offsetof(X86RegisterClassStorage, SubClassMasks[765]) - 82 * sizeof(MCRegisterClass),
3099 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 82 * sizeof(MCRegisterClass),
3100 .LaneMask: LaneBitmask(0x000000000000000F),
3101 .AllocationPriority: 0,
3102 .GlobalPriority: false,
3103 .TSFlags: 0x00, /* TSFlags */
3104 .SpillStackID: 0, /* SpillStackID */
3105 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3106 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3107 offsetof(X86RegisterClassStorage, SuperClasses[429]) - 82 * sizeof(MCRegisterClass),
3108 .SuperClassesSize: 2
3109 },
3110 {
3111 offsetof(X86RegisterClassStorage, Regs[945]) - 83 * sizeof(MCRegisterClass),
3112 offsetof(X86RegisterClassStorage, BitSets[1604]) - 83 * sizeof(MCRegisterClass),
3113 .NameIdx: 1447,
3114 .RegSizeInBits: 64,
3115 .RegsSize: 9,
3116 .RegSetSize: 8,
3117 .ID: X86::GR64_NOREXRegClassID,
3118 .CopyCost: 1, /* CopyCost */
3119 .Allocatable: true, /* Allocatable */
3120 .BaseClass: false,
3121 offsetof(X86RegisterClassStorage, SubClassMasks[770]) - 83 * sizeof(MCRegisterClass),
3122 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 83 * sizeof(MCRegisterClass),
3123 .LaneMask: LaneBitmask(0x000000000000000F),
3124 .AllocationPriority: 0,
3125 .GlobalPriority: false,
3126 .TSFlags: 0x00, /* TSFlags */
3127 .SpillStackID: 0, /* SpillStackID */
3128 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3129 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3130 offsetof(X86RegisterClassStorage, SuperClasses[431]) - 83 * sizeof(MCRegisterClass),
3131 .SuperClassesSize: 2
3132 },
3133 {
3134 offsetof(X86RegisterClassStorage, Regs[954]) - 84 * sizeof(MCRegisterClass),
3135 offsetof(X86RegisterClassStorage, BitSets[1612]) - 84 * sizeof(MCRegisterClass),
3136 .NameIdx: 201,
3137 .RegSizeInBits: 64,
3138 .RegsSize: 9,
3139 .RegSetSize: 16,
3140 .ID: X86::GR64_TCW64RegClassID,
3141 .CopyCost: 1, /* CopyCost */
3142 .Allocatable: true, /* Allocatable */
3143 .BaseClass: false,
3144 offsetof(X86RegisterClassStorage, SubClassMasks[775]) - 84 * sizeof(MCRegisterClass),
3145 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 84 * sizeof(MCRegisterClass),
3146 .LaneMask: LaneBitmask(0x000000000000000F),
3147 .AllocationPriority: 0,
3148 .GlobalPriority: false,
3149 .TSFlags: 0x00, /* TSFlags */
3150 .SpillStackID: 0, /* SpillStackID */
3151 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3152 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3153 offsetof(X86RegisterClassStorage, SuperClasses[433]) - 84 * sizeof(MCRegisterClass),
3154 .SuperClassesSize: 2
3155 },
3156 {
3157 offsetof(X86RegisterClassStorage, Regs[963]) - 85 * sizeof(MCRegisterClass),
3158 offsetof(X86RegisterClassStorage, BitSets[1628]) - 85 * sizeof(MCRegisterClass),
3159 .NameIdx: 1851,
3160 .RegSizeInBits: 64,
3161 .RegsSize: 9,
3162 .RegSetSize: 16,
3163 .ID: X86::GR64_TC_with_sub_8bitRegClassID,
3164 .CopyCost: 1, /* CopyCost */
3165 .Allocatable: true, /* Allocatable */
3166 .BaseClass: false,
3167 offsetof(X86RegisterClassStorage, SubClassMasks[780]) - 85 * sizeof(MCRegisterClass),
3168 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 85 * sizeof(MCRegisterClass),
3169 .LaneMask: LaneBitmask(0x000000000000000F),
3170 .AllocationPriority: 0,
3171 .GlobalPriority: false,
3172 .TSFlags: 0x00, /* TSFlags */
3173 .SpillStackID: 0, /* SpillStackID */
3174 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3175 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3176 offsetof(X86RegisterClassStorage, SuperClasses[435]) - 85 * sizeof(MCRegisterClass),
3177 .SuperClassesSize: 5
3178 },
3179 {
3180 offsetof(X86RegisterClassStorage, Regs[972]) - 86 * sizeof(MCRegisterClass),
3181 offsetof(X86RegisterClassStorage, BitSets[1644]) - 86 * sizeof(MCRegisterClass),
3182 .NameIdx: 592,
3183 .RegSizeInBits: 64,
3184 .RegsSize: 8,
3185 .RegSetSize: 16,
3186 .ID: X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
3187 .CopyCost: 1, /* CopyCost */
3188 .Allocatable: true, /* Allocatable */
3189 .BaseClass: false,
3190 offsetof(X86RegisterClassStorage, SubClassMasks[785]) - 86 * sizeof(MCRegisterClass),
3191 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 86 * sizeof(MCRegisterClass),
3192 .LaneMask: LaneBitmask(0x000000000000000F),
3193 .AllocationPriority: 0,
3194 .GlobalPriority: false,
3195 .TSFlags: 0x00, /* TSFlags */
3196 .SpillStackID: 0, /* SpillStackID */
3197 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3198 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3199 offsetof(X86RegisterClassStorage, SuperClasses[440]) - 86 * sizeof(MCRegisterClass),
3200 .SuperClassesSize: 8
3201 },
3202 {
3203 offsetof(X86RegisterClassStorage, Regs[980]) - 87 * sizeof(MCRegisterClass),
3204 offsetof(X86RegisterClassStorage, BitSets[1660]) - 87 * sizeof(MCRegisterClass),
3205 .NameIdx: 1811,
3206 .RegSizeInBits: 64,
3207 .RegsSize: 8,
3208 .RegSetSize: 16,
3209 .ID: X86::GR64_TCW64_with_sub_8bitRegClassID,
3210 .CopyCost: 1, /* CopyCost */
3211 .Allocatable: true, /* Allocatable */
3212 .BaseClass: false,
3213 offsetof(X86RegisterClassStorage, SubClassMasks[790]) - 87 * sizeof(MCRegisterClass),
3214 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 87 * sizeof(MCRegisterClass),
3215 .LaneMask: LaneBitmask(0x000000000000000F),
3216 .AllocationPriority: 0,
3217 .GlobalPriority: false,
3218 .TSFlags: 0x00, /* TSFlags */
3219 .SpillStackID: 0, /* SpillStackID */
3220 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3221 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3222 offsetof(X86RegisterClassStorage, SuperClasses[448]) - 87 * sizeof(MCRegisterClass),
3223 .SuperClassesSize: 5
3224 },
3225 {
3226 offsetof(X86RegisterClassStorage, Regs[988]) - 88 * sizeof(MCRegisterClass),
3227 offsetof(X86RegisterClassStorage, BitSets[1676]) - 88 * sizeof(MCRegisterClass),
3228 .NameIdx: 189,
3229 .RegSizeInBits: 64,
3230 .RegsSize: 8,
3231 .RegSetSize: 16,
3232 .ID: X86::GR64_TC_and_GR64_TCW64RegClassID,
3233 .CopyCost: 1, /* CopyCost */
3234 .Allocatable: true, /* Allocatable */
3235 .BaseClass: false,
3236 offsetof(X86RegisterClassStorage, SubClassMasks[795]) - 88 * sizeof(MCRegisterClass),
3237 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 88 * sizeof(MCRegisterClass),
3238 .LaneMask: LaneBitmask(0x000000000000000F),
3239 .AllocationPriority: 0,
3240 .GlobalPriority: false,
3241 .TSFlags: 0x00, /* TSFlags */
3242 .SpillStackID: 0, /* SpillStackID */
3243 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3244 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3245 offsetof(X86RegisterClassStorage, SuperClasses[453]) - 88 * sizeof(MCRegisterClass),
3246 .SuperClassesSize: 4
3247 },
3248 {
3249 offsetof(X86RegisterClassStorage, Regs[996]) - 89 * sizeof(MCRegisterClass),
3250 offsetof(X86RegisterClassStorage, BitSets[1692]) - 89 * sizeof(MCRegisterClass),
3251 .NameIdx: 1470,
3252 .RegSizeInBits: 64,
3253 .RegsSize: 8,
3254 .RegSetSize: 8,
3255 .ID: X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
3256 .CopyCost: 1, /* CopyCost */
3257 .Allocatable: true, /* Allocatable */
3258 .BaseClass: false,
3259 offsetof(X86RegisterClassStorage, SubClassMasks[800]) - 89 * sizeof(MCRegisterClass),
3260 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 89 * sizeof(MCRegisterClass),
3261 .LaneMask: LaneBitmask(0x000000000000000F),
3262 .AllocationPriority: 0,
3263 .GlobalPriority: false,
3264 .TSFlags: 0x00, /* TSFlags */
3265 .SpillStackID: 0, /* SpillStackID */
3266 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3267 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3268 offsetof(X86RegisterClassStorage, SuperClasses[457]) - 89 * sizeof(MCRegisterClass),
3269 .SuperClassesSize: 5
3270 },
3271 {
3272 offsetof(X86RegisterClassStorage, Regs[1004]) - 90 * sizeof(MCRegisterClass),
3273 offsetof(X86RegisterClassStorage, BitSets[1700]) - 90 * sizeof(MCRegisterClass),
3274 .NameIdx: 163,
3275 .RegSizeInBits: 64,
3276 .RegsSize: 8,
3277 .RegSetSize: 27,
3278 .ID: X86::VK64RegClassID,
3279 .CopyCost: 1, /* CopyCost */
3280 .Allocatable: true, /* Allocatable */
3281 .BaseClass: false,
3282 offsetof(X86RegisterClassStorage, SubClassMasks[805]) - 90 * sizeof(MCRegisterClass),
3283 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 90 * sizeof(MCRegisterClass),
3284 .LaneMask: LaneBitmask(0x0000000000000001),
3285 .AllocationPriority: 0,
3286 .GlobalPriority: false,
3287 .TSFlags: 0x00, /* TSFlags */
3288 .SpillStackID: 0, /* SpillStackID */
3289 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3290 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3291 offsetof(X86RegisterClassStorage, SuperClasses[462]) - 90 * sizeof(MCRegisterClass),
3292 .SuperClassesSize: 6
3293 },
3294 {
3295 offsetof(X86RegisterClassStorage, Regs[1012]) - 91 * sizeof(MCRegisterClass),
3296 offsetof(X86RegisterClassStorage, BitSets[1727]) - 91 * sizeof(MCRegisterClass),
3297 .NameIdx: 184,
3298 .RegSizeInBits: 64,
3299 .RegsSize: 8,
3300 .RegSetSize: 15,
3301 .ID: X86::VR64RegClassID,
3302 .CopyCost: 1, /* CopyCost */
3303 .Allocatable: true, /* Allocatable */
3304 .BaseClass: false,
3305 offsetof(X86RegisterClassStorage, SubClassMasks[820]) - 91 * sizeof(MCRegisterClass),
3306 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 91 * sizeof(MCRegisterClass),
3307 .LaneMask: LaneBitmask(0x0000000000000001),
3308 .AllocationPriority: 0,
3309 .GlobalPriority: false,
3310 .TSFlags: 0x00, /* TSFlags */
3311 .SpillStackID: 0, /* SpillStackID */
3312 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3313 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3314 offsetof(X86RegisterClassStorage, SuperClasses[468]) - 91 * sizeof(MCRegisterClass),
3315 .SuperClassesSize: 0
3316 },
3317 {
3318 offsetof(X86RegisterClassStorage, Regs[1020]) - 92 * sizeof(MCRegisterClass),
3319 offsetof(X86RegisterClassStorage, BitSets[1742]) - 92 * sizeof(MCRegisterClass),
3320 .NameIdx: 659,
3321 .RegSizeInBits: 64,
3322 .RegsSize: 7,
3323 .RegSetSize: 16,
3324 .ID: X86::GR64PLTSafe_and_GR64_TCRegClassID,
3325 .CopyCost: 1, /* CopyCost */
3326 .Allocatable: true, /* Allocatable */
3327 .BaseClass: false,
3328 offsetof(X86RegisterClassStorage, SubClassMasks[825]) - 92 * sizeof(MCRegisterClass),
3329 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 92 * sizeof(MCRegisterClass),
3330 .LaneMask: LaneBitmask(0x000000000000000F),
3331 .AllocationPriority: 0,
3332 .GlobalPriority: false,
3333 .TSFlags: 0x00, /* TSFlags */
3334 .SpillStackID: 0, /* SpillStackID */
3335 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3336 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3337 offsetof(X86RegisterClassStorage, SuperClasses[468]) - 92 * sizeof(MCRegisterClass),
3338 .SuperClassesSize: 10
3339 },
3340 {
3341 offsetof(X86RegisterClassStorage, Regs[1027]) - 93 * sizeof(MCRegisterClass),
3342 offsetof(X86RegisterClassStorage, BitSets[1758]) - 93 * sizeof(MCRegisterClass),
3343 .NameIdx: 224,
3344 .RegSizeInBits: 64,
3345 .RegsSize: 7,
3346 .RegSetSize: 16,
3347 .ID: X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
3348 .CopyCost: 1, /* CopyCost */
3349 .Allocatable: true, /* Allocatable */
3350 .BaseClass: false,
3351 offsetof(X86RegisterClassStorage, SubClassMasks[830]) - 93 * sizeof(MCRegisterClass),
3352 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 93 * sizeof(MCRegisterClass),
3353 .LaneMask: LaneBitmask(0x000000000000000F),
3354 .AllocationPriority: 0,
3355 .GlobalPriority: false,
3356 .TSFlags: 0x00, /* TSFlags */
3357 .SpillStackID: 0, /* SpillStackID */
3358 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3359 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3360 offsetof(X86RegisterClassStorage, SuperClasses[478]) - 93 * sizeof(MCRegisterClass),
3361 .SuperClassesSize: 8
3362 },
3363 {
3364 offsetof(X86RegisterClassStorage, Regs[1034]) - 94 * sizeof(MCRegisterClass),
3365 offsetof(X86RegisterClassStorage, BitSets[1774]) - 94 * sizeof(MCRegisterClass),
3366 .NameIdx: 1271,
3367 .RegSizeInBits: 64,
3368 .RegsSize: 7,
3369 .RegSetSize: 8,
3370 .ID: X86::GR64_NOREX_NOSPRegClassID,
3371 .CopyCost: 1, /* CopyCost */
3372 .Allocatable: true, /* Allocatable */
3373 .BaseClass: false,
3374 offsetof(X86RegisterClassStorage, SubClassMasks[835]) - 94 * sizeof(MCRegisterClass),
3375 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 94 * sizeof(MCRegisterClass),
3376 .LaneMask: LaneBitmask(0x000000000000000F),
3377 .AllocationPriority: 0,
3378 .GlobalPriority: false,
3379 .TSFlags: 0x00, /* TSFlags */
3380 .SpillStackID: 0, /* SpillStackID */
3381 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3382 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3383 offsetof(X86RegisterClassStorage, SuperClasses[486]) - 94 * sizeof(MCRegisterClass),
3384 .SuperClassesSize: 9
3385 },
3386 {
3387 offsetof(X86RegisterClassStorage, Regs[1041]) - 95 * sizeof(MCRegisterClass),
3388 offsetof(X86RegisterClassStorage, BitSets[1782]) - 95 * sizeof(MCRegisterClass),
3389 .NameIdx: 621,
3390 .RegSizeInBits: 64,
3391 .RegsSize: 7,
3392 .RegSetSize: 8,
3393 .ID: X86::GR64_NOREX_and_GR64_TCRegClassID,
3394 .CopyCost: 1, /* CopyCost */
3395 .Allocatable: true, /* Allocatable */
3396 .BaseClass: false,
3397 offsetof(X86RegisterClassStorage, SubClassMasks[840]) - 95 * sizeof(MCRegisterClass),
3398 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 95 * sizeof(MCRegisterClass),
3399 .LaneMask: LaneBitmask(0x000000000000000F),
3400 .AllocationPriority: 0,
3401 .GlobalPriority: false,
3402 .TSFlags: 0x00, /* TSFlags */
3403 .SpillStackID: 0, /* SpillStackID */
3404 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3405 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3406 offsetof(X86RegisterClassStorage, SuperClasses[495]) - 95 * sizeof(MCRegisterClass),
3407 .SuperClassesSize: 4
3408 },
3409 {
3410 offsetof(X86RegisterClassStorage, Regs[1048]) - 96 * sizeof(MCRegisterClass),
3411 offsetof(X86RegisterClassStorage, BitSets[1790]) - 96 * sizeof(MCRegisterClass),
3412 .NameIdx: 1836,
3413 .RegSizeInBits: 64,
3414 .RegsSize: 7,
3415 .RegSetSize: 16,
3416 .ID: X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
3417 .CopyCost: 1, /* CopyCost */
3418 .Allocatable: true, /* Allocatable */
3419 .BaseClass: false,
3420 offsetof(X86RegisterClassStorage, SubClassMasks[845]) - 96 * sizeof(MCRegisterClass),
3421 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 96 * sizeof(MCRegisterClass),
3422 .LaneMask: LaneBitmask(0x000000000000000F),
3423 .AllocationPriority: 0,
3424 .GlobalPriority: false,
3425 .TSFlags: 0x00, /* TSFlags */
3426 .SpillStackID: 0, /* SpillStackID */
3427 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3428 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3429 offsetof(X86RegisterClassStorage, SuperClasses[499]) - 96 * sizeof(MCRegisterClass),
3430 .SuperClassesSize: 9
3431 },
3432 {
3433 offsetof(X86RegisterClassStorage, Regs[1055]) - 97 * sizeof(MCRegisterClass),
3434 offsetof(X86RegisterClassStorage, BitSets[1806]) - 97 * sizeof(MCRegisterClass),
3435 .NameIdx: 1064,
3436 .RegSizeInBits: 64,
3437 .RegsSize: 7,
3438 .RegSetSize: 27,
3439 .ID: X86::VK64WMRegClassID,
3440 .CopyCost: 1, /* CopyCost */
3441 .Allocatable: true, /* Allocatable */
3442 .BaseClass: false,
3443 offsetof(X86RegisterClassStorage, SubClassMasks[850]) - 97 * sizeof(MCRegisterClass),
3444 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 97 * sizeof(MCRegisterClass),
3445 .LaneMask: LaneBitmask(0x0000000000000001),
3446 .AllocationPriority: 0,
3447 .GlobalPriority: false,
3448 .TSFlags: 0x00, /* TSFlags */
3449 .SpillStackID: 0, /* SpillStackID */
3450 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3451 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3452 offsetof(X86RegisterClassStorage, SuperClasses[508]) - 97 * sizeof(MCRegisterClass),
3453 .SuperClassesSize: 13
3454 },
3455 {
3456 offsetof(X86RegisterClassStorage, Regs[1062]) - 98 * sizeof(MCRegisterClass),
3457 offsetof(X86RegisterClassStorage, BitSets[1833]) - 98 * sizeof(MCRegisterClass),
3458 .NameIdx: 212,
3459 .RegSizeInBits: 64,
3460 .RegsSize: 6,
3461 .RegSetSize: 16,
3462 .ID: X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
3463 .CopyCost: 1, /* CopyCost */
3464 .Allocatable: true, /* Allocatable */
3465 .BaseClass: false,
3466 offsetof(X86RegisterClassStorage, SubClassMasks[865]) - 98 * sizeof(MCRegisterClass),
3467 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 98 * sizeof(MCRegisterClass),
3468 .LaneMask: LaneBitmask(0x000000000000000F),
3469 .AllocationPriority: 0,
3470 .GlobalPriority: false,
3471 .TSFlags: 0x00, /* TSFlags */
3472 .SpillStackID: 0, /* SpillStackID */
3473 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3474 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3475 offsetof(X86RegisterClassStorage, SuperClasses[521]) - 98 * sizeof(MCRegisterClass),
3476 .SuperClassesSize: 14
3477 },
3478 {
3479 offsetof(X86RegisterClassStorage, Regs[1068]) - 99 * sizeof(MCRegisterClass),
3480 offsetof(X86RegisterClassStorage, BitSets[1849]) - 99 * sizeof(MCRegisterClass),
3481 .NameIdx: 1458,
3482 .RegSizeInBits: 64,
3483 .RegsSize: 6,
3484 .RegSetSize: 8,
3485 .ID: X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
3486 .CopyCost: 1, /* CopyCost */
3487 .Allocatable: true, /* Allocatable */
3488 .BaseClass: false,
3489 offsetof(X86RegisterClassStorage, SubClassMasks[870]) - 99 * sizeof(MCRegisterClass),
3490 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 99 * sizeof(MCRegisterClass),
3491 .LaneMask: LaneBitmask(0x000000000000000F),
3492 .AllocationPriority: 0,
3493 .GlobalPriority: false,
3494 .TSFlags: 0x00, /* TSFlags */
3495 .SpillStackID: 0, /* SpillStackID */
3496 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3497 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3498 offsetof(X86RegisterClassStorage, SuperClasses[535]) - 99 * sizeof(MCRegisterClass),
3499 .SuperClassesSize: 9
3500 },
3501 {
3502 offsetof(X86RegisterClassStorage, Regs[1074]) - 100 * sizeof(MCRegisterClass),
3503 offsetof(X86RegisterClassStorage, BitSets[1857]) - 100 * sizeof(MCRegisterClass),
3504 .NameIdx: 282,
3505 .RegSizeInBits: 64,
3506 .RegsSize: 5,
3507 .RegSetSize: 16,
3508 .ID: X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
3509 .CopyCost: 1, /* CopyCost */
3510 .Allocatable: true, /* Allocatable */
3511 .BaseClass: false,
3512 offsetof(X86RegisterClassStorage, SubClassMasks[875]) - 100 * sizeof(MCRegisterClass),
3513 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 100 * sizeof(MCRegisterClass),
3514 .LaneMask: LaneBitmask(0x000000000000000F),
3515 .AllocationPriority: 0,
3516 .GlobalPriority: false,
3517 .TSFlags: 0x00, /* TSFlags */
3518 .SpillStackID: 0, /* SpillStackID */
3519 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3520 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3521 offsetof(X86RegisterClassStorage, SuperClasses[544]) - 100 * sizeof(MCRegisterClass),
3522 .SuperClassesSize: 17
3523 },
3524 {
3525 offsetof(X86RegisterClassStorage, Regs[1079]) - 101 * sizeof(MCRegisterClass),
3526 offsetof(X86RegisterClassStorage, BitSets[1873]) - 101 * sizeof(MCRegisterClass),
3527 .NameIdx: 644,
3528 .RegSizeInBits: 64,
3529 .RegsSize: 5,
3530 .RegSetSize: 8,
3531 .ID: X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
3532 .CopyCost: 1, /* CopyCost */
3533 .Allocatable: true, /* Allocatable */
3534 .BaseClass: false,
3535 offsetof(X86RegisterClassStorage, SubClassMasks[880]) - 101 * sizeof(MCRegisterClass),
3536 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 101 * sizeof(MCRegisterClass),
3537 .LaneMask: LaneBitmask(0x000000000000000F),
3538 .AllocationPriority: 0,
3539 .GlobalPriority: false,
3540 .TSFlags: 0x00, /* TSFlags */
3541 .SpillStackID: 0, /* SpillStackID */
3542 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3543 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3544 offsetof(X86RegisterClassStorage, SuperClasses[561]) - 101 * sizeof(MCRegisterClass),
3545 .SuperClassesSize: 16
3546 },
3547 {
3548 offsetof(X86RegisterClassStorage, Regs[1084]) - 102 * sizeof(MCRegisterClass),
3549 offsetof(X86RegisterClassStorage, BitSets[1881]) - 102 * sizeof(MCRegisterClass),
3550 .NameIdx: 256,
3551 .RegSizeInBits: 64,
3552 .RegsSize: 5,
3553 .RegSetSize: 8,
3554 .ID: X86::GR64_NOREX_and_GR64_TCW64RegClassID,
3555 .CopyCost: 1, /* CopyCost */
3556 .Allocatable: true, /* Allocatable */
3557 .BaseClass: false,
3558 offsetof(X86RegisterClassStorage, SubClassMasks[885]) - 102 * sizeof(MCRegisterClass),
3559 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 102 * sizeof(MCRegisterClass),
3560 .LaneMask: LaneBitmask(0x000000000000000F),
3561 .AllocationPriority: 0,
3562 .GlobalPriority: false,
3563 .TSFlags: 0x00, /* TSFlags */
3564 .SpillStackID: 0, /* SpillStackID */
3565 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3566 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3567 offsetof(X86RegisterClassStorage, SuperClasses[577]) - 102 * sizeof(MCRegisterClass),
3568 .SuperClassesSize: 7
3569 },
3570 {
3571 offsetof(X86RegisterClassStorage, Regs[1089]) - 103 * sizeof(MCRegisterClass),
3572 offsetof(X86RegisterClassStorage, BitSets[1889]) - 103 * sizeof(MCRegisterClass),
3573 .NameIdx: 733,
3574 .RegSizeInBits: 64,
3575 .RegsSize: 4,
3576 .RegSetSize: 8,
3577 .ID: X86::GR64_ABCDRegClassID,
3578 .CopyCost: 1, /* CopyCost */
3579 .Allocatable: true, /* Allocatable */
3580 .BaseClass: false,
3581 offsetof(X86RegisterClassStorage, SubClassMasks[890]) - 103 * sizeof(MCRegisterClass),
3582 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 103 * sizeof(MCRegisterClass),
3583 .LaneMask: LaneBitmask(0x000000000000000F),
3584 .AllocationPriority: 0,
3585 .GlobalPriority: false,
3586 .TSFlags: 0x00, /* TSFlags */
3587 .SpillStackID: 0, /* SpillStackID */
3588 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3589 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3590 offsetof(X86RegisterClassStorage, SuperClasses[584]) - 103 * sizeof(MCRegisterClass),
3591 .SuperClassesSize: 10
3592 },
3593 {
3594 offsetof(X86RegisterClassStorage, Regs[1093]) - 104 * sizeof(MCRegisterClass),
3595 offsetof(X86RegisterClassStorage, BitSets[1897]) - 104 * sizeof(MCRegisterClass),
3596 .NameIdx: 561,
3597 .RegSizeInBits: 64,
3598 .RegsSize: 4,
3599 .RegSetSize: 8,
3600 .ID: X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
3601 .CopyCost: 1, /* CopyCost */
3602 .Allocatable: true, /* Allocatable */
3603 .BaseClass: false,
3604 offsetof(X86RegisterClassStorage, SubClassMasks[895]) - 104 * sizeof(MCRegisterClass),
3605 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 104 * sizeof(MCRegisterClass),
3606 .LaneMask: LaneBitmask(0x000000000000000F),
3607 .AllocationPriority: 0,
3608 .GlobalPriority: false,
3609 .TSFlags: 0x00, /* TSFlags */
3610 .SpillStackID: 0, /* SpillStackID */
3611 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3612 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3613 offsetof(X86RegisterClassStorage, SuperClasses[594]) - 104 * sizeof(MCRegisterClass),
3614 .SuperClassesSize: 15
3615 },
3616 {
3617 offsetof(X86RegisterClassStorage, Regs[1097]) - 105 * sizeof(MCRegisterClass),
3618 offsetof(X86RegisterClassStorage, BitSets[1905]) - 105 * sizeof(MCRegisterClass),
3619 .NameIdx: 471,
3620 .RegSizeInBits: 64,
3621 .RegsSize: 3,
3622 .RegSetSize: 8,
3623 .ID: X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
3624 .CopyCost: 1, /* CopyCost */
3625 .Allocatable: true, /* Allocatable */
3626 .BaseClass: false,
3627 offsetof(X86RegisterClassStorage, SubClassMasks[900]) - 105 * sizeof(MCRegisterClass),
3628 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 105 * sizeof(MCRegisterClass),
3629 .LaneMask: LaneBitmask(0x000000000000000F),
3630 .AllocationPriority: 0,
3631 .GlobalPriority: false,
3632 .TSFlags: 0x00, /* TSFlags */
3633 .SpillStackID: 0, /* SpillStackID */
3634 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3635 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3636 offsetof(X86RegisterClassStorage, SuperClasses[609]) - 105 * sizeof(MCRegisterClass),
3637 .SuperClassesSize: 27
3638 },
3639 {
3640 offsetof(X86RegisterClassStorage, Regs[1100]) - 106 * sizeof(MCRegisterClass),
3641 offsetof(X86RegisterClassStorage, BitSets[1913]) - 106 * sizeof(MCRegisterClass),
3642 .NameIdx: 715,
3643 .RegSizeInBits: 64,
3644 .RegsSize: 2,
3645 .RegSetSize: 8,
3646 .ID: X86::GR64_ADRegClassID,
3647 .CopyCost: 1, /* CopyCost */
3648 .Allocatable: true, /* Allocatable */
3649 .BaseClass: false,
3650 offsetof(X86RegisterClassStorage, SubClassMasks[905]) - 106 * sizeof(MCRegisterClass),
3651 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 106 * sizeof(MCRegisterClass),
3652 .LaneMask: LaneBitmask(0x000000000000000F),
3653 .AllocationPriority: 0,
3654 .GlobalPriority: false,
3655 .TSFlags: 0x00, /* TSFlags */
3656 .SpillStackID: 0, /* SpillStackID */
3657 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3658 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3659 offsetof(X86RegisterClassStorage, SuperClasses[636]) - 106 * sizeof(MCRegisterClass),
3660 .SuperClassesSize: 28
3661 },
3662 {
3663 offsetof(X86RegisterClassStorage, Regs[1102]) - 107 * sizeof(MCRegisterClass),
3664 offsetof(X86RegisterClassStorage, BitSets[1921]) - 107 * sizeof(MCRegisterClass),
3665 .NameIdx: 1659,
3666 .RegSizeInBits: 64,
3667 .RegsSize: 2,
3668 .RegSetSize: 16,
3669 .ID: X86::GR64_ArgRefRegClassID,
3670 .CopyCost: 1, /* CopyCost */
3671 .Allocatable: true, /* Allocatable */
3672 .BaseClass: false,
3673 offsetof(X86RegisterClassStorage, SubClassMasks[910]) - 107 * sizeof(MCRegisterClass),
3674 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 107 * sizeof(MCRegisterClass),
3675 .LaneMask: LaneBitmask(0x000000000000000F),
3676 .AllocationPriority: 0,
3677 .GlobalPriority: false,
3678 .TSFlags: 0x00, /* TSFlags */
3679 .SpillStackID: 0, /* SpillStackID */
3680 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3681 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3682 offsetof(X86RegisterClassStorage, SuperClasses[664]) - 107 * sizeof(MCRegisterClass),
3683 .SuperClassesSize: 9
3684 },
3685 {
3686 offsetof(X86RegisterClassStorage, Regs[1104]) - 108 * sizeof(MCRegisterClass),
3687 offsetof(X86RegisterClassStorage, BitSets[1937]) - 108 * sizeof(MCRegisterClass),
3688 .NameIdx: 1170,
3689 .RegSizeInBits: 64,
3690 .RegsSize: 2,
3691 .RegSetSize: 8,
3692 .ID: X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
3693 .CopyCost: 1, /* CopyCost */
3694 .Allocatable: true, /* Allocatable */
3695 .BaseClass: false,
3696 offsetof(X86RegisterClassStorage, SubClassMasks[915]) - 108 * sizeof(MCRegisterClass),
3697 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 108 * sizeof(MCRegisterClass),
3698 .LaneMask: LaneBitmask(0x000000000000000F),
3699 .AllocationPriority: 0,
3700 .GlobalPriority: false,
3701 .TSFlags: 0x00, /* TSFlags */
3702 .SpillStackID: 0, /* SpillStackID */
3703 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3704 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3705 offsetof(X86RegisterClassStorage, SuperClasses[673]) - 108 * sizeof(MCRegisterClass),
3706 .SuperClassesSize: 5
3707 },
3708 {
3709 offsetof(X86RegisterClassStorage, Regs[1106]) - 109 * sizeof(MCRegisterClass),
3710 offsetof(X86RegisterClassStorage, BitSets[1945]) - 109 * sizeof(MCRegisterClass),
3711 .NameIdx: 1624,
3712 .RegSizeInBits: 64,
3713 .RegsSize: 2,
3714 .RegSetSize: 8,
3715 .ID: X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
3716 .CopyCost: 1, /* CopyCost */
3717 .Allocatable: true, /* Allocatable */
3718 .BaseClass: false,
3719 offsetof(X86RegisterClassStorage, SubClassMasks[920]) - 109 * sizeof(MCRegisterClass),
3720 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 109 * sizeof(MCRegisterClass),
3721 .LaneMask: LaneBitmask(0x000000000000000F),
3722 .AllocationPriority: 0,
3723 .GlobalPriority: false,
3724 .TSFlags: 0x00, /* TSFlags */
3725 .SpillStackID: 0, /* SpillStackID */
3726 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3727 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3728 offsetof(X86RegisterClassStorage, SuperClasses[678]) - 109 * sizeof(MCRegisterClass),
3729 .SuperClassesSize: 28
3730 },
3731 {
3732 offsetof(X86RegisterClassStorage, Regs[1108]) - 110 * sizeof(MCRegisterClass),
3733 offsetof(X86RegisterClassStorage, BitSets[1953]) - 110 * sizeof(MCRegisterClass),
3734 .NameIdx: 1287,
3735 .RegSizeInBits: 64,
3736 .RegsSize: 2,
3737 .RegSetSize: 8,
3738 .ID: X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
3739 .CopyCost: 1, /* CopyCost */
3740 .Allocatable: true, /* Allocatable */
3741 .BaseClass: false,
3742 offsetof(X86RegisterClassStorage, SubClassMasks[925]) - 110 * sizeof(MCRegisterClass),
3743 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 110 * sizeof(MCRegisterClass),
3744 .LaneMask: LaneBitmask(0x000000000000000F),
3745 .AllocationPriority: 0,
3746 .GlobalPriority: false,
3747 .TSFlags: 0x00, /* TSFlags */
3748 .SpillStackID: 0, /* SpillStackID */
3749 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3750 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3751 offsetof(X86RegisterClassStorage, SuperClasses[706]) - 110 * sizeof(MCRegisterClass),
3752 .SuperClassesSize: 6
3753 },
3754 {
3755 offsetof(X86RegisterClassStorage, Regs[1110]) - 111 * sizeof(MCRegisterClass),
3756 offsetof(X86RegisterClassStorage, BitSets[1961]) - 111 * sizeof(MCRegisterClass),
3757 .NameIdx: 975,
3758 .RegSizeInBits: 64,
3759 .RegsSize: 2,
3760 .RegSetSize: 8,
3761 .ID: X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID,
3762 .CopyCost: 1, /* CopyCost */
3763 .Allocatable: true, /* Allocatable */
3764 .BaseClass: false,
3765 offsetof(X86RegisterClassStorage, SubClassMasks[930]) - 111 * sizeof(MCRegisterClass),
3766 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 111 * sizeof(MCRegisterClass),
3767 .LaneMask: LaneBitmask(0x000000000000000F),
3768 .AllocationPriority: 0,
3769 .GlobalPriority: false,
3770 .TSFlags: 0x00, /* TSFlags */
3771 .SpillStackID: 0, /* SpillStackID */
3772 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3773 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3774 offsetof(X86RegisterClassStorage, SuperClasses[712]) - 111 * sizeof(MCRegisterClass),
3775 .SuperClassesSize: 10
3776 },
3777 {
3778 offsetof(X86RegisterClassStorage, Regs[1112]) - 112 * sizeof(MCRegisterClass),
3779 offsetof(X86RegisterClassStorage, BitSets[1969]) - 112 * sizeof(MCRegisterClass),
3780 .NameIdx: 432,
3781 .RegSizeInBits: 64,
3782 .RegsSize: 2,
3783 .RegSetSize: 7,
3784 .ID: X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
3785 .CopyCost: 1, /* CopyCost */
3786 .Allocatable: true, /* Allocatable */
3787 .BaseClass: false,
3788 offsetof(X86RegisterClassStorage, SubClassMasks[935]) - 112 * sizeof(MCRegisterClass),
3789 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 112 * sizeof(MCRegisterClass),
3790 .LaneMask: LaneBitmask(0x000000000000000F),
3791 .AllocationPriority: 0,
3792 .GlobalPriority: false,
3793 .TSFlags: 0x00, /* TSFlags */
3794 .SpillStackID: 0, /* SpillStackID */
3795 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3796 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3797 offsetof(X86RegisterClassStorage, SuperClasses[722]) - 112 * sizeof(MCRegisterClass),
3798 .SuperClassesSize: 11
3799 },
3800 {
3801 offsetof(X86RegisterClassStorage, Regs[1114]) - 113 * sizeof(MCRegisterClass),
3802 offsetof(X86RegisterClassStorage, BitSets[1976]) - 113 * sizeof(MCRegisterClass),
3803 .NameIdx: 1137,
3804 .RegSizeInBits: 64,
3805 .RegsSize: 2,
3806 .RegSetSize: 7,
3807 .ID: X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
3808 .CopyCost: 1, /* CopyCost */
3809 .Allocatable: true, /* Allocatable */
3810 .BaseClass: false,
3811 offsetof(X86RegisterClassStorage, SubClassMasks[940]) - 113 * sizeof(MCRegisterClass),
3812 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 113 * sizeof(MCRegisterClass),
3813 .LaneMask: LaneBitmask(0x000000000000000F),
3814 .AllocationPriority: 0,
3815 .GlobalPriority: false,
3816 .TSFlags: 0x00, /* TSFlags */
3817 .SpillStackID: 0, /* SpillStackID */
3818 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3819 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3820 offsetof(X86RegisterClassStorage, SuperClasses[733]) - 113 * sizeof(MCRegisterClass),
3821 .SuperClassesSize: 10
3822 },
3823 {
3824 offsetof(X86RegisterClassStorage, Regs[1116]) - 114 * sizeof(MCRegisterClass),
3825 offsetof(X86RegisterClassStorage, BitSets[1983]) - 114 * sizeof(MCRegisterClass),
3826 .NameIdx: 896,
3827 .RegSizeInBits: 64,
3828 .RegsSize: 2,
3829 .RegSetSize: 8,
3830 .ID: X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
3831 .CopyCost: 1, /* CopyCost */
3832 .Allocatable: true, /* Allocatable */
3833 .BaseClass: false,
3834 offsetof(X86RegisterClassStorage, SubClassMasks[945]) - 114 * sizeof(MCRegisterClass),
3835 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 114 * sizeof(MCRegisterClass),
3836 .LaneMask: LaneBitmask(0x000000000000000F),
3837 .AllocationPriority: 0,
3838 .GlobalPriority: false,
3839 .TSFlags: 0x00, /* TSFlags */
3840 .SpillStackID: 0, /* SpillStackID */
3841 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3842 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3843 offsetof(X86RegisterClassStorage, SuperClasses[743]) - 114 * sizeof(MCRegisterClass),
3844 .SuperClassesSize: 17
3845 },
3846 {
3847 offsetof(X86RegisterClassStorage, Regs[1118]) - 115 * sizeof(MCRegisterClass),
3848 offsetof(X86RegisterClassStorage, BitSets[1991]) - 115 * sizeof(MCRegisterClass),
3849 .NameIdx: 378,
3850 .RegSizeInBits: 64,
3851 .RegsSize: 1,
3852 .RegSetSize: 7,
3853 .ID: X86::GR64_ARegClassID,
3854 .CopyCost: 1, /* CopyCost */
3855 .Allocatable: true, /* Allocatable */
3856 .BaseClass: false,
3857 offsetof(X86RegisterClassStorage, SubClassMasks[950]) - 115 * sizeof(MCRegisterClass),
3858 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 115 * sizeof(MCRegisterClass),
3859 .LaneMask: LaneBitmask(0x000000000000000F),
3860 .AllocationPriority: 0,
3861 .GlobalPriority: false,
3862 .TSFlags: 0x00, /* TSFlags */
3863 .SpillStackID: 0, /* SpillStackID */
3864 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3865 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3866 offsetof(X86RegisterClassStorage, SuperClasses[760]) - 115 * sizeof(MCRegisterClass),
3867 .SuperClassesSize: 29
3868 },
3869 {
3870 offsetof(X86RegisterClassStorage, Regs[1119]) - 116 * sizeof(MCRegisterClass),
3871 offsetof(X86RegisterClassStorage, BitSets[1998]) - 116 * sizeof(MCRegisterClass),
3872 .NameIdx: 683,
3873 .RegSizeInBits: 64,
3874 .RegsSize: 1,
3875 .RegSetSize: 16,
3876 .ID: X86::GR64_ArgRef_and_GR64_TCRegClassID,
3877 .CopyCost: 1, /* CopyCost */
3878 .Allocatable: true, /* Allocatable */
3879 .BaseClass: false,
3880 offsetof(X86RegisterClassStorage, SubClassMasks[955]) - 116 * sizeof(MCRegisterClass),
3881 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 116 * sizeof(MCRegisterClass),
3882 .LaneMask: LaneBitmask(0x000000000000000F),
3883 .AllocationPriority: 0,
3884 .GlobalPriority: false,
3885 .TSFlags: 0x00, /* TSFlags */
3886 .SpillStackID: 0, /* SpillStackID */
3887 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3888 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3889 offsetof(X86RegisterClassStorage, SuperClasses[789]) - 116 * sizeof(MCRegisterClass),
3890 .SuperClassesSize: 16
3891 },
3892 {
3893 offsetof(X86RegisterClassStorage, Regs[1120]) - 117 * sizeof(MCRegisterClass),
3894 offsetof(X86RegisterClassStorage, BitSets[2014]) - 117 * sizeof(MCRegisterClass),
3895 .NameIdx: 1373,
3896 .RegSizeInBits: 64,
3897 .RegsSize: 1,
3898 .RegSetSize: 8,
3899 .ID: X86::GR64_and_LOW32_ADDR_ACCESSRegClassID,
3900 .CopyCost: 1, /* CopyCost */
3901 .Allocatable: true, /* Allocatable */
3902 .BaseClass: false,
3903 offsetof(X86RegisterClassStorage, SubClassMasks[960]) - 117 * sizeof(MCRegisterClass),
3904 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 117 * sizeof(MCRegisterClass),
3905 .LaneMask: LaneBitmask(0x000000000000000F),
3906 .AllocationPriority: 0,
3907 .GlobalPriority: false,
3908 .TSFlags: 0x00, /* TSFlags */
3909 .SpillStackID: 0, /* SpillStackID */
3910 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3911 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3912 offsetof(X86RegisterClassStorage, SuperClasses[805]) - 117 * sizeof(MCRegisterClass),
3913 .SuperClassesSize: 13
3914 },
3915 {
3916 offsetof(X86RegisterClassStorage, Regs[1121]) - 118 * sizeof(MCRegisterClass),
3917 offsetof(X86RegisterClassStorage, BitSets[2022]) - 118 * sizeof(MCRegisterClass),
3918 .NameIdx: 929,
3919 .RegSizeInBits: 64,
3920 .RegsSize: 1,
3921 .RegSetSize: 7,
3922 .ID: X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID,
3923 .CopyCost: 1, /* CopyCost */
3924 .Allocatable: true, /* Allocatable */
3925 .BaseClass: false,
3926 offsetof(X86RegisterClassStorage, SubClassMasks[965]) - 118 * sizeof(MCRegisterClass),
3927 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 118 * sizeof(MCRegisterClass),
3928 .LaneMask: LaneBitmask(0x000000000000000F),
3929 .AllocationPriority: 0,
3930 .GlobalPriority: false,
3931 .TSFlags: 0x00, /* TSFlags */
3932 .SpillStackID: 0, /* SpillStackID */
3933 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3934 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3935 offsetof(X86RegisterClassStorage, SuperClasses[818]) - 118 * sizeof(MCRegisterClass),
3936 .SuperClassesSize: 13
3937 },
3938 {
3939 offsetof(X86RegisterClassStorage, Regs[1122]) - 119 * sizeof(MCRegisterClass),
3940 offsetof(X86RegisterClassStorage, BitSets[2029]) - 119 * sizeof(MCRegisterClass),
3941 .NameIdx: 1577,
3942 .RegSizeInBits: 64,
3943 .RegsSize: 1,
3944 .RegSetSize: 8,
3945 .ID: X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID,
3946 .CopyCost: 1, /* CopyCost */
3947 .Allocatable: true, /* Allocatable */
3948 .BaseClass: false,
3949 offsetof(X86RegisterClassStorage, SubClassMasks[970]) - 119 * sizeof(MCRegisterClass),
3950 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 119 * sizeof(MCRegisterClass),
3951 .LaneMask: LaneBitmask(0x000000000000000F),
3952 .AllocationPriority: 0,
3953 .GlobalPriority: false,
3954 .TSFlags: 0x00, /* TSFlags */
3955 .SpillStackID: 0, /* SpillStackID */
3956 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3957 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3958 offsetof(X86RegisterClassStorage, SuperClasses[831]) - 119 * sizeof(MCRegisterClass),
3959 .SuperClassesSize: 30
3960 },
3961 {
3962 offsetof(X86RegisterClassStorage, Regs[1123]) - 120 * sizeof(MCRegisterClass),
3963 offsetof(X86RegisterClassStorage, BitSets[2037]) - 120 * sizeof(MCRegisterClass),
3964 .NameIdx: 385,
3965 .RegSizeInBits: 64,
3966 .RegsSize: 1,
3967 .RegSetSize: 7,
3968 .ID: X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID,
3969 .CopyCost: 1, /* CopyCost */
3970 .Allocatable: true, /* Allocatable */
3971 .BaseClass: false,
3972 offsetof(X86RegisterClassStorage, SubClassMasks[975]) - 120 * sizeof(MCRegisterClass),
3973 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 120 * sizeof(MCRegisterClass),
3974 .LaneMask: LaneBitmask(0x000000000000000F),
3975 .AllocationPriority: 0,
3976 .GlobalPriority: false,
3977 .TSFlags: 0x00, /* TSFlags */
3978 .SpillStackID: 0, /* SpillStackID */
3979 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3980 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3981 offsetof(X86RegisterClassStorage, SuperClasses[861]) - 120 * sizeof(MCRegisterClass),
3982 .SuperClassesSize: 30
3983 },
3984 {
3985 offsetof(X86RegisterClassStorage, Regs[1124]) - 121 * sizeof(MCRegisterClass),
3986 offsetof(X86RegisterClassStorage, BitSets[2044]) - 121 * sizeof(MCRegisterClass),
3987 .NameIdx: 1090,
3988 .RegSizeInBits: 64,
3989 .RegsSize: 1,
3990 .RegSetSize: 7,
3991 .ID: X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID,
3992 .CopyCost: 1, /* CopyCost */
3993 .Allocatable: true, /* Allocatable */
3994 .BaseClass: false,
3995 offsetof(X86RegisterClassStorage, SubClassMasks[980]) - 121 * sizeof(MCRegisterClass),
3996 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 121 * sizeof(MCRegisterClass),
3997 .LaneMask: LaneBitmask(0x000000000000000F),
3998 .AllocationPriority: 0,
3999 .GlobalPriority: false,
4000 .TSFlags: 0x00, /* TSFlags */
4001 .SpillStackID: 0, /* SpillStackID */
4002 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4003 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4004 offsetof(X86RegisterClassStorage, SuperClasses[891]) - 121 * sizeof(MCRegisterClass),
4005 .SuperClassesSize: 19
4006 },
4007 {
4008 offsetof(X86RegisterClassStorage, Regs[1125]) - 122 * sizeof(MCRegisterClass),
4009 offsetof(X86RegisterClassStorage, BitSets[2051]) - 122 * sizeof(MCRegisterClass),
4010 .NameIdx: 516,
4011 .RegSizeInBits: 64,
4012 .RegsSize: 1,
4013 .RegSetSize: 8,
4014 .ID: X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID,
4015 .CopyCost: 1, /* CopyCost */
4016 .Allocatable: true, /* Allocatable */
4017 .BaseClass: false,
4018 offsetof(X86RegisterClassStorage, SubClassMasks[985]) - 122 * sizeof(MCRegisterClass),
4019 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 122 * sizeof(MCRegisterClass),
4020 .LaneMask: LaneBitmask(0x000000000000000F),
4021 .AllocationPriority: 0,
4022 .GlobalPriority: false,
4023 .TSFlags: 0x00, /* TSFlags */
4024 .SpillStackID: 0, /* SpillStackID */
4025 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4026 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4027 offsetof(X86RegisterClassStorage, SuperClasses[910]) - 122 * sizeof(MCRegisterClass),
4028 .SuperClassesSize: 17
4029 },
4030 {
4031 offsetof(X86RegisterClassStorage, Regs[1126]) - 123 * sizeof(MCRegisterClass),
4032 offsetof(X86RegisterClassStorage, BitSets[2059]) - 123 * sizeof(MCRegisterClass),
4033 .NameIdx: 803,
4034 .RegSizeInBits: 64,
4035 .RegsSize: 1,
4036 .RegSetSize: 8,
4037 .ID: X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID,
4038 .CopyCost: 1, /* CopyCost */
4039 .Allocatable: true, /* Allocatable */
4040 .BaseClass: false,
4041 offsetof(X86RegisterClassStorage, SubClassMasks[990]) - 123 * sizeof(MCRegisterClass),
4042 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 123 * sizeof(MCRegisterClass),
4043 .LaneMask: LaneBitmask(0x000000000000000F),
4044 .AllocationPriority: 0,
4045 .GlobalPriority: false,
4046 .TSFlags: 0x00, /* TSFlags */
4047 .SpillStackID: 0, /* SpillStackID */
4048 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4049 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4050 offsetof(X86RegisterClassStorage, SuperClasses[927]) - 123 * sizeof(MCRegisterClass),
4051 .SuperClassesSize: 19
4052 },
4053 {
4054 offsetof(X86RegisterClassStorage, Regs[1127]) - 124 * sizeof(MCRegisterClass),
4055 offsetof(X86RegisterClassStorage, BitSets[2067]) - 124 * sizeof(MCRegisterClass),
4056 .NameIdx: 849,
4057 .RegSizeInBits: 64,
4058 .RegsSize: 1,
4059 .RegSetSize: 7,
4060 .ID: X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID,
4061 .CopyCost: 1, /* CopyCost */
4062 .Allocatable: true, /* Allocatable */
4063 .BaseClass: false,
4064 offsetof(X86RegisterClassStorage, SubClassMasks[995]) - 124 * sizeof(MCRegisterClass),
4065 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 124 * sizeof(MCRegisterClass),
4066 .LaneMask: LaneBitmask(0x000000000000000F),
4067 .AllocationPriority: 0,
4068 .GlobalPriority: false,
4069 .TSFlags: 0x00, /* TSFlags */
4070 .SpillStackID: 0, /* SpillStackID */
4071 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4072 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4073 offsetof(X86RegisterClassStorage, SuperClasses[946]) - 124 * sizeof(MCRegisterClass),
4074 .SuperClassesSize: 19
4075 },
4076 {
4077 offsetof(X86RegisterClassStorage, Regs[1128]) - 125 * sizeof(MCRegisterClass),
4078 offsetof(X86RegisterClassStorage, BitSets[2074]) - 125 * sizeof(MCRegisterClass),
4079 .NameIdx: 1400,
4080 .RegSizeInBits: 80,
4081 .RegsSize: 8,
4082 .RegSetSize: 17,
4083 .ID: X86::RSTRegClassID,
4084 .CopyCost: 1, /* CopyCost */
4085 .Allocatable: false, /* Allocatable */
4086 .BaseClass: false,
4087 offsetof(X86RegisterClassStorage, SubClassMasks[1000]) - 125 * sizeof(MCRegisterClass),
4088 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 125 * sizeof(MCRegisterClass),
4089 .LaneMask: LaneBitmask(0x0000000000000001),
4090 .AllocationPriority: 0,
4091 .GlobalPriority: false,
4092 .TSFlags: 0x00, /* TSFlags */
4093 .SpillStackID: 0, /* SpillStackID */
4094 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4095 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4096 offsetof(X86RegisterClassStorage, SuperClasses[965]) - 125 * sizeof(MCRegisterClass),
4097 .SuperClassesSize: 0
4098 },
4099 {
4100 offsetof(X86RegisterClassStorage, Regs[1136]) - 126 * sizeof(MCRegisterClass),
4101 offsetof(X86RegisterClassStorage, BitSets[2091]) - 126 * sizeof(MCRegisterClass),
4102 .NameIdx: 0,
4103 .RegSizeInBits: 80,
4104 .RegsSize: 7,
4105 .RegSetSize: 14,
4106 .ID: X86::RFP80RegClassID,
4107 .CopyCost: 1, /* CopyCost */
4108 .Allocatable: true, /* Allocatable */
4109 .BaseClass: false,
4110 offsetof(X86RegisterClassStorage, SubClassMasks[1005]) - 126 * sizeof(MCRegisterClass),
4111 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 126 * sizeof(MCRegisterClass),
4112 .LaneMask: LaneBitmask(0x0000000000000001),
4113 .AllocationPriority: 0,
4114 .GlobalPriority: false,
4115 .TSFlags: 0x00, /* TSFlags */
4116 .SpillStackID: 0, /* SpillStackID */
4117 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4118 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4119 offsetof(X86RegisterClassStorage, SuperClasses[965]) - 126 * sizeof(MCRegisterClass),
4120 .SuperClassesSize: 2
4121 },
4122 {
4123 offsetof(X86RegisterClassStorage, Regs[1143]) - 127 * sizeof(MCRegisterClass),
4124 offsetof(X86RegisterClassStorage, BitSets[2105]) - 127 * sizeof(MCRegisterClass),
4125 .NameIdx: 351,
4126 .RegSizeInBits: 80,
4127 .RegsSize: 1,
4128 .RegSetSize: 14,
4129 .ID: X86::RFP80_7RegClassID,
4130 .CopyCost: 1, /* CopyCost */
4131 .Allocatable: false, /* Allocatable */
4132 .BaseClass: false,
4133 offsetof(X86RegisterClassStorage, SubClassMasks[1010]) - 127 * sizeof(MCRegisterClass),
4134 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 127 * sizeof(MCRegisterClass),
4135 .LaneMask: LaneBitmask(0x0000000000000001),
4136 .AllocationPriority: 0,
4137 .GlobalPriority: false,
4138 .TSFlags: 0x00, /* TSFlags */
4139 .SpillStackID: 0, /* SpillStackID */
4140 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4141 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4142 offsetof(X86RegisterClassStorage, SuperClasses[967]) - 127 * sizeof(MCRegisterClass),
4143 .SuperClassesSize: 0
4144 },
4145 {
4146 offsetof(X86RegisterClassStorage, Regs[1144]) - 128 * sizeof(MCRegisterClass),
4147 offsetof(X86RegisterClassStorage, BitSets[2119]) - 128 * sizeof(MCRegisterClass),
4148 .NameIdx: 1429,
4149 .RegSizeInBits: 128,
4150 .RegsSize: 32,
4151 .RegSetSize: 29,
4152 .ID: X86::VR128XRegClassID,
4153 .CopyCost: 1, /* CopyCost */
4154 .Allocatable: true, /* Allocatable */
4155 .BaseClass: false,
4156 offsetof(X86RegisterClassStorage, SubClassMasks[1015]) - 128 * sizeof(MCRegisterClass),
4157 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 128 * sizeof(MCRegisterClass),
4158 .LaneMask: LaneBitmask(0x0000000000000001),
4159 .AllocationPriority: 0,
4160 .GlobalPriority: false,
4161 .TSFlags: 0x00, /* TSFlags */
4162 .SpillStackID: 0, /* SpillStackID */
4163 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4164 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4165 offsetof(X86RegisterClassStorage, SuperClasses[967]) - 128 * sizeof(MCRegisterClass),
4166 .SuperClassesSize: 3
4167 },
4168 {
4169 offsetof(X86RegisterClassStorage, Regs[1176]) - 129 * sizeof(MCRegisterClass),
4170 offsetof(X86RegisterClassStorage, BitSets[2148]) - 129 * sizeof(MCRegisterClass),
4171 .NameIdx: 359,
4172 .RegSizeInBits: 128,
4173 .RegsSize: 16,
4174 .RegSetSize: 19,
4175 .ID: X86::VR128RegClassID,
4176 .CopyCost: 1, /* CopyCost */
4177 .Allocatable: true, /* Allocatable */
4178 .BaseClass: false,
4179 offsetof(X86RegisterClassStorage, SubClassMasks[1025]) - 129 * sizeof(MCRegisterClass),
4180 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 129 * sizeof(MCRegisterClass),
4181 .LaneMask: LaneBitmask(0x0000000000000001),
4182 .AllocationPriority: 0,
4183 .GlobalPriority: false,
4184 .TSFlags: 0x00, /* TSFlags */
4185 .SpillStackID: 0, /* SpillStackID */
4186 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4187 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4188 offsetof(X86RegisterClassStorage, SuperClasses[970]) - 129 * sizeof(MCRegisterClass),
4189 .SuperClassesSize: 7
4190 },
4191 {
4192 offsetof(X86RegisterClassStorage, Regs[1192]) - 130 * sizeof(MCRegisterClass),
4193 offsetof(X86RegisterClassStorage, BitSets[2167]) - 130 * sizeof(MCRegisterClass),
4194 .NameIdx: 1422,
4195 .RegSizeInBits: 256,
4196 .RegsSize: 32,
4197 .RegSetSize: 31,
4198 .ID: X86::VR256XRegClassID,
4199 .CopyCost: 1, /* CopyCost */
4200 .Allocatable: true, /* Allocatable */
4201 .BaseClass: false,
4202 offsetof(X86RegisterClassStorage, SubClassMasks[1035]) - 130 * sizeof(MCRegisterClass),
4203 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[14]) - 130 * sizeof(MCRegisterClass),
4204 .LaneMask: LaneBitmask(0x0000000000000040),
4205 .AllocationPriority: 0,
4206 .GlobalPriority: false,
4207 .TSFlags: 0x00, /* TSFlags */
4208 .SpillStackID: 0, /* SpillStackID */
4209 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4210 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4211 offsetof(X86RegisterClassStorage, SuperClasses[977]) - 130 * sizeof(MCRegisterClass),
4212 .SuperClassesSize: 0
4213 },
4214 {
4215 offsetof(X86RegisterClassStorage, Regs[1224]) - 131 * sizeof(MCRegisterClass),
4216 offsetof(X86RegisterClassStorage, BitSets[2198]) - 131 * sizeof(MCRegisterClass),
4217 .NameIdx: 345,
4218 .RegSizeInBits: 256,
4219 .RegsSize: 16,
4220 .RegSetSize: 26,
4221 .ID: X86::VR256RegClassID,
4222 .CopyCost: 1, /* CopyCost */
4223 .Allocatable: true, /* Allocatable */
4224 .BaseClass: false,
4225 offsetof(X86RegisterClassStorage, SubClassMasks[1045]) - 131 * sizeof(MCRegisterClass),
4226 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[14]) - 131 * sizeof(MCRegisterClass),
4227 .LaneMask: LaneBitmask(0x0000000000000040),
4228 .AllocationPriority: 0,
4229 .GlobalPriority: false,
4230 .TSFlags: 0x00, /* TSFlags */
4231 .SpillStackID: 0, /* SpillStackID */
4232 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4233 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4234 offsetof(X86RegisterClassStorage, SuperClasses[977]) - 131 * sizeof(MCRegisterClass),
4235 .SuperClassesSize: 1
4236 },
4237 {
4238 offsetof(X86RegisterClassStorage, Regs[1240]) - 132 * sizeof(MCRegisterClass),
4239 offsetof(X86RegisterClassStorage, BitSets[2224]) - 132 * sizeof(MCRegisterClass),
4240 .NameIdx: 10,
4241 .RegSizeInBits: 512,
4242 .RegsSize: 32,
4243 .RegSetSize: 35,
4244 .ID: X86::VR512RegClassID,
4245 .CopyCost: 1, /* CopyCost */
4246 .Allocatable: true, /* Allocatable */
4247 .BaseClass: false,
4248 offsetof(X86RegisterClassStorage, SubClassMasks[1055]) - 132 * sizeof(MCRegisterClass),
4249 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 132 * sizeof(MCRegisterClass),
4250 .LaneMask: LaneBitmask(0x0000000000000040),
4251 .AllocationPriority: 0,
4252 .GlobalPriority: false,
4253 .TSFlags: 0x00, /* TSFlags */
4254 .SpillStackID: 0, /* SpillStackID */
4255 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4256 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4257 offsetof(X86RegisterClassStorage, SuperClasses[978]) - 132 * sizeof(MCRegisterClass),
4258 .SuperClassesSize: 0
4259 },
4260 {
4261 offsetof(X86RegisterClassStorage, Regs[1272]) - 133 * sizeof(MCRegisterClass),
4262 offsetof(X86RegisterClassStorage, BitSets[2259]) - 133 * sizeof(MCRegisterClass),
4263 .NameIdx: 313,
4264 .RegSizeInBits: 512,
4265 .RegsSize: 16,
4266 .RegSetSize: 33,
4267 .ID: X86::VR512_0_15RegClassID,
4268 .CopyCost: 1, /* CopyCost */
4269 .Allocatable: true, /* Allocatable */
4270 .BaseClass: false,
4271 offsetof(X86RegisterClassStorage, SubClassMasks[1060]) - 133 * sizeof(MCRegisterClass),
4272 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 133 * sizeof(MCRegisterClass),
4273 .LaneMask: LaneBitmask(0x0000000000000040),
4274 .AllocationPriority: 0,
4275 .GlobalPriority: false,
4276 .TSFlags: 0x00, /* TSFlags */
4277 .SpillStackID: 0, /* SpillStackID */
4278 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4279 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4280 offsetof(X86RegisterClassStorage, SuperClasses[978]) - 133 * sizeof(MCRegisterClass),
4281 .SuperClassesSize: 1
4282 },
4283 {
4284 offsetof(X86RegisterClassStorage, Regs[1288]) - 134 * sizeof(MCRegisterClass),
4285 offsetof(X86RegisterClassStorage, BitSets[2292]) - 134 * sizeof(MCRegisterClass),
4286 .NameIdx: 753,
4287 .RegSizeInBits: 8192,
4288 .RegsSize: 8,
4289 .RegSetSize: 37,
4290 .ID: X86::TILERegClassID,
4291 .CopyCost: 255, /* CopyCost */
4292 .Allocatable: true, /* Allocatable */
4293 .BaseClass: false,
4294 offsetof(X86RegisterClassStorage, SubClassMasks[1065]) - 134 * sizeof(MCRegisterClass),
4295 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 134 * sizeof(MCRegisterClass),
4296 .LaneMask: LaneBitmask(0x0000000000000001),
4297 .AllocationPriority: 0,
4298 .GlobalPriority: false,
4299 .TSFlags: 0x00, /* TSFlags */
4300 .SpillStackID: 0, /* SpillStackID */
4301 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4302 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4303 offsetof(X86RegisterClassStorage, SuperClasses[979]) - 134 * sizeof(MCRegisterClass),
4304 .SuperClassesSize: 0
4305 },
4306 },
4307 .Regs: {
4308 /* 0 */ X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::R20B, X86::R21B, X86::R28B, X86::R29B, X86::R30B, X86::R31B,
4309 /* 36 */ X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH, X86::R16BH, X86::R17BH, X86::R18BH, X86::R19BH, X86::R20BH, X86::R21BH, X86::R22BH, X86::R23BH, X86::R24BH, X86::R25BH, X86::R26BH, X86::R27BH, X86::R28BH, X86::R29BH, X86::R30BH, X86::R31BH,
4310 /* 64 */ X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
4311 /* 84 */ X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
4312 /* 92 */ X86::AH, X86::CH, X86::DH, X86::BH,
4313 /* 96 */ X86::AL, X86::CL, X86::DL, X86::BL,
4314 /* 100 */ X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH, X86::R16WH, X86::R17WH, X86::R18WH, X86::R19WH, X86::R20WH, X86::R21WH, X86::R22WH, X86::R23WH, X86::R24WH, X86::R25WH, X86::R26WH, X86::R27WH, X86::R28WH, X86::R29WH, X86::R30WH, X86::R31WH,
4315 /* 133 */ X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R16W, X86::R17W, X86::R18W, X86::R19W, X86::R22W, X86::R23W, X86::R24W, X86::R25W, X86::R26W, X86::R27W, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::R20W, X86::R21W, X86::R28W, X86::R29W, X86::R30W, X86::R31W,
4316 /* 165 */ X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
4317 /* 181 */ X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP,
4318 /* 189 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4319 /* 197 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4320 /* 205 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4321 /* 213 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4322 /* 221 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4323 /* 229 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4324 /* 236 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4325 /* 243 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4326 /* 250 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4327 /* 257 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4328 /* 264 */ X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS,
4329 /* 270 */ X86::AX, X86::CX, X86::DX, X86::BX,
4330 /* 274 */ X86::FPSW,
4331 /* 275 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
4332 /* 307 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
4333 /* 323 */ X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
4334 /* 327 */ X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
4335 /* 331 */ X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
4336 /* 335 */ X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
4337 /* 339 */ X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
4338 /* 343 */ X86::K2_K3, X86::K4_K5, X86::K6_K7,
4339 /* 346 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::R30D, X86::R31D, X86::RIP, X86::RBP,
4340 /* 380 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::R30D, X86::R31D, X86::RIP,
4341 /* 413 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::R30D, X86::R31D, X86::RBP,
4342 /* 446 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
4343 /* 478 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::R30D, X86::R31D,
4344 /* 510 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::R30D, X86::R31D,
4345 /* 541 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP,
4346 /* 558 */ X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15,
4347 /* 574 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
4348 /* 590 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
4349 /* 606 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
4350 /* 621 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP,
4351 /* 630 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP,
4352 /* 638 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4353 /* 646 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,
4354 /* 653 */ X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
4355 /* 660 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4356 /* 667 */ X86::EAX, X86::ECX, X86::EDX, X86::EBX,
4357 /* 671 */ X86::EAX, X86::ECX, X86::EDX, X86::ESP,
4358 /* 675 */ X86::EAX, X86::ECX, X86::EDX,
4359 /* 678 */ X86::EAX, X86::EDX,
4360 /* 680 */ X86::ECX, X86::EDX,
4361 /* 682 */ X86::EBP, X86::ESP,
4362 /* 684 */ X86::EBX, X86::ESI,
4363 /* 686 */ X86::ECX, X86::EBX,
4364 /* 688 */ X86::EDX, X86::ECX,
4365 /* 690 */ X86::EDI, X86::EBP,
4366 /* 692 */ X86::ESI, X86::EDI,
4367 /* 694 */ X86::RIP, X86::RBP,
4368 /* 696 */ X86::EFLAGS,
4369 /* 697 */ X86::DF,
4370 /* 698 */ X86::EBX,
4371 /* 699 */ X86::EDX,
4372 /* 700 */ X86::ECX,
4373 /* 701 */ X86::EBP,
4374 /* 702 */ X86::ESP,
4375 /* 703 */ X86::ESI,
4376 /* 704 */ X86::EDI,
4377 /* 705 */ X86::RBP,
4378 /* 706 */ X86::RIP,
4379 /* 707 */ X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
4380 /* 714 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::R30, X86::R31, X86::RBP, X86::RSP, X86::RIP,
4381 /* 747 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
4382 /* 779 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::R30, X86::R31, X86::RBP, X86::RSP,
4383 /* 811 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::R30, X86::R31, X86::RBP,
4384 /* 842 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
4385 /* 859 */ X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15,
4386 /* 875 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
4387 /* 891 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
4388 /* 907 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
4389 /* 922 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
4390 /* 935 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
4391 /* 945 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
4392 /* 954 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP,
4393 /* 963 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP,
4394 /* 972 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11,
4395 /* 980 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP,
4396 /* 988 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
4397 /* 996 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP,
4398 /* 1004 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4399 /* 1012 */ X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
4400 /* 1020 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9,
4401 /* 1027 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11,
4402 /* 1034 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP,
4403 /* 1041 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP,
4404 /* 1048 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP,
4405 /* 1055 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4406 /* 1062 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11,
4407 /* 1068 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP,
4408 /* 1074 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9,
4409 /* 1079 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI,
4410 /* 1084 */ X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP,
4411 /* 1089 */ X86::RAX, X86::RCX, X86::RDX, X86::RBX,
4412 /* 1093 */ X86::RAX, X86::RCX, X86::RDX, X86::RSP,
4413 /* 1097 */ X86::RAX, X86::RCX, X86::RDX,
4414 /* 1100 */ X86::RAX, X86::RDX,
4415 /* 1102 */ X86::R10, X86::R11,
4416 /* 1104 */ X86::RBP, X86::RIP,
4417 /* 1106 */ X86::RCX, X86::RDX,
4418 /* 1108 */ X86::RBP, X86::RSP,
4419 /* 1110 */ X86::RSI, X86::RBX,
4420 /* 1112 */ X86::RCX, X86::RBX,
4421 /* 1114 */ X86::RDI, X86::RBP,
4422 /* 1116 */ X86::RSI, X86::RDI,
4423 /* 1118 */ X86::RAX,
4424 /* 1119 */ X86::R11,
4425 /* 1120 */ X86::RIP,
4426 /* 1121 */ X86::RBX,
4427 /* 1122 */ X86::RDX,
4428 /* 1123 */ X86::RCX,
4429 /* 1124 */ X86::RBP,
4430 /* 1125 */ X86::RSP,
4431 /* 1126 */ X86::RSI,
4432 /* 1127 */ X86::RDI,
4433 /* 1128 */ X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
4434 /* 1136 */ X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
4435 /* 1143 */ X86::FP7,
4436 /* 1144 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
4437 /* 1176 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
4438 /* 1192 */ X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31,
4439 /* 1224 */ X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15,
4440 /* 1240 */ X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31,
4441 /* 1272 */ X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15,
4442 /* 1288 */ X86::TMM0, X86::TMM1, X86::TMM2, X86::TMM3, X86::TMM4, X86::TMM5, X86::TMM6, X86::TMM7,
4443 },
4444 .BitSets: {
4445 /* 0 */ 0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
4446 /* 41 */ 0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
4447 /* 84 */ 0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4448 /* 104 */ 0x36, 0x8c, 0x08,
4449 /* 107 */ 0x12, 0x84,
4450 /* 109 */ 0x24, 0x08, 0x08,
4451 /* 112 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
4452 /* 161 */ 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
4453 /* 208 */ 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4454 /* 231 */ 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02,
4455 /* 240 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4456 /* 267 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4457 /* 294 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4458 /* 321 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4459 /* 348 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4460 /* 375 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
4461 /* 402 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
4462 /* 429 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
4463 /* 456 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
4464 /* 483 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
4465 /* 510 */ 0x00, 0x10, 0x10, 0x80, 0x50, 0x00, 0x00, 0x00, 0x10,
4466 /* 519 */ 0x08, 0x22, 0x20,
4467 /* 522 */ 0x00, 0x00, 0x00, 0x00, 0x08,
4468 /* 527 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4469 /* 556 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4470 /* 575 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
4471 /* 611 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
4472 /* 647 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
4473 /* 683 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
4474 /* 719 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
4475 /* 755 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
4476 /* 791 */ 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
4477 /* 836 */ 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
4478 /* 881 */ 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
4479 /* 926 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4480 /* 955 */ 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
4481 /* 1000 */ 0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
4482 /* 1045 */ 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4483 /* 1067 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4484 /* 1080 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4485 /* 1099 */ 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4486 /* 1121 */ 0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4487 /* 1143 */ 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10,
4488 /* 1150 */ 0x00, 0x00, 0xc0, 0x0f, 0x03,
4489 /* 1155 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4490 /* 1182 */ 0x00, 0x00, 0xc0, 0x0f, 0x01,
4491 /* 1187 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
4492 /* 1201 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
4493 /* 1228 */ 0x00, 0x00, 0x40, 0x0b,
4494 /* 1232 */ 0x00, 0x00, 0x40, 0x0a, 0x02,
4495 /* 1237 */ 0x00, 0x00, 0x40, 0x0a,
4496 /* 1241 */ 0x00, 0x00, 0x40, 0x08,
4497 /* 1245 */ 0x00, 0x00, 0x00, 0x0a,
4498 /* 1249 */ 0x00, 0x00, 0x80, 0x00, 0x02,
4499 /* 1254 */ 0x00, 0x00, 0x00, 0x01, 0x01,
4500 /* 1259 */ 0x00, 0x00, 0x00, 0x03,
4501 /* 1263 */ 0x00, 0x00, 0x00, 0x0a,
4502 /* 1267 */ 0x00, 0x00, 0x80, 0x04,
4503 /* 1271 */ 0x00, 0x00, 0x00, 0x04, 0x01,
4504 /* 1276 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
4505 /* 1284 */ 0x00, 0x00, 0x00, 0x10,
4506 /* 1288 */ 0x00, 0x40,
4507 /* 1290 */ 0x00, 0x00, 0x00, 0x01,
4508 /* 1294 */ 0x00, 0x00, 0x00, 0x08,
4509 /* 1298 */ 0x00, 0x00, 0x00, 0x02,
4510 /* 1302 */ 0x00, 0x00, 0x80,
4511 /* 1305 */ 0x00, 0x00, 0x00, 0x00, 0x02,
4512 /* 1310 */ 0x00, 0x00, 0x00, 0x00, 0x01,
4513 /* 1315 */ 0x00, 0x00, 0x00, 0x04,
4514 /* 1319 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
4515 /* 1326 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
4516 /* 1334 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
4517 /* 1348 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
4518 /* 1387 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4519 /* 1416 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
4520 /* 1455 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
4521 /* 1494 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4522 /* 1510 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4523 /* 1521 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4524 /* 1540 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4525 /* 1556 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4526 /* 1572 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x79,
4527 /* 1588 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
4528 /* 1604 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35,
4529 /* 1612 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
4530 /* 1628 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
4531 /* 1644 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
4532 /* 1660 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
4533 /* 1676 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
4534 /* 1692 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31,
4535 /* 1700 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4536 /* 1727 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4537 /* 1742 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
4538 /* 1758 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
4539 /* 1774 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11,
4540 /* 1782 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35,
4541 /* 1790 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
4542 /* 1806 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
4543 /* 1833 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
4544 /* 1849 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31,
4545 /* 1857 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
4546 /* 1873 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11,
4547 /* 1881 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25,
4548 /* 1889 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0x01,
4549 /* 1897 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21,
4550 /* 1905 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01,
4551 /* 1913 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01,
4552 /* 1921 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,
4553 /* 1937 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
4554 /* 1945 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01,
4555 /* 1953 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x20,
4556 /* 1961 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x10,
4557 /* 1969 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
4558 /* 1976 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90,
4559 /* 1983 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10,
4560 /* 1991 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
4561 /* 1998 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
4562 /* 2014 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
4563 /* 2022 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
4564 /* 2029 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
4565 /* 2037 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
4566 /* 2044 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
4567 /* 2051 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
4568 /* 2059 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
4569 /* 2067 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
4570 /* 2074 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4571 /* 2091 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
4572 /* 2105 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
4573 /* 2119 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4574 /* 2148 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4575 /* 2167 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x80, 0xff, 0x7f,
4576 /* 2198 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4577 /* 2224 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
4578 /* 2259 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4579 /* 2292 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
4580 },
4581 .SubClassMasks: {
4582 // 0 GR8
4583 0x0000003d, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4584 0x00200380, 0xc7ff2f3a, 0x72e38c3f, 0x1fdfefbd, 0x00000000, // sub_8bit
4585 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
4586 // 15 GRH8
4587 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4588 // 20 GR8_NOREX2
4589 0x0000003c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4590 0x00200300, 0xc7ff2f20, 0x72e3803f, 0x1fdfefbd, 0x00000000, // sub_8bit
4591 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
4592 // 35 GR8_NOREX
4593 0x00000038, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4594 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit
4595 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
4596 // 50 GR8_ABCD_H
4597 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4598 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
4599 // 60 GR8_ABCD_L
4600 0x00000020, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4601 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit
4602 // 70 GRH16
4603 0x00000040, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4604 // 75 GR16
4605 0x00200380, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4606 0x00000000, 0xc7ff2f3a, 0x72e38c3f, 0x1fdfefbd, 0x00000000, // sub_16bit
4607 // 85 GR16_NOREX2
4608 0x00200300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4609 0x00000000, 0xc7ff2f20, 0x72e3803f, 0x1fdfefbd, 0x00000000, // sub_16bit
4610 // 95 GR16_NOREX
4611 0x00200200, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4612 0x00000000, 0xc7ff2c00, 0x4200003f, 0x1fcfe7a8, 0x00000000, // sub_16bit
4613 // 105 VK1
4614 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
4615 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4616 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4617 // 120 VK16
4618 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
4619 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4620 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4621 // 135 VK2
4622 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
4623 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4624 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4625 // 150 VK4
4626 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
4627 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4628 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4629 // 165 VK8
4630 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
4631 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4632 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4633 // 180 VK16WM
4634 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
4635 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4636 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4637 // 195 VK1WM
4638 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
4639 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4640 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4641 // 210 VK2WM
4642 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
4643 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4644 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4645 // 225 VK4WM
4646 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
4647 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4648 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4649 // 240 VK8WM
4650 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
4651 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4652 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4653 // 255 SEGMENT_REG
4654 0x00100000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4655 // 260 GR16_ABCD
4656 0x00200000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4657 0x00000000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_16bit
4658 // 270 FPCCR
4659 0x00400000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4660 // 275 FR16X
4661 0x01800000, 0x00000084, 0x00004200, 0x00000000, 0x00000003,
4662 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
4663 // 285 FR16
4664 0x01000000, 0x00000080, 0x00004000, 0x00000000, 0x00000002,
4665 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
4666 // 295 VK16PAIR
4667 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4668 // 300 VK1PAIR
4669 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4670 // 305 VK2PAIR
4671 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4672 // 310 VK4PAIR
4673 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4674 // 315 VK8PAIR
4675 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4676 // 320 VK1PAIR_with_sub_mask_0_in_VK1WM
4677 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4678 // 325 LOW32_ADDR_ACCESS_RBP
4679 0x80000000, 0xcfff2f3b, 0x0000007f, 0x02201000, 0x00000000,
4680 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
4681 // 335 LOW32_ADDR_ACCESS
4682 0x00000000, 0xc7ff2b19, 0x0000005f, 0x00200000, 0x00000000,
4683 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
4684 // 345 LOW32_ADDR_ACCESS_RBP_with_sub_8bit
4685 0x00000000, 0xc7ff2f3a, 0x0000003f, 0x02000000, 0x00000000,
4686 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
4687 // 355 FR32X
4688 0x00000000, 0x00000084, 0x00004200, 0x00000000, 0x00000003,
4689 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
4690 // 365 GR32
4691 0x00000000, 0xc7ff2b18, 0x0000001f, 0x00000000, 0x00000000,
4692 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
4693 // 375 GR32_NOSP
4694 0x00000000, 0xc7dd2210, 0x0000001b, 0x00000000, 0x00000000,
4695 0x00000000, 0x00000000, 0x70430820, 0x1bdfaeb4, 0x00000000, // sub_32bit
4696 // 385 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
4697 0x00000000, 0xc7ff2f20, 0x0000003f, 0x02000000, 0x00000000,
4698 0x00000000, 0x00000000, 0x72e38020, 0x1fdfefbd, 0x00000000, // sub_32bit
4699 // 395 DEBUG_REG
4700 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00000000,
4701 // 400 FR32
4702 0x00000000, 0x00000080, 0x00004000, 0x00000000, 0x00000002,
4703 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
4704 // 410 GR32_NOREX2
4705 0x00000000, 0xc7ff2b00, 0x0000001f, 0x00000000, 0x00000000,
4706 0x00000000, 0x00000000, 0x72e38020, 0x1fdfefbd, 0x00000000, // sub_32bit
4707 // 420 GR32_NOREX2_NOSP
4708 0x00000000, 0xc7dd2200, 0x0000001b, 0x00000000, 0x00000000,
4709 0x00000000, 0x00000000, 0x70430020, 0x1bdfaeb4, 0x00000000, // sub_32bit
4710 // 430 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
4711 0x00000000, 0xc7ff2c00, 0x0000003f, 0x02000000, 0x00000000,
4712 0x00000000, 0x00000000, 0x42000020, 0x1fcfe7a8, 0x00000000, // sub_32bit
4713 // 440 GR32_NOREX
4714 0x00000000, 0xc7ff2800, 0x0000001f, 0x00000000, 0x00000000,
4715 0x00000000, 0x00000000, 0x42000020, 0x1fcfe7a8, 0x00000000, // sub_32bit
4716 // 450 VK32
4717 0x00000000, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
4718 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4719 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4720 // 465 GR32_NOREX_NOSP
4721 0x00000000, 0xc7dd2000, 0x0000001b, 0x00000000, 0x00000000,
4722 0x00000000, 0x00000000, 0x40000020, 0x1bcfa6a0, 0x00000000, // sub_32bit
4723 // 475 RFP32
4724 0x00000000, 0x00004000, 0x00000080, 0x40000000, 0x00000000,
4725 // 480 VK32WM
4726 0x00000000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
4727 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4728 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4729 // 495 GR32_ABCD
4730 0x00000000, 0xc19d0000, 0x00000001, 0x00000000, 0x00000000,
4731 0x00000000, 0x00000000, 0x00000000, 0x01c92680, 0x00000000, // sub_32bit
4732 // 505 GR32_TC
4733 0x00000000, 0x811e0000, 0x00000005, 0x00000000, 0x00000000,
4734 0x00000000, 0x00000000, 0x00000000, 0x05882700, 0x00000000, // sub_32bit
4735 // 515 GR32_ABCD_and_GR32_TC
4736 0x00000000, 0x811c0000, 0x00000001, 0x00000000, 0x00000000,
4737 0x00000000, 0x00000000, 0x00000000, 0x01882600, 0x00000000, // sub_32bit
4738 // 525 GR32_AD
4739 0x00000000, 0x80080000, 0x00000000, 0x00000000, 0x00000000,
4740 0x00000000, 0x00000000, 0x00000000, 0x00880400, 0x00000000, // sub_32bit
4741 // 535 GR32_ArgRef
4742 0x00000000, 0x81100000, 0x00000001, 0x00000000, 0x00000000,
4743 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000, // sub_32bit
4744 // 545 GR32_BPSP
4745 0x00000000, 0x00200000, 0x00000006, 0x00000000, 0x00000000,
4746 0x00000000, 0x00000000, 0x00000020, 0x06004000, 0x00000000, // sub_32bit
4747 // 555 GR32_BSI
4748 0x00000000, 0x40400000, 0x00000008, 0x00000000, 0x00000000,
4749 0x00000000, 0x00000000, 0x00000000, 0x08408000, 0x00000000, // sub_32bit
4750 // 565 GR32_CB
4751 0x00000000, 0x40800000, 0x00000001, 0x00000000, 0x00000000,
4752 0x00000000, 0x00000000, 0x00000000, 0x01410000, 0x00000000, // sub_32bit
4753 // 575 GR32_DC
4754 0x00000000, 0x81000000, 0x00000001, 0x00000000, 0x00000000,
4755 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000, // sub_32bit
4756 // 585 GR32_DIBP
4757 0x00000000, 0x02000000, 0x00000012, 0x00000000, 0x00000000,
4758 0x00000000, 0x00000000, 0x00000020, 0x12020000, 0x00000000, // sub_32bit
4759 // 595 GR32_SIDI
4760 0x00000000, 0x04000000, 0x00000018, 0x00000000, 0x00000000,
4761 0x00000000, 0x00000000, 0x00000000, 0x18040000, 0x00000000, // sub_32bit
4762 // 605 LOW32_ADDR_ACCESS_RBP_with_sub_32bit
4763 0x00000000, 0x08000000, 0x00000060, 0x02201000, 0x00000000,
4764 // 610 CCR
4765 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000,
4766 // 615 DFCCR
4767 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000,
4768 // 620 GR32_ABCD_and_GR32_BSI
4769 0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000,
4770 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000, // sub_32bit
4771 // 630 GR32_AD_and_GR32_ArgRef
4772 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000,
4773 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000, // sub_32bit
4774 // 640 GR32_ArgRef_and_GR32_CB
4775 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
4776 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000, // sub_32bit
4777 // 650 GR32_BPSP_and_GR32_DIBP
4778 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000,
4779 0x00000000, 0x00000000, 0x00000020, 0x02000000, 0x00000000, // sub_32bit
4780 // 660 GR32_BPSP_and_GR32_TC
4781 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000,
4782 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000, // sub_32bit
4783 // 670 GR32_BSI_and_GR32_SIDI
4784 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000,
4785 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000, // sub_32bit
4786 // 680 GR32_DIBP_and_GR32_SIDI
4787 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000,
4788 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000, // sub_32bit
4789 // 690 LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
4790 0x00000000, 0x00000000, 0x00000020, 0x02000000, 0x00000000,
4791 // 695 LOW32_ADDR_ACCESS_with_sub_32bit
4792 0x00000000, 0x00000000, 0x00000040, 0x00200000, 0x00000000,
4793 // 700 RFP64
4794 0x00000000, 0x00000000, 0x00000080, 0x40000000, 0x00000000,
4795 // 705 GR64
4796 0x00000000, 0x00000000, 0xf3ff9d00, 0x1ffffffd, 0x00000000,
4797 // 710 FR64X
4798 0x00000000, 0x00000000, 0x00004200, 0x00000000, 0x00000003,
4799 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
4800 // 720 GR64_with_sub_8bit
4801 0x00000000, 0x00000000, 0x72e38c00, 0x1fdfefbd, 0x00000000,
4802 // 725 GR64_NOSP
4803 0x00000000, 0x00000000, 0x70430800, 0x1bdfaeb4, 0x00000000,
4804 // 730 GR64_NOREX2
4805 0x00000000, 0x00000000, 0xf3ff9000, 0x1ffffffd, 0x00000000,
4806 // 735 CONTROL_REG
4807 0x00000000, 0x00000000, 0x00002000, 0x00000000, 0x00000000,
4808 // 740 FR64
4809 0x00000000, 0x00000000, 0x00004000, 0x00000000, 0x00000002,
4810 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
4811 // 750 GR64_with_sub_16bit_in_GR16_NOREX2
4812 0x00000000, 0x00000000, 0x72e38000, 0x1fdfefbd, 0x00000000,
4813 // 755 GR64_NOREX2_NOSP
4814 0x00000000, 0x00000000, 0x70430000, 0x1bdfaeb4, 0x00000000,
4815 // 760 GR64PLTSafe
4816 0x00000000, 0x00000000, 0x50020000, 0x1bcfa6b0, 0x00000000,
4817 // 765 GR64_TC
4818 0x00000000, 0x00000000, 0x91640000, 0x1dbc277d, 0x00000000,
4819 // 770 GR64_NOREX
4820 0x00000000, 0x00000000, 0xc2080000, 0x1feff7e8, 0x00000000,
4821 // 775 GR64_TCW64
4822 0x00000000, 0x00000000, 0x21900000, 0x05b82f55, 0x00000000,
4823 // 780 GR64_TC_with_sub_8bit
4824 0x00000000, 0x00000000, 0x10600000, 0x1d9c273d, 0x00000000,
4825 // 785 GR64_NOREX2_NOSP_and_GR64_TC
4826 0x00000000, 0x00000000, 0x10400000, 0x199c2634, 0x00000000,
4827 // 790 GR64_TCW64_with_sub_8bit
4828 0x00000000, 0x00000000, 0x20800000, 0x05982f15, 0x00000000,
4829 // 795 GR64_TC_and_GR64_TCW64
4830 0x00000000, 0x00000000, 0x01000000, 0x05b82755, 0x00000000,
4831 // 800 GR64_with_sub_16bit_in_GR16_NOREX
4832 0x00000000, 0x00000000, 0x42000000, 0x1fcfe7a8, 0x00000000,
4833 // 805 VK64
4834 0x00000000, 0x00000000, 0x04000000, 0x00000002, 0x00000000,
4835 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4836 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4837 // 820 VR64
4838 0x00000000, 0x00000000, 0x08000000, 0x00000000, 0x00000000,
4839 // 825 GR64PLTSafe_and_GR64_TC
4840 0x00000000, 0x00000000, 0x10000000, 0x198c2630, 0x00000000,
4841 // 830 GR64_NOREX2_NOSP_and_GR64_TCW64
4842 0x00000000, 0x00000000, 0x20000000, 0x01982e14, 0x00000000,
4843 // 835 GR64_NOREX_NOSP
4844 0x00000000, 0x00000000, 0x40000000, 0x1bcfa6a0, 0x00000000,
4845 // 840 GR64_NOREX_and_GR64_TC
4846 0x00000000, 0x00000000, 0x80000000, 0x1dac2768, 0x00000000,
4847 // 845 GR64_TCW64_and_GR64_TC_with_sub_8bit
4848 0x00000000, 0x00000000, 0x00000000, 0x05982715, 0x00000000,
4849 // 850 VK64WM
4850 0x00000000, 0x00000000, 0x00000000, 0x00000002, 0x00000000,
4851 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4852 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4853 // 865 GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
4854 0x00000000, 0x00000000, 0x00000000, 0x01982614, 0x00000000,
4855 // 870 GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
4856 0x00000000, 0x00000000, 0x00000000, 0x1d8c2728, 0x00000000,
4857 // 875 GR64PLTSafe_and_GR64_TCW64
4858 0x00000000, 0x00000000, 0x00000000, 0x01882610, 0x00000000,
4859 // 880 GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
4860 0x00000000, 0x00000000, 0x00000000, 0x198c2620, 0x00000000,
4861 // 885 GR64_NOREX_and_GR64_TCW64
4862 0x00000000, 0x00000000, 0x00000000, 0x05a82740, 0x00000000,
4863 // 890 GR64_ABCD
4864 0x00000000, 0x00000000, 0x00000000, 0x01c92680, 0x00000000,
4865 // 895 GR64_with_sub_32bit_in_GR32_TC
4866 0x00000000, 0x00000000, 0x00000000, 0x05882700, 0x00000000,
4867 // 900 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
4868 0x00000000, 0x00000000, 0x00000000, 0x01882600, 0x00000000,
4869 // 905 GR64_AD
4870 0x00000000, 0x00000000, 0x00000000, 0x00880400, 0x00000000,
4871 // 910 GR64_ArgRef
4872 0x00000000, 0x00000000, 0x00000000, 0x00100800, 0x00000000,
4873 // 915 GR64_and_LOW32_ADDR_ACCESS_RBP
4874 0x00000000, 0x00000000, 0x00000000, 0x02201000, 0x00000000,
4875 // 920 GR64_with_sub_32bit_in_GR32_ArgRef
4876 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000,
4877 // 925 GR64_with_sub_32bit_in_GR32_BPSP
4878 0x00000000, 0x00000000, 0x00000000, 0x06004000, 0x00000000,
4879 // 930 GR64_with_sub_32bit_in_GR32_BSI
4880 0x00000000, 0x00000000, 0x00000000, 0x08408000, 0x00000000,
4881 // 935 GR64_with_sub_32bit_in_GR32_CB
4882 0x00000000, 0x00000000, 0x00000000, 0x01410000, 0x00000000,
4883 // 940 GR64_with_sub_32bit_in_GR32_DIBP
4884 0x00000000, 0x00000000, 0x00000000, 0x12020000, 0x00000000,
4885 // 945 GR64_with_sub_32bit_in_GR32_SIDI
4886 0x00000000, 0x00000000, 0x00000000, 0x18040000, 0x00000000,
4887 // 950 GR64_A
4888 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000,
4889 // 955 GR64_ArgRef_and_GR64_TC
4890 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00000000,
4891 // 960 GR64_and_LOW32_ADDR_ACCESS
4892 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00000000,
4893 // 965 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
4894 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000,
4895 // 970 GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
4896 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000,
4897 // 975 GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
4898 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000,
4899 // 980 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
4900 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x00000000,
4901 // 985 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
4902 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000,
4903 // 990 GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
4904 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000,
4905 // 995 GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
4906 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000,
4907 // 1000 RST
4908 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000,
4909 // 1005 RFP80
4910 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00000000,
4911 // 1010 RFP80_7
4912 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000000,
4913 // 1015 VR128X
4914 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000003,
4915 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
4916 // 1025 VR128
4917 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002,
4918 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
4919 // 1035 VR256X
4920 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c,
4921 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000030, // sub_ymm
4922 // 1045 VR256
4923 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008,
4924 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_ymm
4925 // 1055 VR512
4926 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000030,
4927 // 1060 VR512_0_15
4928 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020,
4929 // 1065 TILE
4930 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040,
4931 },
4932 .SuperRegIdxSeqs: {
4933 /* 0 */ 1, 0,
4934 /* 2 */ 1, 2, 0,
4935 /* 5 */ 4, 0,
4936 /* 7 */ 6, 0,
4937 /* 9 */ 7, 8, 0,
4938 /* 12 */ 9, 0,
4939 /* 14 */ 10, 0,
4940 },
4941 .SuperClasses: {
4942 /* 0 GR8 */
4943 /* 0 GRH8 */
4944 /* 0 GR8_NOREX2 */ X86::GR8RegClassID,
4945 /* 1 GR8_NOREX */ X86::GR8RegClassID, X86::GR8_NOREX2RegClassID,
4946 /* 3 GR8_ABCD_H */ X86::GR8RegClassID, X86::GR8_NOREX2RegClassID, X86::GR8_NOREXRegClassID,
4947 /* 6 GR8_ABCD_L */ X86::GR8RegClassID, X86::GR8_NOREX2RegClassID, X86::GR8_NOREXRegClassID,
4948 /* 9 GRH16 */
4949 /* 9 GR16 */
4950 /* 9 GR16_NOREX2 */ X86::GR16RegClassID,
4951 /* 10 GR16_NOREX */ X86::GR16RegClassID, X86::GR16_NOREX2RegClassID,
4952 /* 12 VK1 */ X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID,
4953 /* 16 VK16 */ X86::VK1RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID,
4954 /* 20 VK2 */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK4RegClassID, X86::VK8RegClassID,
4955 /* 24 VK4 */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK8RegClassID,
4956 /* 28 VK8 */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID,
4957 /* 32 VK16WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK1WMRegClassID, X86::VK2WMRegClassID, X86::VK4WMRegClassID, X86::VK8WMRegClassID,
4958 /* 41 VK1WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK16WMRegClassID, X86::VK2WMRegClassID, X86::VK4WMRegClassID, X86::VK8WMRegClassID,
4959 /* 50 VK2WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK16WMRegClassID, X86::VK1WMRegClassID, X86::VK4WMRegClassID, X86::VK8WMRegClassID,
4960 /* 59 VK4WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK16WMRegClassID, X86::VK1WMRegClassID, X86::VK2WMRegClassID, X86::VK8WMRegClassID,
4961 /* 68 VK8WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK16WMRegClassID, X86::VK1WMRegClassID, X86::VK2WMRegClassID, X86::VK4WMRegClassID,
4962 /* 77 SEGMENT_REG */
4963 /* 77 GR16_ABCD */ X86::GR16RegClassID, X86::GR16_NOREX2RegClassID, X86::GR16_NOREXRegClassID,
4964 /* 80 FPCCR */
4965 /* 80 FR16X */
4966 /* 80 FR16 */ X86::FR16XRegClassID,
4967 /* 81 VK16PAIR */ X86::VK1PAIRRegClassID, X86::VK2PAIRRegClassID, X86::VK4PAIRRegClassID, X86::VK8PAIRRegClassID,
4968 /* 85 VK1PAIR */ X86::VK16PAIRRegClassID, X86::VK2PAIRRegClassID, X86::VK4PAIRRegClassID, X86::VK8PAIRRegClassID,
4969 /* 89 VK2PAIR */ X86::VK16PAIRRegClassID, X86::VK1PAIRRegClassID, X86::VK4PAIRRegClassID, X86::VK8PAIRRegClassID,
4970 /* 93 VK4PAIR */ X86::VK16PAIRRegClassID, X86::VK1PAIRRegClassID, X86::VK2PAIRRegClassID, X86::VK8PAIRRegClassID,
4971 /* 97 VK8PAIR */ X86::VK16PAIRRegClassID, X86::VK1PAIRRegClassID, X86::VK2PAIRRegClassID, X86::VK4PAIRRegClassID,
4972 /* 101 VK1PAIR_with_sub_mask_0_in_VK1WM */ X86::VK16PAIRRegClassID, X86::VK1PAIRRegClassID, X86::VK2PAIRRegClassID, X86::VK4PAIRRegClassID, X86::VK8PAIRRegClassID,
4973 /* 106 LOW32_ADDR_ACCESS_RBP */
4974 /* 106 LOW32_ADDR_ACCESS */ X86::LOW32_ADDR_ACCESS_RBPRegClassID,
4975 /* 107 LOW32_ADDR_ACCESS_RBP_with_sub_8bit */ X86::LOW32_ADDR_ACCESS_RBPRegClassID,
4976 /* 108 FR32X */ X86::FR16XRegClassID,
4977 /* 109 GR32 */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
4978 /* 112 GR32_NOSP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID,
4979 /* 116 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
4980 /* 118 DEBUG_REG */
4981 /* 118 FR32 */ X86::FR16XRegClassID, X86::FR16RegClassID, X86::FR32XRegClassID,
4982 /* 121 GR32_NOREX2 */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
4983 /* 126 GR32_NOREX2_NOSP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID,
4984 /* 133 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
4985 /* 136 GR32_NOREX */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
4986 /* 143 VK32 */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID,
4987 /* 148 GR32_NOREX_NOSP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID,
4988 /* 158 RFP32 */
4989 /* 158 VK32WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK16WMRegClassID, X86::VK1WMRegClassID, X86::VK2WMRegClassID, X86::VK4WMRegClassID, X86::VK8WMRegClassID, X86::VK32RegClassID,
4990 /* 169 GR32_ABCD */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID,
4991 /* 180 GR32_TC */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID,
4992 /* 188 GR32_ABCD_and_GR32_TC */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_TCRegClassID,
4993 /* 201 GR32_AD */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_TCRegClassID, X86::GR32_ABCD_and_GR32_TCRegClassID,
4994 /* 215 GR32_ArgRef */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_TCRegClassID, X86::GR32_ABCD_and_GR32_TCRegClassID,
4995 /* 229 GR32_BPSP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID,
4996 /* 237 GR32_BSI */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID,
4997 /* 248 GR32_CB */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID,
4998 /* 260 GR32_DC */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_TCRegClassID, X86::GR32_ABCD_and_GR32_TCRegClassID, X86::GR32_ArgRefRegClassID,
4999 /* 275 GR32_DIBP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID,
5000 /* 286 GR32_SIDI */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID,
5001 /* 297 LOW32_ADDR_ACCESS_RBP_with_sub_32bit */ X86::LOW32_ADDR_ACCESS_RBPRegClassID,
5002 /* 298 CCR */
5003 /* 298 DFCCR */
5004 /* 298 GR32_ABCD_and_GR32_BSI */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_BSIRegClassID, X86::GR32_CBRegClassID,
5005 /* 312 GR32_AD_and_GR32_ArgRef */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_TCRegClassID, X86::GR32_ABCD_and_GR32_TCRegClassID, X86::GR32_ADRegClassID, X86::GR32_ArgRefRegClassID, X86::GR32_DCRegClassID,
5006 /* 329 GR32_ArgRef_and_GR32_CB */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_TCRegClassID, X86::GR32_ABCD_and_GR32_TCRegClassID, X86::GR32_ArgRefRegClassID, X86::GR32_CBRegClassID, X86::GR32_DCRegClassID,
5007 /* 346 GR32_BPSP_and_GR32_DIBP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_BPSPRegClassID, X86::GR32_DIBPRegClassID,
5008 /* 359 GR32_BPSP_and_GR32_TC */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_TCRegClassID, X86::GR32_BPSPRegClassID,
5009 /* 369 GR32_BSI_and_GR32_SIDI */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_BSIRegClassID, X86::GR32_SIDIRegClassID,
5010 /* 382 GR32_DIBP_and_GR32_SIDI */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_DIBPRegClassID, X86::GR32_SIDIRegClassID,
5011 /* 395 LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
5012 /* 400 LOW32_ADDR_ACCESS_with_sub_32bit */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
5013 /* 403 RFP64 */ X86::RFP32RegClassID,
5014 /* 404 GR64 */
5015 /* 404 FR64X */ X86::FR16XRegClassID, X86::FR32XRegClassID,
5016 /* 406 GR64_with_sub_8bit */ X86::GR64RegClassID,
5017 /* 407 GR64_NOSP */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID,
5018 /* 409 GR64_NOREX2 */ X86::GR64RegClassID,
5019 /* 410 CONTROL_REG */
5020 /* 410 FR64 */ X86::FR16XRegClassID, X86::FR16RegClassID, X86::FR32XRegClassID, X86::FR32RegClassID, X86::FR64XRegClassID,
5021 /* 415 GR64_with_sub_16bit_in_GR16_NOREX2 */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID,
5022 /* 418 GR64_NOREX2_NOSP */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
5023 /* 423 GR64PLTSafe */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID,
5024 /* 429 GR64_TC */ X86::GR64RegClassID, X86::GR64_NOREX2RegClassID,
5025 /* 431 GR64_NOREX */ X86::GR64RegClassID, X86::GR64_NOREX2RegClassID,
5026 /* 433 GR64_TCW64 */ X86::GR64RegClassID, X86::GR64_NOREX2RegClassID,
5027 /* 435 GR64_TC_with_sub_8bit */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_TCRegClassID,
5028 /* 440 GR64_NOREX2_NOSP_and_GR64_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64_TCRegClassID, X86::GR64_TC_with_sub_8bitRegClassID,
5029 /* 448 GR64_TCW64_with_sub_8bit */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_TCW64RegClassID,
5030 /* 453 GR64_TC_and_GR64_TCW64 */ X86::GR64RegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_TCW64RegClassID,
5031 /* 457 GR64_with_sub_16bit_in_GR16_NOREX */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREXRegClassID,
5032 /* 462 VK64 */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK32RegClassID,
5033 /* 468 VR64 */
5034 /* 468 GR64PLTSafe_and_GR64_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
5035 /* 478 GR64_NOREX2_NOSP_and_GR64_TCW64 */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID,
5036 /* 486 GR64_NOREX_NOSP */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
5037 /* 495 GR64_NOREX_and_GR64_TC */ X86::GR64RegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID,
5038 /* 499 GR64_TCW64_and_GR64_TC_with_sub_8bit */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID,
5039 /* 508 VK64WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK16WMRegClassID, X86::VK1WMRegClassID, X86::VK2WMRegClassID, X86::VK4WMRegClassID, X86::VK8WMRegClassID, X86::VK32RegClassID, X86::VK32WMRegClassID, X86::VK64RegClassID,
5040 /* 521 GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64_TCRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
5041 /* 535 GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID,
5042 /* 544 GR64PLTSafe_and_GR64_TCW64 */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
5043 /* 561 GR64_NOREX_and_GR64PLTSafe_and_GR64_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
5044 /* 577 GR64_NOREX_and_GR64_TCW64 */ X86::GR64RegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID,
5045 /* 584 GR64_ABCD */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_NOSPRegClassID,
5046 /* 594 GR64_with_sub_32bit_in_GR32_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID,
5047 /* 609 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
5048 /* 636 GR64_AD */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
5049 /* 664 GR64_ArgRef */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
5050 /* 673 GR64_and_LOW32_ADDR_ACCESS_RBP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, X86::GR64RegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_NOREXRegClassID,
5051 /* 678 GR64_with_sub_32bit_in_GR32_ArgRef */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
5052 /* 706 GR64_with_sub_32bit_in_GR32_BPSP */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
5053 /* 712 GR64_with_sub_32bit_in_GR32_BSI */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_NOSPRegClassID,
5054 /* 722 GR64_with_sub_32bit_in_GR32_CB */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_ABCDRegClassID,
5055 /* 733 GR64_with_sub_32bit_in_GR32_DIBP */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_NOSPRegClassID,
5056 /* 743 GR64_with_sub_32bit_in_GR32_SIDI */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
5057 /* 760 GR64_A */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, X86::GR64_ADRegClassID,
5058 /* 789 GR64_ArgRef_and_GR64_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64_TCRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_ArgRefRegClassID,
5059 /* 805 GR64_and_LOW32_ADDR_ACCESS */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, X86::GR64RegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
5060 /* 818 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
5061 /* 831 GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, X86::GR64_ADRegClassID, X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
5062 /* 861 GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID, X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
5063 /* 891 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
5064 /* 910 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
5065 /* 927 GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
5066 /* 946 GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
5067 /* 965 RST */
5068 /* 965 RFP80 */ X86::RFP32RegClassID, X86::RFP64RegClassID,
5069 /* 967 RFP80_7 */
5070 /* 967 VR128X */ X86::FR16XRegClassID, X86::FR32XRegClassID, X86::FR64XRegClassID,
5071 /* 970 VR128 */ X86::FR16XRegClassID, X86::FR16RegClassID, X86::FR32XRegClassID, X86::FR32RegClassID, X86::FR64XRegClassID, X86::FR64RegClassID, X86::VR128XRegClassID,
5072 /* 977 VR256X */
5073 /* 977 VR256 */ X86::VR256XRegClassID,
5074 /* 978 VR512 */
5075 /* 978 VR512_0_15 */ X86::VR512RegClassID,
5076 /* 979 TILE */
5077 }
5078};
5079
5080const MCRegisterClass &getX86MCRegisterClass(unsigned RC) {
5081 return X86MCRegisterClassStorage.Classes[RC];
5082}
5083
5084// X86 Dwarf<->LLVM register mappings.
5085extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
5086 { .FromReg: 0U, .ToReg: X86::RAX },
5087 { .FromReg: 1U, .ToReg: X86::RDX },
5088 { .FromReg: 2U, .ToReg: X86::RCX },
5089 { .FromReg: 3U, .ToReg: X86::RBX },
5090 { .FromReg: 4U, .ToReg: X86::RSI },
5091 { .FromReg: 5U, .ToReg: X86::RDI },
5092 { .FromReg: 6U, .ToReg: X86::RBP },
5093 { .FromReg: 7U, .ToReg: X86::RSP },
5094 { .FromReg: 8U, .ToReg: X86::R8 },
5095 { .FromReg: 9U, .ToReg: X86::R9 },
5096 { .FromReg: 10U, .ToReg: X86::R10 },
5097 { .FromReg: 11U, .ToReg: X86::R11 },
5098 { .FromReg: 12U, .ToReg: X86::R12 },
5099 { .FromReg: 13U, .ToReg: X86::R13 },
5100 { .FromReg: 14U, .ToReg: X86::R14 },
5101 { .FromReg: 15U, .ToReg: X86::R15 },
5102 { .FromReg: 16U, .ToReg: X86::RIP },
5103 { .FromReg: 17U, .ToReg: X86::XMM0 },
5104 { .FromReg: 18U, .ToReg: X86::XMM1 },
5105 { .FromReg: 19U, .ToReg: X86::XMM2 },
5106 { .FromReg: 20U, .ToReg: X86::XMM3 },
5107 { .FromReg: 21U, .ToReg: X86::XMM4 },
5108 { .FromReg: 22U, .ToReg: X86::XMM5 },
5109 { .FromReg: 23U, .ToReg: X86::XMM6 },
5110 { .FromReg: 24U, .ToReg: X86::XMM7 },
5111 { .FromReg: 25U, .ToReg: X86::XMM8 },
5112 { .FromReg: 26U, .ToReg: X86::XMM9 },
5113 { .FromReg: 27U, .ToReg: X86::XMM10 },
5114 { .FromReg: 28U, .ToReg: X86::XMM11 },
5115 { .FromReg: 29U, .ToReg: X86::XMM12 },
5116 { .FromReg: 30U, .ToReg: X86::XMM13 },
5117 { .FromReg: 31U, .ToReg: X86::XMM14 },
5118 { .FromReg: 32U, .ToReg: X86::XMM15 },
5119 { .FromReg: 33U, .ToReg: X86::ST0 },
5120 { .FromReg: 34U, .ToReg: X86::ST1 },
5121 { .FromReg: 35U, .ToReg: X86::ST2 },
5122 { .FromReg: 36U, .ToReg: X86::ST3 },
5123 { .FromReg: 37U, .ToReg: X86::ST4 },
5124 { .FromReg: 38U, .ToReg: X86::ST5 },
5125 { .FromReg: 39U, .ToReg: X86::ST6 },
5126 { .FromReg: 40U, .ToReg: X86::ST7 },
5127 { .FromReg: 41U, .ToReg: X86::MM0 },
5128 { .FromReg: 42U, .ToReg: X86::MM1 },
5129 { .FromReg: 43U, .ToReg: X86::MM2 },
5130 { .FromReg: 44U, .ToReg: X86::MM3 },
5131 { .FromReg: 45U, .ToReg: X86::MM4 },
5132 { .FromReg: 46U, .ToReg: X86::MM5 },
5133 { .FromReg: 47U, .ToReg: X86::MM6 },
5134 { .FromReg: 48U, .ToReg: X86::MM7 },
5135 { .FromReg: 49U, .ToReg: X86::RFLAGS },
5136 { .FromReg: 50U, .ToReg: X86::ES },
5137 { .FromReg: 51U, .ToReg: X86::CS },
5138 { .FromReg: 52U, .ToReg: X86::SS },
5139 { .FromReg: 53U, .ToReg: X86::DS },
5140 { .FromReg: 54U, .ToReg: X86::FS },
5141 { .FromReg: 55U, .ToReg: X86::GS },
5142 { .FromReg: 58U, .ToReg: X86::FS_BASE },
5143 { .FromReg: 59U, .ToReg: X86::GS_BASE },
5144 { .FromReg: 67U, .ToReg: X86::XMM16 },
5145 { .FromReg: 68U, .ToReg: X86::XMM17 },
5146 { .FromReg: 69U, .ToReg: X86::XMM18 },
5147 { .FromReg: 70U, .ToReg: X86::XMM19 },
5148 { .FromReg: 71U, .ToReg: X86::XMM20 },
5149 { .FromReg: 72U, .ToReg: X86::XMM21 },
5150 { .FromReg: 73U, .ToReg: X86::XMM22 },
5151 { .FromReg: 74U, .ToReg: X86::XMM23 },
5152 { .FromReg: 75U, .ToReg: X86::XMM24 },
5153 { .FromReg: 76U, .ToReg: X86::XMM25 },
5154 { .FromReg: 77U, .ToReg: X86::XMM26 },
5155 { .FromReg: 78U, .ToReg: X86::XMM27 },
5156 { .FromReg: 79U, .ToReg: X86::XMM28 },
5157 { .FromReg: 80U, .ToReg: X86::XMM29 },
5158 { .FromReg: 81U, .ToReg: X86::XMM30 },
5159 { .FromReg: 82U, .ToReg: X86::XMM31 },
5160 { .FromReg: 118U, .ToReg: X86::K0 },
5161 { .FromReg: 119U, .ToReg: X86::K1 },
5162 { .FromReg: 120U, .ToReg: X86::K2 },
5163 { .FromReg: 121U, .ToReg: X86::K3 },
5164 { .FromReg: 122U, .ToReg: X86::K4 },
5165 { .FromReg: 123U, .ToReg: X86::K5 },
5166 { .FromReg: 124U, .ToReg: X86::K6 },
5167 { .FromReg: 125U, .ToReg: X86::K7 },
5168 { .FromReg: 130U, .ToReg: X86::R16 },
5169 { .FromReg: 131U, .ToReg: X86::R17 },
5170 { .FromReg: 132U, .ToReg: X86::R18 },
5171 { .FromReg: 133U, .ToReg: X86::R19 },
5172 { .FromReg: 134U, .ToReg: X86::R20 },
5173 { .FromReg: 135U, .ToReg: X86::R21 },
5174 { .FromReg: 136U, .ToReg: X86::R22 },
5175 { .FromReg: 137U, .ToReg: X86::R23 },
5176 { .FromReg: 138U, .ToReg: X86::R24 },
5177 { .FromReg: 139U, .ToReg: X86::R25 },
5178 { .FromReg: 140U, .ToReg: X86::R26 },
5179 { .FromReg: 141U, .ToReg: X86::R27 },
5180 { .FromReg: 142U, .ToReg: X86::R28 },
5181 { .FromReg: 143U, .ToReg: X86::R29 },
5182 { .FromReg: 144U, .ToReg: X86::R30 },
5183 { .FromReg: 145U, .ToReg: X86::R31 },
5184};
5185extern const unsigned X86DwarfFlavour0Dwarf2LSize = std::size(X86DwarfFlavour0Dwarf2L);
5186
5187extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
5188 { .FromReg: 0U, .ToReg: X86::EAX },
5189 { .FromReg: 1U, .ToReg: X86::ECX },
5190 { .FromReg: 2U, .ToReg: X86::EDX },
5191 { .FromReg: 3U, .ToReg: X86::EBX },
5192 { .FromReg: 4U, .ToReg: X86::EBP },
5193 { .FromReg: 5U, .ToReg: X86::ESP },
5194 { .FromReg: 6U, .ToReg: X86::ESI },
5195 { .FromReg: 7U, .ToReg: X86::EDI },
5196 { .FromReg: 8U, .ToReg: X86::EIP },
5197 { .FromReg: 9U, .ToReg: X86::EFLAGS },
5198 { .FromReg: 12U, .ToReg: X86::ST0 },
5199 { .FromReg: 13U, .ToReg: X86::ST1 },
5200 { .FromReg: 14U, .ToReg: X86::ST2 },
5201 { .FromReg: 15U, .ToReg: X86::ST3 },
5202 { .FromReg: 16U, .ToReg: X86::ST4 },
5203 { .FromReg: 17U, .ToReg: X86::ST5 },
5204 { .FromReg: 18U, .ToReg: X86::ST6 },
5205 { .FromReg: 19U, .ToReg: X86::ST7 },
5206 { .FromReg: 21U, .ToReg: X86::XMM0 },
5207 { .FromReg: 22U, .ToReg: X86::XMM1 },
5208 { .FromReg: 23U, .ToReg: X86::XMM2 },
5209 { .FromReg: 24U, .ToReg: X86::XMM3 },
5210 { .FromReg: 25U, .ToReg: X86::XMM4 },
5211 { .FromReg: 26U, .ToReg: X86::XMM5 },
5212 { .FromReg: 27U, .ToReg: X86::XMM6 },
5213 { .FromReg: 28U, .ToReg: X86::XMM7 },
5214 { .FromReg: 29U, .ToReg: X86::MM0 },
5215 { .FromReg: 30U, .ToReg: X86::MM1 },
5216 { .FromReg: 31U, .ToReg: X86::MM2 },
5217 { .FromReg: 32U, .ToReg: X86::MM3 },
5218 { .FromReg: 33U, .ToReg: X86::MM4 },
5219 { .FromReg: 34U, .ToReg: X86::MM5 },
5220 { .FromReg: 35U, .ToReg: X86::MM6 },
5221 { .FromReg: 36U, .ToReg: X86::MM7 },
5222 { .FromReg: 93U, .ToReg: X86::K0 },
5223 { .FromReg: 94U, .ToReg: X86::K1 },
5224 { .FromReg: 95U, .ToReg: X86::K2 },
5225 { .FromReg: 96U, .ToReg: X86::K3 },
5226 { .FromReg: 97U, .ToReg: X86::K4 },
5227 { .FromReg: 98U, .ToReg: X86::K5 },
5228 { .FromReg: 99U, .ToReg: X86::K6 },
5229 { .FromReg: 100U, .ToReg: X86::K7 },
5230};
5231extern const unsigned X86DwarfFlavour1Dwarf2LSize = std::size(X86DwarfFlavour1Dwarf2L);
5232
5233extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
5234 { .FromReg: 0U, .ToReg: X86::EAX },
5235 { .FromReg: 1U, .ToReg: X86::ECX },
5236 { .FromReg: 2U, .ToReg: X86::EDX },
5237 { .FromReg: 3U, .ToReg: X86::EBX },
5238 { .FromReg: 4U, .ToReg: X86::ESP },
5239 { .FromReg: 5U, .ToReg: X86::EBP },
5240 { .FromReg: 6U, .ToReg: X86::ESI },
5241 { .FromReg: 7U, .ToReg: X86::EDI },
5242 { .FromReg: 8U, .ToReg: X86::EIP },
5243 { .FromReg: 9U, .ToReg: X86::EFLAGS },
5244 { .FromReg: 11U, .ToReg: X86::ST0 },
5245 { .FromReg: 12U, .ToReg: X86::ST1 },
5246 { .FromReg: 13U, .ToReg: X86::ST2 },
5247 { .FromReg: 14U, .ToReg: X86::ST3 },
5248 { .FromReg: 15U, .ToReg: X86::ST4 },
5249 { .FromReg: 16U, .ToReg: X86::ST5 },
5250 { .FromReg: 17U, .ToReg: X86::ST6 },
5251 { .FromReg: 18U, .ToReg: X86::ST7 },
5252 { .FromReg: 21U, .ToReg: X86::XMM0 },
5253 { .FromReg: 22U, .ToReg: X86::XMM1 },
5254 { .FromReg: 23U, .ToReg: X86::XMM2 },
5255 { .FromReg: 24U, .ToReg: X86::XMM3 },
5256 { .FromReg: 25U, .ToReg: X86::XMM4 },
5257 { .FromReg: 26U, .ToReg: X86::XMM5 },
5258 { .FromReg: 27U, .ToReg: X86::XMM6 },
5259 { .FromReg: 28U, .ToReg: X86::XMM7 },
5260 { .FromReg: 29U, .ToReg: X86::MM0 },
5261 { .FromReg: 30U, .ToReg: X86::MM1 },
5262 { .FromReg: 31U, .ToReg: X86::MM2 },
5263 { .FromReg: 32U, .ToReg: X86::MM3 },
5264 { .FromReg: 33U, .ToReg: X86::MM4 },
5265 { .FromReg: 34U, .ToReg: X86::MM5 },
5266 { .FromReg: 35U, .ToReg: X86::MM6 },
5267 { .FromReg: 36U, .ToReg: X86::MM7 },
5268 { .FromReg: 40U, .ToReg: X86::ES },
5269 { .FromReg: 41U, .ToReg: X86::CS },
5270 { .FromReg: 42U, .ToReg: X86::SS },
5271 { .FromReg: 43U, .ToReg: X86::DS },
5272 { .FromReg: 44U, .ToReg: X86::FS },
5273 { .FromReg: 45U, .ToReg: X86::GS },
5274 { .FromReg: 93U, .ToReg: X86::K0 },
5275 { .FromReg: 94U, .ToReg: X86::K1 },
5276 { .FromReg: 95U, .ToReg: X86::K2 },
5277 { .FromReg: 96U, .ToReg: X86::K3 },
5278 { .FromReg: 97U, .ToReg: X86::K4 },
5279 { .FromReg: 98U, .ToReg: X86::K5 },
5280 { .FromReg: 99U, .ToReg: X86::K6 },
5281 { .FromReg: 100U, .ToReg: X86::K7 },
5282};
5283extern const unsigned X86DwarfFlavour2Dwarf2LSize = std::size(X86DwarfFlavour2Dwarf2L);
5284
5285extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
5286 { .FromReg: 0U, .ToReg: X86::RAX },
5287 { .FromReg: 1U, .ToReg: X86::RDX },
5288 { .FromReg: 2U, .ToReg: X86::RCX },
5289 { .FromReg: 3U, .ToReg: X86::RBX },
5290 { .FromReg: 4U, .ToReg: X86::RSI },
5291 { .FromReg: 5U, .ToReg: X86::RDI },
5292 { .FromReg: 6U, .ToReg: X86::RBP },
5293 { .FromReg: 7U, .ToReg: X86::RSP },
5294 { .FromReg: 8U, .ToReg: X86::R8 },
5295 { .FromReg: 9U, .ToReg: X86::R9 },
5296 { .FromReg: 10U, .ToReg: X86::R10 },
5297 { .FromReg: 11U, .ToReg: X86::R11 },
5298 { .FromReg: 12U, .ToReg: X86::R12 },
5299 { .FromReg: 13U, .ToReg: X86::R13 },
5300 { .FromReg: 14U, .ToReg: X86::R14 },
5301 { .FromReg: 15U, .ToReg: X86::R15 },
5302 { .FromReg: 16U, .ToReg: X86::RIP },
5303 { .FromReg: 17U, .ToReg: X86::XMM0 },
5304 { .FromReg: 18U, .ToReg: X86::XMM1 },
5305 { .FromReg: 19U, .ToReg: X86::XMM2 },
5306 { .FromReg: 20U, .ToReg: X86::XMM3 },
5307 { .FromReg: 21U, .ToReg: X86::XMM4 },
5308 { .FromReg: 22U, .ToReg: X86::XMM5 },
5309 { .FromReg: 23U, .ToReg: X86::XMM6 },
5310 { .FromReg: 24U, .ToReg: X86::XMM7 },
5311 { .FromReg: 25U, .ToReg: X86::XMM8 },
5312 { .FromReg: 26U, .ToReg: X86::XMM9 },
5313 { .FromReg: 27U, .ToReg: X86::XMM10 },
5314 { .FromReg: 28U, .ToReg: X86::XMM11 },
5315 { .FromReg: 29U, .ToReg: X86::XMM12 },
5316 { .FromReg: 30U, .ToReg: X86::XMM13 },
5317 { .FromReg: 31U, .ToReg: X86::XMM14 },
5318 { .FromReg: 32U, .ToReg: X86::XMM15 },
5319 { .FromReg: 33U, .ToReg: X86::ST0 },
5320 { .FromReg: 34U, .ToReg: X86::ST1 },
5321 { .FromReg: 35U, .ToReg: X86::ST2 },
5322 { .FromReg: 36U, .ToReg: X86::ST3 },
5323 { .FromReg: 37U, .ToReg: X86::ST4 },
5324 { .FromReg: 38U, .ToReg: X86::ST5 },
5325 { .FromReg: 39U, .ToReg: X86::ST6 },
5326 { .FromReg: 40U, .ToReg: X86::ST7 },
5327 { .FromReg: 41U, .ToReg: X86::MM0 },
5328 { .FromReg: 42U, .ToReg: X86::MM1 },
5329 { .FromReg: 43U, .ToReg: X86::MM2 },
5330 { .FromReg: 44U, .ToReg: X86::MM3 },
5331 { .FromReg: 45U, .ToReg: X86::MM4 },
5332 { .FromReg: 46U, .ToReg: X86::MM5 },
5333 { .FromReg: 47U, .ToReg: X86::MM6 },
5334 { .FromReg: 48U, .ToReg: X86::MM7 },
5335 { .FromReg: 49U, .ToReg: X86::RFLAGS },
5336 { .FromReg: 50U, .ToReg: X86::ES },
5337 { .FromReg: 51U, .ToReg: X86::CS },
5338 { .FromReg: 52U, .ToReg: X86::SS },
5339 { .FromReg: 53U, .ToReg: X86::DS },
5340 { .FromReg: 54U, .ToReg: X86::FS },
5341 { .FromReg: 55U, .ToReg: X86::GS },
5342 { .FromReg: 58U, .ToReg: X86::FS_BASE },
5343 { .FromReg: 59U, .ToReg: X86::GS_BASE },
5344 { .FromReg: 67U, .ToReg: X86::XMM16 },
5345 { .FromReg: 68U, .ToReg: X86::XMM17 },
5346 { .FromReg: 69U, .ToReg: X86::XMM18 },
5347 { .FromReg: 70U, .ToReg: X86::XMM19 },
5348 { .FromReg: 71U, .ToReg: X86::XMM20 },
5349 { .FromReg: 72U, .ToReg: X86::XMM21 },
5350 { .FromReg: 73U, .ToReg: X86::XMM22 },
5351 { .FromReg: 74U, .ToReg: X86::XMM23 },
5352 { .FromReg: 75U, .ToReg: X86::XMM24 },
5353 { .FromReg: 76U, .ToReg: X86::XMM25 },
5354 { .FromReg: 77U, .ToReg: X86::XMM26 },
5355 { .FromReg: 78U, .ToReg: X86::XMM27 },
5356 { .FromReg: 79U, .ToReg: X86::XMM28 },
5357 { .FromReg: 80U, .ToReg: X86::XMM29 },
5358 { .FromReg: 81U, .ToReg: X86::XMM30 },
5359 { .FromReg: 82U, .ToReg: X86::XMM31 },
5360 { .FromReg: 118U, .ToReg: X86::K0 },
5361 { .FromReg: 119U, .ToReg: X86::K1 },
5362 { .FromReg: 120U, .ToReg: X86::K2 },
5363 { .FromReg: 121U, .ToReg: X86::K3 },
5364 { .FromReg: 122U, .ToReg: X86::K4 },
5365 { .FromReg: 123U, .ToReg: X86::K5 },
5366 { .FromReg: 124U, .ToReg: X86::K6 },
5367 { .FromReg: 125U, .ToReg: X86::K7 },
5368 { .FromReg: 130U, .ToReg: X86::R16 },
5369 { .FromReg: 131U, .ToReg: X86::R17 },
5370 { .FromReg: 132U, .ToReg: X86::R18 },
5371 { .FromReg: 133U, .ToReg: X86::R19 },
5372 { .FromReg: 134U, .ToReg: X86::R20 },
5373 { .FromReg: 135U, .ToReg: X86::R21 },
5374 { .FromReg: 136U, .ToReg: X86::R22 },
5375 { .FromReg: 137U, .ToReg: X86::R23 },
5376 { .FromReg: 138U, .ToReg: X86::R24 },
5377 { .FromReg: 139U, .ToReg: X86::R25 },
5378 { .FromReg: 140U, .ToReg: X86::R26 },
5379 { .FromReg: 141U, .ToReg: X86::R27 },
5380 { .FromReg: 142U, .ToReg: X86::R28 },
5381 { .FromReg: 143U, .ToReg: X86::R29 },
5382 { .FromReg: 144U, .ToReg: X86::R30 },
5383 { .FromReg: 145U, .ToReg: X86::R31 },
5384};
5385extern const unsigned X86EHFlavour0Dwarf2LSize = std::size(X86EHFlavour0Dwarf2L);
5386
5387extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
5388 { .FromReg: 0U, .ToReg: X86::EAX },
5389 { .FromReg: 1U, .ToReg: X86::ECX },
5390 { .FromReg: 2U, .ToReg: X86::EDX },
5391 { .FromReg: 3U, .ToReg: X86::EBX },
5392 { .FromReg: 4U, .ToReg: X86::EBP },
5393 { .FromReg: 5U, .ToReg: X86::ESP },
5394 { .FromReg: 6U, .ToReg: X86::ESI },
5395 { .FromReg: 7U, .ToReg: X86::EDI },
5396 { .FromReg: 8U, .ToReg: X86::EIP },
5397 { .FromReg: 9U, .ToReg: X86::EFLAGS },
5398 { .FromReg: 12U, .ToReg: X86::ST0 },
5399 { .FromReg: 13U, .ToReg: X86::ST1 },
5400 { .FromReg: 14U, .ToReg: X86::ST2 },
5401 { .FromReg: 15U, .ToReg: X86::ST3 },
5402 { .FromReg: 16U, .ToReg: X86::ST4 },
5403 { .FromReg: 17U, .ToReg: X86::ST5 },
5404 { .FromReg: 18U, .ToReg: X86::ST6 },
5405 { .FromReg: 19U, .ToReg: X86::ST7 },
5406 { .FromReg: 21U, .ToReg: X86::XMM0 },
5407 { .FromReg: 22U, .ToReg: X86::XMM1 },
5408 { .FromReg: 23U, .ToReg: X86::XMM2 },
5409 { .FromReg: 24U, .ToReg: X86::XMM3 },
5410 { .FromReg: 25U, .ToReg: X86::XMM4 },
5411 { .FromReg: 26U, .ToReg: X86::XMM5 },
5412 { .FromReg: 27U, .ToReg: X86::XMM6 },
5413 { .FromReg: 28U, .ToReg: X86::XMM7 },
5414 { .FromReg: 29U, .ToReg: X86::MM0 },
5415 { .FromReg: 30U, .ToReg: X86::MM1 },
5416 { .FromReg: 31U, .ToReg: X86::MM2 },
5417 { .FromReg: 32U, .ToReg: X86::MM3 },
5418 { .FromReg: 33U, .ToReg: X86::MM4 },
5419 { .FromReg: 34U, .ToReg: X86::MM5 },
5420 { .FromReg: 35U, .ToReg: X86::MM6 },
5421 { .FromReg: 36U, .ToReg: X86::MM7 },
5422 { .FromReg: 93U, .ToReg: X86::K0 },
5423 { .FromReg: 94U, .ToReg: X86::K1 },
5424 { .FromReg: 95U, .ToReg: X86::K2 },
5425 { .FromReg: 96U, .ToReg: X86::K3 },
5426 { .FromReg: 97U, .ToReg: X86::K4 },
5427 { .FromReg: 98U, .ToReg: X86::K5 },
5428 { .FromReg: 99U, .ToReg: X86::K6 },
5429 { .FromReg: 100U, .ToReg: X86::K7 },
5430};
5431extern const unsigned X86EHFlavour1Dwarf2LSize = std::size(X86EHFlavour1Dwarf2L);
5432
5433extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
5434 { .FromReg: 0U, .ToReg: X86::EAX },
5435 { .FromReg: 1U, .ToReg: X86::ECX },
5436 { .FromReg: 2U, .ToReg: X86::EDX },
5437 { .FromReg: 3U, .ToReg: X86::EBX },
5438 { .FromReg: 4U, .ToReg: X86::ESP },
5439 { .FromReg: 5U, .ToReg: X86::EBP },
5440 { .FromReg: 6U, .ToReg: X86::ESI },
5441 { .FromReg: 7U, .ToReg: X86::EDI },
5442 { .FromReg: 8U, .ToReg: X86::EIP },
5443 { .FromReg: 9U, .ToReg: X86::EFLAGS },
5444 { .FromReg: 11U, .ToReg: X86::ST0 },
5445 { .FromReg: 12U, .ToReg: X86::ST1 },
5446 { .FromReg: 13U, .ToReg: X86::ST2 },
5447 { .FromReg: 14U, .ToReg: X86::ST3 },
5448 { .FromReg: 15U, .ToReg: X86::ST4 },
5449 { .FromReg: 16U, .ToReg: X86::ST5 },
5450 { .FromReg: 17U, .ToReg: X86::ST6 },
5451 { .FromReg: 18U, .ToReg: X86::ST7 },
5452 { .FromReg: 21U, .ToReg: X86::XMM0 },
5453 { .FromReg: 22U, .ToReg: X86::XMM1 },
5454 { .FromReg: 23U, .ToReg: X86::XMM2 },
5455 { .FromReg: 24U, .ToReg: X86::XMM3 },
5456 { .FromReg: 25U, .ToReg: X86::XMM4 },
5457 { .FromReg: 26U, .ToReg: X86::XMM5 },
5458 { .FromReg: 27U, .ToReg: X86::XMM6 },
5459 { .FromReg: 28U, .ToReg: X86::XMM7 },
5460 { .FromReg: 29U, .ToReg: X86::MM0 },
5461 { .FromReg: 30U, .ToReg: X86::MM1 },
5462 { .FromReg: 31U, .ToReg: X86::MM2 },
5463 { .FromReg: 32U, .ToReg: X86::MM3 },
5464 { .FromReg: 33U, .ToReg: X86::MM4 },
5465 { .FromReg: 34U, .ToReg: X86::MM5 },
5466 { .FromReg: 35U, .ToReg: X86::MM6 },
5467 { .FromReg: 36U, .ToReg: X86::MM7 },
5468 { .FromReg: 40U, .ToReg: X86::ES },
5469 { .FromReg: 41U, .ToReg: X86::CS },
5470 { .FromReg: 42U, .ToReg: X86::SS },
5471 { .FromReg: 43U, .ToReg: X86::DS },
5472 { .FromReg: 44U, .ToReg: X86::FS },
5473 { .FromReg: 45U, .ToReg: X86::GS },
5474 { .FromReg: 93U, .ToReg: X86::K0 },
5475 { .FromReg: 94U, .ToReg: X86::K1 },
5476 { .FromReg: 95U, .ToReg: X86::K2 },
5477 { .FromReg: 96U, .ToReg: X86::K3 },
5478 { .FromReg: 97U, .ToReg: X86::K4 },
5479 { .FromReg: 98U, .ToReg: X86::K5 },
5480 { .FromReg: 99U, .ToReg: X86::K6 },
5481 { .FromReg: 100U, .ToReg: X86::K7 },
5482};
5483extern const unsigned X86EHFlavour2Dwarf2LSize = std::size(X86EHFlavour2Dwarf2L);
5484
5485extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
5486 { .FromReg: X86::CS, .ToReg: 51U },
5487 { .FromReg: X86::DS, .ToReg: 53U },
5488 { .FromReg: X86::EAX, .ToReg: -2U },
5489 { .FromReg: X86::EBP, .ToReg: -2U },
5490 { .FromReg: X86::EBX, .ToReg: -2U },
5491 { .FromReg: X86::ECX, .ToReg: -2U },
5492 { .FromReg: X86::EDI, .ToReg: -2U },
5493 { .FromReg: X86::EDX, .ToReg: -2U },
5494 { .FromReg: X86::EFLAGS, .ToReg: 49U },
5495 { .FromReg: X86::EIP, .ToReg: -2U },
5496 { .FromReg: X86::ES, .ToReg: 50U },
5497 { .FromReg: X86::ESI, .ToReg: -2U },
5498 { .FromReg: X86::ESP, .ToReg: -2U },
5499 { .FromReg: X86::FS, .ToReg: 54U },
5500 { .FromReg: X86::FS_BASE, .ToReg: 58U },
5501 { .FromReg: X86::GS, .ToReg: 55U },
5502 { .FromReg: X86::GS_BASE, .ToReg: 59U },
5503 { .FromReg: X86::RAX, .ToReg: 0U },
5504 { .FromReg: X86::RBP, .ToReg: 6U },
5505 { .FromReg: X86::RBX, .ToReg: 3U },
5506 { .FromReg: X86::RCX, .ToReg: 2U },
5507 { .FromReg: X86::RDI, .ToReg: 5U },
5508 { .FromReg: X86::RDX, .ToReg: 1U },
5509 { .FromReg: X86::RFLAGS, .ToReg: 49U },
5510 { .FromReg: X86::RIP, .ToReg: 16U },
5511 { .FromReg: X86::RSI, .ToReg: 4U },
5512 { .FromReg: X86::RSP, .ToReg: 7U },
5513 { .FromReg: X86::SS, .ToReg: 52U },
5514 { .FromReg: X86::_EFLAGS, .ToReg: 49U },
5515 { .FromReg: X86::MM0, .ToReg: 41U },
5516 { .FromReg: X86::MM1, .ToReg: 42U },
5517 { .FromReg: X86::MM2, .ToReg: 43U },
5518 { .FromReg: X86::MM3, .ToReg: 44U },
5519 { .FromReg: X86::MM4, .ToReg: 45U },
5520 { .FromReg: X86::MM5, .ToReg: 46U },
5521 { .FromReg: X86::MM6, .ToReg: 47U },
5522 { .FromReg: X86::MM7, .ToReg: 48U },
5523 { .FromReg: X86::R8, .ToReg: 8U },
5524 { .FromReg: X86::R9, .ToReg: 9U },
5525 { .FromReg: X86::R10, .ToReg: 10U },
5526 { .FromReg: X86::R11, .ToReg: 11U },
5527 { .FromReg: X86::R12, .ToReg: 12U },
5528 { .FromReg: X86::R13, .ToReg: 13U },
5529 { .FromReg: X86::R14, .ToReg: 14U },
5530 { .FromReg: X86::R15, .ToReg: 15U },
5531 { .FromReg: X86::ST0, .ToReg: 33U },
5532 { .FromReg: X86::ST1, .ToReg: 34U },
5533 { .FromReg: X86::ST2, .ToReg: 35U },
5534 { .FromReg: X86::ST3, .ToReg: 36U },
5535 { .FromReg: X86::ST4, .ToReg: 37U },
5536 { .FromReg: X86::ST5, .ToReg: 38U },
5537 { .FromReg: X86::ST6, .ToReg: 39U },
5538 { .FromReg: X86::ST7, .ToReg: 40U },
5539 { .FromReg: X86::XMM0, .ToReg: 17U },
5540 { .FromReg: X86::XMM1, .ToReg: 18U },
5541 { .FromReg: X86::XMM2, .ToReg: 19U },
5542 { .FromReg: X86::XMM3, .ToReg: 20U },
5543 { .FromReg: X86::XMM4, .ToReg: 21U },
5544 { .FromReg: X86::XMM5, .ToReg: 22U },
5545 { .FromReg: X86::XMM6, .ToReg: 23U },
5546 { .FromReg: X86::XMM7, .ToReg: 24U },
5547 { .FromReg: X86::XMM8, .ToReg: 25U },
5548 { .FromReg: X86::XMM9, .ToReg: 26U },
5549 { .FromReg: X86::XMM10, .ToReg: 27U },
5550 { .FromReg: X86::XMM11, .ToReg: 28U },
5551 { .FromReg: X86::XMM12, .ToReg: 29U },
5552 { .FromReg: X86::XMM13, .ToReg: 30U },
5553 { .FromReg: X86::XMM14, .ToReg: 31U },
5554 { .FromReg: X86::XMM15, .ToReg: 32U },
5555 { .FromReg: X86::YMM0, .ToReg: 17U },
5556 { .FromReg: X86::YMM1, .ToReg: 18U },
5557 { .FromReg: X86::YMM2, .ToReg: 19U },
5558 { .FromReg: X86::YMM3, .ToReg: 20U },
5559 { .FromReg: X86::YMM4, .ToReg: 21U },
5560 { .FromReg: X86::YMM5, .ToReg: 22U },
5561 { .FromReg: X86::YMM6, .ToReg: 23U },
5562 { .FromReg: X86::YMM7, .ToReg: 24U },
5563 { .FromReg: X86::YMM8, .ToReg: 25U },
5564 { .FromReg: X86::YMM9, .ToReg: 26U },
5565 { .FromReg: X86::YMM10, .ToReg: 27U },
5566 { .FromReg: X86::YMM11, .ToReg: 28U },
5567 { .FromReg: X86::YMM12, .ToReg: 29U },
5568 { .FromReg: X86::YMM13, .ToReg: 30U },
5569 { .FromReg: X86::YMM14, .ToReg: 31U },
5570 { .FromReg: X86::YMM15, .ToReg: 32U },
5571 { .FromReg: X86::K0, .ToReg: 118U },
5572 { .FromReg: X86::K1, .ToReg: 119U },
5573 { .FromReg: X86::K2, .ToReg: 120U },
5574 { .FromReg: X86::K3, .ToReg: 121U },
5575 { .FromReg: X86::K4, .ToReg: 122U },
5576 { .FromReg: X86::K5, .ToReg: 123U },
5577 { .FromReg: X86::K6, .ToReg: 124U },
5578 { .FromReg: X86::K7, .ToReg: 125U },
5579 { .FromReg: X86::XMM16, .ToReg: 67U },
5580 { .FromReg: X86::XMM17, .ToReg: 68U },
5581 { .FromReg: X86::XMM18, .ToReg: 69U },
5582 { .FromReg: X86::XMM19, .ToReg: 70U },
5583 { .FromReg: X86::XMM20, .ToReg: 71U },
5584 { .FromReg: X86::XMM21, .ToReg: 72U },
5585 { .FromReg: X86::XMM22, .ToReg: 73U },
5586 { .FromReg: X86::XMM23, .ToReg: 74U },
5587 { .FromReg: X86::XMM24, .ToReg: 75U },
5588 { .FromReg: X86::XMM25, .ToReg: 76U },
5589 { .FromReg: X86::XMM26, .ToReg: 77U },
5590 { .FromReg: X86::XMM27, .ToReg: 78U },
5591 { .FromReg: X86::XMM28, .ToReg: 79U },
5592 { .FromReg: X86::XMM29, .ToReg: 80U },
5593 { .FromReg: X86::XMM30, .ToReg: 81U },
5594 { .FromReg: X86::XMM31, .ToReg: 82U },
5595 { .FromReg: X86::YMM16, .ToReg: 67U },
5596 { .FromReg: X86::YMM17, .ToReg: 68U },
5597 { .FromReg: X86::YMM18, .ToReg: 69U },
5598 { .FromReg: X86::YMM19, .ToReg: 70U },
5599 { .FromReg: X86::YMM20, .ToReg: 71U },
5600 { .FromReg: X86::YMM21, .ToReg: 72U },
5601 { .FromReg: X86::YMM22, .ToReg: 73U },
5602 { .FromReg: X86::YMM23, .ToReg: 74U },
5603 { .FromReg: X86::YMM24, .ToReg: 75U },
5604 { .FromReg: X86::YMM25, .ToReg: 76U },
5605 { .FromReg: X86::YMM26, .ToReg: 77U },
5606 { .FromReg: X86::YMM27, .ToReg: 78U },
5607 { .FromReg: X86::YMM28, .ToReg: 79U },
5608 { .FromReg: X86::YMM29, .ToReg: 80U },
5609 { .FromReg: X86::YMM30, .ToReg: 81U },
5610 { .FromReg: X86::YMM31, .ToReg: 82U },
5611 { .FromReg: X86::ZMM0, .ToReg: 17U },
5612 { .FromReg: X86::ZMM1, .ToReg: 18U },
5613 { .FromReg: X86::ZMM2, .ToReg: 19U },
5614 { .FromReg: X86::ZMM3, .ToReg: 20U },
5615 { .FromReg: X86::ZMM4, .ToReg: 21U },
5616 { .FromReg: X86::ZMM5, .ToReg: 22U },
5617 { .FromReg: X86::ZMM6, .ToReg: 23U },
5618 { .FromReg: X86::ZMM7, .ToReg: 24U },
5619 { .FromReg: X86::ZMM8, .ToReg: 25U },
5620 { .FromReg: X86::ZMM9, .ToReg: 26U },
5621 { .FromReg: X86::ZMM10, .ToReg: 27U },
5622 { .FromReg: X86::ZMM11, .ToReg: 28U },
5623 { .FromReg: X86::ZMM12, .ToReg: 29U },
5624 { .FromReg: X86::ZMM13, .ToReg: 30U },
5625 { .FromReg: X86::ZMM14, .ToReg: 31U },
5626 { .FromReg: X86::ZMM15, .ToReg: 32U },
5627 { .FromReg: X86::ZMM16, .ToReg: 67U },
5628 { .FromReg: X86::ZMM17, .ToReg: 68U },
5629 { .FromReg: X86::ZMM18, .ToReg: 69U },
5630 { .FromReg: X86::ZMM19, .ToReg: 70U },
5631 { .FromReg: X86::ZMM20, .ToReg: 71U },
5632 { .FromReg: X86::ZMM21, .ToReg: 72U },
5633 { .FromReg: X86::ZMM22, .ToReg: 73U },
5634 { .FromReg: X86::ZMM23, .ToReg: 74U },
5635 { .FromReg: X86::ZMM24, .ToReg: 75U },
5636 { .FromReg: X86::ZMM25, .ToReg: 76U },
5637 { .FromReg: X86::ZMM26, .ToReg: 77U },
5638 { .FromReg: X86::ZMM27, .ToReg: 78U },
5639 { .FromReg: X86::ZMM28, .ToReg: 79U },
5640 { .FromReg: X86::ZMM29, .ToReg: 80U },
5641 { .FromReg: X86::ZMM30, .ToReg: 81U },
5642 { .FromReg: X86::ZMM31, .ToReg: 82U },
5643 { .FromReg: X86::R16, .ToReg: 130U },
5644 { .FromReg: X86::R17, .ToReg: 131U },
5645 { .FromReg: X86::R18, .ToReg: 132U },
5646 { .FromReg: X86::R19, .ToReg: 133U },
5647 { .FromReg: X86::R20, .ToReg: 134U },
5648 { .FromReg: X86::R21, .ToReg: 135U },
5649 { .FromReg: X86::R22, .ToReg: 136U },
5650 { .FromReg: X86::R23, .ToReg: 137U },
5651 { .FromReg: X86::R24, .ToReg: 138U },
5652 { .FromReg: X86::R25, .ToReg: 139U },
5653 { .FromReg: X86::R26, .ToReg: 140U },
5654 { .FromReg: X86::R27, .ToReg: 141U },
5655 { .FromReg: X86::R28, .ToReg: 142U },
5656 { .FromReg: X86::R29, .ToReg: 143U },
5657 { .FromReg: X86::R30, .ToReg: 144U },
5658 { .FromReg: X86::R31, .ToReg: 145U },
5659};
5660extern const unsigned X86DwarfFlavour0L2DwarfSize = std::size(X86DwarfFlavour0L2Dwarf);
5661
5662extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
5663 { .FromReg: X86::CS, .ToReg: -2U },
5664 { .FromReg: X86::DS, .ToReg: -2U },
5665 { .FromReg: X86::EAX, .ToReg: 0U },
5666 { .FromReg: X86::EBP, .ToReg: 4U },
5667 { .FromReg: X86::EBX, .ToReg: 3U },
5668 { .FromReg: X86::ECX, .ToReg: 1U },
5669 { .FromReg: X86::EDI, .ToReg: 7U },
5670 { .FromReg: X86::EDX, .ToReg: 2U },
5671 { .FromReg: X86::EFLAGS, .ToReg: 9U },
5672 { .FromReg: X86::EIP, .ToReg: 8U },
5673 { .FromReg: X86::ES, .ToReg: -2U },
5674 { .FromReg: X86::ESI, .ToReg: 6U },
5675 { .FromReg: X86::ESP, .ToReg: 5U },
5676 { .FromReg: X86::FS, .ToReg: -2U },
5677 { .FromReg: X86::FS_BASE, .ToReg: -2U },
5678 { .FromReg: X86::GS, .ToReg: -2U },
5679 { .FromReg: X86::GS_BASE, .ToReg: -2U },
5680 { .FromReg: X86::RAX, .ToReg: -2U },
5681 { .FromReg: X86::RBP, .ToReg: -2U },
5682 { .FromReg: X86::RBX, .ToReg: -2U },
5683 { .FromReg: X86::RCX, .ToReg: -2U },
5684 { .FromReg: X86::RDI, .ToReg: -2U },
5685 { .FromReg: X86::RDX, .ToReg: -2U },
5686 { .FromReg: X86::RFLAGS, .ToReg: -2U },
5687 { .FromReg: X86::RIP, .ToReg: -2U },
5688 { .FromReg: X86::RSI, .ToReg: -2U },
5689 { .FromReg: X86::RSP, .ToReg: -2U },
5690 { .FromReg: X86::SS, .ToReg: -2U },
5691 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
5692 { .FromReg: X86::MM0, .ToReg: 29U },
5693 { .FromReg: X86::MM1, .ToReg: 30U },
5694 { .FromReg: X86::MM2, .ToReg: 31U },
5695 { .FromReg: X86::MM3, .ToReg: 32U },
5696 { .FromReg: X86::MM4, .ToReg: 33U },
5697 { .FromReg: X86::MM5, .ToReg: 34U },
5698 { .FromReg: X86::MM6, .ToReg: 35U },
5699 { .FromReg: X86::MM7, .ToReg: 36U },
5700 { .FromReg: X86::R8, .ToReg: -2U },
5701 { .FromReg: X86::R9, .ToReg: -2U },
5702 { .FromReg: X86::R10, .ToReg: -2U },
5703 { .FromReg: X86::R11, .ToReg: -2U },
5704 { .FromReg: X86::R12, .ToReg: -2U },
5705 { .FromReg: X86::R13, .ToReg: -2U },
5706 { .FromReg: X86::R14, .ToReg: -2U },
5707 { .FromReg: X86::R15, .ToReg: -2U },
5708 { .FromReg: X86::ST0, .ToReg: 12U },
5709 { .FromReg: X86::ST1, .ToReg: 13U },
5710 { .FromReg: X86::ST2, .ToReg: 14U },
5711 { .FromReg: X86::ST3, .ToReg: 15U },
5712 { .FromReg: X86::ST4, .ToReg: 16U },
5713 { .FromReg: X86::ST5, .ToReg: 17U },
5714 { .FromReg: X86::ST6, .ToReg: 18U },
5715 { .FromReg: X86::ST7, .ToReg: 19U },
5716 { .FromReg: X86::XMM0, .ToReg: 21U },
5717 { .FromReg: X86::XMM1, .ToReg: 22U },
5718 { .FromReg: X86::XMM2, .ToReg: 23U },
5719 { .FromReg: X86::XMM3, .ToReg: 24U },
5720 { .FromReg: X86::XMM4, .ToReg: 25U },
5721 { .FromReg: X86::XMM5, .ToReg: 26U },
5722 { .FromReg: X86::XMM6, .ToReg: 27U },
5723 { .FromReg: X86::XMM7, .ToReg: 28U },
5724 { .FromReg: X86::XMM8, .ToReg: -2U },
5725 { .FromReg: X86::XMM9, .ToReg: -2U },
5726 { .FromReg: X86::XMM10, .ToReg: -2U },
5727 { .FromReg: X86::XMM11, .ToReg: -2U },
5728 { .FromReg: X86::XMM12, .ToReg: -2U },
5729 { .FromReg: X86::XMM13, .ToReg: -2U },
5730 { .FromReg: X86::XMM14, .ToReg: -2U },
5731 { .FromReg: X86::XMM15, .ToReg: -2U },
5732 { .FromReg: X86::YMM0, .ToReg: 21U },
5733 { .FromReg: X86::YMM1, .ToReg: 22U },
5734 { .FromReg: X86::YMM2, .ToReg: 23U },
5735 { .FromReg: X86::YMM3, .ToReg: 24U },
5736 { .FromReg: X86::YMM4, .ToReg: 25U },
5737 { .FromReg: X86::YMM5, .ToReg: 26U },
5738 { .FromReg: X86::YMM6, .ToReg: 27U },
5739 { .FromReg: X86::YMM7, .ToReg: 28U },
5740 { .FromReg: X86::YMM8, .ToReg: -2U },
5741 { .FromReg: X86::YMM9, .ToReg: -2U },
5742 { .FromReg: X86::YMM10, .ToReg: -2U },
5743 { .FromReg: X86::YMM11, .ToReg: -2U },
5744 { .FromReg: X86::YMM12, .ToReg: -2U },
5745 { .FromReg: X86::YMM13, .ToReg: -2U },
5746 { .FromReg: X86::YMM14, .ToReg: -2U },
5747 { .FromReg: X86::YMM15, .ToReg: -2U },
5748 { .FromReg: X86::K0, .ToReg: 93U },
5749 { .FromReg: X86::K1, .ToReg: 94U },
5750 { .FromReg: X86::K2, .ToReg: 95U },
5751 { .FromReg: X86::K3, .ToReg: 96U },
5752 { .FromReg: X86::K4, .ToReg: 97U },
5753 { .FromReg: X86::K5, .ToReg: 98U },
5754 { .FromReg: X86::K6, .ToReg: 99U },
5755 { .FromReg: X86::K7, .ToReg: 100U },
5756 { .FromReg: X86::XMM16, .ToReg: -2U },
5757 { .FromReg: X86::XMM17, .ToReg: -2U },
5758 { .FromReg: X86::XMM18, .ToReg: -2U },
5759 { .FromReg: X86::XMM19, .ToReg: -2U },
5760 { .FromReg: X86::XMM20, .ToReg: -2U },
5761 { .FromReg: X86::XMM21, .ToReg: -2U },
5762 { .FromReg: X86::XMM22, .ToReg: -2U },
5763 { .FromReg: X86::XMM23, .ToReg: -2U },
5764 { .FromReg: X86::XMM24, .ToReg: -2U },
5765 { .FromReg: X86::XMM25, .ToReg: -2U },
5766 { .FromReg: X86::XMM26, .ToReg: -2U },
5767 { .FromReg: X86::XMM27, .ToReg: -2U },
5768 { .FromReg: X86::XMM28, .ToReg: -2U },
5769 { .FromReg: X86::XMM29, .ToReg: -2U },
5770 { .FromReg: X86::XMM30, .ToReg: -2U },
5771 { .FromReg: X86::XMM31, .ToReg: -2U },
5772 { .FromReg: X86::YMM16, .ToReg: -2U },
5773 { .FromReg: X86::YMM17, .ToReg: -2U },
5774 { .FromReg: X86::YMM18, .ToReg: -2U },
5775 { .FromReg: X86::YMM19, .ToReg: -2U },
5776 { .FromReg: X86::YMM20, .ToReg: -2U },
5777 { .FromReg: X86::YMM21, .ToReg: -2U },
5778 { .FromReg: X86::YMM22, .ToReg: -2U },
5779 { .FromReg: X86::YMM23, .ToReg: -2U },
5780 { .FromReg: X86::YMM24, .ToReg: -2U },
5781 { .FromReg: X86::YMM25, .ToReg: -2U },
5782 { .FromReg: X86::YMM26, .ToReg: -2U },
5783 { .FromReg: X86::YMM27, .ToReg: -2U },
5784 { .FromReg: X86::YMM28, .ToReg: -2U },
5785 { .FromReg: X86::YMM29, .ToReg: -2U },
5786 { .FromReg: X86::YMM30, .ToReg: -2U },
5787 { .FromReg: X86::YMM31, .ToReg: -2U },
5788 { .FromReg: X86::ZMM0, .ToReg: 21U },
5789 { .FromReg: X86::ZMM1, .ToReg: 22U },
5790 { .FromReg: X86::ZMM2, .ToReg: 23U },
5791 { .FromReg: X86::ZMM3, .ToReg: 24U },
5792 { .FromReg: X86::ZMM4, .ToReg: 25U },
5793 { .FromReg: X86::ZMM5, .ToReg: 26U },
5794 { .FromReg: X86::ZMM6, .ToReg: 27U },
5795 { .FromReg: X86::ZMM7, .ToReg: 28U },
5796 { .FromReg: X86::ZMM8, .ToReg: -2U },
5797 { .FromReg: X86::ZMM9, .ToReg: -2U },
5798 { .FromReg: X86::ZMM10, .ToReg: -2U },
5799 { .FromReg: X86::ZMM11, .ToReg: -2U },
5800 { .FromReg: X86::ZMM12, .ToReg: -2U },
5801 { .FromReg: X86::ZMM13, .ToReg: -2U },
5802 { .FromReg: X86::ZMM14, .ToReg: -2U },
5803 { .FromReg: X86::ZMM15, .ToReg: -2U },
5804 { .FromReg: X86::ZMM16, .ToReg: -2U },
5805 { .FromReg: X86::ZMM17, .ToReg: -2U },
5806 { .FromReg: X86::ZMM18, .ToReg: -2U },
5807 { .FromReg: X86::ZMM19, .ToReg: -2U },
5808 { .FromReg: X86::ZMM20, .ToReg: -2U },
5809 { .FromReg: X86::ZMM21, .ToReg: -2U },
5810 { .FromReg: X86::ZMM22, .ToReg: -2U },
5811 { .FromReg: X86::ZMM23, .ToReg: -2U },
5812 { .FromReg: X86::ZMM24, .ToReg: -2U },
5813 { .FromReg: X86::ZMM25, .ToReg: -2U },
5814 { .FromReg: X86::ZMM26, .ToReg: -2U },
5815 { .FromReg: X86::ZMM27, .ToReg: -2U },
5816 { .FromReg: X86::ZMM28, .ToReg: -2U },
5817 { .FromReg: X86::ZMM29, .ToReg: -2U },
5818 { .FromReg: X86::ZMM30, .ToReg: -2U },
5819 { .FromReg: X86::ZMM31, .ToReg: -2U },
5820 { .FromReg: X86::R16, .ToReg: -2U },
5821 { .FromReg: X86::R17, .ToReg: -2U },
5822 { .FromReg: X86::R18, .ToReg: -2U },
5823 { .FromReg: X86::R19, .ToReg: -2U },
5824 { .FromReg: X86::R20, .ToReg: -2U },
5825 { .FromReg: X86::R21, .ToReg: -2U },
5826 { .FromReg: X86::R22, .ToReg: -2U },
5827 { .FromReg: X86::R23, .ToReg: -2U },
5828 { .FromReg: X86::R24, .ToReg: -2U },
5829 { .FromReg: X86::R25, .ToReg: -2U },
5830 { .FromReg: X86::R26, .ToReg: -2U },
5831 { .FromReg: X86::R27, .ToReg: -2U },
5832 { .FromReg: X86::R28, .ToReg: -2U },
5833 { .FromReg: X86::R29, .ToReg: -2U },
5834 { .FromReg: X86::R30, .ToReg: -2U },
5835 { .FromReg: X86::R31, .ToReg: -2U },
5836};
5837extern const unsigned X86DwarfFlavour1L2DwarfSize = std::size(X86DwarfFlavour1L2Dwarf);
5838
5839extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
5840 { .FromReg: X86::CS, .ToReg: 41U },
5841 { .FromReg: X86::DS, .ToReg: 43U },
5842 { .FromReg: X86::EAX, .ToReg: 0U },
5843 { .FromReg: X86::EBP, .ToReg: 5U },
5844 { .FromReg: X86::EBX, .ToReg: 3U },
5845 { .FromReg: X86::ECX, .ToReg: 1U },
5846 { .FromReg: X86::EDI, .ToReg: 7U },
5847 { .FromReg: X86::EDX, .ToReg: 2U },
5848 { .FromReg: X86::EFLAGS, .ToReg: 9U },
5849 { .FromReg: X86::EIP, .ToReg: 8U },
5850 { .FromReg: X86::ES, .ToReg: 40U },
5851 { .FromReg: X86::ESI, .ToReg: 6U },
5852 { .FromReg: X86::ESP, .ToReg: 4U },
5853 { .FromReg: X86::FS, .ToReg: 44U },
5854 { .FromReg: X86::FS_BASE, .ToReg: -2U },
5855 { .FromReg: X86::GS, .ToReg: 45U },
5856 { .FromReg: X86::GS_BASE, .ToReg: -2U },
5857 { .FromReg: X86::RAX, .ToReg: -2U },
5858 { .FromReg: X86::RBP, .ToReg: -2U },
5859 { .FromReg: X86::RBX, .ToReg: -2U },
5860 { .FromReg: X86::RCX, .ToReg: -2U },
5861 { .FromReg: X86::RDI, .ToReg: -2U },
5862 { .FromReg: X86::RDX, .ToReg: -2U },
5863 { .FromReg: X86::RFLAGS, .ToReg: -2U },
5864 { .FromReg: X86::RIP, .ToReg: -2U },
5865 { .FromReg: X86::RSI, .ToReg: -2U },
5866 { .FromReg: X86::RSP, .ToReg: -2U },
5867 { .FromReg: X86::SS, .ToReg: 42U },
5868 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
5869 { .FromReg: X86::MM0, .ToReg: 29U },
5870 { .FromReg: X86::MM1, .ToReg: 30U },
5871 { .FromReg: X86::MM2, .ToReg: 31U },
5872 { .FromReg: X86::MM3, .ToReg: 32U },
5873 { .FromReg: X86::MM4, .ToReg: 33U },
5874 { .FromReg: X86::MM5, .ToReg: 34U },
5875 { .FromReg: X86::MM6, .ToReg: 35U },
5876 { .FromReg: X86::MM7, .ToReg: 36U },
5877 { .FromReg: X86::R8, .ToReg: -2U },
5878 { .FromReg: X86::R9, .ToReg: -2U },
5879 { .FromReg: X86::R10, .ToReg: -2U },
5880 { .FromReg: X86::R11, .ToReg: -2U },
5881 { .FromReg: X86::R12, .ToReg: -2U },
5882 { .FromReg: X86::R13, .ToReg: -2U },
5883 { .FromReg: X86::R14, .ToReg: -2U },
5884 { .FromReg: X86::R15, .ToReg: -2U },
5885 { .FromReg: X86::ST0, .ToReg: 11U },
5886 { .FromReg: X86::ST1, .ToReg: 12U },
5887 { .FromReg: X86::ST2, .ToReg: 13U },
5888 { .FromReg: X86::ST3, .ToReg: 14U },
5889 { .FromReg: X86::ST4, .ToReg: 15U },
5890 { .FromReg: X86::ST5, .ToReg: 16U },
5891 { .FromReg: X86::ST6, .ToReg: 17U },
5892 { .FromReg: X86::ST7, .ToReg: 18U },
5893 { .FromReg: X86::XMM0, .ToReg: 21U },
5894 { .FromReg: X86::XMM1, .ToReg: 22U },
5895 { .FromReg: X86::XMM2, .ToReg: 23U },
5896 { .FromReg: X86::XMM3, .ToReg: 24U },
5897 { .FromReg: X86::XMM4, .ToReg: 25U },
5898 { .FromReg: X86::XMM5, .ToReg: 26U },
5899 { .FromReg: X86::XMM6, .ToReg: 27U },
5900 { .FromReg: X86::XMM7, .ToReg: 28U },
5901 { .FromReg: X86::XMM8, .ToReg: -2U },
5902 { .FromReg: X86::XMM9, .ToReg: -2U },
5903 { .FromReg: X86::XMM10, .ToReg: -2U },
5904 { .FromReg: X86::XMM11, .ToReg: -2U },
5905 { .FromReg: X86::XMM12, .ToReg: -2U },
5906 { .FromReg: X86::XMM13, .ToReg: -2U },
5907 { .FromReg: X86::XMM14, .ToReg: -2U },
5908 { .FromReg: X86::XMM15, .ToReg: -2U },
5909 { .FromReg: X86::YMM0, .ToReg: 21U },
5910 { .FromReg: X86::YMM1, .ToReg: 22U },
5911 { .FromReg: X86::YMM2, .ToReg: 23U },
5912 { .FromReg: X86::YMM3, .ToReg: 24U },
5913 { .FromReg: X86::YMM4, .ToReg: 25U },
5914 { .FromReg: X86::YMM5, .ToReg: 26U },
5915 { .FromReg: X86::YMM6, .ToReg: 27U },
5916 { .FromReg: X86::YMM7, .ToReg: 28U },
5917 { .FromReg: X86::YMM8, .ToReg: -2U },
5918 { .FromReg: X86::YMM9, .ToReg: -2U },
5919 { .FromReg: X86::YMM10, .ToReg: -2U },
5920 { .FromReg: X86::YMM11, .ToReg: -2U },
5921 { .FromReg: X86::YMM12, .ToReg: -2U },
5922 { .FromReg: X86::YMM13, .ToReg: -2U },
5923 { .FromReg: X86::YMM14, .ToReg: -2U },
5924 { .FromReg: X86::YMM15, .ToReg: -2U },
5925 { .FromReg: X86::K0, .ToReg: 93U },
5926 { .FromReg: X86::K1, .ToReg: 94U },
5927 { .FromReg: X86::K2, .ToReg: 95U },
5928 { .FromReg: X86::K3, .ToReg: 96U },
5929 { .FromReg: X86::K4, .ToReg: 97U },
5930 { .FromReg: X86::K5, .ToReg: 98U },
5931 { .FromReg: X86::K6, .ToReg: 99U },
5932 { .FromReg: X86::K7, .ToReg: 100U },
5933 { .FromReg: X86::XMM16, .ToReg: -2U },
5934 { .FromReg: X86::XMM17, .ToReg: -2U },
5935 { .FromReg: X86::XMM18, .ToReg: -2U },
5936 { .FromReg: X86::XMM19, .ToReg: -2U },
5937 { .FromReg: X86::XMM20, .ToReg: -2U },
5938 { .FromReg: X86::XMM21, .ToReg: -2U },
5939 { .FromReg: X86::XMM22, .ToReg: -2U },
5940 { .FromReg: X86::XMM23, .ToReg: -2U },
5941 { .FromReg: X86::XMM24, .ToReg: -2U },
5942 { .FromReg: X86::XMM25, .ToReg: -2U },
5943 { .FromReg: X86::XMM26, .ToReg: -2U },
5944 { .FromReg: X86::XMM27, .ToReg: -2U },
5945 { .FromReg: X86::XMM28, .ToReg: -2U },
5946 { .FromReg: X86::XMM29, .ToReg: -2U },
5947 { .FromReg: X86::XMM30, .ToReg: -2U },
5948 { .FromReg: X86::XMM31, .ToReg: -2U },
5949 { .FromReg: X86::YMM16, .ToReg: -2U },
5950 { .FromReg: X86::YMM17, .ToReg: -2U },
5951 { .FromReg: X86::YMM18, .ToReg: -2U },
5952 { .FromReg: X86::YMM19, .ToReg: -2U },
5953 { .FromReg: X86::YMM20, .ToReg: -2U },
5954 { .FromReg: X86::YMM21, .ToReg: -2U },
5955 { .FromReg: X86::YMM22, .ToReg: -2U },
5956 { .FromReg: X86::YMM23, .ToReg: -2U },
5957 { .FromReg: X86::YMM24, .ToReg: -2U },
5958 { .FromReg: X86::YMM25, .ToReg: -2U },
5959 { .FromReg: X86::YMM26, .ToReg: -2U },
5960 { .FromReg: X86::YMM27, .ToReg: -2U },
5961 { .FromReg: X86::YMM28, .ToReg: -2U },
5962 { .FromReg: X86::YMM29, .ToReg: -2U },
5963 { .FromReg: X86::YMM30, .ToReg: -2U },
5964 { .FromReg: X86::YMM31, .ToReg: -2U },
5965 { .FromReg: X86::ZMM0, .ToReg: 21U },
5966 { .FromReg: X86::ZMM1, .ToReg: 22U },
5967 { .FromReg: X86::ZMM2, .ToReg: 23U },
5968 { .FromReg: X86::ZMM3, .ToReg: 24U },
5969 { .FromReg: X86::ZMM4, .ToReg: 25U },
5970 { .FromReg: X86::ZMM5, .ToReg: 26U },
5971 { .FromReg: X86::ZMM6, .ToReg: 27U },
5972 { .FromReg: X86::ZMM7, .ToReg: 28U },
5973 { .FromReg: X86::ZMM8, .ToReg: -2U },
5974 { .FromReg: X86::ZMM9, .ToReg: -2U },
5975 { .FromReg: X86::ZMM10, .ToReg: -2U },
5976 { .FromReg: X86::ZMM11, .ToReg: -2U },
5977 { .FromReg: X86::ZMM12, .ToReg: -2U },
5978 { .FromReg: X86::ZMM13, .ToReg: -2U },
5979 { .FromReg: X86::ZMM14, .ToReg: -2U },
5980 { .FromReg: X86::ZMM15, .ToReg: -2U },
5981 { .FromReg: X86::ZMM16, .ToReg: -2U },
5982 { .FromReg: X86::ZMM17, .ToReg: -2U },
5983 { .FromReg: X86::ZMM18, .ToReg: -2U },
5984 { .FromReg: X86::ZMM19, .ToReg: -2U },
5985 { .FromReg: X86::ZMM20, .ToReg: -2U },
5986 { .FromReg: X86::ZMM21, .ToReg: -2U },
5987 { .FromReg: X86::ZMM22, .ToReg: -2U },
5988 { .FromReg: X86::ZMM23, .ToReg: -2U },
5989 { .FromReg: X86::ZMM24, .ToReg: -2U },
5990 { .FromReg: X86::ZMM25, .ToReg: -2U },
5991 { .FromReg: X86::ZMM26, .ToReg: -2U },
5992 { .FromReg: X86::ZMM27, .ToReg: -2U },
5993 { .FromReg: X86::ZMM28, .ToReg: -2U },
5994 { .FromReg: X86::ZMM29, .ToReg: -2U },
5995 { .FromReg: X86::ZMM30, .ToReg: -2U },
5996 { .FromReg: X86::ZMM31, .ToReg: -2U },
5997 { .FromReg: X86::R16, .ToReg: -2U },
5998 { .FromReg: X86::R17, .ToReg: -2U },
5999 { .FromReg: X86::R18, .ToReg: -2U },
6000 { .FromReg: X86::R19, .ToReg: -2U },
6001 { .FromReg: X86::R20, .ToReg: -2U },
6002 { .FromReg: X86::R21, .ToReg: -2U },
6003 { .FromReg: X86::R22, .ToReg: -2U },
6004 { .FromReg: X86::R23, .ToReg: -2U },
6005 { .FromReg: X86::R24, .ToReg: -2U },
6006 { .FromReg: X86::R25, .ToReg: -2U },
6007 { .FromReg: X86::R26, .ToReg: -2U },
6008 { .FromReg: X86::R27, .ToReg: -2U },
6009 { .FromReg: X86::R28, .ToReg: -2U },
6010 { .FromReg: X86::R29, .ToReg: -2U },
6011 { .FromReg: X86::R30, .ToReg: -2U },
6012 { .FromReg: X86::R31, .ToReg: -2U },
6013};
6014extern const unsigned X86DwarfFlavour2L2DwarfSize = std::size(X86DwarfFlavour2L2Dwarf);
6015
6016extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
6017 { .FromReg: X86::CS, .ToReg: 51U },
6018 { .FromReg: X86::DS, .ToReg: 53U },
6019 { .FromReg: X86::EAX, .ToReg: -2U },
6020 { .FromReg: X86::EBP, .ToReg: -2U },
6021 { .FromReg: X86::EBX, .ToReg: -2U },
6022 { .FromReg: X86::ECX, .ToReg: -2U },
6023 { .FromReg: X86::EDI, .ToReg: -2U },
6024 { .FromReg: X86::EDX, .ToReg: -2U },
6025 { .FromReg: X86::EFLAGS, .ToReg: 49U },
6026 { .FromReg: X86::EIP, .ToReg: -2U },
6027 { .FromReg: X86::ES, .ToReg: 50U },
6028 { .FromReg: X86::ESI, .ToReg: -2U },
6029 { .FromReg: X86::ESP, .ToReg: -2U },
6030 { .FromReg: X86::FS, .ToReg: 54U },
6031 { .FromReg: X86::FS_BASE, .ToReg: 58U },
6032 { .FromReg: X86::GS, .ToReg: 55U },
6033 { .FromReg: X86::GS_BASE, .ToReg: 59U },
6034 { .FromReg: X86::RAX, .ToReg: 0U },
6035 { .FromReg: X86::RBP, .ToReg: 6U },
6036 { .FromReg: X86::RBX, .ToReg: 3U },
6037 { .FromReg: X86::RCX, .ToReg: 2U },
6038 { .FromReg: X86::RDI, .ToReg: 5U },
6039 { .FromReg: X86::RDX, .ToReg: 1U },
6040 { .FromReg: X86::RFLAGS, .ToReg: 49U },
6041 { .FromReg: X86::RIP, .ToReg: 16U },
6042 { .FromReg: X86::RSI, .ToReg: 4U },
6043 { .FromReg: X86::RSP, .ToReg: 7U },
6044 { .FromReg: X86::SS, .ToReg: 52U },
6045 { .FromReg: X86::_EFLAGS, .ToReg: 49U },
6046 { .FromReg: X86::MM0, .ToReg: 41U },
6047 { .FromReg: X86::MM1, .ToReg: 42U },
6048 { .FromReg: X86::MM2, .ToReg: 43U },
6049 { .FromReg: X86::MM3, .ToReg: 44U },
6050 { .FromReg: X86::MM4, .ToReg: 45U },
6051 { .FromReg: X86::MM5, .ToReg: 46U },
6052 { .FromReg: X86::MM6, .ToReg: 47U },
6053 { .FromReg: X86::MM7, .ToReg: 48U },
6054 { .FromReg: X86::R8, .ToReg: 8U },
6055 { .FromReg: X86::R9, .ToReg: 9U },
6056 { .FromReg: X86::R10, .ToReg: 10U },
6057 { .FromReg: X86::R11, .ToReg: 11U },
6058 { .FromReg: X86::R12, .ToReg: 12U },
6059 { .FromReg: X86::R13, .ToReg: 13U },
6060 { .FromReg: X86::R14, .ToReg: 14U },
6061 { .FromReg: X86::R15, .ToReg: 15U },
6062 { .FromReg: X86::ST0, .ToReg: 33U },
6063 { .FromReg: X86::ST1, .ToReg: 34U },
6064 { .FromReg: X86::ST2, .ToReg: 35U },
6065 { .FromReg: X86::ST3, .ToReg: 36U },
6066 { .FromReg: X86::ST4, .ToReg: 37U },
6067 { .FromReg: X86::ST5, .ToReg: 38U },
6068 { .FromReg: X86::ST6, .ToReg: 39U },
6069 { .FromReg: X86::ST7, .ToReg: 40U },
6070 { .FromReg: X86::XMM0, .ToReg: 17U },
6071 { .FromReg: X86::XMM1, .ToReg: 18U },
6072 { .FromReg: X86::XMM2, .ToReg: 19U },
6073 { .FromReg: X86::XMM3, .ToReg: 20U },
6074 { .FromReg: X86::XMM4, .ToReg: 21U },
6075 { .FromReg: X86::XMM5, .ToReg: 22U },
6076 { .FromReg: X86::XMM6, .ToReg: 23U },
6077 { .FromReg: X86::XMM7, .ToReg: 24U },
6078 { .FromReg: X86::XMM8, .ToReg: 25U },
6079 { .FromReg: X86::XMM9, .ToReg: 26U },
6080 { .FromReg: X86::XMM10, .ToReg: 27U },
6081 { .FromReg: X86::XMM11, .ToReg: 28U },
6082 { .FromReg: X86::XMM12, .ToReg: 29U },
6083 { .FromReg: X86::XMM13, .ToReg: 30U },
6084 { .FromReg: X86::XMM14, .ToReg: 31U },
6085 { .FromReg: X86::XMM15, .ToReg: 32U },
6086 { .FromReg: X86::YMM0, .ToReg: 17U },
6087 { .FromReg: X86::YMM1, .ToReg: 18U },
6088 { .FromReg: X86::YMM2, .ToReg: 19U },
6089 { .FromReg: X86::YMM3, .ToReg: 20U },
6090 { .FromReg: X86::YMM4, .ToReg: 21U },
6091 { .FromReg: X86::YMM5, .ToReg: 22U },
6092 { .FromReg: X86::YMM6, .ToReg: 23U },
6093 { .FromReg: X86::YMM7, .ToReg: 24U },
6094 { .FromReg: X86::YMM8, .ToReg: 25U },
6095 { .FromReg: X86::YMM9, .ToReg: 26U },
6096 { .FromReg: X86::YMM10, .ToReg: 27U },
6097 { .FromReg: X86::YMM11, .ToReg: 28U },
6098 { .FromReg: X86::YMM12, .ToReg: 29U },
6099 { .FromReg: X86::YMM13, .ToReg: 30U },
6100 { .FromReg: X86::YMM14, .ToReg: 31U },
6101 { .FromReg: X86::YMM15, .ToReg: 32U },
6102 { .FromReg: X86::K0, .ToReg: 118U },
6103 { .FromReg: X86::K1, .ToReg: 119U },
6104 { .FromReg: X86::K2, .ToReg: 120U },
6105 { .FromReg: X86::K3, .ToReg: 121U },
6106 { .FromReg: X86::K4, .ToReg: 122U },
6107 { .FromReg: X86::K5, .ToReg: 123U },
6108 { .FromReg: X86::K6, .ToReg: 124U },
6109 { .FromReg: X86::K7, .ToReg: 125U },
6110 { .FromReg: X86::XMM16, .ToReg: 67U },
6111 { .FromReg: X86::XMM17, .ToReg: 68U },
6112 { .FromReg: X86::XMM18, .ToReg: 69U },
6113 { .FromReg: X86::XMM19, .ToReg: 70U },
6114 { .FromReg: X86::XMM20, .ToReg: 71U },
6115 { .FromReg: X86::XMM21, .ToReg: 72U },
6116 { .FromReg: X86::XMM22, .ToReg: 73U },
6117 { .FromReg: X86::XMM23, .ToReg: 74U },
6118 { .FromReg: X86::XMM24, .ToReg: 75U },
6119 { .FromReg: X86::XMM25, .ToReg: 76U },
6120 { .FromReg: X86::XMM26, .ToReg: 77U },
6121 { .FromReg: X86::XMM27, .ToReg: 78U },
6122 { .FromReg: X86::XMM28, .ToReg: 79U },
6123 { .FromReg: X86::XMM29, .ToReg: 80U },
6124 { .FromReg: X86::XMM30, .ToReg: 81U },
6125 { .FromReg: X86::XMM31, .ToReg: 82U },
6126 { .FromReg: X86::YMM16, .ToReg: 67U },
6127 { .FromReg: X86::YMM17, .ToReg: 68U },
6128 { .FromReg: X86::YMM18, .ToReg: 69U },
6129 { .FromReg: X86::YMM19, .ToReg: 70U },
6130 { .FromReg: X86::YMM20, .ToReg: 71U },
6131 { .FromReg: X86::YMM21, .ToReg: 72U },
6132 { .FromReg: X86::YMM22, .ToReg: 73U },
6133 { .FromReg: X86::YMM23, .ToReg: 74U },
6134 { .FromReg: X86::YMM24, .ToReg: 75U },
6135 { .FromReg: X86::YMM25, .ToReg: 76U },
6136 { .FromReg: X86::YMM26, .ToReg: 77U },
6137 { .FromReg: X86::YMM27, .ToReg: 78U },
6138 { .FromReg: X86::YMM28, .ToReg: 79U },
6139 { .FromReg: X86::YMM29, .ToReg: 80U },
6140 { .FromReg: X86::YMM30, .ToReg: 81U },
6141 { .FromReg: X86::YMM31, .ToReg: 82U },
6142 { .FromReg: X86::ZMM0, .ToReg: 17U },
6143 { .FromReg: X86::ZMM1, .ToReg: 18U },
6144 { .FromReg: X86::ZMM2, .ToReg: 19U },
6145 { .FromReg: X86::ZMM3, .ToReg: 20U },
6146 { .FromReg: X86::ZMM4, .ToReg: 21U },
6147 { .FromReg: X86::ZMM5, .ToReg: 22U },
6148 { .FromReg: X86::ZMM6, .ToReg: 23U },
6149 { .FromReg: X86::ZMM7, .ToReg: 24U },
6150 { .FromReg: X86::ZMM8, .ToReg: 25U },
6151 { .FromReg: X86::ZMM9, .ToReg: 26U },
6152 { .FromReg: X86::ZMM10, .ToReg: 27U },
6153 { .FromReg: X86::ZMM11, .ToReg: 28U },
6154 { .FromReg: X86::ZMM12, .ToReg: 29U },
6155 { .FromReg: X86::ZMM13, .ToReg: 30U },
6156 { .FromReg: X86::ZMM14, .ToReg: 31U },
6157 { .FromReg: X86::ZMM15, .ToReg: 32U },
6158 { .FromReg: X86::ZMM16, .ToReg: 67U },
6159 { .FromReg: X86::ZMM17, .ToReg: 68U },
6160 { .FromReg: X86::ZMM18, .ToReg: 69U },
6161 { .FromReg: X86::ZMM19, .ToReg: 70U },
6162 { .FromReg: X86::ZMM20, .ToReg: 71U },
6163 { .FromReg: X86::ZMM21, .ToReg: 72U },
6164 { .FromReg: X86::ZMM22, .ToReg: 73U },
6165 { .FromReg: X86::ZMM23, .ToReg: 74U },
6166 { .FromReg: X86::ZMM24, .ToReg: 75U },
6167 { .FromReg: X86::ZMM25, .ToReg: 76U },
6168 { .FromReg: X86::ZMM26, .ToReg: 77U },
6169 { .FromReg: X86::ZMM27, .ToReg: 78U },
6170 { .FromReg: X86::ZMM28, .ToReg: 79U },
6171 { .FromReg: X86::ZMM29, .ToReg: 80U },
6172 { .FromReg: X86::ZMM30, .ToReg: 81U },
6173 { .FromReg: X86::ZMM31, .ToReg: 82U },
6174 { .FromReg: X86::R16, .ToReg: 130U },
6175 { .FromReg: X86::R17, .ToReg: 131U },
6176 { .FromReg: X86::R18, .ToReg: 132U },
6177 { .FromReg: X86::R19, .ToReg: 133U },
6178 { .FromReg: X86::R20, .ToReg: 134U },
6179 { .FromReg: X86::R21, .ToReg: 135U },
6180 { .FromReg: X86::R22, .ToReg: 136U },
6181 { .FromReg: X86::R23, .ToReg: 137U },
6182 { .FromReg: X86::R24, .ToReg: 138U },
6183 { .FromReg: X86::R25, .ToReg: 139U },
6184 { .FromReg: X86::R26, .ToReg: 140U },
6185 { .FromReg: X86::R27, .ToReg: 141U },
6186 { .FromReg: X86::R28, .ToReg: 142U },
6187 { .FromReg: X86::R29, .ToReg: 143U },
6188 { .FromReg: X86::R30, .ToReg: 144U },
6189 { .FromReg: X86::R31, .ToReg: 145U },
6190};
6191extern const unsigned X86EHFlavour0L2DwarfSize = std::size(X86EHFlavour0L2Dwarf);
6192
6193extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
6194 { .FromReg: X86::CS, .ToReg: -2U },
6195 { .FromReg: X86::DS, .ToReg: -2U },
6196 { .FromReg: X86::EAX, .ToReg: 0U },
6197 { .FromReg: X86::EBP, .ToReg: 4U },
6198 { .FromReg: X86::EBX, .ToReg: 3U },
6199 { .FromReg: X86::ECX, .ToReg: 1U },
6200 { .FromReg: X86::EDI, .ToReg: 7U },
6201 { .FromReg: X86::EDX, .ToReg: 2U },
6202 { .FromReg: X86::EFLAGS, .ToReg: 9U },
6203 { .FromReg: X86::EIP, .ToReg: 8U },
6204 { .FromReg: X86::ES, .ToReg: -2U },
6205 { .FromReg: X86::ESI, .ToReg: 6U },
6206 { .FromReg: X86::ESP, .ToReg: 5U },
6207 { .FromReg: X86::FS, .ToReg: -2U },
6208 { .FromReg: X86::FS_BASE, .ToReg: -2U },
6209 { .FromReg: X86::GS, .ToReg: -2U },
6210 { .FromReg: X86::GS_BASE, .ToReg: -2U },
6211 { .FromReg: X86::RAX, .ToReg: -2U },
6212 { .FromReg: X86::RBP, .ToReg: -2U },
6213 { .FromReg: X86::RBX, .ToReg: -2U },
6214 { .FromReg: X86::RCX, .ToReg: -2U },
6215 { .FromReg: X86::RDI, .ToReg: -2U },
6216 { .FromReg: X86::RDX, .ToReg: -2U },
6217 { .FromReg: X86::RFLAGS, .ToReg: -2U },
6218 { .FromReg: X86::RIP, .ToReg: -2U },
6219 { .FromReg: X86::RSI, .ToReg: -2U },
6220 { .FromReg: X86::RSP, .ToReg: -2U },
6221 { .FromReg: X86::SS, .ToReg: -2U },
6222 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
6223 { .FromReg: X86::MM0, .ToReg: 29U },
6224 { .FromReg: X86::MM1, .ToReg: 30U },
6225 { .FromReg: X86::MM2, .ToReg: 31U },
6226 { .FromReg: X86::MM3, .ToReg: 32U },
6227 { .FromReg: X86::MM4, .ToReg: 33U },
6228 { .FromReg: X86::MM5, .ToReg: 34U },
6229 { .FromReg: X86::MM6, .ToReg: 35U },
6230 { .FromReg: X86::MM7, .ToReg: 36U },
6231 { .FromReg: X86::R8, .ToReg: -2U },
6232 { .FromReg: X86::R9, .ToReg: -2U },
6233 { .FromReg: X86::R10, .ToReg: -2U },
6234 { .FromReg: X86::R11, .ToReg: -2U },
6235 { .FromReg: X86::R12, .ToReg: -2U },
6236 { .FromReg: X86::R13, .ToReg: -2U },
6237 { .FromReg: X86::R14, .ToReg: -2U },
6238 { .FromReg: X86::R15, .ToReg: -2U },
6239 { .FromReg: X86::ST0, .ToReg: 12U },
6240 { .FromReg: X86::ST1, .ToReg: 13U },
6241 { .FromReg: X86::ST2, .ToReg: 14U },
6242 { .FromReg: X86::ST3, .ToReg: 15U },
6243 { .FromReg: X86::ST4, .ToReg: 16U },
6244 { .FromReg: X86::ST5, .ToReg: 17U },
6245 { .FromReg: X86::ST6, .ToReg: 18U },
6246 { .FromReg: X86::ST7, .ToReg: 19U },
6247 { .FromReg: X86::XMM0, .ToReg: 21U },
6248 { .FromReg: X86::XMM1, .ToReg: 22U },
6249 { .FromReg: X86::XMM2, .ToReg: 23U },
6250 { .FromReg: X86::XMM3, .ToReg: 24U },
6251 { .FromReg: X86::XMM4, .ToReg: 25U },
6252 { .FromReg: X86::XMM5, .ToReg: 26U },
6253 { .FromReg: X86::XMM6, .ToReg: 27U },
6254 { .FromReg: X86::XMM7, .ToReg: 28U },
6255 { .FromReg: X86::XMM8, .ToReg: -2U },
6256 { .FromReg: X86::XMM9, .ToReg: -2U },
6257 { .FromReg: X86::XMM10, .ToReg: -2U },
6258 { .FromReg: X86::XMM11, .ToReg: -2U },
6259 { .FromReg: X86::XMM12, .ToReg: -2U },
6260 { .FromReg: X86::XMM13, .ToReg: -2U },
6261 { .FromReg: X86::XMM14, .ToReg: -2U },
6262 { .FromReg: X86::XMM15, .ToReg: -2U },
6263 { .FromReg: X86::YMM0, .ToReg: 21U },
6264 { .FromReg: X86::YMM1, .ToReg: 22U },
6265 { .FromReg: X86::YMM2, .ToReg: 23U },
6266 { .FromReg: X86::YMM3, .ToReg: 24U },
6267 { .FromReg: X86::YMM4, .ToReg: 25U },
6268 { .FromReg: X86::YMM5, .ToReg: 26U },
6269 { .FromReg: X86::YMM6, .ToReg: 27U },
6270 { .FromReg: X86::YMM7, .ToReg: 28U },
6271 { .FromReg: X86::YMM8, .ToReg: -2U },
6272 { .FromReg: X86::YMM9, .ToReg: -2U },
6273 { .FromReg: X86::YMM10, .ToReg: -2U },
6274 { .FromReg: X86::YMM11, .ToReg: -2U },
6275 { .FromReg: X86::YMM12, .ToReg: -2U },
6276 { .FromReg: X86::YMM13, .ToReg: -2U },
6277 { .FromReg: X86::YMM14, .ToReg: -2U },
6278 { .FromReg: X86::YMM15, .ToReg: -2U },
6279 { .FromReg: X86::K0, .ToReg: 93U },
6280 { .FromReg: X86::K1, .ToReg: 94U },
6281 { .FromReg: X86::K2, .ToReg: 95U },
6282 { .FromReg: X86::K3, .ToReg: 96U },
6283 { .FromReg: X86::K4, .ToReg: 97U },
6284 { .FromReg: X86::K5, .ToReg: 98U },
6285 { .FromReg: X86::K6, .ToReg: 99U },
6286 { .FromReg: X86::K7, .ToReg: 100U },
6287 { .FromReg: X86::XMM16, .ToReg: -2U },
6288 { .FromReg: X86::XMM17, .ToReg: -2U },
6289 { .FromReg: X86::XMM18, .ToReg: -2U },
6290 { .FromReg: X86::XMM19, .ToReg: -2U },
6291 { .FromReg: X86::XMM20, .ToReg: -2U },
6292 { .FromReg: X86::XMM21, .ToReg: -2U },
6293 { .FromReg: X86::XMM22, .ToReg: -2U },
6294 { .FromReg: X86::XMM23, .ToReg: -2U },
6295 { .FromReg: X86::XMM24, .ToReg: -2U },
6296 { .FromReg: X86::XMM25, .ToReg: -2U },
6297 { .FromReg: X86::XMM26, .ToReg: -2U },
6298 { .FromReg: X86::XMM27, .ToReg: -2U },
6299 { .FromReg: X86::XMM28, .ToReg: -2U },
6300 { .FromReg: X86::XMM29, .ToReg: -2U },
6301 { .FromReg: X86::XMM30, .ToReg: -2U },
6302 { .FromReg: X86::XMM31, .ToReg: -2U },
6303 { .FromReg: X86::YMM16, .ToReg: -2U },
6304 { .FromReg: X86::YMM17, .ToReg: -2U },
6305 { .FromReg: X86::YMM18, .ToReg: -2U },
6306 { .FromReg: X86::YMM19, .ToReg: -2U },
6307 { .FromReg: X86::YMM20, .ToReg: -2U },
6308 { .FromReg: X86::YMM21, .ToReg: -2U },
6309 { .FromReg: X86::YMM22, .ToReg: -2U },
6310 { .FromReg: X86::YMM23, .ToReg: -2U },
6311 { .FromReg: X86::YMM24, .ToReg: -2U },
6312 { .FromReg: X86::YMM25, .ToReg: -2U },
6313 { .FromReg: X86::YMM26, .ToReg: -2U },
6314 { .FromReg: X86::YMM27, .ToReg: -2U },
6315 { .FromReg: X86::YMM28, .ToReg: -2U },
6316 { .FromReg: X86::YMM29, .ToReg: -2U },
6317 { .FromReg: X86::YMM30, .ToReg: -2U },
6318 { .FromReg: X86::YMM31, .ToReg: -2U },
6319 { .FromReg: X86::ZMM0, .ToReg: 21U },
6320 { .FromReg: X86::ZMM1, .ToReg: 22U },
6321 { .FromReg: X86::ZMM2, .ToReg: 23U },
6322 { .FromReg: X86::ZMM3, .ToReg: 24U },
6323 { .FromReg: X86::ZMM4, .ToReg: 25U },
6324 { .FromReg: X86::ZMM5, .ToReg: 26U },
6325 { .FromReg: X86::ZMM6, .ToReg: 27U },
6326 { .FromReg: X86::ZMM7, .ToReg: 28U },
6327 { .FromReg: X86::ZMM8, .ToReg: -2U },
6328 { .FromReg: X86::ZMM9, .ToReg: -2U },
6329 { .FromReg: X86::ZMM10, .ToReg: -2U },
6330 { .FromReg: X86::ZMM11, .ToReg: -2U },
6331 { .FromReg: X86::ZMM12, .ToReg: -2U },
6332 { .FromReg: X86::ZMM13, .ToReg: -2U },
6333 { .FromReg: X86::ZMM14, .ToReg: -2U },
6334 { .FromReg: X86::ZMM15, .ToReg: -2U },
6335 { .FromReg: X86::ZMM16, .ToReg: -2U },
6336 { .FromReg: X86::ZMM17, .ToReg: -2U },
6337 { .FromReg: X86::ZMM18, .ToReg: -2U },
6338 { .FromReg: X86::ZMM19, .ToReg: -2U },
6339 { .FromReg: X86::ZMM20, .ToReg: -2U },
6340 { .FromReg: X86::ZMM21, .ToReg: -2U },
6341 { .FromReg: X86::ZMM22, .ToReg: -2U },
6342 { .FromReg: X86::ZMM23, .ToReg: -2U },
6343 { .FromReg: X86::ZMM24, .ToReg: -2U },
6344 { .FromReg: X86::ZMM25, .ToReg: -2U },
6345 { .FromReg: X86::ZMM26, .ToReg: -2U },
6346 { .FromReg: X86::ZMM27, .ToReg: -2U },
6347 { .FromReg: X86::ZMM28, .ToReg: -2U },
6348 { .FromReg: X86::ZMM29, .ToReg: -2U },
6349 { .FromReg: X86::ZMM30, .ToReg: -2U },
6350 { .FromReg: X86::ZMM31, .ToReg: -2U },
6351 { .FromReg: X86::R16, .ToReg: -2U },
6352 { .FromReg: X86::R17, .ToReg: -2U },
6353 { .FromReg: X86::R18, .ToReg: -2U },
6354 { .FromReg: X86::R19, .ToReg: -2U },
6355 { .FromReg: X86::R20, .ToReg: -2U },
6356 { .FromReg: X86::R21, .ToReg: -2U },
6357 { .FromReg: X86::R22, .ToReg: -2U },
6358 { .FromReg: X86::R23, .ToReg: -2U },
6359 { .FromReg: X86::R24, .ToReg: -2U },
6360 { .FromReg: X86::R25, .ToReg: -2U },
6361 { .FromReg: X86::R26, .ToReg: -2U },
6362 { .FromReg: X86::R27, .ToReg: -2U },
6363 { .FromReg: X86::R28, .ToReg: -2U },
6364 { .FromReg: X86::R29, .ToReg: -2U },
6365 { .FromReg: X86::R30, .ToReg: -2U },
6366 { .FromReg: X86::R31, .ToReg: -2U },
6367};
6368extern const unsigned X86EHFlavour1L2DwarfSize = std::size(X86EHFlavour1L2Dwarf);
6369
6370extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
6371 { .FromReg: X86::CS, .ToReg: 41U },
6372 { .FromReg: X86::DS, .ToReg: 43U },
6373 { .FromReg: X86::EAX, .ToReg: 0U },
6374 { .FromReg: X86::EBP, .ToReg: 5U },
6375 { .FromReg: X86::EBX, .ToReg: 3U },
6376 { .FromReg: X86::ECX, .ToReg: 1U },
6377 { .FromReg: X86::EDI, .ToReg: 7U },
6378 { .FromReg: X86::EDX, .ToReg: 2U },
6379 { .FromReg: X86::EFLAGS, .ToReg: 9U },
6380 { .FromReg: X86::EIP, .ToReg: 8U },
6381 { .FromReg: X86::ES, .ToReg: 40U },
6382 { .FromReg: X86::ESI, .ToReg: 6U },
6383 { .FromReg: X86::ESP, .ToReg: 4U },
6384 { .FromReg: X86::FS, .ToReg: 44U },
6385 { .FromReg: X86::FS_BASE, .ToReg: -2U },
6386 { .FromReg: X86::GS, .ToReg: 45U },
6387 { .FromReg: X86::GS_BASE, .ToReg: -2U },
6388 { .FromReg: X86::RAX, .ToReg: -2U },
6389 { .FromReg: X86::RBP, .ToReg: -2U },
6390 { .FromReg: X86::RBX, .ToReg: -2U },
6391 { .FromReg: X86::RCX, .ToReg: -2U },
6392 { .FromReg: X86::RDI, .ToReg: -2U },
6393 { .FromReg: X86::RDX, .ToReg: -2U },
6394 { .FromReg: X86::RFLAGS, .ToReg: -2U },
6395 { .FromReg: X86::RIP, .ToReg: -2U },
6396 { .FromReg: X86::RSI, .ToReg: -2U },
6397 { .FromReg: X86::RSP, .ToReg: -2U },
6398 { .FromReg: X86::SS, .ToReg: 42U },
6399 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
6400 { .FromReg: X86::MM0, .ToReg: 29U },
6401 { .FromReg: X86::MM1, .ToReg: 30U },
6402 { .FromReg: X86::MM2, .ToReg: 31U },
6403 { .FromReg: X86::MM3, .ToReg: 32U },
6404 { .FromReg: X86::MM4, .ToReg: 33U },
6405 { .FromReg: X86::MM5, .ToReg: 34U },
6406 { .FromReg: X86::MM6, .ToReg: 35U },
6407 { .FromReg: X86::MM7, .ToReg: 36U },
6408 { .FromReg: X86::R8, .ToReg: -2U },
6409 { .FromReg: X86::R9, .ToReg: -2U },
6410 { .FromReg: X86::R10, .ToReg: -2U },
6411 { .FromReg: X86::R11, .ToReg: -2U },
6412 { .FromReg: X86::R12, .ToReg: -2U },
6413 { .FromReg: X86::R13, .ToReg: -2U },
6414 { .FromReg: X86::R14, .ToReg: -2U },
6415 { .FromReg: X86::R15, .ToReg: -2U },
6416 { .FromReg: X86::ST0, .ToReg: 11U },
6417 { .FromReg: X86::ST1, .ToReg: 12U },
6418 { .FromReg: X86::ST2, .ToReg: 13U },
6419 { .FromReg: X86::ST3, .ToReg: 14U },
6420 { .FromReg: X86::ST4, .ToReg: 15U },
6421 { .FromReg: X86::ST5, .ToReg: 16U },
6422 { .FromReg: X86::ST6, .ToReg: 17U },
6423 { .FromReg: X86::ST7, .ToReg: 18U },
6424 { .FromReg: X86::XMM0, .ToReg: 21U },
6425 { .FromReg: X86::XMM1, .ToReg: 22U },
6426 { .FromReg: X86::XMM2, .ToReg: 23U },
6427 { .FromReg: X86::XMM3, .ToReg: 24U },
6428 { .FromReg: X86::XMM4, .ToReg: 25U },
6429 { .FromReg: X86::XMM5, .ToReg: 26U },
6430 { .FromReg: X86::XMM6, .ToReg: 27U },
6431 { .FromReg: X86::XMM7, .ToReg: 28U },
6432 { .FromReg: X86::XMM8, .ToReg: -2U },
6433 { .FromReg: X86::XMM9, .ToReg: -2U },
6434 { .FromReg: X86::XMM10, .ToReg: -2U },
6435 { .FromReg: X86::XMM11, .ToReg: -2U },
6436 { .FromReg: X86::XMM12, .ToReg: -2U },
6437 { .FromReg: X86::XMM13, .ToReg: -2U },
6438 { .FromReg: X86::XMM14, .ToReg: -2U },
6439 { .FromReg: X86::XMM15, .ToReg: -2U },
6440 { .FromReg: X86::YMM0, .ToReg: 21U },
6441 { .FromReg: X86::YMM1, .ToReg: 22U },
6442 { .FromReg: X86::YMM2, .ToReg: 23U },
6443 { .FromReg: X86::YMM3, .ToReg: 24U },
6444 { .FromReg: X86::YMM4, .ToReg: 25U },
6445 { .FromReg: X86::YMM5, .ToReg: 26U },
6446 { .FromReg: X86::YMM6, .ToReg: 27U },
6447 { .FromReg: X86::YMM7, .ToReg: 28U },
6448 { .FromReg: X86::YMM8, .ToReg: -2U },
6449 { .FromReg: X86::YMM9, .ToReg: -2U },
6450 { .FromReg: X86::YMM10, .ToReg: -2U },
6451 { .FromReg: X86::YMM11, .ToReg: -2U },
6452 { .FromReg: X86::YMM12, .ToReg: -2U },
6453 { .FromReg: X86::YMM13, .ToReg: -2U },
6454 { .FromReg: X86::YMM14, .ToReg: -2U },
6455 { .FromReg: X86::YMM15, .ToReg: -2U },
6456 { .FromReg: X86::K0, .ToReg: 93U },
6457 { .FromReg: X86::K1, .ToReg: 94U },
6458 { .FromReg: X86::K2, .ToReg: 95U },
6459 { .FromReg: X86::K3, .ToReg: 96U },
6460 { .FromReg: X86::K4, .ToReg: 97U },
6461 { .FromReg: X86::K5, .ToReg: 98U },
6462 { .FromReg: X86::K6, .ToReg: 99U },
6463 { .FromReg: X86::K7, .ToReg: 100U },
6464 { .FromReg: X86::XMM16, .ToReg: -2U },
6465 { .FromReg: X86::XMM17, .ToReg: -2U },
6466 { .FromReg: X86::XMM18, .ToReg: -2U },
6467 { .FromReg: X86::XMM19, .ToReg: -2U },
6468 { .FromReg: X86::XMM20, .ToReg: -2U },
6469 { .FromReg: X86::XMM21, .ToReg: -2U },
6470 { .FromReg: X86::XMM22, .ToReg: -2U },
6471 { .FromReg: X86::XMM23, .ToReg: -2U },
6472 { .FromReg: X86::XMM24, .ToReg: -2U },
6473 { .FromReg: X86::XMM25, .ToReg: -2U },
6474 { .FromReg: X86::XMM26, .ToReg: -2U },
6475 { .FromReg: X86::XMM27, .ToReg: -2U },
6476 { .FromReg: X86::XMM28, .ToReg: -2U },
6477 { .FromReg: X86::XMM29, .ToReg: -2U },
6478 { .FromReg: X86::XMM30, .ToReg: -2U },
6479 { .FromReg: X86::XMM31, .ToReg: -2U },
6480 { .FromReg: X86::YMM16, .ToReg: -2U },
6481 { .FromReg: X86::YMM17, .ToReg: -2U },
6482 { .FromReg: X86::YMM18, .ToReg: -2U },
6483 { .FromReg: X86::YMM19, .ToReg: -2U },
6484 { .FromReg: X86::YMM20, .ToReg: -2U },
6485 { .FromReg: X86::YMM21, .ToReg: -2U },
6486 { .FromReg: X86::YMM22, .ToReg: -2U },
6487 { .FromReg: X86::YMM23, .ToReg: -2U },
6488 { .FromReg: X86::YMM24, .ToReg: -2U },
6489 { .FromReg: X86::YMM25, .ToReg: -2U },
6490 { .FromReg: X86::YMM26, .ToReg: -2U },
6491 { .FromReg: X86::YMM27, .ToReg: -2U },
6492 { .FromReg: X86::YMM28, .ToReg: -2U },
6493 { .FromReg: X86::YMM29, .ToReg: -2U },
6494 { .FromReg: X86::YMM30, .ToReg: -2U },
6495 { .FromReg: X86::YMM31, .ToReg: -2U },
6496 { .FromReg: X86::ZMM0, .ToReg: 21U },
6497 { .FromReg: X86::ZMM1, .ToReg: 22U },
6498 { .FromReg: X86::ZMM2, .ToReg: 23U },
6499 { .FromReg: X86::ZMM3, .ToReg: 24U },
6500 { .FromReg: X86::ZMM4, .ToReg: 25U },
6501 { .FromReg: X86::ZMM5, .ToReg: 26U },
6502 { .FromReg: X86::ZMM6, .ToReg: 27U },
6503 { .FromReg: X86::ZMM7, .ToReg: 28U },
6504 { .FromReg: X86::ZMM8, .ToReg: -2U },
6505 { .FromReg: X86::ZMM9, .ToReg: -2U },
6506 { .FromReg: X86::ZMM10, .ToReg: -2U },
6507 { .FromReg: X86::ZMM11, .ToReg: -2U },
6508 { .FromReg: X86::ZMM12, .ToReg: -2U },
6509 { .FromReg: X86::ZMM13, .ToReg: -2U },
6510 { .FromReg: X86::ZMM14, .ToReg: -2U },
6511 { .FromReg: X86::ZMM15, .ToReg: -2U },
6512 { .FromReg: X86::ZMM16, .ToReg: -2U },
6513 { .FromReg: X86::ZMM17, .ToReg: -2U },
6514 { .FromReg: X86::ZMM18, .ToReg: -2U },
6515 { .FromReg: X86::ZMM19, .ToReg: -2U },
6516 { .FromReg: X86::ZMM20, .ToReg: -2U },
6517 { .FromReg: X86::ZMM21, .ToReg: -2U },
6518 { .FromReg: X86::ZMM22, .ToReg: -2U },
6519 { .FromReg: X86::ZMM23, .ToReg: -2U },
6520 { .FromReg: X86::ZMM24, .ToReg: -2U },
6521 { .FromReg: X86::ZMM25, .ToReg: -2U },
6522 { .FromReg: X86::ZMM26, .ToReg: -2U },
6523 { .FromReg: X86::ZMM27, .ToReg: -2U },
6524 { .FromReg: X86::ZMM28, .ToReg: -2U },
6525 { .FromReg: X86::ZMM29, .ToReg: -2U },
6526 { .FromReg: X86::ZMM30, .ToReg: -2U },
6527 { .FromReg: X86::ZMM31, .ToReg: -2U },
6528 { .FromReg: X86::R16, .ToReg: -2U },
6529 { .FromReg: X86::R17, .ToReg: -2U },
6530 { .FromReg: X86::R18, .ToReg: -2U },
6531 { .FromReg: X86::R19, .ToReg: -2U },
6532 { .FromReg: X86::R20, .ToReg: -2U },
6533 { .FromReg: X86::R21, .ToReg: -2U },
6534 { .FromReg: X86::R22, .ToReg: -2U },
6535 { .FromReg: X86::R23, .ToReg: -2U },
6536 { .FromReg: X86::R24, .ToReg: -2U },
6537 { .FromReg: X86::R25, .ToReg: -2U },
6538 { .FromReg: X86::R26, .ToReg: -2U },
6539 { .FromReg: X86::R27, .ToReg: -2U },
6540 { .FromReg: X86::R28, .ToReg: -2U },
6541 { .FromReg: X86::R29, .ToReg: -2U },
6542 { .FromReg: X86::R30, .ToReg: -2U },
6543 { .FromReg: X86::R31, .ToReg: -2U },
6544};
6545extern const unsigned X86EHFlavour2L2DwarfSize = std::size(X86EHFlavour2L2Dwarf);
6546
6547extern const uint16_t X86RegEncodingTable[] = {
6548 0,
6549 4,
6550 0,
6551 0,
6552 7,
6553 3,
6554 5,
6555 65535,
6556 5,
6557 3,
6558 5,
6559 1,
6560 1,
6561 1,
6562 0,
6563 6,
6564 7,
6565 65535,
6566 7,
6567 2,
6568 3,
6569 2,
6570 0,
6571 5,
6572 3,
6573 1,
6574 7,
6575 2,
6576 0,
6577 0,
6578 4,
6579 0,
6580 6,
6581 4,
6582 0,
6583 0,
6584 4,
6585 0,
6586 5,
6587 0,
6588 65535,
6589 65535,
6590 65535,
6591 65535,
6592 65535,
6593 65535,
6594 65535,
6595 65535,
6596 65535,
6597 0,
6598 0,
6599 0,
6600 5,
6601 3,
6602 1,
6603 7,
6604 2,
6605 0,
6606 0,
6607 4,
6608 6,
6609 4,
6610 6,
6611 65535,
6612 6,
6613 4,
6614 65535,
6615 4,
6616 2,
6617 0,
6618 0,
6619 0,
6620 1,
6621 2,
6622 3,
6623 4,
6624 5,
6625 6,
6626 7,
6627 8,
6628 9,
6629 10,
6630 11,
6631 12,
6632 13,
6633 14,
6634 15,
6635 0,
6636 1,
6637 2,
6638 3,
6639 4,
6640 5,
6641 6,
6642 7,
6643 8,
6644 9,
6645 10,
6646 11,
6647 12,
6648 13,
6649 14,
6650 15,
6651 0,
6652 0,
6653 0,
6654 0,
6655 0,
6656 0,
6657 0,
6658 0,
6659 0,
6660 1,
6661 2,
6662 3,
6663 4,
6664 5,
6665 6,
6666 7,
6667 8,
6668 9,
6669 10,
6670 11,
6671 12,
6672 13,
6673 14,
6674 15,
6675 0,
6676 1,
6677 2,
6678 3,
6679 4,
6680 5,
6681 6,
6682 7,
6683 0,
6684 1,
6685 2,
6686 3,
6687 4,
6688 5,
6689 6,
6690 7,
6691 8,
6692 9,
6693 10,
6694 11,
6695 12,
6696 13,
6697 14,
6698 15,
6699 8,
6700 9,
6701 10,
6702 11,
6703 12,
6704 13,
6705 14,
6706 15,
6707 65535,
6708 65535,
6709 65535,
6710 65535,
6711 65535,
6712 65535,
6713 65535,
6714 65535,
6715 8,
6716 9,
6717 10,
6718 11,
6719 12,
6720 13,
6721 14,
6722 15,
6723 8,
6724 9,
6725 10,
6726 11,
6727 12,
6728 13,
6729 14,
6730 15,
6731 65535,
6732 65535,
6733 65535,
6734 65535,
6735 65535,
6736 65535,
6737 65535,
6738 65535,
6739 0,
6740 1,
6741 2,
6742 3,
6743 4,
6744 5,
6745 6,
6746 7,
6747 8,
6748 9,
6749 10,
6750 11,
6751 12,
6752 13,
6753 14,
6754 15,
6755 0,
6756 1,
6757 2,
6758 3,
6759 4,
6760 5,
6761 6,
6762 7,
6763 16,
6764 17,
6765 18,
6766 19,
6767 20,
6768 21,
6769 22,
6770 23,
6771 24,
6772 25,
6773 26,
6774 27,
6775 28,
6776 29,
6777 30,
6778 31,
6779 16,
6780 17,
6781 18,
6782 19,
6783 20,
6784 21,
6785 22,
6786 23,
6787 24,
6788 25,
6789 26,
6790 27,
6791 28,
6792 29,
6793 30,
6794 31,
6795 0,
6796 1,
6797 2,
6798 3,
6799 4,
6800 5,
6801 6,
6802 7,
6803 8,
6804 9,
6805 10,
6806 11,
6807 12,
6808 13,
6809 14,
6810 15,
6811 16,
6812 17,
6813 18,
6814 19,
6815 20,
6816 21,
6817 22,
6818 23,
6819 24,
6820 25,
6821 26,
6822 27,
6823 28,
6824 29,
6825 30,
6826 31,
6827 0,
6828 2,
6829 4,
6830 6,
6831 0,
6832 0,
6833 1,
6834 2,
6835 3,
6836 4,
6837 5,
6838 6,
6839 7,
6840 16,
6841 17,
6842 18,
6843 19,
6844 20,
6845 21,
6846 22,
6847 23,
6848 24,
6849 25,
6850 26,
6851 27,
6852 28,
6853 29,
6854 30,
6855 31,
6856 16,
6857 17,
6858 18,
6859 19,
6860 20,
6861 21,
6862 22,
6863 23,
6864 24,
6865 25,
6866 26,
6867 27,
6868 28,
6869 29,
6870 30,
6871 31,
6872 65535,
6873 65535,
6874 65535,
6875 65535,
6876 65535,
6877 65535,
6878 65535,
6879 65535,
6880 65535,
6881 65535,
6882 65535,
6883 65535,
6884 65535,
6885 65535,
6886 65535,
6887 65535,
6888 16,
6889 17,
6890 18,
6891 19,
6892 20,
6893 21,
6894 22,
6895 23,
6896 24,
6897 25,
6898 26,
6899 27,
6900 28,
6901 29,
6902 30,
6903 31,
6904 16,
6905 17,
6906 18,
6907 19,
6908 20,
6909 21,
6910 22,
6911 23,
6912 24,
6913 25,
6914 26,
6915 27,
6916 28,
6917 29,
6918 30,
6919 31,
6920 65535,
6921 65535,
6922 65535,
6923 65535,
6924 65535,
6925 65535,
6926 65535,
6927 65535,
6928 65535,
6929 65535,
6930 65535,
6931 65535,
6932 65535,
6933 65535,
6934 65535,
6935 65535,
6936};
6937static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
6938 RI->InitMCRegisterInfo(D: X86RegDesc, NR: 388, RA, PC, C: X86MCRegisterClassStorage.Classes, NC: 135, RURoots: X86RegUnitRoots, NRU: 221, DL: X86RegDiffLists, RUMS: X86LaneMaskLists, Strings: X86RegStrings, ClassStrings: X86RegClassStrings, SubIndices: X86SubRegIdxLists, NumIndices: 11,
6939RET: X86RegEncodingTable, RUI: nullptr);
6940
6941 switch (DwarfFlavour) {
6942 default:
6943 llvm_unreachable("Unknown DWARF flavour");
6944 case 0:
6945 RI->mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour0Dwarf2L, Size: X86DwarfFlavour0Dwarf2LSize, isEH: false);
6946 break;
6947 case 1:
6948 RI->mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour1Dwarf2L, Size: X86DwarfFlavour1Dwarf2LSize, isEH: false);
6949 break;
6950 case 2:
6951 RI->mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour2Dwarf2L, Size: X86DwarfFlavour2Dwarf2LSize, isEH: false);
6952 break;
6953 }
6954 switch (EHFlavour) {
6955 default:
6956 llvm_unreachable("Unknown DWARF flavour");
6957 case 0:
6958 RI->mapDwarfRegsToLLVMRegs(Map: X86EHFlavour0Dwarf2L, Size: X86EHFlavour0Dwarf2LSize, isEH: true);
6959 break;
6960 case 1:
6961 RI->mapDwarfRegsToLLVMRegs(Map: X86EHFlavour1Dwarf2L, Size: X86EHFlavour1Dwarf2LSize, isEH: true);
6962 break;
6963 case 2:
6964 RI->mapDwarfRegsToLLVMRegs(Map: X86EHFlavour2Dwarf2L, Size: X86EHFlavour2Dwarf2LSize, isEH: true);
6965 break;
6966 }
6967 switch (DwarfFlavour) {
6968 default:
6969 llvm_unreachable("Unknown DWARF flavour");
6970 case 0:
6971 RI->mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour0L2Dwarf, Size: X86DwarfFlavour0L2DwarfSize, isEH: false);
6972 break;
6973 case 1:
6974 RI->mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour1L2Dwarf, Size: X86DwarfFlavour1L2DwarfSize, isEH: false);
6975 break;
6976 case 2:
6977 RI->mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour2L2Dwarf, Size: X86DwarfFlavour2L2DwarfSize, isEH: false);
6978 break;
6979 }
6980 switch (EHFlavour) {
6981 default:
6982 llvm_unreachable("Unknown DWARF flavour");
6983 case 0:
6984 RI->mapLLVMRegsToDwarfRegs(Map: X86EHFlavour0L2Dwarf, Size: X86EHFlavour0L2DwarfSize, isEH: true);
6985 break;
6986 case 1:
6987 RI->mapLLVMRegsToDwarfRegs(Map: X86EHFlavour1L2Dwarf, Size: X86EHFlavour1L2DwarfSize, isEH: true);
6988 break;
6989 case 2:
6990 RI->mapLLVMRegsToDwarfRegs(Map: X86EHFlavour2L2Dwarf, Size: X86EHFlavour2L2DwarfSize, isEH: true);
6991 break;
6992 }
6993}
6994
6995
6996} // namespace llvm
6997