1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t X86RegDiffLists[] = {
12 /* 0 */ -56, -56, 0,
13 /* 3 */ -32, -48, 0,
14 /* 6 */ 32, -16, -48, 0,
15 /* 10 */ 48, -16, -48, 0,
16 /* 14 */ 16, -8, -48, 0,
17 /* 18 */ 24, -8, -48, 0,
18 /* 22 */ -28, 32, 2, -1, -18, 0,
19 /* 28 */ -32, -16, 0,
20 /* 31 */ -28, 30, 2, -1, -16, 0,
21 /* 37 */ -2, -4, 0,
22 /* 40 */ -29, 20, -3, 0,
23 /* 44 */ -4, -1, 0,
24 /* 47 */ -2, -1, 0,
25 /* 50 */ -1, -1, 0,
26 /* 53 */ 2, -1, 0,
27 /* 56 */ -72, 1, 0,
28 /* 59 */ -71, 1, 0,
29 /* 62 */ -70, 1, 0,
30 /* 65 */ -69, 1, 0,
31 /* 68 */ 1, 1, 0,
32 /* 71 */ 3, 0,
33 /* 73 */ 1, 7, 0,
34 /* 76 */ 3, 7, 0,
35 /* 79 */ -24, 8, 0,
36 /* 82 */ 1, 11, 0,
37 /* 85 */ 1, 14, 0,
38 /* 88 */ -48, 16, 0,
39 /* 91 */ 48, 8, -24, 8, 24, 0,
40 /* 97 */ -29, -10, 2, -1, 27, 0,
41 /* 103 */ -2, -32, 28, 0,
42 /* 107 */ -1, -32, 28, 0,
43 /* 111 */ -2, -30, 28, 0,
44 /* 115 */ -1, -30, 28, 0,
45 /* 119 */ -15, 28, 0,
46 /* 122 */ -20, 29, 0,
47 /* 125 */ -18, 29, 0,
48 /* 128 */ -17, 29, 0,
49 /* 131 */ 2, 6, 29, 0,
50 /* 135 */ 6, 6, 29, 0,
51 /* 139 */ -2, 10, 29, 0,
52 /* 143 */ -1, 10, 29, 0,
53 /* 147 */ 2, 12, 29, 0,
54 /* 151 */ 3, 12, 29, 0,
55 /* 155 */ 4, 15, 29, 0,
56 /* 159 */ 5, 15, 29, 0,
57 /* 163 */ -2, 17, 29, 0,
58 /* 167 */ -1, 17, 29, 0,
59 /* 171 */ 1, 19, 29, 0,
60 /* 175 */ 2, 19, 29, 0,
61 /* 179 */ -29, -6, -2, -4, 30, 0,
62 /* 185 */ 16, 32, 0,
63 /* 188 */ -29, -12, -2, -1, 33, 0,
64 /* 194 */ -29, -17, 2, -1, 34, 0,
65 /* 200 */ -29, -15, -4, -1, 38, 0,
66 /* 206 */ -29, -19, -1, -1, 39, 0,
67 /* 212 */ 48, 16, -48, 16, 48, 0,
68 /* 218 */ 56, 56, 0,
69 /* 221 */ 68, 0,
70 /* 223 */ 69, 0,
71 /* 225 */ 70, 0,
72 /* 227 */ 71, 0,
73 /* 229 */ 72, 0,
74};
75
76extern const LaneBitmask X86LaneMaskLists[] = {
77 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
78 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004),
79 /* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000008),
80 /* 7 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
81 /* 10 */ LaneBitmask(0x0000000000000007), LaneBitmask(0x0000000000000008),
82 /* 12 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020),
83 /* 14 */ LaneBitmask(0x0000000000000040),
84 /* 15 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
85};
86
87extern const uint16_t X86SubRegIdxLists[] = {
88 /* 0 */ 1, 2,
89 /* 2 */ 1, 3,
90 /* 4 */ 6, 4, 1, 2, 5,
91 /* 9 */ 6, 4, 1, 3, 5,
92 /* 14 */ 6, 4, 5,
93 /* 17 */ 7, 8,
94 /* 19 */ 10, 9,
95};
96
97
98#ifdef __GNUC__
99#pragma GCC diagnostic push
100#pragma GCC diagnostic ignored "-Woverlength-strings"
101#endif
102extern const char X86RegStrings[] = {
103 /* 0 */ "XMM10\000"
104 /* 6 */ "YMM10\000"
105 /* 12 */ "ZMM10\000"
106 /* 18 */ "CR10\000"
107 /* 23 */ "DR10\000"
108 /* 28 */ "XMM20\000"
109 /* 34 */ "YMM20\000"
110 /* 40 */ "ZMM20\000"
111 /* 46 */ "R20\000"
112 /* 50 */ "XMM30\000"
113 /* 56 */ "YMM30\000"
114 /* 62 */ "ZMM30\000"
115 /* 68 */ "R30\000"
116 /* 72 */ "K0\000"
117 /* 75 */ "TMM0\000"
118 /* 80 */ "XMM0\000"
119 /* 85 */ "YMM0\000"
120 /* 90 */ "ZMM0\000"
121 /* 95 */ "FP0\000"
122 /* 99 */ "CR0\000"
123 /* 103 */ "DR0\000"
124 /* 107 */ "ST0\000"
125 /* 111 */ "XMM11\000"
126 /* 117 */ "YMM11\000"
127 /* 123 */ "ZMM11\000"
128 /* 129 */ "CR11\000"
129 /* 134 */ "DR11\000"
130 /* 139 */ "XMM21\000"
131 /* 145 */ "YMM21\000"
132 /* 151 */ "ZMM21\000"
133 /* 157 */ "R21\000"
134 /* 161 */ "XMM31\000"
135 /* 167 */ "YMM31\000"
136 /* 173 */ "ZMM31\000"
137 /* 179 */ "R31\000"
138 /* 183 */ "K0_K1\000"
139 /* 189 */ "TMM1\000"
140 /* 194 */ "XMM1\000"
141 /* 199 */ "YMM1\000"
142 /* 204 */ "ZMM1\000"
143 /* 209 */ "FP1\000"
144 /* 213 */ "CR1\000"
145 /* 217 */ "DR1\000"
146 /* 221 */ "ST1\000"
147 /* 225 */ "XMM12\000"
148 /* 231 */ "YMM12\000"
149 /* 237 */ "ZMM12\000"
150 /* 243 */ "CR12\000"
151 /* 248 */ "DR12\000"
152 /* 253 */ "XMM22\000"
153 /* 259 */ "YMM22\000"
154 /* 265 */ "ZMM22\000"
155 /* 271 */ "R22\000"
156 /* 275 */ "K2\000"
157 /* 278 */ "TMM2\000"
158 /* 283 */ "XMM2\000"
159 /* 288 */ "YMM2\000"
160 /* 293 */ "ZMM2\000"
161 /* 298 */ "FP2\000"
162 /* 302 */ "CR2\000"
163 /* 306 */ "DR2\000"
164 /* 310 */ "ST2\000"
165 /* 314 */ "XMM13\000"
166 /* 320 */ "YMM13\000"
167 /* 326 */ "ZMM13\000"
168 /* 332 */ "CR13\000"
169 /* 337 */ "DR13\000"
170 /* 342 */ "XMM23\000"
171 /* 348 */ "YMM23\000"
172 /* 354 */ "ZMM23\000"
173 /* 360 */ "R23\000"
174 /* 364 */ "K2_K3\000"
175 /* 370 */ "TMM3\000"
176 /* 375 */ "XMM3\000"
177 /* 380 */ "YMM3\000"
178 /* 385 */ "ZMM3\000"
179 /* 390 */ "FP3\000"
180 /* 394 */ "CR3\000"
181 /* 398 */ "DR3\000"
182 /* 402 */ "ST3\000"
183 /* 406 */ "XMM14\000"
184 /* 412 */ "YMM14\000"
185 /* 418 */ "ZMM14\000"
186 /* 424 */ "CR14\000"
187 /* 429 */ "DR14\000"
188 /* 434 */ "XMM24\000"
189 /* 440 */ "YMM24\000"
190 /* 446 */ "ZMM24\000"
191 /* 452 */ "R24\000"
192 /* 456 */ "K4\000"
193 /* 459 */ "TMM4\000"
194 /* 464 */ "XMM4\000"
195 /* 469 */ "YMM4\000"
196 /* 474 */ "ZMM4\000"
197 /* 479 */ "FP4\000"
198 /* 483 */ "CR4\000"
199 /* 487 */ "DR4\000"
200 /* 491 */ "ST4\000"
201 /* 495 */ "XMM15\000"
202 /* 501 */ "YMM15\000"
203 /* 507 */ "ZMM15\000"
204 /* 513 */ "CR15\000"
205 /* 518 */ "DR15\000"
206 /* 523 */ "XMM25\000"
207 /* 529 */ "YMM25\000"
208 /* 535 */ "ZMM25\000"
209 /* 541 */ "R25\000"
210 /* 545 */ "K4_K5\000"
211 /* 551 */ "TMM5\000"
212 /* 556 */ "XMM5\000"
213 /* 561 */ "YMM5\000"
214 /* 566 */ "ZMM5\000"
215 /* 571 */ "FP5\000"
216 /* 575 */ "CR5\000"
217 /* 579 */ "DR5\000"
218 /* 583 */ "ST5\000"
219 /* 587 */ "XMM16\000"
220 /* 593 */ "YMM16\000"
221 /* 599 */ "ZMM16\000"
222 /* 605 */ "R16\000"
223 /* 609 */ "XMM26\000"
224 /* 615 */ "YMM26\000"
225 /* 621 */ "ZMM26\000"
226 /* 627 */ "R26\000"
227 /* 631 */ "K6\000"
228 /* 634 */ "TMM6\000"
229 /* 639 */ "XMM6\000"
230 /* 644 */ "YMM6\000"
231 /* 649 */ "ZMM6\000"
232 /* 654 */ "FP6\000"
233 /* 658 */ "CR6\000"
234 /* 662 */ "DR6\000"
235 /* 666 */ "ST6\000"
236 /* 670 */ "XMM17\000"
237 /* 676 */ "YMM17\000"
238 /* 682 */ "ZMM17\000"
239 /* 688 */ "R17\000"
240 /* 692 */ "XMM27\000"
241 /* 698 */ "YMM27\000"
242 /* 704 */ "ZMM27\000"
243 /* 710 */ "R27\000"
244 /* 714 */ "K6_K7\000"
245 /* 720 */ "TMM7\000"
246 /* 725 */ "XMM7\000"
247 /* 730 */ "YMM7\000"
248 /* 735 */ "ZMM7\000"
249 /* 740 */ "FP7\000"
250 /* 744 */ "CR7\000"
251 /* 748 */ "DR7\000"
252 /* 752 */ "ST7\000"
253 /* 756 */ "XMM18\000"
254 /* 762 */ "YMM18\000"
255 /* 768 */ "ZMM18\000"
256 /* 774 */ "R18\000"
257 /* 778 */ "XMM28\000"
258 /* 784 */ "YMM28\000"
259 /* 790 */ "ZMM28\000"
260 /* 796 */ "R28\000"
261 /* 800 */ "XMM8\000"
262 /* 805 */ "YMM8\000"
263 /* 810 */ "ZMM8\000"
264 /* 815 */ "CR8\000"
265 /* 819 */ "DR8\000"
266 /* 823 */ "XMM19\000"
267 /* 829 */ "YMM19\000"
268 /* 835 */ "ZMM19\000"
269 /* 841 */ "R19\000"
270 /* 845 */ "XMM29\000"
271 /* 851 */ "YMM29\000"
272 /* 857 */ "ZMM29\000"
273 /* 863 */ "R29\000"
274 /* 867 */ "XMM9\000"
275 /* 872 */ "YMM9\000"
276 /* 877 */ "ZMM9\000"
277 /* 882 */ "CR9\000"
278 /* 886 */ "DR9\000"
279 /* 890 */ "R10B\000"
280 /* 895 */ "R20B\000"
281 /* 900 */ "R30B\000"
282 /* 905 */ "R11B\000"
283 /* 910 */ "R21B\000"
284 /* 915 */ "R31B\000"
285 /* 920 */ "R12B\000"
286 /* 925 */ "R22B\000"
287 /* 930 */ "R13B\000"
288 /* 935 */ "R23B\000"
289 /* 940 */ "R14B\000"
290 /* 945 */ "R24B\000"
291 /* 950 */ "R15B\000"
292 /* 955 */ "R25B\000"
293 /* 960 */ "R16B\000"
294 /* 965 */ "R26B\000"
295 /* 970 */ "R17B\000"
296 /* 975 */ "R27B\000"
297 /* 980 */ "R18B\000"
298 /* 985 */ "R28B\000"
299 /* 990 */ "R8B\000"
300 /* 994 */ "R19B\000"
301 /* 999 */ "R29B\000"
302 /* 1004 */ "R9B\000"
303 /* 1008 */ "R10D\000"
304 /* 1013 */ "R20D\000"
305 /* 1018 */ "R30D\000"
306 /* 1023 */ "R11D\000"
307 /* 1028 */ "R21D\000"
308 /* 1033 */ "R31D\000"
309 /* 1038 */ "R12D\000"
310 /* 1043 */ "R22D\000"
311 /* 1048 */ "R13D\000"
312 /* 1053 */ "R23D\000"
313 /* 1058 */ "R14D\000"
314 /* 1063 */ "R24D\000"
315 /* 1068 */ "R15D\000"
316 /* 1073 */ "R25D\000"
317 /* 1078 */ "R16D\000"
318 /* 1083 */ "R26D\000"
319 /* 1088 */ "R17D\000"
320 /* 1093 */ "R27D\000"
321 /* 1098 */ "R18D\000"
322 /* 1103 */ "R28D\000"
323 /* 1108 */ "R8D\000"
324 /* 1112 */ "R19D\000"
325 /* 1117 */ "R29D\000"
326 /* 1122 */ "R9D\000"
327 /* 1126 */ "FS_BASE\000"
328 /* 1134 */ "GS_BASE\000"
329 /* 1142 */ "DF\000"
330 /* 1145 */ "TMMCFG\000"
331 /* 1152 */ "AH\000"
332 /* 1155 */ "R10BH\000"
333 /* 1161 */ "R20BH\000"
334 /* 1167 */ "R30BH\000"
335 /* 1173 */ "R11BH\000"
336 /* 1179 */ "R21BH\000"
337 /* 1185 */ "R31BH\000"
338 /* 1191 */ "R12BH\000"
339 /* 1197 */ "R22BH\000"
340 /* 1203 */ "R13BH\000"
341 /* 1209 */ "R23BH\000"
342 /* 1215 */ "R14BH\000"
343 /* 1221 */ "R24BH\000"
344 /* 1227 */ "R15BH\000"
345 /* 1233 */ "R25BH\000"
346 /* 1239 */ "R16BH\000"
347 /* 1245 */ "R26BH\000"
348 /* 1251 */ "R17BH\000"
349 /* 1257 */ "R27BH\000"
350 /* 1263 */ "R18BH\000"
351 /* 1269 */ "R28BH\000"
352 /* 1275 */ "R8BH\000"
353 /* 1280 */ "R19BH\000"
354 /* 1286 */ "R29BH\000"
355 /* 1292 */ "R9BH\000"
356 /* 1297 */ "CH\000"
357 /* 1300 */ "DH\000"
358 /* 1303 */ "DIH\000"
359 /* 1307 */ "SIH\000"
360 /* 1311 */ "BPH\000"
361 /* 1315 */ "SPH\000"
362 /* 1319 */ "R10WH\000"
363 /* 1325 */ "R20WH\000"
364 /* 1331 */ "R30WH\000"
365 /* 1337 */ "R11WH\000"
366 /* 1343 */ "R21WH\000"
367 /* 1349 */ "R31WH\000"
368 /* 1355 */ "R12WH\000"
369 /* 1361 */ "R22WH\000"
370 /* 1367 */ "R13WH\000"
371 /* 1373 */ "R23WH\000"
372 /* 1379 */ "R14WH\000"
373 /* 1385 */ "R24WH\000"
374 /* 1391 */ "R15WH\000"
375 /* 1397 */ "R25WH\000"
376 /* 1403 */ "R16WH\000"
377 /* 1409 */ "R26WH\000"
378 /* 1415 */ "R17WH\000"
379 /* 1421 */ "R27WH\000"
380 /* 1427 */ "R18WH\000"
381 /* 1433 */ "R28WH\000"
382 /* 1439 */ "R8WH\000"
383 /* 1444 */ "R19WH\000"
384 /* 1450 */ "R29WH\000"
385 /* 1456 */ "R9WH\000"
386 /* 1461 */ "EDI\000"
387 /* 1465 */ "HDI\000"
388 /* 1469 */ "RDI\000"
389 /* 1473 */ "ESI\000"
390 /* 1477 */ "HSI\000"
391 /* 1481 */ "RSI\000"
392 /* 1485 */ "AL\000"
393 /* 1488 */ "BL\000"
394 /* 1491 */ "CL\000"
395 /* 1494 */ "DL\000"
396 /* 1497 */ "DIL\000"
397 /* 1501 */ "SIL\000"
398 /* 1505 */ "BPL\000"
399 /* 1509 */ "SPL\000"
400 /* 1513 */ "EBP\000"
401 /* 1517 */ "HBP\000"
402 /* 1521 */ "RBP\000"
403 /* 1525 */ "EIP\000"
404 /* 1529 */ "HIP\000"
405 /* 1533 */ "RIP\000"
406 /* 1537 */ "ESP\000"
407 /* 1541 */ "HSP\000"
408 /* 1545 */ "RSP\000"
409 /* 1549 */ "SSP\000"
410 /* 1553 */ "MXCSR\000"
411 /* 1559 */ "CS\000"
412 /* 1562 */ "DS\000"
413 /* 1565 */ "ES\000"
414 /* 1568 */ "FS\000"
415 /* 1571 */ "_EFLAGS\000"
416 /* 1579 */ "RFLAGS\000"
417 /* 1586 */ "SS\000"
418 /* 1589 */ "R10W\000"
419 /* 1594 */ "R20W\000"
420 /* 1599 */ "R30W\000"
421 /* 1604 */ "R11W\000"
422 /* 1609 */ "R21W\000"
423 /* 1614 */ "R31W\000"
424 /* 1619 */ "R12W\000"
425 /* 1624 */ "R22W\000"
426 /* 1629 */ "R13W\000"
427 /* 1634 */ "R23W\000"
428 /* 1639 */ "R14W\000"
429 /* 1644 */ "R24W\000"
430 /* 1649 */ "R15W\000"
431 /* 1654 */ "R25W\000"
432 /* 1659 */ "R16W\000"
433 /* 1664 */ "R26W\000"
434 /* 1669 */ "R17W\000"
435 /* 1674 */ "R27W\000"
436 /* 1679 */ "R18W\000"
437 /* 1684 */ "R28W\000"
438 /* 1689 */ "R8W\000"
439 /* 1693 */ "R19W\000"
440 /* 1698 */ "R29W\000"
441 /* 1703 */ "R9W\000"
442 /* 1707 */ "FPCW\000"
443 /* 1712 */ "FPSW\000"
444 /* 1717 */ "EAX\000"
445 /* 1721 */ "HAX\000"
446 /* 1725 */ "RAX\000"
447 /* 1729 */ "EBX\000"
448 /* 1733 */ "HBX\000"
449 /* 1737 */ "RBX\000"
450 /* 1741 */ "ECX\000"
451 /* 1745 */ "HCX\000"
452 /* 1749 */ "RCX\000"
453 /* 1753 */ "EDX\000"
454 /* 1757 */ "HDX\000"
455 /* 1761 */ "RDX\000"
456 /* 1765 */ "EIZ\000"
457 /* 1769 */ "RIZ\000"
458};
459#ifdef __GNUC__
460#pragma GCC diagnostic pop
461#endif
462
463extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
464 { .Name: 5, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
465 { .Name: 1152, .SubRegs: 2, .SuperRegs: 175, .SubRegIndices: 2, .RegUnits: 8192, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
466 { .Name: 1485, .SubRegs: 2, .SuperRegs: 171, .SubRegIndices: 2, .RegUnits: 8193, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
467 { .Name: 1718, .SubRegs: 50, .SuperRegs: 172, .SubRegIndices: 0, .RegUnits: 233472, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
468 { .Name: 1158, .SubRegs: 2, .SuperRegs: 159, .SubRegIndices: 2, .RegUnits: 8194, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
469 { .Name: 1488, .SubRegs: 2, .SuperRegs: 155, .SubRegIndices: 2, .RegUnits: 8195, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
470 { .Name: 1514, .SubRegs: 53, .SuperRegs: 164, .SubRegIndices: 2, .RegUnits: 233476, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
471 { .Name: 1311, .SubRegs: 2, .SuperRegs: 167, .SubRegIndices: 2, .RegUnits: 8197, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
472 { .Name: 1505, .SubRegs: 2, .SuperRegs: 163, .SubRegIndices: 2, .RegUnits: 8196, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
473 { .Name: 1730, .SubRegs: 44, .SuperRegs: 156, .SubRegIndices: 0, .RegUnits: 233474, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
474 { .Name: 1297, .SubRegs: 2, .SuperRegs: 151, .SubRegIndices: 2, .RegUnits: 8198, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
475 { .Name: 1491, .SubRegs: 2, .SuperRegs: 147, .SubRegIndices: 2, .RegUnits: 8199, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
476 { .Name: 1559, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8200, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
477 { .Name: 1742, .SubRegs: 47, .SuperRegs: 148, .SubRegIndices: 0, .RegUnits: 233478, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
478 { .Name: 1142, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8201, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
479 { .Name: 1300, .SubRegs: 2, .SuperRegs: 135, .SubRegIndices: 2, .RegUnits: 8202, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
480 { .Name: 1462, .SubRegs: 53, .SuperRegs: 140, .SubRegIndices: 2, .RegUnits: 233483, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
481 { .Name: 1303, .SubRegs: 2, .SuperRegs: 143, .SubRegIndices: 2, .RegUnits: 8204, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
482 { .Name: 1497, .SubRegs: 2, .SuperRegs: 139, .SubRegIndices: 2, .RegUnits: 8203, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
483 { .Name: 1494, .SubRegs: 2, .SuperRegs: 131, .SubRegIndices: 2, .RegUnits: 8205, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
484 { .Name: 1562, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8206, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
485 { .Name: 1754, .SubRegs: 37, .SuperRegs: 132, .SubRegIndices: 0, .RegUnits: 290826, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
486 { .Name: 1717, .SubRegs: 207, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 348160, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
487 { .Name: 1513, .SubRegs: 195, .SuperRegs: 123, .SubRegIndices: 10, .RegUnits: 335876, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
488 { .Name: 1729, .SubRegs: 201, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 348162, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
489 { .Name: 1741, .SubRegs: 189, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 335878, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
490 { .Name: 1461, .SubRegs: 98, .SuperRegs: 123, .SubRegIndices: 10, .RegUnits: 299019, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
491 { .Name: 1753, .SubRegs: 180, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 311306, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
492 { .Name: 1572, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8213, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
493 { .Name: 1525, .SubRegs: 41, .SuperRegs: 123, .SubRegIndices: 15, .RegUnits: 233494, .RegUnitLaneMasks: 10, .IsConstant: 0, .IsArtificial: 0 },
494 { .Name: 1765, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8216, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
495 { .Name: 1565, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8217, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
496 { .Name: 1473, .SubRegs: 32, .SuperRegs: 105, .SubRegIndices: 10, .RegUnits: 278554, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
497 { .Name: 1537, .SubRegs: 23, .SuperRegs: 105, .SubRegIndices: 10, .RegUnits: 278557, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
498 { .Name: 1707, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8224, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
499 { .Name: 1712, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8225, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
500 { .Name: 1568, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8226, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
501 { .Name: 1126, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8227, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
502 { .Name: 1576, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8228, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
503 { .Name: 1134, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8229, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
504 { .Name: 1721, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8207, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
505 { .Name: 1517, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8208, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
506 { .Name: 1733, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8209, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
507 { .Name: 1745, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8210, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
508 { .Name: 1465, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8211, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
509 { .Name: 1757, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8212, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
510 { .Name: 1529, .SubRegs: 2, .SuperRegs: 128, .SubRegIndices: 2, .RegUnits: 8215, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
511 { .Name: 1477, .SubRegs: 2, .SuperRegs: 119, .SubRegIndices: 2, .RegUnits: 8220, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
512 { .Name: 1541, .SubRegs: 2, .SuperRegs: 119, .SubRegIndices: 2, .RegUnits: 8223, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
513 { .Name: 1526, .SubRegs: 2, .SuperRegs: 122, .SubRegIndices: 2, .RegUnits: 8214, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
514 { .Name: 1553, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8230, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
515 { .Name: 1725, .SubRegs: 206, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 348160, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
516 { .Name: 1521, .SubRegs: 194, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 335876, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
517 { .Name: 1737, .SubRegs: 200, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 348162, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
518 { .Name: 1749, .SubRegs: 188, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 335878, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
519 { .Name: 1469, .SubRegs: 97, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 299019, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
520 { .Name: 1761, .SubRegs: 179, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 311306, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
521 { .Name: 1579, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8231, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
522 { .Name: 1533, .SubRegs: 40, .SuperRegs: 2, .SubRegIndices: 14, .RegUnits: 233494, .RegUnitLaneMasks: 10, .IsConstant: 0, .IsArtificial: 0 },
523 { .Name: 1769, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8232, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
524 { .Name: 1481, .SubRegs: 31, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278554, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
525 { .Name: 1545, .SubRegs: 22, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278557, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
526 { .Name: 1474, .SubRegs: 53, .SuperRegs: 112, .SubRegIndices: 2, .RegUnits: 233498, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
527 { .Name: 1307, .SubRegs: 2, .SuperRegs: 115, .SubRegIndices: 2, .RegUnits: 8219, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
528 { .Name: 1501, .SubRegs: 2, .SuperRegs: 111, .SubRegIndices: 2, .RegUnits: 8218, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
529 { .Name: 1538, .SubRegs: 53, .SuperRegs: 104, .SubRegIndices: 2, .RegUnits: 233501, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
530 { .Name: 1315, .SubRegs: 2, .SuperRegs: 107, .SubRegIndices: 2, .RegUnits: 8222, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
531 { .Name: 1509, .SubRegs: 2, .SuperRegs: 103, .SubRegIndices: 2, .RegUnits: 8221, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
532 { .Name: 1586, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8233, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
533 { .Name: 1549, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8234, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
534 { .Name: 1571, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8235, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
535 { .Name: 99, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8236, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
536 { .Name: 213, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8237, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
537 { .Name: 302, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8238, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
538 { .Name: 394, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8239, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
539 { .Name: 483, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8240, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
540 { .Name: 575, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8241, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
541 { .Name: 658, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8242, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
542 { .Name: 744, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8243, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
543 { .Name: 815, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8244, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
544 { .Name: 882, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8245, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
545 { .Name: 18, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8246, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
546 { .Name: 129, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8247, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
547 { .Name: 243, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8248, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
548 { .Name: 332, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8249, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
549 { .Name: 424, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8250, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
550 { .Name: 513, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8251, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
551 { .Name: 103, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8252, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
552 { .Name: 217, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8253, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
553 { .Name: 306, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8254, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
554 { .Name: 398, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8255, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
555 { .Name: 487, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8256, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
556 { .Name: 579, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8257, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
557 { .Name: 662, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8258, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
558 { .Name: 748, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8259, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
559 { .Name: 819, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8260, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
560 { .Name: 886, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8261, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
561 { .Name: 23, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8262, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
562 { .Name: 134, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8263, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
563 { .Name: 248, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8264, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
564 { .Name: 337, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8265, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
565 { .Name: 429, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8266, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
566 { .Name: 518, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8267, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
567 { .Name: 95, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8268, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
568 { .Name: 209, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8269, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
569 { .Name: 298, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8270, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
570 { .Name: 390, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8271, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
571 { .Name: 479, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8272, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
572 { .Name: 571, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8273, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
573 { .Name: 654, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8274, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
574 { .Name: 740, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8275, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
575 { .Name: 76, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8276, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
576 { .Name: 190, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8277, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
577 { .Name: 279, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8278, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
578 { .Name: 371, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8279, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
579 { .Name: 460, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8280, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
580 { .Name: 552, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8281, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
581 { .Name: 635, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8282, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
582 { .Name: 721, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8283, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
583 { .Name: 816, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278620, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
584 { .Name: 883, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278623, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
585 { .Name: 19, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278626, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
586 { .Name: 130, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278629, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
587 { .Name: 244, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278632, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
588 { .Name: 333, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278635, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
589 { .Name: 425, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278638, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
590 { .Name: 514, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278641, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
591 { .Name: 107, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8308, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
592 { .Name: 221, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8309, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
593 { .Name: 310, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8310, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
594 { .Name: 402, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8311, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
595 { .Name: 491, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8312, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
596 { .Name: 583, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8313, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
597 { .Name: 666, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8314, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
598 { .Name: 752, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8315, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
599 { .Name: 80, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8316, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
600 { .Name: 194, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8317, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
601 { .Name: 283, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8318, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
602 { .Name: 375, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8319, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
603 { .Name: 464, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8320, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
604 { .Name: 556, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8321, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
605 { .Name: 639, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8322, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
606 { .Name: 725, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8323, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
607 { .Name: 800, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8324, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
608 { .Name: 867, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8325, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
609 { .Name: 0, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8326, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
610 { .Name: 111, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8327, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
611 { .Name: 225, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8328, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
612 { .Name: 314, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8329, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
613 { .Name: 406, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8330, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
614 { .Name: 495, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8331, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
615 { .Name: 990, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8284, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
616 { .Name: 1004, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8287, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
617 { .Name: 890, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8290, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
618 { .Name: 905, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8293, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
619 { .Name: 920, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8296, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
620 { .Name: 930, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8299, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
621 { .Name: 940, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8302, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
622 { .Name: 950, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8305, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
623 { .Name: 1275, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8285, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
624 { .Name: 1292, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8288, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
625 { .Name: 1155, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8291, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
626 { .Name: 1173, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8294, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
627 { .Name: 1191, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8297, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
628 { .Name: 1203, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8300, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
629 { .Name: 1215, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8303, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
630 { .Name: 1227, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8306, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
631 { .Name: 1108, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278620, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
632 { .Name: 1122, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278623, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
633 { .Name: 1008, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278626, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
634 { .Name: 1023, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278629, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
635 { .Name: 1038, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278632, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
636 { .Name: 1048, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278635, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
637 { .Name: 1058, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278638, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
638 { .Name: 1068, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278641, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
639 { .Name: 1689, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233564, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
640 { .Name: 1703, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233567, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
641 { .Name: 1589, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233570, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
642 { .Name: 1604, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233573, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
643 { .Name: 1619, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233576, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
644 { .Name: 1629, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233579, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
645 { .Name: 1639, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233582, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
646 { .Name: 1649, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233585, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
647 { .Name: 1439, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8286, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
648 { .Name: 1456, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8289, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
649 { .Name: 1319, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8292, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
650 { .Name: 1337, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8295, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
651 { .Name: 1355, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8298, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
652 { .Name: 1367, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8301, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
653 { .Name: 1379, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8304, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
654 { .Name: 1391, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8307, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
655 { .Name: 85, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8316, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
656 { .Name: 199, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8317, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
657 { .Name: 288, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8318, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
658 { .Name: 380, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8319, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
659 { .Name: 469, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8320, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
660 { .Name: 561, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8321, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
661 { .Name: 644, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8322, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
662 { .Name: 730, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8323, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
663 { .Name: 805, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8324, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
664 { .Name: 872, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8325, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
665 { .Name: 6, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8326, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
666 { .Name: 117, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8327, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
667 { .Name: 231, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8328, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
668 { .Name: 320, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8329, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
669 { .Name: 412, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8330, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
670 { .Name: 501, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8331, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
671 { .Name: 72, .SubRegs: 2, .SuperRegs: 229, .SubRegIndices: 2, .RegUnits: 8332, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
672 { .Name: 186, .SubRegs: 2, .SuperRegs: 227, .SubRegIndices: 2, .RegUnits: 8333, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
673 { .Name: 275, .SubRegs: 2, .SuperRegs: 227, .SubRegIndices: 2, .RegUnits: 8334, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
674 { .Name: 367, .SubRegs: 2, .SuperRegs: 225, .SubRegIndices: 2, .RegUnits: 8335, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
675 { .Name: 456, .SubRegs: 2, .SuperRegs: 225, .SubRegIndices: 2, .RegUnits: 8336, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
676 { .Name: 548, .SubRegs: 2, .SuperRegs: 223, .SubRegIndices: 2, .RegUnits: 8337, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
677 { .Name: 631, .SubRegs: 2, .SuperRegs: 223, .SubRegIndices: 2, .RegUnits: 8338, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
678 { .Name: 717, .SubRegs: 2, .SuperRegs: 221, .SubRegIndices: 2, .RegUnits: 8339, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
679 { .Name: 587, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8340, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
680 { .Name: 670, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8341, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
681 { .Name: 756, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8342, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
682 { .Name: 823, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8343, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
683 { .Name: 28, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8344, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
684 { .Name: 139, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8345, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
685 { .Name: 253, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8346, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
686 { .Name: 342, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8347, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
687 { .Name: 434, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8348, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
688 { .Name: 523, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8349, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
689 { .Name: 609, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8350, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
690 { .Name: 692, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8351, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
691 { .Name: 778, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8352, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
692 { .Name: 845, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8353, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
693 { .Name: 50, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8354, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
694 { .Name: 161, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8355, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
695 { .Name: 593, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8340, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
696 { .Name: 676, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8341, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
697 { .Name: 762, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8342, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
698 { .Name: 829, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8343, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
699 { .Name: 34, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8344, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
700 { .Name: 145, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8345, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
701 { .Name: 259, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8346, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
702 { .Name: 348, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8347, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
703 { .Name: 440, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8348, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
704 { .Name: 529, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8349, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
705 { .Name: 615, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8350, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
706 { .Name: 698, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8351, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
707 { .Name: 784, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8352, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
708 { .Name: 851, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8353, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
709 { .Name: 56, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8354, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
710 { .Name: 167, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8355, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
711 { .Name: 90, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8316, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
712 { .Name: 204, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8317, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
713 { .Name: 293, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8318, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
714 { .Name: 385, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8319, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
715 { .Name: 474, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8320, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
716 { .Name: 566, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8321, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
717 { .Name: 649, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8322, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
718 { .Name: 735, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8323, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
719 { .Name: 810, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8324, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
720 { .Name: 877, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8325, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
721 { .Name: 12, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8326, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
722 { .Name: 123, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8327, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
723 { .Name: 237, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8328, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
724 { .Name: 326, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8329, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
725 { .Name: 418, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8330, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
726 { .Name: 507, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8331, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
727 { .Name: 599, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8340, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
728 { .Name: 682, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8341, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
729 { .Name: 768, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8342, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
730 { .Name: 835, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8343, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
731 { .Name: 40, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8344, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
732 { .Name: 151, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8345, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
733 { .Name: 265, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8346, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
734 { .Name: 354, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8347, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
735 { .Name: 446, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8348, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
736 { .Name: 535, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8349, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
737 { .Name: 621, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8350, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
738 { .Name: 704, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8351, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
739 { .Name: 790, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8352, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
740 { .Name: 857, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8353, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
741 { .Name: 62, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8354, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
742 { .Name: 173, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8355, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
743 { .Name: 183, .SubRegs: 56, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233612, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
744 { .Name: 364, .SubRegs: 59, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233614, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
745 { .Name: 545, .SubRegs: 62, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233616, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
746 { .Name: 714, .SubRegs: 65, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233618, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
747 { .Name: 1145, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8356, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
748 { .Name: 75, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8357, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
749 { .Name: 189, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8358, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
750 { .Name: 278, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8359, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
751 { .Name: 370, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8360, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
752 { .Name: 459, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8361, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
753 { .Name: 551, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8362, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
754 { .Name: 634, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8363, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
755 { .Name: 720, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8364, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
756 { .Name: 605, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278701, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
757 { .Name: 688, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278704, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
758 { .Name: 774, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278707, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
759 { .Name: 841, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278710, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
760 { .Name: 46, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278713, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
761 { .Name: 157, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278716, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
762 { .Name: 271, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278719, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
763 { .Name: 360, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278722, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
764 { .Name: 452, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278725, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
765 { .Name: 541, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278728, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
766 { .Name: 627, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278731, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
767 { .Name: 710, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278734, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
768 { .Name: 796, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278737, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
769 { .Name: 863, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278740, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
770 { .Name: 68, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278743, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
771 { .Name: 179, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278746, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
772 { .Name: 960, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8365, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
773 { .Name: 970, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8368, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
774 { .Name: 980, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8371, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
775 { .Name: 994, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8374, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
776 { .Name: 895, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8377, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
777 { .Name: 910, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8380, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
778 { .Name: 925, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8383, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
779 { .Name: 935, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8386, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
780 { .Name: 945, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8389, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
781 { .Name: 955, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8392, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
782 { .Name: 965, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8395, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
783 { .Name: 975, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8398, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
784 { .Name: 985, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8401, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
785 { .Name: 999, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8404, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
786 { .Name: 900, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8407, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
787 { .Name: 915, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8410, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
788 { .Name: 1239, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8366, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
789 { .Name: 1251, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8369, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
790 { .Name: 1263, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8372, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
791 { .Name: 1280, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8375, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
792 { .Name: 1161, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8378, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
793 { .Name: 1179, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8381, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
794 { .Name: 1197, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8384, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
795 { .Name: 1209, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8387, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
796 { .Name: 1221, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8390, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
797 { .Name: 1233, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8393, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
798 { .Name: 1245, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8396, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
799 { .Name: 1257, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8399, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
800 { .Name: 1269, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8402, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
801 { .Name: 1286, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8405, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
802 { .Name: 1167, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8408, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
803 { .Name: 1185, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8411, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
804 { .Name: 1078, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278701, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
805 { .Name: 1088, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278704, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
806 { .Name: 1098, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278707, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
807 { .Name: 1112, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278710, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
808 { .Name: 1013, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278713, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
809 { .Name: 1028, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278716, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
810 { .Name: 1043, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278719, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
811 { .Name: 1053, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278722, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
812 { .Name: 1063, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278725, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
813 { .Name: 1073, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278728, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
814 { .Name: 1083, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278731, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
815 { .Name: 1093, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278734, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
816 { .Name: 1103, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278737, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
817 { .Name: 1117, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278740, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
818 { .Name: 1018, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278743, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
819 { .Name: 1033, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278746, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
820 { .Name: 1659, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233645, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
821 { .Name: 1669, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233648, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
822 { .Name: 1679, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233651, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
823 { .Name: 1693, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233654, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
824 { .Name: 1594, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233657, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
825 { .Name: 1609, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233660, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
826 { .Name: 1624, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233663, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
827 { .Name: 1634, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233666, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
828 { .Name: 1644, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233669, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
829 { .Name: 1654, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233672, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
830 { .Name: 1664, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233675, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
831 { .Name: 1674, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233678, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
832 { .Name: 1684, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233681, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
833 { .Name: 1698, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233684, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
834 { .Name: 1599, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233687, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
835 { .Name: 1614, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233690, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
836 { .Name: 1403, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8367, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
837 { .Name: 1415, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8370, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
838 { .Name: 1427, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8373, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
839 { .Name: 1444, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8376, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
840 { .Name: 1325, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8379, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
841 { .Name: 1343, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8382, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
842 { .Name: 1361, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8385, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
843 { .Name: 1373, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8388, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
844 { .Name: 1385, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8391, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
845 { .Name: 1397, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8394, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
846 { .Name: 1409, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8397, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
847 { .Name: 1421, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8400, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
848 { .Name: 1433, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8403, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
849 { .Name: 1450, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8406, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
850 { .Name: 1331, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8409, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
851 { .Name: 1349, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8412, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
852};
853
854extern const MCPhysReg X86RegUnitRoots[][2] = {
855 { X86::AH },
856 { X86::AL },
857 { X86::BH },
858 { X86::BL },
859 { X86::BPL },
860 { X86::BPH },
861 { X86::CH },
862 { X86::CL },
863 { X86::CS },
864 { X86::DF },
865 { X86::DH },
866 { X86::DIL },
867 { X86::DIH },
868 { X86::DL },
869 { X86::DS },
870 { X86::HAX },
871 { X86::HBP },
872 { X86::HBX },
873 { X86::HCX },
874 { X86::HDI },
875 { X86::HDX },
876 { X86::EFLAGS },
877 { X86::IP },
878 { X86::HIP },
879 { X86::EIZ },
880 { X86::ES },
881 { X86::SIL },
882 { X86::SIH },
883 { X86::HSI },
884 { X86::SPL },
885 { X86::SPH },
886 { X86::HSP },
887 { X86::FPCW },
888 { X86::FPSW },
889 { X86::FS },
890 { X86::FS_BASE },
891 { X86::GS },
892 { X86::GS_BASE },
893 { X86::MXCSR },
894 { X86::RFLAGS },
895 { X86::RIZ },
896 { X86::SS },
897 { X86::SSP },
898 { X86::_EFLAGS },
899 { X86::CR0 },
900 { X86::CR1 },
901 { X86::CR2 },
902 { X86::CR3 },
903 { X86::CR4 },
904 { X86::CR5 },
905 { X86::CR6 },
906 { X86::CR7 },
907 { X86::CR8 },
908 { X86::CR9 },
909 { X86::CR10 },
910 { X86::CR11 },
911 { X86::CR12 },
912 { X86::CR13 },
913 { X86::CR14 },
914 { X86::CR15 },
915 { X86::DR0 },
916 { X86::DR1 },
917 { X86::DR2 },
918 { X86::DR3 },
919 { X86::DR4 },
920 { X86::DR5 },
921 { X86::DR6 },
922 { X86::DR7 },
923 { X86::DR8 },
924 { X86::DR9 },
925 { X86::DR10 },
926 { X86::DR11 },
927 { X86::DR12 },
928 { X86::DR13 },
929 { X86::DR14 },
930 { X86::DR15 },
931 { X86::FP0 },
932 { X86::FP1 },
933 { X86::FP2 },
934 { X86::FP3 },
935 { X86::FP4 },
936 { X86::FP5 },
937 { X86::FP6 },
938 { X86::FP7 },
939 { X86::MM0 },
940 { X86::MM1 },
941 { X86::MM2 },
942 { X86::MM3 },
943 { X86::MM4 },
944 { X86::MM5 },
945 { X86::MM6 },
946 { X86::MM7 },
947 { X86::R8B },
948 { X86::R8BH },
949 { X86::R8WH },
950 { X86::R9B },
951 { X86::R9BH },
952 { X86::R9WH },
953 { X86::R10B },
954 { X86::R10BH },
955 { X86::R10WH },
956 { X86::R11B },
957 { X86::R11BH },
958 { X86::R11WH },
959 { X86::R12B },
960 { X86::R12BH },
961 { X86::R12WH },
962 { X86::R13B },
963 { X86::R13BH },
964 { X86::R13WH },
965 { X86::R14B },
966 { X86::R14BH },
967 { X86::R14WH },
968 { X86::R15B },
969 { X86::R15BH },
970 { X86::R15WH },
971 { X86::ST0 },
972 { X86::ST1 },
973 { X86::ST2 },
974 { X86::ST3 },
975 { X86::ST4 },
976 { X86::ST5 },
977 { X86::ST6 },
978 { X86::ST7 },
979 { X86::XMM0 },
980 { X86::XMM1 },
981 { X86::XMM2 },
982 { X86::XMM3 },
983 { X86::XMM4 },
984 { X86::XMM5 },
985 { X86::XMM6 },
986 { X86::XMM7 },
987 { X86::XMM8 },
988 { X86::XMM9 },
989 { X86::XMM10 },
990 { X86::XMM11 },
991 { X86::XMM12 },
992 { X86::XMM13 },
993 { X86::XMM14 },
994 { X86::XMM15 },
995 { X86::K0 },
996 { X86::K1 },
997 { X86::K2 },
998 { X86::K3 },
999 { X86::K4 },
1000 { X86::K5 },
1001 { X86::K6 },
1002 { X86::K7 },
1003 { X86::XMM16 },
1004 { X86::XMM17 },
1005 { X86::XMM18 },
1006 { X86::XMM19 },
1007 { X86::XMM20 },
1008 { X86::XMM21 },
1009 { X86::XMM22 },
1010 { X86::XMM23 },
1011 { X86::XMM24 },
1012 { X86::XMM25 },
1013 { X86::XMM26 },
1014 { X86::XMM27 },
1015 { X86::XMM28 },
1016 { X86::XMM29 },
1017 { X86::XMM30 },
1018 { X86::XMM31 },
1019 { X86::TMMCFG },
1020 { X86::TMM0 },
1021 { X86::TMM1 },
1022 { X86::TMM2 },
1023 { X86::TMM3 },
1024 { X86::TMM4 },
1025 { X86::TMM5 },
1026 { X86::TMM6 },
1027 { X86::TMM7 },
1028 { X86::R16B },
1029 { X86::R16BH },
1030 { X86::R16WH },
1031 { X86::R17B },
1032 { X86::R17BH },
1033 { X86::R17WH },
1034 { X86::R18B },
1035 { X86::R18BH },
1036 { X86::R18WH },
1037 { X86::R19B },
1038 { X86::R19BH },
1039 { X86::R19WH },
1040 { X86::R20B },
1041 { X86::R20BH },
1042 { X86::R20WH },
1043 { X86::R21B },
1044 { X86::R21BH },
1045 { X86::R21WH },
1046 { X86::R22B },
1047 { X86::R22BH },
1048 { X86::R22WH },
1049 { X86::R23B },
1050 { X86::R23BH },
1051 { X86::R23WH },
1052 { X86::R24B },
1053 { X86::R24BH },
1054 { X86::R24WH },
1055 { X86::R25B },
1056 { X86::R25BH },
1057 { X86::R25WH },
1058 { X86::R26B },
1059 { X86::R26BH },
1060 { X86::R26WH },
1061 { X86::R27B },
1062 { X86::R27BH },
1063 { X86::R27WH },
1064 { X86::R28B },
1065 { X86::R28BH },
1066 { X86::R28WH },
1067 { X86::R29B },
1068 { X86::R29BH },
1069 { X86::R29WH },
1070 { X86::R30B },
1071 { X86::R30BH },
1072 { X86::R30WH },
1073 { X86::R31B },
1074 { X86::R31BH },
1075 { X86::R31WH },
1076};
1077
1078// Register classes...
1079
1080#ifdef __GNUC__
1081#pragma GCC diagnostic push
1082#pragma GCC diagnostic ignored "-Woverlength-strings"
1083#endif
1084extern const char X86RegClassStrings[] = {
1085 /* 0 */ "RFP80\000"
1086 /* 6 */ "VK1\000"
1087 /* 10 */ "VR512\000"
1088 /* 16 */ "VK32\000"
1089 /* 21 */ "RFP32\000"
1090 /* 27 */ "FR32\000"
1091 /* 32 */ "GR32\000"
1092 /* 37 */ "VK2\000"
1093 /* 41 */ "GR32_NOREX2\000"
1094 /* 53 */ "GR64_NOREX2\000"
1095 /* 65 */ "GR64_with_sub_16bit_in_GR16_NOREX2\000"
1096 /* 100 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2\000"
1097 /* 152 */ "GR8_NOREX2\000"
1098 /* 163 */ "VK64\000"
1099 /* 168 */ "RFP64\000"
1100 /* 174 */ "FR64\000"
1101 /* 179 */ "GR64\000"
1102 /* 184 */ "VR64\000"
1103 /* 189 */ "GR64_TC_and_GR64_TCW64\000"
1104 /* 212 */ "GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64\000"
1105 /* 256 */ "GR64_NOREX_and_GR64_TCW64\000"
1106 /* 282 */ "GR64PLTSafe_and_GR64_TCW64\000"
1107 /* 309 */ "VK4\000"
1108 /* 313 */ "VR512_0_15\000"
1109 /* 324 */ "GRH16\000"
1110 /* 330 */ "VK16\000"
1111 /* 335 */ "FR16\000"
1112 /* 340 */ "GR16\000"
1113 /* 345 */ "VR256\000"
1114 /* 351 */ "RFP80_7\000"
1115 /* 359 */ "VR128\000"
1116 /* 365 */ "GRH8\000"
1117 /* 370 */ "VK8\000"
1118 /* 374 */ "GR8\000"
1119 /* 378 */ "GR64_A\000"
1120 /* 385 */ "GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB\000"
1121 /* 432 */ "GR64_with_sub_32bit_in_GR32_CB\000"
1122 /* 463 */ "GR32_DC\000"
1123 /* 471 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC\000"
1124 /* 516 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC\000"
1125 /* 561 */ "GR64_with_sub_32bit_in_GR32_TC\000"
1126 /* 592 */ "GR64_NOREX2_NOSP_and_GR64_TC\000"
1127 /* 621 */ "GR64_NOREX_and_GR64_TC\000"
1128 /* 644 */ "GR64_NOREX_and_GR64PLTSafe_and_GR64_TC\000"
1129 /* 683 */ "GR64_ArgRef_and_GR64_TC\000"
1130 /* 707 */ "GR32_AD\000"
1131 /* 715 */ "GR64_AD\000"
1132 /* 723 */ "GR32_ABCD\000"
1133 /* 733 */ "GR64_ABCD\000"
1134 /* 743 */ "GR16_ABCD\000"
1135 /* 753 */ "TILE\000"
1136 /* 758 */ "DEBUG_REG\000"
1137 /* 768 */ "CONTROL_REG\000"
1138 /* 780 */ "SEGMENT_REG\000"
1139 /* 792 */ "GR8_ABCD_H\000"
1140 /* 803 */ "GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI\000"
1141 /* 849 */ "GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI\000"
1142 /* 896 */ "GR64_with_sub_32bit_in_GR32_SIDI\000"
1143 /* 929 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI\000"
1144 /* 975 */ "GR64_with_sub_32bit_in_GR32_BSI\000"
1145 /* 1007 */ "GR8_ABCD_L\000"
1146 /* 1018 */ "VK1PAIR_with_sub_mask_0_in_VK1WM\000"
1147 /* 1051 */ "VK32WM\000"
1148 /* 1058 */ "VK2WM\000"
1149 /* 1064 */ "VK64WM\000"
1150 /* 1071 */ "VK4WM\000"
1151 /* 1077 */ "VK16WM\000"
1152 /* 1084 */ "VK8WM\000"
1153 /* 1090 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP\000"
1154 /* 1137 */ "GR64_with_sub_32bit_in_GR32_DIBP\000"
1155 /* 1170 */ "GR64_and_LOW32_ADDR_ACCESS_RBP\000"
1156 /* 1201 */ "GR32_NOSP\000"
1157 /* 1211 */ "GR32_NOREX2_NOSP\000"
1158 /* 1228 */ "GR64_NOREX2_NOSP\000"
1159 /* 1245 */ "GR64_NOSP\000"
1160 /* 1255 */ "GR32_NOREX_NOSP\000"
1161 /* 1271 */ "GR64_NOREX_NOSP\000"
1162 /* 1287 */ "GR64_with_sub_32bit_in_GR32_BPSP\000"
1163 /* 1320 */ "DFCCR\000"
1164 /* 1326 */ "FPCCR\000"
1165 /* 1332 */ "VK1PAIR\000"
1166 /* 1340 */ "VK2PAIR\000"
1167 /* 1348 */ "VK4PAIR\000"
1168 /* 1356 */ "VK16PAIR\000"
1169 /* 1365 */ "VK8PAIR\000"
1170 /* 1373 */ "GR64_and_LOW32_ADDR_ACCESS\000"
1171 /* 1400 */ "RST\000"
1172 /* 1404 */ "FR32X\000"
1173 /* 1410 */ "FR64X\000"
1174 /* 1416 */ "FR16X\000"
1175 /* 1422 */ "VR256X\000"
1176 /* 1429 */ "VR128X\000"
1177 /* 1436 */ "GR32_NOREX\000"
1178 /* 1447 */ "GR64_NOREX\000"
1179 /* 1458 */ "GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX\000"
1180 /* 1504 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX\000"
1181 /* 1555 */ "GR8_NOREX\000"
1182 /* 1565 */ "GR64PLTSafe\000"
1183 /* 1577 */ "GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef\000"
1184 /* 1624 */ "GR64_with_sub_32bit_in_GR32_ArgRef\000"
1185 /* 1659 */ "GR64_ArgRef\000"
1186 /* 1671 */ "LOW32_ADDR_ACCESS_RBP_with_sub_32bit\000"
1187 /* 1708 */ "LOW32_ADDR_ACCESS_with_sub_32bit\000"
1188 /* 1741 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit\000"
1189 /* 1792 */ "GR64_with_sub_8bit\000"
1190 /* 1811 */ "GR64_TCW64_with_sub_8bit\000"
1191 /* 1836 */ "GR64_TCW64_and_GR64_TC_with_sub_8bit\000"
1192 /* 1873 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit\000"
1193};
1194#ifdef __GNUC__
1195#pragma GCC diagnostic pop
1196#endif
1197
1198using X86RegisterClassStorage = MCRegisterClassStorage<135, 1296, 927, 1070, 16, 979>;
1199extern const MCRegisterClassStorage<135, 1296, 927, 1070, 16, 979> X86MCRegisterClassStorage = {
1200 .Classes: {
1201 {
1202 offsetof(X86RegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
1203 offsetof(X86RegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
1204 .NameIdx: 374,
1205 .RegSizeInBits: 8,
1206 .RegsSize: 36,
1207 .RegSetBegin: 1, /* MinRegVal */
1208 .RegSetSize: 323, /* RegSetSize */
1209 .ID: X86::GR8RegClassID,
1210 .CopyCost: 1, /* CopyCost */
1211 .Allocatable: true, /* Allocatable */
1212 .BaseClass: false,
1213 offsetof(X86RegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
1214 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[2]) - 0 * sizeof(MCRegisterClass),
1215 .LaneMask: LaneBitmask(0x0000000000000001),
1216 .AllocationPriority: 0,
1217 .GlobalPriority: false,
1218 .TSFlags: 0x00, /* TSFlags */
1219 .SpillStackID: 0, /* SpillStackID */
1220 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1221 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1222 offsetof(X86RegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
1223 .SuperClassesSize: 0
1224 },
1225 {
1226 offsetof(X86RegisterClassStorage, Regs[36]) - 1 * sizeof(MCRegisterClass),
1227 offsetof(X86RegisterClassStorage, BitSets[41]) - 1 * sizeof(MCRegisterClass),
1228 .NameIdx: 365,
1229 .RegSizeInBits: 8,
1230 .RegsSize: 28,
1231 .RegSetBegin: 7, /* MinRegVal */
1232 .RegSetSize: 333, /* RegSetSize */
1233 .ID: X86::GRH8RegClassID,
1234 .CopyCost: 1, /* CopyCost */
1235 .Allocatable: false, /* Allocatable */
1236 .BaseClass: false,
1237 offsetof(X86RegisterClassStorage, SubClassMasks[15]) - 1 * sizeof(MCRegisterClass),
1238 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 1 * sizeof(MCRegisterClass),
1239 .LaneMask: LaneBitmask(0x0000000000000001),
1240 .AllocationPriority: 0,
1241 .GlobalPriority: false,
1242 .TSFlags: 0x00, /* TSFlags */
1243 .SpillStackID: 0, /* SpillStackID */
1244 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1245 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1246 offsetof(X86RegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
1247 .SuperClassesSize: 0
1248 },
1249 {
1250 offsetof(X86RegisterClassStorage, Regs[64]) - 2 * sizeof(MCRegisterClass),
1251 offsetof(X86RegisterClassStorage, BitSets[83]) - 2 * sizeof(MCRegisterClass),
1252 .NameIdx: 152,
1253 .RegSizeInBits: 8,
1254 .RegsSize: 20,
1255 .RegSetBegin: 1, /* MinRegVal */
1256 .RegSetSize: 158, /* RegSetSize */
1257 .ID: X86::GR8_NOREX2RegClassID,
1258 .CopyCost: 1, /* CopyCost */
1259 .Allocatable: true, /* Allocatable */
1260 .BaseClass: false,
1261 offsetof(X86RegisterClassStorage, SubClassMasks[20]) - 2 * sizeof(MCRegisterClass),
1262 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[2]) - 2 * sizeof(MCRegisterClass),
1263 .LaneMask: LaneBitmask(0x0000000000000001),
1264 .AllocationPriority: 0,
1265 .GlobalPriority: false,
1266 .TSFlags: 0x00, /* TSFlags */
1267 .SpillStackID: 0, /* SpillStackID */
1268 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1269 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1270 offsetof(X86RegisterClassStorage, SuperClasses[0]) - 2 * sizeof(MCRegisterClass),
1271 .SuperClassesSize: 1
1272 },
1273 {
1274 offsetof(X86RegisterClassStorage, Regs[84]) - 3 * sizeof(MCRegisterClass),
1275 offsetof(X86RegisterClassStorage, BitSets[103]) - 3 * sizeof(MCRegisterClass),
1276 .NameIdx: 1555,
1277 .RegSizeInBits: 8,
1278 .RegsSize: 8,
1279 .RegSetBegin: 1, /* MinRegVal */
1280 .RegSetSize: 19, /* RegSetSize */
1281 .ID: X86::GR8_NOREXRegClassID,
1282 .CopyCost: 1, /* CopyCost */
1283 .Allocatable: true, /* Allocatable */
1284 .BaseClass: false,
1285 offsetof(X86RegisterClassStorage, SubClassMasks[35]) - 3 * sizeof(MCRegisterClass),
1286 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[2]) - 3 * sizeof(MCRegisterClass),
1287 .LaneMask: LaneBitmask(0x0000000000000001),
1288 .AllocationPriority: 0,
1289 .GlobalPriority: false,
1290 .TSFlags: 0x00, /* TSFlags */
1291 .SpillStackID: 0, /* SpillStackID */
1292 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1293 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1294 offsetof(X86RegisterClassStorage, SuperClasses[1]) - 3 * sizeof(MCRegisterClass),
1295 .SuperClassesSize: 2
1296 },
1297 {
1298 offsetof(X86RegisterClassStorage, Regs[92]) - 4 * sizeof(MCRegisterClass),
1299 offsetof(X86RegisterClassStorage, BitSets[106]) - 4 * sizeof(MCRegisterClass),
1300 .NameIdx: 792,
1301 .RegSizeInBits: 8,
1302 .RegsSize: 4,
1303 .RegSetBegin: 1, /* MinRegVal */
1304 .RegSetSize: 15, /* RegSetSize */
1305 .ID: X86::GR8_ABCD_HRegClassID,
1306 .CopyCost: 1, /* CopyCost */
1307 .Allocatable: true, /* Allocatable */
1308 .BaseClass: false,
1309 offsetof(X86RegisterClassStorage, SubClassMasks[50]) - 4 * sizeof(MCRegisterClass),
1310 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[3]) - 4 * sizeof(MCRegisterClass),
1311 .LaneMask: LaneBitmask(0x0000000000000001),
1312 .AllocationPriority: 0,
1313 .GlobalPriority: false,
1314 .TSFlags: 0x00, /* TSFlags */
1315 .SpillStackID: 0, /* SpillStackID */
1316 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1317 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1318 offsetof(X86RegisterClassStorage, SuperClasses[3]) - 4 * sizeof(MCRegisterClass),
1319 .SuperClassesSize: 3
1320 },
1321 {
1322 offsetof(X86RegisterClassStorage, Regs[96]) - 5 * sizeof(MCRegisterClass),
1323 offsetof(X86RegisterClassStorage, BitSets[108]) - 5 * sizeof(MCRegisterClass),
1324 .NameIdx: 1007,
1325 .RegSizeInBits: 8,
1326 .RegsSize: 4,
1327 .RegSetBegin: 2, /* MinRegVal */
1328 .RegSetSize: 18, /* RegSetSize */
1329 .ID: X86::GR8_ABCD_LRegClassID,
1330 .CopyCost: 1, /* CopyCost */
1331 .Allocatable: true, /* Allocatable */
1332 .BaseClass: false,
1333 offsetof(X86RegisterClassStorage, SubClassMasks[60]) - 5 * sizeof(MCRegisterClass),
1334 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[0]) - 5 * sizeof(MCRegisterClass),
1335 .LaneMask: LaneBitmask(0x0000000000000001),
1336 .AllocationPriority: 0,
1337 .GlobalPriority: false,
1338 .TSFlags: 0x00, /* TSFlags */
1339 .SpillStackID: 0, /* SpillStackID */
1340 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1341 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1342 offsetof(X86RegisterClassStorage, SuperClasses[6]) - 5 * sizeof(MCRegisterClass),
1343 .SuperClassesSize: 3
1344 },
1345 {
1346 offsetof(X86RegisterClassStorage, Regs[100]) - 6 * sizeof(MCRegisterClass),
1347 offsetof(X86RegisterClassStorage, BitSets[111]) - 6 * sizeof(MCRegisterClass),
1348 .NameIdx: 324,
1349 .RegSizeInBits: 16,
1350 .RegsSize: 33,
1351 .RegSetBegin: 40, /* MinRegVal */
1352 .RegSetSize: 348, /* RegSetSize */
1353 .ID: X86::GRH16RegClassID,
1354 .CopyCost: 1, /* CopyCost */
1355 .Allocatable: false, /* Allocatable */
1356 .BaseClass: false,
1357 offsetof(X86RegisterClassStorage, SubClassMasks[70]) - 6 * sizeof(MCRegisterClass),
1358 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 6 * sizeof(MCRegisterClass),
1359 .LaneMask: LaneBitmask(0x0000000000000001),
1360 .AllocationPriority: 0,
1361 .GlobalPriority: false,
1362 .TSFlags: 0x00, /* TSFlags */
1363 .SpillStackID: 0, /* SpillStackID */
1364 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1365 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1366 offsetof(X86RegisterClassStorage, SuperClasses[9]) - 6 * sizeof(MCRegisterClass),
1367 .SuperClassesSize: 0
1368 },
1369 {
1370 offsetof(X86RegisterClassStorage, Regs[133]) - 7 * sizeof(MCRegisterClass),
1371 offsetof(X86RegisterClassStorage, BitSets[155]) - 7 * sizeof(MCRegisterClass),
1372 .NameIdx: 340,
1373 .RegSizeInBits: 16,
1374 .RegsSize: 32,
1375 .RegSetBegin: 3, /* MinRegVal */
1376 .RegSetSize: 369, /* RegSetSize */
1377 .ID: X86::GR16RegClassID,
1378 .CopyCost: 1, /* CopyCost */
1379 .Allocatable: true, /* Allocatable */
1380 .BaseClass: false,
1381 offsetof(X86RegisterClassStorage, SubClassMasks[75]) - 7 * sizeof(MCRegisterClass),
1382 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[5]) - 7 * sizeof(MCRegisterClass),
1383 .LaneMask: LaneBitmask(0x0000000000000003),
1384 .AllocationPriority: 0,
1385 .GlobalPriority: false,
1386 .TSFlags: 0x00, /* TSFlags */
1387 .SpillStackID: 0, /* SpillStackID */
1388 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1389 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1390 offsetof(X86RegisterClassStorage, SuperClasses[9]) - 7 * sizeof(MCRegisterClass),
1391 .SuperClassesSize: 0
1392 },
1393 {
1394 offsetof(X86RegisterClassStorage, Regs[165]) - 8 * sizeof(MCRegisterClass),
1395 offsetof(X86RegisterClassStorage, BitSets[202]) - 8 * sizeof(MCRegisterClass),
1396 .NameIdx: 88,
1397 .RegSizeInBits: 16,
1398 .RegsSize: 16,
1399 .RegSetBegin: 3, /* MinRegVal */
1400 .RegSetSize: 180, /* RegSetSize */
1401 .ID: X86::GR16_NOREX2RegClassID,
1402 .CopyCost: 1, /* CopyCost */
1403 .Allocatable: true, /* Allocatable */
1404 .BaseClass: false,
1405 offsetof(X86RegisterClassStorage, SubClassMasks[85]) - 8 * sizeof(MCRegisterClass),
1406 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[5]) - 8 * sizeof(MCRegisterClass),
1407 .LaneMask: LaneBitmask(0x0000000000000003),
1408 .AllocationPriority: 0,
1409 .GlobalPriority: false,
1410 .TSFlags: 0x00, /* TSFlags */
1411 .SpillStackID: 0, /* SpillStackID */
1412 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1413 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1414 offsetof(X86RegisterClassStorage, SuperClasses[9]) - 8 * sizeof(MCRegisterClass),
1415 .SuperClassesSize: 1
1416 },
1417 {
1418 offsetof(X86RegisterClassStorage, Regs[181]) - 9 * sizeof(MCRegisterClass),
1419 offsetof(X86RegisterClassStorage, BitSets[225]) - 9 * sizeof(MCRegisterClass),
1420 .NameIdx: 1493,
1421 .RegSizeInBits: 16,
1422 .RegsSize: 8,
1423 .RegSetBegin: 3, /* MinRegVal */
1424 .RegSetSize: 63, /* RegSetSize */
1425 .ID: X86::GR16_NOREXRegClassID,
1426 .CopyCost: 1, /* CopyCost */
1427 .Allocatable: true, /* Allocatable */
1428 .BaseClass: false,
1429 offsetof(X86RegisterClassStorage, SubClassMasks[95]) - 9 * sizeof(MCRegisterClass),
1430 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[5]) - 9 * sizeof(MCRegisterClass),
1431 .LaneMask: LaneBitmask(0x0000000000000003),
1432 .AllocationPriority: 0,
1433 .GlobalPriority: false,
1434 .TSFlags: 0x00, /* TSFlags */
1435 .SpillStackID: 0, /* SpillStackID */
1436 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1437 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1438 offsetof(X86RegisterClassStorage, SuperClasses[10]) - 9 * sizeof(MCRegisterClass),
1439 .SuperClassesSize: 2
1440 },
1441 {
1442 offsetof(X86RegisterClassStorage, Regs[189]) - 10 * sizeof(MCRegisterClass),
1443 offsetof(X86RegisterClassStorage, BitSets[233]) - 10 * sizeof(MCRegisterClass),
1444 .NameIdx: 6,
1445 .RegSizeInBits: 16,
1446 .RegsSize: 8,
1447 .RegSetBegin: 207, /* MinRegVal */
1448 .RegSetSize: 8, /* RegSetSize */
1449 .ID: X86::VK1RegClassID,
1450 .CopyCost: 1, /* CopyCost */
1451 .Allocatable: true, /* Allocatable */
1452 .BaseClass: false,
1453 offsetof(X86RegisterClassStorage, SubClassMasks[105]) - 10 * sizeof(MCRegisterClass),
1454 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 10 * sizeof(MCRegisterClass),
1455 .LaneMask: LaneBitmask(0x0000000000000001),
1456 .AllocationPriority: 0,
1457 .GlobalPriority: false,
1458 .TSFlags: 0x00, /* TSFlags */
1459 .SpillStackID: 0, /* SpillStackID */
1460 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1461 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1462 offsetof(X86RegisterClassStorage, SuperClasses[12]) - 10 * sizeof(MCRegisterClass),
1463 .SuperClassesSize: 4
1464 },
1465 {
1466 offsetof(X86RegisterClassStorage, Regs[197]) - 11 * sizeof(MCRegisterClass),
1467 offsetof(X86RegisterClassStorage, BitSets[234]) - 11 * sizeof(MCRegisterClass),
1468 .NameIdx: 330,
1469 .RegSizeInBits: 16,
1470 .RegsSize: 8,
1471 .RegSetBegin: 207, /* MinRegVal */
1472 .RegSetSize: 8, /* RegSetSize */
1473 .ID: X86::VK16RegClassID,
1474 .CopyCost: 1, /* CopyCost */
1475 .Allocatable: true, /* Allocatable */
1476 .BaseClass: false,
1477 offsetof(X86RegisterClassStorage, SubClassMasks[120]) - 11 * sizeof(MCRegisterClass),
1478 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 11 * sizeof(MCRegisterClass),
1479 .LaneMask: LaneBitmask(0x0000000000000001),
1480 .AllocationPriority: 0,
1481 .GlobalPriority: false,
1482 .TSFlags: 0x00, /* TSFlags */
1483 .SpillStackID: 0, /* SpillStackID */
1484 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1485 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1486 offsetof(X86RegisterClassStorage, SuperClasses[16]) - 11 * sizeof(MCRegisterClass),
1487 .SuperClassesSize: 4
1488 },
1489 {
1490 offsetof(X86RegisterClassStorage, Regs[205]) - 12 * sizeof(MCRegisterClass),
1491 offsetof(X86RegisterClassStorage, BitSets[235]) - 12 * sizeof(MCRegisterClass),
1492 .NameIdx: 37,
1493 .RegSizeInBits: 16,
1494 .RegsSize: 8,
1495 .RegSetBegin: 207, /* MinRegVal */
1496 .RegSetSize: 8, /* RegSetSize */
1497 .ID: X86::VK2RegClassID,
1498 .CopyCost: 1, /* CopyCost */
1499 .Allocatable: true, /* Allocatable */
1500 .BaseClass: false,
1501 offsetof(X86RegisterClassStorage, SubClassMasks[135]) - 12 * sizeof(MCRegisterClass),
1502 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 12 * sizeof(MCRegisterClass),
1503 .LaneMask: LaneBitmask(0x0000000000000001),
1504 .AllocationPriority: 0,
1505 .GlobalPriority: false,
1506 .TSFlags: 0x00, /* TSFlags */
1507 .SpillStackID: 0, /* SpillStackID */
1508 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1509 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1510 offsetof(X86RegisterClassStorage, SuperClasses[20]) - 12 * sizeof(MCRegisterClass),
1511 .SuperClassesSize: 4
1512 },
1513 {
1514 offsetof(X86RegisterClassStorage, Regs[213]) - 13 * sizeof(MCRegisterClass),
1515 offsetof(X86RegisterClassStorage, BitSets[236]) - 13 * sizeof(MCRegisterClass),
1516 .NameIdx: 309,
1517 .RegSizeInBits: 16,
1518 .RegsSize: 8,
1519 .RegSetBegin: 207, /* MinRegVal */
1520 .RegSetSize: 8, /* RegSetSize */
1521 .ID: X86::VK4RegClassID,
1522 .CopyCost: 1, /* CopyCost */
1523 .Allocatable: true, /* Allocatable */
1524 .BaseClass: false,
1525 offsetof(X86RegisterClassStorage, SubClassMasks[150]) - 13 * sizeof(MCRegisterClass),
1526 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 13 * sizeof(MCRegisterClass),
1527 .LaneMask: LaneBitmask(0x0000000000000001),
1528 .AllocationPriority: 0,
1529 .GlobalPriority: false,
1530 .TSFlags: 0x00, /* TSFlags */
1531 .SpillStackID: 0, /* SpillStackID */
1532 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1533 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1534 offsetof(X86RegisterClassStorage, SuperClasses[24]) - 13 * sizeof(MCRegisterClass),
1535 .SuperClassesSize: 4
1536 },
1537 {
1538 offsetof(X86RegisterClassStorage, Regs[221]) - 14 * sizeof(MCRegisterClass),
1539 offsetof(X86RegisterClassStorage, BitSets[237]) - 14 * sizeof(MCRegisterClass),
1540 .NameIdx: 370,
1541 .RegSizeInBits: 16,
1542 .RegsSize: 8,
1543 .RegSetBegin: 207, /* MinRegVal */
1544 .RegSetSize: 8, /* RegSetSize */
1545 .ID: X86::VK8RegClassID,
1546 .CopyCost: 1, /* CopyCost */
1547 .Allocatable: true, /* Allocatable */
1548 .BaseClass: false,
1549 offsetof(X86RegisterClassStorage, SubClassMasks[165]) - 14 * sizeof(MCRegisterClass),
1550 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 14 * sizeof(MCRegisterClass),
1551 .LaneMask: LaneBitmask(0x0000000000000001),
1552 .AllocationPriority: 0,
1553 .GlobalPriority: false,
1554 .TSFlags: 0x00, /* TSFlags */
1555 .SpillStackID: 0, /* SpillStackID */
1556 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1557 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1558 offsetof(X86RegisterClassStorage, SuperClasses[28]) - 14 * sizeof(MCRegisterClass),
1559 .SuperClassesSize: 4
1560 },
1561 {
1562 offsetof(X86RegisterClassStorage, Regs[229]) - 15 * sizeof(MCRegisterClass),
1563 offsetof(X86RegisterClassStorage, BitSets[238]) - 15 * sizeof(MCRegisterClass),
1564 .NameIdx: 1077,
1565 .RegSizeInBits: 16,
1566 .RegsSize: 7,
1567 .RegSetBegin: 208, /* MinRegVal */
1568 .RegSetSize: 7, /* RegSetSize */
1569 .ID: X86::VK16WMRegClassID,
1570 .CopyCost: 1, /* CopyCost */
1571 .Allocatable: true, /* Allocatable */
1572 .BaseClass: false,
1573 offsetof(X86RegisterClassStorage, SubClassMasks[180]) - 15 * sizeof(MCRegisterClass),
1574 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 15 * sizeof(MCRegisterClass),
1575 .LaneMask: LaneBitmask(0x0000000000000001),
1576 .AllocationPriority: 0,
1577 .GlobalPriority: false,
1578 .TSFlags: 0x00, /* TSFlags */
1579 .SpillStackID: 0, /* SpillStackID */
1580 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1581 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1582 offsetof(X86RegisterClassStorage, SuperClasses[32]) - 15 * sizeof(MCRegisterClass),
1583 .SuperClassesSize: 9
1584 },
1585 {
1586 offsetof(X86RegisterClassStorage, Regs[236]) - 16 * sizeof(MCRegisterClass),
1587 offsetof(X86RegisterClassStorage, BitSets[239]) - 16 * sizeof(MCRegisterClass),
1588 .NameIdx: 1045,
1589 .RegSizeInBits: 16,
1590 .RegsSize: 7,
1591 .RegSetBegin: 208, /* MinRegVal */
1592 .RegSetSize: 7, /* RegSetSize */
1593 .ID: X86::VK1WMRegClassID,
1594 .CopyCost: 1, /* CopyCost */
1595 .Allocatable: true, /* Allocatable */
1596 .BaseClass: false,
1597 offsetof(X86RegisterClassStorage, SubClassMasks[195]) - 16 * sizeof(MCRegisterClass),
1598 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 16 * sizeof(MCRegisterClass),
1599 .LaneMask: LaneBitmask(0x0000000000000001),
1600 .AllocationPriority: 0,
1601 .GlobalPriority: false,
1602 .TSFlags: 0x00, /* TSFlags */
1603 .SpillStackID: 0, /* SpillStackID */
1604 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1605 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1606 offsetof(X86RegisterClassStorage, SuperClasses[41]) - 16 * sizeof(MCRegisterClass),
1607 .SuperClassesSize: 9
1608 },
1609 {
1610 offsetof(X86RegisterClassStorage, Regs[243]) - 17 * sizeof(MCRegisterClass),
1611 offsetof(X86RegisterClassStorage, BitSets[240]) - 17 * sizeof(MCRegisterClass),
1612 .NameIdx: 1058,
1613 .RegSizeInBits: 16,
1614 .RegsSize: 7,
1615 .RegSetBegin: 208, /* MinRegVal */
1616 .RegSetSize: 7, /* RegSetSize */
1617 .ID: X86::VK2WMRegClassID,
1618 .CopyCost: 1, /* CopyCost */
1619 .Allocatable: true, /* Allocatable */
1620 .BaseClass: false,
1621 offsetof(X86RegisterClassStorage, SubClassMasks[210]) - 17 * sizeof(MCRegisterClass),
1622 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 17 * sizeof(MCRegisterClass),
1623 .LaneMask: LaneBitmask(0x0000000000000001),
1624 .AllocationPriority: 0,
1625 .GlobalPriority: false,
1626 .TSFlags: 0x00, /* TSFlags */
1627 .SpillStackID: 0, /* SpillStackID */
1628 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1629 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1630 offsetof(X86RegisterClassStorage, SuperClasses[50]) - 17 * sizeof(MCRegisterClass),
1631 .SuperClassesSize: 9
1632 },
1633 {
1634 offsetof(X86RegisterClassStorage, Regs[250]) - 18 * sizeof(MCRegisterClass),
1635 offsetof(X86RegisterClassStorage, BitSets[241]) - 18 * sizeof(MCRegisterClass),
1636 .NameIdx: 1071,
1637 .RegSizeInBits: 16,
1638 .RegsSize: 7,
1639 .RegSetBegin: 208, /* MinRegVal */
1640 .RegSetSize: 7, /* RegSetSize */
1641 .ID: X86::VK4WMRegClassID,
1642 .CopyCost: 1, /* CopyCost */
1643 .Allocatable: true, /* Allocatable */
1644 .BaseClass: false,
1645 offsetof(X86RegisterClassStorage, SubClassMasks[225]) - 18 * sizeof(MCRegisterClass),
1646 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 18 * sizeof(MCRegisterClass),
1647 .LaneMask: LaneBitmask(0x0000000000000001),
1648 .AllocationPriority: 0,
1649 .GlobalPriority: false,
1650 .TSFlags: 0x00, /* TSFlags */
1651 .SpillStackID: 0, /* SpillStackID */
1652 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1653 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1654 offsetof(X86RegisterClassStorage, SuperClasses[59]) - 18 * sizeof(MCRegisterClass),
1655 .SuperClassesSize: 9
1656 },
1657 {
1658 offsetof(X86RegisterClassStorage, Regs[257]) - 19 * sizeof(MCRegisterClass),
1659 offsetof(X86RegisterClassStorage, BitSets[242]) - 19 * sizeof(MCRegisterClass),
1660 .NameIdx: 1084,
1661 .RegSizeInBits: 16,
1662 .RegsSize: 7,
1663 .RegSetBegin: 208, /* MinRegVal */
1664 .RegSetSize: 7, /* RegSetSize */
1665 .ID: X86::VK8WMRegClassID,
1666 .CopyCost: 1, /* CopyCost */
1667 .Allocatable: true, /* Allocatable */
1668 .BaseClass: false,
1669 offsetof(X86RegisterClassStorage, SubClassMasks[240]) - 19 * sizeof(MCRegisterClass),
1670 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 19 * sizeof(MCRegisterClass),
1671 .LaneMask: LaneBitmask(0x0000000000000001),
1672 .AllocationPriority: 0,
1673 .GlobalPriority: false,
1674 .TSFlags: 0x00, /* TSFlags */
1675 .SpillStackID: 0, /* SpillStackID */
1676 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1677 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1678 offsetof(X86RegisterClassStorage, SuperClasses[68]) - 19 * sizeof(MCRegisterClass),
1679 .SuperClassesSize: 9
1680 },
1681 {
1682 offsetof(X86RegisterClassStorage, Regs[264]) - 20 * sizeof(MCRegisterClass),
1683 offsetof(X86RegisterClassStorage, BitSets[243]) - 20 * sizeof(MCRegisterClass),
1684 .NameIdx: 780,
1685 .RegSizeInBits: 16,
1686 .RegsSize: 6,
1687 .RegSetBegin: 12, /* MinRegVal */
1688 .RegSetSize: 57, /* RegSetSize */
1689 .ID: X86::SEGMENT_REGRegClassID,
1690 .CopyCost: 1, /* CopyCost */
1691 .Allocatable: true, /* Allocatable */
1692 .BaseClass: false,
1693 offsetof(X86RegisterClassStorage, SubClassMasks[255]) - 20 * sizeof(MCRegisterClass),
1694 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 20 * sizeof(MCRegisterClass),
1695 .LaneMask: LaneBitmask(0x0000000000000001),
1696 .AllocationPriority: 0,
1697 .GlobalPriority: false,
1698 .TSFlags: 0x00, /* TSFlags */
1699 .SpillStackID: 0, /* SpillStackID */
1700 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1701 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1702 offsetof(X86RegisterClassStorage, SuperClasses[77]) - 20 * sizeof(MCRegisterClass),
1703 .SuperClassesSize: 0
1704 },
1705 {
1706 offsetof(X86RegisterClassStorage, Regs[270]) - 21 * sizeof(MCRegisterClass),
1707 offsetof(X86RegisterClassStorage, BitSets[251]) - 21 * sizeof(MCRegisterClass),
1708 .NameIdx: 743,
1709 .RegSizeInBits: 16,
1710 .RegsSize: 4,
1711 .RegSetBegin: 3, /* MinRegVal */
1712 .RegSetSize: 19, /* RegSetSize */
1713 .ID: X86::GR16_ABCDRegClassID,
1714 .CopyCost: 1, /* CopyCost */
1715 .Allocatable: true, /* Allocatable */
1716 .BaseClass: false,
1717 offsetof(X86RegisterClassStorage, SubClassMasks[260]) - 21 * sizeof(MCRegisterClass),
1718 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[5]) - 21 * sizeof(MCRegisterClass),
1719 .LaneMask: LaneBitmask(0x0000000000000003),
1720 .AllocationPriority: 0,
1721 .GlobalPriority: false,
1722 .TSFlags: 0x00, /* TSFlags */
1723 .SpillStackID: 0, /* SpillStackID */
1724 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1725 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1726 offsetof(X86RegisterClassStorage, SuperClasses[77]) - 21 * sizeof(MCRegisterClass),
1727 .SuperClassesSize: 3
1728 },
1729 {
1730 offsetof(X86RegisterClassStorage, Regs[274]) - 22 * sizeof(MCRegisterClass),
1731 offsetof(X86RegisterClassStorage, BitSets[254]) - 22 * sizeof(MCRegisterClass),
1732 .NameIdx: 1326,
1733 .RegSizeInBits: 16,
1734 .RegsSize: 1,
1735 .RegSetBegin: 35, /* MinRegVal */
1736 .RegSetSize: 1, /* RegSetSize */
1737 .ID: X86::FPCCRRegClassID,
1738 .CopyCost: 255, /* CopyCost */
1739 .Allocatable: false, /* Allocatable */
1740 .BaseClass: false,
1741 offsetof(X86RegisterClassStorage, SubClassMasks[270]) - 22 * sizeof(MCRegisterClass),
1742 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 22 * sizeof(MCRegisterClass),
1743 .LaneMask: LaneBitmask(0x0000000000000001),
1744 .AllocationPriority: 0,
1745 .GlobalPriority: false,
1746 .TSFlags: 0x00, /* TSFlags */
1747 .SpillStackID: 0, /* SpillStackID */
1748 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1749 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1750 offsetof(X86RegisterClassStorage, SuperClasses[80]) - 22 * sizeof(MCRegisterClass),
1751 .SuperClassesSize: 0
1752 },
1753 {
1754 offsetof(X86RegisterClassStorage, Regs[275]) - 23 * sizeof(MCRegisterClass),
1755 offsetof(X86RegisterClassStorage, BitSets[255]) - 23 * sizeof(MCRegisterClass),
1756 .NameIdx: 1416,
1757 .RegSizeInBits: 32,
1758 .RegsSize: 32,
1759 .RegSetBegin: 135, /* MinRegVal */
1760 .RegSetSize: 96, /* RegSetSize */
1761 .ID: X86::FR16XRegClassID,
1762 .CopyCost: 1, /* CopyCost */
1763 .Allocatable: true, /* Allocatable */
1764 .BaseClass: false,
1765 offsetof(X86RegisterClassStorage, SubClassMasks[275]) - 23 * sizeof(MCRegisterClass),
1766 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 23 * sizeof(MCRegisterClass),
1767 .LaneMask: LaneBitmask(0x0000000000000001),
1768 .AllocationPriority: 0,
1769 .GlobalPriority: false,
1770 .TSFlags: 0x00, /* TSFlags */
1771 .SpillStackID: 0, /* SpillStackID */
1772 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1773 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1774 offsetof(X86RegisterClassStorage, SuperClasses[80]) - 23 * sizeof(MCRegisterClass),
1775 .SuperClassesSize: 0
1776 },
1777 {
1778 offsetof(X86RegisterClassStorage, Regs[307]) - 24 * sizeof(MCRegisterClass),
1779 offsetof(X86RegisterClassStorage, BitSets[267]) - 24 * sizeof(MCRegisterClass),
1780 .NameIdx: 335,
1781 .RegSizeInBits: 32,
1782 .RegsSize: 16,
1783 .RegSetBegin: 135, /* MinRegVal */
1784 .RegSetSize: 16, /* RegSetSize */
1785 .ID: X86::FR16RegClassID,
1786 .CopyCost: 1, /* CopyCost */
1787 .Allocatable: true, /* Allocatable */
1788 .BaseClass: false,
1789 offsetof(X86RegisterClassStorage, SubClassMasks[285]) - 24 * sizeof(MCRegisterClass),
1790 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 24 * sizeof(MCRegisterClass),
1791 .LaneMask: LaneBitmask(0x0000000000000001),
1792 .AllocationPriority: 0,
1793 .GlobalPriority: false,
1794 .TSFlags: 0x00, /* TSFlags */
1795 .SpillStackID: 0, /* SpillStackID */
1796 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1797 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1798 offsetof(X86RegisterClassStorage, SuperClasses[80]) - 24 * sizeof(MCRegisterClass),
1799 .SuperClassesSize: 1
1800 },
1801 {
1802 offsetof(X86RegisterClassStorage, Regs[323]) - 25 * sizeof(MCRegisterClass),
1803 offsetof(X86RegisterClassStorage, BitSets[269]) - 25 * sizeof(MCRegisterClass),
1804 .NameIdx: 1356,
1805 .RegSizeInBits: 32,
1806 .RegsSize: 4,
1807 .RegSetBegin: 279, /* MinRegVal */
1808 .RegSetSize: 4, /* RegSetSize */
1809 .ID: X86::VK16PAIRRegClassID,
1810 .CopyCost: 1, /* CopyCost */
1811 .Allocatable: true, /* Allocatable */
1812 .BaseClass: false,
1813 offsetof(X86RegisterClassStorage, SubClassMasks[295]) - 25 * sizeof(MCRegisterClass),
1814 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 25 * sizeof(MCRegisterClass),
1815 .LaneMask: LaneBitmask(0x0000000000000030),
1816 .AllocationPriority: 0,
1817 .GlobalPriority: false,
1818 .TSFlags: 0x00, /* TSFlags */
1819 .SpillStackID: 0, /* SpillStackID */
1820 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1821 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1822 offsetof(X86RegisterClassStorage, SuperClasses[81]) - 25 * sizeof(MCRegisterClass),
1823 .SuperClassesSize: 4
1824 },
1825 {
1826 offsetof(X86RegisterClassStorage, Regs[327]) - 26 * sizeof(MCRegisterClass),
1827 offsetof(X86RegisterClassStorage, BitSets[270]) - 26 * sizeof(MCRegisterClass),
1828 .NameIdx: 1332,
1829 .RegSizeInBits: 32,
1830 .RegsSize: 4,
1831 .RegSetBegin: 279, /* MinRegVal */
1832 .RegSetSize: 4, /* RegSetSize */
1833 .ID: X86::VK1PAIRRegClassID,
1834 .CopyCost: 1, /* CopyCost */
1835 .Allocatable: true, /* Allocatable */
1836 .BaseClass: false,
1837 offsetof(X86RegisterClassStorage, SubClassMasks[300]) - 26 * sizeof(MCRegisterClass),
1838 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 26 * sizeof(MCRegisterClass),
1839 .LaneMask: LaneBitmask(0x0000000000000030),
1840 .AllocationPriority: 0,
1841 .GlobalPriority: false,
1842 .TSFlags: 0x00, /* TSFlags */
1843 .SpillStackID: 0, /* SpillStackID */
1844 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1845 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1846 offsetof(X86RegisterClassStorage, SuperClasses[85]) - 26 * sizeof(MCRegisterClass),
1847 .SuperClassesSize: 4
1848 },
1849 {
1850 offsetof(X86RegisterClassStorage, Regs[331]) - 27 * sizeof(MCRegisterClass),
1851 offsetof(X86RegisterClassStorage, BitSets[271]) - 27 * sizeof(MCRegisterClass),
1852 .NameIdx: 1340,
1853 .RegSizeInBits: 32,
1854 .RegsSize: 4,
1855 .RegSetBegin: 279, /* MinRegVal */
1856 .RegSetSize: 4, /* RegSetSize */
1857 .ID: X86::VK2PAIRRegClassID,
1858 .CopyCost: 1, /* CopyCost */
1859 .Allocatable: true, /* Allocatable */
1860 .BaseClass: false,
1861 offsetof(X86RegisterClassStorage, SubClassMasks[305]) - 27 * sizeof(MCRegisterClass),
1862 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 27 * sizeof(MCRegisterClass),
1863 .LaneMask: LaneBitmask(0x0000000000000030),
1864 .AllocationPriority: 0,
1865 .GlobalPriority: false,
1866 .TSFlags: 0x00, /* TSFlags */
1867 .SpillStackID: 0, /* SpillStackID */
1868 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1869 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1870 offsetof(X86RegisterClassStorage, SuperClasses[89]) - 27 * sizeof(MCRegisterClass),
1871 .SuperClassesSize: 4
1872 },
1873 {
1874 offsetof(X86RegisterClassStorage, Regs[335]) - 28 * sizeof(MCRegisterClass),
1875 offsetof(X86RegisterClassStorage, BitSets[272]) - 28 * sizeof(MCRegisterClass),
1876 .NameIdx: 1348,
1877 .RegSizeInBits: 32,
1878 .RegsSize: 4,
1879 .RegSetBegin: 279, /* MinRegVal */
1880 .RegSetSize: 4, /* RegSetSize */
1881 .ID: X86::VK4PAIRRegClassID,
1882 .CopyCost: 1, /* CopyCost */
1883 .Allocatable: true, /* Allocatable */
1884 .BaseClass: false,
1885 offsetof(X86RegisterClassStorage, SubClassMasks[310]) - 28 * sizeof(MCRegisterClass),
1886 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 28 * sizeof(MCRegisterClass),
1887 .LaneMask: LaneBitmask(0x0000000000000030),
1888 .AllocationPriority: 0,
1889 .GlobalPriority: false,
1890 .TSFlags: 0x00, /* TSFlags */
1891 .SpillStackID: 0, /* SpillStackID */
1892 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1893 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1894 offsetof(X86RegisterClassStorage, SuperClasses[93]) - 28 * sizeof(MCRegisterClass),
1895 .SuperClassesSize: 4
1896 },
1897 {
1898 offsetof(X86RegisterClassStorage, Regs[339]) - 29 * sizeof(MCRegisterClass),
1899 offsetof(X86RegisterClassStorage, BitSets[273]) - 29 * sizeof(MCRegisterClass),
1900 .NameIdx: 1365,
1901 .RegSizeInBits: 32,
1902 .RegsSize: 4,
1903 .RegSetBegin: 279, /* MinRegVal */
1904 .RegSetSize: 4, /* RegSetSize */
1905 .ID: X86::VK8PAIRRegClassID,
1906 .CopyCost: 1, /* CopyCost */
1907 .Allocatable: true, /* Allocatable */
1908 .BaseClass: false,
1909 offsetof(X86RegisterClassStorage, SubClassMasks[315]) - 29 * sizeof(MCRegisterClass),
1910 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 29 * sizeof(MCRegisterClass),
1911 .LaneMask: LaneBitmask(0x0000000000000030),
1912 .AllocationPriority: 0,
1913 .GlobalPriority: false,
1914 .TSFlags: 0x00, /* TSFlags */
1915 .SpillStackID: 0, /* SpillStackID */
1916 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1917 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1918 offsetof(X86RegisterClassStorage, SuperClasses[97]) - 29 * sizeof(MCRegisterClass),
1919 .SuperClassesSize: 4
1920 },
1921 {
1922 offsetof(X86RegisterClassStorage, Regs[343]) - 30 * sizeof(MCRegisterClass),
1923 offsetof(X86RegisterClassStorage, BitSets[274]) - 30 * sizeof(MCRegisterClass),
1924 .NameIdx: 1018,
1925 .RegSizeInBits: 32,
1926 .RegsSize: 3,
1927 .RegSetBegin: 280, /* MinRegVal */
1928 .RegSetSize: 3, /* RegSetSize */
1929 .ID: X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID,
1930 .CopyCost: 1, /* CopyCost */
1931 .Allocatable: true, /* Allocatable */
1932 .BaseClass: false,
1933 offsetof(X86RegisterClassStorage, SubClassMasks[320]) - 30 * sizeof(MCRegisterClass),
1934 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 30 * sizeof(MCRegisterClass),
1935 .LaneMask: LaneBitmask(0x0000000000000030),
1936 .AllocationPriority: 0,
1937 .GlobalPriority: false,
1938 .TSFlags: 0x00, /* TSFlags */
1939 .SpillStackID: 0, /* SpillStackID */
1940 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1941 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1942 offsetof(X86RegisterClassStorage, SuperClasses[101]) - 30 * sizeof(MCRegisterClass),
1943 .SuperClassesSize: 5
1944 },
1945 {
1946 offsetof(X86RegisterClassStorage, Regs[346]) - 31 * sizeof(MCRegisterClass),
1947 offsetof(X86RegisterClassStorage, BitSets[275]) - 31 * sizeof(MCRegisterClass),
1948 .NameIdx: 1179,
1949 .RegSizeInBits: 32,
1950 .RegsSize: 34,
1951 .RegSetBegin: 22, /* MinRegVal */
1952 .RegSetSize: 334, /* RegSetSize */
1953 .ID: X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1954 .CopyCost: 1, /* CopyCost */
1955 .Allocatable: true, /* Allocatable */
1956 .BaseClass: false,
1957 offsetof(X86RegisterClassStorage, SubClassMasks[325]) - 31 * sizeof(MCRegisterClass),
1958 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 31 * sizeof(MCRegisterClass),
1959 .LaneMask: LaneBitmask(0x000000000000000F),
1960 .AllocationPriority: 0,
1961 .GlobalPriority: false,
1962 .TSFlags: 0x00, /* TSFlags */
1963 .SpillStackID: 0, /* SpillStackID */
1964 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1965 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1966 offsetof(X86RegisterClassStorage, SuperClasses[106]) - 31 * sizeof(MCRegisterClass),
1967 .SuperClassesSize: 0
1968 },
1969 {
1970 offsetof(X86RegisterClassStorage, Regs[380]) - 32 * sizeof(MCRegisterClass),
1971 offsetof(X86RegisterClassStorage, BitSets[317]) - 32 * sizeof(MCRegisterClass),
1972 .NameIdx: 1382,
1973 .RegSizeInBits: 32,
1974 .RegsSize: 33,
1975 .RegSetBegin: 22, /* MinRegVal */
1976 .RegSetSize: 334, /* RegSetSize */
1977 .ID: X86::LOW32_ADDR_ACCESSRegClassID,
1978 .CopyCost: 1, /* CopyCost */
1979 .Allocatable: true, /* Allocatable */
1980 .BaseClass: false,
1981 offsetof(X86RegisterClassStorage, SubClassMasks[335]) - 32 * sizeof(MCRegisterClass),
1982 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 32 * sizeof(MCRegisterClass),
1983 .LaneMask: LaneBitmask(0x000000000000000F),
1984 .AllocationPriority: 0,
1985 .GlobalPriority: false,
1986 .TSFlags: 0x00, /* TSFlags */
1987 .SpillStackID: 0, /* SpillStackID */
1988 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1989 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1990 offsetof(X86RegisterClassStorage, SuperClasses[106]) - 32 * sizeof(MCRegisterClass),
1991 .SuperClassesSize: 1
1992 },
1993 {
1994 offsetof(X86RegisterClassStorage, Regs[413]) - 33 * sizeof(MCRegisterClass),
1995 offsetof(X86RegisterClassStorage, BitSets[359]) - 33 * sizeof(MCRegisterClass),
1996 .NameIdx: 1873,
1997 .RegSizeInBits: 32,
1998 .RegsSize: 33,
1999 .RegSetBegin: 22, /* MinRegVal */
2000 .RegSetSize: 334, /* RegSetSize */
2001 .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
2002 .CopyCost: 1, /* CopyCost */
2003 .Allocatable: true, /* Allocatable */
2004 .BaseClass: false,
2005 offsetof(X86RegisterClassStorage, SubClassMasks[345]) - 33 * sizeof(MCRegisterClass),
2006 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 33 * sizeof(MCRegisterClass),
2007 .LaneMask: LaneBitmask(0x000000000000000F),
2008 .AllocationPriority: 0,
2009 .GlobalPriority: false,
2010 .TSFlags: 0x00, /* TSFlags */
2011 .SpillStackID: 0, /* SpillStackID */
2012 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2013 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2014 offsetof(X86RegisterClassStorage, SuperClasses[107]) - 33 * sizeof(MCRegisterClass),
2015 .SuperClassesSize: 1
2016 },
2017 {
2018 offsetof(X86RegisterClassStorage, Regs[446]) - 34 * sizeof(MCRegisterClass),
2019 offsetof(X86RegisterClassStorage, BitSets[401]) - 34 * sizeof(MCRegisterClass),
2020 .NameIdx: 1404,
2021 .RegSizeInBits: 32,
2022 .RegsSize: 32,
2023 .RegSetBegin: 135, /* MinRegVal */
2024 .RegSetSize: 96, /* RegSetSize */
2025 .ID: X86::FR32XRegClassID,
2026 .CopyCost: 1, /* CopyCost */
2027 .Allocatable: true, /* Allocatable */
2028 .BaseClass: false,
2029 offsetof(X86RegisterClassStorage, SubClassMasks[355]) - 34 * sizeof(MCRegisterClass),
2030 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 34 * sizeof(MCRegisterClass),
2031 .LaneMask: LaneBitmask(0x0000000000000001),
2032 .AllocationPriority: 0,
2033 .GlobalPriority: false,
2034 .TSFlags: 0x00, /* TSFlags */
2035 .SpillStackID: 0, /* SpillStackID */
2036 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2037 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2038 offsetof(X86RegisterClassStorage, SuperClasses[108]) - 34 * sizeof(MCRegisterClass),
2039 .SuperClassesSize: 1
2040 },
2041 {
2042 offsetof(X86RegisterClassStorage, Regs[478]) - 35 * sizeof(MCRegisterClass),
2043 offsetof(X86RegisterClassStorage, BitSets[413]) - 35 * sizeof(MCRegisterClass),
2044 .NameIdx: 32,
2045 .RegSizeInBits: 32,
2046 .RegsSize: 32,
2047 .RegSetBegin: 22, /* MinRegVal */
2048 .RegSetSize: 334, /* RegSetSize */
2049 .ID: X86::GR32RegClassID,
2050 .CopyCost: 1, /* CopyCost */
2051 .Allocatable: true, /* Allocatable */
2052 .BaseClass: false,
2053 offsetof(X86RegisterClassStorage, SubClassMasks[365]) - 35 * sizeof(MCRegisterClass),
2054 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 35 * sizeof(MCRegisterClass),
2055 .LaneMask: LaneBitmask(0x000000000000000F),
2056 .AllocationPriority: 0,
2057 .GlobalPriority: false,
2058 .TSFlags: 0x00, /* TSFlags */
2059 .SpillStackID: 0, /* SpillStackID */
2060 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2061 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2062 offsetof(X86RegisterClassStorage, SuperClasses[109]) - 35 * sizeof(MCRegisterClass),
2063 .SuperClassesSize: 3
2064 },
2065 {
2066 offsetof(X86RegisterClassStorage, Regs[510]) - 36 * sizeof(MCRegisterClass),
2067 offsetof(X86RegisterClassStorage, BitSets[455]) - 36 * sizeof(MCRegisterClass),
2068 .NameIdx: 1201,
2069 .RegSizeInBits: 32,
2070 .RegsSize: 31,
2071 .RegSetBegin: 22, /* MinRegVal */
2072 .RegSetSize: 334, /* RegSetSize */
2073 .ID: X86::GR32_NOSPRegClassID,
2074 .CopyCost: 1, /* CopyCost */
2075 .Allocatable: true, /* Allocatable */
2076 .BaseClass: false,
2077 offsetof(X86RegisterClassStorage, SubClassMasks[375]) - 36 * sizeof(MCRegisterClass),
2078 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 36 * sizeof(MCRegisterClass),
2079 .LaneMask: LaneBitmask(0x000000000000000F),
2080 .AllocationPriority: 0,
2081 .GlobalPriority: false,
2082 .TSFlags: 0x00, /* TSFlags */
2083 .SpillStackID: 0, /* SpillStackID */
2084 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2085 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2086 offsetof(X86RegisterClassStorage, SuperClasses[112]) - 36 * sizeof(MCRegisterClass),
2087 .SuperClassesSize: 4
2088 },
2089 {
2090 offsetof(X86RegisterClassStorage, Regs[541]) - 37 * sizeof(MCRegisterClass),
2091 offsetof(X86RegisterClassStorage, BitSets[497]) - 37 * sizeof(MCRegisterClass),
2092 .NameIdx: 100,
2093 .RegSizeInBits: 32,
2094 .RegsSize: 17,
2095 .RegSetBegin: 22, /* MinRegVal */
2096 .RegSetSize: 153, /* RegSetSize */
2097 .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
2098 .CopyCost: 1, /* CopyCost */
2099 .Allocatable: true, /* Allocatable */
2100 .BaseClass: false,
2101 offsetof(X86RegisterClassStorage, SubClassMasks[385]) - 37 * sizeof(MCRegisterClass),
2102 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 37 * sizeof(MCRegisterClass),
2103 .LaneMask: LaneBitmask(0x000000000000000F),
2104 .AllocationPriority: 0,
2105 .GlobalPriority: false,
2106 .TSFlags: 0x00, /* TSFlags */
2107 .SpillStackID: 0, /* SpillStackID */
2108 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2109 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2110 offsetof(X86RegisterClassStorage, SuperClasses[116]) - 37 * sizeof(MCRegisterClass),
2111 .SuperClassesSize: 2
2112 },
2113 {
2114 offsetof(X86RegisterClassStorage, Regs[558]) - 38 * sizeof(MCRegisterClass),
2115 offsetof(X86RegisterClassStorage, BitSets[517]) - 38 * sizeof(MCRegisterClass),
2116 .NameIdx: 758,
2117 .RegSizeInBits: 32,
2118 .RegsSize: 16,
2119 .RegSetBegin: 87, /* MinRegVal */
2120 .RegSetSize: 16, /* RegSetSize */
2121 .ID: X86::DEBUG_REGRegClassID,
2122 .CopyCost: 1, /* CopyCost */
2123 .Allocatable: true, /* Allocatable */
2124 .BaseClass: false,
2125 offsetof(X86RegisterClassStorage, SubClassMasks[395]) - 38 * sizeof(MCRegisterClass),
2126 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 38 * sizeof(MCRegisterClass),
2127 .LaneMask: LaneBitmask(0x0000000000000001),
2128 .AllocationPriority: 0,
2129 .GlobalPriority: false,
2130 .TSFlags: 0x00, /* TSFlags */
2131 .SpillStackID: 0, /* SpillStackID */
2132 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2133 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2134 offsetof(X86RegisterClassStorage, SuperClasses[118]) - 38 * sizeof(MCRegisterClass),
2135 .SuperClassesSize: 0
2136 },
2137 {
2138 offsetof(X86RegisterClassStorage, Regs[574]) - 39 * sizeof(MCRegisterClass),
2139 offsetof(X86RegisterClassStorage, BitSets[519]) - 39 * sizeof(MCRegisterClass),
2140 .NameIdx: 27,
2141 .RegSizeInBits: 32,
2142 .RegsSize: 16,
2143 .RegSetBegin: 135, /* MinRegVal */
2144 .RegSetSize: 16, /* RegSetSize */
2145 .ID: X86::FR32RegClassID,
2146 .CopyCost: 1, /* CopyCost */
2147 .Allocatable: true, /* Allocatable */
2148 .BaseClass: false,
2149 offsetof(X86RegisterClassStorage, SubClassMasks[400]) - 39 * sizeof(MCRegisterClass),
2150 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 39 * sizeof(MCRegisterClass),
2151 .LaneMask: LaneBitmask(0x0000000000000001),
2152 .AllocationPriority: 0,
2153 .GlobalPriority: false,
2154 .TSFlags: 0x00, /* TSFlags */
2155 .SpillStackID: 0, /* SpillStackID */
2156 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2157 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2158 offsetof(X86RegisterClassStorage, SuperClasses[118]) - 39 * sizeof(MCRegisterClass),
2159 .SuperClassesSize: 3
2160 },
2161 {
2162 offsetof(X86RegisterClassStorage, Regs[590]) - 40 * sizeof(MCRegisterClass),
2163 offsetof(X86RegisterClassStorage, BitSets[521]) - 40 * sizeof(MCRegisterClass),
2164 .NameIdx: 41,
2165 .RegSizeInBits: 32,
2166 .RegsSize: 16,
2167 .RegSetBegin: 22, /* MinRegVal */
2168 .RegSetSize: 153, /* RegSetSize */
2169 .ID: X86::GR32_NOREX2RegClassID,
2170 .CopyCost: 1, /* CopyCost */
2171 .Allocatable: true, /* Allocatable */
2172 .BaseClass: false,
2173 offsetof(X86RegisterClassStorage, SubClassMasks[410]) - 40 * sizeof(MCRegisterClass),
2174 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 40 * sizeof(MCRegisterClass),
2175 .LaneMask: LaneBitmask(0x000000000000000F),
2176 .AllocationPriority: 0,
2177 .GlobalPriority: false,
2178 .TSFlags: 0x00, /* TSFlags */
2179 .SpillStackID: 0, /* SpillStackID */
2180 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2181 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2182 offsetof(X86RegisterClassStorage, SuperClasses[121]) - 40 * sizeof(MCRegisterClass),
2183 .SuperClassesSize: 5
2184 },
2185 {
2186 offsetof(X86RegisterClassStorage, Regs[606]) - 41 * sizeof(MCRegisterClass),
2187 offsetof(X86RegisterClassStorage, BitSets[541]) - 41 * sizeof(MCRegisterClass),
2188 .NameIdx: 1211,
2189 .RegSizeInBits: 32,
2190 .RegsSize: 15,
2191 .RegSetBegin: 22, /* MinRegVal */
2192 .RegSetSize: 153, /* RegSetSize */
2193 .ID: X86::GR32_NOREX2_NOSPRegClassID,
2194 .CopyCost: 1, /* CopyCost */
2195 .Allocatable: true, /* Allocatable */
2196 .BaseClass: false,
2197 offsetof(X86RegisterClassStorage, SubClassMasks[420]) - 41 * sizeof(MCRegisterClass),
2198 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 41 * sizeof(MCRegisterClass),
2199 .LaneMask: LaneBitmask(0x000000000000000F),
2200 .AllocationPriority: 0,
2201 .GlobalPriority: false,
2202 .TSFlags: 0x00, /* TSFlags */
2203 .SpillStackID: 0, /* SpillStackID */
2204 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2205 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2206 offsetof(X86RegisterClassStorage, SuperClasses[126]) - 41 * sizeof(MCRegisterClass),
2207 .SuperClassesSize: 7
2208 },
2209 {
2210 offsetof(X86RegisterClassStorage, Regs[621]) - 42 * sizeof(MCRegisterClass),
2211 offsetof(X86RegisterClassStorage, BitSets[561]) - 42 * sizeof(MCRegisterClass),
2212 .NameIdx: 1504,
2213 .RegSizeInBits: 32,
2214 .RegsSize: 9,
2215 .RegSetBegin: 22, /* MinRegVal */
2216 .RegSetSize: 31, /* RegSetSize */
2217 .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
2218 .CopyCost: 1, /* CopyCost */
2219 .Allocatable: true, /* Allocatable */
2220 .BaseClass: false,
2221 offsetof(X86RegisterClassStorage, SubClassMasks[430]) - 42 * sizeof(MCRegisterClass),
2222 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 42 * sizeof(MCRegisterClass),
2223 .LaneMask: LaneBitmask(0x000000000000000F),
2224 .AllocationPriority: 0,
2225 .GlobalPriority: false,
2226 .TSFlags: 0x00, /* TSFlags */
2227 .SpillStackID: 0, /* SpillStackID */
2228 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2229 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2230 offsetof(X86RegisterClassStorage, SuperClasses[133]) - 42 * sizeof(MCRegisterClass),
2231 .SuperClassesSize: 3
2232 },
2233 {
2234 offsetof(X86RegisterClassStorage, Regs[630]) - 43 * sizeof(MCRegisterClass),
2235 offsetof(X86RegisterClassStorage, BitSets[565]) - 43 * sizeof(MCRegisterClass),
2236 .NameIdx: 1436,
2237 .RegSizeInBits: 32,
2238 .RegsSize: 8,
2239 .RegSetBegin: 22, /* MinRegVal */
2240 .RegSetSize: 12, /* RegSetSize */
2241 .ID: X86::GR32_NOREXRegClassID,
2242 .CopyCost: 1, /* CopyCost */
2243 .Allocatable: true, /* Allocatable */
2244 .BaseClass: false,
2245 offsetof(X86RegisterClassStorage, SubClassMasks[440]) - 43 * sizeof(MCRegisterClass),
2246 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 43 * sizeof(MCRegisterClass),
2247 .LaneMask: LaneBitmask(0x000000000000000F),
2248 .AllocationPriority: 0,
2249 .GlobalPriority: false,
2250 .TSFlags: 0x00, /* TSFlags */
2251 .SpillStackID: 0, /* SpillStackID */
2252 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2253 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2254 offsetof(X86RegisterClassStorage, SuperClasses[136]) - 43 * sizeof(MCRegisterClass),
2255 .SuperClassesSize: 7
2256 },
2257 {
2258 offsetof(X86RegisterClassStorage, Regs[638]) - 44 * sizeof(MCRegisterClass),
2259 offsetof(X86RegisterClassStorage, BitSets[567]) - 44 * sizeof(MCRegisterClass),
2260 .NameIdx: 16,
2261 .RegSizeInBits: 32,
2262 .RegsSize: 8,
2263 .RegSetBegin: 207, /* MinRegVal */
2264 .RegSetSize: 8, /* RegSetSize */
2265 .ID: X86::VK32RegClassID,
2266 .CopyCost: 1, /* CopyCost */
2267 .Allocatable: true, /* Allocatable */
2268 .BaseClass: false,
2269 offsetof(X86RegisterClassStorage, SubClassMasks[450]) - 44 * sizeof(MCRegisterClass),
2270 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 44 * sizeof(MCRegisterClass),
2271 .LaneMask: LaneBitmask(0x0000000000000001),
2272 .AllocationPriority: 0,
2273 .GlobalPriority: false,
2274 .TSFlags: 0x00, /* TSFlags */
2275 .SpillStackID: 0, /* SpillStackID */
2276 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2277 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2278 offsetof(X86RegisterClassStorage, SuperClasses[143]) - 44 * sizeof(MCRegisterClass),
2279 .SuperClassesSize: 5
2280 },
2281 {
2282 offsetof(X86RegisterClassStorage, Regs[646]) - 45 * sizeof(MCRegisterClass),
2283 offsetof(X86RegisterClassStorage, BitSets[568]) - 45 * sizeof(MCRegisterClass),
2284 .NameIdx: 1255,
2285 .RegSizeInBits: 32,
2286 .RegsSize: 7,
2287 .RegSetBegin: 22, /* MinRegVal */
2288 .RegSetSize: 11, /* RegSetSize */
2289 .ID: X86::GR32_NOREX_NOSPRegClassID,
2290 .CopyCost: 1, /* CopyCost */
2291 .Allocatable: true, /* Allocatable */
2292 .BaseClass: false,
2293 offsetof(X86RegisterClassStorage, SubClassMasks[465]) - 45 * sizeof(MCRegisterClass),
2294 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 45 * sizeof(MCRegisterClass),
2295 .LaneMask: LaneBitmask(0x000000000000000F),
2296 .AllocationPriority: 0,
2297 .GlobalPriority: false,
2298 .TSFlags: 0x00, /* TSFlags */
2299 .SpillStackID: 0, /* SpillStackID */
2300 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2301 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2302 offsetof(X86RegisterClassStorage, SuperClasses[148]) - 45 * sizeof(MCRegisterClass),
2303 .SuperClassesSize: 10
2304 },
2305 {
2306 offsetof(X86RegisterClassStorage, Regs[653]) - 46 * sizeof(MCRegisterClass),
2307 offsetof(X86RegisterClassStorage, BitSets[570]) - 46 * sizeof(MCRegisterClass),
2308 .NameIdx: 21,
2309 .RegSizeInBits: 32,
2310 .RegsSize: 7,
2311 .RegSetBegin: 103, /* MinRegVal */
2312 .RegSetSize: 7, /* RegSetSize */
2313 .ID: X86::RFP32RegClassID,
2314 .CopyCost: 1, /* CopyCost */
2315 .Allocatable: true, /* Allocatable */
2316 .BaseClass: false,
2317 offsetof(X86RegisterClassStorage, SubClassMasks[475]) - 46 * sizeof(MCRegisterClass),
2318 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 46 * sizeof(MCRegisterClass),
2319 .LaneMask: LaneBitmask(0x0000000000000001),
2320 .AllocationPriority: 0,
2321 .GlobalPriority: false,
2322 .TSFlags: 0x00, /* TSFlags */
2323 .SpillStackID: 0, /* SpillStackID */
2324 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2325 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2326 offsetof(X86RegisterClassStorage, SuperClasses[158]) - 46 * sizeof(MCRegisterClass),
2327 .SuperClassesSize: 0
2328 },
2329 {
2330 offsetof(X86RegisterClassStorage, Regs[660]) - 47 * sizeof(MCRegisterClass),
2331 offsetof(X86RegisterClassStorage, BitSets[571]) - 47 * sizeof(MCRegisterClass),
2332 .NameIdx: 1051,
2333 .RegSizeInBits: 32,
2334 .RegsSize: 7,
2335 .RegSetBegin: 208, /* MinRegVal */
2336 .RegSetSize: 7, /* RegSetSize */
2337 .ID: X86::VK32WMRegClassID,
2338 .CopyCost: 1, /* CopyCost */
2339 .Allocatable: true, /* Allocatable */
2340 .BaseClass: false,
2341 offsetof(X86RegisterClassStorage, SubClassMasks[480]) - 47 * sizeof(MCRegisterClass),
2342 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 47 * sizeof(MCRegisterClass),
2343 .LaneMask: LaneBitmask(0x0000000000000001),
2344 .AllocationPriority: 0,
2345 .GlobalPriority: false,
2346 .TSFlags: 0x00, /* TSFlags */
2347 .SpillStackID: 0, /* SpillStackID */
2348 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2349 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2350 offsetof(X86RegisterClassStorage, SuperClasses[158]) - 47 * sizeof(MCRegisterClass),
2351 .SuperClassesSize: 11
2352 },
2353 {
2354 offsetof(X86RegisterClassStorage, Regs[667]) - 48 * sizeof(MCRegisterClass),
2355 offsetof(X86RegisterClassStorage, BitSets[572]) - 48 * sizeof(MCRegisterClass),
2356 .NameIdx: 723,
2357 .RegSizeInBits: 32,
2358 .RegsSize: 4,
2359 .RegSetBegin: 22, /* MinRegVal */
2360 .RegSetSize: 6, /* RegSetSize */
2361 .ID: X86::GR32_ABCDRegClassID,
2362 .CopyCost: 1, /* CopyCost */
2363 .Allocatable: true, /* Allocatable */
2364 .BaseClass: false,
2365 offsetof(X86RegisterClassStorage, SubClassMasks[495]) - 48 * sizeof(MCRegisterClass),
2366 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 48 * sizeof(MCRegisterClass),
2367 .LaneMask: LaneBitmask(0x000000000000000F),
2368 .AllocationPriority: 0,
2369 .GlobalPriority: false,
2370 .TSFlags: 0x00, /* TSFlags */
2371 .SpillStackID: 0, /* SpillStackID */
2372 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2373 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2374 offsetof(X86RegisterClassStorage, SuperClasses[169]) - 48 * sizeof(MCRegisterClass),
2375 .SuperClassesSize: 11
2376 },
2377 {
2378 offsetof(X86RegisterClassStorage, Regs[671]) - 49 * sizeof(MCRegisterClass),
2379 offsetof(X86RegisterClassStorage, BitSets[573]) - 49 * sizeof(MCRegisterClass),
2380 .NameIdx: 508,
2381 .RegSizeInBits: 32,
2382 .RegsSize: 4,
2383 .RegSetBegin: 22, /* MinRegVal */
2384 .RegSetSize: 12, /* RegSetSize */
2385 .ID: X86::GR32_TCRegClassID,
2386 .CopyCost: 1, /* CopyCost */
2387 .Allocatable: true, /* Allocatable */
2388 .BaseClass: false,
2389 offsetof(X86RegisterClassStorage, SubClassMasks[505]) - 49 * sizeof(MCRegisterClass),
2390 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 49 * sizeof(MCRegisterClass),
2391 .LaneMask: LaneBitmask(0x000000000000000F),
2392 .AllocationPriority: 0,
2393 .GlobalPriority: false,
2394 .TSFlags: 0x00, /* TSFlags */
2395 .SpillStackID: 0, /* SpillStackID */
2396 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2397 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2398 offsetof(X86RegisterClassStorage, SuperClasses[180]) - 49 * sizeof(MCRegisterClass),
2399 .SuperClassesSize: 8
2400 },
2401 {
2402 offsetof(X86RegisterClassStorage, Regs[675]) - 50 * sizeof(MCRegisterClass),
2403 offsetof(X86RegisterClassStorage, BitSets[575]) - 50 * sizeof(MCRegisterClass),
2404 .NameIdx: 494,
2405 .RegSizeInBits: 32,
2406 .RegsSize: 3,
2407 .RegSetBegin: 22, /* MinRegVal */
2408 .RegSetSize: 6, /* RegSetSize */
2409 .ID: X86::GR32_ABCD_and_GR32_TCRegClassID,
2410 .CopyCost: 1, /* CopyCost */
2411 .Allocatable: true, /* Allocatable */
2412 .BaseClass: false,
2413 offsetof(X86RegisterClassStorage, SubClassMasks[515]) - 50 * sizeof(MCRegisterClass),
2414 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 50 * sizeof(MCRegisterClass),
2415 .LaneMask: LaneBitmask(0x000000000000000F),
2416 .AllocationPriority: 0,
2417 .GlobalPriority: false,
2418 .TSFlags: 0x00, /* TSFlags */
2419 .SpillStackID: 0, /* SpillStackID */
2420 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2421 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2422 offsetof(X86RegisterClassStorage, SuperClasses[188]) - 50 * sizeof(MCRegisterClass),
2423 .SuperClassesSize: 13
2424 },
2425 {
2426 offsetof(X86RegisterClassStorage, Regs[678]) - 51 * sizeof(MCRegisterClass),
2427 offsetof(X86RegisterClassStorage, BitSets[576]) - 51 * sizeof(MCRegisterClass),
2428 .NameIdx: 707,
2429 .RegSizeInBits: 32,
2430 .RegsSize: 2,
2431 .RegSetBegin: 22, /* MinRegVal */
2432 .RegSetSize: 6, /* RegSetSize */
2433 .ID: X86::GR32_ADRegClassID,
2434 .CopyCost: 1, /* CopyCost */
2435 .Allocatable: true, /* Allocatable */
2436 .BaseClass: false,
2437 offsetof(X86RegisterClassStorage, SubClassMasks[525]) - 51 * sizeof(MCRegisterClass),
2438 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 51 * sizeof(MCRegisterClass),
2439 .LaneMask: LaneBitmask(0x000000000000000F),
2440 .AllocationPriority: 0,
2441 .GlobalPriority: false,
2442 .TSFlags: 0x00, /* TSFlags */
2443 .SpillStackID: 0, /* SpillStackID */
2444 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2445 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2446 offsetof(X86RegisterClassStorage, SuperClasses[201]) - 51 * sizeof(MCRegisterClass),
2447 .SuperClassesSize: 14
2448 },
2449 {
2450 offsetof(X86RegisterClassStorage, Regs[680]) - 52 * sizeof(MCRegisterClass),
2451 offsetof(X86RegisterClassStorage, BitSets[577]) - 52 * sizeof(MCRegisterClass),
2452 .NameIdx: 1612,
2453 .RegSizeInBits: 32,
2454 .RegsSize: 2,
2455 .RegSetBegin: 25, /* MinRegVal */
2456 .RegSetSize: 3, /* RegSetSize */
2457 .ID: X86::GR32_ArgRefRegClassID,
2458 .CopyCost: 1, /* CopyCost */
2459 .Allocatable: true, /* Allocatable */
2460 .BaseClass: false,
2461 offsetof(X86RegisterClassStorage, SubClassMasks[535]) - 52 * sizeof(MCRegisterClass),
2462 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 52 * sizeof(MCRegisterClass),
2463 .LaneMask: LaneBitmask(0x000000000000000F),
2464 .AllocationPriority: 0,
2465 .GlobalPriority: false,
2466 .TSFlags: 0x00, /* TSFlags */
2467 .SpillStackID: 0, /* SpillStackID */
2468 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2469 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2470 offsetof(X86RegisterClassStorage, SuperClasses[215]) - 52 * sizeof(MCRegisterClass),
2471 .SuperClassesSize: 14
2472 },
2473 {
2474 offsetof(X86RegisterClassStorage, Regs[682]) - 53 * sizeof(MCRegisterClass),
2475 offsetof(X86RegisterClassStorage, BitSets[578]) - 53 * sizeof(MCRegisterClass),
2476 .NameIdx: 1310,
2477 .RegSizeInBits: 32,
2478 .RegsSize: 2,
2479 .RegSetBegin: 23, /* MinRegVal */
2480 .RegSetSize: 11, /* RegSetSize */
2481 .ID: X86::GR32_BPSPRegClassID,
2482 .CopyCost: 1, /* CopyCost */
2483 .Allocatable: true, /* Allocatable */
2484 .BaseClass: false,
2485 offsetof(X86RegisterClassStorage, SubClassMasks[545]) - 53 * sizeof(MCRegisterClass),
2486 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 53 * sizeof(MCRegisterClass),
2487 .LaneMask: LaneBitmask(0x000000000000000F),
2488 .AllocationPriority: 0,
2489 .GlobalPriority: false,
2490 .TSFlags: 0x00, /* TSFlags */
2491 .SpillStackID: 0, /* SpillStackID */
2492 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2493 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2494 offsetof(X86RegisterClassStorage, SuperClasses[229]) - 53 * sizeof(MCRegisterClass),
2495 .SuperClassesSize: 8
2496 },
2497 {
2498 offsetof(X86RegisterClassStorage, Regs[684]) - 54 * sizeof(MCRegisterClass),
2499 offsetof(X86RegisterClassStorage, BitSets[580]) - 54 * sizeof(MCRegisterClass),
2500 .NameIdx: 966,
2501 .RegSizeInBits: 32,
2502 .RegsSize: 2,
2503 .RegSetBegin: 24, /* MinRegVal */
2504 .RegSetSize: 9, /* RegSetSize */
2505 .ID: X86::GR32_BSIRegClassID,
2506 .CopyCost: 1, /* CopyCost */
2507 .Allocatable: true, /* Allocatable */
2508 .BaseClass: false,
2509 offsetof(X86RegisterClassStorage, SubClassMasks[555]) - 54 * sizeof(MCRegisterClass),
2510 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 54 * sizeof(MCRegisterClass),
2511 .LaneMask: LaneBitmask(0x000000000000000F),
2512 .AllocationPriority: 0,
2513 .GlobalPriority: false,
2514 .TSFlags: 0x00, /* TSFlags */
2515 .SpillStackID: 0, /* SpillStackID */
2516 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2517 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2518 offsetof(X86RegisterClassStorage, SuperClasses[237]) - 54 * sizeof(MCRegisterClass),
2519 .SuperClassesSize: 11
2520 },
2521 {
2522 offsetof(X86RegisterClassStorage, Regs[686]) - 55 * sizeof(MCRegisterClass),
2523 offsetof(X86RegisterClassStorage, BitSets[582]) - 55 * sizeof(MCRegisterClass),
2524 .NameIdx: 424,
2525 .RegSizeInBits: 32,
2526 .RegsSize: 2,
2527 .RegSetBegin: 24, /* MinRegVal */
2528 .RegSetSize: 2, /* RegSetSize */
2529 .ID: X86::GR32_CBRegClassID,
2530 .CopyCost: 1, /* CopyCost */
2531 .Allocatable: true, /* Allocatable */
2532 .BaseClass: false,
2533 offsetof(X86RegisterClassStorage, SubClassMasks[565]) - 55 * sizeof(MCRegisterClass),
2534 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 55 * sizeof(MCRegisterClass),
2535 .LaneMask: LaneBitmask(0x000000000000000F),
2536 .AllocationPriority: 0,
2537 .GlobalPriority: false,
2538 .TSFlags: 0x00, /* TSFlags */
2539 .SpillStackID: 0, /* SpillStackID */
2540 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2541 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2542 offsetof(X86RegisterClassStorage, SuperClasses[248]) - 55 * sizeof(MCRegisterClass),
2543 .SuperClassesSize: 12
2544 },
2545 {
2546 offsetof(X86RegisterClassStorage, Regs[688]) - 56 * sizeof(MCRegisterClass),
2547 offsetof(X86RegisterClassStorage, BitSets[583]) - 56 * sizeof(MCRegisterClass),
2548 .NameIdx: 463,
2549 .RegSizeInBits: 32,
2550 .RegsSize: 2,
2551 .RegSetBegin: 25, /* MinRegVal */
2552 .RegSetSize: 3, /* RegSetSize */
2553 .ID: X86::GR32_DCRegClassID,
2554 .CopyCost: 1, /* CopyCost */
2555 .Allocatable: true, /* Allocatable */
2556 .BaseClass: false,
2557 offsetof(X86RegisterClassStorage, SubClassMasks[575]) - 56 * sizeof(MCRegisterClass),
2558 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 56 * sizeof(MCRegisterClass),
2559 .LaneMask: LaneBitmask(0x000000000000000F),
2560 .AllocationPriority: 0,
2561 .GlobalPriority: false,
2562 .TSFlags: 0x00, /* TSFlags */
2563 .SpillStackID: 0, /* SpillStackID */
2564 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2565 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2566 offsetof(X86RegisterClassStorage, SuperClasses[260]) - 56 * sizeof(MCRegisterClass),
2567 .SuperClassesSize: 15
2568 },
2569 {
2570 offsetof(X86RegisterClassStorage, Regs[690]) - 57 * sizeof(MCRegisterClass),
2571 offsetof(X86RegisterClassStorage, BitSets[584]) - 57 * sizeof(MCRegisterClass),
2572 .NameIdx: 1127,
2573 .RegSizeInBits: 32,
2574 .RegsSize: 2,
2575 .RegSetBegin: 23, /* MinRegVal */
2576 .RegSetSize: 4, /* RegSetSize */
2577 .ID: X86::GR32_DIBPRegClassID,
2578 .CopyCost: 1, /* CopyCost */
2579 .Allocatable: true, /* Allocatable */
2580 .BaseClass: false,
2581 offsetof(X86RegisterClassStorage, SubClassMasks[585]) - 57 * sizeof(MCRegisterClass),
2582 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 57 * sizeof(MCRegisterClass),
2583 .LaneMask: LaneBitmask(0x000000000000000F),
2584 .AllocationPriority: 0,
2585 .GlobalPriority: false,
2586 .TSFlags: 0x00, /* TSFlags */
2587 .SpillStackID: 0, /* SpillStackID */
2588 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2589 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2590 offsetof(X86RegisterClassStorage, SuperClasses[275]) - 57 * sizeof(MCRegisterClass),
2591 .SuperClassesSize: 11
2592 },
2593 {
2594 offsetof(X86RegisterClassStorage, Regs[692]) - 58 * sizeof(MCRegisterClass),
2595 offsetof(X86RegisterClassStorage, BitSets[585]) - 58 * sizeof(MCRegisterClass),
2596 .NameIdx: 839,
2597 .RegSizeInBits: 32,
2598 .RegsSize: 2,
2599 .RegSetBegin: 26, /* MinRegVal */
2600 .RegSetSize: 7, /* RegSetSize */
2601 .ID: X86::GR32_SIDIRegClassID,
2602 .CopyCost: 1, /* CopyCost */
2603 .Allocatable: true, /* Allocatable */
2604 .BaseClass: false,
2605 offsetof(X86RegisterClassStorage, SubClassMasks[595]) - 58 * sizeof(MCRegisterClass),
2606 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 58 * sizeof(MCRegisterClass),
2607 .LaneMask: LaneBitmask(0x000000000000000F),
2608 .AllocationPriority: 0,
2609 .GlobalPriority: false,
2610 .TSFlags: 0x00, /* TSFlags */
2611 .SpillStackID: 0, /* SpillStackID */
2612 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2613 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2614 offsetof(X86RegisterClassStorage, SuperClasses[286]) - 58 * sizeof(MCRegisterClass),
2615 .SuperClassesSize: 11
2616 },
2617 {
2618 offsetof(X86RegisterClassStorage, Regs[694]) - 59 * sizeof(MCRegisterClass),
2619 offsetof(X86RegisterClassStorage, BitSets[586]) - 59 * sizeof(MCRegisterClass),
2620 .NameIdx: 1671,
2621 .RegSizeInBits: 32,
2622 .RegsSize: 2,
2623 .RegSetBegin: 52, /* MinRegVal */
2624 .RegSetSize: 7, /* RegSetSize */
2625 .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
2626 .CopyCost: 1, /* CopyCost */
2627 .Allocatable: true, /* Allocatable */
2628 .BaseClass: false,
2629 offsetof(X86RegisterClassStorage, SubClassMasks[605]) - 59 * sizeof(MCRegisterClass),
2630 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 59 * sizeof(MCRegisterClass),
2631 .LaneMask: LaneBitmask(0x000000000000000F),
2632 .AllocationPriority: 0,
2633 .GlobalPriority: false,
2634 .TSFlags: 0x00, /* TSFlags */
2635 .SpillStackID: 0, /* SpillStackID */
2636 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2637 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2638 offsetof(X86RegisterClassStorage, SuperClasses[297]) - 59 * sizeof(MCRegisterClass),
2639 .SuperClassesSize: 1
2640 },
2641 {
2642 offsetof(X86RegisterClassStorage, Regs[696]) - 60 * sizeof(MCRegisterClass),
2643 offsetof(X86RegisterClassStorage, BitSets[587]) - 60 * sizeof(MCRegisterClass),
2644 .NameIdx: 1322,
2645 .RegSizeInBits: 32,
2646 .RegsSize: 1,
2647 .RegSetBegin: 28, /* MinRegVal */
2648 .RegSetSize: 1, /* RegSetSize */
2649 .ID: X86::CCRRegClassID,
2650 .CopyCost: 255, /* CopyCost */
2651 .Allocatable: false, /* Allocatable */
2652 .BaseClass: false,
2653 offsetof(X86RegisterClassStorage, SubClassMasks[610]) - 60 * sizeof(MCRegisterClass),
2654 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 60 * sizeof(MCRegisterClass),
2655 .LaneMask: LaneBitmask(0x0000000000000001),
2656 .AllocationPriority: 0,
2657 .GlobalPriority: false,
2658 .TSFlags: 0x00, /* TSFlags */
2659 .SpillStackID: 0, /* SpillStackID */
2660 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2661 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2662 offsetof(X86RegisterClassStorage, SuperClasses[298]) - 60 * sizeof(MCRegisterClass),
2663 .SuperClassesSize: 0
2664 },
2665 {
2666 offsetof(X86RegisterClassStorage, Regs[697]) - 61 * sizeof(MCRegisterClass),
2667 offsetof(X86RegisterClassStorage, BitSets[588]) - 61 * sizeof(MCRegisterClass),
2668 .NameIdx: 1320,
2669 .RegSizeInBits: 32,
2670 .RegsSize: 1,
2671 .RegSetBegin: 14, /* MinRegVal */
2672 .RegSetSize: 1, /* RegSetSize */
2673 .ID: X86::DFCCRRegClassID,
2674 .CopyCost: 255, /* CopyCost */
2675 .Allocatable: false, /* Allocatable */
2676 .BaseClass: false,
2677 offsetof(X86RegisterClassStorage, SubClassMasks[615]) - 61 * sizeof(MCRegisterClass),
2678 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 61 * sizeof(MCRegisterClass),
2679 .LaneMask: LaneBitmask(0x0000000000000001),
2680 .AllocationPriority: 0,
2681 .GlobalPriority: false,
2682 .TSFlags: 0x00, /* TSFlags */
2683 .SpillStackID: 0, /* SpillStackID */
2684 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2685 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2686 offsetof(X86RegisterClassStorage, SuperClasses[298]) - 61 * sizeof(MCRegisterClass),
2687 .SuperClassesSize: 0
2688 },
2689 {
2690 offsetof(X86RegisterClassStorage, Regs[698]) - 62 * sizeof(MCRegisterClass),
2691 offsetof(X86RegisterClassStorage, BitSets[589]) - 62 * sizeof(MCRegisterClass),
2692 .NameIdx: 952,
2693 .RegSizeInBits: 32,
2694 .RegsSize: 1,
2695 .RegSetBegin: 24, /* MinRegVal */
2696 .RegSetSize: 1, /* RegSetSize */
2697 .ID: X86::GR32_ABCD_and_GR32_BSIRegClassID,
2698 .CopyCost: 1, /* CopyCost */
2699 .Allocatable: true, /* Allocatable */
2700 .BaseClass: false,
2701 offsetof(X86RegisterClassStorage, SubClassMasks[620]) - 62 * sizeof(MCRegisterClass),
2702 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 62 * sizeof(MCRegisterClass),
2703 .LaneMask: LaneBitmask(0x000000000000000F),
2704 .AllocationPriority: 0,
2705 .GlobalPriority: false,
2706 .TSFlags: 0x00, /* TSFlags */
2707 .SpillStackID: 0, /* SpillStackID */
2708 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2709 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2710 offsetof(X86RegisterClassStorage, SuperClasses[298]) - 62 * sizeof(MCRegisterClass),
2711 .SuperClassesSize: 14
2712 },
2713 {
2714 offsetof(X86RegisterClassStorage, Regs[699]) - 63 * sizeof(MCRegisterClass),
2715 offsetof(X86RegisterClassStorage, BitSets[590]) - 63 * sizeof(MCRegisterClass),
2716 .NameIdx: 1600,
2717 .RegSizeInBits: 32,
2718 .RegsSize: 1,
2719 .RegSetBegin: 27, /* MinRegVal */
2720 .RegSetSize: 1, /* RegSetSize */
2721 .ID: X86::GR32_AD_and_GR32_ArgRefRegClassID,
2722 .CopyCost: 1, /* CopyCost */
2723 .Allocatable: true, /* Allocatable */
2724 .BaseClass: false,
2725 offsetof(X86RegisterClassStorage, SubClassMasks[630]) - 63 * sizeof(MCRegisterClass),
2726 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 63 * sizeof(MCRegisterClass),
2727 .LaneMask: LaneBitmask(0x000000000000000F),
2728 .AllocationPriority: 0,
2729 .GlobalPriority: false,
2730 .TSFlags: 0x00, /* TSFlags */
2731 .SpillStackID: 0, /* SpillStackID */
2732 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2733 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2734 offsetof(X86RegisterClassStorage, SuperClasses[312]) - 63 * sizeof(MCRegisterClass),
2735 .SuperClassesSize: 17
2736 },
2737 {
2738 offsetof(X86RegisterClassStorage, Regs[700]) - 64 * sizeof(MCRegisterClass),
2739 offsetof(X86RegisterClassStorage, BitSets[591]) - 64 * sizeof(MCRegisterClass),
2740 .NameIdx: 408,
2741 .RegSizeInBits: 32,
2742 .RegsSize: 1,
2743 .RegSetBegin: 25, /* MinRegVal */
2744 .RegSetSize: 1, /* RegSetSize */
2745 .ID: X86::GR32_ArgRef_and_GR32_CBRegClassID,
2746 .CopyCost: 1, /* CopyCost */
2747 .Allocatable: true, /* Allocatable */
2748 .BaseClass: false,
2749 offsetof(X86RegisterClassStorage, SubClassMasks[640]) - 64 * sizeof(MCRegisterClass),
2750 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 64 * sizeof(MCRegisterClass),
2751 .LaneMask: LaneBitmask(0x000000000000000F),
2752 .AllocationPriority: 0,
2753 .GlobalPriority: false,
2754 .TSFlags: 0x00, /* TSFlags */
2755 .SpillStackID: 0, /* SpillStackID */
2756 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2757 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2758 offsetof(X86RegisterClassStorage, SuperClasses[329]) - 64 * sizeof(MCRegisterClass),
2759 .SuperClassesSize: 17
2760 },
2761 {
2762 offsetof(X86RegisterClassStorage, Regs[701]) - 65 * sizeof(MCRegisterClass),
2763 offsetof(X86RegisterClassStorage, BitSets[592]) - 65 * sizeof(MCRegisterClass),
2764 .NameIdx: 1113,
2765 .RegSizeInBits: 32,
2766 .RegsSize: 1,
2767 .RegSetBegin: 23, /* MinRegVal */
2768 .RegSetSize: 1, /* RegSetSize */
2769 .ID: X86::GR32_BPSP_and_GR32_DIBPRegClassID,
2770 .CopyCost: 1, /* CopyCost */
2771 .Allocatable: true, /* Allocatable */
2772 .BaseClass: false,
2773 offsetof(X86RegisterClassStorage, SubClassMasks[650]) - 65 * sizeof(MCRegisterClass),
2774 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 65 * sizeof(MCRegisterClass),
2775 .LaneMask: LaneBitmask(0x000000000000000F),
2776 .AllocationPriority: 0,
2777 .GlobalPriority: false,
2778 .TSFlags: 0x00, /* TSFlags */
2779 .SpillStackID: 0, /* SpillStackID */
2780 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2781 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2782 offsetof(X86RegisterClassStorage, SuperClasses[346]) - 65 * sizeof(MCRegisterClass),
2783 .SuperClassesSize: 13
2784 },
2785 {
2786 offsetof(X86RegisterClassStorage, Regs[702]) - 66 * sizeof(MCRegisterClass),
2787 offsetof(X86RegisterClassStorage, BitSets[593]) - 66 * sizeof(MCRegisterClass),
2788 .NameIdx: 539,
2789 .RegSizeInBits: 32,
2790 .RegsSize: 1,
2791 .RegSetBegin: 33, /* MinRegVal */
2792 .RegSetSize: 1, /* RegSetSize */
2793 .ID: X86::GR32_BPSP_and_GR32_TCRegClassID,
2794 .CopyCost: 1, /* CopyCost */
2795 .Allocatable: true, /* Allocatable */
2796 .BaseClass: false,
2797 offsetof(X86RegisterClassStorage, SubClassMasks[660]) - 66 * sizeof(MCRegisterClass),
2798 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 66 * sizeof(MCRegisterClass),
2799 .LaneMask: LaneBitmask(0x000000000000000F),
2800 .AllocationPriority: 0,
2801 .GlobalPriority: false,
2802 .TSFlags: 0x00, /* TSFlags */
2803 .SpillStackID: 0, /* SpillStackID */
2804 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2805 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2806 offsetof(X86RegisterClassStorage, SuperClasses[359]) - 66 * sizeof(MCRegisterClass),
2807 .SuperClassesSize: 10
2808 },
2809 {
2810 offsetof(X86RegisterClassStorage, Regs[703]) - 67 * sizeof(MCRegisterClass),
2811 offsetof(X86RegisterClassStorage, BitSets[594]) - 67 * sizeof(MCRegisterClass),
2812 .NameIdx: 826,
2813 .RegSizeInBits: 32,
2814 .RegsSize: 1,
2815 .RegSetBegin: 32, /* MinRegVal */
2816 .RegSetSize: 1, /* RegSetSize */
2817 .ID: X86::GR32_BSI_and_GR32_SIDIRegClassID,
2818 .CopyCost: 1, /* CopyCost */
2819 .Allocatable: true, /* Allocatable */
2820 .BaseClass: false,
2821 offsetof(X86RegisterClassStorage, SubClassMasks[670]) - 67 * sizeof(MCRegisterClass),
2822 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 67 * sizeof(MCRegisterClass),
2823 .LaneMask: LaneBitmask(0x000000000000000F),
2824 .AllocationPriority: 0,
2825 .GlobalPriority: false,
2826 .TSFlags: 0x00, /* TSFlags */
2827 .SpillStackID: 0, /* SpillStackID */
2828 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2829 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2830 offsetof(X86RegisterClassStorage, SuperClasses[369]) - 67 * sizeof(MCRegisterClass),
2831 .SuperClassesSize: 13
2832 },
2833 {
2834 offsetof(X86RegisterClassStorage, Regs[704]) - 68 * sizeof(MCRegisterClass),
2835 offsetof(X86RegisterClassStorage, BitSets[595]) - 68 * sizeof(MCRegisterClass),
2836 .NameIdx: 872,
2837 .RegSizeInBits: 32,
2838 .RegsSize: 1,
2839 .RegSetBegin: 26, /* MinRegVal */
2840 .RegSetSize: 1, /* RegSetSize */
2841 .ID: X86::GR32_DIBP_and_GR32_SIDIRegClassID,
2842 .CopyCost: 1, /* CopyCost */
2843 .Allocatable: true, /* Allocatable */
2844 .BaseClass: false,
2845 offsetof(X86RegisterClassStorage, SubClassMasks[680]) - 68 * sizeof(MCRegisterClass),
2846 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[7]) - 68 * sizeof(MCRegisterClass),
2847 .LaneMask: LaneBitmask(0x000000000000000F),
2848 .AllocationPriority: 0,
2849 .GlobalPriority: false,
2850 .TSFlags: 0x00, /* TSFlags */
2851 .SpillStackID: 0, /* SpillStackID */
2852 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2853 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2854 offsetof(X86RegisterClassStorage, SuperClasses[382]) - 68 * sizeof(MCRegisterClass),
2855 .SuperClassesSize: 13
2856 },
2857 {
2858 offsetof(X86RegisterClassStorage, Regs[705]) - 69 * sizeof(MCRegisterClass),
2859 offsetof(X86RegisterClassStorage, BitSets[596]) - 69 * sizeof(MCRegisterClass),
2860 .NameIdx: 1741,
2861 .RegSizeInBits: 32,
2862 .RegsSize: 1,
2863 .RegSetBegin: 52, /* MinRegVal */
2864 .RegSetSize: 1, /* RegSetSize */
2865 .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID,
2866 .CopyCost: 1, /* CopyCost */
2867 .Allocatable: true, /* Allocatable */
2868 .BaseClass: false,
2869 offsetof(X86RegisterClassStorage, SubClassMasks[690]) - 69 * sizeof(MCRegisterClass),
2870 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 69 * sizeof(MCRegisterClass),
2871 .LaneMask: LaneBitmask(0x000000000000000F),
2872 .AllocationPriority: 0,
2873 .GlobalPriority: false,
2874 .TSFlags: 0x00, /* TSFlags */
2875 .SpillStackID: 0, /* SpillStackID */
2876 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2877 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2878 offsetof(X86RegisterClassStorage, SuperClasses[395]) - 69 * sizeof(MCRegisterClass),
2879 .SuperClassesSize: 5
2880 },
2881 {
2882 offsetof(X86RegisterClassStorage, Regs[706]) - 70 * sizeof(MCRegisterClass),
2883 offsetof(X86RegisterClassStorage, BitSets[597]) - 70 * sizeof(MCRegisterClass),
2884 .NameIdx: 1708,
2885 .RegSizeInBits: 32,
2886 .RegsSize: 1,
2887 .RegSetBegin: 58, /* MinRegVal */
2888 .RegSetSize: 1, /* RegSetSize */
2889 .ID: X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID,
2890 .CopyCost: 1, /* CopyCost */
2891 .Allocatable: true, /* Allocatable */
2892 .BaseClass: false,
2893 offsetof(X86RegisterClassStorage, SubClassMasks[695]) - 70 * sizeof(MCRegisterClass),
2894 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 70 * sizeof(MCRegisterClass),
2895 .LaneMask: LaneBitmask(0x000000000000000F),
2896 .AllocationPriority: 0,
2897 .GlobalPriority: false,
2898 .TSFlags: 0x00, /* TSFlags */
2899 .SpillStackID: 0, /* SpillStackID */
2900 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2901 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2902 offsetof(X86RegisterClassStorage, SuperClasses[400]) - 70 * sizeof(MCRegisterClass),
2903 .SuperClassesSize: 3
2904 },
2905 {
2906 offsetof(X86RegisterClassStorage, Regs[707]) - 71 * sizeof(MCRegisterClass),
2907 offsetof(X86RegisterClassStorage, BitSets[598]) - 71 * sizeof(MCRegisterClass),
2908 .NameIdx: 168,
2909 .RegSizeInBits: 64,
2910 .RegsSize: 7,
2911 .RegSetBegin: 103, /* MinRegVal */
2912 .RegSetSize: 7, /* RegSetSize */
2913 .ID: X86::RFP64RegClassID,
2914 .CopyCost: 1, /* CopyCost */
2915 .Allocatable: true, /* Allocatable */
2916 .BaseClass: false,
2917 offsetof(X86RegisterClassStorage, SubClassMasks[700]) - 71 * sizeof(MCRegisterClass),
2918 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 71 * sizeof(MCRegisterClass),
2919 .LaneMask: LaneBitmask(0x0000000000000001),
2920 .AllocationPriority: 0,
2921 .GlobalPriority: false,
2922 .TSFlags: 0x00, /* TSFlags */
2923 .SpillStackID: 0, /* SpillStackID */
2924 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2925 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2926 offsetof(X86RegisterClassStorage, SuperClasses[403]) - 71 * sizeof(MCRegisterClass),
2927 .SuperClassesSize: 1
2928 },
2929 {
2930 offsetof(X86RegisterClassStorage, Regs[714]) - 72 * sizeof(MCRegisterClass),
2931 offsetof(X86RegisterClassStorage, BitSets[599]) - 72 * sizeof(MCRegisterClass),
2932 .NameIdx: 179,
2933 .RegSizeInBits: 64,
2934 .RegsSize: 33,
2935 .RegSetBegin: 51, /* MinRegVal */
2936 .RegSetSize: 257, /* RegSetSize */
2937 .ID: X86::GR64RegClassID,
2938 .CopyCost: 1, /* CopyCost */
2939 .Allocatable: true, /* Allocatable */
2940 .BaseClass: false,
2941 offsetof(X86RegisterClassStorage, SubClassMasks[705]) - 72 * sizeof(MCRegisterClass),
2942 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 72 * sizeof(MCRegisterClass),
2943 .LaneMask: LaneBitmask(0x000000000000000F),
2944 .AllocationPriority: 0,
2945 .GlobalPriority: false,
2946 .TSFlags: 0x00, /* TSFlags */
2947 .SpillStackID: 0, /* SpillStackID */
2948 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2949 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2950 offsetof(X86RegisterClassStorage, SuperClasses[404]) - 72 * sizeof(MCRegisterClass),
2951 .SuperClassesSize: 0
2952 },
2953 {
2954 offsetof(X86RegisterClassStorage, Regs[747]) - 73 * sizeof(MCRegisterClass),
2955 offsetof(X86RegisterClassStorage, BitSets[632]) - 73 * sizeof(MCRegisterClass),
2956 .NameIdx: 1410,
2957 .RegSizeInBits: 64,
2958 .RegsSize: 32,
2959 .RegSetBegin: 135, /* MinRegVal */
2960 .RegSetSize: 96, /* RegSetSize */
2961 .ID: X86::FR64XRegClassID,
2962 .CopyCost: 1, /* CopyCost */
2963 .Allocatable: true, /* Allocatable */
2964 .BaseClass: false,
2965 offsetof(X86RegisterClassStorage, SubClassMasks[710]) - 73 * sizeof(MCRegisterClass),
2966 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 73 * sizeof(MCRegisterClass),
2967 .LaneMask: LaneBitmask(0x0000000000000001),
2968 .AllocationPriority: 0,
2969 .GlobalPriority: false,
2970 .TSFlags: 0x00, /* TSFlags */
2971 .SpillStackID: 0, /* SpillStackID */
2972 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2973 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2974 offsetof(X86RegisterClassStorage, SuperClasses[404]) - 73 * sizeof(MCRegisterClass),
2975 .SuperClassesSize: 2
2976 },
2977 {
2978 offsetof(X86RegisterClassStorage, Regs[779]) - 74 * sizeof(MCRegisterClass),
2979 offsetof(X86RegisterClassStorage, BitSets[644]) - 74 * sizeof(MCRegisterClass),
2980 .NameIdx: 1792,
2981 .RegSizeInBits: 64,
2982 .RegsSize: 32,
2983 .RegSetBegin: 51, /* MinRegVal */
2984 .RegSetSize: 257, /* RegSetSize */
2985 .ID: X86::GR64_with_sub_8bitRegClassID,
2986 .CopyCost: 1, /* CopyCost */
2987 .Allocatable: true, /* Allocatable */
2988 .BaseClass: false,
2989 offsetof(X86RegisterClassStorage, SubClassMasks[720]) - 74 * sizeof(MCRegisterClass),
2990 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 74 * sizeof(MCRegisterClass),
2991 .LaneMask: LaneBitmask(0x000000000000000F),
2992 .AllocationPriority: 0,
2993 .GlobalPriority: false,
2994 .TSFlags: 0x00, /* TSFlags */
2995 .SpillStackID: 0, /* SpillStackID */
2996 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2997 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2998 offsetof(X86RegisterClassStorage, SuperClasses[406]) - 74 * sizeof(MCRegisterClass),
2999 .SuperClassesSize: 1
3000 },
3001 {
3002 offsetof(X86RegisterClassStorage, Regs[811]) - 75 * sizeof(MCRegisterClass),
3003 offsetof(X86RegisterClassStorage, BitSets[677]) - 75 * sizeof(MCRegisterClass),
3004 .NameIdx: 1245,
3005 .RegSizeInBits: 64,
3006 .RegsSize: 31,
3007 .RegSetBegin: 51, /* MinRegVal */
3008 .RegSetSize: 257, /* RegSetSize */
3009 .ID: X86::GR64_NOSPRegClassID,
3010 .CopyCost: 1, /* CopyCost */
3011 .Allocatable: true, /* Allocatable */
3012 .BaseClass: false,
3013 offsetof(X86RegisterClassStorage, SubClassMasks[725]) - 75 * sizeof(MCRegisterClass),
3014 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 75 * sizeof(MCRegisterClass),
3015 .LaneMask: LaneBitmask(0x000000000000000F),
3016 .AllocationPriority: 0,
3017 .GlobalPriority: false,
3018 .TSFlags: 0x00, /* TSFlags */
3019 .SpillStackID: 0, /* SpillStackID */
3020 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3021 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3022 offsetof(X86RegisterClassStorage, SuperClasses[407]) - 75 * sizeof(MCRegisterClass),
3023 .SuperClassesSize: 2
3024 },
3025 {
3026 offsetof(X86RegisterClassStorage, Regs[842]) - 76 * sizeof(MCRegisterClass),
3027 offsetof(X86RegisterClassStorage, BitSets[710]) - 76 * sizeof(MCRegisterClass),
3028 .NameIdx: 53,
3029 .RegSizeInBits: 64,
3030 .RegsSize: 17,
3031 .RegSetBegin: 51, /* MinRegVal */
3032 .RegSetSize: 76, /* RegSetSize */
3033 .ID: X86::GR64_NOREX2RegClassID,
3034 .CopyCost: 1, /* CopyCost */
3035 .Allocatable: true, /* Allocatable */
3036 .BaseClass: false,
3037 offsetof(X86RegisterClassStorage, SubClassMasks[730]) - 76 * sizeof(MCRegisterClass),
3038 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 76 * sizeof(MCRegisterClass),
3039 .LaneMask: LaneBitmask(0x000000000000000F),
3040 .AllocationPriority: 0,
3041 .GlobalPriority: false,
3042 .TSFlags: 0x00, /* TSFlags */
3043 .SpillStackID: 0, /* SpillStackID */
3044 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3045 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3046 offsetof(X86RegisterClassStorage, SuperClasses[409]) - 76 * sizeof(MCRegisterClass),
3047 .SuperClassesSize: 1
3048 },
3049 {
3050 offsetof(X86RegisterClassStorage, Regs[859]) - 77 * sizeof(MCRegisterClass),
3051 offsetof(X86RegisterClassStorage, BitSets[720]) - 77 * sizeof(MCRegisterClass),
3052 .NameIdx: 768,
3053 .RegSizeInBits: 64,
3054 .RegsSize: 16,
3055 .RegSetBegin: 71, /* MinRegVal */
3056 .RegSetSize: 16, /* RegSetSize */
3057 .ID: X86::CONTROL_REGRegClassID,
3058 .CopyCost: 1, /* CopyCost */
3059 .Allocatable: true, /* Allocatable */
3060 .BaseClass: false,
3061 offsetof(X86RegisterClassStorage, SubClassMasks[735]) - 77 * sizeof(MCRegisterClass),
3062 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 77 * sizeof(MCRegisterClass),
3063 .LaneMask: LaneBitmask(0x0000000000000001),
3064 .AllocationPriority: 0,
3065 .GlobalPriority: false,
3066 .TSFlags: 0x00, /* TSFlags */
3067 .SpillStackID: 0, /* SpillStackID */
3068 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3069 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3070 offsetof(X86RegisterClassStorage, SuperClasses[410]) - 77 * sizeof(MCRegisterClass),
3071 .SuperClassesSize: 0
3072 },
3073 {
3074 offsetof(X86RegisterClassStorage, Regs[875]) - 78 * sizeof(MCRegisterClass),
3075 offsetof(X86RegisterClassStorage, BitSets[722]) - 78 * sizeof(MCRegisterClass),
3076 .NameIdx: 174,
3077 .RegSizeInBits: 64,
3078 .RegsSize: 16,
3079 .RegSetBegin: 135, /* MinRegVal */
3080 .RegSetSize: 16, /* RegSetSize */
3081 .ID: X86::FR64RegClassID,
3082 .CopyCost: 1, /* CopyCost */
3083 .Allocatable: true, /* Allocatable */
3084 .BaseClass: false,
3085 offsetof(X86RegisterClassStorage, SubClassMasks[740]) - 78 * sizeof(MCRegisterClass),
3086 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 78 * sizeof(MCRegisterClass),
3087 .LaneMask: LaneBitmask(0x0000000000000001),
3088 .AllocationPriority: 0,
3089 .GlobalPriority: false,
3090 .TSFlags: 0x00, /* TSFlags */
3091 .SpillStackID: 0, /* SpillStackID */
3092 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3093 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3094 offsetof(X86RegisterClassStorage, SuperClasses[410]) - 78 * sizeof(MCRegisterClass),
3095 .SuperClassesSize: 5
3096 },
3097 {
3098 offsetof(X86RegisterClassStorage, Regs[891]) - 79 * sizeof(MCRegisterClass),
3099 offsetof(X86RegisterClassStorage, BitSets[724]) - 79 * sizeof(MCRegisterClass),
3100 .NameIdx: 65,
3101 .RegSizeInBits: 64,
3102 .RegsSize: 16,
3103 .RegSetBegin: 51, /* MinRegVal */
3104 .RegSetSize: 76, /* RegSetSize */
3105 .ID: X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
3106 .CopyCost: 1, /* CopyCost */
3107 .Allocatable: true, /* Allocatable */
3108 .BaseClass: false,
3109 offsetof(X86RegisterClassStorage, SubClassMasks[750]) - 79 * sizeof(MCRegisterClass),
3110 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 79 * sizeof(MCRegisterClass),
3111 .LaneMask: LaneBitmask(0x000000000000000F),
3112 .AllocationPriority: 0,
3113 .GlobalPriority: false,
3114 .TSFlags: 0x00, /* TSFlags */
3115 .SpillStackID: 0, /* SpillStackID */
3116 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3117 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3118 offsetof(X86RegisterClassStorage, SuperClasses[415]) - 79 * sizeof(MCRegisterClass),
3119 .SuperClassesSize: 3
3120 },
3121 {
3122 offsetof(X86RegisterClassStorage, Regs[907]) - 80 * sizeof(MCRegisterClass),
3123 offsetof(X86RegisterClassStorage, BitSets[734]) - 80 * sizeof(MCRegisterClass),
3124 .NameIdx: 1228,
3125 .RegSizeInBits: 64,
3126 .RegsSize: 15,
3127 .RegSetBegin: 51, /* MinRegVal */
3128 .RegSetSize: 76, /* RegSetSize */
3129 .ID: X86::GR64_NOREX2_NOSPRegClassID,
3130 .CopyCost: 1, /* CopyCost */
3131 .Allocatable: true, /* Allocatable */
3132 .BaseClass: false,
3133 offsetof(X86RegisterClassStorage, SubClassMasks[755]) - 80 * sizeof(MCRegisterClass),
3134 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 80 * sizeof(MCRegisterClass),
3135 .LaneMask: LaneBitmask(0x000000000000000F),
3136 .AllocationPriority: 0,
3137 .GlobalPriority: false,
3138 .TSFlags: 0x00, /* TSFlags */
3139 .SpillStackID: 0, /* SpillStackID */
3140 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3141 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3142 offsetof(X86RegisterClassStorage, SuperClasses[418]) - 80 * sizeof(MCRegisterClass),
3143 .SuperClassesSize: 5
3144 },
3145 {
3146 offsetof(X86RegisterClassStorage, Regs[922]) - 81 * sizeof(MCRegisterClass),
3147 offsetof(X86RegisterClassStorage, BitSets[744]) - 81 * sizeof(MCRegisterClass),
3148 .NameIdx: 1565,
3149 .RegSizeInBits: 64,
3150 .RegsSize: 13,
3151 .RegSetBegin: 51, /* MinRegVal */
3152 .RegSetSize: 76, /* RegSetSize */
3153 .ID: X86::GR64PLTSafeRegClassID,
3154 .CopyCost: 1, /* CopyCost */
3155 .Allocatable: true, /* Allocatable */
3156 .BaseClass: false,
3157 offsetof(X86RegisterClassStorage, SubClassMasks[760]) - 81 * sizeof(MCRegisterClass),
3158 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 81 * sizeof(MCRegisterClass),
3159 .LaneMask: LaneBitmask(0x000000000000000F),
3160 .AllocationPriority: 0,
3161 .GlobalPriority: false,
3162 .TSFlags: 0x00, /* TSFlags */
3163 .SpillStackID: 0, /* SpillStackID */
3164 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3165 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3166 offsetof(X86RegisterClassStorage, SuperClasses[423]) - 81 * sizeof(MCRegisterClass),
3167 .SuperClassesSize: 6
3168 },
3169 {
3170 offsetof(X86RegisterClassStorage, Regs[935]) - 82 * sizeof(MCRegisterClass),
3171 offsetof(X86RegisterClassStorage, BitSets[754]) - 82 * sizeof(MCRegisterClass),
3172 .NameIdx: 613,
3173 .RegSizeInBits: 64,
3174 .RegsSize: 10,
3175 .RegSetBegin: 51, /* MinRegVal */
3176 .RegSetSize: 72, /* RegSetSize */
3177 .ID: X86::GR64_TCRegClassID,
3178 .CopyCost: 1, /* CopyCost */
3179 .Allocatable: true, /* Allocatable */
3180 .BaseClass: false,
3181 offsetof(X86RegisterClassStorage, SubClassMasks[765]) - 82 * sizeof(MCRegisterClass),
3182 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 82 * sizeof(MCRegisterClass),
3183 .LaneMask: LaneBitmask(0x000000000000000F),
3184 .AllocationPriority: 0,
3185 .GlobalPriority: false,
3186 .TSFlags: 0x00, /* TSFlags */
3187 .SpillStackID: 0, /* SpillStackID */
3188 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3189 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3190 offsetof(X86RegisterClassStorage, SuperClasses[429]) - 82 * sizeof(MCRegisterClass),
3191 .SuperClassesSize: 2
3192 },
3193 {
3194 offsetof(X86RegisterClassStorage, Regs[945]) - 83 * sizeof(MCRegisterClass),
3195 offsetof(X86RegisterClassStorage, BitSets[763]) - 83 * sizeof(MCRegisterClass),
3196 .NameIdx: 1447,
3197 .RegSizeInBits: 64,
3198 .RegsSize: 9,
3199 .RegSetBegin: 51, /* MinRegVal */
3200 .RegSetSize: 11, /* RegSetSize */
3201 .ID: X86::GR64_NOREXRegClassID,
3202 .CopyCost: 1, /* CopyCost */
3203 .Allocatable: true, /* Allocatable */
3204 .BaseClass: false,
3205 offsetof(X86RegisterClassStorage, SubClassMasks[770]) - 83 * sizeof(MCRegisterClass),
3206 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 83 * sizeof(MCRegisterClass),
3207 .LaneMask: LaneBitmask(0x000000000000000F),
3208 .AllocationPriority: 0,
3209 .GlobalPriority: false,
3210 .TSFlags: 0x00, /* TSFlags */
3211 .SpillStackID: 0, /* SpillStackID */
3212 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3213 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3214 offsetof(X86RegisterClassStorage, SuperClasses[431]) - 83 * sizeof(MCRegisterClass),
3215 .SuperClassesSize: 2
3216 },
3217 {
3218 offsetof(X86RegisterClassStorage, Regs[954]) - 84 * sizeof(MCRegisterClass),
3219 offsetof(X86RegisterClassStorage, BitSets[765]) - 84 * sizeof(MCRegisterClass),
3220 .NameIdx: 201,
3221 .RegSizeInBits: 64,
3222 .RegsSize: 9,
3223 .RegSetBegin: 51, /* MinRegVal */
3224 .RegSetSize: 72, /* RegSetSize */
3225 .ID: X86::GR64_TCW64RegClassID,
3226 .CopyCost: 1, /* CopyCost */
3227 .Allocatable: true, /* Allocatable */
3228 .BaseClass: false,
3229 offsetof(X86RegisterClassStorage, SubClassMasks[775]) - 84 * sizeof(MCRegisterClass),
3230 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 84 * sizeof(MCRegisterClass),
3231 .LaneMask: LaneBitmask(0x000000000000000F),
3232 .AllocationPriority: 0,
3233 .GlobalPriority: false,
3234 .TSFlags: 0x00, /* TSFlags */
3235 .SpillStackID: 0, /* SpillStackID */
3236 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3237 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3238 offsetof(X86RegisterClassStorage, SuperClasses[433]) - 84 * sizeof(MCRegisterClass),
3239 .SuperClassesSize: 2
3240 },
3241 {
3242 offsetof(X86RegisterClassStorage, Regs[963]) - 85 * sizeof(MCRegisterClass),
3243 offsetof(X86RegisterClassStorage, BitSets[774]) - 85 * sizeof(MCRegisterClass),
3244 .NameIdx: 1851,
3245 .RegSizeInBits: 64,
3246 .RegsSize: 9,
3247 .RegSetBegin: 51, /* MinRegVal */
3248 .RegSetSize: 72, /* RegSetSize */
3249 .ID: X86::GR64_TC_with_sub_8bitRegClassID,
3250 .CopyCost: 1, /* CopyCost */
3251 .Allocatable: true, /* Allocatable */
3252 .BaseClass: false,
3253 offsetof(X86RegisterClassStorage, SubClassMasks[780]) - 85 * sizeof(MCRegisterClass),
3254 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 85 * sizeof(MCRegisterClass),
3255 .LaneMask: LaneBitmask(0x000000000000000F),
3256 .AllocationPriority: 0,
3257 .GlobalPriority: false,
3258 .TSFlags: 0x00, /* TSFlags */
3259 .SpillStackID: 0, /* SpillStackID */
3260 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3261 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3262 offsetof(X86RegisterClassStorage, SuperClasses[435]) - 85 * sizeof(MCRegisterClass),
3263 .SuperClassesSize: 5
3264 },
3265 {
3266 offsetof(X86RegisterClassStorage, Regs[972]) - 86 * sizeof(MCRegisterClass),
3267 offsetof(X86RegisterClassStorage, BitSets[783]) - 86 * sizeof(MCRegisterClass),
3268 .NameIdx: 592,
3269 .RegSizeInBits: 64,
3270 .RegsSize: 8,
3271 .RegSetBegin: 51, /* MinRegVal */
3272 .RegSetSize: 72, /* RegSetSize */
3273 .ID: X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
3274 .CopyCost: 1, /* CopyCost */
3275 .Allocatable: true, /* Allocatable */
3276 .BaseClass: false,
3277 offsetof(X86RegisterClassStorage, SubClassMasks[785]) - 86 * sizeof(MCRegisterClass),
3278 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 86 * sizeof(MCRegisterClass),
3279 .LaneMask: LaneBitmask(0x000000000000000F),
3280 .AllocationPriority: 0,
3281 .GlobalPriority: false,
3282 .TSFlags: 0x00, /* TSFlags */
3283 .SpillStackID: 0, /* SpillStackID */
3284 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3285 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3286 offsetof(X86RegisterClassStorage, SuperClasses[440]) - 86 * sizeof(MCRegisterClass),
3287 .SuperClassesSize: 8
3288 },
3289 {
3290 offsetof(X86RegisterClassStorage, Regs[980]) - 87 * sizeof(MCRegisterClass),
3291 offsetof(X86RegisterClassStorage, BitSets[792]) - 87 * sizeof(MCRegisterClass),
3292 .NameIdx: 1811,
3293 .RegSizeInBits: 64,
3294 .RegsSize: 8,
3295 .RegSetBegin: 51, /* MinRegVal */
3296 .RegSetSize: 72, /* RegSetSize */
3297 .ID: X86::GR64_TCW64_with_sub_8bitRegClassID,
3298 .CopyCost: 1, /* CopyCost */
3299 .Allocatable: true, /* Allocatable */
3300 .BaseClass: false,
3301 offsetof(X86RegisterClassStorage, SubClassMasks[790]) - 87 * sizeof(MCRegisterClass),
3302 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 87 * sizeof(MCRegisterClass),
3303 .LaneMask: LaneBitmask(0x000000000000000F),
3304 .AllocationPriority: 0,
3305 .GlobalPriority: false,
3306 .TSFlags: 0x00, /* TSFlags */
3307 .SpillStackID: 0, /* SpillStackID */
3308 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3309 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3310 offsetof(X86RegisterClassStorage, SuperClasses[448]) - 87 * sizeof(MCRegisterClass),
3311 .SuperClassesSize: 5
3312 },
3313 {
3314 offsetof(X86RegisterClassStorage, Regs[988]) - 88 * sizeof(MCRegisterClass),
3315 offsetof(X86RegisterClassStorage, BitSets[801]) - 88 * sizeof(MCRegisterClass),
3316 .NameIdx: 189,
3317 .RegSizeInBits: 64,
3318 .RegsSize: 8,
3319 .RegSetBegin: 51, /* MinRegVal */
3320 .RegSetSize: 72, /* RegSetSize */
3321 .ID: X86::GR64_TC_and_GR64_TCW64RegClassID,
3322 .CopyCost: 1, /* CopyCost */
3323 .Allocatable: true, /* Allocatable */
3324 .BaseClass: false,
3325 offsetof(X86RegisterClassStorage, SubClassMasks[795]) - 88 * sizeof(MCRegisterClass),
3326 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 88 * sizeof(MCRegisterClass),
3327 .LaneMask: LaneBitmask(0x000000000000000F),
3328 .AllocationPriority: 0,
3329 .GlobalPriority: false,
3330 .TSFlags: 0x00, /* TSFlags */
3331 .SpillStackID: 0, /* SpillStackID */
3332 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3333 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3334 offsetof(X86RegisterClassStorage, SuperClasses[453]) - 88 * sizeof(MCRegisterClass),
3335 .SuperClassesSize: 4
3336 },
3337 {
3338 offsetof(X86RegisterClassStorage, Regs[996]) - 89 * sizeof(MCRegisterClass),
3339 offsetof(X86RegisterClassStorage, BitSets[810]) - 89 * sizeof(MCRegisterClass),
3340 .NameIdx: 1470,
3341 .RegSizeInBits: 64,
3342 .RegsSize: 8,
3343 .RegSetBegin: 51, /* MinRegVal */
3344 .RegSetSize: 11, /* RegSetSize */
3345 .ID: X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
3346 .CopyCost: 1, /* CopyCost */
3347 .Allocatable: true, /* Allocatable */
3348 .BaseClass: false,
3349 offsetof(X86RegisterClassStorage, SubClassMasks[800]) - 89 * sizeof(MCRegisterClass),
3350 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 89 * sizeof(MCRegisterClass),
3351 .LaneMask: LaneBitmask(0x000000000000000F),
3352 .AllocationPriority: 0,
3353 .GlobalPriority: false,
3354 .TSFlags: 0x00, /* TSFlags */
3355 .SpillStackID: 0, /* SpillStackID */
3356 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3357 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3358 offsetof(X86RegisterClassStorage, SuperClasses[457]) - 89 * sizeof(MCRegisterClass),
3359 .SuperClassesSize: 5
3360 },
3361 {
3362 offsetof(X86RegisterClassStorage, Regs[1004]) - 90 * sizeof(MCRegisterClass),
3363 offsetof(X86RegisterClassStorage, BitSets[812]) - 90 * sizeof(MCRegisterClass),
3364 .NameIdx: 163,
3365 .RegSizeInBits: 64,
3366 .RegsSize: 8,
3367 .RegSetBegin: 207, /* MinRegVal */
3368 .RegSetSize: 8, /* RegSetSize */
3369 .ID: X86::VK64RegClassID,
3370 .CopyCost: 1, /* CopyCost */
3371 .Allocatable: true, /* Allocatable */
3372 .BaseClass: false,
3373 offsetof(X86RegisterClassStorage, SubClassMasks[805]) - 90 * sizeof(MCRegisterClass),
3374 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 90 * sizeof(MCRegisterClass),
3375 .LaneMask: LaneBitmask(0x0000000000000001),
3376 .AllocationPriority: 0,
3377 .GlobalPriority: false,
3378 .TSFlags: 0x00, /* TSFlags */
3379 .SpillStackID: 0, /* SpillStackID */
3380 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3381 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3382 offsetof(X86RegisterClassStorage, SuperClasses[462]) - 90 * sizeof(MCRegisterClass),
3383 .SuperClassesSize: 6
3384 },
3385 {
3386 offsetof(X86RegisterClassStorage, Regs[1012]) - 91 * sizeof(MCRegisterClass),
3387 offsetof(X86RegisterClassStorage, BitSets[813]) - 91 * sizeof(MCRegisterClass),
3388 .NameIdx: 184,
3389 .RegSizeInBits: 64,
3390 .RegsSize: 8,
3391 .RegSetBegin: 111, /* MinRegVal */
3392 .RegSetSize: 8, /* RegSetSize */
3393 .ID: X86::VR64RegClassID,
3394 .CopyCost: 1, /* CopyCost */
3395 .Allocatable: true, /* Allocatable */
3396 .BaseClass: false,
3397 offsetof(X86RegisterClassStorage, SubClassMasks[820]) - 91 * sizeof(MCRegisterClass),
3398 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 91 * sizeof(MCRegisterClass),
3399 .LaneMask: LaneBitmask(0x0000000000000001),
3400 .AllocationPriority: 0,
3401 .GlobalPriority: false,
3402 .TSFlags: 0x00, /* TSFlags */
3403 .SpillStackID: 0, /* SpillStackID */
3404 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3405 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3406 offsetof(X86RegisterClassStorage, SuperClasses[468]) - 91 * sizeof(MCRegisterClass),
3407 .SuperClassesSize: 0
3408 },
3409 {
3410 offsetof(X86RegisterClassStorage, Regs[1020]) - 92 * sizeof(MCRegisterClass),
3411 offsetof(X86RegisterClassStorage, BitSets[814]) - 92 * sizeof(MCRegisterClass),
3412 .NameIdx: 659,
3413 .RegSizeInBits: 64,
3414 .RegsSize: 7,
3415 .RegSetBegin: 51, /* MinRegVal */
3416 .RegSetSize: 70, /* RegSetSize */
3417 .ID: X86::GR64PLTSafe_and_GR64_TCRegClassID,
3418 .CopyCost: 1, /* CopyCost */
3419 .Allocatable: true, /* Allocatable */
3420 .BaseClass: false,
3421 offsetof(X86RegisterClassStorage, SubClassMasks[825]) - 92 * sizeof(MCRegisterClass),
3422 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 92 * sizeof(MCRegisterClass),
3423 .LaneMask: LaneBitmask(0x000000000000000F),
3424 .AllocationPriority: 0,
3425 .GlobalPriority: false,
3426 .TSFlags: 0x00, /* TSFlags */
3427 .SpillStackID: 0, /* SpillStackID */
3428 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3429 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3430 offsetof(X86RegisterClassStorage, SuperClasses[468]) - 92 * sizeof(MCRegisterClass),
3431 .SuperClassesSize: 10
3432 },
3433 {
3434 offsetof(X86RegisterClassStorage, Regs[1027]) - 93 * sizeof(MCRegisterClass),
3435 offsetof(X86RegisterClassStorage, BitSets[823]) - 93 * sizeof(MCRegisterClass),
3436 .NameIdx: 224,
3437 .RegSizeInBits: 64,
3438 .RegsSize: 7,
3439 .RegSetBegin: 51, /* MinRegVal */
3440 .RegSetSize: 72, /* RegSetSize */
3441 .ID: X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
3442 .CopyCost: 1, /* CopyCost */
3443 .Allocatable: true, /* Allocatable */
3444 .BaseClass: false,
3445 offsetof(X86RegisterClassStorage, SubClassMasks[830]) - 93 * sizeof(MCRegisterClass),
3446 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 93 * sizeof(MCRegisterClass),
3447 .LaneMask: LaneBitmask(0x000000000000000F),
3448 .AllocationPriority: 0,
3449 .GlobalPriority: false,
3450 .TSFlags: 0x00, /* TSFlags */
3451 .SpillStackID: 0, /* SpillStackID */
3452 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3453 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3454 offsetof(X86RegisterClassStorage, SuperClasses[478]) - 93 * sizeof(MCRegisterClass),
3455 .SuperClassesSize: 8
3456 },
3457 {
3458 offsetof(X86RegisterClassStorage, Regs[1034]) - 94 * sizeof(MCRegisterClass),
3459 offsetof(X86RegisterClassStorage, BitSets[832]) - 94 * sizeof(MCRegisterClass),
3460 .NameIdx: 1271,
3461 .RegSizeInBits: 64,
3462 .RegsSize: 7,
3463 .RegSetBegin: 51, /* MinRegVal */
3464 .RegSetSize: 10, /* RegSetSize */
3465 .ID: X86::GR64_NOREX_NOSPRegClassID,
3466 .CopyCost: 1, /* CopyCost */
3467 .Allocatable: true, /* Allocatable */
3468 .BaseClass: false,
3469 offsetof(X86RegisterClassStorage, SubClassMasks[835]) - 94 * sizeof(MCRegisterClass),
3470 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 94 * sizeof(MCRegisterClass),
3471 .LaneMask: LaneBitmask(0x000000000000000F),
3472 .AllocationPriority: 0,
3473 .GlobalPriority: false,
3474 .TSFlags: 0x00, /* TSFlags */
3475 .SpillStackID: 0, /* SpillStackID */
3476 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3477 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3478 offsetof(X86RegisterClassStorage, SuperClasses[486]) - 94 * sizeof(MCRegisterClass),
3479 .SuperClassesSize: 9
3480 },
3481 {
3482 offsetof(X86RegisterClassStorage, Regs[1041]) - 95 * sizeof(MCRegisterClass),
3483 offsetof(X86RegisterClassStorage, BitSets[834]) - 95 * sizeof(MCRegisterClass),
3484 .NameIdx: 621,
3485 .RegSizeInBits: 64,
3486 .RegsSize: 7,
3487 .RegSetBegin: 51, /* MinRegVal */
3488 .RegSetSize: 11, /* RegSetSize */
3489 .ID: X86::GR64_NOREX_and_GR64_TCRegClassID,
3490 .CopyCost: 1, /* CopyCost */
3491 .Allocatable: true, /* Allocatable */
3492 .BaseClass: false,
3493 offsetof(X86RegisterClassStorage, SubClassMasks[840]) - 95 * sizeof(MCRegisterClass),
3494 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 95 * sizeof(MCRegisterClass),
3495 .LaneMask: LaneBitmask(0x000000000000000F),
3496 .AllocationPriority: 0,
3497 .GlobalPriority: false,
3498 .TSFlags: 0x00, /* TSFlags */
3499 .SpillStackID: 0, /* SpillStackID */
3500 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3501 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3502 offsetof(X86RegisterClassStorage, SuperClasses[495]) - 95 * sizeof(MCRegisterClass),
3503 .SuperClassesSize: 4
3504 },
3505 {
3506 offsetof(X86RegisterClassStorage, Regs[1048]) - 96 * sizeof(MCRegisterClass),
3507 offsetof(X86RegisterClassStorage, BitSets[836]) - 96 * sizeof(MCRegisterClass),
3508 .NameIdx: 1836,
3509 .RegSizeInBits: 64,
3510 .RegsSize: 7,
3511 .RegSetBegin: 51, /* MinRegVal */
3512 .RegSetSize: 72, /* RegSetSize */
3513 .ID: X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
3514 .CopyCost: 1, /* CopyCost */
3515 .Allocatable: true, /* Allocatable */
3516 .BaseClass: false,
3517 offsetof(X86RegisterClassStorage, SubClassMasks[845]) - 96 * sizeof(MCRegisterClass),
3518 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 96 * sizeof(MCRegisterClass),
3519 .LaneMask: LaneBitmask(0x000000000000000F),
3520 .AllocationPriority: 0,
3521 .GlobalPriority: false,
3522 .TSFlags: 0x00, /* TSFlags */
3523 .SpillStackID: 0, /* SpillStackID */
3524 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3525 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3526 offsetof(X86RegisterClassStorage, SuperClasses[499]) - 96 * sizeof(MCRegisterClass),
3527 .SuperClassesSize: 9
3528 },
3529 {
3530 offsetof(X86RegisterClassStorage, Regs[1055]) - 97 * sizeof(MCRegisterClass),
3531 offsetof(X86RegisterClassStorage, BitSets[845]) - 97 * sizeof(MCRegisterClass),
3532 .NameIdx: 1064,
3533 .RegSizeInBits: 64,
3534 .RegsSize: 7,
3535 .RegSetBegin: 208, /* MinRegVal */
3536 .RegSetSize: 7, /* RegSetSize */
3537 .ID: X86::VK64WMRegClassID,
3538 .CopyCost: 1, /* CopyCost */
3539 .Allocatable: true, /* Allocatable */
3540 .BaseClass: false,
3541 offsetof(X86RegisterClassStorage, SubClassMasks[850]) - 97 * sizeof(MCRegisterClass),
3542 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[9]) - 97 * sizeof(MCRegisterClass),
3543 .LaneMask: LaneBitmask(0x0000000000000001),
3544 .AllocationPriority: 0,
3545 .GlobalPriority: false,
3546 .TSFlags: 0x00, /* TSFlags */
3547 .SpillStackID: 0, /* SpillStackID */
3548 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3549 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3550 offsetof(X86RegisterClassStorage, SuperClasses[508]) - 97 * sizeof(MCRegisterClass),
3551 .SuperClassesSize: 13
3552 },
3553 {
3554 offsetof(X86RegisterClassStorage, Regs[1062]) - 98 * sizeof(MCRegisterClass),
3555 offsetof(X86RegisterClassStorage, BitSets[846]) - 98 * sizeof(MCRegisterClass),
3556 .NameIdx: 212,
3557 .RegSizeInBits: 64,
3558 .RegsSize: 6,
3559 .RegSetBegin: 51, /* MinRegVal */
3560 .RegSetSize: 72, /* RegSetSize */
3561 .ID: X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
3562 .CopyCost: 1, /* CopyCost */
3563 .Allocatable: true, /* Allocatable */
3564 .BaseClass: false,
3565 offsetof(X86RegisterClassStorage, SubClassMasks[865]) - 98 * sizeof(MCRegisterClass),
3566 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 98 * sizeof(MCRegisterClass),
3567 .LaneMask: LaneBitmask(0x000000000000000F),
3568 .AllocationPriority: 0,
3569 .GlobalPriority: false,
3570 .TSFlags: 0x00, /* TSFlags */
3571 .SpillStackID: 0, /* SpillStackID */
3572 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3573 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3574 offsetof(X86RegisterClassStorage, SuperClasses[521]) - 98 * sizeof(MCRegisterClass),
3575 .SuperClassesSize: 14
3576 },
3577 {
3578 offsetof(X86RegisterClassStorage, Regs[1068]) - 99 * sizeof(MCRegisterClass),
3579 offsetof(X86RegisterClassStorage, BitSets[855]) - 99 * sizeof(MCRegisterClass),
3580 .NameIdx: 1458,
3581 .RegSizeInBits: 64,
3582 .RegsSize: 6,
3583 .RegSetBegin: 51, /* MinRegVal */
3584 .RegSetSize: 11, /* RegSetSize */
3585 .ID: X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
3586 .CopyCost: 1, /* CopyCost */
3587 .Allocatable: true, /* Allocatable */
3588 .BaseClass: false,
3589 offsetof(X86RegisterClassStorage, SubClassMasks[870]) - 99 * sizeof(MCRegisterClass),
3590 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 99 * sizeof(MCRegisterClass),
3591 .LaneMask: LaneBitmask(0x000000000000000F),
3592 .AllocationPriority: 0,
3593 .GlobalPriority: false,
3594 .TSFlags: 0x00, /* TSFlags */
3595 .SpillStackID: 0, /* SpillStackID */
3596 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3597 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3598 offsetof(X86RegisterClassStorage, SuperClasses[535]) - 99 * sizeof(MCRegisterClass),
3599 .SuperClassesSize: 9
3600 },
3601 {
3602 offsetof(X86RegisterClassStorage, Regs[1074]) - 100 * sizeof(MCRegisterClass),
3603 offsetof(X86RegisterClassStorage, BitSets[857]) - 100 * sizeof(MCRegisterClass),
3604 .NameIdx: 282,
3605 .RegSizeInBits: 64,
3606 .RegsSize: 5,
3607 .RegSetBegin: 51, /* MinRegVal */
3608 .RegSetSize: 70, /* RegSetSize */
3609 .ID: X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
3610 .CopyCost: 1, /* CopyCost */
3611 .Allocatable: true, /* Allocatable */
3612 .BaseClass: false,
3613 offsetof(X86RegisterClassStorage, SubClassMasks[875]) - 100 * sizeof(MCRegisterClass),
3614 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 100 * sizeof(MCRegisterClass),
3615 .LaneMask: LaneBitmask(0x000000000000000F),
3616 .AllocationPriority: 0,
3617 .GlobalPriority: false,
3618 .TSFlags: 0x00, /* TSFlags */
3619 .SpillStackID: 0, /* SpillStackID */
3620 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3621 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3622 offsetof(X86RegisterClassStorage, SuperClasses[544]) - 100 * sizeof(MCRegisterClass),
3623 .SuperClassesSize: 17
3624 },
3625 {
3626 offsetof(X86RegisterClassStorage, Regs[1079]) - 101 * sizeof(MCRegisterClass),
3627 offsetof(X86RegisterClassStorage, BitSets[866]) - 101 * sizeof(MCRegisterClass),
3628 .NameIdx: 644,
3629 .RegSizeInBits: 64,
3630 .RegsSize: 5,
3631 .RegSetBegin: 51, /* MinRegVal */
3632 .RegSetSize: 10, /* RegSetSize */
3633 .ID: X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
3634 .CopyCost: 1, /* CopyCost */
3635 .Allocatable: true, /* Allocatable */
3636 .BaseClass: false,
3637 offsetof(X86RegisterClassStorage, SubClassMasks[880]) - 101 * sizeof(MCRegisterClass),
3638 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 101 * sizeof(MCRegisterClass),
3639 .LaneMask: LaneBitmask(0x000000000000000F),
3640 .AllocationPriority: 0,
3641 .GlobalPriority: false,
3642 .TSFlags: 0x00, /* TSFlags */
3643 .SpillStackID: 0, /* SpillStackID */
3644 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3645 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3646 offsetof(X86RegisterClassStorage, SuperClasses[561]) - 101 * sizeof(MCRegisterClass),
3647 .SuperClassesSize: 16
3648 },
3649 {
3650 offsetof(X86RegisterClassStorage, Regs[1084]) - 102 * sizeof(MCRegisterClass),
3651 offsetof(X86RegisterClassStorage, BitSets[868]) - 102 * sizeof(MCRegisterClass),
3652 .NameIdx: 256,
3653 .RegSizeInBits: 64,
3654 .RegsSize: 5,
3655 .RegSetBegin: 51, /* MinRegVal */
3656 .RegSetSize: 11, /* RegSetSize */
3657 .ID: X86::GR64_NOREX_and_GR64_TCW64RegClassID,
3658 .CopyCost: 1, /* CopyCost */
3659 .Allocatable: true, /* Allocatable */
3660 .BaseClass: false,
3661 offsetof(X86RegisterClassStorage, SubClassMasks[885]) - 102 * sizeof(MCRegisterClass),
3662 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 102 * sizeof(MCRegisterClass),
3663 .LaneMask: LaneBitmask(0x000000000000000F),
3664 .AllocationPriority: 0,
3665 .GlobalPriority: false,
3666 .TSFlags: 0x00, /* TSFlags */
3667 .SpillStackID: 0, /* SpillStackID */
3668 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3669 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3670 offsetof(X86RegisterClassStorage, SuperClasses[577]) - 102 * sizeof(MCRegisterClass),
3671 .SuperClassesSize: 7
3672 },
3673 {
3674 offsetof(X86RegisterClassStorage, Regs[1089]) - 103 * sizeof(MCRegisterClass),
3675 offsetof(X86RegisterClassStorage, BitSets[870]) - 103 * sizeof(MCRegisterClass),
3676 .NameIdx: 733,
3677 .RegSizeInBits: 64,
3678 .RegsSize: 4,
3679 .RegSetBegin: 51, /* MinRegVal */
3680 .RegSetSize: 6, /* RegSetSize */
3681 .ID: X86::GR64_ABCDRegClassID,
3682 .CopyCost: 1, /* CopyCost */
3683 .Allocatable: true, /* Allocatable */
3684 .BaseClass: false,
3685 offsetof(X86RegisterClassStorage, SubClassMasks[890]) - 103 * sizeof(MCRegisterClass),
3686 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 103 * sizeof(MCRegisterClass),
3687 .LaneMask: LaneBitmask(0x000000000000000F),
3688 .AllocationPriority: 0,
3689 .GlobalPriority: false,
3690 .TSFlags: 0x00, /* TSFlags */
3691 .SpillStackID: 0, /* SpillStackID */
3692 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3693 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3694 offsetof(X86RegisterClassStorage, SuperClasses[584]) - 103 * sizeof(MCRegisterClass),
3695 .SuperClassesSize: 10
3696 },
3697 {
3698 offsetof(X86RegisterClassStorage, Regs[1093]) - 104 * sizeof(MCRegisterClass),
3699 offsetof(X86RegisterClassStorage, BitSets[871]) - 104 * sizeof(MCRegisterClass),
3700 .NameIdx: 561,
3701 .RegSizeInBits: 64,
3702 .RegsSize: 4,
3703 .RegSetBegin: 51, /* MinRegVal */
3704 .RegSetSize: 11, /* RegSetSize */
3705 .ID: X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
3706 .CopyCost: 1, /* CopyCost */
3707 .Allocatable: true, /* Allocatable */
3708 .BaseClass: false,
3709 offsetof(X86RegisterClassStorage, SubClassMasks[895]) - 104 * sizeof(MCRegisterClass),
3710 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 104 * sizeof(MCRegisterClass),
3711 .LaneMask: LaneBitmask(0x000000000000000F),
3712 .AllocationPriority: 0,
3713 .GlobalPriority: false,
3714 .TSFlags: 0x00, /* TSFlags */
3715 .SpillStackID: 0, /* SpillStackID */
3716 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3717 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3718 offsetof(X86RegisterClassStorage, SuperClasses[594]) - 104 * sizeof(MCRegisterClass),
3719 .SuperClassesSize: 15
3720 },
3721 {
3722 offsetof(X86RegisterClassStorage, Regs[1097]) - 105 * sizeof(MCRegisterClass),
3723 offsetof(X86RegisterClassStorage, BitSets[873]) - 105 * sizeof(MCRegisterClass),
3724 .NameIdx: 471,
3725 .RegSizeInBits: 64,
3726 .RegsSize: 3,
3727 .RegSetBegin: 51, /* MinRegVal */
3728 .RegSetSize: 6, /* RegSetSize */
3729 .ID: X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
3730 .CopyCost: 1, /* CopyCost */
3731 .Allocatable: true, /* Allocatable */
3732 .BaseClass: false,
3733 offsetof(X86RegisterClassStorage, SubClassMasks[900]) - 105 * sizeof(MCRegisterClass),
3734 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 105 * sizeof(MCRegisterClass),
3735 .LaneMask: LaneBitmask(0x000000000000000F),
3736 .AllocationPriority: 0,
3737 .GlobalPriority: false,
3738 .TSFlags: 0x00, /* TSFlags */
3739 .SpillStackID: 0, /* SpillStackID */
3740 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3741 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3742 offsetof(X86RegisterClassStorage, SuperClasses[609]) - 105 * sizeof(MCRegisterClass),
3743 .SuperClassesSize: 27
3744 },
3745 {
3746 offsetof(X86RegisterClassStorage, Regs[1100]) - 106 * sizeof(MCRegisterClass),
3747 offsetof(X86RegisterClassStorage, BitSets[874]) - 106 * sizeof(MCRegisterClass),
3748 .NameIdx: 715,
3749 .RegSizeInBits: 64,
3750 .RegsSize: 2,
3751 .RegSetBegin: 51, /* MinRegVal */
3752 .RegSetSize: 6, /* RegSetSize */
3753 .ID: X86::GR64_ADRegClassID,
3754 .CopyCost: 1, /* CopyCost */
3755 .Allocatable: true, /* Allocatable */
3756 .BaseClass: false,
3757 offsetof(X86RegisterClassStorage, SubClassMasks[905]) - 106 * sizeof(MCRegisterClass),
3758 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 106 * sizeof(MCRegisterClass),
3759 .LaneMask: LaneBitmask(0x000000000000000F),
3760 .AllocationPriority: 0,
3761 .GlobalPriority: false,
3762 .TSFlags: 0x00, /* TSFlags */
3763 .SpillStackID: 0, /* SpillStackID */
3764 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3765 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3766 offsetof(X86RegisterClassStorage, SuperClasses[636]) - 106 * sizeof(MCRegisterClass),
3767 .SuperClassesSize: 28
3768 },
3769 {
3770 offsetof(X86RegisterClassStorage, Regs[1102]) - 107 * sizeof(MCRegisterClass),
3771 offsetof(X86RegisterClassStorage, BitSets[875]) - 107 * sizeof(MCRegisterClass),
3772 .NameIdx: 1659,
3773 .RegSizeInBits: 64,
3774 .RegsSize: 2,
3775 .RegSetBegin: 121, /* MinRegVal */
3776 .RegSetSize: 2, /* RegSetSize */
3777 .ID: X86::GR64_ArgRefRegClassID,
3778 .CopyCost: 1, /* CopyCost */
3779 .Allocatable: true, /* Allocatable */
3780 .BaseClass: false,
3781 offsetof(X86RegisterClassStorage, SubClassMasks[910]) - 107 * sizeof(MCRegisterClass),
3782 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 107 * sizeof(MCRegisterClass),
3783 .LaneMask: LaneBitmask(0x000000000000000F),
3784 .AllocationPriority: 0,
3785 .GlobalPriority: false,
3786 .TSFlags: 0x00, /* TSFlags */
3787 .SpillStackID: 0, /* SpillStackID */
3788 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3789 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3790 offsetof(X86RegisterClassStorage, SuperClasses[664]) - 107 * sizeof(MCRegisterClass),
3791 .SuperClassesSize: 9
3792 },
3793 {
3794 offsetof(X86RegisterClassStorage, Regs[1104]) - 108 * sizeof(MCRegisterClass),
3795 offsetof(X86RegisterClassStorage, BitSets[876]) - 108 * sizeof(MCRegisterClass),
3796 .NameIdx: 1170,
3797 .RegSizeInBits: 64,
3798 .RegsSize: 2,
3799 .RegSetBegin: 52, /* MinRegVal */
3800 .RegSetSize: 7, /* RegSetSize */
3801 .ID: X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
3802 .CopyCost: 1, /* CopyCost */
3803 .Allocatable: true, /* Allocatable */
3804 .BaseClass: false,
3805 offsetof(X86RegisterClassStorage, SubClassMasks[915]) - 108 * sizeof(MCRegisterClass),
3806 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 108 * sizeof(MCRegisterClass),
3807 .LaneMask: LaneBitmask(0x000000000000000F),
3808 .AllocationPriority: 0,
3809 .GlobalPriority: false,
3810 .TSFlags: 0x00, /* TSFlags */
3811 .SpillStackID: 0, /* SpillStackID */
3812 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3813 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3814 offsetof(X86RegisterClassStorage, SuperClasses[673]) - 108 * sizeof(MCRegisterClass),
3815 .SuperClassesSize: 5
3816 },
3817 {
3818 offsetof(X86RegisterClassStorage, Regs[1106]) - 109 * sizeof(MCRegisterClass),
3819 offsetof(X86RegisterClassStorage, BitSets[877]) - 109 * sizeof(MCRegisterClass),
3820 .NameIdx: 1624,
3821 .RegSizeInBits: 64,
3822 .RegsSize: 2,
3823 .RegSetBegin: 54, /* MinRegVal */
3824 .RegSetSize: 3, /* RegSetSize */
3825 .ID: X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
3826 .CopyCost: 1, /* CopyCost */
3827 .Allocatable: true, /* Allocatable */
3828 .BaseClass: false,
3829 offsetof(X86RegisterClassStorage, SubClassMasks[920]) - 109 * sizeof(MCRegisterClass),
3830 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 109 * sizeof(MCRegisterClass),
3831 .LaneMask: LaneBitmask(0x000000000000000F),
3832 .AllocationPriority: 0,
3833 .GlobalPriority: false,
3834 .TSFlags: 0x00, /* TSFlags */
3835 .SpillStackID: 0, /* SpillStackID */
3836 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3837 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3838 offsetof(X86RegisterClassStorage, SuperClasses[678]) - 109 * sizeof(MCRegisterClass),
3839 .SuperClassesSize: 28
3840 },
3841 {
3842 offsetof(X86RegisterClassStorage, Regs[1108]) - 110 * sizeof(MCRegisterClass),
3843 offsetof(X86RegisterClassStorage, BitSets[878]) - 110 * sizeof(MCRegisterClass),
3844 .NameIdx: 1287,
3845 .RegSizeInBits: 64,
3846 .RegsSize: 2,
3847 .RegSetBegin: 52, /* MinRegVal */
3848 .RegSetSize: 10, /* RegSetSize */
3849 .ID: X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
3850 .CopyCost: 1, /* CopyCost */
3851 .Allocatable: true, /* Allocatable */
3852 .BaseClass: false,
3853 offsetof(X86RegisterClassStorage, SubClassMasks[925]) - 110 * sizeof(MCRegisterClass),
3854 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 110 * sizeof(MCRegisterClass),
3855 .LaneMask: LaneBitmask(0x000000000000000F),
3856 .AllocationPriority: 0,
3857 .GlobalPriority: false,
3858 .TSFlags: 0x00, /* TSFlags */
3859 .SpillStackID: 0, /* SpillStackID */
3860 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3861 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3862 offsetof(X86RegisterClassStorage, SuperClasses[706]) - 110 * sizeof(MCRegisterClass),
3863 .SuperClassesSize: 6
3864 },
3865 {
3866 offsetof(X86RegisterClassStorage, Regs[1110]) - 111 * sizeof(MCRegisterClass),
3867 offsetof(X86RegisterClassStorage, BitSets[880]) - 111 * sizeof(MCRegisterClass),
3868 .NameIdx: 975,
3869 .RegSizeInBits: 64,
3870 .RegsSize: 2,
3871 .RegSetBegin: 53, /* MinRegVal */
3872 .RegSetSize: 8, /* RegSetSize */
3873 .ID: X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID,
3874 .CopyCost: 1, /* CopyCost */
3875 .Allocatable: true, /* Allocatable */
3876 .BaseClass: false,
3877 offsetof(X86RegisterClassStorage, SubClassMasks[930]) - 111 * sizeof(MCRegisterClass),
3878 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 111 * sizeof(MCRegisterClass),
3879 .LaneMask: LaneBitmask(0x000000000000000F),
3880 .AllocationPriority: 0,
3881 .GlobalPriority: false,
3882 .TSFlags: 0x00, /* TSFlags */
3883 .SpillStackID: 0, /* SpillStackID */
3884 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3885 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3886 offsetof(X86RegisterClassStorage, SuperClasses[712]) - 111 * sizeof(MCRegisterClass),
3887 .SuperClassesSize: 10
3888 },
3889 {
3890 offsetof(X86RegisterClassStorage, Regs[1112]) - 112 * sizeof(MCRegisterClass),
3891 offsetof(X86RegisterClassStorage, BitSets[881]) - 112 * sizeof(MCRegisterClass),
3892 .NameIdx: 432,
3893 .RegSizeInBits: 64,
3894 .RegsSize: 2,
3895 .RegSetBegin: 53, /* MinRegVal */
3896 .RegSetSize: 2, /* RegSetSize */
3897 .ID: X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
3898 .CopyCost: 1, /* CopyCost */
3899 .Allocatable: true, /* Allocatable */
3900 .BaseClass: false,
3901 offsetof(X86RegisterClassStorage, SubClassMasks[935]) - 112 * sizeof(MCRegisterClass),
3902 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 112 * sizeof(MCRegisterClass),
3903 .LaneMask: LaneBitmask(0x000000000000000F),
3904 .AllocationPriority: 0,
3905 .GlobalPriority: false,
3906 .TSFlags: 0x00, /* TSFlags */
3907 .SpillStackID: 0, /* SpillStackID */
3908 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3909 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3910 offsetof(X86RegisterClassStorage, SuperClasses[722]) - 112 * sizeof(MCRegisterClass),
3911 .SuperClassesSize: 11
3912 },
3913 {
3914 offsetof(X86RegisterClassStorage, Regs[1114]) - 113 * sizeof(MCRegisterClass),
3915 offsetof(X86RegisterClassStorage, BitSets[882]) - 113 * sizeof(MCRegisterClass),
3916 .NameIdx: 1137,
3917 .RegSizeInBits: 64,
3918 .RegsSize: 2,
3919 .RegSetBegin: 52, /* MinRegVal */
3920 .RegSetSize: 4, /* RegSetSize */
3921 .ID: X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
3922 .CopyCost: 1, /* CopyCost */
3923 .Allocatable: true, /* Allocatable */
3924 .BaseClass: false,
3925 offsetof(X86RegisterClassStorage, SubClassMasks[940]) - 113 * sizeof(MCRegisterClass),
3926 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 113 * sizeof(MCRegisterClass),
3927 .LaneMask: LaneBitmask(0x000000000000000F),
3928 .AllocationPriority: 0,
3929 .GlobalPriority: false,
3930 .TSFlags: 0x00, /* TSFlags */
3931 .SpillStackID: 0, /* SpillStackID */
3932 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3933 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3934 offsetof(X86RegisterClassStorage, SuperClasses[733]) - 113 * sizeof(MCRegisterClass),
3935 .SuperClassesSize: 10
3936 },
3937 {
3938 offsetof(X86RegisterClassStorage, Regs[1116]) - 114 * sizeof(MCRegisterClass),
3939 offsetof(X86RegisterClassStorage, BitSets[883]) - 114 * sizeof(MCRegisterClass),
3940 .NameIdx: 896,
3941 .RegSizeInBits: 64,
3942 .RegsSize: 2,
3943 .RegSetBegin: 55, /* MinRegVal */
3944 .RegSetSize: 6, /* RegSetSize */
3945 .ID: X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
3946 .CopyCost: 1, /* CopyCost */
3947 .Allocatable: true, /* Allocatable */
3948 .BaseClass: false,
3949 offsetof(X86RegisterClassStorage, SubClassMasks[945]) - 114 * sizeof(MCRegisterClass),
3950 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 114 * sizeof(MCRegisterClass),
3951 .LaneMask: LaneBitmask(0x000000000000000F),
3952 .AllocationPriority: 0,
3953 .GlobalPriority: false,
3954 .TSFlags: 0x00, /* TSFlags */
3955 .SpillStackID: 0, /* SpillStackID */
3956 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3957 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3958 offsetof(X86RegisterClassStorage, SuperClasses[743]) - 114 * sizeof(MCRegisterClass),
3959 .SuperClassesSize: 17
3960 },
3961 {
3962 offsetof(X86RegisterClassStorage, Regs[1118]) - 115 * sizeof(MCRegisterClass),
3963 offsetof(X86RegisterClassStorage, BitSets[884]) - 115 * sizeof(MCRegisterClass),
3964 .NameIdx: 378,
3965 .RegSizeInBits: 64,
3966 .RegsSize: 1,
3967 .RegSetBegin: 51, /* MinRegVal */
3968 .RegSetSize: 1, /* RegSetSize */
3969 .ID: X86::GR64_ARegClassID,
3970 .CopyCost: 1, /* CopyCost */
3971 .Allocatable: true, /* Allocatable */
3972 .BaseClass: false,
3973 offsetof(X86RegisterClassStorage, SubClassMasks[950]) - 115 * sizeof(MCRegisterClass),
3974 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 115 * sizeof(MCRegisterClass),
3975 .LaneMask: LaneBitmask(0x000000000000000F),
3976 .AllocationPriority: 0,
3977 .GlobalPriority: false,
3978 .TSFlags: 0x00, /* TSFlags */
3979 .SpillStackID: 0, /* SpillStackID */
3980 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3981 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3982 offsetof(X86RegisterClassStorage, SuperClasses[760]) - 115 * sizeof(MCRegisterClass),
3983 .SuperClassesSize: 29
3984 },
3985 {
3986 offsetof(X86RegisterClassStorage, Regs[1119]) - 116 * sizeof(MCRegisterClass),
3987 offsetof(X86RegisterClassStorage, BitSets[885]) - 116 * sizeof(MCRegisterClass),
3988 .NameIdx: 683,
3989 .RegSizeInBits: 64,
3990 .RegsSize: 1,
3991 .RegSetBegin: 122, /* MinRegVal */
3992 .RegSetSize: 1, /* RegSetSize */
3993 .ID: X86::GR64_ArgRef_and_GR64_TCRegClassID,
3994 .CopyCost: 1, /* CopyCost */
3995 .Allocatable: true, /* Allocatable */
3996 .BaseClass: false,
3997 offsetof(X86RegisterClassStorage, SubClassMasks[955]) - 116 * sizeof(MCRegisterClass),
3998 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 116 * sizeof(MCRegisterClass),
3999 .LaneMask: LaneBitmask(0x000000000000000F),
4000 .AllocationPriority: 0,
4001 .GlobalPriority: false,
4002 .TSFlags: 0x00, /* TSFlags */
4003 .SpillStackID: 0, /* SpillStackID */
4004 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4005 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4006 offsetof(X86RegisterClassStorage, SuperClasses[789]) - 116 * sizeof(MCRegisterClass),
4007 .SuperClassesSize: 16
4008 },
4009 {
4010 offsetof(X86RegisterClassStorage, Regs[1120]) - 117 * sizeof(MCRegisterClass),
4011 offsetof(X86RegisterClassStorage, BitSets[886]) - 117 * sizeof(MCRegisterClass),
4012 .NameIdx: 1373,
4013 .RegSizeInBits: 64,
4014 .RegsSize: 1,
4015 .RegSetBegin: 58, /* MinRegVal */
4016 .RegSetSize: 1, /* RegSetSize */
4017 .ID: X86::GR64_and_LOW32_ADDR_ACCESSRegClassID,
4018 .CopyCost: 1, /* CopyCost */
4019 .Allocatable: true, /* Allocatable */
4020 .BaseClass: false,
4021 offsetof(X86RegisterClassStorage, SubClassMasks[960]) - 117 * sizeof(MCRegisterClass),
4022 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 117 * sizeof(MCRegisterClass),
4023 .LaneMask: LaneBitmask(0x000000000000000F),
4024 .AllocationPriority: 0,
4025 .GlobalPriority: false,
4026 .TSFlags: 0x00, /* TSFlags */
4027 .SpillStackID: 0, /* SpillStackID */
4028 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4029 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4030 offsetof(X86RegisterClassStorage, SuperClasses[805]) - 117 * sizeof(MCRegisterClass),
4031 .SuperClassesSize: 13
4032 },
4033 {
4034 offsetof(X86RegisterClassStorage, Regs[1121]) - 118 * sizeof(MCRegisterClass),
4035 offsetof(X86RegisterClassStorage, BitSets[887]) - 118 * sizeof(MCRegisterClass),
4036 .NameIdx: 929,
4037 .RegSizeInBits: 64,
4038 .RegsSize: 1,
4039 .RegSetBegin: 53, /* MinRegVal */
4040 .RegSetSize: 1, /* RegSetSize */
4041 .ID: X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID,
4042 .CopyCost: 1, /* CopyCost */
4043 .Allocatable: true, /* Allocatable */
4044 .BaseClass: false,
4045 offsetof(X86RegisterClassStorage, SubClassMasks[965]) - 118 * sizeof(MCRegisterClass),
4046 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 118 * sizeof(MCRegisterClass),
4047 .LaneMask: LaneBitmask(0x000000000000000F),
4048 .AllocationPriority: 0,
4049 .GlobalPriority: false,
4050 .TSFlags: 0x00, /* TSFlags */
4051 .SpillStackID: 0, /* SpillStackID */
4052 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4053 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4054 offsetof(X86RegisterClassStorage, SuperClasses[818]) - 118 * sizeof(MCRegisterClass),
4055 .SuperClassesSize: 13
4056 },
4057 {
4058 offsetof(X86RegisterClassStorage, Regs[1122]) - 119 * sizeof(MCRegisterClass),
4059 offsetof(X86RegisterClassStorage, BitSets[888]) - 119 * sizeof(MCRegisterClass),
4060 .NameIdx: 1577,
4061 .RegSizeInBits: 64,
4062 .RegsSize: 1,
4063 .RegSetBegin: 56, /* MinRegVal */
4064 .RegSetSize: 1, /* RegSetSize */
4065 .ID: X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID,
4066 .CopyCost: 1, /* CopyCost */
4067 .Allocatable: true, /* Allocatable */
4068 .BaseClass: false,
4069 offsetof(X86RegisterClassStorage, SubClassMasks[970]) - 119 * sizeof(MCRegisterClass),
4070 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 119 * sizeof(MCRegisterClass),
4071 .LaneMask: LaneBitmask(0x000000000000000F),
4072 .AllocationPriority: 0,
4073 .GlobalPriority: false,
4074 .TSFlags: 0x00, /* TSFlags */
4075 .SpillStackID: 0, /* SpillStackID */
4076 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4077 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4078 offsetof(X86RegisterClassStorage, SuperClasses[831]) - 119 * sizeof(MCRegisterClass),
4079 .SuperClassesSize: 30
4080 },
4081 {
4082 offsetof(X86RegisterClassStorage, Regs[1123]) - 120 * sizeof(MCRegisterClass),
4083 offsetof(X86RegisterClassStorage, BitSets[889]) - 120 * sizeof(MCRegisterClass),
4084 .NameIdx: 385,
4085 .RegSizeInBits: 64,
4086 .RegsSize: 1,
4087 .RegSetBegin: 54, /* MinRegVal */
4088 .RegSetSize: 1, /* RegSetSize */
4089 .ID: X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID,
4090 .CopyCost: 1, /* CopyCost */
4091 .Allocatable: true, /* Allocatable */
4092 .BaseClass: false,
4093 offsetof(X86RegisterClassStorage, SubClassMasks[975]) - 120 * sizeof(MCRegisterClass),
4094 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 120 * sizeof(MCRegisterClass),
4095 .LaneMask: LaneBitmask(0x000000000000000F),
4096 .AllocationPriority: 0,
4097 .GlobalPriority: false,
4098 .TSFlags: 0x00, /* TSFlags */
4099 .SpillStackID: 0, /* SpillStackID */
4100 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4101 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4102 offsetof(X86RegisterClassStorage, SuperClasses[861]) - 120 * sizeof(MCRegisterClass),
4103 .SuperClassesSize: 30
4104 },
4105 {
4106 offsetof(X86RegisterClassStorage, Regs[1124]) - 121 * sizeof(MCRegisterClass),
4107 offsetof(X86RegisterClassStorage, BitSets[890]) - 121 * sizeof(MCRegisterClass),
4108 .NameIdx: 1090,
4109 .RegSizeInBits: 64,
4110 .RegsSize: 1,
4111 .RegSetBegin: 52, /* MinRegVal */
4112 .RegSetSize: 1, /* RegSetSize */
4113 .ID: X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID,
4114 .CopyCost: 1, /* CopyCost */
4115 .Allocatable: true, /* Allocatable */
4116 .BaseClass: false,
4117 offsetof(X86RegisterClassStorage, SubClassMasks[980]) - 121 * sizeof(MCRegisterClass),
4118 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 121 * sizeof(MCRegisterClass),
4119 .LaneMask: LaneBitmask(0x000000000000000F),
4120 .AllocationPriority: 0,
4121 .GlobalPriority: false,
4122 .TSFlags: 0x00, /* TSFlags */
4123 .SpillStackID: 0, /* SpillStackID */
4124 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4125 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4126 offsetof(X86RegisterClassStorage, SuperClasses[891]) - 121 * sizeof(MCRegisterClass),
4127 .SuperClassesSize: 19
4128 },
4129 {
4130 offsetof(X86RegisterClassStorage, Regs[1125]) - 122 * sizeof(MCRegisterClass),
4131 offsetof(X86RegisterClassStorage, BitSets[891]) - 122 * sizeof(MCRegisterClass),
4132 .NameIdx: 516,
4133 .RegSizeInBits: 64,
4134 .RegsSize: 1,
4135 .RegSetBegin: 61, /* MinRegVal */
4136 .RegSetSize: 1, /* RegSetSize */
4137 .ID: X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID,
4138 .CopyCost: 1, /* CopyCost */
4139 .Allocatable: true, /* Allocatable */
4140 .BaseClass: false,
4141 offsetof(X86RegisterClassStorage, SubClassMasks[985]) - 122 * sizeof(MCRegisterClass),
4142 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 122 * sizeof(MCRegisterClass),
4143 .LaneMask: LaneBitmask(0x000000000000000F),
4144 .AllocationPriority: 0,
4145 .GlobalPriority: false,
4146 .TSFlags: 0x00, /* TSFlags */
4147 .SpillStackID: 0, /* SpillStackID */
4148 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4149 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4150 offsetof(X86RegisterClassStorage, SuperClasses[910]) - 122 * sizeof(MCRegisterClass),
4151 .SuperClassesSize: 17
4152 },
4153 {
4154 offsetof(X86RegisterClassStorage, Regs[1126]) - 123 * sizeof(MCRegisterClass),
4155 offsetof(X86RegisterClassStorage, BitSets[892]) - 123 * sizeof(MCRegisterClass),
4156 .NameIdx: 803,
4157 .RegSizeInBits: 64,
4158 .RegsSize: 1,
4159 .RegSetBegin: 60, /* MinRegVal */
4160 .RegSetSize: 1, /* RegSetSize */
4161 .ID: X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID,
4162 .CopyCost: 1, /* CopyCost */
4163 .Allocatable: true, /* Allocatable */
4164 .BaseClass: false,
4165 offsetof(X86RegisterClassStorage, SubClassMasks[990]) - 123 * sizeof(MCRegisterClass),
4166 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 123 * sizeof(MCRegisterClass),
4167 .LaneMask: LaneBitmask(0x000000000000000F),
4168 .AllocationPriority: 0,
4169 .GlobalPriority: false,
4170 .TSFlags: 0x00, /* TSFlags */
4171 .SpillStackID: 0, /* SpillStackID */
4172 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4173 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4174 offsetof(X86RegisterClassStorage, SuperClasses[927]) - 123 * sizeof(MCRegisterClass),
4175 .SuperClassesSize: 19
4176 },
4177 {
4178 offsetof(X86RegisterClassStorage, Regs[1127]) - 124 * sizeof(MCRegisterClass),
4179 offsetof(X86RegisterClassStorage, BitSets[893]) - 124 * sizeof(MCRegisterClass),
4180 .NameIdx: 849,
4181 .RegSizeInBits: 64,
4182 .RegsSize: 1,
4183 .RegSetBegin: 55, /* MinRegVal */
4184 .RegSetSize: 1, /* RegSetSize */
4185 .ID: X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID,
4186 .CopyCost: 1, /* CopyCost */
4187 .Allocatable: true, /* Allocatable */
4188 .BaseClass: false,
4189 offsetof(X86RegisterClassStorage, SubClassMasks[995]) - 124 * sizeof(MCRegisterClass),
4190 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 124 * sizeof(MCRegisterClass),
4191 .LaneMask: LaneBitmask(0x000000000000000F),
4192 .AllocationPriority: 0,
4193 .GlobalPriority: false,
4194 .TSFlags: 0x00, /* TSFlags */
4195 .SpillStackID: 0, /* SpillStackID */
4196 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4197 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4198 offsetof(X86RegisterClassStorage, SuperClasses[946]) - 124 * sizeof(MCRegisterClass),
4199 .SuperClassesSize: 19
4200 },
4201 {
4202 offsetof(X86RegisterClassStorage, Regs[1128]) - 125 * sizeof(MCRegisterClass),
4203 offsetof(X86RegisterClassStorage, BitSets[894]) - 125 * sizeof(MCRegisterClass),
4204 .NameIdx: 1400,
4205 .RegSizeInBits: 80,
4206 .RegsSize: 8,
4207 .RegSetBegin: 127, /* MinRegVal */
4208 .RegSetSize: 8, /* RegSetSize */
4209 .ID: X86::RSTRegClassID,
4210 .CopyCost: 1, /* CopyCost */
4211 .Allocatable: false, /* Allocatable */
4212 .BaseClass: false,
4213 offsetof(X86RegisterClassStorage, SubClassMasks[1000]) - 125 * sizeof(MCRegisterClass),
4214 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 125 * sizeof(MCRegisterClass),
4215 .LaneMask: LaneBitmask(0x0000000000000001),
4216 .AllocationPriority: 0,
4217 .GlobalPriority: false,
4218 .TSFlags: 0x00, /* TSFlags */
4219 .SpillStackID: 0, /* SpillStackID */
4220 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4221 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4222 offsetof(X86RegisterClassStorage, SuperClasses[965]) - 125 * sizeof(MCRegisterClass),
4223 .SuperClassesSize: 0
4224 },
4225 {
4226 offsetof(X86RegisterClassStorage, Regs[1136]) - 126 * sizeof(MCRegisterClass),
4227 offsetof(X86RegisterClassStorage, BitSets[895]) - 126 * sizeof(MCRegisterClass),
4228 .NameIdx: 0,
4229 .RegSizeInBits: 80,
4230 .RegsSize: 7,
4231 .RegSetBegin: 103, /* MinRegVal */
4232 .RegSetSize: 7, /* RegSetSize */
4233 .ID: X86::RFP80RegClassID,
4234 .CopyCost: 1, /* CopyCost */
4235 .Allocatable: true, /* Allocatable */
4236 .BaseClass: false,
4237 offsetof(X86RegisterClassStorage, SubClassMasks[1005]) - 126 * sizeof(MCRegisterClass),
4238 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 126 * sizeof(MCRegisterClass),
4239 .LaneMask: LaneBitmask(0x0000000000000001),
4240 .AllocationPriority: 0,
4241 .GlobalPriority: false,
4242 .TSFlags: 0x00, /* TSFlags */
4243 .SpillStackID: 0, /* SpillStackID */
4244 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4245 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4246 offsetof(X86RegisterClassStorage, SuperClasses[965]) - 126 * sizeof(MCRegisterClass),
4247 .SuperClassesSize: 2
4248 },
4249 {
4250 offsetof(X86RegisterClassStorage, Regs[1143]) - 127 * sizeof(MCRegisterClass),
4251 offsetof(X86RegisterClassStorage, BitSets[896]) - 127 * sizeof(MCRegisterClass),
4252 .NameIdx: 351,
4253 .RegSizeInBits: 80,
4254 .RegsSize: 1,
4255 .RegSetBegin: 110, /* MinRegVal */
4256 .RegSetSize: 1, /* RegSetSize */
4257 .ID: X86::RFP80_7RegClassID,
4258 .CopyCost: 1, /* CopyCost */
4259 .Allocatable: false, /* Allocatable */
4260 .BaseClass: false,
4261 offsetof(X86RegisterClassStorage, SubClassMasks[1010]) - 127 * sizeof(MCRegisterClass),
4262 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 127 * sizeof(MCRegisterClass),
4263 .LaneMask: LaneBitmask(0x0000000000000001),
4264 .AllocationPriority: 0,
4265 .GlobalPriority: false,
4266 .TSFlags: 0x00, /* TSFlags */
4267 .SpillStackID: 0, /* SpillStackID */
4268 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4269 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4270 offsetof(X86RegisterClassStorage, SuperClasses[967]) - 127 * sizeof(MCRegisterClass),
4271 .SuperClassesSize: 0
4272 },
4273 {
4274 offsetof(X86RegisterClassStorage, Regs[1144]) - 128 * sizeof(MCRegisterClass),
4275 offsetof(X86RegisterClassStorage, BitSets[897]) - 128 * sizeof(MCRegisterClass),
4276 .NameIdx: 1429,
4277 .RegSizeInBits: 128,
4278 .RegsSize: 32,
4279 .RegSetBegin: 135, /* MinRegVal */
4280 .RegSetSize: 96, /* RegSetSize */
4281 .ID: X86::VR128XRegClassID,
4282 .CopyCost: 1, /* CopyCost */
4283 .Allocatable: true, /* Allocatable */
4284 .BaseClass: false,
4285 offsetof(X86RegisterClassStorage, SubClassMasks[1015]) - 128 * sizeof(MCRegisterClass),
4286 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 128 * sizeof(MCRegisterClass),
4287 .LaneMask: LaneBitmask(0x0000000000000001),
4288 .AllocationPriority: 0,
4289 .GlobalPriority: false,
4290 .TSFlags: 0x00, /* TSFlags */
4291 .SpillStackID: 0, /* SpillStackID */
4292 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4293 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4294 offsetof(X86RegisterClassStorage, SuperClasses[967]) - 128 * sizeof(MCRegisterClass),
4295 .SuperClassesSize: 3
4296 },
4297 {
4298 offsetof(X86RegisterClassStorage, Regs[1176]) - 129 * sizeof(MCRegisterClass),
4299 offsetof(X86RegisterClassStorage, BitSets[909]) - 129 * sizeof(MCRegisterClass),
4300 .NameIdx: 359,
4301 .RegSizeInBits: 128,
4302 .RegsSize: 16,
4303 .RegSetBegin: 135, /* MinRegVal */
4304 .RegSetSize: 16, /* RegSetSize */
4305 .ID: X86::VR128RegClassID,
4306 .CopyCost: 1, /* CopyCost */
4307 .Allocatable: true, /* Allocatable */
4308 .BaseClass: false,
4309 offsetof(X86RegisterClassStorage, SubClassMasks[1025]) - 129 * sizeof(MCRegisterClass),
4310 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[12]) - 129 * sizeof(MCRegisterClass),
4311 .LaneMask: LaneBitmask(0x0000000000000001),
4312 .AllocationPriority: 0,
4313 .GlobalPriority: false,
4314 .TSFlags: 0x00, /* TSFlags */
4315 .SpillStackID: 0, /* SpillStackID */
4316 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4317 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4318 offsetof(X86RegisterClassStorage, SuperClasses[970]) - 129 * sizeof(MCRegisterClass),
4319 .SuperClassesSize: 7
4320 },
4321 {
4322 offsetof(X86RegisterClassStorage, Regs[1192]) - 130 * sizeof(MCRegisterClass),
4323 offsetof(X86RegisterClassStorage, BitSets[911]) - 130 * sizeof(MCRegisterClass),
4324 .NameIdx: 1422,
4325 .RegSizeInBits: 256,
4326 .RegsSize: 32,
4327 .RegSetBegin: 191, /* MinRegVal */
4328 .RegSetSize: 56, /* RegSetSize */
4329 .ID: X86::VR256XRegClassID,
4330 .CopyCost: 1, /* CopyCost */
4331 .Allocatable: true, /* Allocatable */
4332 .BaseClass: false,
4333 offsetof(X86RegisterClassStorage, SubClassMasks[1035]) - 130 * sizeof(MCRegisterClass),
4334 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[14]) - 130 * sizeof(MCRegisterClass),
4335 .LaneMask: LaneBitmask(0x0000000000000040),
4336 .AllocationPriority: 0,
4337 .GlobalPriority: false,
4338 .TSFlags: 0x00, /* TSFlags */
4339 .SpillStackID: 0, /* SpillStackID */
4340 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4341 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4342 offsetof(X86RegisterClassStorage, SuperClasses[977]) - 130 * sizeof(MCRegisterClass),
4343 .SuperClassesSize: 0
4344 },
4345 {
4346 offsetof(X86RegisterClassStorage, Regs[1224]) - 131 * sizeof(MCRegisterClass),
4347 offsetof(X86RegisterClassStorage, BitSets[918]) - 131 * sizeof(MCRegisterClass),
4348 .NameIdx: 345,
4349 .RegSizeInBits: 256,
4350 .RegsSize: 16,
4351 .RegSetBegin: 191, /* MinRegVal */
4352 .RegSetSize: 16, /* RegSetSize */
4353 .ID: X86::VR256RegClassID,
4354 .CopyCost: 1, /* CopyCost */
4355 .Allocatable: true, /* Allocatable */
4356 .BaseClass: false,
4357 offsetof(X86RegisterClassStorage, SubClassMasks[1045]) - 131 * sizeof(MCRegisterClass),
4358 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[14]) - 131 * sizeof(MCRegisterClass),
4359 .LaneMask: LaneBitmask(0x0000000000000040),
4360 .AllocationPriority: 0,
4361 .GlobalPriority: false,
4362 .TSFlags: 0x00, /* TSFlags */
4363 .SpillStackID: 0, /* SpillStackID */
4364 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4365 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4366 offsetof(X86RegisterClassStorage, SuperClasses[977]) - 131 * sizeof(MCRegisterClass),
4367 .SuperClassesSize: 1
4368 },
4369 {
4370 offsetof(X86RegisterClassStorage, Regs[1240]) - 132 * sizeof(MCRegisterClass),
4371 offsetof(X86RegisterClassStorage, BitSets[920]) - 132 * sizeof(MCRegisterClass),
4372 .NameIdx: 10,
4373 .RegSizeInBits: 512,
4374 .RegsSize: 32,
4375 .RegSetBegin: 247, /* MinRegVal */
4376 .RegSetSize: 32, /* RegSetSize */
4377 .ID: X86::VR512RegClassID,
4378 .CopyCost: 1, /* CopyCost */
4379 .Allocatable: true, /* Allocatable */
4380 .BaseClass: false,
4381 offsetof(X86RegisterClassStorage, SubClassMasks[1055]) - 132 * sizeof(MCRegisterClass),
4382 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 132 * sizeof(MCRegisterClass),
4383 .LaneMask: LaneBitmask(0x0000000000000040),
4384 .AllocationPriority: 0,
4385 .GlobalPriority: false,
4386 .TSFlags: 0x00, /* TSFlags */
4387 .SpillStackID: 0, /* SpillStackID */
4388 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4389 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4390 offsetof(X86RegisterClassStorage, SuperClasses[978]) - 132 * sizeof(MCRegisterClass),
4391 .SuperClassesSize: 0
4392 },
4393 {
4394 offsetof(X86RegisterClassStorage, Regs[1272]) - 133 * sizeof(MCRegisterClass),
4395 offsetof(X86RegisterClassStorage, BitSets[924]) - 133 * sizeof(MCRegisterClass),
4396 .NameIdx: 313,
4397 .RegSizeInBits: 512,
4398 .RegsSize: 16,
4399 .RegSetBegin: 247, /* MinRegVal */
4400 .RegSetSize: 16, /* RegSetSize */
4401 .ID: X86::VR512_0_15RegClassID,
4402 .CopyCost: 1, /* CopyCost */
4403 .Allocatable: true, /* Allocatable */
4404 .BaseClass: false,
4405 offsetof(X86RegisterClassStorage, SubClassMasks[1060]) - 133 * sizeof(MCRegisterClass),
4406 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 133 * sizeof(MCRegisterClass),
4407 .LaneMask: LaneBitmask(0x0000000000000040),
4408 .AllocationPriority: 0,
4409 .GlobalPriority: false,
4410 .TSFlags: 0x00, /* TSFlags */
4411 .SpillStackID: 0, /* SpillStackID */
4412 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4413 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4414 offsetof(X86RegisterClassStorage, SuperClasses[978]) - 133 * sizeof(MCRegisterClass),
4415 .SuperClassesSize: 1
4416 },
4417 {
4418 offsetof(X86RegisterClassStorage, Regs[1288]) - 134 * sizeof(MCRegisterClass),
4419 offsetof(X86RegisterClassStorage, BitSets[926]) - 134 * sizeof(MCRegisterClass),
4420 .NameIdx: 753,
4421 .RegSizeInBits: 8192,
4422 .RegsSize: 8,
4423 .RegSetBegin: 284, /* MinRegVal */
4424 .RegSetSize: 8, /* RegSetSize */
4425 .ID: X86::TILERegClassID,
4426 .CopyCost: 255, /* CopyCost */
4427 .Allocatable: true, /* Allocatable */
4428 .BaseClass: false,
4429 offsetof(X86RegisterClassStorage, SubClassMasks[1065]) - 134 * sizeof(MCRegisterClass),
4430 offsetof(X86RegisterClassStorage, SuperRegIdxSeqs[1]) - 134 * sizeof(MCRegisterClass),
4431 .LaneMask: LaneBitmask(0x0000000000000001),
4432 .AllocationPriority: 0,
4433 .GlobalPriority: false,
4434 .TSFlags: 0x00, /* TSFlags */
4435 .SpillStackID: 0, /* SpillStackID */
4436 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4437 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4438 offsetof(X86RegisterClassStorage, SuperClasses[979]) - 134 * sizeof(MCRegisterClass),
4439 .SuperClassesSize: 0
4440 },
4441 },
4442 .Regs: {
4443 /* 0 */ X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::R20B, X86::R21B, X86::R28B, X86::R29B, X86::R30B, X86::R31B,
4444 /* 36 */ X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH, X86::R16BH, X86::R17BH, X86::R18BH, X86::R19BH, X86::R20BH, X86::R21BH, X86::R22BH, X86::R23BH, X86::R24BH, X86::R25BH, X86::R26BH, X86::R27BH, X86::R28BH, X86::R29BH, X86::R30BH, X86::R31BH,
4445 /* 64 */ X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
4446 /* 84 */ X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
4447 /* 92 */ X86::AH, X86::CH, X86::DH, X86::BH,
4448 /* 96 */ X86::AL, X86::CL, X86::DL, X86::BL,
4449 /* 100 */ X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH, X86::R16WH, X86::R17WH, X86::R18WH, X86::R19WH, X86::R20WH, X86::R21WH, X86::R22WH, X86::R23WH, X86::R24WH, X86::R25WH, X86::R26WH, X86::R27WH, X86::R28WH, X86::R29WH, X86::R30WH, X86::R31WH,
4450 /* 133 */ X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R16W, X86::R17W, X86::R18W, X86::R19W, X86::R22W, X86::R23W, X86::R24W, X86::R25W, X86::R26W, X86::R27W, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::R20W, X86::R21W, X86::R28W, X86::R29W, X86::R30W, X86::R31W,
4451 /* 165 */ X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
4452 /* 181 */ X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP,
4453 /* 189 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4454 /* 197 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4455 /* 205 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4456 /* 213 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4457 /* 221 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4458 /* 229 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4459 /* 236 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4460 /* 243 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4461 /* 250 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4462 /* 257 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4463 /* 264 */ X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS,
4464 /* 270 */ X86::AX, X86::CX, X86::DX, X86::BX,
4465 /* 274 */ X86::FPSW,
4466 /* 275 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
4467 /* 307 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
4468 /* 323 */ X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
4469 /* 327 */ X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
4470 /* 331 */ X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
4471 /* 335 */ X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
4472 /* 339 */ X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
4473 /* 343 */ X86::K2_K3, X86::K4_K5, X86::K6_K7,
4474 /* 346 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::R30D, X86::R31D, X86::RIP, X86::RBP,
4475 /* 380 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::R30D, X86::R31D, X86::RIP,
4476 /* 413 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::R30D, X86::R31D, X86::RBP,
4477 /* 446 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
4478 /* 478 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::R30D, X86::R31D,
4479 /* 510 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::R30D, X86::R31D,
4480 /* 541 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP,
4481 /* 558 */ X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15,
4482 /* 574 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
4483 /* 590 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
4484 /* 606 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
4485 /* 621 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP,
4486 /* 630 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP,
4487 /* 638 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4488 /* 646 */ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,
4489 /* 653 */ X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
4490 /* 660 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4491 /* 667 */ X86::EAX, X86::ECX, X86::EDX, X86::EBX,
4492 /* 671 */ X86::EAX, X86::ECX, X86::EDX, X86::ESP,
4493 /* 675 */ X86::EAX, X86::ECX, X86::EDX,
4494 /* 678 */ X86::EAX, X86::EDX,
4495 /* 680 */ X86::ECX, X86::EDX,
4496 /* 682 */ X86::EBP, X86::ESP,
4497 /* 684 */ X86::EBX, X86::ESI,
4498 /* 686 */ X86::ECX, X86::EBX,
4499 /* 688 */ X86::EDX, X86::ECX,
4500 /* 690 */ X86::EDI, X86::EBP,
4501 /* 692 */ X86::ESI, X86::EDI,
4502 /* 694 */ X86::RIP, X86::RBP,
4503 /* 696 */ X86::EFLAGS,
4504 /* 697 */ X86::DF,
4505 /* 698 */ X86::EBX,
4506 /* 699 */ X86::EDX,
4507 /* 700 */ X86::ECX,
4508 /* 701 */ X86::EBP,
4509 /* 702 */ X86::ESP,
4510 /* 703 */ X86::ESI,
4511 /* 704 */ X86::EDI,
4512 /* 705 */ X86::RBP,
4513 /* 706 */ X86::RIP,
4514 /* 707 */ X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
4515 /* 714 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::R30, X86::R31, X86::RBP, X86::RSP, X86::RIP,
4516 /* 747 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
4517 /* 779 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::R30, X86::R31, X86::RBP, X86::RSP,
4518 /* 811 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::R30, X86::R31, X86::RBP,
4519 /* 842 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
4520 /* 859 */ X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15,
4521 /* 875 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
4522 /* 891 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
4523 /* 907 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
4524 /* 922 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
4525 /* 935 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
4526 /* 945 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
4527 /* 954 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP,
4528 /* 963 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP,
4529 /* 972 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11,
4530 /* 980 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP,
4531 /* 988 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
4532 /* 996 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP,
4533 /* 1004 */ X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4534 /* 1012 */ X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
4535 /* 1020 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9,
4536 /* 1027 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11,
4537 /* 1034 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP,
4538 /* 1041 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP,
4539 /* 1048 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP,
4540 /* 1055 */ X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
4541 /* 1062 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11,
4542 /* 1068 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP,
4543 /* 1074 */ X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9,
4544 /* 1079 */ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI,
4545 /* 1084 */ X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP,
4546 /* 1089 */ X86::RAX, X86::RCX, X86::RDX, X86::RBX,
4547 /* 1093 */ X86::RAX, X86::RCX, X86::RDX, X86::RSP,
4548 /* 1097 */ X86::RAX, X86::RCX, X86::RDX,
4549 /* 1100 */ X86::RAX, X86::RDX,
4550 /* 1102 */ X86::R10, X86::R11,
4551 /* 1104 */ X86::RBP, X86::RIP,
4552 /* 1106 */ X86::RCX, X86::RDX,
4553 /* 1108 */ X86::RBP, X86::RSP,
4554 /* 1110 */ X86::RSI, X86::RBX,
4555 /* 1112 */ X86::RCX, X86::RBX,
4556 /* 1114 */ X86::RDI, X86::RBP,
4557 /* 1116 */ X86::RSI, X86::RDI,
4558 /* 1118 */ X86::RAX,
4559 /* 1119 */ X86::R11,
4560 /* 1120 */ X86::RIP,
4561 /* 1121 */ X86::RBX,
4562 /* 1122 */ X86::RDX,
4563 /* 1123 */ X86::RCX,
4564 /* 1124 */ X86::RBP,
4565 /* 1125 */ X86::RSP,
4566 /* 1126 */ X86::RSI,
4567 /* 1127 */ X86::RDI,
4568 /* 1128 */ X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
4569 /* 1136 */ X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
4570 /* 1143 */ X86::FP7,
4571 /* 1144 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
4572 /* 1176 */ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
4573 /* 1192 */ X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31,
4574 /* 1224 */ X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15,
4575 /* 1240 */ X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31,
4576 /* 1272 */ X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15,
4577 /* 1288 */ X86::TMM0, X86::TMM1, X86::TMM2, X86::TMM3, X86::TMM4, X86::TMM5, X86::TMM6, X86::TMM7,
4578 },
4579 .BitSets: {
4580 /* 0 */ 0x9b, 0x46, 0x06, 0x00, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
4581 /* 41 */ 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
4582 /* 83 */ 0x9b, 0x46, 0x06, 0x00, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
4583 /* 103 */ 0x1b, 0x46, 0x04,
4584 /* 106 */ 0x09, 0x42,
4585 /* 108 */ 0x09, 0x02, 0x02,
4586 /* 111 */ 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
4587 /* 155 */ 0x49, 0x24, 0x04, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
4588 /* 202 */ 0x49, 0x24, 0x04, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
4589 /* 225 */ 0x49, 0x24, 0x04, 0x00, 0x00, 0x00, 0x00, 0x48,
4590 /* 233 */ 0xff,
4591 /* 234 */ 0xff,
4592 /* 235 */ 0xff,
4593 /* 236 */ 0xff,
4594 /* 237 */ 0xff,
4595 /* 238 */ 0x7f,
4596 /* 239 */ 0x7f,
4597 /* 240 */ 0x7f,
4598 /* 241 */ 0x7f,
4599 /* 242 */ 0x7f,
4600 /* 243 */ 0x01, 0x01, 0x08, 0x05, 0x00, 0x00, 0x00, 0x01,
4601 /* 251 */ 0x41, 0x04, 0x04,
4602 /* 254 */ 0x01,
4603 /* 255 */ 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
4604 /* 267 */ 0xff, 0xff,
4605 /* 269 */ 0x0f,
4606 /* 270 */ 0x0f,
4607 /* 271 */ 0x0f,
4608 /* 272 */ 0x0f,
4609 /* 273 */ 0x0f,
4610 /* 274 */ 0x07,
4611 /* 275 */ 0x3f, 0x0c, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
4612 /* 317 */ 0x3f, 0x0c, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
4613 /* 359 */ 0x3f, 0x0c, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
4614 /* 401 */ 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
4615 /* 413 */ 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
4616 /* 455 */ 0x3f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
4617 /* 497 */ 0x3f, 0x0c, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
4618 /* 517 */ 0xff, 0xff,
4619 /* 519 */ 0xff, 0xff,
4620 /* 521 */ 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
4621 /* 541 */ 0x3f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
4622 /* 561 */ 0x3f, 0x0c, 0x00, 0x40,
4623 /* 565 */ 0x3f, 0x0c,
4624 /* 567 */ 0xff,
4625 /* 568 */ 0x3f, 0x04,
4626 /* 570 */ 0x7f,
4627 /* 571 */ 0x7f,
4628 /* 572 */ 0x2d,
4629 /* 573 */ 0x29, 0x08,
4630 /* 575 */ 0x29,
4631 /* 576 */ 0x21,
4632 /* 577 */ 0x05,
4633 /* 578 */ 0x01, 0x04,
4634 /* 580 */ 0x01, 0x01,
4635 /* 582 */ 0x03,
4636 /* 583 */ 0x05,
4637 /* 584 */ 0x09,
4638 /* 585 */ 0x41,
4639 /* 586 */ 0x41,
4640 /* 587 */ 0x01,
4641 /* 588 */ 0x01,
4642 /* 589 */ 0x01,
4643 /* 590 */ 0x01,
4644 /* 591 */ 0x01,
4645 /* 592 */ 0x01,
4646 /* 593 */ 0x01,
4647 /* 594 */ 0x01,
4648 /* 595 */ 0x01,
4649 /* 596 */ 0x01,
4650 /* 597 */ 0x01,
4651 /* 598 */ 0x7f,
4652 /* 599 */ 0xbf, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
4653 /* 632 */ 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
4654 /* 644 */ 0x3f, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
4655 /* 677 */ 0x3f, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
4656 /* 710 */ 0xbf, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
4657 /* 720 */ 0xff, 0xff,
4658 /* 722 */ 0xff, 0xff,
4659 /* 724 */ 0x3f, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
4660 /* 734 */ 0x3f, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
4661 /* 744 */ 0x3f, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0f,
4662 /* 754 */ 0xb9, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0,
4663 /* 763 */ 0xbf, 0x06,
4664 /* 765 */ 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
4665 /* 774 */ 0x39, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0,
4666 /* 783 */ 0x39, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0,
4667 /* 792 */ 0x29, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
4668 /* 801 */ 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0,
4669 /* 810 */ 0x3f, 0x06,
4670 /* 812 */ 0xff,
4671 /* 813 */ 0xff,
4672 /* 814 */ 0x39, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
4673 /* 823 */ 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
4674 /* 832 */ 0x3f, 0x02,
4675 /* 834 */ 0xb9, 0x06,
4676 /* 836 */ 0x29, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0,
4677 /* 845 */ 0x7f,
4678 /* 846 */ 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0,
4679 /* 855 */ 0x39, 0x06,
4680 /* 857 */ 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
4681 /* 866 */ 0x39, 0x02,
4682 /* 868 */ 0xa9, 0x04,
4683 /* 870 */ 0x2d,
4684 /* 871 */ 0x29, 0x04,
4685 /* 873 */ 0x29,
4686 /* 874 */ 0x21,
4687 /* 875 */ 0x03,
4688 /* 876 */ 0x41,
4689 /* 877 */ 0x05,
4690 /* 878 */ 0x01, 0x02,
4691 /* 880 */ 0x81,
4692 /* 881 */ 0x03,
4693 /* 882 */ 0x09,
4694 /* 883 */ 0x21,
4695 /* 884 */ 0x01,
4696 /* 885 */ 0x01,
4697 /* 886 */ 0x01,
4698 /* 887 */ 0x01,
4699 /* 888 */ 0x01,
4700 /* 889 */ 0x01,
4701 /* 890 */ 0x01,
4702 /* 891 */ 0x01,
4703 /* 892 */ 0x01,
4704 /* 893 */ 0x01,
4705 /* 894 */ 0xff,
4706 /* 895 */ 0x7f,
4707 /* 896 */ 0x01,
4708 /* 897 */ 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
4709 /* 909 */ 0xff, 0xff,
4710 /* 911 */ 0xff, 0xff, 0x00, 0x00, 0x00, 0xff, 0xff,
4711 /* 918 */ 0xff, 0xff,
4712 /* 920 */ 0xff, 0xff, 0xff, 0xff,
4713 /* 924 */ 0xff, 0xff,
4714 /* 926 */ 0xff,
4715 },
4716 .SubClassMasks: {
4717 // 0 GR8
4718 0x0000003d, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4719 0x00200380, 0xc7ff2f3a, 0x72e38c3f, 0x1fdfefbd, 0x00000000, // sub_8bit
4720 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
4721 // 15 GRH8
4722 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4723 // 20 GR8_NOREX2
4724 0x0000003c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4725 0x00200300, 0xc7ff2f20, 0x72e3803f, 0x1fdfefbd, 0x00000000, // sub_8bit
4726 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
4727 // 35 GR8_NOREX
4728 0x00000038, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4729 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit
4730 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
4731 // 50 GR8_ABCD_H
4732 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4733 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
4734 // 60 GR8_ABCD_L
4735 0x00000020, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4736 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit
4737 // 70 GRH16
4738 0x00000040, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4739 // 75 GR16
4740 0x00200380, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4741 0x00000000, 0xc7ff2f3a, 0x72e38c3f, 0x1fdfefbd, 0x00000000, // sub_16bit
4742 // 85 GR16_NOREX2
4743 0x00200300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4744 0x00000000, 0xc7ff2f20, 0x72e3803f, 0x1fdfefbd, 0x00000000, // sub_16bit
4745 // 95 GR16_NOREX
4746 0x00200200, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4747 0x00000000, 0xc7ff2c00, 0x4200003f, 0x1fcfe7a8, 0x00000000, // sub_16bit
4748 // 105 VK1
4749 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
4750 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4751 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4752 // 120 VK16
4753 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
4754 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4755 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4756 // 135 VK2
4757 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
4758 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4759 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4760 // 150 VK4
4761 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
4762 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4763 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4764 // 165 VK8
4765 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
4766 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4767 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4768 // 180 VK16WM
4769 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
4770 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4771 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4772 // 195 VK1WM
4773 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
4774 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4775 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4776 // 210 VK2WM
4777 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
4778 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4779 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4780 // 225 VK4WM
4781 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
4782 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4783 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4784 // 240 VK8WM
4785 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
4786 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4787 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4788 // 255 SEGMENT_REG
4789 0x00100000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4790 // 260 GR16_ABCD
4791 0x00200000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4792 0x00000000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_16bit
4793 // 270 FPCCR
4794 0x00400000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4795 // 275 FR16X
4796 0x01800000, 0x00000084, 0x00004200, 0x00000000, 0x00000003,
4797 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
4798 // 285 FR16
4799 0x01000000, 0x00000080, 0x00004000, 0x00000000, 0x00000002,
4800 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
4801 // 295 VK16PAIR
4802 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4803 // 300 VK1PAIR
4804 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4805 // 305 VK2PAIR
4806 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4807 // 310 VK4PAIR
4808 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4809 // 315 VK8PAIR
4810 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4811 // 320 VK1PAIR_with_sub_mask_0_in_VK1WM
4812 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4813 // 325 LOW32_ADDR_ACCESS_RBP
4814 0x80000000, 0xcfff2f3b, 0x0000007f, 0x02201000, 0x00000000,
4815 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
4816 // 335 LOW32_ADDR_ACCESS
4817 0x00000000, 0xc7ff2b19, 0x0000005f, 0x00200000, 0x00000000,
4818 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
4819 // 345 LOW32_ADDR_ACCESS_RBP_with_sub_8bit
4820 0x00000000, 0xc7ff2f3a, 0x0000003f, 0x02000000, 0x00000000,
4821 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
4822 // 355 FR32X
4823 0x00000000, 0x00000084, 0x00004200, 0x00000000, 0x00000003,
4824 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
4825 // 365 GR32
4826 0x00000000, 0xc7ff2b18, 0x0000001f, 0x00000000, 0x00000000,
4827 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
4828 // 375 GR32_NOSP
4829 0x00000000, 0xc7dd2210, 0x0000001b, 0x00000000, 0x00000000,
4830 0x00000000, 0x00000000, 0x70430820, 0x1bdfaeb4, 0x00000000, // sub_32bit
4831 // 385 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
4832 0x00000000, 0xc7ff2f20, 0x0000003f, 0x02000000, 0x00000000,
4833 0x00000000, 0x00000000, 0x72e38020, 0x1fdfefbd, 0x00000000, // sub_32bit
4834 // 395 DEBUG_REG
4835 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00000000,
4836 // 400 FR32
4837 0x00000000, 0x00000080, 0x00004000, 0x00000000, 0x00000002,
4838 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
4839 // 410 GR32_NOREX2
4840 0x00000000, 0xc7ff2b00, 0x0000001f, 0x00000000, 0x00000000,
4841 0x00000000, 0x00000000, 0x72e38020, 0x1fdfefbd, 0x00000000, // sub_32bit
4842 // 420 GR32_NOREX2_NOSP
4843 0x00000000, 0xc7dd2200, 0x0000001b, 0x00000000, 0x00000000,
4844 0x00000000, 0x00000000, 0x70430020, 0x1bdfaeb4, 0x00000000, // sub_32bit
4845 // 430 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
4846 0x00000000, 0xc7ff2c00, 0x0000003f, 0x02000000, 0x00000000,
4847 0x00000000, 0x00000000, 0x42000020, 0x1fcfe7a8, 0x00000000, // sub_32bit
4848 // 440 GR32_NOREX
4849 0x00000000, 0xc7ff2800, 0x0000001f, 0x00000000, 0x00000000,
4850 0x00000000, 0x00000000, 0x42000020, 0x1fcfe7a8, 0x00000000, // sub_32bit
4851 // 450 VK32
4852 0x00000000, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
4853 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4854 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4855 // 465 GR32_NOREX_NOSP
4856 0x00000000, 0xc7dd2000, 0x0000001b, 0x00000000, 0x00000000,
4857 0x00000000, 0x00000000, 0x40000020, 0x1bcfa6a0, 0x00000000, // sub_32bit
4858 // 475 RFP32
4859 0x00000000, 0x00004000, 0x00000080, 0x40000000, 0x00000000,
4860 // 480 VK32WM
4861 0x00000000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
4862 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4863 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4864 // 495 GR32_ABCD
4865 0x00000000, 0xc19d0000, 0x00000001, 0x00000000, 0x00000000,
4866 0x00000000, 0x00000000, 0x00000000, 0x01c92680, 0x00000000, // sub_32bit
4867 // 505 GR32_TC
4868 0x00000000, 0x811e0000, 0x00000005, 0x00000000, 0x00000000,
4869 0x00000000, 0x00000000, 0x00000000, 0x05882700, 0x00000000, // sub_32bit
4870 // 515 GR32_ABCD_and_GR32_TC
4871 0x00000000, 0x811c0000, 0x00000001, 0x00000000, 0x00000000,
4872 0x00000000, 0x00000000, 0x00000000, 0x01882600, 0x00000000, // sub_32bit
4873 // 525 GR32_AD
4874 0x00000000, 0x80080000, 0x00000000, 0x00000000, 0x00000000,
4875 0x00000000, 0x00000000, 0x00000000, 0x00880400, 0x00000000, // sub_32bit
4876 // 535 GR32_ArgRef
4877 0x00000000, 0x81100000, 0x00000001, 0x00000000, 0x00000000,
4878 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000, // sub_32bit
4879 // 545 GR32_BPSP
4880 0x00000000, 0x00200000, 0x00000006, 0x00000000, 0x00000000,
4881 0x00000000, 0x00000000, 0x00000020, 0x06004000, 0x00000000, // sub_32bit
4882 // 555 GR32_BSI
4883 0x00000000, 0x40400000, 0x00000008, 0x00000000, 0x00000000,
4884 0x00000000, 0x00000000, 0x00000000, 0x08408000, 0x00000000, // sub_32bit
4885 // 565 GR32_CB
4886 0x00000000, 0x40800000, 0x00000001, 0x00000000, 0x00000000,
4887 0x00000000, 0x00000000, 0x00000000, 0x01410000, 0x00000000, // sub_32bit
4888 // 575 GR32_DC
4889 0x00000000, 0x81000000, 0x00000001, 0x00000000, 0x00000000,
4890 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000, // sub_32bit
4891 // 585 GR32_DIBP
4892 0x00000000, 0x02000000, 0x00000012, 0x00000000, 0x00000000,
4893 0x00000000, 0x00000000, 0x00000020, 0x12020000, 0x00000000, // sub_32bit
4894 // 595 GR32_SIDI
4895 0x00000000, 0x04000000, 0x00000018, 0x00000000, 0x00000000,
4896 0x00000000, 0x00000000, 0x00000000, 0x18040000, 0x00000000, // sub_32bit
4897 // 605 LOW32_ADDR_ACCESS_RBP_with_sub_32bit
4898 0x00000000, 0x08000000, 0x00000060, 0x02201000, 0x00000000,
4899 // 610 CCR
4900 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000,
4901 // 615 DFCCR
4902 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000,
4903 // 620 GR32_ABCD_and_GR32_BSI
4904 0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000,
4905 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000, // sub_32bit
4906 // 630 GR32_AD_and_GR32_ArgRef
4907 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000,
4908 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000, // sub_32bit
4909 // 640 GR32_ArgRef_and_GR32_CB
4910 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
4911 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000, // sub_32bit
4912 // 650 GR32_BPSP_and_GR32_DIBP
4913 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000,
4914 0x00000000, 0x00000000, 0x00000020, 0x02000000, 0x00000000, // sub_32bit
4915 // 660 GR32_BPSP_and_GR32_TC
4916 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000,
4917 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000, // sub_32bit
4918 // 670 GR32_BSI_and_GR32_SIDI
4919 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000,
4920 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000, // sub_32bit
4921 // 680 GR32_DIBP_and_GR32_SIDI
4922 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000,
4923 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000, // sub_32bit
4924 // 690 LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
4925 0x00000000, 0x00000000, 0x00000020, 0x02000000, 0x00000000,
4926 // 695 LOW32_ADDR_ACCESS_with_sub_32bit
4927 0x00000000, 0x00000000, 0x00000040, 0x00200000, 0x00000000,
4928 // 700 RFP64
4929 0x00000000, 0x00000000, 0x00000080, 0x40000000, 0x00000000,
4930 // 705 GR64
4931 0x00000000, 0x00000000, 0xf3ff9d00, 0x1ffffffd, 0x00000000,
4932 // 710 FR64X
4933 0x00000000, 0x00000000, 0x00004200, 0x00000000, 0x00000003,
4934 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
4935 // 720 GR64_with_sub_8bit
4936 0x00000000, 0x00000000, 0x72e38c00, 0x1fdfefbd, 0x00000000,
4937 // 725 GR64_NOSP
4938 0x00000000, 0x00000000, 0x70430800, 0x1bdfaeb4, 0x00000000,
4939 // 730 GR64_NOREX2
4940 0x00000000, 0x00000000, 0xf3ff9000, 0x1ffffffd, 0x00000000,
4941 // 735 CONTROL_REG
4942 0x00000000, 0x00000000, 0x00002000, 0x00000000, 0x00000000,
4943 // 740 FR64
4944 0x00000000, 0x00000000, 0x00004000, 0x00000000, 0x00000002,
4945 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
4946 // 750 GR64_with_sub_16bit_in_GR16_NOREX2
4947 0x00000000, 0x00000000, 0x72e38000, 0x1fdfefbd, 0x00000000,
4948 // 755 GR64_NOREX2_NOSP
4949 0x00000000, 0x00000000, 0x70430000, 0x1bdfaeb4, 0x00000000,
4950 // 760 GR64PLTSafe
4951 0x00000000, 0x00000000, 0x50020000, 0x1bcfa6b0, 0x00000000,
4952 // 765 GR64_TC
4953 0x00000000, 0x00000000, 0x91640000, 0x1dbc277d, 0x00000000,
4954 // 770 GR64_NOREX
4955 0x00000000, 0x00000000, 0xc2080000, 0x1feff7e8, 0x00000000,
4956 // 775 GR64_TCW64
4957 0x00000000, 0x00000000, 0x21900000, 0x05b82f55, 0x00000000,
4958 // 780 GR64_TC_with_sub_8bit
4959 0x00000000, 0x00000000, 0x10600000, 0x1d9c273d, 0x00000000,
4960 // 785 GR64_NOREX2_NOSP_and_GR64_TC
4961 0x00000000, 0x00000000, 0x10400000, 0x199c2634, 0x00000000,
4962 // 790 GR64_TCW64_with_sub_8bit
4963 0x00000000, 0x00000000, 0x20800000, 0x05982f15, 0x00000000,
4964 // 795 GR64_TC_and_GR64_TCW64
4965 0x00000000, 0x00000000, 0x01000000, 0x05b82755, 0x00000000,
4966 // 800 GR64_with_sub_16bit_in_GR16_NOREX
4967 0x00000000, 0x00000000, 0x42000000, 0x1fcfe7a8, 0x00000000,
4968 // 805 VK64
4969 0x00000000, 0x00000000, 0x04000000, 0x00000002, 0x00000000,
4970 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4971 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4972 // 820 VR64
4973 0x00000000, 0x00000000, 0x08000000, 0x00000000, 0x00000000,
4974 // 825 GR64PLTSafe_and_GR64_TC
4975 0x00000000, 0x00000000, 0x10000000, 0x198c2630, 0x00000000,
4976 // 830 GR64_NOREX2_NOSP_and_GR64_TCW64
4977 0x00000000, 0x00000000, 0x20000000, 0x01982e14, 0x00000000,
4978 // 835 GR64_NOREX_NOSP
4979 0x00000000, 0x00000000, 0x40000000, 0x1bcfa6a0, 0x00000000,
4980 // 840 GR64_NOREX_and_GR64_TC
4981 0x00000000, 0x00000000, 0x80000000, 0x1dac2768, 0x00000000,
4982 // 845 GR64_TCW64_and_GR64_TC_with_sub_8bit
4983 0x00000000, 0x00000000, 0x00000000, 0x05982715, 0x00000000,
4984 // 850 VK64WM
4985 0x00000000, 0x00000000, 0x00000000, 0x00000002, 0x00000000,
4986 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4987 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4988 // 865 GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
4989 0x00000000, 0x00000000, 0x00000000, 0x01982614, 0x00000000,
4990 // 870 GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
4991 0x00000000, 0x00000000, 0x00000000, 0x1d8c2728, 0x00000000,
4992 // 875 GR64PLTSafe_and_GR64_TCW64
4993 0x00000000, 0x00000000, 0x00000000, 0x01882610, 0x00000000,
4994 // 880 GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
4995 0x00000000, 0x00000000, 0x00000000, 0x198c2620, 0x00000000,
4996 // 885 GR64_NOREX_and_GR64_TCW64
4997 0x00000000, 0x00000000, 0x00000000, 0x05a82740, 0x00000000,
4998 // 890 GR64_ABCD
4999 0x00000000, 0x00000000, 0x00000000, 0x01c92680, 0x00000000,
5000 // 895 GR64_with_sub_32bit_in_GR32_TC
5001 0x00000000, 0x00000000, 0x00000000, 0x05882700, 0x00000000,
5002 // 900 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5003 0x00000000, 0x00000000, 0x00000000, 0x01882600, 0x00000000,
5004 // 905 GR64_AD
5005 0x00000000, 0x00000000, 0x00000000, 0x00880400, 0x00000000,
5006 // 910 GR64_ArgRef
5007 0x00000000, 0x00000000, 0x00000000, 0x00100800, 0x00000000,
5008 // 915 GR64_and_LOW32_ADDR_ACCESS_RBP
5009 0x00000000, 0x00000000, 0x00000000, 0x02201000, 0x00000000,
5010 // 920 GR64_with_sub_32bit_in_GR32_ArgRef
5011 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000,
5012 // 925 GR64_with_sub_32bit_in_GR32_BPSP
5013 0x00000000, 0x00000000, 0x00000000, 0x06004000, 0x00000000,
5014 // 930 GR64_with_sub_32bit_in_GR32_BSI
5015 0x00000000, 0x00000000, 0x00000000, 0x08408000, 0x00000000,
5016 // 935 GR64_with_sub_32bit_in_GR32_CB
5017 0x00000000, 0x00000000, 0x00000000, 0x01410000, 0x00000000,
5018 // 940 GR64_with_sub_32bit_in_GR32_DIBP
5019 0x00000000, 0x00000000, 0x00000000, 0x12020000, 0x00000000,
5020 // 945 GR64_with_sub_32bit_in_GR32_SIDI
5021 0x00000000, 0x00000000, 0x00000000, 0x18040000, 0x00000000,
5022 // 950 GR64_A
5023 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000,
5024 // 955 GR64_ArgRef_and_GR64_TC
5025 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00000000,
5026 // 960 GR64_and_LOW32_ADDR_ACCESS
5027 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00000000,
5028 // 965 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
5029 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000,
5030 // 970 GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
5031 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000,
5032 // 975 GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
5033 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000,
5034 // 980 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
5035 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x00000000,
5036 // 985 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
5037 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000,
5038 // 990 GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
5039 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000,
5040 // 995 GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
5041 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000,
5042 // 1000 RST
5043 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000,
5044 // 1005 RFP80
5045 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00000000,
5046 // 1010 RFP80_7
5047 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000000,
5048 // 1015 VR128X
5049 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000003,
5050 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
5051 // 1025 VR128
5052 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002,
5053 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
5054 // 1035 VR256X
5055 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c,
5056 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000030, // sub_ymm
5057 // 1045 VR256
5058 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008,
5059 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_ymm
5060 // 1055 VR512
5061 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000030,
5062 // 1060 VR512_0_15
5063 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020,
5064 // 1065 TILE
5065 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040,
5066 },
5067 .SuperRegIdxSeqs: {
5068 /* 0 */ 1, 0,
5069 /* 2 */ 1, 2, 0,
5070 /* 5 */ 4, 0,
5071 /* 7 */ 6, 0,
5072 /* 9 */ 7, 8, 0,
5073 /* 12 */ 9, 0,
5074 /* 14 */ 10, 0,
5075 },
5076 .SuperClasses: {
5077 /* 0 GR8 */
5078 /* 0 GRH8 */
5079 /* 0 GR8_NOREX2 */ X86::GR8RegClassID,
5080 /* 1 GR8_NOREX */ X86::GR8RegClassID, X86::GR8_NOREX2RegClassID,
5081 /* 3 GR8_ABCD_H */ X86::GR8RegClassID, X86::GR8_NOREX2RegClassID, X86::GR8_NOREXRegClassID,
5082 /* 6 GR8_ABCD_L */ X86::GR8RegClassID, X86::GR8_NOREX2RegClassID, X86::GR8_NOREXRegClassID,
5083 /* 9 GRH16 */
5084 /* 9 GR16 */
5085 /* 9 GR16_NOREX2 */ X86::GR16RegClassID,
5086 /* 10 GR16_NOREX */ X86::GR16RegClassID, X86::GR16_NOREX2RegClassID,
5087 /* 12 VK1 */ X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID,
5088 /* 16 VK16 */ X86::VK1RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID,
5089 /* 20 VK2 */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK4RegClassID, X86::VK8RegClassID,
5090 /* 24 VK4 */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK8RegClassID,
5091 /* 28 VK8 */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID,
5092 /* 32 VK16WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK1WMRegClassID, X86::VK2WMRegClassID, X86::VK4WMRegClassID, X86::VK8WMRegClassID,
5093 /* 41 VK1WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK16WMRegClassID, X86::VK2WMRegClassID, X86::VK4WMRegClassID, X86::VK8WMRegClassID,
5094 /* 50 VK2WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK16WMRegClassID, X86::VK1WMRegClassID, X86::VK4WMRegClassID, X86::VK8WMRegClassID,
5095 /* 59 VK4WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK16WMRegClassID, X86::VK1WMRegClassID, X86::VK2WMRegClassID, X86::VK8WMRegClassID,
5096 /* 68 VK8WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK16WMRegClassID, X86::VK1WMRegClassID, X86::VK2WMRegClassID, X86::VK4WMRegClassID,
5097 /* 77 SEGMENT_REG */
5098 /* 77 GR16_ABCD */ X86::GR16RegClassID, X86::GR16_NOREX2RegClassID, X86::GR16_NOREXRegClassID,
5099 /* 80 FPCCR */
5100 /* 80 FR16X */
5101 /* 80 FR16 */ X86::FR16XRegClassID,
5102 /* 81 VK16PAIR */ X86::VK1PAIRRegClassID, X86::VK2PAIRRegClassID, X86::VK4PAIRRegClassID, X86::VK8PAIRRegClassID,
5103 /* 85 VK1PAIR */ X86::VK16PAIRRegClassID, X86::VK2PAIRRegClassID, X86::VK4PAIRRegClassID, X86::VK8PAIRRegClassID,
5104 /* 89 VK2PAIR */ X86::VK16PAIRRegClassID, X86::VK1PAIRRegClassID, X86::VK4PAIRRegClassID, X86::VK8PAIRRegClassID,
5105 /* 93 VK4PAIR */ X86::VK16PAIRRegClassID, X86::VK1PAIRRegClassID, X86::VK2PAIRRegClassID, X86::VK8PAIRRegClassID,
5106 /* 97 VK8PAIR */ X86::VK16PAIRRegClassID, X86::VK1PAIRRegClassID, X86::VK2PAIRRegClassID, X86::VK4PAIRRegClassID,
5107 /* 101 VK1PAIR_with_sub_mask_0_in_VK1WM */ X86::VK16PAIRRegClassID, X86::VK1PAIRRegClassID, X86::VK2PAIRRegClassID, X86::VK4PAIRRegClassID, X86::VK8PAIRRegClassID,
5108 /* 106 LOW32_ADDR_ACCESS_RBP */
5109 /* 106 LOW32_ADDR_ACCESS */ X86::LOW32_ADDR_ACCESS_RBPRegClassID,
5110 /* 107 LOW32_ADDR_ACCESS_RBP_with_sub_8bit */ X86::LOW32_ADDR_ACCESS_RBPRegClassID,
5111 /* 108 FR32X */ X86::FR16XRegClassID,
5112 /* 109 GR32 */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
5113 /* 112 GR32_NOSP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID,
5114 /* 116 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
5115 /* 118 DEBUG_REG */
5116 /* 118 FR32 */ X86::FR16XRegClassID, X86::FR16RegClassID, X86::FR32XRegClassID,
5117 /* 121 GR32_NOREX2 */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
5118 /* 126 GR32_NOREX2_NOSP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID,
5119 /* 133 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
5120 /* 136 GR32_NOREX */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
5121 /* 143 VK32 */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID,
5122 /* 148 GR32_NOREX_NOSP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID,
5123 /* 158 RFP32 */
5124 /* 158 VK32WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK16WMRegClassID, X86::VK1WMRegClassID, X86::VK2WMRegClassID, X86::VK4WMRegClassID, X86::VK8WMRegClassID, X86::VK32RegClassID,
5125 /* 169 GR32_ABCD */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID,
5126 /* 180 GR32_TC */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID,
5127 /* 188 GR32_ABCD_and_GR32_TC */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_TCRegClassID,
5128 /* 201 GR32_AD */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_TCRegClassID, X86::GR32_ABCD_and_GR32_TCRegClassID,
5129 /* 215 GR32_ArgRef */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_TCRegClassID, X86::GR32_ABCD_and_GR32_TCRegClassID,
5130 /* 229 GR32_BPSP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID,
5131 /* 237 GR32_BSI */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID,
5132 /* 248 GR32_CB */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID,
5133 /* 260 GR32_DC */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_TCRegClassID, X86::GR32_ABCD_and_GR32_TCRegClassID, X86::GR32_ArgRefRegClassID,
5134 /* 275 GR32_DIBP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID,
5135 /* 286 GR32_SIDI */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID,
5136 /* 297 LOW32_ADDR_ACCESS_RBP_with_sub_32bit */ X86::LOW32_ADDR_ACCESS_RBPRegClassID,
5137 /* 298 CCR */
5138 /* 298 DFCCR */
5139 /* 298 GR32_ABCD_and_GR32_BSI */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_BSIRegClassID, X86::GR32_CBRegClassID,
5140 /* 312 GR32_AD_and_GR32_ArgRef */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_TCRegClassID, X86::GR32_ABCD_and_GR32_TCRegClassID, X86::GR32_ADRegClassID, X86::GR32_ArgRefRegClassID, X86::GR32_DCRegClassID,
5141 /* 329 GR32_ArgRef_and_GR32_CB */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_ABCDRegClassID, X86::GR32_TCRegClassID, X86::GR32_ABCD_and_GR32_TCRegClassID, X86::GR32_ArgRefRegClassID, X86::GR32_CBRegClassID, X86::GR32_DCRegClassID,
5142 /* 346 GR32_BPSP_and_GR32_DIBP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_BPSPRegClassID, X86::GR32_DIBPRegClassID,
5143 /* 359 GR32_BPSP_and_GR32_TC */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_TCRegClassID, X86::GR32_BPSPRegClassID,
5144 /* 369 GR32_BSI_and_GR32_SIDI */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_BSIRegClassID, X86::GR32_SIDIRegClassID,
5145 /* 382 GR32_DIBP_and_GR32_SIDI */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::GR32RegClassID, X86::GR32_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR32_NOREX2RegClassID, X86::GR32_NOREX2_NOSPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR32_NOREXRegClassID, X86::GR32_NOREX_NOSPRegClassID, X86::GR32_DIBPRegClassID, X86::GR32_SIDIRegClassID,
5146 /* 395 LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
5147 /* 400 LOW32_ADDR_ACCESS_with_sub_32bit */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
5148 /* 403 RFP64 */ X86::RFP32RegClassID,
5149 /* 404 GR64 */
5150 /* 404 FR64X */ X86::FR16XRegClassID, X86::FR32XRegClassID,
5151 /* 406 GR64_with_sub_8bit */ X86::GR64RegClassID,
5152 /* 407 GR64_NOSP */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID,
5153 /* 409 GR64_NOREX2 */ X86::GR64RegClassID,
5154 /* 410 CONTROL_REG */
5155 /* 410 FR64 */ X86::FR16XRegClassID, X86::FR16RegClassID, X86::FR32XRegClassID, X86::FR32RegClassID, X86::FR64XRegClassID,
5156 /* 415 GR64_with_sub_16bit_in_GR16_NOREX2 */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID,
5157 /* 418 GR64_NOREX2_NOSP */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
5158 /* 423 GR64PLTSafe */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID,
5159 /* 429 GR64_TC */ X86::GR64RegClassID, X86::GR64_NOREX2RegClassID,
5160 /* 431 GR64_NOREX */ X86::GR64RegClassID, X86::GR64_NOREX2RegClassID,
5161 /* 433 GR64_TCW64 */ X86::GR64RegClassID, X86::GR64_NOREX2RegClassID,
5162 /* 435 GR64_TC_with_sub_8bit */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_TCRegClassID,
5163 /* 440 GR64_NOREX2_NOSP_and_GR64_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64_TCRegClassID, X86::GR64_TC_with_sub_8bitRegClassID,
5164 /* 448 GR64_TCW64_with_sub_8bit */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_TCW64RegClassID,
5165 /* 453 GR64_TC_and_GR64_TCW64 */ X86::GR64RegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_TCW64RegClassID,
5166 /* 457 GR64_with_sub_16bit_in_GR16_NOREX */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREXRegClassID,
5167 /* 462 VK64 */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK32RegClassID,
5168 /* 468 VR64 */
5169 /* 468 GR64PLTSafe_and_GR64_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
5170 /* 478 GR64_NOREX2_NOSP_and_GR64_TCW64 */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID,
5171 /* 486 GR64_NOREX_NOSP */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
5172 /* 495 GR64_NOREX_and_GR64_TC */ X86::GR64RegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID,
5173 /* 499 GR64_TCW64_and_GR64_TC_with_sub_8bit */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID,
5174 /* 508 VK64WM */ X86::VK1RegClassID, X86::VK16RegClassID, X86::VK2RegClassID, X86::VK4RegClassID, X86::VK8RegClassID, X86::VK16WMRegClassID, X86::VK1WMRegClassID, X86::VK2WMRegClassID, X86::VK4WMRegClassID, X86::VK8WMRegClassID, X86::VK32RegClassID, X86::VK32WMRegClassID, X86::VK64RegClassID,
5175 /* 521 GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64_TCRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
5176 /* 535 GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID,
5177 /* 544 GR64PLTSafe_and_GR64_TCW64 */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
5178 /* 561 GR64_NOREX_and_GR64PLTSafe_and_GR64_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
5179 /* 577 GR64_NOREX_and_GR64_TCW64 */ X86::GR64RegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID,
5180 /* 584 GR64_ABCD */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_NOSPRegClassID,
5181 /* 594 GR64_with_sub_32bit_in_GR32_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID,
5182 /* 609 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
5183 /* 636 GR64_AD */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
5184 /* 664 GR64_ArgRef */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
5185 /* 673 GR64_and_LOW32_ADDR_ACCESS_RBP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, X86::GR64RegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_NOREXRegClassID,
5186 /* 678 GR64_with_sub_32bit_in_GR32_ArgRef */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
5187 /* 706 GR64_with_sub_32bit_in_GR32_BPSP */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
5188 /* 712 GR64_with_sub_32bit_in_GR32_BSI */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_NOSPRegClassID,
5189 /* 722 GR64_with_sub_32bit_in_GR32_CB */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_ABCDRegClassID,
5190 /* 733 GR64_with_sub_32bit_in_GR32_DIBP */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_NOSPRegClassID,
5191 /* 743 GR64_with_sub_32bit_in_GR32_SIDI */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
5192 /* 760 GR64_A */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, X86::GR64_ADRegClassID,
5193 /* 789 GR64_ArgRef_and_GR64_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64_TCRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_ArgRefRegClassID,
5194 /* 805 GR64_and_LOW32_ADDR_ACCESS */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESSRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, X86::GR64RegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
5195 /* 818 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
5196 /* 831 GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, X86::GR64_ADRegClassID, X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
5197 /* 861 GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCW64RegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_ABCDRegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID, X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
5198 /* 891 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP */ X86::LOW32_ADDR_ACCESS_RBPRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
5199 /* 910 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TCW64RegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_TCW64_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_TCW64RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64_TCW64RegClassID, X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
5200 /* 927 GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
5201 /* 946 GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI */ X86::GR64RegClassID, X86::GR64_with_sub_8bitRegClassID, X86::GR64_NOSPRegClassID, X86::GR64_NOREX2RegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, X86::GR64_NOREX2_NOSPRegClassID, X86::GR64PLTSafeRegClassID, X86::GR64_TCRegClassID, X86::GR64_NOREXRegClassID, X86::GR64_TC_with_sub_8bitRegClassID, X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_NOREX_NOSPRegClassID, X86::GR64_NOREX_and_GR64_TCRegClassID, X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
5202 /* 965 RST */
5203 /* 965 RFP80 */ X86::RFP32RegClassID, X86::RFP64RegClassID,
5204 /* 967 RFP80_7 */
5205 /* 967 VR128X */ X86::FR16XRegClassID, X86::FR32XRegClassID, X86::FR64XRegClassID,
5206 /* 970 VR128 */ X86::FR16XRegClassID, X86::FR16RegClassID, X86::FR32XRegClassID, X86::FR32RegClassID, X86::FR64XRegClassID, X86::FR64RegClassID, X86::VR128XRegClassID,
5207 /* 977 VR256X */
5208 /* 977 VR256 */ X86::VR256XRegClassID,
5209 /* 978 VR512 */
5210 /* 978 VR512_0_15 */ X86::VR512RegClassID,
5211 /* 979 TILE */
5212 }
5213};
5214
5215const MCRegisterClass &getX86MCRegisterClass(unsigned RC) {
5216 return X86MCRegisterClassStorage.Classes[RC];
5217}
5218
5219// X86 Dwarf<->LLVM register mappings.
5220extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
5221 { .FromReg: 0U, .ToReg: X86::RAX },
5222 { .FromReg: 1U, .ToReg: X86::RDX },
5223 { .FromReg: 2U, .ToReg: X86::RCX },
5224 { .FromReg: 3U, .ToReg: X86::RBX },
5225 { .FromReg: 4U, .ToReg: X86::RSI },
5226 { .FromReg: 5U, .ToReg: X86::RDI },
5227 { .FromReg: 6U, .ToReg: X86::RBP },
5228 { .FromReg: 7U, .ToReg: X86::RSP },
5229 { .FromReg: 8U, .ToReg: X86::R8 },
5230 { .FromReg: 9U, .ToReg: X86::R9 },
5231 { .FromReg: 10U, .ToReg: X86::R10 },
5232 { .FromReg: 11U, .ToReg: X86::R11 },
5233 { .FromReg: 12U, .ToReg: X86::R12 },
5234 { .FromReg: 13U, .ToReg: X86::R13 },
5235 { .FromReg: 14U, .ToReg: X86::R14 },
5236 { .FromReg: 15U, .ToReg: X86::R15 },
5237 { .FromReg: 16U, .ToReg: X86::RIP },
5238 { .FromReg: 17U, .ToReg: X86::XMM0 },
5239 { .FromReg: 18U, .ToReg: X86::XMM1 },
5240 { .FromReg: 19U, .ToReg: X86::XMM2 },
5241 { .FromReg: 20U, .ToReg: X86::XMM3 },
5242 { .FromReg: 21U, .ToReg: X86::XMM4 },
5243 { .FromReg: 22U, .ToReg: X86::XMM5 },
5244 { .FromReg: 23U, .ToReg: X86::XMM6 },
5245 { .FromReg: 24U, .ToReg: X86::XMM7 },
5246 { .FromReg: 25U, .ToReg: X86::XMM8 },
5247 { .FromReg: 26U, .ToReg: X86::XMM9 },
5248 { .FromReg: 27U, .ToReg: X86::XMM10 },
5249 { .FromReg: 28U, .ToReg: X86::XMM11 },
5250 { .FromReg: 29U, .ToReg: X86::XMM12 },
5251 { .FromReg: 30U, .ToReg: X86::XMM13 },
5252 { .FromReg: 31U, .ToReg: X86::XMM14 },
5253 { .FromReg: 32U, .ToReg: X86::XMM15 },
5254 { .FromReg: 33U, .ToReg: X86::ST0 },
5255 { .FromReg: 34U, .ToReg: X86::ST1 },
5256 { .FromReg: 35U, .ToReg: X86::ST2 },
5257 { .FromReg: 36U, .ToReg: X86::ST3 },
5258 { .FromReg: 37U, .ToReg: X86::ST4 },
5259 { .FromReg: 38U, .ToReg: X86::ST5 },
5260 { .FromReg: 39U, .ToReg: X86::ST6 },
5261 { .FromReg: 40U, .ToReg: X86::ST7 },
5262 { .FromReg: 41U, .ToReg: X86::MM0 },
5263 { .FromReg: 42U, .ToReg: X86::MM1 },
5264 { .FromReg: 43U, .ToReg: X86::MM2 },
5265 { .FromReg: 44U, .ToReg: X86::MM3 },
5266 { .FromReg: 45U, .ToReg: X86::MM4 },
5267 { .FromReg: 46U, .ToReg: X86::MM5 },
5268 { .FromReg: 47U, .ToReg: X86::MM6 },
5269 { .FromReg: 48U, .ToReg: X86::MM7 },
5270 { .FromReg: 49U, .ToReg: X86::RFLAGS },
5271 { .FromReg: 50U, .ToReg: X86::ES },
5272 { .FromReg: 51U, .ToReg: X86::CS },
5273 { .FromReg: 52U, .ToReg: X86::SS },
5274 { .FromReg: 53U, .ToReg: X86::DS },
5275 { .FromReg: 54U, .ToReg: X86::FS },
5276 { .FromReg: 55U, .ToReg: X86::GS },
5277 { .FromReg: 58U, .ToReg: X86::FS_BASE },
5278 { .FromReg: 59U, .ToReg: X86::GS_BASE },
5279 { .FromReg: 67U, .ToReg: X86::XMM16 },
5280 { .FromReg: 68U, .ToReg: X86::XMM17 },
5281 { .FromReg: 69U, .ToReg: X86::XMM18 },
5282 { .FromReg: 70U, .ToReg: X86::XMM19 },
5283 { .FromReg: 71U, .ToReg: X86::XMM20 },
5284 { .FromReg: 72U, .ToReg: X86::XMM21 },
5285 { .FromReg: 73U, .ToReg: X86::XMM22 },
5286 { .FromReg: 74U, .ToReg: X86::XMM23 },
5287 { .FromReg: 75U, .ToReg: X86::XMM24 },
5288 { .FromReg: 76U, .ToReg: X86::XMM25 },
5289 { .FromReg: 77U, .ToReg: X86::XMM26 },
5290 { .FromReg: 78U, .ToReg: X86::XMM27 },
5291 { .FromReg: 79U, .ToReg: X86::XMM28 },
5292 { .FromReg: 80U, .ToReg: X86::XMM29 },
5293 { .FromReg: 81U, .ToReg: X86::XMM30 },
5294 { .FromReg: 82U, .ToReg: X86::XMM31 },
5295 { .FromReg: 118U, .ToReg: X86::K0 },
5296 { .FromReg: 119U, .ToReg: X86::K1 },
5297 { .FromReg: 120U, .ToReg: X86::K2 },
5298 { .FromReg: 121U, .ToReg: X86::K3 },
5299 { .FromReg: 122U, .ToReg: X86::K4 },
5300 { .FromReg: 123U, .ToReg: X86::K5 },
5301 { .FromReg: 124U, .ToReg: X86::K6 },
5302 { .FromReg: 125U, .ToReg: X86::K7 },
5303 { .FromReg: 130U, .ToReg: X86::R16 },
5304 { .FromReg: 131U, .ToReg: X86::R17 },
5305 { .FromReg: 132U, .ToReg: X86::R18 },
5306 { .FromReg: 133U, .ToReg: X86::R19 },
5307 { .FromReg: 134U, .ToReg: X86::R20 },
5308 { .FromReg: 135U, .ToReg: X86::R21 },
5309 { .FromReg: 136U, .ToReg: X86::R22 },
5310 { .FromReg: 137U, .ToReg: X86::R23 },
5311 { .FromReg: 138U, .ToReg: X86::R24 },
5312 { .FromReg: 139U, .ToReg: X86::R25 },
5313 { .FromReg: 140U, .ToReg: X86::R26 },
5314 { .FromReg: 141U, .ToReg: X86::R27 },
5315 { .FromReg: 142U, .ToReg: X86::R28 },
5316 { .FromReg: 143U, .ToReg: X86::R29 },
5317 { .FromReg: 144U, .ToReg: X86::R30 },
5318 { .FromReg: 145U, .ToReg: X86::R31 },
5319};
5320extern const unsigned X86DwarfFlavour0Dwarf2LSize = std::size(X86DwarfFlavour0Dwarf2L);
5321
5322extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
5323 { .FromReg: 0U, .ToReg: X86::EAX },
5324 { .FromReg: 1U, .ToReg: X86::ECX },
5325 { .FromReg: 2U, .ToReg: X86::EDX },
5326 { .FromReg: 3U, .ToReg: X86::EBX },
5327 { .FromReg: 4U, .ToReg: X86::EBP },
5328 { .FromReg: 5U, .ToReg: X86::ESP },
5329 { .FromReg: 6U, .ToReg: X86::ESI },
5330 { .FromReg: 7U, .ToReg: X86::EDI },
5331 { .FromReg: 8U, .ToReg: X86::EIP },
5332 { .FromReg: 9U, .ToReg: X86::EFLAGS },
5333 { .FromReg: 12U, .ToReg: X86::ST0 },
5334 { .FromReg: 13U, .ToReg: X86::ST1 },
5335 { .FromReg: 14U, .ToReg: X86::ST2 },
5336 { .FromReg: 15U, .ToReg: X86::ST3 },
5337 { .FromReg: 16U, .ToReg: X86::ST4 },
5338 { .FromReg: 17U, .ToReg: X86::ST5 },
5339 { .FromReg: 18U, .ToReg: X86::ST6 },
5340 { .FromReg: 19U, .ToReg: X86::ST7 },
5341 { .FromReg: 21U, .ToReg: X86::XMM0 },
5342 { .FromReg: 22U, .ToReg: X86::XMM1 },
5343 { .FromReg: 23U, .ToReg: X86::XMM2 },
5344 { .FromReg: 24U, .ToReg: X86::XMM3 },
5345 { .FromReg: 25U, .ToReg: X86::XMM4 },
5346 { .FromReg: 26U, .ToReg: X86::XMM5 },
5347 { .FromReg: 27U, .ToReg: X86::XMM6 },
5348 { .FromReg: 28U, .ToReg: X86::XMM7 },
5349 { .FromReg: 29U, .ToReg: X86::MM0 },
5350 { .FromReg: 30U, .ToReg: X86::MM1 },
5351 { .FromReg: 31U, .ToReg: X86::MM2 },
5352 { .FromReg: 32U, .ToReg: X86::MM3 },
5353 { .FromReg: 33U, .ToReg: X86::MM4 },
5354 { .FromReg: 34U, .ToReg: X86::MM5 },
5355 { .FromReg: 35U, .ToReg: X86::MM6 },
5356 { .FromReg: 36U, .ToReg: X86::MM7 },
5357 { .FromReg: 93U, .ToReg: X86::K0 },
5358 { .FromReg: 94U, .ToReg: X86::K1 },
5359 { .FromReg: 95U, .ToReg: X86::K2 },
5360 { .FromReg: 96U, .ToReg: X86::K3 },
5361 { .FromReg: 97U, .ToReg: X86::K4 },
5362 { .FromReg: 98U, .ToReg: X86::K5 },
5363 { .FromReg: 99U, .ToReg: X86::K6 },
5364 { .FromReg: 100U, .ToReg: X86::K7 },
5365};
5366extern const unsigned X86DwarfFlavour1Dwarf2LSize = std::size(X86DwarfFlavour1Dwarf2L);
5367
5368extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
5369 { .FromReg: 0U, .ToReg: X86::EAX },
5370 { .FromReg: 1U, .ToReg: X86::ECX },
5371 { .FromReg: 2U, .ToReg: X86::EDX },
5372 { .FromReg: 3U, .ToReg: X86::EBX },
5373 { .FromReg: 4U, .ToReg: X86::ESP },
5374 { .FromReg: 5U, .ToReg: X86::EBP },
5375 { .FromReg: 6U, .ToReg: X86::ESI },
5376 { .FromReg: 7U, .ToReg: X86::EDI },
5377 { .FromReg: 8U, .ToReg: X86::EIP },
5378 { .FromReg: 9U, .ToReg: X86::EFLAGS },
5379 { .FromReg: 11U, .ToReg: X86::ST0 },
5380 { .FromReg: 12U, .ToReg: X86::ST1 },
5381 { .FromReg: 13U, .ToReg: X86::ST2 },
5382 { .FromReg: 14U, .ToReg: X86::ST3 },
5383 { .FromReg: 15U, .ToReg: X86::ST4 },
5384 { .FromReg: 16U, .ToReg: X86::ST5 },
5385 { .FromReg: 17U, .ToReg: X86::ST6 },
5386 { .FromReg: 18U, .ToReg: X86::ST7 },
5387 { .FromReg: 21U, .ToReg: X86::XMM0 },
5388 { .FromReg: 22U, .ToReg: X86::XMM1 },
5389 { .FromReg: 23U, .ToReg: X86::XMM2 },
5390 { .FromReg: 24U, .ToReg: X86::XMM3 },
5391 { .FromReg: 25U, .ToReg: X86::XMM4 },
5392 { .FromReg: 26U, .ToReg: X86::XMM5 },
5393 { .FromReg: 27U, .ToReg: X86::XMM6 },
5394 { .FromReg: 28U, .ToReg: X86::XMM7 },
5395 { .FromReg: 29U, .ToReg: X86::MM0 },
5396 { .FromReg: 30U, .ToReg: X86::MM1 },
5397 { .FromReg: 31U, .ToReg: X86::MM2 },
5398 { .FromReg: 32U, .ToReg: X86::MM3 },
5399 { .FromReg: 33U, .ToReg: X86::MM4 },
5400 { .FromReg: 34U, .ToReg: X86::MM5 },
5401 { .FromReg: 35U, .ToReg: X86::MM6 },
5402 { .FromReg: 36U, .ToReg: X86::MM7 },
5403 { .FromReg: 40U, .ToReg: X86::ES },
5404 { .FromReg: 41U, .ToReg: X86::CS },
5405 { .FromReg: 42U, .ToReg: X86::SS },
5406 { .FromReg: 43U, .ToReg: X86::DS },
5407 { .FromReg: 44U, .ToReg: X86::FS },
5408 { .FromReg: 45U, .ToReg: X86::GS },
5409 { .FromReg: 93U, .ToReg: X86::K0 },
5410 { .FromReg: 94U, .ToReg: X86::K1 },
5411 { .FromReg: 95U, .ToReg: X86::K2 },
5412 { .FromReg: 96U, .ToReg: X86::K3 },
5413 { .FromReg: 97U, .ToReg: X86::K4 },
5414 { .FromReg: 98U, .ToReg: X86::K5 },
5415 { .FromReg: 99U, .ToReg: X86::K6 },
5416 { .FromReg: 100U, .ToReg: X86::K7 },
5417};
5418extern const unsigned X86DwarfFlavour2Dwarf2LSize = std::size(X86DwarfFlavour2Dwarf2L);
5419
5420extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
5421 { .FromReg: 0U, .ToReg: X86::RAX },
5422 { .FromReg: 1U, .ToReg: X86::RDX },
5423 { .FromReg: 2U, .ToReg: X86::RCX },
5424 { .FromReg: 3U, .ToReg: X86::RBX },
5425 { .FromReg: 4U, .ToReg: X86::RSI },
5426 { .FromReg: 5U, .ToReg: X86::RDI },
5427 { .FromReg: 6U, .ToReg: X86::RBP },
5428 { .FromReg: 7U, .ToReg: X86::RSP },
5429 { .FromReg: 8U, .ToReg: X86::R8 },
5430 { .FromReg: 9U, .ToReg: X86::R9 },
5431 { .FromReg: 10U, .ToReg: X86::R10 },
5432 { .FromReg: 11U, .ToReg: X86::R11 },
5433 { .FromReg: 12U, .ToReg: X86::R12 },
5434 { .FromReg: 13U, .ToReg: X86::R13 },
5435 { .FromReg: 14U, .ToReg: X86::R14 },
5436 { .FromReg: 15U, .ToReg: X86::R15 },
5437 { .FromReg: 16U, .ToReg: X86::RIP },
5438 { .FromReg: 17U, .ToReg: X86::XMM0 },
5439 { .FromReg: 18U, .ToReg: X86::XMM1 },
5440 { .FromReg: 19U, .ToReg: X86::XMM2 },
5441 { .FromReg: 20U, .ToReg: X86::XMM3 },
5442 { .FromReg: 21U, .ToReg: X86::XMM4 },
5443 { .FromReg: 22U, .ToReg: X86::XMM5 },
5444 { .FromReg: 23U, .ToReg: X86::XMM6 },
5445 { .FromReg: 24U, .ToReg: X86::XMM7 },
5446 { .FromReg: 25U, .ToReg: X86::XMM8 },
5447 { .FromReg: 26U, .ToReg: X86::XMM9 },
5448 { .FromReg: 27U, .ToReg: X86::XMM10 },
5449 { .FromReg: 28U, .ToReg: X86::XMM11 },
5450 { .FromReg: 29U, .ToReg: X86::XMM12 },
5451 { .FromReg: 30U, .ToReg: X86::XMM13 },
5452 { .FromReg: 31U, .ToReg: X86::XMM14 },
5453 { .FromReg: 32U, .ToReg: X86::XMM15 },
5454 { .FromReg: 33U, .ToReg: X86::ST0 },
5455 { .FromReg: 34U, .ToReg: X86::ST1 },
5456 { .FromReg: 35U, .ToReg: X86::ST2 },
5457 { .FromReg: 36U, .ToReg: X86::ST3 },
5458 { .FromReg: 37U, .ToReg: X86::ST4 },
5459 { .FromReg: 38U, .ToReg: X86::ST5 },
5460 { .FromReg: 39U, .ToReg: X86::ST6 },
5461 { .FromReg: 40U, .ToReg: X86::ST7 },
5462 { .FromReg: 41U, .ToReg: X86::MM0 },
5463 { .FromReg: 42U, .ToReg: X86::MM1 },
5464 { .FromReg: 43U, .ToReg: X86::MM2 },
5465 { .FromReg: 44U, .ToReg: X86::MM3 },
5466 { .FromReg: 45U, .ToReg: X86::MM4 },
5467 { .FromReg: 46U, .ToReg: X86::MM5 },
5468 { .FromReg: 47U, .ToReg: X86::MM6 },
5469 { .FromReg: 48U, .ToReg: X86::MM7 },
5470 { .FromReg: 49U, .ToReg: X86::RFLAGS },
5471 { .FromReg: 50U, .ToReg: X86::ES },
5472 { .FromReg: 51U, .ToReg: X86::CS },
5473 { .FromReg: 52U, .ToReg: X86::SS },
5474 { .FromReg: 53U, .ToReg: X86::DS },
5475 { .FromReg: 54U, .ToReg: X86::FS },
5476 { .FromReg: 55U, .ToReg: X86::GS },
5477 { .FromReg: 58U, .ToReg: X86::FS_BASE },
5478 { .FromReg: 59U, .ToReg: X86::GS_BASE },
5479 { .FromReg: 67U, .ToReg: X86::XMM16 },
5480 { .FromReg: 68U, .ToReg: X86::XMM17 },
5481 { .FromReg: 69U, .ToReg: X86::XMM18 },
5482 { .FromReg: 70U, .ToReg: X86::XMM19 },
5483 { .FromReg: 71U, .ToReg: X86::XMM20 },
5484 { .FromReg: 72U, .ToReg: X86::XMM21 },
5485 { .FromReg: 73U, .ToReg: X86::XMM22 },
5486 { .FromReg: 74U, .ToReg: X86::XMM23 },
5487 { .FromReg: 75U, .ToReg: X86::XMM24 },
5488 { .FromReg: 76U, .ToReg: X86::XMM25 },
5489 { .FromReg: 77U, .ToReg: X86::XMM26 },
5490 { .FromReg: 78U, .ToReg: X86::XMM27 },
5491 { .FromReg: 79U, .ToReg: X86::XMM28 },
5492 { .FromReg: 80U, .ToReg: X86::XMM29 },
5493 { .FromReg: 81U, .ToReg: X86::XMM30 },
5494 { .FromReg: 82U, .ToReg: X86::XMM31 },
5495 { .FromReg: 118U, .ToReg: X86::K0 },
5496 { .FromReg: 119U, .ToReg: X86::K1 },
5497 { .FromReg: 120U, .ToReg: X86::K2 },
5498 { .FromReg: 121U, .ToReg: X86::K3 },
5499 { .FromReg: 122U, .ToReg: X86::K4 },
5500 { .FromReg: 123U, .ToReg: X86::K5 },
5501 { .FromReg: 124U, .ToReg: X86::K6 },
5502 { .FromReg: 125U, .ToReg: X86::K7 },
5503 { .FromReg: 130U, .ToReg: X86::R16 },
5504 { .FromReg: 131U, .ToReg: X86::R17 },
5505 { .FromReg: 132U, .ToReg: X86::R18 },
5506 { .FromReg: 133U, .ToReg: X86::R19 },
5507 { .FromReg: 134U, .ToReg: X86::R20 },
5508 { .FromReg: 135U, .ToReg: X86::R21 },
5509 { .FromReg: 136U, .ToReg: X86::R22 },
5510 { .FromReg: 137U, .ToReg: X86::R23 },
5511 { .FromReg: 138U, .ToReg: X86::R24 },
5512 { .FromReg: 139U, .ToReg: X86::R25 },
5513 { .FromReg: 140U, .ToReg: X86::R26 },
5514 { .FromReg: 141U, .ToReg: X86::R27 },
5515 { .FromReg: 142U, .ToReg: X86::R28 },
5516 { .FromReg: 143U, .ToReg: X86::R29 },
5517 { .FromReg: 144U, .ToReg: X86::R30 },
5518 { .FromReg: 145U, .ToReg: X86::R31 },
5519};
5520extern const unsigned X86EHFlavour0Dwarf2LSize = std::size(X86EHFlavour0Dwarf2L);
5521
5522extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
5523 { .FromReg: 0U, .ToReg: X86::EAX },
5524 { .FromReg: 1U, .ToReg: X86::ECX },
5525 { .FromReg: 2U, .ToReg: X86::EDX },
5526 { .FromReg: 3U, .ToReg: X86::EBX },
5527 { .FromReg: 4U, .ToReg: X86::EBP },
5528 { .FromReg: 5U, .ToReg: X86::ESP },
5529 { .FromReg: 6U, .ToReg: X86::ESI },
5530 { .FromReg: 7U, .ToReg: X86::EDI },
5531 { .FromReg: 8U, .ToReg: X86::EIP },
5532 { .FromReg: 9U, .ToReg: X86::EFLAGS },
5533 { .FromReg: 12U, .ToReg: X86::ST0 },
5534 { .FromReg: 13U, .ToReg: X86::ST1 },
5535 { .FromReg: 14U, .ToReg: X86::ST2 },
5536 { .FromReg: 15U, .ToReg: X86::ST3 },
5537 { .FromReg: 16U, .ToReg: X86::ST4 },
5538 { .FromReg: 17U, .ToReg: X86::ST5 },
5539 { .FromReg: 18U, .ToReg: X86::ST6 },
5540 { .FromReg: 19U, .ToReg: X86::ST7 },
5541 { .FromReg: 21U, .ToReg: X86::XMM0 },
5542 { .FromReg: 22U, .ToReg: X86::XMM1 },
5543 { .FromReg: 23U, .ToReg: X86::XMM2 },
5544 { .FromReg: 24U, .ToReg: X86::XMM3 },
5545 { .FromReg: 25U, .ToReg: X86::XMM4 },
5546 { .FromReg: 26U, .ToReg: X86::XMM5 },
5547 { .FromReg: 27U, .ToReg: X86::XMM6 },
5548 { .FromReg: 28U, .ToReg: X86::XMM7 },
5549 { .FromReg: 29U, .ToReg: X86::MM0 },
5550 { .FromReg: 30U, .ToReg: X86::MM1 },
5551 { .FromReg: 31U, .ToReg: X86::MM2 },
5552 { .FromReg: 32U, .ToReg: X86::MM3 },
5553 { .FromReg: 33U, .ToReg: X86::MM4 },
5554 { .FromReg: 34U, .ToReg: X86::MM5 },
5555 { .FromReg: 35U, .ToReg: X86::MM6 },
5556 { .FromReg: 36U, .ToReg: X86::MM7 },
5557 { .FromReg: 93U, .ToReg: X86::K0 },
5558 { .FromReg: 94U, .ToReg: X86::K1 },
5559 { .FromReg: 95U, .ToReg: X86::K2 },
5560 { .FromReg: 96U, .ToReg: X86::K3 },
5561 { .FromReg: 97U, .ToReg: X86::K4 },
5562 { .FromReg: 98U, .ToReg: X86::K5 },
5563 { .FromReg: 99U, .ToReg: X86::K6 },
5564 { .FromReg: 100U, .ToReg: X86::K7 },
5565};
5566extern const unsigned X86EHFlavour1Dwarf2LSize = std::size(X86EHFlavour1Dwarf2L);
5567
5568extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
5569 { .FromReg: 0U, .ToReg: X86::EAX },
5570 { .FromReg: 1U, .ToReg: X86::ECX },
5571 { .FromReg: 2U, .ToReg: X86::EDX },
5572 { .FromReg: 3U, .ToReg: X86::EBX },
5573 { .FromReg: 4U, .ToReg: X86::ESP },
5574 { .FromReg: 5U, .ToReg: X86::EBP },
5575 { .FromReg: 6U, .ToReg: X86::ESI },
5576 { .FromReg: 7U, .ToReg: X86::EDI },
5577 { .FromReg: 8U, .ToReg: X86::EIP },
5578 { .FromReg: 9U, .ToReg: X86::EFLAGS },
5579 { .FromReg: 11U, .ToReg: X86::ST0 },
5580 { .FromReg: 12U, .ToReg: X86::ST1 },
5581 { .FromReg: 13U, .ToReg: X86::ST2 },
5582 { .FromReg: 14U, .ToReg: X86::ST3 },
5583 { .FromReg: 15U, .ToReg: X86::ST4 },
5584 { .FromReg: 16U, .ToReg: X86::ST5 },
5585 { .FromReg: 17U, .ToReg: X86::ST6 },
5586 { .FromReg: 18U, .ToReg: X86::ST7 },
5587 { .FromReg: 21U, .ToReg: X86::XMM0 },
5588 { .FromReg: 22U, .ToReg: X86::XMM1 },
5589 { .FromReg: 23U, .ToReg: X86::XMM2 },
5590 { .FromReg: 24U, .ToReg: X86::XMM3 },
5591 { .FromReg: 25U, .ToReg: X86::XMM4 },
5592 { .FromReg: 26U, .ToReg: X86::XMM5 },
5593 { .FromReg: 27U, .ToReg: X86::XMM6 },
5594 { .FromReg: 28U, .ToReg: X86::XMM7 },
5595 { .FromReg: 29U, .ToReg: X86::MM0 },
5596 { .FromReg: 30U, .ToReg: X86::MM1 },
5597 { .FromReg: 31U, .ToReg: X86::MM2 },
5598 { .FromReg: 32U, .ToReg: X86::MM3 },
5599 { .FromReg: 33U, .ToReg: X86::MM4 },
5600 { .FromReg: 34U, .ToReg: X86::MM5 },
5601 { .FromReg: 35U, .ToReg: X86::MM6 },
5602 { .FromReg: 36U, .ToReg: X86::MM7 },
5603 { .FromReg: 40U, .ToReg: X86::ES },
5604 { .FromReg: 41U, .ToReg: X86::CS },
5605 { .FromReg: 42U, .ToReg: X86::SS },
5606 { .FromReg: 43U, .ToReg: X86::DS },
5607 { .FromReg: 44U, .ToReg: X86::FS },
5608 { .FromReg: 45U, .ToReg: X86::GS },
5609 { .FromReg: 93U, .ToReg: X86::K0 },
5610 { .FromReg: 94U, .ToReg: X86::K1 },
5611 { .FromReg: 95U, .ToReg: X86::K2 },
5612 { .FromReg: 96U, .ToReg: X86::K3 },
5613 { .FromReg: 97U, .ToReg: X86::K4 },
5614 { .FromReg: 98U, .ToReg: X86::K5 },
5615 { .FromReg: 99U, .ToReg: X86::K6 },
5616 { .FromReg: 100U, .ToReg: X86::K7 },
5617};
5618extern const unsigned X86EHFlavour2Dwarf2LSize = std::size(X86EHFlavour2Dwarf2L);
5619
5620extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
5621 { .FromReg: X86::CS, .ToReg: 51U },
5622 { .FromReg: X86::DS, .ToReg: 53U },
5623 { .FromReg: X86::EAX, .ToReg: -2U },
5624 { .FromReg: X86::EBP, .ToReg: -2U },
5625 { .FromReg: X86::EBX, .ToReg: -2U },
5626 { .FromReg: X86::ECX, .ToReg: -2U },
5627 { .FromReg: X86::EDI, .ToReg: -2U },
5628 { .FromReg: X86::EDX, .ToReg: -2U },
5629 { .FromReg: X86::EFLAGS, .ToReg: 49U },
5630 { .FromReg: X86::EIP, .ToReg: -2U },
5631 { .FromReg: X86::ES, .ToReg: 50U },
5632 { .FromReg: X86::ESI, .ToReg: -2U },
5633 { .FromReg: X86::ESP, .ToReg: -2U },
5634 { .FromReg: X86::FS, .ToReg: 54U },
5635 { .FromReg: X86::FS_BASE, .ToReg: 58U },
5636 { .FromReg: X86::GS, .ToReg: 55U },
5637 { .FromReg: X86::GS_BASE, .ToReg: 59U },
5638 { .FromReg: X86::RAX, .ToReg: 0U },
5639 { .FromReg: X86::RBP, .ToReg: 6U },
5640 { .FromReg: X86::RBX, .ToReg: 3U },
5641 { .FromReg: X86::RCX, .ToReg: 2U },
5642 { .FromReg: X86::RDI, .ToReg: 5U },
5643 { .FromReg: X86::RDX, .ToReg: 1U },
5644 { .FromReg: X86::RFLAGS, .ToReg: 49U },
5645 { .FromReg: X86::RIP, .ToReg: 16U },
5646 { .FromReg: X86::RSI, .ToReg: 4U },
5647 { .FromReg: X86::RSP, .ToReg: 7U },
5648 { .FromReg: X86::SS, .ToReg: 52U },
5649 { .FromReg: X86::_EFLAGS, .ToReg: 49U },
5650 { .FromReg: X86::MM0, .ToReg: 41U },
5651 { .FromReg: X86::MM1, .ToReg: 42U },
5652 { .FromReg: X86::MM2, .ToReg: 43U },
5653 { .FromReg: X86::MM3, .ToReg: 44U },
5654 { .FromReg: X86::MM4, .ToReg: 45U },
5655 { .FromReg: X86::MM5, .ToReg: 46U },
5656 { .FromReg: X86::MM6, .ToReg: 47U },
5657 { .FromReg: X86::MM7, .ToReg: 48U },
5658 { .FromReg: X86::R8, .ToReg: 8U },
5659 { .FromReg: X86::R9, .ToReg: 9U },
5660 { .FromReg: X86::R10, .ToReg: 10U },
5661 { .FromReg: X86::R11, .ToReg: 11U },
5662 { .FromReg: X86::R12, .ToReg: 12U },
5663 { .FromReg: X86::R13, .ToReg: 13U },
5664 { .FromReg: X86::R14, .ToReg: 14U },
5665 { .FromReg: X86::R15, .ToReg: 15U },
5666 { .FromReg: X86::ST0, .ToReg: 33U },
5667 { .FromReg: X86::ST1, .ToReg: 34U },
5668 { .FromReg: X86::ST2, .ToReg: 35U },
5669 { .FromReg: X86::ST3, .ToReg: 36U },
5670 { .FromReg: X86::ST4, .ToReg: 37U },
5671 { .FromReg: X86::ST5, .ToReg: 38U },
5672 { .FromReg: X86::ST6, .ToReg: 39U },
5673 { .FromReg: X86::ST7, .ToReg: 40U },
5674 { .FromReg: X86::XMM0, .ToReg: 17U },
5675 { .FromReg: X86::XMM1, .ToReg: 18U },
5676 { .FromReg: X86::XMM2, .ToReg: 19U },
5677 { .FromReg: X86::XMM3, .ToReg: 20U },
5678 { .FromReg: X86::XMM4, .ToReg: 21U },
5679 { .FromReg: X86::XMM5, .ToReg: 22U },
5680 { .FromReg: X86::XMM6, .ToReg: 23U },
5681 { .FromReg: X86::XMM7, .ToReg: 24U },
5682 { .FromReg: X86::XMM8, .ToReg: 25U },
5683 { .FromReg: X86::XMM9, .ToReg: 26U },
5684 { .FromReg: X86::XMM10, .ToReg: 27U },
5685 { .FromReg: X86::XMM11, .ToReg: 28U },
5686 { .FromReg: X86::XMM12, .ToReg: 29U },
5687 { .FromReg: X86::XMM13, .ToReg: 30U },
5688 { .FromReg: X86::XMM14, .ToReg: 31U },
5689 { .FromReg: X86::XMM15, .ToReg: 32U },
5690 { .FromReg: X86::YMM0, .ToReg: 17U },
5691 { .FromReg: X86::YMM1, .ToReg: 18U },
5692 { .FromReg: X86::YMM2, .ToReg: 19U },
5693 { .FromReg: X86::YMM3, .ToReg: 20U },
5694 { .FromReg: X86::YMM4, .ToReg: 21U },
5695 { .FromReg: X86::YMM5, .ToReg: 22U },
5696 { .FromReg: X86::YMM6, .ToReg: 23U },
5697 { .FromReg: X86::YMM7, .ToReg: 24U },
5698 { .FromReg: X86::YMM8, .ToReg: 25U },
5699 { .FromReg: X86::YMM9, .ToReg: 26U },
5700 { .FromReg: X86::YMM10, .ToReg: 27U },
5701 { .FromReg: X86::YMM11, .ToReg: 28U },
5702 { .FromReg: X86::YMM12, .ToReg: 29U },
5703 { .FromReg: X86::YMM13, .ToReg: 30U },
5704 { .FromReg: X86::YMM14, .ToReg: 31U },
5705 { .FromReg: X86::YMM15, .ToReg: 32U },
5706 { .FromReg: X86::K0, .ToReg: 118U },
5707 { .FromReg: X86::K1, .ToReg: 119U },
5708 { .FromReg: X86::K2, .ToReg: 120U },
5709 { .FromReg: X86::K3, .ToReg: 121U },
5710 { .FromReg: X86::K4, .ToReg: 122U },
5711 { .FromReg: X86::K5, .ToReg: 123U },
5712 { .FromReg: X86::K6, .ToReg: 124U },
5713 { .FromReg: X86::K7, .ToReg: 125U },
5714 { .FromReg: X86::XMM16, .ToReg: 67U },
5715 { .FromReg: X86::XMM17, .ToReg: 68U },
5716 { .FromReg: X86::XMM18, .ToReg: 69U },
5717 { .FromReg: X86::XMM19, .ToReg: 70U },
5718 { .FromReg: X86::XMM20, .ToReg: 71U },
5719 { .FromReg: X86::XMM21, .ToReg: 72U },
5720 { .FromReg: X86::XMM22, .ToReg: 73U },
5721 { .FromReg: X86::XMM23, .ToReg: 74U },
5722 { .FromReg: X86::XMM24, .ToReg: 75U },
5723 { .FromReg: X86::XMM25, .ToReg: 76U },
5724 { .FromReg: X86::XMM26, .ToReg: 77U },
5725 { .FromReg: X86::XMM27, .ToReg: 78U },
5726 { .FromReg: X86::XMM28, .ToReg: 79U },
5727 { .FromReg: X86::XMM29, .ToReg: 80U },
5728 { .FromReg: X86::XMM30, .ToReg: 81U },
5729 { .FromReg: X86::XMM31, .ToReg: 82U },
5730 { .FromReg: X86::YMM16, .ToReg: 67U },
5731 { .FromReg: X86::YMM17, .ToReg: 68U },
5732 { .FromReg: X86::YMM18, .ToReg: 69U },
5733 { .FromReg: X86::YMM19, .ToReg: 70U },
5734 { .FromReg: X86::YMM20, .ToReg: 71U },
5735 { .FromReg: X86::YMM21, .ToReg: 72U },
5736 { .FromReg: X86::YMM22, .ToReg: 73U },
5737 { .FromReg: X86::YMM23, .ToReg: 74U },
5738 { .FromReg: X86::YMM24, .ToReg: 75U },
5739 { .FromReg: X86::YMM25, .ToReg: 76U },
5740 { .FromReg: X86::YMM26, .ToReg: 77U },
5741 { .FromReg: X86::YMM27, .ToReg: 78U },
5742 { .FromReg: X86::YMM28, .ToReg: 79U },
5743 { .FromReg: X86::YMM29, .ToReg: 80U },
5744 { .FromReg: X86::YMM30, .ToReg: 81U },
5745 { .FromReg: X86::YMM31, .ToReg: 82U },
5746 { .FromReg: X86::ZMM0, .ToReg: 17U },
5747 { .FromReg: X86::ZMM1, .ToReg: 18U },
5748 { .FromReg: X86::ZMM2, .ToReg: 19U },
5749 { .FromReg: X86::ZMM3, .ToReg: 20U },
5750 { .FromReg: X86::ZMM4, .ToReg: 21U },
5751 { .FromReg: X86::ZMM5, .ToReg: 22U },
5752 { .FromReg: X86::ZMM6, .ToReg: 23U },
5753 { .FromReg: X86::ZMM7, .ToReg: 24U },
5754 { .FromReg: X86::ZMM8, .ToReg: 25U },
5755 { .FromReg: X86::ZMM9, .ToReg: 26U },
5756 { .FromReg: X86::ZMM10, .ToReg: 27U },
5757 { .FromReg: X86::ZMM11, .ToReg: 28U },
5758 { .FromReg: X86::ZMM12, .ToReg: 29U },
5759 { .FromReg: X86::ZMM13, .ToReg: 30U },
5760 { .FromReg: X86::ZMM14, .ToReg: 31U },
5761 { .FromReg: X86::ZMM15, .ToReg: 32U },
5762 { .FromReg: X86::ZMM16, .ToReg: 67U },
5763 { .FromReg: X86::ZMM17, .ToReg: 68U },
5764 { .FromReg: X86::ZMM18, .ToReg: 69U },
5765 { .FromReg: X86::ZMM19, .ToReg: 70U },
5766 { .FromReg: X86::ZMM20, .ToReg: 71U },
5767 { .FromReg: X86::ZMM21, .ToReg: 72U },
5768 { .FromReg: X86::ZMM22, .ToReg: 73U },
5769 { .FromReg: X86::ZMM23, .ToReg: 74U },
5770 { .FromReg: X86::ZMM24, .ToReg: 75U },
5771 { .FromReg: X86::ZMM25, .ToReg: 76U },
5772 { .FromReg: X86::ZMM26, .ToReg: 77U },
5773 { .FromReg: X86::ZMM27, .ToReg: 78U },
5774 { .FromReg: X86::ZMM28, .ToReg: 79U },
5775 { .FromReg: X86::ZMM29, .ToReg: 80U },
5776 { .FromReg: X86::ZMM30, .ToReg: 81U },
5777 { .FromReg: X86::ZMM31, .ToReg: 82U },
5778 { .FromReg: X86::R16, .ToReg: 130U },
5779 { .FromReg: X86::R17, .ToReg: 131U },
5780 { .FromReg: X86::R18, .ToReg: 132U },
5781 { .FromReg: X86::R19, .ToReg: 133U },
5782 { .FromReg: X86::R20, .ToReg: 134U },
5783 { .FromReg: X86::R21, .ToReg: 135U },
5784 { .FromReg: X86::R22, .ToReg: 136U },
5785 { .FromReg: X86::R23, .ToReg: 137U },
5786 { .FromReg: X86::R24, .ToReg: 138U },
5787 { .FromReg: X86::R25, .ToReg: 139U },
5788 { .FromReg: X86::R26, .ToReg: 140U },
5789 { .FromReg: X86::R27, .ToReg: 141U },
5790 { .FromReg: X86::R28, .ToReg: 142U },
5791 { .FromReg: X86::R29, .ToReg: 143U },
5792 { .FromReg: X86::R30, .ToReg: 144U },
5793 { .FromReg: X86::R31, .ToReg: 145U },
5794};
5795extern const unsigned X86DwarfFlavour0L2DwarfSize = std::size(X86DwarfFlavour0L2Dwarf);
5796
5797extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
5798 { .FromReg: X86::CS, .ToReg: -2U },
5799 { .FromReg: X86::DS, .ToReg: -2U },
5800 { .FromReg: X86::EAX, .ToReg: 0U },
5801 { .FromReg: X86::EBP, .ToReg: 4U },
5802 { .FromReg: X86::EBX, .ToReg: 3U },
5803 { .FromReg: X86::ECX, .ToReg: 1U },
5804 { .FromReg: X86::EDI, .ToReg: 7U },
5805 { .FromReg: X86::EDX, .ToReg: 2U },
5806 { .FromReg: X86::EFLAGS, .ToReg: 9U },
5807 { .FromReg: X86::EIP, .ToReg: 8U },
5808 { .FromReg: X86::ES, .ToReg: -2U },
5809 { .FromReg: X86::ESI, .ToReg: 6U },
5810 { .FromReg: X86::ESP, .ToReg: 5U },
5811 { .FromReg: X86::FS, .ToReg: -2U },
5812 { .FromReg: X86::FS_BASE, .ToReg: -2U },
5813 { .FromReg: X86::GS, .ToReg: -2U },
5814 { .FromReg: X86::GS_BASE, .ToReg: -2U },
5815 { .FromReg: X86::RAX, .ToReg: -2U },
5816 { .FromReg: X86::RBP, .ToReg: -2U },
5817 { .FromReg: X86::RBX, .ToReg: -2U },
5818 { .FromReg: X86::RCX, .ToReg: -2U },
5819 { .FromReg: X86::RDI, .ToReg: -2U },
5820 { .FromReg: X86::RDX, .ToReg: -2U },
5821 { .FromReg: X86::RFLAGS, .ToReg: -2U },
5822 { .FromReg: X86::RIP, .ToReg: -2U },
5823 { .FromReg: X86::RSI, .ToReg: -2U },
5824 { .FromReg: X86::RSP, .ToReg: -2U },
5825 { .FromReg: X86::SS, .ToReg: -2U },
5826 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
5827 { .FromReg: X86::MM0, .ToReg: 29U },
5828 { .FromReg: X86::MM1, .ToReg: 30U },
5829 { .FromReg: X86::MM2, .ToReg: 31U },
5830 { .FromReg: X86::MM3, .ToReg: 32U },
5831 { .FromReg: X86::MM4, .ToReg: 33U },
5832 { .FromReg: X86::MM5, .ToReg: 34U },
5833 { .FromReg: X86::MM6, .ToReg: 35U },
5834 { .FromReg: X86::MM7, .ToReg: 36U },
5835 { .FromReg: X86::R8, .ToReg: -2U },
5836 { .FromReg: X86::R9, .ToReg: -2U },
5837 { .FromReg: X86::R10, .ToReg: -2U },
5838 { .FromReg: X86::R11, .ToReg: -2U },
5839 { .FromReg: X86::R12, .ToReg: -2U },
5840 { .FromReg: X86::R13, .ToReg: -2U },
5841 { .FromReg: X86::R14, .ToReg: -2U },
5842 { .FromReg: X86::R15, .ToReg: -2U },
5843 { .FromReg: X86::ST0, .ToReg: 12U },
5844 { .FromReg: X86::ST1, .ToReg: 13U },
5845 { .FromReg: X86::ST2, .ToReg: 14U },
5846 { .FromReg: X86::ST3, .ToReg: 15U },
5847 { .FromReg: X86::ST4, .ToReg: 16U },
5848 { .FromReg: X86::ST5, .ToReg: 17U },
5849 { .FromReg: X86::ST6, .ToReg: 18U },
5850 { .FromReg: X86::ST7, .ToReg: 19U },
5851 { .FromReg: X86::XMM0, .ToReg: 21U },
5852 { .FromReg: X86::XMM1, .ToReg: 22U },
5853 { .FromReg: X86::XMM2, .ToReg: 23U },
5854 { .FromReg: X86::XMM3, .ToReg: 24U },
5855 { .FromReg: X86::XMM4, .ToReg: 25U },
5856 { .FromReg: X86::XMM5, .ToReg: 26U },
5857 { .FromReg: X86::XMM6, .ToReg: 27U },
5858 { .FromReg: X86::XMM7, .ToReg: 28U },
5859 { .FromReg: X86::XMM8, .ToReg: -2U },
5860 { .FromReg: X86::XMM9, .ToReg: -2U },
5861 { .FromReg: X86::XMM10, .ToReg: -2U },
5862 { .FromReg: X86::XMM11, .ToReg: -2U },
5863 { .FromReg: X86::XMM12, .ToReg: -2U },
5864 { .FromReg: X86::XMM13, .ToReg: -2U },
5865 { .FromReg: X86::XMM14, .ToReg: -2U },
5866 { .FromReg: X86::XMM15, .ToReg: -2U },
5867 { .FromReg: X86::YMM0, .ToReg: 21U },
5868 { .FromReg: X86::YMM1, .ToReg: 22U },
5869 { .FromReg: X86::YMM2, .ToReg: 23U },
5870 { .FromReg: X86::YMM3, .ToReg: 24U },
5871 { .FromReg: X86::YMM4, .ToReg: 25U },
5872 { .FromReg: X86::YMM5, .ToReg: 26U },
5873 { .FromReg: X86::YMM6, .ToReg: 27U },
5874 { .FromReg: X86::YMM7, .ToReg: 28U },
5875 { .FromReg: X86::YMM8, .ToReg: -2U },
5876 { .FromReg: X86::YMM9, .ToReg: -2U },
5877 { .FromReg: X86::YMM10, .ToReg: -2U },
5878 { .FromReg: X86::YMM11, .ToReg: -2U },
5879 { .FromReg: X86::YMM12, .ToReg: -2U },
5880 { .FromReg: X86::YMM13, .ToReg: -2U },
5881 { .FromReg: X86::YMM14, .ToReg: -2U },
5882 { .FromReg: X86::YMM15, .ToReg: -2U },
5883 { .FromReg: X86::K0, .ToReg: 93U },
5884 { .FromReg: X86::K1, .ToReg: 94U },
5885 { .FromReg: X86::K2, .ToReg: 95U },
5886 { .FromReg: X86::K3, .ToReg: 96U },
5887 { .FromReg: X86::K4, .ToReg: 97U },
5888 { .FromReg: X86::K5, .ToReg: 98U },
5889 { .FromReg: X86::K6, .ToReg: 99U },
5890 { .FromReg: X86::K7, .ToReg: 100U },
5891 { .FromReg: X86::XMM16, .ToReg: -2U },
5892 { .FromReg: X86::XMM17, .ToReg: -2U },
5893 { .FromReg: X86::XMM18, .ToReg: -2U },
5894 { .FromReg: X86::XMM19, .ToReg: -2U },
5895 { .FromReg: X86::XMM20, .ToReg: -2U },
5896 { .FromReg: X86::XMM21, .ToReg: -2U },
5897 { .FromReg: X86::XMM22, .ToReg: -2U },
5898 { .FromReg: X86::XMM23, .ToReg: -2U },
5899 { .FromReg: X86::XMM24, .ToReg: -2U },
5900 { .FromReg: X86::XMM25, .ToReg: -2U },
5901 { .FromReg: X86::XMM26, .ToReg: -2U },
5902 { .FromReg: X86::XMM27, .ToReg: -2U },
5903 { .FromReg: X86::XMM28, .ToReg: -2U },
5904 { .FromReg: X86::XMM29, .ToReg: -2U },
5905 { .FromReg: X86::XMM30, .ToReg: -2U },
5906 { .FromReg: X86::XMM31, .ToReg: -2U },
5907 { .FromReg: X86::YMM16, .ToReg: -2U },
5908 { .FromReg: X86::YMM17, .ToReg: -2U },
5909 { .FromReg: X86::YMM18, .ToReg: -2U },
5910 { .FromReg: X86::YMM19, .ToReg: -2U },
5911 { .FromReg: X86::YMM20, .ToReg: -2U },
5912 { .FromReg: X86::YMM21, .ToReg: -2U },
5913 { .FromReg: X86::YMM22, .ToReg: -2U },
5914 { .FromReg: X86::YMM23, .ToReg: -2U },
5915 { .FromReg: X86::YMM24, .ToReg: -2U },
5916 { .FromReg: X86::YMM25, .ToReg: -2U },
5917 { .FromReg: X86::YMM26, .ToReg: -2U },
5918 { .FromReg: X86::YMM27, .ToReg: -2U },
5919 { .FromReg: X86::YMM28, .ToReg: -2U },
5920 { .FromReg: X86::YMM29, .ToReg: -2U },
5921 { .FromReg: X86::YMM30, .ToReg: -2U },
5922 { .FromReg: X86::YMM31, .ToReg: -2U },
5923 { .FromReg: X86::ZMM0, .ToReg: 21U },
5924 { .FromReg: X86::ZMM1, .ToReg: 22U },
5925 { .FromReg: X86::ZMM2, .ToReg: 23U },
5926 { .FromReg: X86::ZMM3, .ToReg: 24U },
5927 { .FromReg: X86::ZMM4, .ToReg: 25U },
5928 { .FromReg: X86::ZMM5, .ToReg: 26U },
5929 { .FromReg: X86::ZMM6, .ToReg: 27U },
5930 { .FromReg: X86::ZMM7, .ToReg: 28U },
5931 { .FromReg: X86::ZMM8, .ToReg: -2U },
5932 { .FromReg: X86::ZMM9, .ToReg: -2U },
5933 { .FromReg: X86::ZMM10, .ToReg: -2U },
5934 { .FromReg: X86::ZMM11, .ToReg: -2U },
5935 { .FromReg: X86::ZMM12, .ToReg: -2U },
5936 { .FromReg: X86::ZMM13, .ToReg: -2U },
5937 { .FromReg: X86::ZMM14, .ToReg: -2U },
5938 { .FromReg: X86::ZMM15, .ToReg: -2U },
5939 { .FromReg: X86::ZMM16, .ToReg: -2U },
5940 { .FromReg: X86::ZMM17, .ToReg: -2U },
5941 { .FromReg: X86::ZMM18, .ToReg: -2U },
5942 { .FromReg: X86::ZMM19, .ToReg: -2U },
5943 { .FromReg: X86::ZMM20, .ToReg: -2U },
5944 { .FromReg: X86::ZMM21, .ToReg: -2U },
5945 { .FromReg: X86::ZMM22, .ToReg: -2U },
5946 { .FromReg: X86::ZMM23, .ToReg: -2U },
5947 { .FromReg: X86::ZMM24, .ToReg: -2U },
5948 { .FromReg: X86::ZMM25, .ToReg: -2U },
5949 { .FromReg: X86::ZMM26, .ToReg: -2U },
5950 { .FromReg: X86::ZMM27, .ToReg: -2U },
5951 { .FromReg: X86::ZMM28, .ToReg: -2U },
5952 { .FromReg: X86::ZMM29, .ToReg: -2U },
5953 { .FromReg: X86::ZMM30, .ToReg: -2U },
5954 { .FromReg: X86::ZMM31, .ToReg: -2U },
5955 { .FromReg: X86::R16, .ToReg: -2U },
5956 { .FromReg: X86::R17, .ToReg: -2U },
5957 { .FromReg: X86::R18, .ToReg: -2U },
5958 { .FromReg: X86::R19, .ToReg: -2U },
5959 { .FromReg: X86::R20, .ToReg: -2U },
5960 { .FromReg: X86::R21, .ToReg: -2U },
5961 { .FromReg: X86::R22, .ToReg: -2U },
5962 { .FromReg: X86::R23, .ToReg: -2U },
5963 { .FromReg: X86::R24, .ToReg: -2U },
5964 { .FromReg: X86::R25, .ToReg: -2U },
5965 { .FromReg: X86::R26, .ToReg: -2U },
5966 { .FromReg: X86::R27, .ToReg: -2U },
5967 { .FromReg: X86::R28, .ToReg: -2U },
5968 { .FromReg: X86::R29, .ToReg: -2U },
5969 { .FromReg: X86::R30, .ToReg: -2U },
5970 { .FromReg: X86::R31, .ToReg: -2U },
5971};
5972extern const unsigned X86DwarfFlavour1L2DwarfSize = std::size(X86DwarfFlavour1L2Dwarf);
5973
5974extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
5975 { .FromReg: X86::CS, .ToReg: 41U },
5976 { .FromReg: X86::DS, .ToReg: 43U },
5977 { .FromReg: X86::EAX, .ToReg: 0U },
5978 { .FromReg: X86::EBP, .ToReg: 5U },
5979 { .FromReg: X86::EBX, .ToReg: 3U },
5980 { .FromReg: X86::ECX, .ToReg: 1U },
5981 { .FromReg: X86::EDI, .ToReg: 7U },
5982 { .FromReg: X86::EDX, .ToReg: 2U },
5983 { .FromReg: X86::EFLAGS, .ToReg: 9U },
5984 { .FromReg: X86::EIP, .ToReg: 8U },
5985 { .FromReg: X86::ES, .ToReg: 40U },
5986 { .FromReg: X86::ESI, .ToReg: 6U },
5987 { .FromReg: X86::ESP, .ToReg: 4U },
5988 { .FromReg: X86::FS, .ToReg: 44U },
5989 { .FromReg: X86::FS_BASE, .ToReg: -2U },
5990 { .FromReg: X86::GS, .ToReg: 45U },
5991 { .FromReg: X86::GS_BASE, .ToReg: -2U },
5992 { .FromReg: X86::RAX, .ToReg: -2U },
5993 { .FromReg: X86::RBP, .ToReg: -2U },
5994 { .FromReg: X86::RBX, .ToReg: -2U },
5995 { .FromReg: X86::RCX, .ToReg: -2U },
5996 { .FromReg: X86::RDI, .ToReg: -2U },
5997 { .FromReg: X86::RDX, .ToReg: -2U },
5998 { .FromReg: X86::RFLAGS, .ToReg: -2U },
5999 { .FromReg: X86::RIP, .ToReg: -2U },
6000 { .FromReg: X86::RSI, .ToReg: -2U },
6001 { .FromReg: X86::RSP, .ToReg: -2U },
6002 { .FromReg: X86::SS, .ToReg: 42U },
6003 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
6004 { .FromReg: X86::MM0, .ToReg: 29U },
6005 { .FromReg: X86::MM1, .ToReg: 30U },
6006 { .FromReg: X86::MM2, .ToReg: 31U },
6007 { .FromReg: X86::MM3, .ToReg: 32U },
6008 { .FromReg: X86::MM4, .ToReg: 33U },
6009 { .FromReg: X86::MM5, .ToReg: 34U },
6010 { .FromReg: X86::MM6, .ToReg: 35U },
6011 { .FromReg: X86::MM7, .ToReg: 36U },
6012 { .FromReg: X86::R8, .ToReg: -2U },
6013 { .FromReg: X86::R9, .ToReg: -2U },
6014 { .FromReg: X86::R10, .ToReg: -2U },
6015 { .FromReg: X86::R11, .ToReg: -2U },
6016 { .FromReg: X86::R12, .ToReg: -2U },
6017 { .FromReg: X86::R13, .ToReg: -2U },
6018 { .FromReg: X86::R14, .ToReg: -2U },
6019 { .FromReg: X86::R15, .ToReg: -2U },
6020 { .FromReg: X86::ST0, .ToReg: 11U },
6021 { .FromReg: X86::ST1, .ToReg: 12U },
6022 { .FromReg: X86::ST2, .ToReg: 13U },
6023 { .FromReg: X86::ST3, .ToReg: 14U },
6024 { .FromReg: X86::ST4, .ToReg: 15U },
6025 { .FromReg: X86::ST5, .ToReg: 16U },
6026 { .FromReg: X86::ST6, .ToReg: 17U },
6027 { .FromReg: X86::ST7, .ToReg: 18U },
6028 { .FromReg: X86::XMM0, .ToReg: 21U },
6029 { .FromReg: X86::XMM1, .ToReg: 22U },
6030 { .FromReg: X86::XMM2, .ToReg: 23U },
6031 { .FromReg: X86::XMM3, .ToReg: 24U },
6032 { .FromReg: X86::XMM4, .ToReg: 25U },
6033 { .FromReg: X86::XMM5, .ToReg: 26U },
6034 { .FromReg: X86::XMM6, .ToReg: 27U },
6035 { .FromReg: X86::XMM7, .ToReg: 28U },
6036 { .FromReg: X86::XMM8, .ToReg: -2U },
6037 { .FromReg: X86::XMM9, .ToReg: -2U },
6038 { .FromReg: X86::XMM10, .ToReg: -2U },
6039 { .FromReg: X86::XMM11, .ToReg: -2U },
6040 { .FromReg: X86::XMM12, .ToReg: -2U },
6041 { .FromReg: X86::XMM13, .ToReg: -2U },
6042 { .FromReg: X86::XMM14, .ToReg: -2U },
6043 { .FromReg: X86::XMM15, .ToReg: -2U },
6044 { .FromReg: X86::YMM0, .ToReg: 21U },
6045 { .FromReg: X86::YMM1, .ToReg: 22U },
6046 { .FromReg: X86::YMM2, .ToReg: 23U },
6047 { .FromReg: X86::YMM3, .ToReg: 24U },
6048 { .FromReg: X86::YMM4, .ToReg: 25U },
6049 { .FromReg: X86::YMM5, .ToReg: 26U },
6050 { .FromReg: X86::YMM6, .ToReg: 27U },
6051 { .FromReg: X86::YMM7, .ToReg: 28U },
6052 { .FromReg: X86::YMM8, .ToReg: -2U },
6053 { .FromReg: X86::YMM9, .ToReg: -2U },
6054 { .FromReg: X86::YMM10, .ToReg: -2U },
6055 { .FromReg: X86::YMM11, .ToReg: -2U },
6056 { .FromReg: X86::YMM12, .ToReg: -2U },
6057 { .FromReg: X86::YMM13, .ToReg: -2U },
6058 { .FromReg: X86::YMM14, .ToReg: -2U },
6059 { .FromReg: X86::YMM15, .ToReg: -2U },
6060 { .FromReg: X86::K0, .ToReg: 93U },
6061 { .FromReg: X86::K1, .ToReg: 94U },
6062 { .FromReg: X86::K2, .ToReg: 95U },
6063 { .FromReg: X86::K3, .ToReg: 96U },
6064 { .FromReg: X86::K4, .ToReg: 97U },
6065 { .FromReg: X86::K5, .ToReg: 98U },
6066 { .FromReg: X86::K6, .ToReg: 99U },
6067 { .FromReg: X86::K7, .ToReg: 100U },
6068 { .FromReg: X86::XMM16, .ToReg: -2U },
6069 { .FromReg: X86::XMM17, .ToReg: -2U },
6070 { .FromReg: X86::XMM18, .ToReg: -2U },
6071 { .FromReg: X86::XMM19, .ToReg: -2U },
6072 { .FromReg: X86::XMM20, .ToReg: -2U },
6073 { .FromReg: X86::XMM21, .ToReg: -2U },
6074 { .FromReg: X86::XMM22, .ToReg: -2U },
6075 { .FromReg: X86::XMM23, .ToReg: -2U },
6076 { .FromReg: X86::XMM24, .ToReg: -2U },
6077 { .FromReg: X86::XMM25, .ToReg: -2U },
6078 { .FromReg: X86::XMM26, .ToReg: -2U },
6079 { .FromReg: X86::XMM27, .ToReg: -2U },
6080 { .FromReg: X86::XMM28, .ToReg: -2U },
6081 { .FromReg: X86::XMM29, .ToReg: -2U },
6082 { .FromReg: X86::XMM30, .ToReg: -2U },
6083 { .FromReg: X86::XMM31, .ToReg: -2U },
6084 { .FromReg: X86::YMM16, .ToReg: -2U },
6085 { .FromReg: X86::YMM17, .ToReg: -2U },
6086 { .FromReg: X86::YMM18, .ToReg: -2U },
6087 { .FromReg: X86::YMM19, .ToReg: -2U },
6088 { .FromReg: X86::YMM20, .ToReg: -2U },
6089 { .FromReg: X86::YMM21, .ToReg: -2U },
6090 { .FromReg: X86::YMM22, .ToReg: -2U },
6091 { .FromReg: X86::YMM23, .ToReg: -2U },
6092 { .FromReg: X86::YMM24, .ToReg: -2U },
6093 { .FromReg: X86::YMM25, .ToReg: -2U },
6094 { .FromReg: X86::YMM26, .ToReg: -2U },
6095 { .FromReg: X86::YMM27, .ToReg: -2U },
6096 { .FromReg: X86::YMM28, .ToReg: -2U },
6097 { .FromReg: X86::YMM29, .ToReg: -2U },
6098 { .FromReg: X86::YMM30, .ToReg: -2U },
6099 { .FromReg: X86::YMM31, .ToReg: -2U },
6100 { .FromReg: X86::ZMM0, .ToReg: 21U },
6101 { .FromReg: X86::ZMM1, .ToReg: 22U },
6102 { .FromReg: X86::ZMM2, .ToReg: 23U },
6103 { .FromReg: X86::ZMM3, .ToReg: 24U },
6104 { .FromReg: X86::ZMM4, .ToReg: 25U },
6105 { .FromReg: X86::ZMM5, .ToReg: 26U },
6106 { .FromReg: X86::ZMM6, .ToReg: 27U },
6107 { .FromReg: X86::ZMM7, .ToReg: 28U },
6108 { .FromReg: X86::ZMM8, .ToReg: -2U },
6109 { .FromReg: X86::ZMM9, .ToReg: -2U },
6110 { .FromReg: X86::ZMM10, .ToReg: -2U },
6111 { .FromReg: X86::ZMM11, .ToReg: -2U },
6112 { .FromReg: X86::ZMM12, .ToReg: -2U },
6113 { .FromReg: X86::ZMM13, .ToReg: -2U },
6114 { .FromReg: X86::ZMM14, .ToReg: -2U },
6115 { .FromReg: X86::ZMM15, .ToReg: -2U },
6116 { .FromReg: X86::ZMM16, .ToReg: -2U },
6117 { .FromReg: X86::ZMM17, .ToReg: -2U },
6118 { .FromReg: X86::ZMM18, .ToReg: -2U },
6119 { .FromReg: X86::ZMM19, .ToReg: -2U },
6120 { .FromReg: X86::ZMM20, .ToReg: -2U },
6121 { .FromReg: X86::ZMM21, .ToReg: -2U },
6122 { .FromReg: X86::ZMM22, .ToReg: -2U },
6123 { .FromReg: X86::ZMM23, .ToReg: -2U },
6124 { .FromReg: X86::ZMM24, .ToReg: -2U },
6125 { .FromReg: X86::ZMM25, .ToReg: -2U },
6126 { .FromReg: X86::ZMM26, .ToReg: -2U },
6127 { .FromReg: X86::ZMM27, .ToReg: -2U },
6128 { .FromReg: X86::ZMM28, .ToReg: -2U },
6129 { .FromReg: X86::ZMM29, .ToReg: -2U },
6130 { .FromReg: X86::ZMM30, .ToReg: -2U },
6131 { .FromReg: X86::ZMM31, .ToReg: -2U },
6132 { .FromReg: X86::R16, .ToReg: -2U },
6133 { .FromReg: X86::R17, .ToReg: -2U },
6134 { .FromReg: X86::R18, .ToReg: -2U },
6135 { .FromReg: X86::R19, .ToReg: -2U },
6136 { .FromReg: X86::R20, .ToReg: -2U },
6137 { .FromReg: X86::R21, .ToReg: -2U },
6138 { .FromReg: X86::R22, .ToReg: -2U },
6139 { .FromReg: X86::R23, .ToReg: -2U },
6140 { .FromReg: X86::R24, .ToReg: -2U },
6141 { .FromReg: X86::R25, .ToReg: -2U },
6142 { .FromReg: X86::R26, .ToReg: -2U },
6143 { .FromReg: X86::R27, .ToReg: -2U },
6144 { .FromReg: X86::R28, .ToReg: -2U },
6145 { .FromReg: X86::R29, .ToReg: -2U },
6146 { .FromReg: X86::R30, .ToReg: -2U },
6147 { .FromReg: X86::R31, .ToReg: -2U },
6148};
6149extern const unsigned X86DwarfFlavour2L2DwarfSize = std::size(X86DwarfFlavour2L2Dwarf);
6150
6151extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
6152 { .FromReg: X86::CS, .ToReg: 51U },
6153 { .FromReg: X86::DS, .ToReg: 53U },
6154 { .FromReg: X86::EAX, .ToReg: -2U },
6155 { .FromReg: X86::EBP, .ToReg: -2U },
6156 { .FromReg: X86::EBX, .ToReg: -2U },
6157 { .FromReg: X86::ECX, .ToReg: -2U },
6158 { .FromReg: X86::EDI, .ToReg: -2U },
6159 { .FromReg: X86::EDX, .ToReg: -2U },
6160 { .FromReg: X86::EFLAGS, .ToReg: 49U },
6161 { .FromReg: X86::EIP, .ToReg: -2U },
6162 { .FromReg: X86::ES, .ToReg: 50U },
6163 { .FromReg: X86::ESI, .ToReg: -2U },
6164 { .FromReg: X86::ESP, .ToReg: -2U },
6165 { .FromReg: X86::FS, .ToReg: 54U },
6166 { .FromReg: X86::FS_BASE, .ToReg: 58U },
6167 { .FromReg: X86::GS, .ToReg: 55U },
6168 { .FromReg: X86::GS_BASE, .ToReg: 59U },
6169 { .FromReg: X86::RAX, .ToReg: 0U },
6170 { .FromReg: X86::RBP, .ToReg: 6U },
6171 { .FromReg: X86::RBX, .ToReg: 3U },
6172 { .FromReg: X86::RCX, .ToReg: 2U },
6173 { .FromReg: X86::RDI, .ToReg: 5U },
6174 { .FromReg: X86::RDX, .ToReg: 1U },
6175 { .FromReg: X86::RFLAGS, .ToReg: 49U },
6176 { .FromReg: X86::RIP, .ToReg: 16U },
6177 { .FromReg: X86::RSI, .ToReg: 4U },
6178 { .FromReg: X86::RSP, .ToReg: 7U },
6179 { .FromReg: X86::SS, .ToReg: 52U },
6180 { .FromReg: X86::_EFLAGS, .ToReg: 49U },
6181 { .FromReg: X86::MM0, .ToReg: 41U },
6182 { .FromReg: X86::MM1, .ToReg: 42U },
6183 { .FromReg: X86::MM2, .ToReg: 43U },
6184 { .FromReg: X86::MM3, .ToReg: 44U },
6185 { .FromReg: X86::MM4, .ToReg: 45U },
6186 { .FromReg: X86::MM5, .ToReg: 46U },
6187 { .FromReg: X86::MM6, .ToReg: 47U },
6188 { .FromReg: X86::MM7, .ToReg: 48U },
6189 { .FromReg: X86::R8, .ToReg: 8U },
6190 { .FromReg: X86::R9, .ToReg: 9U },
6191 { .FromReg: X86::R10, .ToReg: 10U },
6192 { .FromReg: X86::R11, .ToReg: 11U },
6193 { .FromReg: X86::R12, .ToReg: 12U },
6194 { .FromReg: X86::R13, .ToReg: 13U },
6195 { .FromReg: X86::R14, .ToReg: 14U },
6196 { .FromReg: X86::R15, .ToReg: 15U },
6197 { .FromReg: X86::ST0, .ToReg: 33U },
6198 { .FromReg: X86::ST1, .ToReg: 34U },
6199 { .FromReg: X86::ST2, .ToReg: 35U },
6200 { .FromReg: X86::ST3, .ToReg: 36U },
6201 { .FromReg: X86::ST4, .ToReg: 37U },
6202 { .FromReg: X86::ST5, .ToReg: 38U },
6203 { .FromReg: X86::ST6, .ToReg: 39U },
6204 { .FromReg: X86::ST7, .ToReg: 40U },
6205 { .FromReg: X86::XMM0, .ToReg: 17U },
6206 { .FromReg: X86::XMM1, .ToReg: 18U },
6207 { .FromReg: X86::XMM2, .ToReg: 19U },
6208 { .FromReg: X86::XMM3, .ToReg: 20U },
6209 { .FromReg: X86::XMM4, .ToReg: 21U },
6210 { .FromReg: X86::XMM5, .ToReg: 22U },
6211 { .FromReg: X86::XMM6, .ToReg: 23U },
6212 { .FromReg: X86::XMM7, .ToReg: 24U },
6213 { .FromReg: X86::XMM8, .ToReg: 25U },
6214 { .FromReg: X86::XMM9, .ToReg: 26U },
6215 { .FromReg: X86::XMM10, .ToReg: 27U },
6216 { .FromReg: X86::XMM11, .ToReg: 28U },
6217 { .FromReg: X86::XMM12, .ToReg: 29U },
6218 { .FromReg: X86::XMM13, .ToReg: 30U },
6219 { .FromReg: X86::XMM14, .ToReg: 31U },
6220 { .FromReg: X86::XMM15, .ToReg: 32U },
6221 { .FromReg: X86::YMM0, .ToReg: 17U },
6222 { .FromReg: X86::YMM1, .ToReg: 18U },
6223 { .FromReg: X86::YMM2, .ToReg: 19U },
6224 { .FromReg: X86::YMM3, .ToReg: 20U },
6225 { .FromReg: X86::YMM4, .ToReg: 21U },
6226 { .FromReg: X86::YMM5, .ToReg: 22U },
6227 { .FromReg: X86::YMM6, .ToReg: 23U },
6228 { .FromReg: X86::YMM7, .ToReg: 24U },
6229 { .FromReg: X86::YMM8, .ToReg: 25U },
6230 { .FromReg: X86::YMM9, .ToReg: 26U },
6231 { .FromReg: X86::YMM10, .ToReg: 27U },
6232 { .FromReg: X86::YMM11, .ToReg: 28U },
6233 { .FromReg: X86::YMM12, .ToReg: 29U },
6234 { .FromReg: X86::YMM13, .ToReg: 30U },
6235 { .FromReg: X86::YMM14, .ToReg: 31U },
6236 { .FromReg: X86::YMM15, .ToReg: 32U },
6237 { .FromReg: X86::K0, .ToReg: 118U },
6238 { .FromReg: X86::K1, .ToReg: 119U },
6239 { .FromReg: X86::K2, .ToReg: 120U },
6240 { .FromReg: X86::K3, .ToReg: 121U },
6241 { .FromReg: X86::K4, .ToReg: 122U },
6242 { .FromReg: X86::K5, .ToReg: 123U },
6243 { .FromReg: X86::K6, .ToReg: 124U },
6244 { .FromReg: X86::K7, .ToReg: 125U },
6245 { .FromReg: X86::XMM16, .ToReg: 67U },
6246 { .FromReg: X86::XMM17, .ToReg: 68U },
6247 { .FromReg: X86::XMM18, .ToReg: 69U },
6248 { .FromReg: X86::XMM19, .ToReg: 70U },
6249 { .FromReg: X86::XMM20, .ToReg: 71U },
6250 { .FromReg: X86::XMM21, .ToReg: 72U },
6251 { .FromReg: X86::XMM22, .ToReg: 73U },
6252 { .FromReg: X86::XMM23, .ToReg: 74U },
6253 { .FromReg: X86::XMM24, .ToReg: 75U },
6254 { .FromReg: X86::XMM25, .ToReg: 76U },
6255 { .FromReg: X86::XMM26, .ToReg: 77U },
6256 { .FromReg: X86::XMM27, .ToReg: 78U },
6257 { .FromReg: X86::XMM28, .ToReg: 79U },
6258 { .FromReg: X86::XMM29, .ToReg: 80U },
6259 { .FromReg: X86::XMM30, .ToReg: 81U },
6260 { .FromReg: X86::XMM31, .ToReg: 82U },
6261 { .FromReg: X86::YMM16, .ToReg: 67U },
6262 { .FromReg: X86::YMM17, .ToReg: 68U },
6263 { .FromReg: X86::YMM18, .ToReg: 69U },
6264 { .FromReg: X86::YMM19, .ToReg: 70U },
6265 { .FromReg: X86::YMM20, .ToReg: 71U },
6266 { .FromReg: X86::YMM21, .ToReg: 72U },
6267 { .FromReg: X86::YMM22, .ToReg: 73U },
6268 { .FromReg: X86::YMM23, .ToReg: 74U },
6269 { .FromReg: X86::YMM24, .ToReg: 75U },
6270 { .FromReg: X86::YMM25, .ToReg: 76U },
6271 { .FromReg: X86::YMM26, .ToReg: 77U },
6272 { .FromReg: X86::YMM27, .ToReg: 78U },
6273 { .FromReg: X86::YMM28, .ToReg: 79U },
6274 { .FromReg: X86::YMM29, .ToReg: 80U },
6275 { .FromReg: X86::YMM30, .ToReg: 81U },
6276 { .FromReg: X86::YMM31, .ToReg: 82U },
6277 { .FromReg: X86::ZMM0, .ToReg: 17U },
6278 { .FromReg: X86::ZMM1, .ToReg: 18U },
6279 { .FromReg: X86::ZMM2, .ToReg: 19U },
6280 { .FromReg: X86::ZMM3, .ToReg: 20U },
6281 { .FromReg: X86::ZMM4, .ToReg: 21U },
6282 { .FromReg: X86::ZMM5, .ToReg: 22U },
6283 { .FromReg: X86::ZMM6, .ToReg: 23U },
6284 { .FromReg: X86::ZMM7, .ToReg: 24U },
6285 { .FromReg: X86::ZMM8, .ToReg: 25U },
6286 { .FromReg: X86::ZMM9, .ToReg: 26U },
6287 { .FromReg: X86::ZMM10, .ToReg: 27U },
6288 { .FromReg: X86::ZMM11, .ToReg: 28U },
6289 { .FromReg: X86::ZMM12, .ToReg: 29U },
6290 { .FromReg: X86::ZMM13, .ToReg: 30U },
6291 { .FromReg: X86::ZMM14, .ToReg: 31U },
6292 { .FromReg: X86::ZMM15, .ToReg: 32U },
6293 { .FromReg: X86::ZMM16, .ToReg: 67U },
6294 { .FromReg: X86::ZMM17, .ToReg: 68U },
6295 { .FromReg: X86::ZMM18, .ToReg: 69U },
6296 { .FromReg: X86::ZMM19, .ToReg: 70U },
6297 { .FromReg: X86::ZMM20, .ToReg: 71U },
6298 { .FromReg: X86::ZMM21, .ToReg: 72U },
6299 { .FromReg: X86::ZMM22, .ToReg: 73U },
6300 { .FromReg: X86::ZMM23, .ToReg: 74U },
6301 { .FromReg: X86::ZMM24, .ToReg: 75U },
6302 { .FromReg: X86::ZMM25, .ToReg: 76U },
6303 { .FromReg: X86::ZMM26, .ToReg: 77U },
6304 { .FromReg: X86::ZMM27, .ToReg: 78U },
6305 { .FromReg: X86::ZMM28, .ToReg: 79U },
6306 { .FromReg: X86::ZMM29, .ToReg: 80U },
6307 { .FromReg: X86::ZMM30, .ToReg: 81U },
6308 { .FromReg: X86::ZMM31, .ToReg: 82U },
6309 { .FromReg: X86::R16, .ToReg: 130U },
6310 { .FromReg: X86::R17, .ToReg: 131U },
6311 { .FromReg: X86::R18, .ToReg: 132U },
6312 { .FromReg: X86::R19, .ToReg: 133U },
6313 { .FromReg: X86::R20, .ToReg: 134U },
6314 { .FromReg: X86::R21, .ToReg: 135U },
6315 { .FromReg: X86::R22, .ToReg: 136U },
6316 { .FromReg: X86::R23, .ToReg: 137U },
6317 { .FromReg: X86::R24, .ToReg: 138U },
6318 { .FromReg: X86::R25, .ToReg: 139U },
6319 { .FromReg: X86::R26, .ToReg: 140U },
6320 { .FromReg: X86::R27, .ToReg: 141U },
6321 { .FromReg: X86::R28, .ToReg: 142U },
6322 { .FromReg: X86::R29, .ToReg: 143U },
6323 { .FromReg: X86::R30, .ToReg: 144U },
6324 { .FromReg: X86::R31, .ToReg: 145U },
6325};
6326extern const unsigned X86EHFlavour0L2DwarfSize = std::size(X86EHFlavour0L2Dwarf);
6327
6328extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
6329 { .FromReg: X86::CS, .ToReg: -2U },
6330 { .FromReg: X86::DS, .ToReg: -2U },
6331 { .FromReg: X86::EAX, .ToReg: 0U },
6332 { .FromReg: X86::EBP, .ToReg: 4U },
6333 { .FromReg: X86::EBX, .ToReg: 3U },
6334 { .FromReg: X86::ECX, .ToReg: 1U },
6335 { .FromReg: X86::EDI, .ToReg: 7U },
6336 { .FromReg: X86::EDX, .ToReg: 2U },
6337 { .FromReg: X86::EFLAGS, .ToReg: 9U },
6338 { .FromReg: X86::EIP, .ToReg: 8U },
6339 { .FromReg: X86::ES, .ToReg: -2U },
6340 { .FromReg: X86::ESI, .ToReg: 6U },
6341 { .FromReg: X86::ESP, .ToReg: 5U },
6342 { .FromReg: X86::FS, .ToReg: -2U },
6343 { .FromReg: X86::FS_BASE, .ToReg: -2U },
6344 { .FromReg: X86::GS, .ToReg: -2U },
6345 { .FromReg: X86::GS_BASE, .ToReg: -2U },
6346 { .FromReg: X86::RAX, .ToReg: -2U },
6347 { .FromReg: X86::RBP, .ToReg: -2U },
6348 { .FromReg: X86::RBX, .ToReg: -2U },
6349 { .FromReg: X86::RCX, .ToReg: -2U },
6350 { .FromReg: X86::RDI, .ToReg: -2U },
6351 { .FromReg: X86::RDX, .ToReg: -2U },
6352 { .FromReg: X86::RFLAGS, .ToReg: -2U },
6353 { .FromReg: X86::RIP, .ToReg: -2U },
6354 { .FromReg: X86::RSI, .ToReg: -2U },
6355 { .FromReg: X86::RSP, .ToReg: -2U },
6356 { .FromReg: X86::SS, .ToReg: -2U },
6357 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
6358 { .FromReg: X86::MM0, .ToReg: 29U },
6359 { .FromReg: X86::MM1, .ToReg: 30U },
6360 { .FromReg: X86::MM2, .ToReg: 31U },
6361 { .FromReg: X86::MM3, .ToReg: 32U },
6362 { .FromReg: X86::MM4, .ToReg: 33U },
6363 { .FromReg: X86::MM5, .ToReg: 34U },
6364 { .FromReg: X86::MM6, .ToReg: 35U },
6365 { .FromReg: X86::MM7, .ToReg: 36U },
6366 { .FromReg: X86::R8, .ToReg: -2U },
6367 { .FromReg: X86::R9, .ToReg: -2U },
6368 { .FromReg: X86::R10, .ToReg: -2U },
6369 { .FromReg: X86::R11, .ToReg: -2U },
6370 { .FromReg: X86::R12, .ToReg: -2U },
6371 { .FromReg: X86::R13, .ToReg: -2U },
6372 { .FromReg: X86::R14, .ToReg: -2U },
6373 { .FromReg: X86::R15, .ToReg: -2U },
6374 { .FromReg: X86::ST0, .ToReg: 12U },
6375 { .FromReg: X86::ST1, .ToReg: 13U },
6376 { .FromReg: X86::ST2, .ToReg: 14U },
6377 { .FromReg: X86::ST3, .ToReg: 15U },
6378 { .FromReg: X86::ST4, .ToReg: 16U },
6379 { .FromReg: X86::ST5, .ToReg: 17U },
6380 { .FromReg: X86::ST6, .ToReg: 18U },
6381 { .FromReg: X86::ST7, .ToReg: 19U },
6382 { .FromReg: X86::XMM0, .ToReg: 21U },
6383 { .FromReg: X86::XMM1, .ToReg: 22U },
6384 { .FromReg: X86::XMM2, .ToReg: 23U },
6385 { .FromReg: X86::XMM3, .ToReg: 24U },
6386 { .FromReg: X86::XMM4, .ToReg: 25U },
6387 { .FromReg: X86::XMM5, .ToReg: 26U },
6388 { .FromReg: X86::XMM6, .ToReg: 27U },
6389 { .FromReg: X86::XMM7, .ToReg: 28U },
6390 { .FromReg: X86::XMM8, .ToReg: -2U },
6391 { .FromReg: X86::XMM9, .ToReg: -2U },
6392 { .FromReg: X86::XMM10, .ToReg: -2U },
6393 { .FromReg: X86::XMM11, .ToReg: -2U },
6394 { .FromReg: X86::XMM12, .ToReg: -2U },
6395 { .FromReg: X86::XMM13, .ToReg: -2U },
6396 { .FromReg: X86::XMM14, .ToReg: -2U },
6397 { .FromReg: X86::XMM15, .ToReg: -2U },
6398 { .FromReg: X86::YMM0, .ToReg: 21U },
6399 { .FromReg: X86::YMM1, .ToReg: 22U },
6400 { .FromReg: X86::YMM2, .ToReg: 23U },
6401 { .FromReg: X86::YMM3, .ToReg: 24U },
6402 { .FromReg: X86::YMM4, .ToReg: 25U },
6403 { .FromReg: X86::YMM5, .ToReg: 26U },
6404 { .FromReg: X86::YMM6, .ToReg: 27U },
6405 { .FromReg: X86::YMM7, .ToReg: 28U },
6406 { .FromReg: X86::YMM8, .ToReg: -2U },
6407 { .FromReg: X86::YMM9, .ToReg: -2U },
6408 { .FromReg: X86::YMM10, .ToReg: -2U },
6409 { .FromReg: X86::YMM11, .ToReg: -2U },
6410 { .FromReg: X86::YMM12, .ToReg: -2U },
6411 { .FromReg: X86::YMM13, .ToReg: -2U },
6412 { .FromReg: X86::YMM14, .ToReg: -2U },
6413 { .FromReg: X86::YMM15, .ToReg: -2U },
6414 { .FromReg: X86::K0, .ToReg: 93U },
6415 { .FromReg: X86::K1, .ToReg: 94U },
6416 { .FromReg: X86::K2, .ToReg: 95U },
6417 { .FromReg: X86::K3, .ToReg: 96U },
6418 { .FromReg: X86::K4, .ToReg: 97U },
6419 { .FromReg: X86::K5, .ToReg: 98U },
6420 { .FromReg: X86::K6, .ToReg: 99U },
6421 { .FromReg: X86::K7, .ToReg: 100U },
6422 { .FromReg: X86::XMM16, .ToReg: -2U },
6423 { .FromReg: X86::XMM17, .ToReg: -2U },
6424 { .FromReg: X86::XMM18, .ToReg: -2U },
6425 { .FromReg: X86::XMM19, .ToReg: -2U },
6426 { .FromReg: X86::XMM20, .ToReg: -2U },
6427 { .FromReg: X86::XMM21, .ToReg: -2U },
6428 { .FromReg: X86::XMM22, .ToReg: -2U },
6429 { .FromReg: X86::XMM23, .ToReg: -2U },
6430 { .FromReg: X86::XMM24, .ToReg: -2U },
6431 { .FromReg: X86::XMM25, .ToReg: -2U },
6432 { .FromReg: X86::XMM26, .ToReg: -2U },
6433 { .FromReg: X86::XMM27, .ToReg: -2U },
6434 { .FromReg: X86::XMM28, .ToReg: -2U },
6435 { .FromReg: X86::XMM29, .ToReg: -2U },
6436 { .FromReg: X86::XMM30, .ToReg: -2U },
6437 { .FromReg: X86::XMM31, .ToReg: -2U },
6438 { .FromReg: X86::YMM16, .ToReg: -2U },
6439 { .FromReg: X86::YMM17, .ToReg: -2U },
6440 { .FromReg: X86::YMM18, .ToReg: -2U },
6441 { .FromReg: X86::YMM19, .ToReg: -2U },
6442 { .FromReg: X86::YMM20, .ToReg: -2U },
6443 { .FromReg: X86::YMM21, .ToReg: -2U },
6444 { .FromReg: X86::YMM22, .ToReg: -2U },
6445 { .FromReg: X86::YMM23, .ToReg: -2U },
6446 { .FromReg: X86::YMM24, .ToReg: -2U },
6447 { .FromReg: X86::YMM25, .ToReg: -2U },
6448 { .FromReg: X86::YMM26, .ToReg: -2U },
6449 { .FromReg: X86::YMM27, .ToReg: -2U },
6450 { .FromReg: X86::YMM28, .ToReg: -2U },
6451 { .FromReg: X86::YMM29, .ToReg: -2U },
6452 { .FromReg: X86::YMM30, .ToReg: -2U },
6453 { .FromReg: X86::YMM31, .ToReg: -2U },
6454 { .FromReg: X86::ZMM0, .ToReg: 21U },
6455 { .FromReg: X86::ZMM1, .ToReg: 22U },
6456 { .FromReg: X86::ZMM2, .ToReg: 23U },
6457 { .FromReg: X86::ZMM3, .ToReg: 24U },
6458 { .FromReg: X86::ZMM4, .ToReg: 25U },
6459 { .FromReg: X86::ZMM5, .ToReg: 26U },
6460 { .FromReg: X86::ZMM6, .ToReg: 27U },
6461 { .FromReg: X86::ZMM7, .ToReg: 28U },
6462 { .FromReg: X86::ZMM8, .ToReg: -2U },
6463 { .FromReg: X86::ZMM9, .ToReg: -2U },
6464 { .FromReg: X86::ZMM10, .ToReg: -2U },
6465 { .FromReg: X86::ZMM11, .ToReg: -2U },
6466 { .FromReg: X86::ZMM12, .ToReg: -2U },
6467 { .FromReg: X86::ZMM13, .ToReg: -2U },
6468 { .FromReg: X86::ZMM14, .ToReg: -2U },
6469 { .FromReg: X86::ZMM15, .ToReg: -2U },
6470 { .FromReg: X86::ZMM16, .ToReg: -2U },
6471 { .FromReg: X86::ZMM17, .ToReg: -2U },
6472 { .FromReg: X86::ZMM18, .ToReg: -2U },
6473 { .FromReg: X86::ZMM19, .ToReg: -2U },
6474 { .FromReg: X86::ZMM20, .ToReg: -2U },
6475 { .FromReg: X86::ZMM21, .ToReg: -2U },
6476 { .FromReg: X86::ZMM22, .ToReg: -2U },
6477 { .FromReg: X86::ZMM23, .ToReg: -2U },
6478 { .FromReg: X86::ZMM24, .ToReg: -2U },
6479 { .FromReg: X86::ZMM25, .ToReg: -2U },
6480 { .FromReg: X86::ZMM26, .ToReg: -2U },
6481 { .FromReg: X86::ZMM27, .ToReg: -2U },
6482 { .FromReg: X86::ZMM28, .ToReg: -2U },
6483 { .FromReg: X86::ZMM29, .ToReg: -2U },
6484 { .FromReg: X86::ZMM30, .ToReg: -2U },
6485 { .FromReg: X86::ZMM31, .ToReg: -2U },
6486 { .FromReg: X86::R16, .ToReg: -2U },
6487 { .FromReg: X86::R17, .ToReg: -2U },
6488 { .FromReg: X86::R18, .ToReg: -2U },
6489 { .FromReg: X86::R19, .ToReg: -2U },
6490 { .FromReg: X86::R20, .ToReg: -2U },
6491 { .FromReg: X86::R21, .ToReg: -2U },
6492 { .FromReg: X86::R22, .ToReg: -2U },
6493 { .FromReg: X86::R23, .ToReg: -2U },
6494 { .FromReg: X86::R24, .ToReg: -2U },
6495 { .FromReg: X86::R25, .ToReg: -2U },
6496 { .FromReg: X86::R26, .ToReg: -2U },
6497 { .FromReg: X86::R27, .ToReg: -2U },
6498 { .FromReg: X86::R28, .ToReg: -2U },
6499 { .FromReg: X86::R29, .ToReg: -2U },
6500 { .FromReg: X86::R30, .ToReg: -2U },
6501 { .FromReg: X86::R31, .ToReg: -2U },
6502};
6503extern const unsigned X86EHFlavour1L2DwarfSize = std::size(X86EHFlavour1L2Dwarf);
6504
6505extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
6506 { .FromReg: X86::CS, .ToReg: 41U },
6507 { .FromReg: X86::DS, .ToReg: 43U },
6508 { .FromReg: X86::EAX, .ToReg: 0U },
6509 { .FromReg: X86::EBP, .ToReg: 5U },
6510 { .FromReg: X86::EBX, .ToReg: 3U },
6511 { .FromReg: X86::ECX, .ToReg: 1U },
6512 { .FromReg: X86::EDI, .ToReg: 7U },
6513 { .FromReg: X86::EDX, .ToReg: 2U },
6514 { .FromReg: X86::EFLAGS, .ToReg: 9U },
6515 { .FromReg: X86::EIP, .ToReg: 8U },
6516 { .FromReg: X86::ES, .ToReg: 40U },
6517 { .FromReg: X86::ESI, .ToReg: 6U },
6518 { .FromReg: X86::ESP, .ToReg: 4U },
6519 { .FromReg: X86::FS, .ToReg: 44U },
6520 { .FromReg: X86::FS_BASE, .ToReg: -2U },
6521 { .FromReg: X86::GS, .ToReg: 45U },
6522 { .FromReg: X86::GS_BASE, .ToReg: -2U },
6523 { .FromReg: X86::RAX, .ToReg: -2U },
6524 { .FromReg: X86::RBP, .ToReg: -2U },
6525 { .FromReg: X86::RBX, .ToReg: -2U },
6526 { .FromReg: X86::RCX, .ToReg: -2U },
6527 { .FromReg: X86::RDI, .ToReg: -2U },
6528 { .FromReg: X86::RDX, .ToReg: -2U },
6529 { .FromReg: X86::RFLAGS, .ToReg: -2U },
6530 { .FromReg: X86::RIP, .ToReg: -2U },
6531 { .FromReg: X86::RSI, .ToReg: -2U },
6532 { .FromReg: X86::RSP, .ToReg: -2U },
6533 { .FromReg: X86::SS, .ToReg: 42U },
6534 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
6535 { .FromReg: X86::MM0, .ToReg: 29U },
6536 { .FromReg: X86::MM1, .ToReg: 30U },
6537 { .FromReg: X86::MM2, .ToReg: 31U },
6538 { .FromReg: X86::MM3, .ToReg: 32U },
6539 { .FromReg: X86::MM4, .ToReg: 33U },
6540 { .FromReg: X86::MM5, .ToReg: 34U },
6541 { .FromReg: X86::MM6, .ToReg: 35U },
6542 { .FromReg: X86::MM7, .ToReg: 36U },
6543 { .FromReg: X86::R8, .ToReg: -2U },
6544 { .FromReg: X86::R9, .ToReg: -2U },
6545 { .FromReg: X86::R10, .ToReg: -2U },
6546 { .FromReg: X86::R11, .ToReg: -2U },
6547 { .FromReg: X86::R12, .ToReg: -2U },
6548 { .FromReg: X86::R13, .ToReg: -2U },
6549 { .FromReg: X86::R14, .ToReg: -2U },
6550 { .FromReg: X86::R15, .ToReg: -2U },
6551 { .FromReg: X86::ST0, .ToReg: 11U },
6552 { .FromReg: X86::ST1, .ToReg: 12U },
6553 { .FromReg: X86::ST2, .ToReg: 13U },
6554 { .FromReg: X86::ST3, .ToReg: 14U },
6555 { .FromReg: X86::ST4, .ToReg: 15U },
6556 { .FromReg: X86::ST5, .ToReg: 16U },
6557 { .FromReg: X86::ST6, .ToReg: 17U },
6558 { .FromReg: X86::ST7, .ToReg: 18U },
6559 { .FromReg: X86::XMM0, .ToReg: 21U },
6560 { .FromReg: X86::XMM1, .ToReg: 22U },
6561 { .FromReg: X86::XMM2, .ToReg: 23U },
6562 { .FromReg: X86::XMM3, .ToReg: 24U },
6563 { .FromReg: X86::XMM4, .ToReg: 25U },
6564 { .FromReg: X86::XMM5, .ToReg: 26U },
6565 { .FromReg: X86::XMM6, .ToReg: 27U },
6566 { .FromReg: X86::XMM7, .ToReg: 28U },
6567 { .FromReg: X86::XMM8, .ToReg: -2U },
6568 { .FromReg: X86::XMM9, .ToReg: -2U },
6569 { .FromReg: X86::XMM10, .ToReg: -2U },
6570 { .FromReg: X86::XMM11, .ToReg: -2U },
6571 { .FromReg: X86::XMM12, .ToReg: -2U },
6572 { .FromReg: X86::XMM13, .ToReg: -2U },
6573 { .FromReg: X86::XMM14, .ToReg: -2U },
6574 { .FromReg: X86::XMM15, .ToReg: -2U },
6575 { .FromReg: X86::YMM0, .ToReg: 21U },
6576 { .FromReg: X86::YMM1, .ToReg: 22U },
6577 { .FromReg: X86::YMM2, .ToReg: 23U },
6578 { .FromReg: X86::YMM3, .ToReg: 24U },
6579 { .FromReg: X86::YMM4, .ToReg: 25U },
6580 { .FromReg: X86::YMM5, .ToReg: 26U },
6581 { .FromReg: X86::YMM6, .ToReg: 27U },
6582 { .FromReg: X86::YMM7, .ToReg: 28U },
6583 { .FromReg: X86::YMM8, .ToReg: -2U },
6584 { .FromReg: X86::YMM9, .ToReg: -2U },
6585 { .FromReg: X86::YMM10, .ToReg: -2U },
6586 { .FromReg: X86::YMM11, .ToReg: -2U },
6587 { .FromReg: X86::YMM12, .ToReg: -2U },
6588 { .FromReg: X86::YMM13, .ToReg: -2U },
6589 { .FromReg: X86::YMM14, .ToReg: -2U },
6590 { .FromReg: X86::YMM15, .ToReg: -2U },
6591 { .FromReg: X86::K0, .ToReg: 93U },
6592 { .FromReg: X86::K1, .ToReg: 94U },
6593 { .FromReg: X86::K2, .ToReg: 95U },
6594 { .FromReg: X86::K3, .ToReg: 96U },
6595 { .FromReg: X86::K4, .ToReg: 97U },
6596 { .FromReg: X86::K5, .ToReg: 98U },
6597 { .FromReg: X86::K6, .ToReg: 99U },
6598 { .FromReg: X86::K7, .ToReg: 100U },
6599 { .FromReg: X86::XMM16, .ToReg: -2U },
6600 { .FromReg: X86::XMM17, .ToReg: -2U },
6601 { .FromReg: X86::XMM18, .ToReg: -2U },
6602 { .FromReg: X86::XMM19, .ToReg: -2U },
6603 { .FromReg: X86::XMM20, .ToReg: -2U },
6604 { .FromReg: X86::XMM21, .ToReg: -2U },
6605 { .FromReg: X86::XMM22, .ToReg: -2U },
6606 { .FromReg: X86::XMM23, .ToReg: -2U },
6607 { .FromReg: X86::XMM24, .ToReg: -2U },
6608 { .FromReg: X86::XMM25, .ToReg: -2U },
6609 { .FromReg: X86::XMM26, .ToReg: -2U },
6610 { .FromReg: X86::XMM27, .ToReg: -2U },
6611 { .FromReg: X86::XMM28, .ToReg: -2U },
6612 { .FromReg: X86::XMM29, .ToReg: -2U },
6613 { .FromReg: X86::XMM30, .ToReg: -2U },
6614 { .FromReg: X86::XMM31, .ToReg: -2U },
6615 { .FromReg: X86::YMM16, .ToReg: -2U },
6616 { .FromReg: X86::YMM17, .ToReg: -2U },
6617 { .FromReg: X86::YMM18, .ToReg: -2U },
6618 { .FromReg: X86::YMM19, .ToReg: -2U },
6619 { .FromReg: X86::YMM20, .ToReg: -2U },
6620 { .FromReg: X86::YMM21, .ToReg: -2U },
6621 { .FromReg: X86::YMM22, .ToReg: -2U },
6622 { .FromReg: X86::YMM23, .ToReg: -2U },
6623 { .FromReg: X86::YMM24, .ToReg: -2U },
6624 { .FromReg: X86::YMM25, .ToReg: -2U },
6625 { .FromReg: X86::YMM26, .ToReg: -2U },
6626 { .FromReg: X86::YMM27, .ToReg: -2U },
6627 { .FromReg: X86::YMM28, .ToReg: -2U },
6628 { .FromReg: X86::YMM29, .ToReg: -2U },
6629 { .FromReg: X86::YMM30, .ToReg: -2U },
6630 { .FromReg: X86::YMM31, .ToReg: -2U },
6631 { .FromReg: X86::ZMM0, .ToReg: 21U },
6632 { .FromReg: X86::ZMM1, .ToReg: 22U },
6633 { .FromReg: X86::ZMM2, .ToReg: 23U },
6634 { .FromReg: X86::ZMM3, .ToReg: 24U },
6635 { .FromReg: X86::ZMM4, .ToReg: 25U },
6636 { .FromReg: X86::ZMM5, .ToReg: 26U },
6637 { .FromReg: X86::ZMM6, .ToReg: 27U },
6638 { .FromReg: X86::ZMM7, .ToReg: 28U },
6639 { .FromReg: X86::ZMM8, .ToReg: -2U },
6640 { .FromReg: X86::ZMM9, .ToReg: -2U },
6641 { .FromReg: X86::ZMM10, .ToReg: -2U },
6642 { .FromReg: X86::ZMM11, .ToReg: -2U },
6643 { .FromReg: X86::ZMM12, .ToReg: -2U },
6644 { .FromReg: X86::ZMM13, .ToReg: -2U },
6645 { .FromReg: X86::ZMM14, .ToReg: -2U },
6646 { .FromReg: X86::ZMM15, .ToReg: -2U },
6647 { .FromReg: X86::ZMM16, .ToReg: -2U },
6648 { .FromReg: X86::ZMM17, .ToReg: -2U },
6649 { .FromReg: X86::ZMM18, .ToReg: -2U },
6650 { .FromReg: X86::ZMM19, .ToReg: -2U },
6651 { .FromReg: X86::ZMM20, .ToReg: -2U },
6652 { .FromReg: X86::ZMM21, .ToReg: -2U },
6653 { .FromReg: X86::ZMM22, .ToReg: -2U },
6654 { .FromReg: X86::ZMM23, .ToReg: -2U },
6655 { .FromReg: X86::ZMM24, .ToReg: -2U },
6656 { .FromReg: X86::ZMM25, .ToReg: -2U },
6657 { .FromReg: X86::ZMM26, .ToReg: -2U },
6658 { .FromReg: X86::ZMM27, .ToReg: -2U },
6659 { .FromReg: X86::ZMM28, .ToReg: -2U },
6660 { .FromReg: X86::ZMM29, .ToReg: -2U },
6661 { .FromReg: X86::ZMM30, .ToReg: -2U },
6662 { .FromReg: X86::ZMM31, .ToReg: -2U },
6663 { .FromReg: X86::R16, .ToReg: -2U },
6664 { .FromReg: X86::R17, .ToReg: -2U },
6665 { .FromReg: X86::R18, .ToReg: -2U },
6666 { .FromReg: X86::R19, .ToReg: -2U },
6667 { .FromReg: X86::R20, .ToReg: -2U },
6668 { .FromReg: X86::R21, .ToReg: -2U },
6669 { .FromReg: X86::R22, .ToReg: -2U },
6670 { .FromReg: X86::R23, .ToReg: -2U },
6671 { .FromReg: X86::R24, .ToReg: -2U },
6672 { .FromReg: X86::R25, .ToReg: -2U },
6673 { .FromReg: X86::R26, .ToReg: -2U },
6674 { .FromReg: X86::R27, .ToReg: -2U },
6675 { .FromReg: X86::R28, .ToReg: -2U },
6676 { .FromReg: X86::R29, .ToReg: -2U },
6677 { .FromReg: X86::R30, .ToReg: -2U },
6678 { .FromReg: X86::R31, .ToReg: -2U },
6679};
6680extern const unsigned X86EHFlavour2L2DwarfSize = std::size(X86EHFlavour2L2Dwarf);
6681
6682extern const uint16_t X86RegEncodingTable[] = {
6683 0,
6684 4,
6685 0,
6686 0,
6687 7,
6688 3,
6689 5,
6690 65535,
6691 5,
6692 3,
6693 5,
6694 1,
6695 1,
6696 1,
6697 0,
6698 6,
6699 7,
6700 65535,
6701 7,
6702 2,
6703 3,
6704 2,
6705 0,
6706 5,
6707 3,
6708 1,
6709 7,
6710 2,
6711 0,
6712 0,
6713 4,
6714 0,
6715 6,
6716 4,
6717 0,
6718 0,
6719 4,
6720 0,
6721 5,
6722 0,
6723 65535,
6724 65535,
6725 65535,
6726 65535,
6727 65535,
6728 65535,
6729 65535,
6730 65535,
6731 65535,
6732 0,
6733 0,
6734 0,
6735 5,
6736 3,
6737 1,
6738 7,
6739 2,
6740 0,
6741 0,
6742 4,
6743 6,
6744 4,
6745 6,
6746 65535,
6747 6,
6748 4,
6749 65535,
6750 4,
6751 2,
6752 0,
6753 0,
6754 0,
6755 1,
6756 2,
6757 3,
6758 4,
6759 5,
6760 6,
6761 7,
6762 8,
6763 9,
6764 10,
6765 11,
6766 12,
6767 13,
6768 14,
6769 15,
6770 0,
6771 1,
6772 2,
6773 3,
6774 4,
6775 5,
6776 6,
6777 7,
6778 8,
6779 9,
6780 10,
6781 11,
6782 12,
6783 13,
6784 14,
6785 15,
6786 0,
6787 0,
6788 0,
6789 0,
6790 0,
6791 0,
6792 0,
6793 0,
6794 0,
6795 1,
6796 2,
6797 3,
6798 4,
6799 5,
6800 6,
6801 7,
6802 8,
6803 9,
6804 10,
6805 11,
6806 12,
6807 13,
6808 14,
6809 15,
6810 0,
6811 1,
6812 2,
6813 3,
6814 4,
6815 5,
6816 6,
6817 7,
6818 0,
6819 1,
6820 2,
6821 3,
6822 4,
6823 5,
6824 6,
6825 7,
6826 8,
6827 9,
6828 10,
6829 11,
6830 12,
6831 13,
6832 14,
6833 15,
6834 8,
6835 9,
6836 10,
6837 11,
6838 12,
6839 13,
6840 14,
6841 15,
6842 65535,
6843 65535,
6844 65535,
6845 65535,
6846 65535,
6847 65535,
6848 65535,
6849 65535,
6850 8,
6851 9,
6852 10,
6853 11,
6854 12,
6855 13,
6856 14,
6857 15,
6858 8,
6859 9,
6860 10,
6861 11,
6862 12,
6863 13,
6864 14,
6865 15,
6866 65535,
6867 65535,
6868 65535,
6869 65535,
6870 65535,
6871 65535,
6872 65535,
6873 65535,
6874 0,
6875 1,
6876 2,
6877 3,
6878 4,
6879 5,
6880 6,
6881 7,
6882 8,
6883 9,
6884 10,
6885 11,
6886 12,
6887 13,
6888 14,
6889 15,
6890 0,
6891 1,
6892 2,
6893 3,
6894 4,
6895 5,
6896 6,
6897 7,
6898 16,
6899 17,
6900 18,
6901 19,
6902 20,
6903 21,
6904 22,
6905 23,
6906 24,
6907 25,
6908 26,
6909 27,
6910 28,
6911 29,
6912 30,
6913 31,
6914 16,
6915 17,
6916 18,
6917 19,
6918 20,
6919 21,
6920 22,
6921 23,
6922 24,
6923 25,
6924 26,
6925 27,
6926 28,
6927 29,
6928 30,
6929 31,
6930 0,
6931 1,
6932 2,
6933 3,
6934 4,
6935 5,
6936 6,
6937 7,
6938 8,
6939 9,
6940 10,
6941 11,
6942 12,
6943 13,
6944 14,
6945 15,
6946 16,
6947 17,
6948 18,
6949 19,
6950 20,
6951 21,
6952 22,
6953 23,
6954 24,
6955 25,
6956 26,
6957 27,
6958 28,
6959 29,
6960 30,
6961 31,
6962 0,
6963 2,
6964 4,
6965 6,
6966 0,
6967 0,
6968 1,
6969 2,
6970 3,
6971 4,
6972 5,
6973 6,
6974 7,
6975 16,
6976 17,
6977 18,
6978 19,
6979 20,
6980 21,
6981 22,
6982 23,
6983 24,
6984 25,
6985 26,
6986 27,
6987 28,
6988 29,
6989 30,
6990 31,
6991 16,
6992 17,
6993 18,
6994 19,
6995 20,
6996 21,
6997 22,
6998 23,
6999 24,
7000 25,
7001 26,
7002 27,
7003 28,
7004 29,
7005 30,
7006 31,
7007 65535,
7008 65535,
7009 65535,
7010 65535,
7011 65535,
7012 65535,
7013 65535,
7014 65535,
7015 65535,
7016 65535,
7017 65535,
7018 65535,
7019 65535,
7020 65535,
7021 65535,
7022 65535,
7023 16,
7024 17,
7025 18,
7026 19,
7027 20,
7028 21,
7029 22,
7030 23,
7031 24,
7032 25,
7033 26,
7034 27,
7035 28,
7036 29,
7037 30,
7038 31,
7039 16,
7040 17,
7041 18,
7042 19,
7043 20,
7044 21,
7045 22,
7046 23,
7047 24,
7048 25,
7049 26,
7050 27,
7051 28,
7052 29,
7053 30,
7054 31,
7055 65535,
7056 65535,
7057 65535,
7058 65535,
7059 65535,
7060 65535,
7061 65535,
7062 65535,
7063 65535,
7064 65535,
7065 65535,
7066 65535,
7067 65535,
7068 65535,
7069 65535,
7070 65535,
7071};
7072static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
7073 RI->InitMCRegisterInfo(D: X86RegDesc, NR: 388, RA, PC, C: X86MCRegisterClassStorage.Classes, NC: 135, RURoots: X86RegUnitRoots, NRU: 221, DL: X86RegDiffLists, RUMS: X86LaneMaskLists, Strings: X86RegStrings, ClassStrings: X86RegClassStrings, SubIndices: X86SubRegIdxLists, NumIndices: 11,
7074RET: X86RegEncodingTable, RUI: nullptr);
7075
7076 switch (DwarfFlavour) {
7077 default:
7078 llvm_unreachable("Unknown DWARF flavour");
7079 case 0:
7080 RI->mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour0Dwarf2L, Size: X86DwarfFlavour0Dwarf2LSize, isEH: false);
7081 break;
7082 case 1:
7083 RI->mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour1Dwarf2L, Size: X86DwarfFlavour1Dwarf2LSize, isEH: false);
7084 break;
7085 case 2:
7086 RI->mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour2Dwarf2L, Size: X86DwarfFlavour2Dwarf2LSize, isEH: false);
7087 break;
7088 }
7089 switch (EHFlavour) {
7090 default:
7091 llvm_unreachable("Unknown DWARF flavour");
7092 case 0:
7093 RI->mapDwarfRegsToLLVMRegs(Map: X86EHFlavour0Dwarf2L, Size: X86EHFlavour0Dwarf2LSize, isEH: true);
7094 break;
7095 case 1:
7096 RI->mapDwarfRegsToLLVMRegs(Map: X86EHFlavour1Dwarf2L, Size: X86EHFlavour1Dwarf2LSize, isEH: true);
7097 break;
7098 case 2:
7099 RI->mapDwarfRegsToLLVMRegs(Map: X86EHFlavour2Dwarf2L, Size: X86EHFlavour2Dwarf2LSize, isEH: true);
7100 break;
7101 }
7102 switch (DwarfFlavour) {
7103 default:
7104 llvm_unreachable("Unknown DWARF flavour");
7105 case 0:
7106 RI->mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour0L2Dwarf, Size: X86DwarfFlavour0L2DwarfSize, isEH: false);
7107 break;
7108 case 1:
7109 RI->mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour1L2Dwarf, Size: X86DwarfFlavour1L2DwarfSize, isEH: false);
7110 break;
7111 case 2:
7112 RI->mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour2L2Dwarf, Size: X86DwarfFlavour2L2DwarfSize, isEH: false);
7113 break;
7114 }
7115 switch (EHFlavour) {
7116 default:
7117 llvm_unreachable("Unknown DWARF flavour");
7118 case 0:
7119 RI->mapLLVMRegsToDwarfRegs(Map: X86EHFlavour0L2Dwarf, Size: X86EHFlavour0L2DwarfSize, isEH: true);
7120 break;
7121 case 1:
7122 RI->mapLLVMRegsToDwarfRegs(Map: X86EHFlavour1L2Dwarf, Size: X86EHFlavour1L2DwarfSize, isEH: true);
7123 break;
7124 case 2:
7125 RI->mapLLVMRegsToDwarfRegs(Map: X86EHFlavour2L2Dwarf, Size: X86EHFlavour2L2DwarfSize, isEH: true);
7126 break;
7127 }
7128}
7129
7130
7131} // namespace llvm
7132