1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t X86RegDiffLists[] = {
12 /* 0 */ -56, -56, 0,
13 /* 3 */ -32, -48, 0,
14 /* 6 */ 32, -16, -48, 0,
15 /* 10 */ 48, -16, -48, 0,
16 /* 14 */ 16, -8, -48, 0,
17 /* 18 */ 24, -8, -48, 0,
18 /* 22 */ -28, 32, 2, -1, -18, 0,
19 /* 28 */ -32, -16, 0,
20 /* 31 */ -28, 30, 2, -1, -16, 0,
21 /* 37 */ -2, -4, 0,
22 /* 40 */ -29, 20, -3, 0,
23 /* 44 */ -4, -1, 0,
24 /* 47 */ -2, -1, 0,
25 /* 50 */ -1, -1, 0,
26 /* 53 */ 2, -1, 0,
27 /* 56 */ -72, 1, 0,
28 /* 59 */ -71, 1, 0,
29 /* 62 */ -70, 1, 0,
30 /* 65 */ -69, 1, 0,
31 /* 68 */ 1, 1, 0,
32 /* 71 */ 3, 0,
33 /* 73 */ 1, 7, 0,
34 /* 76 */ 3, 7, 0,
35 /* 79 */ -24, 8, 0,
36 /* 82 */ 1, 11, 0,
37 /* 85 */ 1, 14, 0,
38 /* 88 */ -48, 16, 0,
39 /* 91 */ 48, 8, -24, 8, 24, 0,
40 /* 97 */ -29, -10, 2, -1, 27, 0,
41 /* 103 */ -2, -32, 28, 0,
42 /* 107 */ -1, -32, 28, 0,
43 /* 111 */ -2, -30, 28, 0,
44 /* 115 */ -1, -30, 28, 0,
45 /* 119 */ -15, 28, 0,
46 /* 122 */ -20, 29, 0,
47 /* 125 */ -18, 29, 0,
48 /* 128 */ -17, 29, 0,
49 /* 131 */ 2, 6, 29, 0,
50 /* 135 */ 6, 6, 29, 0,
51 /* 139 */ -2, 10, 29, 0,
52 /* 143 */ -1, 10, 29, 0,
53 /* 147 */ 2, 12, 29, 0,
54 /* 151 */ 3, 12, 29, 0,
55 /* 155 */ 4, 15, 29, 0,
56 /* 159 */ 5, 15, 29, 0,
57 /* 163 */ -2, 17, 29, 0,
58 /* 167 */ -1, 17, 29, 0,
59 /* 171 */ 1, 19, 29, 0,
60 /* 175 */ 2, 19, 29, 0,
61 /* 179 */ -29, -6, -2, -4, 30, 0,
62 /* 185 */ 16, 32, 0,
63 /* 188 */ -29, -12, -2, -1, 33, 0,
64 /* 194 */ -29, -17, 2, -1, 34, 0,
65 /* 200 */ -29, -15, -4, -1, 38, 0,
66 /* 206 */ -29, -19, -1, -1, 39, 0,
67 /* 212 */ 48, 16, -48, 16, 48, 0,
68 /* 218 */ 56, 56, 0,
69 /* 221 */ 68, 0,
70 /* 223 */ 69, 0,
71 /* 225 */ 70, 0,
72 /* 227 */ 71, 0,
73 /* 229 */ 72, 0,
74};
75
76extern const LaneBitmask X86LaneMaskLists[] = {
77 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
78 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004),
79 /* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000008),
80 /* 7 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
81 /* 10 */ LaneBitmask(0x0000000000000007), LaneBitmask(0x0000000000000008),
82 /* 12 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020),
83 /* 14 */ LaneBitmask(0x0000000000000040),
84 /* 15 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
85};
86
87extern const uint16_t X86SubRegIdxLists[] = {
88 /* 0 */ 1, 2,
89 /* 2 */ 1, 3,
90 /* 4 */ 6, 4, 1, 2, 5,
91 /* 9 */ 6, 4, 1, 3, 5,
92 /* 14 */ 6, 4, 5,
93 /* 17 */ 7, 8,
94 /* 19 */ 10, 9,
95};
96
97
98#ifdef __GNUC__
99#pragma GCC diagnostic push
100#pragma GCC diagnostic ignored "-Woverlength-strings"
101#endif
102extern const char X86RegStrings[] = {
103 /* 0 */ "XMM10\000"
104 /* 6 */ "YMM10\000"
105 /* 12 */ "ZMM10\000"
106 /* 18 */ "CR10\000"
107 /* 23 */ "DR10\000"
108 /* 28 */ "XMM20\000"
109 /* 34 */ "YMM20\000"
110 /* 40 */ "ZMM20\000"
111 /* 46 */ "R20\000"
112 /* 50 */ "XMM30\000"
113 /* 56 */ "YMM30\000"
114 /* 62 */ "ZMM30\000"
115 /* 68 */ "R30\000"
116 /* 72 */ "K0\000"
117 /* 75 */ "TMM0\000"
118 /* 80 */ "XMM0\000"
119 /* 85 */ "YMM0\000"
120 /* 90 */ "ZMM0\000"
121 /* 95 */ "FP0\000"
122 /* 99 */ "CR0\000"
123 /* 103 */ "DR0\000"
124 /* 107 */ "ST0\000"
125 /* 111 */ "XMM11\000"
126 /* 117 */ "YMM11\000"
127 /* 123 */ "ZMM11\000"
128 /* 129 */ "CR11\000"
129 /* 134 */ "DR11\000"
130 /* 139 */ "XMM21\000"
131 /* 145 */ "YMM21\000"
132 /* 151 */ "ZMM21\000"
133 /* 157 */ "R21\000"
134 /* 161 */ "XMM31\000"
135 /* 167 */ "YMM31\000"
136 /* 173 */ "ZMM31\000"
137 /* 179 */ "R31\000"
138 /* 183 */ "K0_K1\000"
139 /* 189 */ "TMM1\000"
140 /* 194 */ "XMM1\000"
141 /* 199 */ "YMM1\000"
142 /* 204 */ "ZMM1\000"
143 /* 209 */ "FP1\000"
144 /* 213 */ "CR1\000"
145 /* 217 */ "DR1\000"
146 /* 221 */ "ST1\000"
147 /* 225 */ "XMM12\000"
148 /* 231 */ "YMM12\000"
149 /* 237 */ "ZMM12\000"
150 /* 243 */ "CR12\000"
151 /* 248 */ "DR12\000"
152 /* 253 */ "XMM22\000"
153 /* 259 */ "YMM22\000"
154 /* 265 */ "ZMM22\000"
155 /* 271 */ "R22\000"
156 /* 275 */ "K2\000"
157 /* 278 */ "TMM2\000"
158 /* 283 */ "XMM2\000"
159 /* 288 */ "YMM2\000"
160 /* 293 */ "ZMM2\000"
161 /* 298 */ "FP2\000"
162 /* 302 */ "CR2\000"
163 /* 306 */ "DR2\000"
164 /* 310 */ "ST2\000"
165 /* 314 */ "XMM13\000"
166 /* 320 */ "YMM13\000"
167 /* 326 */ "ZMM13\000"
168 /* 332 */ "CR13\000"
169 /* 337 */ "DR13\000"
170 /* 342 */ "XMM23\000"
171 /* 348 */ "YMM23\000"
172 /* 354 */ "ZMM23\000"
173 /* 360 */ "R23\000"
174 /* 364 */ "K2_K3\000"
175 /* 370 */ "TMM3\000"
176 /* 375 */ "XMM3\000"
177 /* 380 */ "YMM3\000"
178 /* 385 */ "ZMM3\000"
179 /* 390 */ "FP3\000"
180 /* 394 */ "CR3\000"
181 /* 398 */ "DR3\000"
182 /* 402 */ "ST3\000"
183 /* 406 */ "XMM14\000"
184 /* 412 */ "YMM14\000"
185 /* 418 */ "ZMM14\000"
186 /* 424 */ "CR14\000"
187 /* 429 */ "DR14\000"
188 /* 434 */ "XMM24\000"
189 /* 440 */ "YMM24\000"
190 /* 446 */ "ZMM24\000"
191 /* 452 */ "R24\000"
192 /* 456 */ "K4\000"
193 /* 459 */ "TMM4\000"
194 /* 464 */ "XMM4\000"
195 /* 469 */ "YMM4\000"
196 /* 474 */ "ZMM4\000"
197 /* 479 */ "FP4\000"
198 /* 483 */ "CR4\000"
199 /* 487 */ "DR4\000"
200 /* 491 */ "ST4\000"
201 /* 495 */ "XMM15\000"
202 /* 501 */ "YMM15\000"
203 /* 507 */ "ZMM15\000"
204 /* 513 */ "CR15\000"
205 /* 518 */ "DR15\000"
206 /* 523 */ "XMM25\000"
207 /* 529 */ "YMM25\000"
208 /* 535 */ "ZMM25\000"
209 /* 541 */ "R25\000"
210 /* 545 */ "K4_K5\000"
211 /* 551 */ "TMM5\000"
212 /* 556 */ "XMM5\000"
213 /* 561 */ "YMM5\000"
214 /* 566 */ "ZMM5\000"
215 /* 571 */ "FP5\000"
216 /* 575 */ "CR5\000"
217 /* 579 */ "DR5\000"
218 /* 583 */ "ST5\000"
219 /* 587 */ "XMM16\000"
220 /* 593 */ "YMM16\000"
221 /* 599 */ "ZMM16\000"
222 /* 605 */ "R16\000"
223 /* 609 */ "XMM26\000"
224 /* 615 */ "YMM26\000"
225 /* 621 */ "ZMM26\000"
226 /* 627 */ "R26\000"
227 /* 631 */ "K6\000"
228 /* 634 */ "TMM6\000"
229 /* 639 */ "XMM6\000"
230 /* 644 */ "YMM6\000"
231 /* 649 */ "ZMM6\000"
232 /* 654 */ "FP6\000"
233 /* 658 */ "CR6\000"
234 /* 662 */ "DR6\000"
235 /* 666 */ "ST6\000"
236 /* 670 */ "XMM17\000"
237 /* 676 */ "YMM17\000"
238 /* 682 */ "ZMM17\000"
239 /* 688 */ "R17\000"
240 /* 692 */ "XMM27\000"
241 /* 698 */ "YMM27\000"
242 /* 704 */ "ZMM27\000"
243 /* 710 */ "R27\000"
244 /* 714 */ "K6_K7\000"
245 /* 720 */ "TMM7\000"
246 /* 725 */ "XMM7\000"
247 /* 730 */ "YMM7\000"
248 /* 735 */ "ZMM7\000"
249 /* 740 */ "FP7\000"
250 /* 744 */ "CR7\000"
251 /* 748 */ "DR7\000"
252 /* 752 */ "ST7\000"
253 /* 756 */ "XMM18\000"
254 /* 762 */ "YMM18\000"
255 /* 768 */ "ZMM18\000"
256 /* 774 */ "R18\000"
257 /* 778 */ "XMM28\000"
258 /* 784 */ "YMM28\000"
259 /* 790 */ "ZMM28\000"
260 /* 796 */ "R28\000"
261 /* 800 */ "XMM8\000"
262 /* 805 */ "YMM8\000"
263 /* 810 */ "ZMM8\000"
264 /* 815 */ "CR8\000"
265 /* 819 */ "DR8\000"
266 /* 823 */ "XMM19\000"
267 /* 829 */ "YMM19\000"
268 /* 835 */ "ZMM19\000"
269 /* 841 */ "R19\000"
270 /* 845 */ "XMM29\000"
271 /* 851 */ "YMM29\000"
272 /* 857 */ "ZMM29\000"
273 /* 863 */ "R29\000"
274 /* 867 */ "XMM9\000"
275 /* 872 */ "YMM9\000"
276 /* 877 */ "ZMM9\000"
277 /* 882 */ "CR9\000"
278 /* 886 */ "DR9\000"
279 /* 890 */ "R10B\000"
280 /* 895 */ "R20B\000"
281 /* 900 */ "R30B\000"
282 /* 905 */ "R11B\000"
283 /* 910 */ "R21B\000"
284 /* 915 */ "R31B\000"
285 /* 920 */ "R12B\000"
286 /* 925 */ "R22B\000"
287 /* 930 */ "R13B\000"
288 /* 935 */ "R23B\000"
289 /* 940 */ "R14B\000"
290 /* 945 */ "R24B\000"
291 /* 950 */ "R15B\000"
292 /* 955 */ "R25B\000"
293 /* 960 */ "R16B\000"
294 /* 965 */ "R26B\000"
295 /* 970 */ "R17B\000"
296 /* 975 */ "R27B\000"
297 /* 980 */ "R18B\000"
298 /* 985 */ "R28B\000"
299 /* 990 */ "R8B\000"
300 /* 994 */ "R19B\000"
301 /* 999 */ "R29B\000"
302 /* 1004 */ "R9B\000"
303 /* 1008 */ "R10D\000"
304 /* 1013 */ "R20D\000"
305 /* 1018 */ "R30D\000"
306 /* 1023 */ "R11D\000"
307 /* 1028 */ "R21D\000"
308 /* 1033 */ "R31D\000"
309 /* 1038 */ "R12D\000"
310 /* 1043 */ "R22D\000"
311 /* 1048 */ "R13D\000"
312 /* 1053 */ "R23D\000"
313 /* 1058 */ "R14D\000"
314 /* 1063 */ "R24D\000"
315 /* 1068 */ "R15D\000"
316 /* 1073 */ "R25D\000"
317 /* 1078 */ "R16D\000"
318 /* 1083 */ "R26D\000"
319 /* 1088 */ "R17D\000"
320 /* 1093 */ "R27D\000"
321 /* 1098 */ "R18D\000"
322 /* 1103 */ "R28D\000"
323 /* 1108 */ "R8D\000"
324 /* 1112 */ "R19D\000"
325 /* 1117 */ "R29D\000"
326 /* 1122 */ "R9D\000"
327 /* 1126 */ "FS_BASE\000"
328 /* 1134 */ "GS_BASE\000"
329 /* 1142 */ "DF\000"
330 /* 1145 */ "TMMCFG\000"
331 /* 1152 */ "AH\000"
332 /* 1155 */ "R10BH\000"
333 /* 1161 */ "R20BH\000"
334 /* 1167 */ "R30BH\000"
335 /* 1173 */ "R11BH\000"
336 /* 1179 */ "R21BH\000"
337 /* 1185 */ "R31BH\000"
338 /* 1191 */ "R12BH\000"
339 /* 1197 */ "R22BH\000"
340 /* 1203 */ "R13BH\000"
341 /* 1209 */ "R23BH\000"
342 /* 1215 */ "R14BH\000"
343 /* 1221 */ "R24BH\000"
344 /* 1227 */ "R15BH\000"
345 /* 1233 */ "R25BH\000"
346 /* 1239 */ "R16BH\000"
347 /* 1245 */ "R26BH\000"
348 /* 1251 */ "R17BH\000"
349 /* 1257 */ "R27BH\000"
350 /* 1263 */ "R18BH\000"
351 /* 1269 */ "R28BH\000"
352 /* 1275 */ "R8BH\000"
353 /* 1280 */ "R19BH\000"
354 /* 1286 */ "R29BH\000"
355 /* 1292 */ "R9BH\000"
356 /* 1297 */ "CH\000"
357 /* 1300 */ "DH\000"
358 /* 1303 */ "DIH\000"
359 /* 1307 */ "SIH\000"
360 /* 1311 */ "BPH\000"
361 /* 1315 */ "SPH\000"
362 /* 1319 */ "R10WH\000"
363 /* 1325 */ "R20WH\000"
364 /* 1331 */ "R30WH\000"
365 /* 1337 */ "R11WH\000"
366 /* 1343 */ "R21WH\000"
367 /* 1349 */ "R31WH\000"
368 /* 1355 */ "R12WH\000"
369 /* 1361 */ "R22WH\000"
370 /* 1367 */ "R13WH\000"
371 /* 1373 */ "R23WH\000"
372 /* 1379 */ "R14WH\000"
373 /* 1385 */ "R24WH\000"
374 /* 1391 */ "R15WH\000"
375 /* 1397 */ "R25WH\000"
376 /* 1403 */ "R16WH\000"
377 /* 1409 */ "R26WH\000"
378 /* 1415 */ "R17WH\000"
379 /* 1421 */ "R27WH\000"
380 /* 1427 */ "R18WH\000"
381 /* 1433 */ "R28WH\000"
382 /* 1439 */ "R8WH\000"
383 /* 1444 */ "R19WH\000"
384 /* 1450 */ "R29WH\000"
385 /* 1456 */ "R9WH\000"
386 /* 1461 */ "EDI\000"
387 /* 1465 */ "HDI\000"
388 /* 1469 */ "RDI\000"
389 /* 1473 */ "ESI\000"
390 /* 1477 */ "HSI\000"
391 /* 1481 */ "RSI\000"
392 /* 1485 */ "AL\000"
393 /* 1488 */ "BL\000"
394 /* 1491 */ "CL\000"
395 /* 1494 */ "DL\000"
396 /* 1497 */ "DIL\000"
397 /* 1501 */ "SIL\000"
398 /* 1505 */ "BPL\000"
399 /* 1509 */ "SPL\000"
400 /* 1513 */ "EBP\000"
401 /* 1517 */ "HBP\000"
402 /* 1521 */ "RBP\000"
403 /* 1525 */ "EIP\000"
404 /* 1529 */ "HIP\000"
405 /* 1533 */ "RIP\000"
406 /* 1537 */ "ESP\000"
407 /* 1541 */ "HSP\000"
408 /* 1545 */ "RSP\000"
409 /* 1549 */ "SSP\000"
410 /* 1553 */ "MXCSR\000"
411 /* 1559 */ "CS\000"
412 /* 1562 */ "DS\000"
413 /* 1565 */ "ES\000"
414 /* 1568 */ "FS\000"
415 /* 1571 */ "_EFLAGS\000"
416 /* 1579 */ "RFLAGS\000"
417 /* 1586 */ "SS\000"
418 /* 1589 */ "R10W\000"
419 /* 1594 */ "R20W\000"
420 /* 1599 */ "R30W\000"
421 /* 1604 */ "R11W\000"
422 /* 1609 */ "R21W\000"
423 /* 1614 */ "R31W\000"
424 /* 1619 */ "R12W\000"
425 /* 1624 */ "R22W\000"
426 /* 1629 */ "R13W\000"
427 /* 1634 */ "R23W\000"
428 /* 1639 */ "R14W\000"
429 /* 1644 */ "R24W\000"
430 /* 1649 */ "R15W\000"
431 /* 1654 */ "R25W\000"
432 /* 1659 */ "R16W\000"
433 /* 1664 */ "R26W\000"
434 /* 1669 */ "R17W\000"
435 /* 1674 */ "R27W\000"
436 /* 1679 */ "R18W\000"
437 /* 1684 */ "R28W\000"
438 /* 1689 */ "R8W\000"
439 /* 1693 */ "R19W\000"
440 /* 1698 */ "R29W\000"
441 /* 1703 */ "R9W\000"
442 /* 1707 */ "FPCW\000"
443 /* 1712 */ "FPSW\000"
444 /* 1717 */ "EAX\000"
445 /* 1721 */ "HAX\000"
446 /* 1725 */ "RAX\000"
447 /* 1729 */ "EBX\000"
448 /* 1733 */ "HBX\000"
449 /* 1737 */ "RBX\000"
450 /* 1741 */ "ECX\000"
451 /* 1745 */ "HCX\000"
452 /* 1749 */ "RCX\000"
453 /* 1753 */ "EDX\000"
454 /* 1757 */ "HDX\000"
455 /* 1761 */ "RDX\000"
456 /* 1765 */ "EIZ\000"
457 /* 1769 */ "RIZ\000"
458};
459#ifdef __GNUC__
460#pragma GCC diagnostic pop
461#endif
462
463extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
464 { .Name: 5, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
465 { .Name: 1152, .SubRegs: 2, .SuperRegs: 175, .SubRegIndices: 2, .RegUnits: 8192, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
466 { .Name: 1485, .SubRegs: 2, .SuperRegs: 171, .SubRegIndices: 2, .RegUnits: 8193, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
467 { .Name: 1718, .SubRegs: 50, .SuperRegs: 172, .SubRegIndices: 0, .RegUnits: 233472, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
468 { .Name: 1158, .SubRegs: 2, .SuperRegs: 159, .SubRegIndices: 2, .RegUnits: 8194, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
469 { .Name: 1488, .SubRegs: 2, .SuperRegs: 155, .SubRegIndices: 2, .RegUnits: 8195, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
470 { .Name: 1514, .SubRegs: 53, .SuperRegs: 164, .SubRegIndices: 2, .RegUnits: 233476, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
471 { .Name: 1311, .SubRegs: 2, .SuperRegs: 167, .SubRegIndices: 2, .RegUnits: 8197, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
472 { .Name: 1505, .SubRegs: 2, .SuperRegs: 163, .SubRegIndices: 2, .RegUnits: 8196, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
473 { .Name: 1730, .SubRegs: 44, .SuperRegs: 156, .SubRegIndices: 0, .RegUnits: 233474, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
474 { .Name: 1297, .SubRegs: 2, .SuperRegs: 151, .SubRegIndices: 2, .RegUnits: 8198, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
475 { .Name: 1491, .SubRegs: 2, .SuperRegs: 147, .SubRegIndices: 2, .RegUnits: 8199, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
476 { .Name: 1559, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8200, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
477 { .Name: 1742, .SubRegs: 47, .SuperRegs: 148, .SubRegIndices: 0, .RegUnits: 233478, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
478 { .Name: 1142, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8201, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
479 { .Name: 1300, .SubRegs: 2, .SuperRegs: 135, .SubRegIndices: 2, .RegUnits: 8202, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
480 { .Name: 1462, .SubRegs: 53, .SuperRegs: 140, .SubRegIndices: 2, .RegUnits: 233483, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
481 { .Name: 1303, .SubRegs: 2, .SuperRegs: 143, .SubRegIndices: 2, .RegUnits: 8204, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
482 { .Name: 1497, .SubRegs: 2, .SuperRegs: 139, .SubRegIndices: 2, .RegUnits: 8203, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
483 { .Name: 1494, .SubRegs: 2, .SuperRegs: 131, .SubRegIndices: 2, .RegUnits: 8205, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
484 { .Name: 1562, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8206, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
485 { .Name: 1754, .SubRegs: 37, .SuperRegs: 132, .SubRegIndices: 0, .RegUnits: 290826, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
486 { .Name: 1717, .SubRegs: 207, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 348160, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
487 { .Name: 1513, .SubRegs: 195, .SuperRegs: 123, .SubRegIndices: 10, .RegUnits: 335876, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
488 { .Name: 1729, .SubRegs: 201, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 348162, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
489 { .Name: 1741, .SubRegs: 189, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 335878, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
490 { .Name: 1461, .SubRegs: 98, .SuperRegs: 123, .SubRegIndices: 10, .RegUnits: 299019, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
491 { .Name: 1753, .SubRegs: 180, .SuperRegs: 123, .SubRegIndices: 5, .RegUnits: 311306, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
492 { .Name: 1572, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8213, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
493 { .Name: 1525, .SubRegs: 41, .SuperRegs: 123, .SubRegIndices: 15, .RegUnits: 233494, .RegUnitLaneMasks: 10, .IsConstant: 0, .IsArtificial: 0 },
494 { .Name: 1765, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8216, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
495 { .Name: 1565, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8217, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
496 { .Name: 1473, .SubRegs: 32, .SuperRegs: 105, .SubRegIndices: 10, .RegUnits: 278554, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
497 { .Name: 1537, .SubRegs: 23, .SuperRegs: 105, .SubRegIndices: 10, .RegUnits: 278557, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
498 { .Name: 1707, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8224, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
499 { .Name: 1712, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8225, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
500 { .Name: 1568, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8226, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
501 { .Name: 1126, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8227, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
502 { .Name: 1576, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8228, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
503 { .Name: 1134, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8229, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
504 { .Name: 1721, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8207, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
505 { .Name: 1517, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8208, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
506 { .Name: 1733, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8209, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
507 { .Name: 1745, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8210, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
508 { .Name: 1465, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8211, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
509 { .Name: 1757, .SubRegs: 2, .SuperRegs: 125, .SubRegIndices: 2, .RegUnits: 8212, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
510 { .Name: 1529, .SubRegs: 2, .SuperRegs: 128, .SubRegIndices: 2, .RegUnits: 8215, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
511 { .Name: 1477, .SubRegs: 2, .SuperRegs: 119, .SubRegIndices: 2, .RegUnits: 8220, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
512 { .Name: 1541, .SubRegs: 2, .SuperRegs: 119, .SubRegIndices: 2, .RegUnits: 8223, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
513 { .Name: 1526, .SubRegs: 2, .SuperRegs: 122, .SubRegIndices: 2, .RegUnits: 8214, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
514 { .Name: 1553, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8230, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
515 { .Name: 1725, .SubRegs: 206, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 348160, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
516 { .Name: 1521, .SubRegs: 194, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 335876, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
517 { .Name: 1737, .SubRegs: 200, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 348162, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
518 { .Name: 1749, .SubRegs: 188, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 335878, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
519 { .Name: 1469, .SubRegs: 97, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 299019, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
520 { .Name: 1761, .SubRegs: 179, .SuperRegs: 2, .SubRegIndices: 4, .RegUnits: 311306, .RegUnitLaneMasks: 4, .IsConstant: 0, .IsArtificial: 0 },
521 { .Name: 1579, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8231, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
522 { .Name: 1533, .SubRegs: 40, .SuperRegs: 2, .SubRegIndices: 14, .RegUnits: 233494, .RegUnitLaneMasks: 10, .IsConstant: 0, .IsArtificial: 0 },
523 { .Name: 1769, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8232, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
524 { .Name: 1481, .SubRegs: 31, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278554, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
525 { .Name: 1545, .SubRegs: 22, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278557, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
526 { .Name: 1474, .SubRegs: 53, .SuperRegs: 112, .SubRegIndices: 2, .RegUnits: 233498, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
527 { .Name: 1307, .SubRegs: 2, .SuperRegs: 115, .SubRegIndices: 2, .RegUnits: 8219, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
528 { .Name: 1501, .SubRegs: 2, .SuperRegs: 111, .SubRegIndices: 2, .RegUnits: 8218, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
529 { .Name: 1538, .SubRegs: 53, .SuperRegs: 104, .SubRegIndices: 2, .RegUnits: 233501, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
530 { .Name: 1315, .SubRegs: 2, .SuperRegs: 107, .SubRegIndices: 2, .RegUnits: 8222, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
531 { .Name: 1509, .SubRegs: 2, .SuperRegs: 103, .SubRegIndices: 2, .RegUnits: 8221, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
532 { .Name: 1586, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8233, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
533 { .Name: 1549, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8234, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
534 { .Name: 1571, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8235, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
535 { .Name: 99, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8236, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
536 { .Name: 213, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8237, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
537 { .Name: 302, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8238, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
538 { .Name: 394, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8239, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
539 { .Name: 483, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8240, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
540 { .Name: 575, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8241, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
541 { .Name: 658, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8242, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
542 { .Name: 744, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8243, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
543 { .Name: 815, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8244, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
544 { .Name: 882, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8245, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
545 { .Name: 18, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8246, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
546 { .Name: 129, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8247, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
547 { .Name: 243, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8248, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
548 { .Name: 332, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8249, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
549 { .Name: 424, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8250, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
550 { .Name: 513, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8251, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
551 { .Name: 103, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8252, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
552 { .Name: 217, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8253, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
553 { .Name: 306, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8254, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
554 { .Name: 398, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8255, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
555 { .Name: 487, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8256, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
556 { .Name: 579, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8257, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
557 { .Name: 662, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8258, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
558 { .Name: 748, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8259, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
559 { .Name: 819, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8260, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
560 { .Name: 886, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8261, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
561 { .Name: 23, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8262, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
562 { .Name: 134, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8263, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
563 { .Name: 248, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8264, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
564 { .Name: 337, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8265, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
565 { .Name: 429, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8266, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
566 { .Name: 518, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8267, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
567 { .Name: 95, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8268, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
568 { .Name: 209, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8269, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
569 { .Name: 298, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8270, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
570 { .Name: 390, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8271, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
571 { .Name: 479, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8272, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
572 { .Name: 571, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8273, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
573 { .Name: 654, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8274, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
574 { .Name: 740, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8275, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
575 { .Name: 76, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8276, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
576 { .Name: 190, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8277, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
577 { .Name: 279, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8278, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
578 { .Name: 371, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8279, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
579 { .Name: 460, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8280, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
580 { .Name: 552, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8281, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
581 { .Name: 635, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8282, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
582 { .Name: 721, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8283, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
583 { .Name: 816, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278620, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
584 { .Name: 883, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278623, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
585 { .Name: 19, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278626, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
586 { .Name: 130, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278629, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
587 { .Name: 244, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278632, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
588 { .Name: 333, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278635, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
589 { .Name: 425, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278638, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
590 { .Name: 514, .SubRegs: 91, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278641, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
591 { .Name: 107, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8308, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
592 { .Name: 221, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8309, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
593 { .Name: 310, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8310, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
594 { .Name: 402, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8311, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
595 { .Name: 491, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8312, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
596 { .Name: 583, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8313, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
597 { .Name: 666, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8314, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
598 { .Name: 752, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8315, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
599 { .Name: 80, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8316, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
600 { .Name: 194, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8317, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
601 { .Name: 283, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8318, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
602 { .Name: 375, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8319, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
603 { .Name: 464, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8320, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
604 { .Name: 556, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8321, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
605 { .Name: 639, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8322, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
606 { .Name: 725, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8323, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
607 { .Name: 800, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8324, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
608 { .Name: 867, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8325, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
609 { .Name: 0, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8326, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
610 { .Name: 111, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8327, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
611 { .Name: 225, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8328, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
612 { .Name: 314, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8329, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
613 { .Name: 406, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8330, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
614 { .Name: 495, .SubRegs: 2, .SuperRegs: 218, .SubRegIndices: 2, .RegUnits: 8331, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
615 { .Name: 990, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8284, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
616 { .Name: 1004, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8287, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
617 { .Name: 890, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8290, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
618 { .Name: 905, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8293, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
619 { .Name: 920, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8296, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
620 { .Name: 930, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8299, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
621 { .Name: 940, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8302, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
622 { .Name: 950, .SubRegs: 2, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 8305, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
623 { .Name: 1275, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8285, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
624 { .Name: 1292, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8288, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
625 { .Name: 1155, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8291, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
626 { .Name: 1173, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8294, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
627 { .Name: 1191, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8297, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
628 { .Name: 1203, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8300, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
629 { .Name: 1215, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8303, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
630 { .Name: 1227, .SubRegs: 2, .SuperRegs: 14, .SubRegIndices: 2, .RegUnits: 8306, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
631 { .Name: 1108, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278620, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
632 { .Name: 1122, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278623, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
633 { .Name: 1008, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278626, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
634 { .Name: 1023, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278629, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
635 { .Name: 1038, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278632, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
636 { .Name: 1048, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278635, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
637 { .Name: 1058, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278638, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
638 { .Name: 1068, .SubRegs: 92, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278641, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
639 { .Name: 1689, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233564, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
640 { .Name: 1703, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233567, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
641 { .Name: 1589, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233570, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
642 { .Name: 1604, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233573, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
643 { .Name: 1619, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233576, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
644 { .Name: 1629, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233579, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
645 { .Name: 1639, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233582, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
646 { .Name: 1649, .SubRegs: 79, .SuperRegs: 15, .SubRegIndices: 2, .RegUnits: 233585, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
647 { .Name: 1439, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8286, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
648 { .Name: 1456, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8289, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
649 { .Name: 1319, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8292, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
650 { .Name: 1337, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8295, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
651 { .Name: 1355, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8298, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
652 { .Name: 1367, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8301, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
653 { .Name: 1379, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8304, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
654 { .Name: 1391, .SubRegs: 2, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 8307, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
655 { .Name: 85, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8316, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
656 { .Name: 199, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8317, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
657 { .Name: 288, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8318, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
658 { .Name: 380, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8319, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
659 { .Name: 469, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8320, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
660 { .Name: 561, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8321, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
661 { .Name: 644, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8322, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
662 { .Name: 730, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8323, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
663 { .Name: 805, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8324, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
664 { .Name: 872, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8325, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
665 { .Name: 6, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8326, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
666 { .Name: 117, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8327, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
667 { .Name: 231, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8328, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
668 { .Name: 320, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8329, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
669 { .Name: 412, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8330, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
670 { .Name: 501, .SubRegs: 1, .SuperRegs: 219, .SubRegIndices: 20, .RegUnits: 8331, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
671 { .Name: 72, .SubRegs: 2, .SuperRegs: 229, .SubRegIndices: 2, .RegUnits: 8332, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
672 { .Name: 186, .SubRegs: 2, .SuperRegs: 227, .SubRegIndices: 2, .RegUnits: 8333, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
673 { .Name: 275, .SubRegs: 2, .SuperRegs: 227, .SubRegIndices: 2, .RegUnits: 8334, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
674 { .Name: 367, .SubRegs: 2, .SuperRegs: 225, .SubRegIndices: 2, .RegUnits: 8335, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
675 { .Name: 456, .SubRegs: 2, .SuperRegs: 225, .SubRegIndices: 2, .RegUnits: 8336, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
676 { .Name: 548, .SubRegs: 2, .SuperRegs: 223, .SubRegIndices: 2, .RegUnits: 8337, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
677 { .Name: 631, .SubRegs: 2, .SuperRegs: 223, .SubRegIndices: 2, .RegUnits: 8338, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
678 { .Name: 717, .SubRegs: 2, .SuperRegs: 221, .SubRegIndices: 2, .RegUnits: 8339, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
679 { .Name: 587, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8340, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
680 { .Name: 670, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8341, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
681 { .Name: 756, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8342, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
682 { .Name: 823, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8343, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
683 { .Name: 28, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8344, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
684 { .Name: 139, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8345, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
685 { .Name: 253, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8346, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
686 { .Name: 342, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8347, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
687 { .Name: 434, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8348, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
688 { .Name: 523, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8349, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
689 { .Name: 609, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8350, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
690 { .Name: 692, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8351, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
691 { .Name: 778, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8352, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
692 { .Name: 845, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8353, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
693 { .Name: 50, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8354, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
694 { .Name: 161, .SubRegs: 2, .SuperRegs: 185, .SubRegIndices: 2, .RegUnits: 8355, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
695 { .Name: 593, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8340, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
696 { .Name: 676, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8341, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
697 { .Name: 762, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8342, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
698 { .Name: 829, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8343, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
699 { .Name: 34, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8344, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
700 { .Name: 145, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8345, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
701 { .Name: 259, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8346, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
702 { .Name: 348, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8347, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
703 { .Name: 440, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8348, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
704 { .Name: 529, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8349, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
705 { .Name: 615, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8350, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
706 { .Name: 698, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8351, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
707 { .Name: 784, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8352, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
708 { .Name: 851, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8353, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
709 { .Name: 56, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8354, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
710 { .Name: 167, .SubRegs: 29, .SuperRegs: 186, .SubRegIndices: 20, .RegUnits: 8355, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
711 { .Name: 90, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8316, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
712 { .Name: 204, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8317, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
713 { .Name: 293, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8318, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
714 { .Name: 385, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8319, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
715 { .Name: 474, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8320, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
716 { .Name: 566, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8321, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
717 { .Name: 649, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8322, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
718 { .Name: 735, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8323, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
719 { .Name: 810, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8324, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
720 { .Name: 877, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8325, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
721 { .Name: 12, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8326, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
722 { .Name: 123, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8327, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
723 { .Name: 237, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8328, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
724 { .Name: 326, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8329, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
725 { .Name: 418, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8330, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
726 { .Name: 507, .SubRegs: 0, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8331, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
727 { .Name: 599, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8340, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
728 { .Name: 682, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8341, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
729 { .Name: 768, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8342, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
730 { .Name: 835, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8343, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
731 { .Name: 40, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8344, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
732 { .Name: 151, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8345, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
733 { .Name: 265, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8346, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
734 { .Name: 354, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8347, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
735 { .Name: 446, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8348, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
736 { .Name: 535, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8349, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
737 { .Name: 621, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8350, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
738 { .Name: 704, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8351, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
739 { .Name: 790, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8352, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
740 { .Name: 857, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8353, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
741 { .Name: 62, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8354, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
742 { .Name: 173, .SubRegs: 28, .SuperRegs: 2, .SubRegIndices: 19, .RegUnits: 8355, .RegUnitLaneMasks: 14, .IsConstant: 0, .IsArtificial: 0 },
743 { .Name: 183, .SubRegs: 56, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233612, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
744 { .Name: 364, .SubRegs: 59, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233614, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
745 { .Name: 545, .SubRegs: 62, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233616, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
746 { .Name: 714, .SubRegs: 65, .SuperRegs: 2, .SubRegIndices: 17, .RegUnits: 233618, .RegUnitLaneMasks: 12, .IsConstant: 0, .IsArtificial: 0 },
747 { .Name: 1145, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8356, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
748 { .Name: 75, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8357, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
749 { .Name: 189, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8358, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
750 { .Name: 278, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8359, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
751 { .Name: 370, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8360, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
752 { .Name: 459, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8361, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
753 { .Name: 551, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8362, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
754 { .Name: 634, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8363, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
755 { .Name: 720, .SubRegs: 2, .SuperRegs: 2, .SubRegIndices: 2, .RegUnits: 8364, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
756 { .Name: 605, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278701, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
757 { .Name: 688, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278704, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
758 { .Name: 774, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278707, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
759 { .Name: 841, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278710, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
760 { .Name: 46, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278713, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
761 { .Name: 157, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278716, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
762 { .Name: 271, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278719, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
763 { .Name: 360, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278722, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
764 { .Name: 452, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278725, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
765 { .Name: 541, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278728, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
766 { .Name: 627, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278731, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
767 { .Name: 710, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278734, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
768 { .Name: 796, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278737, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
769 { .Name: 863, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278740, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
770 { .Name: 68, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278743, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
771 { .Name: 179, .SubRegs: 212, .SuperRegs: 2, .SubRegIndices: 9, .RegUnits: 278746, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
772 { .Name: 960, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8365, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
773 { .Name: 970, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8368, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
774 { .Name: 980, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8371, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
775 { .Name: 994, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8374, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
776 { .Name: 895, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8377, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
777 { .Name: 910, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8380, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
778 { .Name: 925, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8383, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
779 { .Name: 935, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8386, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
780 { .Name: 945, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8389, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
781 { .Name: 955, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8392, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
782 { .Name: 965, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8395, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
783 { .Name: 975, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8398, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
784 { .Name: 985, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8401, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
785 { .Name: 999, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8404, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
786 { .Name: 900, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8407, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
787 { .Name: 915, .SubRegs: 2, .SuperRegs: 10, .SubRegIndices: 2, .RegUnits: 8410, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 0 },
788 { .Name: 1239, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8366, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
789 { .Name: 1251, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8369, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
790 { .Name: 1263, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8372, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
791 { .Name: 1280, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8375, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
792 { .Name: 1161, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8378, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
793 { .Name: 1179, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8381, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
794 { .Name: 1197, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8384, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
795 { .Name: 1209, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8387, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
796 { .Name: 1221, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8390, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
797 { .Name: 1233, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8393, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
798 { .Name: 1245, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8396, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
799 { .Name: 1257, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8399, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
800 { .Name: 1269, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8402, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
801 { .Name: 1286, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8405, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
802 { .Name: 1167, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8408, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
803 { .Name: 1185, .SubRegs: 2, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 8411, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
804 { .Name: 1078, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278701, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
805 { .Name: 1088, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278704, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
806 { .Name: 1098, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278707, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
807 { .Name: 1112, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278710, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
808 { .Name: 1013, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278713, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
809 { .Name: 1028, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278716, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
810 { .Name: 1043, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278719, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
811 { .Name: 1053, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278722, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
812 { .Name: 1063, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278725, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
813 { .Name: 1073, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278728, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
814 { .Name: 1083, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278731, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
815 { .Name: 1093, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278734, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
816 { .Name: 1103, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278737, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
817 { .Name: 1117, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278740, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
818 { .Name: 1018, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278743, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
819 { .Name: 1033, .SubRegs: 213, .SuperRegs: 4, .SubRegIndices: 10, .RegUnits: 278746, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
820 { .Name: 1659, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233645, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
821 { .Name: 1669, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233648, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
822 { .Name: 1679, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233651, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
823 { .Name: 1693, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233654, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
824 { .Name: 1594, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233657, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
825 { .Name: 1609, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233660, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
826 { .Name: 1624, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233663, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
827 { .Name: 1634, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233666, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
828 { .Name: 1644, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233669, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
829 { .Name: 1654, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233672, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
830 { .Name: 1664, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233675, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
831 { .Name: 1674, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233678, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
832 { .Name: 1684, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233681, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
833 { .Name: 1698, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233684, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
834 { .Name: 1599, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233687, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
835 { .Name: 1614, .SubRegs: 88, .SuperRegs: 7, .SubRegIndices: 2, .RegUnits: 233690, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
836 { .Name: 1403, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8367, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
837 { .Name: 1415, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8370, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
838 { .Name: 1427, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8373, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
839 { .Name: 1444, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8376, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
840 { .Name: 1325, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8379, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
841 { .Name: 1343, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8382, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
842 { .Name: 1361, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8385, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
843 { .Name: 1373, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8388, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
844 { .Name: 1385, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8391, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
845 { .Name: 1397, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8394, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
846 { .Name: 1409, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8397, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
847 { .Name: 1421, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8400, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
848 { .Name: 1433, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8403, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
849 { .Name: 1450, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8406, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
850 { .Name: 1331, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8409, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
851 { .Name: 1349, .SubRegs: 2, .SuperRegs: 3, .SubRegIndices: 2, .RegUnits: 8412, .RegUnitLaneMasks: 15, .IsConstant: 0, .IsArtificial: 1 },
852};
853
854extern const MCPhysReg X86RegUnitRoots[][2] = {
855 { X86::AH },
856 { X86::AL },
857 { X86::BH },
858 { X86::BL },
859 { X86::BPL },
860 { X86::BPH },
861 { X86::CH },
862 { X86::CL },
863 { X86::CS },
864 { X86::DF },
865 { X86::DH },
866 { X86::DIL },
867 { X86::DIH },
868 { X86::DL },
869 { X86::DS },
870 { X86::HAX },
871 { X86::HBP },
872 { X86::HBX },
873 { X86::HCX },
874 { X86::HDI },
875 { X86::HDX },
876 { X86::EFLAGS },
877 { X86::IP },
878 { X86::HIP },
879 { X86::EIZ },
880 { X86::ES },
881 { X86::SIL },
882 { X86::SIH },
883 { X86::HSI },
884 { X86::SPL },
885 { X86::SPH },
886 { X86::HSP },
887 { X86::FPCW },
888 { X86::FPSW },
889 { X86::FS },
890 { X86::FS_BASE },
891 { X86::GS },
892 { X86::GS_BASE },
893 { X86::MXCSR },
894 { X86::RFLAGS },
895 { X86::RIZ },
896 { X86::SS },
897 { X86::SSP },
898 { X86::_EFLAGS },
899 { X86::CR0 },
900 { X86::CR1 },
901 { X86::CR2 },
902 { X86::CR3 },
903 { X86::CR4 },
904 { X86::CR5 },
905 { X86::CR6 },
906 { X86::CR7 },
907 { X86::CR8 },
908 { X86::CR9 },
909 { X86::CR10 },
910 { X86::CR11 },
911 { X86::CR12 },
912 { X86::CR13 },
913 { X86::CR14 },
914 { X86::CR15 },
915 { X86::DR0 },
916 { X86::DR1 },
917 { X86::DR2 },
918 { X86::DR3 },
919 { X86::DR4 },
920 { X86::DR5 },
921 { X86::DR6 },
922 { X86::DR7 },
923 { X86::DR8 },
924 { X86::DR9 },
925 { X86::DR10 },
926 { X86::DR11 },
927 { X86::DR12 },
928 { X86::DR13 },
929 { X86::DR14 },
930 { X86::DR15 },
931 { X86::FP0 },
932 { X86::FP1 },
933 { X86::FP2 },
934 { X86::FP3 },
935 { X86::FP4 },
936 { X86::FP5 },
937 { X86::FP6 },
938 { X86::FP7 },
939 { X86::MM0 },
940 { X86::MM1 },
941 { X86::MM2 },
942 { X86::MM3 },
943 { X86::MM4 },
944 { X86::MM5 },
945 { X86::MM6 },
946 { X86::MM7 },
947 { X86::R8B },
948 { X86::R8BH },
949 { X86::R8WH },
950 { X86::R9B },
951 { X86::R9BH },
952 { X86::R9WH },
953 { X86::R10B },
954 { X86::R10BH },
955 { X86::R10WH },
956 { X86::R11B },
957 { X86::R11BH },
958 { X86::R11WH },
959 { X86::R12B },
960 { X86::R12BH },
961 { X86::R12WH },
962 { X86::R13B },
963 { X86::R13BH },
964 { X86::R13WH },
965 { X86::R14B },
966 { X86::R14BH },
967 { X86::R14WH },
968 { X86::R15B },
969 { X86::R15BH },
970 { X86::R15WH },
971 { X86::ST0 },
972 { X86::ST1 },
973 { X86::ST2 },
974 { X86::ST3 },
975 { X86::ST4 },
976 { X86::ST5 },
977 { X86::ST6 },
978 { X86::ST7 },
979 { X86::XMM0 },
980 { X86::XMM1 },
981 { X86::XMM2 },
982 { X86::XMM3 },
983 { X86::XMM4 },
984 { X86::XMM5 },
985 { X86::XMM6 },
986 { X86::XMM7 },
987 { X86::XMM8 },
988 { X86::XMM9 },
989 { X86::XMM10 },
990 { X86::XMM11 },
991 { X86::XMM12 },
992 { X86::XMM13 },
993 { X86::XMM14 },
994 { X86::XMM15 },
995 { X86::K0 },
996 { X86::K1 },
997 { X86::K2 },
998 { X86::K3 },
999 { X86::K4 },
1000 { X86::K5 },
1001 { X86::K6 },
1002 { X86::K7 },
1003 { X86::XMM16 },
1004 { X86::XMM17 },
1005 { X86::XMM18 },
1006 { X86::XMM19 },
1007 { X86::XMM20 },
1008 { X86::XMM21 },
1009 { X86::XMM22 },
1010 { X86::XMM23 },
1011 { X86::XMM24 },
1012 { X86::XMM25 },
1013 { X86::XMM26 },
1014 { X86::XMM27 },
1015 { X86::XMM28 },
1016 { X86::XMM29 },
1017 { X86::XMM30 },
1018 { X86::XMM31 },
1019 { X86::TMMCFG },
1020 { X86::TMM0 },
1021 { X86::TMM1 },
1022 { X86::TMM2 },
1023 { X86::TMM3 },
1024 { X86::TMM4 },
1025 { X86::TMM5 },
1026 { X86::TMM6 },
1027 { X86::TMM7 },
1028 { X86::R16B },
1029 { X86::R16BH },
1030 { X86::R16WH },
1031 { X86::R17B },
1032 { X86::R17BH },
1033 { X86::R17WH },
1034 { X86::R18B },
1035 { X86::R18BH },
1036 { X86::R18WH },
1037 { X86::R19B },
1038 { X86::R19BH },
1039 { X86::R19WH },
1040 { X86::R20B },
1041 { X86::R20BH },
1042 { X86::R20WH },
1043 { X86::R21B },
1044 { X86::R21BH },
1045 { X86::R21WH },
1046 { X86::R22B },
1047 { X86::R22BH },
1048 { X86::R22WH },
1049 { X86::R23B },
1050 { X86::R23BH },
1051 { X86::R23WH },
1052 { X86::R24B },
1053 { X86::R24BH },
1054 { X86::R24WH },
1055 { X86::R25B },
1056 { X86::R25BH },
1057 { X86::R25WH },
1058 { X86::R26B },
1059 { X86::R26BH },
1060 { X86::R26WH },
1061 { X86::R27B },
1062 { X86::R27BH },
1063 { X86::R27WH },
1064 { X86::R28B },
1065 { X86::R28BH },
1066 { X86::R28WH },
1067 { X86::R29B },
1068 { X86::R29BH },
1069 { X86::R29WH },
1070 { X86::R30B },
1071 { X86::R30BH },
1072 { X86::R30WH },
1073 { X86::R31B },
1074 { X86::R31BH },
1075 { X86::R31WH },
1076};
1077
1078namespace { // Register classes...
1079 // GR8 Register Class...
1080 const MCPhysReg GR8[] = {
1081 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R30B, X86::R31B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::R20B, X86::R21B, X86::R28B, X86::R29B,
1082 };
1083
1084 // GR8 Bit set.
1085 const uint8_t GR8Bits[] = {
1086 0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1087 };
1088
1089 // GRH8 Register Class...
1090 const MCPhysReg GRH8[] = {
1091 X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH, X86::R16BH, X86::R17BH, X86::R18BH, X86::R19BH, X86::R20BH, X86::R21BH, X86::R22BH, X86::R23BH, X86::R24BH, X86::R25BH, X86::R26BH, X86::R27BH, X86::R28BH, X86::R29BH, X86::R30BH, X86::R31BH,
1092 };
1093
1094 // GRH8 Bit set.
1095 const uint8_t GRH8Bits[] = {
1096 0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1097 };
1098
1099 // GR8_NOREX2 Register Class...
1100 const MCPhysReg GR8_NOREX2[] = {
1101 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
1102 };
1103
1104 // GR8_NOREX2 Bit set.
1105 const uint8_t GR8_NOREX2Bits[] = {
1106 0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1107 };
1108
1109 // GR8_NOREX Register Class...
1110 const MCPhysReg GR8_NOREX[] = {
1111 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
1112 };
1113
1114 // GR8_NOREX Bit set.
1115 const uint8_t GR8_NOREXBits[] = {
1116 0x36, 0x8c, 0x08,
1117 };
1118
1119 // GR8_ABCD_H Register Class...
1120 const MCPhysReg GR8_ABCD_H[] = {
1121 X86::AH, X86::CH, X86::DH, X86::BH,
1122 };
1123
1124 // GR8_ABCD_H Bit set.
1125 const uint8_t GR8_ABCD_HBits[] = {
1126 0x12, 0x84,
1127 };
1128
1129 // GR8_ABCD_L Register Class...
1130 const MCPhysReg GR8_ABCD_L[] = {
1131 X86::AL, X86::CL, X86::DL, X86::BL,
1132 };
1133
1134 // GR8_ABCD_L Bit set.
1135 const uint8_t GR8_ABCD_LBits[] = {
1136 0x24, 0x08, 0x08,
1137 };
1138
1139 // GRH16 Register Class...
1140 const MCPhysReg GRH16[] = {
1141 X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH, X86::R16WH, X86::R17WH, X86::R18WH, X86::R19WH, X86::R20WH, X86::R21WH, X86::R22WH, X86::R23WH, X86::R24WH, X86::R25WH, X86::R26WH, X86::R27WH, X86::R28WH, X86::R29WH, X86::R30WH, X86::R31WH,
1142 };
1143
1144 // GRH16 Bit set.
1145 const uint8_t GRH16Bits[] = {
1146 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1147 };
1148
1149 // GR16 Register Class...
1150 const MCPhysReg GR16[] = {
1151 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R16W, X86::R17W, X86::R18W, X86::R19W, X86::R22W, X86::R23W, X86::R24W, X86::R25W, X86::R26W, X86::R27W, X86::R30W, X86::R31W, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::R20W, X86::R21W, X86::R28W, X86::R29W,
1152 };
1153
1154 // GR16 Bit set.
1155 const uint8_t GR16Bits[] = {
1156 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1157 };
1158
1159 // GR16_NOREX2 Register Class...
1160 const MCPhysReg GR16_NOREX2[] = {
1161 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
1162 };
1163
1164 // GR16_NOREX2 Bit set.
1165 const uint8_t GR16_NOREX2Bits[] = {
1166 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1167 };
1168
1169 // GR16_NOREX Register Class...
1170 const MCPhysReg GR16_NOREX[] = {
1171 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP,
1172 };
1173
1174 // GR16_NOREX Bit set.
1175 const uint8_t GR16_NOREXBits[] = {
1176 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02,
1177 };
1178
1179 // VK1 Register Class...
1180 const MCPhysReg VK1[] = {
1181 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1182 };
1183
1184 // VK1 Bit set.
1185 const uint8_t VK1Bits[] = {
1186 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1187 };
1188
1189 // VK16 Register Class...
1190 const MCPhysReg VK16[] = {
1191 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1192 };
1193
1194 // VK16 Bit set.
1195 const uint8_t VK16Bits[] = {
1196 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1197 };
1198
1199 // VK2 Register Class...
1200 const MCPhysReg VK2[] = {
1201 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1202 };
1203
1204 // VK2 Bit set.
1205 const uint8_t VK2Bits[] = {
1206 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1207 };
1208
1209 // VK4 Register Class...
1210 const MCPhysReg VK4[] = {
1211 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1212 };
1213
1214 // VK4 Bit set.
1215 const uint8_t VK4Bits[] = {
1216 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1217 };
1218
1219 // VK8 Register Class...
1220 const MCPhysReg VK8[] = {
1221 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1222 };
1223
1224 // VK8 Bit set.
1225 const uint8_t VK8Bits[] = {
1226 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1227 };
1228
1229 // VK16WM Register Class...
1230 const MCPhysReg VK16WM[] = {
1231 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1232 };
1233
1234 // VK16WM Bit set.
1235 const uint8_t VK16WMBits[] = {
1236 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1237 };
1238
1239 // VK1WM Register Class...
1240 const MCPhysReg VK1WM[] = {
1241 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1242 };
1243
1244 // VK1WM Bit set.
1245 const uint8_t VK1WMBits[] = {
1246 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1247 };
1248
1249 // VK2WM Register Class...
1250 const MCPhysReg VK2WM[] = {
1251 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1252 };
1253
1254 // VK2WM Bit set.
1255 const uint8_t VK2WMBits[] = {
1256 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1257 };
1258
1259 // VK4WM Register Class...
1260 const MCPhysReg VK4WM[] = {
1261 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1262 };
1263
1264 // VK4WM Bit set.
1265 const uint8_t VK4WMBits[] = {
1266 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1267 };
1268
1269 // VK8WM Register Class...
1270 const MCPhysReg VK8WM[] = {
1271 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1272 };
1273
1274 // VK8WM Bit set.
1275 const uint8_t VK8WMBits[] = {
1276 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1277 };
1278
1279 // SEGMENT_REG Register Class...
1280 const MCPhysReg SEGMENT_REG[] = {
1281 X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS,
1282 };
1283
1284 // SEGMENT_REG Bit set.
1285 const uint8_t SEGMENT_REGBits[] = {
1286 0x00, 0x10, 0x10, 0x80, 0x50, 0x00, 0x00, 0x00, 0x10,
1287 };
1288
1289 // GR16_ABCD Register Class...
1290 const MCPhysReg GR16_ABCD[] = {
1291 X86::AX, X86::CX, X86::DX, X86::BX,
1292 };
1293
1294 // GR16_ABCD Bit set.
1295 const uint8_t GR16_ABCDBits[] = {
1296 0x08, 0x22, 0x20,
1297 };
1298
1299 // FPCCR Register Class...
1300 const MCPhysReg FPCCR[] = {
1301 X86::FPSW,
1302 };
1303
1304 // FPCCR Bit set.
1305 const uint8_t FPCCRBits[] = {
1306 0x00, 0x00, 0x00, 0x00, 0x08,
1307 };
1308
1309 // FR16X Register Class...
1310 const MCPhysReg FR16X[] = {
1311 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
1312 };
1313
1314 // FR16X Bit set.
1315 const uint8_t FR16XBits[] = {
1316 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1317 };
1318
1319 // FR16 Register Class...
1320 const MCPhysReg FR16[] = {
1321 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
1322 };
1323
1324 // FR16 Bit set.
1325 const uint8_t FR16Bits[] = {
1326 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1327 };
1328
1329 // VK16PAIR Register Class...
1330 const MCPhysReg VK16PAIR[] = {
1331 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1332 };
1333
1334 // VK16PAIR Bit set.
1335 const uint8_t VK16PAIRBits[] = {
1336 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1337 };
1338
1339 // VK1PAIR Register Class...
1340 const MCPhysReg VK1PAIR[] = {
1341 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1342 };
1343
1344 // VK1PAIR Bit set.
1345 const uint8_t VK1PAIRBits[] = {
1346 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1347 };
1348
1349 // VK2PAIR Register Class...
1350 const MCPhysReg VK2PAIR[] = {
1351 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1352 };
1353
1354 // VK2PAIR Bit set.
1355 const uint8_t VK2PAIRBits[] = {
1356 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1357 };
1358
1359 // VK4PAIR Register Class...
1360 const MCPhysReg VK4PAIR[] = {
1361 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1362 };
1363
1364 // VK4PAIR Bit set.
1365 const uint8_t VK4PAIRBits[] = {
1366 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1367 };
1368
1369 // VK8PAIR Register Class...
1370 const MCPhysReg VK8PAIR[] = {
1371 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1372 };
1373
1374 // VK8PAIR Bit set.
1375 const uint8_t VK8PAIRBits[] = {
1376 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1377 };
1378
1379 // VK1PAIR_with_sub_mask_0_in_VK1WM Register Class...
1380 const MCPhysReg VK1PAIR_with_sub_mask_0_in_VK1WM[] = {
1381 X86::K2_K3, X86::K4_K5, X86::K6_K7,
1382 };
1383
1384 // VK1PAIR_with_sub_mask_0_in_VK1WM Bit set.
1385 const uint8_t VK1PAIR_with_sub_mask_0_in_VK1WMBits[] = {
1386 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
1387 };
1388
1389 // LOW32_ADDR_ACCESS_RBP Register Class...
1390 const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
1391 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::RIP, X86::RBP,
1392 };
1393
1394 // LOW32_ADDR_ACCESS_RBP Bit set.
1395 const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
1396 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1397 };
1398
1399 // LOW32_ADDR_ACCESS Register Class...
1400 const MCPhysReg LOW32_ADDR_ACCESS[] = {
1401 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::RIP,
1402 };
1403
1404 // LOW32_ADDR_ACCESS Bit set.
1405 const uint8_t LOW32_ADDR_ACCESSBits[] = {
1406 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1407 };
1408
1409 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
1410 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
1411 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::RBP,
1412 };
1413
1414 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
1415 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
1416 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1417 };
1418
1419 // FR32X Register Class...
1420 const MCPhysReg FR32X[] = {
1421 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
1422 };
1423
1424 // FR32X Bit set.
1425 const uint8_t FR32XBits[] = {
1426 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1427 };
1428
1429 // GR32 Register Class...
1430 const MCPhysReg GR32[] = {
1431 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D,
1432 };
1433
1434 // GR32 Bit set.
1435 const uint8_t GR32Bits[] = {
1436 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1437 };
1438
1439 // GR32_NOSP Register Class...
1440 const MCPhysReg GR32_NOSP[] = {
1441 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D,
1442 };
1443
1444 // GR32_NOSP Bit set.
1445 const uint8_t GR32_NOSPBits[] = {
1446 0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1447 };
1448
1449 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 Register Class...
1450 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2[] = {
1451 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP,
1452 };
1453
1454 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 Bit set.
1455 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits[] = {
1456 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1457 };
1458
1459 // DEBUG_REG Register Class...
1460 const MCPhysReg DEBUG_REG[] = {
1461 X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15,
1462 };
1463
1464 // DEBUG_REG Bit set.
1465 const uint8_t DEBUG_REGBits[] = {
1466 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1467 };
1468
1469 // FR32 Register Class...
1470 const MCPhysReg FR32[] = {
1471 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
1472 };
1473
1474 // FR32 Bit set.
1475 const uint8_t FR32Bits[] = {
1476 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1477 };
1478
1479 // GR32_NOREX2 Register Class...
1480 const MCPhysReg GR32_NOREX2[] = {
1481 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
1482 };
1483
1484 // GR32_NOREX2 Bit set.
1485 const uint8_t GR32_NOREX2Bits[] = {
1486 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1487 };
1488
1489 // GR32_NOREX2_NOSP Register Class...
1490 const MCPhysReg GR32_NOREX2_NOSP[] = {
1491 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
1492 };
1493
1494 // GR32_NOREX2_NOSP Bit set.
1495 const uint8_t GR32_NOREX2_NOSPBits[] = {
1496 0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1497 };
1498
1499 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
1500 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
1501 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP,
1502 };
1503
1504 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
1505 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
1506 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10,
1507 };
1508
1509 // GR32_NOREX Register Class...
1510 const MCPhysReg GR32_NOREX[] = {
1511 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP,
1512 };
1513
1514 // GR32_NOREX Bit set.
1515 const uint8_t GR32_NOREXBits[] = {
1516 0x00, 0x00, 0xc0, 0x0f, 0x03,
1517 };
1518
1519 // VK32 Register Class...
1520 const MCPhysReg VK32[] = {
1521 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1522 };
1523
1524 // VK32 Bit set.
1525 const uint8_t VK32Bits[] = {
1526 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1527 };
1528
1529 // GR32_NOREX_NOSP Register Class...
1530 const MCPhysReg GR32_NOREX_NOSP[] = {
1531 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,
1532 };
1533
1534 // GR32_NOREX_NOSP Bit set.
1535 const uint8_t GR32_NOREX_NOSPBits[] = {
1536 0x00, 0x00, 0xc0, 0x0f, 0x01,
1537 };
1538
1539 // RFP32 Register Class...
1540 const MCPhysReg RFP32[] = {
1541 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
1542 };
1543
1544 // RFP32 Bit set.
1545 const uint8_t RFP32Bits[] = {
1546 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
1547 };
1548
1549 // VK32WM Register Class...
1550 const MCPhysReg VK32WM[] = {
1551 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1552 };
1553
1554 // VK32WM Bit set.
1555 const uint8_t VK32WMBits[] = {
1556 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1557 };
1558
1559 // GR32_ABCD Register Class...
1560 const MCPhysReg GR32_ABCD[] = {
1561 X86::EAX, X86::ECX, X86::EDX, X86::EBX,
1562 };
1563
1564 // GR32_ABCD Bit set.
1565 const uint8_t GR32_ABCDBits[] = {
1566 0x00, 0x00, 0x40, 0x0b,
1567 };
1568
1569 // GR32_TC Register Class...
1570 const MCPhysReg GR32_TC[] = {
1571 X86::EAX, X86::ECX, X86::EDX, X86::ESP,
1572 };
1573
1574 // GR32_TC Bit set.
1575 const uint8_t GR32_TCBits[] = {
1576 0x00, 0x00, 0x40, 0x0a, 0x02,
1577 };
1578
1579 // GR32_ABCD_and_GR32_TC Register Class...
1580 const MCPhysReg GR32_ABCD_and_GR32_TC[] = {
1581 X86::EAX, X86::ECX, X86::EDX,
1582 };
1583
1584 // GR32_ABCD_and_GR32_TC Bit set.
1585 const uint8_t GR32_ABCD_and_GR32_TCBits[] = {
1586 0x00, 0x00, 0x40, 0x0a,
1587 };
1588
1589 // GR32_AD Register Class...
1590 const MCPhysReg GR32_AD[] = {
1591 X86::EAX, X86::EDX,
1592 };
1593
1594 // GR32_AD Bit set.
1595 const uint8_t GR32_ADBits[] = {
1596 0x00, 0x00, 0x40, 0x08,
1597 };
1598
1599 // GR32_ArgRef Register Class...
1600 const MCPhysReg GR32_ArgRef[] = {
1601 X86::ECX, X86::EDX,
1602 };
1603
1604 // GR32_ArgRef Bit set.
1605 const uint8_t GR32_ArgRefBits[] = {
1606 0x00, 0x00, 0x00, 0x0a,
1607 };
1608
1609 // GR32_BPSP Register Class...
1610 const MCPhysReg GR32_BPSP[] = {
1611 X86::EBP, X86::ESP,
1612 };
1613
1614 // GR32_BPSP Bit set.
1615 const uint8_t GR32_BPSPBits[] = {
1616 0x00, 0x00, 0x80, 0x00, 0x02,
1617 };
1618
1619 // GR32_BSI Register Class...
1620 const MCPhysReg GR32_BSI[] = {
1621 X86::EBX, X86::ESI,
1622 };
1623
1624 // GR32_BSI Bit set.
1625 const uint8_t GR32_BSIBits[] = {
1626 0x00, 0x00, 0x00, 0x01, 0x01,
1627 };
1628
1629 // GR32_CB Register Class...
1630 const MCPhysReg GR32_CB[] = {
1631 X86::ECX, X86::EBX,
1632 };
1633
1634 // GR32_CB Bit set.
1635 const uint8_t GR32_CBBits[] = {
1636 0x00, 0x00, 0x00, 0x03,
1637 };
1638
1639 // GR32_DC Register Class...
1640 const MCPhysReg GR32_DC[] = {
1641 X86::EDX, X86::ECX,
1642 };
1643
1644 // GR32_DC Bit set.
1645 const uint8_t GR32_DCBits[] = {
1646 0x00, 0x00, 0x00, 0x0a,
1647 };
1648
1649 // GR32_DIBP Register Class...
1650 const MCPhysReg GR32_DIBP[] = {
1651 X86::EDI, X86::EBP,
1652 };
1653
1654 // GR32_DIBP Bit set.
1655 const uint8_t GR32_DIBPBits[] = {
1656 0x00, 0x00, 0x80, 0x04,
1657 };
1658
1659 // GR32_SIDI Register Class...
1660 const MCPhysReg GR32_SIDI[] = {
1661 X86::ESI, X86::EDI,
1662 };
1663
1664 // GR32_SIDI Bit set.
1665 const uint8_t GR32_SIDIBits[] = {
1666 0x00, 0x00, 0x00, 0x04, 0x01,
1667 };
1668
1669 // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
1670 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
1671 X86::RIP, X86::RBP,
1672 };
1673
1674 // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
1675 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
1676 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
1677 };
1678
1679 // CCR Register Class...
1680 const MCPhysReg CCR[] = {
1681 X86::EFLAGS,
1682 };
1683
1684 // CCR Bit set.
1685 const uint8_t CCRBits[] = {
1686 0x00, 0x00, 0x00, 0x10,
1687 };
1688
1689 // DFCCR Register Class...
1690 const MCPhysReg DFCCR[] = {
1691 X86::DF,
1692 };
1693
1694 // DFCCR Bit set.
1695 const uint8_t DFCCRBits[] = {
1696 0x00, 0x40,
1697 };
1698
1699 // GR32_ABCD_and_GR32_BSI Register Class...
1700 const MCPhysReg GR32_ABCD_and_GR32_BSI[] = {
1701 X86::EBX,
1702 };
1703
1704 // GR32_ABCD_and_GR32_BSI Bit set.
1705 const uint8_t GR32_ABCD_and_GR32_BSIBits[] = {
1706 0x00, 0x00, 0x00, 0x01,
1707 };
1708
1709 // GR32_AD_and_GR32_ArgRef Register Class...
1710 const MCPhysReg GR32_AD_and_GR32_ArgRef[] = {
1711 X86::EDX,
1712 };
1713
1714 // GR32_AD_and_GR32_ArgRef Bit set.
1715 const uint8_t GR32_AD_and_GR32_ArgRefBits[] = {
1716 0x00, 0x00, 0x00, 0x08,
1717 };
1718
1719 // GR32_ArgRef_and_GR32_CB Register Class...
1720 const MCPhysReg GR32_ArgRef_and_GR32_CB[] = {
1721 X86::ECX,
1722 };
1723
1724 // GR32_ArgRef_and_GR32_CB Bit set.
1725 const uint8_t GR32_ArgRef_and_GR32_CBBits[] = {
1726 0x00, 0x00, 0x00, 0x02,
1727 };
1728
1729 // GR32_BPSP_and_GR32_DIBP Register Class...
1730 const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = {
1731 X86::EBP,
1732 };
1733
1734 // GR32_BPSP_and_GR32_DIBP Bit set.
1735 const uint8_t GR32_BPSP_and_GR32_DIBPBits[] = {
1736 0x00, 0x00, 0x80,
1737 };
1738
1739 // GR32_BPSP_and_GR32_TC Register Class...
1740 const MCPhysReg GR32_BPSP_and_GR32_TC[] = {
1741 X86::ESP,
1742 };
1743
1744 // GR32_BPSP_and_GR32_TC Bit set.
1745 const uint8_t GR32_BPSP_and_GR32_TCBits[] = {
1746 0x00, 0x00, 0x00, 0x00, 0x02,
1747 };
1748
1749 // GR32_BSI_and_GR32_SIDI Register Class...
1750 const MCPhysReg GR32_BSI_and_GR32_SIDI[] = {
1751 X86::ESI,
1752 };
1753
1754 // GR32_BSI_and_GR32_SIDI Bit set.
1755 const uint8_t GR32_BSI_and_GR32_SIDIBits[] = {
1756 0x00, 0x00, 0x00, 0x00, 0x01,
1757 };
1758
1759 // GR32_DIBP_and_GR32_SIDI Register Class...
1760 const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = {
1761 X86::EDI,
1762 };
1763
1764 // GR32_DIBP_and_GR32_SIDI Bit set.
1765 const uint8_t GR32_DIBP_and_GR32_SIDIBits[] = {
1766 0x00, 0x00, 0x00, 0x04,
1767 };
1768
1769 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
1770 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
1771 X86::RBP,
1772 };
1773
1774 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
1775 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
1776 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
1777 };
1778
1779 // LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
1780 const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
1781 X86::RIP,
1782 };
1783
1784 // LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
1785 const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
1786 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
1787 };
1788
1789 // RFP64 Register Class...
1790 const MCPhysReg RFP64[] = {
1791 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
1792 };
1793
1794 // RFP64 Bit set.
1795 const uint8_t RFP64Bits[] = {
1796 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
1797 };
1798
1799 // GR64 Register Class...
1800 const MCPhysReg GR64[] = {
1801 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::RBP, X86::RSP, X86::RIP,
1802 };
1803
1804 // GR64 Bit set.
1805 const uint8_t GR64Bits[] = {
1806 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1807 };
1808
1809 // FR64X Register Class...
1810 const MCPhysReg FR64X[] = {
1811 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
1812 };
1813
1814 // FR64X Bit set.
1815 const uint8_t FR64XBits[] = {
1816 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1817 };
1818
1819 // GR64_with_sub_8bit Register Class...
1820 const MCPhysReg GR64_with_sub_8bit[] = {
1821 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::RBP, X86::RSP,
1822 };
1823
1824 // GR64_with_sub_8bit Bit set.
1825 const uint8_t GR64_with_sub_8bitBits[] = {
1826 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1827 };
1828
1829 // GR64_NOSP Register Class...
1830 const MCPhysReg GR64_NOSP[] = {
1831 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::RBP,
1832 };
1833
1834 // GR64_NOSP Bit set.
1835 const uint8_t GR64_NOSPBits[] = {
1836 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1837 };
1838
1839 // GR64_NOREX2 Register Class...
1840 const MCPhysReg GR64_NOREX2[] = {
1841 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
1842 };
1843
1844 // GR64_NOREX2 Bit set.
1845 const uint8_t GR64_NOREX2Bits[] = {
1846 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1847 };
1848
1849 // CONTROL_REG Register Class...
1850 const MCPhysReg CONTROL_REG[] = {
1851 X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15,
1852 };
1853
1854 // CONTROL_REG Bit set.
1855 const uint8_t CONTROL_REGBits[] = {
1856 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1857 };
1858
1859 // FR64 Register Class...
1860 const MCPhysReg FR64[] = {
1861 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
1862 };
1863
1864 // FR64 Bit set.
1865 const uint8_t FR64Bits[] = {
1866 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1867 };
1868
1869 // GR64_with_sub_16bit_in_GR16_NOREX2 Register Class...
1870 const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX2[] = {
1871 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
1872 };
1873
1874 // GR64_with_sub_16bit_in_GR16_NOREX2 Bit set.
1875 const uint8_t GR64_with_sub_16bit_in_GR16_NOREX2Bits[] = {
1876 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1877 };
1878
1879 // GR64_NOREX2_NOSP Register Class...
1880 const MCPhysReg GR64_NOREX2_NOSP[] = {
1881 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
1882 };
1883
1884 // GR64_NOREX2_NOSP Bit set.
1885 const uint8_t GR64_NOREX2_NOSPBits[] = {
1886 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1887 };
1888
1889 // GR64PLTSafe Register Class...
1890 const MCPhysReg GR64PLTSafe[] = {
1891 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
1892 };
1893
1894 // GR64PLTSafe Bit set.
1895 const uint8_t GR64PLTSafeBits[] = {
1896 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x79,
1897 };
1898
1899 // GR64_TC Register Class...
1900 const MCPhysReg GR64_TC[] = {
1901 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
1902 };
1903
1904 // GR64_TC Bit set.
1905 const uint8_t GR64_TCBits[] = {
1906 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
1907 };
1908
1909 // GR64_NOREX Register Class...
1910 const MCPhysReg GR64_NOREX[] = {
1911 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
1912 };
1913
1914 // GR64_NOREX Bit set.
1915 const uint8_t GR64_NOREXBits[] = {
1916 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35,
1917 };
1918
1919 // GR64_TCW64 Register Class...
1920 const MCPhysReg GR64_TCW64[] = {
1921 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP,
1922 };
1923
1924 // GR64_TCW64 Bit set.
1925 const uint8_t GR64_TCW64Bits[] = {
1926 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1927 };
1928
1929 // GR64_TC_with_sub_8bit Register Class...
1930 const MCPhysReg GR64_TC_with_sub_8bit[] = {
1931 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP,
1932 };
1933
1934 // GR64_TC_with_sub_8bit Bit set.
1935 const uint8_t GR64_TC_with_sub_8bitBits[] = {
1936 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
1937 };
1938
1939 // GR64_NOREX2_NOSP_and_GR64_TC Register Class...
1940 const MCPhysReg GR64_NOREX2_NOSP_and_GR64_TC[] = {
1941 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11,
1942 };
1943
1944 // GR64_NOREX2_NOSP_and_GR64_TC Bit set.
1945 const uint8_t GR64_NOREX2_NOSP_and_GR64_TCBits[] = {
1946 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
1947 };
1948
1949 // GR64_TCW64_with_sub_8bit Register Class...
1950 const MCPhysReg GR64_TCW64_with_sub_8bit[] = {
1951 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP,
1952 };
1953
1954 // GR64_TCW64_with_sub_8bit Bit set.
1955 const uint8_t GR64_TCW64_with_sub_8bitBits[] = {
1956 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1957 };
1958
1959 // GR64_TC_and_GR64_TCW64 Register Class...
1960 const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
1961 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
1962 };
1963
1964 // GR64_TC_and_GR64_TCW64 Bit set.
1965 const uint8_t GR64_TC_and_GR64_TCW64Bits[] = {
1966 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
1967 };
1968
1969 // GR64_with_sub_16bit_in_GR16_NOREX Register Class...
1970 const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
1971 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP,
1972 };
1973
1974 // GR64_with_sub_16bit_in_GR16_NOREX Bit set.
1975 const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
1976 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31,
1977 };
1978
1979 // VK64 Register Class...
1980 const MCPhysReg VK64[] = {
1981 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1982 };
1983
1984 // VK64 Bit set.
1985 const uint8_t VK64Bits[] = {
1986 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1987 };
1988
1989 // VR64 Register Class...
1990 const MCPhysReg VR64[] = {
1991 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
1992 };
1993
1994 // VR64 Bit set.
1995 const uint8_t VR64Bits[] = {
1996 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1997 };
1998
1999 // GR64PLTSafe_and_GR64_TC Register Class...
2000 const MCPhysReg GR64PLTSafe_and_GR64_TC[] = {
2001 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9,
2002 };
2003
2004 // GR64PLTSafe_and_GR64_TC Bit set.
2005 const uint8_t GR64PLTSafe_and_GR64_TCBits[] = {
2006 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
2007 };
2008
2009 // GR64_NOREX2_NOSP_and_GR64_TCW64 Register Class...
2010 const MCPhysReg GR64_NOREX2_NOSP_and_GR64_TCW64[] = {
2011 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11,
2012 };
2013
2014 // GR64_NOREX2_NOSP_and_GR64_TCW64 Bit set.
2015 const uint8_t GR64_NOREX2_NOSP_and_GR64_TCW64Bits[] = {
2016 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
2017 };
2018
2019 // GR64_NOREX_NOSP Register Class...
2020 const MCPhysReg GR64_NOREX_NOSP[] = {
2021 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP,
2022 };
2023
2024 // GR64_NOREX_NOSP Bit set.
2025 const uint8_t GR64_NOREX_NOSPBits[] = {
2026 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11,
2027 };
2028
2029 // GR64_NOREX_and_GR64_TC Register Class...
2030 const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
2031 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP,
2032 };
2033
2034 // GR64_NOREX_and_GR64_TC Bit set.
2035 const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
2036 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35,
2037 };
2038
2039 // GR64_TCW64_and_GR64_TC_with_sub_8bit Register Class...
2040 const MCPhysReg GR64_TCW64_and_GR64_TC_with_sub_8bit[] = {
2041 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP,
2042 };
2043
2044 // GR64_TCW64_and_GR64_TC_with_sub_8bit Bit set.
2045 const uint8_t GR64_TCW64_and_GR64_TC_with_sub_8bitBits[] = {
2046 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2047 };
2048
2049 // VK64WM Register Class...
2050 const MCPhysReg VK64WM[] = {
2051 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
2052 };
2053
2054 // VK64WM Bit set.
2055 const uint8_t VK64WMBits[] = {
2056 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
2057 };
2058
2059 // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 Register Class...
2060 const MCPhysReg GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64[] = {
2061 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11,
2062 };
2063
2064 // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 Bit set.
2065 const uint8_t GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits[] = {
2066 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2067 };
2068
2069 // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Register Class...
2070 const MCPhysReg GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX[] = {
2071 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP,
2072 };
2073
2074 // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Bit set.
2075 const uint8_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
2076 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31,
2077 };
2078
2079 // GR64PLTSafe_and_GR64_TCW64 Register Class...
2080 const MCPhysReg GR64PLTSafe_and_GR64_TCW64[] = {
2081 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9,
2082 };
2083
2084 // GR64PLTSafe_and_GR64_TCW64 Bit set.
2085 const uint8_t GR64PLTSafe_and_GR64_TCW64Bits[] = {
2086 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
2087 };
2088
2089 // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Register Class...
2090 const MCPhysReg GR64_NOREX_and_GR64PLTSafe_and_GR64_TC[] = {
2091 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI,
2092 };
2093
2094 // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Bit set.
2095 const uint8_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits[] = {
2096 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11,
2097 };
2098
2099 // GR64_NOREX_and_GR64_TCW64 Register Class...
2100 const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
2101 X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP,
2102 };
2103
2104 // GR64_NOREX_and_GR64_TCW64 Bit set.
2105 const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = {
2106 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25,
2107 };
2108
2109 // GR64_ABCD Register Class...
2110 const MCPhysReg GR64_ABCD[] = {
2111 X86::RAX, X86::RCX, X86::RDX, X86::RBX,
2112 };
2113
2114 // GR64_ABCD Bit set.
2115 const uint8_t GR64_ABCDBits[] = {
2116 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0x01,
2117 };
2118
2119 // GR64_with_sub_32bit_in_GR32_TC Register Class...
2120 const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
2121 X86::RAX, X86::RCX, X86::RDX, X86::RSP,
2122 };
2123
2124 // GR64_with_sub_32bit_in_GR32_TC Bit set.
2125 const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
2126 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21,
2127 };
2128
2129 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Register Class...
2130 const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC[] = {
2131 X86::RAX, X86::RCX, X86::RDX,
2132 };
2133
2134 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Bit set.
2135 const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits[] = {
2136 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01,
2137 };
2138
2139 // GR64_AD Register Class...
2140 const MCPhysReg GR64_AD[] = {
2141 X86::RAX, X86::RDX,
2142 };
2143
2144 // GR64_AD Bit set.
2145 const uint8_t GR64_ADBits[] = {
2146 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01,
2147 };
2148
2149 // GR64_ArgRef Register Class...
2150 const MCPhysReg GR64_ArgRef[] = {
2151 X86::R10, X86::R11,
2152 };
2153
2154 // GR64_ArgRef Bit set.
2155 const uint8_t GR64_ArgRefBits[] = {
2156 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,
2157 };
2158
2159 // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class...
2160 const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
2161 X86::RBP, X86::RIP,
2162 };
2163
2164 // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set.
2165 const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = {
2166 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
2167 };
2168
2169 // GR64_with_sub_32bit_in_GR32_ArgRef Register Class...
2170 const MCPhysReg GR64_with_sub_32bit_in_GR32_ArgRef[] = {
2171 X86::RCX, X86::RDX,
2172 };
2173
2174 // GR64_with_sub_32bit_in_GR32_ArgRef Bit set.
2175 const uint8_t GR64_with_sub_32bit_in_GR32_ArgRefBits[] = {
2176 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01,
2177 };
2178
2179 // GR64_with_sub_32bit_in_GR32_BPSP Register Class...
2180 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP[] = {
2181 X86::RBP, X86::RSP,
2182 };
2183
2184 // GR64_with_sub_32bit_in_GR32_BPSP Bit set.
2185 const uint8_t GR64_with_sub_32bit_in_GR32_BPSPBits[] = {
2186 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x20,
2187 };
2188
2189 // GR64_with_sub_32bit_in_GR32_BSI Register Class...
2190 const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI[] = {
2191 X86::RSI, X86::RBX,
2192 };
2193
2194 // GR64_with_sub_32bit_in_GR32_BSI Bit set.
2195 const uint8_t GR64_with_sub_32bit_in_GR32_BSIBits[] = {
2196 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x10,
2197 };
2198
2199 // GR64_with_sub_32bit_in_GR32_CB Register Class...
2200 const MCPhysReg GR64_with_sub_32bit_in_GR32_CB[] = {
2201 X86::RCX, X86::RBX,
2202 };
2203
2204 // GR64_with_sub_32bit_in_GR32_CB Bit set.
2205 const uint8_t GR64_with_sub_32bit_in_GR32_CBBits[] = {
2206 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
2207 };
2208
2209 // GR64_with_sub_32bit_in_GR32_DIBP Register Class...
2210 const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP[] = {
2211 X86::RDI, X86::RBP,
2212 };
2213
2214 // GR64_with_sub_32bit_in_GR32_DIBP Bit set.
2215 const uint8_t GR64_with_sub_32bit_in_GR32_DIBPBits[] = {
2216 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90,
2217 };
2218
2219 // GR64_with_sub_32bit_in_GR32_SIDI Register Class...
2220 const MCPhysReg GR64_with_sub_32bit_in_GR32_SIDI[] = {
2221 X86::RSI, X86::RDI,
2222 };
2223
2224 // GR64_with_sub_32bit_in_GR32_SIDI Bit set.
2225 const uint8_t GR64_with_sub_32bit_in_GR32_SIDIBits[] = {
2226 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10,
2227 };
2228
2229 // GR64_A Register Class...
2230 const MCPhysReg GR64_A[] = {
2231 X86::RAX,
2232 };
2233
2234 // GR64_A Bit set.
2235 const uint8_t GR64_ABits[] = {
2236 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2237 };
2238
2239 // GR64_ArgRef_and_GR64_TC Register Class...
2240 const MCPhysReg GR64_ArgRef_and_GR64_TC[] = {
2241 X86::R11,
2242 };
2243
2244 // GR64_ArgRef_and_GR64_TC Bit set.
2245 const uint8_t GR64_ArgRef_and_GR64_TCBits[] = {
2246 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2247 };
2248
2249 // GR64_and_LOW32_ADDR_ACCESS Register Class...
2250 const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
2251 X86::RIP,
2252 };
2253
2254 // GR64_and_LOW32_ADDR_ACCESS Bit set.
2255 const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = {
2256 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2257 };
2258
2259 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Register Class...
2260 const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI[] = {
2261 X86::RBX,
2262 };
2263
2264 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Bit set.
2265 const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits[] = {
2266 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2267 };
2268
2269 // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef Register Class...
2270 const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef[] = {
2271 X86::RDX,
2272 };
2273
2274 // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef Bit set.
2275 const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits[] = {
2276 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
2277 };
2278
2279 // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB Register Class...
2280 const MCPhysReg GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB[] = {
2281 X86::RCX,
2282 };
2283
2284 // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB Bit set.
2285 const uint8_t GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits[] = {
2286 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2287 };
2288
2289 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Register Class...
2290 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP[] = {
2291 X86::RBP,
2292 };
2293
2294 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Bit set.
2295 const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits[] = {
2296 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2297 };
2298
2299 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Register Class...
2300 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC[] = {
2301 X86::RSP,
2302 };
2303
2304 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Bit set.
2305 const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits[] = {
2306 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2307 };
2308
2309 // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Register Class...
2310 const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI[] = {
2311 X86::RSI,
2312 };
2313
2314 // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Bit set.
2315 const uint8_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits[] = {
2316 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2317 };
2318
2319 // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Register Class...
2320 const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI[] = {
2321 X86::RDI,
2322 };
2323
2324 // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Bit set.
2325 const uint8_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits[] = {
2326 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
2327 };
2328
2329 // RST Register Class...
2330 const MCPhysReg RST[] = {
2331 X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
2332 };
2333
2334 // RST Bit set.
2335 const uint8_t RSTBits[] = {
2336 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2337 };
2338
2339 // RFP80 Register Class...
2340 const MCPhysReg RFP80[] = {
2341 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
2342 };
2343
2344 // RFP80 Bit set.
2345 const uint8_t RFP80Bits[] = {
2346 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
2347 };
2348
2349 // RFP80_7 Register Class...
2350 const MCPhysReg RFP80_7[] = {
2351 X86::FP7,
2352 };
2353
2354 // RFP80_7 Bit set.
2355 const uint8_t RFP80_7Bits[] = {
2356 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2357 };
2358
2359 // VR128X Register Class...
2360 const MCPhysReg VR128X[] = {
2361 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
2362 };
2363
2364 // VR128X Bit set.
2365 const uint8_t VR128XBits[] = {
2366 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2367 };
2368
2369 // VR128 Register Class...
2370 const MCPhysReg VR128[] = {
2371 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
2372 };
2373
2374 // VR128 Bit set.
2375 const uint8_t VR128Bits[] = {
2376 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2377 };
2378
2379 // VR256X Register Class...
2380 const MCPhysReg VR256X[] = {
2381 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31,
2382 };
2383
2384 // VR256X Bit set.
2385 const uint8_t VR256XBits[] = {
2386 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x80, 0xff, 0x7f,
2387 };
2388
2389 // VR256 Register Class...
2390 const MCPhysReg VR256[] = {
2391 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15,
2392 };
2393
2394 // VR256 Bit set.
2395 const uint8_t VR256Bits[] = {
2396 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2397 };
2398
2399 // VR512 Register Class...
2400 const MCPhysReg VR512[] = {
2401 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31,
2402 };
2403
2404 // VR512 Bit set.
2405 const uint8_t VR512Bits[] = {
2406 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
2407 };
2408
2409 // VR512_0_15 Register Class...
2410 const MCPhysReg VR512_0_15[] = {
2411 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15,
2412 };
2413
2414 // VR512_0_15 Bit set.
2415 const uint8_t VR512_0_15Bits[] = {
2416 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2417 };
2418
2419 // TILE Register Class...
2420 const MCPhysReg TILE[] = {
2421 X86::TMM0, X86::TMM1, X86::TMM2, X86::TMM3, X86::TMM4, X86::TMM5, X86::TMM6, X86::TMM7,
2422 };
2423
2424 // TILE Bit set.
2425 const uint8_t TILEBits[] = {
2426 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
2427 };
2428
2429} // end anonymous namespace
2430
2431
2432#ifdef __GNUC__
2433#pragma GCC diagnostic push
2434#pragma GCC diagnostic ignored "-Woverlength-strings"
2435#endif
2436extern const char X86RegClassStrings[] = {
2437 /* 0 */ "RFP80\000"
2438 /* 6 */ "VK1\000"
2439 /* 10 */ "VR512\000"
2440 /* 16 */ "VK32\000"
2441 /* 21 */ "RFP32\000"
2442 /* 27 */ "FR32\000"
2443 /* 32 */ "GR32\000"
2444 /* 37 */ "VK2\000"
2445 /* 41 */ "GR32_NOREX2\000"
2446 /* 53 */ "GR64_NOREX2\000"
2447 /* 65 */ "GR64_with_sub_16bit_in_GR16_NOREX2\000"
2448 /* 100 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2\000"
2449 /* 152 */ "GR8_NOREX2\000"
2450 /* 163 */ "VK64\000"
2451 /* 168 */ "RFP64\000"
2452 /* 174 */ "FR64\000"
2453 /* 179 */ "GR64\000"
2454 /* 184 */ "VR64\000"
2455 /* 189 */ "GR64_TC_and_GR64_TCW64\000"
2456 /* 212 */ "GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64\000"
2457 /* 256 */ "GR64_NOREX_and_GR64_TCW64\000"
2458 /* 282 */ "GR64PLTSafe_and_GR64_TCW64\000"
2459 /* 309 */ "VK4\000"
2460 /* 313 */ "VR512_0_15\000"
2461 /* 324 */ "GRH16\000"
2462 /* 330 */ "VK16\000"
2463 /* 335 */ "FR16\000"
2464 /* 340 */ "GR16\000"
2465 /* 345 */ "VR256\000"
2466 /* 351 */ "RFP80_7\000"
2467 /* 359 */ "VR128\000"
2468 /* 365 */ "GRH8\000"
2469 /* 370 */ "VK8\000"
2470 /* 374 */ "GR8\000"
2471 /* 378 */ "GR64_A\000"
2472 /* 385 */ "GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB\000"
2473 /* 432 */ "GR64_with_sub_32bit_in_GR32_CB\000"
2474 /* 463 */ "GR32_DC\000"
2475 /* 471 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC\000"
2476 /* 516 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC\000"
2477 /* 561 */ "GR64_with_sub_32bit_in_GR32_TC\000"
2478 /* 592 */ "GR64_NOREX2_NOSP_and_GR64_TC\000"
2479 /* 621 */ "GR64_NOREX_and_GR64_TC\000"
2480 /* 644 */ "GR64_NOREX_and_GR64PLTSafe_and_GR64_TC\000"
2481 /* 683 */ "GR64_ArgRef_and_GR64_TC\000"
2482 /* 707 */ "GR32_AD\000"
2483 /* 715 */ "GR64_AD\000"
2484 /* 723 */ "GR32_ABCD\000"
2485 /* 733 */ "GR64_ABCD\000"
2486 /* 743 */ "GR16_ABCD\000"
2487 /* 753 */ "TILE\000"
2488 /* 758 */ "DEBUG_REG\000"
2489 /* 768 */ "CONTROL_REG\000"
2490 /* 780 */ "SEGMENT_REG\000"
2491 /* 792 */ "GR8_ABCD_H\000"
2492 /* 803 */ "GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI\000"
2493 /* 849 */ "GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI\000"
2494 /* 896 */ "GR64_with_sub_32bit_in_GR32_SIDI\000"
2495 /* 929 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI\000"
2496 /* 975 */ "GR64_with_sub_32bit_in_GR32_BSI\000"
2497 /* 1007 */ "GR8_ABCD_L\000"
2498 /* 1018 */ "VK1PAIR_with_sub_mask_0_in_VK1WM\000"
2499 /* 1051 */ "VK32WM\000"
2500 /* 1058 */ "VK2WM\000"
2501 /* 1064 */ "VK64WM\000"
2502 /* 1071 */ "VK4WM\000"
2503 /* 1077 */ "VK16WM\000"
2504 /* 1084 */ "VK8WM\000"
2505 /* 1090 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP\000"
2506 /* 1137 */ "GR64_with_sub_32bit_in_GR32_DIBP\000"
2507 /* 1170 */ "GR64_and_LOW32_ADDR_ACCESS_RBP\000"
2508 /* 1201 */ "GR32_NOSP\000"
2509 /* 1211 */ "GR32_NOREX2_NOSP\000"
2510 /* 1228 */ "GR64_NOREX2_NOSP\000"
2511 /* 1245 */ "GR64_NOSP\000"
2512 /* 1255 */ "GR32_NOREX_NOSP\000"
2513 /* 1271 */ "GR64_NOREX_NOSP\000"
2514 /* 1287 */ "GR64_with_sub_32bit_in_GR32_BPSP\000"
2515 /* 1320 */ "DFCCR\000"
2516 /* 1326 */ "FPCCR\000"
2517 /* 1332 */ "VK1PAIR\000"
2518 /* 1340 */ "VK2PAIR\000"
2519 /* 1348 */ "VK4PAIR\000"
2520 /* 1356 */ "VK16PAIR\000"
2521 /* 1365 */ "VK8PAIR\000"
2522 /* 1373 */ "GR64_and_LOW32_ADDR_ACCESS\000"
2523 /* 1400 */ "RST\000"
2524 /* 1404 */ "FR32X\000"
2525 /* 1410 */ "FR64X\000"
2526 /* 1416 */ "FR16X\000"
2527 /* 1422 */ "VR256X\000"
2528 /* 1429 */ "VR128X\000"
2529 /* 1436 */ "GR32_NOREX\000"
2530 /* 1447 */ "GR64_NOREX\000"
2531 /* 1458 */ "GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX\000"
2532 /* 1504 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX\000"
2533 /* 1555 */ "GR8_NOREX\000"
2534 /* 1565 */ "GR64PLTSafe\000"
2535 /* 1577 */ "GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef\000"
2536 /* 1624 */ "GR64_with_sub_32bit_in_GR32_ArgRef\000"
2537 /* 1659 */ "GR64_ArgRef\000"
2538 /* 1671 */ "LOW32_ADDR_ACCESS_RBP_with_sub_32bit\000"
2539 /* 1708 */ "LOW32_ADDR_ACCESS_with_sub_32bit\000"
2540 /* 1741 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit\000"
2541 /* 1792 */ "GR64_with_sub_8bit\000"
2542 /* 1811 */ "GR64_TCW64_with_sub_8bit\000"
2543 /* 1836 */ "GR64_TCW64_and_GR64_TC_with_sub_8bit\000"
2544 /* 1873 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit\000"
2545};
2546#ifdef __GNUC__
2547#pragma GCC diagnostic pop
2548#endif
2549
2550extern const MCRegisterClass X86MCRegisterClasses[] = {
2551 { .RegsBegin: GR8, .RegSet: GR8Bits, .NameIdx: 374, .RegsSize: 36, .RegSetSize: sizeof(GR8Bits), .ID: X86::GR8RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2552 { .RegsBegin: GRH8, .RegSet: GRH8Bits, .NameIdx: 365, .RegsSize: 28, .RegSetSize: sizeof(GRH8Bits), .ID: X86::GRH8RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2553 { .RegsBegin: GR8_NOREX2, .RegSet: GR8_NOREX2Bits, .NameIdx: 152, .RegsSize: 20, .RegSetSize: sizeof(GR8_NOREX2Bits), .ID: X86::GR8_NOREX2RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2554 { .RegsBegin: GR8_NOREX, .RegSet: GR8_NOREXBits, .NameIdx: 1555, .RegsSize: 8, .RegSetSize: sizeof(GR8_NOREXBits), .ID: X86::GR8_NOREXRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2555 { .RegsBegin: GR8_ABCD_H, .RegSet: GR8_ABCD_HBits, .NameIdx: 792, .RegsSize: 4, .RegSetSize: sizeof(GR8_ABCD_HBits), .ID: X86::GR8_ABCD_HRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2556 { .RegsBegin: GR8_ABCD_L, .RegSet: GR8_ABCD_LBits, .NameIdx: 1007, .RegsSize: 4, .RegSetSize: sizeof(GR8_ABCD_LBits), .ID: X86::GR8_ABCD_LRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2557 { .RegsBegin: GRH16, .RegSet: GRH16Bits, .NameIdx: 324, .RegsSize: 33, .RegSetSize: sizeof(GRH16Bits), .ID: X86::GRH16RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2558 { .RegsBegin: GR16, .RegSet: GR16Bits, .NameIdx: 340, .RegsSize: 32, .RegSetSize: sizeof(GR16Bits), .ID: X86::GR16RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2559 { .RegsBegin: GR16_NOREX2, .RegSet: GR16_NOREX2Bits, .NameIdx: 88, .RegsSize: 16, .RegSetSize: sizeof(GR16_NOREX2Bits), .ID: X86::GR16_NOREX2RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2560 { .RegsBegin: GR16_NOREX, .RegSet: GR16_NOREXBits, .NameIdx: 1493, .RegsSize: 8, .RegSetSize: sizeof(GR16_NOREXBits), .ID: X86::GR16_NOREXRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2561 { .RegsBegin: VK1, .RegSet: VK1Bits, .NameIdx: 6, .RegsSize: 8, .RegSetSize: sizeof(VK1Bits), .ID: X86::VK1RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2562 { .RegsBegin: VK16, .RegSet: VK16Bits, .NameIdx: 330, .RegsSize: 8, .RegSetSize: sizeof(VK16Bits), .ID: X86::VK16RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2563 { .RegsBegin: VK2, .RegSet: VK2Bits, .NameIdx: 37, .RegsSize: 8, .RegSetSize: sizeof(VK2Bits), .ID: X86::VK2RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2564 { .RegsBegin: VK4, .RegSet: VK4Bits, .NameIdx: 309, .RegsSize: 8, .RegSetSize: sizeof(VK4Bits), .ID: X86::VK4RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2565 { .RegsBegin: VK8, .RegSet: VK8Bits, .NameIdx: 370, .RegsSize: 8, .RegSetSize: sizeof(VK8Bits), .ID: X86::VK8RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2566 { .RegsBegin: VK16WM, .RegSet: VK16WMBits, .NameIdx: 1077, .RegsSize: 7, .RegSetSize: sizeof(VK16WMBits), .ID: X86::VK16WMRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2567 { .RegsBegin: VK1WM, .RegSet: VK1WMBits, .NameIdx: 1045, .RegsSize: 7, .RegSetSize: sizeof(VK1WMBits), .ID: X86::VK1WMRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2568 { .RegsBegin: VK2WM, .RegSet: VK2WMBits, .NameIdx: 1058, .RegsSize: 7, .RegSetSize: sizeof(VK2WMBits), .ID: X86::VK2WMRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2569 { .RegsBegin: VK4WM, .RegSet: VK4WMBits, .NameIdx: 1071, .RegsSize: 7, .RegSetSize: sizeof(VK4WMBits), .ID: X86::VK4WMRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2570 { .RegsBegin: VK8WM, .RegSet: VK8WMBits, .NameIdx: 1084, .RegsSize: 7, .RegSetSize: sizeof(VK8WMBits), .ID: X86::VK8WMRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2571 { .RegsBegin: SEGMENT_REG, .RegSet: SEGMENT_REGBits, .NameIdx: 780, .RegsSize: 6, .RegSetSize: sizeof(SEGMENT_REGBits), .ID: X86::SEGMENT_REGRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2572 { .RegsBegin: GR16_ABCD, .RegSet: GR16_ABCDBits, .NameIdx: 743, .RegsSize: 4, .RegSetSize: sizeof(GR16_ABCDBits), .ID: X86::GR16_ABCDRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2573 { .RegsBegin: FPCCR, .RegSet: FPCCRBits, .NameIdx: 1326, .RegsSize: 1, .RegSetSize: sizeof(FPCCRBits), .ID: X86::FPCCRRegClassID, .RegSizeInBits: 16, .CopyCost: 255, .Allocatable: false, .BaseClass: false },
2574 { .RegsBegin: FR16X, .RegSet: FR16XBits, .NameIdx: 1416, .RegsSize: 32, .RegSetSize: sizeof(FR16XBits), .ID: X86::FR16XRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2575 { .RegsBegin: FR16, .RegSet: FR16Bits, .NameIdx: 335, .RegsSize: 16, .RegSetSize: sizeof(FR16Bits), .ID: X86::FR16RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2576 { .RegsBegin: VK16PAIR, .RegSet: VK16PAIRBits, .NameIdx: 1356, .RegsSize: 4, .RegSetSize: sizeof(VK16PAIRBits), .ID: X86::VK16PAIRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2577 { .RegsBegin: VK1PAIR, .RegSet: VK1PAIRBits, .NameIdx: 1332, .RegsSize: 4, .RegSetSize: sizeof(VK1PAIRBits), .ID: X86::VK1PAIRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2578 { .RegsBegin: VK2PAIR, .RegSet: VK2PAIRBits, .NameIdx: 1340, .RegsSize: 4, .RegSetSize: sizeof(VK2PAIRBits), .ID: X86::VK2PAIRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2579 { .RegsBegin: VK4PAIR, .RegSet: VK4PAIRBits, .NameIdx: 1348, .RegsSize: 4, .RegSetSize: sizeof(VK4PAIRBits), .ID: X86::VK4PAIRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2580 { .RegsBegin: VK8PAIR, .RegSet: VK8PAIRBits, .NameIdx: 1365, .RegsSize: 4, .RegSetSize: sizeof(VK8PAIRBits), .ID: X86::VK8PAIRRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2581 { .RegsBegin: VK1PAIR_with_sub_mask_0_in_VK1WM, .RegSet: VK1PAIR_with_sub_mask_0_in_VK1WMBits, .NameIdx: 1018, .RegsSize: 3, .RegSetSize: sizeof(VK1PAIR_with_sub_mask_0_in_VK1WMBits), .ID: X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2582 { .RegsBegin: LOW32_ADDR_ACCESS_RBP, .RegSet: LOW32_ADDR_ACCESS_RBPBits, .NameIdx: 1179, .RegsSize: 34, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_RBPBits), .ID: X86::LOW32_ADDR_ACCESS_RBPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2583 { .RegsBegin: LOW32_ADDR_ACCESS, .RegSet: LOW32_ADDR_ACCESSBits, .NameIdx: 1382, .RegsSize: 33, .RegSetSize: sizeof(LOW32_ADDR_ACCESSBits), .ID: X86::LOW32_ADDR_ACCESSRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2584 { .RegsBegin: LOW32_ADDR_ACCESS_RBP_with_sub_8bit, .RegSet: LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, .NameIdx: 1873, .RegsSize: 33, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits), .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2585 { .RegsBegin: FR32X, .RegSet: FR32XBits, .NameIdx: 1404, .RegsSize: 32, .RegSetSize: sizeof(FR32XBits), .ID: X86::FR32XRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2586 { .RegsBegin: GR32, .RegSet: GR32Bits, .NameIdx: 32, .RegsSize: 32, .RegSetSize: sizeof(GR32Bits), .ID: X86::GR32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2587 { .RegsBegin: GR32_NOSP, .RegSet: GR32_NOSPBits, .NameIdx: 1201, .RegsSize: 31, .RegSetSize: sizeof(GR32_NOSPBits), .ID: X86::GR32_NOSPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2588 { .RegsBegin: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2, .RegSet: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits, .NameIdx: 100, .RegsSize: 17, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits), .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2589 { .RegsBegin: DEBUG_REG, .RegSet: DEBUG_REGBits, .NameIdx: 758, .RegsSize: 16, .RegSetSize: sizeof(DEBUG_REGBits), .ID: X86::DEBUG_REGRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2590 { .RegsBegin: FR32, .RegSet: FR32Bits, .NameIdx: 27, .RegsSize: 16, .RegSetSize: sizeof(FR32Bits), .ID: X86::FR32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2591 { .RegsBegin: GR32_NOREX2, .RegSet: GR32_NOREX2Bits, .NameIdx: 41, .RegsSize: 16, .RegSetSize: sizeof(GR32_NOREX2Bits), .ID: X86::GR32_NOREX2RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2592 { .RegsBegin: GR32_NOREX2_NOSP, .RegSet: GR32_NOREX2_NOSPBits, .NameIdx: 1211, .RegsSize: 15, .RegSetSize: sizeof(GR32_NOREX2_NOSPBits), .ID: X86::GR32_NOREX2_NOSPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2593 { .RegsBegin: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, .RegSet: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, .NameIdx: 1504, .RegsSize: 9, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits), .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2594 { .RegsBegin: GR32_NOREX, .RegSet: GR32_NOREXBits, .NameIdx: 1436, .RegsSize: 8, .RegSetSize: sizeof(GR32_NOREXBits), .ID: X86::GR32_NOREXRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2595 { .RegsBegin: VK32, .RegSet: VK32Bits, .NameIdx: 16, .RegsSize: 8, .RegSetSize: sizeof(VK32Bits), .ID: X86::VK32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2596 { .RegsBegin: GR32_NOREX_NOSP, .RegSet: GR32_NOREX_NOSPBits, .NameIdx: 1255, .RegsSize: 7, .RegSetSize: sizeof(GR32_NOREX_NOSPBits), .ID: X86::GR32_NOREX_NOSPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2597 { .RegsBegin: RFP32, .RegSet: RFP32Bits, .NameIdx: 21, .RegsSize: 7, .RegSetSize: sizeof(RFP32Bits), .ID: X86::RFP32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2598 { .RegsBegin: VK32WM, .RegSet: VK32WMBits, .NameIdx: 1051, .RegsSize: 7, .RegSetSize: sizeof(VK32WMBits), .ID: X86::VK32WMRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2599 { .RegsBegin: GR32_ABCD, .RegSet: GR32_ABCDBits, .NameIdx: 723, .RegsSize: 4, .RegSetSize: sizeof(GR32_ABCDBits), .ID: X86::GR32_ABCDRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2600 { .RegsBegin: GR32_TC, .RegSet: GR32_TCBits, .NameIdx: 508, .RegsSize: 4, .RegSetSize: sizeof(GR32_TCBits), .ID: X86::GR32_TCRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2601 { .RegsBegin: GR32_ABCD_and_GR32_TC, .RegSet: GR32_ABCD_and_GR32_TCBits, .NameIdx: 494, .RegsSize: 3, .RegSetSize: sizeof(GR32_ABCD_and_GR32_TCBits), .ID: X86::GR32_ABCD_and_GR32_TCRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2602 { .RegsBegin: GR32_AD, .RegSet: GR32_ADBits, .NameIdx: 707, .RegsSize: 2, .RegSetSize: sizeof(GR32_ADBits), .ID: X86::GR32_ADRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2603 { .RegsBegin: GR32_ArgRef, .RegSet: GR32_ArgRefBits, .NameIdx: 1612, .RegsSize: 2, .RegSetSize: sizeof(GR32_ArgRefBits), .ID: X86::GR32_ArgRefRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2604 { .RegsBegin: GR32_BPSP, .RegSet: GR32_BPSPBits, .NameIdx: 1310, .RegsSize: 2, .RegSetSize: sizeof(GR32_BPSPBits), .ID: X86::GR32_BPSPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2605 { .RegsBegin: GR32_BSI, .RegSet: GR32_BSIBits, .NameIdx: 966, .RegsSize: 2, .RegSetSize: sizeof(GR32_BSIBits), .ID: X86::GR32_BSIRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2606 { .RegsBegin: GR32_CB, .RegSet: GR32_CBBits, .NameIdx: 424, .RegsSize: 2, .RegSetSize: sizeof(GR32_CBBits), .ID: X86::GR32_CBRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2607 { .RegsBegin: GR32_DC, .RegSet: GR32_DCBits, .NameIdx: 463, .RegsSize: 2, .RegSetSize: sizeof(GR32_DCBits), .ID: X86::GR32_DCRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2608 { .RegsBegin: GR32_DIBP, .RegSet: GR32_DIBPBits, .NameIdx: 1127, .RegsSize: 2, .RegSetSize: sizeof(GR32_DIBPBits), .ID: X86::GR32_DIBPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2609 { .RegsBegin: GR32_SIDI, .RegSet: GR32_SIDIBits, .NameIdx: 839, .RegsSize: 2, .RegSetSize: sizeof(GR32_SIDIBits), .ID: X86::GR32_SIDIRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2610 { .RegsBegin: LOW32_ADDR_ACCESS_RBP_with_sub_32bit, .RegSet: LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, .NameIdx: 1671, .RegsSize: 2, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits), .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2611 { .RegsBegin: CCR, .RegSet: CCRBits, .NameIdx: 1322, .RegsSize: 1, .RegSetSize: sizeof(CCRBits), .ID: X86::CCRRegClassID, .RegSizeInBits: 32, .CopyCost: 255, .Allocatable: false, .BaseClass: false },
2612 { .RegsBegin: DFCCR, .RegSet: DFCCRBits, .NameIdx: 1320, .RegsSize: 1, .RegSetSize: sizeof(DFCCRBits), .ID: X86::DFCCRRegClassID, .RegSizeInBits: 32, .CopyCost: 255, .Allocatable: false, .BaseClass: false },
2613 { .RegsBegin: GR32_ABCD_and_GR32_BSI, .RegSet: GR32_ABCD_and_GR32_BSIBits, .NameIdx: 952, .RegsSize: 1, .RegSetSize: sizeof(GR32_ABCD_and_GR32_BSIBits), .ID: X86::GR32_ABCD_and_GR32_BSIRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2614 { .RegsBegin: GR32_AD_and_GR32_ArgRef, .RegSet: GR32_AD_and_GR32_ArgRefBits, .NameIdx: 1600, .RegsSize: 1, .RegSetSize: sizeof(GR32_AD_and_GR32_ArgRefBits), .ID: X86::GR32_AD_and_GR32_ArgRefRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2615 { .RegsBegin: GR32_ArgRef_and_GR32_CB, .RegSet: GR32_ArgRef_and_GR32_CBBits, .NameIdx: 408, .RegsSize: 1, .RegSetSize: sizeof(GR32_ArgRef_and_GR32_CBBits), .ID: X86::GR32_ArgRef_and_GR32_CBRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2616 { .RegsBegin: GR32_BPSP_and_GR32_DIBP, .RegSet: GR32_BPSP_and_GR32_DIBPBits, .NameIdx: 1113, .RegsSize: 1, .RegSetSize: sizeof(GR32_BPSP_and_GR32_DIBPBits), .ID: X86::GR32_BPSP_and_GR32_DIBPRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2617 { .RegsBegin: GR32_BPSP_and_GR32_TC, .RegSet: GR32_BPSP_and_GR32_TCBits, .NameIdx: 539, .RegsSize: 1, .RegSetSize: sizeof(GR32_BPSP_and_GR32_TCBits), .ID: X86::GR32_BPSP_and_GR32_TCRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2618 { .RegsBegin: GR32_BSI_and_GR32_SIDI, .RegSet: GR32_BSI_and_GR32_SIDIBits, .NameIdx: 826, .RegsSize: 1, .RegSetSize: sizeof(GR32_BSI_and_GR32_SIDIBits), .ID: X86::GR32_BSI_and_GR32_SIDIRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2619 { .RegsBegin: GR32_DIBP_and_GR32_SIDI, .RegSet: GR32_DIBP_and_GR32_SIDIBits, .NameIdx: 872, .RegsSize: 1, .RegSetSize: sizeof(GR32_DIBP_and_GR32_SIDIBits), .ID: X86::GR32_DIBP_and_GR32_SIDIRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2620 { .RegsBegin: LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, .RegSet: LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, .NameIdx: 1741, .RegsSize: 1, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits), .ID: X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2621 { .RegsBegin: LOW32_ADDR_ACCESS_with_sub_32bit, .RegSet: LOW32_ADDR_ACCESS_with_sub_32bitBits, .NameIdx: 1708, .RegsSize: 1, .RegSetSize: sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits), .ID: X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2622 { .RegsBegin: RFP64, .RegSet: RFP64Bits, .NameIdx: 168, .RegsSize: 7, .RegSetSize: sizeof(RFP64Bits), .ID: X86::RFP64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2623 { .RegsBegin: GR64, .RegSet: GR64Bits, .NameIdx: 179, .RegsSize: 33, .RegSetSize: sizeof(GR64Bits), .ID: X86::GR64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2624 { .RegsBegin: FR64X, .RegSet: FR64XBits, .NameIdx: 1410, .RegsSize: 32, .RegSetSize: sizeof(FR64XBits), .ID: X86::FR64XRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2625 { .RegsBegin: GR64_with_sub_8bit, .RegSet: GR64_with_sub_8bitBits, .NameIdx: 1792, .RegsSize: 32, .RegSetSize: sizeof(GR64_with_sub_8bitBits), .ID: X86::GR64_with_sub_8bitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2626 { .RegsBegin: GR64_NOSP, .RegSet: GR64_NOSPBits, .NameIdx: 1245, .RegsSize: 31, .RegSetSize: sizeof(GR64_NOSPBits), .ID: X86::GR64_NOSPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2627 { .RegsBegin: GR64_NOREX2, .RegSet: GR64_NOREX2Bits, .NameIdx: 53, .RegsSize: 17, .RegSetSize: sizeof(GR64_NOREX2Bits), .ID: X86::GR64_NOREX2RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2628 { .RegsBegin: CONTROL_REG, .RegSet: CONTROL_REGBits, .NameIdx: 768, .RegsSize: 16, .RegSetSize: sizeof(CONTROL_REGBits), .ID: X86::CONTROL_REGRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2629 { .RegsBegin: FR64, .RegSet: FR64Bits, .NameIdx: 174, .RegsSize: 16, .RegSetSize: sizeof(FR64Bits), .ID: X86::FR64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2630 { .RegsBegin: GR64_with_sub_16bit_in_GR16_NOREX2, .RegSet: GR64_with_sub_16bit_in_GR16_NOREX2Bits, .NameIdx: 65, .RegsSize: 16, .RegSetSize: sizeof(GR64_with_sub_16bit_in_GR16_NOREX2Bits), .ID: X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2631 { .RegsBegin: GR64_NOREX2_NOSP, .RegSet: GR64_NOREX2_NOSPBits, .NameIdx: 1228, .RegsSize: 15, .RegSetSize: sizeof(GR64_NOREX2_NOSPBits), .ID: X86::GR64_NOREX2_NOSPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2632 { .RegsBegin: GR64PLTSafe, .RegSet: GR64PLTSafeBits, .NameIdx: 1565, .RegsSize: 13, .RegSetSize: sizeof(GR64PLTSafeBits), .ID: X86::GR64PLTSafeRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2633 { .RegsBegin: GR64_TC, .RegSet: GR64_TCBits, .NameIdx: 613, .RegsSize: 10, .RegSetSize: sizeof(GR64_TCBits), .ID: X86::GR64_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2634 { .RegsBegin: GR64_NOREX, .RegSet: GR64_NOREXBits, .NameIdx: 1447, .RegsSize: 9, .RegSetSize: sizeof(GR64_NOREXBits), .ID: X86::GR64_NOREXRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2635 { .RegsBegin: GR64_TCW64, .RegSet: GR64_TCW64Bits, .NameIdx: 201, .RegsSize: 9, .RegSetSize: sizeof(GR64_TCW64Bits), .ID: X86::GR64_TCW64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2636 { .RegsBegin: GR64_TC_with_sub_8bit, .RegSet: GR64_TC_with_sub_8bitBits, .NameIdx: 1851, .RegsSize: 9, .RegSetSize: sizeof(GR64_TC_with_sub_8bitBits), .ID: X86::GR64_TC_with_sub_8bitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2637 { .RegsBegin: GR64_NOREX2_NOSP_and_GR64_TC, .RegSet: GR64_NOREX2_NOSP_and_GR64_TCBits, .NameIdx: 592, .RegsSize: 8, .RegSetSize: sizeof(GR64_NOREX2_NOSP_and_GR64_TCBits), .ID: X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2638 { .RegsBegin: GR64_TCW64_with_sub_8bit, .RegSet: GR64_TCW64_with_sub_8bitBits, .NameIdx: 1811, .RegsSize: 8, .RegSetSize: sizeof(GR64_TCW64_with_sub_8bitBits), .ID: X86::GR64_TCW64_with_sub_8bitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2639 { .RegsBegin: GR64_TC_and_GR64_TCW64, .RegSet: GR64_TC_and_GR64_TCW64Bits, .NameIdx: 189, .RegsSize: 8, .RegSetSize: sizeof(GR64_TC_and_GR64_TCW64Bits), .ID: X86::GR64_TC_and_GR64_TCW64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2640 { .RegsBegin: GR64_with_sub_16bit_in_GR16_NOREX, .RegSet: GR64_with_sub_16bit_in_GR16_NOREXBits, .NameIdx: 1470, .RegsSize: 8, .RegSetSize: sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits), .ID: X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2641 { .RegsBegin: VK64, .RegSet: VK64Bits, .NameIdx: 163, .RegsSize: 8, .RegSetSize: sizeof(VK64Bits), .ID: X86::VK64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2642 { .RegsBegin: VR64, .RegSet: VR64Bits, .NameIdx: 184, .RegsSize: 8, .RegSetSize: sizeof(VR64Bits), .ID: X86::VR64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2643 { .RegsBegin: GR64PLTSafe_and_GR64_TC, .RegSet: GR64PLTSafe_and_GR64_TCBits, .NameIdx: 659, .RegsSize: 7, .RegSetSize: sizeof(GR64PLTSafe_and_GR64_TCBits), .ID: X86::GR64PLTSafe_and_GR64_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2644 { .RegsBegin: GR64_NOREX2_NOSP_and_GR64_TCW64, .RegSet: GR64_NOREX2_NOSP_and_GR64_TCW64Bits, .NameIdx: 224, .RegsSize: 7, .RegSetSize: sizeof(GR64_NOREX2_NOSP_and_GR64_TCW64Bits), .ID: X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2645 { .RegsBegin: GR64_NOREX_NOSP, .RegSet: GR64_NOREX_NOSPBits, .NameIdx: 1271, .RegsSize: 7, .RegSetSize: sizeof(GR64_NOREX_NOSPBits), .ID: X86::GR64_NOREX_NOSPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2646 { .RegsBegin: GR64_NOREX_and_GR64_TC, .RegSet: GR64_NOREX_and_GR64_TCBits, .NameIdx: 621, .RegsSize: 7, .RegSetSize: sizeof(GR64_NOREX_and_GR64_TCBits), .ID: X86::GR64_NOREX_and_GR64_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2647 { .RegsBegin: GR64_TCW64_and_GR64_TC_with_sub_8bit, .RegSet: GR64_TCW64_and_GR64_TC_with_sub_8bitBits, .NameIdx: 1836, .RegsSize: 7, .RegSetSize: sizeof(GR64_TCW64_and_GR64_TC_with_sub_8bitBits), .ID: X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2648 { .RegsBegin: VK64WM, .RegSet: VK64WMBits, .NameIdx: 1064, .RegsSize: 7, .RegSetSize: sizeof(VK64WMBits), .ID: X86::VK64WMRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2649 { .RegsBegin: GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64, .RegSet: GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits, .NameIdx: 212, .RegsSize: 6, .RegSetSize: sizeof(GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits), .ID: X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2650 { .RegsBegin: GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX, .RegSet: GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits, .NameIdx: 1458, .RegsSize: 6, .RegSetSize: sizeof(GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits), .ID: X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2651 { .RegsBegin: GR64PLTSafe_and_GR64_TCW64, .RegSet: GR64PLTSafe_and_GR64_TCW64Bits, .NameIdx: 282, .RegsSize: 5, .RegSetSize: sizeof(GR64PLTSafe_and_GR64_TCW64Bits), .ID: X86::GR64PLTSafe_and_GR64_TCW64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2652 { .RegsBegin: GR64_NOREX_and_GR64PLTSafe_and_GR64_TC, .RegSet: GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits, .NameIdx: 644, .RegsSize: 5, .RegSetSize: sizeof(GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits), .ID: X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2653 { .RegsBegin: GR64_NOREX_and_GR64_TCW64, .RegSet: GR64_NOREX_and_GR64_TCW64Bits, .NameIdx: 256, .RegsSize: 5, .RegSetSize: sizeof(GR64_NOREX_and_GR64_TCW64Bits), .ID: X86::GR64_NOREX_and_GR64_TCW64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2654 { .RegsBegin: GR64_ABCD, .RegSet: GR64_ABCDBits, .NameIdx: 733, .RegsSize: 4, .RegSetSize: sizeof(GR64_ABCDBits), .ID: X86::GR64_ABCDRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2655 { .RegsBegin: GR64_with_sub_32bit_in_GR32_TC, .RegSet: GR64_with_sub_32bit_in_GR32_TCBits, .NameIdx: 561, .RegsSize: 4, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_TCBits), .ID: X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2656 { .RegsBegin: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC, .RegSet: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits, .NameIdx: 471, .RegsSize: 3, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits), .ID: X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2657 { .RegsBegin: GR64_AD, .RegSet: GR64_ADBits, .NameIdx: 715, .RegsSize: 2, .RegSetSize: sizeof(GR64_ADBits), .ID: X86::GR64_ADRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2658 { .RegsBegin: GR64_ArgRef, .RegSet: GR64_ArgRefBits, .NameIdx: 1659, .RegsSize: 2, .RegSetSize: sizeof(GR64_ArgRefBits), .ID: X86::GR64_ArgRefRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2659 { .RegsBegin: GR64_and_LOW32_ADDR_ACCESS_RBP, .RegSet: GR64_and_LOW32_ADDR_ACCESS_RBPBits, .NameIdx: 1170, .RegsSize: 2, .RegSetSize: sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits), .ID: X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2660 { .RegsBegin: GR64_with_sub_32bit_in_GR32_ArgRef, .RegSet: GR64_with_sub_32bit_in_GR32_ArgRefBits, .NameIdx: 1624, .RegsSize: 2, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_ArgRefBits), .ID: X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2661 { .RegsBegin: GR64_with_sub_32bit_in_GR32_BPSP, .RegSet: GR64_with_sub_32bit_in_GR32_BPSPBits, .NameIdx: 1287, .RegsSize: 2, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_BPSPBits), .ID: X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2662 { .RegsBegin: GR64_with_sub_32bit_in_GR32_BSI, .RegSet: GR64_with_sub_32bit_in_GR32_BSIBits, .NameIdx: 975, .RegsSize: 2, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_BSIBits), .ID: X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2663 { .RegsBegin: GR64_with_sub_32bit_in_GR32_CB, .RegSet: GR64_with_sub_32bit_in_GR32_CBBits, .NameIdx: 432, .RegsSize: 2, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_CBBits), .ID: X86::GR64_with_sub_32bit_in_GR32_CBRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2664 { .RegsBegin: GR64_with_sub_32bit_in_GR32_DIBP, .RegSet: GR64_with_sub_32bit_in_GR32_DIBPBits, .NameIdx: 1137, .RegsSize: 2, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_DIBPBits), .ID: X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2665 { .RegsBegin: GR64_with_sub_32bit_in_GR32_SIDI, .RegSet: GR64_with_sub_32bit_in_GR32_SIDIBits, .NameIdx: 896, .RegsSize: 2, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_SIDIBits), .ID: X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2666 { .RegsBegin: GR64_A, .RegSet: GR64_ABits, .NameIdx: 378, .RegsSize: 1, .RegSetSize: sizeof(GR64_ABits), .ID: X86::GR64_ARegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2667 { .RegsBegin: GR64_ArgRef_and_GR64_TC, .RegSet: GR64_ArgRef_and_GR64_TCBits, .NameIdx: 683, .RegsSize: 1, .RegSetSize: sizeof(GR64_ArgRef_and_GR64_TCBits), .ID: X86::GR64_ArgRef_and_GR64_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2668 { .RegsBegin: GR64_and_LOW32_ADDR_ACCESS, .RegSet: GR64_and_LOW32_ADDR_ACCESSBits, .NameIdx: 1373, .RegsSize: 1, .RegSetSize: sizeof(GR64_and_LOW32_ADDR_ACCESSBits), .ID: X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2669 { .RegsBegin: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI, .RegSet: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits, .NameIdx: 929, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits), .ID: X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2670 { .RegsBegin: GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef, .RegSet: GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits, .NameIdx: 1577, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits), .ID: X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2671 { .RegsBegin: GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB, .RegSet: GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits, .NameIdx: 385, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits), .ID: X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2672 { .RegsBegin: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP, .RegSet: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits, .NameIdx: 1090, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits), .ID: X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2673 { .RegsBegin: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC, .RegSet: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits, .NameIdx: 516, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits), .ID: X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2674 { .RegsBegin: GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI, .RegSet: GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits, .NameIdx: 803, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits), .ID: X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2675 { .RegsBegin: GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI, .RegSet: GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits, .NameIdx: 849, .RegsSize: 1, .RegSetSize: sizeof(GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits), .ID: X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2676 { .RegsBegin: RST, .RegSet: RSTBits, .NameIdx: 1400, .RegsSize: 8, .RegSetSize: sizeof(RSTBits), .ID: X86::RSTRegClassID, .RegSizeInBits: 80, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2677 { .RegsBegin: RFP80, .RegSet: RFP80Bits, .NameIdx: 0, .RegsSize: 7, .RegSetSize: sizeof(RFP80Bits), .ID: X86::RFP80RegClassID, .RegSizeInBits: 80, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2678 { .RegsBegin: RFP80_7, .RegSet: RFP80_7Bits, .NameIdx: 351, .RegsSize: 1, .RegSetSize: sizeof(RFP80_7Bits), .ID: X86::RFP80_7RegClassID, .RegSizeInBits: 80, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
2679 { .RegsBegin: VR128X, .RegSet: VR128XBits, .NameIdx: 1429, .RegsSize: 32, .RegSetSize: sizeof(VR128XBits), .ID: X86::VR128XRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2680 { .RegsBegin: VR128, .RegSet: VR128Bits, .NameIdx: 359, .RegsSize: 16, .RegSetSize: sizeof(VR128Bits), .ID: X86::VR128RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2681 { .RegsBegin: VR256X, .RegSet: VR256XBits, .NameIdx: 1422, .RegsSize: 32, .RegSetSize: sizeof(VR256XBits), .ID: X86::VR256XRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2682 { .RegsBegin: VR256, .RegSet: VR256Bits, .NameIdx: 345, .RegsSize: 16, .RegSetSize: sizeof(VR256Bits), .ID: X86::VR256RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2683 { .RegsBegin: VR512, .RegSet: VR512Bits, .NameIdx: 10, .RegsSize: 32, .RegSetSize: sizeof(VR512Bits), .ID: X86::VR512RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2684 { .RegsBegin: VR512_0_15, .RegSet: VR512_0_15Bits, .NameIdx: 313, .RegsSize: 16, .RegSetSize: sizeof(VR512_0_15Bits), .ID: X86::VR512_0_15RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
2685 { .RegsBegin: TILE, .RegSet: TILEBits, .NameIdx: 753, .RegsSize: 8, .RegSetSize: sizeof(TILEBits), .ID: X86::TILERegClassID, .RegSizeInBits: 8192, .CopyCost: 255, .Allocatable: true, .BaseClass: false },
2686};
2687
2688// X86 Dwarf<->LLVM register mappings.
2689extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
2690 { .FromReg: 0U, .ToReg: X86::RAX },
2691 { .FromReg: 1U, .ToReg: X86::RDX },
2692 { .FromReg: 2U, .ToReg: X86::RCX },
2693 { .FromReg: 3U, .ToReg: X86::RBX },
2694 { .FromReg: 4U, .ToReg: X86::RSI },
2695 { .FromReg: 5U, .ToReg: X86::RDI },
2696 { .FromReg: 6U, .ToReg: X86::RBP },
2697 { .FromReg: 7U, .ToReg: X86::RSP },
2698 { .FromReg: 8U, .ToReg: X86::R8 },
2699 { .FromReg: 9U, .ToReg: X86::R9 },
2700 { .FromReg: 10U, .ToReg: X86::R10 },
2701 { .FromReg: 11U, .ToReg: X86::R11 },
2702 { .FromReg: 12U, .ToReg: X86::R12 },
2703 { .FromReg: 13U, .ToReg: X86::R13 },
2704 { .FromReg: 14U, .ToReg: X86::R14 },
2705 { .FromReg: 15U, .ToReg: X86::R15 },
2706 { .FromReg: 16U, .ToReg: X86::RIP },
2707 { .FromReg: 17U, .ToReg: X86::XMM0 },
2708 { .FromReg: 18U, .ToReg: X86::XMM1 },
2709 { .FromReg: 19U, .ToReg: X86::XMM2 },
2710 { .FromReg: 20U, .ToReg: X86::XMM3 },
2711 { .FromReg: 21U, .ToReg: X86::XMM4 },
2712 { .FromReg: 22U, .ToReg: X86::XMM5 },
2713 { .FromReg: 23U, .ToReg: X86::XMM6 },
2714 { .FromReg: 24U, .ToReg: X86::XMM7 },
2715 { .FromReg: 25U, .ToReg: X86::XMM8 },
2716 { .FromReg: 26U, .ToReg: X86::XMM9 },
2717 { .FromReg: 27U, .ToReg: X86::XMM10 },
2718 { .FromReg: 28U, .ToReg: X86::XMM11 },
2719 { .FromReg: 29U, .ToReg: X86::XMM12 },
2720 { .FromReg: 30U, .ToReg: X86::XMM13 },
2721 { .FromReg: 31U, .ToReg: X86::XMM14 },
2722 { .FromReg: 32U, .ToReg: X86::XMM15 },
2723 { .FromReg: 33U, .ToReg: X86::ST0 },
2724 { .FromReg: 34U, .ToReg: X86::ST1 },
2725 { .FromReg: 35U, .ToReg: X86::ST2 },
2726 { .FromReg: 36U, .ToReg: X86::ST3 },
2727 { .FromReg: 37U, .ToReg: X86::ST4 },
2728 { .FromReg: 38U, .ToReg: X86::ST5 },
2729 { .FromReg: 39U, .ToReg: X86::ST6 },
2730 { .FromReg: 40U, .ToReg: X86::ST7 },
2731 { .FromReg: 41U, .ToReg: X86::MM0 },
2732 { .FromReg: 42U, .ToReg: X86::MM1 },
2733 { .FromReg: 43U, .ToReg: X86::MM2 },
2734 { .FromReg: 44U, .ToReg: X86::MM3 },
2735 { .FromReg: 45U, .ToReg: X86::MM4 },
2736 { .FromReg: 46U, .ToReg: X86::MM5 },
2737 { .FromReg: 47U, .ToReg: X86::MM6 },
2738 { .FromReg: 48U, .ToReg: X86::MM7 },
2739 { .FromReg: 49U, .ToReg: X86::RFLAGS },
2740 { .FromReg: 50U, .ToReg: X86::ES },
2741 { .FromReg: 51U, .ToReg: X86::CS },
2742 { .FromReg: 52U, .ToReg: X86::SS },
2743 { .FromReg: 53U, .ToReg: X86::DS },
2744 { .FromReg: 54U, .ToReg: X86::FS },
2745 { .FromReg: 55U, .ToReg: X86::GS },
2746 { .FromReg: 58U, .ToReg: X86::FS_BASE },
2747 { .FromReg: 59U, .ToReg: X86::GS_BASE },
2748 { .FromReg: 67U, .ToReg: X86::XMM16 },
2749 { .FromReg: 68U, .ToReg: X86::XMM17 },
2750 { .FromReg: 69U, .ToReg: X86::XMM18 },
2751 { .FromReg: 70U, .ToReg: X86::XMM19 },
2752 { .FromReg: 71U, .ToReg: X86::XMM20 },
2753 { .FromReg: 72U, .ToReg: X86::XMM21 },
2754 { .FromReg: 73U, .ToReg: X86::XMM22 },
2755 { .FromReg: 74U, .ToReg: X86::XMM23 },
2756 { .FromReg: 75U, .ToReg: X86::XMM24 },
2757 { .FromReg: 76U, .ToReg: X86::XMM25 },
2758 { .FromReg: 77U, .ToReg: X86::XMM26 },
2759 { .FromReg: 78U, .ToReg: X86::XMM27 },
2760 { .FromReg: 79U, .ToReg: X86::XMM28 },
2761 { .FromReg: 80U, .ToReg: X86::XMM29 },
2762 { .FromReg: 81U, .ToReg: X86::XMM30 },
2763 { .FromReg: 82U, .ToReg: X86::XMM31 },
2764 { .FromReg: 118U, .ToReg: X86::K0 },
2765 { .FromReg: 119U, .ToReg: X86::K1 },
2766 { .FromReg: 120U, .ToReg: X86::K2 },
2767 { .FromReg: 121U, .ToReg: X86::K3 },
2768 { .FromReg: 122U, .ToReg: X86::K4 },
2769 { .FromReg: 123U, .ToReg: X86::K5 },
2770 { .FromReg: 124U, .ToReg: X86::K6 },
2771 { .FromReg: 125U, .ToReg: X86::K7 },
2772 { .FromReg: 130U, .ToReg: X86::R16 },
2773 { .FromReg: 131U, .ToReg: X86::R17 },
2774 { .FromReg: 132U, .ToReg: X86::R18 },
2775 { .FromReg: 133U, .ToReg: X86::R19 },
2776 { .FromReg: 134U, .ToReg: X86::R20 },
2777 { .FromReg: 135U, .ToReg: X86::R21 },
2778 { .FromReg: 136U, .ToReg: X86::R22 },
2779 { .FromReg: 137U, .ToReg: X86::R23 },
2780 { .FromReg: 138U, .ToReg: X86::R24 },
2781 { .FromReg: 139U, .ToReg: X86::R25 },
2782 { .FromReg: 140U, .ToReg: X86::R26 },
2783 { .FromReg: 141U, .ToReg: X86::R27 },
2784 { .FromReg: 142U, .ToReg: X86::R28 },
2785 { .FromReg: 143U, .ToReg: X86::R29 },
2786 { .FromReg: 144U, .ToReg: X86::R30 },
2787 { .FromReg: 145U, .ToReg: X86::R31 },
2788};
2789extern const unsigned X86DwarfFlavour0Dwarf2LSize = std::size(X86DwarfFlavour0Dwarf2L);
2790
2791extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
2792 { .FromReg: 0U, .ToReg: X86::EAX },
2793 { .FromReg: 1U, .ToReg: X86::ECX },
2794 { .FromReg: 2U, .ToReg: X86::EDX },
2795 { .FromReg: 3U, .ToReg: X86::EBX },
2796 { .FromReg: 4U, .ToReg: X86::EBP },
2797 { .FromReg: 5U, .ToReg: X86::ESP },
2798 { .FromReg: 6U, .ToReg: X86::ESI },
2799 { .FromReg: 7U, .ToReg: X86::EDI },
2800 { .FromReg: 8U, .ToReg: X86::EIP },
2801 { .FromReg: 9U, .ToReg: X86::EFLAGS },
2802 { .FromReg: 12U, .ToReg: X86::ST0 },
2803 { .FromReg: 13U, .ToReg: X86::ST1 },
2804 { .FromReg: 14U, .ToReg: X86::ST2 },
2805 { .FromReg: 15U, .ToReg: X86::ST3 },
2806 { .FromReg: 16U, .ToReg: X86::ST4 },
2807 { .FromReg: 17U, .ToReg: X86::ST5 },
2808 { .FromReg: 18U, .ToReg: X86::ST6 },
2809 { .FromReg: 19U, .ToReg: X86::ST7 },
2810 { .FromReg: 21U, .ToReg: X86::XMM0 },
2811 { .FromReg: 22U, .ToReg: X86::XMM1 },
2812 { .FromReg: 23U, .ToReg: X86::XMM2 },
2813 { .FromReg: 24U, .ToReg: X86::XMM3 },
2814 { .FromReg: 25U, .ToReg: X86::XMM4 },
2815 { .FromReg: 26U, .ToReg: X86::XMM5 },
2816 { .FromReg: 27U, .ToReg: X86::XMM6 },
2817 { .FromReg: 28U, .ToReg: X86::XMM7 },
2818 { .FromReg: 29U, .ToReg: X86::MM0 },
2819 { .FromReg: 30U, .ToReg: X86::MM1 },
2820 { .FromReg: 31U, .ToReg: X86::MM2 },
2821 { .FromReg: 32U, .ToReg: X86::MM3 },
2822 { .FromReg: 33U, .ToReg: X86::MM4 },
2823 { .FromReg: 34U, .ToReg: X86::MM5 },
2824 { .FromReg: 35U, .ToReg: X86::MM6 },
2825 { .FromReg: 36U, .ToReg: X86::MM7 },
2826 { .FromReg: 93U, .ToReg: X86::K0 },
2827 { .FromReg: 94U, .ToReg: X86::K1 },
2828 { .FromReg: 95U, .ToReg: X86::K2 },
2829 { .FromReg: 96U, .ToReg: X86::K3 },
2830 { .FromReg: 97U, .ToReg: X86::K4 },
2831 { .FromReg: 98U, .ToReg: X86::K5 },
2832 { .FromReg: 99U, .ToReg: X86::K6 },
2833 { .FromReg: 100U, .ToReg: X86::K7 },
2834};
2835extern const unsigned X86DwarfFlavour1Dwarf2LSize = std::size(X86DwarfFlavour1Dwarf2L);
2836
2837extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
2838 { .FromReg: 0U, .ToReg: X86::EAX },
2839 { .FromReg: 1U, .ToReg: X86::ECX },
2840 { .FromReg: 2U, .ToReg: X86::EDX },
2841 { .FromReg: 3U, .ToReg: X86::EBX },
2842 { .FromReg: 4U, .ToReg: X86::ESP },
2843 { .FromReg: 5U, .ToReg: X86::EBP },
2844 { .FromReg: 6U, .ToReg: X86::ESI },
2845 { .FromReg: 7U, .ToReg: X86::EDI },
2846 { .FromReg: 8U, .ToReg: X86::EIP },
2847 { .FromReg: 9U, .ToReg: X86::EFLAGS },
2848 { .FromReg: 11U, .ToReg: X86::ST0 },
2849 { .FromReg: 12U, .ToReg: X86::ST1 },
2850 { .FromReg: 13U, .ToReg: X86::ST2 },
2851 { .FromReg: 14U, .ToReg: X86::ST3 },
2852 { .FromReg: 15U, .ToReg: X86::ST4 },
2853 { .FromReg: 16U, .ToReg: X86::ST5 },
2854 { .FromReg: 17U, .ToReg: X86::ST6 },
2855 { .FromReg: 18U, .ToReg: X86::ST7 },
2856 { .FromReg: 21U, .ToReg: X86::XMM0 },
2857 { .FromReg: 22U, .ToReg: X86::XMM1 },
2858 { .FromReg: 23U, .ToReg: X86::XMM2 },
2859 { .FromReg: 24U, .ToReg: X86::XMM3 },
2860 { .FromReg: 25U, .ToReg: X86::XMM4 },
2861 { .FromReg: 26U, .ToReg: X86::XMM5 },
2862 { .FromReg: 27U, .ToReg: X86::XMM6 },
2863 { .FromReg: 28U, .ToReg: X86::XMM7 },
2864 { .FromReg: 29U, .ToReg: X86::MM0 },
2865 { .FromReg: 30U, .ToReg: X86::MM1 },
2866 { .FromReg: 31U, .ToReg: X86::MM2 },
2867 { .FromReg: 32U, .ToReg: X86::MM3 },
2868 { .FromReg: 33U, .ToReg: X86::MM4 },
2869 { .FromReg: 34U, .ToReg: X86::MM5 },
2870 { .FromReg: 35U, .ToReg: X86::MM6 },
2871 { .FromReg: 36U, .ToReg: X86::MM7 },
2872 { .FromReg: 40U, .ToReg: X86::ES },
2873 { .FromReg: 41U, .ToReg: X86::CS },
2874 { .FromReg: 42U, .ToReg: X86::SS },
2875 { .FromReg: 43U, .ToReg: X86::DS },
2876 { .FromReg: 44U, .ToReg: X86::FS },
2877 { .FromReg: 45U, .ToReg: X86::GS },
2878 { .FromReg: 93U, .ToReg: X86::K0 },
2879 { .FromReg: 94U, .ToReg: X86::K1 },
2880 { .FromReg: 95U, .ToReg: X86::K2 },
2881 { .FromReg: 96U, .ToReg: X86::K3 },
2882 { .FromReg: 97U, .ToReg: X86::K4 },
2883 { .FromReg: 98U, .ToReg: X86::K5 },
2884 { .FromReg: 99U, .ToReg: X86::K6 },
2885 { .FromReg: 100U, .ToReg: X86::K7 },
2886};
2887extern const unsigned X86DwarfFlavour2Dwarf2LSize = std::size(X86DwarfFlavour2Dwarf2L);
2888
2889extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
2890 { .FromReg: 0U, .ToReg: X86::RAX },
2891 { .FromReg: 1U, .ToReg: X86::RDX },
2892 { .FromReg: 2U, .ToReg: X86::RCX },
2893 { .FromReg: 3U, .ToReg: X86::RBX },
2894 { .FromReg: 4U, .ToReg: X86::RSI },
2895 { .FromReg: 5U, .ToReg: X86::RDI },
2896 { .FromReg: 6U, .ToReg: X86::RBP },
2897 { .FromReg: 7U, .ToReg: X86::RSP },
2898 { .FromReg: 8U, .ToReg: X86::R8 },
2899 { .FromReg: 9U, .ToReg: X86::R9 },
2900 { .FromReg: 10U, .ToReg: X86::R10 },
2901 { .FromReg: 11U, .ToReg: X86::R11 },
2902 { .FromReg: 12U, .ToReg: X86::R12 },
2903 { .FromReg: 13U, .ToReg: X86::R13 },
2904 { .FromReg: 14U, .ToReg: X86::R14 },
2905 { .FromReg: 15U, .ToReg: X86::R15 },
2906 { .FromReg: 16U, .ToReg: X86::RIP },
2907 { .FromReg: 17U, .ToReg: X86::XMM0 },
2908 { .FromReg: 18U, .ToReg: X86::XMM1 },
2909 { .FromReg: 19U, .ToReg: X86::XMM2 },
2910 { .FromReg: 20U, .ToReg: X86::XMM3 },
2911 { .FromReg: 21U, .ToReg: X86::XMM4 },
2912 { .FromReg: 22U, .ToReg: X86::XMM5 },
2913 { .FromReg: 23U, .ToReg: X86::XMM6 },
2914 { .FromReg: 24U, .ToReg: X86::XMM7 },
2915 { .FromReg: 25U, .ToReg: X86::XMM8 },
2916 { .FromReg: 26U, .ToReg: X86::XMM9 },
2917 { .FromReg: 27U, .ToReg: X86::XMM10 },
2918 { .FromReg: 28U, .ToReg: X86::XMM11 },
2919 { .FromReg: 29U, .ToReg: X86::XMM12 },
2920 { .FromReg: 30U, .ToReg: X86::XMM13 },
2921 { .FromReg: 31U, .ToReg: X86::XMM14 },
2922 { .FromReg: 32U, .ToReg: X86::XMM15 },
2923 { .FromReg: 33U, .ToReg: X86::ST0 },
2924 { .FromReg: 34U, .ToReg: X86::ST1 },
2925 { .FromReg: 35U, .ToReg: X86::ST2 },
2926 { .FromReg: 36U, .ToReg: X86::ST3 },
2927 { .FromReg: 37U, .ToReg: X86::ST4 },
2928 { .FromReg: 38U, .ToReg: X86::ST5 },
2929 { .FromReg: 39U, .ToReg: X86::ST6 },
2930 { .FromReg: 40U, .ToReg: X86::ST7 },
2931 { .FromReg: 41U, .ToReg: X86::MM0 },
2932 { .FromReg: 42U, .ToReg: X86::MM1 },
2933 { .FromReg: 43U, .ToReg: X86::MM2 },
2934 { .FromReg: 44U, .ToReg: X86::MM3 },
2935 { .FromReg: 45U, .ToReg: X86::MM4 },
2936 { .FromReg: 46U, .ToReg: X86::MM5 },
2937 { .FromReg: 47U, .ToReg: X86::MM6 },
2938 { .FromReg: 48U, .ToReg: X86::MM7 },
2939 { .FromReg: 49U, .ToReg: X86::RFLAGS },
2940 { .FromReg: 50U, .ToReg: X86::ES },
2941 { .FromReg: 51U, .ToReg: X86::CS },
2942 { .FromReg: 52U, .ToReg: X86::SS },
2943 { .FromReg: 53U, .ToReg: X86::DS },
2944 { .FromReg: 54U, .ToReg: X86::FS },
2945 { .FromReg: 55U, .ToReg: X86::GS },
2946 { .FromReg: 58U, .ToReg: X86::FS_BASE },
2947 { .FromReg: 59U, .ToReg: X86::GS_BASE },
2948 { .FromReg: 67U, .ToReg: X86::XMM16 },
2949 { .FromReg: 68U, .ToReg: X86::XMM17 },
2950 { .FromReg: 69U, .ToReg: X86::XMM18 },
2951 { .FromReg: 70U, .ToReg: X86::XMM19 },
2952 { .FromReg: 71U, .ToReg: X86::XMM20 },
2953 { .FromReg: 72U, .ToReg: X86::XMM21 },
2954 { .FromReg: 73U, .ToReg: X86::XMM22 },
2955 { .FromReg: 74U, .ToReg: X86::XMM23 },
2956 { .FromReg: 75U, .ToReg: X86::XMM24 },
2957 { .FromReg: 76U, .ToReg: X86::XMM25 },
2958 { .FromReg: 77U, .ToReg: X86::XMM26 },
2959 { .FromReg: 78U, .ToReg: X86::XMM27 },
2960 { .FromReg: 79U, .ToReg: X86::XMM28 },
2961 { .FromReg: 80U, .ToReg: X86::XMM29 },
2962 { .FromReg: 81U, .ToReg: X86::XMM30 },
2963 { .FromReg: 82U, .ToReg: X86::XMM31 },
2964 { .FromReg: 118U, .ToReg: X86::K0 },
2965 { .FromReg: 119U, .ToReg: X86::K1 },
2966 { .FromReg: 120U, .ToReg: X86::K2 },
2967 { .FromReg: 121U, .ToReg: X86::K3 },
2968 { .FromReg: 122U, .ToReg: X86::K4 },
2969 { .FromReg: 123U, .ToReg: X86::K5 },
2970 { .FromReg: 124U, .ToReg: X86::K6 },
2971 { .FromReg: 125U, .ToReg: X86::K7 },
2972 { .FromReg: 130U, .ToReg: X86::R16 },
2973 { .FromReg: 131U, .ToReg: X86::R17 },
2974 { .FromReg: 132U, .ToReg: X86::R18 },
2975 { .FromReg: 133U, .ToReg: X86::R19 },
2976 { .FromReg: 134U, .ToReg: X86::R20 },
2977 { .FromReg: 135U, .ToReg: X86::R21 },
2978 { .FromReg: 136U, .ToReg: X86::R22 },
2979 { .FromReg: 137U, .ToReg: X86::R23 },
2980 { .FromReg: 138U, .ToReg: X86::R24 },
2981 { .FromReg: 139U, .ToReg: X86::R25 },
2982 { .FromReg: 140U, .ToReg: X86::R26 },
2983 { .FromReg: 141U, .ToReg: X86::R27 },
2984 { .FromReg: 142U, .ToReg: X86::R28 },
2985 { .FromReg: 143U, .ToReg: X86::R29 },
2986 { .FromReg: 144U, .ToReg: X86::R30 },
2987 { .FromReg: 145U, .ToReg: X86::R31 },
2988};
2989extern const unsigned X86EHFlavour0Dwarf2LSize = std::size(X86EHFlavour0Dwarf2L);
2990
2991extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
2992 { .FromReg: 0U, .ToReg: X86::EAX },
2993 { .FromReg: 1U, .ToReg: X86::ECX },
2994 { .FromReg: 2U, .ToReg: X86::EDX },
2995 { .FromReg: 3U, .ToReg: X86::EBX },
2996 { .FromReg: 4U, .ToReg: X86::EBP },
2997 { .FromReg: 5U, .ToReg: X86::ESP },
2998 { .FromReg: 6U, .ToReg: X86::ESI },
2999 { .FromReg: 7U, .ToReg: X86::EDI },
3000 { .FromReg: 8U, .ToReg: X86::EIP },
3001 { .FromReg: 9U, .ToReg: X86::EFLAGS },
3002 { .FromReg: 12U, .ToReg: X86::ST0 },
3003 { .FromReg: 13U, .ToReg: X86::ST1 },
3004 { .FromReg: 14U, .ToReg: X86::ST2 },
3005 { .FromReg: 15U, .ToReg: X86::ST3 },
3006 { .FromReg: 16U, .ToReg: X86::ST4 },
3007 { .FromReg: 17U, .ToReg: X86::ST5 },
3008 { .FromReg: 18U, .ToReg: X86::ST6 },
3009 { .FromReg: 19U, .ToReg: X86::ST7 },
3010 { .FromReg: 21U, .ToReg: X86::XMM0 },
3011 { .FromReg: 22U, .ToReg: X86::XMM1 },
3012 { .FromReg: 23U, .ToReg: X86::XMM2 },
3013 { .FromReg: 24U, .ToReg: X86::XMM3 },
3014 { .FromReg: 25U, .ToReg: X86::XMM4 },
3015 { .FromReg: 26U, .ToReg: X86::XMM5 },
3016 { .FromReg: 27U, .ToReg: X86::XMM6 },
3017 { .FromReg: 28U, .ToReg: X86::XMM7 },
3018 { .FromReg: 29U, .ToReg: X86::MM0 },
3019 { .FromReg: 30U, .ToReg: X86::MM1 },
3020 { .FromReg: 31U, .ToReg: X86::MM2 },
3021 { .FromReg: 32U, .ToReg: X86::MM3 },
3022 { .FromReg: 33U, .ToReg: X86::MM4 },
3023 { .FromReg: 34U, .ToReg: X86::MM5 },
3024 { .FromReg: 35U, .ToReg: X86::MM6 },
3025 { .FromReg: 36U, .ToReg: X86::MM7 },
3026 { .FromReg: 93U, .ToReg: X86::K0 },
3027 { .FromReg: 94U, .ToReg: X86::K1 },
3028 { .FromReg: 95U, .ToReg: X86::K2 },
3029 { .FromReg: 96U, .ToReg: X86::K3 },
3030 { .FromReg: 97U, .ToReg: X86::K4 },
3031 { .FromReg: 98U, .ToReg: X86::K5 },
3032 { .FromReg: 99U, .ToReg: X86::K6 },
3033 { .FromReg: 100U, .ToReg: X86::K7 },
3034};
3035extern const unsigned X86EHFlavour1Dwarf2LSize = std::size(X86EHFlavour1Dwarf2L);
3036
3037extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
3038 { .FromReg: 0U, .ToReg: X86::EAX },
3039 { .FromReg: 1U, .ToReg: X86::ECX },
3040 { .FromReg: 2U, .ToReg: X86::EDX },
3041 { .FromReg: 3U, .ToReg: X86::EBX },
3042 { .FromReg: 4U, .ToReg: X86::ESP },
3043 { .FromReg: 5U, .ToReg: X86::EBP },
3044 { .FromReg: 6U, .ToReg: X86::ESI },
3045 { .FromReg: 7U, .ToReg: X86::EDI },
3046 { .FromReg: 8U, .ToReg: X86::EIP },
3047 { .FromReg: 9U, .ToReg: X86::EFLAGS },
3048 { .FromReg: 11U, .ToReg: X86::ST0 },
3049 { .FromReg: 12U, .ToReg: X86::ST1 },
3050 { .FromReg: 13U, .ToReg: X86::ST2 },
3051 { .FromReg: 14U, .ToReg: X86::ST3 },
3052 { .FromReg: 15U, .ToReg: X86::ST4 },
3053 { .FromReg: 16U, .ToReg: X86::ST5 },
3054 { .FromReg: 17U, .ToReg: X86::ST6 },
3055 { .FromReg: 18U, .ToReg: X86::ST7 },
3056 { .FromReg: 21U, .ToReg: X86::XMM0 },
3057 { .FromReg: 22U, .ToReg: X86::XMM1 },
3058 { .FromReg: 23U, .ToReg: X86::XMM2 },
3059 { .FromReg: 24U, .ToReg: X86::XMM3 },
3060 { .FromReg: 25U, .ToReg: X86::XMM4 },
3061 { .FromReg: 26U, .ToReg: X86::XMM5 },
3062 { .FromReg: 27U, .ToReg: X86::XMM6 },
3063 { .FromReg: 28U, .ToReg: X86::XMM7 },
3064 { .FromReg: 29U, .ToReg: X86::MM0 },
3065 { .FromReg: 30U, .ToReg: X86::MM1 },
3066 { .FromReg: 31U, .ToReg: X86::MM2 },
3067 { .FromReg: 32U, .ToReg: X86::MM3 },
3068 { .FromReg: 33U, .ToReg: X86::MM4 },
3069 { .FromReg: 34U, .ToReg: X86::MM5 },
3070 { .FromReg: 35U, .ToReg: X86::MM6 },
3071 { .FromReg: 36U, .ToReg: X86::MM7 },
3072 { .FromReg: 40U, .ToReg: X86::ES },
3073 { .FromReg: 41U, .ToReg: X86::CS },
3074 { .FromReg: 42U, .ToReg: X86::SS },
3075 { .FromReg: 43U, .ToReg: X86::DS },
3076 { .FromReg: 44U, .ToReg: X86::FS },
3077 { .FromReg: 45U, .ToReg: X86::GS },
3078 { .FromReg: 93U, .ToReg: X86::K0 },
3079 { .FromReg: 94U, .ToReg: X86::K1 },
3080 { .FromReg: 95U, .ToReg: X86::K2 },
3081 { .FromReg: 96U, .ToReg: X86::K3 },
3082 { .FromReg: 97U, .ToReg: X86::K4 },
3083 { .FromReg: 98U, .ToReg: X86::K5 },
3084 { .FromReg: 99U, .ToReg: X86::K6 },
3085 { .FromReg: 100U, .ToReg: X86::K7 },
3086};
3087extern const unsigned X86EHFlavour2Dwarf2LSize = std::size(X86EHFlavour2Dwarf2L);
3088
3089extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
3090 { .FromReg: X86::CS, .ToReg: 51U },
3091 { .FromReg: X86::DS, .ToReg: 53U },
3092 { .FromReg: X86::EAX, .ToReg: -2U },
3093 { .FromReg: X86::EBP, .ToReg: -2U },
3094 { .FromReg: X86::EBX, .ToReg: -2U },
3095 { .FromReg: X86::ECX, .ToReg: -2U },
3096 { .FromReg: X86::EDI, .ToReg: -2U },
3097 { .FromReg: X86::EDX, .ToReg: -2U },
3098 { .FromReg: X86::EFLAGS, .ToReg: 49U },
3099 { .FromReg: X86::EIP, .ToReg: -2U },
3100 { .FromReg: X86::ES, .ToReg: 50U },
3101 { .FromReg: X86::ESI, .ToReg: -2U },
3102 { .FromReg: X86::ESP, .ToReg: -2U },
3103 { .FromReg: X86::FS, .ToReg: 54U },
3104 { .FromReg: X86::FS_BASE, .ToReg: 58U },
3105 { .FromReg: X86::GS, .ToReg: 55U },
3106 { .FromReg: X86::GS_BASE, .ToReg: 59U },
3107 { .FromReg: X86::RAX, .ToReg: 0U },
3108 { .FromReg: X86::RBP, .ToReg: 6U },
3109 { .FromReg: X86::RBX, .ToReg: 3U },
3110 { .FromReg: X86::RCX, .ToReg: 2U },
3111 { .FromReg: X86::RDI, .ToReg: 5U },
3112 { .FromReg: X86::RDX, .ToReg: 1U },
3113 { .FromReg: X86::RFLAGS, .ToReg: 49U },
3114 { .FromReg: X86::RIP, .ToReg: 16U },
3115 { .FromReg: X86::RSI, .ToReg: 4U },
3116 { .FromReg: X86::RSP, .ToReg: 7U },
3117 { .FromReg: X86::SS, .ToReg: 52U },
3118 { .FromReg: X86::_EFLAGS, .ToReg: 49U },
3119 { .FromReg: X86::MM0, .ToReg: 41U },
3120 { .FromReg: X86::MM1, .ToReg: 42U },
3121 { .FromReg: X86::MM2, .ToReg: 43U },
3122 { .FromReg: X86::MM3, .ToReg: 44U },
3123 { .FromReg: X86::MM4, .ToReg: 45U },
3124 { .FromReg: X86::MM5, .ToReg: 46U },
3125 { .FromReg: X86::MM6, .ToReg: 47U },
3126 { .FromReg: X86::MM7, .ToReg: 48U },
3127 { .FromReg: X86::R8, .ToReg: 8U },
3128 { .FromReg: X86::R9, .ToReg: 9U },
3129 { .FromReg: X86::R10, .ToReg: 10U },
3130 { .FromReg: X86::R11, .ToReg: 11U },
3131 { .FromReg: X86::R12, .ToReg: 12U },
3132 { .FromReg: X86::R13, .ToReg: 13U },
3133 { .FromReg: X86::R14, .ToReg: 14U },
3134 { .FromReg: X86::R15, .ToReg: 15U },
3135 { .FromReg: X86::ST0, .ToReg: 33U },
3136 { .FromReg: X86::ST1, .ToReg: 34U },
3137 { .FromReg: X86::ST2, .ToReg: 35U },
3138 { .FromReg: X86::ST3, .ToReg: 36U },
3139 { .FromReg: X86::ST4, .ToReg: 37U },
3140 { .FromReg: X86::ST5, .ToReg: 38U },
3141 { .FromReg: X86::ST6, .ToReg: 39U },
3142 { .FromReg: X86::ST7, .ToReg: 40U },
3143 { .FromReg: X86::XMM0, .ToReg: 17U },
3144 { .FromReg: X86::XMM1, .ToReg: 18U },
3145 { .FromReg: X86::XMM2, .ToReg: 19U },
3146 { .FromReg: X86::XMM3, .ToReg: 20U },
3147 { .FromReg: X86::XMM4, .ToReg: 21U },
3148 { .FromReg: X86::XMM5, .ToReg: 22U },
3149 { .FromReg: X86::XMM6, .ToReg: 23U },
3150 { .FromReg: X86::XMM7, .ToReg: 24U },
3151 { .FromReg: X86::XMM8, .ToReg: 25U },
3152 { .FromReg: X86::XMM9, .ToReg: 26U },
3153 { .FromReg: X86::XMM10, .ToReg: 27U },
3154 { .FromReg: X86::XMM11, .ToReg: 28U },
3155 { .FromReg: X86::XMM12, .ToReg: 29U },
3156 { .FromReg: X86::XMM13, .ToReg: 30U },
3157 { .FromReg: X86::XMM14, .ToReg: 31U },
3158 { .FromReg: X86::XMM15, .ToReg: 32U },
3159 { .FromReg: X86::YMM0, .ToReg: 17U },
3160 { .FromReg: X86::YMM1, .ToReg: 18U },
3161 { .FromReg: X86::YMM2, .ToReg: 19U },
3162 { .FromReg: X86::YMM3, .ToReg: 20U },
3163 { .FromReg: X86::YMM4, .ToReg: 21U },
3164 { .FromReg: X86::YMM5, .ToReg: 22U },
3165 { .FromReg: X86::YMM6, .ToReg: 23U },
3166 { .FromReg: X86::YMM7, .ToReg: 24U },
3167 { .FromReg: X86::YMM8, .ToReg: 25U },
3168 { .FromReg: X86::YMM9, .ToReg: 26U },
3169 { .FromReg: X86::YMM10, .ToReg: 27U },
3170 { .FromReg: X86::YMM11, .ToReg: 28U },
3171 { .FromReg: X86::YMM12, .ToReg: 29U },
3172 { .FromReg: X86::YMM13, .ToReg: 30U },
3173 { .FromReg: X86::YMM14, .ToReg: 31U },
3174 { .FromReg: X86::YMM15, .ToReg: 32U },
3175 { .FromReg: X86::K0, .ToReg: 118U },
3176 { .FromReg: X86::K1, .ToReg: 119U },
3177 { .FromReg: X86::K2, .ToReg: 120U },
3178 { .FromReg: X86::K3, .ToReg: 121U },
3179 { .FromReg: X86::K4, .ToReg: 122U },
3180 { .FromReg: X86::K5, .ToReg: 123U },
3181 { .FromReg: X86::K6, .ToReg: 124U },
3182 { .FromReg: X86::K7, .ToReg: 125U },
3183 { .FromReg: X86::XMM16, .ToReg: 67U },
3184 { .FromReg: X86::XMM17, .ToReg: 68U },
3185 { .FromReg: X86::XMM18, .ToReg: 69U },
3186 { .FromReg: X86::XMM19, .ToReg: 70U },
3187 { .FromReg: X86::XMM20, .ToReg: 71U },
3188 { .FromReg: X86::XMM21, .ToReg: 72U },
3189 { .FromReg: X86::XMM22, .ToReg: 73U },
3190 { .FromReg: X86::XMM23, .ToReg: 74U },
3191 { .FromReg: X86::XMM24, .ToReg: 75U },
3192 { .FromReg: X86::XMM25, .ToReg: 76U },
3193 { .FromReg: X86::XMM26, .ToReg: 77U },
3194 { .FromReg: X86::XMM27, .ToReg: 78U },
3195 { .FromReg: X86::XMM28, .ToReg: 79U },
3196 { .FromReg: X86::XMM29, .ToReg: 80U },
3197 { .FromReg: X86::XMM30, .ToReg: 81U },
3198 { .FromReg: X86::XMM31, .ToReg: 82U },
3199 { .FromReg: X86::YMM16, .ToReg: 67U },
3200 { .FromReg: X86::YMM17, .ToReg: 68U },
3201 { .FromReg: X86::YMM18, .ToReg: 69U },
3202 { .FromReg: X86::YMM19, .ToReg: 70U },
3203 { .FromReg: X86::YMM20, .ToReg: 71U },
3204 { .FromReg: X86::YMM21, .ToReg: 72U },
3205 { .FromReg: X86::YMM22, .ToReg: 73U },
3206 { .FromReg: X86::YMM23, .ToReg: 74U },
3207 { .FromReg: X86::YMM24, .ToReg: 75U },
3208 { .FromReg: X86::YMM25, .ToReg: 76U },
3209 { .FromReg: X86::YMM26, .ToReg: 77U },
3210 { .FromReg: X86::YMM27, .ToReg: 78U },
3211 { .FromReg: X86::YMM28, .ToReg: 79U },
3212 { .FromReg: X86::YMM29, .ToReg: 80U },
3213 { .FromReg: X86::YMM30, .ToReg: 81U },
3214 { .FromReg: X86::YMM31, .ToReg: 82U },
3215 { .FromReg: X86::ZMM0, .ToReg: 17U },
3216 { .FromReg: X86::ZMM1, .ToReg: 18U },
3217 { .FromReg: X86::ZMM2, .ToReg: 19U },
3218 { .FromReg: X86::ZMM3, .ToReg: 20U },
3219 { .FromReg: X86::ZMM4, .ToReg: 21U },
3220 { .FromReg: X86::ZMM5, .ToReg: 22U },
3221 { .FromReg: X86::ZMM6, .ToReg: 23U },
3222 { .FromReg: X86::ZMM7, .ToReg: 24U },
3223 { .FromReg: X86::ZMM8, .ToReg: 25U },
3224 { .FromReg: X86::ZMM9, .ToReg: 26U },
3225 { .FromReg: X86::ZMM10, .ToReg: 27U },
3226 { .FromReg: X86::ZMM11, .ToReg: 28U },
3227 { .FromReg: X86::ZMM12, .ToReg: 29U },
3228 { .FromReg: X86::ZMM13, .ToReg: 30U },
3229 { .FromReg: X86::ZMM14, .ToReg: 31U },
3230 { .FromReg: X86::ZMM15, .ToReg: 32U },
3231 { .FromReg: X86::ZMM16, .ToReg: 67U },
3232 { .FromReg: X86::ZMM17, .ToReg: 68U },
3233 { .FromReg: X86::ZMM18, .ToReg: 69U },
3234 { .FromReg: X86::ZMM19, .ToReg: 70U },
3235 { .FromReg: X86::ZMM20, .ToReg: 71U },
3236 { .FromReg: X86::ZMM21, .ToReg: 72U },
3237 { .FromReg: X86::ZMM22, .ToReg: 73U },
3238 { .FromReg: X86::ZMM23, .ToReg: 74U },
3239 { .FromReg: X86::ZMM24, .ToReg: 75U },
3240 { .FromReg: X86::ZMM25, .ToReg: 76U },
3241 { .FromReg: X86::ZMM26, .ToReg: 77U },
3242 { .FromReg: X86::ZMM27, .ToReg: 78U },
3243 { .FromReg: X86::ZMM28, .ToReg: 79U },
3244 { .FromReg: X86::ZMM29, .ToReg: 80U },
3245 { .FromReg: X86::ZMM30, .ToReg: 81U },
3246 { .FromReg: X86::ZMM31, .ToReg: 82U },
3247 { .FromReg: X86::R16, .ToReg: 130U },
3248 { .FromReg: X86::R17, .ToReg: 131U },
3249 { .FromReg: X86::R18, .ToReg: 132U },
3250 { .FromReg: X86::R19, .ToReg: 133U },
3251 { .FromReg: X86::R20, .ToReg: 134U },
3252 { .FromReg: X86::R21, .ToReg: 135U },
3253 { .FromReg: X86::R22, .ToReg: 136U },
3254 { .FromReg: X86::R23, .ToReg: 137U },
3255 { .FromReg: X86::R24, .ToReg: 138U },
3256 { .FromReg: X86::R25, .ToReg: 139U },
3257 { .FromReg: X86::R26, .ToReg: 140U },
3258 { .FromReg: X86::R27, .ToReg: 141U },
3259 { .FromReg: X86::R28, .ToReg: 142U },
3260 { .FromReg: X86::R29, .ToReg: 143U },
3261 { .FromReg: X86::R30, .ToReg: 144U },
3262 { .FromReg: X86::R31, .ToReg: 145U },
3263};
3264extern const unsigned X86DwarfFlavour0L2DwarfSize = std::size(X86DwarfFlavour0L2Dwarf);
3265
3266extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
3267 { .FromReg: X86::CS, .ToReg: -2U },
3268 { .FromReg: X86::DS, .ToReg: -2U },
3269 { .FromReg: X86::EAX, .ToReg: 0U },
3270 { .FromReg: X86::EBP, .ToReg: 4U },
3271 { .FromReg: X86::EBX, .ToReg: 3U },
3272 { .FromReg: X86::ECX, .ToReg: 1U },
3273 { .FromReg: X86::EDI, .ToReg: 7U },
3274 { .FromReg: X86::EDX, .ToReg: 2U },
3275 { .FromReg: X86::EFLAGS, .ToReg: 9U },
3276 { .FromReg: X86::EIP, .ToReg: 8U },
3277 { .FromReg: X86::ES, .ToReg: -2U },
3278 { .FromReg: X86::ESI, .ToReg: 6U },
3279 { .FromReg: X86::ESP, .ToReg: 5U },
3280 { .FromReg: X86::FS, .ToReg: -2U },
3281 { .FromReg: X86::FS_BASE, .ToReg: -2U },
3282 { .FromReg: X86::GS, .ToReg: -2U },
3283 { .FromReg: X86::GS_BASE, .ToReg: -2U },
3284 { .FromReg: X86::RAX, .ToReg: -2U },
3285 { .FromReg: X86::RBP, .ToReg: -2U },
3286 { .FromReg: X86::RBX, .ToReg: -2U },
3287 { .FromReg: X86::RCX, .ToReg: -2U },
3288 { .FromReg: X86::RDI, .ToReg: -2U },
3289 { .FromReg: X86::RDX, .ToReg: -2U },
3290 { .FromReg: X86::RFLAGS, .ToReg: -2U },
3291 { .FromReg: X86::RIP, .ToReg: -2U },
3292 { .FromReg: X86::RSI, .ToReg: -2U },
3293 { .FromReg: X86::RSP, .ToReg: -2U },
3294 { .FromReg: X86::SS, .ToReg: -2U },
3295 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
3296 { .FromReg: X86::MM0, .ToReg: 29U },
3297 { .FromReg: X86::MM1, .ToReg: 30U },
3298 { .FromReg: X86::MM2, .ToReg: 31U },
3299 { .FromReg: X86::MM3, .ToReg: 32U },
3300 { .FromReg: X86::MM4, .ToReg: 33U },
3301 { .FromReg: X86::MM5, .ToReg: 34U },
3302 { .FromReg: X86::MM6, .ToReg: 35U },
3303 { .FromReg: X86::MM7, .ToReg: 36U },
3304 { .FromReg: X86::R8, .ToReg: -2U },
3305 { .FromReg: X86::R9, .ToReg: -2U },
3306 { .FromReg: X86::R10, .ToReg: -2U },
3307 { .FromReg: X86::R11, .ToReg: -2U },
3308 { .FromReg: X86::R12, .ToReg: -2U },
3309 { .FromReg: X86::R13, .ToReg: -2U },
3310 { .FromReg: X86::R14, .ToReg: -2U },
3311 { .FromReg: X86::R15, .ToReg: -2U },
3312 { .FromReg: X86::ST0, .ToReg: 12U },
3313 { .FromReg: X86::ST1, .ToReg: 13U },
3314 { .FromReg: X86::ST2, .ToReg: 14U },
3315 { .FromReg: X86::ST3, .ToReg: 15U },
3316 { .FromReg: X86::ST4, .ToReg: 16U },
3317 { .FromReg: X86::ST5, .ToReg: 17U },
3318 { .FromReg: X86::ST6, .ToReg: 18U },
3319 { .FromReg: X86::ST7, .ToReg: 19U },
3320 { .FromReg: X86::XMM0, .ToReg: 21U },
3321 { .FromReg: X86::XMM1, .ToReg: 22U },
3322 { .FromReg: X86::XMM2, .ToReg: 23U },
3323 { .FromReg: X86::XMM3, .ToReg: 24U },
3324 { .FromReg: X86::XMM4, .ToReg: 25U },
3325 { .FromReg: X86::XMM5, .ToReg: 26U },
3326 { .FromReg: X86::XMM6, .ToReg: 27U },
3327 { .FromReg: X86::XMM7, .ToReg: 28U },
3328 { .FromReg: X86::XMM8, .ToReg: -2U },
3329 { .FromReg: X86::XMM9, .ToReg: -2U },
3330 { .FromReg: X86::XMM10, .ToReg: -2U },
3331 { .FromReg: X86::XMM11, .ToReg: -2U },
3332 { .FromReg: X86::XMM12, .ToReg: -2U },
3333 { .FromReg: X86::XMM13, .ToReg: -2U },
3334 { .FromReg: X86::XMM14, .ToReg: -2U },
3335 { .FromReg: X86::XMM15, .ToReg: -2U },
3336 { .FromReg: X86::YMM0, .ToReg: 21U },
3337 { .FromReg: X86::YMM1, .ToReg: 22U },
3338 { .FromReg: X86::YMM2, .ToReg: 23U },
3339 { .FromReg: X86::YMM3, .ToReg: 24U },
3340 { .FromReg: X86::YMM4, .ToReg: 25U },
3341 { .FromReg: X86::YMM5, .ToReg: 26U },
3342 { .FromReg: X86::YMM6, .ToReg: 27U },
3343 { .FromReg: X86::YMM7, .ToReg: 28U },
3344 { .FromReg: X86::YMM8, .ToReg: -2U },
3345 { .FromReg: X86::YMM9, .ToReg: -2U },
3346 { .FromReg: X86::YMM10, .ToReg: -2U },
3347 { .FromReg: X86::YMM11, .ToReg: -2U },
3348 { .FromReg: X86::YMM12, .ToReg: -2U },
3349 { .FromReg: X86::YMM13, .ToReg: -2U },
3350 { .FromReg: X86::YMM14, .ToReg: -2U },
3351 { .FromReg: X86::YMM15, .ToReg: -2U },
3352 { .FromReg: X86::K0, .ToReg: 93U },
3353 { .FromReg: X86::K1, .ToReg: 94U },
3354 { .FromReg: X86::K2, .ToReg: 95U },
3355 { .FromReg: X86::K3, .ToReg: 96U },
3356 { .FromReg: X86::K4, .ToReg: 97U },
3357 { .FromReg: X86::K5, .ToReg: 98U },
3358 { .FromReg: X86::K6, .ToReg: 99U },
3359 { .FromReg: X86::K7, .ToReg: 100U },
3360 { .FromReg: X86::XMM16, .ToReg: -2U },
3361 { .FromReg: X86::XMM17, .ToReg: -2U },
3362 { .FromReg: X86::XMM18, .ToReg: -2U },
3363 { .FromReg: X86::XMM19, .ToReg: -2U },
3364 { .FromReg: X86::XMM20, .ToReg: -2U },
3365 { .FromReg: X86::XMM21, .ToReg: -2U },
3366 { .FromReg: X86::XMM22, .ToReg: -2U },
3367 { .FromReg: X86::XMM23, .ToReg: -2U },
3368 { .FromReg: X86::XMM24, .ToReg: -2U },
3369 { .FromReg: X86::XMM25, .ToReg: -2U },
3370 { .FromReg: X86::XMM26, .ToReg: -2U },
3371 { .FromReg: X86::XMM27, .ToReg: -2U },
3372 { .FromReg: X86::XMM28, .ToReg: -2U },
3373 { .FromReg: X86::XMM29, .ToReg: -2U },
3374 { .FromReg: X86::XMM30, .ToReg: -2U },
3375 { .FromReg: X86::XMM31, .ToReg: -2U },
3376 { .FromReg: X86::YMM16, .ToReg: -2U },
3377 { .FromReg: X86::YMM17, .ToReg: -2U },
3378 { .FromReg: X86::YMM18, .ToReg: -2U },
3379 { .FromReg: X86::YMM19, .ToReg: -2U },
3380 { .FromReg: X86::YMM20, .ToReg: -2U },
3381 { .FromReg: X86::YMM21, .ToReg: -2U },
3382 { .FromReg: X86::YMM22, .ToReg: -2U },
3383 { .FromReg: X86::YMM23, .ToReg: -2U },
3384 { .FromReg: X86::YMM24, .ToReg: -2U },
3385 { .FromReg: X86::YMM25, .ToReg: -2U },
3386 { .FromReg: X86::YMM26, .ToReg: -2U },
3387 { .FromReg: X86::YMM27, .ToReg: -2U },
3388 { .FromReg: X86::YMM28, .ToReg: -2U },
3389 { .FromReg: X86::YMM29, .ToReg: -2U },
3390 { .FromReg: X86::YMM30, .ToReg: -2U },
3391 { .FromReg: X86::YMM31, .ToReg: -2U },
3392 { .FromReg: X86::ZMM0, .ToReg: 21U },
3393 { .FromReg: X86::ZMM1, .ToReg: 22U },
3394 { .FromReg: X86::ZMM2, .ToReg: 23U },
3395 { .FromReg: X86::ZMM3, .ToReg: 24U },
3396 { .FromReg: X86::ZMM4, .ToReg: 25U },
3397 { .FromReg: X86::ZMM5, .ToReg: 26U },
3398 { .FromReg: X86::ZMM6, .ToReg: 27U },
3399 { .FromReg: X86::ZMM7, .ToReg: 28U },
3400 { .FromReg: X86::ZMM8, .ToReg: -2U },
3401 { .FromReg: X86::ZMM9, .ToReg: -2U },
3402 { .FromReg: X86::ZMM10, .ToReg: -2U },
3403 { .FromReg: X86::ZMM11, .ToReg: -2U },
3404 { .FromReg: X86::ZMM12, .ToReg: -2U },
3405 { .FromReg: X86::ZMM13, .ToReg: -2U },
3406 { .FromReg: X86::ZMM14, .ToReg: -2U },
3407 { .FromReg: X86::ZMM15, .ToReg: -2U },
3408 { .FromReg: X86::ZMM16, .ToReg: -2U },
3409 { .FromReg: X86::ZMM17, .ToReg: -2U },
3410 { .FromReg: X86::ZMM18, .ToReg: -2U },
3411 { .FromReg: X86::ZMM19, .ToReg: -2U },
3412 { .FromReg: X86::ZMM20, .ToReg: -2U },
3413 { .FromReg: X86::ZMM21, .ToReg: -2U },
3414 { .FromReg: X86::ZMM22, .ToReg: -2U },
3415 { .FromReg: X86::ZMM23, .ToReg: -2U },
3416 { .FromReg: X86::ZMM24, .ToReg: -2U },
3417 { .FromReg: X86::ZMM25, .ToReg: -2U },
3418 { .FromReg: X86::ZMM26, .ToReg: -2U },
3419 { .FromReg: X86::ZMM27, .ToReg: -2U },
3420 { .FromReg: X86::ZMM28, .ToReg: -2U },
3421 { .FromReg: X86::ZMM29, .ToReg: -2U },
3422 { .FromReg: X86::ZMM30, .ToReg: -2U },
3423 { .FromReg: X86::ZMM31, .ToReg: -2U },
3424 { .FromReg: X86::R16, .ToReg: -2U },
3425 { .FromReg: X86::R17, .ToReg: -2U },
3426 { .FromReg: X86::R18, .ToReg: -2U },
3427 { .FromReg: X86::R19, .ToReg: -2U },
3428 { .FromReg: X86::R20, .ToReg: -2U },
3429 { .FromReg: X86::R21, .ToReg: -2U },
3430 { .FromReg: X86::R22, .ToReg: -2U },
3431 { .FromReg: X86::R23, .ToReg: -2U },
3432 { .FromReg: X86::R24, .ToReg: -2U },
3433 { .FromReg: X86::R25, .ToReg: -2U },
3434 { .FromReg: X86::R26, .ToReg: -2U },
3435 { .FromReg: X86::R27, .ToReg: -2U },
3436 { .FromReg: X86::R28, .ToReg: -2U },
3437 { .FromReg: X86::R29, .ToReg: -2U },
3438 { .FromReg: X86::R30, .ToReg: -2U },
3439 { .FromReg: X86::R31, .ToReg: -2U },
3440};
3441extern const unsigned X86DwarfFlavour1L2DwarfSize = std::size(X86DwarfFlavour1L2Dwarf);
3442
3443extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
3444 { .FromReg: X86::CS, .ToReg: 41U },
3445 { .FromReg: X86::DS, .ToReg: 43U },
3446 { .FromReg: X86::EAX, .ToReg: 0U },
3447 { .FromReg: X86::EBP, .ToReg: 5U },
3448 { .FromReg: X86::EBX, .ToReg: 3U },
3449 { .FromReg: X86::ECX, .ToReg: 1U },
3450 { .FromReg: X86::EDI, .ToReg: 7U },
3451 { .FromReg: X86::EDX, .ToReg: 2U },
3452 { .FromReg: X86::EFLAGS, .ToReg: 9U },
3453 { .FromReg: X86::EIP, .ToReg: 8U },
3454 { .FromReg: X86::ES, .ToReg: 40U },
3455 { .FromReg: X86::ESI, .ToReg: 6U },
3456 { .FromReg: X86::ESP, .ToReg: 4U },
3457 { .FromReg: X86::FS, .ToReg: 44U },
3458 { .FromReg: X86::FS_BASE, .ToReg: -2U },
3459 { .FromReg: X86::GS, .ToReg: 45U },
3460 { .FromReg: X86::GS_BASE, .ToReg: -2U },
3461 { .FromReg: X86::RAX, .ToReg: -2U },
3462 { .FromReg: X86::RBP, .ToReg: -2U },
3463 { .FromReg: X86::RBX, .ToReg: -2U },
3464 { .FromReg: X86::RCX, .ToReg: -2U },
3465 { .FromReg: X86::RDI, .ToReg: -2U },
3466 { .FromReg: X86::RDX, .ToReg: -2U },
3467 { .FromReg: X86::RFLAGS, .ToReg: -2U },
3468 { .FromReg: X86::RIP, .ToReg: -2U },
3469 { .FromReg: X86::RSI, .ToReg: -2U },
3470 { .FromReg: X86::RSP, .ToReg: -2U },
3471 { .FromReg: X86::SS, .ToReg: 42U },
3472 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
3473 { .FromReg: X86::MM0, .ToReg: 29U },
3474 { .FromReg: X86::MM1, .ToReg: 30U },
3475 { .FromReg: X86::MM2, .ToReg: 31U },
3476 { .FromReg: X86::MM3, .ToReg: 32U },
3477 { .FromReg: X86::MM4, .ToReg: 33U },
3478 { .FromReg: X86::MM5, .ToReg: 34U },
3479 { .FromReg: X86::MM6, .ToReg: 35U },
3480 { .FromReg: X86::MM7, .ToReg: 36U },
3481 { .FromReg: X86::R8, .ToReg: -2U },
3482 { .FromReg: X86::R9, .ToReg: -2U },
3483 { .FromReg: X86::R10, .ToReg: -2U },
3484 { .FromReg: X86::R11, .ToReg: -2U },
3485 { .FromReg: X86::R12, .ToReg: -2U },
3486 { .FromReg: X86::R13, .ToReg: -2U },
3487 { .FromReg: X86::R14, .ToReg: -2U },
3488 { .FromReg: X86::R15, .ToReg: -2U },
3489 { .FromReg: X86::ST0, .ToReg: 11U },
3490 { .FromReg: X86::ST1, .ToReg: 12U },
3491 { .FromReg: X86::ST2, .ToReg: 13U },
3492 { .FromReg: X86::ST3, .ToReg: 14U },
3493 { .FromReg: X86::ST4, .ToReg: 15U },
3494 { .FromReg: X86::ST5, .ToReg: 16U },
3495 { .FromReg: X86::ST6, .ToReg: 17U },
3496 { .FromReg: X86::ST7, .ToReg: 18U },
3497 { .FromReg: X86::XMM0, .ToReg: 21U },
3498 { .FromReg: X86::XMM1, .ToReg: 22U },
3499 { .FromReg: X86::XMM2, .ToReg: 23U },
3500 { .FromReg: X86::XMM3, .ToReg: 24U },
3501 { .FromReg: X86::XMM4, .ToReg: 25U },
3502 { .FromReg: X86::XMM5, .ToReg: 26U },
3503 { .FromReg: X86::XMM6, .ToReg: 27U },
3504 { .FromReg: X86::XMM7, .ToReg: 28U },
3505 { .FromReg: X86::XMM8, .ToReg: -2U },
3506 { .FromReg: X86::XMM9, .ToReg: -2U },
3507 { .FromReg: X86::XMM10, .ToReg: -2U },
3508 { .FromReg: X86::XMM11, .ToReg: -2U },
3509 { .FromReg: X86::XMM12, .ToReg: -2U },
3510 { .FromReg: X86::XMM13, .ToReg: -2U },
3511 { .FromReg: X86::XMM14, .ToReg: -2U },
3512 { .FromReg: X86::XMM15, .ToReg: -2U },
3513 { .FromReg: X86::YMM0, .ToReg: 21U },
3514 { .FromReg: X86::YMM1, .ToReg: 22U },
3515 { .FromReg: X86::YMM2, .ToReg: 23U },
3516 { .FromReg: X86::YMM3, .ToReg: 24U },
3517 { .FromReg: X86::YMM4, .ToReg: 25U },
3518 { .FromReg: X86::YMM5, .ToReg: 26U },
3519 { .FromReg: X86::YMM6, .ToReg: 27U },
3520 { .FromReg: X86::YMM7, .ToReg: 28U },
3521 { .FromReg: X86::YMM8, .ToReg: -2U },
3522 { .FromReg: X86::YMM9, .ToReg: -2U },
3523 { .FromReg: X86::YMM10, .ToReg: -2U },
3524 { .FromReg: X86::YMM11, .ToReg: -2U },
3525 { .FromReg: X86::YMM12, .ToReg: -2U },
3526 { .FromReg: X86::YMM13, .ToReg: -2U },
3527 { .FromReg: X86::YMM14, .ToReg: -2U },
3528 { .FromReg: X86::YMM15, .ToReg: -2U },
3529 { .FromReg: X86::K0, .ToReg: 93U },
3530 { .FromReg: X86::K1, .ToReg: 94U },
3531 { .FromReg: X86::K2, .ToReg: 95U },
3532 { .FromReg: X86::K3, .ToReg: 96U },
3533 { .FromReg: X86::K4, .ToReg: 97U },
3534 { .FromReg: X86::K5, .ToReg: 98U },
3535 { .FromReg: X86::K6, .ToReg: 99U },
3536 { .FromReg: X86::K7, .ToReg: 100U },
3537 { .FromReg: X86::XMM16, .ToReg: -2U },
3538 { .FromReg: X86::XMM17, .ToReg: -2U },
3539 { .FromReg: X86::XMM18, .ToReg: -2U },
3540 { .FromReg: X86::XMM19, .ToReg: -2U },
3541 { .FromReg: X86::XMM20, .ToReg: -2U },
3542 { .FromReg: X86::XMM21, .ToReg: -2U },
3543 { .FromReg: X86::XMM22, .ToReg: -2U },
3544 { .FromReg: X86::XMM23, .ToReg: -2U },
3545 { .FromReg: X86::XMM24, .ToReg: -2U },
3546 { .FromReg: X86::XMM25, .ToReg: -2U },
3547 { .FromReg: X86::XMM26, .ToReg: -2U },
3548 { .FromReg: X86::XMM27, .ToReg: -2U },
3549 { .FromReg: X86::XMM28, .ToReg: -2U },
3550 { .FromReg: X86::XMM29, .ToReg: -2U },
3551 { .FromReg: X86::XMM30, .ToReg: -2U },
3552 { .FromReg: X86::XMM31, .ToReg: -2U },
3553 { .FromReg: X86::YMM16, .ToReg: -2U },
3554 { .FromReg: X86::YMM17, .ToReg: -2U },
3555 { .FromReg: X86::YMM18, .ToReg: -2U },
3556 { .FromReg: X86::YMM19, .ToReg: -2U },
3557 { .FromReg: X86::YMM20, .ToReg: -2U },
3558 { .FromReg: X86::YMM21, .ToReg: -2U },
3559 { .FromReg: X86::YMM22, .ToReg: -2U },
3560 { .FromReg: X86::YMM23, .ToReg: -2U },
3561 { .FromReg: X86::YMM24, .ToReg: -2U },
3562 { .FromReg: X86::YMM25, .ToReg: -2U },
3563 { .FromReg: X86::YMM26, .ToReg: -2U },
3564 { .FromReg: X86::YMM27, .ToReg: -2U },
3565 { .FromReg: X86::YMM28, .ToReg: -2U },
3566 { .FromReg: X86::YMM29, .ToReg: -2U },
3567 { .FromReg: X86::YMM30, .ToReg: -2U },
3568 { .FromReg: X86::YMM31, .ToReg: -2U },
3569 { .FromReg: X86::ZMM0, .ToReg: 21U },
3570 { .FromReg: X86::ZMM1, .ToReg: 22U },
3571 { .FromReg: X86::ZMM2, .ToReg: 23U },
3572 { .FromReg: X86::ZMM3, .ToReg: 24U },
3573 { .FromReg: X86::ZMM4, .ToReg: 25U },
3574 { .FromReg: X86::ZMM5, .ToReg: 26U },
3575 { .FromReg: X86::ZMM6, .ToReg: 27U },
3576 { .FromReg: X86::ZMM7, .ToReg: 28U },
3577 { .FromReg: X86::ZMM8, .ToReg: -2U },
3578 { .FromReg: X86::ZMM9, .ToReg: -2U },
3579 { .FromReg: X86::ZMM10, .ToReg: -2U },
3580 { .FromReg: X86::ZMM11, .ToReg: -2U },
3581 { .FromReg: X86::ZMM12, .ToReg: -2U },
3582 { .FromReg: X86::ZMM13, .ToReg: -2U },
3583 { .FromReg: X86::ZMM14, .ToReg: -2U },
3584 { .FromReg: X86::ZMM15, .ToReg: -2U },
3585 { .FromReg: X86::ZMM16, .ToReg: -2U },
3586 { .FromReg: X86::ZMM17, .ToReg: -2U },
3587 { .FromReg: X86::ZMM18, .ToReg: -2U },
3588 { .FromReg: X86::ZMM19, .ToReg: -2U },
3589 { .FromReg: X86::ZMM20, .ToReg: -2U },
3590 { .FromReg: X86::ZMM21, .ToReg: -2U },
3591 { .FromReg: X86::ZMM22, .ToReg: -2U },
3592 { .FromReg: X86::ZMM23, .ToReg: -2U },
3593 { .FromReg: X86::ZMM24, .ToReg: -2U },
3594 { .FromReg: X86::ZMM25, .ToReg: -2U },
3595 { .FromReg: X86::ZMM26, .ToReg: -2U },
3596 { .FromReg: X86::ZMM27, .ToReg: -2U },
3597 { .FromReg: X86::ZMM28, .ToReg: -2U },
3598 { .FromReg: X86::ZMM29, .ToReg: -2U },
3599 { .FromReg: X86::ZMM30, .ToReg: -2U },
3600 { .FromReg: X86::ZMM31, .ToReg: -2U },
3601 { .FromReg: X86::R16, .ToReg: -2U },
3602 { .FromReg: X86::R17, .ToReg: -2U },
3603 { .FromReg: X86::R18, .ToReg: -2U },
3604 { .FromReg: X86::R19, .ToReg: -2U },
3605 { .FromReg: X86::R20, .ToReg: -2U },
3606 { .FromReg: X86::R21, .ToReg: -2U },
3607 { .FromReg: X86::R22, .ToReg: -2U },
3608 { .FromReg: X86::R23, .ToReg: -2U },
3609 { .FromReg: X86::R24, .ToReg: -2U },
3610 { .FromReg: X86::R25, .ToReg: -2U },
3611 { .FromReg: X86::R26, .ToReg: -2U },
3612 { .FromReg: X86::R27, .ToReg: -2U },
3613 { .FromReg: X86::R28, .ToReg: -2U },
3614 { .FromReg: X86::R29, .ToReg: -2U },
3615 { .FromReg: X86::R30, .ToReg: -2U },
3616 { .FromReg: X86::R31, .ToReg: -2U },
3617};
3618extern const unsigned X86DwarfFlavour2L2DwarfSize = std::size(X86DwarfFlavour2L2Dwarf);
3619
3620extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
3621 { .FromReg: X86::CS, .ToReg: 51U },
3622 { .FromReg: X86::DS, .ToReg: 53U },
3623 { .FromReg: X86::EAX, .ToReg: -2U },
3624 { .FromReg: X86::EBP, .ToReg: -2U },
3625 { .FromReg: X86::EBX, .ToReg: -2U },
3626 { .FromReg: X86::ECX, .ToReg: -2U },
3627 { .FromReg: X86::EDI, .ToReg: -2U },
3628 { .FromReg: X86::EDX, .ToReg: -2U },
3629 { .FromReg: X86::EFLAGS, .ToReg: 49U },
3630 { .FromReg: X86::EIP, .ToReg: -2U },
3631 { .FromReg: X86::ES, .ToReg: 50U },
3632 { .FromReg: X86::ESI, .ToReg: -2U },
3633 { .FromReg: X86::ESP, .ToReg: -2U },
3634 { .FromReg: X86::FS, .ToReg: 54U },
3635 { .FromReg: X86::FS_BASE, .ToReg: 58U },
3636 { .FromReg: X86::GS, .ToReg: 55U },
3637 { .FromReg: X86::GS_BASE, .ToReg: 59U },
3638 { .FromReg: X86::RAX, .ToReg: 0U },
3639 { .FromReg: X86::RBP, .ToReg: 6U },
3640 { .FromReg: X86::RBX, .ToReg: 3U },
3641 { .FromReg: X86::RCX, .ToReg: 2U },
3642 { .FromReg: X86::RDI, .ToReg: 5U },
3643 { .FromReg: X86::RDX, .ToReg: 1U },
3644 { .FromReg: X86::RFLAGS, .ToReg: 49U },
3645 { .FromReg: X86::RIP, .ToReg: 16U },
3646 { .FromReg: X86::RSI, .ToReg: 4U },
3647 { .FromReg: X86::RSP, .ToReg: 7U },
3648 { .FromReg: X86::SS, .ToReg: 52U },
3649 { .FromReg: X86::_EFLAGS, .ToReg: 49U },
3650 { .FromReg: X86::MM0, .ToReg: 41U },
3651 { .FromReg: X86::MM1, .ToReg: 42U },
3652 { .FromReg: X86::MM2, .ToReg: 43U },
3653 { .FromReg: X86::MM3, .ToReg: 44U },
3654 { .FromReg: X86::MM4, .ToReg: 45U },
3655 { .FromReg: X86::MM5, .ToReg: 46U },
3656 { .FromReg: X86::MM6, .ToReg: 47U },
3657 { .FromReg: X86::MM7, .ToReg: 48U },
3658 { .FromReg: X86::R8, .ToReg: 8U },
3659 { .FromReg: X86::R9, .ToReg: 9U },
3660 { .FromReg: X86::R10, .ToReg: 10U },
3661 { .FromReg: X86::R11, .ToReg: 11U },
3662 { .FromReg: X86::R12, .ToReg: 12U },
3663 { .FromReg: X86::R13, .ToReg: 13U },
3664 { .FromReg: X86::R14, .ToReg: 14U },
3665 { .FromReg: X86::R15, .ToReg: 15U },
3666 { .FromReg: X86::ST0, .ToReg: 33U },
3667 { .FromReg: X86::ST1, .ToReg: 34U },
3668 { .FromReg: X86::ST2, .ToReg: 35U },
3669 { .FromReg: X86::ST3, .ToReg: 36U },
3670 { .FromReg: X86::ST4, .ToReg: 37U },
3671 { .FromReg: X86::ST5, .ToReg: 38U },
3672 { .FromReg: X86::ST6, .ToReg: 39U },
3673 { .FromReg: X86::ST7, .ToReg: 40U },
3674 { .FromReg: X86::XMM0, .ToReg: 17U },
3675 { .FromReg: X86::XMM1, .ToReg: 18U },
3676 { .FromReg: X86::XMM2, .ToReg: 19U },
3677 { .FromReg: X86::XMM3, .ToReg: 20U },
3678 { .FromReg: X86::XMM4, .ToReg: 21U },
3679 { .FromReg: X86::XMM5, .ToReg: 22U },
3680 { .FromReg: X86::XMM6, .ToReg: 23U },
3681 { .FromReg: X86::XMM7, .ToReg: 24U },
3682 { .FromReg: X86::XMM8, .ToReg: 25U },
3683 { .FromReg: X86::XMM9, .ToReg: 26U },
3684 { .FromReg: X86::XMM10, .ToReg: 27U },
3685 { .FromReg: X86::XMM11, .ToReg: 28U },
3686 { .FromReg: X86::XMM12, .ToReg: 29U },
3687 { .FromReg: X86::XMM13, .ToReg: 30U },
3688 { .FromReg: X86::XMM14, .ToReg: 31U },
3689 { .FromReg: X86::XMM15, .ToReg: 32U },
3690 { .FromReg: X86::YMM0, .ToReg: 17U },
3691 { .FromReg: X86::YMM1, .ToReg: 18U },
3692 { .FromReg: X86::YMM2, .ToReg: 19U },
3693 { .FromReg: X86::YMM3, .ToReg: 20U },
3694 { .FromReg: X86::YMM4, .ToReg: 21U },
3695 { .FromReg: X86::YMM5, .ToReg: 22U },
3696 { .FromReg: X86::YMM6, .ToReg: 23U },
3697 { .FromReg: X86::YMM7, .ToReg: 24U },
3698 { .FromReg: X86::YMM8, .ToReg: 25U },
3699 { .FromReg: X86::YMM9, .ToReg: 26U },
3700 { .FromReg: X86::YMM10, .ToReg: 27U },
3701 { .FromReg: X86::YMM11, .ToReg: 28U },
3702 { .FromReg: X86::YMM12, .ToReg: 29U },
3703 { .FromReg: X86::YMM13, .ToReg: 30U },
3704 { .FromReg: X86::YMM14, .ToReg: 31U },
3705 { .FromReg: X86::YMM15, .ToReg: 32U },
3706 { .FromReg: X86::K0, .ToReg: 118U },
3707 { .FromReg: X86::K1, .ToReg: 119U },
3708 { .FromReg: X86::K2, .ToReg: 120U },
3709 { .FromReg: X86::K3, .ToReg: 121U },
3710 { .FromReg: X86::K4, .ToReg: 122U },
3711 { .FromReg: X86::K5, .ToReg: 123U },
3712 { .FromReg: X86::K6, .ToReg: 124U },
3713 { .FromReg: X86::K7, .ToReg: 125U },
3714 { .FromReg: X86::XMM16, .ToReg: 67U },
3715 { .FromReg: X86::XMM17, .ToReg: 68U },
3716 { .FromReg: X86::XMM18, .ToReg: 69U },
3717 { .FromReg: X86::XMM19, .ToReg: 70U },
3718 { .FromReg: X86::XMM20, .ToReg: 71U },
3719 { .FromReg: X86::XMM21, .ToReg: 72U },
3720 { .FromReg: X86::XMM22, .ToReg: 73U },
3721 { .FromReg: X86::XMM23, .ToReg: 74U },
3722 { .FromReg: X86::XMM24, .ToReg: 75U },
3723 { .FromReg: X86::XMM25, .ToReg: 76U },
3724 { .FromReg: X86::XMM26, .ToReg: 77U },
3725 { .FromReg: X86::XMM27, .ToReg: 78U },
3726 { .FromReg: X86::XMM28, .ToReg: 79U },
3727 { .FromReg: X86::XMM29, .ToReg: 80U },
3728 { .FromReg: X86::XMM30, .ToReg: 81U },
3729 { .FromReg: X86::XMM31, .ToReg: 82U },
3730 { .FromReg: X86::YMM16, .ToReg: 67U },
3731 { .FromReg: X86::YMM17, .ToReg: 68U },
3732 { .FromReg: X86::YMM18, .ToReg: 69U },
3733 { .FromReg: X86::YMM19, .ToReg: 70U },
3734 { .FromReg: X86::YMM20, .ToReg: 71U },
3735 { .FromReg: X86::YMM21, .ToReg: 72U },
3736 { .FromReg: X86::YMM22, .ToReg: 73U },
3737 { .FromReg: X86::YMM23, .ToReg: 74U },
3738 { .FromReg: X86::YMM24, .ToReg: 75U },
3739 { .FromReg: X86::YMM25, .ToReg: 76U },
3740 { .FromReg: X86::YMM26, .ToReg: 77U },
3741 { .FromReg: X86::YMM27, .ToReg: 78U },
3742 { .FromReg: X86::YMM28, .ToReg: 79U },
3743 { .FromReg: X86::YMM29, .ToReg: 80U },
3744 { .FromReg: X86::YMM30, .ToReg: 81U },
3745 { .FromReg: X86::YMM31, .ToReg: 82U },
3746 { .FromReg: X86::ZMM0, .ToReg: 17U },
3747 { .FromReg: X86::ZMM1, .ToReg: 18U },
3748 { .FromReg: X86::ZMM2, .ToReg: 19U },
3749 { .FromReg: X86::ZMM3, .ToReg: 20U },
3750 { .FromReg: X86::ZMM4, .ToReg: 21U },
3751 { .FromReg: X86::ZMM5, .ToReg: 22U },
3752 { .FromReg: X86::ZMM6, .ToReg: 23U },
3753 { .FromReg: X86::ZMM7, .ToReg: 24U },
3754 { .FromReg: X86::ZMM8, .ToReg: 25U },
3755 { .FromReg: X86::ZMM9, .ToReg: 26U },
3756 { .FromReg: X86::ZMM10, .ToReg: 27U },
3757 { .FromReg: X86::ZMM11, .ToReg: 28U },
3758 { .FromReg: X86::ZMM12, .ToReg: 29U },
3759 { .FromReg: X86::ZMM13, .ToReg: 30U },
3760 { .FromReg: X86::ZMM14, .ToReg: 31U },
3761 { .FromReg: X86::ZMM15, .ToReg: 32U },
3762 { .FromReg: X86::ZMM16, .ToReg: 67U },
3763 { .FromReg: X86::ZMM17, .ToReg: 68U },
3764 { .FromReg: X86::ZMM18, .ToReg: 69U },
3765 { .FromReg: X86::ZMM19, .ToReg: 70U },
3766 { .FromReg: X86::ZMM20, .ToReg: 71U },
3767 { .FromReg: X86::ZMM21, .ToReg: 72U },
3768 { .FromReg: X86::ZMM22, .ToReg: 73U },
3769 { .FromReg: X86::ZMM23, .ToReg: 74U },
3770 { .FromReg: X86::ZMM24, .ToReg: 75U },
3771 { .FromReg: X86::ZMM25, .ToReg: 76U },
3772 { .FromReg: X86::ZMM26, .ToReg: 77U },
3773 { .FromReg: X86::ZMM27, .ToReg: 78U },
3774 { .FromReg: X86::ZMM28, .ToReg: 79U },
3775 { .FromReg: X86::ZMM29, .ToReg: 80U },
3776 { .FromReg: X86::ZMM30, .ToReg: 81U },
3777 { .FromReg: X86::ZMM31, .ToReg: 82U },
3778 { .FromReg: X86::R16, .ToReg: 130U },
3779 { .FromReg: X86::R17, .ToReg: 131U },
3780 { .FromReg: X86::R18, .ToReg: 132U },
3781 { .FromReg: X86::R19, .ToReg: 133U },
3782 { .FromReg: X86::R20, .ToReg: 134U },
3783 { .FromReg: X86::R21, .ToReg: 135U },
3784 { .FromReg: X86::R22, .ToReg: 136U },
3785 { .FromReg: X86::R23, .ToReg: 137U },
3786 { .FromReg: X86::R24, .ToReg: 138U },
3787 { .FromReg: X86::R25, .ToReg: 139U },
3788 { .FromReg: X86::R26, .ToReg: 140U },
3789 { .FromReg: X86::R27, .ToReg: 141U },
3790 { .FromReg: X86::R28, .ToReg: 142U },
3791 { .FromReg: X86::R29, .ToReg: 143U },
3792 { .FromReg: X86::R30, .ToReg: 144U },
3793 { .FromReg: X86::R31, .ToReg: 145U },
3794};
3795extern const unsigned X86EHFlavour0L2DwarfSize = std::size(X86EHFlavour0L2Dwarf);
3796
3797extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
3798 { .FromReg: X86::CS, .ToReg: -2U },
3799 { .FromReg: X86::DS, .ToReg: -2U },
3800 { .FromReg: X86::EAX, .ToReg: 0U },
3801 { .FromReg: X86::EBP, .ToReg: 4U },
3802 { .FromReg: X86::EBX, .ToReg: 3U },
3803 { .FromReg: X86::ECX, .ToReg: 1U },
3804 { .FromReg: X86::EDI, .ToReg: 7U },
3805 { .FromReg: X86::EDX, .ToReg: 2U },
3806 { .FromReg: X86::EFLAGS, .ToReg: 9U },
3807 { .FromReg: X86::EIP, .ToReg: 8U },
3808 { .FromReg: X86::ES, .ToReg: -2U },
3809 { .FromReg: X86::ESI, .ToReg: 6U },
3810 { .FromReg: X86::ESP, .ToReg: 5U },
3811 { .FromReg: X86::FS, .ToReg: -2U },
3812 { .FromReg: X86::FS_BASE, .ToReg: -2U },
3813 { .FromReg: X86::GS, .ToReg: -2U },
3814 { .FromReg: X86::GS_BASE, .ToReg: -2U },
3815 { .FromReg: X86::RAX, .ToReg: -2U },
3816 { .FromReg: X86::RBP, .ToReg: -2U },
3817 { .FromReg: X86::RBX, .ToReg: -2U },
3818 { .FromReg: X86::RCX, .ToReg: -2U },
3819 { .FromReg: X86::RDI, .ToReg: -2U },
3820 { .FromReg: X86::RDX, .ToReg: -2U },
3821 { .FromReg: X86::RFLAGS, .ToReg: -2U },
3822 { .FromReg: X86::RIP, .ToReg: -2U },
3823 { .FromReg: X86::RSI, .ToReg: -2U },
3824 { .FromReg: X86::RSP, .ToReg: -2U },
3825 { .FromReg: X86::SS, .ToReg: -2U },
3826 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
3827 { .FromReg: X86::MM0, .ToReg: 29U },
3828 { .FromReg: X86::MM1, .ToReg: 30U },
3829 { .FromReg: X86::MM2, .ToReg: 31U },
3830 { .FromReg: X86::MM3, .ToReg: 32U },
3831 { .FromReg: X86::MM4, .ToReg: 33U },
3832 { .FromReg: X86::MM5, .ToReg: 34U },
3833 { .FromReg: X86::MM6, .ToReg: 35U },
3834 { .FromReg: X86::MM7, .ToReg: 36U },
3835 { .FromReg: X86::R8, .ToReg: -2U },
3836 { .FromReg: X86::R9, .ToReg: -2U },
3837 { .FromReg: X86::R10, .ToReg: -2U },
3838 { .FromReg: X86::R11, .ToReg: -2U },
3839 { .FromReg: X86::R12, .ToReg: -2U },
3840 { .FromReg: X86::R13, .ToReg: -2U },
3841 { .FromReg: X86::R14, .ToReg: -2U },
3842 { .FromReg: X86::R15, .ToReg: -2U },
3843 { .FromReg: X86::ST0, .ToReg: 12U },
3844 { .FromReg: X86::ST1, .ToReg: 13U },
3845 { .FromReg: X86::ST2, .ToReg: 14U },
3846 { .FromReg: X86::ST3, .ToReg: 15U },
3847 { .FromReg: X86::ST4, .ToReg: 16U },
3848 { .FromReg: X86::ST5, .ToReg: 17U },
3849 { .FromReg: X86::ST6, .ToReg: 18U },
3850 { .FromReg: X86::ST7, .ToReg: 19U },
3851 { .FromReg: X86::XMM0, .ToReg: 21U },
3852 { .FromReg: X86::XMM1, .ToReg: 22U },
3853 { .FromReg: X86::XMM2, .ToReg: 23U },
3854 { .FromReg: X86::XMM3, .ToReg: 24U },
3855 { .FromReg: X86::XMM4, .ToReg: 25U },
3856 { .FromReg: X86::XMM5, .ToReg: 26U },
3857 { .FromReg: X86::XMM6, .ToReg: 27U },
3858 { .FromReg: X86::XMM7, .ToReg: 28U },
3859 { .FromReg: X86::XMM8, .ToReg: -2U },
3860 { .FromReg: X86::XMM9, .ToReg: -2U },
3861 { .FromReg: X86::XMM10, .ToReg: -2U },
3862 { .FromReg: X86::XMM11, .ToReg: -2U },
3863 { .FromReg: X86::XMM12, .ToReg: -2U },
3864 { .FromReg: X86::XMM13, .ToReg: -2U },
3865 { .FromReg: X86::XMM14, .ToReg: -2U },
3866 { .FromReg: X86::XMM15, .ToReg: -2U },
3867 { .FromReg: X86::YMM0, .ToReg: 21U },
3868 { .FromReg: X86::YMM1, .ToReg: 22U },
3869 { .FromReg: X86::YMM2, .ToReg: 23U },
3870 { .FromReg: X86::YMM3, .ToReg: 24U },
3871 { .FromReg: X86::YMM4, .ToReg: 25U },
3872 { .FromReg: X86::YMM5, .ToReg: 26U },
3873 { .FromReg: X86::YMM6, .ToReg: 27U },
3874 { .FromReg: X86::YMM7, .ToReg: 28U },
3875 { .FromReg: X86::YMM8, .ToReg: -2U },
3876 { .FromReg: X86::YMM9, .ToReg: -2U },
3877 { .FromReg: X86::YMM10, .ToReg: -2U },
3878 { .FromReg: X86::YMM11, .ToReg: -2U },
3879 { .FromReg: X86::YMM12, .ToReg: -2U },
3880 { .FromReg: X86::YMM13, .ToReg: -2U },
3881 { .FromReg: X86::YMM14, .ToReg: -2U },
3882 { .FromReg: X86::YMM15, .ToReg: -2U },
3883 { .FromReg: X86::K0, .ToReg: 93U },
3884 { .FromReg: X86::K1, .ToReg: 94U },
3885 { .FromReg: X86::K2, .ToReg: 95U },
3886 { .FromReg: X86::K3, .ToReg: 96U },
3887 { .FromReg: X86::K4, .ToReg: 97U },
3888 { .FromReg: X86::K5, .ToReg: 98U },
3889 { .FromReg: X86::K6, .ToReg: 99U },
3890 { .FromReg: X86::K7, .ToReg: 100U },
3891 { .FromReg: X86::XMM16, .ToReg: -2U },
3892 { .FromReg: X86::XMM17, .ToReg: -2U },
3893 { .FromReg: X86::XMM18, .ToReg: -2U },
3894 { .FromReg: X86::XMM19, .ToReg: -2U },
3895 { .FromReg: X86::XMM20, .ToReg: -2U },
3896 { .FromReg: X86::XMM21, .ToReg: -2U },
3897 { .FromReg: X86::XMM22, .ToReg: -2U },
3898 { .FromReg: X86::XMM23, .ToReg: -2U },
3899 { .FromReg: X86::XMM24, .ToReg: -2U },
3900 { .FromReg: X86::XMM25, .ToReg: -2U },
3901 { .FromReg: X86::XMM26, .ToReg: -2U },
3902 { .FromReg: X86::XMM27, .ToReg: -2U },
3903 { .FromReg: X86::XMM28, .ToReg: -2U },
3904 { .FromReg: X86::XMM29, .ToReg: -2U },
3905 { .FromReg: X86::XMM30, .ToReg: -2U },
3906 { .FromReg: X86::XMM31, .ToReg: -2U },
3907 { .FromReg: X86::YMM16, .ToReg: -2U },
3908 { .FromReg: X86::YMM17, .ToReg: -2U },
3909 { .FromReg: X86::YMM18, .ToReg: -2U },
3910 { .FromReg: X86::YMM19, .ToReg: -2U },
3911 { .FromReg: X86::YMM20, .ToReg: -2U },
3912 { .FromReg: X86::YMM21, .ToReg: -2U },
3913 { .FromReg: X86::YMM22, .ToReg: -2U },
3914 { .FromReg: X86::YMM23, .ToReg: -2U },
3915 { .FromReg: X86::YMM24, .ToReg: -2U },
3916 { .FromReg: X86::YMM25, .ToReg: -2U },
3917 { .FromReg: X86::YMM26, .ToReg: -2U },
3918 { .FromReg: X86::YMM27, .ToReg: -2U },
3919 { .FromReg: X86::YMM28, .ToReg: -2U },
3920 { .FromReg: X86::YMM29, .ToReg: -2U },
3921 { .FromReg: X86::YMM30, .ToReg: -2U },
3922 { .FromReg: X86::YMM31, .ToReg: -2U },
3923 { .FromReg: X86::ZMM0, .ToReg: 21U },
3924 { .FromReg: X86::ZMM1, .ToReg: 22U },
3925 { .FromReg: X86::ZMM2, .ToReg: 23U },
3926 { .FromReg: X86::ZMM3, .ToReg: 24U },
3927 { .FromReg: X86::ZMM4, .ToReg: 25U },
3928 { .FromReg: X86::ZMM5, .ToReg: 26U },
3929 { .FromReg: X86::ZMM6, .ToReg: 27U },
3930 { .FromReg: X86::ZMM7, .ToReg: 28U },
3931 { .FromReg: X86::ZMM8, .ToReg: -2U },
3932 { .FromReg: X86::ZMM9, .ToReg: -2U },
3933 { .FromReg: X86::ZMM10, .ToReg: -2U },
3934 { .FromReg: X86::ZMM11, .ToReg: -2U },
3935 { .FromReg: X86::ZMM12, .ToReg: -2U },
3936 { .FromReg: X86::ZMM13, .ToReg: -2U },
3937 { .FromReg: X86::ZMM14, .ToReg: -2U },
3938 { .FromReg: X86::ZMM15, .ToReg: -2U },
3939 { .FromReg: X86::ZMM16, .ToReg: -2U },
3940 { .FromReg: X86::ZMM17, .ToReg: -2U },
3941 { .FromReg: X86::ZMM18, .ToReg: -2U },
3942 { .FromReg: X86::ZMM19, .ToReg: -2U },
3943 { .FromReg: X86::ZMM20, .ToReg: -2U },
3944 { .FromReg: X86::ZMM21, .ToReg: -2U },
3945 { .FromReg: X86::ZMM22, .ToReg: -2U },
3946 { .FromReg: X86::ZMM23, .ToReg: -2U },
3947 { .FromReg: X86::ZMM24, .ToReg: -2U },
3948 { .FromReg: X86::ZMM25, .ToReg: -2U },
3949 { .FromReg: X86::ZMM26, .ToReg: -2U },
3950 { .FromReg: X86::ZMM27, .ToReg: -2U },
3951 { .FromReg: X86::ZMM28, .ToReg: -2U },
3952 { .FromReg: X86::ZMM29, .ToReg: -2U },
3953 { .FromReg: X86::ZMM30, .ToReg: -2U },
3954 { .FromReg: X86::ZMM31, .ToReg: -2U },
3955 { .FromReg: X86::R16, .ToReg: -2U },
3956 { .FromReg: X86::R17, .ToReg: -2U },
3957 { .FromReg: X86::R18, .ToReg: -2U },
3958 { .FromReg: X86::R19, .ToReg: -2U },
3959 { .FromReg: X86::R20, .ToReg: -2U },
3960 { .FromReg: X86::R21, .ToReg: -2U },
3961 { .FromReg: X86::R22, .ToReg: -2U },
3962 { .FromReg: X86::R23, .ToReg: -2U },
3963 { .FromReg: X86::R24, .ToReg: -2U },
3964 { .FromReg: X86::R25, .ToReg: -2U },
3965 { .FromReg: X86::R26, .ToReg: -2U },
3966 { .FromReg: X86::R27, .ToReg: -2U },
3967 { .FromReg: X86::R28, .ToReg: -2U },
3968 { .FromReg: X86::R29, .ToReg: -2U },
3969 { .FromReg: X86::R30, .ToReg: -2U },
3970 { .FromReg: X86::R31, .ToReg: -2U },
3971};
3972extern const unsigned X86EHFlavour1L2DwarfSize = std::size(X86EHFlavour1L2Dwarf);
3973
3974extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
3975 { .FromReg: X86::CS, .ToReg: 41U },
3976 { .FromReg: X86::DS, .ToReg: 43U },
3977 { .FromReg: X86::EAX, .ToReg: 0U },
3978 { .FromReg: X86::EBP, .ToReg: 5U },
3979 { .FromReg: X86::EBX, .ToReg: 3U },
3980 { .FromReg: X86::ECX, .ToReg: 1U },
3981 { .FromReg: X86::EDI, .ToReg: 7U },
3982 { .FromReg: X86::EDX, .ToReg: 2U },
3983 { .FromReg: X86::EFLAGS, .ToReg: 9U },
3984 { .FromReg: X86::EIP, .ToReg: 8U },
3985 { .FromReg: X86::ES, .ToReg: 40U },
3986 { .FromReg: X86::ESI, .ToReg: 6U },
3987 { .FromReg: X86::ESP, .ToReg: 4U },
3988 { .FromReg: X86::FS, .ToReg: 44U },
3989 { .FromReg: X86::FS_BASE, .ToReg: -2U },
3990 { .FromReg: X86::GS, .ToReg: 45U },
3991 { .FromReg: X86::GS_BASE, .ToReg: -2U },
3992 { .FromReg: X86::RAX, .ToReg: -2U },
3993 { .FromReg: X86::RBP, .ToReg: -2U },
3994 { .FromReg: X86::RBX, .ToReg: -2U },
3995 { .FromReg: X86::RCX, .ToReg: -2U },
3996 { .FromReg: X86::RDI, .ToReg: -2U },
3997 { .FromReg: X86::RDX, .ToReg: -2U },
3998 { .FromReg: X86::RFLAGS, .ToReg: -2U },
3999 { .FromReg: X86::RIP, .ToReg: -2U },
4000 { .FromReg: X86::RSI, .ToReg: -2U },
4001 { .FromReg: X86::RSP, .ToReg: -2U },
4002 { .FromReg: X86::SS, .ToReg: 42U },
4003 { .FromReg: X86::_EFLAGS, .ToReg: 9U },
4004 { .FromReg: X86::MM0, .ToReg: 29U },
4005 { .FromReg: X86::MM1, .ToReg: 30U },
4006 { .FromReg: X86::MM2, .ToReg: 31U },
4007 { .FromReg: X86::MM3, .ToReg: 32U },
4008 { .FromReg: X86::MM4, .ToReg: 33U },
4009 { .FromReg: X86::MM5, .ToReg: 34U },
4010 { .FromReg: X86::MM6, .ToReg: 35U },
4011 { .FromReg: X86::MM7, .ToReg: 36U },
4012 { .FromReg: X86::R8, .ToReg: -2U },
4013 { .FromReg: X86::R9, .ToReg: -2U },
4014 { .FromReg: X86::R10, .ToReg: -2U },
4015 { .FromReg: X86::R11, .ToReg: -2U },
4016 { .FromReg: X86::R12, .ToReg: -2U },
4017 { .FromReg: X86::R13, .ToReg: -2U },
4018 { .FromReg: X86::R14, .ToReg: -2U },
4019 { .FromReg: X86::R15, .ToReg: -2U },
4020 { .FromReg: X86::ST0, .ToReg: 11U },
4021 { .FromReg: X86::ST1, .ToReg: 12U },
4022 { .FromReg: X86::ST2, .ToReg: 13U },
4023 { .FromReg: X86::ST3, .ToReg: 14U },
4024 { .FromReg: X86::ST4, .ToReg: 15U },
4025 { .FromReg: X86::ST5, .ToReg: 16U },
4026 { .FromReg: X86::ST6, .ToReg: 17U },
4027 { .FromReg: X86::ST7, .ToReg: 18U },
4028 { .FromReg: X86::XMM0, .ToReg: 21U },
4029 { .FromReg: X86::XMM1, .ToReg: 22U },
4030 { .FromReg: X86::XMM2, .ToReg: 23U },
4031 { .FromReg: X86::XMM3, .ToReg: 24U },
4032 { .FromReg: X86::XMM4, .ToReg: 25U },
4033 { .FromReg: X86::XMM5, .ToReg: 26U },
4034 { .FromReg: X86::XMM6, .ToReg: 27U },
4035 { .FromReg: X86::XMM7, .ToReg: 28U },
4036 { .FromReg: X86::XMM8, .ToReg: -2U },
4037 { .FromReg: X86::XMM9, .ToReg: -2U },
4038 { .FromReg: X86::XMM10, .ToReg: -2U },
4039 { .FromReg: X86::XMM11, .ToReg: -2U },
4040 { .FromReg: X86::XMM12, .ToReg: -2U },
4041 { .FromReg: X86::XMM13, .ToReg: -2U },
4042 { .FromReg: X86::XMM14, .ToReg: -2U },
4043 { .FromReg: X86::XMM15, .ToReg: -2U },
4044 { .FromReg: X86::YMM0, .ToReg: 21U },
4045 { .FromReg: X86::YMM1, .ToReg: 22U },
4046 { .FromReg: X86::YMM2, .ToReg: 23U },
4047 { .FromReg: X86::YMM3, .ToReg: 24U },
4048 { .FromReg: X86::YMM4, .ToReg: 25U },
4049 { .FromReg: X86::YMM5, .ToReg: 26U },
4050 { .FromReg: X86::YMM6, .ToReg: 27U },
4051 { .FromReg: X86::YMM7, .ToReg: 28U },
4052 { .FromReg: X86::YMM8, .ToReg: -2U },
4053 { .FromReg: X86::YMM9, .ToReg: -2U },
4054 { .FromReg: X86::YMM10, .ToReg: -2U },
4055 { .FromReg: X86::YMM11, .ToReg: -2U },
4056 { .FromReg: X86::YMM12, .ToReg: -2U },
4057 { .FromReg: X86::YMM13, .ToReg: -2U },
4058 { .FromReg: X86::YMM14, .ToReg: -2U },
4059 { .FromReg: X86::YMM15, .ToReg: -2U },
4060 { .FromReg: X86::K0, .ToReg: 93U },
4061 { .FromReg: X86::K1, .ToReg: 94U },
4062 { .FromReg: X86::K2, .ToReg: 95U },
4063 { .FromReg: X86::K3, .ToReg: 96U },
4064 { .FromReg: X86::K4, .ToReg: 97U },
4065 { .FromReg: X86::K5, .ToReg: 98U },
4066 { .FromReg: X86::K6, .ToReg: 99U },
4067 { .FromReg: X86::K7, .ToReg: 100U },
4068 { .FromReg: X86::XMM16, .ToReg: -2U },
4069 { .FromReg: X86::XMM17, .ToReg: -2U },
4070 { .FromReg: X86::XMM18, .ToReg: -2U },
4071 { .FromReg: X86::XMM19, .ToReg: -2U },
4072 { .FromReg: X86::XMM20, .ToReg: -2U },
4073 { .FromReg: X86::XMM21, .ToReg: -2U },
4074 { .FromReg: X86::XMM22, .ToReg: -2U },
4075 { .FromReg: X86::XMM23, .ToReg: -2U },
4076 { .FromReg: X86::XMM24, .ToReg: -2U },
4077 { .FromReg: X86::XMM25, .ToReg: -2U },
4078 { .FromReg: X86::XMM26, .ToReg: -2U },
4079 { .FromReg: X86::XMM27, .ToReg: -2U },
4080 { .FromReg: X86::XMM28, .ToReg: -2U },
4081 { .FromReg: X86::XMM29, .ToReg: -2U },
4082 { .FromReg: X86::XMM30, .ToReg: -2U },
4083 { .FromReg: X86::XMM31, .ToReg: -2U },
4084 { .FromReg: X86::YMM16, .ToReg: -2U },
4085 { .FromReg: X86::YMM17, .ToReg: -2U },
4086 { .FromReg: X86::YMM18, .ToReg: -2U },
4087 { .FromReg: X86::YMM19, .ToReg: -2U },
4088 { .FromReg: X86::YMM20, .ToReg: -2U },
4089 { .FromReg: X86::YMM21, .ToReg: -2U },
4090 { .FromReg: X86::YMM22, .ToReg: -2U },
4091 { .FromReg: X86::YMM23, .ToReg: -2U },
4092 { .FromReg: X86::YMM24, .ToReg: -2U },
4093 { .FromReg: X86::YMM25, .ToReg: -2U },
4094 { .FromReg: X86::YMM26, .ToReg: -2U },
4095 { .FromReg: X86::YMM27, .ToReg: -2U },
4096 { .FromReg: X86::YMM28, .ToReg: -2U },
4097 { .FromReg: X86::YMM29, .ToReg: -2U },
4098 { .FromReg: X86::YMM30, .ToReg: -2U },
4099 { .FromReg: X86::YMM31, .ToReg: -2U },
4100 { .FromReg: X86::ZMM0, .ToReg: 21U },
4101 { .FromReg: X86::ZMM1, .ToReg: 22U },
4102 { .FromReg: X86::ZMM2, .ToReg: 23U },
4103 { .FromReg: X86::ZMM3, .ToReg: 24U },
4104 { .FromReg: X86::ZMM4, .ToReg: 25U },
4105 { .FromReg: X86::ZMM5, .ToReg: 26U },
4106 { .FromReg: X86::ZMM6, .ToReg: 27U },
4107 { .FromReg: X86::ZMM7, .ToReg: 28U },
4108 { .FromReg: X86::ZMM8, .ToReg: -2U },
4109 { .FromReg: X86::ZMM9, .ToReg: -2U },
4110 { .FromReg: X86::ZMM10, .ToReg: -2U },
4111 { .FromReg: X86::ZMM11, .ToReg: -2U },
4112 { .FromReg: X86::ZMM12, .ToReg: -2U },
4113 { .FromReg: X86::ZMM13, .ToReg: -2U },
4114 { .FromReg: X86::ZMM14, .ToReg: -2U },
4115 { .FromReg: X86::ZMM15, .ToReg: -2U },
4116 { .FromReg: X86::ZMM16, .ToReg: -2U },
4117 { .FromReg: X86::ZMM17, .ToReg: -2U },
4118 { .FromReg: X86::ZMM18, .ToReg: -2U },
4119 { .FromReg: X86::ZMM19, .ToReg: -2U },
4120 { .FromReg: X86::ZMM20, .ToReg: -2U },
4121 { .FromReg: X86::ZMM21, .ToReg: -2U },
4122 { .FromReg: X86::ZMM22, .ToReg: -2U },
4123 { .FromReg: X86::ZMM23, .ToReg: -2U },
4124 { .FromReg: X86::ZMM24, .ToReg: -2U },
4125 { .FromReg: X86::ZMM25, .ToReg: -2U },
4126 { .FromReg: X86::ZMM26, .ToReg: -2U },
4127 { .FromReg: X86::ZMM27, .ToReg: -2U },
4128 { .FromReg: X86::ZMM28, .ToReg: -2U },
4129 { .FromReg: X86::ZMM29, .ToReg: -2U },
4130 { .FromReg: X86::ZMM30, .ToReg: -2U },
4131 { .FromReg: X86::ZMM31, .ToReg: -2U },
4132 { .FromReg: X86::R16, .ToReg: -2U },
4133 { .FromReg: X86::R17, .ToReg: -2U },
4134 { .FromReg: X86::R18, .ToReg: -2U },
4135 { .FromReg: X86::R19, .ToReg: -2U },
4136 { .FromReg: X86::R20, .ToReg: -2U },
4137 { .FromReg: X86::R21, .ToReg: -2U },
4138 { .FromReg: X86::R22, .ToReg: -2U },
4139 { .FromReg: X86::R23, .ToReg: -2U },
4140 { .FromReg: X86::R24, .ToReg: -2U },
4141 { .FromReg: X86::R25, .ToReg: -2U },
4142 { .FromReg: X86::R26, .ToReg: -2U },
4143 { .FromReg: X86::R27, .ToReg: -2U },
4144 { .FromReg: X86::R28, .ToReg: -2U },
4145 { .FromReg: X86::R29, .ToReg: -2U },
4146 { .FromReg: X86::R30, .ToReg: -2U },
4147 { .FromReg: X86::R31, .ToReg: -2U },
4148};
4149extern const unsigned X86EHFlavour2L2DwarfSize = std::size(X86EHFlavour2L2Dwarf);
4150
4151extern const uint16_t X86RegEncodingTable[] = {
4152 0,
4153 4,
4154 0,
4155 0,
4156 7,
4157 3,
4158 5,
4159 65535,
4160 5,
4161 3,
4162 5,
4163 1,
4164 1,
4165 1,
4166 0,
4167 6,
4168 7,
4169 65535,
4170 7,
4171 2,
4172 3,
4173 2,
4174 0,
4175 5,
4176 3,
4177 1,
4178 7,
4179 2,
4180 0,
4181 0,
4182 4,
4183 0,
4184 6,
4185 4,
4186 0,
4187 0,
4188 4,
4189 0,
4190 5,
4191 0,
4192 65535,
4193 65535,
4194 65535,
4195 65535,
4196 65535,
4197 65535,
4198 65535,
4199 65535,
4200 65535,
4201 0,
4202 0,
4203 0,
4204 5,
4205 3,
4206 1,
4207 7,
4208 2,
4209 0,
4210 0,
4211 4,
4212 6,
4213 4,
4214 6,
4215 65535,
4216 6,
4217 4,
4218 65535,
4219 4,
4220 2,
4221 0,
4222 0,
4223 0,
4224 1,
4225 2,
4226 3,
4227 4,
4228 5,
4229 6,
4230 7,
4231 8,
4232 9,
4233 10,
4234 11,
4235 12,
4236 13,
4237 14,
4238 15,
4239 0,
4240 1,
4241 2,
4242 3,
4243 4,
4244 5,
4245 6,
4246 7,
4247 8,
4248 9,
4249 10,
4250 11,
4251 12,
4252 13,
4253 14,
4254 15,
4255 0,
4256 0,
4257 0,
4258 0,
4259 0,
4260 0,
4261 0,
4262 0,
4263 0,
4264 1,
4265 2,
4266 3,
4267 4,
4268 5,
4269 6,
4270 7,
4271 8,
4272 9,
4273 10,
4274 11,
4275 12,
4276 13,
4277 14,
4278 15,
4279 0,
4280 1,
4281 2,
4282 3,
4283 4,
4284 5,
4285 6,
4286 7,
4287 0,
4288 1,
4289 2,
4290 3,
4291 4,
4292 5,
4293 6,
4294 7,
4295 8,
4296 9,
4297 10,
4298 11,
4299 12,
4300 13,
4301 14,
4302 15,
4303 8,
4304 9,
4305 10,
4306 11,
4307 12,
4308 13,
4309 14,
4310 15,
4311 65535,
4312 65535,
4313 65535,
4314 65535,
4315 65535,
4316 65535,
4317 65535,
4318 65535,
4319 8,
4320 9,
4321 10,
4322 11,
4323 12,
4324 13,
4325 14,
4326 15,
4327 8,
4328 9,
4329 10,
4330 11,
4331 12,
4332 13,
4333 14,
4334 15,
4335 65535,
4336 65535,
4337 65535,
4338 65535,
4339 65535,
4340 65535,
4341 65535,
4342 65535,
4343 0,
4344 1,
4345 2,
4346 3,
4347 4,
4348 5,
4349 6,
4350 7,
4351 8,
4352 9,
4353 10,
4354 11,
4355 12,
4356 13,
4357 14,
4358 15,
4359 0,
4360 1,
4361 2,
4362 3,
4363 4,
4364 5,
4365 6,
4366 7,
4367 16,
4368 17,
4369 18,
4370 19,
4371 20,
4372 21,
4373 22,
4374 23,
4375 24,
4376 25,
4377 26,
4378 27,
4379 28,
4380 29,
4381 30,
4382 31,
4383 16,
4384 17,
4385 18,
4386 19,
4387 20,
4388 21,
4389 22,
4390 23,
4391 24,
4392 25,
4393 26,
4394 27,
4395 28,
4396 29,
4397 30,
4398 31,
4399 0,
4400 1,
4401 2,
4402 3,
4403 4,
4404 5,
4405 6,
4406 7,
4407 8,
4408 9,
4409 10,
4410 11,
4411 12,
4412 13,
4413 14,
4414 15,
4415 16,
4416 17,
4417 18,
4418 19,
4419 20,
4420 21,
4421 22,
4422 23,
4423 24,
4424 25,
4425 26,
4426 27,
4427 28,
4428 29,
4429 30,
4430 31,
4431 0,
4432 2,
4433 4,
4434 6,
4435 0,
4436 0,
4437 1,
4438 2,
4439 3,
4440 4,
4441 5,
4442 6,
4443 7,
4444 16,
4445 17,
4446 18,
4447 19,
4448 20,
4449 21,
4450 22,
4451 23,
4452 24,
4453 25,
4454 26,
4455 27,
4456 28,
4457 29,
4458 30,
4459 31,
4460 16,
4461 17,
4462 18,
4463 19,
4464 20,
4465 21,
4466 22,
4467 23,
4468 24,
4469 25,
4470 26,
4471 27,
4472 28,
4473 29,
4474 30,
4475 31,
4476 65535,
4477 65535,
4478 65535,
4479 65535,
4480 65535,
4481 65535,
4482 65535,
4483 65535,
4484 65535,
4485 65535,
4486 65535,
4487 65535,
4488 65535,
4489 65535,
4490 65535,
4491 65535,
4492 16,
4493 17,
4494 18,
4495 19,
4496 20,
4497 21,
4498 22,
4499 23,
4500 24,
4501 25,
4502 26,
4503 27,
4504 28,
4505 29,
4506 30,
4507 31,
4508 16,
4509 17,
4510 18,
4511 19,
4512 20,
4513 21,
4514 22,
4515 23,
4516 24,
4517 25,
4518 26,
4519 27,
4520 28,
4521 29,
4522 30,
4523 31,
4524 65535,
4525 65535,
4526 65535,
4527 65535,
4528 65535,
4529 65535,
4530 65535,
4531 65535,
4532 65535,
4533 65535,
4534 65535,
4535 65535,
4536 65535,
4537 65535,
4538 65535,
4539 65535,
4540};
4541static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
4542 RI->InitMCRegisterInfo(D: X86RegDesc, NR: 388, RA, PC, C: X86MCRegisterClasses, NC: 135, RURoots: X86RegUnitRoots, NRU: 221, DL: X86RegDiffLists, RUMS: X86LaneMaskLists, Strings: X86RegStrings, ClassStrings: X86RegClassStrings, SubIndices: X86SubRegIdxLists, NumIndices: 11,
4543RET: X86RegEncodingTable);
4544
4545 switch (DwarfFlavour) {
4546 default:
4547 llvm_unreachable("Unknown DWARF flavour");
4548 case 0:
4549 RI->mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour0Dwarf2L, Size: X86DwarfFlavour0Dwarf2LSize, isEH: false);
4550 break;
4551 case 1:
4552 RI->mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour1Dwarf2L, Size: X86DwarfFlavour1Dwarf2LSize, isEH: false);
4553 break;
4554 case 2:
4555 RI->mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour2Dwarf2L, Size: X86DwarfFlavour2Dwarf2LSize, isEH: false);
4556 break;
4557 }
4558 switch (EHFlavour) {
4559 default:
4560 llvm_unreachable("Unknown DWARF flavour");
4561 case 0:
4562 RI->mapDwarfRegsToLLVMRegs(Map: X86EHFlavour0Dwarf2L, Size: X86EHFlavour0Dwarf2LSize, isEH: true);
4563 break;
4564 case 1:
4565 RI->mapDwarfRegsToLLVMRegs(Map: X86EHFlavour1Dwarf2L, Size: X86EHFlavour1Dwarf2LSize, isEH: true);
4566 break;
4567 case 2:
4568 RI->mapDwarfRegsToLLVMRegs(Map: X86EHFlavour2Dwarf2L, Size: X86EHFlavour2Dwarf2LSize, isEH: true);
4569 break;
4570 }
4571 switch (DwarfFlavour) {
4572 default:
4573 llvm_unreachable("Unknown DWARF flavour");
4574 case 0:
4575 RI->mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour0L2Dwarf, Size: X86DwarfFlavour0L2DwarfSize, isEH: false);
4576 break;
4577 case 1:
4578 RI->mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour1L2Dwarf, Size: X86DwarfFlavour1L2DwarfSize, isEH: false);
4579 break;
4580 case 2:
4581 RI->mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour2L2Dwarf, Size: X86DwarfFlavour2L2DwarfSize, isEH: false);
4582 break;
4583 }
4584 switch (EHFlavour) {
4585 default:
4586 llvm_unreachable("Unknown DWARF flavour");
4587 case 0:
4588 RI->mapLLVMRegsToDwarfRegs(Map: X86EHFlavour0L2Dwarf, Size: X86EHFlavour0L2DwarfSize, isEH: true);
4589 break;
4590 case 1:
4591 RI->mapLLVMRegsToDwarfRegs(Map: X86EHFlavour1L2Dwarf, Size: X86EHFlavour1L2DwarfSize, isEH: true);
4592 break;
4593 case 2:
4594 RI->mapLLVMRegsToDwarfRegs(Map: X86EHFlavour2L2Dwarf, Size: X86EHFlavour2L2DwarfSize, isEH: true);
4595 break;
4596 }
4597}
4598
4599} // end namespace llvm
4600
4601