1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides X86 specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86MCTargetDesc.h"
14#include "TargetInfo/X86TargetInfo.h"
15#include "X86ATTInstPrinter.h"
16#include "X86BaseInfo.h"
17#include "X86IntelInstPrinter.h"
18#include "X86MCAsmInfo.h"
19#include "X86MCLFIRewriter.h"
20#include "X86MCOptions.h"
21#include "X86TargetStreamer.h"
22#include "llvm-c/Visibility.h"
23#include "llvm/ADT/APInt.h"
24#include "llvm/DebugInfo/CodeView/CodeView.h"
25#include "llvm/MC/MCDwarf.h"
26#include "llvm/MC/MCInstrAnalysis.h"
27#include "llvm/MC/MCInstrInfo.h"
28#include "llvm/MC/MCRegisterInfo.h"
29#include "llvm/MC/MCStreamer.h"
30#include "llvm/MC/MCSubtargetInfo.h"
31#include "llvm/MC/TargetRegistry.h"
32#include "llvm/Option/LibraryOptions.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/TargetParser/Host.h"
35#include "llvm/TargetParser/Triple.h"
36
37using namespace llvm;
38
39#define GET_REGINFO_MC_DESC
40#include "X86GenRegisterInfo.inc"
41
42#define GET_INSTRINFO_MC_DESC
43#define GET_INSTRINFO_MC_HELPERS
44#define ENABLE_INSTR_PREDICATE_VERIFIER
45#include "X86GenInstrInfo.inc"
46
47#define GET_SUBTARGETINFO_MC_DESC
48#include "X86GenSubtargetInfo.inc"
49
50#define OPTIONS_STRUCT_DEFS
51#include "X86MCOptions.inc"
52
53std::string X86_MC::ParseX86Triple(const Triple &TT) {
54 std::string FS;
55 // SSE2 should default to enabled in 64-bit mode, but can be turned off
56 // explicitly.
57 if (TT.isX86_64())
58 FS = "+64bit-mode,-32bit-mode,-16bit-mode,+sse2";
59 else if (TT.getEnvironment() != Triple::CODE16)
60 FS = "-64bit-mode,+32bit-mode,-16bit-mode";
61 else
62 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
63
64 if (TT.isX32())
65 FS += ",+x32";
66
67 return FS;
68}
69
70unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
71 if (TT.isX86_64())
72 return DWARFFlavour::X86_64;
73
74 if (TT.isOSDarwin())
75 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
76 if (TT.isOSCygMing())
77 // Unsupported by now, just quick fallback
78 return DWARFFlavour::X86_32_Generic;
79 return DWARFFlavour::X86_32_Generic;
80}
81
82bool X86_MC::hasLockPrefix(const MCInst &MI) {
83 return MI.getFlags() & X86::IP_HAS_LOCK;
84}
85
86static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) {
87 const MCOperand &Base = MI.getOperand(i: Op + X86::AddrBaseReg);
88 const MCOperand &Index = MI.getOperand(i: Op + X86::AddrIndexReg);
89 const MCRegisterClass &RC = getX86MCRegisterClass(RC: RegClassID);
90
91 return (Base.isReg() && Base.getReg() && RC.contains(Reg: Base.getReg())) ||
92 (Index.isReg() && Index.getReg() && RC.contains(Reg: Index.getReg()));
93}
94
95bool X86_MC::is16BitMemOperand(const MCInst &MI, unsigned Op,
96 const MCSubtargetInfo &STI) {
97 const MCOperand &Base = MI.getOperand(i: Op + X86::AddrBaseReg);
98 const MCOperand &Index = MI.getOperand(i: Op + X86::AddrIndexReg);
99
100 if (STI.hasFeature(Feature: X86::Is16Bit) && Base.isReg() && !Base.getReg() &&
101 Index.isReg() && !Index.getReg())
102 return true;
103 return isMemOperand(MI, Op, RegClassID: X86::GR16RegClassID);
104}
105
106bool X86_MC::is32BitMemOperand(const MCInst &MI, unsigned Op) {
107 const MCOperand &Base = MI.getOperand(i: Op + X86::AddrBaseReg);
108 const MCOperand &Index = MI.getOperand(i: Op + X86::AddrIndexReg);
109 if (Base.isReg() && Base.getReg() == X86::EIP) {
110 assert(Index.isReg() && !Index.getReg() && "Invalid eip-based address");
111 return true;
112 }
113 if (Index.isReg() && Index.getReg() == X86::EIZ)
114 return true;
115 return isMemOperand(MI, Op, RegClassID: X86::GR32RegClassID);
116}
117
118#ifndef NDEBUG
119bool X86_MC::is64BitMemOperand(const MCInst &MI, unsigned Op) {
120 return isMemOperand(MI, Op, X86::GR64RegClassID);
121}
122#endif
123
124bool X86_MC::needsAddressSizeOverride(const MCInst &MI,
125 const MCSubtargetInfo &STI,
126 int MemoryOperand, uint64_t TSFlags) {
127 uint64_t AdSize = TSFlags & X86II::AdSizeMask;
128 bool Is16BitMode = STI.hasFeature(Feature: X86::Is16Bit);
129 bool Is32BitMode = STI.hasFeature(Feature: X86::Is32Bit);
130 bool Is64BitMode = STI.hasFeature(Feature: X86::Is64Bit);
131 if ((Is16BitMode && AdSize == X86II::AdSize32) ||
132 (Is32BitMode && AdSize == X86II::AdSize16) ||
133 (Is64BitMode && AdSize == X86II::AdSize32))
134 return true;
135 uint64_t Form = TSFlags & X86II::FormMask;
136 switch (Form) {
137 default:
138 break;
139 case X86II::RawFrmDstSrc: {
140 MCRegister siReg = MI.getOperand(i: 1).getReg();
141 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||
142 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||
143 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
144 "SI and DI register sizes do not match");
145 return (!Is32BitMode && siReg == X86::ESI) ||
146 (Is32BitMode && siReg == X86::SI);
147 }
148 case X86II::RawFrmSrc: {
149 MCRegister siReg = MI.getOperand(i: 0).getReg();
150 return (!Is32BitMode && siReg == X86::ESI) ||
151 (Is32BitMode && siReg == X86::SI);
152 }
153 case X86II::RawFrmDst: {
154 MCRegister siReg = MI.getOperand(i: 0).getReg();
155 return (!Is32BitMode && siReg == X86::EDI) ||
156 (Is32BitMode && siReg == X86::DI);
157 }
158 }
159
160 // Determine where the memory operand starts, if present.
161 if (MemoryOperand < 0)
162 return false;
163
164 if (STI.hasFeature(Feature: X86::Is64Bit)) {
165 assert(!is16BitMemOperand(MI, MemoryOperand, STI));
166 return is32BitMemOperand(MI, Op: MemoryOperand);
167 }
168 if (STI.hasFeature(Feature: X86::Is32Bit)) {
169 assert(!is64BitMemOperand(MI, MemoryOperand));
170 return is16BitMemOperand(MI, Op: MemoryOperand, STI);
171 }
172 assert(STI.hasFeature(X86::Is16Bit));
173 assert(!is64BitMemOperand(MI, MemoryOperand));
174 return !is16BitMemOperand(MI, Op: MemoryOperand, STI);
175}
176
177void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
178 // FIXME: TableGen these.
179 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
180 unsigned SEH = MRI->getEncodingValue(Reg);
181 MRI->mapLLVMRegToSEHReg(LLVMReg: Reg, SEHReg: SEH);
182 }
183
184 // Mapping from CodeView to MC register id.
185 static const struct {
186 codeview::RegisterId CVReg;
187 MCPhysReg Reg;
188 } RegMap[] = {
189 {.CVReg: codeview::RegisterId::AL, .Reg: X86::AL},
190 {.CVReg: codeview::RegisterId::CL, .Reg: X86::CL},
191 {.CVReg: codeview::RegisterId::DL, .Reg: X86::DL},
192 {.CVReg: codeview::RegisterId::BL, .Reg: X86::BL},
193 {.CVReg: codeview::RegisterId::AH, .Reg: X86::AH},
194 {.CVReg: codeview::RegisterId::CH, .Reg: X86::CH},
195 {.CVReg: codeview::RegisterId::DH, .Reg: X86::DH},
196 {.CVReg: codeview::RegisterId::BH, .Reg: X86::BH},
197 {.CVReg: codeview::RegisterId::AX, .Reg: X86::AX},
198 {.CVReg: codeview::RegisterId::CX, .Reg: X86::CX},
199 {.CVReg: codeview::RegisterId::DX, .Reg: X86::DX},
200 {.CVReg: codeview::RegisterId::BX, .Reg: X86::BX},
201 {.CVReg: codeview::RegisterId::SP, .Reg: X86::SP},
202 {.CVReg: codeview::RegisterId::BP, .Reg: X86::BP},
203 {.CVReg: codeview::RegisterId::SI, .Reg: X86::SI},
204 {.CVReg: codeview::RegisterId::DI, .Reg: X86::DI},
205 {.CVReg: codeview::RegisterId::EAX, .Reg: X86::EAX},
206 {.CVReg: codeview::RegisterId::ECX, .Reg: X86::ECX},
207 {.CVReg: codeview::RegisterId::EDX, .Reg: X86::EDX},
208 {.CVReg: codeview::RegisterId::EBX, .Reg: X86::EBX},
209 {.CVReg: codeview::RegisterId::ESP, .Reg: X86::ESP},
210 {.CVReg: codeview::RegisterId::EBP, .Reg: X86::EBP},
211 {.CVReg: codeview::RegisterId::ESI, .Reg: X86::ESI},
212 {.CVReg: codeview::RegisterId::EDI, .Reg: X86::EDI},
213
214 {.CVReg: codeview::RegisterId::EFLAGS, .Reg: X86::EFLAGS},
215
216 {.CVReg: codeview::RegisterId::ST0, .Reg: X86::ST0},
217 {.CVReg: codeview::RegisterId::ST1, .Reg: X86::ST1},
218 {.CVReg: codeview::RegisterId::ST2, .Reg: X86::ST2},
219 {.CVReg: codeview::RegisterId::ST3, .Reg: X86::ST3},
220 {.CVReg: codeview::RegisterId::ST4, .Reg: X86::ST4},
221 {.CVReg: codeview::RegisterId::ST5, .Reg: X86::ST5},
222 {.CVReg: codeview::RegisterId::ST6, .Reg: X86::ST6},
223 {.CVReg: codeview::RegisterId::ST7, .Reg: X86::ST7},
224
225 {.CVReg: codeview::RegisterId::ST0, .Reg: X86::FP0},
226 {.CVReg: codeview::RegisterId::ST1, .Reg: X86::FP1},
227 {.CVReg: codeview::RegisterId::ST2, .Reg: X86::FP2},
228 {.CVReg: codeview::RegisterId::ST3, .Reg: X86::FP3},
229 {.CVReg: codeview::RegisterId::ST4, .Reg: X86::FP4},
230 {.CVReg: codeview::RegisterId::ST5, .Reg: X86::FP5},
231 {.CVReg: codeview::RegisterId::ST6, .Reg: X86::FP6},
232 {.CVReg: codeview::RegisterId::ST7, .Reg: X86::FP7},
233
234 {.CVReg: codeview::RegisterId::MM0, .Reg: X86::MM0},
235 {.CVReg: codeview::RegisterId::MM1, .Reg: X86::MM1},
236 {.CVReg: codeview::RegisterId::MM2, .Reg: X86::MM2},
237 {.CVReg: codeview::RegisterId::MM3, .Reg: X86::MM3},
238 {.CVReg: codeview::RegisterId::MM4, .Reg: X86::MM4},
239 {.CVReg: codeview::RegisterId::MM5, .Reg: X86::MM5},
240 {.CVReg: codeview::RegisterId::MM6, .Reg: X86::MM6},
241 {.CVReg: codeview::RegisterId::MM7, .Reg: X86::MM7},
242
243 {.CVReg: codeview::RegisterId::XMM0, .Reg: X86::XMM0},
244 {.CVReg: codeview::RegisterId::XMM1, .Reg: X86::XMM1},
245 {.CVReg: codeview::RegisterId::XMM2, .Reg: X86::XMM2},
246 {.CVReg: codeview::RegisterId::XMM3, .Reg: X86::XMM3},
247 {.CVReg: codeview::RegisterId::XMM4, .Reg: X86::XMM4},
248 {.CVReg: codeview::RegisterId::XMM5, .Reg: X86::XMM5},
249 {.CVReg: codeview::RegisterId::XMM6, .Reg: X86::XMM6},
250 {.CVReg: codeview::RegisterId::XMM7, .Reg: X86::XMM7},
251
252 {.CVReg: codeview::RegisterId::XMM8, .Reg: X86::XMM8},
253 {.CVReg: codeview::RegisterId::XMM9, .Reg: X86::XMM9},
254 {.CVReg: codeview::RegisterId::XMM10, .Reg: X86::XMM10},
255 {.CVReg: codeview::RegisterId::XMM11, .Reg: X86::XMM11},
256 {.CVReg: codeview::RegisterId::XMM12, .Reg: X86::XMM12},
257 {.CVReg: codeview::RegisterId::XMM13, .Reg: X86::XMM13},
258 {.CVReg: codeview::RegisterId::XMM14, .Reg: X86::XMM14},
259 {.CVReg: codeview::RegisterId::XMM15, .Reg: X86::XMM15},
260
261 {.CVReg: codeview::RegisterId::SIL, .Reg: X86::SIL},
262 {.CVReg: codeview::RegisterId::DIL, .Reg: X86::DIL},
263 {.CVReg: codeview::RegisterId::BPL, .Reg: X86::BPL},
264 {.CVReg: codeview::RegisterId::SPL, .Reg: X86::SPL},
265 {.CVReg: codeview::RegisterId::RAX, .Reg: X86::RAX},
266 {.CVReg: codeview::RegisterId::RBX, .Reg: X86::RBX},
267 {.CVReg: codeview::RegisterId::RCX, .Reg: X86::RCX},
268 {.CVReg: codeview::RegisterId::RDX, .Reg: X86::RDX},
269 {.CVReg: codeview::RegisterId::RSI, .Reg: X86::RSI},
270 {.CVReg: codeview::RegisterId::RDI, .Reg: X86::RDI},
271 {.CVReg: codeview::RegisterId::RBP, .Reg: X86::RBP},
272 {.CVReg: codeview::RegisterId::RSP, .Reg: X86::RSP},
273 {.CVReg: codeview::RegisterId::R8, .Reg: X86::R8},
274 {.CVReg: codeview::RegisterId::R9, .Reg: X86::R9},
275 {.CVReg: codeview::RegisterId::R10, .Reg: X86::R10},
276 {.CVReg: codeview::RegisterId::R11, .Reg: X86::R11},
277 {.CVReg: codeview::RegisterId::R12, .Reg: X86::R12},
278 {.CVReg: codeview::RegisterId::R13, .Reg: X86::R13},
279 {.CVReg: codeview::RegisterId::R14, .Reg: X86::R14},
280 {.CVReg: codeview::RegisterId::R15, .Reg: X86::R15},
281 {.CVReg: codeview::RegisterId::R16, .Reg: X86::R16},
282 {.CVReg: codeview::RegisterId::R17, .Reg: X86::R17},
283 {.CVReg: codeview::RegisterId::R18, .Reg: X86::R18},
284 {.CVReg: codeview::RegisterId::R19, .Reg: X86::R19},
285 {.CVReg: codeview::RegisterId::R20, .Reg: X86::R20},
286 {.CVReg: codeview::RegisterId::R21, .Reg: X86::R21},
287 {.CVReg: codeview::RegisterId::R22, .Reg: X86::R22},
288 {.CVReg: codeview::RegisterId::R23, .Reg: X86::R23},
289 {.CVReg: codeview::RegisterId::R24, .Reg: X86::R24},
290 {.CVReg: codeview::RegisterId::R25, .Reg: X86::R25},
291 {.CVReg: codeview::RegisterId::R26, .Reg: X86::R26},
292 {.CVReg: codeview::RegisterId::R27, .Reg: X86::R27},
293 {.CVReg: codeview::RegisterId::R28, .Reg: X86::R28},
294 {.CVReg: codeview::RegisterId::R29, .Reg: X86::R29},
295 {.CVReg: codeview::RegisterId::R30, .Reg: X86::R30},
296 {.CVReg: codeview::RegisterId::R31, .Reg: X86::R31},
297 {.CVReg: codeview::RegisterId::R8B, .Reg: X86::R8B},
298 {.CVReg: codeview::RegisterId::R9B, .Reg: X86::R9B},
299 {.CVReg: codeview::RegisterId::R10B, .Reg: X86::R10B},
300 {.CVReg: codeview::RegisterId::R11B, .Reg: X86::R11B},
301 {.CVReg: codeview::RegisterId::R12B, .Reg: X86::R12B},
302 {.CVReg: codeview::RegisterId::R13B, .Reg: X86::R13B},
303 {.CVReg: codeview::RegisterId::R14B, .Reg: X86::R14B},
304 {.CVReg: codeview::RegisterId::R15B, .Reg: X86::R15B},
305 {.CVReg: codeview::RegisterId::R16B, .Reg: X86::R16B},
306 {.CVReg: codeview::RegisterId::R17B, .Reg: X86::R17B},
307 {.CVReg: codeview::RegisterId::R18B, .Reg: X86::R18B},
308 {.CVReg: codeview::RegisterId::R19B, .Reg: X86::R19B},
309 {.CVReg: codeview::RegisterId::R20B, .Reg: X86::R20B},
310 {.CVReg: codeview::RegisterId::R21B, .Reg: X86::R21B},
311 {.CVReg: codeview::RegisterId::R22B, .Reg: X86::R22B},
312 {.CVReg: codeview::RegisterId::R23B, .Reg: X86::R23B},
313 {.CVReg: codeview::RegisterId::R24B, .Reg: X86::R24B},
314 {.CVReg: codeview::RegisterId::R25B, .Reg: X86::R25B},
315 {.CVReg: codeview::RegisterId::R26B, .Reg: X86::R26B},
316 {.CVReg: codeview::RegisterId::R27B, .Reg: X86::R27B},
317 {.CVReg: codeview::RegisterId::R28B, .Reg: X86::R28B},
318 {.CVReg: codeview::RegisterId::R29B, .Reg: X86::R29B},
319 {.CVReg: codeview::RegisterId::R30B, .Reg: X86::R30B},
320 {.CVReg: codeview::RegisterId::R31B, .Reg: X86::R31B},
321 {.CVReg: codeview::RegisterId::R8W, .Reg: X86::R8W},
322 {.CVReg: codeview::RegisterId::R9W, .Reg: X86::R9W},
323 {.CVReg: codeview::RegisterId::R10W, .Reg: X86::R10W},
324 {.CVReg: codeview::RegisterId::R11W, .Reg: X86::R11W},
325 {.CVReg: codeview::RegisterId::R12W, .Reg: X86::R12W},
326 {.CVReg: codeview::RegisterId::R13W, .Reg: X86::R13W},
327 {.CVReg: codeview::RegisterId::R14W, .Reg: X86::R14W},
328 {.CVReg: codeview::RegisterId::R15W, .Reg: X86::R15W},
329 {.CVReg: codeview::RegisterId::R16W, .Reg: X86::R16W},
330 {.CVReg: codeview::RegisterId::R17W, .Reg: X86::R17W},
331 {.CVReg: codeview::RegisterId::R18W, .Reg: X86::R18W},
332 {.CVReg: codeview::RegisterId::R19W, .Reg: X86::R19W},
333 {.CVReg: codeview::RegisterId::R20W, .Reg: X86::R20W},
334 {.CVReg: codeview::RegisterId::R21W, .Reg: X86::R21W},
335 {.CVReg: codeview::RegisterId::R22W, .Reg: X86::R22W},
336 {.CVReg: codeview::RegisterId::R23W, .Reg: X86::R23W},
337 {.CVReg: codeview::RegisterId::R24W, .Reg: X86::R24W},
338 {.CVReg: codeview::RegisterId::R25W, .Reg: X86::R25W},
339 {.CVReg: codeview::RegisterId::R26W, .Reg: X86::R26W},
340 {.CVReg: codeview::RegisterId::R27W, .Reg: X86::R27W},
341 {.CVReg: codeview::RegisterId::R28W, .Reg: X86::R28W},
342 {.CVReg: codeview::RegisterId::R29W, .Reg: X86::R29W},
343 {.CVReg: codeview::RegisterId::R30W, .Reg: X86::R30W},
344 {.CVReg: codeview::RegisterId::R31W, .Reg: X86::R31W},
345 {.CVReg: codeview::RegisterId::R8D, .Reg: X86::R8D},
346 {.CVReg: codeview::RegisterId::R9D, .Reg: X86::R9D},
347 {.CVReg: codeview::RegisterId::R10D, .Reg: X86::R10D},
348 {.CVReg: codeview::RegisterId::R11D, .Reg: X86::R11D},
349 {.CVReg: codeview::RegisterId::R12D, .Reg: X86::R12D},
350 {.CVReg: codeview::RegisterId::R13D, .Reg: X86::R13D},
351 {.CVReg: codeview::RegisterId::R14D, .Reg: X86::R14D},
352 {.CVReg: codeview::RegisterId::R15D, .Reg: X86::R15D},
353 {.CVReg: codeview::RegisterId::R16D, .Reg: X86::R16D},
354 {.CVReg: codeview::RegisterId::R17D, .Reg: X86::R17D},
355 {.CVReg: codeview::RegisterId::R18D, .Reg: X86::R18D},
356 {.CVReg: codeview::RegisterId::R19D, .Reg: X86::R19D},
357 {.CVReg: codeview::RegisterId::R20D, .Reg: X86::R20D},
358 {.CVReg: codeview::RegisterId::R21D, .Reg: X86::R21D},
359 {.CVReg: codeview::RegisterId::R22D, .Reg: X86::R22D},
360 {.CVReg: codeview::RegisterId::R23D, .Reg: X86::R23D},
361 {.CVReg: codeview::RegisterId::R24D, .Reg: X86::R24D},
362 {.CVReg: codeview::RegisterId::R25D, .Reg: X86::R25D},
363 {.CVReg: codeview::RegisterId::R26D, .Reg: X86::R26D},
364 {.CVReg: codeview::RegisterId::R27D, .Reg: X86::R27D},
365 {.CVReg: codeview::RegisterId::R28D, .Reg: X86::R28D},
366 {.CVReg: codeview::RegisterId::R29D, .Reg: X86::R29D},
367 {.CVReg: codeview::RegisterId::R30D, .Reg: X86::R30D},
368 {.CVReg: codeview::RegisterId::R31D, .Reg: X86::R31D},
369 {.CVReg: codeview::RegisterId::AMD64_YMM0, .Reg: X86::YMM0},
370 {.CVReg: codeview::RegisterId::AMD64_YMM1, .Reg: X86::YMM1},
371 {.CVReg: codeview::RegisterId::AMD64_YMM2, .Reg: X86::YMM2},
372 {.CVReg: codeview::RegisterId::AMD64_YMM3, .Reg: X86::YMM3},
373 {.CVReg: codeview::RegisterId::AMD64_YMM4, .Reg: X86::YMM4},
374 {.CVReg: codeview::RegisterId::AMD64_YMM5, .Reg: X86::YMM5},
375 {.CVReg: codeview::RegisterId::AMD64_YMM6, .Reg: X86::YMM6},
376 {.CVReg: codeview::RegisterId::AMD64_YMM7, .Reg: X86::YMM7},
377 {.CVReg: codeview::RegisterId::AMD64_YMM8, .Reg: X86::YMM8},
378 {.CVReg: codeview::RegisterId::AMD64_YMM9, .Reg: X86::YMM9},
379 {.CVReg: codeview::RegisterId::AMD64_YMM10, .Reg: X86::YMM10},
380 {.CVReg: codeview::RegisterId::AMD64_YMM11, .Reg: X86::YMM11},
381 {.CVReg: codeview::RegisterId::AMD64_YMM12, .Reg: X86::YMM12},
382 {.CVReg: codeview::RegisterId::AMD64_YMM13, .Reg: X86::YMM13},
383 {.CVReg: codeview::RegisterId::AMD64_YMM14, .Reg: X86::YMM14},
384 {.CVReg: codeview::RegisterId::AMD64_YMM15, .Reg: X86::YMM15},
385 {.CVReg: codeview::RegisterId::AMD64_YMM16, .Reg: X86::YMM16},
386 {.CVReg: codeview::RegisterId::AMD64_YMM17, .Reg: X86::YMM17},
387 {.CVReg: codeview::RegisterId::AMD64_YMM18, .Reg: X86::YMM18},
388 {.CVReg: codeview::RegisterId::AMD64_YMM19, .Reg: X86::YMM19},
389 {.CVReg: codeview::RegisterId::AMD64_YMM20, .Reg: X86::YMM20},
390 {.CVReg: codeview::RegisterId::AMD64_YMM21, .Reg: X86::YMM21},
391 {.CVReg: codeview::RegisterId::AMD64_YMM22, .Reg: X86::YMM22},
392 {.CVReg: codeview::RegisterId::AMD64_YMM23, .Reg: X86::YMM23},
393 {.CVReg: codeview::RegisterId::AMD64_YMM24, .Reg: X86::YMM24},
394 {.CVReg: codeview::RegisterId::AMD64_YMM25, .Reg: X86::YMM25},
395 {.CVReg: codeview::RegisterId::AMD64_YMM26, .Reg: X86::YMM26},
396 {.CVReg: codeview::RegisterId::AMD64_YMM27, .Reg: X86::YMM27},
397 {.CVReg: codeview::RegisterId::AMD64_YMM28, .Reg: X86::YMM28},
398 {.CVReg: codeview::RegisterId::AMD64_YMM29, .Reg: X86::YMM29},
399 {.CVReg: codeview::RegisterId::AMD64_YMM30, .Reg: X86::YMM30},
400 {.CVReg: codeview::RegisterId::AMD64_YMM31, .Reg: X86::YMM31},
401 {.CVReg: codeview::RegisterId::AMD64_ZMM0, .Reg: X86::ZMM0},
402 {.CVReg: codeview::RegisterId::AMD64_ZMM1, .Reg: X86::ZMM1},
403 {.CVReg: codeview::RegisterId::AMD64_ZMM2, .Reg: X86::ZMM2},
404 {.CVReg: codeview::RegisterId::AMD64_ZMM3, .Reg: X86::ZMM3},
405 {.CVReg: codeview::RegisterId::AMD64_ZMM4, .Reg: X86::ZMM4},
406 {.CVReg: codeview::RegisterId::AMD64_ZMM5, .Reg: X86::ZMM5},
407 {.CVReg: codeview::RegisterId::AMD64_ZMM6, .Reg: X86::ZMM6},
408 {.CVReg: codeview::RegisterId::AMD64_ZMM7, .Reg: X86::ZMM7},
409 {.CVReg: codeview::RegisterId::AMD64_ZMM8, .Reg: X86::ZMM8},
410 {.CVReg: codeview::RegisterId::AMD64_ZMM9, .Reg: X86::ZMM9},
411 {.CVReg: codeview::RegisterId::AMD64_ZMM10, .Reg: X86::ZMM10},
412 {.CVReg: codeview::RegisterId::AMD64_ZMM11, .Reg: X86::ZMM11},
413 {.CVReg: codeview::RegisterId::AMD64_ZMM12, .Reg: X86::ZMM12},
414 {.CVReg: codeview::RegisterId::AMD64_ZMM13, .Reg: X86::ZMM13},
415 {.CVReg: codeview::RegisterId::AMD64_ZMM14, .Reg: X86::ZMM14},
416 {.CVReg: codeview::RegisterId::AMD64_ZMM15, .Reg: X86::ZMM15},
417 {.CVReg: codeview::RegisterId::AMD64_ZMM16, .Reg: X86::ZMM16},
418 {.CVReg: codeview::RegisterId::AMD64_ZMM17, .Reg: X86::ZMM17},
419 {.CVReg: codeview::RegisterId::AMD64_ZMM18, .Reg: X86::ZMM18},
420 {.CVReg: codeview::RegisterId::AMD64_ZMM19, .Reg: X86::ZMM19},
421 {.CVReg: codeview::RegisterId::AMD64_ZMM20, .Reg: X86::ZMM20},
422 {.CVReg: codeview::RegisterId::AMD64_ZMM21, .Reg: X86::ZMM21},
423 {.CVReg: codeview::RegisterId::AMD64_ZMM22, .Reg: X86::ZMM22},
424 {.CVReg: codeview::RegisterId::AMD64_ZMM23, .Reg: X86::ZMM23},
425 {.CVReg: codeview::RegisterId::AMD64_ZMM24, .Reg: X86::ZMM24},
426 {.CVReg: codeview::RegisterId::AMD64_ZMM25, .Reg: X86::ZMM25},
427 {.CVReg: codeview::RegisterId::AMD64_ZMM26, .Reg: X86::ZMM26},
428 {.CVReg: codeview::RegisterId::AMD64_ZMM27, .Reg: X86::ZMM27},
429 {.CVReg: codeview::RegisterId::AMD64_ZMM28, .Reg: X86::ZMM28},
430 {.CVReg: codeview::RegisterId::AMD64_ZMM29, .Reg: X86::ZMM29},
431 {.CVReg: codeview::RegisterId::AMD64_ZMM30, .Reg: X86::ZMM30},
432 {.CVReg: codeview::RegisterId::AMD64_ZMM31, .Reg: X86::ZMM31},
433 {.CVReg: codeview::RegisterId::AMD64_K0, .Reg: X86::K0},
434 {.CVReg: codeview::RegisterId::AMD64_K1, .Reg: X86::K1},
435 {.CVReg: codeview::RegisterId::AMD64_K2, .Reg: X86::K2},
436 {.CVReg: codeview::RegisterId::AMD64_K3, .Reg: X86::K3},
437 {.CVReg: codeview::RegisterId::AMD64_K4, .Reg: X86::K4},
438 {.CVReg: codeview::RegisterId::AMD64_K5, .Reg: X86::K5},
439 {.CVReg: codeview::RegisterId::AMD64_K6, .Reg: X86::K6},
440 {.CVReg: codeview::RegisterId::AMD64_K7, .Reg: X86::K7},
441 {.CVReg: codeview::RegisterId::AMD64_XMM16, .Reg: X86::XMM16},
442 {.CVReg: codeview::RegisterId::AMD64_XMM17, .Reg: X86::XMM17},
443 {.CVReg: codeview::RegisterId::AMD64_XMM18, .Reg: X86::XMM18},
444 {.CVReg: codeview::RegisterId::AMD64_XMM19, .Reg: X86::XMM19},
445 {.CVReg: codeview::RegisterId::AMD64_XMM20, .Reg: X86::XMM20},
446 {.CVReg: codeview::RegisterId::AMD64_XMM21, .Reg: X86::XMM21},
447 {.CVReg: codeview::RegisterId::AMD64_XMM22, .Reg: X86::XMM22},
448 {.CVReg: codeview::RegisterId::AMD64_XMM23, .Reg: X86::XMM23},
449 {.CVReg: codeview::RegisterId::AMD64_XMM24, .Reg: X86::XMM24},
450 {.CVReg: codeview::RegisterId::AMD64_XMM25, .Reg: X86::XMM25},
451 {.CVReg: codeview::RegisterId::AMD64_XMM26, .Reg: X86::XMM26},
452 {.CVReg: codeview::RegisterId::AMD64_XMM27, .Reg: X86::XMM27},
453 {.CVReg: codeview::RegisterId::AMD64_XMM28, .Reg: X86::XMM28},
454 {.CVReg: codeview::RegisterId::AMD64_XMM29, .Reg: X86::XMM29},
455 {.CVReg: codeview::RegisterId::AMD64_XMM30, .Reg: X86::XMM30},
456 {.CVReg: codeview::RegisterId::AMD64_XMM31, .Reg: X86::XMM31},
457
458 };
459 for (const auto &I : RegMap)
460 MRI->mapLLVMRegToCVReg(LLVMReg: I.Reg, CVReg: static_cast<int>(I.CVReg));
461}
462
463MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
464 StringRef CPU, StringRef FS) {
465 std::string ArchFS = X86_MC::ParseX86Triple(TT);
466 assert(!ArchFS.empty() && "Failed to parse X86 triple");
467 if (!FS.empty())
468 ArchFS = (Twine(ArchFS) + "," + FS).str();
469
470 if (CPU.empty())
471 CPU = "generic";
472
473 return createX86MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS: ArchFS);
474}
475
476static MCInstrInfo *createX86MCInstrInfo() {
477 MCInstrInfo *X = new MCInstrInfo();
478 InitX86MCInstrInfo(II: X);
479 return X;
480}
481
482static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
483 unsigned RA = TT.isX86_64() ? X86::RIP // Should have dwarf #16.
484 : X86::EIP; // Should have dwarf #8.
485
486 MCRegisterInfo *X = new MCRegisterInfo();
487 InitX86MCRegisterInfo(RI: X, RA, DwarfFlavour: X86_MC::getDwarfRegFlavour(TT, isEH: false),
488 EHFlavour: X86_MC::getDwarfRegFlavour(TT, isEH: true), PC: RA);
489 X86_MC::initLLVMToSEHAndCVRegMapping(MRI: X);
490 return X;
491}
492
493static void populateReservedIdentifiers(MCAsmInfo &MAI,
494 const MCRegisterInfo &MRI) {
495 auto &Set = MAI.getReservedIdentifiers();
496 // Register names: `call rsi` is misassembled as an indirect call. Use the
497 // Intel printer's table directly — it's the lowercase asm name in stable
498 // storage. MRI::getName() returns the uppercase enum name and would need
499 // an extra .lower() heap allocation per entry.
500 for (unsigned i = 1, e = MRI.getNumRegs(); i < e; ++i)
501 if (const char *Name = X86IntelInstPrinter::getRegisterName(Reg: i))
502 if (Name[0])
503 Set.insert(V: CachedHashStringRef(Name));
504 // Keywords that GAS Intel syntax misparses as constants, modifiers, or
505 // pseudo-registers instead of symbol references (e.g., `call byte` calls
506 // address 1, not symbol "byte"; `call flat` errors out).
507 for (StringRef KW : {"byte", "word", "dword", "fword", "qword", "mmword",
508 "tbyte", "oword", "xmmword", "ymmword", "zmmword",
509 "offset", "flat", "near", "far", "short"})
510 Set.insert(V: CachedHashStringRef(KW));
511 // Operator keywords parsed by GAS/X86AsmParser in Intel mode.
512 for (StringRef KW : {"and", "eq", "ge", "gt", "le", "lt", "mod", "ne", "not",
513 "or", "shl", "shr", "xor"})
514 Set.insert(V: CachedHashStringRef(KW));
515}
516
517static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
518 const Triple &TheTriple,
519 const MCTargetOptions &Options) {
520 bool is64Bit = TheTriple.isX86_64();
521
522 MCAsmInfo *MAI;
523 if (TheTriple.isOSBinFormatMachO()) {
524 if (is64Bit)
525 MAI = new X86_64MCAsmInfoDarwin(TheTriple, Options);
526 else
527 MAI = new X86MCAsmInfoDarwin(TheTriple, Options);
528 } else if (TheTriple.isOSBinFormatELF()) {
529 // Force the use of an ELF container.
530 MAI = new X86ELFMCAsmInfo(TheTriple, Options);
531 } else if (TheTriple.isWindowsMSVCEnvironment() ||
532 TheTriple.isWindowsCoreCLREnvironment() || TheTriple.isUEFI()) {
533 if (Options.getAssemblyLanguage().equals_insensitive(RHS: "masm"))
534 MAI = new X86MCAsmInfoMicrosoftMASM(TheTriple, Options);
535 else
536 MAI = new X86MCAsmInfoMicrosoft(TheTriple, Options);
537 } else if (TheTriple.isOSCygMing() ||
538 TheTriple.isWindowsItaniumEnvironment()) {
539 MAI = new X86MCAsmInfoGNUCOFF(TheTriple, Options);
540 } else {
541 // The default is ELF.
542 MAI = new X86ELFMCAsmInfo(TheTriple, Options);
543 }
544
545 // Only Intel-syntax output needs to avoid register/keyword collisions; AT&T
546 // disambiguates registers with '%' and doesn't treat `byte`, `ptr`, etc. as
547 // keywords.
548 if (MAI->getOutputAssemblerDialect() != 0)
549 populateReservedIdentifiers(MAI&: *MAI, MRI);
550
551 // Initialize initial frame state.
552 // Calculate amount of bytes used for return address storing
553 int stackGrowth = is64Bit ? -8 : -4;
554
555 // Initial state of the frame pointer is esp+stackGrowth.
556 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
557 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
558 L: nullptr, Register: MRI.getDwarfRegNum(Reg: StackPtr, isEH: true), Offset: -stackGrowth);
559 MAI->addInitialFrameState(Inst);
560
561 // Add return address to move list
562 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
563 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
564 L: nullptr, Register: MRI.getDwarfRegNum(Reg: InstPtr, isEH: true), Offset: stackGrowth);
565 MAI->addInitialFrameState(Inst: Inst2);
566
567 return MAI;
568}
569
570static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
571 unsigned SyntaxVariant,
572 const MCAsmInfo &MAI,
573 const MCInstrInfo &MII,
574 const MCRegisterInfo &MRI) {
575 if (SyntaxVariant == 0)
576 return new X86ATTInstPrinter(MAI, MII, MRI);
577 if (SyntaxVariant == 1)
578 return new X86IntelInstPrinter(MAI, MII, MRI);
579 return nullptr;
580}
581
582static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
583 MCContext &Ctx) {
584 // Default to the stock relocation info.
585 return llvm::createMCRelocationInfo(TT: TheTriple, Ctx);
586}
587
588namespace llvm {
589namespace X86_MC {
590
591class X86MCInstrAnalysis : public MCInstrAnalysis {
592 X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete;
593 X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete;
594 ~X86MCInstrAnalysis() override = default;
595
596public:
597 X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {}
598
599#define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
600#include "X86GenSubtargetInfo.inc"
601
602 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
603 APInt &Mask) const override;
604 std::vector<std::pair<uint64_t, uint64_t>>
605 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
606 const MCSubtargetInfo &STI) const override;
607
608 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
609 uint64_t &Target) const override;
610 std::optional<uint64_t>
611 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,
612 uint64_t Addr, uint64_t Size) const override;
613 std::optional<uint64_t>
614 getMemoryOperandRelocationOffset(const MCInst &Inst,
615 uint64_t Size) const override;
616};
617
618#define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
619#include "X86GenSubtargetInfo.inc"
620
621bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
622 const MCInst &Inst,
623 APInt &Mask) const {
624 const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode());
625 unsigned NumDefs = Desc.getNumDefs();
626 unsigned NumImplicitDefs = Desc.implicit_defs().size();
627 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
628 "Unexpected number of bits in the mask!");
629
630 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
631 bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX;
632 bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP;
633
634 const MCRegisterClass &GR32RC = MRI.getRegClass(i: X86::GR32RegClassID);
635 const MCRegisterClass &VR128XRC = MRI.getRegClass(i: X86::VR128XRegClassID);
636 const MCRegisterClass &VR256XRC = MRI.getRegClass(i: X86::VR256XRegClassID);
637
638 auto ClearsSuperReg = [&](MCRegister RegID) {
639 // On X86-64, a general purpose integer register is viewed as a 64-bit
640 // register internal to the processor.
641 // An update to the lower 32 bits of a 64 bit integer register is
642 // architecturally defined to zero extend the upper 32 bits.
643 if (GR32RC.contains(Reg: RegID))
644 return true;
645
646 // Early exit if this instruction has no vex/evex/xop prefix.
647 if (!HasEVEX && !HasVEX && !HasXOP)
648 return false;
649
650 // All VEX and EVEX encoded instructions are defined to zero the high bits
651 // of the destination register up to VLMAX (i.e. the maximum vector register
652 // width pertaining to the instruction).
653 // We assume the same behavior for XOP instructions too.
654 return VR128XRC.contains(Reg: RegID) || VR256XRC.contains(Reg: RegID);
655 };
656
657 Mask.clearAllBits();
658 for (unsigned I = 0, E = NumDefs; I < E; ++I) {
659 const MCOperand &Op = Inst.getOperand(i: I);
660 if (ClearsSuperReg(Op.getReg()))
661 Mask.setBit(I);
662 }
663
664 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
665 const MCPhysReg Reg = Desc.implicit_defs()[I];
666 if (ClearsSuperReg(Reg))
667 Mask.setBit(NumDefs + I);
668 }
669
670 return Mask.getBoolValue();
671}
672
673static std::vector<std::pair<uint64_t, uint64_t>>
674findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {
675 // Do a lightweight parsing of PLT entries.
676 std::vector<std::pair<uint64_t, uint64_t>> Result;
677 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
678 // Recognize a jmp.
679 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) {
680 // The jmp instruction at the beginning of each PLT entry jumps to the
681 // address of the base of the .got.plt section plus the immediate.
682 // Set the 1 << 32 bit to let ELFObjectFileBase::getPltEntries convert the
683 // offset to an address. Imm may be a negative int32_t if the GOT entry is
684 // in .got.
685 uint32_t Imm = support::endian::read32le(P: PltContents.data() + Byte + 2);
686 Result.emplace_back(args: PltSectionVA + Byte, args: Imm | (uint64_t(1) << 32));
687 Byte += 6;
688 } else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
689 // The jmp instruction at the beginning of each PLT entry jumps to the
690 // immediate.
691 uint32_t Imm = support::endian::read32le(P: PltContents.data() + Byte + 2);
692 Result.push_back(x: std::make_pair(x: PltSectionVA + Byte, y&: Imm));
693 Byte += 6;
694 } else
695 Byte++;
696 }
697 return Result;
698}
699
700static std::vector<std::pair<uint64_t, uint64_t>>
701findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {
702 // Do a lightweight parsing of PLT entries.
703 std::vector<std::pair<uint64_t, uint64_t>> Result;
704 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
705 // Recognize a jmp.
706 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
707 // The jmp instruction at the beginning of each PLT entry jumps to the
708 // address of the next instruction plus the immediate.
709 uint32_t Imm = support::endian::read32le(P: PltContents.data() + Byte + 2);
710 Result.push_back(
711 x: std::make_pair(x: PltSectionVA + Byte, y: PltSectionVA + Byte + 6 + Imm));
712 Byte += 6;
713 } else
714 Byte++;
715 }
716 return Result;
717}
718
719std::vector<std::pair<uint64_t, uint64_t>>
720X86MCInstrAnalysis::findPltEntries(uint64_t PltSectionVA,
721 ArrayRef<uint8_t> PltContents,
722 const MCSubtargetInfo &STI) const {
723 const Triple &TargetTriple = STI.getTargetTriple();
724 switch (TargetTriple.getArch()) {
725 case Triple::x86:
726 return findX86PltEntries(PltSectionVA, PltContents);
727 case Triple::x86_64:
728 return findX86_64PltEntries(PltSectionVA, PltContents);
729 default:
730 return {};
731 }
732}
733
734bool X86MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
735 uint64_t Size, uint64_t &Target) const {
736 if (Inst.getNumOperands() == 0 ||
737 Info->get(Opcode: Inst.getOpcode()).operands()[0].OperandType !=
738 MCOI::OPERAND_PCREL)
739 return false;
740 Target = Addr + Size + Inst.getOperand(i: 0).getImm();
741 return true;
742}
743
744std::optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress(
745 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
746 uint64_t Size) const {
747 const MCInstrDesc &MCID = Info->get(Opcode: Inst.getOpcode());
748 int MemOpStart = X86II::getMemoryOperandIdx(Desc: MCID);
749 if (MemOpStart == -1)
750 return std::nullopt;
751
752 const MCOperand &SegReg = Inst.getOperand(i: MemOpStart + X86::AddrSegmentReg);
753 const MCOperand &BaseReg = Inst.getOperand(i: MemOpStart + X86::AddrBaseReg);
754 const MCOperand &IndexReg = Inst.getOperand(i: MemOpStart + X86::AddrIndexReg);
755 const MCOperand &ScaleAmt = Inst.getOperand(i: MemOpStart + X86::AddrScaleAmt);
756 const MCOperand &Disp = Inst.getOperand(i: MemOpStart + X86::AddrDisp);
757 if (SegReg.getReg() || IndexReg.getReg() || ScaleAmt.getImm() != 1 ||
758 !Disp.isImm())
759 return std::nullopt;
760
761 // RIP-relative addressing.
762 if (BaseReg.getReg() == X86::RIP)
763 return Addr + Size + Disp.getImm();
764
765 return std::nullopt;
766}
767
768std::optional<uint64_t>
769X86MCInstrAnalysis::getMemoryOperandRelocationOffset(const MCInst &Inst,
770 uint64_t Size) const {
771 if (Inst.getOpcode() != X86::LEA64r)
772 return std::nullopt;
773 const MCInstrDesc &MCID = Info->get(Opcode: Inst.getOpcode());
774 int MemOpStart = X86II::getMemoryOperandIdx(Desc: MCID);
775 if (MemOpStart == -1)
776 return std::nullopt;
777 const MCOperand &SegReg = Inst.getOperand(i: MemOpStart + X86::AddrSegmentReg);
778 const MCOperand &BaseReg = Inst.getOperand(i: MemOpStart + X86::AddrBaseReg);
779 const MCOperand &IndexReg = Inst.getOperand(i: MemOpStart + X86::AddrIndexReg);
780 const MCOperand &ScaleAmt = Inst.getOperand(i: MemOpStart + X86::AddrScaleAmt);
781 const MCOperand &Disp = Inst.getOperand(i: MemOpStart + X86::AddrDisp);
782 // Must be a simple rip-relative address.
783 if (BaseReg.getReg() != X86::RIP || SegReg.getReg() || IndexReg.getReg() ||
784 ScaleAmt.getImm() != 1 || !Disp.isImm())
785 return std::nullopt;
786 // rip-relative ModR/M immediate is 32 bits.
787 assert(Size > 4 && "invalid instruction size for rip-relative lea");
788 return Size - 4;
789}
790
791} // end of namespace X86_MC
792
793} // end of namespace llvm
794
795static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
796 return new X86_MC::X86MCInstrAnalysis(Info);
797}
798
799static MCLFIRewriter *
800createX86MCLFIRewriter(MCContext &Ctx,
801 std::unique_ptr<MCRegisterInfo> &&RegInfo,
802 std::unique_ptr<MCInstrInfo> &&InstInfo) {
803 return new X86::X86MCLFIRewriter(Ctx, std::move(RegInfo),
804 std::move(InstInfo));
805}
806
807// Force static initialization.
808extern "C" LLVM_C_ABI void LLVMInitializeX86TargetMC() {
809 static opt::RegisterLibraryOptions<X86MCOptions> O;
810 for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
811 // Register the MC asm info.
812 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
813
814 // Register the MC instruction info.
815 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createX86MCInstrInfo);
816
817 // Register the MC register info.
818 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createX86MCRegisterInfo);
819
820 // Register the MC subtarget info.
821 TargetRegistry::RegisterMCSubtargetInfo(T&: *T,
822 Fn: X86_MC::createX86MCSubtargetInfo);
823
824 // Register the MC instruction analyzer.
825 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createX86MCInstrAnalysis);
826
827 // Register the code emitter.
828 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createX86MCCodeEmitter);
829
830 // Register the LFI rewriter.
831 TargetRegistry::RegisterMCLFIRewriter(T&: *T, Fn: createX86MCLFIRewriter);
832
833 // Register the obj target streamer.
834 TargetRegistry::RegisterObjectTargetStreamer(T&: *T,
835 Fn: createX86ObjectTargetStreamer);
836
837 // Register the asm target streamer.
838 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createX86AsmTargetStreamer);
839
840 // Register the null streamer.
841 TargetRegistry::RegisterNullTargetStreamer(T&: *T, Fn: createX86NullTargetStreamer);
842
843 TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createX86WinCOFFStreamer);
844 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createX86ELFStreamer);
845
846 // Register the MCInstPrinter.
847 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createX86MCInstPrinter);
848
849 // Register the MC relocation info.
850 TargetRegistry::RegisterMCRelocationInfo(T&: *T, Fn: createX86MCRelocationInfo);
851 }
852
853 // Register the asm backend.
854 TargetRegistry::RegisterMCAsmBackend(T&: getTheX86_32Target(),
855 Fn: createX86_32AsmBackend);
856 TargetRegistry::RegisterMCAsmBackend(T&: getTheX86_64Target(),
857 Fn: createX86_64AsmBackend);
858}
859
860MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size,
861 bool High) {
862#define DEFAULT_NOREG \
863 default: \
864 return X86::NoRegister;
865#define SUB_SUPER(R1, R2, R3, R4, R) \
866 case X86::R1: \
867 case X86::R2: \
868 case X86::R3: \
869 case X86::R4: \
870 return X86::R;
871#define A_SUB_SUPER(R) \
872 case X86::AH: \
873 SUB_SUPER(AL, AX, EAX, RAX, R)
874#define D_SUB_SUPER(R) \
875 case X86::DH: \
876 SUB_SUPER(DL, DX, EDX, RDX, R)
877#define C_SUB_SUPER(R) \
878 case X86::CH: \
879 SUB_SUPER(CL, CX, ECX, RCX, R)
880#define B_SUB_SUPER(R) \
881 case X86::BH: \
882 SUB_SUPER(BL, BX, EBX, RBX, R)
883#define SI_SUB_SUPER(R) SUB_SUPER(SIL, SI, ESI, RSI, R)
884#define DI_SUB_SUPER(R) SUB_SUPER(DIL, DI, EDI, RDI, R)
885#define BP_SUB_SUPER(R) SUB_SUPER(BPL, BP, EBP, RBP, R)
886#define SP_SUB_SUPER(R) SUB_SUPER(SPL, SP, ESP, RSP, R)
887#define NO_SUB_SUPER(NO, REG) \
888 SUB_SUPER(R##NO##B, R##NO##W, R##NO##D, R##NO, REG)
889#define NO_SUB_SUPER_B(NO) NO_SUB_SUPER(NO, R##NO##B)
890#define NO_SUB_SUPER_W(NO) NO_SUB_SUPER(NO, R##NO##W)
891#define NO_SUB_SUPER_D(NO) NO_SUB_SUPER(NO, R##NO##D)
892#define NO_SUB_SUPER_Q(NO) NO_SUB_SUPER(NO, R##NO)
893 switch (Size) {
894 default:
895 llvm_unreachable("illegal register size");
896 case 8:
897 if (High) {
898 switch (Reg.id()) {
899 DEFAULT_NOREG
900 A_SUB_SUPER(AH)
901 D_SUB_SUPER(DH)
902 C_SUB_SUPER(CH)
903 B_SUB_SUPER(BH)
904 }
905 } else {
906 switch (Reg.id()) {
907 DEFAULT_NOREG
908 A_SUB_SUPER(AL)
909 D_SUB_SUPER(DL)
910 C_SUB_SUPER(CL)
911 B_SUB_SUPER(BL)
912 SI_SUB_SUPER(SIL)
913 DI_SUB_SUPER(DIL)
914 BP_SUB_SUPER(BPL)
915 SP_SUB_SUPER(SPL)
916 NO_SUB_SUPER_B(8)
917 NO_SUB_SUPER_B(9)
918 NO_SUB_SUPER_B(10)
919 NO_SUB_SUPER_B(11)
920 NO_SUB_SUPER_B(12)
921 NO_SUB_SUPER_B(13)
922 NO_SUB_SUPER_B(14)
923 NO_SUB_SUPER_B(15)
924 NO_SUB_SUPER_B(16)
925 NO_SUB_SUPER_B(17)
926 NO_SUB_SUPER_B(18)
927 NO_SUB_SUPER_B(19)
928 NO_SUB_SUPER_B(20)
929 NO_SUB_SUPER_B(21)
930 NO_SUB_SUPER_B(22)
931 NO_SUB_SUPER_B(23)
932 NO_SUB_SUPER_B(24)
933 NO_SUB_SUPER_B(25)
934 NO_SUB_SUPER_B(26)
935 NO_SUB_SUPER_B(27)
936 NO_SUB_SUPER_B(28)
937 NO_SUB_SUPER_B(29)
938 NO_SUB_SUPER_B(30)
939 NO_SUB_SUPER_B(31)
940 }
941 }
942 case 16:
943 switch (Reg.id()) {
944 DEFAULT_NOREG
945 A_SUB_SUPER(AX)
946 D_SUB_SUPER(DX)
947 C_SUB_SUPER(CX)
948 B_SUB_SUPER(BX)
949 SI_SUB_SUPER(SI)
950 DI_SUB_SUPER(DI)
951 BP_SUB_SUPER(BP)
952 SP_SUB_SUPER(SP)
953 NO_SUB_SUPER_W(8)
954 NO_SUB_SUPER_W(9)
955 NO_SUB_SUPER_W(10)
956 NO_SUB_SUPER_W(11)
957 NO_SUB_SUPER_W(12)
958 NO_SUB_SUPER_W(13)
959 NO_SUB_SUPER_W(14)
960 NO_SUB_SUPER_W(15)
961 NO_SUB_SUPER_W(16)
962 NO_SUB_SUPER_W(17)
963 NO_SUB_SUPER_W(18)
964 NO_SUB_SUPER_W(19)
965 NO_SUB_SUPER_W(20)
966 NO_SUB_SUPER_W(21)
967 NO_SUB_SUPER_W(22)
968 NO_SUB_SUPER_W(23)
969 NO_SUB_SUPER_W(24)
970 NO_SUB_SUPER_W(25)
971 NO_SUB_SUPER_W(26)
972 NO_SUB_SUPER_W(27)
973 NO_SUB_SUPER_W(28)
974 NO_SUB_SUPER_W(29)
975 NO_SUB_SUPER_W(30)
976 NO_SUB_SUPER_W(31)
977 }
978 case 32:
979 switch (Reg.id()) {
980 DEFAULT_NOREG
981 A_SUB_SUPER(EAX)
982 D_SUB_SUPER(EDX)
983 C_SUB_SUPER(ECX)
984 B_SUB_SUPER(EBX)
985 SI_SUB_SUPER(ESI)
986 DI_SUB_SUPER(EDI)
987 BP_SUB_SUPER(EBP)
988 SP_SUB_SUPER(ESP)
989 NO_SUB_SUPER_D(8)
990 NO_SUB_SUPER_D(9)
991 NO_SUB_SUPER_D(10)
992 NO_SUB_SUPER_D(11)
993 NO_SUB_SUPER_D(12)
994 NO_SUB_SUPER_D(13)
995 NO_SUB_SUPER_D(14)
996 NO_SUB_SUPER_D(15)
997 NO_SUB_SUPER_D(16)
998 NO_SUB_SUPER_D(17)
999 NO_SUB_SUPER_D(18)
1000 NO_SUB_SUPER_D(19)
1001 NO_SUB_SUPER_D(20)
1002 NO_SUB_SUPER_D(21)
1003 NO_SUB_SUPER_D(22)
1004 NO_SUB_SUPER_D(23)
1005 NO_SUB_SUPER_D(24)
1006 NO_SUB_SUPER_D(25)
1007 NO_SUB_SUPER_D(26)
1008 NO_SUB_SUPER_D(27)
1009 NO_SUB_SUPER_D(28)
1010 NO_SUB_SUPER_D(29)
1011 NO_SUB_SUPER_D(30)
1012 NO_SUB_SUPER_D(31)
1013 }
1014 case 64:
1015 switch (Reg.id()) {
1016 DEFAULT_NOREG
1017 A_SUB_SUPER(RAX)
1018 D_SUB_SUPER(RDX)
1019 C_SUB_SUPER(RCX)
1020 B_SUB_SUPER(RBX)
1021 SI_SUB_SUPER(RSI)
1022 DI_SUB_SUPER(RDI)
1023 BP_SUB_SUPER(RBP)
1024 SP_SUB_SUPER(RSP)
1025 NO_SUB_SUPER_Q(8)
1026 NO_SUB_SUPER_Q(9)
1027 NO_SUB_SUPER_Q(10)
1028 NO_SUB_SUPER_Q(11)
1029 NO_SUB_SUPER_Q(12)
1030 NO_SUB_SUPER_Q(13)
1031 NO_SUB_SUPER_Q(14)
1032 NO_SUB_SUPER_Q(15)
1033 NO_SUB_SUPER_Q(16)
1034 NO_SUB_SUPER_Q(17)
1035 NO_SUB_SUPER_Q(18)
1036 NO_SUB_SUPER_Q(19)
1037 NO_SUB_SUPER_Q(20)
1038 NO_SUB_SUPER_Q(21)
1039 NO_SUB_SUPER_Q(22)
1040 NO_SUB_SUPER_Q(23)
1041 NO_SUB_SUPER_Q(24)
1042 NO_SUB_SUPER_Q(25)
1043 NO_SUB_SUPER_Q(26)
1044 NO_SUB_SUPER_Q(27)
1045 NO_SUB_SUPER_Q(28)
1046 NO_SUB_SUPER_Q(29)
1047 NO_SUB_SUPER_Q(30)
1048 NO_SUB_SUPER_Q(31)
1049 }
1050 }
1051}
1052