1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides X86 specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86MCTargetDesc.h"
14#include "TargetInfo/X86TargetInfo.h"
15#include "X86ATTInstPrinter.h"
16#include "X86BaseInfo.h"
17#include "X86IntelInstPrinter.h"
18#include "X86MCAsmInfo.h"
19#include "X86TargetStreamer.h"
20#include "llvm-c/Visibility.h"
21#include "llvm/ADT/APInt.h"
22#include "llvm/DebugInfo/CodeView/CodeView.h"
23#include "llvm/MC/MCDwarf.h"
24#include "llvm/MC/MCInstrAnalysis.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCRegisterInfo.h"
27#include "llvm/MC/MCStreamer.h"
28#include "llvm/MC/MCSubtargetInfo.h"
29#include "llvm/MC/TargetRegistry.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/TargetParser/Host.h"
32#include "llvm/TargetParser/Triple.h"
33
34using namespace llvm;
35
36#define GET_REGINFO_MC_DESC
37#include "X86GenRegisterInfo.inc"
38
39#define GET_INSTRINFO_MC_DESC
40#define GET_INSTRINFO_MC_HELPERS
41#define ENABLE_INSTR_PREDICATE_VERIFIER
42#include "X86GenInstrInfo.inc"
43
44#define GET_SUBTARGETINFO_MC_DESC
45#include "X86GenSubtargetInfo.inc"
46
47std::string X86_MC::ParseX86Triple(const Triple &TT) {
48 std::string FS;
49 // SSE2 should default to enabled in 64-bit mode, but can be turned off
50 // explicitly.
51 if (TT.isX86_64())
52 FS = "+64bit-mode,-32bit-mode,-16bit-mode,+sse2";
53 else if (TT.getEnvironment() != Triple::CODE16)
54 FS = "-64bit-mode,+32bit-mode,-16bit-mode";
55 else
56 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
57
58 if (TT.isX32())
59 FS += ",+x32";
60
61 return FS;
62}
63
64unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
65 if (TT.isX86_64())
66 return DWARFFlavour::X86_64;
67
68 if (TT.isOSDarwin())
69 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
70 if (TT.isOSCygMing())
71 // Unsupported by now, just quick fallback
72 return DWARFFlavour::X86_32_Generic;
73 return DWARFFlavour::X86_32_Generic;
74}
75
76bool X86_MC::hasLockPrefix(const MCInst &MI) {
77 return MI.getFlags() & X86::IP_HAS_LOCK;
78}
79
80static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) {
81 const MCOperand &Base = MI.getOperand(i: Op + X86::AddrBaseReg);
82 const MCOperand &Index = MI.getOperand(i: Op + X86::AddrIndexReg);
83 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID];
84
85 return (Base.isReg() && Base.getReg() && RC.contains(Reg: Base.getReg())) ||
86 (Index.isReg() && Index.getReg() && RC.contains(Reg: Index.getReg()));
87}
88
89bool X86_MC::is16BitMemOperand(const MCInst &MI, unsigned Op,
90 const MCSubtargetInfo &STI) {
91 const MCOperand &Base = MI.getOperand(i: Op + X86::AddrBaseReg);
92 const MCOperand &Index = MI.getOperand(i: Op + X86::AddrIndexReg);
93
94 if (STI.hasFeature(Feature: X86::Is16Bit) && Base.isReg() && !Base.getReg() &&
95 Index.isReg() && !Index.getReg())
96 return true;
97 return isMemOperand(MI, Op, RegClassID: X86::GR16RegClassID);
98}
99
100bool X86_MC::is32BitMemOperand(const MCInst &MI, unsigned Op) {
101 const MCOperand &Base = MI.getOperand(i: Op + X86::AddrBaseReg);
102 const MCOperand &Index = MI.getOperand(i: Op + X86::AddrIndexReg);
103 if (Base.isReg() && Base.getReg() == X86::EIP) {
104 assert(Index.isReg() && !Index.getReg() && "Invalid eip-based address");
105 return true;
106 }
107 if (Index.isReg() && Index.getReg() == X86::EIZ)
108 return true;
109 return isMemOperand(MI, Op, RegClassID: X86::GR32RegClassID);
110}
111
112#ifndef NDEBUG
113bool X86_MC::is64BitMemOperand(const MCInst &MI, unsigned Op) {
114 return isMemOperand(MI, Op, X86::GR64RegClassID);
115}
116#endif
117
118bool X86_MC::needsAddressSizeOverride(const MCInst &MI,
119 const MCSubtargetInfo &STI,
120 int MemoryOperand, uint64_t TSFlags) {
121 uint64_t AdSize = TSFlags & X86II::AdSizeMask;
122 bool Is16BitMode = STI.hasFeature(Feature: X86::Is16Bit);
123 bool Is32BitMode = STI.hasFeature(Feature: X86::Is32Bit);
124 bool Is64BitMode = STI.hasFeature(Feature: X86::Is64Bit);
125 if ((Is16BitMode && AdSize == X86II::AdSize32) ||
126 (Is32BitMode && AdSize == X86II::AdSize16) ||
127 (Is64BitMode && AdSize == X86II::AdSize32))
128 return true;
129 uint64_t Form = TSFlags & X86II::FormMask;
130 switch (Form) {
131 default:
132 break;
133 case X86II::RawFrmDstSrc: {
134 MCRegister siReg = MI.getOperand(i: 1).getReg();
135 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||
136 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||
137 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
138 "SI and DI register sizes do not match");
139 return (!Is32BitMode && siReg == X86::ESI) ||
140 (Is32BitMode && siReg == X86::SI);
141 }
142 case X86II::RawFrmSrc: {
143 MCRegister siReg = MI.getOperand(i: 0).getReg();
144 return (!Is32BitMode && siReg == X86::ESI) ||
145 (Is32BitMode && siReg == X86::SI);
146 }
147 case X86II::RawFrmDst: {
148 MCRegister siReg = MI.getOperand(i: 0).getReg();
149 return (!Is32BitMode && siReg == X86::EDI) ||
150 (Is32BitMode && siReg == X86::DI);
151 }
152 }
153
154 // Determine where the memory operand starts, if present.
155 if (MemoryOperand < 0)
156 return false;
157
158 if (STI.hasFeature(Feature: X86::Is64Bit)) {
159 assert(!is16BitMemOperand(MI, MemoryOperand, STI));
160 return is32BitMemOperand(MI, Op: MemoryOperand);
161 }
162 if (STI.hasFeature(Feature: X86::Is32Bit)) {
163 assert(!is64BitMemOperand(MI, MemoryOperand));
164 return is16BitMemOperand(MI, Op: MemoryOperand, STI);
165 }
166 assert(STI.hasFeature(X86::Is16Bit));
167 assert(!is64BitMemOperand(MI, MemoryOperand));
168 return !is16BitMemOperand(MI, Op: MemoryOperand, STI);
169}
170
171void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
172 // FIXME: TableGen these.
173 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
174 unsigned SEH = MRI->getEncodingValue(Reg);
175 MRI->mapLLVMRegToSEHReg(LLVMReg: Reg, SEHReg: SEH);
176 }
177
178 // Mapping from CodeView to MC register id.
179 static const struct {
180 codeview::RegisterId CVReg;
181 MCPhysReg Reg;
182 } RegMap[] = {
183 {.CVReg: codeview::RegisterId::AL, .Reg: X86::AL},
184 {.CVReg: codeview::RegisterId::CL, .Reg: X86::CL},
185 {.CVReg: codeview::RegisterId::DL, .Reg: X86::DL},
186 {.CVReg: codeview::RegisterId::BL, .Reg: X86::BL},
187 {.CVReg: codeview::RegisterId::AH, .Reg: X86::AH},
188 {.CVReg: codeview::RegisterId::CH, .Reg: X86::CH},
189 {.CVReg: codeview::RegisterId::DH, .Reg: X86::DH},
190 {.CVReg: codeview::RegisterId::BH, .Reg: X86::BH},
191 {.CVReg: codeview::RegisterId::AX, .Reg: X86::AX},
192 {.CVReg: codeview::RegisterId::CX, .Reg: X86::CX},
193 {.CVReg: codeview::RegisterId::DX, .Reg: X86::DX},
194 {.CVReg: codeview::RegisterId::BX, .Reg: X86::BX},
195 {.CVReg: codeview::RegisterId::SP, .Reg: X86::SP},
196 {.CVReg: codeview::RegisterId::BP, .Reg: X86::BP},
197 {.CVReg: codeview::RegisterId::SI, .Reg: X86::SI},
198 {.CVReg: codeview::RegisterId::DI, .Reg: X86::DI},
199 {.CVReg: codeview::RegisterId::EAX, .Reg: X86::EAX},
200 {.CVReg: codeview::RegisterId::ECX, .Reg: X86::ECX},
201 {.CVReg: codeview::RegisterId::EDX, .Reg: X86::EDX},
202 {.CVReg: codeview::RegisterId::EBX, .Reg: X86::EBX},
203 {.CVReg: codeview::RegisterId::ESP, .Reg: X86::ESP},
204 {.CVReg: codeview::RegisterId::EBP, .Reg: X86::EBP},
205 {.CVReg: codeview::RegisterId::ESI, .Reg: X86::ESI},
206 {.CVReg: codeview::RegisterId::EDI, .Reg: X86::EDI},
207
208 {.CVReg: codeview::RegisterId::EFLAGS, .Reg: X86::EFLAGS},
209
210 {.CVReg: codeview::RegisterId::ST0, .Reg: X86::ST0},
211 {.CVReg: codeview::RegisterId::ST1, .Reg: X86::ST1},
212 {.CVReg: codeview::RegisterId::ST2, .Reg: X86::ST2},
213 {.CVReg: codeview::RegisterId::ST3, .Reg: X86::ST3},
214 {.CVReg: codeview::RegisterId::ST4, .Reg: X86::ST4},
215 {.CVReg: codeview::RegisterId::ST5, .Reg: X86::ST5},
216 {.CVReg: codeview::RegisterId::ST6, .Reg: X86::ST6},
217 {.CVReg: codeview::RegisterId::ST7, .Reg: X86::ST7},
218
219 {.CVReg: codeview::RegisterId::ST0, .Reg: X86::FP0},
220 {.CVReg: codeview::RegisterId::ST1, .Reg: X86::FP1},
221 {.CVReg: codeview::RegisterId::ST2, .Reg: X86::FP2},
222 {.CVReg: codeview::RegisterId::ST3, .Reg: X86::FP3},
223 {.CVReg: codeview::RegisterId::ST4, .Reg: X86::FP4},
224 {.CVReg: codeview::RegisterId::ST5, .Reg: X86::FP5},
225 {.CVReg: codeview::RegisterId::ST6, .Reg: X86::FP6},
226 {.CVReg: codeview::RegisterId::ST7, .Reg: X86::FP7},
227
228 {.CVReg: codeview::RegisterId::MM0, .Reg: X86::MM0},
229 {.CVReg: codeview::RegisterId::MM1, .Reg: X86::MM1},
230 {.CVReg: codeview::RegisterId::MM2, .Reg: X86::MM2},
231 {.CVReg: codeview::RegisterId::MM3, .Reg: X86::MM3},
232 {.CVReg: codeview::RegisterId::MM4, .Reg: X86::MM4},
233 {.CVReg: codeview::RegisterId::MM5, .Reg: X86::MM5},
234 {.CVReg: codeview::RegisterId::MM6, .Reg: X86::MM6},
235 {.CVReg: codeview::RegisterId::MM7, .Reg: X86::MM7},
236
237 {.CVReg: codeview::RegisterId::XMM0, .Reg: X86::XMM0},
238 {.CVReg: codeview::RegisterId::XMM1, .Reg: X86::XMM1},
239 {.CVReg: codeview::RegisterId::XMM2, .Reg: X86::XMM2},
240 {.CVReg: codeview::RegisterId::XMM3, .Reg: X86::XMM3},
241 {.CVReg: codeview::RegisterId::XMM4, .Reg: X86::XMM4},
242 {.CVReg: codeview::RegisterId::XMM5, .Reg: X86::XMM5},
243 {.CVReg: codeview::RegisterId::XMM6, .Reg: X86::XMM6},
244 {.CVReg: codeview::RegisterId::XMM7, .Reg: X86::XMM7},
245
246 {.CVReg: codeview::RegisterId::XMM8, .Reg: X86::XMM8},
247 {.CVReg: codeview::RegisterId::XMM9, .Reg: X86::XMM9},
248 {.CVReg: codeview::RegisterId::XMM10, .Reg: X86::XMM10},
249 {.CVReg: codeview::RegisterId::XMM11, .Reg: X86::XMM11},
250 {.CVReg: codeview::RegisterId::XMM12, .Reg: X86::XMM12},
251 {.CVReg: codeview::RegisterId::XMM13, .Reg: X86::XMM13},
252 {.CVReg: codeview::RegisterId::XMM14, .Reg: X86::XMM14},
253 {.CVReg: codeview::RegisterId::XMM15, .Reg: X86::XMM15},
254
255 {.CVReg: codeview::RegisterId::SIL, .Reg: X86::SIL},
256 {.CVReg: codeview::RegisterId::DIL, .Reg: X86::DIL},
257 {.CVReg: codeview::RegisterId::BPL, .Reg: X86::BPL},
258 {.CVReg: codeview::RegisterId::SPL, .Reg: X86::SPL},
259 {.CVReg: codeview::RegisterId::RAX, .Reg: X86::RAX},
260 {.CVReg: codeview::RegisterId::RBX, .Reg: X86::RBX},
261 {.CVReg: codeview::RegisterId::RCX, .Reg: X86::RCX},
262 {.CVReg: codeview::RegisterId::RDX, .Reg: X86::RDX},
263 {.CVReg: codeview::RegisterId::RSI, .Reg: X86::RSI},
264 {.CVReg: codeview::RegisterId::RDI, .Reg: X86::RDI},
265 {.CVReg: codeview::RegisterId::RBP, .Reg: X86::RBP},
266 {.CVReg: codeview::RegisterId::RSP, .Reg: X86::RSP},
267 {.CVReg: codeview::RegisterId::R8, .Reg: X86::R8},
268 {.CVReg: codeview::RegisterId::R9, .Reg: X86::R9},
269 {.CVReg: codeview::RegisterId::R10, .Reg: X86::R10},
270 {.CVReg: codeview::RegisterId::R11, .Reg: X86::R11},
271 {.CVReg: codeview::RegisterId::R12, .Reg: X86::R12},
272 {.CVReg: codeview::RegisterId::R13, .Reg: X86::R13},
273 {.CVReg: codeview::RegisterId::R14, .Reg: X86::R14},
274 {.CVReg: codeview::RegisterId::R15, .Reg: X86::R15},
275 {.CVReg: codeview::RegisterId::R16, .Reg: X86::R16},
276 {.CVReg: codeview::RegisterId::R17, .Reg: X86::R17},
277 {.CVReg: codeview::RegisterId::R18, .Reg: X86::R18},
278 {.CVReg: codeview::RegisterId::R19, .Reg: X86::R19},
279 {.CVReg: codeview::RegisterId::R20, .Reg: X86::R20},
280 {.CVReg: codeview::RegisterId::R21, .Reg: X86::R21},
281 {.CVReg: codeview::RegisterId::R22, .Reg: X86::R22},
282 {.CVReg: codeview::RegisterId::R23, .Reg: X86::R23},
283 {.CVReg: codeview::RegisterId::R24, .Reg: X86::R24},
284 {.CVReg: codeview::RegisterId::R25, .Reg: X86::R25},
285 {.CVReg: codeview::RegisterId::R26, .Reg: X86::R26},
286 {.CVReg: codeview::RegisterId::R27, .Reg: X86::R27},
287 {.CVReg: codeview::RegisterId::R28, .Reg: X86::R28},
288 {.CVReg: codeview::RegisterId::R29, .Reg: X86::R29},
289 {.CVReg: codeview::RegisterId::R30, .Reg: X86::R30},
290 {.CVReg: codeview::RegisterId::R31, .Reg: X86::R31},
291 {.CVReg: codeview::RegisterId::R8B, .Reg: X86::R8B},
292 {.CVReg: codeview::RegisterId::R9B, .Reg: X86::R9B},
293 {.CVReg: codeview::RegisterId::R10B, .Reg: X86::R10B},
294 {.CVReg: codeview::RegisterId::R11B, .Reg: X86::R11B},
295 {.CVReg: codeview::RegisterId::R12B, .Reg: X86::R12B},
296 {.CVReg: codeview::RegisterId::R13B, .Reg: X86::R13B},
297 {.CVReg: codeview::RegisterId::R14B, .Reg: X86::R14B},
298 {.CVReg: codeview::RegisterId::R15B, .Reg: X86::R15B},
299 {.CVReg: codeview::RegisterId::R16B, .Reg: X86::R16B},
300 {.CVReg: codeview::RegisterId::R17B, .Reg: X86::R17B},
301 {.CVReg: codeview::RegisterId::R18B, .Reg: X86::R18B},
302 {.CVReg: codeview::RegisterId::R19B, .Reg: X86::R19B},
303 {.CVReg: codeview::RegisterId::R20B, .Reg: X86::R20B},
304 {.CVReg: codeview::RegisterId::R21B, .Reg: X86::R21B},
305 {.CVReg: codeview::RegisterId::R22B, .Reg: X86::R22B},
306 {.CVReg: codeview::RegisterId::R23B, .Reg: X86::R23B},
307 {.CVReg: codeview::RegisterId::R24B, .Reg: X86::R24B},
308 {.CVReg: codeview::RegisterId::R25B, .Reg: X86::R25B},
309 {.CVReg: codeview::RegisterId::R26B, .Reg: X86::R26B},
310 {.CVReg: codeview::RegisterId::R27B, .Reg: X86::R27B},
311 {.CVReg: codeview::RegisterId::R28B, .Reg: X86::R28B},
312 {.CVReg: codeview::RegisterId::R29B, .Reg: X86::R29B},
313 {.CVReg: codeview::RegisterId::R30B, .Reg: X86::R30B},
314 {.CVReg: codeview::RegisterId::R31B, .Reg: X86::R31B},
315 {.CVReg: codeview::RegisterId::R8W, .Reg: X86::R8W},
316 {.CVReg: codeview::RegisterId::R9W, .Reg: X86::R9W},
317 {.CVReg: codeview::RegisterId::R10W, .Reg: X86::R10W},
318 {.CVReg: codeview::RegisterId::R11W, .Reg: X86::R11W},
319 {.CVReg: codeview::RegisterId::R12W, .Reg: X86::R12W},
320 {.CVReg: codeview::RegisterId::R13W, .Reg: X86::R13W},
321 {.CVReg: codeview::RegisterId::R14W, .Reg: X86::R14W},
322 {.CVReg: codeview::RegisterId::R15W, .Reg: X86::R15W},
323 {.CVReg: codeview::RegisterId::R16W, .Reg: X86::R16W},
324 {.CVReg: codeview::RegisterId::R17W, .Reg: X86::R17W},
325 {.CVReg: codeview::RegisterId::R18W, .Reg: X86::R18W},
326 {.CVReg: codeview::RegisterId::R19W, .Reg: X86::R19W},
327 {.CVReg: codeview::RegisterId::R20W, .Reg: X86::R20W},
328 {.CVReg: codeview::RegisterId::R21W, .Reg: X86::R21W},
329 {.CVReg: codeview::RegisterId::R22W, .Reg: X86::R22W},
330 {.CVReg: codeview::RegisterId::R23W, .Reg: X86::R23W},
331 {.CVReg: codeview::RegisterId::R24W, .Reg: X86::R24W},
332 {.CVReg: codeview::RegisterId::R25W, .Reg: X86::R25W},
333 {.CVReg: codeview::RegisterId::R26W, .Reg: X86::R26W},
334 {.CVReg: codeview::RegisterId::R27W, .Reg: X86::R27W},
335 {.CVReg: codeview::RegisterId::R28W, .Reg: X86::R28W},
336 {.CVReg: codeview::RegisterId::R29W, .Reg: X86::R29W},
337 {.CVReg: codeview::RegisterId::R30W, .Reg: X86::R30W},
338 {.CVReg: codeview::RegisterId::R31W, .Reg: X86::R31W},
339 {.CVReg: codeview::RegisterId::R8D, .Reg: X86::R8D},
340 {.CVReg: codeview::RegisterId::R9D, .Reg: X86::R9D},
341 {.CVReg: codeview::RegisterId::R10D, .Reg: X86::R10D},
342 {.CVReg: codeview::RegisterId::R11D, .Reg: X86::R11D},
343 {.CVReg: codeview::RegisterId::R12D, .Reg: X86::R12D},
344 {.CVReg: codeview::RegisterId::R13D, .Reg: X86::R13D},
345 {.CVReg: codeview::RegisterId::R14D, .Reg: X86::R14D},
346 {.CVReg: codeview::RegisterId::R15D, .Reg: X86::R15D},
347 {.CVReg: codeview::RegisterId::R16D, .Reg: X86::R16D},
348 {.CVReg: codeview::RegisterId::R17D, .Reg: X86::R17D},
349 {.CVReg: codeview::RegisterId::R18D, .Reg: X86::R18D},
350 {.CVReg: codeview::RegisterId::R19D, .Reg: X86::R19D},
351 {.CVReg: codeview::RegisterId::R20D, .Reg: X86::R20D},
352 {.CVReg: codeview::RegisterId::R21D, .Reg: X86::R21D},
353 {.CVReg: codeview::RegisterId::R22D, .Reg: X86::R22D},
354 {.CVReg: codeview::RegisterId::R23D, .Reg: X86::R23D},
355 {.CVReg: codeview::RegisterId::R24D, .Reg: X86::R24D},
356 {.CVReg: codeview::RegisterId::R25D, .Reg: X86::R25D},
357 {.CVReg: codeview::RegisterId::R26D, .Reg: X86::R26D},
358 {.CVReg: codeview::RegisterId::R27D, .Reg: X86::R27D},
359 {.CVReg: codeview::RegisterId::R28D, .Reg: X86::R28D},
360 {.CVReg: codeview::RegisterId::R29D, .Reg: X86::R29D},
361 {.CVReg: codeview::RegisterId::R30D, .Reg: X86::R30D},
362 {.CVReg: codeview::RegisterId::R31D, .Reg: X86::R31D},
363 {.CVReg: codeview::RegisterId::AMD64_YMM0, .Reg: X86::YMM0},
364 {.CVReg: codeview::RegisterId::AMD64_YMM1, .Reg: X86::YMM1},
365 {.CVReg: codeview::RegisterId::AMD64_YMM2, .Reg: X86::YMM2},
366 {.CVReg: codeview::RegisterId::AMD64_YMM3, .Reg: X86::YMM3},
367 {.CVReg: codeview::RegisterId::AMD64_YMM4, .Reg: X86::YMM4},
368 {.CVReg: codeview::RegisterId::AMD64_YMM5, .Reg: X86::YMM5},
369 {.CVReg: codeview::RegisterId::AMD64_YMM6, .Reg: X86::YMM6},
370 {.CVReg: codeview::RegisterId::AMD64_YMM7, .Reg: X86::YMM7},
371 {.CVReg: codeview::RegisterId::AMD64_YMM8, .Reg: X86::YMM8},
372 {.CVReg: codeview::RegisterId::AMD64_YMM9, .Reg: X86::YMM9},
373 {.CVReg: codeview::RegisterId::AMD64_YMM10, .Reg: X86::YMM10},
374 {.CVReg: codeview::RegisterId::AMD64_YMM11, .Reg: X86::YMM11},
375 {.CVReg: codeview::RegisterId::AMD64_YMM12, .Reg: X86::YMM12},
376 {.CVReg: codeview::RegisterId::AMD64_YMM13, .Reg: X86::YMM13},
377 {.CVReg: codeview::RegisterId::AMD64_YMM14, .Reg: X86::YMM14},
378 {.CVReg: codeview::RegisterId::AMD64_YMM15, .Reg: X86::YMM15},
379 {.CVReg: codeview::RegisterId::AMD64_YMM16, .Reg: X86::YMM16},
380 {.CVReg: codeview::RegisterId::AMD64_YMM17, .Reg: X86::YMM17},
381 {.CVReg: codeview::RegisterId::AMD64_YMM18, .Reg: X86::YMM18},
382 {.CVReg: codeview::RegisterId::AMD64_YMM19, .Reg: X86::YMM19},
383 {.CVReg: codeview::RegisterId::AMD64_YMM20, .Reg: X86::YMM20},
384 {.CVReg: codeview::RegisterId::AMD64_YMM21, .Reg: X86::YMM21},
385 {.CVReg: codeview::RegisterId::AMD64_YMM22, .Reg: X86::YMM22},
386 {.CVReg: codeview::RegisterId::AMD64_YMM23, .Reg: X86::YMM23},
387 {.CVReg: codeview::RegisterId::AMD64_YMM24, .Reg: X86::YMM24},
388 {.CVReg: codeview::RegisterId::AMD64_YMM25, .Reg: X86::YMM25},
389 {.CVReg: codeview::RegisterId::AMD64_YMM26, .Reg: X86::YMM26},
390 {.CVReg: codeview::RegisterId::AMD64_YMM27, .Reg: X86::YMM27},
391 {.CVReg: codeview::RegisterId::AMD64_YMM28, .Reg: X86::YMM28},
392 {.CVReg: codeview::RegisterId::AMD64_YMM29, .Reg: X86::YMM29},
393 {.CVReg: codeview::RegisterId::AMD64_YMM30, .Reg: X86::YMM30},
394 {.CVReg: codeview::RegisterId::AMD64_YMM31, .Reg: X86::YMM31},
395 {.CVReg: codeview::RegisterId::AMD64_ZMM0, .Reg: X86::ZMM0},
396 {.CVReg: codeview::RegisterId::AMD64_ZMM1, .Reg: X86::ZMM1},
397 {.CVReg: codeview::RegisterId::AMD64_ZMM2, .Reg: X86::ZMM2},
398 {.CVReg: codeview::RegisterId::AMD64_ZMM3, .Reg: X86::ZMM3},
399 {.CVReg: codeview::RegisterId::AMD64_ZMM4, .Reg: X86::ZMM4},
400 {.CVReg: codeview::RegisterId::AMD64_ZMM5, .Reg: X86::ZMM5},
401 {.CVReg: codeview::RegisterId::AMD64_ZMM6, .Reg: X86::ZMM6},
402 {.CVReg: codeview::RegisterId::AMD64_ZMM7, .Reg: X86::ZMM7},
403 {.CVReg: codeview::RegisterId::AMD64_ZMM8, .Reg: X86::ZMM8},
404 {.CVReg: codeview::RegisterId::AMD64_ZMM9, .Reg: X86::ZMM9},
405 {.CVReg: codeview::RegisterId::AMD64_ZMM10, .Reg: X86::ZMM10},
406 {.CVReg: codeview::RegisterId::AMD64_ZMM11, .Reg: X86::ZMM11},
407 {.CVReg: codeview::RegisterId::AMD64_ZMM12, .Reg: X86::ZMM12},
408 {.CVReg: codeview::RegisterId::AMD64_ZMM13, .Reg: X86::ZMM13},
409 {.CVReg: codeview::RegisterId::AMD64_ZMM14, .Reg: X86::ZMM14},
410 {.CVReg: codeview::RegisterId::AMD64_ZMM15, .Reg: X86::ZMM15},
411 {.CVReg: codeview::RegisterId::AMD64_ZMM16, .Reg: X86::ZMM16},
412 {.CVReg: codeview::RegisterId::AMD64_ZMM17, .Reg: X86::ZMM17},
413 {.CVReg: codeview::RegisterId::AMD64_ZMM18, .Reg: X86::ZMM18},
414 {.CVReg: codeview::RegisterId::AMD64_ZMM19, .Reg: X86::ZMM19},
415 {.CVReg: codeview::RegisterId::AMD64_ZMM20, .Reg: X86::ZMM20},
416 {.CVReg: codeview::RegisterId::AMD64_ZMM21, .Reg: X86::ZMM21},
417 {.CVReg: codeview::RegisterId::AMD64_ZMM22, .Reg: X86::ZMM22},
418 {.CVReg: codeview::RegisterId::AMD64_ZMM23, .Reg: X86::ZMM23},
419 {.CVReg: codeview::RegisterId::AMD64_ZMM24, .Reg: X86::ZMM24},
420 {.CVReg: codeview::RegisterId::AMD64_ZMM25, .Reg: X86::ZMM25},
421 {.CVReg: codeview::RegisterId::AMD64_ZMM26, .Reg: X86::ZMM26},
422 {.CVReg: codeview::RegisterId::AMD64_ZMM27, .Reg: X86::ZMM27},
423 {.CVReg: codeview::RegisterId::AMD64_ZMM28, .Reg: X86::ZMM28},
424 {.CVReg: codeview::RegisterId::AMD64_ZMM29, .Reg: X86::ZMM29},
425 {.CVReg: codeview::RegisterId::AMD64_ZMM30, .Reg: X86::ZMM30},
426 {.CVReg: codeview::RegisterId::AMD64_ZMM31, .Reg: X86::ZMM31},
427 {.CVReg: codeview::RegisterId::AMD64_K0, .Reg: X86::K0},
428 {.CVReg: codeview::RegisterId::AMD64_K1, .Reg: X86::K1},
429 {.CVReg: codeview::RegisterId::AMD64_K2, .Reg: X86::K2},
430 {.CVReg: codeview::RegisterId::AMD64_K3, .Reg: X86::K3},
431 {.CVReg: codeview::RegisterId::AMD64_K4, .Reg: X86::K4},
432 {.CVReg: codeview::RegisterId::AMD64_K5, .Reg: X86::K5},
433 {.CVReg: codeview::RegisterId::AMD64_K6, .Reg: X86::K6},
434 {.CVReg: codeview::RegisterId::AMD64_K7, .Reg: X86::K7},
435 {.CVReg: codeview::RegisterId::AMD64_XMM16, .Reg: X86::XMM16},
436 {.CVReg: codeview::RegisterId::AMD64_XMM17, .Reg: X86::XMM17},
437 {.CVReg: codeview::RegisterId::AMD64_XMM18, .Reg: X86::XMM18},
438 {.CVReg: codeview::RegisterId::AMD64_XMM19, .Reg: X86::XMM19},
439 {.CVReg: codeview::RegisterId::AMD64_XMM20, .Reg: X86::XMM20},
440 {.CVReg: codeview::RegisterId::AMD64_XMM21, .Reg: X86::XMM21},
441 {.CVReg: codeview::RegisterId::AMD64_XMM22, .Reg: X86::XMM22},
442 {.CVReg: codeview::RegisterId::AMD64_XMM23, .Reg: X86::XMM23},
443 {.CVReg: codeview::RegisterId::AMD64_XMM24, .Reg: X86::XMM24},
444 {.CVReg: codeview::RegisterId::AMD64_XMM25, .Reg: X86::XMM25},
445 {.CVReg: codeview::RegisterId::AMD64_XMM26, .Reg: X86::XMM26},
446 {.CVReg: codeview::RegisterId::AMD64_XMM27, .Reg: X86::XMM27},
447 {.CVReg: codeview::RegisterId::AMD64_XMM28, .Reg: X86::XMM28},
448 {.CVReg: codeview::RegisterId::AMD64_XMM29, .Reg: X86::XMM29},
449 {.CVReg: codeview::RegisterId::AMD64_XMM30, .Reg: X86::XMM30},
450 {.CVReg: codeview::RegisterId::AMD64_XMM31, .Reg: X86::XMM31},
451
452 };
453 for (const auto &I : RegMap)
454 MRI->mapLLVMRegToCVReg(LLVMReg: I.Reg, CVReg: static_cast<int>(I.CVReg));
455}
456
457MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
458 StringRef CPU, StringRef FS) {
459 std::string ArchFS = X86_MC::ParseX86Triple(TT);
460 assert(!ArchFS.empty() && "Failed to parse X86 triple");
461 if (!FS.empty())
462 ArchFS = (Twine(ArchFS) + "," + FS).str();
463
464 if (CPU.empty())
465 CPU = "generic";
466
467 return createX86MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS: ArchFS);
468}
469
470static MCInstrInfo *createX86MCInstrInfo() {
471 MCInstrInfo *X = new MCInstrInfo();
472 InitX86MCInstrInfo(II: X);
473 return X;
474}
475
476static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
477 unsigned RA = TT.isX86_64() ? X86::RIP // Should have dwarf #16.
478 : X86::EIP; // Should have dwarf #8.
479
480 MCRegisterInfo *X = new MCRegisterInfo();
481 InitX86MCRegisterInfo(RI: X, RA, DwarfFlavour: X86_MC::getDwarfRegFlavour(TT, isEH: false),
482 EHFlavour: X86_MC::getDwarfRegFlavour(TT, isEH: true), PC: RA);
483 X86_MC::initLLVMToSEHAndCVRegMapping(MRI: X);
484 return X;
485}
486
487static void populateReservedIdentifiers(MCAsmInfo &MAI,
488 const MCRegisterInfo &MRI) {
489 auto &Set = MAI.getReservedIdentifiers();
490 // Register names: `call rsi` is misassembled as an indirect call. Use the
491 // Intel printer's table directly — it's the lowercase asm name in stable
492 // storage. MRI::getName() returns the uppercase enum name and would need
493 // an extra .lower() heap allocation per entry.
494 for (unsigned i = 1, e = MRI.getNumRegs(); i < e; ++i)
495 if (const char *Name = X86IntelInstPrinter::getRegisterName(Reg: i))
496 if (Name[0])
497 Set.insert(V: CachedHashStringRef(Name));
498 // Keywords that GAS Intel syntax misparses as constants, modifiers, or
499 // pseudo-registers instead of symbol references (e.g., `call byte` calls
500 // address 1, not symbol "byte"; `call flat` errors out).
501 for (StringRef KW : {"byte", "word", "dword", "fword", "qword", "mmword",
502 "tbyte", "oword", "xmmword", "ymmword", "zmmword",
503 "offset", "flat", "near", "far", "short"})
504 Set.insert(V: CachedHashStringRef(KW));
505 // Operator keywords parsed by GAS/X86AsmParser in Intel mode.
506 for (StringRef KW : {"and", "eq", "ge", "gt", "le", "lt", "mod", "ne", "not",
507 "or", "shl", "shr", "xor"})
508 Set.insert(V: CachedHashStringRef(KW));
509}
510
511static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
512 const Triple &TheTriple,
513 const MCTargetOptions &Options) {
514 bool is64Bit = TheTriple.isX86_64();
515
516 MCAsmInfo *MAI;
517 if (TheTriple.isOSBinFormatMachO()) {
518 if (is64Bit)
519 MAI = new X86_64MCAsmInfoDarwin(TheTriple, Options);
520 else
521 MAI = new X86MCAsmInfoDarwin(TheTriple, Options);
522 } else if (TheTriple.isOSBinFormatELF()) {
523 // Force the use of an ELF container.
524 MAI = new X86ELFMCAsmInfo(TheTriple, Options);
525 } else if (TheTriple.isWindowsMSVCEnvironment() ||
526 TheTriple.isWindowsCoreCLREnvironment() || TheTriple.isUEFI()) {
527 if (Options.getAssemblyLanguage().equals_insensitive(RHS: "masm"))
528 MAI = new X86MCAsmInfoMicrosoftMASM(TheTriple, Options);
529 else
530 MAI = new X86MCAsmInfoMicrosoft(TheTriple, Options);
531 } else if (TheTriple.isOSCygMing() ||
532 TheTriple.isWindowsItaniumEnvironment()) {
533 MAI = new X86MCAsmInfoGNUCOFF(TheTriple, Options);
534 } else {
535 // The default is ELF.
536 MAI = new X86ELFMCAsmInfo(TheTriple, Options);
537 }
538 populateReservedIdentifiers(MAI&: *MAI, MRI);
539
540 // Initialize initial frame state.
541 // Calculate amount of bytes used for return address storing
542 int stackGrowth = is64Bit ? -8 : -4;
543
544 // Initial state of the frame pointer is esp+stackGrowth.
545 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
546 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
547 L: nullptr, Register: MRI.getDwarfRegNum(Reg: StackPtr, isEH: true), Offset: -stackGrowth);
548 MAI->addInitialFrameState(Inst);
549
550 // Add return address to move list
551 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
552 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
553 L: nullptr, Register: MRI.getDwarfRegNum(Reg: InstPtr, isEH: true), Offset: stackGrowth);
554 MAI->addInitialFrameState(Inst: Inst2);
555
556 return MAI;
557}
558
559static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
560 unsigned SyntaxVariant,
561 const MCAsmInfo &MAI,
562 const MCInstrInfo &MII,
563 const MCRegisterInfo &MRI) {
564 if (SyntaxVariant == 0)
565 return new X86ATTInstPrinter(MAI, MII, MRI);
566 if (SyntaxVariant == 1)
567 return new X86IntelInstPrinter(MAI, MII, MRI);
568 return nullptr;
569}
570
571static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
572 MCContext &Ctx) {
573 // Default to the stock relocation info.
574 return llvm::createMCRelocationInfo(TT: TheTriple, Ctx);
575}
576
577namespace llvm {
578namespace X86_MC {
579
580class X86MCInstrAnalysis : public MCInstrAnalysis {
581 X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete;
582 X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete;
583 ~X86MCInstrAnalysis() override = default;
584
585public:
586 X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {}
587
588#define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
589#include "X86GenSubtargetInfo.inc"
590
591 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
592 APInt &Mask) const override;
593 std::vector<std::pair<uint64_t, uint64_t>>
594 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
595 const MCSubtargetInfo &STI) const override;
596
597 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
598 uint64_t &Target) const override;
599 std::optional<uint64_t>
600 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,
601 uint64_t Addr, uint64_t Size) const override;
602 std::optional<uint64_t>
603 getMemoryOperandRelocationOffset(const MCInst &Inst,
604 uint64_t Size) const override;
605};
606
607#define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
608#include "X86GenSubtargetInfo.inc"
609
610bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
611 const MCInst &Inst,
612 APInt &Mask) const {
613 const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode());
614 unsigned NumDefs = Desc.getNumDefs();
615 unsigned NumImplicitDefs = Desc.implicit_defs().size();
616 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
617 "Unexpected number of bits in the mask!");
618
619 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
620 bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX;
621 bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP;
622
623 const MCRegisterClass &GR32RC = MRI.getRegClass(i: X86::GR32RegClassID);
624 const MCRegisterClass &VR128XRC = MRI.getRegClass(i: X86::VR128XRegClassID);
625 const MCRegisterClass &VR256XRC = MRI.getRegClass(i: X86::VR256XRegClassID);
626
627 auto ClearsSuperReg = [=](MCRegister RegID) {
628 // On X86-64, a general purpose integer register is viewed as a 64-bit
629 // register internal to the processor.
630 // An update to the lower 32 bits of a 64 bit integer register is
631 // architecturally defined to zero extend the upper 32 bits.
632 if (GR32RC.contains(Reg: RegID))
633 return true;
634
635 // Early exit if this instruction has no vex/evex/xop prefix.
636 if (!HasEVEX && !HasVEX && !HasXOP)
637 return false;
638
639 // All VEX and EVEX encoded instructions are defined to zero the high bits
640 // of the destination register up to VLMAX (i.e. the maximum vector register
641 // width pertaining to the instruction).
642 // We assume the same behavior for XOP instructions too.
643 return VR128XRC.contains(Reg: RegID) || VR256XRC.contains(Reg: RegID);
644 };
645
646 Mask.clearAllBits();
647 for (unsigned I = 0, E = NumDefs; I < E; ++I) {
648 const MCOperand &Op = Inst.getOperand(i: I);
649 if (ClearsSuperReg(Op.getReg()))
650 Mask.setBit(I);
651 }
652
653 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
654 const MCPhysReg Reg = Desc.implicit_defs()[I];
655 if (ClearsSuperReg(Reg))
656 Mask.setBit(NumDefs + I);
657 }
658
659 return Mask.getBoolValue();
660}
661
662static std::vector<std::pair<uint64_t, uint64_t>>
663findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {
664 // Do a lightweight parsing of PLT entries.
665 std::vector<std::pair<uint64_t, uint64_t>> Result;
666 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
667 // Recognize a jmp.
668 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) {
669 // The jmp instruction at the beginning of each PLT entry jumps to the
670 // address of the base of the .got.plt section plus the immediate.
671 // Set the 1 << 32 bit to let ELFObjectFileBase::getPltEntries convert the
672 // offset to an address. Imm may be a negative int32_t if the GOT entry is
673 // in .got.
674 uint32_t Imm = support::endian::read32le(P: PltContents.data() + Byte + 2);
675 Result.emplace_back(args: PltSectionVA + Byte, args: Imm | (uint64_t(1) << 32));
676 Byte += 6;
677 } else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
678 // The jmp instruction at the beginning of each PLT entry jumps to the
679 // immediate.
680 uint32_t Imm = support::endian::read32le(P: PltContents.data() + Byte + 2);
681 Result.push_back(x: std::make_pair(x: PltSectionVA + Byte, y&: Imm));
682 Byte += 6;
683 } else
684 Byte++;
685 }
686 return Result;
687}
688
689static std::vector<std::pair<uint64_t, uint64_t>>
690findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {
691 // Do a lightweight parsing of PLT entries.
692 std::vector<std::pair<uint64_t, uint64_t>> Result;
693 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
694 // Recognize a jmp.
695 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
696 // The jmp instruction at the beginning of each PLT entry jumps to the
697 // address of the next instruction plus the immediate.
698 uint32_t Imm = support::endian::read32le(P: PltContents.data() + Byte + 2);
699 Result.push_back(
700 x: std::make_pair(x: PltSectionVA + Byte, y: PltSectionVA + Byte + 6 + Imm));
701 Byte += 6;
702 } else
703 Byte++;
704 }
705 return Result;
706}
707
708std::vector<std::pair<uint64_t, uint64_t>>
709X86MCInstrAnalysis::findPltEntries(uint64_t PltSectionVA,
710 ArrayRef<uint8_t> PltContents,
711 const MCSubtargetInfo &STI) const {
712 const Triple &TargetTriple = STI.getTargetTriple();
713 switch (TargetTriple.getArch()) {
714 case Triple::x86:
715 return findX86PltEntries(PltSectionVA, PltContents);
716 case Triple::x86_64:
717 return findX86_64PltEntries(PltSectionVA, PltContents);
718 default:
719 return {};
720 }
721}
722
723bool X86MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
724 uint64_t Size, uint64_t &Target) const {
725 if (Inst.getNumOperands() == 0 ||
726 Info->get(Opcode: Inst.getOpcode()).operands()[0].OperandType !=
727 MCOI::OPERAND_PCREL)
728 return false;
729 Target = Addr + Size + Inst.getOperand(i: 0).getImm();
730 return true;
731}
732
733std::optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress(
734 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
735 uint64_t Size) const {
736 const MCInstrDesc &MCID = Info->get(Opcode: Inst.getOpcode());
737 int MemOpStart = X86II::getMemoryOperandNo(TSFlags: MCID.TSFlags);
738 if (MemOpStart == -1)
739 return std::nullopt;
740 MemOpStart += X86II::getOperandBias(Desc: MCID);
741
742 const MCOperand &SegReg = Inst.getOperand(i: MemOpStart + X86::AddrSegmentReg);
743 const MCOperand &BaseReg = Inst.getOperand(i: MemOpStart + X86::AddrBaseReg);
744 const MCOperand &IndexReg = Inst.getOperand(i: MemOpStart + X86::AddrIndexReg);
745 const MCOperand &ScaleAmt = Inst.getOperand(i: MemOpStart + X86::AddrScaleAmt);
746 const MCOperand &Disp = Inst.getOperand(i: MemOpStart + X86::AddrDisp);
747 if (SegReg.getReg() || IndexReg.getReg() || ScaleAmt.getImm() != 1 ||
748 !Disp.isImm())
749 return std::nullopt;
750
751 // RIP-relative addressing.
752 if (BaseReg.getReg() == X86::RIP)
753 return Addr + Size + Disp.getImm();
754
755 return std::nullopt;
756}
757
758std::optional<uint64_t>
759X86MCInstrAnalysis::getMemoryOperandRelocationOffset(const MCInst &Inst,
760 uint64_t Size) const {
761 if (Inst.getOpcode() != X86::LEA64r)
762 return std::nullopt;
763 const MCInstrDesc &MCID = Info->get(Opcode: Inst.getOpcode());
764 int MemOpStart = X86II::getMemoryOperandNo(TSFlags: MCID.TSFlags);
765 if (MemOpStart == -1)
766 return std::nullopt;
767 MemOpStart += X86II::getOperandBias(Desc: MCID);
768 const MCOperand &SegReg = Inst.getOperand(i: MemOpStart + X86::AddrSegmentReg);
769 const MCOperand &BaseReg = Inst.getOperand(i: MemOpStart + X86::AddrBaseReg);
770 const MCOperand &IndexReg = Inst.getOperand(i: MemOpStart + X86::AddrIndexReg);
771 const MCOperand &ScaleAmt = Inst.getOperand(i: MemOpStart + X86::AddrScaleAmt);
772 const MCOperand &Disp = Inst.getOperand(i: MemOpStart + X86::AddrDisp);
773 // Must be a simple rip-relative address.
774 if (BaseReg.getReg() != X86::RIP || SegReg.getReg() || IndexReg.getReg() ||
775 ScaleAmt.getImm() != 1 || !Disp.isImm())
776 return std::nullopt;
777 // rip-relative ModR/M immediate is 32 bits.
778 assert(Size > 4 && "invalid instruction size for rip-relative lea");
779 return Size - 4;
780}
781
782} // end of namespace X86_MC
783
784} // end of namespace llvm
785
786static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
787 return new X86_MC::X86MCInstrAnalysis(Info);
788}
789
790// Force static initialization.
791extern "C" LLVM_C_ABI void LLVMInitializeX86TargetMC() {
792 for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
793 // Register the MC asm info.
794 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
795
796 // Register the MC instruction info.
797 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createX86MCInstrInfo);
798
799 // Register the MC register info.
800 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createX86MCRegisterInfo);
801
802 // Register the MC subtarget info.
803 TargetRegistry::RegisterMCSubtargetInfo(T&: *T,
804 Fn: X86_MC::createX86MCSubtargetInfo);
805
806 // Register the MC instruction analyzer.
807 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createX86MCInstrAnalysis);
808
809 // Register the code emitter.
810 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createX86MCCodeEmitter);
811
812 // Register the obj target streamer.
813 TargetRegistry::RegisterObjectTargetStreamer(T&: *T,
814 Fn: createX86ObjectTargetStreamer);
815
816 // Register the asm target streamer.
817 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createX86AsmTargetStreamer);
818
819 // Register the null streamer.
820 TargetRegistry::RegisterNullTargetStreamer(T&: *T, Fn: createX86NullTargetStreamer);
821
822 TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createX86WinCOFFStreamer);
823 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createX86ELFStreamer);
824
825 // Register the MCInstPrinter.
826 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createX86MCInstPrinter);
827
828 // Register the MC relocation info.
829 TargetRegistry::RegisterMCRelocationInfo(T&: *T, Fn: createX86MCRelocationInfo);
830 }
831
832 // Register the asm backend.
833 TargetRegistry::RegisterMCAsmBackend(T&: getTheX86_32Target(),
834 Fn: createX86_32AsmBackend);
835 TargetRegistry::RegisterMCAsmBackend(T&: getTheX86_64Target(),
836 Fn: createX86_64AsmBackend);
837}
838
839MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size,
840 bool High) {
841#define DEFAULT_NOREG \
842 default: \
843 return X86::NoRegister;
844#define SUB_SUPER(R1, R2, R3, R4, R) \
845 case X86::R1: \
846 case X86::R2: \
847 case X86::R3: \
848 case X86::R4: \
849 return X86::R;
850#define A_SUB_SUPER(R) \
851 case X86::AH: \
852 SUB_SUPER(AL, AX, EAX, RAX, R)
853#define D_SUB_SUPER(R) \
854 case X86::DH: \
855 SUB_SUPER(DL, DX, EDX, RDX, R)
856#define C_SUB_SUPER(R) \
857 case X86::CH: \
858 SUB_SUPER(CL, CX, ECX, RCX, R)
859#define B_SUB_SUPER(R) \
860 case X86::BH: \
861 SUB_SUPER(BL, BX, EBX, RBX, R)
862#define SI_SUB_SUPER(R) SUB_SUPER(SIL, SI, ESI, RSI, R)
863#define DI_SUB_SUPER(R) SUB_SUPER(DIL, DI, EDI, RDI, R)
864#define BP_SUB_SUPER(R) SUB_SUPER(BPL, BP, EBP, RBP, R)
865#define SP_SUB_SUPER(R) SUB_SUPER(SPL, SP, ESP, RSP, R)
866#define NO_SUB_SUPER(NO, REG) \
867 SUB_SUPER(R##NO##B, R##NO##W, R##NO##D, R##NO, REG)
868#define NO_SUB_SUPER_B(NO) NO_SUB_SUPER(NO, R##NO##B)
869#define NO_SUB_SUPER_W(NO) NO_SUB_SUPER(NO, R##NO##W)
870#define NO_SUB_SUPER_D(NO) NO_SUB_SUPER(NO, R##NO##D)
871#define NO_SUB_SUPER_Q(NO) NO_SUB_SUPER(NO, R##NO)
872 switch (Size) {
873 default:
874 llvm_unreachable("illegal register size");
875 case 8:
876 if (High) {
877 switch (Reg.id()) {
878 DEFAULT_NOREG
879 A_SUB_SUPER(AH)
880 D_SUB_SUPER(DH)
881 C_SUB_SUPER(CH)
882 B_SUB_SUPER(BH)
883 }
884 } else {
885 switch (Reg.id()) {
886 DEFAULT_NOREG
887 A_SUB_SUPER(AL)
888 D_SUB_SUPER(DL)
889 C_SUB_SUPER(CL)
890 B_SUB_SUPER(BL)
891 SI_SUB_SUPER(SIL)
892 DI_SUB_SUPER(DIL)
893 BP_SUB_SUPER(BPL)
894 SP_SUB_SUPER(SPL)
895 NO_SUB_SUPER_B(8)
896 NO_SUB_SUPER_B(9)
897 NO_SUB_SUPER_B(10)
898 NO_SUB_SUPER_B(11)
899 NO_SUB_SUPER_B(12)
900 NO_SUB_SUPER_B(13)
901 NO_SUB_SUPER_B(14)
902 NO_SUB_SUPER_B(15)
903 NO_SUB_SUPER_B(16)
904 NO_SUB_SUPER_B(17)
905 NO_SUB_SUPER_B(18)
906 NO_SUB_SUPER_B(19)
907 NO_SUB_SUPER_B(20)
908 NO_SUB_SUPER_B(21)
909 NO_SUB_SUPER_B(22)
910 NO_SUB_SUPER_B(23)
911 NO_SUB_SUPER_B(24)
912 NO_SUB_SUPER_B(25)
913 NO_SUB_SUPER_B(26)
914 NO_SUB_SUPER_B(27)
915 NO_SUB_SUPER_B(28)
916 NO_SUB_SUPER_B(29)
917 NO_SUB_SUPER_B(30)
918 NO_SUB_SUPER_B(31)
919 }
920 }
921 case 16:
922 switch (Reg.id()) {
923 DEFAULT_NOREG
924 A_SUB_SUPER(AX)
925 D_SUB_SUPER(DX)
926 C_SUB_SUPER(CX)
927 B_SUB_SUPER(BX)
928 SI_SUB_SUPER(SI)
929 DI_SUB_SUPER(DI)
930 BP_SUB_SUPER(BP)
931 SP_SUB_SUPER(SP)
932 NO_SUB_SUPER_W(8)
933 NO_SUB_SUPER_W(9)
934 NO_SUB_SUPER_W(10)
935 NO_SUB_SUPER_W(11)
936 NO_SUB_SUPER_W(12)
937 NO_SUB_SUPER_W(13)
938 NO_SUB_SUPER_W(14)
939 NO_SUB_SUPER_W(15)
940 NO_SUB_SUPER_W(16)
941 NO_SUB_SUPER_W(17)
942 NO_SUB_SUPER_W(18)
943 NO_SUB_SUPER_W(19)
944 NO_SUB_SUPER_W(20)
945 NO_SUB_SUPER_W(21)
946 NO_SUB_SUPER_W(22)
947 NO_SUB_SUPER_W(23)
948 NO_SUB_SUPER_W(24)
949 NO_SUB_SUPER_W(25)
950 NO_SUB_SUPER_W(26)
951 NO_SUB_SUPER_W(27)
952 NO_SUB_SUPER_W(28)
953 NO_SUB_SUPER_W(29)
954 NO_SUB_SUPER_W(30)
955 NO_SUB_SUPER_W(31)
956 }
957 case 32:
958 switch (Reg.id()) {
959 DEFAULT_NOREG
960 A_SUB_SUPER(EAX)
961 D_SUB_SUPER(EDX)
962 C_SUB_SUPER(ECX)
963 B_SUB_SUPER(EBX)
964 SI_SUB_SUPER(ESI)
965 DI_SUB_SUPER(EDI)
966 BP_SUB_SUPER(EBP)
967 SP_SUB_SUPER(ESP)
968 NO_SUB_SUPER_D(8)
969 NO_SUB_SUPER_D(9)
970 NO_SUB_SUPER_D(10)
971 NO_SUB_SUPER_D(11)
972 NO_SUB_SUPER_D(12)
973 NO_SUB_SUPER_D(13)
974 NO_SUB_SUPER_D(14)
975 NO_SUB_SUPER_D(15)
976 NO_SUB_SUPER_D(16)
977 NO_SUB_SUPER_D(17)
978 NO_SUB_SUPER_D(18)
979 NO_SUB_SUPER_D(19)
980 NO_SUB_SUPER_D(20)
981 NO_SUB_SUPER_D(21)
982 NO_SUB_SUPER_D(22)
983 NO_SUB_SUPER_D(23)
984 NO_SUB_SUPER_D(24)
985 NO_SUB_SUPER_D(25)
986 NO_SUB_SUPER_D(26)
987 NO_SUB_SUPER_D(27)
988 NO_SUB_SUPER_D(28)
989 NO_SUB_SUPER_D(29)
990 NO_SUB_SUPER_D(30)
991 NO_SUB_SUPER_D(31)
992 }
993 case 64:
994 switch (Reg.id()) {
995 DEFAULT_NOREG
996 A_SUB_SUPER(RAX)
997 D_SUB_SUPER(RDX)
998 C_SUB_SUPER(RCX)
999 B_SUB_SUPER(RBX)
1000 SI_SUB_SUPER(RSI)
1001 DI_SUB_SUPER(RDI)
1002 BP_SUB_SUPER(RBP)
1003 SP_SUB_SUPER(RSP)
1004 NO_SUB_SUPER_Q(8)
1005 NO_SUB_SUPER_Q(9)
1006 NO_SUB_SUPER_Q(10)
1007 NO_SUB_SUPER_Q(11)
1008 NO_SUB_SUPER_Q(12)
1009 NO_SUB_SUPER_Q(13)
1010 NO_SUB_SUPER_Q(14)
1011 NO_SUB_SUPER_Q(15)
1012 NO_SUB_SUPER_Q(16)
1013 NO_SUB_SUPER_Q(17)
1014 NO_SUB_SUPER_Q(18)
1015 NO_SUB_SUPER_Q(19)
1016 NO_SUB_SUPER_Q(20)
1017 NO_SUB_SUPER_Q(21)
1018 NO_SUB_SUPER_Q(22)
1019 NO_SUB_SUPER_Q(23)
1020 NO_SUB_SUPER_Q(24)
1021 NO_SUB_SUPER_Q(25)
1022 NO_SUB_SUPER_Q(26)
1023 NO_SUB_SUPER_Q(27)
1024 NO_SUB_SUPER_Q(28)
1025 NO_SUB_SUPER_Q(29)
1026 NO_SUB_SUPER_Q(30)
1027 NO_SUB_SUPER_Q(31)
1028 }
1029 }
1030}
1031