1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides X86 specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86MCTargetDesc.h"
14#include "TargetInfo/X86TargetInfo.h"
15#include "X86ATTInstPrinter.h"
16#include "X86BaseInfo.h"
17#include "X86IntelInstPrinter.h"
18#include "X86MCAsmInfo.h"
19#include "X86MCLFIRewriter.h"
20#include "X86TargetStreamer.h"
21#include "llvm-c/Visibility.h"
22#include "llvm/ADT/APInt.h"
23#include "llvm/DebugInfo/CodeView/CodeView.h"
24#include "llvm/MC/MCDwarf.h"
25#include "llvm/MC/MCInstrAnalysis.h"
26#include "llvm/MC/MCInstrInfo.h"
27#include "llvm/MC/MCRegisterInfo.h"
28#include "llvm/MC/MCStreamer.h"
29#include "llvm/MC/MCSubtargetInfo.h"
30#include "llvm/MC/TargetRegistry.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/TargetParser/Host.h"
33#include "llvm/TargetParser/Triple.h"
34
35using namespace llvm;
36
37#define GET_REGINFO_MC_DESC
38#include "X86GenRegisterInfo.inc"
39
40#define GET_INSTRINFO_MC_DESC
41#define GET_INSTRINFO_MC_HELPERS
42#define ENABLE_INSTR_PREDICATE_VERIFIER
43#include "X86GenInstrInfo.inc"
44
45#define GET_SUBTARGETINFO_MC_DESC
46#include "X86GenSubtargetInfo.inc"
47
48std::string X86_MC::ParseX86Triple(const Triple &TT) {
49 std::string FS;
50 // SSE2 should default to enabled in 64-bit mode, but can be turned off
51 // explicitly.
52 if (TT.isX86_64())
53 FS = "+64bit-mode,-32bit-mode,-16bit-mode,+sse2";
54 else if (TT.getEnvironment() != Triple::CODE16)
55 FS = "-64bit-mode,+32bit-mode,-16bit-mode";
56 else
57 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
58
59 if (TT.isX32())
60 FS += ",+x32";
61
62 return FS;
63}
64
65unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
66 if (TT.isX86_64())
67 return DWARFFlavour::X86_64;
68
69 if (TT.isOSDarwin())
70 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
71 if (TT.isOSCygMing())
72 // Unsupported by now, just quick fallback
73 return DWARFFlavour::X86_32_Generic;
74 return DWARFFlavour::X86_32_Generic;
75}
76
77bool X86_MC::hasLockPrefix(const MCInst &MI) {
78 return MI.getFlags() & X86::IP_HAS_LOCK;
79}
80
81static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) {
82 const MCOperand &Base = MI.getOperand(i: Op + X86::AddrBaseReg);
83 const MCOperand &Index = MI.getOperand(i: Op + X86::AddrIndexReg);
84 const MCRegisterClass &RC = getX86MCRegisterClass(RC: RegClassID);
85
86 return (Base.isReg() && Base.getReg() && RC.contains(Reg: Base.getReg())) ||
87 (Index.isReg() && Index.getReg() && RC.contains(Reg: Index.getReg()));
88}
89
90bool X86_MC::is16BitMemOperand(const MCInst &MI, unsigned Op,
91 const MCSubtargetInfo &STI) {
92 const MCOperand &Base = MI.getOperand(i: Op + X86::AddrBaseReg);
93 const MCOperand &Index = MI.getOperand(i: Op + X86::AddrIndexReg);
94
95 if (STI.hasFeature(Feature: X86::Is16Bit) && Base.isReg() && !Base.getReg() &&
96 Index.isReg() && !Index.getReg())
97 return true;
98 return isMemOperand(MI, Op, RegClassID: X86::GR16RegClassID);
99}
100
101bool X86_MC::is32BitMemOperand(const MCInst &MI, unsigned Op) {
102 const MCOperand &Base = MI.getOperand(i: Op + X86::AddrBaseReg);
103 const MCOperand &Index = MI.getOperand(i: Op + X86::AddrIndexReg);
104 if (Base.isReg() && Base.getReg() == X86::EIP) {
105 assert(Index.isReg() && !Index.getReg() && "Invalid eip-based address");
106 return true;
107 }
108 if (Index.isReg() && Index.getReg() == X86::EIZ)
109 return true;
110 return isMemOperand(MI, Op, RegClassID: X86::GR32RegClassID);
111}
112
113#ifndef NDEBUG
114bool X86_MC::is64BitMemOperand(const MCInst &MI, unsigned Op) {
115 return isMemOperand(MI, Op, X86::GR64RegClassID);
116}
117#endif
118
119bool X86_MC::needsAddressSizeOverride(const MCInst &MI,
120 const MCSubtargetInfo &STI,
121 int MemoryOperand, uint64_t TSFlags) {
122 uint64_t AdSize = TSFlags & X86II::AdSizeMask;
123 bool Is16BitMode = STI.hasFeature(Feature: X86::Is16Bit);
124 bool Is32BitMode = STI.hasFeature(Feature: X86::Is32Bit);
125 bool Is64BitMode = STI.hasFeature(Feature: X86::Is64Bit);
126 if ((Is16BitMode && AdSize == X86II::AdSize32) ||
127 (Is32BitMode && AdSize == X86II::AdSize16) ||
128 (Is64BitMode && AdSize == X86II::AdSize32))
129 return true;
130 uint64_t Form = TSFlags & X86II::FormMask;
131 switch (Form) {
132 default:
133 break;
134 case X86II::RawFrmDstSrc: {
135 MCRegister siReg = MI.getOperand(i: 1).getReg();
136 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||
137 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||
138 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
139 "SI and DI register sizes do not match");
140 return (!Is32BitMode && siReg == X86::ESI) ||
141 (Is32BitMode && siReg == X86::SI);
142 }
143 case X86II::RawFrmSrc: {
144 MCRegister siReg = MI.getOperand(i: 0).getReg();
145 return (!Is32BitMode && siReg == X86::ESI) ||
146 (Is32BitMode && siReg == X86::SI);
147 }
148 case X86II::RawFrmDst: {
149 MCRegister siReg = MI.getOperand(i: 0).getReg();
150 return (!Is32BitMode && siReg == X86::EDI) ||
151 (Is32BitMode && siReg == X86::DI);
152 }
153 }
154
155 // Determine where the memory operand starts, if present.
156 if (MemoryOperand < 0)
157 return false;
158
159 if (STI.hasFeature(Feature: X86::Is64Bit)) {
160 assert(!is16BitMemOperand(MI, MemoryOperand, STI));
161 return is32BitMemOperand(MI, Op: MemoryOperand);
162 }
163 if (STI.hasFeature(Feature: X86::Is32Bit)) {
164 assert(!is64BitMemOperand(MI, MemoryOperand));
165 return is16BitMemOperand(MI, Op: MemoryOperand, STI);
166 }
167 assert(STI.hasFeature(X86::Is16Bit));
168 assert(!is64BitMemOperand(MI, MemoryOperand));
169 return !is16BitMemOperand(MI, Op: MemoryOperand, STI);
170}
171
172void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
173 // FIXME: TableGen these.
174 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
175 unsigned SEH = MRI->getEncodingValue(Reg);
176 MRI->mapLLVMRegToSEHReg(LLVMReg: Reg, SEHReg: SEH);
177 }
178
179 // Mapping from CodeView to MC register id.
180 static const struct {
181 codeview::RegisterId CVReg;
182 MCPhysReg Reg;
183 } RegMap[] = {
184 {.CVReg: codeview::RegisterId::AL, .Reg: X86::AL},
185 {.CVReg: codeview::RegisterId::CL, .Reg: X86::CL},
186 {.CVReg: codeview::RegisterId::DL, .Reg: X86::DL},
187 {.CVReg: codeview::RegisterId::BL, .Reg: X86::BL},
188 {.CVReg: codeview::RegisterId::AH, .Reg: X86::AH},
189 {.CVReg: codeview::RegisterId::CH, .Reg: X86::CH},
190 {.CVReg: codeview::RegisterId::DH, .Reg: X86::DH},
191 {.CVReg: codeview::RegisterId::BH, .Reg: X86::BH},
192 {.CVReg: codeview::RegisterId::AX, .Reg: X86::AX},
193 {.CVReg: codeview::RegisterId::CX, .Reg: X86::CX},
194 {.CVReg: codeview::RegisterId::DX, .Reg: X86::DX},
195 {.CVReg: codeview::RegisterId::BX, .Reg: X86::BX},
196 {.CVReg: codeview::RegisterId::SP, .Reg: X86::SP},
197 {.CVReg: codeview::RegisterId::BP, .Reg: X86::BP},
198 {.CVReg: codeview::RegisterId::SI, .Reg: X86::SI},
199 {.CVReg: codeview::RegisterId::DI, .Reg: X86::DI},
200 {.CVReg: codeview::RegisterId::EAX, .Reg: X86::EAX},
201 {.CVReg: codeview::RegisterId::ECX, .Reg: X86::ECX},
202 {.CVReg: codeview::RegisterId::EDX, .Reg: X86::EDX},
203 {.CVReg: codeview::RegisterId::EBX, .Reg: X86::EBX},
204 {.CVReg: codeview::RegisterId::ESP, .Reg: X86::ESP},
205 {.CVReg: codeview::RegisterId::EBP, .Reg: X86::EBP},
206 {.CVReg: codeview::RegisterId::ESI, .Reg: X86::ESI},
207 {.CVReg: codeview::RegisterId::EDI, .Reg: X86::EDI},
208
209 {.CVReg: codeview::RegisterId::EFLAGS, .Reg: X86::EFLAGS},
210
211 {.CVReg: codeview::RegisterId::ST0, .Reg: X86::ST0},
212 {.CVReg: codeview::RegisterId::ST1, .Reg: X86::ST1},
213 {.CVReg: codeview::RegisterId::ST2, .Reg: X86::ST2},
214 {.CVReg: codeview::RegisterId::ST3, .Reg: X86::ST3},
215 {.CVReg: codeview::RegisterId::ST4, .Reg: X86::ST4},
216 {.CVReg: codeview::RegisterId::ST5, .Reg: X86::ST5},
217 {.CVReg: codeview::RegisterId::ST6, .Reg: X86::ST6},
218 {.CVReg: codeview::RegisterId::ST7, .Reg: X86::ST7},
219
220 {.CVReg: codeview::RegisterId::ST0, .Reg: X86::FP0},
221 {.CVReg: codeview::RegisterId::ST1, .Reg: X86::FP1},
222 {.CVReg: codeview::RegisterId::ST2, .Reg: X86::FP2},
223 {.CVReg: codeview::RegisterId::ST3, .Reg: X86::FP3},
224 {.CVReg: codeview::RegisterId::ST4, .Reg: X86::FP4},
225 {.CVReg: codeview::RegisterId::ST5, .Reg: X86::FP5},
226 {.CVReg: codeview::RegisterId::ST6, .Reg: X86::FP6},
227 {.CVReg: codeview::RegisterId::ST7, .Reg: X86::FP7},
228
229 {.CVReg: codeview::RegisterId::MM0, .Reg: X86::MM0},
230 {.CVReg: codeview::RegisterId::MM1, .Reg: X86::MM1},
231 {.CVReg: codeview::RegisterId::MM2, .Reg: X86::MM2},
232 {.CVReg: codeview::RegisterId::MM3, .Reg: X86::MM3},
233 {.CVReg: codeview::RegisterId::MM4, .Reg: X86::MM4},
234 {.CVReg: codeview::RegisterId::MM5, .Reg: X86::MM5},
235 {.CVReg: codeview::RegisterId::MM6, .Reg: X86::MM6},
236 {.CVReg: codeview::RegisterId::MM7, .Reg: X86::MM7},
237
238 {.CVReg: codeview::RegisterId::XMM0, .Reg: X86::XMM0},
239 {.CVReg: codeview::RegisterId::XMM1, .Reg: X86::XMM1},
240 {.CVReg: codeview::RegisterId::XMM2, .Reg: X86::XMM2},
241 {.CVReg: codeview::RegisterId::XMM3, .Reg: X86::XMM3},
242 {.CVReg: codeview::RegisterId::XMM4, .Reg: X86::XMM4},
243 {.CVReg: codeview::RegisterId::XMM5, .Reg: X86::XMM5},
244 {.CVReg: codeview::RegisterId::XMM6, .Reg: X86::XMM6},
245 {.CVReg: codeview::RegisterId::XMM7, .Reg: X86::XMM7},
246
247 {.CVReg: codeview::RegisterId::XMM8, .Reg: X86::XMM8},
248 {.CVReg: codeview::RegisterId::XMM9, .Reg: X86::XMM9},
249 {.CVReg: codeview::RegisterId::XMM10, .Reg: X86::XMM10},
250 {.CVReg: codeview::RegisterId::XMM11, .Reg: X86::XMM11},
251 {.CVReg: codeview::RegisterId::XMM12, .Reg: X86::XMM12},
252 {.CVReg: codeview::RegisterId::XMM13, .Reg: X86::XMM13},
253 {.CVReg: codeview::RegisterId::XMM14, .Reg: X86::XMM14},
254 {.CVReg: codeview::RegisterId::XMM15, .Reg: X86::XMM15},
255
256 {.CVReg: codeview::RegisterId::SIL, .Reg: X86::SIL},
257 {.CVReg: codeview::RegisterId::DIL, .Reg: X86::DIL},
258 {.CVReg: codeview::RegisterId::BPL, .Reg: X86::BPL},
259 {.CVReg: codeview::RegisterId::SPL, .Reg: X86::SPL},
260 {.CVReg: codeview::RegisterId::RAX, .Reg: X86::RAX},
261 {.CVReg: codeview::RegisterId::RBX, .Reg: X86::RBX},
262 {.CVReg: codeview::RegisterId::RCX, .Reg: X86::RCX},
263 {.CVReg: codeview::RegisterId::RDX, .Reg: X86::RDX},
264 {.CVReg: codeview::RegisterId::RSI, .Reg: X86::RSI},
265 {.CVReg: codeview::RegisterId::RDI, .Reg: X86::RDI},
266 {.CVReg: codeview::RegisterId::RBP, .Reg: X86::RBP},
267 {.CVReg: codeview::RegisterId::RSP, .Reg: X86::RSP},
268 {.CVReg: codeview::RegisterId::R8, .Reg: X86::R8},
269 {.CVReg: codeview::RegisterId::R9, .Reg: X86::R9},
270 {.CVReg: codeview::RegisterId::R10, .Reg: X86::R10},
271 {.CVReg: codeview::RegisterId::R11, .Reg: X86::R11},
272 {.CVReg: codeview::RegisterId::R12, .Reg: X86::R12},
273 {.CVReg: codeview::RegisterId::R13, .Reg: X86::R13},
274 {.CVReg: codeview::RegisterId::R14, .Reg: X86::R14},
275 {.CVReg: codeview::RegisterId::R15, .Reg: X86::R15},
276 {.CVReg: codeview::RegisterId::R16, .Reg: X86::R16},
277 {.CVReg: codeview::RegisterId::R17, .Reg: X86::R17},
278 {.CVReg: codeview::RegisterId::R18, .Reg: X86::R18},
279 {.CVReg: codeview::RegisterId::R19, .Reg: X86::R19},
280 {.CVReg: codeview::RegisterId::R20, .Reg: X86::R20},
281 {.CVReg: codeview::RegisterId::R21, .Reg: X86::R21},
282 {.CVReg: codeview::RegisterId::R22, .Reg: X86::R22},
283 {.CVReg: codeview::RegisterId::R23, .Reg: X86::R23},
284 {.CVReg: codeview::RegisterId::R24, .Reg: X86::R24},
285 {.CVReg: codeview::RegisterId::R25, .Reg: X86::R25},
286 {.CVReg: codeview::RegisterId::R26, .Reg: X86::R26},
287 {.CVReg: codeview::RegisterId::R27, .Reg: X86::R27},
288 {.CVReg: codeview::RegisterId::R28, .Reg: X86::R28},
289 {.CVReg: codeview::RegisterId::R29, .Reg: X86::R29},
290 {.CVReg: codeview::RegisterId::R30, .Reg: X86::R30},
291 {.CVReg: codeview::RegisterId::R31, .Reg: X86::R31},
292 {.CVReg: codeview::RegisterId::R8B, .Reg: X86::R8B},
293 {.CVReg: codeview::RegisterId::R9B, .Reg: X86::R9B},
294 {.CVReg: codeview::RegisterId::R10B, .Reg: X86::R10B},
295 {.CVReg: codeview::RegisterId::R11B, .Reg: X86::R11B},
296 {.CVReg: codeview::RegisterId::R12B, .Reg: X86::R12B},
297 {.CVReg: codeview::RegisterId::R13B, .Reg: X86::R13B},
298 {.CVReg: codeview::RegisterId::R14B, .Reg: X86::R14B},
299 {.CVReg: codeview::RegisterId::R15B, .Reg: X86::R15B},
300 {.CVReg: codeview::RegisterId::R16B, .Reg: X86::R16B},
301 {.CVReg: codeview::RegisterId::R17B, .Reg: X86::R17B},
302 {.CVReg: codeview::RegisterId::R18B, .Reg: X86::R18B},
303 {.CVReg: codeview::RegisterId::R19B, .Reg: X86::R19B},
304 {.CVReg: codeview::RegisterId::R20B, .Reg: X86::R20B},
305 {.CVReg: codeview::RegisterId::R21B, .Reg: X86::R21B},
306 {.CVReg: codeview::RegisterId::R22B, .Reg: X86::R22B},
307 {.CVReg: codeview::RegisterId::R23B, .Reg: X86::R23B},
308 {.CVReg: codeview::RegisterId::R24B, .Reg: X86::R24B},
309 {.CVReg: codeview::RegisterId::R25B, .Reg: X86::R25B},
310 {.CVReg: codeview::RegisterId::R26B, .Reg: X86::R26B},
311 {.CVReg: codeview::RegisterId::R27B, .Reg: X86::R27B},
312 {.CVReg: codeview::RegisterId::R28B, .Reg: X86::R28B},
313 {.CVReg: codeview::RegisterId::R29B, .Reg: X86::R29B},
314 {.CVReg: codeview::RegisterId::R30B, .Reg: X86::R30B},
315 {.CVReg: codeview::RegisterId::R31B, .Reg: X86::R31B},
316 {.CVReg: codeview::RegisterId::R8W, .Reg: X86::R8W},
317 {.CVReg: codeview::RegisterId::R9W, .Reg: X86::R9W},
318 {.CVReg: codeview::RegisterId::R10W, .Reg: X86::R10W},
319 {.CVReg: codeview::RegisterId::R11W, .Reg: X86::R11W},
320 {.CVReg: codeview::RegisterId::R12W, .Reg: X86::R12W},
321 {.CVReg: codeview::RegisterId::R13W, .Reg: X86::R13W},
322 {.CVReg: codeview::RegisterId::R14W, .Reg: X86::R14W},
323 {.CVReg: codeview::RegisterId::R15W, .Reg: X86::R15W},
324 {.CVReg: codeview::RegisterId::R16W, .Reg: X86::R16W},
325 {.CVReg: codeview::RegisterId::R17W, .Reg: X86::R17W},
326 {.CVReg: codeview::RegisterId::R18W, .Reg: X86::R18W},
327 {.CVReg: codeview::RegisterId::R19W, .Reg: X86::R19W},
328 {.CVReg: codeview::RegisterId::R20W, .Reg: X86::R20W},
329 {.CVReg: codeview::RegisterId::R21W, .Reg: X86::R21W},
330 {.CVReg: codeview::RegisterId::R22W, .Reg: X86::R22W},
331 {.CVReg: codeview::RegisterId::R23W, .Reg: X86::R23W},
332 {.CVReg: codeview::RegisterId::R24W, .Reg: X86::R24W},
333 {.CVReg: codeview::RegisterId::R25W, .Reg: X86::R25W},
334 {.CVReg: codeview::RegisterId::R26W, .Reg: X86::R26W},
335 {.CVReg: codeview::RegisterId::R27W, .Reg: X86::R27W},
336 {.CVReg: codeview::RegisterId::R28W, .Reg: X86::R28W},
337 {.CVReg: codeview::RegisterId::R29W, .Reg: X86::R29W},
338 {.CVReg: codeview::RegisterId::R30W, .Reg: X86::R30W},
339 {.CVReg: codeview::RegisterId::R31W, .Reg: X86::R31W},
340 {.CVReg: codeview::RegisterId::R8D, .Reg: X86::R8D},
341 {.CVReg: codeview::RegisterId::R9D, .Reg: X86::R9D},
342 {.CVReg: codeview::RegisterId::R10D, .Reg: X86::R10D},
343 {.CVReg: codeview::RegisterId::R11D, .Reg: X86::R11D},
344 {.CVReg: codeview::RegisterId::R12D, .Reg: X86::R12D},
345 {.CVReg: codeview::RegisterId::R13D, .Reg: X86::R13D},
346 {.CVReg: codeview::RegisterId::R14D, .Reg: X86::R14D},
347 {.CVReg: codeview::RegisterId::R15D, .Reg: X86::R15D},
348 {.CVReg: codeview::RegisterId::R16D, .Reg: X86::R16D},
349 {.CVReg: codeview::RegisterId::R17D, .Reg: X86::R17D},
350 {.CVReg: codeview::RegisterId::R18D, .Reg: X86::R18D},
351 {.CVReg: codeview::RegisterId::R19D, .Reg: X86::R19D},
352 {.CVReg: codeview::RegisterId::R20D, .Reg: X86::R20D},
353 {.CVReg: codeview::RegisterId::R21D, .Reg: X86::R21D},
354 {.CVReg: codeview::RegisterId::R22D, .Reg: X86::R22D},
355 {.CVReg: codeview::RegisterId::R23D, .Reg: X86::R23D},
356 {.CVReg: codeview::RegisterId::R24D, .Reg: X86::R24D},
357 {.CVReg: codeview::RegisterId::R25D, .Reg: X86::R25D},
358 {.CVReg: codeview::RegisterId::R26D, .Reg: X86::R26D},
359 {.CVReg: codeview::RegisterId::R27D, .Reg: X86::R27D},
360 {.CVReg: codeview::RegisterId::R28D, .Reg: X86::R28D},
361 {.CVReg: codeview::RegisterId::R29D, .Reg: X86::R29D},
362 {.CVReg: codeview::RegisterId::R30D, .Reg: X86::R30D},
363 {.CVReg: codeview::RegisterId::R31D, .Reg: X86::R31D},
364 {.CVReg: codeview::RegisterId::AMD64_YMM0, .Reg: X86::YMM0},
365 {.CVReg: codeview::RegisterId::AMD64_YMM1, .Reg: X86::YMM1},
366 {.CVReg: codeview::RegisterId::AMD64_YMM2, .Reg: X86::YMM2},
367 {.CVReg: codeview::RegisterId::AMD64_YMM3, .Reg: X86::YMM3},
368 {.CVReg: codeview::RegisterId::AMD64_YMM4, .Reg: X86::YMM4},
369 {.CVReg: codeview::RegisterId::AMD64_YMM5, .Reg: X86::YMM5},
370 {.CVReg: codeview::RegisterId::AMD64_YMM6, .Reg: X86::YMM6},
371 {.CVReg: codeview::RegisterId::AMD64_YMM7, .Reg: X86::YMM7},
372 {.CVReg: codeview::RegisterId::AMD64_YMM8, .Reg: X86::YMM8},
373 {.CVReg: codeview::RegisterId::AMD64_YMM9, .Reg: X86::YMM9},
374 {.CVReg: codeview::RegisterId::AMD64_YMM10, .Reg: X86::YMM10},
375 {.CVReg: codeview::RegisterId::AMD64_YMM11, .Reg: X86::YMM11},
376 {.CVReg: codeview::RegisterId::AMD64_YMM12, .Reg: X86::YMM12},
377 {.CVReg: codeview::RegisterId::AMD64_YMM13, .Reg: X86::YMM13},
378 {.CVReg: codeview::RegisterId::AMD64_YMM14, .Reg: X86::YMM14},
379 {.CVReg: codeview::RegisterId::AMD64_YMM15, .Reg: X86::YMM15},
380 {.CVReg: codeview::RegisterId::AMD64_YMM16, .Reg: X86::YMM16},
381 {.CVReg: codeview::RegisterId::AMD64_YMM17, .Reg: X86::YMM17},
382 {.CVReg: codeview::RegisterId::AMD64_YMM18, .Reg: X86::YMM18},
383 {.CVReg: codeview::RegisterId::AMD64_YMM19, .Reg: X86::YMM19},
384 {.CVReg: codeview::RegisterId::AMD64_YMM20, .Reg: X86::YMM20},
385 {.CVReg: codeview::RegisterId::AMD64_YMM21, .Reg: X86::YMM21},
386 {.CVReg: codeview::RegisterId::AMD64_YMM22, .Reg: X86::YMM22},
387 {.CVReg: codeview::RegisterId::AMD64_YMM23, .Reg: X86::YMM23},
388 {.CVReg: codeview::RegisterId::AMD64_YMM24, .Reg: X86::YMM24},
389 {.CVReg: codeview::RegisterId::AMD64_YMM25, .Reg: X86::YMM25},
390 {.CVReg: codeview::RegisterId::AMD64_YMM26, .Reg: X86::YMM26},
391 {.CVReg: codeview::RegisterId::AMD64_YMM27, .Reg: X86::YMM27},
392 {.CVReg: codeview::RegisterId::AMD64_YMM28, .Reg: X86::YMM28},
393 {.CVReg: codeview::RegisterId::AMD64_YMM29, .Reg: X86::YMM29},
394 {.CVReg: codeview::RegisterId::AMD64_YMM30, .Reg: X86::YMM30},
395 {.CVReg: codeview::RegisterId::AMD64_YMM31, .Reg: X86::YMM31},
396 {.CVReg: codeview::RegisterId::AMD64_ZMM0, .Reg: X86::ZMM0},
397 {.CVReg: codeview::RegisterId::AMD64_ZMM1, .Reg: X86::ZMM1},
398 {.CVReg: codeview::RegisterId::AMD64_ZMM2, .Reg: X86::ZMM2},
399 {.CVReg: codeview::RegisterId::AMD64_ZMM3, .Reg: X86::ZMM3},
400 {.CVReg: codeview::RegisterId::AMD64_ZMM4, .Reg: X86::ZMM4},
401 {.CVReg: codeview::RegisterId::AMD64_ZMM5, .Reg: X86::ZMM5},
402 {.CVReg: codeview::RegisterId::AMD64_ZMM6, .Reg: X86::ZMM6},
403 {.CVReg: codeview::RegisterId::AMD64_ZMM7, .Reg: X86::ZMM7},
404 {.CVReg: codeview::RegisterId::AMD64_ZMM8, .Reg: X86::ZMM8},
405 {.CVReg: codeview::RegisterId::AMD64_ZMM9, .Reg: X86::ZMM9},
406 {.CVReg: codeview::RegisterId::AMD64_ZMM10, .Reg: X86::ZMM10},
407 {.CVReg: codeview::RegisterId::AMD64_ZMM11, .Reg: X86::ZMM11},
408 {.CVReg: codeview::RegisterId::AMD64_ZMM12, .Reg: X86::ZMM12},
409 {.CVReg: codeview::RegisterId::AMD64_ZMM13, .Reg: X86::ZMM13},
410 {.CVReg: codeview::RegisterId::AMD64_ZMM14, .Reg: X86::ZMM14},
411 {.CVReg: codeview::RegisterId::AMD64_ZMM15, .Reg: X86::ZMM15},
412 {.CVReg: codeview::RegisterId::AMD64_ZMM16, .Reg: X86::ZMM16},
413 {.CVReg: codeview::RegisterId::AMD64_ZMM17, .Reg: X86::ZMM17},
414 {.CVReg: codeview::RegisterId::AMD64_ZMM18, .Reg: X86::ZMM18},
415 {.CVReg: codeview::RegisterId::AMD64_ZMM19, .Reg: X86::ZMM19},
416 {.CVReg: codeview::RegisterId::AMD64_ZMM20, .Reg: X86::ZMM20},
417 {.CVReg: codeview::RegisterId::AMD64_ZMM21, .Reg: X86::ZMM21},
418 {.CVReg: codeview::RegisterId::AMD64_ZMM22, .Reg: X86::ZMM22},
419 {.CVReg: codeview::RegisterId::AMD64_ZMM23, .Reg: X86::ZMM23},
420 {.CVReg: codeview::RegisterId::AMD64_ZMM24, .Reg: X86::ZMM24},
421 {.CVReg: codeview::RegisterId::AMD64_ZMM25, .Reg: X86::ZMM25},
422 {.CVReg: codeview::RegisterId::AMD64_ZMM26, .Reg: X86::ZMM26},
423 {.CVReg: codeview::RegisterId::AMD64_ZMM27, .Reg: X86::ZMM27},
424 {.CVReg: codeview::RegisterId::AMD64_ZMM28, .Reg: X86::ZMM28},
425 {.CVReg: codeview::RegisterId::AMD64_ZMM29, .Reg: X86::ZMM29},
426 {.CVReg: codeview::RegisterId::AMD64_ZMM30, .Reg: X86::ZMM30},
427 {.CVReg: codeview::RegisterId::AMD64_ZMM31, .Reg: X86::ZMM31},
428 {.CVReg: codeview::RegisterId::AMD64_K0, .Reg: X86::K0},
429 {.CVReg: codeview::RegisterId::AMD64_K1, .Reg: X86::K1},
430 {.CVReg: codeview::RegisterId::AMD64_K2, .Reg: X86::K2},
431 {.CVReg: codeview::RegisterId::AMD64_K3, .Reg: X86::K3},
432 {.CVReg: codeview::RegisterId::AMD64_K4, .Reg: X86::K4},
433 {.CVReg: codeview::RegisterId::AMD64_K5, .Reg: X86::K5},
434 {.CVReg: codeview::RegisterId::AMD64_K6, .Reg: X86::K6},
435 {.CVReg: codeview::RegisterId::AMD64_K7, .Reg: X86::K7},
436 {.CVReg: codeview::RegisterId::AMD64_XMM16, .Reg: X86::XMM16},
437 {.CVReg: codeview::RegisterId::AMD64_XMM17, .Reg: X86::XMM17},
438 {.CVReg: codeview::RegisterId::AMD64_XMM18, .Reg: X86::XMM18},
439 {.CVReg: codeview::RegisterId::AMD64_XMM19, .Reg: X86::XMM19},
440 {.CVReg: codeview::RegisterId::AMD64_XMM20, .Reg: X86::XMM20},
441 {.CVReg: codeview::RegisterId::AMD64_XMM21, .Reg: X86::XMM21},
442 {.CVReg: codeview::RegisterId::AMD64_XMM22, .Reg: X86::XMM22},
443 {.CVReg: codeview::RegisterId::AMD64_XMM23, .Reg: X86::XMM23},
444 {.CVReg: codeview::RegisterId::AMD64_XMM24, .Reg: X86::XMM24},
445 {.CVReg: codeview::RegisterId::AMD64_XMM25, .Reg: X86::XMM25},
446 {.CVReg: codeview::RegisterId::AMD64_XMM26, .Reg: X86::XMM26},
447 {.CVReg: codeview::RegisterId::AMD64_XMM27, .Reg: X86::XMM27},
448 {.CVReg: codeview::RegisterId::AMD64_XMM28, .Reg: X86::XMM28},
449 {.CVReg: codeview::RegisterId::AMD64_XMM29, .Reg: X86::XMM29},
450 {.CVReg: codeview::RegisterId::AMD64_XMM30, .Reg: X86::XMM30},
451 {.CVReg: codeview::RegisterId::AMD64_XMM31, .Reg: X86::XMM31},
452
453 };
454 for (const auto &I : RegMap)
455 MRI->mapLLVMRegToCVReg(LLVMReg: I.Reg, CVReg: static_cast<int>(I.CVReg));
456}
457
458MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
459 StringRef CPU, StringRef FS) {
460 std::string ArchFS = X86_MC::ParseX86Triple(TT);
461 assert(!ArchFS.empty() && "Failed to parse X86 triple");
462 if (!FS.empty())
463 ArchFS = (Twine(ArchFS) + "," + FS).str();
464
465 if (CPU.empty())
466 CPU = "generic";
467
468 return createX86MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS: ArchFS);
469}
470
471static MCInstrInfo *createX86MCInstrInfo() {
472 MCInstrInfo *X = new MCInstrInfo();
473 InitX86MCInstrInfo(II: X);
474 return X;
475}
476
477static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
478 unsigned RA = TT.isX86_64() ? X86::RIP // Should have dwarf #16.
479 : X86::EIP; // Should have dwarf #8.
480
481 MCRegisterInfo *X = new MCRegisterInfo();
482 InitX86MCRegisterInfo(RI: X, RA, DwarfFlavour: X86_MC::getDwarfRegFlavour(TT, isEH: false),
483 EHFlavour: X86_MC::getDwarfRegFlavour(TT, isEH: true), PC: RA);
484 X86_MC::initLLVMToSEHAndCVRegMapping(MRI: X);
485 return X;
486}
487
488static void populateReservedIdentifiers(MCAsmInfo &MAI,
489 const MCRegisterInfo &MRI) {
490 auto &Set = MAI.getReservedIdentifiers();
491 // Register names: `call rsi` is misassembled as an indirect call. Use the
492 // Intel printer's table directly — it's the lowercase asm name in stable
493 // storage. MRI::getName() returns the uppercase enum name and would need
494 // an extra .lower() heap allocation per entry.
495 for (unsigned i = 1, e = MRI.getNumRegs(); i < e; ++i)
496 if (const char *Name = X86IntelInstPrinter::getRegisterName(Reg: i))
497 if (Name[0])
498 Set.insert(V: CachedHashStringRef(Name));
499 // Keywords that GAS Intel syntax misparses as constants, modifiers, or
500 // pseudo-registers instead of symbol references (e.g., `call byte` calls
501 // address 1, not symbol "byte"; `call flat` errors out).
502 for (StringRef KW : {"byte", "word", "dword", "fword", "qword", "mmword",
503 "tbyte", "oword", "xmmword", "ymmword", "zmmword",
504 "offset", "flat", "near", "far", "short"})
505 Set.insert(V: CachedHashStringRef(KW));
506 // Operator keywords parsed by GAS/X86AsmParser in Intel mode.
507 for (StringRef KW : {"and", "eq", "ge", "gt", "le", "lt", "mod", "ne", "not",
508 "or", "shl", "shr", "xor"})
509 Set.insert(V: CachedHashStringRef(KW));
510}
511
512static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
513 const Triple &TheTriple,
514 const MCTargetOptions &Options) {
515 bool is64Bit = TheTriple.isX86_64();
516
517 MCAsmInfo *MAI;
518 if (TheTriple.isOSBinFormatMachO()) {
519 if (is64Bit)
520 MAI = new X86_64MCAsmInfoDarwin(TheTriple, Options);
521 else
522 MAI = new X86MCAsmInfoDarwin(TheTriple, Options);
523 } else if (TheTriple.isOSBinFormatELF()) {
524 // Force the use of an ELF container.
525 MAI = new X86ELFMCAsmInfo(TheTriple, Options);
526 } else if (TheTriple.isWindowsMSVCEnvironment() ||
527 TheTriple.isWindowsCoreCLREnvironment() || TheTriple.isUEFI()) {
528 if (Options.getAssemblyLanguage().equals_insensitive(RHS: "masm"))
529 MAI = new X86MCAsmInfoMicrosoftMASM(TheTriple, Options);
530 else
531 MAI = new X86MCAsmInfoMicrosoft(TheTriple, Options);
532 } else if (TheTriple.isOSCygMing() ||
533 TheTriple.isWindowsItaniumEnvironment()) {
534 MAI = new X86MCAsmInfoGNUCOFF(TheTriple, Options);
535 } else {
536 // The default is ELF.
537 MAI = new X86ELFMCAsmInfo(TheTriple, Options);
538 }
539
540 // Only Intel-syntax output needs to avoid register/keyword collisions; AT&T
541 // disambiguates registers with '%' and doesn't treat `byte`, `ptr`, etc. as
542 // keywords.
543 if (MAI->getOutputAssemblerDialect() != 0)
544 populateReservedIdentifiers(MAI&: *MAI, MRI);
545
546 // Initialize initial frame state.
547 // Calculate amount of bytes used for return address storing
548 int stackGrowth = is64Bit ? -8 : -4;
549
550 // Initial state of the frame pointer is esp+stackGrowth.
551 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
552 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
553 L: nullptr, Register: MRI.getDwarfRegNum(Reg: StackPtr, isEH: true), Offset: -stackGrowth);
554 MAI->addInitialFrameState(Inst);
555
556 // Add return address to move list
557 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
558 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
559 L: nullptr, Register: MRI.getDwarfRegNum(Reg: InstPtr, isEH: true), Offset: stackGrowth);
560 MAI->addInitialFrameState(Inst: Inst2);
561
562 return MAI;
563}
564
565static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
566 unsigned SyntaxVariant,
567 const MCAsmInfo &MAI,
568 const MCInstrInfo &MII,
569 const MCRegisterInfo &MRI) {
570 if (SyntaxVariant == 0)
571 return new X86ATTInstPrinter(MAI, MII, MRI);
572 if (SyntaxVariant == 1)
573 return new X86IntelInstPrinter(MAI, MII, MRI);
574 return nullptr;
575}
576
577static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
578 MCContext &Ctx) {
579 // Default to the stock relocation info.
580 return llvm::createMCRelocationInfo(TT: TheTriple, Ctx);
581}
582
583namespace llvm {
584namespace X86_MC {
585
586class X86MCInstrAnalysis : public MCInstrAnalysis {
587 X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete;
588 X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete;
589 ~X86MCInstrAnalysis() override = default;
590
591public:
592 X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {}
593
594#define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
595#include "X86GenSubtargetInfo.inc"
596
597 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
598 APInt &Mask) const override;
599 std::vector<std::pair<uint64_t, uint64_t>>
600 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
601 const MCSubtargetInfo &STI) const override;
602
603 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
604 uint64_t &Target) const override;
605 std::optional<uint64_t>
606 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,
607 uint64_t Addr, uint64_t Size) const override;
608 std::optional<uint64_t>
609 getMemoryOperandRelocationOffset(const MCInst &Inst,
610 uint64_t Size) const override;
611};
612
613#define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
614#include "X86GenSubtargetInfo.inc"
615
616bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
617 const MCInst &Inst,
618 APInt &Mask) const {
619 const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode());
620 unsigned NumDefs = Desc.getNumDefs();
621 unsigned NumImplicitDefs = Desc.implicit_defs().size();
622 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
623 "Unexpected number of bits in the mask!");
624
625 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
626 bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX;
627 bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP;
628
629 const MCRegisterClass &GR32RC = MRI.getRegClass(i: X86::GR32RegClassID);
630 const MCRegisterClass &VR128XRC = MRI.getRegClass(i: X86::VR128XRegClassID);
631 const MCRegisterClass &VR256XRC = MRI.getRegClass(i: X86::VR256XRegClassID);
632
633 auto ClearsSuperReg = [&](MCRegister RegID) {
634 // On X86-64, a general purpose integer register is viewed as a 64-bit
635 // register internal to the processor.
636 // An update to the lower 32 bits of a 64 bit integer register is
637 // architecturally defined to zero extend the upper 32 bits.
638 if (GR32RC.contains(Reg: RegID))
639 return true;
640
641 // Early exit if this instruction has no vex/evex/xop prefix.
642 if (!HasEVEX && !HasVEX && !HasXOP)
643 return false;
644
645 // All VEX and EVEX encoded instructions are defined to zero the high bits
646 // of the destination register up to VLMAX (i.e. the maximum vector register
647 // width pertaining to the instruction).
648 // We assume the same behavior for XOP instructions too.
649 return VR128XRC.contains(Reg: RegID) || VR256XRC.contains(Reg: RegID);
650 };
651
652 Mask.clearAllBits();
653 for (unsigned I = 0, E = NumDefs; I < E; ++I) {
654 const MCOperand &Op = Inst.getOperand(i: I);
655 if (ClearsSuperReg(Op.getReg()))
656 Mask.setBit(I);
657 }
658
659 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
660 const MCPhysReg Reg = Desc.implicit_defs()[I];
661 if (ClearsSuperReg(Reg))
662 Mask.setBit(NumDefs + I);
663 }
664
665 return Mask.getBoolValue();
666}
667
668static std::vector<std::pair<uint64_t, uint64_t>>
669findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {
670 // Do a lightweight parsing of PLT entries.
671 std::vector<std::pair<uint64_t, uint64_t>> Result;
672 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
673 // Recognize a jmp.
674 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) {
675 // The jmp instruction at the beginning of each PLT entry jumps to the
676 // address of the base of the .got.plt section plus the immediate.
677 // Set the 1 << 32 bit to let ELFObjectFileBase::getPltEntries convert the
678 // offset to an address. Imm may be a negative int32_t if the GOT entry is
679 // in .got.
680 uint32_t Imm = support::endian::read32le(P: PltContents.data() + Byte + 2);
681 Result.emplace_back(args: PltSectionVA + Byte, args: Imm | (uint64_t(1) << 32));
682 Byte += 6;
683 } else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
684 // The jmp instruction at the beginning of each PLT entry jumps to the
685 // immediate.
686 uint32_t Imm = support::endian::read32le(P: PltContents.data() + Byte + 2);
687 Result.push_back(x: std::make_pair(x: PltSectionVA + Byte, y&: Imm));
688 Byte += 6;
689 } else
690 Byte++;
691 }
692 return Result;
693}
694
695static std::vector<std::pair<uint64_t, uint64_t>>
696findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {
697 // Do a lightweight parsing of PLT entries.
698 std::vector<std::pair<uint64_t, uint64_t>> Result;
699 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
700 // Recognize a jmp.
701 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
702 // The jmp instruction at the beginning of each PLT entry jumps to the
703 // address of the next instruction plus the immediate.
704 uint32_t Imm = support::endian::read32le(P: PltContents.data() + Byte + 2);
705 Result.push_back(
706 x: std::make_pair(x: PltSectionVA + Byte, y: PltSectionVA + Byte + 6 + Imm));
707 Byte += 6;
708 } else
709 Byte++;
710 }
711 return Result;
712}
713
714std::vector<std::pair<uint64_t, uint64_t>>
715X86MCInstrAnalysis::findPltEntries(uint64_t PltSectionVA,
716 ArrayRef<uint8_t> PltContents,
717 const MCSubtargetInfo &STI) const {
718 const Triple &TargetTriple = STI.getTargetTriple();
719 switch (TargetTriple.getArch()) {
720 case Triple::x86:
721 return findX86PltEntries(PltSectionVA, PltContents);
722 case Triple::x86_64:
723 return findX86_64PltEntries(PltSectionVA, PltContents);
724 default:
725 return {};
726 }
727}
728
729bool X86MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
730 uint64_t Size, uint64_t &Target) const {
731 if (Inst.getNumOperands() == 0 ||
732 Info->get(Opcode: Inst.getOpcode()).operands()[0].OperandType !=
733 MCOI::OPERAND_PCREL)
734 return false;
735 Target = Addr + Size + Inst.getOperand(i: 0).getImm();
736 return true;
737}
738
739std::optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress(
740 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
741 uint64_t Size) const {
742 const MCInstrDesc &MCID = Info->get(Opcode: Inst.getOpcode());
743 int MemOpStart = X86II::getMemoryOperandIdx(Desc: MCID);
744 if (MemOpStart == -1)
745 return std::nullopt;
746
747 const MCOperand &SegReg = Inst.getOperand(i: MemOpStart + X86::AddrSegmentReg);
748 const MCOperand &BaseReg = Inst.getOperand(i: MemOpStart + X86::AddrBaseReg);
749 const MCOperand &IndexReg = Inst.getOperand(i: MemOpStart + X86::AddrIndexReg);
750 const MCOperand &ScaleAmt = Inst.getOperand(i: MemOpStart + X86::AddrScaleAmt);
751 const MCOperand &Disp = Inst.getOperand(i: MemOpStart + X86::AddrDisp);
752 if (SegReg.getReg() || IndexReg.getReg() || ScaleAmt.getImm() != 1 ||
753 !Disp.isImm())
754 return std::nullopt;
755
756 // RIP-relative addressing.
757 if (BaseReg.getReg() == X86::RIP)
758 return Addr + Size + Disp.getImm();
759
760 return std::nullopt;
761}
762
763std::optional<uint64_t>
764X86MCInstrAnalysis::getMemoryOperandRelocationOffset(const MCInst &Inst,
765 uint64_t Size) const {
766 if (Inst.getOpcode() != X86::LEA64r)
767 return std::nullopt;
768 const MCInstrDesc &MCID = Info->get(Opcode: Inst.getOpcode());
769 int MemOpStart = X86II::getMemoryOperandIdx(Desc: MCID);
770 if (MemOpStart == -1)
771 return std::nullopt;
772 const MCOperand &SegReg = Inst.getOperand(i: MemOpStart + X86::AddrSegmentReg);
773 const MCOperand &BaseReg = Inst.getOperand(i: MemOpStart + X86::AddrBaseReg);
774 const MCOperand &IndexReg = Inst.getOperand(i: MemOpStart + X86::AddrIndexReg);
775 const MCOperand &ScaleAmt = Inst.getOperand(i: MemOpStart + X86::AddrScaleAmt);
776 const MCOperand &Disp = Inst.getOperand(i: MemOpStart + X86::AddrDisp);
777 // Must be a simple rip-relative address.
778 if (BaseReg.getReg() != X86::RIP || SegReg.getReg() || IndexReg.getReg() ||
779 ScaleAmt.getImm() != 1 || !Disp.isImm())
780 return std::nullopt;
781 // rip-relative ModR/M immediate is 32 bits.
782 assert(Size > 4 && "invalid instruction size for rip-relative lea");
783 return Size - 4;
784}
785
786} // end of namespace X86_MC
787
788} // end of namespace llvm
789
790static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
791 return new X86_MC::X86MCInstrAnalysis(Info);
792}
793
794static MCLFIRewriter *
795createX86MCLFIRewriter(MCContext &Ctx,
796 std::unique_ptr<MCRegisterInfo> &&RegInfo,
797 std::unique_ptr<MCInstrInfo> &&InstInfo) {
798 return new X86::X86MCLFIRewriter(Ctx, std::move(RegInfo),
799 std::move(InstInfo));
800}
801
802// Force static initialization.
803extern "C" LLVM_C_ABI void LLVMInitializeX86TargetMC() {
804 for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
805 // Register the MC asm info.
806 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
807
808 // Register the MC instruction info.
809 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createX86MCInstrInfo);
810
811 // Register the MC register info.
812 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createX86MCRegisterInfo);
813
814 // Register the MC subtarget info.
815 TargetRegistry::RegisterMCSubtargetInfo(T&: *T,
816 Fn: X86_MC::createX86MCSubtargetInfo);
817
818 // Register the MC instruction analyzer.
819 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createX86MCInstrAnalysis);
820
821 // Register the code emitter.
822 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createX86MCCodeEmitter);
823
824 // Register the LFI rewriter.
825 TargetRegistry::RegisterMCLFIRewriter(T&: *T, Fn: createX86MCLFIRewriter);
826
827 // Register the obj target streamer.
828 TargetRegistry::RegisterObjectTargetStreamer(T&: *T,
829 Fn: createX86ObjectTargetStreamer);
830
831 // Register the asm target streamer.
832 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createX86AsmTargetStreamer);
833
834 // Register the null streamer.
835 TargetRegistry::RegisterNullTargetStreamer(T&: *T, Fn: createX86NullTargetStreamer);
836
837 TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createX86WinCOFFStreamer);
838 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createX86ELFStreamer);
839
840 // Register the MCInstPrinter.
841 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createX86MCInstPrinter);
842
843 // Register the MC relocation info.
844 TargetRegistry::RegisterMCRelocationInfo(T&: *T, Fn: createX86MCRelocationInfo);
845 }
846
847 // Register the asm backend.
848 TargetRegistry::RegisterMCAsmBackend(T&: getTheX86_32Target(),
849 Fn: createX86_32AsmBackend);
850 TargetRegistry::RegisterMCAsmBackend(T&: getTheX86_64Target(),
851 Fn: createX86_64AsmBackend);
852}
853
854MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size,
855 bool High) {
856#define DEFAULT_NOREG \
857 default: \
858 return X86::NoRegister;
859#define SUB_SUPER(R1, R2, R3, R4, R) \
860 case X86::R1: \
861 case X86::R2: \
862 case X86::R3: \
863 case X86::R4: \
864 return X86::R;
865#define A_SUB_SUPER(R) \
866 case X86::AH: \
867 SUB_SUPER(AL, AX, EAX, RAX, R)
868#define D_SUB_SUPER(R) \
869 case X86::DH: \
870 SUB_SUPER(DL, DX, EDX, RDX, R)
871#define C_SUB_SUPER(R) \
872 case X86::CH: \
873 SUB_SUPER(CL, CX, ECX, RCX, R)
874#define B_SUB_SUPER(R) \
875 case X86::BH: \
876 SUB_SUPER(BL, BX, EBX, RBX, R)
877#define SI_SUB_SUPER(R) SUB_SUPER(SIL, SI, ESI, RSI, R)
878#define DI_SUB_SUPER(R) SUB_SUPER(DIL, DI, EDI, RDI, R)
879#define BP_SUB_SUPER(R) SUB_SUPER(BPL, BP, EBP, RBP, R)
880#define SP_SUB_SUPER(R) SUB_SUPER(SPL, SP, ESP, RSP, R)
881#define NO_SUB_SUPER(NO, REG) \
882 SUB_SUPER(R##NO##B, R##NO##W, R##NO##D, R##NO, REG)
883#define NO_SUB_SUPER_B(NO) NO_SUB_SUPER(NO, R##NO##B)
884#define NO_SUB_SUPER_W(NO) NO_SUB_SUPER(NO, R##NO##W)
885#define NO_SUB_SUPER_D(NO) NO_SUB_SUPER(NO, R##NO##D)
886#define NO_SUB_SUPER_Q(NO) NO_SUB_SUPER(NO, R##NO)
887 switch (Size) {
888 default:
889 llvm_unreachable("illegal register size");
890 case 8:
891 if (High) {
892 switch (Reg.id()) {
893 DEFAULT_NOREG
894 A_SUB_SUPER(AH)
895 D_SUB_SUPER(DH)
896 C_SUB_SUPER(CH)
897 B_SUB_SUPER(BH)
898 }
899 } else {
900 switch (Reg.id()) {
901 DEFAULT_NOREG
902 A_SUB_SUPER(AL)
903 D_SUB_SUPER(DL)
904 C_SUB_SUPER(CL)
905 B_SUB_SUPER(BL)
906 SI_SUB_SUPER(SIL)
907 DI_SUB_SUPER(DIL)
908 BP_SUB_SUPER(BPL)
909 SP_SUB_SUPER(SPL)
910 NO_SUB_SUPER_B(8)
911 NO_SUB_SUPER_B(9)
912 NO_SUB_SUPER_B(10)
913 NO_SUB_SUPER_B(11)
914 NO_SUB_SUPER_B(12)
915 NO_SUB_SUPER_B(13)
916 NO_SUB_SUPER_B(14)
917 NO_SUB_SUPER_B(15)
918 NO_SUB_SUPER_B(16)
919 NO_SUB_SUPER_B(17)
920 NO_SUB_SUPER_B(18)
921 NO_SUB_SUPER_B(19)
922 NO_SUB_SUPER_B(20)
923 NO_SUB_SUPER_B(21)
924 NO_SUB_SUPER_B(22)
925 NO_SUB_SUPER_B(23)
926 NO_SUB_SUPER_B(24)
927 NO_SUB_SUPER_B(25)
928 NO_SUB_SUPER_B(26)
929 NO_SUB_SUPER_B(27)
930 NO_SUB_SUPER_B(28)
931 NO_SUB_SUPER_B(29)
932 NO_SUB_SUPER_B(30)
933 NO_SUB_SUPER_B(31)
934 }
935 }
936 case 16:
937 switch (Reg.id()) {
938 DEFAULT_NOREG
939 A_SUB_SUPER(AX)
940 D_SUB_SUPER(DX)
941 C_SUB_SUPER(CX)
942 B_SUB_SUPER(BX)
943 SI_SUB_SUPER(SI)
944 DI_SUB_SUPER(DI)
945 BP_SUB_SUPER(BP)
946 SP_SUB_SUPER(SP)
947 NO_SUB_SUPER_W(8)
948 NO_SUB_SUPER_W(9)
949 NO_SUB_SUPER_W(10)
950 NO_SUB_SUPER_W(11)
951 NO_SUB_SUPER_W(12)
952 NO_SUB_SUPER_W(13)
953 NO_SUB_SUPER_W(14)
954 NO_SUB_SUPER_W(15)
955 NO_SUB_SUPER_W(16)
956 NO_SUB_SUPER_W(17)
957 NO_SUB_SUPER_W(18)
958 NO_SUB_SUPER_W(19)
959 NO_SUB_SUPER_W(20)
960 NO_SUB_SUPER_W(21)
961 NO_SUB_SUPER_W(22)
962 NO_SUB_SUPER_W(23)
963 NO_SUB_SUPER_W(24)
964 NO_SUB_SUPER_W(25)
965 NO_SUB_SUPER_W(26)
966 NO_SUB_SUPER_W(27)
967 NO_SUB_SUPER_W(28)
968 NO_SUB_SUPER_W(29)
969 NO_SUB_SUPER_W(30)
970 NO_SUB_SUPER_W(31)
971 }
972 case 32:
973 switch (Reg.id()) {
974 DEFAULT_NOREG
975 A_SUB_SUPER(EAX)
976 D_SUB_SUPER(EDX)
977 C_SUB_SUPER(ECX)
978 B_SUB_SUPER(EBX)
979 SI_SUB_SUPER(ESI)
980 DI_SUB_SUPER(EDI)
981 BP_SUB_SUPER(EBP)
982 SP_SUB_SUPER(ESP)
983 NO_SUB_SUPER_D(8)
984 NO_SUB_SUPER_D(9)
985 NO_SUB_SUPER_D(10)
986 NO_SUB_SUPER_D(11)
987 NO_SUB_SUPER_D(12)
988 NO_SUB_SUPER_D(13)
989 NO_SUB_SUPER_D(14)
990 NO_SUB_SUPER_D(15)
991 NO_SUB_SUPER_D(16)
992 NO_SUB_SUPER_D(17)
993 NO_SUB_SUPER_D(18)
994 NO_SUB_SUPER_D(19)
995 NO_SUB_SUPER_D(20)
996 NO_SUB_SUPER_D(21)
997 NO_SUB_SUPER_D(22)
998 NO_SUB_SUPER_D(23)
999 NO_SUB_SUPER_D(24)
1000 NO_SUB_SUPER_D(25)
1001 NO_SUB_SUPER_D(26)
1002 NO_SUB_SUPER_D(27)
1003 NO_SUB_SUPER_D(28)
1004 NO_SUB_SUPER_D(29)
1005 NO_SUB_SUPER_D(30)
1006 NO_SUB_SUPER_D(31)
1007 }
1008 case 64:
1009 switch (Reg.id()) {
1010 DEFAULT_NOREG
1011 A_SUB_SUPER(RAX)
1012 D_SUB_SUPER(RDX)
1013 C_SUB_SUPER(RCX)
1014 B_SUB_SUPER(RBX)
1015 SI_SUB_SUPER(RSI)
1016 DI_SUB_SUPER(RDI)
1017 BP_SUB_SUPER(RBP)
1018 SP_SUB_SUPER(RSP)
1019 NO_SUB_SUPER_Q(8)
1020 NO_SUB_SUPER_Q(9)
1021 NO_SUB_SUPER_Q(10)
1022 NO_SUB_SUPER_Q(11)
1023 NO_SUB_SUPER_Q(12)
1024 NO_SUB_SUPER_Q(13)
1025 NO_SUB_SUPER_Q(14)
1026 NO_SUB_SUPER_Q(15)
1027 NO_SUB_SUPER_Q(16)
1028 NO_SUB_SUPER_Q(17)
1029 NO_SUB_SUPER_Q(18)
1030 NO_SUB_SUPER_Q(19)
1031 NO_SUB_SUPER_Q(20)
1032 NO_SUB_SUPER_Q(21)
1033 NO_SUB_SUPER_Q(22)
1034 NO_SUB_SUPER_Q(23)
1035 NO_SUB_SUPER_Q(24)
1036 NO_SUB_SUPER_Q(25)
1037 NO_SUB_SUPER_Q(26)
1038 NO_SUB_SUPER_Q(27)
1039 NO_SUB_SUPER_Q(28)
1040 NO_SUB_SUPER_Q(29)
1041 NO_SUB_SUPER_Q(30)
1042 NO_SUB_SUPER_Q(31)
1043 }
1044 }
1045}
1046