1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass XCoreMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15};
16static constexpr char XCoreSubRegIndexStrings[] = {
17 /* dummy */ 0
18};
19
20
21static constexpr uint32_t XCoreSubRegIndexNameOffsets[] = {
22 /* dummy */ 0
23};
24
25static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
26 { .Offset: 65535, .Size: 65535 },
27};
28
29
30static const LaneBitmask SubRegIndexLaneMaskTable[] = {
31 LaneBitmask::getAll(),
32 };
33
34
35
36static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
37 // Mode = 0 (DefaultMode)
38 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // RRegs
39 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GRRegs
40};
41static const uint32_t RRegsSubClassMask[] = {
42 0x00000003,
43};
44
45static const uint32_t GRRegsSubClassMask[] = {
46 0x00000002,
47};
48
49static const uint16_t SuperRegIdxSeqs[] = {
50 /* 0 */ 0,
51};
52
53static unsigned const GRRegsSuperclasses[] = {
54 XCore::RRegsRegClassID,
55};
56
57namespace XCore {
58
59// Register class instances
60 extern const TargetRegisterClass RRegsRegClass = {
61 .MC: &XCoreMCRegisterClasses[RRegsRegClassID],
62 .SubClassMask: RRegsSubClassMask,
63 .SuperRegIndices: SuperRegIdxSeqs + 0,
64 .LaneMask: LaneBitmask(0x0000000000000001),
65 .AllocationPriority: 0,
66 .GlobalPriority: false,
67 .TSFlags: 0x00, /* TSFlags */
68 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
69 .CoveredBySubRegs: false, /* CoveredBySubRegs */
70 .SuperClasses: nullptr, .SuperClassesSize: 0,
71 .OrderFunc: nullptr
72 };
73
74 extern const TargetRegisterClass GRRegsRegClass = {
75 .MC: &XCoreMCRegisterClasses[GRRegsRegClassID],
76 .SubClassMask: GRRegsSubClassMask,
77 .SuperRegIndices: SuperRegIdxSeqs + 0,
78 .LaneMask: LaneBitmask(0x0000000000000001),
79 .AllocationPriority: 0,
80 .GlobalPriority: false,
81 .TSFlags: 0x00, /* TSFlags */
82 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
83 .CoveredBySubRegs: false, /* CoveredBySubRegs */
84 .SuperClasses: GRRegsSuperclasses, .SuperClassesSize: 1,
85 .OrderFunc: nullptr
86 };
87
88
89} // namespace XCore
90namespace {
91
92 const TargetRegisterClass *const RegisterClasses[] = {
93 &XCore::RRegsRegClass,
94 &XCore::GRRegsRegClass,
95 };
96} // namespace
97
98static const uint8_t CostPerUseTable[] = {
990, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
100
101
102static const bool InAllocatableClassTable[] = {
103false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
104
105
106static const TargetRegisterInfoDesc XCoreRegInfoDesc = { // Extra Descriptors
107.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
108
109/// Get the weight in units of pressure for this register class.
110const RegClassWeight &XCoreGenRegisterInfo::
111getRegClassWeight(const TargetRegisterClass *RC) const {
112 static const RegClassWeight RCWeightTable[] = {
113 {.RegWeight: 0, .WeightLimit: 12}, // RRegs
114 {.RegWeight: 1, .WeightLimit: 12}, // GRRegs
115 };
116 return RCWeightTable[RC->getID()];
117}
118
119/// Get the weight in units of pressure for this register unit.
120unsigned XCoreGenRegisterInfo::
121getRegUnitWeight(MCRegUnit RegUnit) const {
122 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
123 // All register units have unit weight.
124 return 1;
125}
126
127
128// Get the number of dimensions of register pressure.
129unsigned XCoreGenRegisterInfo::getNumRegPressureSets() const {
130 return 1;
131}
132
133// Get the name of this register unit pressure set.
134const char *XCoreGenRegisterInfo::
135getRegPressureSetName(unsigned Idx) const {
136 static const char *PressureNameTable[] = {
137 "GRRegs",
138 };
139 return PressureNameTable[Idx];
140}
141
142// Get the register unit pressure limit for this dimension.
143// This limit must be adjusted dynamically for reserved registers.
144unsigned XCoreGenRegisterInfo::
145getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
146 static const uint8_t PressureLimitTable[] = {
147 12, // 0: GRRegs
148 };
149 return PressureLimitTable[Idx];
150}
151
152/// Table of pressure sets per register class or unit.
153static const int RCSetsTable[] = {
154 /* 0 */ 0, -1,
155};
156
157/// Get the dimensions of register pressure impacted by this register class.
158/// Returns a -1 terminated array of pressure set IDs
159const int *XCoreGenRegisterInfo::
160getRegClassPressureSets(const TargetRegisterClass *RC) const {
161 static const uint8_t RCSetStartTable[] = {
162 1,0,};
163 return &RCSetsTable[RCSetStartTable[RC->getID()]];
164}
165
166/// Get the dimensions of register pressure impacted by this register unit.
167/// Returns a -1 terminated array of pressure set IDs
168const int *XCoreGenRegisterInfo::
169getRegUnitPressureSets(MCRegUnit RegUnit) const {
170 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
171 static const uint8_t RUSetStartTable[] = {
172 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,};
173 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
174}
175
176extern const MCRegisterDesc XCoreRegDesc[];
177extern const int16_t XCoreRegDiffLists[];
178extern const LaneBitmask XCoreLaneMaskLists[];
179extern const char XCoreRegStrings[];
180extern const char XCoreRegClassStrings[];
181extern const MCPhysReg XCoreRegUnitRoots[][2];
182extern const uint16_t XCoreSubRegIdxLists[];
183extern const uint16_t XCoreRegEncodingTable[];
184// XCore Dwarf<->LLVM register mappings.
185extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[];
186extern const unsigned XCoreDwarfFlavour0Dwarf2LSize;
187
188extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[];
189extern const unsigned XCoreEHFlavour0Dwarf2LSize;
190
191extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[];
192extern const unsigned XCoreDwarfFlavour0L2DwarfSize;
193
194extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[];
195extern const unsigned XCoreEHFlavour0L2DwarfSize;
196
197
198XCoreGenRegisterInfo::
199XCoreGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
200 unsigned PC, unsigned HwMode)
201 : TargetRegisterInfo(&XCoreRegInfoDesc, RegisterClasses, RegisterClasses+2,
202 XCoreSubRegIndexStrings, XCoreSubRegIndexNameOffsets,
203 SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
204
205 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
206 InitMCRegisterInfo(D: XCoreRegDesc, NR: 17, RA, PC,
207 C: XCoreMCRegisterClasses, NC: 2,
208 RURoots: XCoreRegUnitRoots,
209 NRU: 16,
210 DL: XCoreRegDiffLists,
211 RUMS: XCoreLaneMaskLists,
212 Strings: XCoreRegStrings,
213 ClassStrings: XCoreRegClassStrings,
214 SubIndices: XCoreSubRegIdxLists,
215 NumIndices: 1,
216 RET: XCoreRegEncodingTable,
217 RUI: nullptr);
218
219 switch (DwarfFlavour) {
220 default:
221 llvm_unreachable("Unknown DWARF flavour");
222 case 0:
223 mapDwarfRegsToLLVMRegs(Map: XCoreDwarfFlavour0Dwarf2L, Size: XCoreDwarfFlavour0Dwarf2LSize, isEH: false);
224 break;
225 }
226 switch (EHFlavour) {
227 default:
228 llvm_unreachable("Unknown DWARF flavour");
229 case 0:
230 mapDwarfRegsToLLVMRegs(Map: XCoreEHFlavour0Dwarf2L, Size: XCoreEHFlavour0Dwarf2LSize, isEH: true);
231 break;
232 }
233 switch (DwarfFlavour) {
234 default:
235 llvm_unreachable("Unknown DWARF flavour");
236 case 0:
237 mapLLVMRegsToDwarfRegs(Map: XCoreDwarfFlavour0L2Dwarf, Size: XCoreDwarfFlavour0L2DwarfSize, isEH: false);
238 break;
239 }
240 switch (EHFlavour) {
241 default:
242 llvm_unreachable("Unknown DWARF flavour");
243 case 0:
244 mapLLVMRegsToDwarfRegs(Map: XCoreEHFlavour0L2Dwarf, Size: XCoreEHFlavour0L2DwarfSize, isEH: true);
245 break;
246 }
247}
248
249
250
251ArrayRef<const uint32_t *> XCoreGenRegisterInfo::getRegMasks() const {
252 return {};
253}
254
255bool XCoreGenRegisterInfo::
256isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
257 return
258 false;
259}
260
261bool XCoreGenRegisterInfo::
262isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
263 return
264 false;
265}
266
267bool XCoreGenRegisterInfo::
268isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
269 return
270 false;
271}
272
273bool XCoreGenRegisterInfo::
274isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
275 return
276 false;
277}
278
279bool XCoreGenRegisterInfo::
280isConstantPhysReg(MCRegister PhysReg) const {
281 return
282 false;
283}
284
285ArrayRef<const char *> XCoreGenRegisterInfo::getRegMaskNames() const {
286 return {};
287}
288
289const XCoreFrameLowering *
290XCoreGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
291 return static_cast<const XCoreFrameLowering *>(
292 MF.getSubtarget().getFrameLowering());
293}
294
295
296} // namespace llvm
297