1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<2, 28, 4, 2, 1, 1> XCoreMCRegisterClassStorage;
12
13static const MVT::SimpleValueType XCoreVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15};
16static constexpr char XCoreSubRegIndexStrings[] = {
17 /* dummy */ 0
18};
19
20
21static constexpr uint32_t XCoreSubRegIndexNameOffsets[] = {
22 /* dummy */ 0
23};
24
25static const TargetRegisterInfo::SubRegCoveredBits XCoreSubRegIdxRangeTable[] = {
26 { .Offset: 4294967295, .Size: 4294967295 },
27};
28
29
30static const LaneBitmask XCoreSubRegIndexLaneMaskTable[] = {
31 LaneBitmask::getAll(),
32 };
33
34
35
36static const TargetRegisterInfo::RegClassInfo XCoreRegClassInfos[] = {
37 // Mode = 0 (DefaultMode)
38 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*XCoreVTLists+*/.VTListOffset: 0 }, // RRegs
39 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*XCoreVTLists+*/.VTListOffset: 0 }, // GRRegs
40};
41
42static const uint8_t XCoreCostPerUseTable[] = {
430, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
44
45
46static const bool XCoreInAllocatableClassTable[] = {
47false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
48
49
50static const TargetRegisterInfoDesc XCoreRegInfoDesc = { // Extra Descriptors
51.CostPerUse: XCoreCostPerUseTable, .NumCosts: 1, .InAllocatableClass: XCoreInAllocatableClassTable};
52
53/// Get the weight in units of pressure for this register class.
54const RegClassWeight &XCoreGenRegisterInfo::
55getRegClassWeight(const TargetRegisterClass *RC) const {
56 static const RegClassWeight RCWeightTable[] = {
57 {.RegWeight: 0, .WeightLimit: 12}, // RRegs
58 {.RegWeight: 1, .WeightLimit: 12}, // GRRegs
59 };
60 return RCWeightTable[RC->getID()];
61}
62
63/// Get the weight in units of pressure for this register unit.
64unsigned XCoreGenRegisterInfo::
65getRegUnitWeight(MCRegUnit RegUnit) const {
66 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
67 // All register units have unit weight.
68 return 1;
69}
70
71
72// Get the number of dimensions of register pressure.
73unsigned XCoreGenRegisterInfo::getNumRegPressureSets() const {
74 return 1;
75}
76
77// Get the name of this register unit pressure set.
78const char *XCoreGenRegisterInfo::
79getRegPressureSetName(unsigned Idx) const {
80 static const char *PressureNameTable[] = {
81 "GRRegs",
82 };
83 return PressureNameTable[Idx];
84}
85
86// Get the register unit pressure limit for this dimension.
87// This limit must be adjusted dynamically for reserved registers.
88unsigned XCoreGenRegisterInfo::
89getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
90 static const uint8_t PressureLimitTable[] = {
91 12, // 0: GRRegs
92 };
93 return PressureLimitTable[Idx];
94}
95
96/// Get the register class for this pressure set with the largest
97/// `RegClassWeight::WeightLimit`.
98const TargetRegisterClass *XCoreGenRegisterInfo::
99getLargestRegClassForRegPressureSet(unsigned Idx) const {
100 static const uint8_t PSetRegClassTable[] = {
101 XCore::GRRegsRegClassID, // 0: GRRegs
102 };
103 return getRegClass(i: PSetRegClassTable[Idx]);
104}
105
106/// Table of pressure sets per register class or unit.
107static const int RCSetsTable[] = {
108 /* 0 */ 0, -1,
109};
110
111/// Get the dimensions of register pressure impacted by this register class.
112/// Returns a -1 terminated array of pressure set IDs
113const int *XCoreGenRegisterInfo::
114getRegClassPressureSets(const TargetRegisterClass *RC) const {
115 static const uint8_t RCSetStartTable[] = {
116 1,0,};
117 return &RCSetsTable[RCSetStartTable[RC->getID()]];
118}
119
120/// Get the dimensions of register pressure impacted by this register unit.
121/// Returns a -1 terminated array of pressure set IDs
122const int *XCoreGenRegisterInfo::
123getRegUnitPressureSets(MCRegUnit RegUnit) const {
124 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
125 static const uint8_t RUSetStartTable[] = {
126 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,};
127 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
128}
129
130
131// Register to minimal register class mapping
132
133const TargetRegisterClass *XCoreGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
134 static const uint16_t InvalidRegClassID = UINT16_MAX;
135
136 static const uint16_t Mapping[17] = {
137 InvalidRegClassID, // NoRegister
138 XCore::RRegsRegClassID, // CP
139 XCore::RRegsRegClassID, // DP
140 XCore::RRegsRegClassID, // LR
141 XCore::RRegsRegClassID, // SP
142 XCore::GRRegsRegClassID, // R0
143 XCore::GRRegsRegClassID, // R1
144 XCore::GRRegsRegClassID, // R2
145 XCore::GRRegsRegClassID, // R3
146 XCore::GRRegsRegClassID, // R4
147 XCore::GRRegsRegClassID, // R5
148 XCore::GRRegsRegClassID, // R6
149 XCore::GRRegsRegClassID, // R7
150 XCore::GRRegsRegClassID, // R8
151 XCore::GRRegsRegClassID, // R9
152 XCore::GRRegsRegClassID, // R10
153 XCore::GRRegsRegClassID, // R11
154 };
155
156 assert(Reg < ArrayRef(Mapping).size());
157 unsigned RCID = Mapping[Reg.id()];
158 if (RCID == InvalidRegClassID)
159 return nullptr;
160 return &XCoreMCRegisterClassStorage.Classes[RCID];
161}
162extern const MCRegisterDesc XCoreRegDesc[];
163extern const int16_t XCoreRegDiffLists[];
164extern const LaneBitmask XCoreLaneMaskLists[];
165extern const char XCoreRegStrings[];
166extern const char XCoreRegClassStrings[];
167extern const MCPhysReg XCoreRegUnitRoots[][2];
168extern const uint16_t XCoreSubRegIdxLists[];
169extern const uint16_t XCoreRegEncodingTable[];
170// XCore Dwarf<->LLVM register mappings.
171extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[];
172extern const unsigned XCoreDwarfFlavour0Dwarf2LSize;
173
174extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[];
175extern const unsigned XCoreEHFlavour0Dwarf2LSize;
176
177extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[];
178extern const unsigned XCoreDwarfFlavour0L2DwarfSize;
179
180extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[];
181extern const unsigned XCoreEHFlavour0L2DwarfSize;
182
183
184XCoreGenRegisterInfo::
185XCoreGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
186 unsigned PC, unsigned HwMode)
187 : TargetRegisterInfo(&XCoreRegInfoDesc,
188 XCoreSubRegIndexStrings, XCoreSubRegIndexNameOffsets,
189 XCoreSubRegIdxRangeTable, XCoreSubRegIndexLaneMaskTable,
190
191 LaneBitmask(0xFFFFFFFFFFFFFFFF), XCoreRegClassInfos, XCoreVTLists, HwMode) {
192 InitMCRegisterInfo(D: XCoreRegDesc, NR: 17, RA, PC,
193 C: &getXCoreMCRegisterClass(RC: 0), NC: 2, RURoots: XCoreRegUnitRoots, NRU: 16, DL: XCoreRegDiffLists,
194 RUMS: XCoreLaneMaskLists, Strings: XCoreRegStrings, ClassStrings: XCoreRegClassStrings, SubIndices: XCoreSubRegIdxLists, NumIndices: 1,
195 RET: XCoreRegEncodingTable, RUI: nullptr);
196
197 switch (DwarfFlavour) {
198 default:
199 llvm_unreachable("Unknown DWARF flavour");
200 case 0:
201 mapDwarfRegsToLLVMRegs(Map: XCoreDwarfFlavour0Dwarf2L, Size: XCoreDwarfFlavour0Dwarf2LSize, isEH: false);
202 break;
203 }
204 switch (EHFlavour) {
205 default:
206 llvm_unreachable("Unknown DWARF flavour");
207 case 0:
208 mapDwarfRegsToLLVMRegs(Map: XCoreEHFlavour0Dwarf2L, Size: XCoreEHFlavour0Dwarf2LSize, isEH: true);
209 break;
210 }
211 switch (DwarfFlavour) {
212 default:
213 llvm_unreachable("Unknown DWARF flavour");
214 case 0:
215 mapLLVMRegsToDwarfRegs(Map: XCoreDwarfFlavour0L2Dwarf, Size: XCoreDwarfFlavour0L2DwarfSize, isEH: false);
216 break;
217 }
218 switch (EHFlavour) {
219 default:
220 llvm_unreachable("Unknown DWARF flavour");
221 case 0:
222 mapLLVMRegsToDwarfRegs(Map: XCoreEHFlavour0L2Dwarf, Size: XCoreEHFlavour0L2DwarfSize, isEH: true);
223 break;
224 }
225}
226
227
228
229ArrayRef<const uint32_t *> XCoreGenRegisterInfo::getRegMasks() const {
230 return {};
231}
232
233bool XCoreGenRegisterInfo::
234isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
235 return
236 false;
237}
238
239bool XCoreGenRegisterInfo::
240isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
241 return
242 false;
243}
244
245bool XCoreGenRegisterInfo::
246isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
247 return
248 false;
249}
250
251bool XCoreGenRegisterInfo::
252isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
253 return
254 false;
255}
256
257bool XCoreGenRegisterInfo::
258isConstantPhysReg(MCRegister PhysReg) const {
259 return
260 false;
261}
262
263ArrayRef<const char *> XCoreGenRegisterInfo::getRegMaskNames() const {
264 return {};
265}
266
267const XCoreFrameLowering *
268XCoreGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
269 return static_cast<const XCoreFrameLowering *>(
270 MF.getSubtarget().getFrameLowering());
271}
272
273
274} // namespace llvm
275