1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass XCoreMCRegisterClasses[];
12
13static const MVT::SimpleValueType XCoreVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15};
16static constexpr char XCoreSubRegIndexStrings[] = {
17 /* dummy */ 0
18};
19
20
21static constexpr uint32_t XCoreSubRegIndexNameOffsets[] = {
22 /* dummy */ 0
23};
24
25static const TargetRegisterInfo::SubRegCoveredBits XCoreSubRegIdxRangeTable[] = {
26 { .Offset: 4294967295, .Size: 4294967295 },
27};
28
29
30static const LaneBitmask XCoreSubRegIndexLaneMaskTable[] = {
31 LaneBitmask::getAll(),
32 };
33
34
35
36static const TargetRegisterInfo::RegClassInfo XCoreRegClassInfos[] = {
37 // Mode = 0 (DefaultMode)
38 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*XCoreVTLists+*/.VTListOffset: 0 }, // RRegs
39 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*XCoreVTLists+*/.VTListOffset: 0 }, // GRRegs
40};
41static const uint32_t RRegsSubClassMask[] = {
42 0x00000003,
43};
44
45static const uint32_t GRRegsSubClassMask[] = {
46 0x00000002,
47};
48
49static const uint16_t SuperRegIdxSeqs[] = {
50 /* 0 */ 0,
51};
52
53static unsigned const GRRegsSuperclasses[] = {
54 XCore::RRegsRegClassID,
55};
56
57namespace XCore {
58
59// Register class instances.
60 extern const TargetRegisterClass RRegsRegClass = {
61 .MC: &XCoreMCRegisterClasses[RRegsRegClassID],
62 .SubClassMask: RRegsSubClassMask,
63 .SuperRegIndices: SuperRegIdxSeqs + 0,
64 .LaneMask: LaneBitmask(0x0000000000000001),
65 .AllocationPriority: 0,
66 .GlobalPriority: false,
67 .TSFlags: 0x00, /* TSFlags */
68 .SpillStackID: 0, /* SpillStackID */
69 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
70 .CoveredBySubRegs: false, /* CoveredBySubRegs */
71 .SuperClasses: nullptr, .SuperClassesSize: 0,
72 .OrderFunc: nullptr
73 };
74
75 extern const TargetRegisterClass GRRegsRegClass = {
76 .MC: &XCoreMCRegisterClasses[GRRegsRegClassID],
77 .SubClassMask: GRRegsSubClassMask,
78 .SuperRegIndices: SuperRegIdxSeqs + 0,
79 .LaneMask: LaneBitmask(0x0000000000000001),
80 .AllocationPriority: 0,
81 .GlobalPriority: false,
82 .TSFlags: 0x00, /* TSFlags */
83 .SpillStackID: 0, /* SpillStackID */
84 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
85 .CoveredBySubRegs: false, /* CoveredBySubRegs */
86 .SuperClasses: GRRegsSuperclasses, .SuperClassesSize: 1,
87 .OrderFunc: nullptr
88 };
89
90
91} // namespace XCore
92static const TargetRegisterClass *const XCoreRegisterClasses[] = {
93 &XCore::RRegsRegClass,
94 &XCore::GRRegsRegClass,
95 };
96
97static const uint8_t XCoreCostPerUseTable[] = {
980, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
99
100
101static const bool XCoreInAllocatableClassTable[] = {
102false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
103
104
105static const TargetRegisterInfoDesc XCoreRegInfoDesc = { // Extra Descriptors
106.CostPerUse: XCoreCostPerUseTable, .NumCosts: 1, .InAllocatableClass: XCoreInAllocatableClassTable};
107
108/// Get the weight in units of pressure for this register class.
109const RegClassWeight &XCoreGenRegisterInfo::
110getRegClassWeight(const TargetRegisterClass *RC) const {
111 static const RegClassWeight RCWeightTable[] = {
112 {.RegWeight: 0, .WeightLimit: 12}, // RRegs
113 {.RegWeight: 1, .WeightLimit: 12}, // GRRegs
114 };
115 return RCWeightTable[RC->getID()];
116}
117
118/// Get the weight in units of pressure for this register unit.
119unsigned XCoreGenRegisterInfo::
120getRegUnitWeight(MCRegUnit RegUnit) const {
121 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
122 // All register units have unit weight.
123 return 1;
124}
125
126
127// Get the number of dimensions of register pressure.
128unsigned XCoreGenRegisterInfo::getNumRegPressureSets() const {
129 return 1;
130}
131
132// Get the name of this register unit pressure set.
133const char *XCoreGenRegisterInfo::
134getRegPressureSetName(unsigned Idx) const {
135 static const char *PressureNameTable[] = {
136 "GRRegs",
137 };
138 return PressureNameTable[Idx];
139}
140
141// Get the register unit pressure limit for this dimension.
142// This limit must be adjusted dynamically for reserved registers.
143unsigned XCoreGenRegisterInfo::
144getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
145 static const uint8_t PressureLimitTable[] = {
146 12, // 0: GRRegs
147 };
148 return PressureLimitTable[Idx];
149}
150
151/// Table of pressure sets per register class or unit.
152static const int RCSetsTable[] = {
153 /* 0 */ 0, -1,
154};
155
156/// Get the dimensions of register pressure impacted by this register class.
157/// Returns a -1 terminated array of pressure set IDs
158const int *XCoreGenRegisterInfo::
159getRegClassPressureSets(const TargetRegisterClass *RC) const {
160 static const uint8_t RCSetStartTable[] = {
161 1,0,};
162 return &RCSetsTable[RCSetStartTable[RC->getID()]];
163}
164
165/// Get the dimensions of register pressure impacted by this register unit.
166/// Returns a -1 terminated array of pressure set IDs
167const int *XCoreGenRegisterInfo::
168getRegUnitPressureSets(MCRegUnit RegUnit) const {
169 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
170 static const uint8_t RUSetStartTable[] = {
171 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,};
172 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
173}
174
175
176// Register to minimal register class mapping
177
178const TargetRegisterClass *XCoreGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
179 static const uint16_t InvalidRegClassID = UINT16_MAX;
180
181 static const uint16_t Mapping[17] = {
182 InvalidRegClassID, // NoRegister
183 XCore::RRegsRegClassID, // CP
184 XCore::RRegsRegClassID, // DP
185 XCore::RRegsRegClassID, // LR
186 XCore::RRegsRegClassID, // SP
187 XCore::GRRegsRegClassID, // R0
188 XCore::GRRegsRegClassID, // R1
189 XCore::GRRegsRegClassID, // R2
190 XCore::GRRegsRegClassID, // R3
191 XCore::GRRegsRegClassID, // R4
192 XCore::GRRegsRegClassID, // R5
193 XCore::GRRegsRegClassID, // R6
194 XCore::GRRegsRegClassID, // R7
195 XCore::GRRegsRegClassID, // R8
196 XCore::GRRegsRegClassID, // R9
197 XCore::GRRegsRegClassID, // R10
198 XCore::GRRegsRegClassID, // R11
199 };
200
201 assert(Reg < ArrayRef(Mapping).size());
202 unsigned RCID = Mapping[Reg.id()];
203 if (RCID == InvalidRegClassID)
204 return nullptr;
205 return XCoreRegisterClasses[RCID];
206}
207extern const MCRegisterDesc XCoreRegDesc[];
208extern const int16_t XCoreRegDiffLists[];
209extern const LaneBitmask XCoreLaneMaskLists[];
210extern const char XCoreRegStrings[];
211extern const char XCoreRegClassStrings[];
212extern const MCPhysReg XCoreRegUnitRoots[][2];
213extern const uint16_t XCoreSubRegIdxLists[];
214extern const uint16_t XCoreRegEncodingTable[];
215// XCore Dwarf<->LLVM register mappings.
216extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[];
217extern const unsigned XCoreDwarfFlavour0Dwarf2LSize;
218
219extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[];
220extern const unsigned XCoreEHFlavour0Dwarf2LSize;
221
222extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[];
223extern const unsigned XCoreDwarfFlavour0L2DwarfSize;
224
225extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[];
226extern const unsigned XCoreEHFlavour0L2DwarfSize;
227
228
229XCoreGenRegisterInfo::
230XCoreGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
231 unsigned PC, unsigned HwMode)
232 : TargetRegisterInfo(&XCoreRegInfoDesc, XCoreRegisterClasses,
233 XCoreSubRegIndexStrings, XCoreSubRegIndexNameOffsets,
234 XCoreSubRegIdxRangeTable, XCoreSubRegIndexLaneMaskTable,
235
236 LaneBitmask(0xFFFFFFFFFFFFFFFF), XCoreRegClassInfos, XCoreVTLists, HwMode) {
237 InitMCRegisterInfo(D: XCoreRegDesc, NR: 17, RA, PC,
238 C: XCoreMCRegisterClasses, NC: 2, RURoots: XCoreRegUnitRoots, NRU: 16, DL: XCoreRegDiffLists,
239 RUMS: XCoreLaneMaskLists, Strings: XCoreRegStrings, ClassStrings: XCoreRegClassStrings, SubIndices: XCoreSubRegIdxLists, NumIndices: 1,
240 RET: XCoreRegEncodingTable, RUI: nullptr);
241
242 switch (DwarfFlavour) {
243 default:
244 llvm_unreachable("Unknown DWARF flavour");
245 case 0:
246 mapDwarfRegsToLLVMRegs(Map: XCoreDwarfFlavour0Dwarf2L, Size: XCoreDwarfFlavour0Dwarf2LSize, isEH: false);
247 break;
248 }
249 switch (EHFlavour) {
250 default:
251 llvm_unreachable("Unknown DWARF flavour");
252 case 0:
253 mapDwarfRegsToLLVMRegs(Map: XCoreEHFlavour0Dwarf2L, Size: XCoreEHFlavour0Dwarf2LSize, isEH: true);
254 break;
255 }
256 switch (DwarfFlavour) {
257 default:
258 llvm_unreachable("Unknown DWARF flavour");
259 case 0:
260 mapLLVMRegsToDwarfRegs(Map: XCoreDwarfFlavour0L2Dwarf, Size: XCoreDwarfFlavour0L2DwarfSize, isEH: false);
261 break;
262 }
263 switch (EHFlavour) {
264 default:
265 llvm_unreachable("Unknown DWARF flavour");
266 case 0:
267 mapLLVMRegsToDwarfRegs(Map: XCoreEHFlavour0L2Dwarf, Size: XCoreEHFlavour0L2DwarfSize, isEH: true);
268 break;
269 }
270}
271
272
273
274ArrayRef<const uint32_t *> XCoreGenRegisterInfo::getRegMasks() const {
275 return {};
276}
277
278bool XCoreGenRegisterInfo::
279isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
280 return
281 false;
282}
283
284bool XCoreGenRegisterInfo::
285isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
286 return
287 false;
288}
289
290bool XCoreGenRegisterInfo::
291isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
292 return
293 false;
294}
295
296bool XCoreGenRegisterInfo::
297isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
298 return
299 false;
300}
301
302bool XCoreGenRegisterInfo::
303isConstantPhysReg(MCRegister PhysReg) const {
304 return
305 false;
306}
307
308ArrayRef<const char *> XCoreGenRegisterInfo::getRegMaskNames() const {
309 return {};
310}
311
312const XCoreFrameLowering *
313XCoreGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
314 return static_cast<const XCoreFrameLowering *>(
315 MF.getSubtarget().getFrameLowering());
316}
317
318
319} // namespace llvm
320