1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass XCoreMCRegisterClasses[];
12
13static const MVT::SimpleValueType XCoreVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15};
16static constexpr char XCoreSubRegIndexStrings[] = {
17 /* dummy */ 0
18};
19
20
21static constexpr uint32_t XCoreSubRegIndexNameOffsets[] = {
22 /* dummy */ 0
23};
24
25static const TargetRegisterInfo::SubRegCoveredBits XCoreSubRegIdxRangeTable[] = {
26 { .Offset: 65535, .Size: 65535 },
27};
28
29
30static const LaneBitmask XCoreSubRegIndexLaneMaskTable[] = {
31 LaneBitmask::getAll(),
32 };
33
34
35
36static const TargetRegisterInfo::RegClassInfo XCoreRegClassInfos[] = {
37 // Mode = 0 (DefaultMode)
38 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*XCoreVTLists+*/.VTListOffset: 0 }, // RRegs
39 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*XCoreVTLists+*/.VTListOffset: 0 }, // GRRegs
40};
41static const uint32_t RRegsSubClassMask[] = {
42 0x00000003,
43};
44
45static const uint32_t GRRegsSubClassMask[] = {
46 0x00000002,
47};
48
49static const uint16_t SuperRegIdxSeqs[] = {
50 /* 0 */ 0,
51};
52
53static unsigned const GRRegsSuperclasses[] = {
54 XCore::RRegsRegClassID,
55};
56
57namespace XCore {
58
59// Register class instances.
60 extern const TargetRegisterClass RRegsRegClass = {
61 .MC: &XCoreMCRegisterClasses[RRegsRegClassID],
62 .SubClassMask: RRegsSubClassMask,
63 .SuperRegIndices: SuperRegIdxSeqs + 0,
64 .LaneMask: LaneBitmask(0x0000000000000001),
65 .AllocationPriority: 0,
66 .GlobalPriority: false,
67 .TSFlags: 0x00, /* TSFlags */
68 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
69 .CoveredBySubRegs: false, /* CoveredBySubRegs */
70 .SuperClasses: nullptr, .SuperClassesSize: 0,
71 .OrderFunc: nullptr
72 };
73
74 extern const TargetRegisterClass GRRegsRegClass = {
75 .MC: &XCoreMCRegisterClasses[GRRegsRegClassID],
76 .SubClassMask: GRRegsSubClassMask,
77 .SuperRegIndices: SuperRegIdxSeqs + 0,
78 .LaneMask: LaneBitmask(0x0000000000000001),
79 .AllocationPriority: 0,
80 .GlobalPriority: false,
81 .TSFlags: 0x00, /* TSFlags */
82 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
83 .CoveredBySubRegs: false, /* CoveredBySubRegs */
84 .SuperClasses: GRRegsSuperclasses, .SuperClassesSize: 1,
85 .OrderFunc: nullptr
86 };
87
88
89} // namespace XCore
90static const TargetRegisterClass *const XCoreRegisterClasses[] = {
91 &XCore::RRegsRegClass,
92 &XCore::GRRegsRegClass,
93 };
94
95static const uint8_t XCoreCostPerUseTable[] = {
960, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
97
98
99static const bool XCoreInAllocatableClassTable[] = {
100false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
101
102
103static const TargetRegisterInfoDesc XCoreRegInfoDesc = { // Extra Descriptors
104.CostPerUse: XCoreCostPerUseTable, .NumCosts: 1, .InAllocatableClass: XCoreInAllocatableClassTable};
105
106/// Get the weight in units of pressure for this register class.
107const RegClassWeight &XCoreGenRegisterInfo::
108getRegClassWeight(const TargetRegisterClass *RC) const {
109 static const RegClassWeight RCWeightTable[] = {
110 {.RegWeight: 0, .WeightLimit: 12}, // RRegs
111 {.RegWeight: 1, .WeightLimit: 12}, // GRRegs
112 };
113 return RCWeightTable[RC->getID()];
114}
115
116/// Get the weight in units of pressure for this register unit.
117unsigned XCoreGenRegisterInfo::
118getRegUnitWeight(MCRegUnit RegUnit) const {
119 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
120 // All register units have unit weight.
121 return 1;
122}
123
124
125// Get the number of dimensions of register pressure.
126unsigned XCoreGenRegisterInfo::getNumRegPressureSets() const {
127 return 1;
128}
129
130// Get the name of this register unit pressure set.
131const char *XCoreGenRegisterInfo::
132getRegPressureSetName(unsigned Idx) const {
133 static const char *PressureNameTable[] = {
134 "GRRegs",
135 };
136 return PressureNameTable[Idx];
137}
138
139// Get the register unit pressure limit for this dimension.
140// This limit must be adjusted dynamically for reserved registers.
141unsigned XCoreGenRegisterInfo::
142getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
143 static const uint8_t PressureLimitTable[] = {
144 12, // 0: GRRegs
145 };
146 return PressureLimitTable[Idx];
147}
148
149/// Table of pressure sets per register class or unit.
150static const int RCSetsTable[] = {
151 /* 0 */ 0, -1,
152};
153
154/// Get the dimensions of register pressure impacted by this register class.
155/// Returns a -1 terminated array of pressure set IDs
156const int *XCoreGenRegisterInfo::
157getRegClassPressureSets(const TargetRegisterClass *RC) const {
158 static const uint8_t RCSetStartTable[] = {
159 1,0,};
160 return &RCSetsTable[RCSetStartTable[RC->getID()]];
161}
162
163/// Get the dimensions of register pressure impacted by this register unit.
164/// Returns a -1 terminated array of pressure set IDs
165const int *XCoreGenRegisterInfo::
166getRegUnitPressureSets(MCRegUnit RegUnit) const {
167 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
168 static const uint8_t RUSetStartTable[] = {
169 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,};
170 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
171}
172
173extern const MCRegisterDesc XCoreRegDesc[];
174extern const int16_t XCoreRegDiffLists[];
175extern const LaneBitmask XCoreLaneMaskLists[];
176extern const char XCoreRegStrings[];
177extern const char XCoreRegClassStrings[];
178extern const MCPhysReg XCoreRegUnitRoots[][2];
179extern const uint16_t XCoreSubRegIdxLists[];
180extern const uint16_t XCoreRegEncodingTable[];
181// XCore Dwarf<->LLVM register mappings.
182extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[];
183extern const unsigned XCoreDwarfFlavour0Dwarf2LSize;
184
185extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[];
186extern const unsigned XCoreEHFlavour0Dwarf2LSize;
187
188extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[];
189extern const unsigned XCoreDwarfFlavour0L2DwarfSize;
190
191extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[];
192extern const unsigned XCoreEHFlavour0L2DwarfSize;
193
194
195XCoreGenRegisterInfo::
196XCoreGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
197 unsigned PC, unsigned HwMode)
198 : TargetRegisterInfo(&XCoreRegInfoDesc, XCoreRegisterClasses,
199 XCoreSubRegIndexStrings, XCoreSubRegIndexNameOffsets,
200 XCoreSubRegIdxRangeTable, XCoreSubRegIndexLaneMaskTable,
201
202 LaneBitmask(0xFFFFFFFFFFFFFFFF), XCoreRegClassInfos, XCoreVTLists, HwMode) {
203 InitMCRegisterInfo(D: XCoreRegDesc, NR: 17, RA, PC,
204 C: XCoreMCRegisterClasses, NC: 2, RURoots: XCoreRegUnitRoots, NRU: 16, DL: XCoreRegDiffLists,
205 RUMS: XCoreLaneMaskLists, Strings: XCoreRegStrings, ClassStrings: XCoreRegClassStrings, SubIndices: XCoreSubRegIdxLists, NumIndices: 1,
206 RET: XCoreRegEncodingTable, RUI: nullptr);
207
208 switch (DwarfFlavour) {
209 default:
210 llvm_unreachable("Unknown DWARF flavour");
211 case 0:
212 mapDwarfRegsToLLVMRegs(Map: XCoreDwarfFlavour0Dwarf2L, Size: XCoreDwarfFlavour0Dwarf2LSize, isEH: false);
213 break;
214 }
215 switch (EHFlavour) {
216 default:
217 llvm_unreachable("Unknown DWARF flavour");
218 case 0:
219 mapDwarfRegsToLLVMRegs(Map: XCoreEHFlavour0Dwarf2L, Size: XCoreEHFlavour0Dwarf2LSize, isEH: true);
220 break;
221 }
222 switch (DwarfFlavour) {
223 default:
224 llvm_unreachable("Unknown DWARF flavour");
225 case 0:
226 mapLLVMRegsToDwarfRegs(Map: XCoreDwarfFlavour0L2Dwarf, Size: XCoreDwarfFlavour0L2DwarfSize, isEH: false);
227 break;
228 }
229 switch (EHFlavour) {
230 default:
231 llvm_unreachable("Unknown DWARF flavour");
232 case 0:
233 mapLLVMRegsToDwarfRegs(Map: XCoreEHFlavour0L2Dwarf, Size: XCoreEHFlavour0L2DwarfSize, isEH: true);
234 break;
235 }
236}
237
238
239
240ArrayRef<const uint32_t *> XCoreGenRegisterInfo::getRegMasks() const {
241 return {};
242}
243
244bool XCoreGenRegisterInfo::
245isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
246 return
247 false;
248}
249
250bool XCoreGenRegisterInfo::
251isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
252 return
253 false;
254}
255
256bool XCoreGenRegisterInfo::
257isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
258 return
259 false;
260}
261
262bool XCoreGenRegisterInfo::
263isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
264 return
265 false;
266}
267
268bool XCoreGenRegisterInfo::
269isConstantPhysReg(MCRegister PhysReg) const {
270 return
271 false;
272}
273
274ArrayRef<const char *> XCoreGenRegisterInfo::getRegMaskNames() const {
275 return {};
276}
277
278const XCoreFrameLowering *
279XCoreGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
280 return static_cast<const XCoreFrameLowering *>(
281 MF.getSubtarget().getFrameLowering());
282}
283
284
285} // namespace llvm
286