1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<2, 28, 6, 2, 1, 1> XCoreMCRegisterClassStorage;
12
13static const MVT::SimpleValueType XCoreVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15};
16static constexpr char XCoreSubRegIndexStrings[] = {
17 /* dummy */ 0
18};
19
20
21static constexpr uint32_t XCoreSubRegIndexNameOffsets[] = {
22 /* dummy */ 0
23};
24
25static const TargetRegisterInfo::SubRegCoveredBits XCoreSubRegIdxRangeTable[] = {
26 { .Offset: 4294967295, .Size: 4294967295 },
27};
28
29
30static const LaneBitmask XCoreSubRegIndexLaneMaskTable[] = {
31 LaneBitmask::getAll(),
32 };
33
34
35
36static const TargetRegisterInfo::RegClassInfo XCoreRegClassInfos[] = {
37 // Mode = 0 (DefaultMode)
38 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*XCoreVTLists+*/.VTListOffset: 0 }, // RRegs
39 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*XCoreVTLists+*/.VTListOffset: 0 }, // GRRegs
40};
41
42static const uint8_t XCoreCostPerUseTable[] = {
430, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
44
45
46static const bool XCoreInAllocatableClassTable[] = {
47false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
48
49
50static const TargetRegisterInfoDesc XCoreRegInfoDesc = { // Extra Descriptors
51.CostPerUse: XCoreCostPerUseTable, .NumCosts: 1, .InAllocatableClass: XCoreInAllocatableClassTable};
52
53/// Get the weight in units of pressure for this register class.
54const RegClassWeight &XCoreGenRegisterInfo::
55getRegClassWeight(const TargetRegisterClass *RC) const {
56 static const RegClassWeight RCWeightTable[] = {
57 {.RegWeight: 0, .WeightLimit: 12}, // RRegs
58 {.RegWeight: 1, .WeightLimit: 12}, // GRRegs
59 };
60 return RCWeightTable[RC->getID()];
61}
62
63/// Get the weight in units of pressure for this register unit.
64unsigned XCoreGenRegisterInfo::
65getRegUnitWeight(MCRegUnit RegUnit) const {
66 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
67 // All register units have unit weight.
68 return 1;
69}
70
71
72// Get the number of dimensions of register pressure.
73unsigned XCoreGenRegisterInfo::getNumRegPressureSets() const {
74 return 1;
75}
76
77// Get the name of this register unit pressure set.
78const char *XCoreGenRegisterInfo::
79getRegPressureSetName(unsigned Idx) const {
80 static const char *PressureNameTable[] = {
81 "GRRegs",
82 };
83 return PressureNameTable[Idx];
84}
85
86// Get the register unit pressure limit for this dimension.
87// This limit must be adjusted dynamically for reserved registers.
88unsigned XCoreGenRegisterInfo::
89getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
90 static const uint8_t PressureLimitTable[] = {
91 12, // 0: GRRegs
92 };
93 return PressureLimitTable[Idx];
94}
95
96/// Table of pressure sets per register class or unit.
97static const int RCSetsTable[] = {
98 /* 0 */ 0, -1,
99};
100
101/// Get the dimensions of register pressure impacted by this register class.
102/// Returns a -1 terminated array of pressure set IDs
103const int *XCoreGenRegisterInfo::
104getRegClassPressureSets(const TargetRegisterClass *RC) const {
105 static const uint8_t RCSetStartTable[] = {
106 1,0,};
107 return &RCSetsTable[RCSetStartTable[RC->getID()]];
108}
109
110/// Get the dimensions of register pressure impacted by this register unit.
111/// Returns a -1 terminated array of pressure set IDs
112const int *XCoreGenRegisterInfo::
113getRegUnitPressureSets(MCRegUnit RegUnit) const {
114 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
115 static const uint8_t RUSetStartTable[] = {
116 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,};
117 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
118}
119
120
121// Register to minimal register class mapping
122
123const TargetRegisterClass *XCoreGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
124 static const uint16_t InvalidRegClassID = UINT16_MAX;
125
126 static const uint16_t Mapping[17] = {
127 InvalidRegClassID, // NoRegister
128 XCore::RRegsRegClassID, // CP
129 XCore::RRegsRegClassID, // DP
130 XCore::RRegsRegClassID, // LR
131 XCore::RRegsRegClassID, // SP
132 XCore::GRRegsRegClassID, // R0
133 XCore::GRRegsRegClassID, // R1
134 XCore::GRRegsRegClassID, // R2
135 XCore::GRRegsRegClassID, // R3
136 XCore::GRRegsRegClassID, // R4
137 XCore::GRRegsRegClassID, // R5
138 XCore::GRRegsRegClassID, // R6
139 XCore::GRRegsRegClassID, // R7
140 XCore::GRRegsRegClassID, // R8
141 XCore::GRRegsRegClassID, // R9
142 XCore::GRRegsRegClassID, // R10
143 XCore::GRRegsRegClassID, // R11
144 };
145
146 assert(Reg < ArrayRef(Mapping).size());
147 unsigned RCID = Mapping[Reg.id()];
148 if (RCID == InvalidRegClassID)
149 return nullptr;
150 return &XCoreMCRegisterClassStorage.Classes[RCID];
151}
152extern const MCRegisterDesc XCoreRegDesc[];
153extern const int16_t XCoreRegDiffLists[];
154extern const LaneBitmask XCoreLaneMaskLists[];
155extern const char XCoreRegStrings[];
156extern const char XCoreRegClassStrings[];
157extern const MCPhysReg XCoreRegUnitRoots[][2];
158extern const uint16_t XCoreSubRegIdxLists[];
159extern const uint16_t XCoreRegEncodingTable[];
160// XCore Dwarf<->LLVM register mappings.
161extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[];
162extern const unsigned XCoreDwarfFlavour0Dwarf2LSize;
163
164extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[];
165extern const unsigned XCoreEHFlavour0Dwarf2LSize;
166
167extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[];
168extern const unsigned XCoreDwarfFlavour0L2DwarfSize;
169
170extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[];
171extern const unsigned XCoreEHFlavour0L2DwarfSize;
172
173
174XCoreGenRegisterInfo::
175XCoreGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
176 unsigned PC, unsigned HwMode)
177 : TargetRegisterInfo(&XCoreRegInfoDesc,
178 XCoreSubRegIndexStrings, XCoreSubRegIndexNameOffsets,
179 XCoreSubRegIdxRangeTable, XCoreSubRegIndexLaneMaskTable,
180
181 LaneBitmask(0xFFFFFFFFFFFFFFFF), XCoreRegClassInfos, XCoreVTLists, HwMode) {
182 InitMCRegisterInfo(D: XCoreRegDesc, NR: 17, RA, PC,
183 C: &getXCoreMCRegisterClass(RC: 0), NC: 2, RURoots: XCoreRegUnitRoots, NRU: 16, DL: XCoreRegDiffLists,
184 RUMS: XCoreLaneMaskLists, Strings: XCoreRegStrings, ClassStrings: XCoreRegClassStrings, SubIndices: XCoreSubRegIdxLists, NumIndices: 1,
185 RET: XCoreRegEncodingTable, RUI: nullptr);
186
187 switch (DwarfFlavour) {
188 default:
189 llvm_unreachable("Unknown DWARF flavour");
190 case 0:
191 mapDwarfRegsToLLVMRegs(Map: XCoreDwarfFlavour0Dwarf2L, Size: XCoreDwarfFlavour0Dwarf2LSize, isEH: false);
192 break;
193 }
194 switch (EHFlavour) {
195 default:
196 llvm_unreachable("Unknown DWARF flavour");
197 case 0:
198 mapDwarfRegsToLLVMRegs(Map: XCoreEHFlavour0Dwarf2L, Size: XCoreEHFlavour0Dwarf2LSize, isEH: true);
199 break;
200 }
201 switch (DwarfFlavour) {
202 default:
203 llvm_unreachable("Unknown DWARF flavour");
204 case 0:
205 mapLLVMRegsToDwarfRegs(Map: XCoreDwarfFlavour0L2Dwarf, Size: XCoreDwarfFlavour0L2DwarfSize, isEH: false);
206 break;
207 }
208 switch (EHFlavour) {
209 default:
210 llvm_unreachable("Unknown DWARF flavour");
211 case 0:
212 mapLLVMRegsToDwarfRegs(Map: XCoreEHFlavour0L2Dwarf, Size: XCoreEHFlavour0L2DwarfSize, isEH: true);
213 break;
214 }
215}
216
217
218
219ArrayRef<const uint32_t *> XCoreGenRegisterInfo::getRegMasks() const {
220 return {};
221}
222
223bool XCoreGenRegisterInfo::
224isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
225 return
226 false;
227}
228
229bool XCoreGenRegisterInfo::
230isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
231 return
232 false;
233}
234
235bool XCoreGenRegisterInfo::
236isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
237 return
238 false;
239}
240
241bool XCoreGenRegisterInfo::
242isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
243 return
244 false;
245}
246
247bool XCoreGenRegisterInfo::
248isConstantPhysReg(MCRegister PhysReg) const {
249 return
250 false;
251}
252
253ArrayRef<const char *> XCoreGenRegisterInfo::getRegMaskNames() const {
254 return {};
255}
256
257const XCoreFrameLowering *
258XCoreGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
259 return static_cast<const XCoreFrameLowering *>(
260 MF.getSubtarget().getFrameLowering());
261}
262
263
264} // namespace llvm
265