1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass XCoreMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15};
16
17static const char *SubRegIndexNameTable[] = { "" };
18
19static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
20 { .Offset: 65535, .Size: 65535 },
21};
22
23
24static const LaneBitmask SubRegIndexLaneMaskTable[] = {
25 LaneBitmask::getAll(),
26 };
27
28
29
30static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
31 // Mode = 0 (Default)
32 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // RRegs
33 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // GRRegs
34};
35static const uint32_t RRegsSubClassMask[] = {
36 0x00000003,
37};
38
39static const uint32_t GRRegsSubClassMask[] = {
40 0x00000002,
41};
42
43static const uint16_t SuperRegIdxSeqs[] = {
44 /* 0 */ 0,
45};
46
47static unsigned const GRRegsSuperclasses[] = {
48 XCore::RRegsRegClassID,
49};
50
51
52namespace XCore { // Register class instances
53 extern const TargetRegisterClass RRegsRegClass = {
54 .MC: &XCoreMCRegisterClasses[RRegsRegClassID],
55 .SubClassMask: RRegsSubClassMask,
56 .SuperRegIndices: SuperRegIdxSeqs + 0,
57 .LaneMask: LaneBitmask(0x0000000000000001),
58 .AllocationPriority: 0,
59 .GlobalPriority: false,
60 .TSFlags: 0x00, /* TSFlags */
61 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
62 .CoveredBySubRegs: false, /* CoveredBySubRegs */
63 .SuperClasses: nullptr, .SuperClassesSize: 0,
64 .OrderFunc: nullptr
65 };
66
67 extern const TargetRegisterClass GRRegsRegClass = {
68 .MC: &XCoreMCRegisterClasses[GRRegsRegClassID],
69 .SubClassMask: GRRegsSubClassMask,
70 .SuperRegIndices: SuperRegIdxSeqs + 0,
71 .LaneMask: LaneBitmask(0x0000000000000001),
72 .AllocationPriority: 0,
73 .GlobalPriority: false,
74 .TSFlags: 0x00, /* TSFlags */
75 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
76 .CoveredBySubRegs: false, /* CoveredBySubRegs */
77 .SuperClasses: GRRegsSuperclasses, .SuperClassesSize: 1,
78 .OrderFunc: nullptr
79 };
80
81} // end namespace XCore
82
83namespace {
84 const TargetRegisterClass *const RegisterClasses[] = {
85 &XCore::RRegsRegClass,
86 &XCore::GRRegsRegClass,
87 };
88} // end anonymous namespace
89
90static const uint8_t CostPerUseTable[] = {
910, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
92
93
94static const bool InAllocatableClassTable[] = {
95false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
96
97
98static const TargetRegisterInfoDesc XCoreRegInfoDesc = { // Extra Descriptors
99.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
100
101/// Get the weight in units of pressure for this register class.
102const RegClassWeight &XCoreGenRegisterInfo::
103getRegClassWeight(const TargetRegisterClass *RC) const {
104 static const RegClassWeight RCWeightTable[] = {
105 {.RegWeight: 0, .WeightLimit: 12}, // RRegs
106 {.RegWeight: 1, .WeightLimit: 12}, // GRRegs
107 };
108 return RCWeightTable[RC->getID()];
109}
110
111/// Get the weight in units of pressure for this register unit.
112unsigned XCoreGenRegisterInfo::
113getRegUnitWeight(MCRegUnit RegUnit) const {
114 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
115 // All register units have unit weight.
116 return 1;
117}
118
119
120// Get the number of dimensions of register pressure.
121unsigned XCoreGenRegisterInfo::getNumRegPressureSets() const {
122 return 1;
123}
124
125// Get the name of this register unit pressure set.
126const char *XCoreGenRegisterInfo::
127getRegPressureSetName(unsigned Idx) const {
128 static const char *PressureNameTable[] = {
129 "GRRegs",
130 };
131 return PressureNameTable[Idx];
132}
133
134// Get the register unit pressure limit for this dimension.
135// This limit must be adjusted dynamically for reserved registers.
136unsigned XCoreGenRegisterInfo::
137getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
138 static const uint8_t PressureLimitTable[] = {
139 12, // 0: GRRegs
140 };
141 return PressureLimitTable[Idx];
142}
143
144/// Table of pressure sets per register class or unit.
145static const int RCSetsTable[] = {
146 /* 0 */ 0, -1,
147};
148
149/// Get the dimensions of register pressure impacted by this register class.
150/// Returns a -1 terminated array of pressure set IDs
151const int *XCoreGenRegisterInfo::
152getRegClassPressureSets(const TargetRegisterClass *RC) const {
153 static const uint8_t RCSetStartTable[] = {
154 1,0,};
155 return &RCSetsTable[RCSetStartTable[RC->getID()]];
156}
157
158/// Get the dimensions of register pressure impacted by this register unit.
159/// Returns a -1 terminated array of pressure set IDs
160const int *XCoreGenRegisterInfo::
161getRegUnitPressureSets(MCRegUnit RegUnit) const {
162 assert(static_cast<unsigned>(RegUnit) < 16 && "invalid register unit");
163 static const uint8_t RUSetStartTable[] = {
164 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,};
165 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
166}
167
168extern const MCRegisterDesc XCoreRegDesc[];
169extern const int16_t XCoreRegDiffLists[];
170extern const LaneBitmask XCoreLaneMaskLists[];
171extern const char XCoreRegStrings[];
172extern const char XCoreRegClassStrings[];
173extern const MCPhysReg XCoreRegUnitRoots[][2];
174extern const uint16_t XCoreSubRegIdxLists[];
175extern const uint16_t XCoreRegEncodingTable[];
176// XCore Dwarf<->LLVM register mappings.
177extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[];
178extern const unsigned XCoreDwarfFlavour0Dwarf2LSize;
179
180extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[];
181extern const unsigned XCoreEHFlavour0Dwarf2LSize;
182
183extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[];
184extern const unsigned XCoreDwarfFlavour0L2DwarfSize;
185
186extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[];
187extern const unsigned XCoreEHFlavour0L2DwarfSize;
188
189XCoreGenRegisterInfo::
190XCoreGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
191 unsigned PC, unsigned HwMode)
192 : TargetRegisterInfo(&XCoreRegInfoDesc, RegisterClasses, RegisterClasses+2,
193 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
194 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
195 InitMCRegisterInfo(D: XCoreRegDesc, NR: 17, RA, PC,
196 C: XCoreMCRegisterClasses, NC: 2,
197 RURoots: XCoreRegUnitRoots,
198 NRU: 16,
199 DL: XCoreRegDiffLists,
200 RUMS: XCoreLaneMaskLists,
201 Strings: XCoreRegStrings,
202 ClassStrings: XCoreRegClassStrings,
203 SubIndices: XCoreSubRegIdxLists,
204 NumIndices: 1,
205 RET: XCoreRegEncodingTable);
206
207 switch (DwarfFlavour) {
208 default:
209 llvm_unreachable("Unknown DWARF flavour");
210 case 0:
211 mapDwarfRegsToLLVMRegs(Map: XCoreDwarfFlavour0Dwarf2L, Size: XCoreDwarfFlavour0Dwarf2LSize, isEH: false);
212 break;
213 }
214 switch (EHFlavour) {
215 default:
216 llvm_unreachable("Unknown DWARF flavour");
217 case 0:
218 mapDwarfRegsToLLVMRegs(Map: XCoreEHFlavour0Dwarf2L, Size: XCoreEHFlavour0Dwarf2LSize, isEH: true);
219 break;
220 }
221 switch (DwarfFlavour) {
222 default:
223 llvm_unreachable("Unknown DWARF flavour");
224 case 0:
225 mapLLVMRegsToDwarfRegs(Map: XCoreDwarfFlavour0L2Dwarf, Size: XCoreDwarfFlavour0L2DwarfSize, isEH: false);
226 break;
227 }
228 switch (EHFlavour) {
229 default:
230 llvm_unreachable("Unknown DWARF flavour");
231 case 0:
232 mapLLVMRegsToDwarfRegs(Map: XCoreEHFlavour0L2Dwarf, Size: XCoreEHFlavour0L2DwarfSize, isEH: true);
233 break;
234 }
235}
236
237
238
239ArrayRef<const uint32_t *> XCoreGenRegisterInfo::getRegMasks() const {
240 return {};
241}
242
243bool XCoreGenRegisterInfo::
244isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
245 return
246 false;
247}
248
249bool XCoreGenRegisterInfo::
250isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
251 return
252 false;
253}
254
255bool XCoreGenRegisterInfo::
256isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
257 return
258 false;
259}
260
261bool XCoreGenRegisterInfo::
262isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
263 return
264 false;
265}
266
267bool XCoreGenRegisterInfo::
268isConstantPhysReg(MCRegister PhysReg) const {
269 return
270 false;
271}
272
273ArrayRef<const char *> XCoreGenRegisterInfo::getRegMaskNames() const {
274 return {};
275}
276
277const XCoreFrameLowering *
278XCoreGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
279 return static_cast<const XCoreFrameLowering *>(
280 MF.getSubtarget().getFrameLowering());
281}
282
283} // end namespace llvm
284
285